TSTP Solution File: SYN546+1 by Refute---2015
View Problem
- Process Solution
%------------------------------------------------------------------------------
% File : Refute---2015
% Problem : SYN546+1 : TPTP v6.4.0. Released v2.1.0.
% Transfm : none
% Format : tptp:raw
% Command : isabelle tptp_refute %d %s
% Computer : n080.star.cs.uiowa.edu
% Model : x86_64 x86_64
% CPU : Intel(R) Xeon(R) CPU E5-2609 0 2.40GHz
% Memory : 32218.75MB
% OS : Linux 3.10.0-327.10.1.el7.x86_64
% CPULimit : 300s
% DateTime : Thu Apr 14 06:42:21 EDT 2016
% Result : CounterSatisfiable 135.34s
% Output : Assurance 0s
% Verified :
% SZS Type : None (Parsing solution fails)
% Syntax : Number of formulae : 0
% Comments :
%------------------------------------------------------------------------------
%----No solution output by system
%------------------------------------------------------------------------------
%----ORIGINAL SYSTEM OUTPUT
% 0.00/0.03 % Problem : SYN546+1 : TPTP v6.4.0. Released v2.1.0.
% 0.00/0.04 % Command : isabelle tptp_refute %d %s
% 0.03/0.22 % Computer : n080.star.cs.uiowa.edu
% 0.03/0.22 % Model : x86_64 x86_64
% 0.03/0.22 % CPU : Intel(R) Xeon(R) CPU E5-2609 0 @ 2.40GHz
% 0.03/0.22 % Memory : 32218.75MB
% 0.03/0.22 % OS : Linux 3.10.0-327.10.1.el7.x86_64
% 0.03/0.22 % CPULimit : 300
% 0.03/0.22 % DateTime : Sat Apr 9 00:16:09 CDT 2016
% 0.03/0.22 % CPUTime:
% 6.31/5.81 > val it = (): unit
% 7.13/6.61 Trying to find a model that refutes: ~ (((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((~ bnd_c2_0 |
% 7.13/6.61 ~ bnd_c3_0) |
% 7.13/6.61 ((bnd_ndr1_0 & bnd_c8_1 bnd_a298) &
% 7.13/6.61 ~ bnd_c1_1 bnd_a298) &
% 7.13/6.61 ~ bnd_c3_1 bnd_a298) &
% 7.13/6.61 (bnd_c7_0 | bnd_c3_0)) &
% 7.13/6.61 ((bnd_c3_0 |
% 7.13/6.61 ((bnd_ndr1_0 & ~ bnd_c3_1 bnd_a299) &
% 7.13/6.61 (ALL U.
% 7.13/6.61 bnd_ndr1_1 bnd_a299 -->
% 7.13/6.61 (~ bnd_c4_2 bnd_a299 U |
% 7.13/6.61 ~ bnd_c1_2 bnd_a299 U) |
% 7.13/6.61 ~ bnd_c3_2 bnd_a299 U)) &
% 7.13/6.61 ~ bnd_c7_1 bnd_a299) |
% 7.13/6.61 bnd_c8_0)) &
% 7.13/6.61 ((((((bnd_ndr1_0 &
% 7.13/6.61 (ALL V.
% 7.13/6.61 bnd_ndr1_1 bnd_a300 -->
% 7.13/6.61 (bnd_c1_2 bnd_a300 V |
% 7.13/6.61 bnd_c6_2 bnd_a300 V) |
% 7.13/6.61 ~ bnd_c2_2 bnd_a300 V)) &
% 7.13/6.61 bnd_ndr1_1 bnd_a300) &
% 7.13/6.61 bnd_c5_2 bnd_a300 bnd_a301) &
% 7.13/6.61 ~ bnd_c1_2 bnd_a300 bnd_a301) &
% 7.13/6.61 ~ bnd_c2_2 bnd_a300 bnd_a301) &
% 7.13/6.61 bnd_c2_1 bnd_a300 |
% 7.13/6.61 ((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a302) &
% 7.13/6.61 bnd_c6_2 bnd_a302 bnd_a303) &
% 7.13/6.61 ~ bnd_c1_2 bnd_a302 bnd_a303) &
% 7.13/6.61 ~ bnd_c5_2 bnd_a302 bnd_a303) &
% 7.13/6.61 bnd_c2_1 bnd_a302)) &
% 7.13/6.61 (((ALL W.
% 7.13/6.61 bnd_ndr1_0 -->
% 7.13/6.61 ((ALL X.
% 7.13/6.61 bnd_ndr1_1 W -->
% 7.13/6.61 (~ bnd_c8_2 W X | bnd_c3_2 W X) |
% 7.13/6.61 bnd_c2_2 W X) |
% 7.13/6.61 ~ bnd_c5_1 W) |
% 7.13/6.61 (ALL Y.
% 7.13/6.61 bnd_ndr1_1 W -->
% 7.13/6.61 bnd_c5_2 W Y | ~ bnd_c8_2 W Y)) |
% 7.13/6.61 bnd_c6_0) |
% 7.13/6.61 ((bnd_ndr1_0 & bnd_c1_1 bnd_a304) &
% 7.13/6.61 bnd_c3_1 bnd_a304) &
% 7.13/6.61 ~ bnd_c5_1 bnd_a304)) &
% 7.13/6.61 ((~ bnd_c5_0 | ~ bnd_c3_0) | ~ bnd_c1_0)) &
% 7.13/6.61 ((~ bnd_c3_0 |
% 7.13/6.61 (((((bnd_ndr1_0 &
% 7.13/6.61 (ALL Z.
% 7.13/6.61 bnd_ndr1_1 bnd_a305 -->
% 7.13/6.61 (~ bnd_c6_2 bnd_a305 Z |
% 7.13/6.61 bnd_c4_2 bnd_a305 Z) |
% 7.13/6.61 ~ bnd_c8_2 bnd_a305 Z)) &
% 7.13/6.61 ~ bnd_c5_1 bnd_a305) &
% 7.13/6.61 bnd_ndr1_1 bnd_a305) &
% 7.13/6.61 ~ bnd_c3_2 bnd_a305 bnd_a306) &
% 7.13/6.61 bnd_c2_2 bnd_a305 bnd_a306) &
% 7.13/6.61 bnd_c8_2 bnd_a305 bnd_a306) |
% 7.13/6.61 bnd_c1_0)) &
% 7.13/6.61 ((bnd_c4_0 |
% 7.13/6.61 ((((bnd_ndr1_0 & bnd_c1_1 bnd_a307) &
% 7.13/6.61 bnd_ndr1_1 bnd_a307) &
% 7.13/6.61 ~ bnd_c6_2 bnd_a307 bnd_a308) &
% 7.13/6.61 bnd_c3_2 bnd_a307 bnd_a308) &
% 7.13/6.61 (ALL X1.
% 7.13/6.61 bnd_ndr1_1 bnd_a307 -->
% 7.13/6.61 (bnd_c5_2 bnd_a307 X1 | bnd_c7_2 bnd_a307 X1) |
% 7.13/6.61 bnd_c1_2 bnd_a307 X1)) |
% 7.13/6.61 bnd_c8_0)) &
% 7.13/6.61 (bnd_c6_0 | bnd_c7_0)) &
% 7.13/6.61 (((bnd_ndr1_0 & ~ bnd_c7_1 bnd_a309) &
% 7.13/6.61 (ALL X2.
% 7.13/6.61 bnd_ndr1_1 bnd_a309 -->
% 7.13/6.61 (bnd_c3_2 bnd_a309 X2 | ~ bnd_c2_2 bnd_a309 X2) |
% 7.13/6.61 bnd_c6_2 bnd_a309 X2)) &
% 7.13/6.61 bnd_c3_1 bnd_a309 |
% 7.13/6.61 bnd_c5_0)) &
% 7.13/6.61 (((ALL X3.
% 7.13/6.61 bnd_ndr1_0 -->
% 7.13/6.61 (~ bnd_c1_1 X3 | bnd_c4_1 X3) | bnd_c8_1 X3) |
% 7.13/6.61 (ALL X4.
% 7.13/6.61 bnd_ndr1_0 -->
% 7.13/6.61 (~ bnd_c1_1 X4 | ~ bnd_c2_1 X4) | ~ bnd_c8_1 X4)) |
% 7.13/6.61 bnd_c8_0)) &
% 7.13/6.61 (((ALL X5.
% 7.13/6.61 bnd_ndr1_0 -->
% 7.13/6.61 (bnd_c4_1 X5 |
% 7.13/6.61 (ALL X6.
% 7.13/6.61 bnd_ndr1_1 X5 -->
% 7.13/6.61 (~ bnd_c1_2 X5 X6 | bnd_c7_2 X5 X6) |
% 7.13/6.61 ~ bnd_c5_2 X5 X6)) |
% 7.13/6.61 ((bnd_ndr1_1 X5 & bnd_c7_2 X5 bnd_a310) &
% 7.13/6.61 bnd_c6_2 X5 bnd_a310) &
% 7.13/6.61 ~ bnd_c3_2 X5 bnd_a310) |
% 7.13/6.61 ~ bnd_c6_0) |
% 7.13/6.61 bnd_c7_0)) &
% 7.13/6.61 ((~ bnd_c5_0 | ~ bnd_c7_0) | ~ bnd_c6_0)) &
% 7.13/6.61 (bnd_c7_0 | ~ bnd_c5_0)) &
% 7.13/6.61 ((((((((((bnd_ndr1_0 &
% 7.13/6.61 (ALL X7.
% 7.13/6.61 bnd_ndr1_1 bnd_a311 -->
% 7.13/6.61 ~ bnd_c7_2 bnd_a311 X7 |
% 7.13/6.61 ~ bnd_c8_2 bnd_a311 X7)) &
% 7.13/6.61 bnd_ndr1_1 bnd_a311) &
% 7.13/6.61 bnd_c1_2 bnd_a311 bnd_a312) &
% 7.13/6.61 ~ bnd_c4_2 bnd_a311 bnd_a312) &
% 7.13/6.61 ~ bnd_c5_2 bnd_a311 bnd_a312) &
% 7.13/6.61 bnd_ndr1_1 bnd_a311) &
% 7.13/6.61 ~ bnd_c7_2 bnd_a311 bnd_a313) &
% 7.13/6.61 ~ bnd_c4_2 bnd_a311 bnd_a313) &
% 7.13/6.61 ~ bnd_c5_2 bnd_a311 bnd_a313 |
% 7.13/6.61 bnd_c5_0) |
% 7.13/6.61 ~ bnd_c2_0)) &
% 7.13/6.61 ((~ bnd_c4_0 |
% 7.13/6.61 ((bnd_ndr1_0 & bnd_c6_1 bnd_a314) & ~ bnd_c1_1 bnd_a314) &
% 7.13/6.61 ~ bnd_c8_1 bnd_a314) |
% 7.13/6.61 bnd_c8_0)) &
% 7.13/6.61 ((bnd_c3_0 |
% 7.13/6.61 (ALL X8.
% 7.13/6.61 bnd_ndr1_0 -->
% 7.13/6.61 (bnd_c2_1 X8 | bnd_c7_1 X8) |
% 7.13/6.61 (ALL X9.
% 7.13/6.61 bnd_ndr1_1 X8 -->
% 7.13/6.61 (~ bnd_c6_2 X8 X9 | ~ bnd_c2_2 X8 X9) |
% 7.13/6.61 bnd_c1_2 X8 X9))) |
% 7.13/6.61 ~ bnd_c2_0)) &
% 7.13/6.61 ((((bnd_ndr1_0 & ~ bnd_c4_1 bnd_a315) &
% 7.13/6.61 (ALL X10.
% 7.13/6.61 bnd_ndr1_1 bnd_a315 -->
% 7.13/6.61 (~ bnd_c2_2 bnd_a315 X10 | ~ bnd_c5_2 bnd_a315 X10) |
% 7.13/6.61 ~ bnd_c1_2 bnd_a315 X10)) &
% 7.13/6.61 ~ bnd_c2_1 bnd_a315 |
% 7.13/6.61 ~ bnd_c6_0) |
% 7.13/6.61 bnd_ndr1_0 & bnd_c4_1 bnd_a316)) &
% 7.13/6.61 ((~ bnd_c8_0 |
% 7.13/6.61 ((bnd_ndr1_0 &
% 7.13/6.61 (ALL X11.
% 7.13/6.61 bnd_ndr1_1 bnd_a317 -->
% 7.13/6.61 (bnd_c3_2 bnd_a317 X11 | bnd_c6_2 bnd_a317 X11) |
% 7.13/6.61 bnd_c7_2 bnd_a317 X11)) &
% 7.13/6.61 bnd_c8_1 bnd_a317) &
% 7.13/6.61 (ALL X12.
% 7.13/6.61 bnd_ndr1_1 bnd_a317 -->
% 7.13/6.61 (bnd_c4_2 bnd_a317 X12 | bnd_c8_2 bnd_a317 X12) |
% 7.13/6.61 bnd_c5_2 bnd_a317 X12)) |
% 7.13/6.61 (ALL X13.
% 7.13/6.61 bnd_ndr1_0 -->
% 7.13/6.61 (ALL X14.
% 7.13/6.61 bnd_ndr1_1 X13 -->
% 7.13/6.61 (bnd_c3_2 X13 X14 | ~ bnd_c1_2 X13 X14) |
% 7.13/6.61 ~ bnd_c8_2 X13 X14) |
% 7.13/6.61 ((bnd_ndr1_1 X13 & bnd_c7_2 X13 bnd_a318) &
% 7.13/6.61 ~ bnd_c2_2 X13 bnd_a318) &
% 7.13/6.61 ~ bnd_c1_2 X13 bnd_a318))) &
% 7.13/6.61 ((bnd_c2_0 | ~ bnd_c4_0) | bnd_c3_0)) &
% 7.13/6.61 ((~ bnd_c4_0 | ~ bnd_c6_0) |
% 7.13/6.61 (ALL X15.
% 7.13/6.61 bnd_ndr1_0 -->
% 7.13/6.61 ((ALL X16.
% 7.13/6.61 bnd_ndr1_1 X15 --> bnd_c8_2 X15 X16 | bnd_c6_2 X15 X16) |
% 7.13/6.61 ((bnd_ndr1_1 X15 & bnd_c5_2 X15 bnd_a319) &
% 7.13/6.61 ~ bnd_c7_2 X15 bnd_a319) &
% 7.13/6.61 bnd_c4_2 X15 bnd_a319) |
% 7.13/6.61 (ALL X17.
% 7.13/6.61 bnd_ndr1_1 X15 -->
% 7.13/6.61 (bnd_c1_2 X15 X17 | ~ bnd_c2_2 X15 X17) |
% 7.13/6.61 bnd_c5_2 X15 X17)))) &
% 7.13/6.61 (((ALL X18.
% 7.13/6.61 bnd_ndr1_0 -->
% 7.13/6.61 (((bnd_ndr1_1 X18 & bnd_c1_2 X18 bnd_a320) &
% 7.13/6.61 bnd_c3_2 X18 bnd_a320) &
% 7.13/6.61 bnd_c4_2 X18 bnd_a320 |
% 7.13/6.61 ~ bnd_c6_1 X18) |
% 7.13/6.61 (ALL X19.
% 7.13/6.61 bnd_ndr1_1 X18 --> bnd_c4_2 X18 X19 | ~ bnd_c7_2 X18 X19)) |
% 7.13/6.61 (ALL X20.
% 7.13/6.61 bnd_ndr1_0 --> (~ bnd_c6_1 X20 | bnd_c4_1 X20) | bnd_c1_1 X20)) |
% 7.13/6.61 ((((bnd_ndr1_0 &
% 7.13/6.61 (ALL X21.
% 7.13/6.61 bnd_ndr1_1 bnd_a321 -->
% 7.13/6.61 (~ bnd_c2_2 bnd_a321 X21 | ~ bnd_c4_2 bnd_a321 X21) |
% 7.13/6.61 bnd_c6_2 bnd_a321 X21)) &
% 7.13/6.61 bnd_ndr1_1 bnd_a321) &
% 7.13/6.61 ~ bnd_c8_2 bnd_a321 bnd_a322) &
% 7.13/6.61 ~ bnd_c6_2 bnd_a321 bnd_a322) &
% 7.13/6.61 bnd_c5_2 bnd_a321 bnd_a322)) &
% 7.13/6.61 ((((((bnd_ndr1_0 & bnd_c1_1 bnd_a323) & bnd_ndr1_1 bnd_a323) &
% 7.13/6.61 bnd_c4_2 bnd_a323 bnd_a324) &
% 7.13/6.61 ~ bnd_c6_2 bnd_a323 bnd_a324) &
% 7.13/6.61 ~ bnd_c5_2 bnd_a323 bnd_a324 |
% 7.13/6.61 ((bnd_ndr1_0 & bnd_c4_1 bnd_a325) &
% 7.13/6.61 (ALL X22.
% 7.13/6.61 bnd_ndr1_1 bnd_a325 -->
% 7.13/6.61 (~ bnd_c7_2 bnd_a325 X22 | ~ bnd_c5_2 bnd_a325 X22) |
% 7.13/6.61 ~ bnd_c1_2 bnd_a325 X22)) &
% 7.13/6.61 bnd_c6_1 bnd_a325) |
% 7.13/6.61 bnd_c2_0)) &
% 7.13/6.61 ((ALL X23.
% 7.13/6.61 bnd_ndr1_0 -->
% 7.13/6.61 ((ALL X24.
% 7.13/6.61 bnd_ndr1_1 X23 --> ~ bnd_c1_2 X23 X24 | ~ bnd_c6_2 X23 X24) |
% 7.13/6.61 (ALL X25.
% 7.13/6.61 bnd_ndr1_1 X23 -->
% 7.13/6.61 (bnd_c5_2 X23 X25 | bnd_c7_2 X23 X25) | ~ bnd_c8_2 X23 X25)) |
% 7.13/6.61 ~ bnd_c5_1 X23) |
% 7.13/6.61 (((((bnd_ndr1_0 & bnd_c8_1 bnd_a326) & bnd_ndr1_1 bnd_a326) &
% 7.13/6.61 ~ bnd_c1_2 bnd_a326 bnd_a327) &
% 7.13/6.61 bnd_c8_2 bnd_a326 bnd_a327) &
% 7.13/6.61 ~ bnd_c2_2 bnd_a326 bnd_a327) &
% 7.13/6.61 (ALL X26.
% 7.13/6.61 bnd_ndr1_1 bnd_a326 -->
% 7.13/6.61 ~ bnd_c8_2 bnd_a326 X26 | bnd_c7_2 bnd_a326 X26))) &
% 7.13/6.61 (((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a328) & bnd_c5_2 bnd_a328 bnd_a329) &
% 7.13/6.61 bnd_c2_2 bnd_a328 bnd_a329) &
% 7.13/6.61 ~ bnd_c4_2 bnd_a328 bnd_a329) &
% 7.13/6.61 bnd_c6_1 bnd_a328) &
% 7.13/6.61 ~ bnd_c4_1 bnd_a328 |
% 7.13/6.61 ~ bnd_c2_0) |
% 7.13/6.61 ((((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a330) &
% 7.13/6.61 ~ bnd_c5_2 bnd_a330 bnd_a331) &
% 7.13/6.61 bnd_c6_2 bnd_a330 bnd_a331) &
% 7.13/6.61 ~ bnd_c1_2 bnd_a330 bnd_a331) &
% 7.13/6.61 bnd_ndr1_1 bnd_a330) &
% 7.13/6.61 ~ bnd_c8_2 bnd_a330 bnd_a332) &
% 7.13/6.61 ~ bnd_c2_2 bnd_a330 bnd_a332) &
% 7.13/6.61 ~ bnd_c5_2 bnd_a330 bnd_a332) &
% 7.13/6.61 ~ bnd_c6_1 bnd_a330)) &
% 7.13/6.61 ((~ bnd_c3_0 |
% 7.13/6.61 (ALL X27.
% 7.13/6.61 bnd_ndr1_0 -->
% 7.13/6.61 (bnd_c4_1 X27 |
% 7.13/6.61 ((bnd_ndr1_1 X27 & ~ bnd_c7_2 X27 bnd_a333) &
% 7.13/6.61 bnd_c2_2 X27 bnd_a333) &
% 7.13/6.61 bnd_c6_2 X27 bnd_a333) |
% 7.13/6.61 (ALL X28.
% 7.13/6.61 bnd_ndr1_1 X27 -->
% 7.13/6.61 (~ bnd_c1_2 X27 X28 | ~ bnd_c5_2 X27 X28) | bnd_c8_2 X27 X28))) |
% 7.13/6.61 (((((bnd_ndr1_0 & ~ bnd_c6_1 bnd_a334) & ~ bnd_c1_1 bnd_a334) &
% 7.13/6.61 bnd_ndr1_1 bnd_a334) &
% 7.13/6.61 ~ bnd_c3_2 bnd_a334 bnd_a335) &
% 7.13/6.61 ~ bnd_c4_2 bnd_a334 bnd_a335) &
% 7.13/6.61 bnd_c5_2 bnd_a334 bnd_a335)) &
% 7.13/6.61 ((~ bnd_c5_0 | bnd_c6_0) | bnd_c7_0)) &
% 7.13/6.61 (((bnd_ndr1_0 & bnd_c5_1 bnd_a336) &
% 7.13/6.61 bnd_c3_1 bnd_a336 |
% 7.13/6.61 ~ bnd_c1_0) |
% 7.13/6.61 ~ bnd_c8_0)) &
% 7.13/6.61 ((~ bnd_c8_0 | ~ bnd_c6_0) |
% 7.13/6.61 bnd_c3_0)) &
% 7.13/6.61 ((~ bnd_c2_0 | ~ bnd_c5_0) | bnd_c7_0)) &
% 7.13/6.61 (((ALL X29.
% 7.13/6.61 bnd_ndr1_0 -->
% 7.13/6.61 (bnd_c3_1 X29 | ~ bnd_c2_1 X29) |
% 7.13/6.61 ((bnd_ndr1_1 X29 & bnd_c8_2 X29 bnd_a337) & bnd_c5_2 X29 bnd_a337) &
% 7.13/6.61 ~ bnd_c7_2 X29 bnd_a337) |
% 7.13/6.61 bnd_ndr1_0 & bnd_c1_1 bnd_a338) |
% 7.13/6.61 bnd_c4_0)) &
% 7.13/6.61 (((ALL X30.
% 7.13/6.61 bnd_ndr1_0 -->
% 7.13/6.61 (ALL X31.
% 7.13/6.61 bnd_ndr1_1 X30 -->
% 7.13/6.61 (bnd_c1_2 X30 X31 | bnd_c8_2 X30 X31) | ~ bnd_c4_2 X30 X31) |
% 7.13/6.61 ~ bnd_c2_1 X30) |
% 7.13/6.61 ~ bnd_c6_0) |
% 7.13/6.61 ~ bnd_c5_0)) &
% 7.13/6.61 ((((bnd_ndr1_0 & ~ bnd_c2_1 bnd_a339) &
% 7.13/6.61 (ALL X32.
% 7.13/6.61 bnd_ndr1_1 bnd_a339 --> bnd_c8_2 bnd_a339 X32 | bnd_c2_2 bnd_a339 X32)) &
% 7.13/6.61 (ALL X33.
% 7.13/6.61 bnd_ndr1_1 bnd_a339 --> bnd_c8_2 bnd_a339 X33 | ~ bnd_c7_2 bnd_a339 X33) |
% 7.13/6.61 bnd_c3_0) |
% 7.13/6.61 ~ bnd_c2_0)) &
% 7.13/6.61 ((ALL X34.
% 7.13/6.61 bnd_ndr1_0 -->
% 7.13/6.61 (((bnd_ndr1_1 X34 &
% 7.13/6.61 ~ bnd_c8_2 X34 bnd_a340) &
% 7.13/6.61 bnd_c6_2 X34 bnd_a340) &
% 7.13/6.61 ~ bnd_c3_2 X34 bnd_a340 |
% 7.13/6.61 (bnd_ndr1_1 X34 &
% 7.13/6.61 bnd_c1_2 X34 bnd_a341) &
% 7.13/6.61 bnd_c7_2 X34 bnd_a341) |
% 7.13/6.61 ~ bnd_c2_1 X34) |
% 7.13/6.61 bnd_c2_0)) &
% 7.13/6.61 ((bnd_c5_0 |
% 7.13/6.61 (ALL X35.
% 7.13/6.61 bnd_ndr1_0 -->
% 7.13/6.61 ((ALL X36.
% 7.13/6.61 bnd_ndr1_1 X35 --> bnd_c7_2 X35 X36 | ~ bnd_c5_2 X35 X36) |
% 7.13/6.61 bnd_c5_1 X35) |
% 7.13/6.61 bnd_c8_1 X35)) |
% 7.13/6.61 (ALL X37.
% 7.13/6.61 bnd_ndr1_0 -->
% 7.13/6.61 ((ALL X38.
% 7.13/6.61 bnd_ndr1_1 X37 --> bnd_c8_2 X37 X38 | bnd_c3_2 X37 X38) |
% 7.13/6.61 ~ bnd_c2_1 X37) |
% 7.13/6.61 (ALL X39.
% 7.13/6.61 bnd_ndr1_1 X37 -->
% 7.13/6.61 (~ bnd_c6_2 X37 X39 | bnd_c8_2 X37 X39) | bnd_c7_2 X37 X39)))) &
% 7.13/6.61 (((ALL X40.
% 7.13/6.61 bnd_ndr1_0 -->
% 7.13/6.61 (bnd_c3_1 X40 | bnd_c1_1 X40) |
% 7.13/6.61 ~ bnd_c2_1 X40) |
% 7.13/6.61 (((((bnd_ndr1_0 &
% 7.13/6.61 (ALL X41.
% 7.13/6.61 bnd_ndr1_1 bnd_a342 --> bnd_c4_2 bnd_a342 X41 | bnd_c5_2 bnd_a342 X41)) &
% 7.13/6.61 (ALL X42.
% 7.13/6.61 bnd_ndr1_1 bnd_a342 -->
% 7.13/6.61 (bnd_c5_2 bnd_a342 X42 | ~ bnd_c8_2 bnd_a342 X42) |
% 7.13/6.61 ~ bnd_c4_2 bnd_a342 X42)) &
% 7.13/6.61 bnd_ndr1_1 bnd_a342) &
% 7.13/6.61 bnd_c7_2 bnd_a342 bnd_a343) &
% 7.13/6.61 bnd_c8_2 bnd_a342 bnd_a343) &
% 7.13/6.61 ~ bnd_c4_2 bnd_a342 bnd_a343) |
% 7.13/6.61 (ALL X43.
% 7.13/6.61 bnd_ndr1_0 -->
% 7.13/6.61 (((bnd_ndr1_1 X43 &
% 7.13/6.61 bnd_c4_2 X43 bnd_a344) &
% 7.13/6.61 bnd_c7_2 X43 bnd_a344) &
% 7.13/6.61 ~ bnd_c6_2 X43 bnd_a344 |
% 7.13/6.61 (ALL X44.
% 7.13/6.61 bnd_ndr1_1 X43 --> ~ bnd_c6_2 X43 X44 | bnd_c4_2 X43 X44)) |
% 7.13/6.61 bnd_c6_1 X43))) &
% 7.13/6.61 ((bnd_c6_0 | ~ bnd_c4_0) | ~ bnd_c3_0)) &
% 7.13/6.61 ((~ bnd_c6_0 |
% 7.13/6.61 (((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a345) &
% 7.13/6.61 bnd_c5_2 bnd_a345 bnd_a346) &
% 7.13/6.61 ~ bnd_c1_2 bnd_a345 bnd_a346) &
% 7.13/6.61 bnd_c2_2 bnd_a345 bnd_a346) &
% 7.13/6.61 bnd_c2_1 bnd_a345) &
% 7.13/6.61 bnd_c6_1 bnd_a345) |
% 7.13/6.61 (((((bnd_ndr1_0 & bnd_c4_1 bnd_a347) &
% 7.13/6.61 bnd_ndr1_1 bnd_a347) &
% 7.13/6.61 bnd_c2_2 bnd_a347 bnd_a348) &
% 7.13/6.61 ~ bnd_c4_2 bnd_a347 bnd_a348) &
% 7.13/6.61 bnd_c3_2 bnd_a347 bnd_a348) &
% 7.13/6.61 bnd_c8_1 bnd_a347)) &
% 7.13/6.61 ((((bnd_ndr1_0 & ~ bnd_c3_1 bnd_a349) &
% 7.13/6.61 ~ bnd_c5_1 bnd_a349) &
% 7.13/6.61 ~ bnd_c8_1 bnd_a349 |
% 7.13/6.61 bnd_c1_0) |
% 7.13/6.61 ~ bnd_c5_0)) &
% 7.13/6.61 ((((bnd_ndr1_0 &
% 7.13/6.61 (ALL X45.
% 7.13/6.61 bnd_ndr1_1 bnd_a350 -->
% 7.13/6.61 (bnd_c1_2 bnd_a350 X45 |
% 7.13/6.61 bnd_c8_2 bnd_a350 X45) |
% 7.13/6.61 bnd_c4_2 bnd_a350 X45)) &
% 7.13/6.61 (ALL X46.
% 7.13/6.61 bnd_ndr1_1 bnd_a350 -->
% 7.13/6.61 (~ bnd_c3_2 bnd_a350 X46 |
% 7.13/6.61 bnd_c4_2 bnd_a350 X46) |
% 7.13/6.61 ~ bnd_c5_2 bnd_a350 X46)) &
% 7.13/6.61 (ALL X47.
% 7.13/6.61 bnd_ndr1_1 bnd_a350 -->
% 7.13/6.61 (bnd_c2_2 bnd_a350 X47 |
% 7.13/6.61 ~ bnd_c6_2 bnd_a350 X47) |
% 7.13/6.61 bnd_c4_2 bnd_a350 X47) |
% 7.13/6.61 (bnd_ndr1_0 &
% 7.13/6.61 (ALL X48.
% 7.13/6.61 bnd_ndr1_1 bnd_a351 -->
% 7.13/6.61 (bnd_c1_2 bnd_a351 X48 |
% 7.13/6.61 ~ bnd_c6_2 bnd_a351 X48) |
% 7.13/6.61 ~ bnd_c7_2 bnd_a351 X48)) &
% 7.13/6.61 (ALL X49.
% 7.13/6.61 bnd_ndr1_1 bnd_a351 -->
% 7.13/6.61 (bnd_c2_2 bnd_a351 X49 |
% 7.13/6.61 bnd_c4_2 bnd_a351 X49) |
% 7.13/6.61 bnd_c5_2 bnd_a351 X49)) |
% 7.13/6.61 (((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a352) &
% 7.13/6.61 bnd_c6_2 bnd_a352 bnd_a353) &
% 7.13/6.61 bnd_c4_2 bnd_a352 bnd_a353) &
% 7.13/6.61 ~ bnd_c8_2 bnd_a352 bnd_a353) &
% 7.13/6.61 (ALL X50.
% 7.13/6.61 bnd_ndr1_1 bnd_a352 -->
% 7.13/6.61 (~ bnd_c5_2 bnd_a352 X50 |
% 7.13/6.61 ~ bnd_c8_2 bnd_a352 X50) |
% 7.13/6.61 bnd_c1_2 bnd_a352 X50)) &
% 7.13/6.61 bnd_c2_1 bnd_a352)) &
% 7.13/6.61 ((((bnd_ndr1_0 & bnd_c5_1 bnd_a354) &
% 7.13/6.61 (ALL X51.
% 7.13/6.61 bnd_ndr1_1 bnd_a354 -->
% 7.13/6.61 ~ bnd_c2_2 bnd_a354 X51 |
% 7.13/6.61 bnd_c8_2 bnd_a354 X51)) &
% 7.13/6.61 ~ bnd_c2_1 bnd_a354 |
% 7.13/6.61 (((((bnd_ndr1_0 & bnd_c6_1 bnd_a355) &
% 7.13/6.61 bnd_ndr1_1 bnd_a355) &
% 7.13/6.61 bnd_c1_2 bnd_a355 bnd_a356) &
% 7.13/6.61 ~ bnd_c6_2 bnd_a355 bnd_a356) &
% 7.13/6.61 bnd_c8_2 bnd_a355 bnd_a356) &
% 7.13/6.61 ~ bnd_c2_1 bnd_a355) |
% 7.13/6.61 ~ bnd_c7_0)) &
% 7.13/6.61 ((bnd_c1_0 | bnd_c4_0) | bnd_c8_0)) &
% 7.13/6.61 (~ bnd_c1_0 | bnd_c8_0)) &
% 7.13/6.61 ((bnd_c3_0 | ~ bnd_c5_0) |
% 7.13/6.61 (ALL X52.
% 7.13/6.61 bnd_ndr1_0 -->
% 7.13/6.61 ((ALL X53.
% 7.13/6.61 bnd_ndr1_1 X52 -->
% 7.13/6.61 (~ bnd_c6_2 X52 X53 | bnd_c2_2 X52 X53) |
% 7.13/6.61 bnd_c1_2 X52 X53) |
% 7.13/6.61 ~ bnd_c4_1 X52) |
% 7.13/6.61 ~ bnd_c6_1 X52))) &
% 7.13/6.61 (((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a357) &
% 7.13/6.61 ~ bnd_c3_2 bnd_a357 bnd_a358) &
% 7.13/6.61 bnd_c7_2 bnd_a357 bnd_a358) &
% 7.13/6.61 ~ bnd_c6_2 bnd_a357 bnd_a358) &
% 7.13/6.61 (ALL X54.
% 7.13/6.61 bnd_ndr1_1 bnd_a357 -->
% 7.13/6.61 (bnd_c1_2 bnd_a357 X54 |
% 7.13/6.61 ~ bnd_c4_2 bnd_a357 X54) |
% 7.13/6.61 ~ bnd_c5_2 bnd_a357 X54)) &
% 7.13/6.61 (ALL X55.
% 7.13/6.61 bnd_ndr1_1 bnd_a357 -->
% 7.13/6.61 (bnd_c5_2 bnd_a357 X55 |
% 7.13/6.61 ~ bnd_c7_2 bnd_a357 X55) |
% 7.13/6.61 ~ bnd_c8_2 bnd_a357 X55) |
% 7.13/6.61 (ALL X56.
% 7.13/6.61 bnd_ndr1_0 -->
% 7.13/6.61 (((bnd_ndr1_1 X56 & ~ bnd_c6_2 X56 bnd_a359) &
% 7.13/6.61 bnd_c8_2 X56 bnd_a359) &
% 7.13/6.61 ~ bnd_c4_2 X56 bnd_a359 |
% 7.13/6.61 (ALL X57.
% 7.13/6.61 bnd_ndr1_1 X56 -->
% 7.13/6.61 (bnd_c7_2 X56 X57 | bnd_c4_2 X56 X57) |
% 7.13/6.61 ~ bnd_c1_2 X56 X57)) |
% 7.13/6.61 ((bnd_ndr1_1 X56 & ~ bnd_c5_2 X56 bnd_a360) &
% 7.13/6.61 ~ bnd_c4_2 X56 bnd_a360) &
% 7.13/6.61 ~ bnd_c8_2 X56 bnd_a360)) |
% 7.13/6.61 (ALL X58.
% 7.13/6.61 bnd_ndr1_0 -->
% 7.13/6.61 ((bnd_ndr1_1 X58 & bnd_c7_2 X58 bnd_a361) &
% 7.13/6.61 ~ bnd_c5_2 X58 bnd_a361) &
% 7.13/6.61 ~ bnd_c4_2 X58 bnd_a361 |
% 7.13/6.61 ~ bnd_c6_1 X58))) &
% 7.13/6.61 (((ALL X59.
% 7.13/6.61 bnd_ndr1_0 -->
% 7.13/6.61 (~ bnd_c7_1 X59 |
% 7.13/6.61 (ALL X60.
% 7.13/6.61 bnd_ndr1_1 X59 -->
% 7.13/6.61 (bnd_c4_2 X59 X60 | ~ bnd_c7_2 X59 X60) |
% 7.13/6.61 bnd_c2_2 X59 X60)) |
% 7.13/6.61 (ALL X61.
% 7.13/6.61 bnd_ndr1_1 X59 -->
% 7.13/6.61 (bnd_c7_2 X59 X61 | ~ bnd_c3_2 X59 X61) |
% 7.13/6.61 bnd_c5_2 X59 X61)) |
% 7.13/6.61 (((((bnd_ndr1_0 & bnd_c5_1 bnd_a362) &
% 7.13/6.61 bnd_ndr1_1 bnd_a362) &
% 7.13/6.61 ~ bnd_c6_2 bnd_a362 bnd_a363) &
% 7.13/6.61 bnd_c2_2 bnd_a362 bnd_a363) &
% 7.13/6.61 ~ bnd_c1_2 bnd_a362 bnd_a363) &
% 7.13/6.61 (ALL X62.
% 7.13/6.61 bnd_ndr1_1 bnd_a362 -->
% 7.13/6.61 (bnd_c6_2 bnd_a362 X62 | ~ bnd_c2_2 bnd_a362 X62) |
% 7.13/6.61 bnd_c5_2 bnd_a362 X62)) |
% 7.13/6.61 (ALL X63.
% 7.13/6.61 bnd_ndr1_0 -->
% 7.13/6.61 ((ALL X64.
% 7.13/6.61 bnd_ndr1_1 X63 -->
% 7.13/6.61 ~ bnd_c3_2 X63 X64 | ~ bnd_c8_2 X63 X64) |
% 7.13/6.61 bnd_c8_1 X63) |
% 7.13/6.61 (ALL X65.
% 7.13/6.61 bnd_ndr1_1 X63 -->
% 7.13/6.61 (~ bnd_c7_2 X63 X65 | ~ bnd_c2_2 X63 X65) |
% 7.13/6.61 ~ bnd_c8_2 X63 X65)))) &
% 7.13/6.61 (((ALL X66.
% 7.13/6.61 bnd_ndr1_0 -->
% 7.13/6.61 (bnd_c4_1 X66 | ~ bnd_c1_1 X66) | ~ bnd_c2_1 X66) |
% 7.13/6.61 (ALL X67.
% 7.13/6.61 bnd_ndr1_0 -->
% 7.13/6.61 ((ALL X68.
% 7.13/6.61 bnd_ndr1_1 X67 -->
% 7.13/6.61 (bnd_c5_2 X67 X68 | ~ bnd_c8_2 X67 X68) |
% 7.13/6.61 ~ bnd_c6_2 X67 X68) |
% 7.13/6.61 ((bnd_ndr1_1 X67 & bnd_c2_2 X67 bnd_a364) &
% 7.13/6.61 ~ bnd_c4_2 X67 bnd_a364) &
% 7.13/6.61 bnd_c8_2 X67 bnd_a364) |
% 7.13/6.61 bnd_c8_1 X67)) |
% 7.13/6.61 (ALL X69.
% 7.13/6.61 bnd_ndr1_0 -->
% 7.13/6.61 (bnd_c1_1 X69 |
% 7.13/6.61 (ALL X70.
% 7.13/6.61 bnd_ndr1_1 X69 -->
% 7.13/6.61 (bnd_c5_2 X69 X70 | bnd_c8_2 X69 X70) |
% 7.13/6.61 ~ bnd_c7_2 X69 X70)) |
% 7.13/6.61 bnd_c7_1 X69))) &
% 7.13/6.61 ((((bnd_ndr1_0 &
% 7.13/6.61 (ALL X71.
% 7.13/6.61 bnd_ndr1_1 bnd_a365 -->
% 7.13/6.61 bnd_c4_2 bnd_a365 X71 | bnd_c5_2 bnd_a365 X71)) &
% 7.13/6.61 ~ bnd_c7_1 bnd_a365) &
% 7.13/6.61 bnd_c1_1 bnd_a365 |
% 7.13/6.61 ((bnd_ndr1_0 &
% 7.13/6.61 (ALL X72.
% 7.13/6.61 bnd_ndr1_1 bnd_a366 -->
% 7.13/6.61 (bnd_c1_2 bnd_a366 X72 | bnd_c2_2 bnd_a366 X72) |
% 7.13/6.61 ~ bnd_c4_2 bnd_a366 X72)) &
% 7.13/6.61 (ALL X73.
% 7.13/6.61 bnd_ndr1_1 bnd_a366 -->
% 7.13/6.61 bnd_c7_2 bnd_a366 X73 | bnd_c1_2 bnd_a366 X73)) &
% 7.13/6.61 (ALL X74.
% 7.13/6.61 bnd_ndr1_1 bnd_a366 -->
% 7.13/6.61 bnd_c8_2 bnd_a366 X74 | bnd_c4_2 bnd_a366 X74)) |
% 7.13/6.61 (ALL X75.
% 7.13/6.61 bnd_ndr1_0 -->
% 7.13/6.61 (bnd_c3_1 X75 |
% 7.13/6.61 ((bnd_ndr1_1 X75 & ~ bnd_c8_2 X75 bnd_a367) &
% 7.13/6.61 bnd_c4_2 X75 bnd_a367) &
% 7.13/6.61 bnd_c5_2 X75 bnd_a367) |
% 7.13/6.61 (ALL X76.
% 7.13/6.61 bnd_ndr1_1 X75 -->
% 7.13/6.61 (~ bnd_c1_2 X75 X76 | ~ bnd_c6_2 X75 X76) |
% 7.13/6.61 bnd_c5_2 X75 X76)))) &
% 7.13/6.61 ((~ bnd_c2_0 |
% 7.13/6.61 (ALL X77.
% 7.13/6.61 bnd_ndr1_0 -->
% 7.13/6.61 bnd_c6_1 X77 |
% 7.13/6.61 (bnd_ndr1_1 X77 & ~ bnd_c8_2 X77 bnd_a368) &
% 7.13/6.61 bnd_c4_2 X77 bnd_a368)) |
% 7.13/6.61 (((((bnd_ndr1_0 & bnd_c2_1 bnd_a369) &
% 7.13/6.61 bnd_ndr1_1 bnd_a369) &
% 7.13/6.61 ~ bnd_c4_2 bnd_a369 bnd_a370) &
% 7.13/6.61 ~ bnd_c5_2 bnd_a369 bnd_a370) &
% 7.13/6.61 ~ bnd_c8_2 bnd_a369 bnd_a370) &
% 7.13/6.61 (ALL X78.
% 7.13/6.61 bnd_ndr1_1 bnd_a369 -->
% 7.13/6.61 (bnd_c3_2 bnd_a369 X78 | bnd_c1_2 bnd_a369 X78) |
% 7.13/6.61 bnd_c4_2 bnd_a369 X78))) &
% 7.13/6.61 ((bnd_ndr1_0 & bnd_c3_1 bnd_a371) &
% 7.13/6.61 (ALL X79.
% 7.13/6.61 bnd_ndr1_1 bnd_a371 -->
% 7.13/6.61 (bnd_c4_2 bnd_a371 X79 | ~ bnd_c6_2 bnd_a371 X79) |
% 7.13/6.61 ~ bnd_c5_2 bnd_a371 X79) |
% 7.13/6.61 ~ bnd_c6_0)) &
% 7.13/6.61 ((bnd_c2_0 |
% 7.13/6.61 (ALL X80.
% 7.13/6.61 bnd_ndr1_0 -->
% 7.13/6.61 (~ bnd_c1_1 X80 |
% 7.13/6.61 (ALL X81.
% 7.13/6.61 bnd_ndr1_1 X80 -->
% 7.13/6.61 (bnd_c8_2 X80 X81 | bnd_c3_2 X80 X81) |
% 7.13/6.61 ~ bnd_c1_2 X80 X81)) |
% 7.13/6.61 ((bnd_ndr1_1 X80 & bnd_c4_2 X80 bnd_a372) &
% 7.13/6.61 ~ bnd_c8_2 X80 bnd_a372) &
% 7.13/6.61 ~ bnd_c5_2 X80 bnd_a372)) |
% 7.13/6.61 ((bnd_ndr1_0 & bnd_c8_1 bnd_a373) & bnd_c3_1 bnd_a373) &
% 7.13/6.61 bnd_c5_1 bnd_a373)) &
% 7.13/6.61 (((((((bnd_ndr1_0 &
% 7.13/6.61 (ALL X82.
% 7.13/6.61 bnd_ndr1_1 bnd_a374 -->
% 7.13/6.61 (~ bnd_c5_2 bnd_a374 X82 | bnd_c8_2 bnd_a374 X82) |
% 7.13/6.61 ~ bnd_c1_2 bnd_a374 X82)) &
% 7.13/6.61 (ALL X83.
% 7.13/6.61 bnd_ndr1_1 bnd_a374 -->
% 7.13/6.61 (~ bnd_c5_2 bnd_a374 X83 | bnd_c2_2 bnd_a374 X83) |
% 7.13/6.61 bnd_c4_2 bnd_a374 X83)) &
% 7.13/6.61 bnd_ndr1_1 bnd_a374) &
% 7.13/6.61 ~ bnd_c7_2 bnd_a374 bnd_a375) &
% 7.13/6.61 ~ bnd_c6_2 bnd_a374 bnd_a375) &
% 7.13/6.61 bnd_c5_2 bnd_a374 bnd_a375 |
% 7.13/6.61 ~ bnd_c5_0) |
% 7.13/6.61 ~ bnd_c3_0)) &
% 7.13/6.61 ((~ bnd_c3_0 | ~ bnd_c4_0) |
% 7.13/6.61 (((((bnd_ndr1_0 &
% 7.13/6.61 (ALL X84.
% 7.13/6.61 bnd_ndr1_1 bnd_a376 -->
% 7.13/6.61 (~ bnd_c8_2 bnd_a376 X84 | ~ bnd_c5_2 bnd_a376 X84) |
% 7.13/6.61 bnd_c1_2 bnd_a376 X84)) &
% 7.13/6.61 bnd_ndr1_1 bnd_a376) &
% 7.13/6.61 ~ bnd_c5_2 bnd_a376 bnd_a377) &
% 7.13/6.61 bnd_c3_2 bnd_a376 bnd_a377) &
% 7.13/6.61 ~ bnd_c6_2 bnd_a376 bnd_a377) &
% 7.13/6.61 (ALL X85.
% 7.13/6.61 bnd_ndr1_1 bnd_a376 -->
% 7.13/6.61 (~ bnd_c1_2 bnd_a376 X85 | bnd_c4_2 bnd_a376 X85) |
% 7.13/6.61 bnd_c3_2 bnd_a376 X85))) &
% 7.13/6.61 (((ALL X86.
% 7.13/6.61 bnd_ndr1_0 -->
% 7.13/6.61 (~ bnd_c2_1 X86 |
% 7.13/6.61 ((bnd_ndr1_1 X86 & bnd_c6_2 X86 bnd_a378) &
% 7.13/6.61 ~ bnd_c2_2 X86 bnd_a378) &
% 7.13/6.61 ~ bnd_c5_2 X86 bnd_a378) |
% 7.13/6.61 bnd_c3_1 X86) |
% 7.13/6.61 ((bnd_ndr1_0 &
% 7.13/6.61 (ALL X87.
% 7.13/6.61 bnd_ndr1_1 bnd_a379 -->
% 7.13/6.61 (bnd_c3_2 bnd_a379 X87 | bnd_c5_2 bnd_a379 X87) |
% 7.13/6.61 bnd_c4_2 bnd_a379 X87)) &
% 7.13/6.61 bnd_c3_1 bnd_a379) &
% 7.13/6.61 ~ bnd_c1_1 bnd_a379) |
% 7.13/6.61 bnd_c5_0)) &
% 7.13/6.61 (~ bnd_c6_0 |
% 7.13/6.61 (((((((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a380) &
% 7.13/6.61 bnd_c2_2 bnd_a380 bnd_a381) &
% 7.13/6.61 ~ bnd_c8_2 bnd_a380 bnd_a381) &
% 7.13/6.61 ~ bnd_c1_2 bnd_a380 bnd_a381) &
% 7.13/6.61 bnd_ndr1_1 bnd_a380) &
% 7.13/6.61 ~ bnd_c6_2 bnd_a380 bnd_a382) &
% 7.13/6.61 ~ bnd_c1_2 bnd_a380 bnd_a382) &
% 7.13/6.61 bnd_c3_2 bnd_a380 bnd_a382) &
% 7.13/6.61 bnd_ndr1_1 bnd_a380) &
% 7.13/6.61 bnd_c6_2 bnd_a380 bnd_a383) &
% 7.13/6.61 ~ bnd_c8_2 bnd_a380 bnd_a383) &
% 7.13/6.61 bnd_c1_2 bnd_a380 bnd_a383)) &
% 7.13/6.61 (bnd_c3_0 |
% 7.13/6.61 ((bnd_ndr1_0 & bnd_c6_1 bnd_a384) & ~ bnd_c8_1 bnd_a384) &
% 7.13/6.61 (ALL X88.
% 7.13/6.61 bnd_ndr1_1 bnd_a384 -->
% 7.13/6.61 (~ bnd_c3_2 bnd_a384 X88 | ~ bnd_c2_2 bnd_a384 X88) |
% 7.13/6.61 ~ bnd_c7_2 bnd_a384 X88))) &
% 7.13/6.61 ((~ bnd_c3_0 | bnd_c5_0) |
% 7.13/6.61 (((((bnd_ndr1_0 & bnd_c5_1 bnd_a385) & bnd_c2_1 bnd_a385) &
% 7.13/6.61 bnd_ndr1_1 bnd_a385) &
% 7.13/6.61 ~ bnd_c8_2 bnd_a385 bnd_a386) &
% 7.13/6.61 ~ bnd_c3_2 bnd_a385 bnd_a386) &
% 7.13/6.61 ~ bnd_c6_2 bnd_a385 bnd_a386)) &
% 7.13/6.61 ((bnd_c7_0 | ~ bnd_c5_0) | bnd_c1_0)) &
% 7.13/6.61 ((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a387) &
% 7.13/6.61 bnd_c7_2 bnd_a387 bnd_a388) &
% 7.13/6.61 bnd_c3_2 bnd_a387 bnd_a388) &
% 7.13/6.61 ~ bnd_c8_2 bnd_a387 bnd_a388) &
% 7.13/6.61 bnd_c6_1 bnd_a387) &
% 7.13/6.61 bnd_c1_1 bnd_a387 |
% 7.13/6.61 (ALL X89.
% 7.13/6.61 bnd_ndr1_0 -->
% 7.13/6.61 (((bnd_ndr1_1 X89 & bnd_c2_2 X89 bnd_a389) &
% 7.13/6.61 bnd_c7_2 X89 bnd_a389) &
% 7.13/6.61 ~ bnd_c6_2 X89 bnd_a389 |
% 7.13/6.61 ((bnd_ndr1_1 X89 & ~ bnd_c7_2 X89 bnd_a390) &
% 7.13/6.61 bnd_c3_2 X89 bnd_a390) &
% 7.13/6.61 ~ bnd_c8_2 X89 bnd_a390) |
% 7.13/6.61 ~ bnd_c2_1 X89))) &
% 7.13/6.61 ((bnd_c7_0 | bnd_c3_0) |
% 7.13/6.61 (ALL X90.
% 7.13/6.61 bnd_ndr1_0 -->
% 7.13/6.61 ((ALL X91.
% 7.13/6.61 bnd_ndr1_1 X90 -->
% 7.13/6.61 (bnd_c2_2 X90 X91 | bnd_c4_2 X90 X91) | ~ bnd_c7_2 X90 X91) |
% 7.13/6.61 ~ bnd_c4_1 X90) |
% 7.13/6.61 ~ bnd_c8_1 X90))) &
% 7.13/6.61 (((ALL X92.
% 7.13/6.61 bnd_ndr1_0 -->
% 7.13/6.61 (~ bnd_c5_1 X92 | ~ bnd_c6_1 X92) |
% 7.13/6.61 ((bnd_ndr1_1 X92 & bnd_c7_2 X92 bnd_a391) &
% 7.13/6.61 bnd_c8_2 X92 bnd_a391) &
% 7.13/6.61 ~ bnd_c4_2 X92 bnd_a391) |
% 7.13/6.61 bnd_c1_0) |
% 7.13/6.61 (ALL X93.
% 7.13/6.61 bnd_ndr1_0 -->
% 7.13/6.61 ((ALL X94.
% 7.13/6.61 bnd_ndr1_1 X93 --> ~ bnd_c4_2 X93 X94 | bnd_c8_2 X93 X94) |
% 7.13/6.61 ~ bnd_c3_1 X93) |
% 7.13/6.61 (bnd_ndr1_1 X93 & bnd_c2_2 X93 bnd_a392) &
% 7.13/6.61 ~ bnd_c4_2 X93 bnd_a392))) &
% 7.13/6.61 (((ALL X95.
% 7.13/6.61 bnd_ndr1_0 -->
% 7.13/6.61 (bnd_c2_1 X95 |
% 7.13/6.61 (ALL X96.
% 7.13/6.61 bnd_ndr1_1 X95 -->
% 7.13/6.61 (~ bnd_c4_2 X95 X96 | ~ bnd_c5_2 X95 X96) |
% 7.13/6.61 ~ bnd_c7_2 X95 X96)) |
% 7.13/6.61 ~ bnd_c1_1 X95) |
% 7.13/6.61 bnd_c6_0) |
% 7.13/6.61 ((((bnd_ndr1_0 &
% 7.13/6.61 (ALL X97.
% 7.13/6.61 bnd_ndr1_1 bnd_a393 -->
% 7.13/6.61 (~ bnd_c8_2 bnd_a393 X97 | ~ bnd_c3_2 bnd_a393 X97) |
% 7.13/6.61 bnd_c6_2 bnd_a393 X97)) &
% 7.13/6.61 bnd_ndr1_1 bnd_a393) &
% 7.13/6.61 bnd_c1_2 bnd_a393 bnd_a394) &
% 7.13/6.61 ~ bnd_c4_2 bnd_a393 bnd_a394) &
% 7.13/6.61 ~ bnd_c8_2 bnd_a393 bnd_a394)) &
% 7.13/6.61 ((bnd_c3_0 | bnd_c2_0) | bnd_c6_0)) &
% 7.13/6.61 ((ALL X98.
% 7.13/6.61 bnd_ndr1_0 -->
% 7.13/6.61 ((ALL X99. bnd_ndr1_1 X98 --> bnd_c4_2 X98 X99 | ~ bnd_c7_2 X98 X99) |
% 7.13/6.61 (ALL X100.
% 7.13/6.61 bnd_ndr1_1 X98 --> bnd_c3_2 X98 X100 | ~ bnd_c7_2 X98 X100)) |
% 7.13/6.61 (ALL X101.
% 7.13/6.61 bnd_ndr1_1 X98 -->
% 7.13/6.61 (bnd_c3_2 X98 X101 | ~ bnd_c5_2 X98 X101) | bnd_c8_2 X98 X101)) |
% 7.13/6.61 bnd_c5_0)) &
% 7.13/6.61 (((((((bnd_ndr1_0 &
% 7.13/6.61 (ALL X102.
% 7.13/6.61 bnd_ndr1_1 bnd_a395 -->
% 7.13/6.61 (~ bnd_c7_2 bnd_a395 X102 | bnd_c4_2 bnd_a395 X102) |
% 7.13/6.61 ~ bnd_c2_2 bnd_a395 X102)) &
% 7.13/6.61 bnd_ndr1_1 bnd_a395) &
% 7.13/6.61 ~ bnd_c3_2 bnd_a395 bnd_a396) &
% 7.13/6.61 ~ bnd_c2_2 bnd_a395 bnd_a396) &
% 7.13/6.61 bnd_c4_2 bnd_a395 bnd_a396) &
% 7.13/6.61 ~ bnd_c3_1 bnd_a395 |
% 7.13/6.61 bnd_c8_0) |
% 7.13/6.61 ~ bnd_c7_0)) &
% 7.13/6.61 (bnd_c8_0 | ~ bnd_c1_0)) &
% 7.13/6.61 ((((((((((bnd_ndr1_0 &
% 7.13/6.61 bnd_ndr1_1 bnd_a397) &
% 7.13/6.61 bnd_c5_2 bnd_a397 bnd_a398) &
% 7.13/6.61 ~ bnd_c8_2 bnd_a397 bnd_a398) &
% 7.13/6.61 ~ bnd_c7_2 bnd_a397 bnd_a398) &
% 7.13/6.61 bnd_ndr1_1 bnd_a397) &
% 7.13/6.61 ~ bnd_c7_2 bnd_a397 bnd_a399) &
% 7.13/6.61 bnd_c2_2 bnd_a397 bnd_a399) &
% 7.13/6.61 bnd_c1_2 bnd_a397 bnd_a399) &
% 7.13/6.61 ~ bnd_c3_1 bnd_a397 |
% 7.13/6.61 ((bnd_ndr1_0 & bnd_c7_1 bnd_a400) &
% 7.13/6.61 (ALL X103.
% 7.13/6.61 bnd_ndr1_1 bnd_a400 -->
% 7.13/6.61 bnd_c5_2 bnd_a400 X103 | ~ bnd_c1_2 bnd_a400 X103)) &
% 7.13/6.61 bnd_c5_1 bnd_a400) |
% 7.13/6.61 bnd_c5_0)) &
% 7.13/6.61 ((~ bnd_c3_0 | ~ bnd_c7_0) |
% 7.13/6.61 (ALL X104.
% 7.13/6.61 bnd_ndr1_0 -->
% 7.13/6.61 (((bnd_ndr1_1 X104 & ~ bnd_c2_2 X104 bnd_a401) &
% 7.13/6.61 ~ bnd_c7_2 X104 bnd_a401) &
% 7.13/6.61 ~ bnd_c6_2 X104 bnd_a401 |
% 7.13/6.61 ~ bnd_c1_1 X104) |
% 7.13/6.61 (ALL X105.
% 7.13/6.61 bnd_ndr1_1 X104 --> ~ bnd_c2_2 X104 X105 | ~ bnd_c6_2 X104 X105)))) &
% 7.13/6.61 ((bnd_c4_0 |
% 7.13/6.61 (ALL X106.
% 7.13/6.61 bnd_ndr1_0 -->
% 7.13/6.61 ((ALL X107.
% 7.13/6.61 bnd_ndr1_1 X106 -->
% 7.13/6.61 (~ bnd_c2_2 X106 X107 | ~ bnd_c6_2 X106 X107) | bnd_c7_2 X106 X107) |
% 7.13/6.61 bnd_c6_1 X106) |
% 7.13/6.61 bnd_c8_1 X106)) |
% 7.13/6.61 bnd_c3_0)) &
% 7.13/6.61 (bnd_c7_0 |
% 7.13/6.61 (((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a402) &
% 7.13/6.61 ~ bnd_c4_2 bnd_a402 bnd_a403) &
% 7.13/6.61 bnd_c6_2 bnd_a402 bnd_a403) &
% 7.13/6.61 bnd_c3_2 bnd_a402 bnd_a403) &
% 7.13/6.61 (ALL X108.
% 7.13/6.61 bnd_ndr1_1 bnd_a402 -->
% 7.13/6.61 (bnd_c8_2 bnd_a402 X108 | ~ bnd_c6_2 bnd_a402 X108) |
% 7.13/6.61 bnd_c2_2 bnd_a402 X108)) &
% 7.13/6.61 ~ bnd_c7_1 bnd_a402)) &
% 7.13/6.61 ((ALL X109.
% 7.13/6.61 bnd_ndr1_0 -->
% 7.13/6.61 (bnd_c2_1 X109 | bnd_c8_1 X109) |
% 7.13/6.61 ((bnd_ndr1_1 X109 &
% 7.13/6.61 bnd_c1_2 X109 bnd_a404) &
% 7.13/6.61 ~ bnd_c3_2 X109 bnd_a404) &
% 7.13/6.61 ~ bnd_c6_2 X109 bnd_a404) |
% 7.13/6.61 ~ bnd_c8_0)) &
% 7.13/6.61 ((~ bnd_c2_0 |
% 7.13/6.61 (ALL X110.
% 7.13/6.61 bnd_ndr1_0 -->
% 7.13/6.61 (bnd_c8_1 X110 |
% 7.13/6.61 (ALL X111.
% 7.13/6.61 bnd_ndr1_1 X110 -->
% 7.13/6.61 (bnd_c6_2 X110 X111 | bnd_c2_2 X110 X111) | bnd_c3_2 X110 X111)) |
% 7.13/6.61 bnd_c4_1 X110)) |
% 7.13/6.61 (((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a405) &
% 7.13/6.61 ~ bnd_c8_2 bnd_a405 bnd_a406) &
% 7.13/6.61 bnd_c7_2 bnd_a405 bnd_a406) &
% 7.13/6.61 bnd_c2_2 bnd_a405 bnd_a406) &
% 7.13/6.61 bnd_c6_1 bnd_a405) &
% 7.13/6.61 bnd_ndr1_1 bnd_a405) &
% 7.13/6.61 ~ bnd_c5_2 bnd_a405 bnd_a407) &
% 7.13/6.61 ~ bnd_c6_2 bnd_a405 bnd_a407)) &
% 7.13/6.61 ((bnd_c2_0 |
% 7.13/6.61 (((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a408) &
% 7.13/6.61 ~ bnd_c7_2 bnd_a408 bnd_a409) &
% 7.13/6.61 bnd_c4_2 bnd_a408 bnd_a409) &
% 7.13/6.61 bnd_c1_2 bnd_a408 bnd_a409) &
% 7.13/6.61 (ALL X112.
% 7.13/6.61 bnd_ndr1_1 bnd_a408 -->
% 7.13/6.61 bnd_c7_2 bnd_a408 X112 |
% 7.13/6.61 ~ bnd_c3_2 bnd_a408 X112)) &
% 7.13/6.61 bnd_c8_1 bnd_a408) |
% 7.13/6.61 ~ bnd_c5_0)) &
% 7.13/6.61 ((bnd_c4_0 |
% 7.13/6.61 ((bnd_ndr1_0 & bnd_c1_1 bnd_a410) &
% 7.13/6.61 ~ bnd_c6_1 bnd_a410) &
% 7.13/6.61 (ALL X113.
% 7.13/6.61 bnd_ndr1_1 bnd_a410 -->
% 7.13/6.61 ~ bnd_c1_2 bnd_a410 X113 |
% 7.13/6.61 ~ bnd_c2_2 bnd_a410 X113)) |
% 7.13/6.61 (ALL X114.
% 7.13/6.61 bnd_ndr1_0 -->
% 7.13/6.61 (~ bnd_c6_1 X114 | bnd_c8_1 X114) |
% 7.13/6.61 bnd_c5_1 X114))) &
% 7.13/6.61 (((ALL X115.
% 7.13/6.61 bnd_ndr1_0 -->
% 7.13/6.61 ((ALL X116.
% 7.13/6.61 bnd_ndr1_1 X115 -->
% 7.13/6.61 (bnd_c7_2 X115 X116 | bnd_c3_2 X115 X116) | bnd_c6_2 X115 X116) |
% 7.13/6.61 ((bnd_ndr1_1 X115 &
% 7.13/6.61 ~ bnd_c8_2 X115 bnd_a411) &
% 7.13/6.61 ~ bnd_c2_2 X115 bnd_a411) &
% 7.13/6.61 bnd_c3_2 X115 bnd_a411) |
% 7.13/6.61 ((bnd_ndr1_1 X115 &
% 7.13/6.61 bnd_c2_2 X115 bnd_a412) &
% 7.13/6.61 bnd_c6_2 X115 bnd_a412) &
% 7.13/6.61 bnd_c8_2 X115 bnd_a412) |
% 7.13/6.61 ((bnd_ndr1_0 & ~ bnd_c8_1 bnd_a413) &
% 7.13/6.61 ~ bnd_c3_1 bnd_a413) &
% 7.13/6.61 bnd_c4_1 bnd_a413) |
% 7.13/6.61 ~ bnd_c3_0)) &
% 7.13/6.61 ((bnd_c8_0 | ~ bnd_c7_0) | ~ bnd_c3_0)) &
% 7.13/6.61 ((~ bnd_c3_0 | ~ bnd_c5_0) |
% 7.13/6.61 (((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a414) &
% 7.13/6.61 ~ bnd_c7_2 bnd_a414 bnd_a415) &
% 7.13/6.61 ~ bnd_c1_2 bnd_a414 bnd_a415) &
% 7.13/6.61 bnd_c2_2 bnd_a414 bnd_a415) &
% 7.13/6.61 bnd_c5_1 bnd_a414) &
% 7.13/6.61 ~ bnd_c6_1 bnd_a414)) &
% 7.13/6.61 ((bnd_c4_0 | bnd_c5_0) |
% 7.13/6.61 (ALL X117.
% 7.13/6.61 bnd_ndr1_0 -->
% 7.13/6.61 ((bnd_ndr1_1 X117 &
% 7.13/6.61 ~ bnd_c8_2 X117 bnd_a416) &
% 7.13/6.61 ~ bnd_c7_2 X117 bnd_a416) &
% 7.13/6.61 ~ bnd_c4_2 X117 bnd_a416 |
% 7.13/6.61 ~ bnd_c6_1 X117))) &
% 7.13/6.61 ((~ bnd_c7_0 | ~ bnd_c8_0) |
% 7.13/6.61 ((((bnd_ndr1_0 & bnd_c4_1 bnd_a417) &
% 7.13/6.61 bnd_ndr1_1 bnd_a417) &
% 7.13/6.61 ~ bnd_c3_2 bnd_a417 bnd_a418) &
% 7.13/6.61 ~ bnd_c6_2 bnd_a417 bnd_a418) &
% 7.13/6.61 bnd_c5_1 bnd_a417)) &
% 7.13/6.61 ((ALL X118.
% 7.13/6.61 bnd_ndr1_0 -->
% 7.13/6.61 (~ bnd_c7_1 X118 |
% 7.13/6.61 (ALL X119.
% 7.13/6.61 bnd_ndr1_1 X118 -->
% 7.13/6.61 (bnd_c4_2 X118 X119 | bnd_c5_2 X118 X119) |
% 7.13/6.61 ~ bnd_c8_2 X118 X119)) |
% 7.13/6.61 (ALL X120.
% 7.13/6.61 bnd_ndr1_1 X118 -->
% 7.13/6.61 (~ bnd_c6_2 X118 X120 |
% 7.13/6.61 ~ bnd_c5_2 X118 X120) |
% 7.13/6.61 ~ bnd_c7_2 X118 X120)) |
% 7.13/6.61 ((((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a419) &
% 7.13/6.61 bnd_c1_2 bnd_a419 bnd_a420) &
% 7.13/6.61 bnd_c7_2 bnd_a419 bnd_a420) &
% 7.13/6.61 ~ bnd_c2_2 bnd_a419 bnd_a420) &
% 7.13/6.61 ~ bnd_c1_1 bnd_a419) &
% 7.13/6.61 bnd_ndr1_1 bnd_a419) &
% 7.13/6.61 ~ bnd_c3_2 bnd_a419 bnd_a421) &
% 7.13/6.61 bnd_c2_2 bnd_a419 bnd_a421) &
% 7.13/6.61 ~ bnd_c4_2 bnd_a419 bnd_a421)) &
% 7.13/6.61 (((bnd_ndr1_0 & bnd_c6_1 bnd_a422) &
% 7.13/6.61 ~ bnd_c1_1 bnd_a422) &
% 7.13/6.61 bnd_c4_1 bnd_a422 |
% 7.13/6.61 ~ bnd_c1_0)) &
% 7.13/6.61 ((bnd_c6_0 | ~ bnd_c4_0) | bnd_c1_0)) &
% 7.13/6.61 (((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a423) &
% 7.13/6.61 bnd_c8_2 bnd_a423 bnd_a424) &
% 7.13/6.61 bnd_c1_2 bnd_a423 bnd_a424) &
% 7.13/6.61 bnd_c5_2 bnd_a423 bnd_a424) &
% 7.13/6.61 bnd_c4_1 bnd_a423) &
% 7.13/6.61 ~ bnd_c8_1 bnd_a423 |
% 7.13/6.61 ~ bnd_c7_0) |
% 7.13/6.61 (((((bnd_ndr1_0 & ~ bnd_c4_1 bnd_a425) &
% 7.13/6.61 bnd_ndr1_1 bnd_a425) &
% 7.13/6.61 ~ bnd_c1_2 bnd_a425 bnd_a426) &
% 7.13/6.61 bnd_c3_2 bnd_a425 bnd_a426) &
% 7.13/6.61 bnd_c4_2 bnd_a425 bnd_a426) &
% 7.13/6.61 bnd_c3_1 bnd_a425)) &
% 7.13/6.61 ((~ bnd_c2_0 |
% 7.13/6.61 (ALL X121.
% 7.13/6.61 bnd_ndr1_0 -->
% 7.13/6.61 ((bnd_ndr1_1 X121 & bnd_c8_2 X121 bnd_a427) &
% 7.13/6.61 ~ bnd_c1_2 X121 bnd_a427 |
% 7.13/6.61 (ALL X122.
% 7.13/6.61 bnd_ndr1_1 X121 -->
% 7.13/6.61 (~ bnd_c1_2 X121 X122 | bnd_c4_2 X121 X122) |
% 7.13/6.61 bnd_c5_2 X121 X122)) |
% 7.13/6.61 (ALL X123.
% 7.13/6.61 bnd_ndr1_1 X121 -->
% 7.13/6.61 (bnd_c1_2 X121 X123 | bnd_c3_2 X121 X123) |
% 7.13/6.61 bnd_c5_2 X121 X123))) |
% 7.13/6.61 bnd_c6_0)) &
% 7.13/6.61 (((bnd_ndr1_0 &
% 7.13/6.61 (ALL X124.
% 7.13/6.61 bnd_ndr1_1 bnd_a428 -->
% 7.13/6.61 (bnd_c7_2 bnd_a428 X124 |
% 7.13/6.61 ~ bnd_c8_2 bnd_a428 X124) |
% 7.13/6.61 ~ bnd_c5_2 bnd_a428 X124)) &
% 7.13/6.61 bnd_c3_1 bnd_a428 |
% 7.13/6.61 ~ bnd_c8_0) |
% 7.13/6.61 bnd_c2_0)) &
% 7.13/6.61 ((bnd_c2_0 | ~ bnd_c1_0) |
% 7.13/6.61 (ALL X125.
% 7.13/6.61 bnd_ndr1_0 -->
% 7.13/6.61 ((ALL X126.
% 7.13/6.61 bnd_ndr1_1 X125 -->
% 7.13/6.61 bnd_c7_2 X125 X126 | bnd_c5_2 X125 X126) |
% 7.13/6.61 ((bnd_ndr1_1 X125 & bnd_c5_2 X125 bnd_a429) &
% 7.13/6.61 ~ bnd_c6_2 X125 bnd_a429) &
% 7.13/6.61 bnd_c8_2 X125 bnd_a429) |
% 7.13/6.61 ~ bnd_c2_1 X125))) &
% 7.13/6.61 ((~ bnd_c1_0 | bnd_c5_0) | ~ bnd_c3_0)) &
% 7.13/6.61 (((ALL X127.
% 7.13/6.61 bnd_ndr1_0 -->
% 7.13/6.61 (((bnd_ndr1_1 X127 & ~ bnd_c3_2 X127 bnd_a430) &
% 7.13/6.61 bnd_c6_2 X127 bnd_a430) &
% 7.13/6.61 bnd_c2_2 X127 bnd_a430 |
% 7.13/6.61 ~ bnd_c5_1 X127) |
% 7.13/6.61 bnd_c3_1 X127) |
% 7.13/6.61 (ALL X128. bnd_ndr1_0 --> bnd_c5_1 X128 | bnd_c7_1 X128)) |
% 7.13/6.61 ~ bnd_c6_0)) &
% 7.13/6.61 (((ALL X129.
% 7.13/6.61 bnd_ndr1_0 -->
% 7.13/6.61 (bnd_c4_1 X129 | bnd_c7_1 X129) |
% 7.13/6.61 (ALL X130.
% 7.13/6.61 bnd_ndr1_1 X129 -->
% 7.13/6.61 (~ bnd_c5_2 X129 X130 | bnd_c3_2 X129 X130) |
% 7.13/6.61 bnd_c4_2 X129 X130)) |
% 7.13/6.61 bnd_c6_0) |
% 7.13/6.61 ((bnd_ndr1_0 & ~ bnd_c1_1 bnd_a431) &
% 7.13/6.61 (ALL X131.
% 7.13/6.61 bnd_ndr1_1 bnd_a431 -->
% 7.13/6.61 bnd_c1_2 bnd_a431 X131 | bnd_c3_2 bnd_a431 X131)) &
% 7.13/6.61 ~ bnd_c2_1 bnd_a431)) &
% 7.13/6.61 (((ALL X132.
% 7.13/6.61 bnd_ndr1_0 -->
% 7.13/6.61 ((ALL X133.
% 7.13/6.61 bnd_ndr1_1 X132 -->
% 7.13/6.61 (bnd_c4_2 X132 X133 | ~ bnd_c1_2 X132 X133) |
% 7.13/6.61 ~ bnd_c7_2 X132 X133) |
% 7.13/6.61 ((bnd_ndr1_1 X132 & bnd_c6_2 X132 bnd_a432) &
% 7.13/6.61 bnd_c1_2 X132 bnd_a432) &
% 7.13/6.61 ~ bnd_c7_2 X132 bnd_a432) |
% 7.13/6.61 ((bnd_ndr1_1 X132 & bnd_c5_2 X132 bnd_a433) &
% 7.13/6.61 bnd_c2_2 X132 bnd_a433) &
% 7.13/6.61 bnd_c1_2 X132 bnd_a433) |
% 7.13/6.61 (ALL X134.
% 7.13/6.61 bnd_ndr1_0 -->
% 7.13/6.61 (~ bnd_c3_1 X134 | ~ bnd_c5_1 X134) | bnd_c2_1 X134)) |
% 7.13/6.61 bnd_c6_0)) &
% 7.13/6.61 (((ALL X135.
% 7.13/6.61 bnd_ndr1_0 -->
% 7.13/6.61 (bnd_c7_1 X135 | ~ bnd_c5_1 X135) |
% 7.13/6.61 ((bnd_ndr1_1 X135 & ~ bnd_c3_2 X135 bnd_a434) &
% 7.13/6.61 ~ bnd_c6_2 X135 bnd_a434) &
% 7.13/6.61 ~ bnd_c1_2 X135 bnd_a434) |
% 7.13/6.61 (ALL X136.
% 7.13/6.61 bnd_ndr1_0 -->
% 7.13/6.61 bnd_c4_1 X136 |
% 7.13/6.61 (bnd_ndr1_1 X136 & ~ bnd_c5_2 X136 bnd_a435) &
% 7.13/6.61 ~ bnd_c3_2 X136 bnd_a435)) |
% 7.13/6.61 ~ bnd_c7_0)) &
% 7.13/6.61 ((bnd_c6_0 |
% 7.13/6.61 ((bnd_ndr1_0 &
% 7.13/6.61 (ALL X137.
% 7.13/6.61 bnd_ndr1_1 bnd_a436 -->
% 7.13/6.61 (~ bnd_c4_2 bnd_a436 X137 | ~ bnd_c3_2 bnd_a436 X137) |
% 7.13/6.61 ~ bnd_c5_2 bnd_a436 X137)) &
% 7.13/6.61 bnd_c7_1 bnd_a436) &
% 7.13/6.61 (ALL X138.
% 7.13/6.61 bnd_ndr1_1 bnd_a436 -->
% 7.13/6.61 ~ bnd_c5_2 bnd_a436 X138 | bnd_c2_2 bnd_a436 X138)) |
% 7.13/6.61 ~ bnd_c1_0)) &
% 7.13/6.61 ((bnd_c6_0 |
% 7.13/6.61 (ALL X139.
% 7.13/6.61 bnd_ndr1_0 -->
% 7.13/6.61 ((bnd_ndr1_1 X139 & ~ bnd_c7_2 X139 bnd_a437) &
% 7.13/6.61 ~ bnd_c1_2 X139 bnd_a437 |
% 7.13/6.61 (ALL X140.
% 7.13/6.61 bnd_ndr1_1 X139 -->
% 7.13/6.61 (bnd_c1_2 X139 X140 | ~ bnd_c8_2 X139 X140) |
% 7.13/6.61 ~ bnd_c5_2 X139 X140)) |
% 7.13/6.61 bnd_c6_1 X139)) |
% 7.13/6.61 bnd_c4_0)) &
% 7.13/6.61 ((((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a438) &
% 7.13/6.61 ~ bnd_c6_2 bnd_a438 bnd_a439) &
% 7.13/6.61 bnd_c1_2 bnd_a438 bnd_a439) &
% 7.13/6.61 bnd_ndr1_1 bnd_a438) &
% 7.13/6.61 bnd_c4_2 bnd_a438 bnd_a440) &
% 7.13/6.61 ~ bnd_c5_2 bnd_a438 bnd_a440) &
% 7.13/6.61 ~ bnd_c6_2 bnd_a438 bnd_a440 |
% 7.13/6.61 ((bnd_ndr1_0 &
% 7.13/6.61 (ALL X141.
% 7.13/6.61 bnd_ndr1_1 bnd_a441 -->
% 7.13/6.61 bnd_c4_2 bnd_a441 X141 | bnd_c1_2 bnd_a441 X141)) &
% 7.13/6.61 bnd_c5_1 bnd_a441) &
% 7.13/6.61 ~ bnd_c8_1 bnd_a441) |
% 7.13/6.61 ((bnd_ndr1_0 &
% 7.13/6.61 (ALL X142.
% 7.13/6.61 bnd_ndr1_1 bnd_a442 -->
% 7.13/6.61 (bnd_c8_2 bnd_a442 X142 | ~ bnd_c7_2 bnd_a442 X142) |
% 7.13/6.61 bnd_c6_2 bnd_a442 X142)) &
% 7.13/6.61 ~ bnd_c8_1 bnd_a442) &
% 7.13/6.61 ~ bnd_c2_1 bnd_a442)) &
% 7.13/6.61 (((ALL X143.
% 7.13/6.61 bnd_ndr1_0 -->
% 7.13/6.61 ((ALL X144.
% 7.13/6.61 bnd_ndr1_1 X143 -->
% 7.13/6.61 (~ bnd_c7_2 X143 X144 | ~ bnd_c3_2 X143 X144) |
% 7.13/6.61 ~ bnd_c2_2 X143 X144) |
% 7.13/6.61 (ALL X145.
% 7.13/6.61 bnd_ndr1_1 X143 -->
% 7.13/6.61 (bnd_c1_2 X143 X145 | bnd_c8_2 X143 X145) |
% 7.13/6.61 ~ bnd_c2_2 X143 X145)) |
% 7.13/6.61 bnd_c8_1 X143) |
% 7.13/6.61 ~ bnd_c5_0) |
% 7.13/6.61 (ALL X146.
% 7.13/6.61 bnd_ndr1_0 -->
% 7.13/6.61 (~ bnd_c4_1 X146 |
% 7.13/6.61 ((bnd_ndr1_1 X146 & ~ bnd_c5_2 X146 bnd_a443) &
% 7.13/6.61 ~ bnd_c2_2 X146 bnd_a443) &
% 7.13/6.61 ~ bnd_c7_2 X146 bnd_a443) |
% 7.13/6.61 (ALL X147.
% 7.13/6.61 bnd_ndr1_1 X146 -->
% 7.13/6.61 (~ bnd_c7_2 X146 X147 | ~ bnd_c2_2 X146 X147) |
% 7.13/6.61 ~ bnd_c3_2 X146 X147)))) &
% 7.13/6.61 ((~ bnd_c6_0 |
% 7.13/6.61 (ALL X148.
% 7.13/6.61 bnd_ndr1_0 -->
% 7.13/6.61 (~ bnd_c8_1 X148 | ~ bnd_c4_1 X148) |
% 7.13/6.61 ((bnd_ndr1_1 X148 & bnd_c7_2 X148 bnd_a444) &
% 7.13/6.61 bnd_c2_2 X148 bnd_a444) &
% 7.13/6.61 bnd_c4_2 X148 bnd_a444)) |
% 7.13/6.61 ((((((((bnd_ndr1_0 & ~ bnd_c2_1 bnd_a445) & bnd_ndr1_1 bnd_a445) &
% 7.13/6.61 ~ bnd_c5_2 bnd_a445 bnd_a446) &
% 7.13/6.61 bnd_c3_2 bnd_a445 bnd_a446) &
% 7.13/6.61 ~ bnd_c8_2 bnd_a445 bnd_a446) &
% 7.13/6.61 bnd_ndr1_1 bnd_a445) &
% 7.13/6.61 ~ bnd_c5_2 bnd_a445 bnd_a447) &
% 7.13/6.61 ~ bnd_c2_2 bnd_a445 bnd_a447) &
% 7.13/6.61 bnd_c4_2 bnd_a445 bnd_a447)) &
% 7.13/6.61 ((((bnd_ndr1_0 & ~ bnd_c8_1 bnd_a448) &
% 7.13/6.61 (ALL X149.
% 7.13/6.61 bnd_ndr1_1 bnd_a448 -->
% 7.13/6.61 bnd_c3_2 bnd_a448 X149 | ~ bnd_c1_2 bnd_a448 X149)) &
% 7.13/6.61 (ALL X150.
% 7.13/6.61 bnd_ndr1_1 bnd_a448 -->
% 7.13/6.61 (~ bnd_c7_2 bnd_a448 X150 | ~ bnd_c3_2 bnd_a448 X150) |
% 7.13/6.61 ~ bnd_c4_2 bnd_a448 X150) |
% 7.13/6.61 (ALL X151.
% 7.13/6.61 bnd_ndr1_0 -->
% 7.13/6.61 ((ALL X152.
% 7.13/6.61 bnd_ndr1_1 X151 -->
% 7.13/6.61 ~ bnd_c5_2 X151 X152 | bnd_c1_2 X151 X152) |
% 7.13/6.61 (ALL X153.
% 7.13/6.61 bnd_ndr1_1 X151 -->
% 7.13/6.61 (bnd_c5_2 X151 X153 | bnd_c7_2 X151 X153) |
% 7.13/6.61 ~ bnd_c2_2 X151 X153)) |
% 7.13/6.61 (ALL X154.
% 7.13/6.61 bnd_ndr1_1 X151 -->
% 7.13/6.61 (bnd_c3_2 X151 X154 | ~ bnd_c5_2 X151 X154) |
% 7.13/6.61 bnd_c8_2 X151 X154))) |
% 7.13/6.61 bnd_c3_0)) &
% 7.13/6.61 ((((((((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a449) &
% 7.13/6.61 ~ bnd_c7_2 bnd_a449 bnd_a450) &
% 7.13/6.61 bnd_c6_2 bnd_a449 bnd_a450) &
% 7.13/6.61 ~ bnd_c8_2 bnd_a449 bnd_a450) &
% 7.13/6.61 bnd_ndr1_1 bnd_a449) &
% 7.13/6.61 bnd_c8_2 bnd_a449 bnd_a451) &
% 7.13/6.61 ~ bnd_c2_2 bnd_a449 bnd_a451) &
% 7.13/6.61 ~ bnd_c4_2 bnd_a449 bnd_a451) &
% 7.13/6.61 bnd_ndr1_1 bnd_a449) &
% 7.13/6.61 bnd_c7_2 bnd_a449 bnd_a452) &
% 7.13/6.61 ~ bnd_c4_2 bnd_a449 bnd_a452 |
% 7.13/6.61 bnd_c2_0) |
% 7.13/6.61 ~ bnd_c1_0)) &
% 7.13/6.61 ((bnd_c1_0 | bnd_c4_0) |
% 7.13/6.61 ((bnd_ndr1_0 &
% 7.13/6.61 (ALL X155.
% 7.13/6.61 bnd_ndr1_1 bnd_a453 -->
% 7.13/6.61 (~ bnd_c3_2 bnd_a453 X155 | ~ bnd_c2_2 bnd_a453 X155) |
% 7.13/6.61 bnd_c7_2 bnd_a453 X155)) &
% 7.13/6.61 (ALL X156.
% 7.13/6.61 bnd_ndr1_1 bnd_a453 -->
% 7.13/6.61 (bnd_c3_2 bnd_a453 X156 | ~ bnd_c8_2 bnd_a453 X156) |
% 7.13/6.62 ~ bnd_c4_2 bnd_a453 X156)) &
% 7.13/6.62 bnd_c3_1 bnd_a453)) &
% 7.13/6.62 ((~ bnd_c4_0 |
% 7.13/6.62 (((((bnd_ndr1_0 & ~ bnd_c2_1 bnd_a454) & bnd_ndr1_1 bnd_a454) &
% 7.13/6.62 ~ bnd_c2_2 bnd_a454 bnd_a455) &
% 7.13/6.62 bnd_c8_2 bnd_a454 bnd_a455) &
% 7.13/6.62 bnd_c4_2 bnd_a454 bnd_a455) &
% 7.13/6.62 ~ bnd_c1_1 bnd_a454) |
% 7.13/6.62 bnd_c7_0))
% 16.24/15.72 Unfolded term: ~ (((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((~ bnd_c2_0 |
% 16.24/15.72 ~ bnd_c3_0) |
% 16.24/15.72 ((bnd_ndr1_0 & bnd_c8_1 bnd_a298) &
% 16.24/15.72 ~ bnd_c1_1 bnd_a298) &
% 16.24/15.72 ~ bnd_c3_1 bnd_a298) &
% 16.24/15.72 (bnd_c7_0 | bnd_c3_0)) &
% 16.24/15.72 ((bnd_c3_0 |
% 16.24/15.72 ((bnd_ndr1_0 & ~ bnd_c3_1 bnd_a299) &
% 16.24/15.72 (ALL U.
% 16.24/15.72 bnd_ndr1_1 bnd_a299 -->
% 16.24/15.72 (~ bnd_c4_2 bnd_a299 U |
% 16.24/15.72 ~ bnd_c1_2 bnd_a299 U) |
% 16.24/15.72 ~ bnd_c3_2 bnd_a299 U)) &
% 16.24/15.72 ~ bnd_c7_1 bnd_a299) |
% 16.24/15.72 bnd_c8_0)) &
% 16.24/15.72 ((((((bnd_ndr1_0 &
% 16.24/15.72 (ALL V.
% 16.24/15.72 bnd_ndr1_1 bnd_a300 -->
% 16.24/15.72 (bnd_c1_2 bnd_a300 V |
% 16.24/15.72 bnd_c6_2 bnd_a300 V) |
% 16.24/15.72 ~ bnd_c2_2 bnd_a300 V)) &
% 16.24/15.72 bnd_ndr1_1 bnd_a300) &
% 16.24/15.72 bnd_c5_2 bnd_a300 bnd_a301) &
% 16.24/15.72 ~ bnd_c1_2 bnd_a300 bnd_a301) &
% 16.24/15.72 ~ bnd_c2_2 bnd_a300 bnd_a301) &
% 16.24/15.72 bnd_c2_1 bnd_a300 |
% 16.24/15.72 ((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a302) &
% 16.24/15.72 bnd_c6_2 bnd_a302 bnd_a303) &
% 16.24/15.72 ~ bnd_c1_2 bnd_a302 bnd_a303) &
% 16.24/15.72 ~ bnd_c5_2 bnd_a302 bnd_a303) &
% 16.24/15.72 bnd_c2_1 bnd_a302)) &
% 16.24/15.72 (((ALL W.
% 16.24/15.72 bnd_ndr1_0 -->
% 16.24/15.72 ((ALL X.
% 16.24/15.72 bnd_ndr1_1 W -->
% 16.24/15.72 (~ bnd_c8_2 W X | bnd_c3_2 W X) |
% 16.24/15.72 bnd_c2_2 W X) |
% 16.24/15.72 ~ bnd_c5_1 W) |
% 16.24/15.72 (ALL Y.
% 16.24/15.72 bnd_ndr1_1 W -->
% 16.24/15.72 bnd_c5_2 W Y | ~ bnd_c8_2 W Y)) |
% 16.24/15.72 bnd_c6_0) |
% 16.24/15.72 ((bnd_ndr1_0 & bnd_c1_1 bnd_a304) &
% 16.24/15.72 bnd_c3_1 bnd_a304) &
% 16.24/15.72 ~ bnd_c5_1 bnd_a304)) &
% 16.24/15.72 ((~ bnd_c5_0 | ~ bnd_c3_0) | ~ bnd_c1_0)) &
% 16.24/15.72 ((~ bnd_c3_0 |
% 16.24/15.72 (((((bnd_ndr1_0 &
% 16.24/15.72 (ALL Z.
% 16.24/15.72 bnd_ndr1_1 bnd_a305 -->
% 16.24/15.72 (~ bnd_c6_2 bnd_a305 Z |
% 16.24/15.72 bnd_c4_2 bnd_a305 Z) |
% 16.24/15.72 ~ bnd_c8_2 bnd_a305 Z)) &
% 16.24/15.72 ~ bnd_c5_1 bnd_a305) &
% 16.24/15.72 bnd_ndr1_1 bnd_a305) &
% 16.24/15.72 ~ bnd_c3_2 bnd_a305 bnd_a306) &
% 16.24/15.72 bnd_c2_2 bnd_a305 bnd_a306) &
% 16.24/15.72 bnd_c8_2 bnd_a305 bnd_a306) |
% 16.24/15.72 bnd_c1_0)) &
% 16.24/15.72 ((bnd_c4_0 |
% 16.24/15.72 ((((bnd_ndr1_0 & bnd_c1_1 bnd_a307) &
% 16.24/15.72 bnd_ndr1_1 bnd_a307) &
% 16.24/15.72 ~ bnd_c6_2 bnd_a307 bnd_a308) &
% 16.24/15.72 bnd_c3_2 bnd_a307 bnd_a308) &
% 16.24/15.72 (ALL X1.
% 16.24/15.72 bnd_ndr1_1 bnd_a307 -->
% 16.24/15.72 (bnd_c5_2 bnd_a307 X1 | bnd_c7_2 bnd_a307 X1) |
% 16.24/15.72 bnd_c1_2 bnd_a307 X1)) |
% 16.24/15.72 bnd_c8_0)) &
% 16.24/15.72 (bnd_c6_0 | bnd_c7_0)) &
% 16.24/15.72 (((bnd_ndr1_0 & ~ bnd_c7_1 bnd_a309) &
% 16.24/15.72 (ALL X2.
% 16.24/15.72 bnd_ndr1_1 bnd_a309 -->
% 16.24/15.72 (bnd_c3_2 bnd_a309 X2 | ~ bnd_c2_2 bnd_a309 X2) |
% 16.24/15.72 bnd_c6_2 bnd_a309 X2)) &
% 16.24/15.72 bnd_c3_1 bnd_a309 |
% 16.24/15.72 bnd_c5_0)) &
% 16.24/15.72 (((ALL X3.
% 16.24/15.72 bnd_ndr1_0 -->
% 16.24/15.72 (~ bnd_c1_1 X3 | bnd_c4_1 X3) | bnd_c8_1 X3) |
% 16.24/15.72 (ALL X4.
% 16.24/15.72 bnd_ndr1_0 -->
% 16.24/15.72 (~ bnd_c1_1 X4 | ~ bnd_c2_1 X4) | ~ bnd_c8_1 X4)) |
% 16.24/15.72 bnd_c8_0)) &
% 16.24/15.72 (((ALL X5.
% 16.24/15.72 bnd_ndr1_0 -->
% 16.24/15.72 (bnd_c4_1 X5 |
% 16.24/15.72 (ALL X6.
% 16.24/15.72 bnd_ndr1_1 X5 -->
% 16.24/15.72 (~ bnd_c1_2 X5 X6 | bnd_c7_2 X5 X6) |
% 16.24/15.72 ~ bnd_c5_2 X5 X6)) |
% 16.24/15.72 ((bnd_ndr1_1 X5 & bnd_c7_2 X5 bnd_a310) &
% 16.24/15.72 bnd_c6_2 X5 bnd_a310) &
% 16.24/15.72 ~ bnd_c3_2 X5 bnd_a310) |
% 16.24/15.72 ~ bnd_c6_0) |
% 16.24/15.72 bnd_c7_0)) &
% 16.24/15.72 ((~ bnd_c5_0 | ~ bnd_c7_0) | ~ bnd_c6_0)) &
% 16.24/15.72 (bnd_c7_0 | ~ bnd_c5_0)) &
% 16.24/15.72 ((((((((((bnd_ndr1_0 &
% 16.24/15.72 (ALL X7.
% 16.24/15.72 bnd_ndr1_1 bnd_a311 -->
% 16.24/15.72 ~ bnd_c7_2 bnd_a311 X7 |
% 16.24/15.72 ~ bnd_c8_2 bnd_a311 X7)) &
% 16.24/15.72 bnd_ndr1_1 bnd_a311) &
% 16.24/15.72 bnd_c1_2 bnd_a311 bnd_a312) &
% 16.24/15.72 ~ bnd_c4_2 bnd_a311 bnd_a312) &
% 16.24/15.72 ~ bnd_c5_2 bnd_a311 bnd_a312) &
% 16.24/15.72 bnd_ndr1_1 bnd_a311) &
% 16.24/15.72 ~ bnd_c7_2 bnd_a311 bnd_a313) &
% 16.24/15.72 ~ bnd_c4_2 bnd_a311 bnd_a313) &
% 16.24/15.72 ~ bnd_c5_2 bnd_a311 bnd_a313 |
% 16.24/15.72 bnd_c5_0) |
% 16.24/15.72 ~ bnd_c2_0)) &
% 16.24/15.72 ((~ bnd_c4_0 |
% 16.24/15.72 ((bnd_ndr1_0 & bnd_c6_1 bnd_a314) & ~ bnd_c1_1 bnd_a314) &
% 16.24/15.72 ~ bnd_c8_1 bnd_a314) |
% 16.24/15.72 bnd_c8_0)) &
% 16.24/15.72 ((bnd_c3_0 |
% 16.24/15.72 (ALL X8.
% 16.24/15.72 bnd_ndr1_0 -->
% 16.24/15.72 (bnd_c2_1 X8 | bnd_c7_1 X8) |
% 16.24/15.72 (ALL X9.
% 16.24/15.72 bnd_ndr1_1 X8 -->
% 16.24/15.72 (~ bnd_c6_2 X8 X9 | ~ bnd_c2_2 X8 X9) |
% 16.24/15.72 bnd_c1_2 X8 X9))) |
% 16.24/15.72 ~ bnd_c2_0)) &
% 16.24/15.72 ((((bnd_ndr1_0 & ~ bnd_c4_1 bnd_a315) &
% 16.24/15.72 (ALL X10.
% 16.24/15.72 bnd_ndr1_1 bnd_a315 -->
% 16.24/15.72 (~ bnd_c2_2 bnd_a315 X10 | ~ bnd_c5_2 bnd_a315 X10) |
% 16.24/15.72 ~ bnd_c1_2 bnd_a315 X10)) &
% 16.24/15.72 ~ bnd_c2_1 bnd_a315 |
% 16.24/15.72 ~ bnd_c6_0) |
% 16.24/15.72 bnd_ndr1_0 & bnd_c4_1 bnd_a316)) &
% 16.24/15.72 ((~ bnd_c8_0 |
% 16.24/15.72 ((bnd_ndr1_0 &
% 16.24/15.72 (ALL X11.
% 16.24/15.72 bnd_ndr1_1 bnd_a317 -->
% 16.24/15.72 (bnd_c3_2 bnd_a317 X11 | bnd_c6_2 bnd_a317 X11) |
% 16.24/15.72 bnd_c7_2 bnd_a317 X11)) &
% 16.24/15.72 bnd_c8_1 bnd_a317) &
% 16.24/15.72 (ALL X12.
% 16.24/15.72 bnd_ndr1_1 bnd_a317 -->
% 16.24/15.72 (bnd_c4_2 bnd_a317 X12 | bnd_c8_2 bnd_a317 X12) |
% 16.24/15.72 bnd_c5_2 bnd_a317 X12)) |
% 16.24/15.72 (ALL X13.
% 16.24/15.72 bnd_ndr1_0 -->
% 16.24/15.72 (ALL X14.
% 16.24/15.72 bnd_ndr1_1 X13 -->
% 16.24/15.72 (bnd_c3_2 X13 X14 | ~ bnd_c1_2 X13 X14) |
% 16.24/15.72 ~ bnd_c8_2 X13 X14) |
% 16.24/15.72 ((bnd_ndr1_1 X13 & bnd_c7_2 X13 bnd_a318) &
% 16.24/15.72 ~ bnd_c2_2 X13 bnd_a318) &
% 16.24/15.72 ~ bnd_c1_2 X13 bnd_a318))) &
% 16.24/15.72 ((bnd_c2_0 | ~ bnd_c4_0) | bnd_c3_0)) &
% 16.24/15.72 ((~ bnd_c4_0 | ~ bnd_c6_0) |
% 16.24/15.72 (ALL X15.
% 16.24/15.72 bnd_ndr1_0 -->
% 16.24/15.72 ((ALL X16.
% 16.24/15.72 bnd_ndr1_1 X15 --> bnd_c8_2 X15 X16 | bnd_c6_2 X15 X16) |
% 16.24/15.72 ((bnd_ndr1_1 X15 & bnd_c5_2 X15 bnd_a319) &
% 16.24/15.72 ~ bnd_c7_2 X15 bnd_a319) &
% 16.24/15.72 bnd_c4_2 X15 bnd_a319) |
% 16.24/15.72 (ALL X17.
% 16.24/15.72 bnd_ndr1_1 X15 -->
% 16.24/15.72 (bnd_c1_2 X15 X17 | ~ bnd_c2_2 X15 X17) |
% 16.24/15.72 bnd_c5_2 X15 X17)))) &
% 16.24/15.72 (((ALL X18.
% 16.24/15.72 bnd_ndr1_0 -->
% 16.24/15.72 (((bnd_ndr1_1 X18 & bnd_c1_2 X18 bnd_a320) &
% 16.24/15.72 bnd_c3_2 X18 bnd_a320) &
% 16.24/15.72 bnd_c4_2 X18 bnd_a320 |
% 16.24/15.72 ~ bnd_c6_1 X18) |
% 16.24/15.72 (ALL X19.
% 16.24/15.72 bnd_ndr1_1 X18 --> bnd_c4_2 X18 X19 | ~ bnd_c7_2 X18 X19)) |
% 16.24/15.72 (ALL X20.
% 16.24/15.72 bnd_ndr1_0 --> (~ bnd_c6_1 X20 | bnd_c4_1 X20) | bnd_c1_1 X20)) |
% 16.24/15.72 ((((bnd_ndr1_0 &
% 16.24/15.72 (ALL X21.
% 16.24/15.72 bnd_ndr1_1 bnd_a321 -->
% 16.24/15.72 (~ bnd_c2_2 bnd_a321 X21 | ~ bnd_c4_2 bnd_a321 X21) |
% 16.24/15.72 bnd_c6_2 bnd_a321 X21)) &
% 16.24/15.72 bnd_ndr1_1 bnd_a321) &
% 16.24/15.72 ~ bnd_c8_2 bnd_a321 bnd_a322) &
% 16.24/15.72 ~ bnd_c6_2 bnd_a321 bnd_a322) &
% 16.24/15.72 bnd_c5_2 bnd_a321 bnd_a322)) &
% 16.24/15.72 ((((((bnd_ndr1_0 & bnd_c1_1 bnd_a323) & bnd_ndr1_1 bnd_a323) &
% 16.24/15.72 bnd_c4_2 bnd_a323 bnd_a324) &
% 16.24/15.72 ~ bnd_c6_2 bnd_a323 bnd_a324) &
% 16.24/15.72 ~ bnd_c5_2 bnd_a323 bnd_a324 |
% 16.24/15.72 ((bnd_ndr1_0 & bnd_c4_1 bnd_a325) &
% 16.24/15.72 (ALL X22.
% 16.24/15.72 bnd_ndr1_1 bnd_a325 -->
% 16.24/15.72 (~ bnd_c7_2 bnd_a325 X22 | ~ bnd_c5_2 bnd_a325 X22) |
% 16.24/15.72 ~ bnd_c1_2 bnd_a325 X22)) &
% 16.24/15.72 bnd_c6_1 bnd_a325) |
% 16.24/15.72 bnd_c2_0)) &
% 16.24/15.72 ((ALL X23.
% 16.24/15.72 bnd_ndr1_0 -->
% 16.24/15.72 ((ALL X24.
% 16.24/15.72 bnd_ndr1_1 X23 --> ~ bnd_c1_2 X23 X24 | ~ bnd_c6_2 X23 X24) |
% 16.24/15.72 (ALL X25.
% 16.24/15.72 bnd_ndr1_1 X23 -->
% 16.24/15.72 (bnd_c5_2 X23 X25 | bnd_c7_2 X23 X25) | ~ bnd_c8_2 X23 X25)) |
% 16.24/15.72 ~ bnd_c5_1 X23) |
% 16.24/15.72 (((((bnd_ndr1_0 & bnd_c8_1 bnd_a326) & bnd_ndr1_1 bnd_a326) &
% 16.24/15.72 ~ bnd_c1_2 bnd_a326 bnd_a327) &
% 16.24/15.72 bnd_c8_2 bnd_a326 bnd_a327) &
% 16.24/15.72 ~ bnd_c2_2 bnd_a326 bnd_a327) &
% 16.24/15.72 (ALL X26.
% 16.24/15.72 bnd_ndr1_1 bnd_a326 -->
% 16.24/15.72 ~ bnd_c8_2 bnd_a326 X26 | bnd_c7_2 bnd_a326 X26))) &
% 16.24/15.72 (((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a328) & bnd_c5_2 bnd_a328 bnd_a329) &
% 16.24/15.72 bnd_c2_2 bnd_a328 bnd_a329) &
% 16.24/15.72 ~ bnd_c4_2 bnd_a328 bnd_a329) &
% 16.24/15.72 bnd_c6_1 bnd_a328) &
% 16.24/15.72 ~ bnd_c4_1 bnd_a328 |
% 16.24/15.72 ~ bnd_c2_0) |
% 16.24/15.72 ((((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a330) &
% 16.24/15.72 ~ bnd_c5_2 bnd_a330 bnd_a331) &
% 16.24/15.72 bnd_c6_2 bnd_a330 bnd_a331) &
% 16.24/15.72 ~ bnd_c1_2 bnd_a330 bnd_a331) &
% 16.24/15.72 bnd_ndr1_1 bnd_a330) &
% 16.24/15.72 ~ bnd_c8_2 bnd_a330 bnd_a332) &
% 16.24/15.72 ~ bnd_c2_2 bnd_a330 bnd_a332) &
% 16.24/15.72 ~ bnd_c5_2 bnd_a330 bnd_a332) &
% 16.24/15.72 ~ bnd_c6_1 bnd_a330)) &
% 16.24/15.72 ((~ bnd_c3_0 |
% 16.24/15.72 (ALL X27.
% 16.24/15.72 bnd_ndr1_0 -->
% 16.24/15.72 (bnd_c4_1 X27 |
% 16.24/15.72 ((bnd_ndr1_1 X27 & ~ bnd_c7_2 X27 bnd_a333) &
% 16.24/15.72 bnd_c2_2 X27 bnd_a333) &
% 16.24/15.72 bnd_c6_2 X27 bnd_a333) |
% 16.24/15.72 (ALL X28.
% 16.24/15.72 bnd_ndr1_1 X27 -->
% 16.24/15.72 (~ bnd_c1_2 X27 X28 | ~ bnd_c5_2 X27 X28) | bnd_c8_2 X27 X28))) |
% 16.24/15.72 (((((bnd_ndr1_0 & ~ bnd_c6_1 bnd_a334) & ~ bnd_c1_1 bnd_a334) &
% 16.24/15.72 bnd_ndr1_1 bnd_a334) &
% 16.24/15.72 ~ bnd_c3_2 bnd_a334 bnd_a335) &
% 16.24/15.72 ~ bnd_c4_2 bnd_a334 bnd_a335) &
% 16.24/15.72 bnd_c5_2 bnd_a334 bnd_a335)) &
% 16.24/15.72 ((~ bnd_c5_0 | bnd_c6_0) | bnd_c7_0)) &
% 16.24/15.72 (((bnd_ndr1_0 & bnd_c5_1 bnd_a336) &
% 16.24/15.72 bnd_c3_1 bnd_a336 |
% 16.24/15.72 ~ bnd_c1_0) |
% 16.24/15.72 ~ bnd_c8_0)) &
% 16.24/15.72 ((~ bnd_c8_0 | ~ bnd_c6_0) |
% 16.24/15.72 bnd_c3_0)) &
% 16.24/15.72 ((~ bnd_c2_0 | ~ bnd_c5_0) | bnd_c7_0)) &
% 16.24/15.72 (((ALL X29.
% 16.24/15.72 bnd_ndr1_0 -->
% 16.24/15.72 (bnd_c3_1 X29 | ~ bnd_c2_1 X29) |
% 16.24/15.72 ((bnd_ndr1_1 X29 & bnd_c8_2 X29 bnd_a337) & bnd_c5_2 X29 bnd_a337) &
% 16.24/15.72 ~ bnd_c7_2 X29 bnd_a337) |
% 16.24/15.72 bnd_ndr1_0 & bnd_c1_1 bnd_a338) |
% 16.24/15.72 bnd_c4_0)) &
% 16.24/15.72 (((ALL X30.
% 16.24/15.72 bnd_ndr1_0 -->
% 16.24/15.72 (ALL X31.
% 16.24/15.72 bnd_ndr1_1 X30 -->
% 16.24/15.72 (bnd_c1_2 X30 X31 | bnd_c8_2 X30 X31) | ~ bnd_c4_2 X30 X31) |
% 16.24/15.72 ~ bnd_c2_1 X30) |
% 16.24/15.72 ~ bnd_c6_0) |
% 16.24/15.72 ~ bnd_c5_0)) &
% 16.24/15.72 ((((bnd_ndr1_0 & ~ bnd_c2_1 bnd_a339) &
% 16.24/15.72 (ALL X32.
% 16.24/15.72 bnd_ndr1_1 bnd_a339 --> bnd_c8_2 bnd_a339 X32 | bnd_c2_2 bnd_a339 X32)) &
% 16.24/15.72 (ALL X33.
% 16.24/15.72 bnd_ndr1_1 bnd_a339 --> bnd_c8_2 bnd_a339 X33 | ~ bnd_c7_2 bnd_a339 X33) |
% 16.24/15.72 bnd_c3_0) |
% 16.24/15.72 ~ bnd_c2_0)) &
% 16.24/15.72 ((ALL X34.
% 16.24/15.72 bnd_ndr1_0 -->
% 16.24/15.72 (((bnd_ndr1_1 X34 &
% 16.24/15.72 ~ bnd_c8_2 X34 bnd_a340) &
% 16.24/15.72 bnd_c6_2 X34 bnd_a340) &
% 16.24/15.72 ~ bnd_c3_2 X34 bnd_a340 |
% 16.24/15.72 (bnd_ndr1_1 X34 &
% 16.24/15.72 bnd_c1_2 X34 bnd_a341) &
% 16.24/15.72 bnd_c7_2 X34 bnd_a341) |
% 16.24/15.72 ~ bnd_c2_1 X34) |
% 16.24/15.72 bnd_c2_0)) &
% 16.24/15.72 ((bnd_c5_0 |
% 16.24/15.72 (ALL X35.
% 16.24/15.72 bnd_ndr1_0 -->
% 16.24/15.72 ((ALL X36.
% 16.24/15.72 bnd_ndr1_1 X35 --> bnd_c7_2 X35 X36 | ~ bnd_c5_2 X35 X36) |
% 16.24/15.72 bnd_c5_1 X35) |
% 16.24/15.72 bnd_c8_1 X35)) |
% 16.24/15.72 (ALL X37.
% 16.24/15.72 bnd_ndr1_0 -->
% 16.24/15.72 ((ALL X38.
% 16.24/15.72 bnd_ndr1_1 X37 --> bnd_c8_2 X37 X38 | bnd_c3_2 X37 X38) |
% 16.24/15.72 ~ bnd_c2_1 X37) |
% 16.24/15.72 (ALL X39.
% 16.24/15.72 bnd_ndr1_1 X37 -->
% 16.24/15.72 (~ bnd_c6_2 X37 X39 | bnd_c8_2 X37 X39) | bnd_c7_2 X37 X39)))) &
% 16.24/15.72 (((ALL X40.
% 16.24/15.72 bnd_ndr1_0 -->
% 16.24/15.72 (bnd_c3_1 X40 | bnd_c1_1 X40) |
% 16.24/15.72 ~ bnd_c2_1 X40) |
% 16.24/15.72 (((((bnd_ndr1_0 &
% 16.24/15.72 (ALL X41.
% 16.24/15.72 bnd_ndr1_1 bnd_a342 --> bnd_c4_2 bnd_a342 X41 | bnd_c5_2 bnd_a342 X41)) &
% 16.24/15.72 (ALL X42.
% 16.24/15.72 bnd_ndr1_1 bnd_a342 -->
% 16.24/15.72 (bnd_c5_2 bnd_a342 X42 | ~ bnd_c8_2 bnd_a342 X42) |
% 16.24/15.72 ~ bnd_c4_2 bnd_a342 X42)) &
% 16.24/15.72 bnd_ndr1_1 bnd_a342) &
% 16.24/15.72 bnd_c7_2 bnd_a342 bnd_a343) &
% 16.24/15.72 bnd_c8_2 bnd_a342 bnd_a343) &
% 16.24/15.72 ~ bnd_c4_2 bnd_a342 bnd_a343) |
% 16.24/15.72 (ALL X43.
% 16.24/15.72 bnd_ndr1_0 -->
% 16.24/15.72 (((bnd_ndr1_1 X43 &
% 16.24/15.72 bnd_c4_2 X43 bnd_a344) &
% 16.24/15.72 bnd_c7_2 X43 bnd_a344) &
% 16.24/15.72 ~ bnd_c6_2 X43 bnd_a344 |
% 16.24/15.72 (ALL X44.
% 16.24/15.72 bnd_ndr1_1 X43 --> ~ bnd_c6_2 X43 X44 | bnd_c4_2 X43 X44)) |
% 16.24/15.72 bnd_c6_1 X43))) &
% 16.24/15.72 ((bnd_c6_0 | ~ bnd_c4_0) | ~ bnd_c3_0)) &
% 16.24/15.72 ((~ bnd_c6_0 |
% 16.24/15.72 (((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a345) &
% 16.24/15.72 bnd_c5_2 bnd_a345 bnd_a346) &
% 16.24/15.72 ~ bnd_c1_2 bnd_a345 bnd_a346) &
% 16.24/15.72 bnd_c2_2 bnd_a345 bnd_a346) &
% 16.24/15.72 bnd_c2_1 bnd_a345) &
% 16.24/15.72 bnd_c6_1 bnd_a345) |
% 16.24/15.72 (((((bnd_ndr1_0 & bnd_c4_1 bnd_a347) &
% 16.24/15.72 bnd_ndr1_1 bnd_a347) &
% 16.24/15.72 bnd_c2_2 bnd_a347 bnd_a348) &
% 16.24/15.72 ~ bnd_c4_2 bnd_a347 bnd_a348) &
% 16.24/15.72 bnd_c3_2 bnd_a347 bnd_a348) &
% 16.24/15.72 bnd_c8_1 bnd_a347)) &
% 16.24/15.72 ((((bnd_ndr1_0 & ~ bnd_c3_1 bnd_a349) &
% 16.24/15.72 ~ bnd_c5_1 bnd_a349) &
% 16.24/15.72 ~ bnd_c8_1 bnd_a349 |
% 16.24/15.72 bnd_c1_0) |
% 16.24/15.72 ~ bnd_c5_0)) &
% 16.24/15.72 ((((bnd_ndr1_0 &
% 16.24/15.72 (ALL X45.
% 16.24/15.72 bnd_ndr1_1 bnd_a350 -->
% 16.24/15.72 (bnd_c1_2 bnd_a350 X45 |
% 16.24/15.72 bnd_c8_2 bnd_a350 X45) |
% 16.24/15.72 bnd_c4_2 bnd_a350 X45)) &
% 16.24/15.72 (ALL X46.
% 16.24/15.72 bnd_ndr1_1 bnd_a350 -->
% 16.24/15.72 (~ bnd_c3_2 bnd_a350 X46 |
% 16.24/15.72 bnd_c4_2 bnd_a350 X46) |
% 16.24/15.72 ~ bnd_c5_2 bnd_a350 X46)) &
% 16.24/15.72 (ALL X47.
% 16.24/15.72 bnd_ndr1_1 bnd_a350 -->
% 16.24/15.72 (bnd_c2_2 bnd_a350 X47 |
% 16.24/15.72 ~ bnd_c6_2 bnd_a350 X47) |
% 16.24/15.72 bnd_c4_2 bnd_a350 X47) |
% 16.24/15.72 (bnd_ndr1_0 &
% 16.24/15.72 (ALL X48.
% 16.24/15.72 bnd_ndr1_1 bnd_a351 -->
% 16.24/15.72 (bnd_c1_2 bnd_a351 X48 |
% 16.24/15.72 ~ bnd_c6_2 bnd_a351 X48) |
% 16.24/15.72 ~ bnd_c7_2 bnd_a351 X48)) &
% 16.24/15.72 (ALL X49.
% 16.24/15.72 bnd_ndr1_1 bnd_a351 -->
% 16.24/15.72 (bnd_c2_2 bnd_a351 X49 |
% 16.24/15.72 bnd_c4_2 bnd_a351 X49) |
% 16.24/15.72 bnd_c5_2 bnd_a351 X49)) |
% 16.24/15.72 (((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a352) &
% 16.24/15.72 bnd_c6_2 bnd_a352 bnd_a353) &
% 16.24/15.72 bnd_c4_2 bnd_a352 bnd_a353) &
% 16.24/15.72 ~ bnd_c8_2 bnd_a352 bnd_a353) &
% 16.24/15.72 (ALL X50.
% 16.24/15.72 bnd_ndr1_1 bnd_a352 -->
% 16.24/15.72 (~ bnd_c5_2 bnd_a352 X50 |
% 16.24/15.72 ~ bnd_c8_2 bnd_a352 X50) |
% 16.24/15.72 bnd_c1_2 bnd_a352 X50)) &
% 16.24/15.72 bnd_c2_1 bnd_a352)) &
% 16.24/15.72 ((((bnd_ndr1_0 & bnd_c5_1 bnd_a354) &
% 16.24/15.72 (ALL X51.
% 16.24/15.72 bnd_ndr1_1 bnd_a354 -->
% 16.24/15.72 ~ bnd_c2_2 bnd_a354 X51 |
% 16.24/15.72 bnd_c8_2 bnd_a354 X51)) &
% 16.24/15.72 ~ bnd_c2_1 bnd_a354 |
% 16.24/15.72 (((((bnd_ndr1_0 & bnd_c6_1 bnd_a355) &
% 16.24/15.72 bnd_ndr1_1 bnd_a355) &
% 16.24/15.72 bnd_c1_2 bnd_a355 bnd_a356) &
% 16.24/15.72 ~ bnd_c6_2 bnd_a355 bnd_a356) &
% 16.24/15.72 bnd_c8_2 bnd_a355 bnd_a356) &
% 16.24/15.72 ~ bnd_c2_1 bnd_a355) |
% 16.24/15.72 ~ bnd_c7_0)) &
% 16.24/15.72 ((bnd_c1_0 | bnd_c4_0) | bnd_c8_0)) &
% 16.24/15.72 (~ bnd_c1_0 | bnd_c8_0)) &
% 16.24/15.72 ((bnd_c3_0 | ~ bnd_c5_0) |
% 16.24/15.72 (ALL X52.
% 16.24/15.72 bnd_ndr1_0 -->
% 16.24/15.72 ((ALL X53.
% 16.24/15.72 bnd_ndr1_1 X52 -->
% 16.24/15.72 (~ bnd_c6_2 X52 X53 | bnd_c2_2 X52 X53) |
% 16.24/15.72 bnd_c1_2 X52 X53) |
% 16.24/15.72 ~ bnd_c4_1 X52) |
% 16.24/15.72 ~ bnd_c6_1 X52))) &
% 16.24/15.72 (((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a357) &
% 16.24/15.72 ~ bnd_c3_2 bnd_a357 bnd_a358) &
% 16.24/15.72 bnd_c7_2 bnd_a357 bnd_a358) &
% 16.24/15.72 ~ bnd_c6_2 bnd_a357 bnd_a358) &
% 16.24/15.72 (ALL X54.
% 16.24/15.72 bnd_ndr1_1 bnd_a357 -->
% 16.24/15.72 (bnd_c1_2 bnd_a357 X54 |
% 16.24/15.72 ~ bnd_c4_2 bnd_a357 X54) |
% 16.24/15.72 ~ bnd_c5_2 bnd_a357 X54)) &
% 16.24/15.72 (ALL X55.
% 16.24/15.72 bnd_ndr1_1 bnd_a357 -->
% 16.24/15.72 (bnd_c5_2 bnd_a357 X55 |
% 16.24/15.72 ~ bnd_c7_2 bnd_a357 X55) |
% 16.24/15.72 ~ bnd_c8_2 bnd_a357 X55) |
% 16.24/15.72 (ALL X56.
% 16.24/15.72 bnd_ndr1_0 -->
% 16.24/15.72 (((bnd_ndr1_1 X56 & ~ bnd_c6_2 X56 bnd_a359) &
% 16.24/15.72 bnd_c8_2 X56 bnd_a359) &
% 16.24/15.72 ~ bnd_c4_2 X56 bnd_a359 |
% 16.24/15.72 (ALL X57.
% 16.24/15.72 bnd_ndr1_1 X56 -->
% 16.24/15.72 (bnd_c7_2 X56 X57 | bnd_c4_2 X56 X57) |
% 16.24/15.72 ~ bnd_c1_2 X56 X57)) |
% 16.24/15.72 ((bnd_ndr1_1 X56 & ~ bnd_c5_2 X56 bnd_a360) &
% 16.24/15.72 ~ bnd_c4_2 X56 bnd_a360) &
% 16.24/15.72 ~ bnd_c8_2 X56 bnd_a360)) |
% 16.24/15.72 (ALL X58.
% 16.24/15.72 bnd_ndr1_0 -->
% 16.24/15.72 ((bnd_ndr1_1 X58 & bnd_c7_2 X58 bnd_a361) &
% 16.24/15.72 ~ bnd_c5_2 X58 bnd_a361) &
% 16.24/15.72 ~ bnd_c4_2 X58 bnd_a361 |
% 16.24/15.72 ~ bnd_c6_1 X58))) &
% 16.24/15.72 (((ALL X59.
% 16.24/15.72 bnd_ndr1_0 -->
% 16.24/15.72 (~ bnd_c7_1 X59 |
% 16.24/15.72 (ALL X60.
% 16.24/15.72 bnd_ndr1_1 X59 -->
% 16.24/15.72 (bnd_c4_2 X59 X60 | ~ bnd_c7_2 X59 X60) |
% 16.24/15.72 bnd_c2_2 X59 X60)) |
% 16.24/15.72 (ALL X61.
% 16.24/15.72 bnd_ndr1_1 X59 -->
% 16.24/15.72 (bnd_c7_2 X59 X61 | ~ bnd_c3_2 X59 X61) |
% 16.24/15.72 bnd_c5_2 X59 X61)) |
% 16.24/15.72 (((((bnd_ndr1_0 & bnd_c5_1 bnd_a362) &
% 16.24/15.72 bnd_ndr1_1 bnd_a362) &
% 16.24/15.72 ~ bnd_c6_2 bnd_a362 bnd_a363) &
% 16.24/15.72 bnd_c2_2 bnd_a362 bnd_a363) &
% 16.24/15.72 ~ bnd_c1_2 bnd_a362 bnd_a363) &
% 16.24/15.72 (ALL X62.
% 16.24/15.72 bnd_ndr1_1 bnd_a362 -->
% 16.24/15.72 (bnd_c6_2 bnd_a362 X62 | ~ bnd_c2_2 bnd_a362 X62) |
% 16.24/15.72 bnd_c5_2 bnd_a362 X62)) |
% 16.24/15.72 (ALL X63.
% 16.24/15.72 bnd_ndr1_0 -->
% 16.24/15.72 ((ALL X64.
% 16.24/15.72 bnd_ndr1_1 X63 -->
% 16.24/15.72 ~ bnd_c3_2 X63 X64 | ~ bnd_c8_2 X63 X64) |
% 16.24/15.72 bnd_c8_1 X63) |
% 16.24/15.72 (ALL X65.
% 16.24/15.72 bnd_ndr1_1 X63 -->
% 16.24/15.72 (~ bnd_c7_2 X63 X65 | ~ bnd_c2_2 X63 X65) |
% 16.24/15.72 ~ bnd_c8_2 X63 X65)))) &
% 16.24/15.72 (((ALL X66.
% 16.24/15.72 bnd_ndr1_0 -->
% 16.24/15.72 (bnd_c4_1 X66 | ~ bnd_c1_1 X66) | ~ bnd_c2_1 X66) |
% 16.24/15.72 (ALL X67.
% 16.24/15.72 bnd_ndr1_0 -->
% 16.24/15.72 ((ALL X68.
% 16.24/15.72 bnd_ndr1_1 X67 -->
% 16.24/15.72 (bnd_c5_2 X67 X68 | ~ bnd_c8_2 X67 X68) |
% 16.24/15.72 ~ bnd_c6_2 X67 X68) |
% 16.24/15.72 ((bnd_ndr1_1 X67 & bnd_c2_2 X67 bnd_a364) &
% 16.24/15.72 ~ bnd_c4_2 X67 bnd_a364) &
% 16.24/15.72 bnd_c8_2 X67 bnd_a364) |
% 16.24/15.72 bnd_c8_1 X67)) |
% 16.24/15.72 (ALL X69.
% 16.24/15.72 bnd_ndr1_0 -->
% 16.24/15.72 (bnd_c1_1 X69 |
% 16.24/15.72 (ALL X70.
% 16.24/15.72 bnd_ndr1_1 X69 -->
% 16.24/15.72 (bnd_c5_2 X69 X70 | bnd_c8_2 X69 X70) |
% 16.24/15.72 ~ bnd_c7_2 X69 X70)) |
% 16.24/15.72 bnd_c7_1 X69))) &
% 16.24/15.72 ((((bnd_ndr1_0 &
% 16.24/15.72 (ALL X71.
% 16.24/15.72 bnd_ndr1_1 bnd_a365 -->
% 16.24/15.72 bnd_c4_2 bnd_a365 X71 | bnd_c5_2 bnd_a365 X71)) &
% 16.24/15.72 ~ bnd_c7_1 bnd_a365) &
% 16.24/15.72 bnd_c1_1 bnd_a365 |
% 16.24/15.72 ((bnd_ndr1_0 &
% 16.24/15.72 (ALL X72.
% 16.24/15.72 bnd_ndr1_1 bnd_a366 -->
% 16.24/15.72 (bnd_c1_2 bnd_a366 X72 | bnd_c2_2 bnd_a366 X72) |
% 16.24/15.72 ~ bnd_c4_2 bnd_a366 X72)) &
% 16.24/15.72 (ALL X73.
% 16.24/15.72 bnd_ndr1_1 bnd_a366 -->
% 16.24/15.72 bnd_c7_2 bnd_a366 X73 | bnd_c1_2 bnd_a366 X73)) &
% 16.24/15.72 (ALL X74.
% 16.24/15.72 bnd_ndr1_1 bnd_a366 -->
% 16.24/15.72 bnd_c8_2 bnd_a366 X74 | bnd_c4_2 bnd_a366 X74)) |
% 16.24/15.72 (ALL X75.
% 16.24/15.72 bnd_ndr1_0 -->
% 16.24/15.72 (bnd_c3_1 X75 |
% 16.24/15.72 ((bnd_ndr1_1 X75 & ~ bnd_c8_2 X75 bnd_a367) &
% 16.24/15.72 bnd_c4_2 X75 bnd_a367) &
% 16.24/15.72 bnd_c5_2 X75 bnd_a367) |
% 16.24/15.72 (ALL X76.
% 16.24/15.72 bnd_ndr1_1 X75 -->
% 16.24/15.72 (~ bnd_c1_2 X75 X76 | ~ bnd_c6_2 X75 X76) |
% 16.24/15.72 bnd_c5_2 X75 X76)))) &
% 16.24/15.72 ((~ bnd_c2_0 |
% 16.24/15.72 (ALL X77.
% 16.24/15.72 bnd_ndr1_0 -->
% 16.24/15.72 bnd_c6_1 X77 |
% 16.24/15.72 (bnd_ndr1_1 X77 & ~ bnd_c8_2 X77 bnd_a368) &
% 16.24/15.72 bnd_c4_2 X77 bnd_a368)) |
% 16.24/15.72 (((((bnd_ndr1_0 & bnd_c2_1 bnd_a369) &
% 16.24/15.72 bnd_ndr1_1 bnd_a369) &
% 16.24/15.72 ~ bnd_c4_2 bnd_a369 bnd_a370) &
% 16.24/15.72 ~ bnd_c5_2 bnd_a369 bnd_a370) &
% 16.24/15.72 ~ bnd_c8_2 bnd_a369 bnd_a370) &
% 16.24/15.72 (ALL X78.
% 16.24/15.72 bnd_ndr1_1 bnd_a369 -->
% 16.24/15.72 (bnd_c3_2 bnd_a369 X78 | bnd_c1_2 bnd_a369 X78) |
% 16.24/15.72 bnd_c4_2 bnd_a369 X78))) &
% 16.24/15.72 ((bnd_ndr1_0 & bnd_c3_1 bnd_a371) &
% 16.24/15.72 (ALL X79.
% 16.24/15.72 bnd_ndr1_1 bnd_a371 -->
% 16.24/15.72 (bnd_c4_2 bnd_a371 X79 | ~ bnd_c6_2 bnd_a371 X79) |
% 16.24/15.72 ~ bnd_c5_2 bnd_a371 X79) |
% 16.24/15.72 ~ bnd_c6_0)) &
% 16.24/15.72 ((bnd_c2_0 |
% 16.24/15.72 (ALL X80.
% 16.24/15.72 bnd_ndr1_0 -->
% 16.24/15.72 (~ bnd_c1_1 X80 |
% 16.24/15.72 (ALL X81.
% 16.24/15.72 bnd_ndr1_1 X80 -->
% 16.24/15.72 (bnd_c8_2 X80 X81 | bnd_c3_2 X80 X81) |
% 16.24/15.72 ~ bnd_c1_2 X80 X81)) |
% 16.24/15.72 ((bnd_ndr1_1 X80 & bnd_c4_2 X80 bnd_a372) &
% 16.24/15.72 ~ bnd_c8_2 X80 bnd_a372) &
% 16.24/15.72 ~ bnd_c5_2 X80 bnd_a372)) |
% 16.24/15.72 ((bnd_ndr1_0 & bnd_c8_1 bnd_a373) & bnd_c3_1 bnd_a373) &
% 16.24/15.72 bnd_c5_1 bnd_a373)) &
% 16.24/15.72 (((((((bnd_ndr1_0 &
% 16.24/15.72 (ALL X82.
% 16.24/15.72 bnd_ndr1_1 bnd_a374 -->
% 16.24/15.72 (~ bnd_c5_2 bnd_a374 X82 | bnd_c8_2 bnd_a374 X82) |
% 16.24/15.72 ~ bnd_c1_2 bnd_a374 X82)) &
% 16.24/15.72 (ALL X83.
% 16.24/15.72 bnd_ndr1_1 bnd_a374 -->
% 16.24/15.72 (~ bnd_c5_2 bnd_a374 X83 | bnd_c2_2 bnd_a374 X83) |
% 16.24/15.72 bnd_c4_2 bnd_a374 X83)) &
% 16.24/15.72 bnd_ndr1_1 bnd_a374) &
% 16.24/15.72 ~ bnd_c7_2 bnd_a374 bnd_a375) &
% 16.24/15.72 ~ bnd_c6_2 bnd_a374 bnd_a375) &
% 16.24/15.72 bnd_c5_2 bnd_a374 bnd_a375 |
% 16.24/15.72 ~ bnd_c5_0) |
% 16.24/15.72 ~ bnd_c3_0)) &
% 16.24/15.72 ((~ bnd_c3_0 | ~ bnd_c4_0) |
% 16.24/15.72 (((((bnd_ndr1_0 &
% 16.24/15.72 (ALL X84.
% 16.24/15.72 bnd_ndr1_1 bnd_a376 -->
% 16.24/15.72 (~ bnd_c8_2 bnd_a376 X84 | ~ bnd_c5_2 bnd_a376 X84) |
% 16.24/15.72 bnd_c1_2 bnd_a376 X84)) &
% 16.24/15.72 bnd_ndr1_1 bnd_a376) &
% 16.24/15.72 ~ bnd_c5_2 bnd_a376 bnd_a377) &
% 16.24/15.72 bnd_c3_2 bnd_a376 bnd_a377) &
% 16.24/15.72 ~ bnd_c6_2 bnd_a376 bnd_a377) &
% 16.24/15.72 (ALL X85.
% 16.24/15.72 bnd_ndr1_1 bnd_a376 -->
% 16.24/15.72 (~ bnd_c1_2 bnd_a376 X85 | bnd_c4_2 bnd_a376 X85) |
% 16.24/15.72 bnd_c3_2 bnd_a376 X85))) &
% 16.24/15.72 (((ALL X86.
% 16.24/15.72 bnd_ndr1_0 -->
% 16.24/15.72 (~ bnd_c2_1 X86 |
% 16.24/15.72 ((bnd_ndr1_1 X86 & bnd_c6_2 X86 bnd_a378) &
% 16.24/15.72 ~ bnd_c2_2 X86 bnd_a378) &
% 16.24/15.72 ~ bnd_c5_2 X86 bnd_a378) |
% 16.24/15.72 bnd_c3_1 X86) |
% 16.24/15.72 ((bnd_ndr1_0 &
% 16.24/15.72 (ALL X87.
% 16.24/15.72 bnd_ndr1_1 bnd_a379 -->
% 16.24/15.72 (bnd_c3_2 bnd_a379 X87 | bnd_c5_2 bnd_a379 X87) |
% 16.24/15.72 bnd_c4_2 bnd_a379 X87)) &
% 16.24/15.72 bnd_c3_1 bnd_a379) &
% 16.24/15.72 ~ bnd_c1_1 bnd_a379) |
% 16.24/15.72 bnd_c5_0)) &
% 16.24/15.72 (~ bnd_c6_0 |
% 16.24/15.72 (((((((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a380) &
% 16.24/15.72 bnd_c2_2 bnd_a380 bnd_a381) &
% 16.24/15.72 ~ bnd_c8_2 bnd_a380 bnd_a381) &
% 16.24/15.72 ~ bnd_c1_2 bnd_a380 bnd_a381) &
% 16.24/15.72 bnd_ndr1_1 bnd_a380) &
% 16.24/15.72 ~ bnd_c6_2 bnd_a380 bnd_a382) &
% 16.24/15.72 ~ bnd_c1_2 bnd_a380 bnd_a382) &
% 16.24/15.72 bnd_c3_2 bnd_a380 bnd_a382) &
% 16.24/15.72 bnd_ndr1_1 bnd_a380) &
% 16.24/15.72 bnd_c6_2 bnd_a380 bnd_a383) &
% 16.24/15.72 ~ bnd_c8_2 bnd_a380 bnd_a383) &
% 16.24/15.72 bnd_c1_2 bnd_a380 bnd_a383)) &
% 16.24/15.72 (bnd_c3_0 |
% 16.24/15.72 ((bnd_ndr1_0 & bnd_c6_1 bnd_a384) & ~ bnd_c8_1 bnd_a384) &
% 16.24/15.72 (ALL X88.
% 16.24/15.72 bnd_ndr1_1 bnd_a384 -->
% 16.24/15.72 (~ bnd_c3_2 bnd_a384 X88 | ~ bnd_c2_2 bnd_a384 X88) |
% 16.24/15.72 ~ bnd_c7_2 bnd_a384 X88))) &
% 16.24/15.72 ((~ bnd_c3_0 | bnd_c5_0) |
% 16.24/15.72 (((((bnd_ndr1_0 & bnd_c5_1 bnd_a385) & bnd_c2_1 bnd_a385) &
% 16.24/15.72 bnd_ndr1_1 bnd_a385) &
% 16.24/15.72 ~ bnd_c8_2 bnd_a385 bnd_a386) &
% 16.24/15.72 ~ bnd_c3_2 bnd_a385 bnd_a386) &
% 16.24/15.72 ~ bnd_c6_2 bnd_a385 bnd_a386)) &
% 16.24/15.72 ((bnd_c7_0 | ~ bnd_c5_0) | bnd_c1_0)) &
% 16.24/15.72 ((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a387) &
% 16.24/15.72 bnd_c7_2 bnd_a387 bnd_a388) &
% 16.24/15.72 bnd_c3_2 bnd_a387 bnd_a388) &
% 16.24/15.72 ~ bnd_c8_2 bnd_a387 bnd_a388) &
% 16.24/15.72 bnd_c6_1 bnd_a387) &
% 16.24/15.72 bnd_c1_1 bnd_a387 |
% 16.24/15.72 (ALL X89.
% 16.24/15.72 bnd_ndr1_0 -->
% 16.24/15.72 (((bnd_ndr1_1 X89 & bnd_c2_2 X89 bnd_a389) &
% 16.24/15.72 bnd_c7_2 X89 bnd_a389) &
% 16.24/15.72 ~ bnd_c6_2 X89 bnd_a389 |
% 16.24/15.72 ((bnd_ndr1_1 X89 & ~ bnd_c7_2 X89 bnd_a390) &
% 16.24/15.72 bnd_c3_2 X89 bnd_a390) &
% 16.24/15.72 ~ bnd_c8_2 X89 bnd_a390) |
% 16.24/15.72 ~ bnd_c2_1 X89))) &
% 16.24/15.72 ((bnd_c7_0 | bnd_c3_0) |
% 16.24/15.72 (ALL X90.
% 16.24/15.72 bnd_ndr1_0 -->
% 16.24/15.72 ((ALL X91.
% 16.24/15.72 bnd_ndr1_1 X90 -->
% 16.24/15.72 (bnd_c2_2 X90 X91 | bnd_c4_2 X90 X91) | ~ bnd_c7_2 X90 X91) |
% 16.24/15.72 ~ bnd_c4_1 X90) |
% 16.24/15.72 ~ bnd_c8_1 X90))) &
% 16.24/15.72 (((ALL X92.
% 16.24/15.72 bnd_ndr1_0 -->
% 16.24/15.72 (~ bnd_c5_1 X92 | ~ bnd_c6_1 X92) |
% 16.24/15.72 ((bnd_ndr1_1 X92 & bnd_c7_2 X92 bnd_a391) &
% 16.24/15.72 bnd_c8_2 X92 bnd_a391) &
% 16.24/15.72 ~ bnd_c4_2 X92 bnd_a391) |
% 16.24/15.72 bnd_c1_0) |
% 16.24/15.72 (ALL X93.
% 16.24/15.72 bnd_ndr1_0 -->
% 16.24/15.72 ((ALL X94.
% 16.24/15.72 bnd_ndr1_1 X93 --> ~ bnd_c4_2 X93 X94 | bnd_c8_2 X93 X94) |
% 16.24/15.72 ~ bnd_c3_1 X93) |
% 16.24/15.72 (bnd_ndr1_1 X93 & bnd_c2_2 X93 bnd_a392) &
% 16.24/15.72 ~ bnd_c4_2 X93 bnd_a392))) &
% 16.24/15.72 (((ALL X95.
% 16.24/15.72 bnd_ndr1_0 -->
% 16.24/15.72 (bnd_c2_1 X95 |
% 16.24/15.72 (ALL X96.
% 16.24/15.72 bnd_ndr1_1 X95 -->
% 16.24/15.72 (~ bnd_c4_2 X95 X96 | ~ bnd_c5_2 X95 X96) |
% 16.24/15.72 ~ bnd_c7_2 X95 X96)) |
% 16.24/15.72 ~ bnd_c1_1 X95) |
% 16.24/15.72 bnd_c6_0) |
% 16.24/15.72 ((((bnd_ndr1_0 &
% 16.24/15.72 (ALL X97.
% 16.24/15.72 bnd_ndr1_1 bnd_a393 -->
% 16.24/15.72 (~ bnd_c8_2 bnd_a393 X97 | ~ bnd_c3_2 bnd_a393 X97) |
% 16.24/15.72 bnd_c6_2 bnd_a393 X97)) &
% 16.24/15.72 bnd_ndr1_1 bnd_a393) &
% 16.24/15.72 bnd_c1_2 bnd_a393 bnd_a394) &
% 16.24/15.72 ~ bnd_c4_2 bnd_a393 bnd_a394) &
% 16.24/15.72 ~ bnd_c8_2 bnd_a393 bnd_a394)) &
% 16.24/15.72 ((bnd_c3_0 | bnd_c2_0) | bnd_c6_0)) &
% 16.24/15.72 ((ALL X98.
% 16.24/15.72 bnd_ndr1_0 -->
% 16.24/15.72 ((ALL X99. bnd_ndr1_1 X98 --> bnd_c4_2 X98 X99 | ~ bnd_c7_2 X98 X99) |
% 16.24/15.72 (ALL X100.
% 16.24/15.72 bnd_ndr1_1 X98 --> bnd_c3_2 X98 X100 | ~ bnd_c7_2 X98 X100)) |
% 16.24/15.72 (ALL X101.
% 16.24/15.72 bnd_ndr1_1 X98 -->
% 16.24/15.72 (bnd_c3_2 X98 X101 | ~ bnd_c5_2 X98 X101) | bnd_c8_2 X98 X101)) |
% 16.24/15.72 bnd_c5_0)) &
% 16.24/15.72 (((((((bnd_ndr1_0 &
% 16.24/15.72 (ALL X102.
% 16.24/15.72 bnd_ndr1_1 bnd_a395 -->
% 16.24/15.72 (~ bnd_c7_2 bnd_a395 X102 | bnd_c4_2 bnd_a395 X102) |
% 16.24/15.72 ~ bnd_c2_2 bnd_a395 X102)) &
% 16.24/15.72 bnd_ndr1_1 bnd_a395) &
% 16.24/15.72 ~ bnd_c3_2 bnd_a395 bnd_a396) &
% 16.24/15.72 ~ bnd_c2_2 bnd_a395 bnd_a396) &
% 16.24/15.72 bnd_c4_2 bnd_a395 bnd_a396) &
% 16.24/15.72 ~ bnd_c3_1 bnd_a395 |
% 16.24/15.72 bnd_c8_0) |
% 16.24/15.72 ~ bnd_c7_0)) &
% 16.24/15.72 (bnd_c8_0 | ~ bnd_c1_0)) &
% 16.24/15.72 ((((((((((bnd_ndr1_0 &
% 16.24/15.72 bnd_ndr1_1 bnd_a397) &
% 16.24/15.72 bnd_c5_2 bnd_a397 bnd_a398) &
% 16.24/15.72 ~ bnd_c8_2 bnd_a397 bnd_a398) &
% 16.24/15.72 ~ bnd_c7_2 bnd_a397 bnd_a398) &
% 16.24/15.72 bnd_ndr1_1 bnd_a397) &
% 16.24/15.72 ~ bnd_c7_2 bnd_a397 bnd_a399) &
% 16.24/15.72 bnd_c2_2 bnd_a397 bnd_a399) &
% 16.24/15.72 bnd_c1_2 bnd_a397 bnd_a399) &
% 16.24/15.72 ~ bnd_c3_1 bnd_a397 |
% 16.24/15.72 ((bnd_ndr1_0 & bnd_c7_1 bnd_a400) &
% 16.24/15.72 (ALL X103.
% 16.24/15.72 bnd_ndr1_1 bnd_a400 -->
% 16.24/15.72 bnd_c5_2 bnd_a400 X103 | ~ bnd_c1_2 bnd_a400 X103)) &
% 16.24/15.72 bnd_c5_1 bnd_a400) |
% 16.24/15.72 bnd_c5_0)) &
% 16.24/15.72 ((~ bnd_c3_0 | ~ bnd_c7_0) |
% 16.24/15.72 (ALL X104.
% 16.24/15.72 bnd_ndr1_0 -->
% 16.24/15.72 (((bnd_ndr1_1 X104 & ~ bnd_c2_2 X104 bnd_a401) &
% 16.24/15.72 ~ bnd_c7_2 X104 bnd_a401) &
% 16.24/15.72 ~ bnd_c6_2 X104 bnd_a401 |
% 16.24/15.72 ~ bnd_c1_1 X104) |
% 16.24/15.72 (ALL X105.
% 16.24/15.72 bnd_ndr1_1 X104 --> ~ bnd_c2_2 X104 X105 | ~ bnd_c6_2 X104 X105)))) &
% 16.24/15.72 ((bnd_c4_0 |
% 16.24/15.72 (ALL X106.
% 16.24/15.72 bnd_ndr1_0 -->
% 16.24/15.72 ((ALL X107.
% 16.24/15.72 bnd_ndr1_1 X106 -->
% 16.24/15.72 (~ bnd_c2_2 X106 X107 | ~ bnd_c6_2 X106 X107) | bnd_c7_2 X106 X107) |
% 16.24/15.72 bnd_c6_1 X106) |
% 16.24/15.72 bnd_c8_1 X106)) |
% 16.24/15.72 bnd_c3_0)) &
% 16.24/15.72 (bnd_c7_0 |
% 16.24/15.72 (((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a402) &
% 16.24/15.72 ~ bnd_c4_2 bnd_a402 bnd_a403) &
% 16.24/15.72 bnd_c6_2 bnd_a402 bnd_a403) &
% 16.24/15.72 bnd_c3_2 bnd_a402 bnd_a403) &
% 16.24/15.72 (ALL X108.
% 16.24/15.72 bnd_ndr1_1 bnd_a402 -->
% 16.24/15.72 (bnd_c8_2 bnd_a402 X108 | ~ bnd_c6_2 bnd_a402 X108) |
% 16.24/15.72 bnd_c2_2 bnd_a402 X108)) &
% 16.24/15.72 ~ bnd_c7_1 bnd_a402)) &
% 16.24/15.72 ((ALL X109.
% 16.24/15.72 bnd_ndr1_0 -->
% 16.24/15.72 (bnd_c2_1 X109 | bnd_c8_1 X109) |
% 16.24/15.72 ((bnd_ndr1_1 X109 &
% 16.24/15.72 bnd_c1_2 X109 bnd_a404) &
% 16.24/15.72 ~ bnd_c3_2 X109 bnd_a404) &
% 16.24/15.72 ~ bnd_c6_2 X109 bnd_a404) |
% 16.24/15.72 ~ bnd_c8_0)) &
% 16.24/15.72 ((~ bnd_c2_0 |
% 16.24/15.72 (ALL X110.
% 16.24/15.72 bnd_ndr1_0 -->
% 16.24/15.72 (bnd_c8_1 X110 |
% 16.24/15.72 (ALL X111.
% 16.24/15.72 bnd_ndr1_1 X110 -->
% 16.24/15.72 (bnd_c6_2 X110 X111 | bnd_c2_2 X110 X111) | bnd_c3_2 X110 X111)) |
% 16.24/15.72 bnd_c4_1 X110)) |
% 16.24/15.72 (((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a405) &
% 16.24/15.72 ~ bnd_c8_2 bnd_a405 bnd_a406) &
% 16.24/15.72 bnd_c7_2 bnd_a405 bnd_a406) &
% 16.24/15.72 bnd_c2_2 bnd_a405 bnd_a406) &
% 16.24/15.72 bnd_c6_1 bnd_a405) &
% 16.24/15.72 bnd_ndr1_1 bnd_a405) &
% 16.24/15.72 ~ bnd_c5_2 bnd_a405 bnd_a407) &
% 16.24/15.72 ~ bnd_c6_2 bnd_a405 bnd_a407)) &
% 16.24/15.72 ((bnd_c2_0 |
% 16.24/15.72 (((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a408) &
% 16.24/15.72 ~ bnd_c7_2 bnd_a408 bnd_a409) &
% 16.24/15.72 bnd_c4_2 bnd_a408 bnd_a409) &
% 16.24/15.72 bnd_c1_2 bnd_a408 bnd_a409) &
% 16.24/15.72 (ALL X112.
% 16.24/15.72 bnd_ndr1_1 bnd_a408 -->
% 16.24/15.72 bnd_c7_2 bnd_a408 X112 |
% 16.24/15.72 ~ bnd_c3_2 bnd_a408 X112)) &
% 16.24/15.72 bnd_c8_1 bnd_a408) |
% 16.24/15.72 ~ bnd_c5_0)) &
% 16.24/15.72 ((bnd_c4_0 |
% 16.24/15.72 ((bnd_ndr1_0 & bnd_c1_1 bnd_a410) &
% 16.24/15.72 ~ bnd_c6_1 bnd_a410) &
% 16.24/15.72 (ALL X113.
% 16.24/15.72 bnd_ndr1_1 bnd_a410 -->
% 16.24/15.72 ~ bnd_c1_2 bnd_a410 X113 |
% 16.24/15.72 ~ bnd_c2_2 bnd_a410 X113)) |
% 16.24/15.72 (ALL X114.
% 16.24/15.72 bnd_ndr1_0 -->
% 16.24/15.72 (~ bnd_c6_1 X114 | bnd_c8_1 X114) |
% 16.24/15.72 bnd_c5_1 X114))) &
% 16.24/15.72 (((ALL X115.
% 16.24/15.72 bnd_ndr1_0 -->
% 16.24/15.72 ((ALL X116.
% 16.24/15.72 bnd_ndr1_1 X115 -->
% 16.24/15.72 (bnd_c7_2 X115 X116 | bnd_c3_2 X115 X116) | bnd_c6_2 X115 X116) |
% 16.24/15.72 ((bnd_ndr1_1 X115 &
% 16.24/15.72 ~ bnd_c8_2 X115 bnd_a411) &
% 16.24/15.72 ~ bnd_c2_2 X115 bnd_a411) &
% 16.24/15.72 bnd_c3_2 X115 bnd_a411) |
% 16.24/15.72 ((bnd_ndr1_1 X115 &
% 16.24/15.72 bnd_c2_2 X115 bnd_a412) &
% 16.24/15.72 bnd_c6_2 X115 bnd_a412) &
% 16.24/15.72 bnd_c8_2 X115 bnd_a412) |
% 16.24/15.72 ((bnd_ndr1_0 & ~ bnd_c8_1 bnd_a413) &
% 16.24/15.72 ~ bnd_c3_1 bnd_a413) &
% 16.24/15.72 bnd_c4_1 bnd_a413) |
% 16.24/15.72 ~ bnd_c3_0)) &
% 16.24/15.72 ((bnd_c8_0 | ~ bnd_c7_0) | ~ bnd_c3_0)) &
% 16.24/15.72 ((~ bnd_c3_0 | ~ bnd_c5_0) |
% 16.24/15.72 (((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a414) &
% 16.24/15.72 ~ bnd_c7_2 bnd_a414 bnd_a415) &
% 16.24/15.72 ~ bnd_c1_2 bnd_a414 bnd_a415) &
% 16.24/15.72 bnd_c2_2 bnd_a414 bnd_a415) &
% 16.24/15.72 bnd_c5_1 bnd_a414) &
% 16.24/15.72 ~ bnd_c6_1 bnd_a414)) &
% 16.24/15.72 ((bnd_c4_0 | bnd_c5_0) |
% 16.24/15.72 (ALL X117.
% 16.24/15.72 bnd_ndr1_0 -->
% 16.24/15.72 ((bnd_ndr1_1 X117 &
% 16.24/15.72 ~ bnd_c8_2 X117 bnd_a416) &
% 16.24/15.72 ~ bnd_c7_2 X117 bnd_a416) &
% 16.24/15.72 ~ bnd_c4_2 X117 bnd_a416 |
% 16.24/15.72 ~ bnd_c6_1 X117))) &
% 16.24/15.72 ((~ bnd_c7_0 | ~ bnd_c8_0) |
% 16.24/15.72 ((((bnd_ndr1_0 & bnd_c4_1 bnd_a417) &
% 16.24/15.72 bnd_ndr1_1 bnd_a417) &
% 16.24/15.72 ~ bnd_c3_2 bnd_a417 bnd_a418) &
% 16.24/15.72 ~ bnd_c6_2 bnd_a417 bnd_a418) &
% 16.24/15.72 bnd_c5_1 bnd_a417)) &
% 16.24/15.72 ((ALL X118.
% 16.24/15.72 bnd_ndr1_0 -->
% 16.24/15.72 (~ bnd_c7_1 X118 |
% 16.24/15.72 (ALL X119.
% 16.24/15.72 bnd_ndr1_1 X118 -->
% 16.24/15.72 (bnd_c4_2 X118 X119 | bnd_c5_2 X118 X119) |
% 16.24/15.72 ~ bnd_c8_2 X118 X119)) |
% 16.24/15.72 (ALL X120.
% 16.24/15.72 bnd_ndr1_1 X118 -->
% 16.24/15.72 (~ bnd_c6_2 X118 X120 |
% 16.24/15.72 ~ bnd_c5_2 X118 X120) |
% 16.24/15.72 ~ bnd_c7_2 X118 X120)) |
% 16.24/15.72 ((((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a419) &
% 16.24/15.72 bnd_c1_2 bnd_a419 bnd_a420) &
% 16.24/15.72 bnd_c7_2 bnd_a419 bnd_a420) &
% 16.24/15.72 ~ bnd_c2_2 bnd_a419 bnd_a420) &
% 16.24/15.72 ~ bnd_c1_1 bnd_a419) &
% 16.24/15.72 bnd_ndr1_1 bnd_a419) &
% 16.24/15.72 ~ bnd_c3_2 bnd_a419 bnd_a421) &
% 16.24/15.72 bnd_c2_2 bnd_a419 bnd_a421) &
% 16.24/15.72 ~ bnd_c4_2 bnd_a419 bnd_a421)) &
% 16.24/15.72 (((bnd_ndr1_0 & bnd_c6_1 bnd_a422) &
% 16.24/15.72 ~ bnd_c1_1 bnd_a422) &
% 16.24/15.72 bnd_c4_1 bnd_a422 |
% 16.24/15.72 ~ bnd_c1_0)) &
% 16.24/15.72 ((bnd_c6_0 | ~ bnd_c4_0) | bnd_c1_0)) &
% 16.24/15.72 (((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a423) &
% 16.24/15.72 bnd_c8_2 bnd_a423 bnd_a424) &
% 16.24/15.72 bnd_c1_2 bnd_a423 bnd_a424) &
% 16.24/15.72 bnd_c5_2 bnd_a423 bnd_a424) &
% 16.24/15.72 bnd_c4_1 bnd_a423) &
% 16.24/15.72 ~ bnd_c8_1 bnd_a423 |
% 16.24/15.72 ~ bnd_c7_0) |
% 16.24/15.72 (((((bnd_ndr1_0 & ~ bnd_c4_1 bnd_a425) &
% 16.24/15.72 bnd_ndr1_1 bnd_a425) &
% 16.24/15.72 ~ bnd_c1_2 bnd_a425 bnd_a426) &
% 16.24/15.72 bnd_c3_2 bnd_a425 bnd_a426) &
% 16.24/15.72 bnd_c4_2 bnd_a425 bnd_a426) &
% 16.24/15.72 bnd_c3_1 bnd_a425)) &
% 16.24/15.72 ((~ bnd_c2_0 |
% 16.24/15.72 (ALL X121.
% 16.24/15.72 bnd_ndr1_0 -->
% 16.24/15.72 ((bnd_ndr1_1 X121 & bnd_c8_2 X121 bnd_a427) &
% 16.24/15.72 ~ bnd_c1_2 X121 bnd_a427 |
% 16.24/15.72 (ALL X122.
% 16.24/15.72 bnd_ndr1_1 X121 -->
% 16.24/15.72 (~ bnd_c1_2 X121 X122 | bnd_c4_2 X121 X122) |
% 16.24/15.72 bnd_c5_2 X121 X122)) |
% 16.24/15.72 (ALL X123.
% 16.24/15.72 bnd_ndr1_1 X121 -->
% 16.24/15.72 (bnd_c1_2 X121 X123 | bnd_c3_2 X121 X123) |
% 16.24/15.72 bnd_c5_2 X121 X123))) |
% 16.24/15.72 bnd_c6_0)) &
% 16.24/15.72 (((bnd_ndr1_0 &
% 16.24/15.72 (ALL X124.
% 16.24/15.72 bnd_ndr1_1 bnd_a428 -->
% 16.24/15.72 (bnd_c7_2 bnd_a428 X124 |
% 16.24/15.72 ~ bnd_c8_2 bnd_a428 X124) |
% 16.24/15.72 ~ bnd_c5_2 bnd_a428 X124)) &
% 16.24/15.72 bnd_c3_1 bnd_a428 |
% 16.24/15.72 ~ bnd_c8_0) |
% 16.24/15.72 bnd_c2_0)) &
% 16.24/15.72 ((bnd_c2_0 | ~ bnd_c1_0) |
% 16.24/15.72 (ALL X125.
% 16.24/15.72 bnd_ndr1_0 -->
% 16.24/15.72 ((ALL X126.
% 16.24/15.72 bnd_ndr1_1 X125 -->
% 16.24/15.72 bnd_c7_2 X125 X126 | bnd_c5_2 X125 X126) |
% 16.24/15.72 ((bnd_ndr1_1 X125 & bnd_c5_2 X125 bnd_a429) &
% 16.24/15.72 ~ bnd_c6_2 X125 bnd_a429) &
% 16.24/15.72 bnd_c8_2 X125 bnd_a429) |
% 16.24/15.72 ~ bnd_c2_1 X125))) &
% 16.24/15.72 ((~ bnd_c1_0 | bnd_c5_0) | ~ bnd_c3_0)) &
% 16.24/15.72 (((ALL X127.
% 16.24/15.72 bnd_ndr1_0 -->
% 16.24/15.72 (((bnd_ndr1_1 X127 & ~ bnd_c3_2 X127 bnd_a430) &
% 16.24/15.72 bnd_c6_2 X127 bnd_a430) &
% 16.24/15.72 bnd_c2_2 X127 bnd_a430 |
% 16.24/15.72 ~ bnd_c5_1 X127) |
% 16.24/15.72 bnd_c3_1 X127) |
% 16.24/15.72 (ALL X128. bnd_ndr1_0 --> bnd_c5_1 X128 | bnd_c7_1 X128)) |
% 16.24/15.72 ~ bnd_c6_0)) &
% 16.24/15.72 (((ALL X129.
% 16.24/15.72 bnd_ndr1_0 -->
% 16.24/15.72 (bnd_c4_1 X129 | bnd_c7_1 X129) |
% 16.24/15.72 (ALL X130.
% 16.24/15.72 bnd_ndr1_1 X129 -->
% 16.24/15.72 (~ bnd_c5_2 X129 X130 | bnd_c3_2 X129 X130) |
% 16.24/15.72 bnd_c4_2 X129 X130)) |
% 16.24/15.72 bnd_c6_0) |
% 16.24/15.72 ((bnd_ndr1_0 & ~ bnd_c1_1 bnd_a431) &
% 16.24/15.72 (ALL X131.
% 16.24/15.72 bnd_ndr1_1 bnd_a431 -->
% 16.24/15.72 bnd_c1_2 bnd_a431 X131 | bnd_c3_2 bnd_a431 X131)) &
% 16.24/15.72 ~ bnd_c2_1 bnd_a431)) &
% 16.24/15.72 (((ALL X132.
% 16.24/15.72 bnd_ndr1_0 -->
% 16.24/15.72 ((ALL X133.
% 16.24/15.72 bnd_ndr1_1 X132 -->
% 16.24/15.72 (bnd_c4_2 X132 X133 | ~ bnd_c1_2 X132 X133) |
% 16.24/15.72 ~ bnd_c7_2 X132 X133) |
% 16.24/15.72 ((bnd_ndr1_1 X132 & bnd_c6_2 X132 bnd_a432) &
% 16.24/15.72 bnd_c1_2 X132 bnd_a432) &
% 16.24/15.72 ~ bnd_c7_2 X132 bnd_a432) |
% 16.24/15.72 ((bnd_ndr1_1 X132 & bnd_c5_2 X132 bnd_a433) &
% 16.24/15.72 bnd_c2_2 X132 bnd_a433) &
% 16.24/15.72 bnd_c1_2 X132 bnd_a433) |
% 16.24/15.72 (ALL X134.
% 16.24/15.72 bnd_ndr1_0 -->
% 16.24/15.72 (~ bnd_c3_1 X134 | ~ bnd_c5_1 X134) | bnd_c2_1 X134)) |
% 16.24/15.72 bnd_c6_0)) &
% 16.24/15.72 (((ALL X135.
% 16.24/15.72 bnd_ndr1_0 -->
% 16.24/15.72 (bnd_c7_1 X135 | ~ bnd_c5_1 X135) |
% 16.24/15.72 ((bnd_ndr1_1 X135 & ~ bnd_c3_2 X135 bnd_a434) &
% 16.24/15.72 ~ bnd_c6_2 X135 bnd_a434) &
% 16.24/15.72 ~ bnd_c1_2 X135 bnd_a434) |
% 16.24/15.72 (ALL X136.
% 16.24/15.72 bnd_ndr1_0 -->
% 16.24/15.72 bnd_c4_1 X136 |
% 16.24/15.72 (bnd_ndr1_1 X136 & ~ bnd_c5_2 X136 bnd_a435) &
% 16.24/15.72 ~ bnd_c3_2 X136 bnd_a435)) |
% 16.24/15.72 ~ bnd_c7_0)) &
% 16.24/15.72 ((bnd_c6_0 |
% 16.24/15.72 ((bnd_ndr1_0 &
% 16.24/15.72 (ALL X137.
% 16.24/15.72 bnd_ndr1_1 bnd_a436 -->
% 16.24/15.72 (~ bnd_c4_2 bnd_a436 X137 | ~ bnd_c3_2 bnd_a436 X137) |
% 16.24/15.72 ~ bnd_c5_2 bnd_a436 X137)) &
% 16.24/15.72 bnd_c7_1 bnd_a436) &
% 16.24/15.72 (ALL X138.
% 16.24/15.72 bnd_ndr1_1 bnd_a436 -->
% 16.24/15.72 ~ bnd_c5_2 bnd_a436 X138 | bnd_c2_2 bnd_a436 X138)) |
% 16.24/15.72 ~ bnd_c1_0)) &
% 16.24/15.72 ((bnd_c6_0 |
% 16.24/15.72 (ALL X139.
% 16.24/15.72 bnd_ndr1_0 -->
% 16.24/15.72 ((bnd_ndr1_1 X139 & ~ bnd_c7_2 X139 bnd_a437) &
% 16.24/15.72 ~ bnd_c1_2 X139 bnd_a437 |
% 16.24/15.72 (ALL X140.
% 16.24/15.72 bnd_ndr1_1 X139 -->
% 16.24/15.72 (bnd_c1_2 X139 X140 | ~ bnd_c8_2 X139 X140) |
% 16.24/15.72 ~ bnd_c5_2 X139 X140)) |
% 16.24/15.72 bnd_c6_1 X139)) |
% 16.24/15.72 bnd_c4_0)) &
% 16.24/15.72 ((((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a438) &
% 16.24/15.72 ~ bnd_c6_2 bnd_a438 bnd_a439) &
% 16.24/15.72 bnd_c1_2 bnd_a438 bnd_a439) &
% 16.24/15.72 bnd_ndr1_1 bnd_a438) &
% 16.24/15.72 bnd_c4_2 bnd_a438 bnd_a440) &
% 16.24/15.72 ~ bnd_c5_2 bnd_a438 bnd_a440) &
% 16.24/15.72 ~ bnd_c6_2 bnd_a438 bnd_a440 |
% 16.24/15.72 ((bnd_ndr1_0 &
% 16.24/15.72 (ALL X141.
% 16.24/15.72 bnd_ndr1_1 bnd_a441 -->
% 16.24/15.72 bnd_c4_2 bnd_a441 X141 | bnd_c1_2 bnd_a441 X141)) &
% 16.24/15.72 bnd_c5_1 bnd_a441) &
% 16.24/15.72 ~ bnd_c8_1 bnd_a441) |
% 16.24/15.72 ((bnd_ndr1_0 &
% 16.24/15.72 (ALL X142.
% 16.24/15.72 bnd_ndr1_1 bnd_a442 -->
% 16.24/15.72 (bnd_c8_2 bnd_a442 X142 | ~ bnd_c7_2 bnd_a442 X142) |
% 16.24/15.72 bnd_c6_2 bnd_a442 X142)) &
% 16.24/15.72 ~ bnd_c8_1 bnd_a442) &
% 16.24/15.72 ~ bnd_c2_1 bnd_a442)) &
% 16.24/15.72 (((ALL X143.
% 16.24/15.72 bnd_ndr1_0 -->
% 16.24/15.72 ((ALL X144.
% 16.24/15.72 bnd_ndr1_1 X143 -->
% 16.24/15.72 (~ bnd_c7_2 X143 X144 | ~ bnd_c3_2 X143 X144) |
% 16.24/15.72 ~ bnd_c2_2 X143 X144) |
% 16.24/15.72 (ALL X145.
% 16.24/15.72 bnd_ndr1_1 X143 -->
% 16.24/15.72 (bnd_c1_2 X143 X145 | bnd_c8_2 X143 X145) |
% 16.24/15.72 ~ bnd_c2_2 X143 X145)) |
% 16.24/15.72 bnd_c8_1 X143) |
% 16.24/15.72 ~ bnd_c5_0) |
% 16.24/15.72 (ALL X146.
% 16.24/15.72 bnd_ndr1_0 -->
% 16.24/15.72 (~ bnd_c4_1 X146 |
% 16.24/15.72 ((bnd_ndr1_1 X146 & ~ bnd_c5_2 X146 bnd_a443) &
% 16.24/15.72 ~ bnd_c2_2 X146 bnd_a443) &
% 16.24/15.72 ~ bnd_c7_2 X146 bnd_a443) |
% 16.24/15.72 (ALL X147.
% 16.24/15.72 bnd_ndr1_1 X146 -->
% 16.24/15.72 (~ bnd_c7_2 X146 X147 | ~ bnd_c2_2 X146 X147) |
% 16.24/15.72 ~ bnd_c3_2 X146 X147)))) &
% 16.24/15.72 ((~ bnd_c6_0 |
% 16.24/15.72 (ALL X148.
% 16.24/15.72 bnd_ndr1_0 -->
% 16.24/15.72 (~ bnd_c8_1 X148 | ~ bnd_c4_1 X148) |
% 16.24/15.72 ((bnd_ndr1_1 X148 & bnd_c7_2 X148 bnd_a444) &
% 16.24/15.72 bnd_c2_2 X148 bnd_a444) &
% 16.24/15.72 bnd_c4_2 X148 bnd_a444)) |
% 16.24/15.72 ((((((((bnd_ndr1_0 & ~ bnd_c2_1 bnd_a445) & bnd_ndr1_1 bnd_a445) &
% 16.24/15.72 ~ bnd_c5_2 bnd_a445 bnd_a446) &
% 16.24/15.72 bnd_c3_2 bnd_a445 bnd_a446) &
% 16.24/15.72 ~ bnd_c8_2 bnd_a445 bnd_a446) &
% 16.24/15.72 bnd_ndr1_1 bnd_a445) &
% 16.24/15.72 ~ bnd_c5_2 bnd_a445 bnd_a447) &
% 16.24/15.72 ~ bnd_c2_2 bnd_a445 bnd_a447) &
% 16.24/15.72 bnd_c4_2 bnd_a445 bnd_a447)) &
% 16.24/15.72 ((((bnd_ndr1_0 & ~ bnd_c8_1 bnd_a448) &
% 16.24/15.72 (ALL X149.
% 16.24/15.72 bnd_ndr1_1 bnd_a448 -->
% 16.24/15.72 bnd_c3_2 bnd_a448 X149 | ~ bnd_c1_2 bnd_a448 X149)) &
% 16.24/15.72 (ALL X150.
% 16.24/15.72 bnd_ndr1_1 bnd_a448 -->
% 16.24/15.72 (~ bnd_c7_2 bnd_a448 X150 | ~ bnd_c3_2 bnd_a448 X150) |
% 16.24/15.72 ~ bnd_c4_2 bnd_a448 X150) |
% 16.24/15.72 (ALL X151.
% 16.24/15.72 bnd_ndr1_0 -->
% 16.24/15.72 ((ALL X152.
% 16.24/15.72 bnd_ndr1_1 X151 -->
% 16.24/15.72 ~ bnd_c5_2 X151 X152 | bnd_c1_2 X151 X152) |
% 16.24/15.72 (ALL X153.
% 16.24/15.72 bnd_ndr1_1 X151 -->
% 16.24/15.72 (bnd_c5_2 X151 X153 | bnd_c7_2 X151 X153) |
% 16.24/15.72 ~ bnd_c2_2 X151 X153)) |
% 16.24/15.72 (ALL X154.
% 16.24/15.72 bnd_ndr1_1 X151 -->
% 16.24/15.72 (bnd_c3_2 X151 X154 | ~ bnd_c5_2 X151 X154) |
% 16.24/15.72 bnd_c8_2 X151 X154))) |
% 16.24/15.72 bnd_c3_0)) &
% 16.24/15.72 ((((((((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a449) &
% 16.24/15.72 ~ bnd_c7_2 bnd_a449 bnd_a450) &
% 16.24/15.72 bnd_c6_2 bnd_a449 bnd_a450) &
% 16.24/15.72 ~ bnd_c8_2 bnd_a449 bnd_a450) &
% 16.24/15.72 bnd_ndr1_1 bnd_a449) &
% 16.24/15.72 bnd_c8_2 bnd_a449 bnd_a451) &
% 16.24/15.72 ~ bnd_c2_2 bnd_a449 bnd_a451) &
% 16.24/15.72 ~ bnd_c4_2 bnd_a449 bnd_a451) &
% 16.24/15.72 bnd_ndr1_1 bnd_a449) &
% 16.24/15.72 bnd_c7_2 bnd_a449 bnd_a452) &
% 16.24/15.72 ~ bnd_c4_2 bnd_a449 bnd_a452 |
% 16.24/15.72 bnd_c2_0) |
% 16.24/15.72 ~ bnd_c1_0)) &
% 16.24/15.72 ((bnd_c1_0 | bnd_c4_0) |
% 16.24/15.72 ((bnd_ndr1_0 &
% 16.24/15.72 (ALL X155.
% 16.24/15.72 bnd_ndr1_1 bnd_a453 -->
% 16.24/15.72 (~ bnd_c3_2 bnd_a453 X155 | ~ bnd_c2_2 bnd_a453 X155) |
% 16.24/15.72 bnd_c7_2 bnd_a453 X155)) &
% 16.24/15.72 (ALL X156.
% 16.24/15.72 bnd_ndr1_1 bnd_a453 -->
% 16.24/15.72 (bnd_c3_2 bnd_a453 X156 | ~ bnd_c8_2 bnd_a453 X156) |
% 16.24/15.72 ~ bnd_c4_2 bnd_a453 X156)) &
% 16.24/15.72 bnd_c3_1 bnd_a453)) &
% 16.24/15.72 ((~ bnd_c4_0 |
% 16.24/15.72 (((((bnd_ndr1_0 & ~ bnd_c2_1 bnd_a454) & bnd_ndr1_1 bnd_a454) &
% 16.24/15.72 ~ bnd_c2_2 bnd_a454 bnd_a455) &
% 16.24/15.72 bnd_c8_2 bnd_a454 bnd_a455) &
% 16.24/15.72 bnd_c4_2 bnd_a454 bnd_a455) &
% 16.24/15.72 ~ bnd_c1_1 bnd_a454) |
% 16.24/15.72 bnd_c7_0))
% 16.24/15.72 Adding axioms...
% 16.24/15.74 Typedef.type_definition_def
% 44.68/44.11 ...done.
% 44.68/44.14 Ground types: ?'b, TPTP_Interpret.ind
% 44.68/44.14 Translating term (sizes: 1, 1) ...
% 67.83/67.27 Invoking SAT solver...
% 67.83/67.27 No model exists.
% 67.83/67.27 Translating term (sizes: 2, 1) ...
% 91.69/91.01 Invoking SAT solver...
% 91.69/91.01 No model exists.
% 91.69/91.01 Translating term (sizes: 1, 2) ...
% 133.74/132.98 Invoking SAT solver...
% 135.34/134.52 Model found:
% 135.34/134.52 Size of types: ?'b: 1, TPTP_Interpret.ind: 2
% 135.34/134.52 bnd_a455: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a454: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a453: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a452: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a451: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a450: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a449: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a448: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a447: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a446: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a445: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a444: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a443: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a442: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a441: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a440: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a439: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a438: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a437: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a436: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a435: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a434: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a433: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a432: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a431: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a430: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a429: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a428: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a427: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a426: ??.TPTP_Interpret.ind1
% 135.34/134.52 bnd_a425: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a424: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a423: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a422: ??.TPTP_Interpret.ind1
% 135.34/134.52 bnd_a421: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a420: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a419: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a418: ??.TPTP_Interpret.ind1
% 135.34/134.52 bnd_a417: ??.TPTP_Interpret.ind1
% 135.34/134.52 bnd_a416: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a415: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a414: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a413: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a412: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a411: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a410: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a409: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a408: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a407: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a406: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a405: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a404: ??.TPTP_Interpret.ind1
% 135.34/134.52 bnd_a403: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a402: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a401: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a400: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a399: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a398: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a397: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a396: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a395: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a394: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a393: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a392: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a391: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a390: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a389: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a388: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a387: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a386: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a385: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a384: ??.TPTP_Interpret.ind1
% 135.34/134.52 bnd_a383: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a382: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a381: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a380: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a379: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a378: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a377: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a376: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a375: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a374: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a373: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a372: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a371: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a370: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a369: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a368: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a367: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a366: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a365: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a364: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a363: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a362: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a361: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a360: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a359: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a358: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a357: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a356: ??.TPTP_Interpret.ind1
% 135.34/134.52 bnd_a355: ??.TPTP_Interpret.ind1
% 135.34/134.52 bnd_a354: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a353: ??.TPTP_Interpret.ind1
% 135.34/134.52 bnd_a352: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a351: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a350: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a349: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a348: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a347: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a346: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a345: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a344: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a343: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a342: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a341: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a340: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a339: ??.TPTP_Interpret.ind1
% 135.34/134.52 bnd_a338: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a337: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a336: ??.TPTP_Interpret.ind1
% 135.34/134.52 bnd_a335: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a334: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a333: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a332: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a331: ??.TPTP_Interpret.ind1
% 135.34/134.52 bnd_a330: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a329: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a328: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a327: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a326: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a325: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a324: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a323: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a322: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a321: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a320: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a319: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a318: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a317: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a316: ??.TPTP_Interpret.ind1
% 135.34/134.52 bnd_a315: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a314: ??.TPTP_Interpret.ind1
% 135.34/134.52 bnd_c6_1: {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, True)}
% 135.34/134.52 bnd_a313: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a312: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a311: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a310: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_c4_1: {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, True)}
% 135.34/134.52 bnd_a309: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_c7_2: {(??.TPTP_Interpret.ind0,
% 135.34/134.52 {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, False)}),
% 135.34/134.52 (??.TPTP_Interpret.ind1,
% 135.34/134.52 {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, False)})}
% 135.34/134.52 bnd_a308: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a307: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_c4_0: True
% 135.34/134.52 bnd_a306: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_a305: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_c1_0: True
% 135.34/134.52 bnd_c5_0: True
% 135.34/134.52 bnd_a304: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_c6_0: False
% 135.34/134.52 bnd_c5_1: {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, True)}
% 135.34/134.52 bnd_c8_2: {(??.TPTP_Interpret.ind0,
% 135.34/134.52 {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, False)}),
% 135.34/134.52 (??.TPTP_Interpret.ind1,
% 135.34/134.52 {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, True)})}
% 135.34/134.52 bnd_a303: ??.TPTP_Interpret.ind1
% 135.34/134.52 bnd_a302: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_c2_1: {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, False)}
% 135.34/134.52 bnd_a301: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_c5_2: {(??.TPTP_Interpret.ind0,
% 135.34/134.52 {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, False)}),
% 135.34/134.52 (??.TPTP_Interpret.ind1,
% 135.34/134.52 {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, False)})}
% 135.34/134.52 bnd_c2_2: {(??.TPTP_Interpret.ind0,
% 135.34/134.52 {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, False)}),
% 135.34/134.52 (??.TPTP_Interpret.ind1,
% 135.34/134.52 {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, False)})}
% 135.34/134.52 bnd_c6_2: {(??.TPTP_Interpret.ind0,
% 135.34/134.52 {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, True)}),
% 135.34/134.52 (??.TPTP_Interpret.ind1,
% 135.34/134.52 {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, False)})}
% 135.34/134.52 bnd_a300: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_c8_0: True
% 135.34/134.52 bnd_c7_1: {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, True)}
% 135.34/134.52 bnd_c3_2: {(??.TPTP_Interpret.ind0,
% 135.34/134.52 {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, True)}),
% 135.34/134.52 (??.TPTP_Interpret.ind1,
% 135.34/134.52 {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, False)})}
% 135.34/134.52 bnd_c1_2: {(??.TPTP_Interpret.ind0,
% 135.34/134.52 {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, False)}),
% 135.34/134.52 (??.TPTP_Interpret.ind1,
% 135.34/134.52 {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, True)})}
% 135.34/134.52 bnd_c4_2: {(??.TPTP_Interpret.ind0,
% 135.34/134.52 {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, True)}),
% 135.34/134.52 (??.TPTP_Interpret.ind1,
% 135.34/134.52 {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, True)})}
% 135.34/134.52 bnd_ndr1_1: {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, True)}
% 135.34/134.52 bnd_a299: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_c7_0: True
% 135.34/134.52 bnd_c3_1: {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, True)}
% 135.34/134.52 bnd_c1_1: {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, False)}
% 135.34/134.52 bnd_a298: ??.TPTP_Interpret.ind0
% 135.34/134.52 bnd_c8_1: {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, False)}
% 135.34/134.52 bnd_ndr1_0: True
% 135.34/134.52 bnd_c3_0: False
% 135.34/134.52 bnd_c2_0: True
% 135.34/134.52
% 135.34/134.52 % SZS status CounterSatisfiable
%------------------------------------------------------------------------------