TSTP Solution File: SYN545+1 by Refute---2015
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%------------------------------------------------------------------------------
% File : Refute---2015
% Problem : SYN545+1 : TPTP v6.4.0. Released v2.1.0.
% Transfm : none
% Format : tptp:raw
% Command : isabelle tptp_refute %d %s
% Computer : n162.star.cs.uiowa.edu
% Model : x86_64 x86_64
% CPU : Intel(R) Xeon(R) CPU E5-2609 0 2.40GHz
% Memory : 32218.75MB
% OS : Linux 3.10.0-327.10.1.el7.x86_64
% CPULimit : 300s
% DateTime : Thu Apr 14 06:42:20 EDT 2016
% Result : CounterSatisfiable 136.18s
% Output : Assurance 0s
% Verified :
% SZS Type : None (Parsing solution fails)
% Syntax : Number of formulae : 0
% Comments :
%------------------------------------------------------------------------------
%----No solution output by system
%------------------------------------------------------------------------------
%----ORIGINAL SYSTEM OUTPUT
% 0.00/0.03 % Problem : SYN545+1 : TPTP v6.4.0. Released v2.1.0.
% 0.02/0.04 % Command : isabelle tptp_refute %d %s
% 0.03/0.23 % Computer : n162.star.cs.uiowa.edu
% 0.03/0.23 % Model : x86_64 x86_64
% 0.03/0.23 % CPU : Intel(R) Xeon(R) CPU E5-2609 0 @ 2.40GHz
% 0.03/0.23 % Memory : 32218.75MB
% 0.03/0.23 % OS : Linux 3.10.0-327.10.1.el7.x86_64
% 0.03/0.23 % CPULimit : 300
% 0.03/0.23 % DateTime : Sat Apr 9 00:15:54 CDT 2016
% 0.03/0.23 % CPUTime:
% 6.32/5.88 > val it = (): unit
% 7.12/6.68 Trying to find a model that refutes: ~ (((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((~ bnd_c3_0 |
% 7.12/6.68 (ALL U.
% 7.12/6.68 bnd_ndr1_0 -->
% 7.12/6.68 ((ALL V.
% 7.12/6.68 bnd_ndr1_1 U -->
% 7.12/6.68 bnd_c3_2 U V | bnd_c4_2 U V) |
% 7.12/6.68 ((bnd_ndr1_1 U & ~ bnd_c7_2 U bnd_a147) &
% 7.12/6.68 ~ bnd_c3_2 U bnd_a147) &
% 7.12/6.68 bnd_c5_2 U bnd_a147) |
% 7.12/6.68 (ALL W.
% 7.12/6.68 bnd_ndr1_1 U -->
% 7.12/6.68 (~ bnd_c5_2 U W | bnd_c4_2 U W) |
% 7.12/6.68 ~ bnd_c7_2 U W))) &
% 7.12/6.68 ((~ bnd_c8_0 | ~ bnd_c1_0) | ~ bnd_c2_0)) &
% 7.12/6.68 (((((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a148) &
% 7.12/6.68 ~ bnd_c1_2 bnd_a148 bnd_a149) &
% 7.12/6.68 bnd_c7_2 bnd_a148 bnd_a149) &
% 7.12/6.68 bnd_c2_2 bnd_a148 bnd_a149) &
% 7.12/6.68 (ALL X.
% 7.12/6.68 bnd_ndr1_1 bnd_a148 -->
% 7.12/6.68 (bnd_c5_2 bnd_a148 X | ~ bnd_c8_2 bnd_a148 X) |
% 7.12/6.68 ~ bnd_c4_2 bnd_a148 X)) &
% 7.12/6.68 bnd_ndr1_1 bnd_a148) &
% 7.12/6.68 ~ bnd_c1_2 bnd_a148 bnd_a150) &
% 7.12/6.68 ~ bnd_c8_2 bnd_a148 bnd_a150 |
% 7.12/6.68 ~ bnd_c8_0) |
% 7.12/6.68 bnd_c7_0)) &
% 7.12/6.68 (((ALL Y.
% 7.12/6.68 bnd_ndr1_0 -->
% 7.12/6.68 (~ bnd_c6_1 Y |
% 7.12/6.68 (ALL Z.
% 7.12/6.68 bnd_ndr1_1 Y -->
% 7.12/6.68 (~ bnd_c5_2 Y Z | bnd_c3_2 Y Z) |
% 7.12/6.68 bnd_c4_2 Y Z)) |
% 7.12/6.68 ~ bnd_c8_1 Y) |
% 7.12/6.68 bnd_c3_0) |
% 7.12/6.68 bnd_c8_0)) &
% 7.12/6.68 ((~ bnd_c4_0 |
% 7.12/6.68 (ALL X1.
% 7.12/6.68 bnd_ndr1_0 -->
% 7.12/6.68 (bnd_c8_1 X1 | bnd_c6_1 X1) | bnd_c2_1 X1)) |
% 7.12/6.68 (ALL X2.
% 7.12/6.68 bnd_ndr1_0 -->
% 7.12/6.68 (~ bnd_c3_1 X2 |
% 7.12/6.68 ((bnd_ndr1_1 X2 & ~ bnd_c8_2 X2 bnd_a151) &
% 7.12/6.68 ~ bnd_c1_2 X2 bnd_a151) &
% 7.12/6.68 ~ bnd_c5_2 X2 bnd_a151) |
% 7.12/6.68 bnd_c5_1 X2))) &
% 7.12/6.68 (~ bnd_c7_0 |
% 7.12/6.68 (ALL X3.
% 7.12/6.68 bnd_ndr1_0 -->
% 7.12/6.68 ((ALL X4.
% 7.12/6.68 bnd_ndr1_1 X3 -->
% 7.12/6.68 (~ bnd_c3_2 X3 X4 | bnd_c7_2 X3 X4) |
% 7.12/6.68 ~ bnd_c5_2 X3 X4) |
% 7.12/6.68 ((bnd_ndr1_1 X3 & ~ bnd_c4_2 X3 bnd_a152) &
% 7.12/6.68 ~ bnd_c3_2 X3 bnd_a152) &
% 7.12/6.68 bnd_c7_2 X3 bnd_a152) |
% 7.12/6.68 ~ bnd_c5_1 X3))) &
% 7.12/6.68 ((~ bnd_c4_0 |
% 7.12/6.68 ((bnd_ndr1_0 & ~ bnd_c4_1 bnd_a153) &
% 7.12/6.68 ~ bnd_c1_1 bnd_a153) &
% 7.12/6.68 (ALL X5.
% 7.12/6.68 bnd_ndr1_1 bnd_a153 -->
% 7.12/6.68 (bnd_c8_2 bnd_a153 X5 | ~ bnd_c3_2 bnd_a153 X5) |
% 7.12/6.68 bnd_c5_2 bnd_a153 X5)) |
% 7.12/6.68 ~ bnd_c1_0)) &
% 7.12/6.68 ((((bnd_ndr1_0 & bnd_c4_1 bnd_a154) & bnd_c6_1 bnd_a154) &
% 7.12/6.68 bnd_c2_1 bnd_a154 |
% 7.12/6.68 (((((bnd_ndr1_0 &
% 7.12/6.68 (ALL X6.
% 7.12/6.68 bnd_ndr1_1 bnd_a155 -->
% 7.12/6.68 (~ bnd_c4_2 bnd_a155 X6 | ~ bnd_c2_2 bnd_a155 X6) |
% 7.12/6.68 bnd_c3_2 bnd_a155 X6)) &
% 7.12/6.68 ~ bnd_c7_1 bnd_a155) &
% 7.12/6.68 bnd_ndr1_1 bnd_a155) &
% 7.12/6.68 bnd_c2_2 bnd_a155 bnd_a156) &
% 7.12/6.68 bnd_c7_2 bnd_a155 bnd_a156) &
% 7.12/6.68 ~ bnd_c5_2 bnd_a155 bnd_a156) |
% 7.12/6.68 (bnd_ndr1_0 & ~ bnd_c4_1 bnd_a157) & bnd_c5_1 bnd_a157)) &
% 7.12/6.68 ((((bnd_ndr1_0 &
% 7.12/6.68 (ALL X7.
% 7.12/6.68 bnd_ndr1_1 bnd_a158 -->
% 7.12/6.68 (bnd_c4_2 bnd_a158 X7 | ~ bnd_c1_2 bnd_a158 X7) |
% 7.12/6.68 bnd_c8_2 bnd_a158 X7)) &
% 7.12/6.68 ~ bnd_c4_1 bnd_a158) &
% 7.12/6.68 bnd_c1_1 bnd_a158 |
% 7.12/6.68 bnd_c1_0) |
% 7.12/6.68 bnd_c5_0)) &
% 7.12/6.68 (((ALL X8.
% 7.12/6.68 bnd_ndr1_0 -->
% 7.12/6.68 (~ bnd_c3_1 X8 |
% 7.12/6.68 (ALL X9.
% 7.12/6.68 bnd_ndr1_1 X8 -->
% 7.12/6.68 (~ bnd_c4_2 X8 X9 | bnd_c8_2 X8 X9) |
% 7.12/6.68 bnd_c2_2 X8 X9)) |
% 7.12/6.68 bnd_c2_1 X8) |
% 7.12/6.68 ((bnd_ndr1_0 &
% 7.12/6.68 (ALL X10.
% 7.12/6.68 bnd_ndr1_1 bnd_a159 -->
% 7.12/6.68 (bnd_c2_2 bnd_a159 X10 | ~ bnd_c4_2 bnd_a159 X10) |
% 7.12/6.68 ~ bnd_c8_2 bnd_a159 X10)) &
% 7.12/6.68 ~ bnd_c4_1 bnd_a159) &
% 7.12/6.68 bnd_c2_1 bnd_a159) |
% 7.12/6.68 ~ bnd_c2_0)) &
% 7.12/6.68 (((((((bnd_ndr1_0 &
% 7.12/6.68 (ALL X11.
% 7.12/6.68 bnd_ndr1_1 bnd_a160 --> ~ bnd_c6_2 bnd_a160 X11)) &
% 7.12/6.68 ~ bnd_c6_1 bnd_a160) &
% 7.12/6.68 bnd_ndr1_1 bnd_a160) &
% 7.12/6.68 bnd_c8_2 bnd_a160 bnd_a161) &
% 7.12/6.68 ~ bnd_c5_2 bnd_a160 bnd_a161) &
% 7.12/6.68 bnd_c2_2 bnd_a160 bnd_a161 |
% 7.12/6.68 (ALL X12. bnd_ndr1_0 --> bnd_c8_1 X12 | ~ bnd_c1_1 X12)) |
% 7.12/6.68 (ALL X13.
% 7.12/6.68 bnd_ndr1_0 -->
% 7.12/6.68 (bnd_c4_1 X13 |
% 7.12/6.68 (ALL X14.
% 7.12/6.68 bnd_ndr1_1 X13 -->
% 7.12/6.68 ~ bnd_c7_2 X13 X14 | bnd_c2_2 X13 X14)) |
% 7.12/6.68 bnd_c5_1 X13))) &
% 7.12/6.68 ((((((bnd_ndr1_0 & ~ bnd_c8_1 bnd_a162) &
% 7.12/6.68 (ALL X15.
% 7.12/6.68 bnd_ndr1_1 bnd_a162 -->
% 7.12/6.68 (bnd_c8_2 bnd_a162 X15 | bnd_c3_2 bnd_a162 X15) |
% 7.12/6.68 ~ bnd_c7_2 bnd_a162 X15)) &
% 7.12/6.68 bnd_ndr1_1 bnd_a162) &
% 7.12/6.68 ~ bnd_c5_2 bnd_a162 bnd_a163) &
% 7.12/6.68 ~ bnd_c6_2 bnd_a162 bnd_a163) &
% 7.12/6.68 bnd_c8_2 bnd_a162 bnd_a163 |
% 7.12/6.68 bnd_c5_0)) &
% 7.12/6.68 ((~ bnd_c7_0 |
% 7.12/6.68 (((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a164) &
% 7.12/6.68 ~ bnd_c2_2 bnd_a164 bnd_a165) &
% 7.12/6.68 ~ bnd_c5_2 bnd_a164 bnd_a165) &
% 7.12/6.68 bnd_c3_2 bnd_a164 bnd_a165) &
% 7.12/6.68 (ALL X16.
% 7.12/6.68 bnd_ndr1_1 bnd_a164 -->
% 7.12/6.68 ~ bnd_c8_2 bnd_a164 X16 | ~ bnd_c2_2 bnd_a164 X16)) &
% 7.12/6.68 bnd_c6_1 bnd_a164) |
% 7.12/6.68 (((((bnd_ndr1_0 & bnd_c1_1 bnd_a166) & bnd_ndr1_1 bnd_a166) &
% 7.12/6.68 bnd_c7_2 bnd_a166 bnd_a167) &
% 7.12/6.68 ~ bnd_c8_2 bnd_a166 bnd_a167) &
% 7.12/6.68 ~ bnd_c3_2 bnd_a166 bnd_a167) &
% 7.12/6.68 bnd_c7_1 bnd_a166)) &
% 7.12/6.68 ((bnd_c3_0 |
% 7.12/6.68 ((bnd_ndr1_0 & ~ bnd_c2_1 bnd_a168) &
% 7.12/6.68 (ALL X17.
% 7.12/6.68 bnd_ndr1_1 bnd_a168 -->
% 7.12/6.68 (bnd_c2_2 bnd_a168 X17 | ~ bnd_c5_2 bnd_a168 X17) |
% 7.12/6.68 ~ bnd_c8_2 bnd_a168 X17)) &
% 7.12/6.68 ~ bnd_c6_1 bnd_a168) |
% 7.12/6.68 ~ bnd_c4_0)) &
% 7.12/6.68 ((~ bnd_c4_0 | ~ bnd_c2_0) |
% 7.12/6.68 (ALL X18.
% 7.12/6.68 bnd_ndr1_0 -->
% 7.12/6.68 ((ALL X19.
% 7.12/6.68 bnd_ndr1_1 X18 -->
% 7.12/6.68 ~ bnd_c4_2 X18 X19 | ~ bnd_c1_2 X18 X19) |
% 7.12/6.68 ~ bnd_c8_1 X18) |
% 7.12/6.68 (ALL X20.
% 7.12/6.68 bnd_ndr1_1 X18 -->
% 7.12/6.68 (~ bnd_c6_2 X18 X20 | ~ bnd_c3_2 X18 X20) |
% 7.12/6.68 ~ bnd_c1_2 X18 X20)))) &
% 7.12/6.68 ((ALL X21.
% 7.12/6.68 bnd_ndr1_0 -->
% 7.12/6.68 (ALL X22.
% 7.12/6.68 bnd_ndr1_1 X21 -->
% 7.12/6.68 (bnd_c2_2 X21 X22 | bnd_c1_2 X21 X22) | ~ bnd_c7_2 X21 X22) |
% 7.12/6.68 bnd_c4_1 X21) |
% 7.12/6.68 (ALL X23.
% 7.12/6.68 bnd_ndr1_0 -->
% 7.12/6.68 ((ALL X24.
% 7.12/6.68 bnd_ndr1_1 X23 -->
% 7.12/6.68 (~ bnd_c5_2 X23 X24 | bnd_c3_2 X23 X24) |
% 7.12/6.68 bnd_c2_2 X23 X24) |
% 7.12/6.68 bnd_c1_1 X23) |
% 7.12/6.68 ~ bnd_c7_1 X23))) &
% 7.12/6.68 ((~ bnd_c4_0 | ~ bnd_c7_0) |
% 7.12/6.68 ((bnd_ndr1_0 & bnd_c2_1 bnd_a169) & bnd_c8_1 bnd_a169) &
% 7.12/6.68 ~ bnd_c6_1 bnd_a169)) &
% 7.12/6.68 ((bnd_c8_0 | bnd_c7_0) | ~ bnd_c3_0)) &
% 7.12/6.68 ((bnd_c7_0 |
% 7.12/6.68 ((bnd_ndr1_0 & ~ bnd_c5_1 bnd_a170) & ~ bnd_c7_1 bnd_a170) &
% 7.12/6.68 (ALL X25.
% 7.12/6.68 bnd_ndr1_1 bnd_a170 -->
% 7.12/6.68 (bnd_c3_2 bnd_a170 X25 | ~ bnd_c2_2 bnd_a170 X25) |
% 7.12/6.68 ~ bnd_c4_2 bnd_a170 X25)) |
% 7.12/6.68 bnd_c6_0)) &
% 7.12/6.68 ((~ bnd_c1_0 |
% 7.12/6.68 (ALL X26.
% 7.12/6.68 bnd_ndr1_0 --> (bnd_c3_1 X26 | ~ bnd_c4_1 X26) | bnd_c5_1 X26)) |
% 7.12/6.68 (((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a171) & ~ bnd_c1_2 bnd_a171 bnd_a172) &
% 7.12/6.68 bnd_c5_2 bnd_a171 bnd_a172) &
% 7.12/6.68 bnd_c2_2 bnd_a171 bnd_a172) &
% 7.12/6.68 bnd_c4_1 bnd_a171) &
% 7.12/6.68 ~ bnd_c2_1 bnd_a171)) &
% 7.12/6.68 ((((bnd_ndr1_0 &
% 7.12/6.68 (ALL X27.
% 7.12/6.68 bnd_ndr1_1 bnd_a173 -->
% 7.12/6.68 ~ bnd_c8_2 bnd_a173 X27 | ~ bnd_c1_2 bnd_a173 X27)) &
% 7.12/6.68 (ALL X28.
% 7.12/6.68 bnd_ndr1_1 bnd_a173 -->
% 7.12/6.68 (~ bnd_c7_2 bnd_a173 X28 | bnd_c8_2 bnd_a173 X28) |
% 7.12/6.68 bnd_c5_2 bnd_a173 X28)) &
% 7.12/6.68 ~ bnd_c6_1 bnd_a173 |
% 7.12/6.68 ((bnd_ndr1_0 & ~ bnd_c3_1 bnd_a174) & bnd_c5_1 bnd_a174) &
% 7.12/6.68 (ALL X29.
% 7.12/6.68 bnd_ndr1_1 bnd_a174 -->
% 7.12/6.68 (~ bnd_c8_2 bnd_a174 X29 | ~ bnd_c5_2 bnd_a174 X29) |
% 7.12/6.68 bnd_c6_2 bnd_a174 X29)) |
% 7.12/6.68 (ALL X30.
% 7.12/6.68 bnd_ndr1_0 -->
% 7.12/6.68 (((bnd_ndr1_1 X30 & bnd_c5_2 X30 bnd_a175) &
% 7.12/6.68 ~ bnd_c2_2 X30 bnd_a175) &
% 7.12/6.68 bnd_c3_2 X30 bnd_a175 |
% 7.12/6.68 (ALL X31.
% 7.12/6.68 bnd_ndr1_1 X30 -->
% 7.12/6.68 (bnd_c4_2 X30 X31 | bnd_c3_2 X30 X31) | bnd_c6_2 X30 X31)) |
% 7.12/6.68 bnd_c3_1 X30))) &
% 7.12/6.68 ((((((((((bnd_ndr1_0 &
% 7.12/6.68 (ALL X32.
% 7.12/6.68 bnd_ndr1_1 bnd_a176 -->
% 7.12/6.68 (~ bnd_c2_2 bnd_a176 X32 | bnd_c7_2 bnd_a176 X32) |
% 7.12/6.68 ~ bnd_c3_2 bnd_a176 X32)) &
% 7.12/6.68 bnd_ndr1_1 bnd_a176) &
% 7.12/6.68 ~ bnd_c2_2 bnd_a176 bnd_a177) &
% 7.12/6.68 ~ bnd_c6_2 bnd_a176 bnd_a177) &
% 7.12/6.68 ~ bnd_c3_2 bnd_a176 bnd_a177) &
% 7.12/6.68 bnd_ndr1_1 bnd_a176) &
% 7.12/6.68 bnd_c8_2 bnd_a176 bnd_a178) &
% 7.12/6.68 ~ bnd_c4_2 bnd_a176 bnd_a178) &
% 7.12/6.68 ~ bnd_c7_2 bnd_a176 bnd_a178 |
% 7.12/6.68 bnd_c7_0) |
% 7.12/6.68 (((((bnd_ndr1_0 &
% 7.12/6.68 (ALL X33.
% 7.12/6.68 bnd_ndr1_1 bnd_a179 -->
% 7.12/6.68 bnd_c2_2 bnd_a179 X33 | ~ bnd_c3_2 bnd_a179 X33)) &
% 7.12/6.68 ~ bnd_c2_1 bnd_a179) &
% 7.12/6.68 bnd_ndr1_1 bnd_a179) &
% 7.12/6.68 bnd_c2_2 bnd_a179 bnd_a180) &
% 7.12/6.68 bnd_c3_2 bnd_a179 bnd_a180) &
% 7.12/6.68 bnd_c6_2 bnd_a179 bnd_a180)) &
% 7.12/6.68 (((ALL X34.
% 7.12/6.68 bnd_ndr1_0 -->
% 7.12/6.68 ((ALL X35.
% 7.12/6.68 bnd_ndr1_1 X34 -->
% 7.12/6.68 (~ bnd_c8_2 X34 X35 | ~ bnd_c1_2 X34 X35) | ~ bnd_c3_2 X34 X35) |
% 7.12/6.68 ~ bnd_c3_1 X34) |
% 7.12/6.68 (ALL X36.
% 7.12/6.68 bnd_ndr1_1 X34 --> ~ bnd_c5_2 X34 X36 | ~ bnd_c6_2 X34 X36)) |
% 7.12/6.68 bnd_c5_0) |
% 7.12/6.68 ((bnd_ndr1_0 &
% 7.12/6.68 (ALL X37.
% 7.12/6.68 bnd_ndr1_1 bnd_a181 -->
% 7.12/6.68 (~ bnd_c2_2 bnd_a181 X37 | ~ bnd_c6_2 bnd_a181 X37) |
% 7.12/6.68 ~ bnd_c4_2 bnd_a181 X37)) &
% 7.12/6.68 bnd_c2_1 bnd_a181) &
% 7.12/6.68 (ALL X38.
% 7.12/6.68 bnd_ndr1_1 bnd_a181 -->
% 7.12/6.68 (~ bnd_c2_2 bnd_a181 X38 | bnd_c4_2 bnd_a181 X38) |
% 7.12/6.68 ~ bnd_c3_2 bnd_a181 X38))) &
% 7.12/6.68 (((ALL X39.
% 7.12/6.68 bnd_ndr1_0 -->
% 7.12/6.68 (bnd_c8_1 X39 |
% 7.12/6.68 (ALL X40.
% 7.12/6.68 bnd_ndr1_1 X39 -->
% 7.12/6.68 (bnd_c7_2 X39 X40 | ~ bnd_c1_2 X39 X40) | bnd_c5_2 X39 X40)) |
% 7.12/6.68 bnd_c1_1 X39) |
% 7.12/6.68 bnd_c6_0) |
% 7.12/6.68 ~ bnd_c1_0)) &
% 7.12/6.68 ((bnd_c3_0 | bnd_c6_0) | bnd_c8_0)) &
% 7.12/6.68 (bnd_c1_0 |
% 7.12/6.68 ((bnd_ndr1_0 &
% 7.12/6.68 (ALL X41.
% 7.12/6.68 bnd_ndr1_1 bnd_a182 -->
% 7.12/6.68 (~ bnd_c2_2 bnd_a182 X41 | bnd_c1_2 bnd_a182 X41) |
% 7.12/6.68 ~ bnd_c4_2 bnd_a182 X41)) &
% 7.12/6.68 (ALL X42.
% 7.12/6.68 bnd_ndr1_1 bnd_a182 -->
% 7.12/6.68 (~ bnd_c7_2 bnd_a182 X42 | ~ bnd_c6_2 bnd_a182 X42) |
% 7.12/6.68 ~ bnd_c1_2 bnd_a182 X42)) &
% 7.12/6.68 ~ bnd_c1_1 bnd_a182)) &
% 7.12/6.68 ((bnd_c7_0 | ~ bnd_c1_0) |
% 7.12/6.68 (((((bnd_ndr1_0 & bnd_c1_1 bnd_a183) &
% 7.12/6.68 bnd_ndr1_1 bnd_a183) &
% 7.12/6.68 bnd_c7_2 bnd_a183 bnd_a184) &
% 7.12/6.68 bnd_c5_2 bnd_a183 bnd_a184) &
% 7.12/6.68 bnd_c3_2 bnd_a183 bnd_a184) &
% 7.12/6.68 bnd_c4_1 bnd_a183)) &
% 7.12/6.68 ((bnd_c4_0 | bnd_c2_0) |
% 7.12/6.68 (ALL X43.
% 7.12/6.68 bnd_ndr1_0 -->
% 7.12/6.68 ((ALL X44.
% 7.12/6.68 bnd_ndr1_1 X43 -->
% 7.12/6.68 (bnd_c5_2 X43 X44 | ~ bnd_c6_2 X43 X44) | ~ bnd_c8_2 X43 X44) |
% 7.12/6.68 bnd_c6_1 X43) |
% 7.12/6.68 (ALL X45.
% 7.12/6.68 bnd_ndr1_1 X43 --> ~ bnd_c5_2 X43 X45 | ~ bnd_c7_2 X43 X45)))) &
% 7.12/6.68 ((bnd_c1_0 | ~ bnd_c3_0) |
% 7.12/6.68 (ALL X46.
% 7.12/6.68 bnd_ndr1_0 -->
% 7.12/6.68 (bnd_c3_1 X46 |
% 7.12/6.68 ((bnd_ndr1_1 X46 &
% 7.12/6.68 bnd_c7_2 X46 bnd_a185) &
% 7.12/6.68 bnd_c4_2 X46 bnd_a185) &
% 7.12/6.68 bnd_c5_2 X46 bnd_a185) |
% 7.12/6.68 ~ bnd_c5_1 X46))) &
% 7.12/6.68 ((bnd_c1_0 |
% 7.12/6.68 (ALL X47.
% 7.12/6.68 bnd_ndr1_0 -->
% 7.12/6.68 (~ bnd_c1_1 X47 |
% 7.12/6.68 (ALL X48.
% 7.12/6.68 bnd_ndr1_1 X47 -->
% 7.12/6.68 (bnd_c7_2 X47 X48 | ~ bnd_c8_2 X47 X48) | bnd_c6_2 X47 X48)) |
% 7.12/6.68 (ALL X49.
% 7.12/6.68 bnd_ndr1_1 X47 -->
% 7.12/6.68 (bnd_c4_2 X47 X49 | bnd_c5_2 X47 X49) | ~ bnd_c1_2 X47 X49))) |
% 7.12/6.68 bnd_c5_0)) &
% 7.12/6.68 ((bnd_c2_0 | ~ bnd_c3_0) |
% 7.12/6.68 ((bnd_ndr1_0 &
% 7.12/6.68 (ALL X50.
% 7.12/6.68 bnd_ndr1_1 bnd_a186 -->
% 7.12/6.68 (~ bnd_c8_2 bnd_a186 X50 |
% 7.12/6.68 bnd_c5_2 bnd_a186 X50) |
% 7.12/6.68 ~ bnd_c1_2 bnd_a186 X50)) &
% 7.12/6.68 ~ bnd_c7_1 bnd_a186) &
% 7.12/6.68 bnd_c1_1 bnd_a186)) &
% 7.12/6.68 ((((((bnd_ndr1_0 & bnd_c4_1 bnd_a187) &
% 7.12/6.68 bnd_ndr1_1 bnd_a187) &
% 7.12/6.68 ~ bnd_c4_2 bnd_a187 bnd_a188) &
% 7.12/6.68 ~ bnd_c6_2 bnd_a187 bnd_a188) &
% 7.12/6.68 ~ bnd_c3_1 bnd_a187 |
% 7.12/6.68 ((bnd_ndr1_0 & ~ bnd_c6_1 bnd_a189) &
% 7.12/6.68 (ALL X51.
% 7.12/6.68 bnd_ndr1_1 bnd_a189 -->
% 7.12/6.68 (~ bnd_c2_2 bnd_a189 X51 |
% 7.12/6.68 bnd_c7_2 bnd_a189 X51) |
% 7.12/6.68 ~ bnd_c8_2 bnd_a189 X51)) &
% 7.12/6.68 (ALL X52.
% 7.12/6.68 bnd_ndr1_1 bnd_a189 -->
% 7.12/6.68 (~ bnd_c8_2 bnd_a189 X52 |
% 7.12/6.68 ~ bnd_c1_2 bnd_a189 X52) |
% 7.12/6.68 bnd_c6_2 bnd_a189 X52)) |
% 7.12/6.68 (ALL X53.
% 7.12/6.68 bnd_ndr1_0 -->
% 7.12/6.68 ((ALL X54.
% 7.12/6.68 bnd_ndr1_1 X53 -->
% 7.12/6.68 (bnd_c2_2 X53 X54 | bnd_c4_2 X53 X54) | bnd_c1_2 X53 X54) |
% 7.12/6.68 (ALL X55.
% 7.12/6.68 bnd_ndr1_1 X53 -->
% 7.12/6.68 (~ bnd_c3_2 X53 X55 | bnd_c6_2 X53 X55) | ~ bnd_c8_2 X53 X55)) |
% 7.12/6.68 ~ bnd_c7_1 X53))) &
% 7.12/6.68 (((ALL X56.
% 7.12/6.68 bnd_ndr1_0 -->
% 7.12/6.68 (bnd_c3_1 X56 |
% 7.12/6.68 ((bnd_ndr1_1 X56 &
% 7.12/6.68 ~ bnd_c3_2 X56 bnd_a190) &
% 7.12/6.68 bnd_c1_2 X56 bnd_a190) &
% 7.12/6.68 ~ bnd_c6_2 X56 bnd_a190) |
% 7.12/6.68 bnd_c2_1 X56) |
% 7.12/6.68 (ALL X57.
% 7.12/6.68 bnd_ndr1_0 -->
% 7.12/6.68 (bnd_c8_1 X57 |
% 7.12/6.68 (ALL X58.
% 7.12/6.68 bnd_ndr1_1 X57 --> bnd_c6_2 X57 X58 | bnd_c7_2 X57 X58)) |
% 7.12/6.68 (ALL X59.
% 7.12/6.68 bnd_ndr1_1 X57 -->
% 7.12/6.68 (bnd_c3_2 X57 X59 |
% 7.12/6.68 ~ bnd_c2_2 X57 X59) |
% 7.12/6.68 ~ bnd_c6_2 X57 X59))) |
% 7.12/6.68 ((((bnd_ndr1_0 & ~ bnd_c5_1 bnd_a191) &
% 7.12/6.68 bnd_c1_1 bnd_a191) &
% 7.12/6.68 bnd_ndr1_1 bnd_a191) &
% 7.12/6.68 bnd_c7_2 bnd_a191 bnd_a192) &
% 7.12/6.68 ~ bnd_c8_2 bnd_a191 bnd_a192)) &
% 7.12/6.68 ((bnd_c1_0 |
% 7.12/6.68 (ALL X60.
% 7.12/6.68 bnd_ndr1_0 -->
% 7.12/6.68 ((ALL X61.
% 7.12/6.68 bnd_ndr1_1 X60 -->
% 7.12/6.68 (~ bnd_c6_2 X60 X61 |
% 7.12/6.68 ~ bnd_c7_2 X60 X61) |
% 7.12/6.68 bnd_c2_2 X60 X61) |
% 7.12/6.68 ~ bnd_c3_1 X60) |
% 7.12/6.68 bnd_c5_1 X60)) |
% 7.12/6.68 (((((bnd_ndr1_0 & ~ bnd_c1_1 bnd_a193) &
% 7.12/6.68 ~ bnd_c7_1 bnd_a193) &
% 7.12/6.68 bnd_ndr1_1 bnd_a193) &
% 7.12/6.68 ~ bnd_c4_2 bnd_a193 bnd_a194) &
% 7.12/6.68 ~ bnd_c6_2 bnd_a193 bnd_a194) &
% 7.12/6.68 bnd_c7_2 bnd_a193 bnd_a194)) &
% 7.12/6.68 (((ALL X62.
% 7.12/6.68 bnd_ndr1_0 -->
% 7.12/6.68 ((ALL X63.
% 7.12/6.68 bnd_ndr1_1 X62 -->
% 7.12/6.68 (~ bnd_c1_2 X62 X63 |
% 7.12/6.68 ~ bnd_c6_2 X62 X63) |
% 7.12/6.68 ~ bnd_c3_2 X62 X63) |
% 7.12/6.68 ~ bnd_c4_1 X62) |
% 7.12/6.68 ~ bnd_c2_1 X62) |
% 7.12/6.68 bnd_ndr1_0 &
% 7.12/6.68 (ALL X64.
% 7.12/6.68 bnd_ndr1_1 bnd_a195 -->
% 7.12/6.68 (bnd_c4_2 bnd_a195 X64 |
% 7.12/6.68 ~ bnd_c6_2 bnd_a195 X64) |
% 7.12/6.68 bnd_c5_2 bnd_a195 X64)) |
% 7.12/6.68 ((bnd_ndr1_0 & bnd_c2_1 bnd_a196) &
% 7.12/6.68 ~ bnd_c4_1 bnd_a196) &
% 7.12/6.68 (ALL X65.
% 7.12/6.68 bnd_ndr1_1 bnd_a196 -->
% 7.12/6.68 ~ bnd_c1_2 bnd_a196 X65 |
% 7.12/6.68 ~ bnd_c4_2 bnd_a196 X65))) &
% 7.12/6.68 (bnd_c5_0 |
% 7.12/6.68 (((((bnd_ndr1_0 & ~ bnd_c8_1 bnd_a197) &
% 7.12/6.68 ~ bnd_c6_1 bnd_a197) &
% 7.12/6.68 bnd_ndr1_1 bnd_a197) &
% 7.12/6.68 bnd_c4_2 bnd_a197 bnd_a198) &
% 7.12/6.68 ~ bnd_c6_2 bnd_a197 bnd_a198) &
% 7.12/6.68 ~ bnd_c1_2 bnd_a197 bnd_a198)) &
% 7.12/6.68 ((~ bnd_c5_0 | bnd_c7_0) | bnd_c8_0)) &
% 7.12/6.68 ((bnd_ndr1_0 & bnd_c1_1 bnd_a199 |
% 7.12/6.68 (bnd_ndr1_0 & ~ bnd_c1_1 bnd_a200) &
% 7.12/6.68 bnd_c6_1 bnd_a200) |
% 7.12/6.68 (ALL X66.
% 7.12/6.68 bnd_ndr1_0 -->
% 7.12/6.68 ((ALL X67.
% 7.12/6.68 bnd_ndr1_1 X66 -->
% 7.12/6.68 bnd_c2_2 X66 X67 | bnd_c7_2 X66 X67) |
% 7.12/6.68 ((bnd_ndr1_1 X66 & bnd_c1_2 X66 bnd_a201) &
% 7.12/6.68 bnd_c8_2 X66 bnd_a201) &
% 7.12/6.68 bnd_c7_2 X66 bnd_a201) |
% 7.12/6.68 ~ bnd_c2_1 X66))) &
% 7.12/6.68 (((ALL X68.
% 7.12/6.68 bnd_ndr1_0 -->
% 7.12/6.68 (ALL X69.
% 7.12/6.68 bnd_ndr1_1 X68 -->
% 7.12/6.68 (bnd_c2_2 X68 X69 | bnd_c4_2 X68 X69) |
% 7.12/6.68 ~ bnd_c5_2 X68 X69) |
% 7.12/6.68 ~ bnd_c2_1 X68) |
% 7.12/6.68 ((bnd_ndr1_0 & bnd_c7_1 bnd_a202) &
% 7.12/6.68 (ALL X70.
% 7.12/6.68 bnd_ndr1_1 bnd_a202 -->
% 7.12/6.68 (~ bnd_c6_2 bnd_a202 X70 |
% 7.12/6.68 bnd_c3_2 bnd_a202 X70) |
% 7.12/6.68 bnd_c8_2 bnd_a202 X70)) &
% 7.12/6.68 (ALL X71.
% 7.12/6.68 bnd_ndr1_1 bnd_a202 -->
% 7.12/6.68 (bnd_c6_2 bnd_a202 X71 | bnd_c7_2 bnd_a202 X71) |
% 7.12/6.68 ~ bnd_c3_2 bnd_a202 X71)) |
% 7.12/6.68 ((bnd_ndr1_0 & bnd_c4_1 bnd_a203) &
% 7.12/6.68 bnd_c8_1 bnd_a203) &
% 7.12/6.68 (ALL X72.
% 7.12/6.68 bnd_ndr1_1 bnd_a203 -->
% 7.12/6.68 (~ bnd_c1_2 bnd_a203 X72 |
% 7.12/6.68 ~ bnd_c5_2 bnd_a203 X72) |
% 7.12/6.68 ~ bnd_c8_2 bnd_a203 X72))) &
% 7.12/6.68 (bnd_c1_0 |
% 7.12/6.68 ((((bnd_ndr1_0 &
% 7.12/6.68 (ALL X73.
% 7.12/6.68 bnd_ndr1_1 bnd_a204 -->
% 7.12/6.68 bnd_c8_2 bnd_a204 X73 |
% 7.12/6.68 bnd_c2_2 bnd_a204 X73)) &
% 7.12/6.68 bnd_c8_1 bnd_a204) &
% 7.12/6.68 bnd_ndr1_1 bnd_a204) &
% 7.12/6.68 bnd_c7_2 bnd_a204 bnd_a205) &
% 7.12/6.68 bnd_c3_2 bnd_a204 bnd_a205)) &
% 7.12/6.68 ((bnd_c3_0 |
% 7.12/6.68 (ALL X74.
% 7.12/6.68 bnd_ndr1_0 -->
% 7.12/6.68 ((ALL X75.
% 7.12/6.68 bnd_ndr1_1 X74 -->
% 7.12/6.68 ~ bnd_c5_2 X74 X75 | ~ bnd_c4_2 X74 X75) |
% 7.12/6.68 ((bnd_ndr1_1 X74 & bnd_c3_2 X74 bnd_a206) &
% 7.12/6.68 bnd_c6_2 X74 bnd_a206) &
% 7.12/6.68 bnd_c4_2 X74 bnd_a206) |
% 7.12/6.68 ((bnd_ndr1_1 X74 & ~ bnd_c3_2 X74 bnd_a207) &
% 7.12/6.68 bnd_c8_2 X74 bnd_a207) &
% 7.12/6.68 ~ bnd_c5_2 X74 bnd_a207)) |
% 7.12/6.68 bnd_c4_0)) &
% 7.12/6.68 (((((((bnd_ndr1_0 & bnd_c8_1 bnd_a208) &
% 7.12/6.68 bnd_ndr1_1 bnd_a208) &
% 7.12/6.68 ~ bnd_c6_2 bnd_a208 bnd_a209) &
% 7.12/6.68 ~ bnd_c2_2 bnd_a208 bnd_a209) &
% 7.12/6.68 ~ bnd_c3_2 bnd_a208 bnd_a209) &
% 7.12/6.68 ~ bnd_c1_1 bnd_a208 |
% 7.12/6.68 (ALL X76.
% 7.12/6.68 bnd_ndr1_0 -->
% 7.12/6.68 ((ALL X77.
% 7.12/6.68 bnd_ndr1_1 X76 -->
% 7.12/6.68 (bnd_c7_2 X76 X77 | bnd_c4_2 X76 X77) |
% 7.12/6.68 ~ bnd_c6_2 X76 X77) |
% 7.12/6.68 (ALL X78.
% 7.12/6.68 bnd_ndr1_1 X76 -->
% 7.12/6.68 (~ bnd_c1_2 X76 X78 | bnd_c4_2 X76 X78) |
% 7.12/6.68 ~ bnd_c7_2 X76 X78)) |
% 7.12/6.68 bnd_c7_1 X76)) |
% 7.12/6.68 ~ bnd_c8_0)) &
% 7.12/6.68 (~ bnd_c6_0 |
% 7.12/6.68 (ALL X79.
% 7.12/6.68 bnd_ndr1_0 -->
% 7.12/6.68 ~ bnd_c4_1 X79 |
% 7.12/6.68 ((bnd_ndr1_1 X79 & ~ bnd_c5_2 X79 bnd_a210) &
% 7.12/6.68 bnd_c4_2 X79 bnd_a210) &
% 7.12/6.68 bnd_c8_2 X79 bnd_a210))) &
% 7.12/6.68 ((~ bnd_c5_0 | ~ bnd_c7_0) | bnd_c3_0)) &
% 7.12/6.68 ((bnd_c5_0 | ~ bnd_c4_0) | ~ bnd_c1_0)) &
% 7.12/6.68 ((((((bnd_ndr1_0 & bnd_c4_1 bnd_a211) & ~ bnd_c3_1 bnd_a211) &
% 7.12/6.68 bnd_ndr1_1 bnd_a211) &
% 7.12/6.68 ~ bnd_c1_2 bnd_a211 bnd_a212) &
% 7.12/6.68 ~ bnd_c8_2 bnd_a211 bnd_a212 |
% 7.12/6.68 (ALL X80.
% 7.12/6.68 bnd_ndr1_0 -->
% 7.12/6.68 (bnd_c5_1 X80 | ~ bnd_c4_1 X80) |
% 7.12/6.68 ((bnd_ndr1_1 X80 & bnd_c2_2 X80 bnd_a213) &
% 7.12/6.68 ~ bnd_c3_2 X80 bnd_a213) &
% 7.12/6.68 bnd_c7_2 X80 bnd_a213)) |
% 7.12/6.68 bnd_c7_0)) &
% 7.12/6.68 ((~ bnd_c2_0 |
% 7.12/6.68 (ALL X81.
% 7.12/6.68 bnd_ndr1_0 -->
% 7.12/6.68 (~ bnd_c1_1 X81 |
% 7.12/6.68 ((bnd_ndr1_1 X81 & ~ bnd_c2_2 X81 bnd_a214) &
% 7.12/6.68 bnd_c7_2 X81 bnd_a214) &
% 7.12/6.68 bnd_c4_2 X81 bnd_a214) |
% 7.12/6.68 bnd_c2_1 X81)) |
% 7.12/6.68 bnd_c4_0)) &
% 7.12/6.68 ((ALL X82.
% 7.12/6.68 bnd_ndr1_0 -->
% 7.12/6.68 (bnd_c2_1 X82 | ~ bnd_c5_1 X82) |
% 7.12/6.68 (ALL X83.
% 7.12/6.68 bnd_ndr1_1 X82 -->
% 7.12/6.68 (~ bnd_c2_2 X82 X83 | bnd_c3_2 X82 X83) |
% 7.12/6.68 bnd_c8_2 X82 X83)) |
% 7.12/6.68 bnd_c8_0)) &
% 7.12/6.68 (((((((bnd_ndr1_0 & bnd_c7_1 bnd_a215) & bnd_ndr1_1 bnd_a215) &
% 7.12/6.68 ~ bnd_c1_2 bnd_a215 bnd_a216) &
% 7.12/6.68 ~ bnd_c4_2 bnd_a215 bnd_a216) &
% 7.12/6.68 bnd_c3_2 bnd_a215 bnd_a216) &
% 7.12/6.68 ~ bnd_c2_1 bnd_a215 |
% 7.12/6.68 bnd_c7_0) |
% 7.12/6.68 bnd_c8_0)) &
% 7.12/6.68 (((bnd_ndr1_0 & bnd_c8_1 bnd_a217) & bnd_c7_1 bnd_a217) &
% 7.12/6.68 ~ bnd_c1_1 bnd_a217 |
% 7.12/6.68 ~ bnd_c4_0)) &
% 7.12/6.68 ((~ bnd_c5_0 |
% 7.12/6.68 (ALL X84.
% 7.12/6.68 bnd_ndr1_0 -->
% 7.12/6.68 (bnd_c5_1 X84 |
% 7.12/6.68 (ALL X85.
% 7.12/6.68 bnd_ndr1_1 X84 -->
% 7.12/6.68 (bnd_c7_2 X84 X85 | ~ bnd_c5_2 X84 X85) |
% 7.12/6.68 ~ bnd_c6_2 X84 X85)) |
% 7.12/6.68 ~ bnd_c7_1 X84)) |
% 7.12/6.68 bnd_c4_0)) &
% 7.12/6.68 ((((((bnd_ndr1_0 & ~ bnd_c5_1 bnd_a218) & bnd_ndr1_1 bnd_a218) &
% 7.12/6.68 ~ bnd_c5_2 bnd_a218 bnd_a219) &
% 7.12/6.68 bnd_c4_2 bnd_a218 bnd_a219) &
% 7.12/6.68 ~ bnd_c1_1 bnd_a218 |
% 7.12/6.68 (ALL X86.
% 7.12/6.68 bnd_ndr1_0 -->
% 7.12/6.68 ((ALL X87.
% 7.12/6.68 bnd_ndr1_1 X86 -->
% 7.12/6.68 (~ bnd_c1_2 X86 X87 | ~ bnd_c7_2 X86 X87) |
% 7.12/6.68 bnd_c8_2 X86 X87) |
% 7.12/6.68 ((bnd_ndr1_1 X86 & ~ bnd_c3_2 X86 bnd_a220) &
% 7.12/6.68 ~ bnd_c5_2 X86 bnd_a220) &
% 7.12/6.68 bnd_c1_2 X86 bnd_a220) |
% 7.12/6.68 (ALL X88.
% 7.12/6.68 bnd_ndr1_1 X86 -->
% 7.12/6.68 (bnd_c6_2 X86 X88 | ~ bnd_c8_2 X86 X88) |
% 7.12/6.68 ~ bnd_c4_2 X86 X88))) |
% 7.12/6.68 bnd_c4_0)) &
% 7.12/6.68 ((((bnd_ndr1_0 &
% 7.12/6.68 (ALL X89.
% 7.12/6.68 bnd_ndr1_1 bnd_a221 -->
% 7.12/6.68 (~ bnd_c7_2 bnd_a221 X89 | bnd_c2_2 bnd_a221 X89) |
% 7.12/6.68 bnd_c4_2 bnd_a221 X89)) &
% 7.12/6.68 ~ bnd_c1_1 bnd_a221) &
% 7.12/6.68 ~ bnd_c2_1 bnd_a221 |
% 7.12/6.68 ~ bnd_c2_0) |
% 7.12/6.68 ((bnd_ndr1_0 &
% 7.12/6.68 (ALL X90.
% 7.12/6.68 bnd_ndr1_1 bnd_a222 -->
% 7.12/6.68 bnd_c5_2 bnd_a222 X90 | bnd_c2_2 bnd_a222 X90)) &
% 7.12/6.68 ~ bnd_c1_1 bnd_a222) &
% 7.12/6.68 ~ bnd_c6_1 bnd_a222)) &
% 7.12/6.68 ((bnd_c1_0 | bnd_c2_0) | bnd_c5_0)) &
% 7.12/6.68 ((bnd_c1_0 |
% 7.12/6.68 ((bnd_ndr1_0 & ~ bnd_c4_1 bnd_a223) &
% 7.12/6.68 (ALL X91.
% 7.12/6.68 bnd_ndr1_1 bnd_a223 -->
% 7.12/6.68 bnd_c6_2 bnd_a223 X91 | ~ bnd_c4_2 bnd_a223 X91)) &
% 7.12/6.68 (ALL X92.
% 7.12/6.68 bnd_ndr1_1 bnd_a223 -->
% 7.12/6.68 bnd_c7_2 bnd_a223 X92 | bnd_c2_2 bnd_a223 X92)) |
% 7.12/6.68 (ALL X93.
% 7.12/6.68 bnd_ndr1_0 -->
% 7.12/6.68 ((bnd_ndr1_1 X93 & bnd_c3_2 X93 bnd_a224) &
% 7.12/6.68 ~ bnd_c5_2 X93 bnd_a224 |
% 7.12/6.68 bnd_c1_1 X93) |
% 7.12/6.68 ((bnd_ndr1_1 X93 & bnd_c8_2 X93 bnd_a225) &
% 7.12/6.68 bnd_c2_2 X93 bnd_a225) &
% 7.12/6.68 ~ bnd_c4_2 X93 bnd_a225))) &
% 7.12/6.68 ((~ bnd_c1_0 |
% 7.12/6.68 ((bnd_ndr1_0 &
% 7.12/6.68 (ALL X94.
% 7.12/6.68 bnd_ndr1_1 bnd_a226 -->
% 7.12/6.68 (~ bnd_c6_2 bnd_a226 X94 | bnd_c7_2 bnd_a226 X94) |
% 7.12/6.68 ~ bnd_c5_2 bnd_a226 X94)) &
% 7.12/6.68 (ALL X95.
% 7.12/6.68 bnd_ndr1_1 bnd_a226 -->
% 7.12/6.68 (bnd_c5_2 bnd_a226 X95 | ~ bnd_c8_2 bnd_a226 X95) |
% 7.12/6.68 bnd_c6_2 bnd_a226 X95)) &
% 7.12/6.68 ~ bnd_c5_1 bnd_a226) |
% 7.12/6.68 ((((bnd_ndr1_0 &
% 7.12/6.68 (ALL X96.
% 7.12/6.68 bnd_ndr1_1 bnd_a227 -->
% 7.12/6.68 (bnd_c5_2 bnd_a227 X96 | bnd_c2_2 bnd_a227 X96) |
% 7.12/6.68 ~ bnd_c4_2 bnd_a227 X96)) &
% 7.12/6.68 (ALL X97.
% 7.12/6.68 bnd_ndr1_1 bnd_a227 -->
% 7.12/6.68 (bnd_c2_2 bnd_a227 X97 | ~ bnd_c7_2 bnd_a227 X97) |
% 7.12/6.68 ~ bnd_c4_2 bnd_a227 X97)) &
% 7.12/6.68 bnd_ndr1_1 bnd_a227) &
% 7.12/6.68 bnd_c7_2 bnd_a227 bnd_a228) &
% 7.12/6.68 bnd_c6_2 bnd_a227 bnd_a228)) &
% 7.12/6.68 (((bnd_ndr1_0 & bnd_c1_1 bnd_a229) &
% 7.12/6.68 (ALL X98.
% 7.12/6.68 bnd_ndr1_1 bnd_a229 -->
% 7.12/6.68 (bnd_c2_2 bnd_a229 X98 | bnd_c1_2 bnd_a229 X98) |
% 7.12/6.68 bnd_c8_2 bnd_a229 X98)) &
% 7.12/6.68 (ALL X99.
% 7.12/6.68 bnd_ndr1_1 bnd_a229 -->
% 7.12/6.68 (~ bnd_c4_2 bnd_a229 X99 | bnd_c3_2 bnd_a229 X99) |
% 7.12/6.68 bnd_c1_2 bnd_a229 X99) |
% 7.12/6.68 ~ bnd_c2_0)) &
% 7.12/6.68 ((bnd_c8_0 |
% 7.12/6.68 (ALL X100.
% 7.12/6.68 bnd_ndr1_0 -->
% 7.12/6.68 ((ALL X101.
% 7.12/6.68 bnd_ndr1_1 X100 -->
% 7.12/6.68 (bnd_c7_2 X100 X101 | ~ bnd_c4_2 X100 X101) |
% 7.12/6.68 ~ bnd_c6_2 X100 X101) |
% 7.12/6.68 ((bnd_ndr1_1 X100 & ~ bnd_c8_2 X100 bnd_a230) &
% 7.12/6.68 bnd_c7_2 X100 bnd_a230) &
% 7.12/6.68 ~ bnd_c6_2 X100 bnd_a230) |
% 7.12/6.68 bnd_c7_1 X100)) |
% 7.12/6.68 ~ bnd_c1_0)) &
% 7.12/6.68 (((((((bnd_ndr1_0 & ~ bnd_c8_1 bnd_a231) & bnd_ndr1_1 bnd_a231) &
% 7.12/6.68 bnd_c4_2 bnd_a231 bnd_a232) &
% 7.12/6.68 bnd_c6_2 bnd_a231 bnd_a232) &
% 7.12/6.68 bnd_c5_2 bnd_a231 bnd_a232) &
% 7.12/6.68 bnd_c4_1 bnd_a231 |
% 7.12/6.68 (ALL X102.
% 7.12/6.68 bnd_ndr1_0 -->
% 7.12/6.68 ((ALL X103.
% 7.12/6.68 bnd_ndr1_1 X102 --> ~ bnd_c6_2 X102 X103 | bnd_c3_2 X102 X103) |
% 7.12/6.68 ~ bnd_c3_1 X102) |
% 7.12/6.68 ~ bnd_c5_1 X102)) |
% 7.12/6.68 (ALL X104.
% 7.12/6.68 bnd_ndr1_0 -->
% 7.12/6.68 (~ bnd_c1_1 X104 | bnd_c2_1 X104) |
% 7.12/6.68 (ALL X105.
% 7.12/6.68 bnd_ndr1_1 X104 -->
% 7.12/6.68 (~ bnd_c7_2 X104 X105 | bnd_c1_2 X104 X105) |
% 7.12/6.68 ~ bnd_c4_2 X104 X105)))) &
% 7.12/6.68 ((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a233) & bnd_c6_2 bnd_a233 bnd_a234) &
% 7.12/6.68 bnd_c3_2 bnd_a233 bnd_a234) &
% 7.12/6.68 bnd_c1_2 bnd_a233 bnd_a234) &
% 7.12/6.68 (ALL X106.
% 7.12/6.68 bnd_ndr1_1 bnd_a233 -->
% 7.12/6.68 ~ bnd_c4_2 bnd_a233 X106 | ~ bnd_c3_2 bnd_a233 X106)) &
% 7.12/6.68 (ALL X107.
% 7.12/6.68 bnd_ndr1_1 bnd_a233 -->
% 7.12/6.68 bnd_c6_2 bnd_a233 X107 | ~ bnd_c8_2 bnd_a233 X107) |
% 7.12/6.68 ((bnd_ndr1_0 & ~ bnd_c1_1 bnd_a235) & ~ bnd_c3_1 bnd_a235) &
% 7.12/6.68 (ALL X108.
% 7.12/6.68 bnd_ndr1_1 bnd_a235 -->
% 7.12/6.68 ~ bnd_c4_2 bnd_a235 X108 | bnd_c8_2 bnd_a235 X108))) &
% 7.12/6.68 ((~ bnd_c7_0 |
% 7.12/6.68 (ALL X109.
% 7.12/6.68 bnd_ndr1_0 -->
% 7.12/6.68 (~ bnd_c6_1 X109 |
% 7.12/6.68 ((bnd_ndr1_1 X109 & bnd_c5_2 X109 bnd_a236) &
% 7.12/6.68 ~ bnd_c6_2 X109 bnd_a236) &
% 7.12/6.68 ~ bnd_c4_2 X109 bnd_a236) |
% 7.12/6.68 ~ bnd_c8_1 X109)) |
% 7.12/6.68 bnd_c1_0)) &
% 7.12/6.68 (((((((bnd_ndr1_0 & bnd_c1_1 bnd_a237) &
% 7.12/6.68 bnd_ndr1_1 bnd_a237) &
% 7.12/6.68 bnd_c2_2 bnd_a237 bnd_a238) &
% 7.12/6.68 ~ bnd_c7_2 bnd_a237 bnd_a238) &
% 7.12/6.68 ~ bnd_c1_2 bnd_a237 bnd_a238) &
% 7.12/6.68 ~ bnd_c7_1 bnd_a237 |
% 7.12/6.68 (ALL X110.
% 7.12/6.68 bnd_ndr1_0 -->
% 7.12/6.68 (((bnd_ndr1_1 X110 & ~ bnd_c5_2 X110 bnd_a239) &
% 7.12/6.68 bnd_c7_2 X110 bnd_a239) &
% 7.12/6.68 bnd_c8_2 X110 bnd_a239 |
% 7.12/6.68 (ALL X111.
% 7.12/6.68 bnd_ndr1_1 X110 -->
% 7.12/6.68 (~ bnd_c5_2 X110 X111 | bnd_c8_2 X110 X111) |
% 7.12/6.68 bnd_c7_2 X110 X111)) |
% 7.12/6.68 (bnd_ndr1_1 X110 & ~ bnd_c1_2 X110 bnd_a240) &
% 7.12/6.68 bnd_c7_2 X110 bnd_a240)) |
% 7.12/6.68 bnd_c6_0)) &
% 7.12/6.68 ((((((((((bnd_ndr1_0 &
% 7.12/6.68 bnd_ndr1_1 bnd_a241) &
% 7.12/6.68 ~ bnd_c1_2 bnd_a241 bnd_a242) &
% 7.12/6.68 ~ bnd_c7_2 bnd_a241 bnd_a242) &
% 7.12/6.68 ~ bnd_c4_2 bnd_a241 bnd_a242) &
% 7.12/6.68 (ALL X112.
% 7.12/6.68 bnd_ndr1_1 bnd_a241 -->
% 7.12/6.68 (bnd_c6_2 bnd_a241 X112 | ~ bnd_c4_2 bnd_a241 X112) |
% 7.12/6.68 bnd_c5_2 bnd_a241 X112)) &
% 7.12/6.68 bnd_ndr1_1 bnd_a241) &
% 7.12/6.68 ~ bnd_c6_2 bnd_a241 bnd_a243) &
% 7.12/6.68 bnd_c4_2 bnd_a241 bnd_a243) &
% 7.12/6.68 bnd_c5_2 bnd_a241 bnd_a243 |
% 7.12/6.68 ((((((bnd_ndr1_0 &
% 7.12/6.68 bnd_ndr1_1 bnd_a244) &
% 7.12/6.68 bnd_c4_2 bnd_a244 bnd_a245) &
% 7.12/6.68 ~ bnd_c2_2 bnd_a244 bnd_a245) &
% 7.12/6.68 bnd_ndr1_1 bnd_a244) &
% 7.12/6.68 ~ bnd_c3_2 bnd_a244 bnd_a246) &
% 7.12/6.68 bnd_c8_2 bnd_a244 bnd_a246) &
% 7.12/6.68 ~ bnd_c7_2 bnd_a244 bnd_a246) |
% 7.12/6.68 ~ bnd_c6_0)) &
% 7.12/6.68 (((ALL X113.
% 7.12/6.68 bnd_ndr1_0 -->
% 7.12/6.68 (bnd_c2_1 X113 | bnd_c3_1 X113) |
% 7.12/6.68 (ALL X114.
% 7.12/6.68 bnd_ndr1_1 X113 -->
% 7.12/6.68 (~ bnd_c3_2 X113 X114 | ~ bnd_c6_2 X113 X114) |
% 7.12/6.68 ~ bnd_c8_2 X113 X114)) |
% 7.12/6.68 ~ bnd_c4_0) |
% 7.12/6.68 (ALL X115.
% 7.12/6.68 bnd_ndr1_0 -->
% 7.12/6.68 (bnd_c4_1 X115 | bnd_c3_1 X115) |
% 7.12/6.68 (ALL X116.
% 7.12/6.68 bnd_ndr1_1 X115 -->
% 7.12/6.68 (bnd_c5_2 X115 X116 | bnd_c3_2 X115 X116) | ~ bnd_c8_2 X115 X116)))) &
% 7.12/6.68 ((bnd_c4_0 | ~ bnd_c5_0) | bnd_c3_0)) &
% 7.12/6.68 ((bnd_c8_0 |
% 7.12/6.68 (ALL X117.
% 7.12/6.68 bnd_ndr1_0 -->
% 7.12/6.68 ((bnd_ndr1_1 X117 & ~ bnd_c5_2 X117 bnd_a247) & ~ bnd_c1_2 X117 bnd_a247 |
% 7.12/6.68 bnd_c1_1 X117) |
% 7.12/6.68 ~ bnd_c7_1 X117)) |
% 7.12/6.68 (ALL X118.
% 7.12/6.68 bnd_ndr1_0 -->
% 7.12/6.68 (bnd_c2_1 X118 | ~ bnd_c7_1 X118) |
% 7.12/6.68 ~ bnd_c5_1 X118))) &
% 7.12/6.68 ((~ bnd_c2_0 |
% 7.12/6.68 (ALL X119.
% 7.12/6.68 bnd_ndr1_0 -->
% 7.12/6.68 (((bnd_ndr1_1 X119 &
% 7.12/6.68 bnd_c3_2 X119 bnd_a248) &
% 7.12/6.68 ~ bnd_c6_2 X119 bnd_a248) &
% 7.12/6.68 bnd_c7_2 X119 bnd_a248 |
% 7.12/6.68 ~ bnd_c8_1 X119) |
% 7.12/6.68 bnd_c2_1 X119)) |
% 7.12/6.68 ((bnd_ndr1_0 & ~ bnd_c1_1 bnd_a249) &
% 7.12/6.68 ~ bnd_c7_1 bnd_a249) &
% 7.12/6.68 (ALL X120.
% 7.12/6.68 bnd_ndr1_1 bnd_a249 -->
% 7.12/6.68 (~ bnd_c4_2 bnd_a249 X120 |
% 7.12/6.68 ~ bnd_c2_2 bnd_a249 X120) |
% 7.12/6.68 bnd_c5_2 bnd_a249 X120))) &
% 7.12/6.68 (((ALL X121.
% 7.12/6.68 bnd_ndr1_0 -->
% 7.12/6.68 (bnd_c3_1 X121 |
% 7.12/6.68 ((bnd_ndr1_1 X121 &
% 7.12/6.68 bnd_c7_2 X121 bnd_a250) &
% 7.12/6.68 bnd_c8_2 X121 bnd_a250) &
% 7.12/6.68 bnd_c5_2 X121 bnd_a250) |
% 7.12/6.68 ((bnd_ndr1_1 X121 &
% 7.12/6.68 ~ bnd_c8_2 X121 bnd_a251) &
% 7.12/6.68 ~ bnd_c2_2 X121 bnd_a251) &
% 7.12/6.68 ~ bnd_c3_2 X121 bnd_a251) |
% 7.12/6.68 bnd_c8_0) |
% 7.12/6.68 ~ bnd_c6_0)) &
% 7.12/6.68 ((((bnd_ndr1_0 & bnd_c1_1 bnd_a252) &
% 7.12/6.68 ~ bnd_c7_1 bnd_a252) &
% 7.12/6.68 (ALL X122.
% 7.12/6.68 bnd_ndr1_1 bnd_a252 -->
% 7.12/6.68 (bnd_c5_2 bnd_a252 X122 |
% 7.12/6.68 ~ bnd_c2_2 bnd_a252 X122) |
% 7.12/6.68 ~ bnd_c4_2 bnd_a252 X122) |
% 7.12/6.68 ~ bnd_c4_0) |
% 7.12/6.68 (ALL X123. bnd_ndr1_0 --> ~ bnd_c8_1 X123))) &
% 7.12/6.68 (((ALL X124.
% 7.12/6.68 bnd_ndr1_0 -->
% 7.12/6.68 bnd_c1_1 X124 | ~ bnd_c3_1 X124) |
% 7.12/6.68 ((bnd_ndr1_0 & ~ bnd_c8_1 bnd_a253) &
% 7.12/6.68 ~ bnd_c7_1 bnd_a253) &
% 7.12/6.68 (ALL X125.
% 7.12/6.68 bnd_ndr1_1 bnd_a253 -->
% 7.12/6.68 (bnd_c2_2 bnd_a253 X125 |
% 7.12/6.68 bnd_c3_2 bnd_a253 X125) |
% 7.12/6.68 bnd_c5_2 bnd_a253 X125)) |
% 7.12/6.68 (ALL X126.
% 7.12/6.68 bnd_ndr1_0 -->
% 7.12/6.68 (((bnd_ndr1_1 X126 &
% 7.12/6.68 ~ bnd_c5_2 X126 bnd_a254) &
% 7.12/6.68 ~ bnd_c6_2 X126 bnd_a254) &
% 7.12/6.68 bnd_c1_2 X126 bnd_a254 |
% 7.12/6.68 bnd_c5_1 X126) |
% 7.12/6.68 ((bnd_ndr1_1 X126 &
% 7.12/6.68 ~ bnd_c3_2 X126 bnd_a255) &
% 7.12/6.68 ~ bnd_c8_2 X126 bnd_a255) &
% 7.12/6.68 bnd_c7_2 X126 bnd_a255))) &
% 7.12/6.68 ((bnd_c4_0 | ~ bnd_c6_0) |
% 7.12/6.68 (ALL X127.
% 7.12/6.68 bnd_ndr1_0 -->
% 7.12/6.68 (bnd_c8_1 X127 | ~ bnd_c6_1 X127) |
% 7.12/6.68 (ALL X128.
% 7.12/6.68 bnd_ndr1_1 X127 -->
% 7.12/6.68 (~ bnd_c1_2 X127 X128 |
% 7.12/6.68 bnd_c4_2 X127 X128) |
% 7.12/6.68 bnd_c6_2 X127 X128)))) &
% 7.12/6.68 ((~ bnd_c1_0 | bnd_c4_0) | ~ bnd_c6_0)) &
% 7.12/6.68 ((((((bnd_ndr1_0 & bnd_c1_1 bnd_a256) &
% 7.12/6.68 (ALL X129.
% 7.12/6.68 bnd_ndr1_1 bnd_a256 -->
% 7.12/6.68 (~ bnd_c3_2 bnd_a256 X129 |
% 7.12/6.68 ~ bnd_c5_2 bnd_a256 X129) |
% 7.12/6.68 ~ bnd_c4_2 bnd_a256 X129)) &
% 7.12/6.68 bnd_ndr1_1 bnd_a256) &
% 7.12/6.68 ~ bnd_c1_2 bnd_a256 bnd_a257) &
% 7.12/6.68 ~ bnd_c7_2 bnd_a256 bnd_a257 |
% 7.12/6.68 (ALL X130.
% 7.12/6.68 bnd_ndr1_0 -->
% 7.12/6.68 (~ bnd_c5_1 X130 | bnd_c1_1 X130) |
% 7.12/6.68 bnd_c3_1 X130)) |
% 7.12/6.68 bnd_c6_0)) &
% 7.12/6.68 ((bnd_c7_0 |
% 7.12/6.68 (ALL X131.
% 7.12/6.68 bnd_ndr1_0 -->
% 7.12/6.68 (~ bnd_c7_1 X131 |
% 7.12/6.68 ((bnd_ndr1_1 X131 &
% 7.12/6.68 ~ bnd_c7_2 X131 bnd_a258) &
% 7.12/6.68 bnd_c3_2 X131 bnd_a258) &
% 7.12/6.68 bnd_c4_2 X131 bnd_a258) |
% 7.12/6.68 bnd_c1_1 X131)) |
% 7.12/6.68 ((bnd_ndr1_0 &
% 7.12/6.68 (ALL X132.
% 7.12/6.68 bnd_ndr1_1 bnd_a259 -->
% 7.12/6.68 (bnd_c1_2 bnd_a259 X132 |
% 7.12/6.68 bnd_c8_2 bnd_a259 X132) |
% 7.12/6.68 bnd_c3_2 bnd_a259 X132)) &
% 7.12/6.68 bnd_c6_1 bnd_a259) &
% 7.12/6.68 ~ bnd_c7_1 bnd_a259)) &
% 7.12/6.68 ((bnd_c6_0 | bnd_c5_0) |
% 7.12/6.68 (ALL X133.
% 7.12/6.68 bnd_ndr1_0 -->
% 7.12/6.68 ((ALL X134.
% 7.12/6.68 bnd_ndr1_1 X133 -->
% 7.12/6.68 (~ bnd_c7_2 X133 X134 |
% 7.12/6.68 bnd_c8_2 X133 X134) |
% 7.12/6.68 bnd_c1_2 X133 X134) |
% 7.12/6.68 ((bnd_ndr1_1 X133 & ~ bnd_c7_2 X133 bnd_a260) &
% 7.12/6.68 ~ bnd_c2_2 X133 bnd_a260) &
% 7.12/6.68 ~ bnd_c1_2 X133 bnd_a260) |
% 7.12/6.68 ((bnd_ndr1_1 X133 & ~ bnd_c6_2 X133 bnd_a261) &
% 7.12/6.68 bnd_c2_2 X133 bnd_a261) &
% 7.12/6.68 bnd_c1_2 X133 bnd_a261))) &
% 7.12/6.68 (bnd_c1_0 | bnd_c4_0)) &
% 7.12/6.68 (((ALL X135.
% 7.12/6.68 bnd_ndr1_0 -->
% 7.12/6.68 (bnd_c2_1 X135 |
% 7.12/6.68 ((bnd_ndr1_1 X135 & bnd_c4_2 X135 bnd_a262) &
% 7.12/6.68 ~ bnd_c2_2 X135 bnd_a262) &
% 7.12/6.68 bnd_c1_2 X135 bnd_a262) |
% 7.12/6.68 (ALL X136.
% 7.12/6.68 bnd_ndr1_1 X135 -->
% 7.12/6.68 (bnd_c5_2 X135 X136 | bnd_c1_2 X135 X136) |
% 7.12/6.68 ~ bnd_c3_2 X135 X136)) |
% 7.12/6.68 ~ bnd_c6_0) |
% 7.12/6.68 bnd_c1_0)) &
% 7.12/6.68 (((ALL X137.
% 7.12/6.68 bnd_ndr1_0 -->
% 7.12/6.68 bnd_c3_1 X137 |
% 7.12/6.68 (ALL X138.
% 7.12/6.68 bnd_ndr1_1 X137 -->
% 7.12/6.68 (~ bnd_c3_2 X137 X138 |
% 7.12/6.68 ~ bnd_c2_2 X137 X138) |
% 7.12/6.68 ~ bnd_c4_2 X137 X138)) |
% 7.12/6.68 bnd_c1_0) |
% 7.12/6.68 ~ bnd_c7_0)) &
% 7.12/6.68 ((~ bnd_c7_0 |
% 7.12/6.68 (ALL X139.
% 7.12/6.68 bnd_ndr1_0 -->
% 7.12/6.68 ((ALL X140.
% 7.12/6.68 bnd_ndr1_1 X139 -->
% 7.12/6.68 (~ bnd_c8_2 X139 X140 | bnd_c3_2 X139 X140) |
% 7.12/6.68 ~ bnd_c5_2 X139 X140) |
% 7.12/6.68 ~ bnd_c7_1 X139) |
% 7.12/6.68 bnd_c2_1 X139)) |
% 7.12/6.68 bnd_c5_0)) &
% 7.12/6.68 ((~ bnd_c5_0 |
% 7.12/6.68 (ALL X141.
% 7.12/6.68 bnd_ndr1_0 -->
% 7.12/6.68 (((bnd_ndr1_1 X141 & ~ bnd_c5_2 X141 bnd_a263) &
% 7.12/6.68 ~ bnd_c7_2 X141 bnd_a263) &
% 7.12/6.68 bnd_c4_2 X141 bnd_a263 |
% 7.12/6.68 ~ bnd_c6_1 X141) |
% 7.12/6.68 ((bnd_ndr1_1 X141 & bnd_c5_2 X141 bnd_a264) &
% 7.12/6.68 bnd_c1_2 X141 bnd_a264) &
% 7.12/6.68 bnd_c7_2 X141 bnd_a264)) |
% 7.12/6.68 ~ bnd_c3_0)) &
% 7.12/6.68 (((ALL X142.
% 7.12/6.68 bnd_ndr1_0 --> bnd_c4_1 X142 | ~ bnd_c5_1 X142) |
% 7.12/6.68 bnd_c2_0) |
% 7.12/6.68 (ALL X143.
% 7.12/6.68 bnd_ndr1_0 --> ~ bnd_c2_1 X143 | ~ bnd_c7_1 X143))) &
% 7.12/6.68 ((bnd_c7_0 |
% 7.12/6.68 (((((bnd_ndr1_0 & ~ bnd_c6_1 bnd_a265) &
% 7.12/6.68 (ALL X144.
% 7.12/6.68 bnd_ndr1_1 bnd_a265 -->
% 7.12/6.68 ~ bnd_c4_2 bnd_a265 X144 |
% 7.12/6.68 bnd_c7_2 bnd_a265 X144)) &
% 7.12/6.68 bnd_ndr1_1 bnd_a265) &
% 7.12/6.68 bnd_c4_2 bnd_a265 bnd_a266) &
% 7.12/6.68 bnd_c2_2 bnd_a265 bnd_a266) &
% 7.12/6.68 ~ bnd_c8_2 bnd_a265 bnd_a266) |
% 7.12/6.68 bnd_ndr1_0 &
% 7.12/6.68 (ALL X145.
% 7.12/6.68 bnd_ndr1_1 bnd_a267 -->
% 7.12/6.68 bnd_c6_2 bnd_a267 X145 | bnd_c3_2 bnd_a267 X145))) &
% 7.12/6.68 ((bnd_c4_0 |
% 7.12/6.68 ((((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a268) &
% 7.12/6.68 ~ bnd_c6_2 bnd_a268 bnd_a269) &
% 7.12/6.68 bnd_c2_2 bnd_a268 bnd_a269) &
% 7.12/6.68 bnd_c5_2 bnd_a268 bnd_a269) &
% 7.12/6.68 bnd_ndr1_1 bnd_a268) &
% 7.12/6.68 bnd_c6_2 bnd_a268 bnd_a270) &
% 7.12/6.68 bnd_c8_2 bnd_a268 bnd_a270) &
% 7.12/6.68 bnd_c1_2 bnd_a268 bnd_a270) &
% 7.12/6.68 ~ bnd_c7_1 bnd_a268) |
% 7.12/6.68 bnd_c5_0)) &
% 7.12/6.68 ((((((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a271) &
% 7.12/6.68 ~ bnd_c7_2 bnd_a271 bnd_a272) &
% 7.12/6.68 bnd_c2_2 bnd_a271 bnd_a272) &
% 7.12/6.68 bnd_c1_2 bnd_a271 bnd_a272) &
% 7.12/6.68 bnd_c5_1 bnd_a271) &
% 7.12/6.68 bnd_ndr1_1 bnd_a271) &
% 7.12/6.68 ~ bnd_c3_2 bnd_a271 bnd_a273) &
% 7.12/6.68 ~ bnd_c4_2 bnd_a271 bnd_a273) &
% 7.12/6.68 bnd_c1_2 bnd_a271 bnd_a273 |
% 7.12/6.68 ((bnd_ndr1_0 &
% 7.12/6.68 (ALL X146.
% 7.12/6.68 bnd_ndr1_1 bnd_a274 -->
% 7.12/6.68 (~ bnd_c7_2 bnd_a274 X146 |
% 7.12/6.68 ~ bnd_c4_2 bnd_a274 X146) |
% 7.12/6.68 bnd_c5_2 bnd_a274 X146)) &
% 7.12/6.68 (ALL X147.
% 7.12/6.68 bnd_ndr1_1 bnd_a274 -->
% 7.12/6.68 (~ bnd_c1_2 bnd_a274 X147 | ~ bnd_c5_2 bnd_a274 X147) |
% 7.12/6.68 ~ bnd_c6_2 bnd_a274 X147)) &
% 7.12/6.68 ~ bnd_c7_1 bnd_a274) |
% 7.12/6.68 (ALL X148.
% 7.12/6.68 bnd_ndr1_0 -->
% 7.12/6.68 ~ bnd_c1_1 X148 |
% 7.12/6.68 (ALL X149.
% 7.12/6.68 bnd_ndr1_1 X148 -->
% 7.12/6.68 bnd_c5_2 X148 X149 | ~ bnd_c6_2 X148 X149)))) &
% 7.12/6.68 (((((((bnd_ndr1_0 &
% 7.12/6.68 (ALL X150.
% 7.12/6.68 bnd_ndr1_1 bnd_a275 -->
% 7.12/6.68 (~ bnd_c7_2 bnd_a275 X150 |
% 7.12/6.68 bnd_c5_2 bnd_a275 X150) |
% 7.12/6.68 ~ bnd_c2_2 bnd_a275 X150)) &
% 7.12/6.68 bnd_ndr1_1 bnd_a275) &
% 7.12/6.68 bnd_c2_2 bnd_a275 bnd_a276) &
% 7.12/6.68 bnd_c7_2 bnd_a275 bnd_a276) &
% 7.12/6.68 ~ bnd_c3_2 bnd_a275 bnd_a276) &
% 7.12/6.68 ~ bnd_c1_1 bnd_a275 |
% 7.12/6.68 bnd_c4_0) |
% 7.12/6.68 ((bnd_ndr1_0 &
% 7.12/6.68 (ALL X151.
% 7.12/6.68 bnd_ndr1_1 bnd_a277 -->
% 7.12/6.68 (~ bnd_c8_2 bnd_a277 X151 | bnd_c6_2 bnd_a277 X151) |
% 7.12/6.68 bnd_c4_2 bnd_a277 X151)) &
% 7.12/6.68 (ALL X152.
% 7.12/6.68 bnd_ndr1_1 bnd_a277 -->
% 7.12/6.68 (~ bnd_c1_2 bnd_a277 X152 | ~ bnd_c2_2 bnd_a277 X152) |
% 7.12/6.68 bnd_c7_2 bnd_a277 X152)) &
% 7.12/6.68 (ALL X153.
% 7.12/6.68 bnd_ndr1_1 bnd_a277 -->
% 7.12/6.68 ~ bnd_c6_2 bnd_a277 X153 | ~ bnd_c7_2 bnd_a277 X153))) &
% 7.12/6.68 (((ALL X154.
% 7.12/6.68 bnd_ndr1_0 -->
% 7.12/6.68 (bnd_c1_1 X154 |
% 7.12/6.68 (bnd_ndr1_1 X154 & ~ bnd_c3_2 X154 bnd_a278) &
% 7.12/6.68 bnd_c5_2 X154 bnd_a278) |
% 7.12/6.68 ~ bnd_c4_1 X154) |
% 7.12/6.68 bnd_c8_0) |
% 7.12/6.68 bnd_c7_0)) &
% 7.12/6.68 (((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a279) &
% 7.12/6.68 ~ bnd_c4_2 bnd_a279 bnd_a280) &
% 7.12/6.68 ~ bnd_c1_2 bnd_a279 bnd_a280) &
% 7.12/6.68 bnd_c8_2 bnd_a279 bnd_a280) &
% 7.12/6.68 (ALL X155.
% 7.12/6.68 bnd_ndr1_1 bnd_a279 -->
% 7.12/6.68 (bnd_c6_2 bnd_a279 X155 | ~ bnd_c5_2 bnd_a279 X155) |
% 7.12/6.68 bnd_c3_2 bnd_a279 X155)) &
% 7.12/6.68 bnd_c2_1 bnd_a279 |
% 7.12/6.68 ~ bnd_c1_0) |
% 7.12/6.68 ((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a281) &
% 7.12/6.68 bnd_c7_2 bnd_a281 bnd_a282) &
% 7.12/6.68 bnd_c8_2 bnd_a281 bnd_a282) &
% 7.12/6.68 bnd_c2_2 bnd_a281 bnd_a282) &
% 7.12/6.68 bnd_ndr1_1 bnd_a281) &
% 7.12/6.68 bnd_c8_2 bnd_a281 bnd_a283) &
% 7.12/6.68 ~ bnd_c1_2 bnd_a281 bnd_a283)) &
% 7.12/6.68 (((ALL X156.
% 7.12/6.68 bnd_ndr1_0 -->
% 7.12/6.68 (((bnd_ndr1_1 X156 & bnd_c3_2 X156 bnd_a284) &
% 7.12/6.68 bnd_c1_2 X156 bnd_a284) &
% 7.12/6.68 bnd_c5_2 X156 bnd_a284 |
% 7.12/6.68 ((bnd_ndr1_1 X156 & ~ bnd_c8_2 X156 bnd_a285) &
% 7.12/6.68 bnd_c3_2 X156 bnd_a285) &
% 7.12/6.68 ~ bnd_c7_2 X156 bnd_a285) |
% 7.12/6.68 (bnd_ndr1_1 X156 & ~ bnd_c7_2 X156 bnd_a286) &
% 7.12/6.68 ~ bnd_c1_2 X156 bnd_a286) |
% 7.12/6.68 bnd_c6_0) |
% 7.12/6.68 (ALL X157.
% 7.12/6.68 bnd_ndr1_0 -->
% 7.12/6.68 (bnd_c1_1 X157 | ~ bnd_c8_1 X157) | bnd_c6_1 X157))) &
% 7.12/6.68 ((~ bnd_c3_0 | bnd_c4_0) |
% 7.12/6.68 (ALL X158.
% 7.12/6.68 bnd_ndr1_0 -->
% 7.12/6.68 (~ bnd_c8_1 X158 |
% 7.12/6.68 (ALL X159.
% 7.12/6.68 bnd_ndr1_1 X158 -->
% 7.12/6.68 (bnd_c8_2 X158 X159 | ~ bnd_c7_2 X158 X159) |
% 7.12/6.68 ~ bnd_c6_2 X158 X159)) |
% 7.12/6.68 bnd_c4_1 X158))) &
% 7.12/6.68 ((bnd_c2_0 | bnd_c8_0) | ~ bnd_c4_0)) &
% 7.12/6.68 ((bnd_c3_0 | bnd_c5_0) |
% 7.12/6.68 ((bnd_ndr1_0 & bnd_c3_1 bnd_a287) & ~ bnd_c5_1 bnd_a287) &
% 7.12/6.68 bnd_c8_1 bnd_a287)) &
% 7.12/6.68 (((ALL X160.
% 7.12/6.68 bnd_ndr1_0 -->
% 7.12/6.68 (bnd_c6_1 X160 |
% 7.12/6.68 (ALL X161.
% 7.12/6.68 bnd_ndr1_1 X160 -->
% 7.12/6.68 (~ bnd_c3_2 X160 X161 | bnd_c7_2 X160 X161) |
% 7.12/6.68 bnd_c5_2 X160 X161)) |
% 7.12/6.68 ~ bnd_c2_1 X160) |
% 7.12/6.68 (((((bnd_ndr1_0 & ~ bnd_c8_1 bnd_a288) & bnd_ndr1_1 bnd_a288) &
% 7.12/6.68 ~ bnd_c8_2 bnd_a288 bnd_a289) &
% 7.12/6.68 ~ bnd_c4_2 bnd_a288 bnd_a289) &
% 7.12/6.68 ~ bnd_c5_2 bnd_a288 bnd_a289) &
% 7.12/6.68 (ALL X162.
% 7.12/6.68 bnd_ndr1_1 bnd_a288 -->
% 7.12/6.68 (~ bnd_c8_2 bnd_a288 X162 | ~ bnd_c5_2 bnd_a288 X162) |
% 7.12/6.68 ~ bnd_c4_2 bnd_a288 X162)) |
% 7.12/6.68 (ALL X163.
% 7.12/6.68 bnd_ndr1_0 -->
% 7.12/6.68 (((bnd_ndr1_1 X163 & ~ bnd_c8_2 X163 bnd_a290) &
% 7.12/6.68 ~ bnd_c3_2 X163 bnd_a290) &
% 7.12/6.68 ~ bnd_c1_2 X163 bnd_a290 |
% 7.12/6.68 (ALL X164.
% 7.12/6.68 bnd_ndr1_1 X163 -->
% 7.12/6.68 (bnd_c7_2 X163 X164 | bnd_c5_2 X163 X164) |
% 7.12/6.68 bnd_c3_2 X163 X164)) |
% 7.12/6.68 ((bnd_ndr1_1 X163 & bnd_c7_2 X163 bnd_a291) &
% 7.12/6.68 bnd_c2_2 X163 bnd_a291) &
% 7.12/6.68 ~ bnd_c4_2 X163 bnd_a291))) &
% 7.12/6.68 ((~ bnd_c2_0 |
% 7.12/6.68 (ALL X165.
% 7.12/6.68 bnd_ndr1_0 -->
% 7.12/6.68 (((bnd_ndr1_1 X165 & ~ bnd_c5_2 X165 bnd_a292) &
% 7.12/6.68 bnd_c7_2 X165 bnd_a292) &
% 7.12/6.68 bnd_c8_2 X165 bnd_a292 |
% 7.12/6.68 ((bnd_ndr1_1 X165 & bnd_c4_2 X165 bnd_a293) &
% 7.12/6.68 ~ bnd_c3_2 X165 bnd_a293) &
% 7.12/6.68 ~ bnd_c1_2 X165 bnd_a293) |
% 7.12/6.68 bnd_c4_1 X165)) |
% 7.12/6.68 ~ bnd_c4_0)) &
% 7.12/6.68 (bnd_c1_0 |
% 7.12/6.68 (((((bnd_ndr1_0 & bnd_c2_1 bnd_a294) & ~ bnd_c3_1 bnd_a294) &
% 7.12/6.68 bnd_ndr1_1 bnd_a294) &
% 7.12/6.68 ~ bnd_c2_2 bnd_a294 bnd_a295) &
% 7.12/6.68 ~ bnd_c8_2 bnd_a294 bnd_a295) &
% 7.12/6.68 bnd_c7_2 bnd_a294 bnd_a295)) &
% 7.12/6.68 ((bnd_c6_0 |
% 7.12/6.68 (((((bnd_ndr1_0 &
% 7.12/6.68 (ALL X166.
% 7.12/6.68 bnd_ndr1_1 bnd_a296 -->
% 7.12/6.68 (bnd_c2_2 bnd_a296 X166 | ~ bnd_c6_2 bnd_a296 X166) |
% 7.12/6.68 ~ bnd_c7_2 bnd_a296 X166)) &
% 7.12/6.68 bnd_ndr1_1 bnd_a296) &
% 7.12/6.68 ~ bnd_c7_2 bnd_a296 bnd_a297) &
% 7.12/6.68 ~ bnd_c2_2 bnd_a296 bnd_a297) &
% 7.12/6.68 bnd_c5_2 bnd_a296 bnd_a297) &
% 7.12/6.68 ~ bnd_c7_1 bnd_a296) |
% 7.12/6.68 (ALL X167.
% 7.12/6.68 bnd_ndr1_0 --> (bnd_c3_1 X167 | bnd_c4_1 X167) | bnd_c5_1 X167)))
% 16.43/15.96 Unfolded term: ~ (((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((~ bnd_c3_0 |
% 16.43/15.96 (ALL U.
% 16.43/15.96 bnd_ndr1_0 -->
% 16.43/15.96 ((ALL V.
% 16.43/15.96 bnd_ndr1_1 U -->
% 16.43/15.96 bnd_c3_2 U V | bnd_c4_2 U V) |
% 16.43/15.96 ((bnd_ndr1_1 U & ~ bnd_c7_2 U bnd_a147) &
% 16.43/15.96 ~ bnd_c3_2 U bnd_a147) &
% 16.43/15.96 bnd_c5_2 U bnd_a147) |
% 16.43/15.96 (ALL W.
% 16.43/15.96 bnd_ndr1_1 U -->
% 16.43/15.96 (~ bnd_c5_2 U W | bnd_c4_2 U W) |
% 16.43/15.96 ~ bnd_c7_2 U W))) &
% 16.43/15.96 ((~ bnd_c8_0 | ~ bnd_c1_0) | ~ bnd_c2_0)) &
% 16.43/15.96 (((((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a148) &
% 16.43/15.96 ~ bnd_c1_2 bnd_a148 bnd_a149) &
% 16.43/15.96 bnd_c7_2 bnd_a148 bnd_a149) &
% 16.43/15.96 bnd_c2_2 bnd_a148 bnd_a149) &
% 16.43/15.96 (ALL X.
% 16.43/15.96 bnd_ndr1_1 bnd_a148 -->
% 16.43/15.96 (bnd_c5_2 bnd_a148 X | ~ bnd_c8_2 bnd_a148 X) |
% 16.43/15.96 ~ bnd_c4_2 bnd_a148 X)) &
% 16.43/15.96 bnd_ndr1_1 bnd_a148) &
% 16.43/15.96 ~ bnd_c1_2 bnd_a148 bnd_a150) &
% 16.43/15.96 ~ bnd_c8_2 bnd_a148 bnd_a150 |
% 16.43/15.96 ~ bnd_c8_0) |
% 16.43/15.96 bnd_c7_0)) &
% 16.43/15.96 (((ALL Y.
% 16.43/15.96 bnd_ndr1_0 -->
% 16.43/15.96 (~ bnd_c6_1 Y |
% 16.43/15.96 (ALL Z.
% 16.43/15.96 bnd_ndr1_1 Y -->
% 16.43/15.96 (~ bnd_c5_2 Y Z | bnd_c3_2 Y Z) |
% 16.43/15.96 bnd_c4_2 Y Z)) |
% 16.43/15.96 ~ bnd_c8_1 Y) |
% 16.43/15.96 bnd_c3_0) |
% 16.43/15.96 bnd_c8_0)) &
% 16.43/15.96 ((~ bnd_c4_0 |
% 16.43/15.96 (ALL X1.
% 16.43/15.96 bnd_ndr1_0 -->
% 16.43/15.96 (bnd_c8_1 X1 | bnd_c6_1 X1) | bnd_c2_1 X1)) |
% 16.43/15.96 (ALL X2.
% 16.43/15.96 bnd_ndr1_0 -->
% 16.43/15.96 (~ bnd_c3_1 X2 |
% 16.43/15.96 ((bnd_ndr1_1 X2 & ~ bnd_c8_2 X2 bnd_a151) &
% 16.43/15.96 ~ bnd_c1_2 X2 bnd_a151) &
% 16.43/15.96 ~ bnd_c5_2 X2 bnd_a151) |
% 16.43/15.96 bnd_c5_1 X2))) &
% 16.43/15.96 (~ bnd_c7_0 |
% 16.43/15.96 (ALL X3.
% 16.43/15.96 bnd_ndr1_0 -->
% 16.43/15.96 ((ALL X4.
% 16.43/15.96 bnd_ndr1_1 X3 -->
% 16.43/15.96 (~ bnd_c3_2 X3 X4 | bnd_c7_2 X3 X4) |
% 16.43/15.96 ~ bnd_c5_2 X3 X4) |
% 16.43/15.96 ((bnd_ndr1_1 X3 & ~ bnd_c4_2 X3 bnd_a152) &
% 16.43/15.96 ~ bnd_c3_2 X3 bnd_a152) &
% 16.43/15.96 bnd_c7_2 X3 bnd_a152) |
% 16.43/15.96 ~ bnd_c5_1 X3))) &
% 16.43/15.96 ((~ bnd_c4_0 |
% 16.43/15.96 ((bnd_ndr1_0 & ~ bnd_c4_1 bnd_a153) &
% 16.43/15.96 ~ bnd_c1_1 bnd_a153) &
% 16.43/15.96 (ALL X5.
% 16.43/15.96 bnd_ndr1_1 bnd_a153 -->
% 16.43/15.96 (bnd_c8_2 bnd_a153 X5 | ~ bnd_c3_2 bnd_a153 X5) |
% 16.43/15.96 bnd_c5_2 bnd_a153 X5)) |
% 16.43/15.96 ~ bnd_c1_0)) &
% 16.43/15.96 ((((bnd_ndr1_0 & bnd_c4_1 bnd_a154) & bnd_c6_1 bnd_a154) &
% 16.43/15.96 bnd_c2_1 bnd_a154 |
% 16.43/15.96 (((((bnd_ndr1_0 &
% 16.43/15.96 (ALL X6.
% 16.43/15.96 bnd_ndr1_1 bnd_a155 -->
% 16.43/15.96 (~ bnd_c4_2 bnd_a155 X6 | ~ bnd_c2_2 bnd_a155 X6) |
% 16.43/15.96 bnd_c3_2 bnd_a155 X6)) &
% 16.43/15.96 ~ bnd_c7_1 bnd_a155) &
% 16.43/15.96 bnd_ndr1_1 bnd_a155) &
% 16.43/15.96 bnd_c2_2 bnd_a155 bnd_a156) &
% 16.43/15.96 bnd_c7_2 bnd_a155 bnd_a156) &
% 16.43/15.96 ~ bnd_c5_2 bnd_a155 bnd_a156) |
% 16.43/15.96 (bnd_ndr1_0 & ~ bnd_c4_1 bnd_a157) & bnd_c5_1 bnd_a157)) &
% 16.43/15.96 ((((bnd_ndr1_0 &
% 16.43/15.96 (ALL X7.
% 16.43/15.96 bnd_ndr1_1 bnd_a158 -->
% 16.43/15.96 (bnd_c4_2 bnd_a158 X7 | ~ bnd_c1_2 bnd_a158 X7) |
% 16.43/15.96 bnd_c8_2 bnd_a158 X7)) &
% 16.43/15.96 ~ bnd_c4_1 bnd_a158) &
% 16.43/15.96 bnd_c1_1 bnd_a158 |
% 16.43/15.96 bnd_c1_0) |
% 16.43/15.96 bnd_c5_0)) &
% 16.43/15.96 (((ALL X8.
% 16.43/15.96 bnd_ndr1_0 -->
% 16.43/15.96 (~ bnd_c3_1 X8 |
% 16.43/15.96 (ALL X9.
% 16.43/15.96 bnd_ndr1_1 X8 -->
% 16.43/15.96 (~ bnd_c4_2 X8 X9 | bnd_c8_2 X8 X9) |
% 16.43/15.96 bnd_c2_2 X8 X9)) |
% 16.43/15.96 bnd_c2_1 X8) |
% 16.43/15.96 ((bnd_ndr1_0 &
% 16.43/15.96 (ALL X10.
% 16.43/15.96 bnd_ndr1_1 bnd_a159 -->
% 16.43/15.96 (bnd_c2_2 bnd_a159 X10 | ~ bnd_c4_2 bnd_a159 X10) |
% 16.43/15.96 ~ bnd_c8_2 bnd_a159 X10)) &
% 16.43/15.96 ~ bnd_c4_1 bnd_a159) &
% 16.43/15.96 bnd_c2_1 bnd_a159) |
% 16.43/15.96 ~ bnd_c2_0)) &
% 16.43/15.96 (((((((bnd_ndr1_0 &
% 16.43/15.96 (ALL X11.
% 16.43/15.96 bnd_ndr1_1 bnd_a160 --> ~ bnd_c6_2 bnd_a160 X11)) &
% 16.43/15.96 ~ bnd_c6_1 bnd_a160) &
% 16.43/15.96 bnd_ndr1_1 bnd_a160) &
% 16.43/15.96 bnd_c8_2 bnd_a160 bnd_a161) &
% 16.43/15.96 ~ bnd_c5_2 bnd_a160 bnd_a161) &
% 16.43/15.96 bnd_c2_2 bnd_a160 bnd_a161 |
% 16.43/15.96 (ALL X12. bnd_ndr1_0 --> bnd_c8_1 X12 | ~ bnd_c1_1 X12)) |
% 16.43/15.96 (ALL X13.
% 16.43/15.96 bnd_ndr1_0 -->
% 16.43/15.96 (bnd_c4_1 X13 |
% 16.43/15.96 (ALL X14.
% 16.43/15.96 bnd_ndr1_1 X13 -->
% 16.43/15.96 ~ bnd_c7_2 X13 X14 | bnd_c2_2 X13 X14)) |
% 16.43/15.96 bnd_c5_1 X13))) &
% 16.43/15.96 ((((((bnd_ndr1_0 & ~ bnd_c8_1 bnd_a162) &
% 16.43/15.96 (ALL X15.
% 16.43/15.96 bnd_ndr1_1 bnd_a162 -->
% 16.43/15.96 (bnd_c8_2 bnd_a162 X15 | bnd_c3_2 bnd_a162 X15) |
% 16.43/15.96 ~ bnd_c7_2 bnd_a162 X15)) &
% 16.43/15.96 bnd_ndr1_1 bnd_a162) &
% 16.43/15.96 ~ bnd_c5_2 bnd_a162 bnd_a163) &
% 16.43/15.96 ~ bnd_c6_2 bnd_a162 bnd_a163) &
% 16.43/15.96 bnd_c8_2 bnd_a162 bnd_a163 |
% 16.43/15.96 bnd_c5_0)) &
% 16.43/15.96 ((~ bnd_c7_0 |
% 16.43/15.96 (((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a164) &
% 16.43/15.96 ~ bnd_c2_2 bnd_a164 bnd_a165) &
% 16.43/15.96 ~ bnd_c5_2 bnd_a164 bnd_a165) &
% 16.43/15.96 bnd_c3_2 bnd_a164 bnd_a165) &
% 16.43/15.96 (ALL X16.
% 16.43/15.96 bnd_ndr1_1 bnd_a164 -->
% 16.43/15.96 ~ bnd_c8_2 bnd_a164 X16 | ~ bnd_c2_2 bnd_a164 X16)) &
% 16.43/15.96 bnd_c6_1 bnd_a164) |
% 16.43/15.96 (((((bnd_ndr1_0 & bnd_c1_1 bnd_a166) & bnd_ndr1_1 bnd_a166) &
% 16.43/15.96 bnd_c7_2 bnd_a166 bnd_a167) &
% 16.43/15.96 ~ bnd_c8_2 bnd_a166 bnd_a167) &
% 16.43/15.96 ~ bnd_c3_2 bnd_a166 bnd_a167) &
% 16.43/15.96 bnd_c7_1 bnd_a166)) &
% 16.43/15.96 ((bnd_c3_0 |
% 16.43/15.96 ((bnd_ndr1_0 & ~ bnd_c2_1 bnd_a168) &
% 16.43/15.96 (ALL X17.
% 16.43/15.96 bnd_ndr1_1 bnd_a168 -->
% 16.43/15.96 (bnd_c2_2 bnd_a168 X17 | ~ bnd_c5_2 bnd_a168 X17) |
% 16.43/15.96 ~ bnd_c8_2 bnd_a168 X17)) &
% 16.43/15.96 ~ bnd_c6_1 bnd_a168) |
% 16.43/15.96 ~ bnd_c4_0)) &
% 16.43/15.96 ((~ bnd_c4_0 | ~ bnd_c2_0) |
% 16.43/15.96 (ALL X18.
% 16.43/15.96 bnd_ndr1_0 -->
% 16.43/15.96 ((ALL X19.
% 16.43/15.96 bnd_ndr1_1 X18 -->
% 16.43/15.96 ~ bnd_c4_2 X18 X19 | ~ bnd_c1_2 X18 X19) |
% 16.43/15.96 ~ bnd_c8_1 X18) |
% 16.43/15.96 (ALL X20.
% 16.43/15.96 bnd_ndr1_1 X18 -->
% 16.43/15.96 (~ bnd_c6_2 X18 X20 | ~ bnd_c3_2 X18 X20) |
% 16.43/15.96 ~ bnd_c1_2 X18 X20)))) &
% 16.43/15.96 ((ALL X21.
% 16.43/15.96 bnd_ndr1_0 -->
% 16.43/15.96 (ALL X22.
% 16.43/15.96 bnd_ndr1_1 X21 -->
% 16.43/15.96 (bnd_c2_2 X21 X22 | bnd_c1_2 X21 X22) | ~ bnd_c7_2 X21 X22) |
% 16.43/15.96 bnd_c4_1 X21) |
% 16.43/15.96 (ALL X23.
% 16.43/15.96 bnd_ndr1_0 -->
% 16.43/15.96 ((ALL X24.
% 16.43/15.96 bnd_ndr1_1 X23 -->
% 16.43/15.96 (~ bnd_c5_2 X23 X24 | bnd_c3_2 X23 X24) |
% 16.43/15.96 bnd_c2_2 X23 X24) |
% 16.43/15.96 bnd_c1_1 X23) |
% 16.43/15.96 ~ bnd_c7_1 X23))) &
% 16.43/15.96 ((~ bnd_c4_0 | ~ bnd_c7_0) |
% 16.43/15.96 ((bnd_ndr1_0 & bnd_c2_1 bnd_a169) & bnd_c8_1 bnd_a169) &
% 16.43/15.96 ~ bnd_c6_1 bnd_a169)) &
% 16.43/15.96 ((bnd_c8_0 | bnd_c7_0) | ~ bnd_c3_0)) &
% 16.43/15.96 ((bnd_c7_0 |
% 16.43/15.96 ((bnd_ndr1_0 & ~ bnd_c5_1 bnd_a170) & ~ bnd_c7_1 bnd_a170) &
% 16.43/15.96 (ALL X25.
% 16.43/15.96 bnd_ndr1_1 bnd_a170 -->
% 16.43/15.96 (bnd_c3_2 bnd_a170 X25 | ~ bnd_c2_2 bnd_a170 X25) |
% 16.43/15.96 ~ bnd_c4_2 bnd_a170 X25)) |
% 16.43/15.96 bnd_c6_0)) &
% 16.43/15.96 ((~ bnd_c1_0 |
% 16.43/15.96 (ALL X26.
% 16.43/15.96 bnd_ndr1_0 --> (bnd_c3_1 X26 | ~ bnd_c4_1 X26) | bnd_c5_1 X26)) |
% 16.43/15.96 (((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a171) & ~ bnd_c1_2 bnd_a171 bnd_a172) &
% 16.43/15.96 bnd_c5_2 bnd_a171 bnd_a172) &
% 16.43/15.96 bnd_c2_2 bnd_a171 bnd_a172) &
% 16.43/15.96 bnd_c4_1 bnd_a171) &
% 16.43/15.96 ~ bnd_c2_1 bnd_a171)) &
% 16.43/15.96 ((((bnd_ndr1_0 &
% 16.43/15.96 (ALL X27.
% 16.43/15.96 bnd_ndr1_1 bnd_a173 -->
% 16.43/15.96 ~ bnd_c8_2 bnd_a173 X27 | ~ bnd_c1_2 bnd_a173 X27)) &
% 16.43/15.96 (ALL X28.
% 16.43/15.96 bnd_ndr1_1 bnd_a173 -->
% 16.43/15.96 (~ bnd_c7_2 bnd_a173 X28 | bnd_c8_2 bnd_a173 X28) |
% 16.43/15.96 bnd_c5_2 bnd_a173 X28)) &
% 16.43/15.96 ~ bnd_c6_1 bnd_a173 |
% 16.43/15.96 ((bnd_ndr1_0 & ~ bnd_c3_1 bnd_a174) & bnd_c5_1 bnd_a174) &
% 16.43/15.96 (ALL X29.
% 16.43/15.96 bnd_ndr1_1 bnd_a174 -->
% 16.43/15.96 (~ bnd_c8_2 bnd_a174 X29 | ~ bnd_c5_2 bnd_a174 X29) |
% 16.43/15.96 bnd_c6_2 bnd_a174 X29)) |
% 16.43/15.96 (ALL X30.
% 16.43/15.96 bnd_ndr1_0 -->
% 16.43/15.96 (((bnd_ndr1_1 X30 & bnd_c5_2 X30 bnd_a175) &
% 16.43/15.96 ~ bnd_c2_2 X30 bnd_a175) &
% 16.43/15.96 bnd_c3_2 X30 bnd_a175 |
% 16.43/15.96 (ALL X31.
% 16.43/15.96 bnd_ndr1_1 X30 -->
% 16.43/15.96 (bnd_c4_2 X30 X31 | bnd_c3_2 X30 X31) | bnd_c6_2 X30 X31)) |
% 16.43/15.96 bnd_c3_1 X30))) &
% 16.43/15.96 ((((((((((bnd_ndr1_0 &
% 16.43/15.96 (ALL X32.
% 16.43/15.96 bnd_ndr1_1 bnd_a176 -->
% 16.43/15.96 (~ bnd_c2_2 bnd_a176 X32 | bnd_c7_2 bnd_a176 X32) |
% 16.43/15.96 ~ bnd_c3_2 bnd_a176 X32)) &
% 16.43/15.96 bnd_ndr1_1 bnd_a176) &
% 16.43/15.96 ~ bnd_c2_2 bnd_a176 bnd_a177) &
% 16.43/15.96 ~ bnd_c6_2 bnd_a176 bnd_a177) &
% 16.43/15.96 ~ bnd_c3_2 bnd_a176 bnd_a177) &
% 16.43/15.96 bnd_ndr1_1 bnd_a176) &
% 16.43/15.96 bnd_c8_2 bnd_a176 bnd_a178) &
% 16.43/15.96 ~ bnd_c4_2 bnd_a176 bnd_a178) &
% 16.43/15.96 ~ bnd_c7_2 bnd_a176 bnd_a178 |
% 16.43/15.96 bnd_c7_0) |
% 16.43/15.96 (((((bnd_ndr1_0 &
% 16.43/15.96 (ALL X33.
% 16.43/15.96 bnd_ndr1_1 bnd_a179 -->
% 16.43/15.96 bnd_c2_2 bnd_a179 X33 | ~ bnd_c3_2 bnd_a179 X33)) &
% 16.43/15.96 ~ bnd_c2_1 bnd_a179) &
% 16.43/15.96 bnd_ndr1_1 bnd_a179) &
% 16.43/15.96 bnd_c2_2 bnd_a179 bnd_a180) &
% 16.43/15.96 bnd_c3_2 bnd_a179 bnd_a180) &
% 16.43/15.96 bnd_c6_2 bnd_a179 bnd_a180)) &
% 16.43/15.96 (((ALL X34.
% 16.43/15.96 bnd_ndr1_0 -->
% 16.43/15.96 ((ALL X35.
% 16.43/15.96 bnd_ndr1_1 X34 -->
% 16.43/15.96 (~ bnd_c8_2 X34 X35 | ~ bnd_c1_2 X34 X35) | ~ bnd_c3_2 X34 X35) |
% 16.43/15.96 ~ bnd_c3_1 X34) |
% 16.43/15.96 (ALL X36.
% 16.43/15.96 bnd_ndr1_1 X34 --> ~ bnd_c5_2 X34 X36 | ~ bnd_c6_2 X34 X36)) |
% 16.43/15.96 bnd_c5_0) |
% 16.43/15.96 ((bnd_ndr1_0 &
% 16.43/15.96 (ALL X37.
% 16.43/15.96 bnd_ndr1_1 bnd_a181 -->
% 16.43/15.96 (~ bnd_c2_2 bnd_a181 X37 | ~ bnd_c6_2 bnd_a181 X37) |
% 16.43/15.96 ~ bnd_c4_2 bnd_a181 X37)) &
% 16.43/15.96 bnd_c2_1 bnd_a181) &
% 16.43/15.96 (ALL X38.
% 16.43/15.96 bnd_ndr1_1 bnd_a181 -->
% 16.43/15.96 (~ bnd_c2_2 bnd_a181 X38 | bnd_c4_2 bnd_a181 X38) |
% 16.43/15.96 ~ bnd_c3_2 bnd_a181 X38))) &
% 16.43/15.96 (((ALL X39.
% 16.43/15.96 bnd_ndr1_0 -->
% 16.43/15.96 (bnd_c8_1 X39 |
% 16.43/15.96 (ALL X40.
% 16.43/15.96 bnd_ndr1_1 X39 -->
% 16.43/15.96 (bnd_c7_2 X39 X40 | ~ bnd_c1_2 X39 X40) | bnd_c5_2 X39 X40)) |
% 16.43/15.96 bnd_c1_1 X39) |
% 16.43/15.96 bnd_c6_0) |
% 16.43/15.96 ~ bnd_c1_0)) &
% 16.43/15.96 ((bnd_c3_0 | bnd_c6_0) | bnd_c8_0)) &
% 16.43/15.96 (bnd_c1_0 |
% 16.43/15.96 ((bnd_ndr1_0 &
% 16.43/15.96 (ALL X41.
% 16.43/15.96 bnd_ndr1_1 bnd_a182 -->
% 16.43/15.96 (~ bnd_c2_2 bnd_a182 X41 | bnd_c1_2 bnd_a182 X41) |
% 16.43/15.96 ~ bnd_c4_2 bnd_a182 X41)) &
% 16.43/15.96 (ALL X42.
% 16.43/15.96 bnd_ndr1_1 bnd_a182 -->
% 16.43/15.96 (~ bnd_c7_2 bnd_a182 X42 | ~ bnd_c6_2 bnd_a182 X42) |
% 16.43/15.96 ~ bnd_c1_2 bnd_a182 X42)) &
% 16.43/15.96 ~ bnd_c1_1 bnd_a182)) &
% 16.43/15.96 ((bnd_c7_0 | ~ bnd_c1_0) |
% 16.43/15.96 (((((bnd_ndr1_0 & bnd_c1_1 bnd_a183) &
% 16.43/15.96 bnd_ndr1_1 bnd_a183) &
% 16.43/15.96 bnd_c7_2 bnd_a183 bnd_a184) &
% 16.43/15.96 bnd_c5_2 bnd_a183 bnd_a184) &
% 16.43/15.96 bnd_c3_2 bnd_a183 bnd_a184) &
% 16.43/15.96 bnd_c4_1 bnd_a183)) &
% 16.43/15.96 ((bnd_c4_0 | bnd_c2_0) |
% 16.43/15.96 (ALL X43.
% 16.43/15.96 bnd_ndr1_0 -->
% 16.43/15.96 ((ALL X44.
% 16.43/15.96 bnd_ndr1_1 X43 -->
% 16.43/15.96 (bnd_c5_2 X43 X44 | ~ bnd_c6_2 X43 X44) | ~ bnd_c8_2 X43 X44) |
% 16.43/15.96 bnd_c6_1 X43) |
% 16.43/15.96 (ALL X45.
% 16.43/15.96 bnd_ndr1_1 X43 --> ~ bnd_c5_2 X43 X45 | ~ bnd_c7_2 X43 X45)))) &
% 16.43/15.96 ((bnd_c1_0 | ~ bnd_c3_0) |
% 16.43/15.96 (ALL X46.
% 16.43/15.96 bnd_ndr1_0 -->
% 16.43/15.96 (bnd_c3_1 X46 |
% 16.43/15.96 ((bnd_ndr1_1 X46 &
% 16.43/15.96 bnd_c7_2 X46 bnd_a185) &
% 16.43/15.96 bnd_c4_2 X46 bnd_a185) &
% 16.43/15.96 bnd_c5_2 X46 bnd_a185) |
% 16.43/15.96 ~ bnd_c5_1 X46))) &
% 16.43/15.96 ((bnd_c1_0 |
% 16.43/15.96 (ALL X47.
% 16.43/15.96 bnd_ndr1_0 -->
% 16.43/15.96 (~ bnd_c1_1 X47 |
% 16.43/15.96 (ALL X48.
% 16.43/15.96 bnd_ndr1_1 X47 -->
% 16.43/15.96 (bnd_c7_2 X47 X48 | ~ bnd_c8_2 X47 X48) | bnd_c6_2 X47 X48)) |
% 16.43/15.96 (ALL X49.
% 16.43/15.96 bnd_ndr1_1 X47 -->
% 16.43/15.96 (bnd_c4_2 X47 X49 | bnd_c5_2 X47 X49) | ~ bnd_c1_2 X47 X49))) |
% 16.43/15.96 bnd_c5_0)) &
% 16.43/15.96 ((bnd_c2_0 | ~ bnd_c3_0) |
% 16.43/15.96 ((bnd_ndr1_0 &
% 16.43/15.96 (ALL X50.
% 16.43/15.96 bnd_ndr1_1 bnd_a186 -->
% 16.43/15.96 (~ bnd_c8_2 bnd_a186 X50 |
% 16.43/15.96 bnd_c5_2 bnd_a186 X50) |
% 16.43/15.96 ~ bnd_c1_2 bnd_a186 X50)) &
% 16.43/15.96 ~ bnd_c7_1 bnd_a186) &
% 16.43/15.96 bnd_c1_1 bnd_a186)) &
% 16.43/15.96 ((((((bnd_ndr1_0 & bnd_c4_1 bnd_a187) &
% 16.43/15.96 bnd_ndr1_1 bnd_a187) &
% 16.43/15.96 ~ bnd_c4_2 bnd_a187 bnd_a188) &
% 16.43/15.96 ~ bnd_c6_2 bnd_a187 bnd_a188) &
% 16.43/15.96 ~ bnd_c3_1 bnd_a187 |
% 16.43/15.96 ((bnd_ndr1_0 & ~ bnd_c6_1 bnd_a189) &
% 16.43/15.96 (ALL X51.
% 16.43/15.96 bnd_ndr1_1 bnd_a189 -->
% 16.43/15.96 (~ bnd_c2_2 bnd_a189 X51 |
% 16.43/15.96 bnd_c7_2 bnd_a189 X51) |
% 16.43/15.96 ~ bnd_c8_2 bnd_a189 X51)) &
% 16.43/15.96 (ALL X52.
% 16.43/15.96 bnd_ndr1_1 bnd_a189 -->
% 16.43/15.96 (~ bnd_c8_2 bnd_a189 X52 |
% 16.43/15.96 ~ bnd_c1_2 bnd_a189 X52) |
% 16.43/15.96 bnd_c6_2 bnd_a189 X52)) |
% 16.43/15.96 (ALL X53.
% 16.43/15.96 bnd_ndr1_0 -->
% 16.43/15.96 ((ALL X54.
% 16.43/15.96 bnd_ndr1_1 X53 -->
% 16.43/15.96 (bnd_c2_2 X53 X54 | bnd_c4_2 X53 X54) | bnd_c1_2 X53 X54) |
% 16.43/15.96 (ALL X55.
% 16.43/15.96 bnd_ndr1_1 X53 -->
% 16.43/15.96 (~ bnd_c3_2 X53 X55 | bnd_c6_2 X53 X55) | ~ bnd_c8_2 X53 X55)) |
% 16.43/15.96 ~ bnd_c7_1 X53))) &
% 16.43/15.96 (((ALL X56.
% 16.43/15.96 bnd_ndr1_0 -->
% 16.43/15.96 (bnd_c3_1 X56 |
% 16.43/15.96 ((bnd_ndr1_1 X56 &
% 16.43/15.96 ~ bnd_c3_2 X56 bnd_a190) &
% 16.43/15.96 bnd_c1_2 X56 bnd_a190) &
% 16.43/15.96 ~ bnd_c6_2 X56 bnd_a190) |
% 16.43/15.96 bnd_c2_1 X56) |
% 16.43/15.96 (ALL X57.
% 16.43/15.96 bnd_ndr1_0 -->
% 16.43/15.96 (bnd_c8_1 X57 |
% 16.43/15.96 (ALL X58.
% 16.43/15.96 bnd_ndr1_1 X57 --> bnd_c6_2 X57 X58 | bnd_c7_2 X57 X58)) |
% 16.43/15.96 (ALL X59.
% 16.43/15.96 bnd_ndr1_1 X57 -->
% 16.43/15.96 (bnd_c3_2 X57 X59 |
% 16.43/15.96 ~ bnd_c2_2 X57 X59) |
% 16.43/15.96 ~ bnd_c6_2 X57 X59))) |
% 16.43/15.96 ((((bnd_ndr1_0 & ~ bnd_c5_1 bnd_a191) &
% 16.43/15.96 bnd_c1_1 bnd_a191) &
% 16.43/15.96 bnd_ndr1_1 bnd_a191) &
% 16.43/15.96 bnd_c7_2 bnd_a191 bnd_a192) &
% 16.43/15.96 ~ bnd_c8_2 bnd_a191 bnd_a192)) &
% 16.43/15.96 ((bnd_c1_0 |
% 16.43/15.96 (ALL X60.
% 16.43/15.96 bnd_ndr1_0 -->
% 16.43/15.96 ((ALL X61.
% 16.43/15.96 bnd_ndr1_1 X60 -->
% 16.43/15.96 (~ bnd_c6_2 X60 X61 |
% 16.43/15.96 ~ bnd_c7_2 X60 X61) |
% 16.43/15.96 bnd_c2_2 X60 X61) |
% 16.43/15.96 ~ bnd_c3_1 X60) |
% 16.43/15.96 bnd_c5_1 X60)) |
% 16.43/15.96 (((((bnd_ndr1_0 & ~ bnd_c1_1 bnd_a193) &
% 16.43/15.96 ~ bnd_c7_1 bnd_a193) &
% 16.43/15.96 bnd_ndr1_1 bnd_a193) &
% 16.43/15.96 ~ bnd_c4_2 bnd_a193 bnd_a194) &
% 16.43/15.96 ~ bnd_c6_2 bnd_a193 bnd_a194) &
% 16.43/15.96 bnd_c7_2 bnd_a193 bnd_a194)) &
% 16.43/15.96 (((ALL X62.
% 16.43/15.96 bnd_ndr1_0 -->
% 16.43/15.96 ((ALL X63.
% 16.43/15.96 bnd_ndr1_1 X62 -->
% 16.43/15.96 (~ bnd_c1_2 X62 X63 |
% 16.43/15.96 ~ bnd_c6_2 X62 X63) |
% 16.43/15.96 ~ bnd_c3_2 X62 X63) |
% 16.43/15.96 ~ bnd_c4_1 X62) |
% 16.43/15.96 ~ bnd_c2_1 X62) |
% 16.43/15.96 bnd_ndr1_0 &
% 16.43/15.96 (ALL X64.
% 16.43/15.96 bnd_ndr1_1 bnd_a195 -->
% 16.43/15.96 (bnd_c4_2 bnd_a195 X64 |
% 16.43/15.96 ~ bnd_c6_2 bnd_a195 X64) |
% 16.43/15.96 bnd_c5_2 bnd_a195 X64)) |
% 16.43/15.96 ((bnd_ndr1_0 & bnd_c2_1 bnd_a196) &
% 16.43/15.96 ~ bnd_c4_1 bnd_a196) &
% 16.43/15.96 (ALL X65.
% 16.43/15.96 bnd_ndr1_1 bnd_a196 -->
% 16.43/15.96 ~ bnd_c1_2 bnd_a196 X65 |
% 16.43/15.96 ~ bnd_c4_2 bnd_a196 X65))) &
% 16.43/15.96 (bnd_c5_0 |
% 16.43/15.96 (((((bnd_ndr1_0 & ~ bnd_c8_1 bnd_a197) &
% 16.43/15.96 ~ bnd_c6_1 bnd_a197) &
% 16.43/15.96 bnd_ndr1_1 bnd_a197) &
% 16.43/15.96 bnd_c4_2 bnd_a197 bnd_a198) &
% 16.43/15.96 ~ bnd_c6_2 bnd_a197 bnd_a198) &
% 16.43/15.96 ~ bnd_c1_2 bnd_a197 bnd_a198)) &
% 16.43/15.96 ((~ bnd_c5_0 | bnd_c7_0) | bnd_c8_0)) &
% 16.43/15.96 ((bnd_ndr1_0 & bnd_c1_1 bnd_a199 |
% 16.43/15.96 (bnd_ndr1_0 & ~ bnd_c1_1 bnd_a200) &
% 16.43/15.96 bnd_c6_1 bnd_a200) |
% 16.43/15.96 (ALL X66.
% 16.43/15.96 bnd_ndr1_0 -->
% 16.43/15.96 ((ALL X67.
% 16.43/15.96 bnd_ndr1_1 X66 -->
% 16.43/15.96 bnd_c2_2 X66 X67 | bnd_c7_2 X66 X67) |
% 16.43/15.96 ((bnd_ndr1_1 X66 & bnd_c1_2 X66 bnd_a201) &
% 16.43/15.96 bnd_c8_2 X66 bnd_a201) &
% 16.43/15.96 bnd_c7_2 X66 bnd_a201) |
% 16.43/15.96 ~ bnd_c2_1 X66))) &
% 16.43/15.96 (((ALL X68.
% 16.43/15.96 bnd_ndr1_0 -->
% 16.43/15.96 (ALL X69.
% 16.43/15.96 bnd_ndr1_1 X68 -->
% 16.43/15.96 (bnd_c2_2 X68 X69 | bnd_c4_2 X68 X69) |
% 16.43/15.96 ~ bnd_c5_2 X68 X69) |
% 16.43/15.96 ~ bnd_c2_1 X68) |
% 16.43/15.96 ((bnd_ndr1_0 & bnd_c7_1 bnd_a202) &
% 16.43/15.96 (ALL X70.
% 16.43/15.96 bnd_ndr1_1 bnd_a202 -->
% 16.43/15.96 (~ bnd_c6_2 bnd_a202 X70 |
% 16.43/15.96 bnd_c3_2 bnd_a202 X70) |
% 16.43/15.96 bnd_c8_2 bnd_a202 X70)) &
% 16.43/15.96 (ALL X71.
% 16.43/15.96 bnd_ndr1_1 bnd_a202 -->
% 16.43/15.96 (bnd_c6_2 bnd_a202 X71 | bnd_c7_2 bnd_a202 X71) |
% 16.43/15.96 ~ bnd_c3_2 bnd_a202 X71)) |
% 16.43/15.96 ((bnd_ndr1_0 & bnd_c4_1 bnd_a203) &
% 16.43/15.96 bnd_c8_1 bnd_a203) &
% 16.43/15.96 (ALL X72.
% 16.43/15.96 bnd_ndr1_1 bnd_a203 -->
% 16.43/15.96 (~ bnd_c1_2 bnd_a203 X72 |
% 16.43/15.96 ~ bnd_c5_2 bnd_a203 X72) |
% 16.43/15.96 ~ bnd_c8_2 bnd_a203 X72))) &
% 16.43/15.96 (bnd_c1_0 |
% 16.43/15.96 ((((bnd_ndr1_0 &
% 16.43/15.96 (ALL X73.
% 16.43/15.96 bnd_ndr1_1 bnd_a204 -->
% 16.43/15.96 bnd_c8_2 bnd_a204 X73 |
% 16.43/15.96 bnd_c2_2 bnd_a204 X73)) &
% 16.43/15.96 bnd_c8_1 bnd_a204) &
% 16.43/15.96 bnd_ndr1_1 bnd_a204) &
% 16.43/15.96 bnd_c7_2 bnd_a204 bnd_a205) &
% 16.43/15.96 bnd_c3_2 bnd_a204 bnd_a205)) &
% 16.43/15.96 ((bnd_c3_0 |
% 16.43/15.96 (ALL X74.
% 16.43/15.96 bnd_ndr1_0 -->
% 16.43/15.96 ((ALL X75.
% 16.43/15.96 bnd_ndr1_1 X74 -->
% 16.43/15.96 ~ bnd_c5_2 X74 X75 | ~ bnd_c4_2 X74 X75) |
% 16.43/15.96 ((bnd_ndr1_1 X74 & bnd_c3_2 X74 bnd_a206) &
% 16.43/15.96 bnd_c6_2 X74 bnd_a206) &
% 16.43/15.96 bnd_c4_2 X74 bnd_a206) |
% 16.43/15.96 ((bnd_ndr1_1 X74 & ~ bnd_c3_2 X74 bnd_a207) &
% 16.43/15.96 bnd_c8_2 X74 bnd_a207) &
% 16.43/15.96 ~ bnd_c5_2 X74 bnd_a207)) |
% 16.43/15.96 bnd_c4_0)) &
% 16.43/15.96 (((((((bnd_ndr1_0 & bnd_c8_1 bnd_a208) &
% 16.43/15.96 bnd_ndr1_1 bnd_a208) &
% 16.43/15.96 ~ bnd_c6_2 bnd_a208 bnd_a209) &
% 16.43/15.96 ~ bnd_c2_2 bnd_a208 bnd_a209) &
% 16.43/15.96 ~ bnd_c3_2 bnd_a208 bnd_a209) &
% 16.43/15.96 ~ bnd_c1_1 bnd_a208 |
% 16.43/15.96 (ALL X76.
% 16.43/15.96 bnd_ndr1_0 -->
% 16.43/15.96 ((ALL X77.
% 16.43/15.96 bnd_ndr1_1 X76 -->
% 16.43/15.96 (bnd_c7_2 X76 X77 | bnd_c4_2 X76 X77) |
% 16.43/15.96 ~ bnd_c6_2 X76 X77) |
% 16.43/15.96 (ALL X78.
% 16.43/15.96 bnd_ndr1_1 X76 -->
% 16.43/15.96 (~ bnd_c1_2 X76 X78 | bnd_c4_2 X76 X78) |
% 16.43/15.96 ~ bnd_c7_2 X76 X78)) |
% 16.43/15.96 bnd_c7_1 X76)) |
% 16.43/15.96 ~ bnd_c8_0)) &
% 16.43/15.96 (~ bnd_c6_0 |
% 16.43/15.96 (ALL X79.
% 16.43/15.96 bnd_ndr1_0 -->
% 16.43/15.96 ~ bnd_c4_1 X79 |
% 16.43/15.96 ((bnd_ndr1_1 X79 & ~ bnd_c5_2 X79 bnd_a210) &
% 16.43/15.96 bnd_c4_2 X79 bnd_a210) &
% 16.43/15.96 bnd_c8_2 X79 bnd_a210))) &
% 16.43/15.96 ((~ bnd_c5_0 | ~ bnd_c7_0) | bnd_c3_0)) &
% 16.43/15.96 ((bnd_c5_0 | ~ bnd_c4_0) | ~ bnd_c1_0)) &
% 16.43/15.96 ((((((bnd_ndr1_0 & bnd_c4_1 bnd_a211) & ~ bnd_c3_1 bnd_a211) &
% 16.43/15.96 bnd_ndr1_1 bnd_a211) &
% 16.43/15.96 ~ bnd_c1_2 bnd_a211 bnd_a212) &
% 16.43/15.96 ~ bnd_c8_2 bnd_a211 bnd_a212 |
% 16.43/15.96 (ALL X80.
% 16.43/15.96 bnd_ndr1_0 -->
% 16.43/15.96 (bnd_c5_1 X80 | ~ bnd_c4_1 X80) |
% 16.43/15.96 ((bnd_ndr1_1 X80 & bnd_c2_2 X80 bnd_a213) &
% 16.43/15.96 ~ bnd_c3_2 X80 bnd_a213) &
% 16.43/15.96 bnd_c7_2 X80 bnd_a213)) |
% 16.43/15.96 bnd_c7_0)) &
% 16.43/15.96 ((~ bnd_c2_0 |
% 16.43/15.96 (ALL X81.
% 16.43/15.96 bnd_ndr1_0 -->
% 16.43/15.96 (~ bnd_c1_1 X81 |
% 16.43/15.96 ((bnd_ndr1_1 X81 & ~ bnd_c2_2 X81 bnd_a214) &
% 16.43/15.96 bnd_c7_2 X81 bnd_a214) &
% 16.43/15.96 bnd_c4_2 X81 bnd_a214) |
% 16.43/15.96 bnd_c2_1 X81)) |
% 16.43/15.96 bnd_c4_0)) &
% 16.43/15.96 ((ALL X82.
% 16.43/15.96 bnd_ndr1_0 -->
% 16.43/15.96 (bnd_c2_1 X82 | ~ bnd_c5_1 X82) |
% 16.43/15.96 (ALL X83.
% 16.43/15.96 bnd_ndr1_1 X82 -->
% 16.43/15.96 (~ bnd_c2_2 X82 X83 | bnd_c3_2 X82 X83) |
% 16.43/15.96 bnd_c8_2 X82 X83)) |
% 16.43/15.96 bnd_c8_0)) &
% 16.43/15.96 (((((((bnd_ndr1_0 & bnd_c7_1 bnd_a215) & bnd_ndr1_1 bnd_a215) &
% 16.43/15.96 ~ bnd_c1_2 bnd_a215 bnd_a216) &
% 16.43/15.96 ~ bnd_c4_2 bnd_a215 bnd_a216) &
% 16.43/15.96 bnd_c3_2 bnd_a215 bnd_a216) &
% 16.43/15.96 ~ bnd_c2_1 bnd_a215 |
% 16.43/15.96 bnd_c7_0) |
% 16.43/15.96 bnd_c8_0)) &
% 16.43/15.96 (((bnd_ndr1_0 & bnd_c8_1 bnd_a217) & bnd_c7_1 bnd_a217) &
% 16.43/15.96 ~ bnd_c1_1 bnd_a217 |
% 16.43/15.96 ~ bnd_c4_0)) &
% 16.43/15.96 ((~ bnd_c5_0 |
% 16.43/15.96 (ALL X84.
% 16.43/15.96 bnd_ndr1_0 -->
% 16.43/15.96 (bnd_c5_1 X84 |
% 16.43/15.96 (ALL X85.
% 16.43/15.96 bnd_ndr1_1 X84 -->
% 16.43/15.96 (bnd_c7_2 X84 X85 | ~ bnd_c5_2 X84 X85) |
% 16.43/15.96 ~ bnd_c6_2 X84 X85)) |
% 16.43/15.96 ~ bnd_c7_1 X84)) |
% 16.43/15.96 bnd_c4_0)) &
% 16.43/15.96 ((((((bnd_ndr1_0 & ~ bnd_c5_1 bnd_a218) & bnd_ndr1_1 bnd_a218) &
% 16.43/15.96 ~ bnd_c5_2 bnd_a218 bnd_a219) &
% 16.43/15.96 bnd_c4_2 bnd_a218 bnd_a219) &
% 16.43/15.96 ~ bnd_c1_1 bnd_a218 |
% 16.43/15.96 (ALL X86.
% 16.43/15.96 bnd_ndr1_0 -->
% 16.43/15.96 ((ALL X87.
% 16.43/15.96 bnd_ndr1_1 X86 -->
% 16.43/15.96 (~ bnd_c1_2 X86 X87 | ~ bnd_c7_2 X86 X87) |
% 16.43/15.96 bnd_c8_2 X86 X87) |
% 16.43/15.96 ((bnd_ndr1_1 X86 & ~ bnd_c3_2 X86 bnd_a220) &
% 16.43/15.96 ~ bnd_c5_2 X86 bnd_a220) &
% 16.43/15.96 bnd_c1_2 X86 bnd_a220) |
% 16.43/15.96 (ALL X88.
% 16.43/15.96 bnd_ndr1_1 X86 -->
% 16.43/15.96 (bnd_c6_2 X86 X88 | ~ bnd_c8_2 X86 X88) |
% 16.43/15.96 ~ bnd_c4_2 X86 X88))) |
% 16.43/15.96 bnd_c4_0)) &
% 16.43/15.96 ((((bnd_ndr1_0 &
% 16.43/15.96 (ALL X89.
% 16.43/15.96 bnd_ndr1_1 bnd_a221 -->
% 16.43/15.96 (~ bnd_c7_2 bnd_a221 X89 | bnd_c2_2 bnd_a221 X89) |
% 16.43/15.96 bnd_c4_2 bnd_a221 X89)) &
% 16.43/15.96 ~ bnd_c1_1 bnd_a221) &
% 16.43/15.96 ~ bnd_c2_1 bnd_a221 |
% 16.43/15.96 ~ bnd_c2_0) |
% 16.43/15.96 ((bnd_ndr1_0 &
% 16.43/15.96 (ALL X90.
% 16.43/15.96 bnd_ndr1_1 bnd_a222 -->
% 16.43/15.96 bnd_c5_2 bnd_a222 X90 | bnd_c2_2 bnd_a222 X90)) &
% 16.43/15.96 ~ bnd_c1_1 bnd_a222) &
% 16.43/15.96 ~ bnd_c6_1 bnd_a222)) &
% 16.43/15.96 ((bnd_c1_0 | bnd_c2_0) | bnd_c5_0)) &
% 16.43/15.96 ((bnd_c1_0 |
% 16.43/15.96 ((bnd_ndr1_0 & ~ bnd_c4_1 bnd_a223) &
% 16.43/15.96 (ALL X91.
% 16.43/15.96 bnd_ndr1_1 bnd_a223 -->
% 16.43/15.96 bnd_c6_2 bnd_a223 X91 | ~ bnd_c4_2 bnd_a223 X91)) &
% 16.43/15.96 (ALL X92.
% 16.43/15.96 bnd_ndr1_1 bnd_a223 -->
% 16.43/15.96 bnd_c7_2 bnd_a223 X92 | bnd_c2_2 bnd_a223 X92)) |
% 16.43/15.96 (ALL X93.
% 16.43/15.96 bnd_ndr1_0 -->
% 16.43/15.96 ((bnd_ndr1_1 X93 & bnd_c3_2 X93 bnd_a224) &
% 16.43/15.96 ~ bnd_c5_2 X93 bnd_a224 |
% 16.43/15.96 bnd_c1_1 X93) |
% 16.43/15.96 ((bnd_ndr1_1 X93 & bnd_c8_2 X93 bnd_a225) &
% 16.43/15.96 bnd_c2_2 X93 bnd_a225) &
% 16.43/15.96 ~ bnd_c4_2 X93 bnd_a225))) &
% 16.43/15.96 ((~ bnd_c1_0 |
% 16.43/15.96 ((bnd_ndr1_0 &
% 16.43/15.96 (ALL X94.
% 16.43/15.96 bnd_ndr1_1 bnd_a226 -->
% 16.43/15.96 (~ bnd_c6_2 bnd_a226 X94 | bnd_c7_2 bnd_a226 X94) |
% 16.43/15.96 ~ bnd_c5_2 bnd_a226 X94)) &
% 16.43/15.96 (ALL X95.
% 16.43/15.96 bnd_ndr1_1 bnd_a226 -->
% 16.43/15.96 (bnd_c5_2 bnd_a226 X95 | ~ bnd_c8_2 bnd_a226 X95) |
% 16.43/15.96 bnd_c6_2 bnd_a226 X95)) &
% 16.43/15.96 ~ bnd_c5_1 bnd_a226) |
% 16.43/15.96 ((((bnd_ndr1_0 &
% 16.43/15.96 (ALL X96.
% 16.43/15.96 bnd_ndr1_1 bnd_a227 -->
% 16.43/15.96 (bnd_c5_2 bnd_a227 X96 | bnd_c2_2 bnd_a227 X96) |
% 16.43/15.96 ~ bnd_c4_2 bnd_a227 X96)) &
% 16.43/15.96 (ALL X97.
% 16.43/15.96 bnd_ndr1_1 bnd_a227 -->
% 16.43/15.96 (bnd_c2_2 bnd_a227 X97 | ~ bnd_c7_2 bnd_a227 X97) |
% 16.43/15.96 ~ bnd_c4_2 bnd_a227 X97)) &
% 16.43/15.96 bnd_ndr1_1 bnd_a227) &
% 16.43/15.96 bnd_c7_2 bnd_a227 bnd_a228) &
% 16.43/15.96 bnd_c6_2 bnd_a227 bnd_a228)) &
% 16.43/15.96 (((bnd_ndr1_0 & bnd_c1_1 bnd_a229) &
% 16.43/15.96 (ALL X98.
% 16.43/15.96 bnd_ndr1_1 bnd_a229 -->
% 16.43/15.96 (bnd_c2_2 bnd_a229 X98 | bnd_c1_2 bnd_a229 X98) |
% 16.43/15.96 bnd_c8_2 bnd_a229 X98)) &
% 16.43/15.96 (ALL X99.
% 16.43/15.96 bnd_ndr1_1 bnd_a229 -->
% 16.43/15.96 (~ bnd_c4_2 bnd_a229 X99 | bnd_c3_2 bnd_a229 X99) |
% 16.43/15.96 bnd_c1_2 bnd_a229 X99) |
% 16.43/15.96 ~ bnd_c2_0)) &
% 16.43/15.96 ((bnd_c8_0 |
% 16.43/15.96 (ALL X100.
% 16.43/15.96 bnd_ndr1_0 -->
% 16.43/15.96 ((ALL X101.
% 16.43/15.96 bnd_ndr1_1 X100 -->
% 16.43/15.96 (bnd_c7_2 X100 X101 | ~ bnd_c4_2 X100 X101) |
% 16.43/15.96 ~ bnd_c6_2 X100 X101) |
% 16.43/15.96 ((bnd_ndr1_1 X100 & ~ bnd_c8_2 X100 bnd_a230) &
% 16.43/15.96 bnd_c7_2 X100 bnd_a230) &
% 16.43/15.96 ~ bnd_c6_2 X100 bnd_a230) |
% 16.43/15.96 bnd_c7_1 X100)) |
% 16.43/15.96 ~ bnd_c1_0)) &
% 16.43/15.96 (((((((bnd_ndr1_0 & ~ bnd_c8_1 bnd_a231) & bnd_ndr1_1 bnd_a231) &
% 16.43/15.96 bnd_c4_2 bnd_a231 bnd_a232) &
% 16.43/15.96 bnd_c6_2 bnd_a231 bnd_a232) &
% 16.43/15.96 bnd_c5_2 bnd_a231 bnd_a232) &
% 16.43/15.96 bnd_c4_1 bnd_a231 |
% 16.43/15.96 (ALL X102.
% 16.43/15.96 bnd_ndr1_0 -->
% 16.43/15.96 ((ALL X103.
% 16.43/15.96 bnd_ndr1_1 X102 --> ~ bnd_c6_2 X102 X103 | bnd_c3_2 X102 X103) |
% 16.43/15.96 ~ bnd_c3_1 X102) |
% 16.43/15.96 ~ bnd_c5_1 X102)) |
% 16.43/15.96 (ALL X104.
% 16.43/15.96 bnd_ndr1_0 -->
% 16.43/15.96 (~ bnd_c1_1 X104 | bnd_c2_1 X104) |
% 16.43/15.96 (ALL X105.
% 16.43/15.96 bnd_ndr1_1 X104 -->
% 16.43/15.96 (~ bnd_c7_2 X104 X105 | bnd_c1_2 X104 X105) |
% 16.43/15.96 ~ bnd_c4_2 X104 X105)))) &
% 16.43/15.96 ((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a233) & bnd_c6_2 bnd_a233 bnd_a234) &
% 16.43/15.96 bnd_c3_2 bnd_a233 bnd_a234) &
% 16.43/15.96 bnd_c1_2 bnd_a233 bnd_a234) &
% 16.43/15.96 (ALL X106.
% 16.43/15.96 bnd_ndr1_1 bnd_a233 -->
% 16.43/15.96 ~ bnd_c4_2 bnd_a233 X106 | ~ bnd_c3_2 bnd_a233 X106)) &
% 16.43/15.96 (ALL X107.
% 16.43/15.96 bnd_ndr1_1 bnd_a233 -->
% 16.43/15.96 bnd_c6_2 bnd_a233 X107 | ~ bnd_c8_2 bnd_a233 X107) |
% 16.43/15.96 ((bnd_ndr1_0 & ~ bnd_c1_1 bnd_a235) & ~ bnd_c3_1 bnd_a235) &
% 16.43/15.96 (ALL X108.
% 16.43/15.96 bnd_ndr1_1 bnd_a235 -->
% 16.43/15.96 ~ bnd_c4_2 bnd_a235 X108 | bnd_c8_2 bnd_a235 X108))) &
% 16.43/15.96 ((~ bnd_c7_0 |
% 16.43/15.96 (ALL X109.
% 16.43/15.96 bnd_ndr1_0 -->
% 16.43/15.96 (~ bnd_c6_1 X109 |
% 16.43/15.96 ((bnd_ndr1_1 X109 & bnd_c5_2 X109 bnd_a236) &
% 16.43/15.96 ~ bnd_c6_2 X109 bnd_a236) &
% 16.43/15.96 ~ bnd_c4_2 X109 bnd_a236) |
% 16.43/15.96 ~ bnd_c8_1 X109)) |
% 16.43/15.96 bnd_c1_0)) &
% 16.43/15.96 (((((((bnd_ndr1_0 & bnd_c1_1 bnd_a237) &
% 16.43/15.96 bnd_ndr1_1 bnd_a237) &
% 16.43/15.96 bnd_c2_2 bnd_a237 bnd_a238) &
% 16.43/15.96 ~ bnd_c7_2 bnd_a237 bnd_a238) &
% 16.43/15.96 ~ bnd_c1_2 bnd_a237 bnd_a238) &
% 16.43/15.96 ~ bnd_c7_1 bnd_a237 |
% 16.43/15.96 (ALL X110.
% 16.43/15.96 bnd_ndr1_0 -->
% 16.43/15.96 (((bnd_ndr1_1 X110 & ~ bnd_c5_2 X110 bnd_a239) &
% 16.43/15.96 bnd_c7_2 X110 bnd_a239) &
% 16.43/15.96 bnd_c8_2 X110 bnd_a239 |
% 16.43/15.96 (ALL X111.
% 16.43/15.96 bnd_ndr1_1 X110 -->
% 16.43/15.96 (~ bnd_c5_2 X110 X111 | bnd_c8_2 X110 X111) |
% 16.43/15.96 bnd_c7_2 X110 X111)) |
% 16.43/15.96 (bnd_ndr1_1 X110 & ~ bnd_c1_2 X110 bnd_a240) &
% 16.43/15.96 bnd_c7_2 X110 bnd_a240)) |
% 16.43/15.96 bnd_c6_0)) &
% 16.43/15.96 ((((((((((bnd_ndr1_0 &
% 16.43/15.96 bnd_ndr1_1 bnd_a241) &
% 16.43/15.96 ~ bnd_c1_2 bnd_a241 bnd_a242) &
% 16.43/15.96 ~ bnd_c7_2 bnd_a241 bnd_a242) &
% 16.43/15.96 ~ bnd_c4_2 bnd_a241 bnd_a242) &
% 16.43/15.96 (ALL X112.
% 16.43/15.96 bnd_ndr1_1 bnd_a241 -->
% 16.43/15.96 (bnd_c6_2 bnd_a241 X112 | ~ bnd_c4_2 bnd_a241 X112) |
% 16.43/15.96 bnd_c5_2 bnd_a241 X112)) &
% 16.43/15.96 bnd_ndr1_1 bnd_a241) &
% 16.43/15.96 ~ bnd_c6_2 bnd_a241 bnd_a243) &
% 16.43/15.96 bnd_c4_2 bnd_a241 bnd_a243) &
% 16.43/15.96 bnd_c5_2 bnd_a241 bnd_a243 |
% 16.43/15.96 ((((((bnd_ndr1_0 &
% 16.43/15.96 bnd_ndr1_1 bnd_a244) &
% 16.43/15.96 bnd_c4_2 bnd_a244 bnd_a245) &
% 16.43/15.96 ~ bnd_c2_2 bnd_a244 bnd_a245) &
% 16.43/15.96 bnd_ndr1_1 bnd_a244) &
% 16.43/15.96 ~ bnd_c3_2 bnd_a244 bnd_a246) &
% 16.43/15.96 bnd_c8_2 bnd_a244 bnd_a246) &
% 16.43/15.96 ~ bnd_c7_2 bnd_a244 bnd_a246) |
% 16.43/15.96 ~ bnd_c6_0)) &
% 16.43/15.96 (((ALL X113.
% 16.43/15.96 bnd_ndr1_0 -->
% 16.43/15.96 (bnd_c2_1 X113 | bnd_c3_1 X113) |
% 16.43/15.96 (ALL X114.
% 16.43/15.96 bnd_ndr1_1 X113 -->
% 16.43/15.96 (~ bnd_c3_2 X113 X114 | ~ bnd_c6_2 X113 X114) |
% 16.43/15.96 ~ bnd_c8_2 X113 X114)) |
% 16.43/15.96 ~ bnd_c4_0) |
% 16.43/15.96 (ALL X115.
% 16.43/15.96 bnd_ndr1_0 -->
% 16.43/15.96 (bnd_c4_1 X115 | bnd_c3_1 X115) |
% 16.43/15.96 (ALL X116.
% 16.43/15.96 bnd_ndr1_1 X115 -->
% 16.43/15.96 (bnd_c5_2 X115 X116 | bnd_c3_2 X115 X116) | ~ bnd_c8_2 X115 X116)))) &
% 16.43/15.96 ((bnd_c4_0 | ~ bnd_c5_0) | bnd_c3_0)) &
% 16.43/15.96 ((bnd_c8_0 |
% 16.43/15.96 (ALL X117.
% 16.43/15.96 bnd_ndr1_0 -->
% 16.43/15.96 ((bnd_ndr1_1 X117 & ~ bnd_c5_2 X117 bnd_a247) & ~ bnd_c1_2 X117 bnd_a247 |
% 16.43/15.96 bnd_c1_1 X117) |
% 16.43/15.96 ~ bnd_c7_1 X117)) |
% 16.43/15.96 (ALL X118.
% 16.43/15.96 bnd_ndr1_0 -->
% 16.43/15.96 (bnd_c2_1 X118 | ~ bnd_c7_1 X118) |
% 16.43/15.96 ~ bnd_c5_1 X118))) &
% 16.43/15.96 ((~ bnd_c2_0 |
% 16.43/15.96 (ALL X119.
% 16.43/15.96 bnd_ndr1_0 -->
% 16.43/15.96 (((bnd_ndr1_1 X119 &
% 16.43/15.96 bnd_c3_2 X119 bnd_a248) &
% 16.43/15.96 ~ bnd_c6_2 X119 bnd_a248) &
% 16.43/15.96 bnd_c7_2 X119 bnd_a248 |
% 16.43/15.96 ~ bnd_c8_1 X119) |
% 16.43/15.96 bnd_c2_1 X119)) |
% 16.43/15.96 ((bnd_ndr1_0 & ~ bnd_c1_1 bnd_a249) &
% 16.43/15.96 ~ bnd_c7_1 bnd_a249) &
% 16.43/15.96 (ALL X120.
% 16.43/15.96 bnd_ndr1_1 bnd_a249 -->
% 16.43/15.96 (~ bnd_c4_2 bnd_a249 X120 |
% 16.43/15.96 ~ bnd_c2_2 bnd_a249 X120) |
% 16.43/15.96 bnd_c5_2 bnd_a249 X120))) &
% 16.43/15.96 (((ALL X121.
% 16.43/15.96 bnd_ndr1_0 -->
% 16.43/15.96 (bnd_c3_1 X121 |
% 16.43/15.96 ((bnd_ndr1_1 X121 &
% 16.43/15.96 bnd_c7_2 X121 bnd_a250) &
% 16.43/15.96 bnd_c8_2 X121 bnd_a250) &
% 16.43/15.96 bnd_c5_2 X121 bnd_a250) |
% 16.43/15.96 ((bnd_ndr1_1 X121 &
% 16.43/15.96 ~ bnd_c8_2 X121 bnd_a251) &
% 16.43/15.96 ~ bnd_c2_2 X121 bnd_a251) &
% 16.43/15.96 ~ bnd_c3_2 X121 bnd_a251) |
% 16.43/15.96 bnd_c8_0) |
% 16.43/15.96 ~ bnd_c6_0)) &
% 16.43/15.96 ((((bnd_ndr1_0 & bnd_c1_1 bnd_a252) &
% 16.43/15.96 ~ bnd_c7_1 bnd_a252) &
% 16.43/15.96 (ALL X122.
% 16.43/15.96 bnd_ndr1_1 bnd_a252 -->
% 16.43/15.96 (bnd_c5_2 bnd_a252 X122 |
% 16.43/15.96 ~ bnd_c2_2 bnd_a252 X122) |
% 16.43/15.96 ~ bnd_c4_2 bnd_a252 X122) |
% 16.43/15.96 ~ bnd_c4_0) |
% 16.43/15.96 (ALL X123. bnd_ndr1_0 --> ~ bnd_c8_1 X123))) &
% 16.43/15.96 (((ALL X124.
% 16.43/15.96 bnd_ndr1_0 -->
% 16.43/15.96 bnd_c1_1 X124 | ~ bnd_c3_1 X124) |
% 16.43/15.96 ((bnd_ndr1_0 & ~ bnd_c8_1 bnd_a253) &
% 16.43/15.96 ~ bnd_c7_1 bnd_a253) &
% 16.43/15.96 (ALL X125.
% 16.43/15.96 bnd_ndr1_1 bnd_a253 -->
% 16.43/15.96 (bnd_c2_2 bnd_a253 X125 |
% 16.43/15.96 bnd_c3_2 bnd_a253 X125) |
% 16.43/15.96 bnd_c5_2 bnd_a253 X125)) |
% 16.43/15.96 (ALL X126.
% 16.43/15.96 bnd_ndr1_0 -->
% 16.43/15.96 (((bnd_ndr1_1 X126 &
% 16.43/15.96 ~ bnd_c5_2 X126 bnd_a254) &
% 16.43/15.96 ~ bnd_c6_2 X126 bnd_a254) &
% 16.43/15.96 bnd_c1_2 X126 bnd_a254 |
% 16.43/15.96 bnd_c5_1 X126) |
% 16.43/15.96 ((bnd_ndr1_1 X126 &
% 16.43/15.96 ~ bnd_c3_2 X126 bnd_a255) &
% 16.43/15.96 ~ bnd_c8_2 X126 bnd_a255) &
% 16.43/15.96 bnd_c7_2 X126 bnd_a255))) &
% 16.43/15.96 ((bnd_c4_0 | ~ bnd_c6_0) |
% 16.43/15.96 (ALL X127.
% 16.43/15.96 bnd_ndr1_0 -->
% 16.43/15.96 (bnd_c8_1 X127 | ~ bnd_c6_1 X127) |
% 16.43/15.96 (ALL X128.
% 16.43/15.96 bnd_ndr1_1 X127 -->
% 16.43/15.96 (~ bnd_c1_2 X127 X128 |
% 16.43/15.96 bnd_c4_2 X127 X128) |
% 16.43/15.96 bnd_c6_2 X127 X128)))) &
% 16.43/15.96 ((~ bnd_c1_0 | bnd_c4_0) | ~ bnd_c6_0)) &
% 16.43/15.96 ((((((bnd_ndr1_0 & bnd_c1_1 bnd_a256) &
% 16.43/15.96 (ALL X129.
% 16.43/15.96 bnd_ndr1_1 bnd_a256 -->
% 16.43/15.96 (~ bnd_c3_2 bnd_a256 X129 |
% 16.43/15.96 ~ bnd_c5_2 bnd_a256 X129) |
% 16.43/15.96 ~ bnd_c4_2 bnd_a256 X129)) &
% 16.43/15.96 bnd_ndr1_1 bnd_a256) &
% 16.43/15.96 ~ bnd_c1_2 bnd_a256 bnd_a257) &
% 16.43/15.96 ~ bnd_c7_2 bnd_a256 bnd_a257 |
% 16.43/15.96 (ALL X130.
% 16.43/15.96 bnd_ndr1_0 -->
% 16.43/15.96 (~ bnd_c5_1 X130 | bnd_c1_1 X130) |
% 16.43/15.96 bnd_c3_1 X130)) |
% 16.43/15.96 bnd_c6_0)) &
% 16.43/15.96 ((bnd_c7_0 |
% 16.43/15.96 (ALL X131.
% 16.43/15.96 bnd_ndr1_0 -->
% 16.43/15.96 (~ bnd_c7_1 X131 |
% 16.43/15.96 ((bnd_ndr1_1 X131 &
% 16.43/15.96 ~ bnd_c7_2 X131 bnd_a258) &
% 16.43/15.96 bnd_c3_2 X131 bnd_a258) &
% 16.43/15.96 bnd_c4_2 X131 bnd_a258) |
% 16.43/15.96 bnd_c1_1 X131)) |
% 16.43/15.96 ((bnd_ndr1_0 &
% 16.43/15.96 (ALL X132.
% 16.43/15.96 bnd_ndr1_1 bnd_a259 -->
% 16.43/15.96 (bnd_c1_2 bnd_a259 X132 |
% 16.43/15.96 bnd_c8_2 bnd_a259 X132) |
% 16.43/15.96 bnd_c3_2 bnd_a259 X132)) &
% 16.43/15.96 bnd_c6_1 bnd_a259) &
% 16.43/15.96 ~ bnd_c7_1 bnd_a259)) &
% 16.43/15.96 ((bnd_c6_0 | bnd_c5_0) |
% 16.43/15.96 (ALL X133.
% 16.43/15.96 bnd_ndr1_0 -->
% 16.43/15.96 ((ALL X134.
% 16.43/15.96 bnd_ndr1_1 X133 -->
% 16.43/15.96 (~ bnd_c7_2 X133 X134 |
% 16.43/15.96 bnd_c8_2 X133 X134) |
% 16.43/15.96 bnd_c1_2 X133 X134) |
% 16.43/15.96 ((bnd_ndr1_1 X133 & ~ bnd_c7_2 X133 bnd_a260) &
% 16.43/15.96 ~ bnd_c2_2 X133 bnd_a260) &
% 16.43/15.96 ~ bnd_c1_2 X133 bnd_a260) |
% 16.43/15.96 ((bnd_ndr1_1 X133 & ~ bnd_c6_2 X133 bnd_a261) &
% 16.43/15.96 bnd_c2_2 X133 bnd_a261) &
% 16.43/15.96 bnd_c1_2 X133 bnd_a261))) &
% 16.43/15.96 (bnd_c1_0 | bnd_c4_0)) &
% 16.43/15.96 (((ALL X135.
% 16.43/15.96 bnd_ndr1_0 -->
% 16.43/15.96 (bnd_c2_1 X135 |
% 16.43/15.96 ((bnd_ndr1_1 X135 & bnd_c4_2 X135 bnd_a262) &
% 16.43/15.96 ~ bnd_c2_2 X135 bnd_a262) &
% 16.43/15.96 bnd_c1_2 X135 bnd_a262) |
% 16.43/15.96 (ALL X136.
% 16.43/15.96 bnd_ndr1_1 X135 -->
% 16.43/15.96 (bnd_c5_2 X135 X136 | bnd_c1_2 X135 X136) |
% 16.43/15.96 ~ bnd_c3_2 X135 X136)) |
% 16.43/15.96 ~ bnd_c6_0) |
% 16.43/15.96 bnd_c1_0)) &
% 16.43/15.96 (((ALL X137.
% 16.43/15.96 bnd_ndr1_0 -->
% 16.43/15.96 bnd_c3_1 X137 |
% 16.43/15.96 (ALL X138.
% 16.43/15.96 bnd_ndr1_1 X137 -->
% 16.43/15.96 (~ bnd_c3_2 X137 X138 |
% 16.43/15.96 ~ bnd_c2_2 X137 X138) |
% 16.43/15.96 ~ bnd_c4_2 X137 X138)) |
% 16.43/15.96 bnd_c1_0) |
% 16.43/15.96 ~ bnd_c7_0)) &
% 16.43/15.96 ((~ bnd_c7_0 |
% 16.43/15.96 (ALL X139.
% 16.43/15.96 bnd_ndr1_0 -->
% 16.43/15.96 ((ALL X140.
% 16.43/15.96 bnd_ndr1_1 X139 -->
% 16.43/15.96 (~ bnd_c8_2 X139 X140 | bnd_c3_2 X139 X140) |
% 16.43/15.96 ~ bnd_c5_2 X139 X140) |
% 16.43/15.96 ~ bnd_c7_1 X139) |
% 16.43/15.96 bnd_c2_1 X139)) |
% 16.43/15.96 bnd_c5_0)) &
% 16.43/15.96 ((~ bnd_c5_0 |
% 16.43/15.96 (ALL X141.
% 16.43/15.96 bnd_ndr1_0 -->
% 16.43/15.96 (((bnd_ndr1_1 X141 & ~ bnd_c5_2 X141 bnd_a263) &
% 16.43/15.96 ~ bnd_c7_2 X141 bnd_a263) &
% 16.43/15.96 bnd_c4_2 X141 bnd_a263 |
% 16.43/15.96 ~ bnd_c6_1 X141) |
% 16.43/15.96 ((bnd_ndr1_1 X141 & bnd_c5_2 X141 bnd_a264) &
% 16.43/15.96 bnd_c1_2 X141 bnd_a264) &
% 16.43/15.96 bnd_c7_2 X141 bnd_a264)) |
% 16.43/15.96 ~ bnd_c3_0)) &
% 16.43/15.96 (((ALL X142.
% 16.43/15.96 bnd_ndr1_0 --> bnd_c4_1 X142 | ~ bnd_c5_1 X142) |
% 16.43/15.96 bnd_c2_0) |
% 16.43/15.96 (ALL X143.
% 16.43/15.96 bnd_ndr1_0 --> ~ bnd_c2_1 X143 | ~ bnd_c7_1 X143))) &
% 16.43/15.96 ((bnd_c7_0 |
% 16.43/15.96 (((((bnd_ndr1_0 & ~ bnd_c6_1 bnd_a265) &
% 16.43/15.96 (ALL X144.
% 16.43/15.96 bnd_ndr1_1 bnd_a265 -->
% 16.43/15.96 ~ bnd_c4_2 bnd_a265 X144 |
% 16.43/15.96 bnd_c7_2 bnd_a265 X144)) &
% 16.43/15.96 bnd_ndr1_1 bnd_a265) &
% 16.43/15.96 bnd_c4_2 bnd_a265 bnd_a266) &
% 16.43/15.96 bnd_c2_2 bnd_a265 bnd_a266) &
% 16.43/15.96 ~ bnd_c8_2 bnd_a265 bnd_a266) |
% 16.43/15.96 bnd_ndr1_0 &
% 16.43/15.96 (ALL X145.
% 16.43/15.96 bnd_ndr1_1 bnd_a267 -->
% 16.43/15.96 bnd_c6_2 bnd_a267 X145 | bnd_c3_2 bnd_a267 X145))) &
% 16.43/15.96 ((bnd_c4_0 |
% 16.43/15.96 ((((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a268) &
% 16.43/15.96 ~ bnd_c6_2 bnd_a268 bnd_a269) &
% 16.43/15.96 bnd_c2_2 bnd_a268 bnd_a269) &
% 16.43/15.96 bnd_c5_2 bnd_a268 bnd_a269) &
% 16.43/15.96 bnd_ndr1_1 bnd_a268) &
% 16.43/15.96 bnd_c6_2 bnd_a268 bnd_a270) &
% 16.43/15.96 bnd_c8_2 bnd_a268 bnd_a270) &
% 16.43/15.96 bnd_c1_2 bnd_a268 bnd_a270) &
% 16.43/15.96 ~ bnd_c7_1 bnd_a268) |
% 16.43/15.96 bnd_c5_0)) &
% 16.43/15.96 ((((((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a271) &
% 16.43/15.96 ~ bnd_c7_2 bnd_a271 bnd_a272) &
% 16.43/15.96 bnd_c2_2 bnd_a271 bnd_a272) &
% 16.43/15.96 bnd_c1_2 bnd_a271 bnd_a272) &
% 16.43/15.96 bnd_c5_1 bnd_a271) &
% 16.43/15.96 bnd_ndr1_1 bnd_a271) &
% 16.43/15.96 ~ bnd_c3_2 bnd_a271 bnd_a273) &
% 16.43/15.96 ~ bnd_c4_2 bnd_a271 bnd_a273) &
% 16.43/15.96 bnd_c1_2 bnd_a271 bnd_a273 |
% 16.43/15.96 ((bnd_ndr1_0 &
% 16.43/15.96 (ALL X146.
% 16.43/15.96 bnd_ndr1_1 bnd_a274 -->
% 16.43/15.96 (~ bnd_c7_2 bnd_a274 X146 |
% 16.43/15.96 ~ bnd_c4_2 bnd_a274 X146) |
% 16.43/15.96 bnd_c5_2 bnd_a274 X146)) &
% 16.43/15.96 (ALL X147.
% 16.43/15.96 bnd_ndr1_1 bnd_a274 -->
% 16.43/15.96 (~ bnd_c1_2 bnd_a274 X147 | ~ bnd_c5_2 bnd_a274 X147) |
% 16.43/15.96 ~ bnd_c6_2 bnd_a274 X147)) &
% 16.43/15.96 ~ bnd_c7_1 bnd_a274) |
% 16.43/15.96 (ALL X148.
% 16.43/15.96 bnd_ndr1_0 -->
% 16.43/15.96 ~ bnd_c1_1 X148 |
% 16.43/15.96 (ALL X149.
% 16.43/15.96 bnd_ndr1_1 X148 -->
% 16.43/15.96 bnd_c5_2 X148 X149 | ~ bnd_c6_2 X148 X149)))) &
% 16.43/15.96 (((((((bnd_ndr1_0 &
% 16.43/15.96 (ALL X150.
% 16.43/15.96 bnd_ndr1_1 bnd_a275 -->
% 16.43/15.96 (~ bnd_c7_2 bnd_a275 X150 |
% 16.43/15.96 bnd_c5_2 bnd_a275 X150) |
% 16.43/15.96 ~ bnd_c2_2 bnd_a275 X150)) &
% 16.43/15.96 bnd_ndr1_1 bnd_a275) &
% 16.43/15.96 bnd_c2_2 bnd_a275 bnd_a276) &
% 16.43/15.96 bnd_c7_2 bnd_a275 bnd_a276) &
% 16.43/15.96 ~ bnd_c3_2 bnd_a275 bnd_a276) &
% 16.43/15.96 ~ bnd_c1_1 bnd_a275 |
% 16.43/15.96 bnd_c4_0) |
% 16.43/15.96 ((bnd_ndr1_0 &
% 16.43/15.96 (ALL X151.
% 16.43/15.96 bnd_ndr1_1 bnd_a277 -->
% 16.43/15.96 (~ bnd_c8_2 bnd_a277 X151 | bnd_c6_2 bnd_a277 X151) |
% 16.43/15.96 bnd_c4_2 bnd_a277 X151)) &
% 16.43/15.96 (ALL X152.
% 16.43/15.96 bnd_ndr1_1 bnd_a277 -->
% 16.43/15.96 (~ bnd_c1_2 bnd_a277 X152 | ~ bnd_c2_2 bnd_a277 X152) |
% 16.43/15.96 bnd_c7_2 bnd_a277 X152)) &
% 16.43/15.96 (ALL X153.
% 16.43/15.96 bnd_ndr1_1 bnd_a277 -->
% 16.43/15.96 ~ bnd_c6_2 bnd_a277 X153 | ~ bnd_c7_2 bnd_a277 X153))) &
% 16.43/15.96 (((ALL X154.
% 16.43/15.96 bnd_ndr1_0 -->
% 16.43/15.96 (bnd_c1_1 X154 |
% 16.43/15.96 (bnd_ndr1_1 X154 & ~ bnd_c3_2 X154 bnd_a278) &
% 16.43/15.96 bnd_c5_2 X154 bnd_a278) |
% 16.43/15.96 ~ bnd_c4_1 X154) |
% 16.43/15.96 bnd_c8_0) |
% 16.43/15.96 bnd_c7_0)) &
% 16.43/15.96 (((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a279) &
% 16.43/15.96 ~ bnd_c4_2 bnd_a279 bnd_a280) &
% 16.43/15.96 ~ bnd_c1_2 bnd_a279 bnd_a280) &
% 16.43/15.96 bnd_c8_2 bnd_a279 bnd_a280) &
% 16.43/15.96 (ALL X155.
% 16.43/15.96 bnd_ndr1_1 bnd_a279 -->
% 16.43/15.96 (bnd_c6_2 bnd_a279 X155 | ~ bnd_c5_2 bnd_a279 X155) |
% 16.43/15.96 bnd_c3_2 bnd_a279 X155)) &
% 16.43/15.96 bnd_c2_1 bnd_a279 |
% 16.43/15.96 ~ bnd_c1_0) |
% 16.43/15.96 ((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a281) &
% 16.43/15.96 bnd_c7_2 bnd_a281 bnd_a282) &
% 16.43/15.96 bnd_c8_2 bnd_a281 bnd_a282) &
% 16.43/15.96 bnd_c2_2 bnd_a281 bnd_a282) &
% 16.43/15.96 bnd_ndr1_1 bnd_a281) &
% 16.43/15.96 bnd_c8_2 bnd_a281 bnd_a283) &
% 16.43/15.96 ~ bnd_c1_2 bnd_a281 bnd_a283)) &
% 16.43/15.96 (((ALL X156.
% 16.43/15.96 bnd_ndr1_0 -->
% 16.43/15.96 (((bnd_ndr1_1 X156 & bnd_c3_2 X156 bnd_a284) &
% 16.43/15.96 bnd_c1_2 X156 bnd_a284) &
% 16.43/15.96 bnd_c5_2 X156 bnd_a284 |
% 16.43/15.96 ((bnd_ndr1_1 X156 & ~ bnd_c8_2 X156 bnd_a285) &
% 16.43/15.96 bnd_c3_2 X156 bnd_a285) &
% 16.43/15.96 ~ bnd_c7_2 X156 bnd_a285) |
% 16.43/15.96 (bnd_ndr1_1 X156 & ~ bnd_c7_2 X156 bnd_a286) &
% 16.43/15.96 ~ bnd_c1_2 X156 bnd_a286) |
% 16.43/15.96 bnd_c6_0) |
% 16.43/15.96 (ALL X157.
% 16.43/15.96 bnd_ndr1_0 -->
% 16.43/15.96 (bnd_c1_1 X157 | ~ bnd_c8_1 X157) | bnd_c6_1 X157))) &
% 16.43/15.96 ((~ bnd_c3_0 | bnd_c4_0) |
% 16.43/15.96 (ALL X158.
% 16.43/15.96 bnd_ndr1_0 -->
% 16.43/15.96 (~ bnd_c8_1 X158 |
% 16.43/15.96 (ALL X159.
% 16.43/15.96 bnd_ndr1_1 X158 -->
% 16.43/15.96 (bnd_c8_2 X158 X159 | ~ bnd_c7_2 X158 X159) |
% 16.43/15.96 ~ bnd_c6_2 X158 X159)) |
% 16.43/15.96 bnd_c4_1 X158))) &
% 16.43/15.96 ((bnd_c2_0 | bnd_c8_0) | ~ bnd_c4_0)) &
% 16.43/15.96 ((bnd_c3_0 | bnd_c5_0) |
% 16.43/15.96 ((bnd_ndr1_0 & bnd_c3_1 bnd_a287) & ~ bnd_c5_1 bnd_a287) &
% 16.43/15.96 bnd_c8_1 bnd_a287)) &
% 16.43/15.96 (((ALL X160.
% 16.43/15.96 bnd_ndr1_0 -->
% 16.43/15.96 (bnd_c6_1 X160 |
% 16.43/15.96 (ALL X161.
% 16.43/15.96 bnd_ndr1_1 X160 -->
% 16.43/15.96 (~ bnd_c3_2 X160 X161 | bnd_c7_2 X160 X161) |
% 16.43/15.96 bnd_c5_2 X160 X161)) |
% 16.43/15.96 ~ bnd_c2_1 X160) |
% 16.43/15.96 (((((bnd_ndr1_0 & ~ bnd_c8_1 bnd_a288) & bnd_ndr1_1 bnd_a288) &
% 16.43/15.96 ~ bnd_c8_2 bnd_a288 bnd_a289) &
% 16.43/15.96 ~ bnd_c4_2 bnd_a288 bnd_a289) &
% 16.43/15.96 ~ bnd_c5_2 bnd_a288 bnd_a289) &
% 16.43/15.96 (ALL X162.
% 16.43/15.96 bnd_ndr1_1 bnd_a288 -->
% 16.43/15.96 (~ bnd_c8_2 bnd_a288 X162 | ~ bnd_c5_2 bnd_a288 X162) |
% 16.43/15.96 ~ bnd_c4_2 bnd_a288 X162)) |
% 16.43/15.96 (ALL X163.
% 16.43/15.96 bnd_ndr1_0 -->
% 16.43/15.96 (((bnd_ndr1_1 X163 & ~ bnd_c8_2 X163 bnd_a290) &
% 16.43/15.96 ~ bnd_c3_2 X163 bnd_a290) &
% 16.43/15.96 ~ bnd_c1_2 X163 bnd_a290 |
% 16.43/15.96 (ALL X164.
% 16.43/15.96 bnd_ndr1_1 X163 -->
% 16.43/15.96 (bnd_c7_2 X163 X164 | bnd_c5_2 X163 X164) |
% 16.43/15.96 bnd_c3_2 X163 X164)) |
% 16.43/15.96 ((bnd_ndr1_1 X163 & bnd_c7_2 X163 bnd_a291) &
% 16.43/15.96 bnd_c2_2 X163 bnd_a291) &
% 16.43/15.96 ~ bnd_c4_2 X163 bnd_a291))) &
% 16.43/15.96 ((~ bnd_c2_0 |
% 16.43/15.96 (ALL X165.
% 16.43/15.96 bnd_ndr1_0 -->
% 16.43/15.96 (((bnd_ndr1_1 X165 & ~ bnd_c5_2 X165 bnd_a292) &
% 16.43/15.96 bnd_c7_2 X165 bnd_a292) &
% 16.43/15.96 bnd_c8_2 X165 bnd_a292 |
% 16.43/15.96 ((bnd_ndr1_1 X165 & bnd_c4_2 X165 bnd_a293) &
% 16.43/15.96 ~ bnd_c3_2 X165 bnd_a293) &
% 16.43/15.96 ~ bnd_c1_2 X165 bnd_a293) |
% 16.43/15.96 bnd_c4_1 X165)) |
% 16.43/15.96 ~ bnd_c4_0)) &
% 16.43/15.96 (bnd_c1_0 |
% 16.43/15.96 (((((bnd_ndr1_0 & bnd_c2_1 bnd_a294) & ~ bnd_c3_1 bnd_a294) &
% 16.43/15.96 bnd_ndr1_1 bnd_a294) &
% 16.43/15.96 ~ bnd_c2_2 bnd_a294 bnd_a295) &
% 16.43/15.96 ~ bnd_c8_2 bnd_a294 bnd_a295) &
% 16.43/15.96 bnd_c7_2 bnd_a294 bnd_a295)) &
% 16.43/15.96 ((bnd_c6_0 |
% 16.43/15.96 (((((bnd_ndr1_0 &
% 16.43/15.96 (ALL X166.
% 16.43/15.96 bnd_ndr1_1 bnd_a296 -->
% 16.43/15.96 (bnd_c2_2 bnd_a296 X166 | ~ bnd_c6_2 bnd_a296 X166) |
% 16.43/15.96 ~ bnd_c7_2 bnd_a296 X166)) &
% 16.43/15.96 bnd_ndr1_1 bnd_a296) &
% 16.43/15.96 ~ bnd_c7_2 bnd_a296 bnd_a297) &
% 16.43/15.96 ~ bnd_c2_2 bnd_a296 bnd_a297) &
% 16.43/15.96 bnd_c5_2 bnd_a296 bnd_a297) &
% 16.43/15.96 ~ bnd_c7_1 bnd_a296) |
% 16.43/15.96 (ALL X167.
% 16.43/15.96 bnd_ndr1_0 --> (bnd_c3_1 X167 | bnd_c4_1 X167) | bnd_c5_1 X167)))
% 16.43/15.96 Adding axioms...
% 16.43/15.97 Typedef.type_definition_def
% 44.98/44.49 ...done.
% 45.08/44.52 Ground types: ?'b, TPTP_Interpret.ind
% 45.08/44.52 Translating term (sizes: 1, 1) ...
% 68.45/67.86 Invoking SAT solver...
% 68.45/67.86 No model exists.
% 68.45/67.86 Translating term (sizes: 2, 1) ...
% 92.50/91.87 Invoking SAT solver...
% 92.50/91.88 No model exists.
% 92.50/91.88 Translating term (sizes: 1, 2) ...
% 135.67/134.85 Invoking SAT solver...
% 136.18/135.35 Model found:
% 136.18/135.35 Size of types: ?'b: 1, TPTP_Interpret.ind: 2
% 136.18/135.35 bnd_a297: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a296: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a295: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a294: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a293: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a292: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a291: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a290: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a289: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a288: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a287: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a286: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a285: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a284: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a283: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a282: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a281: ??.TPTP_Interpret.ind1
% 136.18/135.35 bnd_a280: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a279: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a278: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a277: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a276: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a275: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a274: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a273: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a272: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a271: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a270: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a269: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a268: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a267: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a266: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a265: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a264: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a263: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a262: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a261: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a260: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a259: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a258: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a257: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a256: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a255: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a254: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a253: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a252: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a251: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a250: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a249: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a248: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a247: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a246: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a245: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a244: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a243: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a242: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a241: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a240: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a239: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a238: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a237: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a236: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a235: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a234: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a233: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a232: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a231: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a230: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a229: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a228: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a227: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a226: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a225: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a224: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a223: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a222: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a221: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a220: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a219: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a218: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a217: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a216: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a215: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a214: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a213: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a212: ??.TPTP_Interpret.ind1
% 136.18/135.35 bnd_a211: ??.TPTP_Interpret.ind1
% 136.18/135.35 bnd_a210: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a209: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a208: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a207: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a206: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a205: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a204: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a203: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a202: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a201: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a200: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a199: ??.TPTP_Interpret.ind1
% 136.18/135.35 bnd_a198: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a197: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a196: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a195: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a194: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a193: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a192: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a191: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a190: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a189: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a188: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a187: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a186: ??.TPTP_Interpret.ind1
% 136.18/135.35 bnd_a185: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a184: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a183: ??.TPTP_Interpret.ind1
% 136.18/135.35 bnd_a182: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a181: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a180: ??.TPTP_Interpret.ind1
% 136.18/135.35 bnd_a179: ??.TPTP_Interpret.ind1
% 136.18/135.35 bnd_a178: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a177: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a176: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a175: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a174: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a173: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a172: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a171: ??.TPTP_Interpret.ind1
% 136.18/135.35 bnd_c6_0: False
% 136.18/135.35 bnd_a170: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a169: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a168: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a167: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a166: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a165: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a164: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a163: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a162: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a161: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_c6_2: {(??.TPTP_Interpret.ind0,
% 136.18/135.35 {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, False)}),
% 136.18/135.35 (??.TPTP_Interpret.ind1,
% 136.18/135.35 {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, True)})}
% 136.18/135.35 bnd_a160: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a159: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_c5_0: True
% 136.18/135.35 bnd_a158: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a157: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_a156: ??.TPTP_Interpret.ind1
% 136.18/135.35 bnd_c7_1: {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, False)}
% 136.18/135.35 bnd_a155: ??.TPTP_Interpret.ind1
% 136.18/135.35 bnd_a154: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_c1_1: {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, True)}
% 136.18/135.35 bnd_a153: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_c4_1: {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, True)}
% 136.18/135.35 bnd_a152: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_c5_1: {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, False)}
% 136.18/135.35 bnd_a151: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_c3_1: {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, False)}
% 136.18/135.35 bnd_c2_1: {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, False)}
% 136.18/135.35 bnd_c4_0: False
% 136.18/135.35 bnd_c8_1: {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, False)}
% 136.18/135.35 bnd_c6_1: {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, False)}
% 136.18/135.35 bnd_c7_0: False
% 136.18/135.35 bnd_a150: ??.TPTP_Interpret.ind1
% 136.18/135.35 bnd_c8_2: {(??.TPTP_Interpret.ind0,
% 136.18/135.35 {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, False)}),
% 136.18/135.35 (??.TPTP_Interpret.ind1,
% 136.18/135.35 {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, False)})}
% 136.18/135.35 bnd_c2_2: {(??.TPTP_Interpret.ind0,
% 136.18/135.35 {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, True)}),
% 136.18/135.35 (??.TPTP_Interpret.ind1,
% 136.18/135.35 {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, True)})}
% 136.18/135.35 bnd_a149: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_c1_2: {(??.TPTP_Interpret.ind0,
% 136.18/135.35 {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, False)}),
% 136.18/135.35 (??.TPTP_Interpret.ind1,
% 136.18/135.35 {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, False)})}
% 136.18/135.35 bnd_a148: ??.TPTP_Interpret.ind1
% 136.18/135.35 bnd_c2_0: False
% 136.18/135.35 bnd_c1_0: True
% 136.18/135.35 bnd_c8_0: True
% 136.18/135.35 bnd_c5_2: {(??.TPTP_Interpret.ind0,
% 136.18/135.35 {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, True)}),
% 136.18/135.35 (??.TPTP_Interpret.ind1,
% 136.18/135.35 {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, False)})}
% 136.18/135.35 bnd_a147: ??.TPTP_Interpret.ind0
% 136.18/135.35 bnd_c7_2: {(??.TPTP_Interpret.ind0,
% 136.18/135.35 {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, True)}),
% 136.18/135.35 (??.TPTP_Interpret.ind1,
% 136.18/135.35 {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, True)})}
% 136.18/135.35 bnd_c4_2: {(??.TPTP_Interpret.ind0,
% 136.18/135.35 {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, False)}),
% 136.18/135.35 (??.TPTP_Interpret.ind1,
% 136.18/135.35 {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, False)})}
% 136.18/135.35 bnd_c3_2: {(??.TPTP_Interpret.ind0,
% 136.18/135.35 {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, False)}),
% 136.18/135.35 (??.TPTP_Interpret.ind1,
% 136.18/135.35 {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, True)})}
% 136.18/135.35 bnd_ndr1_1: {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, True)}
% 136.18/135.35 bnd_ndr1_0: True
% 136.18/135.35 bnd_c3_0: True
% 136.18/135.35
% 136.18/135.35 % SZS status CounterSatisfiable
%------------------------------------------------------------------------------