TSTP Solution File: SYN536+1 by Refute---2015
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%------------------------------------------------------------------------------
% File : Refute---2015
% Problem : SYN536+1 : TPTP v6.4.0. Released v2.1.0.
% Transfm : none
% Format : tptp:raw
% Command : isabelle tptp_refute %d %s
% Computer : n117.star.cs.uiowa.edu
% Model : x86_64 x86_64
% CPU : Intel(R) Xeon(R) CPU E5-2609 0 2.40GHz
% Memory : 32218.75MB
% OS : Linux 3.10.0-327.10.1.el7.x86_64
% CPULimit : 300s
% DateTime : Thu Apr 14 06:42:17 EDT 2016
% Result : CounterSatisfiable 17.54s
% Output : Assurance 0s
% Verified :
% SZS Type : None (Parsing solution fails)
% Syntax : Number of formulae : 0
% Comments :
%------------------------------------------------------------------------------
%----No solution output by system
%------------------------------------------------------------------------------
%----ORIGINAL SYSTEM OUTPUT
% 0.00/0.03 % Problem : SYN536+1 : TPTP v6.4.0. Released v2.1.0.
% 0.00/0.04 % Command : isabelle tptp_refute %d %s
% 0.02/0.22 % Computer : n117.star.cs.uiowa.edu
% 0.02/0.22 % Model : x86_64 x86_64
% 0.02/0.22 % CPU : Intel(R) Xeon(R) CPU E5-2609 0 @ 2.40GHz
% 0.02/0.22 % Memory : 32218.75MB
% 0.02/0.22 % OS : Linux 3.10.0-327.10.1.el7.x86_64
% 0.02/0.22 % CPULimit : 300
% 0.02/0.22 % DateTime : Sat Apr 9 00:14:54 CDT 2016
% 0.02/0.23 % CPUTime:
% 6.32/5.83 > val it = (): unit
% 6.62/6.12 Trying to find a model that refutes: ~ (((((((((((((((((((((ALL U.
% 6.62/6.12 bnd_ndr1_0 -->
% 6.62/6.12 bnd_c5_1 U |
% 6.62/6.12 (ALL V.
% 6.62/6.12 bnd_ndr1_1 U -->
% 6.62/6.12 bnd_c3_2 U V | ~ bnd_c2_2 U V)) |
% 6.62/6.12 ~ bnd_c4_0) |
% 6.62/6.12 bnd_c2_0) &
% 6.62/6.12 ((((bnd_ndr1_0 & ~ bnd_c5_1 bnd_a520) &
% 6.62/6.12 (ALL W.
% 6.62/6.12 bnd_ndr1_1 bnd_a520 -->
% 6.62/6.12 (~ bnd_c1_2 bnd_a520 W | ~ bnd_c5_2 bnd_a520 W) |
% 6.62/6.12 ~ bnd_c3_2 bnd_a520 W)) &
% 6.62/6.12 bnd_c1_1 bnd_a520 |
% 6.62/6.12 bnd_c5_0) |
% 6.62/6.12 bnd_c3_0)) &
% 6.62/6.12 (((bnd_ndr1_0 & ~ bnd_c2_1 bnd_a521) &
% 6.62/6.12 (ALL X.
% 6.62/6.12 bnd_ndr1_1 bnd_a521 -->
% 6.62/6.12 (bnd_c1_2 bnd_a521 X | ~ bnd_c2_2 bnd_a521 X) |
% 6.62/6.12 ~ bnd_c5_2 bnd_a521 X)) &
% 6.62/6.12 ~ bnd_c1_1 bnd_a521 |
% 6.62/6.12 (ALL Y.
% 6.62/6.12 bnd_ndr1_0 -->
% 6.62/6.12 ((bnd_ndr1_1 Y & bnd_c5_2 Y bnd_a522) &
% 6.62/6.12 bnd_c2_2 Y bnd_a522 |
% 6.62/6.12 ~ bnd_c3_1 Y) |
% 6.62/6.12 bnd_c5_1 Y))) &
% 6.62/6.12 (((ALL Z.
% 6.62/6.12 bnd_ndr1_0 -->
% 6.62/6.12 ((bnd_ndr1_1 Z & ~ bnd_c3_2 Z bnd_a523) &
% 6.62/6.12 ~ bnd_c1_2 Z bnd_a523 |
% 6.62/6.12 (ALL X1.
% 6.62/6.12 bnd_ndr1_1 Z -->
% 6.62/6.12 (bnd_c1_2 Z X1 | bnd_c2_2 Z X1) |
% 6.62/6.12 bnd_c3_2 Z X1)) |
% 6.62/6.12 bnd_c4_1 Z) |
% 6.62/6.12 (ALL X2.
% 6.62/6.12 bnd_ndr1_0 -->
% 6.62/6.12 ((ALL X3.
% 6.62/6.12 bnd_ndr1_1 X2 -->
% 6.62/6.12 (~ bnd_c1_2 X2 X3 | ~ bnd_c2_2 X2 X3) |
% 6.62/6.12 ~ bnd_c3_2 X2 X3) |
% 6.62/6.12 ((bnd_ndr1_1 X2 & bnd_c1_2 X2 bnd_a524) &
% 6.62/6.12 bnd_c5_2 X2 bnd_a524) &
% 6.62/6.12 ~ bnd_c4_2 X2 bnd_a524) |
% 6.62/6.12 bnd_c4_1 X2)) |
% 6.62/6.12 ~ bnd_c3_0)) &
% 6.62/6.12 ((bnd_c4_0 | bnd_c1_0) | bnd_c5_0)) &
% 6.62/6.12 (~ bnd_c2_0 |
% 6.62/6.12 (((((bnd_ndr1_0 & ~ bnd_c2_1 bnd_a525) &
% 6.62/6.12 bnd_ndr1_1 bnd_a525) &
% 6.62/6.12 ~ bnd_c1_2 bnd_a525 bnd_a526) &
% 6.62/6.12 bnd_c2_2 bnd_a525 bnd_a526) &
% 6.62/6.12 bnd_c4_2 bnd_a525 bnd_a526) &
% 6.62/6.12 bnd_c3_1 bnd_a525)) &
% 6.62/6.12 ((((((bnd_ndr1_0 & bnd_c5_1 bnd_a527) &
% 6.62/6.12 bnd_ndr1_1 bnd_a527) &
% 6.62/6.12 ~ bnd_c3_2 bnd_a527 bnd_a528) &
% 6.62/6.12 bnd_c1_2 bnd_a527 bnd_a528) &
% 6.62/6.12 ~ bnd_c3_1 bnd_a527 |
% 6.62/6.12 (((((((bnd_ndr1_0 & bnd_c4_1 bnd_a529) &
% 6.62/6.12 bnd_ndr1_1 bnd_a529) &
% 6.62/6.12 bnd_c5_2 bnd_a529 bnd_a530) &
% 6.62/6.12 bnd_c4_2 bnd_a529 bnd_a530) &
% 6.62/6.12 bnd_c1_2 bnd_a529 bnd_a530) &
% 6.62/6.12 bnd_ndr1_1 bnd_a529) &
% 6.62/6.12 bnd_c1_2 bnd_a529 bnd_a531) &
% 6.62/6.12 bnd_c5_2 bnd_a529 bnd_a531) |
% 6.62/6.12 ~ bnd_c4_0)) &
% 6.62/6.12 (bnd_c2_0 | ~ bnd_c5_0)) &
% 6.62/6.12 (((ALL X4.
% 6.62/6.12 bnd_ndr1_0 -->
% 6.62/6.12 ((ALL X5.
% 6.62/6.12 bnd_ndr1_1 X4 -->
% 6.62/6.12 (bnd_c2_2 X4 X5 | bnd_c4_2 X4 X5) |
% 6.62/6.12 ~ bnd_c3_2 X4 X5) |
% 6.62/6.12 (ALL X6.
% 6.62/6.12 bnd_ndr1_1 X4 -->
% 6.62/6.12 ~ bnd_c1_2 X4 X6 | bnd_c4_2 X4 X6)) |
% 6.62/6.12 (ALL X7.
% 6.62/6.12 bnd_ndr1_1 X4 -->
% 6.62/6.12 (~ bnd_c3_2 X4 X7 | ~ bnd_c5_2 X4 X7) |
% 6.62/6.12 bnd_c4_2 X4 X7)) |
% 6.62/6.12 (ALL X8. bnd_ndr1_0 --> bnd_c2_1 X8 | ~ bnd_c5_1 X8)) |
% 6.62/6.12 bnd_c1_0)) &
% 6.62/6.12 (((ALL X9.
% 6.62/6.12 bnd_ndr1_0 -->
% 6.62/6.12 ((bnd_ndr1_1 X9 & bnd_c4_2 X9 bnd_a532) &
% 6.62/6.12 ~ bnd_c3_2 X9 bnd_a532) &
% 6.62/6.13 ~ bnd_c5_2 X9 bnd_a532 |
% 6.62/6.13 bnd_c1_1 X9) |
% 6.62/6.13 (bnd_ndr1_0 &
% 6.62/6.13 (ALL X10.
% 6.62/6.13 bnd_ndr1_1 bnd_a533 -->
% 6.62/6.13 (bnd_c4_2 bnd_a533 X10 | bnd_c5_2 bnd_a533 X10) |
% 6.62/6.13 ~ bnd_c3_2 bnd_a533 X10)) &
% 6.62/6.13 ~ bnd_c3_1 bnd_a533) |
% 6.62/6.13 ~ bnd_c2_0)) &
% 6.62/6.13 ((bnd_c5_0 |
% 6.62/6.13 (ALL X11.
% 6.62/6.13 bnd_ndr1_0 -->
% 6.62/6.13 (bnd_c1_1 X11 | bnd_c5_1 X11) | bnd_c4_1 X11)) |
% 6.62/6.13 (ALL X12.
% 6.62/6.13 bnd_ndr1_0 -->
% 6.62/6.13 ((ALL X13.
% 6.62/6.13 bnd_ndr1_1 X12 -->
% 6.62/6.13 (bnd_c3_2 X12 X13 | bnd_c1_2 X12 X13) |
% 6.62/6.13 bnd_c4_2 X12 X13) |
% 6.62/6.13 (bnd_ndr1_1 X12 & bnd_c4_2 X12 bnd_a534) &
% 6.62/6.13 ~ bnd_c3_2 X12 bnd_a534) |
% 6.62/6.13 bnd_c3_1 X12))) &
% 6.62/6.13 ((~ bnd_c1_0 | ~ bnd_c3_0) |
% 6.62/6.13 (ALL X14.
% 6.62/6.13 bnd_ndr1_0 -->
% 6.62/6.13 (ALL X15.
% 6.62/6.13 bnd_ndr1_1 X14 --> bnd_c3_2 X14 X15 | bnd_c2_2 X14 X15) |
% 6.62/6.13 bnd_c5_1 X14))) &
% 6.62/6.13 (bnd_c5_0 | ~ bnd_c3_0)) &
% 6.62/6.13 ((~ bnd_c4_0 |
% 6.62/6.13 (ALL X16.
% 6.62/6.13 bnd_ndr1_0 -->
% 6.62/6.13 (bnd_c1_1 X16 |
% 6.62/6.13 (bnd_ndr1_1 X16 & ~ bnd_c4_2 X16 bnd_a535) &
% 6.62/6.13 ~ bnd_c3_2 X16 bnd_a535) |
% 6.62/6.13 bnd_c4_1 X16)) |
% 6.62/6.13 (ALL X17.
% 6.62/6.13 bnd_ndr1_0 -->
% 6.62/6.13 (ALL X18.
% 6.62/6.13 bnd_ndr1_1 X17 -->
% 6.62/6.13 (bnd_c4_2 X17 X18 | bnd_c1_2 X17 X18) |
% 6.62/6.13 ~ bnd_c3_2 X17 X18) |
% 6.62/6.13 bnd_c5_1 X17))) &
% 6.62/6.13 ((((bnd_ndr1_0 &
% 6.62/6.13 (ALL X19.
% 6.62/6.13 bnd_ndr1_1 bnd_a536 -->
% 6.62/6.13 bnd_c4_2 bnd_a536 X19 | bnd_c2_2 bnd_a536 X19)) &
% 6.62/6.13 ~ bnd_c5_1 bnd_a536) &
% 6.62/6.13 ~ bnd_c1_1 bnd_a536 |
% 6.62/6.13 bnd_c2_0) |
% 6.62/6.13 ~ bnd_c3_0)) &
% 6.62/6.13 ((~ bnd_c2_0 |
% 6.62/6.13 (((bnd_ndr1_0 & bnd_ndr1_1 bnd_a537) & bnd_c2_2 bnd_a537 bnd_a538) &
% 6.62/6.13 bnd_c3_2 bnd_a537 bnd_a538) &
% 6.62/6.13 ~ bnd_c5_1 bnd_a537) |
% 6.62/6.13 (ALL X20.
% 6.62/6.13 bnd_ndr1_0 -->
% 6.62/6.13 (bnd_c4_1 X20 |
% 6.62/6.13 (ALL X21.
% 6.62/6.13 bnd_ndr1_1 X20 -->
% 6.62/6.13 (~ bnd_c1_2 X20 X21 | bnd_c3_2 X20 X21) |
% 6.62/6.13 ~ bnd_c5_2 X20 X21)) |
% 6.62/6.13 ((bnd_ndr1_1 X20 & bnd_c2_2 X20 bnd_a539) &
% 6.62/6.13 bnd_c1_2 X20 bnd_a539) &
% 6.62/6.13 bnd_c5_2 X20 bnd_a539))) &
% 6.62/6.13 ((((bnd_ndr1_0 & bnd_c3_1 bnd_a540) & ~ bnd_c4_1 bnd_a540) &
% 6.62/6.13 (ALL X22.
% 6.62/6.13 bnd_ndr1_1 bnd_a540 -->
% 6.62/6.13 (~ bnd_c3_2 bnd_a540 X22 | ~ bnd_c1_2 bnd_a540 X22) |
% 6.62/6.13 bnd_c2_2 bnd_a540 X22) |
% 6.62/6.13 bnd_c5_0) |
% 6.62/6.13 (bnd_ndr1_0 &
% 6.62/6.13 (ALL X23.
% 6.62/6.13 bnd_ndr1_1 bnd_a541 -->
% 6.62/6.13 (bnd_c2_2 bnd_a541 X23 | ~ bnd_c4_2 bnd_a541 X23) |
% 6.62/6.13 bnd_c3_2 bnd_a541 X23)) &
% 6.62/6.13 (ALL X24.
% 6.62/6.13 bnd_ndr1_1 bnd_a541 -->
% 6.62/6.13 (bnd_c2_2 bnd_a541 X24 | ~ bnd_c5_2 bnd_a541 X24) |
% 6.62/6.13 bnd_c3_2 bnd_a541 X24))) &
% 6.62/6.13 ((~ bnd_c1_0 | ~ bnd_c5_0) |
% 6.62/6.13 (ALL X25.
% 6.62/6.13 bnd_ndr1_0 -->
% 6.62/6.13 (~ bnd_c2_1 X25 |
% 6.62/6.13 (ALL X26.
% 6.62/6.13 bnd_ndr1_1 X25 --> ~ bnd_c1_2 X25 X26 | bnd_c4_2 X25 X26)) |
% 6.62/6.13 ((bnd_ndr1_1 X25 & ~ bnd_c2_2 X25 bnd_a542) &
% 6.62/6.13 ~ bnd_c4_2 X25 bnd_a542) &
% 6.62/6.13 ~ bnd_c5_2 X25 bnd_a542))) &
% 6.62/6.13 ((bnd_c1_0 |
% 6.62/6.13 (ALL X27.
% 6.62/6.13 bnd_ndr1_0 -->
% 6.62/6.13 ((bnd_ndr1_1 X27 & bnd_c2_2 X27 bnd_a543) &
% 6.62/6.13 ~ bnd_c5_2 X27 bnd_a543) &
% 6.62/6.13 ~ bnd_c1_2 X27 bnd_a543 |
% 6.62/6.13 bnd_c1_1 X27)) |
% 6.62/6.13 (((((bnd_ndr1_0 & bnd_c4_1 bnd_a544) & bnd_c1_1 bnd_a544) &
% 6.62/6.13 bnd_ndr1_1 bnd_a544) &
% 6.62/6.13 bnd_c3_2 bnd_a544 bnd_a545) &
% 6.62/6.13 ~ bnd_c1_2 bnd_a544 bnd_a545) &
% 6.62/6.13 ~ bnd_c5_2 bnd_a544 bnd_a545))
% 8.23/7.74 Unfolded term: ~ (((((((((((((((((((((ALL U.
% 8.23/7.74 bnd_ndr1_0 -->
% 8.23/7.74 bnd_c5_1 U |
% 8.23/7.74 (ALL V.
% 8.23/7.74 bnd_ndr1_1 U -->
% 8.23/7.74 bnd_c3_2 U V | ~ bnd_c2_2 U V)) |
% 8.23/7.74 ~ bnd_c4_0) |
% 8.23/7.74 bnd_c2_0) &
% 8.23/7.74 ((((bnd_ndr1_0 & ~ bnd_c5_1 bnd_a520) &
% 8.23/7.74 (ALL W.
% 8.23/7.74 bnd_ndr1_1 bnd_a520 -->
% 8.23/7.74 (~ bnd_c1_2 bnd_a520 W | ~ bnd_c5_2 bnd_a520 W) |
% 8.23/7.74 ~ bnd_c3_2 bnd_a520 W)) &
% 8.23/7.74 bnd_c1_1 bnd_a520 |
% 8.23/7.74 bnd_c5_0) |
% 8.23/7.74 bnd_c3_0)) &
% 8.23/7.74 (((bnd_ndr1_0 & ~ bnd_c2_1 bnd_a521) &
% 8.23/7.74 (ALL X.
% 8.23/7.74 bnd_ndr1_1 bnd_a521 -->
% 8.23/7.74 (bnd_c1_2 bnd_a521 X | ~ bnd_c2_2 bnd_a521 X) |
% 8.23/7.74 ~ bnd_c5_2 bnd_a521 X)) &
% 8.23/7.74 ~ bnd_c1_1 bnd_a521 |
% 8.23/7.74 (ALL Y.
% 8.23/7.74 bnd_ndr1_0 -->
% 8.23/7.74 ((bnd_ndr1_1 Y & bnd_c5_2 Y bnd_a522) &
% 8.23/7.74 bnd_c2_2 Y bnd_a522 |
% 8.23/7.74 ~ bnd_c3_1 Y) |
% 8.23/7.74 bnd_c5_1 Y))) &
% 8.23/7.74 (((ALL Z.
% 8.23/7.74 bnd_ndr1_0 -->
% 8.23/7.74 ((bnd_ndr1_1 Z & ~ bnd_c3_2 Z bnd_a523) &
% 8.23/7.74 ~ bnd_c1_2 Z bnd_a523 |
% 8.23/7.74 (ALL X1.
% 8.23/7.74 bnd_ndr1_1 Z -->
% 8.23/7.74 (bnd_c1_2 Z X1 | bnd_c2_2 Z X1) |
% 8.23/7.74 bnd_c3_2 Z X1)) |
% 8.23/7.74 bnd_c4_1 Z) |
% 8.23/7.74 (ALL X2.
% 8.23/7.74 bnd_ndr1_0 -->
% 8.23/7.74 ((ALL X3.
% 8.23/7.74 bnd_ndr1_1 X2 -->
% 8.23/7.74 (~ bnd_c1_2 X2 X3 | ~ bnd_c2_2 X2 X3) |
% 8.23/7.74 ~ bnd_c3_2 X2 X3) |
% 8.23/7.74 ((bnd_ndr1_1 X2 & bnd_c1_2 X2 bnd_a524) &
% 8.23/7.74 bnd_c5_2 X2 bnd_a524) &
% 8.23/7.74 ~ bnd_c4_2 X2 bnd_a524) |
% 8.23/7.74 bnd_c4_1 X2)) |
% 8.23/7.74 ~ bnd_c3_0)) &
% 8.23/7.74 ((bnd_c4_0 | bnd_c1_0) | bnd_c5_0)) &
% 8.23/7.74 (~ bnd_c2_0 |
% 8.23/7.74 (((((bnd_ndr1_0 & ~ bnd_c2_1 bnd_a525) &
% 8.23/7.74 bnd_ndr1_1 bnd_a525) &
% 8.23/7.74 ~ bnd_c1_2 bnd_a525 bnd_a526) &
% 8.23/7.74 bnd_c2_2 bnd_a525 bnd_a526) &
% 8.23/7.74 bnd_c4_2 bnd_a525 bnd_a526) &
% 8.23/7.74 bnd_c3_1 bnd_a525)) &
% 8.23/7.74 ((((((bnd_ndr1_0 & bnd_c5_1 bnd_a527) &
% 8.23/7.74 bnd_ndr1_1 bnd_a527) &
% 8.23/7.74 ~ bnd_c3_2 bnd_a527 bnd_a528) &
% 8.23/7.74 bnd_c1_2 bnd_a527 bnd_a528) &
% 8.23/7.74 ~ bnd_c3_1 bnd_a527 |
% 8.23/7.74 (((((((bnd_ndr1_0 & bnd_c4_1 bnd_a529) &
% 8.23/7.74 bnd_ndr1_1 bnd_a529) &
% 8.23/7.74 bnd_c5_2 bnd_a529 bnd_a530) &
% 8.23/7.74 bnd_c4_2 bnd_a529 bnd_a530) &
% 8.23/7.74 bnd_c1_2 bnd_a529 bnd_a530) &
% 8.23/7.74 bnd_ndr1_1 bnd_a529) &
% 8.23/7.74 bnd_c1_2 bnd_a529 bnd_a531) &
% 8.23/7.74 bnd_c5_2 bnd_a529 bnd_a531) |
% 8.23/7.74 ~ bnd_c4_0)) &
% 8.23/7.74 (bnd_c2_0 | ~ bnd_c5_0)) &
% 8.23/7.74 (((ALL X4.
% 8.23/7.74 bnd_ndr1_0 -->
% 8.23/7.74 ((ALL X5.
% 8.23/7.74 bnd_ndr1_1 X4 -->
% 8.23/7.74 (bnd_c2_2 X4 X5 | bnd_c4_2 X4 X5) |
% 8.23/7.74 ~ bnd_c3_2 X4 X5) |
% 8.23/7.74 (ALL X6.
% 8.23/7.74 bnd_ndr1_1 X4 -->
% 8.23/7.74 ~ bnd_c1_2 X4 X6 | bnd_c4_2 X4 X6)) |
% 8.23/7.74 (ALL X7.
% 8.23/7.74 bnd_ndr1_1 X4 -->
% 8.23/7.74 (~ bnd_c3_2 X4 X7 | ~ bnd_c5_2 X4 X7) |
% 8.23/7.74 bnd_c4_2 X4 X7)) |
% 8.23/7.74 (ALL X8. bnd_ndr1_0 --> bnd_c2_1 X8 | ~ bnd_c5_1 X8)) |
% 8.23/7.74 bnd_c1_0)) &
% 8.23/7.74 (((ALL X9.
% 8.23/7.74 bnd_ndr1_0 -->
% 8.23/7.74 ((bnd_ndr1_1 X9 & bnd_c4_2 X9 bnd_a532) &
% 8.23/7.74 ~ bnd_c3_2 X9 bnd_a532) &
% 8.23/7.74 ~ bnd_c5_2 X9 bnd_a532 |
% 8.23/7.74 bnd_c1_1 X9) |
% 8.23/7.74 (bnd_ndr1_0 &
% 8.23/7.74 (ALL X10.
% 8.23/7.74 bnd_ndr1_1 bnd_a533 -->
% 8.23/7.74 (bnd_c4_2 bnd_a533 X10 | bnd_c5_2 bnd_a533 X10) |
% 8.23/7.74 ~ bnd_c3_2 bnd_a533 X10)) &
% 8.23/7.74 ~ bnd_c3_1 bnd_a533) |
% 8.23/7.74 ~ bnd_c2_0)) &
% 8.23/7.74 ((bnd_c5_0 |
% 8.23/7.74 (ALL X11.
% 8.23/7.74 bnd_ndr1_0 -->
% 8.23/7.74 (bnd_c1_1 X11 | bnd_c5_1 X11) | bnd_c4_1 X11)) |
% 8.23/7.74 (ALL X12.
% 8.23/7.74 bnd_ndr1_0 -->
% 8.23/7.74 ((ALL X13.
% 8.23/7.74 bnd_ndr1_1 X12 -->
% 8.23/7.74 (bnd_c3_2 X12 X13 | bnd_c1_2 X12 X13) |
% 8.23/7.74 bnd_c4_2 X12 X13) |
% 8.23/7.74 (bnd_ndr1_1 X12 & bnd_c4_2 X12 bnd_a534) &
% 8.23/7.74 ~ bnd_c3_2 X12 bnd_a534) |
% 8.23/7.74 bnd_c3_1 X12))) &
% 8.23/7.74 ((~ bnd_c1_0 | ~ bnd_c3_0) |
% 8.23/7.74 (ALL X14.
% 8.23/7.74 bnd_ndr1_0 -->
% 8.23/7.74 (ALL X15.
% 8.23/7.74 bnd_ndr1_1 X14 --> bnd_c3_2 X14 X15 | bnd_c2_2 X14 X15) |
% 8.23/7.74 bnd_c5_1 X14))) &
% 8.23/7.74 (bnd_c5_0 | ~ bnd_c3_0)) &
% 8.23/7.74 ((~ bnd_c4_0 |
% 8.23/7.74 (ALL X16.
% 8.23/7.74 bnd_ndr1_0 -->
% 8.23/7.74 (bnd_c1_1 X16 |
% 8.23/7.74 (bnd_ndr1_1 X16 & ~ bnd_c4_2 X16 bnd_a535) &
% 8.23/7.74 ~ bnd_c3_2 X16 bnd_a535) |
% 8.23/7.74 bnd_c4_1 X16)) |
% 8.23/7.74 (ALL X17.
% 8.23/7.74 bnd_ndr1_0 -->
% 8.23/7.74 (ALL X18.
% 8.23/7.74 bnd_ndr1_1 X17 -->
% 8.23/7.74 (bnd_c4_2 X17 X18 | bnd_c1_2 X17 X18) |
% 8.23/7.74 ~ bnd_c3_2 X17 X18) |
% 8.23/7.74 bnd_c5_1 X17))) &
% 8.23/7.74 ((((bnd_ndr1_0 &
% 8.23/7.74 (ALL X19.
% 8.23/7.74 bnd_ndr1_1 bnd_a536 -->
% 8.23/7.74 bnd_c4_2 bnd_a536 X19 | bnd_c2_2 bnd_a536 X19)) &
% 8.23/7.74 ~ bnd_c5_1 bnd_a536) &
% 8.23/7.74 ~ bnd_c1_1 bnd_a536 |
% 8.23/7.74 bnd_c2_0) |
% 8.23/7.74 ~ bnd_c3_0)) &
% 8.23/7.74 ((~ bnd_c2_0 |
% 8.23/7.74 (((bnd_ndr1_0 & bnd_ndr1_1 bnd_a537) & bnd_c2_2 bnd_a537 bnd_a538) &
% 8.23/7.74 bnd_c3_2 bnd_a537 bnd_a538) &
% 8.23/7.74 ~ bnd_c5_1 bnd_a537) |
% 8.23/7.74 (ALL X20.
% 8.23/7.74 bnd_ndr1_0 -->
% 8.23/7.74 (bnd_c4_1 X20 |
% 8.23/7.74 (ALL X21.
% 8.23/7.74 bnd_ndr1_1 X20 -->
% 8.23/7.74 (~ bnd_c1_2 X20 X21 | bnd_c3_2 X20 X21) |
% 8.23/7.74 ~ bnd_c5_2 X20 X21)) |
% 8.23/7.74 ((bnd_ndr1_1 X20 & bnd_c2_2 X20 bnd_a539) &
% 8.23/7.74 bnd_c1_2 X20 bnd_a539) &
% 8.23/7.74 bnd_c5_2 X20 bnd_a539))) &
% 8.23/7.74 ((((bnd_ndr1_0 & bnd_c3_1 bnd_a540) & ~ bnd_c4_1 bnd_a540) &
% 8.23/7.74 (ALL X22.
% 8.23/7.74 bnd_ndr1_1 bnd_a540 -->
% 8.23/7.74 (~ bnd_c3_2 bnd_a540 X22 | ~ bnd_c1_2 bnd_a540 X22) |
% 8.23/7.74 bnd_c2_2 bnd_a540 X22) |
% 8.23/7.74 bnd_c5_0) |
% 8.23/7.74 (bnd_ndr1_0 &
% 8.23/7.74 (ALL X23.
% 8.23/7.74 bnd_ndr1_1 bnd_a541 -->
% 8.23/7.74 (bnd_c2_2 bnd_a541 X23 | ~ bnd_c4_2 bnd_a541 X23) |
% 8.23/7.74 bnd_c3_2 bnd_a541 X23)) &
% 8.23/7.74 (ALL X24.
% 8.23/7.74 bnd_ndr1_1 bnd_a541 -->
% 8.23/7.74 (bnd_c2_2 bnd_a541 X24 | ~ bnd_c5_2 bnd_a541 X24) |
% 8.23/7.74 bnd_c3_2 bnd_a541 X24))) &
% 8.23/7.74 ((~ bnd_c1_0 | ~ bnd_c5_0) |
% 8.23/7.74 (ALL X25.
% 8.23/7.74 bnd_ndr1_0 -->
% 8.23/7.74 (~ bnd_c2_1 X25 |
% 8.23/7.74 (ALL X26.
% 8.23/7.74 bnd_ndr1_1 X25 --> ~ bnd_c1_2 X25 X26 | bnd_c4_2 X25 X26)) |
% 8.23/7.74 ((bnd_ndr1_1 X25 & ~ bnd_c2_2 X25 bnd_a542) &
% 8.23/7.74 ~ bnd_c4_2 X25 bnd_a542) &
% 8.23/7.74 ~ bnd_c5_2 X25 bnd_a542))) &
% 8.23/7.74 ((bnd_c1_0 |
% 8.23/7.74 (ALL X27.
% 8.23/7.74 bnd_ndr1_0 -->
% 8.23/7.74 ((bnd_ndr1_1 X27 & bnd_c2_2 X27 bnd_a543) &
% 8.23/7.74 ~ bnd_c5_2 X27 bnd_a543) &
% 8.23/7.74 ~ bnd_c1_2 X27 bnd_a543 |
% 8.23/7.74 bnd_c1_1 X27)) |
% 8.23/7.74 (((((bnd_ndr1_0 & bnd_c4_1 bnd_a544) & bnd_c1_1 bnd_a544) &
% 8.23/7.74 bnd_ndr1_1 bnd_a544) &
% 8.23/7.74 bnd_c3_2 bnd_a544 bnd_a545) &
% 8.23/7.74 ~ bnd_c1_2 bnd_a544 bnd_a545) &
% 8.23/7.74 ~ bnd_c5_2 bnd_a544 bnd_a545))
% 8.23/7.74 Adding axioms...
% 8.23/7.75 Typedef.type_definition_def
% 13.33/12.80 ...done.
% 13.33/12.81 Ground types: ?'b, TPTP_Interpret.ind
% 13.33/12.81 Translating term (sizes: 1, 1) ...
% 17.44/16.92 Invoking SAT solver...
% 17.54/17.03 Model found:
% 17.54/17.03 Size of types: ?'b: 1, TPTP_Interpret.ind: 1
% 17.54/17.03 bnd_a545: ??.TPTP_Interpret.ind0
% 17.54/17.03 bnd_a544: ??.TPTP_Interpret.ind0
% 17.54/17.03 bnd_a543: ??.TPTP_Interpret.ind0
% 17.54/17.03 bnd_a542: ??.TPTP_Interpret.ind0
% 17.54/17.03 bnd_a541: ??.TPTP_Interpret.ind0
% 17.54/17.03 bnd_a540: ??.TPTP_Interpret.ind0
% 17.54/17.03 bnd_a539: ??.TPTP_Interpret.ind0
% 17.54/17.03 bnd_a538: ??.TPTP_Interpret.ind0
% 17.54/17.03 bnd_a537: ??.TPTP_Interpret.ind0
% 17.54/17.03 bnd_a536: ??.TPTP_Interpret.ind0
% 17.54/17.03 bnd_a535: ??.TPTP_Interpret.ind0
% 17.54/17.03 bnd_a534: ??.TPTP_Interpret.ind0
% 17.54/17.03 bnd_a533: ??.TPTP_Interpret.ind0
% 17.54/17.03 bnd_a532: ??.TPTP_Interpret.ind0
% 17.54/17.03 bnd_a531: ??.TPTP_Interpret.ind0
% 17.54/17.03 bnd_a530: ??.TPTP_Interpret.ind0
% 17.54/17.03 bnd_a529: ??.TPTP_Interpret.ind0
% 17.54/17.03 bnd_a528: ??.TPTP_Interpret.ind0
% 17.54/17.03 bnd_a527: ??.TPTP_Interpret.ind0
% 17.54/17.03 bnd_a526: ??.TPTP_Interpret.ind0
% 17.54/17.03 bnd_a525: ??.TPTP_Interpret.ind0
% 17.54/17.03 bnd_c1_0: True
% 17.54/17.03 bnd_c4_2: {(??.TPTP_Interpret.ind0, {(??.TPTP_Interpret.ind0, True)})}
% 17.54/17.03 bnd_a524: ??.TPTP_Interpret.ind0
% 17.54/17.03 bnd_c4_1: {(??.TPTP_Interpret.ind0, True)}
% 17.54/17.03 bnd_a523: ??.TPTP_Interpret.ind0
% 17.54/17.03 bnd_c3_1: {(??.TPTP_Interpret.ind0, False)}
% 17.54/17.03 bnd_a522: ??.TPTP_Interpret.ind0
% 17.54/17.03 bnd_a521: ??.TPTP_Interpret.ind0
% 17.54/17.03 bnd_c2_1: {(??.TPTP_Interpret.ind0, False)}
% 17.54/17.03 bnd_c3_0: False
% 17.54/17.03 bnd_c5_0: False
% 17.54/17.03 bnd_c1_1: {(??.TPTP_Interpret.ind0, True)}
% 17.54/17.03 bnd_c5_2: {(??.TPTP_Interpret.ind0, {(??.TPTP_Interpret.ind0, True)})}
% 17.54/17.03 bnd_c1_2: {(??.TPTP_Interpret.ind0, {(??.TPTP_Interpret.ind0, True)})}
% 17.54/17.03 bnd_a520: ??.TPTP_Interpret.ind0
% 17.54/17.03 bnd_c2_0: False
% 17.54/17.03 bnd_c4_0: False
% 17.54/17.03 bnd_c2_2: {(??.TPTP_Interpret.ind0, {(??.TPTP_Interpret.ind0, True)})}
% 17.54/17.03 bnd_c3_2: {(??.TPTP_Interpret.ind0, {(??.TPTP_Interpret.ind0, False)})}
% 17.54/17.03 bnd_ndr1_1: {(??.TPTP_Interpret.ind0, True)}
% 17.54/17.03 bnd_c5_1: {(??.TPTP_Interpret.ind0, False)}
% 17.54/17.03 bnd_ndr1_0: True
% 17.54/17.03
% 17.54/17.03 % SZS status CounterSatisfiable
%------------------------------------------------------------------------------