TSTP Solution File: SYN535+1 by Refute---2015
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%------------------------------------------------------------------------------
% File : Refute---2015
% Problem : SYN535+1 : TPTP v6.4.0. Released v2.1.0.
% Transfm : none
% Format : tptp:raw
% Command : isabelle tptp_refute %d %s
% Computer : n142.star.cs.uiowa.edu
% Model : x86_64 x86_64
% CPU : Intel(R) Xeon(R) CPU E5-2609 0 2.40GHz
% Memory : 32218.75MB
% OS : Linux 3.10.0-327.10.1.el7.x86_64
% CPULimit : 300s
% DateTime : Thu Apr 14 06:42:17 EDT 2016
% Result : CounterSatisfiable 17.11s
% Output : Assurance 0s
% Verified :
% SZS Type : None (Parsing solution fails)
% Syntax : Number of formulae : 0
% Comments :
%------------------------------------------------------------------------------
%----No solution output by system
%------------------------------------------------------------------------------
%----ORIGINAL SYSTEM OUTPUT
% 0.00/0.03 % Problem : SYN535+1 : TPTP v6.4.0. Released v2.1.0.
% 0.00/0.04 % Command : isabelle tptp_refute %d %s
% 0.03/0.23 % Computer : n142.star.cs.uiowa.edu
% 0.03/0.23 % Model : x86_64 x86_64
% 0.03/0.23 % CPU : Intel(R) Xeon(R) CPU E5-2609 0 @ 2.40GHz
% 0.03/0.23 % Memory : 32218.75MB
% 0.03/0.23 % OS : Linux 3.10.0-327.10.1.el7.x86_64
% 0.03/0.23 % CPULimit : 300
% 0.03/0.23 % DateTime : Sat Apr 9 00:14:54 CDT 2016
% 0.03/0.23 % CPUTime:
% 6.29/5.86 > val it = (): unit
% 6.59/6.16 Trying to find a model that refutes: ~ ((((((((((((((((((((bnd_c4_0 | bnd_c1_0) &
% 6.59/6.16 ((~ bnd_c3_0 |
% 6.59/6.16 (ALL U. bnd_ndr1_0 --> bnd_c4_1 U | bnd_c5_1 U)) |
% 6.59/6.16 bnd_c5_0)) &
% 6.59/6.16 ((bnd_c1_0 |
% 6.59/6.16 (((((bnd_ndr1_0 & ~ bnd_c2_1 bnd_a492) &
% 6.59/6.16 bnd_ndr1_1 bnd_a492) &
% 6.59/6.16 ~ bnd_c5_2 bnd_a492 bnd_a493) &
% 6.59/6.16 ~ bnd_c3_2 bnd_a492 bnd_a493) &
% 6.59/6.16 ~ bnd_c2_2 bnd_a492 bnd_a493) &
% 6.59/6.16 bnd_c5_1 bnd_a492) |
% 6.59/6.16 ((bnd_ndr1_0 & ~ bnd_c3_1 bnd_a494) &
% 6.59/6.16 ~ bnd_c4_1 bnd_a494) &
% 6.59/6.16 (ALL V.
% 6.59/6.16 bnd_ndr1_1 bnd_a494 -->
% 6.59/6.16 (bnd_c3_2 bnd_a494 V | bnd_c1_2 bnd_a494 V) |
% 6.59/6.16 ~ bnd_c4_2 bnd_a494 V))) &
% 6.59/6.16 (bnd_c3_0 |
% 6.59/6.16 (((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a495) &
% 6.59/6.16 bnd_c4_2 bnd_a495 bnd_a496) &
% 6.59/6.16 ~ bnd_c5_2 bnd_a495 bnd_a496) &
% 6.59/6.16 bnd_c2_2 bnd_a495 bnd_a496) &
% 6.59/6.16 bnd_c2_1 bnd_a495) &
% 6.59/6.16 (ALL W.
% 6.59/6.16 bnd_ndr1_1 bnd_a495 -->
% 6.59/6.16 ~ bnd_c5_2 bnd_a495 W | ~ bnd_c3_2 bnd_a495 W))) &
% 6.59/6.16 ((bnd_c3_0 | ~ bnd_c5_0) | bnd_c1_0)) &
% 6.59/6.16 (((ALL X.
% 6.59/6.16 bnd_ndr1_0 -->
% 6.59/6.16 ((ALL Y.
% 6.59/6.16 bnd_ndr1_1 X --> bnd_c2_2 X Y | bnd_c1_2 X Y) |
% 6.59/6.16 ((bnd_ndr1_1 X & bnd_c5_2 X bnd_a497) &
% 6.59/6.16 bnd_c1_2 X bnd_a497) &
% 6.59/6.16 bnd_c3_2 X bnd_a497) |
% 6.59/6.16 bnd_c3_1 X) |
% 6.59/6.16 bnd_c3_0) |
% 6.59/6.16 (bnd_ndr1_0 &
% 6.59/6.16 (ALL Z.
% 6.59/6.16 bnd_ndr1_1 bnd_a498 -->
% 6.59/6.16 ~ bnd_c4_2 bnd_a498 Z | bnd_c3_2 bnd_a498 Z)) &
% 6.59/6.16 bnd_c4_1 bnd_a498)) &
% 6.59/6.16 (bnd_c1_0 | bnd_ndr1_0 & ~ bnd_c4_1 bnd_a499)) &
% 6.59/6.16 ((bnd_c3_0 | ~ bnd_c4_0) | ~ bnd_c1_0)) &
% 6.59/6.16 ((~ bnd_c2_0 |
% 6.59/6.16 (((((bnd_ndr1_0 & ~ bnd_c2_1 bnd_a500) &
% 6.59/6.16 bnd_ndr1_1 bnd_a500) &
% 6.59/6.16 bnd_c1_2 bnd_a500 bnd_a501) &
% 6.59/6.16 ~ bnd_c2_2 bnd_a500 bnd_a501) &
% 6.59/6.16 ~ bnd_c3_2 bnd_a500 bnd_a501) &
% 6.59/6.16 bnd_c3_1 bnd_a500) |
% 6.59/6.16 (ALL X1.
% 6.59/6.16 bnd_ndr1_0 -->
% 6.59/6.16 (bnd_c5_1 X1 |
% 6.59/6.16 (ALL X2.
% 6.59/6.16 bnd_ndr1_1 X1 -->
% 6.59/6.16 (bnd_c3_2 X1 X2 | bnd_c1_2 X1 X2) |
% 6.59/6.16 ~ bnd_c4_2 X1 X2)) |
% 6.59/6.16 ((bnd_ndr1_1 X1 & ~ bnd_c2_2 X1 bnd_a502) &
% 6.59/6.16 ~ bnd_c3_2 X1 bnd_a502) &
% 6.59/6.16 bnd_c5_2 X1 bnd_a502))) &
% 6.59/6.16 (((ALL X3.
% 6.59/6.16 bnd_ndr1_0 -->
% 6.59/6.16 (~ bnd_c3_1 X3 | bnd_c2_1 X3) | ~ bnd_c1_1 X3) |
% 6.59/6.16 bnd_c2_0) |
% 6.59/6.16 ((((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a503) &
% 6.59/6.16 bnd_c4_2 bnd_a503 bnd_a504) &
% 6.59/6.16 ~ bnd_c2_2 bnd_a503 bnd_a504) &
% 6.59/6.16 ~ bnd_c5_2 bnd_a503 bnd_a504) &
% 6.59/6.16 (ALL X4.
% 6.59/6.16 bnd_ndr1_1 bnd_a503 -->
% 6.59/6.16 (~ bnd_c3_2 bnd_a503 X4 | bnd_c1_2 bnd_a503 X4) |
% 6.59/6.16 ~ bnd_c5_2 bnd_a503 X4)) &
% 6.59/6.16 bnd_ndr1_1 bnd_a503) &
% 6.59/6.16 ~ bnd_c3_2 bnd_a503 bnd_a505) &
% 6.59/6.16 ~ bnd_c5_2 bnd_a503 bnd_a505) &
% 6.59/6.16 ~ bnd_c2_2 bnd_a503 bnd_a505)) &
% 6.59/6.16 (((ALL X5.
% 6.59/6.16 bnd_ndr1_0 -->
% 6.59/6.16 (bnd_c4_1 X5 |
% 6.59/6.16 ((bnd_ndr1_1 X5 & bnd_c4_2 X5 bnd_a506) &
% 6.59/6.16 bnd_c5_2 X5 bnd_a506) &
% 6.59/6.16 ~ bnd_c3_2 X5 bnd_a506) |
% 6.59/6.16 ~ bnd_c5_1 X5) |
% 6.59/6.16 ((bnd_ndr1_0 &
% 6.59/6.16 (ALL X6.
% 6.59/6.16 bnd_ndr1_1 bnd_a507 -->
% 6.59/6.16 (~ bnd_c2_2 bnd_a507 X6 | ~ bnd_c3_2 bnd_a507 X6) |
% 6.59/6.16 ~ bnd_c5_2 bnd_a507 X6)) &
% 6.59/6.16 ~ bnd_c4_1 bnd_a507) &
% 6.59/6.16 bnd_c3_1 bnd_a507) |
% 6.59/6.16 (bnd_ndr1_0 & bnd_c5_1 bnd_a508) & bnd_c1_1 bnd_a508)) &
% 6.59/6.16 ((bnd_c3_0 | bnd_c4_0) | ~ bnd_c5_0)) &
% 6.59/6.16 (((bnd_ndr1_0 &
% 6.59/6.16 (ALL X7.
% 6.59/6.16 bnd_ndr1_1 bnd_a509 -->
% 6.59/6.16 (bnd_c4_2 bnd_a509 X7 | ~ bnd_c2_2 bnd_a509 X7) |
% 6.59/6.16 bnd_c5_2 bnd_a509 X7)) &
% 6.59/6.16 ~ bnd_c2_1 bnd_a509 |
% 6.59/6.16 (ALL X8.
% 6.59/6.16 bnd_ndr1_0 -->
% 6.59/6.16 ((bnd_ndr1_1 X8 & ~ bnd_c2_2 X8 bnd_a510) &
% 6.59/6.16 ~ bnd_c3_2 X8 bnd_a510 |
% 6.59/6.16 ~ bnd_c3_1 X8) |
% 6.59/6.16 bnd_c2_1 X8)) |
% 6.59/6.16 (ALL X9.
% 6.59/6.16 bnd_ndr1_0 -->
% 6.59/6.16 bnd_c3_1 X9 |
% 6.59/6.16 (ALL X10.
% 6.59/6.16 bnd_ndr1_1 X9 -->
% 6.59/6.16 ~ bnd_c4_2 X9 X10 | ~ bnd_c3_2 X9 X10)))) &
% 6.59/6.16 ((((bnd_ndr1_0 &
% 6.59/6.16 (ALL X11.
% 6.59/6.16 bnd_ndr1_1 bnd_a511 -->
% 6.59/6.16 (bnd_c2_2 bnd_a511 X11 | bnd_c4_2 bnd_a511 X11) |
% 6.59/6.16 ~ bnd_c3_2 bnd_a511 X11)) &
% 6.59/6.16 ~ bnd_c3_1 bnd_a511) &
% 6.59/6.16 ~ bnd_c2_1 bnd_a511 |
% 6.59/6.16 ~ bnd_c4_0) |
% 6.59/6.16 ((bnd_ndr1_0 & bnd_c4_1 bnd_a512) & ~ bnd_c3_1 bnd_a512) &
% 6.59/6.16 bnd_c1_1 bnd_a512)) &
% 6.59/6.16 (~ bnd_c2_0 | ~ bnd_c5_0)) &
% 6.59/6.16 ((~ bnd_c4_0 |
% 6.59/6.16 (ALL X12.
% 6.59/6.16 bnd_ndr1_0 -->
% 6.59/6.16 (~ bnd_c4_1 X12 | ~ bnd_c3_1 X12) |
% 6.59/6.16 (ALL X13.
% 6.59/6.16 bnd_ndr1_1 X12 -->
% 6.59/6.16 ~ bnd_c4_2 X12 X13 | ~ bnd_c5_2 X12 X13))) |
% 6.59/6.16 ~ bnd_c5_0)) &
% 6.59/6.16 ((((bnd_ndr1_0 & ~ bnd_c4_1 bnd_a513) & bnd_c1_1 bnd_a513) &
% 6.59/6.16 bnd_c3_1 bnd_a513 |
% 6.59/6.16 bnd_c2_0) |
% 6.59/6.16 (((((bnd_ndr1_0 & bnd_c1_1 bnd_a514) & bnd_ndr1_1 bnd_a514) &
% 6.59/6.16 ~ bnd_c5_2 bnd_a514 bnd_a515) &
% 6.59/6.16 bnd_c3_2 bnd_a514 bnd_a515) &
% 6.59/6.16 bnd_c2_2 bnd_a514 bnd_a515) &
% 6.59/6.16 (ALL X14.
% 6.59/6.16 bnd_ndr1_1 bnd_a514 -->
% 6.59/6.16 (~ bnd_c4_2 bnd_a514 X14 | bnd_c5_2 bnd_a514 X14) |
% 6.59/6.16 bnd_c3_2 bnd_a514 X14))) &
% 6.59/6.16 (~ bnd_c1_0 |
% 6.59/6.16 ((bnd_ndr1_0 & bnd_c3_1 bnd_a516) &
% 6.59/6.16 (ALL X15.
% 6.59/6.16 bnd_ndr1_1 bnd_a516 -->
% 6.59/6.16 (~ bnd_c4_2 bnd_a516 X15 | bnd_c3_2 bnd_a516 X15) |
% 6.59/6.16 bnd_c5_2 bnd_a516 X15)) &
% 6.59/6.16 ~ bnd_c1_1 bnd_a516)) &
% 6.59/6.16 ((~ bnd_c2_0 | (ALL X16. bnd_ndr1_0 --> bnd_c5_1 X16)) |
% 6.59/6.16 (ALL X17.
% 6.59/6.16 bnd_ndr1_0 -->
% 6.59/6.16 (~ bnd_c4_1 X17 | ~ bnd_c1_1 X17) |
% 6.59/6.16 (ALL X18.
% 6.59/6.16 bnd_ndr1_1 X17 -->
% 6.59/6.16 (~ bnd_c3_2 X17 X18 | bnd_c5_2 X17 X18) |
% 6.59/6.16 ~ bnd_c1_2 X17 X18)))) &
% 6.59/6.16 (((((((bnd_ndr1_0 & ~ bnd_c2_1 bnd_a517) & bnd_c4_1 bnd_a517) &
% 6.59/6.16 bnd_ndr1_1 bnd_a517) &
% 6.59/6.16 bnd_c3_2 bnd_a517 bnd_a518) &
% 6.59/6.16 ~ bnd_c4_2 bnd_a517 bnd_a518) &
% 6.59/6.16 bnd_c5_2 bnd_a517 bnd_a518 |
% 6.59/6.16 (bnd_ndr1_0 & ~ bnd_c2_1 bnd_a519) & bnd_c1_1 bnd_a519) |
% 6.59/6.16 ~ bnd_c2_0))
% 8.20/7.79 Unfolded term: ~ ((((((((((((((((((((bnd_c4_0 | bnd_c1_0) &
% 8.20/7.79 ((~ bnd_c3_0 |
% 8.20/7.79 (ALL U. bnd_ndr1_0 --> bnd_c4_1 U | bnd_c5_1 U)) |
% 8.20/7.79 bnd_c5_0)) &
% 8.20/7.79 ((bnd_c1_0 |
% 8.20/7.79 (((((bnd_ndr1_0 & ~ bnd_c2_1 bnd_a492) &
% 8.20/7.79 bnd_ndr1_1 bnd_a492) &
% 8.20/7.79 ~ bnd_c5_2 bnd_a492 bnd_a493) &
% 8.20/7.79 ~ bnd_c3_2 bnd_a492 bnd_a493) &
% 8.20/7.79 ~ bnd_c2_2 bnd_a492 bnd_a493) &
% 8.20/7.79 bnd_c5_1 bnd_a492) |
% 8.20/7.79 ((bnd_ndr1_0 & ~ bnd_c3_1 bnd_a494) &
% 8.20/7.79 ~ bnd_c4_1 bnd_a494) &
% 8.20/7.79 (ALL V.
% 8.20/7.79 bnd_ndr1_1 bnd_a494 -->
% 8.20/7.79 (bnd_c3_2 bnd_a494 V | bnd_c1_2 bnd_a494 V) |
% 8.20/7.79 ~ bnd_c4_2 bnd_a494 V))) &
% 8.20/7.79 (bnd_c3_0 |
% 8.20/7.79 (((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a495) &
% 8.20/7.79 bnd_c4_2 bnd_a495 bnd_a496) &
% 8.20/7.79 ~ bnd_c5_2 bnd_a495 bnd_a496) &
% 8.20/7.79 bnd_c2_2 bnd_a495 bnd_a496) &
% 8.20/7.79 bnd_c2_1 bnd_a495) &
% 8.20/7.79 (ALL W.
% 8.20/7.79 bnd_ndr1_1 bnd_a495 -->
% 8.20/7.79 ~ bnd_c5_2 bnd_a495 W | ~ bnd_c3_2 bnd_a495 W))) &
% 8.20/7.79 ((bnd_c3_0 | ~ bnd_c5_0) | bnd_c1_0)) &
% 8.20/7.79 (((ALL X.
% 8.20/7.79 bnd_ndr1_0 -->
% 8.20/7.79 ((ALL Y.
% 8.20/7.79 bnd_ndr1_1 X --> bnd_c2_2 X Y | bnd_c1_2 X Y) |
% 8.20/7.79 ((bnd_ndr1_1 X & bnd_c5_2 X bnd_a497) &
% 8.20/7.79 bnd_c1_2 X bnd_a497) &
% 8.20/7.79 bnd_c3_2 X bnd_a497) |
% 8.20/7.79 bnd_c3_1 X) |
% 8.20/7.79 bnd_c3_0) |
% 8.20/7.79 (bnd_ndr1_0 &
% 8.20/7.79 (ALL Z.
% 8.20/7.79 bnd_ndr1_1 bnd_a498 -->
% 8.20/7.79 ~ bnd_c4_2 bnd_a498 Z | bnd_c3_2 bnd_a498 Z)) &
% 8.20/7.79 bnd_c4_1 bnd_a498)) &
% 8.20/7.79 (bnd_c1_0 | bnd_ndr1_0 & ~ bnd_c4_1 bnd_a499)) &
% 8.20/7.79 ((bnd_c3_0 | ~ bnd_c4_0) | ~ bnd_c1_0)) &
% 8.20/7.79 ((~ bnd_c2_0 |
% 8.20/7.79 (((((bnd_ndr1_0 & ~ bnd_c2_1 bnd_a500) &
% 8.20/7.79 bnd_ndr1_1 bnd_a500) &
% 8.20/7.79 bnd_c1_2 bnd_a500 bnd_a501) &
% 8.20/7.79 ~ bnd_c2_2 bnd_a500 bnd_a501) &
% 8.20/7.79 ~ bnd_c3_2 bnd_a500 bnd_a501) &
% 8.20/7.79 bnd_c3_1 bnd_a500) |
% 8.20/7.79 (ALL X1.
% 8.20/7.79 bnd_ndr1_0 -->
% 8.20/7.79 (bnd_c5_1 X1 |
% 8.20/7.79 (ALL X2.
% 8.20/7.79 bnd_ndr1_1 X1 -->
% 8.20/7.79 (bnd_c3_2 X1 X2 | bnd_c1_2 X1 X2) |
% 8.20/7.79 ~ bnd_c4_2 X1 X2)) |
% 8.20/7.79 ((bnd_ndr1_1 X1 & ~ bnd_c2_2 X1 bnd_a502) &
% 8.20/7.79 ~ bnd_c3_2 X1 bnd_a502) &
% 8.20/7.79 bnd_c5_2 X1 bnd_a502))) &
% 8.20/7.79 (((ALL X3.
% 8.20/7.79 bnd_ndr1_0 -->
% 8.20/7.79 (~ bnd_c3_1 X3 | bnd_c2_1 X3) | ~ bnd_c1_1 X3) |
% 8.20/7.79 bnd_c2_0) |
% 8.20/7.79 ((((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a503) &
% 8.20/7.79 bnd_c4_2 bnd_a503 bnd_a504) &
% 8.20/7.79 ~ bnd_c2_2 bnd_a503 bnd_a504) &
% 8.20/7.79 ~ bnd_c5_2 bnd_a503 bnd_a504) &
% 8.20/7.79 (ALL X4.
% 8.20/7.79 bnd_ndr1_1 bnd_a503 -->
% 8.20/7.79 (~ bnd_c3_2 bnd_a503 X4 | bnd_c1_2 bnd_a503 X4) |
% 8.20/7.79 ~ bnd_c5_2 bnd_a503 X4)) &
% 8.20/7.79 bnd_ndr1_1 bnd_a503) &
% 8.20/7.79 ~ bnd_c3_2 bnd_a503 bnd_a505) &
% 8.20/7.79 ~ bnd_c5_2 bnd_a503 bnd_a505) &
% 8.20/7.79 ~ bnd_c2_2 bnd_a503 bnd_a505)) &
% 8.20/7.79 (((ALL X5.
% 8.20/7.79 bnd_ndr1_0 -->
% 8.20/7.79 (bnd_c4_1 X5 |
% 8.20/7.79 ((bnd_ndr1_1 X5 & bnd_c4_2 X5 bnd_a506) &
% 8.20/7.79 bnd_c5_2 X5 bnd_a506) &
% 8.20/7.79 ~ bnd_c3_2 X5 bnd_a506) |
% 8.20/7.79 ~ bnd_c5_1 X5) |
% 8.20/7.79 ((bnd_ndr1_0 &
% 8.20/7.79 (ALL X6.
% 8.20/7.79 bnd_ndr1_1 bnd_a507 -->
% 8.20/7.79 (~ bnd_c2_2 bnd_a507 X6 | ~ bnd_c3_2 bnd_a507 X6) |
% 8.20/7.79 ~ bnd_c5_2 bnd_a507 X6)) &
% 8.20/7.79 ~ bnd_c4_1 bnd_a507) &
% 8.20/7.79 bnd_c3_1 bnd_a507) |
% 8.20/7.79 (bnd_ndr1_0 & bnd_c5_1 bnd_a508) & bnd_c1_1 bnd_a508)) &
% 8.20/7.79 ((bnd_c3_0 | bnd_c4_0) | ~ bnd_c5_0)) &
% 8.20/7.79 (((bnd_ndr1_0 &
% 8.20/7.79 (ALL X7.
% 8.20/7.79 bnd_ndr1_1 bnd_a509 -->
% 8.20/7.79 (bnd_c4_2 bnd_a509 X7 | ~ bnd_c2_2 bnd_a509 X7) |
% 8.20/7.79 bnd_c5_2 bnd_a509 X7)) &
% 8.20/7.79 ~ bnd_c2_1 bnd_a509 |
% 8.20/7.79 (ALL X8.
% 8.20/7.79 bnd_ndr1_0 -->
% 8.20/7.79 ((bnd_ndr1_1 X8 & ~ bnd_c2_2 X8 bnd_a510) &
% 8.20/7.79 ~ bnd_c3_2 X8 bnd_a510 |
% 8.20/7.79 ~ bnd_c3_1 X8) |
% 8.20/7.79 bnd_c2_1 X8)) |
% 8.20/7.79 (ALL X9.
% 8.20/7.79 bnd_ndr1_0 -->
% 8.20/7.79 bnd_c3_1 X9 |
% 8.20/7.79 (ALL X10.
% 8.20/7.79 bnd_ndr1_1 X9 -->
% 8.20/7.79 ~ bnd_c4_2 X9 X10 | ~ bnd_c3_2 X9 X10)))) &
% 8.20/7.79 ((((bnd_ndr1_0 &
% 8.20/7.79 (ALL X11.
% 8.20/7.79 bnd_ndr1_1 bnd_a511 -->
% 8.20/7.79 (bnd_c2_2 bnd_a511 X11 | bnd_c4_2 bnd_a511 X11) |
% 8.20/7.79 ~ bnd_c3_2 bnd_a511 X11)) &
% 8.20/7.79 ~ bnd_c3_1 bnd_a511) &
% 8.20/7.79 ~ bnd_c2_1 bnd_a511 |
% 8.20/7.79 ~ bnd_c4_0) |
% 8.20/7.79 ((bnd_ndr1_0 & bnd_c4_1 bnd_a512) & ~ bnd_c3_1 bnd_a512) &
% 8.20/7.79 bnd_c1_1 bnd_a512)) &
% 8.20/7.79 (~ bnd_c2_0 | ~ bnd_c5_0)) &
% 8.20/7.79 ((~ bnd_c4_0 |
% 8.20/7.79 (ALL X12.
% 8.20/7.79 bnd_ndr1_0 -->
% 8.20/7.79 (~ bnd_c4_1 X12 | ~ bnd_c3_1 X12) |
% 8.20/7.79 (ALL X13.
% 8.20/7.79 bnd_ndr1_1 X12 -->
% 8.20/7.79 ~ bnd_c4_2 X12 X13 | ~ bnd_c5_2 X12 X13))) |
% 8.20/7.79 ~ bnd_c5_0)) &
% 8.20/7.79 ((((bnd_ndr1_0 & ~ bnd_c4_1 bnd_a513) & bnd_c1_1 bnd_a513) &
% 8.20/7.79 bnd_c3_1 bnd_a513 |
% 8.20/7.79 bnd_c2_0) |
% 8.20/7.79 (((((bnd_ndr1_0 & bnd_c1_1 bnd_a514) & bnd_ndr1_1 bnd_a514) &
% 8.20/7.79 ~ bnd_c5_2 bnd_a514 bnd_a515) &
% 8.20/7.79 bnd_c3_2 bnd_a514 bnd_a515) &
% 8.20/7.79 bnd_c2_2 bnd_a514 bnd_a515) &
% 8.20/7.79 (ALL X14.
% 8.20/7.79 bnd_ndr1_1 bnd_a514 -->
% 8.20/7.79 (~ bnd_c4_2 bnd_a514 X14 | bnd_c5_2 bnd_a514 X14) |
% 8.20/7.79 bnd_c3_2 bnd_a514 X14))) &
% 8.20/7.79 (~ bnd_c1_0 |
% 8.20/7.79 ((bnd_ndr1_0 & bnd_c3_1 bnd_a516) &
% 8.20/7.79 (ALL X15.
% 8.20/7.79 bnd_ndr1_1 bnd_a516 -->
% 8.20/7.79 (~ bnd_c4_2 bnd_a516 X15 | bnd_c3_2 bnd_a516 X15) |
% 8.20/7.79 bnd_c5_2 bnd_a516 X15)) &
% 8.20/7.79 ~ bnd_c1_1 bnd_a516)) &
% 8.20/7.79 ((~ bnd_c2_0 | (ALL X16. bnd_ndr1_0 --> bnd_c5_1 X16)) |
% 8.20/7.79 (ALL X17.
% 8.20/7.79 bnd_ndr1_0 -->
% 8.20/7.79 (~ bnd_c4_1 X17 | ~ bnd_c1_1 X17) |
% 8.20/7.79 (ALL X18.
% 8.20/7.79 bnd_ndr1_1 X17 -->
% 8.20/7.79 (~ bnd_c3_2 X17 X18 | bnd_c5_2 X17 X18) |
% 8.20/7.79 ~ bnd_c1_2 X17 X18)))) &
% 8.20/7.79 (((((((bnd_ndr1_0 & ~ bnd_c2_1 bnd_a517) & bnd_c4_1 bnd_a517) &
% 8.20/7.79 bnd_ndr1_1 bnd_a517) &
% 8.20/7.79 bnd_c3_2 bnd_a517 bnd_a518) &
% 8.20/7.79 ~ bnd_c4_2 bnd_a517 bnd_a518) &
% 8.20/7.79 bnd_c5_2 bnd_a517 bnd_a518 |
% 8.20/7.79 (bnd_ndr1_0 & ~ bnd_c2_1 bnd_a519) & bnd_c1_1 bnd_a519) |
% 8.20/7.79 ~ bnd_c2_0))
% 8.20/7.79 Adding axioms...
% 8.30/7.82 Typedef.type_definition_def
% 13.09/12.60 ...done.
% 13.09/12.61 Ground types: ?'b, TPTP_Interpret.ind
% 13.09/12.61 Translating term (sizes: 1, 1) ...
% 17.01/16.58 Invoking SAT solver...
% 17.11/16.69 Model found:
% 17.11/16.69 Size of types: ?'b: 1, TPTP_Interpret.ind: 1
% 17.11/16.69 bnd_a519: ??.TPTP_Interpret.ind0
% 17.11/16.69 bnd_a518: ??.TPTP_Interpret.ind0
% 17.11/16.69 bnd_a517: ??.TPTP_Interpret.ind0
% 17.11/16.69 bnd_a516: ??.TPTP_Interpret.ind0
% 17.11/16.69 bnd_a515: ??.TPTP_Interpret.ind0
% 17.11/16.69 bnd_a514: ??.TPTP_Interpret.ind0
% 17.11/16.69 bnd_a513: ??.TPTP_Interpret.ind0
% 17.11/16.69 bnd_a512: ??.TPTP_Interpret.ind0
% 17.11/16.69 bnd_a511: ??.TPTP_Interpret.ind0
% 17.11/16.69 bnd_a510: ??.TPTP_Interpret.ind0
% 17.11/16.69 bnd_a509: ??.TPTP_Interpret.ind0
% 17.11/16.69 bnd_a508: ??.TPTP_Interpret.ind0
% 17.11/16.69 bnd_a507: ??.TPTP_Interpret.ind0
% 17.11/16.69 bnd_a506: ??.TPTP_Interpret.ind0
% 17.11/16.69 bnd_a505: ??.TPTP_Interpret.ind0
% 17.11/16.69 bnd_a504: ??.TPTP_Interpret.ind0
% 17.11/16.69 bnd_a503: ??.TPTP_Interpret.ind0
% 17.11/16.69 bnd_c1_1: {(??.TPTP_Interpret.ind0, True)}
% 17.11/16.69 bnd_a502: ??.TPTP_Interpret.ind0
% 17.11/16.69 bnd_a501: ??.TPTP_Interpret.ind0
% 17.11/16.69 bnd_a500: ??.TPTP_Interpret.ind0
% 17.11/16.69 bnd_c2_0: True
% 17.11/16.69 bnd_a499: ??.TPTP_Interpret.ind0
% 17.11/16.69 bnd_a498: ??.TPTP_Interpret.ind0
% 17.11/16.69 bnd_a497: ??.TPTP_Interpret.ind0
% 17.11/16.69 bnd_a496: ??.TPTP_Interpret.ind0
% 17.11/16.69 bnd_a495: ??.TPTP_Interpret.ind0
% 17.11/16.69 bnd_c4_2: {(??.TPTP_Interpret.ind0, {(??.TPTP_Interpret.ind0, True)})}
% 17.11/16.69 bnd_c1_2: {(??.TPTP_Interpret.ind0, {(??.TPTP_Interpret.ind0, True)})}
% 17.11/16.69 bnd_a494: ??.TPTP_Interpret.ind0
% 17.11/16.69 bnd_c3_1: {(??.TPTP_Interpret.ind0, False)}
% 17.11/16.69 bnd_c2_2: {(??.TPTP_Interpret.ind0, {(??.TPTP_Interpret.ind0, False)})}
% 17.11/16.69 bnd_c3_2: {(??.TPTP_Interpret.ind0, {(??.TPTP_Interpret.ind0, False)})}
% 17.11/16.69 bnd_a493: ??.TPTP_Interpret.ind0
% 17.11/16.69 bnd_c5_2: {(??.TPTP_Interpret.ind0, {(??.TPTP_Interpret.ind0, False)})}
% 17.11/16.69 bnd_ndr1_1: {(??.TPTP_Interpret.ind0, True)}
% 17.11/16.69 bnd_a492: ??.TPTP_Interpret.ind0
% 17.11/16.69 bnd_c2_1: {(??.TPTP_Interpret.ind0, False)}
% 17.11/16.69 bnd_c5_0: False
% 17.11/16.69 bnd_c5_1: {(??.TPTP_Interpret.ind0, True)}
% 17.11/16.69 bnd_c4_1: {(??.TPTP_Interpret.ind0, False)}
% 17.11/16.69 bnd_ndr1_0: True
% 17.11/16.69 bnd_c3_0: True
% 17.11/16.69 bnd_c1_0: False
% 17.11/16.69 bnd_c4_0: True
% 17.11/16.69
% 17.11/16.69 % SZS status CounterSatisfiable
%------------------------------------------------------------------------------