TSTP Solution File: SYN532+1 by Refute---2015
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%------------------------------------------------------------------------------
% File : Refute---2015
% Problem : SYN532+1 : TPTP v6.4.0. Released v2.1.0.
% Transfm : none
% Format : tptp:raw
% Command : isabelle tptp_refute %d %s
% Computer : n118.star.cs.uiowa.edu
% Model : x86_64 x86_64
% CPU : Intel(R) Xeon(R) CPU E5-2609 0 2.40GHz
% Memory : 32218.75MB
% OS : Linux 3.10.0-327.10.1.el7.x86_64
% CPULimit : 300s
% DateTime : Thu Apr 14 06:42:16 EDT 2016
% Result : CounterSatisfiable 17.04s
% Output : Assurance 0s
% Verified :
% SZS Type : None (Parsing solution fails)
% Syntax : Number of formulae : 0
% Comments :
%------------------------------------------------------------------------------
%----No solution output by system
%------------------------------------------------------------------------------
%----ORIGINAL SYSTEM OUTPUT
% 0.00/0.03 % Problem : SYN532+1 : TPTP v6.4.0. Released v2.1.0.
% 0.00/0.04 % Command : isabelle tptp_refute %d %s
% 0.03/0.23 % Computer : n118.star.cs.uiowa.edu
% 0.03/0.23 % Model : x86_64 x86_64
% 0.03/0.23 % CPU : Intel(R) Xeon(R) CPU E5-2609 0 @ 2.40GHz
% 0.03/0.23 % Memory : 32218.75MB
% 0.03/0.23 % OS : Linux 3.10.0-327.10.1.el7.x86_64
% 0.03/0.23 % CPULimit : 300
% 0.03/0.23 % DateTime : Sat Apr 9 00:14:39 CDT 2016
% 0.03/0.23 % CPUTime:
% 6.30/5.84 > val it = (): unit
% 6.60/6.14 Trying to find a model that refutes: ~ (((((((((((((((((((((~ bnd_c3_0 | bnd_c5_0) |
% 6.60/6.14 ((bnd_ndr1_0 &
% 6.60/6.14 (ALL U.
% 6.60/6.14 bnd_ndr1_1 bnd_a411 -->
% 6.60/6.14 (bnd_c1_2 bnd_a411 U | bnd_c3_2 bnd_a411 U) |
% 6.60/6.14 bnd_c5_2 bnd_a411 U)) &
% 6.60/6.14 bnd_c2_1 bnd_a411) &
% 6.60/6.14 bnd_c1_1 bnd_a411) &
% 6.60/6.14 (((ALL V. bnd_ndr1_0 --> bnd_c5_1 V | ~ bnd_c3_1 V) |
% 6.60/6.14 ~ bnd_c3_0) |
% 6.60/6.14 ~ bnd_c4_0)) &
% 6.60/6.14 (((ALL W. bnd_ndr1_0 --> ~ bnd_c2_1 W) |
% 6.60/6.14 ((bnd_ndr1_0 & ~ bnd_c4_1 bnd_a412) &
% 6.60/6.14 (ALL X.
% 6.60/6.14 bnd_ndr1_1 bnd_a412 -->
% 6.60/6.14 ~ bnd_c2_2 bnd_a412 X | bnd_c3_2 bnd_a412 X)) &
% 6.60/6.14 ~ bnd_c2_1 bnd_a412) |
% 6.60/6.14 (((((bnd_ndr1_0 & ~ bnd_c2_1 bnd_a413) &
% 6.60/6.14 bnd_ndr1_1 bnd_a413) &
% 6.60/6.14 ~ bnd_c3_2 bnd_a413 bnd_a414) &
% 6.60/6.14 ~ bnd_c5_2 bnd_a413 bnd_a414) &
% 6.60/6.14 bnd_c1_2 bnd_a413 bnd_a414) &
% 6.60/6.14 (ALL Y.
% 6.60/6.14 bnd_ndr1_1 bnd_a413 -->
% 6.60/6.14 bnd_c5_2 bnd_a413 Y | ~ bnd_c1_2 bnd_a413 Y))) &
% 6.60/6.14 ((~ bnd_c4_0 | ~ bnd_c5_0) |
% 6.60/6.14 ((bnd_ndr1_0 & bnd_c2_1 bnd_a415) &
% 6.60/6.14 ~ bnd_c4_1 bnd_a415) &
% 6.60/6.14 bnd_c5_1 bnd_a415)) &
% 6.60/6.14 ((((bnd_ndr1_0 &
% 6.60/6.14 (ALL Z.
% 6.60/6.14 bnd_ndr1_1 bnd_a416 -->
% 6.60/6.14 ~ bnd_c5_2 bnd_a416 Z | ~ bnd_c2_2 bnd_a416 Z)) &
% 6.60/6.14 bnd_c2_1 bnd_a416) &
% 6.60/6.14 (ALL X1. bnd_ndr1_1 bnd_a416 --> bnd_c5_2 bnd_a416 X1) |
% 6.60/6.14 (ALL X2.
% 6.60/6.14 bnd_ndr1_0 -->
% 6.60/6.14 (bnd_ndr1_1 X2 & ~ bnd_c4_2 X2 bnd_a417) &
% 6.60/6.14 bnd_c2_2 X2 bnd_a417 |
% 6.60/6.14 ~ bnd_c2_1 X2)) |
% 6.60/6.14 ((((bnd_ndr1_0 & bnd_c2_1 bnd_a418) &
% 6.60/6.14 bnd_ndr1_1 bnd_a418) &
% 6.60/6.14 bnd_c4_2 bnd_a418 bnd_a419) &
% 6.60/6.14 ~ bnd_c5_2 bnd_a418 bnd_a419) &
% 6.60/6.14 ~ bnd_c3_2 bnd_a418 bnd_a419)) &
% 6.60/6.14 (((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a420) &
% 6.60/6.14 ~ bnd_c4_2 bnd_a420 bnd_a421) &
% 6.60/6.14 bnd_c1_2 bnd_a420 bnd_a421) &
% 6.60/6.14 bnd_c4_1 bnd_a420) &
% 6.60/6.14 bnd_c5_1 bnd_a420 |
% 6.60/6.14 bnd_c4_0)) &
% 6.60/6.14 (((ALL X3.
% 6.60/6.14 bnd_ndr1_0 -->
% 6.60/6.14 (ALL X4.
% 6.60/6.14 bnd_ndr1_1 X3 -->
% 6.60/6.14 (~ bnd_c4_2 X3 X4 | ~ bnd_c2_2 X3 X4) |
% 6.60/6.14 bnd_c5_2 X3 X4) |
% 6.60/6.14 (ALL X5.
% 6.60/6.14 bnd_ndr1_1 X3 -->
% 6.60/6.14 (~ bnd_c2_2 X3 X5 | ~ bnd_c3_2 X3 X5) |
% 6.60/6.14 bnd_c1_2 X3 X5)) |
% 6.60/6.14 bnd_c4_0) |
% 6.60/6.14 ~ bnd_c3_0)) &
% 6.60/6.14 ((~ bnd_c1_0 | ~ bnd_c3_0) | ~ bnd_c5_0)) &
% 6.60/6.14 ((bnd_c1_0 | ~ bnd_c4_0) | bnd_c5_0)) &
% 6.60/6.14 ((bnd_c5_0 | ~ bnd_c3_0) | bnd_c2_0)) &
% 6.60/6.14 ((bnd_c1_0 |
% 6.60/6.14 (((((bnd_ndr1_0 & ~ bnd_c2_1 bnd_a422) &
% 6.60/6.14 bnd_ndr1_1 bnd_a422) &
% 6.60/6.14 bnd_c1_2 bnd_a422 bnd_a423) &
% 6.60/6.14 bnd_c5_2 bnd_a422 bnd_a423) &
% 6.60/6.14 ~ bnd_c2_2 bnd_a422 bnd_a423) &
% 6.60/6.14 ~ bnd_c4_1 bnd_a422) |
% 6.60/6.14 ~ bnd_c3_0)) &
% 6.60/6.14 ((bnd_c5_0 |
% 6.60/6.14 (ALL X6.
% 6.60/6.14 bnd_ndr1_0 -->
% 6.60/6.14 (bnd_c2_1 X6 | bnd_c3_1 X6) |
% 6.60/6.14 ((bnd_ndr1_1 X6 & bnd_c2_2 X6 bnd_a424) &
% 6.60/6.14 ~ bnd_c3_2 X6 bnd_a424) &
% 6.60/6.14 ~ bnd_c5_2 X6 bnd_a424)) |
% 6.60/6.14 (ALL X7.
% 6.60/6.14 bnd_ndr1_0 -->
% 6.60/6.14 (bnd_c5_1 X7 | bnd_c2_1 X7) | ~ bnd_c4_1 X7))) &
% 6.60/6.14 ((bnd_c4_0 | ~ bnd_c3_0) | bnd_c1_0)) &
% 6.60/6.14 ((((((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a425) &
% 6.60/6.14 ~ bnd_c2_2 bnd_a425 bnd_a426) &
% 6.60/6.14 bnd_c4_2 bnd_a425 bnd_a426) &
% 6.60/6.14 ~ bnd_c5_2 bnd_a425 bnd_a426) &
% 6.60/6.14 ~ bnd_c3_1 bnd_a425) &
% 6.60/6.14 bnd_ndr1_1 bnd_a425) &
% 6.60/6.14 ~ bnd_c5_2 bnd_a425 bnd_a427) &
% 6.60/6.14 ~ bnd_c3_2 bnd_a425 bnd_a427) &
% 6.60/6.14 bnd_c2_2 bnd_a425 bnd_a427 |
% 6.60/6.14 (ALL X8.
% 6.60/6.14 bnd_ndr1_0 -->
% 6.60/6.14 ((bnd_ndr1_1 X8 & ~ bnd_c4_2 X8 bnd_a428) &
% 6.60/6.14 ~ bnd_c3_2 X8 bnd_a428 |
% 6.60/6.14 ((bnd_ndr1_1 X8 & bnd_c1_2 X8 bnd_a429) &
% 6.60/6.14 ~ bnd_c4_2 X8 bnd_a429) &
% 6.60/6.14 ~ bnd_c5_2 X8 bnd_a429) |
% 6.60/6.14 ((bnd_ndr1_1 X8 & bnd_c1_2 X8 bnd_a430) &
% 6.60/6.14 ~ bnd_c4_2 X8 bnd_a430) &
% 6.60/6.14 bnd_c5_2 X8 bnd_a430)) |
% 6.60/6.14 (bnd_ndr1_0 & bnd_c3_1 bnd_a431) & ~ bnd_c1_1 bnd_a431)) &
% 6.60/6.14 ((bnd_c1_0 |
% 6.60/6.14 ((((bnd_ndr1_0 &
% 6.60/6.14 (ALL X9.
% 6.60/6.14 bnd_ndr1_1 bnd_a432 -->
% 6.60/6.14 (~ bnd_c2_2 bnd_a432 X9 | bnd_c5_2 bnd_a432 X9) |
% 6.60/6.14 bnd_c4_2 bnd_a432 X9)) &
% 6.60/6.14 ~ bnd_c1_1 bnd_a432) &
% 6.60/6.14 bnd_ndr1_1 bnd_a432) &
% 6.60/6.14 ~ bnd_c3_2 bnd_a432 bnd_a433) &
% 6.60/6.14 ~ bnd_c2_2 bnd_a432 bnd_a433) |
% 6.60/6.14 bnd_c5_0)) &
% 6.60/6.14 (~ bnd_c3_0 | bnd_c1_0)) &
% 6.60/6.14 (((((((((bnd_ndr1_0 &
% 6.60/6.14 (ALL X10.
% 6.60/6.14 bnd_ndr1_1 bnd_a434 -->
% 6.60/6.14 (~ bnd_c4_2 bnd_a434 X10 | bnd_c2_2 bnd_a434 X10) |
% 6.60/6.14 ~ bnd_c3_2 bnd_a434 X10)) &
% 6.60/6.14 bnd_ndr1_1 bnd_a434) &
% 6.60/6.14 bnd_c5_2 bnd_a434 bnd_a435) &
% 6.60/6.14 bnd_c4_2 bnd_a434 bnd_a435) &
% 6.60/6.14 bnd_c3_2 bnd_a434 bnd_a435) &
% 6.60/6.14 bnd_ndr1_1 bnd_a434) &
% 6.60/6.14 ~ bnd_c5_2 bnd_a434 bnd_a436) &
% 6.60/6.14 bnd_c3_2 bnd_a434 bnd_a436 |
% 6.60/6.14 bnd_ndr1_0 & bnd_c4_1 bnd_a437) |
% 6.60/6.14 ((bnd_ndr1_0 & ~ bnd_c5_1 bnd_a438) & bnd_c1_1 bnd_a438) &
% 6.60/6.14 bnd_c2_1 bnd_a438)) &
% 6.60/6.14 ((bnd_ndr1_0 & bnd_c5_1 bnd_a439) &
% 6.60/6.14 (ALL X11.
% 6.60/6.14 bnd_ndr1_1 bnd_a439 -->
% 6.60/6.14 bnd_c5_2 bnd_a439 X11 | bnd_c3_2 bnd_a439 X11) |
% 6.60/6.14 bnd_c3_0)) &
% 6.60/6.14 ((bnd_c5_0 | bnd_c1_0) |
% 6.60/6.14 ((bnd_ndr1_0 &
% 6.60/6.14 (ALL X12.
% 6.60/6.14 bnd_ndr1_1 bnd_a440 -->
% 6.60/6.14 (bnd_c2_2 bnd_a440 X12 | ~ bnd_c3_2 bnd_a440 X12) |
% 6.60/6.14 bnd_c4_2 bnd_a440 X12)) &
% 6.60/6.14 ~ bnd_c5_1 bnd_a440) &
% 6.60/6.14 bnd_c4_1 bnd_a440)) &
% 6.60/6.14 ((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a441) & bnd_c3_2 bnd_a441 bnd_a442) &
% 6.60/6.14 ~ bnd_c1_2 bnd_a441 bnd_a442) &
% 6.60/6.14 (ALL X13.
% 6.60/6.14 bnd_ndr1_1 bnd_a441 -->
% 6.60/6.14 bnd_c5_2 bnd_a441 X13 | ~ bnd_c4_2 bnd_a441 X13)) &
% 6.60/6.14 bnd_c2_1 bnd_a441 |
% 6.60/6.14 (ALL X14.
% 6.60/6.14 bnd_ndr1_0 --> (bnd_c5_1 X14 | bnd_c2_1 X14) | ~ bnd_c1_1 X14)) |
% 6.60/6.14 bnd_c4_0))
% 8.31/7.80 Unfolded term: ~ (((((((((((((((((((((~ bnd_c3_0 | bnd_c5_0) |
% 8.31/7.80 ((bnd_ndr1_0 &
% 8.31/7.80 (ALL U.
% 8.31/7.80 bnd_ndr1_1 bnd_a411 -->
% 8.31/7.80 (bnd_c1_2 bnd_a411 U | bnd_c3_2 bnd_a411 U) |
% 8.31/7.80 bnd_c5_2 bnd_a411 U)) &
% 8.31/7.80 bnd_c2_1 bnd_a411) &
% 8.31/7.80 bnd_c1_1 bnd_a411) &
% 8.31/7.80 (((ALL V. bnd_ndr1_0 --> bnd_c5_1 V | ~ bnd_c3_1 V) |
% 8.31/7.80 ~ bnd_c3_0) |
% 8.31/7.80 ~ bnd_c4_0)) &
% 8.31/7.80 (((ALL W. bnd_ndr1_0 --> ~ bnd_c2_1 W) |
% 8.31/7.80 ((bnd_ndr1_0 & ~ bnd_c4_1 bnd_a412) &
% 8.31/7.80 (ALL X.
% 8.31/7.80 bnd_ndr1_1 bnd_a412 -->
% 8.31/7.80 ~ bnd_c2_2 bnd_a412 X | bnd_c3_2 bnd_a412 X)) &
% 8.31/7.80 ~ bnd_c2_1 bnd_a412) |
% 8.31/7.80 (((((bnd_ndr1_0 & ~ bnd_c2_1 bnd_a413) &
% 8.31/7.80 bnd_ndr1_1 bnd_a413) &
% 8.31/7.80 ~ bnd_c3_2 bnd_a413 bnd_a414) &
% 8.31/7.80 ~ bnd_c5_2 bnd_a413 bnd_a414) &
% 8.31/7.80 bnd_c1_2 bnd_a413 bnd_a414) &
% 8.31/7.80 (ALL Y.
% 8.31/7.80 bnd_ndr1_1 bnd_a413 -->
% 8.31/7.80 bnd_c5_2 bnd_a413 Y | ~ bnd_c1_2 bnd_a413 Y))) &
% 8.31/7.80 ((~ bnd_c4_0 | ~ bnd_c5_0) |
% 8.31/7.80 ((bnd_ndr1_0 & bnd_c2_1 bnd_a415) &
% 8.31/7.80 ~ bnd_c4_1 bnd_a415) &
% 8.31/7.80 bnd_c5_1 bnd_a415)) &
% 8.31/7.80 ((((bnd_ndr1_0 &
% 8.31/7.80 (ALL Z.
% 8.31/7.80 bnd_ndr1_1 bnd_a416 -->
% 8.31/7.80 ~ bnd_c5_2 bnd_a416 Z | ~ bnd_c2_2 bnd_a416 Z)) &
% 8.31/7.80 bnd_c2_1 bnd_a416) &
% 8.31/7.80 (ALL X1. bnd_ndr1_1 bnd_a416 --> bnd_c5_2 bnd_a416 X1) |
% 8.31/7.80 (ALL X2.
% 8.31/7.80 bnd_ndr1_0 -->
% 8.31/7.80 (bnd_ndr1_1 X2 & ~ bnd_c4_2 X2 bnd_a417) &
% 8.31/7.80 bnd_c2_2 X2 bnd_a417 |
% 8.31/7.80 ~ bnd_c2_1 X2)) |
% 8.31/7.80 ((((bnd_ndr1_0 & bnd_c2_1 bnd_a418) &
% 8.31/7.80 bnd_ndr1_1 bnd_a418) &
% 8.31/7.80 bnd_c4_2 bnd_a418 bnd_a419) &
% 8.31/7.80 ~ bnd_c5_2 bnd_a418 bnd_a419) &
% 8.31/7.80 ~ bnd_c3_2 bnd_a418 bnd_a419)) &
% 8.31/7.80 (((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a420) &
% 8.31/7.80 ~ bnd_c4_2 bnd_a420 bnd_a421) &
% 8.31/7.80 bnd_c1_2 bnd_a420 bnd_a421) &
% 8.31/7.80 bnd_c4_1 bnd_a420) &
% 8.31/7.80 bnd_c5_1 bnd_a420 |
% 8.31/7.80 bnd_c4_0)) &
% 8.31/7.80 (((ALL X3.
% 8.31/7.80 bnd_ndr1_0 -->
% 8.31/7.80 (ALL X4.
% 8.31/7.80 bnd_ndr1_1 X3 -->
% 8.31/7.80 (~ bnd_c4_2 X3 X4 | ~ bnd_c2_2 X3 X4) |
% 8.31/7.80 bnd_c5_2 X3 X4) |
% 8.31/7.80 (ALL X5.
% 8.31/7.80 bnd_ndr1_1 X3 -->
% 8.31/7.80 (~ bnd_c2_2 X3 X5 | ~ bnd_c3_2 X3 X5) |
% 8.31/7.80 bnd_c1_2 X3 X5)) |
% 8.31/7.80 bnd_c4_0) |
% 8.31/7.80 ~ bnd_c3_0)) &
% 8.31/7.80 ((~ bnd_c1_0 | ~ bnd_c3_0) | ~ bnd_c5_0)) &
% 8.31/7.80 ((bnd_c1_0 | ~ bnd_c4_0) | bnd_c5_0)) &
% 8.31/7.80 ((bnd_c5_0 | ~ bnd_c3_0) | bnd_c2_0)) &
% 8.31/7.80 ((bnd_c1_0 |
% 8.31/7.80 (((((bnd_ndr1_0 & ~ bnd_c2_1 bnd_a422) &
% 8.31/7.80 bnd_ndr1_1 bnd_a422) &
% 8.31/7.80 bnd_c1_2 bnd_a422 bnd_a423) &
% 8.31/7.80 bnd_c5_2 bnd_a422 bnd_a423) &
% 8.31/7.80 ~ bnd_c2_2 bnd_a422 bnd_a423) &
% 8.31/7.80 ~ bnd_c4_1 bnd_a422) |
% 8.31/7.80 ~ bnd_c3_0)) &
% 8.31/7.80 ((bnd_c5_0 |
% 8.31/7.80 (ALL X6.
% 8.31/7.80 bnd_ndr1_0 -->
% 8.31/7.80 (bnd_c2_1 X6 | bnd_c3_1 X6) |
% 8.31/7.80 ((bnd_ndr1_1 X6 & bnd_c2_2 X6 bnd_a424) &
% 8.31/7.80 ~ bnd_c3_2 X6 bnd_a424) &
% 8.31/7.80 ~ bnd_c5_2 X6 bnd_a424)) |
% 8.31/7.80 (ALL X7.
% 8.31/7.80 bnd_ndr1_0 -->
% 8.31/7.80 (bnd_c5_1 X7 | bnd_c2_1 X7) | ~ bnd_c4_1 X7))) &
% 8.31/7.80 ((bnd_c4_0 | ~ bnd_c3_0) | bnd_c1_0)) &
% 8.31/7.80 ((((((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a425) &
% 8.31/7.80 ~ bnd_c2_2 bnd_a425 bnd_a426) &
% 8.31/7.80 bnd_c4_2 bnd_a425 bnd_a426) &
% 8.31/7.80 ~ bnd_c5_2 bnd_a425 bnd_a426) &
% 8.31/7.80 ~ bnd_c3_1 bnd_a425) &
% 8.31/7.80 bnd_ndr1_1 bnd_a425) &
% 8.31/7.80 ~ bnd_c5_2 bnd_a425 bnd_a427) &
% 8.31/7.80 ~ bnd_c3_2 bnd_a425 bnd_a427) &
% 8.31/7.80 bnd_c2_2 bnd_a425 bnd_a427 |
% 8.31/7.80 (ALL X8.
% 8.31/7.80 bnd_ndr1_0 -->
% 8.31/7.80 ((bnd_ndr1_1 X8 & ~ bnd_c4_2 X8 bnd_a428) &
% 8.31/7.80 ~ bnd_c3_2 X8 bnd_a428 |
% 8.31/7.80 ((bnd_ndr1_1 X8 & bnd_c1_2 X8 bnd_a429) &
% 8.31/7.80 ~ bnd_c4_2 X8 bnd_a429) &
% 8.31/7.80 ~ bnd_c5_2 X8 bnd_a429) |
% 8.31/7.80 ((bnd_ndr1_1 X8 & bnd_c1_2 X8 bnd_a430) &
% 8.31/7.80 ~ bnd_c4_2 X8 bnd_a430) &
% 8.31/7.80 bnd_c5_2 X8 bnd_a430)) |
% 8.31/7.80 (bnd_ndr1_0 & bnd_c3_1 bnd_a431) & ~ bnd_c1_1 bnd_a431)) &
% 8.31/7.80 ((bnd_c1_0 |
% 8.31/7.80 ((((bnd_ndr1_0 &
% 8.31/7.80 (ALL X9.
% 8.31/7.80 bnd_ndr1_1 bnd_a432 -->
% 8.31/7.80 (~ bnd_c2_2 bnd_a432 X9 | bnd_c5_2 bnd_a432 X9) |
% 8.31/7.80 bnd_c4_2 bnd_a432 X9)) &
% 8.31/7.80 ~ bnd_c1_1 bnd_a432) &
% 8.31/7.80 bnd_ndr1_1 bnd_a432) &
% 8.31/7.80 ~ bnd_c3_2 bnd_a432 bnd_a433) &
% 8.31/7.80 ~ bnd_c2_2 bnd_a432 bnd_a433) |
% 8.31/7.80 bnd_c5_0)) &
% 8.31/7.80 (~ bnd_c3_0 | bnd_c1_0)) &
% 8.31/7.80 (((((((((bnd_ndr1_0 &
% 8.31/7.80 (ALL X10.
% 8.31/7.80 bnd_ndr1_1 bnd_a434 -->
% 8.31/7.80 (~ bnd_c4_2 bnd_a434 X10 | bnd_c2_2 bnd_a434 X10) |
% 8.31/7.80 ~ bnd_c3_2 bnd_a434 X10)) &
% 8.31/7.80 bnd_ndr1_1 bnd_a434) &
% 8.31/7.80 bnd_c5_2 bnd_a434 bnd_a435) &
% 8.31/7.80 bnd_c4_2 bnd_a434 bnd_a435) &
% 8.31/7.80 bnd_c3_2 bnd_a434 bnd_a435) &
% 8.31/7.80 bnd_ndr1_1 bnd_a434) &
% 8.31/7.80 ~ bnd_c5_2 bnd_a434 bnd_a436) &
% 8.31/7.80 bnd_c3_2 bnd_a434 bnd_a436 |
% 8.31/7.80 bnd_ndr1_0 & bnd_c4_1 bnd_a437) |
% 8.31/7.80 ((bnd_ndr1_0 & ~ bnd_c5_1 bnd_a438) & bnd_c1_1 bnd_a438) &
% 8.31/7.80 bnd_c2_1 bnd_a438)) &
% 8.31/7.80 ((bnd_ndr1_0 & bnd_c5_1 bnd_a439) &
% 8.31/7.80 (ALL X11.
% 8.31/7.80 bnd_ndr1_1 bnd_a439 -->
% 8.31/7.80 bnd_c5_2 bnd_a439 X11 | bnd_c3_2 bnd_a439 X11) |
% 8.31/7.80 bnd_c3_0)) &
% 8.31/7.80 ((bnd_c5_0 | bnd_c1_0) |
% 8.31/7.80 ((bnd_ndr1_0 &
% 8.31/7.80 (ALL X12.
% 8.31/7.80 bnd_ndr1_1 bnd_a440 -->
% 8.31/7.80 (bnd_c2_2 bnd_a440 X12 | ~ bnd_c3_2 bnd_a440 X12) |
% 8.31/7.80 bnd_c4_2 bnd_a440 X12)) &
% 8.31/7.80 ~ bnd_c5_1 bnd_a440) &
% 8.31/7.80 bnd_c4_1 bnd_a440)) &
% 8.31/7.80 ((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a441) & bnd_c3_2 bnd_a441 bnd_a442) &
% 8.31/7.80 ~ bnd_c1_2 bnd_a441 bnd_a442) &
% 8.31/7.80 (ALL X13.
% 8.31/7.80 bnd_ndr1_1 bnd_a441 -->
% 8.31/7.80 bnd_c5_2 bnd_a441 X13 | ~ bnd_c4_2 bnd_a441 X13)) &
% 8.31/7.80 bnd_c2_1 bnd_a441 |
% 8.31/7.80 (ALL X14.
% 8.31/7.80 bnd_ndr1_0 --> (bnd_c5_1 X14 | bnd_c2_1 X14) | ~ bnd_c1_1 X14)) |
% 8.31/7.80 bnd_c4_0))
% 8.31/7.80 Adding axioms...
% 8.31/7.82 Typedef.type_definition_def
% 13.02/12.59 ...done.
% 13.12/12.60 Ground types: ?'b, TPTP_Interpret.ind
% 13.12/12.60 Translating term (sizes: 1, 1) ...
% 16.94/16.43 Invoking SAT solver...
% 17.04/16.55 Model found:
% 17.04/16.55 Size of types: ?'b: 1, TPTP_Interpret.ind: 1
% 17.04/16.55 bnd_a442: ??.TPTP_Interpret.ind0
% 17.04/16.55 bnd_a441: ??.TPTP_Interpret.ind0
% 17.04/16.55 bnd_a440: ??.TPTP_Interpret.ind0
% 17.04/16.55 bnd_a439: ??.TPTP_Interpret.ind0
% 17.04/16.55 bnd_a438: ??.TPTP_Interpret.ind0
% 17.04/16.55 bnd_a437: ??.TPTP_Interpret.ind0
% 17.04/16.55 bnd_a436: ??.TPTP_Interpret.ind0
% 17.04/16.55 bnd_a435: ??.TPTP_Interpret.ind0
% 17.04/16.55 bnd_a434: ??.TPTP_Interpret.ind0
% 17.04/16.55 bnd_a433: ??.TPTP_Interpret.ind0
% 17.04/16.55 bnd_a432: ??.TPTP_Interpret.ind0
% 17.04/16.55 bnd_a431: ??.TPTP_Interpret.ind0
% 17.04/16.55 bnd_a430: ??.TPTP_Interpret.ind0
% 17.04/16.55 bnd_a429: ??.TPTP_Interpret.ind0
% 17.04/16.55 bnd_a428: ??.TPTP_Interpret.ind0
% 17.04/16.55 bnd_a427: ??.TPTP_Interpret.ind0
% 17.04/16.55 bnd_a426: ??.TPTP_Interpret.ind0
% 17.04/16.55 bnd_a425: ??.TPTP_Interpret.ind0
% 17.04/16.55 bnd_a424: ??.TPTP_Interpret.ind0
% 17.04/16.55 bnd_a423: ??.TPTP_Interpret.ind0
% 17.04/16.55 bnd_a422: ??.TPTP_Interpret.ind0
% 17.04/16.55 bnd_c2_0: True
% 17.04/16.55 bnd_c1_0: True
% 17.04/16.55 bnd_a421: ??.TPTP_Interpret.ind0
% 17.04/16.55 bnd_a420: ??.TPTP_Interpret.ind0
% 17.04/16.55 bnd_a419: ??.TPTP_Interpret.ind0
% 17.04/16.55 bnd_a418: ??.TPTP_Interpret.ind0
% 17.04/16.55 bnd_a417: ??.TPTP_Interpret.ind0
% 17.04/16.55 bnd_c4_2: {(??.TPTP_Interpret.ind0, {(??.TPTP_Interpret.ind0, False)})}
% 17.04/16.55 bnd_a416: ??.TPTP_Interpret.ind0
% 17.04/16.55 bnd_a415: ??.TPTP_Interpret.ind0
% 17.04/16.55 bnd_a414: ??.TPTP_Interpret.ind0
% 17.04/16.55 bnd_a413: ??.TPTP_Interpret.ind0
% 17.04/16.55 bnd_c2_2: {(??.TPTP_Interpret.ind0, {(??.TPTP_Interpret.ind0, False)})}
% 17.04/16.55 bnd_a412: ??.TPTP_Interpret.ind0
% 17.04/16.55 bnd_c4_1: {(??.TPTP_Interpret.ind0, True)}
% 17.04/16.55 bnd_c4_0: True
% 17.04/16.55 bnd_c3_1: {(??.TPTP_Interpret.ind0, True)}
% 17.04/16.55 bnd_c5_1: {(??.TPTP_Interpret.ind0, True)}
% 17.04/16.55 bnd_c1_1: {(??.TPTP_Interpret.ind0, False)}
% 17.04/16.55 bnd_c2_1: {(??.TPTP_Interpret.ind0, False)}
% 17.04/16.55 bnd_c5_2: {(??.TPTP_Interpret.ind0, {(??.TPTP_Interpret.ind0, True)})}
% 17.04/16.55 bnd_c3_2: {(??.TPTP_Interpret.ind0, {(??.TPTP_Interpret.ind0, False)})}
% 17.04/16.55 bnd_c1_2: {(??.TPTP_Interpret.ind0, {(??.TPTP_Interpret.ind0, True)})}
% 17.04/16.55 bnd_a411: ??.TPTP_Interpret.ind0
% 17.04/16.55 bnd_ndr1_1: {(??.TPTP_Interpret.ind0, True)}
% 17.04/16.55 bnd_ndr1_0: True
% 17.04/16.55 bnd_c5_0: False
% 17.04/16.55 bnd_c3_0: False
% 17.04/16.55
% 17.04/16.55 % SZS status CounterSatisfiable
%------------------------------------------------------------------------------