TSTP Solution File: SYN520+1 by Refute---2015
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%------------------------------------------------------------------------------
% File : Refute---2015
% Problem : SYN520+1 : TPTP v6.4.0. Released v2.1.0.
% Transfm : none
% Format : tptp:raw
% Command : isabelle tptp_refute %d %s
% Computer : n040.star.cs.uiowa.edu
% Model : x86_64 x86_64
% CPU : Intel(R) Xeon(R) CPU E5-2609 0 2.40GHz
% Memory : 32218.75MB
% OS : Linux 3.10.0-327.10.1.el7.x86_64
% CPULimit : 300s
% DateTime : Thu Apr 14 06:42:13 EDT 2016
% Result : Timeout 300.03s
% Output : None
% Verified :
% SZS Type : None (Parsing solution fails)
% Syntax : Number of formulae : 0
% Comments :
%------------------------------------------------------------------------------
%----No solution output by system
%------------------------------------------------------------------------------
%----ORIGINAL SYSTEM OUTPUT
% 0.00/0.03 % Problem : SYN520+1 : TPTP v6.4.0. Released v2.1.0.
% 0.00/0.04 % Command : isabelle tptp_refute %d %s
% 0.03/0.23 % Computer : n040.star.cs.uiowa.edu
% 0.03/0.23 % Model : x86_64 x86_64
% 0.03/0.23 % CPU : Intel(R) Xeon(R) CPU E5-2609 0 @ 2.40GHz
% 0.03/0.23 % Memory : 32218.75MB
% 0.03/0.23 % OS : Linux 3.10.0-327.10.1.el7.x86_64
% 0.03/0.23 % CPULimit : 300
% 0.03/0.23 % DateTime : Sat Apr 9 00:12:24 CDT 2016
% 0.03/0.23 % CPUTime:
% 6.30/5.85 > val it = (): unit
% 7.21/6.77 Trying to find a model that refutes: ~ (((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((ALL U.
% 7.21/6.77 bnd_ndr1_0 -->
% 7.21/6.77 ((bnd_ndr1_1 U & ~ bnd_c5_2 U bnd_a1323) &
% 7.21/6.77 ~ bnd_c1_2 U bnd_a1323 |
% 7.21/6.77 (ALL V.
% 7.21/6.77 bnd_ndr1_1 U -->
% 7.21/6.77 ~ bnd_c1_2 U V | ~ bnd_c2_2 U V)) |
% 7.21/6.77 (ALL W.
% 7.21/6.77 bnd_ndr1_1 U -->
% 7.21/6.77 bnd_c4_2 U W | ~ bnd_c3_2 U W)) |
% 7.21/6.77 ~ bnd_c5_0) |
% 7.21/6.77 (ALL X. bnd_ndr1_0 --> bnd_c2_1 X)) &
% 7.21/6.77 ((ALL Y.
% 7.21/6.77 bnd_ndr1_0 -->
% 7.21/6.77 (((bnd_ndr1_1 Y & bnd_c3_2 Y bnd_a1324) &
% 7.21/6.77 bnd_c4_2 Y bnd_a1324) &
% 7.21/6.77 bnd_c5_2 Y bnd_a1324 |
% 7.21/6.77 ~ bnd_c4_1 Y) |
% 7.21/6.77 bnd_c3_1 Y) |
% 7.21/6.77 ((bnd_ndr1_0 & ~ bnd_c1_1 bnd_a1325) &
% 7.21/6.77 bnd_c2_1 bnd_a1325) &
% 7.21/6.77 ~ bnd_c4_1 bnd_a1325)) &
% 7.21/6.77 (~ bnd_c4_0 |
% 7.21/6.77 (ALL Z.
% 7.21/6.77 bnd_ndr1_0 -->
% 7.21/6.77 (bnd_c5_1 Z | ~ bnd_c4_1 Z) |
% 7.21/6.77 ((bnd_ndr1_1 Z & bnd_c5_2 Z bnd_a1326) &
% 7.21/6.77 bnd_c2_2 Z bnd_a1326) &
% 7.21/6.77 ~ bnd_c4_2 Z bnd_a1326))) &
% 7.21/6.77 (((((((bnd_ndr1_0 &
% 7.21/6.77 (ALL X1.
% 7.21/6.77 bnd_ndr1_1 bnd_a1327 -->
% 7.21/6.77 (bnd_c3_2 bnd_a1327 X1 |
% 7.21/6.77 bnd_c1_2 bnd_a1327 X1) |
% 7.21/6.77 bnd_c2_2 bnd_a1327 X1)) &
% 7.21/6.77 bnd_c3_1 bnd_a1327) &
% 7.21/6.77 bnd_ndr1_1 bnd_a1327) &
% 7.21/6.77 ~ bnd_c5_2 bnd_a1327 bnd_a1328) &
% 7.21/6.77 bnd_c3_2 bnd_a1327 bnd_a1328) &
% 7.21/6.77 bnd_c4_2 bnd_a1327 bnd_a1328 |
% 7.21/6.77 (ALL X2.
% 7.21/6.77 bnd_ndr1_0 -->
% 7.21/6.77 (((bnd_ndr1_1 X2 & ~ bnd_c1_2 X2 bnd_a1329) &
% 7.21/6.77 ~ bnd_c4_2 X2 bnd_a1329) &
% 7.21/6.77 bnd_c2_2 X2 bnd_a1329 |
% 7.21/6.77 ((bnd_ndr1_1 X2 & bnd_c1_2 X2 bnd_a1330) &
% 7.21/6.77 ~ bnd_c2_2 X2 bnd_a1330) &
% 7.21/6.77 bnd_c3_2 X2 bnd_a1330) |
% 7.21/6.77 (bnd_ndr1_1 X2 & bnd_c3_2 X2 bnd_a1331) &
% 7.21/6.77 bnd_c2_2 X2 bnd_a1331)) |
% 7.21/6.77 ~ bnd_c5_0)) &
% 7.21/6.77 ((~ bnd_c2_0 | ~ bnd_c4_0) | ~ bnd_c3_0)) &
% 7.21/6.77 ((bnd_c1_0 | ~ bnd_c4_0) |
% 7.21/6.77 ((bnd_ndr1_0 & bnd_c2_1 bnd_a1332) &
% 7.21/6.77 ~ bnd_c1_1 bnd_a1332) &
% 7.21/6.77 ~ bnd_c4_1 bnd_a1332)) &
% 7.21/6.77 ((bnd_c5_0 | ~ bnd_c3_0) |
% 7.21/6.77 (((((bnd_ndr1_0 & bnd_c1_1 bnd_a1333) &
% 7.21/6.77 (ALL X3.
% 7.21/6.77 bnd_ndr1_1 bnd_a1333 -->
% 7.21/6.77 (bnd_c4_2 bnd_a1333 X3 |
% 7.21/6.77 ~ bnd_c1_2 bnd_a1333 X3) |
% 7.21/6.77 ~ bnd_c3_2 bnd_a1333 X3)) &
% 7.21/6.77 bnd_ndr1_1 bnd_a1333) &
% 7.21/6.77 ~ bnd_c1_2 bnd_a1333 bnd_a1334) &
% 7.21/6.77 bnd_c5_2 bnd_a1333 bnd_a1334) &
% 7.21/6.77 bnd_c4_2 bnd_a1333 bnd_a1334)) &
% 7.21/6.77 ((~ bnd_c2_0 | bnd_c3_0) |
% 7.21/6.77 (ALL X4.
% 7.21/6.77 bnd_ndr1_0 -->
% 7.21/6.77 (bnd_c4_1 X4 |
% 7.21/6.77 (ALL X5.
% 7.21/6.77 bnd_ndr1_1 X4 -->
% 7.21/6.77 (~ bnd_c2_2 X4 X5 | ~ bnd_c5_2 X4 X5) |
% 7.21/6.77 bnd_c4_2 X4 X5)) |
% 7.21/6.77 bnd_c5_1 X4))) &
% 7.21/6.77 (((((((bnd_ndr1_0 &
% 7.21/6.77 (ALL X6.
% 7.21/6.77 bnd_ndr1_1 bnd_a1335 -->
% 7.21/6.77 bnd_c3_2 bnd_a1335 X6 |
% 7.21/6.77 ~ bnd_c5_2 bnd_a1335 X6)) &
% 7.21/6.77 bnd_ndr1_1 bnd_a1335) &
% 7.21/6.77 bnd_c5_2 bnd_a1335 bnd_a1336) &
% 7.21/6.77 ~ bnd_c2_2 bnd_a1335 bnd_a1336) &
% 7.21/6.77 ~ bnd_c4_2 bnd_a1335 bnd_a1336) &
% 7.21/6.77 ~ bnd_c3_1 bnd_a1335 |
% 7.21/6.77 ~ bnd_c3_0) |
% 7.21/6.77 (bnd_ndr1_0 & ~ bnd_c5_1 bnd_a1337) &
% 7.21/6.77 ~ bnd_c4_1 bnd_a1337)) &
% 7.21/6.77 (~ bnd_c1_0 |
% 7.21/6.77 ((bnd_ndr1_0 & ~ bnd_c4_1 bnd_a1338) &
% 7.21/6.77 (ALL X7.
% 7.21/6.77 bnd_ndr1_1 bnd_a1338 -->
% 7.21/6.77 (~ bnd_c2_2 bnd_a1338 X7 |
% 7.21/6.77 ~ bnd_c3_2 bnd_a1338 X7) |
% 7.21/6.77 ~ bnd_c5_2 bnd_a1338 X7)) &
% 7.21/6.77 ~ bnd_c2_1 bnd_a1338)) &
% 7.21/6.77 (((bnd_ndr1_0 & bnd_c5_1 bnd_a1339) &
% 7.21/6.77 ~ bnd_c1_1 bnd_a1339) &
% 7.21/6.77 (ALL X8.
% 7.21/6.77 bnd_ndr1_1 bnd_a1339 -->
% 7.21/6.77 (~ bnd_c1_2 bnd_a1339 X8 | ~ bnd_c5_2 bnd_a1339 X8) |
% 7.21/6.77 bnd_c4_2 bnd_a1339 X8) |
% 7.21/6.77 ~ bnd_c1_0)) &
% 7.21/6.77 (((ALL X9.
% 7.21/6.77 bnd_ndr1_0 -->
% 7.21/6.77 (bnd_c2_1 X9 |
% 7.21/6.77 (bnd_ndr1_1 X9 & ~ bnd_c4_2 X9 bnd_a1340) &
% 7.21/6.77 ~ bnd_c2_2 X9 bnd_a1340) |
% 7.21/6.77 (bnd_ndr1_1 X9 & bnd_c5_2 X9 bnd_a1341) &
% 7.21/6.77 ~ bnd_c4_2 X9 bnd_a1341) |
% 7.21/6.77 ~ bnd_c3_0) |
% 7.21/6.77 bnd_c4_0)) &
% 7.21/6.77 ((~ bnd_c4_0 |
% 7.21/6.77 (ALL X10.
% 7.21/6.77 bnd_ndr1_0 --> ~ bnd_c2_1 X10 | ~ bnd_c5_1 X10)) |
% 7.21/6.77 (ALL X11.
% 7.21/6.77 bnd_ndr1_0 --> ~ bnd_c5_1 X11 | ~ bnd_c2_1 X11))) &
% 7.21/6.77 ((((((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a1342) &
% 7.21/6.77 bnd_c1_2 bnd_a1342 bnd_a1343) &
% 7.21/6.77 bnd_c3_2 bnd_a1342 bnd_a1343) &
% 7.21/6.77 ~ bnd_c4_2 bnd_a1342 bnd_a1343) &
% 7.21/6.77 ~ bnd_c4_1 bnd_a1342) &
% 7.21/6.77 bnd_ndr1_1 bnd_a1342) &
% 7.21/6.77 bnd_c2_2 bnd_a1342 bnd_a1344) &
% 7.21/6.77 ~ bnd_c1_2 bnd_a1342 bnd_a1344) &
% 7.21/6.77 ~ bnd_c5_2 bnd_a1342 bnd_a1344 |
% 7.21/6.77 ((bnd_ndr1_0 & ~ bnd_c5_1 bnd_a1345) &
% 7.21/6.77 ~ bnd_c1_1 bnd_a1345) &
% 7.21/6.77 bnd_c3_1 bnd_a1345) |
% 7.21/6.77 bnd_c3_0)) &
% 7.21/6.77 ((bnd_c1_0 | ~ bnd_c2_0) | bnd_c5_0)) &
% 7.21/6.77 ((bnd_c2_0 |
% 7.21/6.77 ((bnd_ndr1_0 & bnd_c3_1 bnd_a1346) & ~ bnd_c4_1 bnd_a1346) &
% 7.21/6.77 bnd_c2_1 bnd_a1346) |
% 7.21/6.77 (ALL X12.
% 7.21/6.77 bnd_ndr1_0 -->
% 7.21/6.77 (~ bnd_c5_1 X12 | bnd_c4_1 X12) |
% 7.21/6.77 (ALL X13.
% 7.21/6.77 bnd_ndr1_1 X12 -->
% 7.21/6.77 bnd_c4_2 X12 X13 | ~ bnd_c3_2 X12 X13)))) &
% 7.21/6.77 (((ALL X14.
% 7.21/6.77 bnd_ndr1_0 -->
% 7.21/6.77 ((ALL X15.
% 7.21/6.77 bnd_ndr1_1 X14 -->
% 7.21/6.77 (~ bnd_c4_2 X14 X15 | bnd_c2_2 X14 X15) |
% 7.21/6.77 ~ bnd_c5_2 X14 X15) |
% 7.21/6.77 ((bnd_ndr1_1 X14 & ~ bnd_c5_2 X14 bnd_a1347) &
% 7.21/6.77 bnd_c4_2 X14 bnd_a1347) &
% 7.21/6.77 bnd_c1_2 X14 bnd_a1347) |
% 7.21/6.77 bnd_c1_1 X14) |
% 7.21/6.77 (ALL X16.
% 7.21/6.77 bnd_ndr1_0 -->
% 7.21/6.77 (~ bnd_c5_1 X16 | bnd_c3_1 X16) | ~ bnd_c4_1 X16)) |
% 7.21/6.77 bnd_c5_0)) &
% 7.21/6.77 (((((((bnd_ndr1_0 & ~ bnd_c4_1 bnd_a1348) &
% 7.21/6.77 (ALL X17.
% 7.21/6.77 bnd_ndr1_1 bnd_a1348 -->
% 7.21/6.77 (bnd_c1_2 bnd_a1348 X17 | ~ bnd_c4_2 bnd_a1348 X17) |
% 7.21/6.77 ~ bnd_c5_2 bnd_a1348 X17)) &
% 7.21/6.77 bnd_ndr1_1 bnd_a1348) &
% 7.21/6.77 ~ bnd_c4_2 bnd_a1348 bnd_a1349) &
% 7.21/6.77 ~ bnd_c3_2 bnd_a1348 bnd_a1349) &
% 7.21/6.77 ~ bnd_c1_2 bnd_a1348 bnd_a1349 |
% 7.21/6.77 (ALL X18. bnd_ndr1_0 --> bnd_c2_1 X18 | ~ bnd_c3_1 X18)) |
% 7.21/6.77 ~ bnd_c4_0)) &
% 7.21/6.77 (bnd_c3_0 | bnd_c2_0)) &
% 7.21/6.77 (bnd_c2_0 |
% 7.21/6.77 (bnd_ndr1_0 & bnd_c5_1 bnd_a1350) & ~ bnd_c2_1 bnd_a1350)) &
% 7.21/6.77 (((bnd_ndr1_0 & ~ bnd_c1_1 bnd_a1351) & ~ bnd_c5_1 bnd_a1351 |
% 7.21/6.77 (ALL X19.
% 7.21/6.77 bnd_ndr1_0 -->
% 7.21/6.77 (~ bnd_c3_1 X19 | bnd_c5_1 X19) | ~ bnd_c4_1 X19)) |
% 7.21/6.77 bnd_c3_0)) &
% 7.21/6.77 ((~ bnd_c2_0 |
% 7.21/6.77 (((((bnd_ndr1_0 & ~ bnd_c4_1 bnd_a1352) &
% 7.21/6.77 (ALL X20.
% 7.21/6.77 bnd_ndr1_1 bnd_a1352 -->
% 7.21/6.77 (~ bnd_c5_2 bnd_a1352 X20 | bnd_c4_2 bnd_a1352 X20) |
% 7.21/6.77 bnd_c1_2 bnd_a1352 X20)) &
% 7.21/6.77 bnd_ndr1_1 bnd_a1352) &
% 7.21/6.77 ~ bnd_c4_2 bnd_a1352 bnd_a1353) &
% 7.21/6.77 bnd_c5_2 bnd_a1352 bnd_a1353) &
% 7.21/6.77 ~ bnd_c3_2 bnd_a1352 bnd_a1353) |
% 7.21/6.77 (ALL X21.
% 7.21/6.77 bnd_ndr1_0 -->
% 7.21/6.77 (~ bnd_c2_1 X21 |
% 7.21/6.77 ((bnd_ndr1_1 X21 & ~ bnd_c3_2 X21 bnd_a1354) &
% 7.21/6.77 bnd_c1_2 X21 bnd_a1354) &
% 7.21/6.77 ~ bnd_c5_2 X21 bnd_a1354) |
% 7.21/6.77 ~ bnd_c5_1 X21))) &
% 7.21/6.77 ((~ bnd_c4_0 |
% 7.21/6.77 (ALL X22.
% 7.21/6.77 bnd_ndr1_0 -->
% 7.21/6.77 (~ bnd_c1_1 X22 | ~ bnd_c5_1 X22) | ~ bnd_c4_1 X22)) |
% 7.21/6.77 (ALL X23.
% 7.21/6.77 bnd_ndr1_0 -->
% 7.21/6.77 ((ALL X24. bnd_ndr1_1 X23 --> bnd_c2_2 X23 X24) |
% 7.21/6.77 ((bnd_ndr1_1 X23 & bnd_c2_2 X23 bnd_a1355) &
% 7.21/6.77 bnd_c5_2 X23 bnd_a1355) &
% 7.21/6.77 ~ bnd_c1_2 X23 bnd_a1355) |
% 7.21/6.77 ~ bnd_c5_1 X23))) &
% 7.21/6.77 ((~ bnd_c3_0 | ~ bnd_c2_0) | bnd_c4_0)) &
% 7.21/6.77 ((~ bnd_c5_0 |
% 7.21/6.77 (ALL X25.
% 7.21/6.77 bnd_ndr1_0 -->
% 7.21/6.77 (~ bnd_c4_1 X25 |
% 7.21/6.77 (ALL X26.
% 7.21/6.77 bnd_ndr1_1 X25 --> bnd_c3_2 X25 X26 | bnd_c4_2 X25 X26)) |
% 7.21/6.77 ((bnd_ndr1_1 X25 & bnd_c5_2 X25 bnd_a1356) &
% 7.21/6.77 bnd_c4_2 X25 bnd_a1356) &
% 7.21/6.77 bnd_c2_2 X25 bnd_a1356)) |
% 7.21/6.77 bnd_c2_0)) &
% 7.21/6.77 (~ bnd_c5_0 | bnd_c3_0)) &
% 7.21/6.77 (((ALL X27.
% 7.21/6.77 bnd_ndr1_0 -->
% 7.21/6.77 (((bnd_ndr1_1 X27 & ~ bnd_c4_2 X27 bnd_a1357) &
% 7.21/6.77 bnd_c5_2 X27 bnd_a1357) &
% 7.21/6.77 bnd_c1_2 X27 bnd_a1357 |
% 7.21/6.77 ((bnd_ndr1_1 X27 & bnd_c3_2 X27 bnd_a1358) &
% 7.21/6.77 bnd_c2_2 X27 bnd_a1358) &
% 7.21/6.77 bnd_c1_2 X27 bnd_a1358) |
% 7.21/6.77 bnd_c1_1 X27) |
% 7.21/6.77 bnd_c4_0) |
% 7.21/6.77 (ALL X28.
% 7.21/6.77 bnd_ndr1_0 -->
% 7.21/6.77 (ALL X29.
% 7.21/6.77 bnd_ndr1_1 X28 --> ~ bnd_c3_2 X28 X29 | ~ bnd_c4_2 X28 X29) |
% 7.21/6.77 ~ bnd_c4_1 X28))) &
% 7.21/6.77 ((~ bnd_c4_0 | bnd_c5_0) | bnd_c1_0)) &
% 7.21/6.77 ((((((bnd_ndr1_0 &
% 7.21/6.77 bnd_c2_1 bnd_a1359) &
% 7.21/6.77 (ALL X30.
% 7.21/6.77 bnd_ndr1_1 bnd_a1359 -->
% 7.21/6.77 (~ bnd_c3_2 bnd_a1359 X30 | bnd_c1_2 bnd_a1359 X30) |
% 7.21/6.77 bnd_c5_2 bnd_a1359 X30)) &
% 7.21/6.77 bnd_ndr1_1 bnd_a1359) &
% 7.21/6.77 ~ bnd_c2_2 bnd_a1359 bnd_a1360) &
% 7.21/6.77 ~ bnd_c1_2 bnd_a1359 bnd_a1360) &
% 7.21/6.77 ~ bnd_c3_2 bnd_a1359 bnd_a1360 |
% 7.21/6.77 (bnd_ndr1_0 & ~ bnd_c1_1 bnd_a1361) & ~ bnd_c5_1 bnd_a1361)) &
% 7.21/6.77 ((~ bnd_c3_0 | bnd_c5_0) |
% 7.21/6.77 ~ bnd_c4_0)) &
% 7.21/6.77 (~ bnd_c2_0 |
% 7.21/6.77 (ALL X31.
% 7.21/6.77 bnd_ndr1_0 -->
% 7.21/6.77 ((ALL X32.
% 7.21/6.77 bnd_ndr1_1 X31 -->
% 7.21/6.77 (~ bnd_c5_2 X31 X32 | bnd_c2_2 X31 X32) | ~ bnd_c4_2 X31 X32) |
% 7.21/6.77 ((bnd_ndr1_1 X31 & bnd_c3_2 X31 bnd_a1362) & bnd_c2_2 X31 bnd_a1362) &
% 7.21/6.77 bnd_c5_2 X31 bnd_a1362) |
% 7.21/6.77 bnd_c1_1 X31))) &
% 7.21/6.77 ((bnd_c1_0 |
% 7.21/6.77 (((((bnd_ndr1_0 &
% 7.21/6.77 (ALL X33.
% 7.21/6.77 bnd_ndr1_1 bnd_a1363 -->
% 7.21/6.77 ~ bnd_c3_2 bnd_a1363 X33 | bnd_c2_2 bnd_a1363 X33)) &
% 7.21/6.77 bnd_ndr1_1 bnd_a1363) &
% 7.21/6.77 ~ bnd_c2_2 bnd_a1363 bnd_a1364) &
% 7.21/6.77 bnd_c5_2 bnd_a1363 bnd_a1364) &
% 7.21/6.77 bnd_c1_2 bnd_a1363 bnd_a1364) &
% 7.21/6.77 ~ bnd_c2_1 bnd_a1363) |
% 7.21/6.77 ~ bnd_c3_0)) &
% 7.21/6.77 ((~ bnd_c4_0 |
% 7.21/6.77 ((bnd_ndr1_0 &
% 7.21/6.77 (ALL X34.
% 7.21/6.77 bnd_ndr1_1 bnd_a1365 -->
% 7.21/6.77 (~ bnd_c5_2 bnd_a1365 X34 | bnd_c2_2 bnd_a1365 X34) |
% 7.21/6.77 bnd_c1_2 bnd_a1365 X34)) &
% 7.21/6.77 (ALL X35.
% 7.21/6.77 bnd_ndr1_1 bnd_a1365 -->
% 7.21/6.77 (bnd_c1_2 bnd_a1365 X35 | ~ bnd_c4_2 bnd_a1365 X35) |
% 7.21/6.77 bnd_c3_2 bnd_a1365 X35)) &
% 7.21/6.77 bnd_c3_1 bnd_a1365) |
% 7.21/6.77 (bnd_ndr1_0 & ~ bnd_c3_1 bnd_a1366) &
% 7.21/6.77 ~ bnd_c1_1 bnd_a1366)) &
% 7.21/6.77 ((((bnd_ndr1_0 & bnd_c4_1 bnd_a1367) &
% 7.21/6.77 (ALL X36.
% 7.21/6.77 bnd_ndr1_1 bnd_a1367 -->
% 7.21/6.77 (bnd_c3_2 bnd_a1367 X36 | ~ bnd_c1_2 bnd_a1367 X36) |
% 7.21/6.77 ~ bnd_c4_2 bnd_a1367 X36)) &
% 7.21/6.77 (ALL X37.
% 7.21/6.77 bnd_ndr1_1 bnd_a1367 -->
% 7.21/6.77 ~ bnd_c3_2 bnd_a1367 X37 | bnd_c5_2 bnd_a1367 X37) |
% 7.21/6.77 ~ bnd_c5_0) |
% 7.21/6.77 ~ bnd_c4_0)) &
% 7.21/6.77 ((~ bnd_c3_0 | ~ bnd_c2_0) | bnd_c1_0)) &
% 7.21/6.77 (bnd_c3_0 |
% 7.21/6.77 (((((bnd_ndr1_0 & bnd_c2_1 bnd_a1368) &
% 7.21/6.77 ~ bnd_c1_1 bnd_a1368) &
% 7.21/6.77 bnd_ndr1_1 bnd_a1368) &
% 7.21/6.77 ~ bnd_c4_2 bnd_a1368 bnd_a1369) &
% 7.21/6.77 ~ bnd_c3_2 bnd_a1368 bnd_a1369) &
% 7.21/6.77 bnd_c1_2 bnd_a1368 bnd_a1369)) &
% 7.21/6.77 (((ALL X38.
% 7.21/6.77 bnd_ndr1_0 -->
% 7.21/6.77 bnd_c4_1 X38 |
% 7.21/6.77 (ALL X39.
% 7.21/6.77 bnd_ndr1_1 X38 -->
% 7.21/6.77 (~ bnd_c4_2 X38 X39 | bnd_c2_2 X38 X39) | ~ bnd_c5_2 X38 X39)) |
% 7.21/6.77 bnd_c2_0) |
% 7.21/6.77 bnd_c1_0)) &
% 7.21/6.77 ((((bnd_ndr1_0 &
% 7.21/6.77 (ALL X40.
% 7.21/6.77 bnd_ndr1_1 bnd_a1370 -->
% 7.21/6.77 (~ bnd_c2_2 bnd_a1370 X40 |
% 7.21/6.77 ~ bnd_c3_2 bnd_a1370 X40) |
% 7.21/6.77 ~ bnd_c5_2 bnd_a1370 X40)) &
% 7.21/6.77 ~ bnd_c2_1 bnd_a1370) &
% 7.21/6.77 bnd_c4_1 bnd_a1370 |
% 7.21/6.77 (ALL X41.
% 7.21/6.77 bnd_ndr1_0 -->
% 7.21/6.77 (((bnd_ndr1_1 X41 &
% 7.21/6.77 ~ bnd_c1_2 X41 bnd_a1371) &
% 7.21/6.77 ~ bnd_c2_2 X41 bnd_a1371) &
% 7.21/6.77 bnd_c3_2 X41 bnd_a1371 |
% 7.21/6.77 bnd_c3_1 X41) |
% 7.21/6.77 ((bnd_ndr1_1 X41 &
% 7.21/6.77 bnd_c1_2 X41 bnd_a1372) &
% 7.21/6.77 ~ bnd_c2_2 X41 bnd_a1372) &
% 7.21/6.77 bnd_c5_2 X41 bnd_a1372)) |
% 7.21/6.77 ~ bnd_c5_0)) &
% 7.21/6.77 (((ALL X42.
% 7.21/6.77 bnd_ndr1_0 -->
% 7.21/6.77 ((ALL X43.
% 7.21/6.77 bnd_ndr1_1 X42 --> bnd_c5_2 X42 X43 | bnd_c4_2 X42 X43) |
% 7.21/6.77 (ALL X44.
% 7.21/6.77 bnd_ndr1_1 X42 -->
% 7.21/6.77 (bnd_c1_2 X42 X44 | bnd_c5_2 X42 X44) | ~ bnd_c3_2 X42 X44)) |
% 7.21/6.77 bnd_c4_1 X42) |
% 7.21/6.77 (ALL X45.
% 7.21/6.77 bnd_ndr1_0 -->
% 7.21/6.77 bnd_c5_1 X45 |
% 7.21/6.77 (ALL X46.
% 7.21/6.77 bnd_ndr1_1 X45 -->
% 7.21/6.77 (bnd_c2_2 X45 X46 |
% 7.21/6.77 ~ bnd_c1_2 X45 X46) |
% 7.21/6.77 bnd_c5_2 X45 X46))) |
% 7.21/6.77 bnd_c3_0)) &
% 7.21/6.77 ((bnd_c5_0 | bnd_c1_0) |
% 7.21/6.77 (ALL X47.
% 7.21/6.77 bnd_ndr1_0 -->
% 7.21/6.77 (((bnd_ndr1_1 X47 &
% 7.21/6.77 ~ bnd_c1_2 X47 bnd_a1373) &
% 7.21/6.77 bnd_c3_2 X47 bnd_a1373) &
% 7.21/6.77 bnd_c2_2 X47 bnd_a1373 |
% 7.21/6.77 ((bnd_ndr1_1 X47 &
% 7.21/6.77 ~ bnd_c1_2 X47 bnd_a1374) &
% 7.21/6.77 bnd_c4_2 X47 bnd_a1374) &
% 7.21/6.77 ~ bnd_c5_2 X47 bnd_a1374) |
% 7.21/6.77 bnd_c1_1 X47))) &
% 7.21/6.77 (((ALL X48.
% 7.21/6.77 bnd_ndr1_0 -->
% 7.21/6.77 (((bnd_ndr1_1 X48 & bnd_c3_2 X48 bnd_a1375) &
% 7.21/6.77 ~ bnd_c2_2 X48 bnd_a1375) &
% 7.21/6.77 bnd_c1_2 X48 bnd_a1375 |
% 7.21/6.77 (bnd_ndr1_1 X48 & bnd_c5_2 X48 bnd_a1376) &
% 7.21/6.77 ~ bnd_c2_2 X48 bnd_a1376) |
% 7.21/6.77 ((bnd_ndr1_1 X48 &
% 7.21/6.77 ~ bnd_c3_2 X48 bnd_a1377) &
% 7.21/6.77 bnd_c5_2 X48 bnd_a1377) &
% 7.21/6.77 ~ bnd_c2_2 X48 bnd_a1377) |
% 7.21/6.77 bnd_c2_0) |
% 7.21/6.77 (bnd_ndr1_0 &
% 7.21/6.77 (ALL X49.
% 7.21/6.77 bnd_ndr1_1 bnd_a1378 -->
% 7.21/6.77 bnd_c1_2 bnd_a1378 X49 |
% 7.21/6.77 bnd_c5_2 bnd_a1378 X49)) &
% 7.21/6.77 ~ bnd_c3_1 bnd_a1378)) &
% 7.21/6.77 (((ALL X50.
% 7.21/6.77 bnd_ndr1_0 -->
% 7.21/6.77 (~ bnd_c2_1 X50 | bnd_c5_1 X50) |
% 7.21/6.77 bnd_c3_1 X50) |
% 7.21/6.77 (ALL X51.
% 7.21/6.77 bnd_ndr1_0 -->
% 7.21/6.77 (((bnd_ndr1_1 X51 &
% 7.21/6.77 ~ bnd_c1_2 X51 bnd_a1379) &
% 7.21/6.77 ~ bnd_c5_2 X51 bnd_a1379) &
% 7.21/6.77 bnd_c2_2 X51 bnd_a1379 |
% 7.21/6.77 (ALL X52.
% 7.21/6.77 bnd_ndr1_1 X51 -->
% 7.21/6.77 (bnd_c4_2 X51 X52 | bnd_c5_2 X51 X52) |
% 7.21/6.77 bnd_c3_2 X51 X52)) |
% 7.21/6.77 bnd_c2_1 X51)) |
% 7.21/6.77 bnd_c4_0)) &
% 7.21/6.77 (~ bnd_c5_0 |
% 7.21/6.77 (bnd_ndr1_0 & ~ bnd_c3_1 bnd_a1380) &
% 7.21/6.77 (ALL X53.
% 7.21/6.77 bnd_ndr1_1 bnd_a1380 -->
% 7.21/6.77 (bnd_c1_2 bnd_a1380 X53 |
% 7.21/6.77 ~ bnd_c3_2 bnd_a1380 X53) |
% 7.21/6.77 ~ bnd_c5_2 bnd_a1380 X53))) &
% 7.21/6.77 (((ALL X54.
% 7.21/6.77 bnd_ndr1_0 -->
% 7.21/6.77 (((bnd_ndr1_1 X54 & bnd_c4_2 X54 bnd_a1381) &
% 7.21/6.77 bnd_c1_2 X54 bnd_a1381) &
% 7.21/6.77 bnd_c3_2 X54 bnd_a1381 |
% 7.21/6.77 ((bnd_ndr1_1 X54 & bnd_c2_2 X54 bnd_a1382) &
% 7.21/6.77 ~ bnd_c3_2 X54 bnd_a1382) &
% 7.21/6.77 ~ bnd_c4_2 X54 bnd_a1382) |
% 7.21/6.77 bnd_c2_1 X54) |
% 7.21/6.77 ~ bnd_c3_0) |
% 7.21/6.77 ~ bnd_c5_0)) &
% 7.21/6.77 ((bnd_c2_0 |
% 7.21/6.77 (ALL X55.
% 7.21/6.77 bnd_ndr1_0 -->
% 7.21/6.77 (bnd_ndr1_1 X55 & bnd_c5_2 X55 bnd_a1383) &
% 7.21/6.77 bnd_c1_2 X55 bnd_a1383 |
% 7.21/6.77 ~ bnd_c5_1 X55)) |
% 7.21/6.77 bnd_c3_0)) &
% 7.21/6.77 (~ bnd_c2_0 | ~ bnd_c3_0)) &
% 7.21/6.77 ((ALL X56.
% 7.21/6.77 bnd_ndr1_0 -->
% 7.21/6.77 (bnd_ndr1_1 X56 & bnd_c5_2 X56 bnd_a1384) &
% 7.21/6.77 bnd_c3_2 X56 bnd_a1384 |
% 7.21/6.77 bnd_c1_1 X56) |
% 7.21/6.77 ~ bnd_c2_0)) &
% 7.21/6.77 ((ALL X57.
% 7.21/6.77 bnd_ndr1_0 -->
% 7.21/6.77 (~ bnd_c5_1 X57 | ~ bnd_c2_1 X57) |
% 7.21/6.77 (ALL X58.
% 7.21/6.77 bnd_ndr1_1 X57 -->
% 7.21/6.77 (bnd_c2_2 X57 X58 | bnd_c3_2 X57 X58) |
% 7.21/6.77 bnd_c5_2 X57 X58)) |
% 7.21/6.77 ((((bnd_ndr1_0 & bnd_c4_1 bnd_a1385) &
% 7.21/6.77 ~ bnd_c2_1 bnd_a1385) &
% 7.21/6.77 bnd_ndr1_1 bnd_a1385) &
% 7.21/6.77 ~ bnd_c2_2 bnd_a1385 bnd_a1386) &
% 7.21/6.77 bnd_c5_2 bnd_a1385 bnd_a1386)) &
% 7.21/6.77 ((bnd_c3_0 | ~ bnd_c4_0) |
% 7.21/6.77 (ALL X59.
% 7.21/6.77 bnd_ndr1_0 -->
% 7.21/6.77 (((bnd_ndr1_1 X59 & ~ bnd_c5_2 X59 bnd_a1387) &
% 7.21/6.77 bnd_c1_2 X59 bnd_a1387) &
% 7.21/6.77 bnd_c2_2 X59 bnd_a1387 |
% 7.21/6.77 (ALL X60.
% 7.21/6.77 bnd_ndr1_1 X59 -->
% 7.21/6.77 ~ bnd_c5_2 X59 X60 | bnd_c3_2 X59 X60)) |
% 7.21/6.77 (ALL X61.
% 7.21/6.77 bnd_ndr1_1 X59 -->
% 7.21/6.77 bnd_c4_2 X59 X61 | bnd_c1_2 X59 X61)))) &
% 7.21/6.77 (((bnd_ndr1_0 &
% 7.21/6.77 (ALL X62.
% 7.21/6.77 bnd_ndr1_1 bnd_a1388 -->
% 7.21/6.77 ~ bnd_c2_2 bnd_a1388 X62 |
% 7.21/6.77 ~ bnd_c4_2 bnd_a1388 X62)) &
% 7.21/6.77 ~ bnd_c1_1 bnd_a1388 |
% 7.21/6.77 ~ bnd_c4_0) |
% 7.21/6.77 ((bnd_ndr1_0 & ~ bnd_c5_1 bnd_a1389) &
% 7.21/6.77 ~ bnd_c2_1 bnd_a1389) &
% 7.21/6.77 ~ bnd_c4_1 bnd_a1389)) &
% 7.21/6.77 ((bnd_c5_0 |
% 7.21/6.77 ((((bnd_ndr1_0 & bnd_c2_1 bnd_a1390) &
% 7.21/6.77 bnd_ndr1_1 bnd_a1390) &
% 7.21/6.77 ~ bnd_c4_2 bnd_a1390 bnd_a1391) &
% 7.21/6.77 bnd_c5_2 bnd_a1390 bnd_a1391) &
% 7.21/6.77 ~ bnd_c3_1 bnd_a1390) |
% 7.21/6.77 ~ bnd_c1_0)) &
% 7.21/6.77 ((((((((((bnd_ndr1_0 & ~ bnd_c3_1 bnd_a1392) &
% 7.21/6.77 bnd_ndr1_1 bnd_a1392) &
% 7.21/6.77 ~ bnd_c4_2 bnd_a1392 bnd_a1393) &
% 7.21/6.77 ~ bnd_c1_2 bnd_a1392 bnd_a1393) &
% 7.21/6.77 bnd_c3_2 bnd_a1392 bnd_a1393) &
% 7.21/6.77 bnd_ndr1_1 bnd_a1392) &
% 7.21/6.77 bnd_c5_2 bnd_a1392 bnd_a1394) &
% 7.21/6.77 ~ bnd_c2_2 bnd_a1392 bnd_a1394) &
% 7.21/6.77 bnd_c4_2 bnd_a1392 bnd_a1394 |
% 7.21/6.77 (ALL X63.
% 7.21/6.77 bnd_ndr1_0 -->
% 7.21/6.77 ((ALL X64.
% 7.21/6.77 bnd_ndr1_1 X63 -->
% 7.21/6.77 (~ bnd_c5_2 X63 X64 | ~ bnd_c2_2 X63 X64) |
% 7.21/6.77 bnd_c3_2 X63 X64) |
% 7.21/6.77 ~ bnd_c5_1 X63) |
% 7.21/6.77 ~ bnd_c1_1 X63)) |
% 7.21/6.77 bnd_c5_0)) &
% 7.21/6.77 (((ALL X65. bnd_ndr1_0 --> ~ bnd_c1_1 X65) |
% 7.21/6.77 (ALL X66.
% 7.21/6.77 bnd_ndr1_0 -->
% 7.21/6.77 ((ALL X67.
% 7.21/6.77 bnd_ndr1_1 X66 -->
% 7.21/6.77 (~ bnd_c2_2 X66 X67 | bnd_c3_2 X66 X67) |
% 7.21/6.77 bnd_c1_2 X66 X67) |
% 7.21/6.77 (ALL X68.
% 7.21/6.77 bnd_ndr1_1 X66 -->
% 7.21/6.77 bnd_c1_2 X66 X68 | bnd_c4_2 X66 X68)) |
% 7.21/6.77 ~ bnd_c2_1 X66)) |
% 7.21/6.77 (ALL X69.
% 7.21/6.77 bnd_ndr1_0 -->
% 7.21/6.77 ((bnd_ndr1_1 X69 & bnd_c3_2 X69 bnd_a1395) &
% 7.21/6.77 bnd_c2_2 X69 bnd_a1395 |
% 7.21/6.77 (ALL X70.
% 7.21/6.77 bnd_ndr1_1 X69 -->
% 7.21/6.77 bnd_c3_2 X69 X70 | bnd_c5_2 X69 X70)) |
% 7.21/6.77 ~ bnd_c3_1 X69))) &
% 7.21/6.77 (((ALL X71.
% 7.21/6.77 bnd_ndr1_0 -->
% 7.21/6.77 (((bnd_ndr1_1 X71 & bnd_c1_2 X71 bnd_a1396) &
% 7.21/6.77 ~ bnd_c2_2 X71 bnd_a1396) &
% 7.21/6.77 ~ bnd_c5_2 X71 bnd_a1396 |
% 7.21/6.77 ~ bnd_c1_1 X71) |
% 7.21/6.77 (ALL X72.
% 7.21/6.77 bnd_ndr1_1 X71 -->
% 7.21/6.77 ~ bnd_c4_2 X71 X72 | ~ bnd_c3_2 X71 X72)) |
% 7.21/6.77 (ALL X73.
% 7.21/6.77 bnd_ndr1_0 -->
% 7.21/6.77 (bnd_c1_1 X73 | bnd_c2_1 X73) | bnd_c5_1 X73)) |
% 7.21/6.77 (ALL X74.
% 7.21/6.77 bnd_ndr1_0 -->
% 7.21/6.77 (~ bnd_c5_1 X74 |
% 7.21/6.77 (ALL X75.
% 7.21/6.77 bnd_ndr1_1 X74 -->
% 7.21/6.77 (~ bnd_c4_2 X74 X75 | ~ bnd_c2_2 X74 X75) |
% 7.21/6.77 ~ bnd_c1_2 X74 X75)) |
% 7.21/6.77 (ALL X76.
% 7.21/6.77 bnd_ndr1_1 X74 -->
% 7.21/6.77 ~ bnd_c5_2 X74 X76 | ~ bnd_c3_2 X74 X76)))) &
% 7.21/6.77 ((bnd_c5_0 | ~ bnd_c2_0) | ~ bnd_c3_0)) &
% 7.21/6.77 (((ALL X77.
% 7.21/6.77 bnd_ndr1_0 -->
% 7.21/6.77 ((ALL X78.
% 7.21/6.77 bnd_ndr1_1 X77 -->
% 7.21/6.77 (bnd_c5_2 X77 X78 | ~ bnd_c2_2 X77 X78) |
% 7.21/6.77 bnd_c4_2 X77 X78) |
% 7.21/6.77 ~ bnd_c2_1 X77) |
% 7.21/6.77 ((bnd_ndr1_1 X77 & bnd_c2_2 X77 bnd_a1397) &
% 7.21/6.77 ~ bnd_c3_2 X77 bnd_a1397) &
% 7.21/6.77 ~ bnd_c1_2 X77 bnd_a1397) |
% 7.21/6.77 ~ bnd_c4_0) |
% 7.21/6.77 (ALL X79.
% 7.21/6.77 bnd_ndr1_0 -->
% 7.21/6.77 bnd_c1_1 X79 |
% 7.21/6.77 ((bnd_ndr1_1 X79 & ~ bnd_c1_2 X79 bnd_a1398) &
% 7.21/6.77 ~ bnd_c4_2 X79 bnd_a1398) &
% 7.21/6.77 ~ bnd_c5_2 X79 bnd_a1398))) &
% 7.21/6.77 (((ALL X80.
% 7.21/6.77 bnd_ndr1_0 -->
% 7.21/6.77 (~ bnd_c2_1 X80 | ~ bnd_c3_1 X80) |
% 7.21/6.77 (bnd_ndr1_1 X80 & bnd_c1_2 X80 bnd_a1399) &
% 7.21/6.77 ~ bnd_c5_2 X80 bnd_a1399) |
% 7.21/6.77 (((((bnd_ndr1_0 & bnd_c4_1 bnd_a1400) & bnd_c2_1 bnd_a1400) &
% 7.21/6.77 bnd_ndr1_1 bnd_a1400) &
% 7.21/6.77 ~ bnd_c1_2 bnd_a1400 bnd_a1401) &
% 7.21/6.77 bnd_c2_2 bnd_a1400 bnd_a1401) &
% 7.21/6.77 ~ bnd_c3_2 bnd_a1400 bnd_a1401) |
% 7.21/6.77 ~ bnd_c4_0)) &
% 7.21/6.77 ((~ bnd_c5_0 |
% 7.21/6.77 ((((((((bnd_ndr1_0 & bnd_c3_1 bnd_a1402) & bnd_ndr1_1 bnd_a1402) &
% 7.21/6.77 ~ bnd_c4_2 bnd_a1402 bnd_a1403) &
% 7.21/6.77 ~ bnd_c3_2 bnd_a1402 bnd_a1403) &
% 7.21/6.77 ~ bnd_c2_2 bnd_a1402 bnd_a1403) &
% 7.21/6.77 bnd_ndr1_1 bnd_a1402) &
% 7.21/6.77 bnd_c3_2 bnd_a1402 bnd_a1404) &
% 7.21/6.77 ~ bnd_c1_2 bnd_a1402 bnd_a1404) &
% 7.21/6.77 ~ bnd_c2_2 bnd_a1402 bnd_a1404) |
% 7.21/6.77 (ALL X81.
% 7.21/6.77 bnd_ndr1_0 -->
% 7.21/6.77 (~ bnd_c3_1 X81 |
% 7.21/6.77 (bnd_ndr1_1 X81 & ~ bnd_c4_2 X81 bnd_a1405) &
% 7.21/6.77 ~ bnd_c5_2 X81 bnd_a1405) |
% 7.21/6.77 bnd_c1_1 X81))) &
% 7.21/6.77 ((~ bnd_c4_0 |
% 7.21/6.77 ((((((((bnd_ndr1_0 & ~ bnd_c5_1 bnd_a1406) &
% 7.21/6.77 bnd_ndr1_1 bnd_a1406) &
% 7.21/6.77 bnd_c5_2 bnd_a1406 bnd_a1407) &
% 7.21/6.77 ~ bnd_c1_2 bnd_a1406 bnd_a1407) &
% 7.21/6.77 ~ bnd_c2_2 bnd_a1406 bnd_a1407) &
% 7.21/6.77 bnd_ndr1_1 bnd_a1406) &
% 7.21/6.77 ~ bnd_c2_2 bnd_a1406 bnd_a1408) &
% 7.21/6.77 ~ bnd_c1_2 bnd_a1406 bnd_a1408) &
% 7.21/6.77 bnd_c5_2 bnd_a1406 bnd_a1408) |
% 7.21/6.77 bnd_c2_0)) &
% 7.21/6.77 (bnd_c1_0 |
% 7.21/6.77 ((bnd_ndr1_0 & ~ bnd_c3_1 bnd_a1409) &
% 7.21/6.77 (ALL X82.
% 7.21/6.77 bnd_ndr1_1 bnd_a1409 -->
% 7.21/6.77 (~ bnd_c4_2 bnd_a1409 X82 | bnd_c1_2 bnd_a1409 X82) |
% 7.21/6.77 bnd_c2_2 bnd_a1409 X82)) &
% 7.21/6.77 (ALL X83.
% 7.21/6.77 bnd_ndr1_1 bnd_a1409 -->
% 7.21/6.77 (~ bnd_c5_2 bnd_a1409 X83 | ~ bnd_c1_2 bnd_a1409 X83) |
% 7.21/6.77 ~ bnd_c4_2 bnd_a1409 X83))) &
% 7.21/6.77 (bnd_c4_0 |
% 7.21/6.77 (ALL X84.
% 7.21/6.77 bnd_ndr1_0 -->
% 7.21/6.77 (~ bnd_c4_1 X84 | bnd_c2_1 X84) |
% 7.21/6.77 (bnd_ndr1_1 X84 & bnd_c5_2 X84 bnd_a1410) &
% 7.21/6.77 ~ bnd_c1_2 X84 bnd_a1410))) &
% 7.21/6.77 ((bnd_c3_0 |
% 7.21/6.77 (ALL X85.
% 7.21/6.77 bnd_ndr1_0 -->
% 7.21/6.77 ((bnd_ndr1_1 X85 & ~ bnd_c1_2 X85 bnd_a1411) &
% 7.21/6.77 bnd_c2_2 X85 bnd_a1411) &
% 7.21/6.77 ~ bnd_c4_2 X85 bnd_a1411 |
% 7.21/6.77 (ALL X86.
% 7.21/6.77 bnd_ndr1_1 X85 --> bnd_c1_2 X85 X86 | bnd_c3_2 X85 X86))) |
% 7.21/6.77 ((bnd_ndr1_0 & bnd_c4_1 bnd_a1412) &
% 7.21/6.77 (ALL X87.
% 7.21/6.77 bnd_ndr1_1 bnd_a1412 -->
% 7.21/6.77 (bnd_c1_2 bnd_a1412 X87 | bnd_c5_2 bnd_a1412 X87) |
% 7.21/6.77 ~ bnd_c3_2 bnd_a1412 X87)) &
% 7.21/6.77 ~ bnd_c5_1 bnd_a1412)) &
% 7.21/6.77 (((ALL X88.
% 7.21/6.77 bnd_ndr1_0 -->
% 7.21/6.77 (((bnd_ndr1_1 X88 & ~ bnd_c2_2 X88 bnd_a1413) &
% 7.21/6.77 bnd_c5_2 X88 bnd_a1413) &
% 7.21/6.77 bnd_c4_2 X88 bnd_a1413 |
% 7.21/6.77 bnd_c3_1 X88) |
% 7.21/6.77 (ALL X89.
% 7.21/6.77 bnd_ndr1_1 X88 -->
% 7.21/6.77 (~ bnd_c1_2 X88 X89 | bnd_c5_2 X88 X89) |
% 7.21/6.77 ~ bnd_c4_2 X88 X89)) |
% 7.21/6.77 (ALL X90.
% 7.21/6.77 bnd_ndr1_0 -->
% 7.21/6.77 (((bnd_ndr1_1 X90 & bnd_c2_2 X90 bnd_a1414) &
% 7.21/6.77 bnd_c4_2 X90 bnd_a1414) &
% 7.21/6.77 bnd_c5_2 X90 bnd_a1414 |
% 7.21/6.77 bnd_c3_1 X90) |
% 7.21/6.77 bnd_c2_1 X90)) |
% 7.21/6.77 bnd_c2_0)) &
% 7.21/6.77 ((~ bnd_c4_0 |
% 7.21/6.77 (ALL X91.
% 7.21/6.77 bnd_ndr1_0 -->
% 7.21/6.77 ((bnd_ndr1_1 X91 & bnd_c3_2 X91 bnd_a1415) &
% 7.21/6.77 ~ bnd_c4_2 X91 bnd_a1415 |
% 7.21/6.77 ~ bnd_c3_1 X91) |
% 7.21/6.77 ~ bnd_c2_1 X91)) |
% 7.21/6.77 ~ bnd_c5_0)) &
% 7.21/6.77 ((((bnd_ndr1_0 & ~ bnd_c2_1 bnd_a1416) & bnd_c3_1 bnd_a1416) &
% 7.21/6.77 bnd_c4_1 bnd_a1416 |
% 7.21/6.77 bnd_c1_0) |
% 7.21/6.77 ~ bnd_c2_0)) &
% 7.21/6.77 (bnd_c3_0 | ~ bnd_c2_0)) &
% 7.21/6.77 (((ALL X92.
% 7.21/6.77 bnd_ndr1_0 -->
% 7.21/6.77 (bnd_c4_1 X92 | ~ bnd_c2_1 X92) |
% 7.21/6.77 ((bnd_ndr1_1 X92 & ~ bnd_c2_2 X92 bnd_a1417) &
% 7.21/6.77 bnd_c1_2 X92 bnd_a1417) &
% 7.21/6.77 bnd_c3_2 X92 bnd_a1417) |
% 7.21/6.77 ((((bnd_ndr1_0 & bnd_c2_1 bnd_a1418) &
% 7.21/6.77 (ALL X93.
% 7.21/6.77 bnd_ndr1_1 bnd_a1418 -->
% 7.21/6.77 (~ bnd_c5_2 bnd_a1418 X93 | bnd_c1_2 bnd_a1418 X93) |
% 7.21/6.77 bnd_c4_2 bnd_a1418 X93)) &
% 7.21/6.77 bnd_ndr1_1 bnd_a1418) &
% 7.21/6.77 ~ bnd_c5_2 bnd_a1418 bnd_a1419) &
% 7.21/6.77 bnd_c4_2 bnd_a1418 bnd_a1419) |
% 7.21/6.77 ~ bnd_c5_0)) &
% 7.21/6.77 ((bnd_c4_0 | ~ bnd_c1_0) | bnd_c5_0)) &
% 7.21/6.77 ((bnd_c4_0 | ~ bnd_c5_0) |
% 7.21/6.77 ((((((((bnd_ndr1_0 &
% 7.21/6.77 bnd_ndr1_1 bnd_a1420) &
% 7.21/6.77 bnd_c3_2 bnd_a1420 bnd_a1421) &
% 7.21/6.77 ~ bnd_c5_2 bnd_a1420 bnd_a1421) &
% 7.21/6.77 bnd_c1_2 bnd_a1420 bnd_a1421) &
% 7.21/6.77 bnd_ndr1_1 bnd_a1420) &
% 7.21/6.77 ~ bnd_c5_2 bnd_a1420 bnd_a1422) &
% 7.21/6.77 bnd_c4_2 bnd_a1420 bnd_a1422) &
% 7.21/6.77 bnd_c3_2 bnd_a1420 bnd_a1422) &
% 7.21/6.77 (ALL X94.
% 7.21/6.77 bnd_ndr1_1 bnd_a1420 -->
% 7.21/6.77 (bnd_c1_2 bnd_a1420 X94 | ~ bnd_c4_2 bnd_a1420 X94) |
% 7.21/6.77 ~ bnd_c2_2 bnd_a1420 X94))) &
% 7.21/6.77 ((bnd_c5_0 | ~ bnd_c4_0) |
% 7.21/6.77 (bnd_ndr1_0 &
% 7.21/6.77 (ALL X95.
% 7.21/6.77 bnd_ndr1_1 bnd_a1423 -->
% 7.21/6.77 ~ bnd_c2_2 bnd_a1423 X95 | ~ bnd_c3_2 bnd_a1423 X95)) &
% 7.21/6.77 bnd_c1_1 bnd_a1423)) &
% 7.21/6.77 (((bnd_ndr1_0 & ~ bnd_c1_1 bnd_a1424) &
% 7.21/6.77 (ALL X96.
% 7.21/6.77 bnd_ndr1_1 bnd_a1424 -->
% 7.21/6.77 (~ bnd_c4_2 bnd_a1424 X96 | bnd_c1_2 bnd_a1424 X96) |
% 7.21/6.77 bnd_c3_2 bnd_a1424 X96)) &
% 7.21/6.77 bnd_c4_1 bnd_a1424 |
% 7.21/6.77 bnd_c2_0)) &
% 7.21/6.77 (~ bnd_c4_0 |
% 7.21/6.77 (ALL X97.
% 7.21/6.77 bnd_ndr1_0 -->
% 7.21/6.77 bnd_c2_1 X97 | ~ bnd_c3_1 X97))) &
% 7.21/6.77 ((bnd_c1_0 | ~ bnd_c4_0) |
% 7.21/6.77 ((((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a1425) &
% 7.21/6.77 ~ bnd_c3_2 bnd_a1425 bnd_a1426) &
% 7.21/6.77 ~ bnd_c2_2 bnd_a1425 bnd_a1426) &
% 7.21/6.77 ~ bnd_c1_2 bnd_a1425 bnd_a1426) &
% 7.21/6.77 bnd_ndr1_1 bnd_a1425) &
% 7.21/6.77 bnd_c4_2 bnd_a1425 bnd_a1427) &
% 7.21/6.77 ~ bnd_c5_2 bnd_a1425 bnd_a1427) &
% 7.21/6.77 ~ bnd_c1_2 bnd_a1425 bnd_a1427) &
% 7.21/6.77 (ALL X98.
% 7.21/6.77 bnd_ndr1_1 bnd_a1425 -->
% 7.21/6.77 (~ bnd_c3_2 bnd_a1425 X98 |
% 7.21/6.77 bnd_c5_2 bnd_a1425 X98) |
% 7.21/6.77 bnd_c2_2 bnd_a1425 X98))) &
% 7.21/6.77 (((((((bnd_ndr1_0 & bnd_c2_1 bnd_a1428) &
% 7.21/6.77 bnd_ndr1_1 bnd_a1428) &
% 7.21/6.77 bnd_c4_2 bnd_a1428 bnd_a1429) &
% 7.21/6.77 ~ bnd_c3_2 bnd_a1428 bnd_a1429) &
% 7.21/6.77 bnd_c2_2 bnd_a1428 bnd_a1429) &
% 7.21/6.77 (ALL X99.
% 7.21/6.77 bnd_ndr1_1 bnd_a1428 -->
% 7.21/6.77 bnd_c2_2 bnd_a1428 X99 |
% 7.21/6.77 ~ bnd_c1_2 bnd_a1428 X99) |
% 7.21/6.77 ((((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a1430) &
% 7.21/6.77 bnd_c1_2 bnd_a1430 bnd_a1431) &
% 7.21/6.77 bnd_c2_2 bnd_a1430 bnd_a1431) &
% 7.21/6.77 bnd_c5_2 bnd_a1430 bnd_a1431) &
% 7.21/6.77 bnd_c2_1 bnd_a1430) &
% 7.21/6.77 bnd_ndr1_1 bnd_a1430) &
% 7.21/6.77 ~ bnd_c1_2 bnd_a1430 bnd_a1432) &
% 7.21/6.77 ~ bnd_c4_2 bnd_a1430 bnd_a1432) &
% 7.21/6.77 ~ bnd_c2_2 bnd_a1430 bnd_a1432) |
% 7.21/6.77 (ALL X100.
% 7.21/6.77 bnd_ndr1_0 -->
% 7.21/6.77 ((bnd_ndr1_1 X100 &
% 7.21/6.77 ~ bnd_c3_2 X100 bnd_a1433) &
% 7.21/6.77 bnd_c5_2 X100 bnd_a1433) &
% 7.21/6.77 bnd_c2_2 X100 bnd_a1433 |
% 7.21/6.77 bnd_c3_1 X100))) &
% 7.21/6.77 (((bnd_ndr1_0 &
% 7.21/6.77 (ALL X101.
% 7.21/6.77 bnd_ndr1_1 bnd_a1434 -->
% 7.21/6.77 bnd_c4_2 bnd_a1434 X101 |
% 7.21/6.77 bnd_c1_2 bnd_a1434 X101)) &
% 7.21/6.77 bnd_c2_1 bnd_a1434) &
% 7.21/6.77 (ALL X102.
% 7.21/6.77 bnd_ndr1_1 bnd_a1434 -->
% 7.21/6.77 (bnd_c1_2 bnd_a1434 X102 |
% 7.21/6.77 bnd_c3_2 bnd_a1434 X102) |
% 7.21/6.77 bnd_c5_2 bnd_a1434 X102) |
% 7.21/6.77 (ALL X103.
% 7.21/6.77 bnd_ndr1_0 -->
% 7.21/6.77 ((bnd_ndr1_1 X103 &
% 7.21/6.77 ~ bnd_c4_2 X103 bnd_a1435) &
% 7.21/6.77 bnd_c2_2 X103 bnd_a1435 |
% 7.21/6.77 bnd_c2_1 X103) |
% 7.21/6.77 (ALL X104.
% 7.21/6.77 bnd_ndr1_1 X103 -->
% 7.21/6.77 (~ bnd_c4_2 X103 X104 | bnd_c5_2 X103 X104) | bnd_c3_2 X103 X104)))) &
% 7.21/6.77 ((bnd_c3_0 | bnd_c1_0) | ~ bnd_c5_0)) &
% 7.21/6.77 ((bnd_c5_0 | bnd_c4_0) |
% 7.21/6.77 (((((bnd_ndr1_0 &
% 7.21/6.77 (ALL X105.
% 7.21/6.77 bnd_ndr1_1 bnd_a1436 -->
% 7.21/6.77 (~ bnd_c2_2 bnd_a1436 X105 |
% 7.21/6.77 bnd_c1_2 bnd_a1436 X105) |
% 7.21/6.77 bnd_c4_2 bnd_a1436 X105)) &
% 7.21/6.77 bnd_ndr1_1 bnd_a1436) &
% 7.21/6.77 ~ bnd_c4_2 bnd_a1436 bnd_a1437) &
% 7.21/6.77 ~ bnd_c2_2 bnd_a1436 bnd_a1437) &
% 7.21/6.77 bnd_c1_2 bnd_a1436 bnd_a1437) &
% 7.21/6.77 (ALL X106.
% 7.21/6.77 bnd_ndr1_1 bnd_a1436 -->
% 7.21/6.77 (bnd_c3_2 bnd_a1436 X106 |
% 7.21/6.77 ~ bnd_c2_2 bnd_a1436 X106) |
% 7.21/6.77 bnd_c5_2 bnd_a1436 X106))) &
% 7.21/6.77 ((~ bnd_c3_0 |
% 7.21/6.77 (bnd_ndr1_0 &
% 7.21/6.77 (ALL X107.
% 7.21/6.77 bnd_ndr1_1 bnd_a1438 -->
% 7.21/6.77 (bnd_c2_2 bnd_a1438 X107 |
% 7.21/6.77 ~ bnd_c3_2 bnd_a1438 X107) |
% 7.21/6.77 ~ bnd_c5_2 bnd_a1438 X107)) &
% 7.21/6.77 bnd_c1_1 bnd_a1438) |
% 7.21/6.77 (((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a1439) &
% 7.21/6.77 ~ bnd_c4_2 bnd_a1439 bnd_a1440) &
% 7.21/6.77 ~ bnd_c3_2 bnd_a1439 bnd_a1440) &
% 7.21/6.77 bnd_ndr1_1 bnd_a1439) &
% 7.21/6.77 bnd_c1_2 bnd_a1439 bnd_a1441) &
% 7.21/6.77 bnd_c5_2 bnd_a1439 bnd_a1441) &
% 7.21/6.77 bnd_c3_2 bnd_a1439 bnd_a1441) &
% 7.21/6.77 bnd_c3_1 bnd_a1439)) &
% 7.21/6.77 (bnd_c1_0 | bnd_c3_0)) &
% 7.21/6.77 (((bnd_ndr1_0 &
% 7.21/6.77 (ALL X108.
% 7.21/6.77 bnd_ndr1_1 bnd_a1442 -->
% 7.21/6.77 (bnd_c3_2 bnd_a1442 X108 |
% 7.21/6.77 bnd_c4_2 bnd_a1442 X108) |
% 7.21/6.77 ~ bnd_c2_2 bnd_a1442 X108)) &
% 7.21/6.77 bnd_c3_1 bnd_a1442) &
% 7.21/6.77 bnd_c2_1 bnd_a1442 |
% 7.21/6.77 ~ bnd_c3_0)) &
% 7.21/6.77 (((ALL X109.
% 7.21/6.77 bnd_ndr1_0 -->
% 7.21/6.77 ((ALL X110.
% 7.21/6.77 bnd_ndr1_1 X109 -->
% 7.21/6.77 (bnd_c2_2 X109 X110 |
% 7.21/6.77 bnd_c5_2 X109 X110) |
% 7.21/6.77 ~ bnd_c4_2 X109 X110) |
% 7.21/6.77 (ALL X111.
% 7.21/6.77 bnd_ndr1_1 X109 -->
% 7.21/6.77 (~ bnd_c1_2 X109 X111 |
% 7.21/6.77 bnd_c2_2 X109 X111) |
% 7.21/6.77 ~ bnd_c4_2 X109 X111)) |
% 7.21/6.77 ~ bnd_c1_1 X109) |
% 7.21/6.77 bnd_c2_0) |
% 7.21/6.77 ((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a1443) &
% 7.21/6.77 bnd_c3_2 bnd_a1443 bnd_a1444) &
% 7.21/6.77 bnd_c1_2 bnd_a1443 bnd_a1444) &
% 7.21/6.77 ~ bnd_c4_2 bnd_a1443 bnd_a1444) &
% 7.21/6.77 ~ bnd_c3_1 bnd_a1443)) &
% 7.21/6.77 ~ bnd_c5_0) &
% 7.21/6.77 (((bnd_ndr1_0 & ~ bnd_c5_1 bnd_a1445) &
% 7.21/6.77 ~ bnd_c1_1 bnd_a1445 |
% 7.21/6.77 ~ bnd_c3_0) |
% 7.21/6.77 ~ bnd_c4_0)) &
% 7.21/6.77 (((bnd_ndr1_0 & ~ bnd_c5_1 bnd_a1446) &
% 7.21/6.77 ~ bnd_c3_1 bnd_a1446) &
% 7.21/6.77 (ALL X112.
% 7.21/6.77 bnd_ndr1_1 bnd_a1446 -->
% 7.21/6.77 (bnd_c3_2 bnd_a1446 X112 |
% 7.21/6.77 ~ bnd_c1_2 bnd_a1446 X112) |
% 7.21/6.77 ~ bnd_c5_2 bnd_a1446 X112) |
% 7.21/6.77 bnd_c1_0)) &
% 7.21/6.77 ((((((((((bnd_ndr1_0 & bnd_c2_1 bnd_a1447) &
% 7.21/6.77 bnd_ndr1_1 bnd_a1447) &
% 7.21/6.77 bnd_c5_2 bnd_a1447 bnd_a1448) &
% 7.21/6.77 bnd_c3_2 bnd_a1447 bnd_a1448) &
% 7.21/6.77 ~ bnd_c1_2 bnd_a1447 bnd_a1448) &
% 7.21/6.77 bnd_ndr1_1 bnd_a1447) &
% 7.21/6.77 ~ bnd_c5_2 bnd_a1447 bnd_a1449) &
% 7.21/6.77 ~ bnd_c3_2 bnd_a1447 bnd_a1449) &
% 7.21/6.77 ~ bnd_c4_2 bnd_a1447 bnd_a1449 |
% 7.21/6.77 ~ bnd_c4_0) |
% 7.21/6.77 (bnd_ndr1_0 & bnd_ndr1_1 bnd_a1450) &
% 7.21/6.77 ~ bnd_c5_2 bnd_a1450 bnd_a1451)) &
% 7.21/6.77 (((((bnd_ndr1_0 & ~ bnd_c5_1 bnd_a1452) &
% 7.21/6.77 bnd_ndr1_1 bnd_a1452) &
% 7.21/6.77 bnd_c2_2 bnd_a1452 bnd_a1453) &
% 7.21/6.77 ~ bnd_c1_2 bnd_a1452 bnd_a1453 |
% 7.21/6.77 bnd_c2_0) |
% 7.21/6.77 ~ bnd_c3_0)) &
% 7.21/6.77 (((bnd_ndr1_0 & ~ bnd_c5_1 bnd_a1454) &
% 7.21/6.77 bnd_c2_1 bnd_a1454 |
% 7.21/6.77 ((((((((bnd_ndr1_0 & bnd_c1_1 bnd_a1455) &
% 7.21/6.77 bnd_ndr1_1 bnd_a1455) &
% 7.21/6.77 ~ bnd_c3_2 bnd_a1455 bnd_a1456) &
% 7.21/6.77 bnd_c2_2 bnd_a1455 bnd_a1456) &
% 7.21/6.77 ~ bnd_c4_2 bnd_a1455 bnd_a1456) &
% 7.21/6.77 bnd_ndr1_1 bnd_a1455) &
% 7.21/6.77 bnd_c5_2 bnd_a1455 bnd_a1457) &
% 7.21/6.77 bnd_c3_2 bnd_a1455 bnd_a1457) &
% 7.21/6.77 ~ bnd_c2_2 bnd_a1455 bnd_a1457) |
% 7.21/6.77 bnd_c4_0)) &
% 7.21/6.77 bnd_ndr1_0) &
% 7.21/6.77 (ALL X113.
% 7.21/6.77 bnd_ndr1_1 bnd_a1458 -->
% 7.21/6.77 bnd_c1_2 bnd_a1458 X113 | ~ bnd_c4_2 bnd_a1458 X113)) &
% 7.21/6.77 (ALL X114.
% 7.21/6.77 bnd_ndr1_1 bnd_a1458 -->
% 7.21/6.77 bnd_c3_2 bnd_a1458 X114 | bnd_c2_2 bnd_a1458 X114)) &
% 7.21/6.77 bnd_c2_1 bnd_a1458) &
% 7.21/6.77 ((ALL X115.
% 7.21/6.77 bnd_ndr1_0 -->
% 7.21/6.77 (bnd_c1_1 X115 |
% 7.21/6.77 (ALL X116.
% 7.21/6.77 bnd_ndr1_1 X115 -->
% 7.21/6.77 (~ bnd_c2_2 X115 X116 | bnd_c4_2 X115 X116) |
% 7.21/6.77 ~ bnd_c3_2 X115 X116)) |
% 7.21/6.77 ((bnd_ndr1_1 X115 & bnd_c4_2 X115 bnd_a1459) &
% 7.21/6.77 ~ bnd_c3_2 X115 bnd_a1459) &
% 7.21/6.77 ~ bnd_c1_2 X115 bnd_a1459) |
% 7.21/6.77 bnd_c4_0)) &
% 7.21/6.77 ((~ bnd_c4_0 |
% 7.21/6.77 ((((bnd_ndr1_0 & bnd_c5_1 bnd_a1460) & bnd_ndr1_1 bnd_a1460) &
% 7.21/6.77 ~ bnd_c2_2 bnd_a1460 bnd_a1461) &
% 7.21/6.77 bnd_c3_2 bnd_a1460 bnd_a1461) &
% 7.21/6.77 ~ bnd_c4_2 bnd_a1460 bnd_a1461) |
% 7.21/6.77 (ALL X117.
% 7.21/6.77 bnd_ndr1_0 -->
% 7.21/6.77 (bnd_c4_1 X117 |
% 7.21/6.77 (bnd_ndr1_1 X117 & bnd_c4_2 X117 bnd_a1462) &
% 7.21/6.77 ~ bnd_c3_2 X117 bnd_a1462) |
% 7.21/6.77 ((bnd_ndr1_1 X117 & ~ bnd_c2_2 X117 bnd_a1463) &
% 7.21/6.77 bnd_c4_2 X117 bnd_a1463) &
% 7.21/6.77 ~ bnd_c3_2 X117 bnd_a1463))) &
% 7.21/6.77 bnd_ndr1_0) &
% 7.21/6.77 bnd_ndr1_1 bnd_a1464) &
% 7.21/6.77 ~ bnd_c5_2 bnd_a1464 bnd_a1465) &
% 7.21/6.77 bnd_c3_2 bnd_a1464 bnd_a1465) &
% 7.21/6.77 bnd_c2_2 bnd_a1464 bnd_a1465) &
% 7.21/6.77 bnd_c2_1 bnd_a1464) &
% 7.21/6.77 bnd_ndr1_1 bnd_a1464) &
% 7.21/6.77 bnd_c2_2 bnd_a1464 bnd_a1466) &
% 7.21/6.77 ~ bnd_c5_2 bnd_a1464 bnd_a1466) &
% 7.21/6.77 ((~ bnd_c3_0 | ~ bnd_c1_0) |
% 7.21/6.77 ((((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a1467) &
% 7.21/6.77 ~ bnd_c5_2 bnd_a1467 bnd_a1468) &
% 7.21/6.77 bnd_c3_2 bnd_a1467 bnd_a1468) &
% 7.21/6.77 bnd_c1_2 bnd_a1467 bnd_a1468) &
% 7.21/6.77 bnd_ndr1_1 bnd_a1467) &
% 7.21/6.77 ~ bnd_c4_2 bnd_a1467 bnd_a1469) &
% 7.21/6.77 bnd_c3_2 bnd_a1467 bnd_a1469) &
% 7.21/6.77 bnd_c1_2 bnd_a1467 bnd_a1469) &
% 7.21/6.77 bnd_c3_1 bnd_a1467)) &
% 7.21/6.77 (((ALL X118.
% 7.21/6.77 bnd_ndr1_0 -->
% 7.21/6.77 (~ bnd_c5_1 X118 | bnd_c1_1 X118) |
% 7.21/6.77 (ALL X119.
% 7.21/6.77 bnd_ndr1_1 X118 -->
% 7.21/6.77 (bnd_c4_2 X118 X119 | ~ bnd_c2_2 X118 X119) |
% 7.21/6.77 bnd_c3_2 X118 X119)) |
% 7.21/6.77 (((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a1470) &
% 7.21/6.77 bnd_c4_2 bnd_a1470 bnd_a1471) &
% 7.21/6.77 ~ bnd_c5_2 bnd_a1470 bnd_a1471) &
% 7.21/6.77 bnd_c2_2 bnd_a1470 bnd_a1471) &
% 7.21/6.77 bnd_ndr1_1 bnd_a1470) &
% 7.21/6.77 bnd_c5_2 bnd_a1470 bnd_a1472) &
% 7.21/6.77 bnd_c1_2 bnd_a1470 bnd_a1472) &
% 7.21/6.77 bnd_c3_2 bnd_a1470 bnd_a1472) |
% 7.21/6.77 ~ bnd_c3_0)) &
% 7.21/6.77 ((~ bnd_c2_0 |
% 7.21/6.77 (ALL X120.
% 7.21/6.77 bnd_ndr1_0 -->
% 7.21/6.77 (((bnd_ndr1_1 X120 & bnd_c3_2 X120 bnd_a1473) &
% 7.21/6.77 ~ bnd_c5_2 X120 bnd_a1473) &
% 7.21/6.77 bnd_c2_2 X120 bnd_a1473 |
% 7.21/6.77 ~ bnd_c4_1 X120) |
% 7.21/6.77 (ALL X121.
% 7.21/6.77 bnd_ndr1_1 X120 -->
% 7.21/6.77 ~ bnd_c1_2 X120 X121 | ~ bnd_c2_2 X120 X121))) |
% 7.21/6.77 (ALL X122.
% 7.21/6.77 bnd_ndr1_0 -->
% 7.21/6.77 ((ALL X123.
% 7.21/6.77 bnd_ndr1_1 X122 --> ~ bnd_c3_2 X122 X123 | bnd_c5_2 X122 X123) |
% 7.21/6.77 ((bnd_ndr1_1 X122 & bnd_c2_2 X122 bnd_a1474) &
% 7.21/6.77 bnd_c5_2 X122 bnd_a1474) &
% 7.21/6.77 bnd_c4_2 X122 bnd_a1474) |
% 7.21/6.77 bnd_c5_1 X122))) &
% 7.21/6.77 ((bnd_c4_0 | bnd_c1_0) | ~ bnd_c2_0)) &
% 7.21/6.77 (((bnd_ndr1_0 &
% 7.21/6.77 (ALL X124.
% 7.21/6.77 bnd_ndr1_1 bnd_a1475 -->
% 7.21/6.77 bnd_c5_2 bnd_a1475 X124 | bnd_c2_2 bnd_a1475 X124)) &
% 7.21/6.77 bnd_c4_1 bnd_a1475) &
% 7.21/6.77 ~ bnd_c5_1 bnd_a1475 |
% 7.21/6.77 bnd_c4_0)) &
% 7.21/6.77 bnd_c3_0) &
% 7.21/6.77 ((ALL X125.
% 7.21/6.77 bnd_ndr1_0 -->
% 7.21/6.77 (~ bnd_c3_1 X125 |
% 7.21/6.78 (ALL X126. bnd_ndr1_1 X125 --> bnd_c5_2 X125 X126 | bnd_c3_2 X125 X126)) |
% 7.21/6.78 ((bnd_ndr1_1 X125 & ~ bnd_c4_2 X125 bnd_a1476) &
% 7.21/6.78 ~ bnd_c2_2 X125 bnd_a1476) &
% 7.21/6.78 ~ bnd_c1_2 X125 bnd_a1476) |
% 7.21/6.78 ~ bnd_c4_0)) &
% 7.21/6.78 (((ALL X127.
% 7.21/6.78 bnd_ndr1_0 -->
% 7.21/6.78 (((bnd_ndr1_1 X127 & bnd_c2_2 X127 bnd_a1477) & ~ bnd_c3_2 X127 bnd_a1477) &
% 7.21/6.78 ~ bnd_c4_2 X127 bnd_a1477 |
% 7.21/6.78 ~ bnd_c1_1 X127) |
% 7.21/6.78 bnd_c5_1 X127) |
% 7.21/6.78 (((((bnd_ndr1_0 &
% 7.21/6.78 (ALL X128.
% 7.21/6.78 bnd_ndr1_1 bnd_a1478 -->
% 7.21/6.78 (bnd_c4_2 bnd_a1478 X128 | bnd_c2_2 bnd_a1478 X128) |
% 7.21/6.78 ~ bnd_c1_2 bnd_a1478 X128)) &
% 7.21/6.78 (ALL X129.
% 7.21/6.78 bnd_ndr1_1 bnd_a1478 -->
% 7.21/6.78 (~ bnd_c1_2 bnd_a1478 X129 | bnd_c3_2 bnd_a1478 X129) |
% 7.21/6.78 bnd_c5_2 bnd_a1478 X129)) &
% 7.21/6.78 bnd_ndr1_1 bnd_a1478) &
% 7.21/6.78 bnd_c5_2 bnd_a1478 bnd_a1479) &
% 7.21/6.78 ~ bnd_c4_2 bnd_a1478 bnd_a1479) &
% 7.21/6.78 bnd_c1_2 bnd_a1478 bnd_a1479) |
% 7.21/6.78 ~ bnd_c2_0)) &
% 7.21/6.78 ((bnd_c1_0 |
% 7.21/6.78 (ALL X130.
% 7.21/6.78 bnd_ndr1_0 -->
% 7.21/6.78 ((bnd_ndr1_1 X130 &
% 7.21/6.78 ~ bnd_c3_2 X130 bnd_a1480) &
% 7.21/6.78 bnd_c4_2 X130 bnd_a1480) &
% 7.21/6.78 ~ bnd_c5_2 X130 bnd_a1480 |
% 7.21/6.78 (bnd_ndr1_1 X130 &
% 7.21/6.78 bnd_c1_2 X130 bnd_a1481) &
% 7.21/6.78 ~ bnd_c2_2 X130 bnd_a1481)) |
% 7.21/6.78 (bnd_ndr1_0 & ~ bnd_c5_1 bnd_a1482) &
% 7.21/6.78 (ALL X131.
% 7.21/6.78 bnd_ndr1_1 bnd_a1482 -->
% 7.21/6.78 (bnd_c3_2 bnd_a1482 X131 |
% 7.21/6.78 ~ bnd_c1_2 bnd_a1482 X131) |
% 7.21/6.78 ~ bnd_c5_2 bnd_a1482 X131))) &
% 7.21/6.78 ((((bnd_ndr1_0 &
% 7.21/6.78 (ALL X132.
% 7.21/6.78 bnd_ndr1_1 bnd_a1483 -->
% 7.21/6.78 (bnd_c3_2 bnd_a1483 X132 | ~ bnd_c2_2 bnd_a1483 X132) |
% 7.21/6.78 bnd_c4_2 bnd_a1483 X132)) &
% 7.21/6.78 ~ bnd_c3_1 bnd_a1483) &
% 7.21/6.78 bnd_c1_1 bnd_a1483 |
% 7.21/6.78 ((((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a1484) &
% 7.21/6.78 bnd_c1_2 bnd_a1484 bnd_a1485) &
% 7.21/6.78 ~ bnd_c3_2 bnd_a1484 bnd_a1485) &
% 7.21/6.78 bnd_c4_2 bnd_a1484 bnd_a1485) &
% 7.21/6.78 ~ bnd_c1_1 bnd_a1484) &
% 7.21/6.78 bnd_ndr1_1 bnd_a1484) &
% 7.21/6.78 bnd_c5_2 bnd_a1484 bnd_a1486) &
% 7.21/6.78 bnd_c2_2 bnd_a1484 bnd_a1486) &
% 7.21/6.78 ~ bnd_c1_2 bnd_a1484 bnd_a1486) |
% 7.21/6.78 (((((bnd_ndr1_0 & bnd_c3_1 bnd_a1487) &
% 7.21/6.78 bnd_c1_1 bnd_a1487) &
% 7.21/6.78 bnd_ndr1_1 bnd_a1487) &
% 7.21/6.78 bnd_c2_2 bnd_a1487 bnd_a1488) &
% 7.21/6.78 bnd_c4_2 bnd_a1487 bnd_a1488) &
% 7.21/6.78 bnd_c5_2 bnd_a1487 bnd_a1488)) &
% 7.21/6.78 (~ bnd_c1_0 | ~ bnd_c2_0)) &
% 7.21/6.78 (ALL X133.
% 7.21/6.78 bnd_ndr1_0 -->
% 7.21/6.78 ((bnd_ndr1_1 X133 &
% 7.21/6.78 ~ bnd_c1_2 X133 bnd_a1489) &
% 7.21/6.78 bnd_c3_2 X133 bnd_a1489 |
% 7.21/6.78 (ALL X134.
% 7.21/6.78 bnd_ndr1_1 X133 -->
% 7.21/6.78 ~ bnd_c5_2 X133 X134 |
% 7.21/6.78 bnd_c4_2 X133 X134)) |
% 7.21/6.78 bnd_c4_1 X133)) &
% 7.21/6.78 (((bnd_ndr1_0 &
% 7.21/6.78 (ALL X135.
% 7.21/6.78 bnd_ndr1_1 bnd_a1490 -->
% 7.21/6.78 ~ bnd_c2_2 bnd_a1490 X135 |
% 7.21/6.78 ~ bnd_c5_2 bnd_a1490 X135)) &
% 7.21/6.78 (ALL X136.
% 7.21/6.78 bnd_ndr1_1 bnd_a1490 -->
% 7.21/6.78 (bnd_c1_2 bnd_a1490 X136 |
% 7.21/6.78 ~ bnd_c5_2 bnd_a1490 X136) |
% 7.21/6.78 bnd_c2_2 bnd_a1490 X136) |
% 7.21/6.78 (ALL X137.
% 7.21/6.78 bnd_ndr1_0 -->
% 7.21/6.78 (bnd_ndr1_1 X137 &
% 7.21/6.78 ~ bnd_c5_2 X137 bnd_a1491) &
% 7.21/6.78 ~ bnd_c1_2 X137 bnd_a1491 |
% 7.21/6.78 ~ bnd_c2_1 X137)) |
% 7.21/6.78 (ALL X138.
% 7.21/6.78 bnd_ndr1_0 -->
% 7.21/6.78 ~ bnd_c3_1 X138 |
% 7.21/6.78 (ALL X139.
% 7.21/6.78 bnd_ndr1_1 X138 -->
% 7.21/6.78 (bnd_c4_2 X138 X139 |
% 7.21/6.78 bnd_c5_2 X138 X139) |
% 7.21/6.78 bnd_c3_2 X138 X139)))) &
% 7.21/6.78 (((ALL X140.
% 7.21/6.78 bnd_ndr1_0 -->
% 7.21/6.78 (((bnd_ndr1_1 X140 &
% 7.21/6.78 bnd_c5_2 X140 bnd_a1492) &
% 7.21/6.78 bnd_c3_2 X140 bnd_a1492) &
% 7.21/6.78 ~ bnd_c4_2 X140 bnd_a1492 |
% 7.21/6.78 (ALL X141.
% 7.21/6.78 bnd_ndr1_1 X140 -->
% 7.21/6.78 (bnd_c5_2 X140 X141 |
% 7.21/6.78 bnd_c1_2 X140 X141) |
% 7.21/6.78 bnd_c2_2 X140 X141)) |
% 7.21/6.78 bnd_c1_1 X140) |
% 7.21/6.78 bnd_c1_0) |
% 7.21/6.78 (bnd_ndr1_0 &
% 7.21/6.78 (ALL X142.
% 7.21/6.78 bnd_ndr1_1 bnd_a1493 -->
% 7.21/6.78 bnd_c2_2 bnd_a1493 X142 |
% 7.21/6.78 bnd_c1_2 bnd_a1493 X142)) &
% 7.21/6.78 ~ bnd_c2_1 bnd_a1493)) &
% 7.21/6.78 bnd_ndr1_0) &
% 7.21/6.78 (ALL X143.
% 7.21/6.78 bnd_ndr1_1 bnd_a1494 -->
% 7.21/6.78 (bnd_c1_2 bnd_a1494 X143 |
% 7.21/6.78 ~ bnd_c2_2 bnd_a1494 X143) |
% 7.21/6.78 bnd_c3_2 bnd_a1494 X143)) &
% 7.21/6.78 (ALL X144.
% 7.21/6.78 bnd_ndr1_1 bnd_a1494 -->
% 7.21/6.78 (~ bnd_c5_2 bnd_a1494 X144 |
% 7.21/6.78 bnd_c3_2 bnd_a1494 X144) |
% 7.21/6.78 bnd_c1_2 bnd_a1494 X144)) &
% 7.21/6.78 bnd_c5_1 bnd_a1494) &
% 7.21/6.78 (((((((bnd_ndr1_0 &
% 7.21/6.78 (ALL X145.
% 7.21/6.78 bnd_ndr1_1 bnd_a1495 -->
% 7.21/6.78 bnd_c1_2 bnd_a1495 X145 |
% 7.21/6.78 ~ bnd_c5_2 bnd_a1495 X145)) &
% 7.21/6.78 bnd_ndr1_1 bnd_a1495) &
% 7.21/6.78 bnd_c1_2 bnd_a1495 bnd_a1496) &
% 7.21/6.78 ~ bnd_c5_2 bnd_a1495 bnd_a1496) &
% 7.21/6.78 bnd_c2_2 bnd_a1495 bnd_a1496) &
% 7.21/6.78 bnd_c2_1 bnd_a1495 |
% 7.21/6.78 (ALL X146.
% 7.21/6.78 bnd_ndr1_0 -->
% 7.21/6.78 bnd_c4_1 X146 |
% 7.21/6.78 ((bnd_ndr1_1 X146 & bnd_c4_2 X146 bnd_a1497) &
% 7.21/6.78 bnd_c5_2 X146 bnd_a1497) &
% 7.21/6.78 bnd_c2_2 X146 bnd_a1497)) |
% 7.21/6.78 (ALL X147.
% 7.21/6.78 bnd_ndr1_0 -->
% 7.21/6.78 (~ bnd_c3_1 X147 |
% 7.21/6.78 (ALL X148.
% 7.21/6.78 bnd_ndr1_1 X147 -->
% 7.21/6.78 (~ bnd_c2_2 X147 X148 |
% 7.21/6.78 ~ bnd_c5_2 X147 X148) |
% 7.21/6.78 bnd_c3_2 X147 X148)) |
% 7.21/6.78 bnd_c5_1 X147))) &
% 7.21/6.78 ((bnd_c2_0 |
% 7.21/6.78 ((bnd_ndr1_0 &
% 7.21/6.78 (ALL X149.
% 7.21/6.78 bnd_ndr1_1 bnd_a1498 -->
% 7.21/6.78 ~ bnd_c4_2 bnd_a1498 X149 |
% 7.21/6.78 bnd_c5_2 bnd_a1498 X149)) &
% 7.21/6.78 ~ bnd_c5_1 bnd_a1498) &
% 7.21/6.78 (ALL X150.
% 7.21/6.78 bnd_ndr1_1 bnd_a1498 -->
% 7.21/6.78 (bnd_c5_2 bnd_a1498 X150 |
% 7.21/6.78 bnd_c4_2 bnd_a1498 X150) |
% 7.21/6.78 bnd_c1_2 bnd_a1498 X150)) |
% 7.21/6.78 bnd_c4_0)) &
% 7.21/6.78 ((((bnd_ndr1_0 & ~ bnd_c3_1 bnd_a1499) &
% 7.21/6.78 ~ bnd_c5_1 bnd_a1499) &
% 7.21/6.78 (ALL X151.
% 7.21/6.78 bnd_ndr1_1 bnd_a1499 -->
% 7.21/6.78 ~ bnd_c1_2 bnd_a1499 X151 |
% 7.21/6.78 bnd_c5_2 bnd_a1499 X151) |
% 7.21/6.78 (((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a1500) &
% 7.21/6.78 ~ bnd_c4_2 bnd_a1500 bnd_a1501) &
% 7.21/6.78 ~ bnd_c3_2 bnd_a1500 bnd_a1501) &
% 7.21/6.78 bnd_c2_2 bnd_a1500 bnd_a1501) &
% 7.21/6.78 bnd_ndr1_1 bnd_a1500) &
% 7.21/6.78 ~ bnd_c4_2 bnd_a1500 bnd_a1502) &
% 7.21/6.78 bnd_c3_2 bnd_a1500 bnd_a1502) &
% 7.21/6.78 bnd_c2_2 bnd_a1500 bnd_a1502) |
% 7.21/6.78 ((bnd_ndr1_0 & ~ bnd_c5_1 bnd_a1503) &
% 7.21/6.78 (ALL X152.
% 7.21/6.78 bnd_ndr1_1 bnd_a1503 -->
% 7.21/6.78 (bnd_c5_2 bnd_a1503 X152 |
% 7.21/6.78 ~ bnd_c2_2 bnd_a1503 X152) |
% 7.21/6.78 ~ bnd_c1_2 bnd_a1503 X152)) &
% 7.21/6.78 ~ bnd_c3_1 bnd_a1503)) &
% 7.21/6.78 (((ALL X153.
% 7.21/6.78 bnd_ndr1_0 -->
% 7.21/6.78 ((ALL X154.
% 7.21/6.78 bnd_ndr1_1 X153 -->
% 7.21/6.78 (bnd_c1_2 X153 X154 | ~ bnd_c4_2 X153 X154) |
% 7.21/6.78 bnd_c3_2 X153 X154) |
% 7.21/6.78 bnd_c2_1 X153) |
% 7.21/6.78 ~ bnd_c3_1 X153) |
% 7.21/6.78 bnd_c1_0) |
% 7.21/6.78 ((bnd_ndr1_0 & ~ bnd_c1_1 bnd_a1504) &
% 7.21/6.78 ~ bnd_c4_1 bnd_a1504) &
% 7.21/6.78 (ALL X155.
% 7.21/6.78 bnd_ndr1_1 bnd_a1504 -->
% 7.21/6.78 (~ bnd_c3_2 bnd_a1504 X155 |
% 7.21/6.78 bnd_c5_2 bnd_a1504 X155) |
% 7.21/6.78 ~ bnd_c4_2 bnd_a1504 X155))) &
% 7.21/6.78 (bnd_c2_0 |
% 7.21/6.78 (ALL X156.
% 7.21/6.78 bnd_ndr1_0 -->
% 7.21/6.78 ((bnd_ndr1_1 X156 & bnd_c2_2 X156 bnd_a1505) &
% 7.21/6.78 ~ bnd_c4_2 X156 bnd_a1505) &
% 7.21/6.78 bnd_c3_2 X156 bnd_a1505 |
% 7.21/6.78 (ALL X157.
% 7.21/6.78 bnd_ndr1_1 X156 -->
% 7.21/6.78 (~ bnd_c5_2 X156 X157 | ~ bnd_c1_2 X156 X157) |
% 7.21/6.78 ~ bnd_c2_2 X156 X157)))) &
% 7.21/6.78 ((bnd_c1_0 | ~ bnd_c2_0) | ~ bnd_c4_0)) &
% 7.21/6.78 (~ bnd_c1_0 |
% 7.21/6.78 ((((bnd_ndr1_0 &
% 7.21/6.78 (ALL X158.
% 7.21/6.78 bnd_ndr1_1 bnd_a1506 -->
% 7.21/6.78 (~ bnd_c1_2 bnd_a1506 X158 |
% 7.21/6.78 bnd_c3_2 bnd_a1506 X158) |
% 7.21/6.78 ~ bnd_c4_2 bnd_a1506 X158)) &
% 7.21/6.78 ~ bnd_c1_1 bnd_a1506) &
% 7.21/6.78 bnd_ndr1_1 bnd_a1506) &
% 7.21/6.78 bnd_c4_2 bnd_a1506 bnd_a1507) &
% 7.21/6.78 ~ bnd_c2_2 bnd_a1506 bnd_a1507)) &
% 7.21/6.78 (bnd_c4_0 | ~ bnd_c2_0)) &
% 7.21/6.78 ((bnd_ndr1_0 & ~ bnd_c3_1 bnd_a1508 |
% 7.21/6.78 (ALL X159. bnd_ndr1_0 --> bnd_c1_1 X159 | bnd_c5_1 X159)) |
% 7.21/6.78 ~ bnd_c1_0)) &
% 7.21/6.78 (((bnd_ndr1_0 &
% 7.21/6.78 (ALL X160.
% 7.21/6.78 bnd_ndr1_1 bnd_a1509 -->
% 7.21/6.78 bnd_c2_2 bnd_a1509 X160 | ~ bnd_c3_2 bnd_a1509 X160)) &
% 7.21/6.78 bnd_c1_1 bnd_a1509) &
% 7.21/6.78 (ALL X161.
% 7.21/6.78 bnd_ndr1_1 bnd_a1509 -->
% 7.21/6.78 (bnd_c1_2 bnd_a1509 X161 | bnd_c3_2 bnd_a1509 X161) |
% 7.21/6.78 bnd_c2_2 bnd_a1509 X161) |
% 7.21/6.78 ~ bnd_c1_0)) &
% 7.21/6.78 (((((bnd_ndr1_0 & bnd_c5_1 bnd_a1510) & bnd_ndr1_1 bnd_a1510) &
% 7.21/6.78 ~ bnd_c2_2 bnd_a1510 bnd_a1511) &
% 7.21/6.78 ~ bnd_c1_2 bnd_a1510 bnd_a1511) &
% 7.21/6.78 ~ bnd_c5_2 bnd_a1510 bnd_a1511 |
% 7.21/6.78 (ALL X162.
% 7.21/6.78 bnd_ndr1_0 -->
% 7.21/6.78 (~ bnd_c3_1 X162 | bnd_c5_1 X162) | ~ bnd_c1_1 X162))) &
% 7.21/6.78 ((~ bnd_c1_0 |
% 7.21/6.78 (ALL X163.
% 7.21/6.78 bnd_ndr1_0 -->
% 7.21/6.78 (((bnd_ndr1_1 X163 & ~ bnd_c2_2 X163 bnd_a1512) &
% 7.21/6.78 ~ bnd_c1_2 X163 bnd_a1512) &
% 7.21/6.78 ~ bnd_c5_2 X163 bnd_a1512 |
% 7.21/6.78 ((bnd_ndr1_1 X163 & bnd_c4_2 X163 bnd_a1513) &
% 7.21/6.78 ~ bnd_c1_2 X163 bnd_a1513) &
% 7.21/6.78 bnd_c2_2 X163 bnd_a1513) |
% 7.21/6.78 (bnd_ndr1_1 X163 & bnd_c3_2 X163 bnd_a1514) &
% 7.21/6.78 bnd_c2_2 X163 bnd_a1514)) |
% 7.21/6.78 bnd_c4_0)) &
% 7.21/6.78 (((bnd_ndr1_0 & bnd_c3_1 bnd_a1515) & bnd_c1_1 bnd_a1515 |
% 7.21/6.78 (bnd_ndr1_0 & bnd_c5_1 bnd_a1516) & ~ bnd_c2_1 bnd_a1516) |
% 7.21/6.78 bnd_c2_0)) &
% 7.21/6.78 ((bnd_c1_0 | ~ bnd_c4_0) |
% 7.21/6.78 (ALL X164.
% 7.21/6.78 bnd_ndr1_0 -->
% 7.21/6.78 ((ALL X165.
% 7.21/6.78 bnd_ndr1_1 X164 -->
% 7.21/6.78 bnd_c1_2 X164 X165 | ~ bnd_c4_2 X164 X165) |
% 7.21/6.78 ((bnd_ndr1_1 X164 & ~ bnd_c3_2 X164 bnd_a1517) &
% 7.21/6.78 ~ bnd_c4_2 X164 bnd_a1517) &
% 7.21/6.78 bnd_c1_2 X164 bnd_a1517) |
% 7.21/6.78 ((bnd_ndr1_1 X164 & ~ bnd_c4_2 X164 bnd_a1518) &
% 7.21/6.78 bnd_c1_2 X164 bnd_a1518) &
% 7.21/6.78 bnd_c5_2 X164 bnd_a1518))) &
% 7.21/6.78 (bnd_c2_0 | ~ bnd_c1_0)) &
% 7.21/6.78 (((ALL X166.
% 7.21/6.78 bnd_ndr1_0 -->
% 7.21/6.78 (ALL X167.
% 7.21/6.78 bnd_ndr1_1 X166 -->
% 7.21/6.78 ~ bnd_c1_2 X166 X167 | bnd_c3_2 X166 X167) |
% 7.21/6.78 ((bnd_ndr1_1 X166 & ~ bnd_c5_2 X166 bnd_a1519) &
% 7.21/6.78 bnd_c3_2 X166 bnd_a1519) &
% 7.21/6.78 ~ bnd_c4_2 X166 bnd_a1519) |
% 7.21/6.78 ((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a1520) &
% 7.21/6.78 ~ bnd_c5_2 bnd_a1520 bnd_a1521) &
% 7.21/6.78 ~ bnd_c3_2 bnd_a1520 bnd_a1521) &
% 7.21/6.78 bnd_ndr1_1 bnd_a1520) &
% 7.21/6.78 bnd_c4_2 bnd_a1520 bnd_a1522) &
% 7.21/6.78 ~ bnd_c3_2 bnd_a1520 bnd_a1522) &
% 7.21/6.78 bnd_c2_1 bnd_a1520) |
% 7.21/6.78 ~ bnd_c2_0)) &
% 7.21/6.78 (((ALL X168.
% 7.21/6.78 bnd_ndr1_0 -->
% 7.21/6.78 (~ bnd_c1_1 X168 |
% 7.21/6.78 (ALL X169.
% 7.21/6.78 bnd_ndr1_1 X168 -->
% 7.21/6.78 (bnd_c4_2 X168 X169 | bnd_c1_2 X168 X169) |
% 7.21/6.78 bnd_c2_2 X168 X169)) |
% 7.21/6.78 ((bnd_ndr1_1 X168 & ~ bnd_c2_2 X168 bnd_a1523) &
% 7.21/6.78 ~ bnd_c5_2 X168 bnd_a1523) &
% 7.21/6.78 ~ bnd_c4_2 X168 bnd_a1523) |
% 7.21/6.78 bnd_c1_0) |
% 7.21/6.78 ((bnd_ndr1_0 &
% 7.21/6.78 (ALL X170.
% 7.21/6.78 bnd_ndr1_1 bnd_a1524 -->
% 7.21/6.78 ~ bnd_c4_2 bnd_a1524 X170 | bnd_c1_2 bnd_a1524 X170)) &
% 7.21/6.78 bnd_ndr1_1 bnd_a1524) &
% 7.21/6.78 bnd_c5_2 bnd_a1524 bnd_a1525)) &
% 7.21/6.78 ((bnd_c2_0 |
% 7.21/6.78 (ALL X171.
% 7.21/6.78 bnd_ndr1_0 -->
% 7.21/6.78 (((bnd_ndr1_1 X171 & bnd_c1_2 X171 bnd_a1526) &
% 7.21/6.78 bnd_c4_2 X171 bnd_a1526) &
% 7.21/6.78 ~ bnd_c2_2 X171 bnd_a1526 |
% 7.21/6.78 bnd_c4_1 X171) |
% 7.21/6.78 ~ bnd_c1_1 X171)) |
% 7.21/6.78 (ALL X172.
% 7.21/6.78 bnd_ndr1_0 -->
% 7.21/6.78 (~ bnd_c1_1 X172 | bnd_c2_1 X172) | ~ bnd_c4_1 X172))) &
% 7.21/6.78 ((ALL X173.
% 7.21/6.78 bnd_ndr1_0 -->
% 7.21/6.78 (~ bnd_c1_1 X173 | ~ bnd_c3_1 X173) | ~ bnd_c2_1 X173) |
% 7.21/6.78 (ALL X174.
% 7.21/6.78 bnd_ndr1_0 -->
% 7.21/6.78 (~ bnd_c5_1 X174 |
% 7.21/6.78 (ALL X175.
% 7.21/6.78 bnd_ndr1_1 X174 -->
% 7.21/6.78 (~ bnd_c1_2 X174 X175 | ~ bnd_c5_2 X174 X175) |
% 7.21/6.78 ~ bnd_c3_2 X174 X175)) |
% 7.21/6.78 ~ bnd_c2_1 X174)))
% 17.92/17.49 Unfolded term: ~ (((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((ALL U.
% 17.92/17.49 bnd_ndr1_0 -->
% 17.92/17.49 ((bnd_ndr1_1 U & ~ bnd_c5_2 U bnd_a1323) &
% 17.92/17.49 ~ bnd_c1_2 U bnd_a1323 |
% 17.92/17.49 (ALL V.
% 17.92/17.49 bnd_ndr1_1 U -->
% 17.92/17.49 ~ bnd_c1_2 U V | ~ bnd_c2_2 U V)) |
% 17.92/17.49 (ALL W.
% 17.92/17.49 bnd_ndr1_1 U -->
% 17.92/17.49 bnd_c4_2 U W | ~ bnd_c3_2 U W)) |
% 17.92/17.49 ~ bnd_c5_0) |
% 17.92/17.49 (ALL X. bnd_ndr1_0 --> bnd_c2_1 X)) &
% 17.92/17.49 ((ALL Y.
% 17.92/17.49 bnd_ndr1_0 -->
% 17.92/17.49 (((bnd_ndr1_1 Y & bnd_c3_2 Y bnd_a1324) &
% 17.92/17.49 bnd_c4_2 Y bnd_a1324) &
% 17.92/17.49 bnd_c5_2 Y bnd_a1324 |
% 17.92/17.49 ~ bnd_c4_1 Y) |
% 17.92/17.49 bnd_c3_1 Y) |
% 17.92/17.49 ((bnd_ndr1_0 & ~ bnd_c1_1 bnd_a1325) &
% 17.92/17.49 bnd_c2_1 bnd_a1325) &
% 17.92/17.49 ~ bnd_c4_1 bnd_a1325)) &
% 17.92/17.49 (~ bnd_c4_0 |
% 17.92/17.49 (ALL Z.
% 17.92/17.49 bnd_ndr1_0 -->
% 17.92/17.49 (bnd_c5_1 Z | ~ bnd_c4_1 Z) |
% 17.92/17.49 ((bnd_ndr1_1 Z & bnd_c5_2 Z bnd_a1326) &
% 17.92/17.49 bnd_c2_2 Z bnd_a1326) &
% 17.92/17.49 ~ bnd_c4_2 Z bnd_a1326))) &
% 17.92/17.49 (((((((bnd_ndr1_0 &
% 17.92/17.49 (ALL X1.
% 17.92/17.49 bnd_ndr1_1 bnd_a1327 -->
% 17.92/17.49 (bnd_c3_2 bnd_a1327 X1 |
% 17.92/17.49 bnd_c1_2 bnd_a1327 X1) |
% 17.92/17.49 bnd_c2_2 bnd_a1327 X1)) &
% 17.92/17.49 bnd_c3_1 bnd_a1327) &
% 17.92/17.49 bnd_ndr1_1 bnd_a1327) &
% 17.92/17.49 ~ bnd_c5_2 bnd_a1327 bnd_a1328) &
% 17.92/17.49 bnd_c3_2 bnd_a1327 bnd_a1328) &
% 17.92/17.49 bnd_c4_2 bnd_a1327 bnd_a1328 |
% 17.92/17.49 (ALL X2.
% 17.92/17.49 bnd_ndr1_0 -->
% 17.92/17.49 (((bnd_ndr1_1 X2 & ~ bnd_c1_2 X2 bnd_a1329) &
% 17.92/17.49 ~ bnd_c4_2 X2 bnd_a1329) &
% 17.92/17.49 bnd_c2_2 X2 bnd_a1329 |
% 17.92/17.49 ((bnd_ndr1_1 X2 & bnd_c1_2 X2 bnd_a1330) &
% 17.92/17.49 ~ bnd_c2_2 X2 bnd_a1330) &
% 17.92/17.49 bnd_c3_2 X2 bnd_a1330) |
% 17.92/17.49 (bnd_ndr1_1 X2 & bnd_c3_2 X2 bnd_a1331) &
% 17.92/17.49 bnd_c2_2 X2 bnd_a1331)) |
% 17.92/17.49 ~ bnd_c5_0)) &
% 17.92/17.49 ((~ bnd_c2_0 | ~ bnd_c4_0) | ~ bnd_c3_0)) &
% 17.92/17.49 ((bnd_c1_0 | ~ bnd_c4_0) |
% 17.92/17.49 ((bnd_ndr1_0 & bnd_c2_1 bnd_a1332) &
% 17.92/17.49 ~ bnd_c1_1 bnd_a1332) &
% 17.92/17.49 ~ bnd_c4_1 bnd_a1332)) &
% 17.92/17.49 ((bnd_c5_0 | ~ bnd_c3_0) |
% 17.92/17.49 (((((bnd_ndr1_0 & bnd_c1_1 bnd_a1333) &
% 17.92/17.49 (ALL X3.
% 17.92/17.49 bnd_ndr1_1 bnd_a1333 -->
% 17.92/17.49 (bnd_c4_2 bnd_a1333 X3 |
% 17.92/17.49 ~ bnd_c1_2 bnd_a1333 X3) |
% 17.92/17.49 ~ bnd_c3_2 bnd_a1333 X3)) &
% 17.92/17.49 bnd_ndr1_1 bnd_a1333) &
% 17.92/17.49 ~ bnd_c1_2 bnd_a1333 bnd_a1334) &
% 17.92/17.49 bnd_c5_2 bnd_a1333 bnd_a1334) &
% 17.92/17.49 bnd_c4_2 bnd_a1333 bnd_a1334)) &
% 17.92/17.49 ((~ bnd_c2_0 | bnd_c3_0) |
% 17.92/17.49 (ALL X4.
% 17.92/17.49 bnd_ndr1_0 -->
% 17.92/17.49 (bnd_c4_1 X4 |
% 17.92/17.49 (ALL X5.
% 17.92/17.49 bnd_ndr1_1 X4 -->
% 17.92/17.49 (~ bnd_c2_2 X4 X5 | ~ bnd_c5_2 X4 X5) |
% 17.92/17.49 bnd_c4_2 X4 X5)) |
% 17.92/17.49 bnd_c5_1 X4))) &
% 17.92/17.49 (((((((bnd_ndr1_0 &
% 17.92/17.49 (ALL X6.
% 17.92/17.49 bnd_ndr1_1 bnd_a1335 -->
% 17.92/17.49 bnd_c3_2 bnd_a1335 X6 |
% 17.92/17.49 ~ bnd_c5_2 bnd_a1335 X6)) &
% 17.92/17.49 bnd_ndr1_1 bnd_a1335) &
% 17.92/17.49 bnd_c5_2 bnd_a1335 bnd_a1336) &
% 17.92/17.49 ~ bnd_c2_2 bnd_a1335 bnd_a1336) &
% 17.92/17.49 ~ bnd_c4_2 bnd_a1335 bnd_a1336) &
% 17.92/17.49 ~ bnd_c3_1 bnd_a1335 |
% 17.92/17.49 ~ bnd_c3_0) |
% 17.92/17.49 (bnd_ndr1_0 & ~ bnd_c5_1 bnd_a1337) &
% 17.92/17.49 ~ bnd_c4_1 bnd_a1337)) &
% 17.92/17.49 (~ bnd_c1_0 |
% 17.92/17.49 ((bnd_ndr1_0 & ~ bnd_c4_1 bnd_a1338) &
% 17.92/17.49 (ALL X7.
% 17.92/17.49 bnd_ndr1_1 bnd_a1338 -->
% 17.92/17.49 (~ bnd_c2_2 bnd_a1338 X7 |
% 17.92/17.49 ~ bnd_c3_2 bnd_a1338 X7) |
% 17.92/17.49 ~ bnd_c5_2 bnd_a1338 X7)) &
% 17.92/17.49 ~ bnd_c2_1 bnd_a1338)) &
% 17.92/17.49 (((bnd_ndr1_0 & bnd_c5_1 bnd_a1339) &
% 17.92/17.49 ~ bnd_c1_1 bnd_a1339) &
% 17.92/17.49 (ALL X8.
% 17.92/17.49 bnd_ndr1_1 bnd_a1339 -->
% 17.92/17.49 (~ bnd_c1_2 bnd_a1339 X8 | ~ bnd_c5_2 bnd_a1339 X8) |
% 17.92/17.49 bnd_c4_2 bnd_a1339 X8) |
% 17.92/17.49 ~ bnd_c1_0)) &
% 17.92/17.49 (((ALL X9.
% 17.92/17.49 bnd_ndr1_0 -->
% 17.92/17.49 (bnd_c2_1 X9 |
% 17.92/17.49 (bnd_ndr1_1 X9 & ~ bnd_c4_2 X9 bnd_a1340) &
% 17.92/17.49 ~ bnd_c2_2 X9 bnd_a1340) |
% 17.92/17.49 (bnd_ndr1_1 X9 & bnd_c5_2 X9 bnd_a1341) &
% 17.92/17.49 ~ bnd_c4_2 X9 bnd_a1341) |
% 17.92/17.49 ~ bnd_c3_0) |
% 17.92/17.49 bnd_c4_0)) &
% 17.92/17.49 ((~ bnd_c4_0 |
% 17.92/17.49 (ALL X10.
% 17.92/17.49 bnd_ndr1_0 --> ~ bnd_c2_1 X10 | ~ bnd_c5_1 X10)) |
% 17.92/17.49 (ALL X11.
% 17.92/17.49 bnd_ndr1_0 --> ~ bnd_c5_1 X11 | ~ bnd_c2_1 X11))) &
% 17.92/17.49 ((((((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a1342) &
% 17.92/17.49 bnd_c1_2 bnd_a1342 bnd_a1343) &
% 17.92/17.49 bnd_c3_2 bnd_a1342 bnd_a1343) &
% 17.92/17.49 ~ bnd_c4_2 bnd_a1342 bnd_a1343) &
% 17.92/17.49 ~ bnd_c4_1 bnd_a1342) &
% 17.92/17.49 bnd_ndr1_1 bnd_a1342) &
% 17.92/17.49 bnd_c2_2 bnd_a1342 bnd_a1344) &
% 17.92/17.49 ~ bnd_c1_2 bnd_a1342 bnd_a1344) &
% 17.92/17.49 ~ bnd_c5_2 bnd_a1342 bnd_a1344 |
% 17.92/17.49 ((bnd_ndr1_0 & ~ bnd_c5_1 bnd_a1345) &
% 17.92/17.49 ~ bnd_c1_1 bnd_a1345) &
% 17.92/17.49 bnd_c3_1 bnd_a1345) |
% 17.92/17.49 bnd_c3_0)) &
% 17.92/17.49 ((bnd_c1_0 | ~ bnd_c2_0) | bnd_c5_0)) &
% 17.92/17.49 ((bnd_c2_0 |
% 17.92/17.49 ((bnd_ndr1_0 & bnd_c3_1 bnd_a1346) & ~ bnd_c4_1 bnd_a1346) &
% 17.92/17.49 bnd_c2_1 bnd_a1346) |
% 17.92/17.49 (ALL X12.
% 17.92/17.49 bnd_ndr1_0 -->
% 17.92/17.49 (~ bnd_c5_1 X12 | bnd_c4_1 X12) |
% 17.92/17.49 (ALL X13.
% 17.92/17.49 bnd_ndr1_1 X12 -->
% 17.92/17.49 bnd_c4_2 X12 X13 | ~ bnd_c3_2 X12 X13)))) &
% 17.92/17.49 (((ALL X14.
% 17.92/17.49 bnd_ndr1_0 -->
% 17.92/17.49 ((ALL X15.
% 17.92/17.49 bnd_ndr1_1 X14 -->
% 17.92/17.49 (~ bnd_c4_2 X14 X15 | bnd_c2_2 X14 X15) |
% 17.92/17.49 ~ bnd_c5_2 X14 X15) |
% 17.92/17.49 ((bnd_ndr1_1 X14 & ~ bnd_c5_2 X14 bnd_a1347) &
% 17.92/17.49 bnd_c4_2 X14 bnd_a1347) &
% 17.92/17.49 bnd_c1_2 X14 bnd_a1347) |
% 17.92/17.49 bnd_c1_1 X14) |
% 17.92/17.49 (ALL X16.
% 17.92/17.49 bnd_ndr1_0 -->
% 17.92/17.49 (~ bnd_c5_1 X16 | bnd_c3_1 X16) | ~ bnd_c4_1 X16)) |
% 17.92/17.49 bnd_c5_0)) &
% 17.92/17.49 (((((((bnd_ndr1_0 & ~ bnd_c4_1 bnd_a1348) &
% 17.92/17.49 (ALL X17.
% 17.92/17.49 bnd_ndr1_1 bnd_a1348 -->
% 17.92/17.49 (bnd_c1_2 bnd_a1348 X17 | ~ bnd_c4_2 bnd_a1348 X17) |
% 17.92/17.49 ~ bnd_c5_2 bnd_a1348 X17)) &
% 17.92/17.49 bnd_ndr1_1 bnd_a1348) &
% 17.92/17.49 ~ bnd_c4_2 bnd_a1348 bnd_a1349) &
% 17.92/17.49 ~ bnd_c3_2 bnd_a1348 bnd_a1349) &
% 17.92/17.49 ~ bnd_c1_2 bnd_a1348 bnd_a1349 |
% 17.92/17.49 (ALL X18. bnd_ndr1_0 --> bnd_c2_1 X18 | ~ bnd_c3_1 X18)) |
% 17.92/17.49 ~ bnd_c4_0)) &
% 17.92/17.49 (bnd_c3_0 | bnd_c2_0)) &
% 17.92/17.49 (bnd_c2_0 |
% 17.92/17.49 (bnd_ndr1_0 & bnd_c5_1 bnd_a1350) & ~ bnd_c2_1 bnd_a1350)) &
% 17.92/17.49 (((bnd_ndr1_0 & ~ bnd_c1_1 bnd_a1351) & ~ bnd_c5_1 bnd_a1351 |
% 17.92/17.49 (ALL X19.
% 17.92/17.49 bnd_ndr1_0 -->
% 17.92/17.49 (~ bnd_c3_1 X19 | bnd_c5_1 X19) | ~ bnd_c4_1 X19)) |
% 17.92/17.49 bnd_c3_0)) &
% 17.92/17.49 ((~ bnd_c2_0 |
% 17.92/17.49 (((((bnd_ndr1_0 & ~ bnd_c4_1 bnd_a1352) &
% 17.92/17.49 (ALL X20.
% 17.92/17.49 bnd_ndr1_1 bnd_a1352 -->
% 17.92/17.49 (~ bnd_c5_2 bnd_a1352 X20 | bnd_c4_2 bnd_a1352 X20) |
% 17.92/17.49 bnd_c1_2 bnd_a1352 X20)) &
% 17.92/17.49 bnd_ndr1_1 bnd_a1352) &
% 17.92/17.49 ~ bnd_c4_2 bnd_a1352 bnd_a1353) &
% 17.92/17.49 bnd_c5_2 bnd_a1352 bnd_a1353) &
% 17.92/17.49 ~ bnd_c3_2 bnd_a1352 bnd_a1353) |
% 17.92/17.49 (ALL X21.
% 17.92/17.49 bnd_ndr1_0 -->
% 17.92/17.49 (~ bnd_c2_1 X21 |
% 17.92/17.49 ((bnd_ndr1_1 X21 & ~ bnd_c3_2 X21 bnd_a1354) &
% 17.92/17.49 bnd_c1_2 X21 bnd_a1354) &
% 17.92/17.49 ~ bnd_c5_2 X21 bnd_a1354) |
% 17.92/17.49 ~ bnd_c5_1 X21))) &
% 17.92/17.49 ((~ bnd_c4_0 |
% 17.92/17.49 (ALL X22.
% 17.92/17.49 bnd_ndr1_0 -->
% 17.92/17.49 (~ bnd_c1_1 X22 | ~ bnd_c5_1 X22) | ~ bnd_c4_1 X22)) |
% 17.92/17.49 (ALL X23.
% 17.92/17.49 bnd_ndr1_0 -->
% 17.92/17.49 ((ALL X24. bnd_ndr1_1 X23 --> bnd_c2_2 X23 X24) |
% 17.92/17.49 ((bnd_ndr1_1 X23 & bnd_c2_2 X23 bnd_a1355) &
% 17.92/17.49 bnd_c5_2 X23 bnd_a1355) &
% 17.92/17.49 ~ bnd_c1_2 X23 bnd_a1355) |
% 17.92/17.49 ~ bnd_c5_1 X23))) &
% 17.92/17.49 ((~ bnd_c3_0 | ~ bnd_c2_0) | bnd_c4_0)) &
% 17.92/17.49 ((~ bnd_c5_0 |
% 17.92/17.49 (ALL X25.
% 17.92/17.49 bnd_ndr1_0 -->
% 17.92/17.49 (~ bnd_c4_1 X25 |
% 17.92/17.49 (ALL X26.
% 17.92/17.49 bnd_ndr1_1 X25 --> bnd_c3_2 X25 X26 | bnd_c4_2 X25 X26)) |
% 17.92/17.49 ((bnd_ndr1_1 X25 & bnd_c5_2 X25 bnd_a1356) &
% 17.92/17.49 bnd_c4_2 X25 bnd_a1356) &
% 17.92/17.49 bnd_c2_2 X25 bnd_a1356)) |
% 17.92/17.49 bnd_c2_0)) &
% 17.92/17.49 (~ bnd_c5_0 | bnd_c3_0)) &
% 17.92/17.49 (((ALL X27.
% 17.92/17.49 bnd_ndr1_0 -->
% 17.92/17.49 (((bnd_ndr1_1 X27 & ~ bnd_c4_2 X27 bnd_a1357) &
% 17.92/17.49 bnd_c5_2 X27 bnd_a1357) &
% 17.92/17.49 bnd_c1_2 X27 bnd_a1357 |
% 17.92/17.49 ((bnd_ndr1_1 X27 & bnd_c3_2 X27 bnd_a1358) &
% 17.92/17.49 bnd_c2_2 X27 bnd_a1358) &
% 17.92/17.49 bnd_c1_2 X27 bnd_a1358) |
% 17.92/17.49 bnd_c1_1 X27) |
% 17.92/17.49 bnd_c4_0) |
% 17.92/17.49 (ALL X28.
% 17.92/17.49 bnd_ndr1_0 -->
% 17.92/17.49 (ALL X29.
% 17.92/17.49 bnd_ndr1_1 X28 --> ~ bnd_c3_2 X28 X29 | ~ bnd_c4_2 X28 X29) |
% 17.92/17.49 ~ bnd_c4_1 X28))) &
% 17.92/17.49 ((~ bnd_c4_0 | bnd_c5_0) | bnd_c1_0)) &
% 17.92/17.49 ((((((bnd_ndr1_0 &
% 17.92/17.49 bnd_c2_1 bnd_a1359) &
% 17.92/17.49 (ALL X30.
% 17.92/17.49 bnd_ndr1_1 bnd_a1359 -->
% 17.92/17.49 (~ bnd_c3_2 bnd_a1359 X30 | bnd_c1_2 bnd_a1359 X30) |
% 17.92/17.49 bnd_c5_2 bnd_a1359 X30)) &
% 17.92/17.49 bnd_ndr1_1 bnd_a1359) &
% 17.92/17.49 ~ bnd_c2_2 bnd_a1359 bnd_a1360) &
% 17.92/17.49 ~ bnd_c1_2 bnd_a1359 bnd_a1360) &
% 17.92/17.49 ~ bnd_c3_2 bnd_a1359 bnd_a1360 |
% 17.92/17.49 (bnd_ndr1_0 & ~ bnd_c1_1 bnd_a1361) & ~ bnd_c5_1 bnd_a1361)) &
% 17.92/17.49 ((~ bnd_c3_0 | bnd_c5_0) |
% 17.92/17.49 ~ bnd_c4_0)) &
% 17.92/17.49 (~ bnd_c2_0 |
% 17.92/17.49 (ALL X31.
% 17.92/17.49 bnd_ndr1_0 -->
% 17.92/17.49 ((ALL X32.
% 17.92/17.49 bnd_ndr1_1 X31 -->
% 17.92/17.49 (~ bnd_c5_2 X31 X32 | bnd_c2_2 X31 X32) | ~ bnd_c4_2 X31 X32) |
% 17.92/17.49 ((bnd_ndr1_1 X31 & bnd_c3_2 X31 bnd_a1362) & bnd_c2_2 X31 bnd_a1362) &
% 17.92/17.49 bnd_c5_2 X31 bnd_a1362) |
% 17.92/17.49 bnd_c1_1 X31))) &
% 17.92/17.49 ((bnd_c1_0 |
% 17.92/17.49 (((((bnd_ndr1_0 &
% 17.92/17.49 (ALL X33.
% 17.92/17.49 bnd_ndr1_1 bnd_a1363 -->
% 17.92/17.49 ~ bnd_c3_2 bnd_a1363 X33 | bnd_c2_2 bnd_a1363 X33)) &
% 17.92/17.49 bnd_ndr1_1 bnd_a1363) &
% 17.92/17.49 ~ bnd_c2_2 bnd_a1363 bnd_a1364) &
% 17.92/17.49 bnd_c5_2 bnd_a1363 bnd_a1364) &
% 17.92/17.49 bnd_c1_2 bnd_a1363 bnd_a1364) &
% 17.92/17.49 ~ bnd_c2_1 bnd_a1363) |
% 17.92/17.49 ~ bnd_c3_0)) &
% 17.92/17.49 ((~ bnd_c4_0 |
% 17.92/17.49 ((bnd_ndr1_0 &
% 17.92/17.49 (ALL X34.
% 17.92/17.49 bnd_ndr1_1 bnd_a1365 -->
% 17.92/17.49 (~ bnd_c5_2 bnd_a1365 X34 | bnd_c2_2 bnd_a1365 X34) |
% 17.92/17.49 bnd_c1_2 bnd_a1365 X34)) &
% 17.92/17.49 (ALL X35.
% 17.92/17.49 bnd_ndr1_1 bnd_a1365 -->
% 17.92/17.49 (bnd_c1_2 bnd_a1365 X35 | ~ bnd_c4_2 bnd_a1365 X35) |
% 17.92/17.49 bnd_c3_2 bnd_a1365 X35)) &
% 17.92/17.49 bnd_c3_1 bnd_a1365) |
% 17.92/17.49 (bnd_ndr1_0 & ~ bnd_c3_1 bnd_a1366) &
% 17.92/17.49 ~ bnd_c1_1 bnd_a1366)) &
% 17.92/17.49 ((((bnd_ndr1_0 & bnd_c4_1 bnd_a1367) &
% 17.92/17.49 (ALL X36.
% 17.92/17.49 bnd_ndr1_1 bnd_a1367 -->
% 17.92/17.49 (bnd_c3_2 bnd_a1367 X36 | ~ bnd_c1_2 bnd_a1367 X36) |
% 17.92/17.49 ~ bnd_c4_2 bnd_a1367 X36)) &
% 17.92/17.49 (ALL X37.
% 17.92/17.49 bnd_ndr1_1 bnd_a1367 -->
% 17.92/17.49 ~ bnd_c3_2 bnd_a1367 X37 | bnd_c5_2 bnd_a1367 X37) |
% 17.92/17.49 ~ bnd_c5_0) |
% 17.92/17.49 ~ bnd_c4_0)) &
% 17.92/17.49 ((~ bnd_c3_0 | ~ bnd_c2_0) | bnd_c1_0)) &
% 17.92/17.49 (bnd_c3_0 |
% 17.92/17.49 (((((bnd_ndr1_0 & bnd_c2_1 bnd_a1368) &
% 17.92/17.49 ~ bnd_c1_1 bnd_a1368) &
% 17.92/17.49 bnd_ndr1_1 bnd_a1368) &
% 17.92/17.49 ~ bnd_c4_2 bnd_a1368 bnd_a1369) &
% 17.92/17.49 ~ bnd_c3_2 bnd_a1368 bnd_a1369) &
% 17.92/17.49 bnd_c1_2 bnd_a1368 bnd_a1369)) &
% 17.92/17.49 (((ALL X38.
% 17.92/17.49 bnd_ndr1_0 -->
% 17.92/17.49 bnd_c4_1 X38 |
% 17.92/17.49 (ALL X39.
% 17.92/17.49 bnd_ndr1_1 X38 -->
% 17.92/17.49 (~ bnd_c4_2 X38 X39 | bnd_c2_2 X38 X39) | ~ bnd_c5_2 X38 X39)) |
% 17.92/17.49 bnd_c2_0) |
% 17.92/17.49 bnd_c1_0)) &
% 17.92/17.49 ((((bnd_ndr1_0 &
% 17.92/17.49 (ALL X40.
% 17.92/17.49 bnd_ndr1_1 bnd_a1370 -->
% 17.92/17.49 (~ bnd_c2_2 bnd_a1370 X40 |
% 17.92/17.49 ~ bnd_c3_2 bnd_a1370 X40) |
% 17.92/17.49 ~ bnd_c5_2 bnd_a1370 X40)) &
% 17.92/17.49 ~ bnd_c2_1 bnd_a1370) &
% 17.92/17.49 bnd_c4_1 bnd_a1370 |
% 17.92/17.49 (ALL X41.
% 17.92/17.49 bnd_ndr1_0 -->
% 17.92/17.49 (((bnd_ndr1_1 X41 &
% 17.92/17.49 ~ bnd_c1_2 X41 bnd_a1371) &
% 17.92/17.49 ~ bnd_c2_2 X41 bnd_a1371) &
% 17.92/17.49 bnd_c3_2 X41 bnd_a1371 |
% 17.92/17.49 bnd_c3_1 X41) |
% 17.92/17.49 ((bnd_ndr1_1 X41 &
% 17.92/17.49 bnd_c1_2 X41 bnd_a1372) &
% 17.92/17.49 ~ bnd_c2_2 X41 bnd_a1372) &
% 17.92/17.49 bnd_c5_2 X41 bnd_a1372)) |
% 17.92/17.49 ~ bnd_c5_0)) &
% 17.92/17.49 (((ALL X42.
% 17.92/17.49 bnd_ndr1_0 -->
% 17.92/17.49 ((ALL X43.
% 17.92/17.49 bnd_ndr1_1 X42 --> bnd_c5_2 X42 X43 | bnd_c4_2 X42 X43) |
% 17.92/17.49 (ALL X44.
% 17.92/17.49 bnd_ndr1_1 X42 -->
% 17.92/17.49 (bnd_c1_2 X42 X44 | bnd_c5_2 X42 X44) | ~ bnd_c3_2 X42 X44)) |
% 17.92/17.49 bnd_c4_1 X42) |
% 17.92/17.49 (ALL X45.
% 17.92/17.49 bnd_ndr1_0 -->
% 17.92/17.49 bnd_c5_1 X45 |
% 17.92/17.49 (ALL X46.
% 17.92/17.49 bnd_ndr1_1 X45 -->
% 17.92/17.49 (bnd_c2_2 X45 X46 |
% 17.92/17.49 ~ bnd_c1_2 X45 X46) |
% 17.92/17.49 bnd_c5_2 X45 X46))) |
% 17.92/17.49 bnd_c3_0)) &
% 17.92/17.49 ((bnd_c5_0 | bnd_c1_0) |
% 17.92/17.49 (ALL X47.
% 17.92/17.49 bnd_ndr1_0 -->
% 17.92/17.49 (((bnd_ndr1_1 X47 &
% 17.92/17.49 ~ bnd_c1_2 X47 bnd_a1373) &
% 17.92/17.49 bnd_c3_2 X47 bnd_a1373) &
% 17.92/17.49 bnd_c2_2 X47 bnd_a1373 |
% 17.92/17.49 ((bnd_ndr1_1 X47 &
% 17.92/17.49 ~ bnd_c1_2 X47 bnd_a1374) &
% 17.92/17.49 bnd_c4_2 X47 bnd_a1374) &
% 17.92/17.49 ~ bnd_c5_2 X47 bnd_a1374) |
% 17.92/17.49 bnd_c1_1 X47))) &
% 17.92/17.49 (((ALL X48.
% 17.92/17.49 bnd_ndr1_0 -->
% 17.92/17.49 (((bnd_ndr1_1 X48 & bnd_c3_2 X48 bnd_a1375) &
% 17.92/17.49 ~ bnd_c2_2 X48 bnd_a1375) &
% 17.92/17.49 bnd_c1_2 X48 bnd_a1375 |
% 17.92/17.49 (bnd_ndr1_1 X48 & bnd_c5_2 X48 bnd_a1376) &
% 17.92/17.49 ~ bnd_c2_2 X48 bnd_a1376) |
% 17.92/17.49 ((bnd_ndr1_1 X48 &
% 17.92/17.49 ~ bnd_c3_2 X48 bnd_a1377) &
% 17.92/17.49 bnd_c5_2 X48 bnd_a1377) &
% 17.92/17.49 ~ bnd_c2_2 X48 bnd_a1377) |
% 17.92/17.49 bnd_c2_0) |
% 17.92/17.49 (bnd_ndr1_0 &
% 17.92/17.49 (ALL X49.
% 17.92/17.49 bnd_ndr1_1 bnd_a1378 -->
% 17.92/17.49 bnd_c1_2 bnd_a1378 X49 |
% 17.92/17.49 bnd_c5_2 bnd_a1378 X49)) &
% 17.92/17.49 ~ bnd_c3_1 bnd_a1378)) &
% 17.92/17.49 (((ALL X50.
% 17.92/17.49 bnd_ndr1_0 -->
% 17.92/17.49 (~ bnd_c2_1 X50 | bnd_c5_1 X50) |
% 17.92/17.49 bnd_c3_1 X50) |
% 17.92/17.49 (ALL X51.
% 17.92/17.49 bnd_ndr1_0 -->
% 17.92/17.49 (((bnd_ndr1_1 X51 &
% 17.92/17.49 ~ bnd_c1_2 X51 bnd_a1379) &
% 17.92/17.49 ~ bnd_c5_2 X51 bnd_a1379) &
% 17.92/17.49 bnd_c2_2 X51 bnd_a1379 |
% 17.92/17.49 (ALL X52.
% 17.92/17.49 bnd_ndr1_1 X51 -->
% 17.92/17.49 (bnd_c4_2 X51 X52 | bnd_c5_2 X51 X52) |
% 17.92/17.49 bnd_c3_2 X51 X52)) |
% 17.92/17.49 bnd_c2_1 X51)) |
% 17.92/17.49 bnd_c4_0)) &
% 17.92/17.49 (~ bnd_c5_0 |
% 17.92/17.49 (bnd_ndr1_0 & ~ bnd_c3_1 bnd_a1380) &
% 17.92/17.49 (ALL X53.
% 17.92/17.49 bnd_ndr1_1 bnd_a1380 -->
% 17.92/17.49 (bnd_c1_2 bnd_a1380 X53 |
% 17.92/17.49 ~ bnd_c3_2 bnd_a1380 X53) |
% 17.92/17.49 ~ bnd_c5_2 bnd_a1380 X53))) &
% 17.92/17.49 (((ALL X54.
% 17.92/17.49 bnd_ndr1_0 -->
% 17.92/17.49 (((bnd_ndr1_1 X54 & bnd_c4_2 X54 bnd_a1381) &
% 17.92/17.49 bnd_c1_2 X54 bnd_a1381) &
% 17.92/17.49 bnd_c3_2 X54 bnd_a1381 |
% 17.92/17.49 ((bnd_ndr1_1 X54 & bnd_c2_2 X54 bnd_a1382) &
% 17.92/17.49 ~ bnd_c3_2 X54 bnd_a1382) &
% 17.92/17.49 ~ bnd_c4_2 X54 bnd_a1382) |
% 17.92/17.49 bnd_c2_1 X54) |
% 17.92/17.49 ~ bnd_c3_0) |
% 17.92/17.49 ~ bnd_c5_0)) &
% 17.92/17.49 ((bnd_c2_0 |
% 17.92/17.49 (ALL X55.
% 17.92/17.49 bnd_ndr1_0 -->
% 17.92/17.49 (bnd_ndr1_1 X55 & bnd_c5_2 X55 bnd_a1383) &
% 17.92/17.49 bnd_c1_2 X55 bnd_a1383 |
% 17.92/17.49 ~ bnd_c5_1 X55)) |
% 17.92/17.49 bnd_c3_0)) &
% 17.92/17.49 (~ bnd_c2_0 | ~ bnd_c3_0)) &
% 17.92/17.49 ((ALL X56.
% 17.92/17.49 bnd_ndr1_0 -->
% 17.92/17.49 (bnd_ndr1_1 X56 & bnd_c5_2 X56 bnd_a1384) &
% 17.92/17.49 bnd_c3_2 X56 bnd_a1384 |
% 17.92/17.49 bnd_c1_1 X56) |
% 17.92/17.49 ~ bnd_c2_0)) &
% 17.92/17.49 ((ALL X57.
% 17.92/17.49 bnd_ndr1_0 -->
% 17.92/17.49 (~ bnd_c5_1 X57 | ~ bnd_c2_1 X57) |
% 17.92/17.49 (ALL X58.
% 17.92/17.49 bnd_ndr1_1 X57 -->
% 17.92/17.49 (bnd_c2_2 X57 X58 | bnd_c3_2 X57 X58) |
% 17.92/17.49 bnd_c5_2 X57 X58)) |
% 17.92/17.49 ((((bnd_ndr1_0 & bnd_c4_1 bnd_a1385) &
% 17.92/17.49 ~ bnd_c2_1 bnd_a1385) &
% 17.92/17.49 bnd_ndr1_1 bnd_a1385) &
% 17.92/17.49 ~ bnd_c2_2 bnd_a1385 bnd_a1386) &
% 17.92/17.49 bnd_c5_2 bnd_a1385 bnd_a1386)) &
% 17.92/17.49 ((bnd_c3_0 | ~ bnd_c4_0) |
% 17.92/17.49 (ALL X59.
% 17.92/17.49 bnd_ndr1_0 -->
% 17.92/17.49 (((bnd_ndr1_1 X59 & ~ bnd_c5_2 X59 bnd_a1387) &
% 17.92/17.49 bnd_c1_2 X59 bnd_a1387) &
% 17.92/17.49 bnd_c2_2 X59 bnd_a1387 |
% 17.92/17.49 (ALL X60.
% 17.92/17.49 bnd_ndr1_1 X59 -->
% 17.92/17.49 ~ bnd_c5_2 X59 X60 | bnd_c3_2 X59 X60)) |
% 17.92/17.49 (ALL X61.
% 17.92/17.49 bnd_ndr1_1 X59 -->
% 17.92/17.49 bnd_c4_2 X59 X61 | bnd_c1_2 X59 X61)))) &
% 17.92/17.49 (((bnd_ndr1_0 &
% 17.92/17.49 (ALL X62.
% 17.92/17.49 bnd_ndr1_1 bnd_a1388 -->
% 17.92/17.49 ~ bnd_c2_2 bnd_a1388 X62 |
% 17.92/17.49 ~ bnd_c4_2 bnd_a1388 X62)) &
% 17.92/17.49 ~ bnd_c1_1 bnd_a1388 |
% 17.92/17.49 ~ bnd_c4_0) |
% 17.92/17.49 ((bnd_ndr1_0 & ~ bnd_c5_1 bnd_a1389) &
% 17.92/17.49 ~ bnd_c2_1 bnd_a1389) &
% 17.92/17.49 ~ bnd_c4_1 bnd_a1389)) &
% 17.92/17.49 ((bnd_c5_0 |
% 17.92/17.49 ((((bnd_ndr1_0 & bnd_c2_1 bnd_a1390) &
% 17.92/17.49 bnd_ndr1_1 bnd_a1390) &
% 17.92/17.49 ~ bnd_c4_2 bnd_a1390 bnd_a1391) &
% 17.92/17.49 bnd_c5_2 bnd_a1390 bnd_a1391) &
% 17.92/17.49 ~ bnd_c3_1 bnd_a1390) |
% 17.92/17.49 ~ bnd_c1_0)) &
% 17.92/17.49 ((((((((((bnd_ndr1_0 & ~ bnd_c3_1 bnd_a1392) &
% 17.92/17.49 bnd_ndr1_1 bnd_a1392) &
% 17.92/17.49 ~ bnd_c4_2 bnd_a1392 bnd_a1393) &
% 17.92/17.49 ~ bnd_c1_2 bnd_a1392 bnd_a1393) &
% 17.92/17.49 bnd_c3_2 bnd_a1392 bnd_a1393) &
% 17.92/17.49 bnd_ndr1_1 bnd_a1392) &
% 17.92/17.49 bnd_c5_2 bnd_a1392 bnd_a1394) &
% 17.92/17.49 ~ bnd_c2_2 bnd_a1392 bnd_a1394) &
% 17.92/17.49 bnd_c4_2 bnd_a1392 bnd_a1394 |
% 17.92/17.49 (ALL X63.
% 17.92/17.49 bnd_ndr1_0 -->
% 17.92/17.49 ((ALL X64.
% 17.92/17.49 bnd_ndr1_1 X63 -->
% 17.92/17.49 (~ bnd_c5_2 X63 X64 | ~ bnd_c2_2 X63 X64) |
% 17.92/17.49 bnd_c3_2 X63 X64) |
% 17.92/17.49 ~ bnd_c5_1 X63) |
% 17.92/17.49 ~ bnd_c1_1 X63)) |
% 17.92/17.49 bnd_c5_0)) &
% 17.92/17.49 (((ALL X65. bnd_ndr1_0 --> ~ bnd_c1_1 X65) |
% 17.92/17.49 (ALL X66.
% 17.92/17.49 bnd_ndr1_0 -->
% 17.92/17.49 ((ALL X67.
% 17.92/17.49 bnd_ndr1_1 X66 -->
% 17.92/17.49 (~ bnd_c2_2 X66 X67 | bnd_c3_2 X66 X67) |
% 17.92/17.49 bnd_c1_2 X66 X67) |
% 17.92/17.49 (ALL X68.
% 17.92/17.49 bnd_ndr1_1 X66 -->
% 17.92/17.49 bnd_c1_2 X66 X68 | bnd_c4_2 X66 X68)) |
% 17.92/17.49 ~ bnd_c2_1 X66)) |
% 17.92/17.49 (ALL X69.
% 17.92/17.49 bnd_ndr1_0 -->
% 17.92/17.49 ((bnd_ndr1_1 X69 & bnd_c3_2 X69 bnd_a1395) &
% 17.92/17.49 bnd_c2_2 X69 bnd_a1395 |
% 17.92/17.49 (ALL X70.
% 17.92/17.49 bnd_ndr1_1 X69 -->
% 17.92/17.49 bnd_c3_2 X69 X70 | bnd_c5_2 X69 X70)) |
% 17.92/17.49 ~ bnd_c3_1 X69))) &
% 17.92/17.49 (((ALL X71.
% 17.92/17.49 bnd_ndr1_0 -->
% 17.92/17.49 (((bnd_ndr1_1 X71 & bnd_c1_2 X71 bnd_a1396) &
% 17.92/17.49 ~ bnd_c2_2 X71 bnd_a1396) &
% 17.92/17.49 ~ bnd_c5_2 X71 bnd_a1396 |
% 17.92/17.49 ~ bnd_c1_1 X71) |
% 17.92/17.49 (ALL X72.
% 17.92/17.49 bnd_ndr1_1 X71 -->
% 17.92/17.49 ~ bnd_c4_2 X71 X72 | ~ bnd_c3_2 X71 X72)) |
% 17.92/17.49 (ALL X73.
% 17.92/17.49 bnd_ndr1_0 -->
% 17.92/17.49 (bnd_c1_1 X73 | bnd_c2_1 X73) | bnd_c5_1 X73)) |
% 17.92/17.49 (ALL X74.
% 17.92/17.49 bnd_ndr1_0 -->
% 17.92/17.49 (~ bnd_c5_1 X74 |
% 17.92/17.49 (ALL X75.
% 17.92/17.49 bnd_ndr1_1 X74 -->
% 17.92/17.49 (~ bnd_c4_2 X74 X75 | ~ bnd_c2_2 X74 X75) |
% 17.92/17.49 ~ bnd_c1_2 X74 X75)) |
% 17.92/17.49 (ALL X76.
% 17.92/17.49 bnd_ndr1_1 X74 -->
% 17.92/17.49 ~ bnd_c5_2 X74 X76 | ~ bnd_c3_2 X74 X76)))) &
% 17.92/17.49 ((bnd_c5_0 | ~ bnd_c2_0) | ~ bnd_c3_0)) &
% 17.92/17.49 (((ALL X77.
% 17.92/17.49 bnd_ndr1_0 -->
% 17.92/17.49 ((ALL X78.
% 17.92/17.49 bnd_ndr1_1 X77 -->
% 17.92/17.49 (bnd_c5_2 X77 X78 | ~ bnd_c2_2 X77 X78) |
% 17.92/17.49 bnd_c4_2 X77 X78) |
% 17.92/17.49 ~ bnd_c2_1 X77) |
% 17.92/17.49 ((bnd_ndr1_1 X77 & bnd_c2_2 X77 bnd_a1397) &
% 17.92/17.49 ~ bnd_c3_2 X77 bnd_a1397) &
% 17.92/17.49 ~ bnd_c1_2 X77 bnd_a1397) |
% 17.92/17.49 ~ bnd_c4_0) |
% 17.92/17.49 (ALL X79.
% 17.92/17.49 bnd_ndr1_0 -->
% 17.92/17.49 bnd_c1_1 X79 |
% 17.92/17.49 ((bnd_ndr1_1 X79 & ~ bnd_c1_2 X79 bnd_a1398) &
% 17.92/17.49 ~ bnd_c4_2 X79 bnd_a1398) &
% 17.92/17.49 ~ bnd_c5_2 X79 bnd_a1398))) &
% 17.92/17.49 (((ALL X80.
% 17.92/17.49 bnd_ndr1_0 -->
% 17.92/17.49 (~ bnd_c2_1 X80 | ~ bnd_c3_1 X80) |
% 17.92/17.49 (bnd_ndr1_1 X80 & bnd_c1_2 X80 bnd_a1399) &
% 17.92/17.49 ~ bnd_c5_2 X80 bnd_a1399) |
% 17.92/17.49 (((((bnd_ndr1_0 & bnd_c4_1 bnd_a1400) & bnd_c2_1 bnd_a1400) &
% 17.92/17.49 bnd_ndr1_1 bnd_a1400) &
% 17.92/17.49 ~ bnd_c1_2 bnd_a1400 bnd_a1401) &
% 17.92/17.49 bnd_c2_2 bnd_a1400 bnd_a1401) &
% 17.92/17.49 ~ bnd_c3_2 bnd_a1400 bnd_a1401) |
% 17.92/17.49 ~ bnd_c4_0)) &
% 17.92/17.49 ((~ bnd_c5_0 |
% 17.92/17.49 ((((((((bnd_ndr1_0 & bnd_c3_1 bnd_a1402) & bnd_ndr1_1 bnd_a1402) &
% 17.92/17.49 ~ bnd_c4_2 bnd_a1402 bnd_a1403) &
% 17.92/17.49 ~ bnd_c3_2 bnd_a1402 bnd_a1403) &
% 17.92/17.49 ~ bnd_c2_2 bnd_a1402 bnd_a1403) &
% 17.92/17.49 bnd_ndr1_1 bnd_a1402) &
% 17.92/17.49 bnd_c3_2 bnd_a1402 bnd_a1404) &
% 17.92/17.49 ~ bnd_c1_2 bnd_a1402 bnd_a1404) &
% 17.92/17.49 ~ bnd_c2_2 bnd_a1402 bnd_a1404) |
% 17.92/17.49 (ALL X81.
% 17.92/17.49 bnd_ndr1_0 -->
% 17.92/17.49 (~ bnd_c3_1 X81 |
% 17.92/17.49 (bnd_ndr1_1 X81 & ~ bnd_c4_2 X81 bnd_a1405) &
% 17.92/17.49 ~ bnd_c5_2 X81 bnd_a1405) |
% 17.92/17.49 bnd_c1_1 X81))) &
% 17.92/17.49 ((~ bnd_c4_0 |
% 17.92/17.49 ((((((((bnd_ndr1_0 & ~ bnd_c5_1 bnd_a1406) &
% 17.92/17.49 bnd_ndr1_1 bnd_a1406) &
% 17.92/17.49 bnd_c5_2 bnd_a1406 bnd_a1407) &
% 17.92/17.49 ~ bnd_c1_2 bnd_a1406 bnd_a1407) &
% 17.92/17.49 ~ bnd_c2_2 bnd_a1406 bnd_a1407) &
% 17.92/17.49 bnd_ndr1_1 bnd_a1406) &
% 17.92/17.49 ~ bnd_c2_2 bnd_a1406 bnd_a1408) &
% 17.92/17.49 ~ bnd_c1_2 bnd_a1406 bnd_a1408) &
% 17.92/17.49 bnd_c5_2 bnd_a1406 bnd_a1408) |
% 17.92/17.49 bnd_c2_0)) &
% 17.92/17.49 (bnd_c1_0 |
% 17.92/17.49 ((bnd_ndr1_0 & ~ bnd_c3_1 bnd_a1409) &
% 17.92/17.49 (ALL X82.
% 17.92/17.49 bnd_ndr1_1 bnd_a1409 -->
% 17.92/17.49 (~ bnd_c4_2 bnd_a1409 X82 | bnd_c1_2 bnd_a1409 X82) |
% 17.92/17.49 bnd_c2_2 bnd_a1409 X82)) &
% 17.92/17.49 (ALL X83.
% 17.92/17.49 bnd_ndr1_1 bnd_a1409 -->
% 17.92/17.49 (~ bnd_c5_2 bnd_a1409 X83 | ~ bnd_c1_2 bnd_a1409 X83) |
% 17.92/17.49 ~ bnd_c4_2 bnd_a1409 X83))) &
% 17.92/17.49 (bnd_c4_0 |
% 17.92/17.49 (ALL X84.
% 17.92/17.49 bnd_ndr1_0 -->
% 17.92/17.49 (~ bnd_c4_1 X84 | bnd_c2_1 X84) |
% 17.92/17.49 (bnd_ndr1_1 X84 & bnd_c5_2 X84 bnd_a1410) &
% 17.92/17.49 ~ bnd_c1_2 X84 bnd_a1410))) &
% 17.92/17.49 ((bnd_c3_0 |
% 17.92/17.49 (ALL X85.
% 17.92/17.49 bnd_ndr1_0 -->
% 17.92/17.49 ((bnd_ndr1_1 X85 & ~ bnd_c1_2 X85 bnd_a1411) &
% 17.92/17.49 bnd_c2_2 X85 bnd_a1411) &
% 17.92/17.49 ~ bnd_c4_2 X85 bnd_a1411 |
% 17.92/17.49 (ALL X86.
% 17.92/17.49 bnd_ndr1_1 X85 --> bnd_c1_2 X85 X86 | bnd_c3_2 X85 X86))) |
% 17.92/17.49 ((bnd_ndr1_0 & bnd_c4_1 bnd_a1412) &
% 17.92/17.49 (ALL X87.
% 17.92/17.49 bnd_ndr1_1 bnd_a1412 -->
% 17.92/17.49 (bnd_c1_2 bnd_a1412 X87 | bnd_c5_2 bnd_a1412 X87) |
% 17.92/17.49 ~ bnd_c3_2 bnd_a1412 X87)) &
% 17.92/17.49 ~ bnd_c5_1 bnd_a1412)) &
% 17.92/17.49 (((ALL X88.
% 17.92/17.49 bnd_ndr1_0 -->
% 17.92/17.49 (((bnd_ndr1_1 X88 & ~ bnd_c2_2 X88 bnd_a1413) &
% 17.92/17.49 bnd_c5_2 X88 bnd_a1413) &
% 17.92/17.49 bnd_c4_2 X88 bnd_a1413 |
% 17.92/17.49 bnd_c3_1 X88) |
% 17.92/17.49 (ALL X89.
% 17.92/17.49 bnd_ndr1_1 X88 -->
% 17.92/17.49 (~ bnd_c1_2 X88 X89 | bnd_c5_2 X88 X89) |
% 17.92/17.49 ~ bnd_c4_2 X88 X89)) |
% 17.92/17.49 (ALL X90.
% 17.92/17.49 bnd_ndr1_0 -->
% 17.92/17.49 (((bnd_ndr1_1 X90 & bnd_c2_2 X90 bnd_a1414) &
% 17.92/17.49 bnd_c4_2 X90 bnd_a1414) &
% 17.92/17.49 bnd_c5_2 X90 bnd_a1414 |
% 17.92/17.49 bnd_c3_1 X90) |
% 17.92/17.49 bnd_c2_1 X90)) |
% 17.92/17.49 bnd_c2_0)) &
% 17.92/17.49 ((~ bnd_c4_0 |
% 17.92/17.49 (ALL X91.
% 17.92/17.49 bnd_ndr1_0 -->
% 17.92/17.49 ((bnd_ndr1_1 X91 & bnd_c3_2 X91 bnd_a1415) &
% 17.92/17.49 ~ bnd_c4_2 X91 bnd_a1415 |
% 17.92/17.49 ~ bnd_c3_1 X91) |
% 17.92/17.49 ~ bnd_c2_1 X91)) |
% 17.92/17.49 ~ bnd_c5_0)) &
% 17.92/17.49 ((((bnd_ndr1_0 & ~ bnd_c2_1 bnd_a1416) & bnd_c3_1 bnd_a1416) &
% 17.92/17.49 bnd_c4_1 bnd_a1416 |
% 17.92/17.49 bnd_c1_0) |
% 17.92/17.49 ~ bnd_c2_0)) &
% 17.92/17.49 (bnd_c3_0 | ~ bnd_c2_0)) &
% 17.92/17.49 (((ALL X92.
% 17.92/17.49 bnd_ndr1_0 -->
% 17.92/17.49 (bnd_c4_1 X92 | ~ bnd_c2_1 X92) |
% 17.92/17.49 ((bnd_ndr1_1 X92 & ~ bnd_c2_2 X92 bnd_a1417) &
% 17.92/17.49 bnd_c1_2 X92 bnd_a1417) &
% 17.92/17.49 bnd_c3_2 X92 bnd_a1417) |
% 17.92/17.49 ((((bnd_ndr1_0 & bnd_c2_1 bnd_a1418) &
% 17.92/17.49 (ALL X93.
% 17.92/17.49 bnd_ndr1_1 bnd_a1418 -->
% 17.92/17.49 (~ bnd_c5_2 bnd_a1418 X93 | bnd_c1_2 bnd_a1418 X93) |
% 17.92/17.49 bnd_c4_2 bnd_a1418 X93)) &
% 17.92/17.49 bnd_ndr1_1 bnd_a1418) &
% 17.92/17.49 ~ bnd_c5_2 bnd_a1418 bnd_a1419) &
% 17.92/17.49 bnd_c4_2 bnd_a1418 bnd_a1419) |
% 17.92/17.49 ~ bnd_c5_0)) &
% 17.92/17.49 ((bnd_c4_0 | ~ bnd_c1_0) | bnd_c5_0)) &
% 17.92/17.49 ((bnd_c4_0 | ~ bnd_c5_0) |
% 17.92/17.49 ((((((((bnd_ndr1_0 &
% 17.92/17.49 bnd_ndr1_1 bnd_a1420) &
% 17.92/17.49 bnd_c3_2 bnd_a1420 bnd_a1421) &
% 17.92/17.49 ~ bnd_c5_2 bnd_a1420 bnd_a1421) &
% 17.92/17.49 bnd_c1_2 bnd_a1420 bnd_a1421) &
% 17.92/17.49 bnd_ndr1_1 bnd_a1420) &
% 17.92/17.49 ~ bnd_c5_2 bnd_a1420 bnd_a1422) &
% 17.92/17.49 bnd_c4_2 bnd_a1420 bnd_a1422) &
% 17.92/17.49 bnd_c3_2 bnd_a1420 bnd_a1422) &
% 17.92/17.49 (ALL X94.
% 17.92/17.49 bnd_ndr1_1 bnd_a1420 -->
% 17.92/17.49 (bnd_c1_2 bnd_a1420 X94 | ~ bnd_c4_2 bnd_a1420 X94) |
% 17.92/17.49 ~ bnd_c2_2 bnd_a1420 X94))) &
% 17.92/17.49 ((bnd_c5_0 | ~ bnd_c4_0) |
% 17.92/17.49 (bnd_ndr1_0 &
% 17.92/17.49 (ALL X95.
% 17.92/17.49 bnd_ndr1_1 bnd_a1423 -->
% 17.92/17.49 ~ bnd_c2_2 bnd_a1423 X95 | ~ bnd_c3_2 bnd_a1423 X95)) &
% 17.92/17.49 bnd_c1_1 bnd_a1423)) &
% 17.92/17.49 (((bnd_ndr1_0 & ~ bnd_c1_1 bnd_a1424) &
% 17.92/17.49 (ALL X96.
% 17.92/17.49 bnd_ndr1_1 bnd_a1424 -->
% 17.92/17.49 (~ bnd_c4_2 bnd_a1424 X96 | bnd_c1_2 bnd_a1424 X96) |
% 17.92/17.49 bnd_c3_2 bnd_a1424 X96)) &
% 17.92/17.49 bnd_c4_1 bnd_a1424 |
% 17.92/17.49 bnd_c2_0)) &
% 17.92/17.49 (~ bnd_c4_0 |
% 17.92/17.49 (ALL X97.
% 17.92/17.49 bnd_ndr1_0 -->
% 17.92/17.49 bnd_c2_1 X97 | ~ bnd_c3_1 X97))) &
% 17.92/17.49 ((bnd_c1_0 | ~ bnd_c4_0) |
% 17.92/17.49 ((((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a1425) &
% 17.92/17.49 ~ bnd_c3_2 bnd_a1425 bnd_a1426) &
% 17.92/17.49 ~ bnd_c2_2 bnd_a1425 bnd_a1426) &
% 17.92/17.49 ~ bnd_c1_2 bnd_a1425 bnd_a1426) &
% 17.92/17.49 bnd_ndr1_1 bnd_a1425) &
% 17.92/17.49 bnd_c4_2 bnd_a1425 bnd_a1427) &
% 17.92/17.49 ~ bnd_c5_2 bnd_a1425 bnd_a1427) &
% 17.92/17.49 ~ bnd_c1_2 bnd_a1425 bnd_a1427) &
% 17.92/17.49 (ALL X98.
% 17.92/17.49 bnd_ndr1_1 bnd_a1425 -->
% 17.92/17.49 (~ bnd_c3_2 bnd_a1425 X98 |
% 17.92/17.49 bnd_c5_2 bnd_a1425 X98) |
% 17.92/17.49 bnd_c2_2 bnd_a1425 X98))) &
% 17.92/17.49 (((((((bnd_ndr1_0 & bnd_c2_1 bnd_a1428) &
% 17.92/17.49 bnd_ndr1_1 bnd_a1428) &
% 17.92/17.49 bnd_c4_2 bnd_a1428 bnd_a1429) &
% 17.92/17.49 ~ bnd_c3_2 bnd_a1428 bnd_a1429) &
% 17.92/17.49 bnd_c2_2 bnd_a1428 bnd_a1429) &
% 17.92/17.49 (ALL X99.
% 17.92/17.49 bnd_ndr1_1 bnd_a1428 -->
% 17.92/17.49 bnd_c2_2 bnd_a1428 X99 |
% 17.92/17.49 ~ bnd_c1_2 bnd_a1428 X99) |
% 17.92/17.49 ((((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a1430) &
% 17.92/17.49 bnd_c1_2 bnd_a1430 bnd_a1431) &
% 17.92/17.49 bnd_c2_2 bnd_a1430 bnd_a1431) &
% 17.92/17.49 bnd_c5_2 bnd_a1430 bnd_a1431) &
% 17.92/17.49 bnd_c2_1 bnd_a1430) &
% 17.92/17.49 bnd_ndr1_1 bnd_a1430) &
% 17.92/17.49 ~ bnd_c1_2 bnd_a1430 bnd_a1432) &
% 17.92/17.49 ~ bnd_c4_2 bnd_a1430 bnd_a1432) &
% 17.92/17.49 ~ bnd_c2_2 bnd_a1430 bnd_a1432) |
% 17.92/17.49 (ALL X100.
% 17.92/17.49 bnd_ndr1_0 -->
% 17.92/17.49 ((bnd_ndr1_1 X100 &
% 17.92/17.49 ~ bnd_c3_2 X100 bnd_a1433) &
% 17.92/17.49 bnd_c5_2 X100 bnd_a1433) &
% 17.92/17.49 bnd_c2_2 X100 bnd_a1433 |
% 17.92/17.49 bnd_c3_1 X100))) &
% 17.92/17.49 (((bnd_ndr1_0 &
% 17.92/17.49 (ALL X101.
% 17.92/17.49 bnd_ndr1_1 bnd_a1434 -->
% 17.92/17.49 bnd_c4_2 bnd_a1434 X101 |
% 17.92/17.49 bnd_c1_2 bnd_a1434 X101)) &
% 17.92/17.49 bnd_c2_1 bnd_a1434) &
% 17.92/17.49 (ALL X102.
% 17.92/17.49 bnd_ndr1_1 bnd_a1434 -->
% 17.92/17.49 (bnd_c1_2 bnd_a1434 X102 |
% 17.92/17.49 bnd_c3_2 bnd_a1434 X102) |
% 17.92/17.49 bnd_c5_2 bnd_a1434 X102) |
% 17.92/17.49 (ALL X103.
% 17.92/17.49 bnd_ndr1_0 -->
% 17.92/17.49 ((bnd_ndr1_1 X103 &
% 17.92/17.49 ~ bnd_c4_2 X103 bnd_a1435) &
% 17.92/17.49 bnd_c2_2 X103 bnd_a1435 |
% 17.92/17.49 bnd_c2_1 X103) |
% 17.92/17.49 (ALL X104.
% 17.92/17.49 bnd_ndr1_1 X103 -->
% 17.92/17.49 (~ bnd_c4_2 X103 X104 | bnd_c5_2 X103 X104) | bnd_c3_2 X103 X104)))) &
% 17.92/17.49 ((bnd_c3_0 | bnd_c1_0) | ~ bnd_c5_0)) &
% 17.92/17.49 ((bnd_c5_0 | bnd_c4_0) |
% 17.92/17.49 (((((bnd_ndr1_0 &
% 17.92/17.49 (ALL X105.
% 17.92/17.49 bnd_ndr1_1 bnd_a1436 -->
% 17.92/17.49 (~ bnd_c2_2 bnd_a1436 X105 |
% 17.92/17.49 bnd_c1_2 bnd_a1436 X105) |
% 17.92/17.49 bnd_c4_2 bnd_a1436 X105)) &
% 17.92/17.49 bnd_ndr1_1 bnd_a1436) &
% 17.92/17.49 ~ bnd_c4_2 bnd_a1436 bnd_a1437) &
% 17.92/17.49 ~ bnd_c2_2 bnd_a1436 bnd_a1437) &
% 17.92/17.49 bnd_c1_2 bnd_a1436 bnd_a1437) &
% 17.92/17.49 (ALL X106.
% 17.92/17.49 bnd_ndr1_1 bnd_a1436 -->
% 17.92/17.49 (bnd_c3_2 bnd_a1436 X106 |
% 17.92/17.49 ~ bnd_c2_2 bnd_a1436 X106) |
% 17.92/17.49 bnd_c5_2 bnd_a1436 X106))) &
% 17.92/17.49 ((~ bnd_c3_0 |
% 17.92/17.49 (bnd_ndr1_0 &
% 17.92/17.49 (ALL X107.
% 17.92/17.49 bnd_ndr1_1 bnd_a1438 -->
% 17.92/17.49 (bnd_c2_2 bnd_a1438 X107 |
% 17.92/17.49 ~ bnd_c3_2 bnd_a1438 X107) |
% 17.92/17.49 ~ bnd_c5_2 bnd_a1438 X107)) &
% 17.92/17.49 bnd_c1_1 bnd_a1438) |
% 17.92/17.49 (((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a1439) &
% 17.92/17.49 ~ bnd_c4_2 bnd_a1439 bnd_a1440) &
% 17.92/17.49 ~ bnd_c3_2 bnd_a1439 bnd_a1440) &
% 17.92/17.49 bnd_ndr1_1 bnd_a1439) &
% 17.92/17.49 bnd_c1_2 bnd_a1439 bnd_a1441) &
% 17.92/17.49 bnd_c5_2 bnd_a1439 bnd_a1441) &
% 17.92/17.49 bnd_c3_2 bnd_a1439 bnd_a1441) &
% 17.92/17.49 bnd_c3_1 bnd_a1439)) &
% 17.92/17.49 (bnd_c1_0 | bnd_c3_0)) &
% 17.92/17.49 (((bnd_ndr1_0 &
% 17.92/17.49 (ALL X108.
% 17.92/17.49 bnd_ndr1_1 bnd_a1442 -->
% 17.92/17.49 (bnd_c3_2 bnd_a1442 X108 |
% 17.92/17.49 bnd_c4_2 bnd_a1442 X108) |
% 17.92/17.49 ~ bnd_c2_2 bnd_a1442 X108)) &
% 17.92/17.49 bnd_c3_1 bnd_a1442) &
% 17.92/17.49 bnd_c2_1 bnd_a1442 |
% 17.92/17.49 ~ bnd_c3_0)) &
% 17.92/17.49 (((ALL X109.
% 17.92/17.49 bnd_ndr1_0 -->
% 17.92/17.49 ((ALL X110.
% 17.92/17.49 bnd_ndr1_1 X109 -->
% 17.92/17.49 (bnd_c2_2 X109 X110 |
% 17.92/17.49 bnd_c5_2 X109 X110) |
% 17.92/17.49 ~ bnd_c4_2 X109 X110) |
% 17.92/17.49 (ALL X111.
% 17.92/17.49 bnd_ndr1_1 X109 -->
% 17.92/17.49 (~ bnd_c1_2 X109 X111 |
% 17.92/17.49 bnd_c2_2 X109 X111) |
% 17.92/17.49 ~ bnd_c4_2 X109 X111)) |
% 17.92/17.49 ~ bnd_c1_1 X109) |
% 17.92/17.49 bnd_c2_0) |
% 17.92/17.49 ((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a1443) &
% 17.92/17.49 bnd_c3_2 bnd_a1443 bnd_a1444) &
% 17.92/17.49 bnd_c1_2 bnd_a1443 bnd_a1444) &
% 17.92/17.49 ~ bnd_c4_2 bnd_a1443 bnd_a1444) &
% 17.92/17.49 ~ bnd_c3_1 bnd_a1443)) &
% 17.92/17.49 ~ bnd_c5_0) &
% 17.92/17.49 (((bnd_ndr1_0 & ~ bnd_c5_1 bnd_a1445) &
% 17.92/17.49 ~ bnd_c1_1 bnd_a1445 |
% 17.92/17.49 ~ bnd_c3_0) |
% 17.92/17.49 ~ bnd_c4_0)) &
% 17.92/17.49 (((bnd_ndr1_0 & ~ bnd_c5_1 bnd_a1446) &
% 17.92/17.49 ~ bnd_c3_1 bnd_a1446) &
% 17.92/17.49 (ALL X112.
% 17.92/17.49 bnd_ndr1_1 bnd_a1446 -->
% 17.92/17.49 (bnd_c3_2 bnd_a1446 X112 |
% 17.92/17.49 ~ bnd_c1_2 bnd_a1446 X112) |
% 17.92/17.49 ~ bnd_c5_2 bnd_a1446 X112) |
% 17.92/17.49 bnd_c1_0)) &
% 17.92/17.49 ((((((((((bnd_ndr1_0 & bnd_c2_1 bnd_a1447) &
% 17.92/17.49 bnd_ndr1_1 bnd_a1447) &
% 17.92/17.49 bnd_c5_2 bnd_a1447 bnd_a1448) &
% 17.92/17.49 bnd_c3_2 bnd_a1447 bnd_a1448) &
% 17.92/17.49 ~ bnd_c1_2 bnd_a1447 bnd_a1448) &
% 17.92/17.49 bnd_ndr1_1 bnd_a1447) &
% 17.92/17.49 ~ bnd_c5_2 bnd_a1447 bnd_a1449) &
% 17.92/17.49 ~ bnd_c3_2 bnd_a1447 bnd_a1449) &
% 17.92/17.49 ~ bnd_c4_2 bnd_a1447 bnd_a1449 |
% 17.92/17.49 ~ bnd_c4_0) |
% 17.92/17.49 (bnd_ndr1_0 & bnd_ndr1_1 bnd_a1450) &
% 17.92/17.49 ~ bnd_c5_2 bnd_a1450 bnd_a1451)) &
% 17.92/17.49 (((((bnd_ndr1_0 & ~ bnd_c5_1 bnd_a1452) &
% 17.92/17.49 bnd_ndr1_1 bnd_a1452) &
% 17.92/17.49 bnd_c2_2 bnd_a1452 bnd_a1453) &
% 17.92/17.49 ~ bnd_c1_2 bnd_a1452 bnd_a1453 |
% 17.92/17.49 bnd_c2_0) |
% 17.92/17.49 ~ bnd_c3_0)) &
% 17.92/17.49 (((bnd_ndr1_0 & ~ bnd_c5_1 bnd_a1454) &
% 17.92/17.49 bnd_c2_1 bnd_a1454 |
% 17.92/17.49 ((((((((bnd_ndr1_0 & bnd_c1_1 bnd_a1455) &
% 17.92/17.49 bnd_ndr1_1 bnd_a1455) &
% 17.92/17.49 ~ bnd_c3_2 bnd_a1455 bnd_a1456) &
% 17.92/17.49 bnd_c2_2 bnd_a1455 bnd_a1456) &
% 17.92/17.49 ~ bnd_c4_2 bnd_a1455 bnd_a1456) &
% 17.92/17.49 bnd_ndr1_1 bnd_a1455) &
% 17.92/17.49 bnd_c5_2 bnd_a1455 bnd_a1457) &
% 17.92/17.49 bnd_c3_2 bnd_a1455 bnd_a1457) &
% 17.92/17.49 ~ bnd_c2_2 bnd_a1455 bnd_a1457) |
% 17.92/17.49 bnd_c4_0)) &
% 17.92/17.49 bnd_ndr1_0) &
% 17.92/17.49 (ALL X113.
% 17.92/17.49 bnd_ndr1_1 bnd_a1458 -->
% 17.92/17.49 bnd_c1_2 bnd_a1458 X113 | ~ bnd_c4_2 bnd_a1458 X113)) &
% 17.92/17.49 (ALL X114.
% 17.92/17.49 bnd_ndr1_1 bnd_a1458 -->
% 17.92/17.49 bnd_c3_2 bnd_a1458 X114 | bnd_c2_2 bnd_a1458 X114)) &
% 17.92/17.49 bnd_c2_1 bnd_a1458) &
% 17.92/17.49 ((ALL X115.
% 17.92/17.49 bnd_ndr1_0 -->
% 17.92/17.49 (bnd_c1_1 X115 |
% 17.92/17.49 (ALL X116.
% 17.92/17.49 bnd_ndr1_1 X115 -->
% 17.92/17.49 (~ bnd_c2_2 X115 X116 | bnd_c4_2 X115 X116) |
% 17.92/17.49 ~ bnd_c3_2 X115 X116)) |
% 17.92/17.49 ((bnd_ndr1_1 X115 & bnd_c4_2 X115 bnd_a1459) &
% 17.92/17.49 ~ bnd_c3_2 X115 bnd_a1459) &
% 17.92/17.49 ~ bnd_c1_2 X115 bnd_a1459) |
% 17.92/17.49 bnd_c4_0)) &
% 17.92/17.49 ((~ bnd_c4_0 |
% 17.92/17.49 ((((bnd_ndr1_0 & bnd_c5_1 bnd_a1460) & bnd_ndr1_1 bnd_a1460) &
% 17.92/17.49 ~ bnd_c2_2 bnd_a1460 bnd_a1461) &
% 17.92/17.49 bnd_c3_2 bnd_a1460 bnd_a1461) &
% 17.92/17.49 ~ bnd_c4_2 bnd_a1460 bnd_a1461) |
% 17.92/17.49 (ALL X117.
% 17.92/17.49 bnd_ndr1_0 -->
% 17.92/17.49 (bnd_c4_1 X117 |
% 17.92/17.49 (bnd_ndr1_1 X117 & bnd_c4_2 X117 bnd_a1462) &
% 17.92/17.49 ~ bnd_c3_2 X117 bnd_a1462) |
% 17.92/17.49 ((bnd_ndr1_1 X117 & ~ bnd_c2_2 X117 bnd_a1463) &
% 17.92/17.49 bnd_c4_2 X117 bnd_a1463) &
% 17.92/17.49 ~ bnd_c3_2 X117 bnd_a1463))) &
% 17.92/17.49 bnd_ndr1_0) &
% 17.92/17.49 bnd_ndr1_1 bnd_a1464) &
% 17.92/17.49 ~ bnd_c5_2 bnd_a1464 bnd_a1465) &
% 17.92/17.49 bnd_c3_2 bnd_a1464 bnd_a1465) &
% 17.92/17.49 bnd_c2_2 bnd_a1464 bnd_a1465) &
% 17.92/17.49 bnd_c2_1 bnd_a1464) &
% 17.92/17.49 bnd_ndr1_1 bnd_a1464) &
% 17.92/17.49 bnd_c2_2 bnd_a1464 bnd_a1466) &
% 17.92/17.49 ~ bnd_c5_2 bnd_a1464 bnd_a1466) &
% 17.92/17.49 ((~ bnd_c3_0 | ~ bnd_c1_0) |
% 17.92/17.49 ((((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a1467) &
% 17.92/17.49 ~ bnd_c5_2 bnd_a1467 bnd_a1468) &
% 17.92/17.49 bnd_c3_2 bnd_a1467 bnd_a1468) &
% 17.92/17.49 bnd_c1_2 bnd_a1467 bnd_a1468) &
% 17.92/17.49 bnd_ndr1_1 bnd_a1467) &
% 17.92/17.49 ~ bnd_c4_2 bnd_a1467 bnd_a1469) &
% 17.92/17.49 bnd_c3_2 bnd_a1467 bnd_a1469) &
% 17.92/17.49 bnd_c1_2 bnd_a1467 bnd_a1469) &
% 17.92/17.49 bnd_c3_1 bnd_a1467)) &
% 17.92/17.49 (((ALL X118.
% 17.92/17.49 bnd_ndr1_0 -->
% 17.92/17.49 (~ bnd_c5_1 X118 | bnd_c1_1 X118) |
% 17.92/17.49 (ALL X119.
% 17.92/17.49 bnd_ndr1_1 X118 -->
% 17.92/17.49 (bnd_c4_2 X118 X119 | ~ bnd_c2_2 X118 X119) |
% 17.92/17.49 bnd_c3_2 X118 X119)) |
% 17.92/17.49 (((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a1470) &
% 17.92/17.49 bnd_c4_2 bnd_a1470 bnd_a1471) &
% 17.92/17.49 ~ bnd_c5_2 bnd_a1470 bnd_a1471) &
% 17.92/17.49 bnd_c2_2 bnd_a1470 bnd_a1471) &
% 17.92/17.49 bnd_ndr1_1 bnd_a1470) &
% 17.92/17.49 bnd_c5_2 bnd_a1470 bnd_a1472) &
% 17.92/17.49 bnd_c1_2 bnd_a1470 bnd_a1472) &
% 17.92/17.49 bnd_c3_2 bnd_a1470 bnd_a1472) |
% 17.92/17.49 ~ bnd_c3_0)) &
% 17.92/17.49 ((~ bnd_c2_0 |
% 17.92/17.49 (ALL X120.
% 17.92/17.49 bnd_ndr1_0 -->
% 17.92/17.49 (((bnd_ndr1_1 X120 & bnd_c3_2 X120 bnd_a1473) &
% 17.92/17.49 ~ bnd_c5_2 X120 bnd_a1473) &
% 17.92/17.49 bnd_c2_2 X120 bnd_a1473 |
% 17.92/17.49 ~ bnd_c4_1 X120) |
% 17.92/17.49 (ALL X121.
% 17.92/17.49 bnd_ndr1_1 X120 -->
% 17.92/17.49 ~ bnd_c1_2 X120 X121 | ~ bnd_c2_2 X120 X121))) |
% 17.92/17.49 (ALL X122.
% 17.92/17.49 bnd_ndr1_0 -->
% 17.92/17.49 ((ALL X123.
% 17.92/17.49 bnd_ndr1_1 X122 --> ~ bnd_c3_2 X122 X123 | bnd_c5_2 X122 X123) |
% 17.92/17.49 ((bnd_ndr1_1 X122 & bnd_c2_2 X122 bnd_a1474) &
% 17.92/17.49 bnd_c5_2 X122 bnd_a1474) &
% 17.92/17.49 bnd_c4_2 X122 bnd_a1474) |
% 17.92/17.49 bnd_c5_1 X122))) &
% 17.92/17.49 ((bnd_c4_0 | bnd_c1_0) | ~ bnd_c2_0)) &
% 17.92/17.49 (((bnd_ndr1_0 &
% 17.92/17.49 (ALL X124.
% 17.92/17.49 bnd_ndr1_1 bnd_a1475 -->
% 17.92/17.49 bnd_c5_2 bnd_a1475 X124 | bnd_c2_2 bnd_a1475 X124)) &
% 17.92/17.49 bnd_c4_1 bnd_a1475) &
% 17.92/17.49 ~ bnd_c5_1 bnd_a1475 |
% 17.92/17.49 bnd_c4_0)) &
% 17.92/17.49 bnd_c3_0) &
% 17.92/17.49 ((ALL X125.
% 17.92/17.49 bnd_ndr1_0 -->
% 17.92/17.49 (~ bnd_c3_1 X125 |
% 17.92/17.49 (ALL X126. bnd_ndr1_1 X125 --> bnd_c5_2 X125 X126 | bnd_c3_2 X125 X126)) |
% 17.92/17.49 ((bnd_ndr1_1 X125 & ~ bnd_c4_2 X125 bnd_a1476) &
% 17.92/17.49 ~ bnd_c2_2 X125 bnd_a1476) &
% 17.92/17.49 ~ bnd_c1_2 X125 bnd_a1476) |
% 17.92/17.49 ~ bnd_c4_0)) &
% 17.92/17.49 (((ALL X127.
% 17.92/17.49 bnd_ndr1_0 -->
% 17.92/17.49 (((bnd_ndr1_1 X127 & bnd_c2_2 X127 bnd_a1477) & ~ bnd_c3_2 X127 bnd_a1477) &
% 17.92/17.49 ~ bnd_c4_2 X127 bnd_a1477 |
% 17.92/17.49 ~ bnd_c1_1 X127) |
% 17.92/17.49 bnd_c5_1 X127) |
% 17.92/17.49 (((((bnd_ndr1_0 &
% 17.92/17.49 (ALL X128.
% 17.92/17.49 bnd_ndr1_1 bnd_a1478 -->
% 17.92/17.49 (bnd_c4_2 bnd_a1478 X128 | bnd_c2_2 bnd_a1478 X128) |
% 17.92/17.49 ~ bnd_c1_2 bnd_a1478 X128)) &
% 17.92/17.49 (ALL X129.
% 17.92/17.49 bnd_ndr1_1 bnd_a1478 -->
% 17.92/17.49 (~ bnd_c1_2 bnd_a1478 X129 | bnd_c3_2 bnd_a1478 X129) |
% 17.92/17.49 bnd_c5_2 bnd_a1478 X129)) &
% 17.92/17.49 bnd_ndr1_1 bnd_a1478) &
% 17.92/17.49 bnd_c5_2 bnd_a1478 bnd_a1479) &
% 17.92/17.49 ~ bnd_c4_2 bnd_a1478 bnd_a1479) &
% 17.92/17.49 bnd_c1_2 bnd_a1478 bnd_a1479) |
% 17.92/17.49 ~ bnd_c2_0)) &
% 17.92/17.49 ((bnd_c1_0 |
% 17.92/17.49 (ALL X130.
% 17.92/17.49 bnd_ndr1_0 -->
% 17.92/17.49 ((bnd_ndr1_1 X130 &
% 17.92/17.49 ~ bnd_c3_2 X130 bnd_a1480) &
% 17.92/17.49 bnd_c4_2 X130 bnd_a1480) &
% 17.92/17.49 ~ bnd_c5_2 X130 bnd_a1480 |
% 17.92/17.49 (bnd_ndr1_1 X130 &
% 17.92/17.49 bnd_c1_2 X130 bnd_a1481) &
% 17.92/17.49 ~ bnd_c2_2 X130 bnd_a1481)) |
% 17.92/17.49 (bnd_ndr1_0 & ~ bnd_c5_1 bnd_a1482) &
% 17.92/17.49 (ALL X131.
% 17.92/17.49 bnd_ndr1_1 bnd_a1482 -->
% 17.92/17.49 (bnd_c3_2 bnd_a1482 X131 |
% 17.92/17.49 ~ bnd_c1_2 bnd_a1482 X131) |
% 17.92/17.49 ~ bnd_c5_2 bnd_a1482 X131))) &
% 17.92/17.49 ((((bnd_ndr1_0 &
% 17.92/17.49 (ALL X132.
% 17.92/17.49 bnd_ndr1_1 bnd_a1483 -->
% 17.92/17.49 (bnd_c3_2 bnd_a1483 X132 | ~ bnd_c2_2 bnd_a1483 X132) |
% 17.92/17.49 bnd_c4_2 bnd_a1483 X132)) &
% 17.92/17.49 ~ bnd_c3_1 bnd_a1483) &
% 17.92/17.49 bnd_c1_1 bnd_a1483 |
% 17.92/17.49 ((((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a1484) &
% 17.92/17.49 bnd_c1_2 bnd_a1484 bnd_a1485) &
% 17.92/17.49 ~ bnd_c3_2 bnd_a1484 bnd_a1485) &
% 17.92/17.49 bnd_c4_2 bnd_a1484 bnd_a1485) &
% 17.92/17.49 ~ bnd_c1_1 bnd_a1484) &
% 17.92/17.49 bnd_ndr1_1 bnd_a1484) &
% 17.92/17.49 bnd_c5_2 bnd_a1484 bnd_a1486) &
% 17.92/17.49 bnd_c2_2 bnd_a1484 bnd_a1486) &
% 17.92/17.49 ~ bnd_c1_2 bnd_a1484 bnd_a1486) |
% 17.92/17.49 (((((bnd_ndr1_0 & bnd_c3_1 bnd_a1487) &
% 17.92/17.49 bnd_c1_1 bnd_a1487) &
% 17.92/17.49 bnd_ndr1_1 bnd_a1487) &
% 17.92/17.49 bnd_c2_2 bnd_a1487 bnd_a1488) &
% 17.92/17.49 bnd_c4_2 bnd_a1487 bnd_a1488) &
% 17.92/17.49 bnd_c5_2 bnd_a1487 bnd_a1488)) &
% 17.92/17.49 (~ bnd_c1_0 | ~ bnd_c2_0)) &
% 17.92/17.49 (ALL X133.
% 17.92/17.49 bnd_ndr1_0 -->
% 17.92/17.49 ((bnd_ndr1_1 X133 &
% 17.92/17.49 ~ bnd_c1_2 X133 bnd_a1489) &
% 17.92/17.49 bnd_c3_2 X133 bnd_a1489 |
% 17.92/17.49 (ALL X134.
% 17.92/17.49 bnd_ndr1_1 X133 -->
% 17.92/17.49 ~ bnd_c5_2 X133 X134 |
% 17.92/17.49 bnd_c4_2 X133 X134)) |
% 17.92/17.49 bnd_c4_1 X133)) &
% 17.92/17.49 (((bnd_ndr1_0 &
% 17.92/17.49 (ALL X135.
% 17.92/17.49 bnd_ndr1_1 bnd_a1490 -->
% 17.92/17.49 ~ bnd_c2_2 bnd_a1490 X135 |
% 17.92/17.49 ~ bnd_c5_2 bnd_a1490 X135)) &
% 17.92/17.49 (ALL X136.
% 17.92/17.49 bnd_ndr1_1 bnd_a1490 -->
% 17.92/17.49 (bnd_c1_2 bnd_a1490 X136 |
% 17.92/17.49 ~ bnd_c5_2 bnd_a1490 X136) |
% 17.92/17.49 bnd_c2_2 bnd_a1490 X136) |
% 17.92/17.49 (ALL X137.
% 17.92/17.49 bnd_ndr1_0 -->
% 17.92/17.49 (bnd_ndr1_1 X137 &
% 17.92/17.49 ~ bnd_c5_2 X137 bnd_a1491) &
% 17.92/17.49 ~ bnd_c1_2 X137 bnd_a1491 |
% 17.92/17.49 ~ bnd_c2_1 X137)) |
% 17.92/17.49 (ALL X138.
% 17.92/17.49 bnd_ndr1_0 -->
% 17.92/17.49 ~ bnd_c3_1 X138 |
% 17.92/17.49 (ALL X139.
% 17.92/17.49 bnd_ndr1_1 X138 -->
% 17.92/17.49 (bnd_c4_2 X138 X139 |
% 17.92/17.49 bnd_c5_2 X138 X139) |
% 17.92/17.49 bnd_c3_2 X138 X139)))) &
% 17.92/17.49 (((ALL X140.
% 17.92/17.49 bnd_ndr1_0 -->
% 17.92/17.49 (((bnd_ndr1_1 X140 &
% 17.92/17.49 bnd_c5_2 X140 bnd_a1492) &
% 17.92/17.49 bnd_c3_2 X140 bnd_a1492) &
% 17.92/17.49 ~ bnd_c4_2 X140 bnd_a1492 |
% 17.92/17.49 (ALL X141.
% 17.92/17.49 bnd_ndr1_1 X140 -->
% 17.92/17.49 (bnd_c5_2 X140 X141 |
% 17.92/17.49 bnd_c1_2 X140 X141) |
% 17.92/17.49 bnd_c2_2 X140 X141)) |
% 17.92/17.49 bnd_c1_1 X140) |
% 17.92/17.49 bnd_c1_0) |
% 17.92/17.49 (bnd_ndr1_0 &
% 17.92/17.49 (ALL X142.
% 17.92/17.49 bnd_ndr1_1 bnd_a1493 -->
% 17.92/17.49 bnd_c2_2 bnd_a1493 X142 |
% 17.92/17.49 bnd_c1_2 bnd_a1493 X142)) &
% 17.92/17.49 ~ bnd_c2_1 bnd_a1493)) &
% 17.92/17.49 bnd_ndr1_0) &
% 17.92/17.49 (ALL X143.
% 17.92/17.49 bnd_ndr1_1 bnd_a1494 -->
% 17.92/17.49 (bnd_c1_2 bnd_a1494 X143 |
% 17.92/17.49 ~ bnd_c2_2 bnd_a1494 X143) |
% 17.92/17.49 bnd_c3_2 bnd_a1494 X143)) &
% 17.92/17.49 (ALL X144.
% 17.92/17.49 bnd_ndr1_1 bnd_a1494 -->
% 17.92/17.49 (~ bnd_c5_2 bnd_a1494 X144 |
% 17.92/17.49 bnd_c3_2 bnd_a1494 X144) |
% 17.92/17.49 bnd_c1_2 bnd_a1494 X144)) &
% 17.92/17.49 bnd_c5_1 bnd_a1494) &
% 17.92/17.49 (((((((bnd_ndr1_0 &
% 17.92/17.49 (ALL X145.
% 17.92/17.49 bnd_ndr1_1 bnd_a1495 -->
% 17.92/17.49 bnd_c1_2 bnd_a1495 X145 |
% 17.92/17.49 ~ bnd_c5_2 bnd_a1495 X145)) &
% 17.92/17.49 bnd_ndr1_1 bnd_a1495) &
% 17.92/17.49 bnd_c1_2 bnd_a1495 bnd_a1496) &
% 17.92/17.49 ~ bnd_c5_2 bnd_a1495 bnd_a1496) &
% 17.92/17.49 bnd_c2_2 bnd_a1495 bnd_a1496) &
% 17.92/17.49 bnd_c2_1 bnd_a1495 |
% 17.92/17.49 (ALL X146.
% 17.92/17.49 bnd_ndr1_0 -->
% 17.92/17.49 bnd_c4_1 X146 |
% 17.92/17.49 ((bnd_ndr1_1 X146 & bnd_c4_2 X146 bnd_a1497) &
% 17.92/17.49 bnd_c5_2 X146 bnd_a1497) &
% 17.92/17.49 bnd_c2_2 X146 bnd_a1497)) |
% 17.92/17.49 (ALL X147.
% 17.92/17.49 bnd_ndr1_0 -->
% 17.92/17.49 (~ bnd_c3_1 X147 |
% 17.92/17.49 (ALL X148.
% 17.92/17.49 bnd_ndr1_1 X147 -->
% 17.92/17.49 (~ bnd_c2_2 X147 X148 |
% 17.92/17.49 ~ bnd_c5_2 X147 X148) |
% 17.92/17.49 bnd_c3_2 X147 X148)) |
% 17.92/17.49 bnd_c5_1 X147))) &
% 17.92/17.49 ((bnd_c2_0 |
% 17.92/17.49 ((bnd_ndr1_0 &
% 17.92/17.49 (ALL X149.
% 17.92/17.49 bnd_ndr1_1 bnd_a1498 -->
% 17.92/17.49 ~ bnd_c4_2 bnd_a1498 X149 |
% 17.92/17.49 bnd_c5_2 bnd_a1498 X149)) &
% 17.92/17.49 ~ bnd_c5_1 bnd_a1498) &
% 17.92/17.49 (ALL X150.
% 17.92/17.49 bnd_ndr1_1 bnd_a1498 -->
% 17.92/17.49 (bnd_c5_2 bnd_a1498 X150 |
% 17.92/17.49 bnd_c4_2 bnd_a1498 X150) |
% 17.92/17.49 bnd_c1_2 bnd_a1498 X150)) |
% 17.92/17.49 bnd_c4_0)) &
% 17.92/17.49 ((((bnd_ndr1_0 & ~ bnd_c3_1 bnd_a1499) &
% 17.92/17.49 ~ bnd_c5_1 bnd_a1499) &
% 17.92/17.49 (ALL X151.
% 17.92/17.49 bnd_ndr1_1 bnd_a1499 -->
% 17.92/17.49 ~ bnd_c1_2 bnd_a1499 X151 |
% 17.92/17.49 bnd_c5_2 bnd_a1499 X151) |
% 17.92/17.49 (((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a1500) &
% 17.92/17.49 ~ bnd_c4_2 bnd_a1500 bnd_a1501) &
% 17.92/17.49 ~ bnd_c3_2 bnd_a1500 bnd_a1501) &
% 17.92/17.49 bnd_c2_2 bnd_a1500 bnd_a1501) &
% 17.92/17.49 bnd_ndr1_1 bnd_a1500) &
% 17.92/17.49 ~ bnd_c4_2 bnd_a1500 bnd_a1502) &
% 17.92/17.49 bnd_c3_2 bnd_a1500 bnd_a1502) &
% 17.92/17.49 bnd_c2_2 bnd_a1500 bnd_a1502) |
% 17.92/17.49 ((bnd_ndr1_0 & ~ bnd_c5_1 bnd_a1503) &
% 17.92/17.49 (ALL X152.
% 17.92/17.49 bnd_ndr1_1 bnd_a1503 -->
% 17.92/17.49 (bnd_c5_2 bnd_a1503 X152 |
% 17.92/17.49 ~ bnd_c2_2 bnd_a1503 X152) |
% 17.92/17.49 ~ bnd_c1_2 bnd_a1503 X152)) &
% 17.92/17.49 ~ bnd_c3_1 bnd_a1503)) &
% 17.92/17.49 (((ALL X153.
% 17.92/17.49 bnd_ndr1_0 -->
% 17.92/17.49 ((ALL X154.
% 17.92/17.49 bnd_ndr1_1 X153 -->
% 17.92/17.49 (bnd_c1_2 X153 X154 | ~ bnd_c4_2 X153 X154) |
% 17.92/17.49 bnd_c3_2 X153 X154) |
% 17.92/17.49 bnd_c2_1 X153) |
% 17.92/17.49 ~ bnd_c3_1 X153) |
% 17.92/17.49 bnd_c1_0) |
% 17.92/17.49 ((bnd_ndr1_0 & ~ bnd_c1_1 bnd_a1504) &
% 17.92/17.49 ~ bnd_c4_1 bnd_a1504) &
% 17.92/17.49 (ALL X155.
% 17.92/17.49 bnd_ndr1_1 bnd_a1504 -->
% 17.92/17.49 (~ bnd_c3_2 bnd_a1504 X155 |
% 17.92/17.49 bnd_c5_2 bnd_a1504 X155) |
% 17.92/17.49 ~ bnd_c4_2 bnd_a1504 X155))) &
% 17.92/17.49 (bnd_c2_0 |
% 17.92/17.49 (ALL X156.
% 17.92/17.49 bnd_ndr1_0 -->
% 17.92/17.49 ((bnd_ndr1_1 X156 & bnd_c2_2 X156 bnd_a1505) &
% 17.92/17.49 ~ bnd_c4_2 X156 bnd_a1505) &
% 17.92/17.49 bnd_c3_2 X156 bnd_a1505 |
% 17.92/17.49 (ALL X157.
% 17.92/17.49 bnd_ndr1_1 X156 -->
% 17.92/17.49 (~ bnd_c5_2 X156 X157 | ~ bnd_c1_2 X156 X157) |
% 17.92/17.49 ~ bnd_c2_2 X156 X157)))) &
% 17.92/17.49 ((bnd_c1_0 | ~ bnd_c2_0) | ~ bnd_c4_0)) &
% 17.92/17.49 (~ bnd_c1_0 |
% 17.92/17.49 ((((bnd_ndr1_0 &
% 17.92/17.49 (ALL X158.
% 17.92/17.49 bnd_ndr1_1 bnd_a1506 -->
% 17.92/17.49 (~ bnd_c1_2 bnd_a1506 X158 |
% 17.92/17.49 bnd_c3_2 bnd_a1506 X158) |
% 17.92/17.49 ~ bnd_c4_2 bnd_a1506 X158)) &
% 17.92/17.49 ~ bnd_c1_1 bnd_a1506) &
% 17.92/17.49 bnd_ndr1_1 bnd_a1506) &
% 17.92/17.49 bnd_c4_2 bnd_a1506 bnd_a1507) &
% 17.92/17.49 ~ bnd_c2_2 bnd_a1506 bnd_a1507)) &
% 17.92/17.49 (bnd_c4_0 | ~ bnd_c2_0)) &
% 17.92/17.49 ((bnd_ndr1_0 & ~ bnd_c3_1 bnd_a1508 |
% 17.92/17.49 (ALL X159. bnd_ndr1_0 --> bnd_c1_1 X159 | bnd_c5_1 X159)) |
% 17.92/17.49 ~ bnd_c1_0)) &
% 17.92/17.49 (((bnd_ndr1_0 &
% 17.92/17.49 (ALL X160.
% 17.92/17.49 bnd_ndr1_1 bnd_a1509 -->
% 17.92/17.49 bnd_c2_2 bnd_a1509 X160 | ~ bnd_c3_2 bnd_a1509 X160)) &
% 17.92/17.49 bnd_c1_1 bnd_a1509) &
% 17.92/17.49 (ALL X161.
% 17.92/17.49 bnd_ndr1_1 bnd_a1509 -->
% 17.92/17.49 (bnd_c1_2 bnd_a1509 X161 | bnd_c3_2 bnd_a1509 X161) |
% 17.92/17.49 bnd_c2_2 bnd_a1509 X161) |
% 17.92/17.49 ~ bnd_c1_0)) &
% 17.92/17.49 (((((bnd_ndr1_0 & bnd_c5_1 bnd_a1510) & bnd_ndr1_1 bnd_a1510) &
% 17.92/17.49 ~ bnd_c2_2 bnd_a1510 bnd_a1511) &
% 17.92/17.49 ~ bnd_c1_2 bnd_a1510 bnd_a1511) &
% 17.92/17.49 ~ bnd_c5_2 bnd_a1510 bnd_a1511 |
% 17.92/17.49 (ALL X162.
% 17.92/17.49 bnd_ndr1_0 -->
% 17.92/17.49 (~ bnd_c3_1 X162 | bnd_c5_1 X162) | ~ bnd_c1_1 X162))) &
% 17.92/17.49 ((~ bnd_c1_0 |
% 17.92/17.49 (ALL X163.
% 17.92/17.49 bnd_ndr1_0 -->
% 17.92/17.49 (((bnd_ndr1_1 X163 & ~ bnd_c2_2 X163 bnd_a1512) &
% 17.92/17.49 ~ bnd_c1_2 X163 bnd_a1512) &
% 17.92/17.49 ~ bnd_c5_2 X163 bnd_a1512 |
% 17.92/17.49 ((bnd_ndr1_1 X163 & bnd_c4_2 X163 bnd_a1513) &
% 17.92/17.49 ~ bnd_c1_2 X163 bnd_a1513) &
% 17.92/17.49 bnd_c2_2 X163 bnd_a1513) |
% 17.92/17.49 (bnd_ndr1_1 X163 & bnd_c3_2 X163 bnd_a1514) &
% 17.92/17.49 bnd_c2_2 X163 bnd_a1514)) |
% 17.92/17.49 bnd_c4_0)) &
% 17.92/17.49 (((bnd_ndr1_0 & bnd_c3_1 bnd_a1515) & bnd_c1_1 bnd_a1515 |
% 17.92/17.49 (bnd_ndr1_0 & bnd_c5_1 bnd_a1516) & ~ bnd_c2_1 bnd_a1516) |
% 17.92/17.49 bnd_c2_0)) &
% 17.92/17.49 ((bnd_c1_0 | ~ bnd_c4_0) |
% 17.92/17.49 (ALL X164.
% 17.92/17.49 bnd_ndr1_0 -->
% 17.92/17.49 ((ALL X165.
% 17.92/17.49 bnd_ndr1_1 X164 -->
% 17.92/17.49 bnd_c1_2 X164 X165 | ~ bnd_c4_2 X164 X165) |
% 17.92/17.49 ((bnd_ndr1_1 X164 & ~ bnd_c3_2 X164 bnd_a1517) &
% 17.92/17.49 ~ bnd_c4_2 X164 bnd_a1517) &
% 17.92/17.49 bnd_c1_2 X164 bnd_a1517) |
% 17.92/17.49 ((bnd_ndr1_1 X164 & ~ bnd_c4_2 X164 bnd_a1518) &
% 17.92/17.49 bnd_c1_2 X164 bnd_a1518) &
% 17.92/17.49 bnd_c5_2 X164 bnd_a1518))) &
% 17.92/17.49 (bnd_c2_0 | ~ bnd_c1_0)) &
% 17.92/17.49 (((ALL X166.
% 17.92/17.49 bnd_ndr1_0 -->
% 17.92/17.49 (ALL X167.
% 17.92/17.49 bnd_ndr1_1 X166 -->
% 17.92/17.49 ~ bnd_c1_2 X166 X167 | bnd_c3_2 X166 X167) |
% 17.92/17.49 ((bnd_ndr1_1 X166 & ~ bnd_c5_2 X166 bnd_a1519) &
% 17.92/17.49 bnd_c3_2 X166 bnd_a1519) &
% 17.92/17.49 ~ bnd_c4_2 X166 bnd_a1519) |
% 17.92/17.49 ((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a1520) &
% 17.92/17.49 ~ bnd_c5_2 bnd_a1520 bnd_a1521) &
% 17.92/17.49 ~ bnd_c3_2 bnd_a1520 bnd_a1521) &
% 17.92/17.49 bnd_ndr1_1 bnd_a1520) &
% 17.92/17.49 bnd_c4_2 bnd_a1520 bnd_a1522) &
% 17.92/17.49 ~ bnd_c3_2 bnd_a1520 bnd_a1522) &
% 17.92/17.49 bnd_c2_1 bnd_a1520) |
% 17.92/17.49 ~ bnd_c2_0)) &
% 17.92/17.49 (((ALL X168.
% 17.92/17.49 bnd_ndr1_0 -->
% 17.92/17.49 (~ bnd_c1_1 X168 |
% 17.92/17.49 (ALL X169.
% 17.92/17.49 bnd_ndr1_1 X168 -->
% 17.92/17.49 (bnd_c4_2 X168 X169 | bnd_c1_2 X168 X169) |
% 17.92/17.49 bnd_c2_2 X168 X169)) |
% 17.92/17.49 ((bnd_ndr1_1 X168 & ~ bnd_c2_2 X168 bnd_a1523) &
% 17.92/17.49 ~ bnd_c5_2 X168 bnd_a1523) &
% 17.92/17.49 ~ bnd_c4_2 X168 bnd_a1523) |
% 17.92/17.49 bnd_c1_0) |
% 17.92/17.49 ((bnd_ndr1_0 &
% 17.92/17.49 (ALL X170.
% 17.92/17.49 bnd_ndr1_1 bnd_a1524 -->
% 17.92/17.49 ~ bnd_c4_2 bnd_a1524 X170 | bnd_c1_2 bnd_a1524 X170)) &
% 17.92/17.49 bnd_ndr1_1 bnd_a1524) &
% 17.92/17.49 bnd_c5_2 bnd_a1524 bnd_a1525)) &
% 17.92/17.49 ((bnd_c2_0 |
% 17.92/17.49 (ALL X171.
% 17.92/17.49 bnd_ndr1_0 -->
% 17.92/17.49 (((bnd_ndr1_1 X171 & bnd_c1_2 X171 bnd_a1526) &
% 17.92/17.49 bnd_c4_2 X171 bnd_a1526) &
% 17.92/17.49 ~ bnd_c2_2 X171 bnd_a1526 |
% 17.92/17.49 bnd_c4_1 X171) |
% 17.92/17.49 ~ bnd_c1_1 X171)) |
% 17.92/17.49 (ALL X172.
% 17.92/17.49 bnd_ndr1_0 -->
% 17.92/17.49 (~ bnd_c1_1 X172 | bnd_c2_1 X172) | ~ bnd_c4_1 X172))) &
% 17.92/17.49 ((ALL X173.
% 17.92/17.49 bnd_ndr1_0 -->
% 17.92/17.49 (~ bnd_c1_1 X173 | ~ bnd_c3_1 X173) | ~ bnd_c2_1 X173) |
% 17.92/17.49 (ALL X174.
% 17.92/17.49 bnd_ndr1_0 -->
% 17.92/17.49 (~ bnd_c5_1 X174 |
% 17.92/17.49 (ALL X175.
% 17.92/17.49 bnd_ndr1_1 X174 -->
% 17.92/17.49 (~ bnd_c1_2 X174 X175 | ~ bnd_c5_2 X174 X175) |
% 17.92/17.49 ~ bnd_c3_2 X174 X175)) |
% 17.92/17.49 ~ bnd_c2_1 X174)))
% 17.92/17.49 Adding axioms...
% 17.92/17.49 Typedef.type_definition_def
% 50.57/50.03 ...done.
% 50.57/50.06 Ground types: ?'b, TPTP_Interpret.ind
% 50.57/50.06 Translating term (sizes: 1, 1) ...
% 77.16/76.55 Invoking SAT solver...
% 77.16/76.55 No model exists.
% 77.16/76.55 Translating term (sizes: 2, 1) ...
% 104.44/103.73 Invoking SAT solver...
% 104.44/103.73 No model exists.
% 104.44/103.73 Translating term (sizes: 1, 2) ...
% 151.01/150.16 Invoking SAT solver...
% 151.01/150.19 No model exists.
% 151.01/150.19 Translating term (sizes: 3, 1) ...
% 180.65/179.66 Invoking SAT solver...
% 180.65/179.67 No model exists.
% 180.65/179.67 Translating term (sizes: 2, 2) ...
% 235.08/233.79 Invoking SAT solver...
% 235.18/233.83 No model exists.
% 235.18/233.83 Translating term (sizes: 1, 3) ...
% 300.03/298.14 /export/starexec/sandbox/solver/lib/scripts/run-polyml-5.5.2: line 82: 5739 CPU time limit exceeded (core dumped) "$ISABELLE_HOME/lib/scripts/feeder" -p -h "$MLTEXT" -t "$MLEXIT" $FEEDER_OPTS
% 300.03/298.14 5740 (core dumped) | { read FPID; "$POLY" -q -i $ML_OPTIONS; RC="$?"; kill -TERM "$FPID"; exit "$RC"; }
% 300.03/298.15 /export/starexec/sandbox/solver/src/HOL/TPTP/lib/Tools/tptp_refute: line 26: 5637 Exit 152 "$ISABELLE_PROCESS" -q -e "use_thy \"/tmp/$SCRATCH\"; exit 1;" HOL-TPTP
% 300.03/298.15 5638 CPU time limit exceeded (core dumped) | grep --line-buffered -v "^###\|^PROOF FAILED for depth\|^Failure node\|inferences so far. Searching to depth\|^val \|^Loading theory\|^Warning-The type of\|^ monotype.$"
%------------------------------------------------------------------------------