TSTP Solution File: SYN519+1 by Refute---2015
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%------------------------------------------------------------------------------
% File : Refute---2015
% Problem : SYN519+1 : TPTP v6.4.0. Released v2.1.0.
% Transfm : none
% Format : tptp:raw
% Command : isabelle tptp_refute %d %s
% Computer : n138.star.cs.uiowa.edu
% Model : x86_64 x86_64
% CPU : Intel(R) Xeon(R) CPU E5-2609 0 2.40GHz
% Memory : 32218.75MB
% OS : Linux 3.10.0-327.10.1.el7.x86_64
% CPULimit : 300s
% DateTime : Thu Apr 14 06:42:12 EDT 2016
% Result : Timeout 285.79s
% Output : None
% Verified :
% SZS Type : None (Parsing solution fails)
% Syntax : Number of formulae : 0
% Comments :
%------------------------------------------------------------------------------
%----No solution output by system
%------------------------------------------------------------------------------
%----ORIGINAL SYSTEM OUTPUT
% 0.00/0.03 % Problem : SYN519+1 : TPTP v6.4.0. Released v2.1.0.
% 0.00/0.04 % Command : isabelle tptp_refute %d %s
% 0.02/0.23 % Computer : n138.star.cs.uiowa.edu
% 0.02/0.23 % Model : x86_64 x86_64
% 0.02/0.23 % CPU : Intel(R) Xeon(R) CPU E5-2609 0 @ 2.40GHz
% 0.02/0.23 % Memory : 32218.75MB
% 0.02/0.23 % OS : Linux 3.10.0-327.10.1.el7.x86_64
% 0.02/0.23 % CPULimit : 300
% 0.02/0.23 % DateTime : Sat Apr 9 00:12:09 CDT 2016
% 0.02/0.23 % CPUTime:
% 6.29/5.85 > val it = (): unit
% 7.10/6.66 Trying to find a model that refutes: ~ (((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((bnd_c1_0 &
% 7.10/6.66 ((bnd_c2_0 | bnd_c3_0) | ~ bnd_c4_0)) &
% 7.10/6.66 ((bnd_c2_0 | bnd_c3_0) |
% 7.10/6.66 (ALL U. bnd_ndr1_0 --> bnd_c2_1 U))) &
% 7.10/6.66 ((bnd_c2_0 | bnd_c3_0) |
% 7.10/6.66 (bnd_ndr1_0 &
% 7.10/6.66 (ALL V.
% 7.10/6.66 bnd_ndr1_1 bnd_a1 -->
% 7.10/6.66 (bnd_c1_2 bnd_a1 V | bnd_c2_2 bnd_a1 V) |
% 7.10/6.66 bnd_c3_2 bnd_a1 V)) &
% 7.10/6.66 (ALL W.
% 7.10/6.66 bnd_ndr1_1 bnd_a1 -->
% 7.10/6.66 bnd_c3_2 bnd_a1 W | ~ bnd_c5_2 bnd_a1 W))) &
% 7.10/6.66 ((bnd_c2_0 | bnd_c5_0) | ~ bnd_c4_0)) &
% 7.10/6.66 (bnd_c2_0 | ~ bnd_c4_0)) &
% 7.10/6.66 (bnd_c2_0 |
% 7.10/6.66 (((bnd_ndr1_0 & bnd_c5_1 bnd_a2) & bnd_ndr1_1 bnd_a2) &
% 7.10/6.66 bnd_c5_2 bnd_a2 bnd_a3) &
% 7.10/6.66 ~ bnd_c4_2 bnd_a2 bnd_a3)) &
% 7.10/6.66 ((bnd_c2_0 | ~ bnd_c3_0) |
% 7.10/6.66 (ALL X.
% 7.10/6.66 bnd_ndr1_0 -->
% 7.10/6.66 (bnd_c1_1 X | bnd_c2_1 X) |
% 7.10/6.66 (bnd_ndr1_1 X & bnd_c2_2 X bnd_a4) &
% 7.10/6.66 ~ bnd_c4_2 X bnd_a4))) &
% 7.10/6.66 ((bnd_c2_0 | ~ bnd_c3_0) |
% 7.10/6.66 (ALL Y.
% 7.10/6.66 bnd_ndr1_0 -->
% 7.10/6.66 (bnd_c2_1 Y | ~ bnd_c1_1 Y) |
% 7.10/6.66 ((bnd_ndr1_1 Y & bnd_c4_2 Y bnd_a5) &
% 7.10/6.66 bnd_c5_2 Y bnd_a5) &
% 7.10/6.66 ~ bnd_c3_2 Y bnd_a5))) &
% 7.10/6.66 ((bnd_c2_0 |
% 7.10/6.66 (ALL Z.
% 7.10/6.66 bnd_ndr1_0 -->
% 7.10/6.66 (bnd_c1_1 Z | ~ bnd_c5_1 Z) |
% 7.10/6.66 ((bnd_ndr1_1 Z & bnd_c2_2 Z bnd_a6) &
% 7.10/6.66 bnd_c4_2 Z bnd_a6) &
% 7.10/6.66 ~ bnd_c1_2 Z bnd_a6)) |
% 7.10/6.66 (((((bnd_ndr1_0 & ~ bnd_c1_1 bnd_a7) &
% 7.10/6.66 (ALL X1.
% 7.10/6.66 bnd_ndr1_1 bnd_a7 -->
% 7.10/6.66 bnd_c2_2 bnd_a7 X1 | bnd_c5_2 bnd_a7 X1)) &
% 7.10/6.66 bnd_ndr1_1 bnd_a7) &
% 7.10/6.66 bnd_c4_2 bnd_a7 bnd_a8) &
% 7.10/6.66 bnd_c5_2 bnd_a7 bnd_a8) &
% 7.10/6.66 ~ bnd_c1_2 bnd_a7 bnd_a8)) &
% 7.10/6.66 ((bnd_c2_0 |
% 7.10/6.66 (ALL X2.
% 7.10/6.66 bnd_ndr1_0 -->
% 7.10/6.66 (~ bnd_c1_1 X2 |
% 7.10/6.66 (ALL X3.
% 7.10/6.66 bnd_ndr1_1 X2 -->
% 7.10/6.66 (bnd_c1_2 X2 X3 | bnd_c3_2 X2 X3) |
% 7.10/6.66 ~ bnd_c5_2 X2 X3)) |
% 7.10/6.66 ((bnd_ndr1_1 X2 & bnd_c1_2 X2 bnd_a9) &
% 7.10/6.66 ~ bnd_c2_2 X2 bnd_a9) &
% 7.10/6.66 ~ bnd_c3_2 X2 bnd_a9)) |
% 7.10/6.66 ((((bnd_ndr1_0 & ~ bnd_c1_1 bnd_a10) &
% 7.10/6.66 (ALL X4.
% 7.10/6.66 bnd_ndr1_1 bnd_a10 -->
% 7.10/6.66 (bnd_c5_2 bnd_a10 X4 | ~ bnd_c1_2 bnd_a10 X4) |
% 7.10/6.66 ~ bnd_c4_2 bnd_a10 X4)) &
% 7.10/6.66 bnd_ndr1_1 bnd_a10) &
% 7.10/6.66 ~ bnd_c3_2 bnd_a10 bnd_a11) &
% 7.10/6.66 ~ bnd_c5_2 bnd_a10 bnd_a11)) &
% 7.10/6.66 ((bnd_c2_0 |
% 7.10/6.66 (ALL X5.
% 7.10/6.66 bnd_ndr1_0 -->
% 7.10/6.66 (~ bnd_c2_1 X5 | ~ bnd_c3_1 X5) | ~ bnd_c5_1 X5)) |
% 7.10/6.66 (ALL X6.
% 7.10/6.66 bnd_ndr1_0 -->
% 7.10/6.66 (~ bnd_c2_1 X6 |
% 7.10/6.66 ((bnd_ndr1_1 X6 & bnd_c1_2 X6 bnd_a12) &
% 7.10/6.66 bnd_c2_2 X6 bnd_a12) &
% 7.10/6.66 ~ bnd_c3_2 X6 bnd_a12) |
% 7.10/6.66 ((bnd_ndr1_1 X6 & ~ bnd_c2_2 X6 bnd_a13) &
% 7.10/6.66 ~ bnd_c4_2 X6 bnd_a13) &
% 7.10/6.66 ~ bnd_c5_2 X6 bnd_a13))) &
% 7.10/6.66 ((bnd_c2_0 |
% 7.10/6.66 (ALL X7.
% 7.10/6.66 bnd_ndr1_0 -->
% 7.10/6.66 (~ bnd_c2_1 X7 |
% 7.10/6.66 (bnd_ndr1_1 X7 & ~ bnd_c2_2 X7 bnd_a14) &
% 7.10/6.66 ~ bnd_c4_2 X7 bnd_a14) |
% 7.10/6.66 (bnd_ndr1_1 X7 & ~ bnd_c4_2 X7 bnd_a15) &
% 7.10/6.66 ~ bnd_c5_2 X7 bnd_a15)) |
% 7.10/6.66 ((((bnd_ndr1_0 & bnd_c5_1 bnd_a16) &
% 7.10/6.66 (ALL X8.
% 7.10/6.66 bnd_ndr1_1 bnd_a16 -->
% 7.10/6.66 bnd_c4_2 bnd_a16 X8 | bnd_c5_2 bnd_a16 X8)) &
% 7.10/6.66 bnd_ndr1_1 bnd_a16) &
% 7.10/6.66 bnd_c5_2 bnd_a16 bnd_a17) &
% 7.10/6.66 ~ bnd_c1_2 bnd_a16 bnd_a17)) &
% 7.10/6.66 ((bnd_c2_0 |
% 7.10/6.66 (ALL X9.
% 7.10/6.66 bnd_ndr1_0 -->
% 7.10/6.66 (~ bnd_c3_1 X9 | ~ bnd_c4_1 X9) |
% 7.10/6.66 (bnd_ndr1_1 X9 & bnd_c2_2 X9 bnd_a18) &
% 7.10/6.66 bnd_c5_2 X9 bnd_a18)) |
% 7.10/6.66 ((bnd_ndr1_0 & bnd_c3_1 bnd_a19) &
% 7.10/6.66 (ALL X10.
% 7.10/6.66 bnd_ndr1_1 bnd_a19 -->
% 7.10/6.66 (bnd_c2_2 bnd_a19 X10 | bnd_c4_2 bnd_a19 X10) |
% 7.10/6.66 ~ bnd_c5_2 bnd_a19 X10)) &
% 7.10/6.66 (ALL X11.
% 7.10/6.66 bnd_ndr1_1 bnd_a19 -->
% 7.10/6.66 (bnd_c3_2 bnd_a19 X11 | ~ bnd_c4_2 bnd_a19 X11) |
% 7.10/6.66 ~ bnd_c5_2 bnd_a19 X11))) &
% 7.10/6.66 ((bnd_c2_0 |
% 7.10/6.66 (ALL X12.
% 7.10/6.66 bnd_ndr1_0 -->
% 7.10/6.66 (~ bnd_c4_1 X12 |
% 7.10/6.66 (ALL X13.
% 7.10/6.66 bnd_ndr1_1 X12 -->
% 7.10/6.66 (bnd_c2_2 X12 X13 | bnd_c4_2 X12 X13) |
% 7.10/6.66 ~ bnd_c5_2 X12 X13)) |
% 7.10/6.66 (ALL X14.
% 7.10/6.66 bnd_ndr1_1 X12 -->
% 7.10/6.66 (bnd_c4_2 X12 X14 | ~ bnd_c1_2 X12 X14) |
% 7.10/6.66 ~ bnd_c3_2 X12 X14))) |
% 7.10/6.66 (((((bnd_ndr1_0 & bnd_c1_1 bnd_a20) & ~ bnd_c2_1 bnd_a20) &
% 7.10/6.66 bnd_ndr1_1 bnd_a20) &
% 7.10/6.66 ~ bnd_c2_2 bnd_a20 bnd_a21) &
% 7.10/6.66 ~ bnd_c3_2 bnd_a20 bnd_a21) &
% 7.10/6.66 ~ bnd_c4_2 bnd_a20 bnd_a21)) &
% 7.10/6.66 (bnd_c2_0 |
% 7.10/6.66 (ALL X15.
% 7.10/6.66 bnd_ndr1_0 -->
% 7.10/6.66 (~ bnd_c4_1 X15 |
% 7.10/6.66 (ALL X16.
% 7.10/6.66 bnd_ndr1_1 X15 -->
% 7.10/6.66 (bnd_c3_2 X15 X16 | bnd_c4_2 X15 X16) |
% 7.10/6.66 bnd_c5_2 X15 X16)) |
% 7.10/6.66 (bnd_ndr1_1 X15 & bnd_c3_2 X15 bnd_a22) &
% 7.10/6.66 ~ bnd_c2_2 X15 bnd_a22))) &
% 7.10/6.66 (bnd_c2_0 |
% 7.10/6.66 (((((bnd_ndr1_0 & ~ bnd_c4_1 bnd_a23) &
% 7.10/6.66 (ALL X17.
% 7.10/6.66 bnd_ndr1_1 bnd_a23 -->
% 7.10/6.66 (bnd_c1_2 bnd_a23 X17 | bnd_c3_2 bnd_a23 X17) |
% 7.10/6.66 bnd_c5_2 bnd_a23 X17)) &
% 7.10/6.66 bnd_ndr1_1 bnd_a23) &
% 7.10/6.66 bnd_c2_2 bnd_a23 bnd_a24) &
% 7.10/6.66 bnd_c3_2 bnd_a23 bnd_a24) &
% 7.10/6.66 ~ bnd_c1_2 bnd_a23 bnd_a24)) &
% 7.10/6.66 ((bnd_c3_0 | bnd_c5_0) |
% 7.10/6.66 (ALL X18.
% 7.10/6.66 bnd_ndr1_0 -->
% 7.10/6.66 ~ bnd_c4_1 X18 |
% 7.10/6.66 ((bnd_ndr1_1 X18 & bnd_c3_2 X18 bnd_a25) &
% 7.10/6.66 ~ bnd_c2_2 X18 bnd_a25) &
% 7.10/6.66 ~ bnd_c4_2 X18 bnd_a25))) &
% 7.10/6.66 ((bnd_c3_0 | bnd_c5_0) |
% 7.10/6.66 (bnd_ndr1_0 & ~ bnd_c1_1 bnd_a26) &
% 7.10/6.66 (ALL X19.
% 7.10/6.66 bnd_ndr1_1 bnd_a26 -->
% 7.10/6.66 (bnd_c2_2 bnd_a26 X19 | bnd_c5_2 bnd_a26 X19) |
% 7.10/6.66 ~ bnd_c3_2 bnd_a26 X19))) &
% 7.10/6.66 (bnd_c3_0 | (bnd_ndr1_0 & bnd_c1_1 bnd_a27) & ~ bnd_c2_1 bnd_a27)) &
% 7.10/6.66 ((bnd_c3_0 | ~ bnd_c2_0) |
% 7.10/6.66 (ALL X20.
% 7.10/6.66 bnd_ndr1_0 -->
% 7.10/6.66 (bnd_c3_1 X20 |
% 7.10/6.66 (ALL X21.
% 7.10/6.66 bnd_ndr1_1 X20 -->
% 7.10/6.66 (bnd_c3_2 X20 X21 | bnd_c4_2 X20 X21) | ~ bnd_c5_2 X20 X21)) |
% 7.10/6.66 ((bnd_ndr1_1 X20 & bnd_c1_2 X20 bnd_a28) &
% 7.10/6.66 ~ bnd_c3_2 X20 bnd_a28) &
% 7.10/6.66 ~ bnd_c4_2 X20 bnd_a28))) &
% 7.10/6.66 ((bnd_c3_0 | ~ bnd_c2_0) |
% 7.10/6.66 (((bnd_ndr1_0 & ~ bnd_c1_1 bnd_a29) & bnd_ndr1_1 bnd_a29) &
% 7.10/6.66 bnd_c3_2 bnd_a29 bnd_a30) &
% 7.10/6.66 ~ bnd_c5_2 bnd_a29 bnd_a30)) &
% 7.10/6.66 ((bnd_c3_0 | ~ bnd_c4_0) |
% 7.10/6.66 (ALL X22.
% 7.10/6.66 bnd_ndr1_0 -->
% 7.10/6.66 ((bnd_ndr1_1 X22 & bnd_c2_2 X22 bnd_a31) & ~ bnd_c4_2 X22 bnd_a31) &
% 7.10/6.66 ~ bnd_c5_2 X22 bnd_a31 |
% 7.10/6.66 (bnd_ndr1_1 X22 & bnd_c4_2 X22 bnd_a32) & bnd_c5_2 X22 bnd_a32))) &
% 7.10/6.66 ((bnd_c3_0 | ~ bnd_c5_0) |
% 7.10/6.66 (ALL X23.
% 7.10/6.66 bnd_ndr1_0 -->
% 7.10/6.66 (bnd_c1_1 X23 | bnd_c2_1 X23) |
% 7.10/6.66 (ALL X24. bnd_ndr1_1 X23 --> bnd_c2_2 X23 X24 | bnd_c5_2 X23 X24)))) &
% 7.10/6.66 ((bnd_c3_0 | ~ bnd_c5_0) |
% 7.10/6.66 ((bnd_ndr1_0 & bnd_c2_1 bnd_a33) & bnd_c5_1 bnd_a33) &
% 7.10/6.66 (ALL X25.
% 7.10/6.66 bnd_ndr1_1 bnd_a33 -->
% 7.10/6.66 (bnd_c3_2 bnd_a33 X25 | bnd_c4_2 bnd_a33 X25) |
% 7.10/6.66 ~ bnd_c1_2 bnd_a33 X25))) &
% 7.10/6.66 ((bnd_c3_0 | ~ bnd_c5_0) |
% 7.10/6.66 (((((bnd_ndr1_0 & ~ bnd_c2_1 bnd_a34) &
% 7.10/6.66 (ALL X26.
% 7.10/6.66 bnd_ndr1_1 bnd_a34 -->
% 7.10/6.66 (bnd_c2_2 bnd_a34 X26 | bnd_c5_2 bnd_a34 X26) |
% 7.10/6.66 ~ bnd_c1_2 bnd_a34 X26)) &
% 7.10/6.66 bnd_ndr1_1 bnd_a34) &
% 7.10/6.66 bnd_c2_2 bnd_a34 bnd_a35) &
% 7.10/6.66 bnd_c5_2 bnd_a34 bnd_a35) &
% 7.10/6.66 ~ bnd_c1_2 bnd_a34 bnd_a35)) &
% 7.10/6.66 (bnd_c3_0 |
% 7.10/6.66 (ALL X27.
% 7.10/6.66 bnd_ndr1_0 --> (bnd_c1_1 X27 | bnd_c2_1 X27) | ~ bnd_c5_1 X27))) &
% 7.10/6.66 ((bnd_c3_0 |
% 7.10/6.66 (ALL X28.
% 7.10/6.66 bnd_ndr1_0 -->
% 7.10/6.66 (bnd_c2_1 X28 | bnd_c4_1 X28) |
% 7.10/6.66 (ALL X29.
% 7.10/6.66 bnd_ndr1_1 X28 -->
% 7.10/6.66 (bnd_c2_2 X28 X29 | bnd_c3_2 X28 X29) | ~ bnd_c1_2 X28 X29))) |
% 7.10/6.66 (ALL X30.
% 7.10/6.66 bnd_ndr1_0 -->
% 7.10/6.66 (ALL X31. bnd_ndr1_1 X30 --> bnd_c1_2 X30 X31 | bnd_c3_2 X30 X31) |
% 7.10/6.66 ((bnd_ndr1_1 X30 & bnd_c3_2 X30 bnd_a36) & ~ bnd_c1_2 X30 bnd_a36) &
% 7.10/6.66 ~ bnd_c2_2 X30 bnd_a36))) &
% 7.10/6.66 ((bnd_c3_0 |
% 7.10/6.66 (ALL X32.
% 7.10/6.66 bnd_ndr1_0 -->
% 7.10/6.66 (bnd_c3_1 X32 | ~ bnd_c5_1 X32) |
% 7.10/6.66 (ALL X33. bnd_ndr1_1 X32 --> ~ bnd_c2_2 X32 X33 | ~ bnd_c5_2 X32 X33))) |
% 7.10/6.66 (ALL X34.
% 7.10/6.66 bnd_ndr1_0 -->
% 7.10/6.66 ((ALL X35.
% 7.10/6.66 bnd_ndr1_1 X34 -->
% 7.10/6.66 (bnd_c2_2 X34 X35 | ~ bnd_c1_2 X34 X35) | ~ bnd_c4_2 X34 X35) |
% 7.10/6.66 (ALL X36.
% 7.10/6.66 bnd_ndr1_1 X34 -->
% 7.10/6.66 (~ bnd_c2_2 X34 X36 | ~ bnd_c3_2 X34 X36) | ~ bnd_c5_2 X34 X36)) |
% 7.10/6.66 (ALL X37.
% 7.10/6.66 bnd_ndr1_1 X34 -->
% 7.10/6.66 (~ bnd_c3_2 X34 X37 | ~ bnd_c4_2 X34 X37) | ~ bnd_c5_2 X34 X37)))) &
% 7.10/6.66 (bnd_c3_0 |
% 7.10/6.66 (ALL X38.
% 7.10/6.66 bnd_ndr1_0 -->
% 7.10/6.66 (bnd_c4_1 X38 | ~ bnd_c2_1 X38) |
% 7.10/6.66 (ALL X39.
% 7.10/6.66 bnd_ndr1_1 X38 -->
% 7.10/6.66 (~ bnd_c2_2 X38 X39 | ~ bnd_c4_2 X38 X39) | ~ bnd_c5_2 X38 X39)))) &
% 7.10/6.66 ((bnd_c3_0 |
% 7.10/6.66 (ALL X40.
% 7.10/6.66 bnd_ndr1_0 -->
% 7.10/6.66 (~ bnd_c4_1 X40 | ~ bnd_c5_1 X40) |
% 7.10/6.66 ((bnd_ndr1_1 X40 & ~ bnd_c2_2 X40 bnd_a37) & ~ bnd_c3_2 X40 bnd_a37) &
% 7.10/6.66 ~ bnd_c4_2 X40 bnd_a37)) |
% 7.10/6.66 ((((bnd_ndr1_0 & ~ bnd_c1_1 bnd_a38) &
% 7.10/6.66 (ALL X41.
% 7.10/6.66 bnd_ndr1_1 bnd_a38 -->
% 7.10/6.66 (bnd_c4_2 bnd_a38 X41 | bnd_c5_2 bnd_a38 X41) | ~ bnd_c3_2 bnd_a38 X41)) &
% 7.10/6.66 bnd_ndr1_1 bnd_a38) &
% 7.10/6.66 bnd_c3_2 bnd_a38 bnd_a39) &
% 7.10/6.66 ~ bnd_c5_2 bnd_a38 bnd_a39)) &
% 7.10/6.66 ((bnd_c3_0 |
% 7.10/6.66 (ALL X42.
% 7.10/6.66 bnd_ndr1_0 -->
% 7.10/6.66 (~ bnd_c4_1 X42 |
% 7.10/6.66 (ALL X43. bnd_ndr1_1 X42 --> ~ bnd_c1_2 X42 X43 | ~ bnd_c4_2 X42 X43)) |
% 7.10/6.66 ((bnd_ndr1_1 X42 &
% 7.10/6.66 bnd_c1_2 X42 bnd_a40) &
% 7.10/6.66 bnd_c4_2 X42 bnd_a40) &
% 7.10/6.66 ~ bnd_c3_2 X42 bnd_a40)) |
% 7.10/6.66 ((bnd_ndr1_0 & bnd_c2_1 bnd_a41) &
% 7.10/6.66 bnd_c5_1 bnd_a41) &
% 7.10/6.66 (ALL X44.
% 7.10/6.66 bnd_ndr1_1 bnd_a41 -->
% 7.10/6.66 ~ bnd_c3_2 bnd_a41 X44 |
% 7.10/6.66 ~ bnd_c5_2 bnd_a41 X44))) &
% 7.10/6.66 ((bnd_c3_0 |
% 7.10/6.66 (ALL X45.
% 7.10/6.66 bnd_ndr1_0 -->
% 7.10/6.66 (ALL X46.
% 7.10/6.66 bnd_ndr1_1 X45 -->
% 7.10/6.66 (bnd_c2_2 X45 X46 | bnd_c4_2 X45 X46) | ~ bnd_c1_2 X45 X46) |
% 7.10/6.66 ((bnd_ndr1_1 X45 &
% 7.10/6.66 bnd_c3_2 X45 bnd_a42) &
% 7.10/6.66 bnd_c4_2 X45 bnd_a42) &
% 7.10/6.66 ~ bnd_c2_2 X45 bnd_a42)) |
% 7.10/6.66 ((bnd_ndr1_0 & bnd_c4_1 bnd_a43) &
% 7.10/6.66 bnd_c5_1 bnd_a43) &
% 7.10/6.66 (ALL X47.
% 7.10/6.66 bnd_ndr1_1 bnd_a43 -->
% 7.10/6.66 (bnd_c1_2 bnd_a43 X47 |
% 7.10/6.66 ~ bnd_c3_2 bnd_a43 X47) |
% 7.10/6.66 ~ bnd_c4_2 bnd_a43 X47))) &
% 7.10/6.66 (bnd_c3_0 |
% 7.10/6.66 (ALL X48.
% 7.10/6.66 bnd_ndr1_0 -->
% 7.10/6.66 ((bnd_ndr1_1 X48 & bnd_c3_2 X48 bnd_a44) &
% 7.10/6.66 ~ bnd_c2_2 X48 bnd_a44) &
% 7.10/6.66 ~ bnd_c4_2 X48 bnd_a44 |
% 7.10/6.66 (bnd_ndr1_1 X48 & bnd_c5_2 X48 bnd_a45) &
% 7.10/6.66 ~ bnd_c4_2 X48 bnd_a45))) &
% 7.10/6.66 (bnd_c3_0 |
% 7.10/6.66 ((bnd_ndr1_0 & bnd_c1_1 bnd_a46) &
% 7.10/6.66 bnd_c2_1 bnd_a46) &
% 7.10/6.66 (ALL X49.
% 7.10/6.66 bnd_ndr1_1 bnd_a46 -->
% 7.10/6.66 bnd_c4_2 bnd_a46 X49 |
% 7.10/6.66 ~ bnd_c2_2 bnd_a46 X49))) &
% 7.10/6.66 (bnd_c3_0 |
% 7.10/6.66 ((bnd_ndr1_0 & ~ bnd_c1_1 bnd_a47) &
% 7.10/6.66 (ALL X50.
% 7.10/6.66 bnd_ndr1_1 bnd_a47 -->
% 7.10/6.66 (bnd_c1_2 bnd_a47 X50 |
% 7.10/6.66 bnd_c4_2 bnd_a47 X50) |
% 7.10/6.66 bnd_c5_2 bnd_a47 X50)) &
% 7.10/6.66 (ALL X51.
% 7.10/6.66 bnd_ndr1_1 bnd_a47 -->
% 7.10/6.66 bnd_c1_2 bnd_a47 X51 |
% 7.10/6.66 ~ bnd_c5_2 bnd_a47 X51))) &
% 7.10/6.66 ((bnd_c3_0 |
% 7.10/6.66 (bnd_ndr1_0 &
% 7.10/6.66 (ALL X52.
% 7.10/6.66 bnd_ndr1_1 bnd_a48 -->
% 7.10/6.66 bnd_c1_2 bnd_a48 X52 |
% 7.10/6.66 ~ bnd_c3_2 bnd_a48 X52)) &
% 7.10/6.66 (ALL X53.
% 7.10/6.66 bnd_ndr1_1 bnd_a48 -->
% 7.10/6.66 bnd_c3_2 bnd_a48 X53 |
% 7.10/6.66 ~ bnd_c2_2 bnd_a48 X53)) |
% 7.10/6.66 bnd_ndr1_0 &
% 7.10/6.66 (ALL X54.
% 7.10/6.66 bnd_ndr1_1 bnd_a49 -->
% 7.10/6.66 (bnd_c1_2 bnd_a49 X54 |
% 7.10/6.66 bnd_c2_2 bnd_a49 X54) |
% 7.10/6.66 bnd_c4_2 bnd_a49 X54))) &
% 7.10/6.66 (bnd_c4_0 | bnd_c5_0)) &
% 7.10/6.66 ((bnd_c4_0 | bnd_c5_0) |
% 7.10/6.66 (ALL X55.
% 7.10/6.66 bnd_ndr1_0 -->
% 7.10/6.66 (bnd_c2_1 X55 | ~ bnd_c1_1 X55) |
% 7.10/6.66 (bnd_ndr1_1 X55 & bnd_c2_2 X55 bnd_a50) &
% 7.10/6.66 bnd_c3_2 X55 bnd_a50))) &
% 7.10/6.66 ((bnd_c4_0 | bnd_c5_0) |
% 7.10/6.66 (ALL X56.
% 7.10/6.66 bnd_ndr1_0 -->
% 7.10/6.66 (~ bnd_c3_1 X56 |
% 7.10/6.66 (ALL X57.
% 7.10/6.66 bnd_ndr1_1 X56 -->
% 7.10/6.66 (bnd_c1_2 X56 X57 | ~ bnd_c2_2 X56 X57) |
% 7.10/6.66 ~ bnd_c5_2 X56 X57)) |
% 7.10/6.66 (ALL X58.
% 7.10/6.66 bnd_ndr1_1 X56 -->
% 7.10/6.66 (bnd_c3_2 X56 X58 | bnd_c4_2 X56 X58) |
% 7.10/6.66 ~ bnd_c5_2 X56 X58)))) &
% 7.10/6.66 bnd_c4_0) &
% 7.10/6.66 (bnd_c5_0 |
% 7.10/6.66 (((((bnd_ndr1_0 & ~ bnd_c4_1 bnd_a51) &
% 7.10/6.66 (ALL X59.
% 7.10/6.66 bnd_ndr1_1 bnd_a51 -->
% 7.10/6.66 (bnd_c2_2 bnd_a51 X59 |
% 7.10/6.66 bnd_c4_2 bnd_a51 X59) |
% 7.10/6.66 ~ bnd_c3_2 bnd_a51 X59)) &
% 7.10/6.66 bnd_ndr1_1 bnd_a51) &
% 7.10/6.66 bnd_c2_2 bnd_a51 bnd_a52) &
% 7.10/6.66 bnd_c3_2 bnd_a51 bnd_a52) &
% 7.10/6.66 ~ bnd_c4_2 bnd_a51 bnd_a52)) &
% 7.10/6.66 (bnd_c5_0 | ~ bnd_c3_0)) &
% 7.10/6.66 ((bnd_c5_0 |
% 7.10/6.66 (ALL X60.
% 7.10/6.66 bnd_ndr1_0 -->
% 7.10/6.66 (bnd_c1_1 X60 |
% 7.10/6.66 (ALL X61.
% 7.10/6.66 bnd_ndr1_1 X60 -->
% 7.10/6.66 bnd_c1_2 X60 X61 | bnd_c3_2 X60 X61)) |
% 7.10/6.66 (ALL X62.
% 7.10/6.66 bnd_ndr1_1 X60 -->
% 7.10/6.66 bnd_c3_2 X60 X62 | bnd_c4_2 X60 X62))) |
% 7.10/6.66 (ALL X63.
% 7.10/6.66 bnd_ndr1_0 -->
% 7.10/6.66 (~ bnd_c2_1 X63 | ~ bnd_c5_1 X63) |
% 7.10/6.66 (bnd_ndr1_1 X63 & bnd_c2_2 X63 bnd_a53) &
% 7.10/6.66 ~ bnd_c4_2 X63 bnd_a53))) &
% 7.10/6.66 ((bnd_c5_0 |
% 7.10/6.66 (ALL X64.
% 7.10/6.66 bnd_ndr1_0 -->
% 7.10/6.66 (bnd_c3_1 X64 | bnd_c4_1 X64) | ~ bnd_c5_1 X64)) |
% 7.10/6.66 (bnd_ndr1_0 & bnd_c3_1 bnd_a54) & bnd_c4_1 bnd_a54)) &
% 7.10/6.66 (~ bnd_c2_0 |
% 7.10/6.66 (ALL X65.
% 7.10/6.66 bnd_ndr1_0 -->
% 7.10/6.66 ((ALL X66.
% 7.10/6.66 bnd_ndr1_1 X65 -->
% 7.10/6.66 (bnd_c5_2 X65 X66 | ~ bnd_c1_2 X65 X66) |
% 7.10/6.66 ~ bnd_c4_2 X65 X66) |
% 7.10/6.66 (ALL X67.
% 7.10/6.66 bnd_ndr1_1 X65 -->
% 7.10/6.66 (~ bnd_c3_2 X65 X67 | ~ bnd_c4_2 X65 X67) |
% 7.10/6.66 ~ bnd_c5_2 X65 X67)) |
% 7.10/6.66 (bnd_ndr1_1 X65 & ~ bnd_c1_2 X65 bnd_a55) &
% 7.10/6.66 ~ bnd_c4_2 X65 bnd_a55))) &
% 7.10/6.66 ~ bnd_c3_0) &
% 7.10/6.66 (ALL X68.
% 7.10/6.66 bnd_ndr1_0 -->
% 7.10/6.66 (bnd_c5_1 X68 | ~ bnd_c4_1 X68) |
% 7.10/6.66 ((bnd_ndr1_1 X68 & bnd_c1_2 X68 bnd_a56) &
% 7.10/6.66 bnd_c5_2 X68 bnd_a56) &
% 7.10/6.66 ~ bnd_c3_2 X68 bnd_a56)) &
% 7.10/6.66 (~ bnd_c5_0 |
% 7.10/6.66 (ALL X69.
% 7.10/6.66 bnd_ndr1_0 -->
% 7.10/6.66 (~ bnd_c3_1 X69 |
% 7.10/6.66 (ALL X70.
% 7.10/6.66 bnd_ndr1_1 X69 -->
% 7.10/6.66 (~ bnd_c2_2 X69 X70 | ~ bnd_c3_2 X69 X70) |
% 7.10/6.66 ~ bnd_c4_2 X69 X70)) |
% 7.10/6.66 ((bnd_ndr1_1 X69 & bnd_c2_2 X69 bnd_a57) &
% 7.10/6.66 bnd_c4_2 X69 bnd_a57) &
% 7.10/6.66 bnd_c5_2 X69 bnd_a57))) &
% 7.10/6.66 ((ALL X71. bnd_ndr1_0 --> bnd_c1_1 X71 | bnd_c3_1 X71) |
% 7.10/6.66 (ALL X72.
% 7.10/6.66 bnd_ndr1_0 -->
% 7.10/6.66 (~ bnd_c2_1 X72 |
% 7.10/6.66 (ALL X73.
% 7.10/6.66 bnd_ndr1_1 X72 -->
% 7.10/6.66 (bnd_c1_2 X72 X73 | bnd_c4_2 X72 X73) |
% 7.10/6.66 ~ bnd_c5_2 X72 X73)) |
% 7.10/6.66 (ALL X74.
% 7.10/6.66 bnd_ndr1_1 X72 -->
% 7.10/6.66 (~ bnd_c1_2 X72 X74 | ~ bnd_c2_2 X72 X74) |
% 7.10/6.66 ~ bnd_c3_2 X72 X74)))) &
% 7.10/6.66 ((ALL X75.
% 7.10/6.66 bnd_ndr1_0 -->
% 7.10/6.66 (bnd_c4_1 X75 | ~ bnd_c5_1 X75) |
% 7.10/6.66 (ALL X76. bnd_ndr1_1 X75 --> ~ bnd_c2_2 X75 X76)) |
% 7.10/6.66 ((bnd_ndr1_0 & bnd_c4_1 bnd_a58) & ~ bnd_c2_1 bnd_a58) &
% 7.10/6.66 (ALL X77.
% 7.10/6.66 bnd_ndr1_1 bnd_a58 -->
% 7.10/6.66 (bnd_c1_2 bnd_a58 X77 | bnd_c2_2 bnd_a58 X77) |
% 7.10/6.66 bnd_c5_2 bnd_a58 X77))) &
% 7.10/6.66 (ALL X78.
% 7.10/6.66 bnd_ndr1_0 -->
% 7.10/6.66 (bnd_c4_1 X78 |
% 7.10/6.66 (bnd_ndr1_1 X78 & bnd_c2_2 X78 bnd_a59) &
% 7.10/6.66 bnd_c3_2 X78 bnd_a59) |
% 7.10/6.66 ((bnd_ndr1_1 X78 & ~ bnd_c2_2 X78 bnd_a60) &
% 7.10/6.66 ~ bnd_c4_2 X78 bnd_a60) &
% 7.10/6.66 ~ bnd_c5_2 X78 bnd_a60)) &
% 7.10/6.66 ((ALL X79.
% 7.10/6.66 bnd_ndr1_0 -->
% 7.10/6.66 (~ bnd_c1_1 X79 |
% 7.10/6.66 (ALL X80.
% 7.10/6.66 bnd_ndr1_1 X79 -->
% 7.10/6.66 bnd_c3_2 X79 X80 | ~ bnd_c1_2 X79 X80)) |
% 7.10/6.66 (ALL X81.
% 7.10/6.66 bnd_ndr1_1 X79 -->
% 7.10/6.66 bnd_c4_2 X79 X81 | ~ bnd_c5_2 X79 X81)) |
% 7.10/6.66 ((((((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a61) &
% 7.10/6.66 bnd_c1_2 bnd_a61 bnd_a62) &
% 7.10/6.66 bnd_c4_2 bnd_a61 bnd_a62) &
% 7.10/6.66 ~ bnd_c2_2 bnd_a61 bnd_a62) &
% 7.10/6.66 bnd_ndr1_1 bnd_a61) &
% 7.10/6.66 bnd_c1_2 bnd_a61 bnd_a63) &
% 7.10/6.66 ~ bnd_c4_2 bnd_a61 bnd_a63) &
% 7.10/6.66 ~ bnd_c5_2 bnd_a61 bnd_a63) &
% 7.10/6.66 bnd_ndr1_1 bnd_a61) &
% 7.10/6.66 ~ bnd_c3_2 bnd_a61 bnd_a64) &
% 7.10/6.66 ~ bnd_c4_2 bnd_a61 bnd_a64)) &
% 7.10/6.66 ((ALL X82.
% 7.10/6.66 bnd_ndr1_0 -->
% 7.10/6.66 ~ bnd_c4_1 X82 |
% 7.10/6.66 (bnd_ndr1_1 X82 & bnd_c1_2 X82 bnd_a65) &
% 7.10/6.66 bnd_c2_2 X82 bnd_a65) |
% 7.10/6.66 ((((bnd_ndr1_0 & bnd_c5_1 bnd_a66) & bnd_ndr1_1 bnd_a66) &
% 7.10/6.66 bnd_c3_2 bnd_a66 bnd_a67) &
% 7.10/6.66 bnd_c5_2 bnd_a66 bnd_a67) &
% 7.10/6.66 ~ bnd_c2_2 bnd_a66 bnd_a67)) &
% 7.10/6.66 ((ALL X83.
% 7.10/6.66 bnd_ndr1_0 -->
% 7.10/6.66 ((ALL X84.
% 7.10/6.66 bnd_ndr1_1 X83 -->
% 7.10/6.66 (bnd_c2_2 X83 X84 | bnd_c4_2 X83 X84) |
% 7.10/6.66 ~ bnd_c5_2 X83 X84) |
% 7.10/6.66 ((bnd_ndr1_1 X83 & bnd_c1_2 X83 bnd_a68) &
% 7.10/6.66 bnd_c3_2 X83 bnd_a68) &
% 7.10/6.66 ~ bnd_c2_2 X83 bnd_a68) |
% 7.10/6.66 ((bnd_ndr1_1 X83 & bnd_c3_2 X83 bnd_a69) &
% 7.10/6.66 ~ bnd_c1_2 X83 bnd_a69) &
% 7.10/6.66 ~ bnd_c2_2 X83 bnd_a69) |
% 7.10/6.66 ((bnd_ndr1_0 & bnd_c2_1 bnd_a70) & ~ bnd_c4_1 bnd_a70) &
% 7.10/6.66 ~ bnd_c5_1 bnd_a70)) &
% 7.10/6.66 (((bnd_ndr1_0 & bnd_c3_1 bnd_a71) & ~ bnd_c2_1 bnd_a71) &
% 7.10/6.66 ~ bnd_c5_1 bnd_a71 |
% 7.10/6.66 ((((bnd_ndr1_0 & ~ bnd_c3_1 bnd_a72) & bnd_ndr1_1 bnd_a72) &
% 7.10/6.66 bnd_c2_2 bnd_a72 bnd_a73) &
% 7.10/6.66 bnd_c3_2 bnd_a72 bnd_a73) &
% 7.10/6.66 ~ bnd_c4_2 bnd_a72 bnd_a73)) &
% 7.10/6.66 ((~ bnd_c2_0 |
% 7.10/6.66 (ALL X85.
% 7.10/6.66 bnd_ndr1_0 -->
% 7.10/6.66 (bnd_c2_1 X85 | bnd_c3_1 X85) | ~ bnd_c1_1 X85)) |
% 7.10/6.66 ((((((((bnd_ndr1_0 & bnd_c2_1 bnd_a74) & bnd_ndr1_1 bnd_a74) &
% 7.10/6.66 bnd_c1_2 bnd_a74 bnd_a75) &
% 7.10/6.66 ~ bnd_c4_2 bnd_a74 bnd_a75) &
% 7.10/6.66 ~ bnd_c5_2 bnd_a74 bnd_a75) &
% 7.10/6.66 bnd_ndr1_1 bnd_a74) &
% 7.10/6.66 bnd_c2_2 bnd_a74 bnd_a76) &
% 7.10/6.66 bnd_c3_2 bnd_a74 bnd_a76) &
% 7.10/6.66 ~ bnd_c1_2 bnd_a74 bnd_a76)) &
% 7.10/6.66 ((~ bnd_c2_0 |
% 7.10/6.66 (ALL X86.
% 7.10/6.66 bnd_ndr1_0 -->
% 7.10/6.66 (bnd_c4_1 X86 | ~ bnd_c3_1 X86) |
% 7.10/6.66 (ALL X87.
% 7.10/6.66 bnd_ndr1_1 X86 -->
% 7.10/6.66 (bnd_c2_2 X86 X87 | bnd_c4_2 X86 X87) | bnd_c5_2 X86 X87))) |
% 7.10/6.66 (ALL X88.
% 7.10/6.66 bnd_ndr1_0 -->
% 7.10/6.66 (bnd_c5_1 X88 | ~ bnd_c2_1 X88) | ~ bnd_c3_1 X88))) &
% 7.10/6.66 ((~ bnd_c2_0 |
% 7.10/6.66 (ALL X89.
% 7.10/6.66 bnd_ndr1_0 -->
% 7.10/6.66 (~ bnd_c2_1 X89 |
% 7.10/6.66 (ALL X90.
% 7.10/6.66 bnd_ndr1_1 X89 -->
% 7.10/6.66 ~ bnd_c2_2 X89 X90 | ~ bnd_c3_2 X89 X90)) |
% 7.10/6.66 (bnd_ndr1_1 X89 & bnd_c2_2 X89 bnd_a77) & bnd_c3_2 X89 bnd_a77)) |
% 7.10/6.66 (ALL X91.
% 7.10/6.66 bnd_ndr1_0 -->
% 7.10/6.66 ~ bnd_c4_1 X91 |
% 7.10/6.66 ((bnd_ndr1_1 X91 & bnd_c4_2 X91 bnd_a78) & bnd_c5_2 X91 bnd_a78) &
% 7.10/6.66 ~ bnd_c3_2 X91 bnd_a78))) &
% 7.10/6.66 ((~ bnd_c2_0 |
% 7.10/6.66 (ALL X92.
% 7.10/6.66 bnd_ndr1_0 -->
% 7.10/6.66 (~ bnd_c5_1 X92 |
% 7.10/6.66 (ALL X93.
% 7.10/6.66 bnd_ndr1_1 X92 --> bnd_c1_2 X92 X93 | ~ bnd_c5_2 X92 X93)) |
% 7.10/6.66 (bnd_ndr1_1 X92 & ~ bnd_c2_2 X92 bnd_a79) &
% 7.10/6.66 ~ bnd_c4_2 X92 bnd_a79)) |
% 7.10/6.66 (bnd_ndr1_0 & ~ bnd_c3_1 bnd_a80) & ~ bnd_c5_1 bnd_a80)) &
% 7.10/6.66 ((~ bnd_c2_0 |
% 7.10/6.66 (ALL X94.
% 7.10/6.66 bnd_ndr1_0 -->
% 7.10/6.66 ((ALL X95.
% 7.10/6.66 bnd_ndr1_1 X94 --> bnd_c5_2 X94 X95 | ~ bnd_c4_2 X94 X95) |
% 7.10/6.66 ((bnd_ndr1_1 X94 & bnd_c2_2 X94 bnd_a81) &
% 7.10/6.66 ~ bnd_c1_2 X94 bnd_a81) &
% 7.10/6.66 ~ bnd_c5_2 X94 bnd_a81) |
% 7.10/6.66 ((bnd_ndr1_1 X94 & bnd_c4_2 X94 bnd_a82) & ~ bnd_c1_2 X94 bnd_a82) &
% 7.10/6.66 ~ bnd_c3_2 X94 bnd_a82)) |
% 7.10/6.66 (((((bnd_ndr1_0 & bnd_c2_1 bnd_a83) & ~ bnd_c4_1 bnd_a83) &
% 7.10/6.66 bnd_ndr1_1 bnd_a83) &
% 7.10/6.66 bnd_c1_2 bnd_a83 bnd_a84) &
% 7.10/6.66 bnd_c2_2 bnd_a83 bnd_a84) &
% 7.10/6.66 bnd_c3_2 bnd_a83 bnd_a84)) &
% 7.10/6.66 (~ bnd_c2_0 |
% 7.10/6.66 ((bnd_ndr1_0 & bnd_c3_1 bnd_a85) &
% 7.10/6.66 (ALL X96.
% 7.10/6.66 bnd_ndr1_1 bnd_a85 -->
% 7.10/6.66 (bnd_c3_2 bnd_a85 X96 | ~ bnd_c1_2 bnd_a85 X96) |
% 7.10/6.66 ~ bnd_c4_2 bnd_a85 X96)) &
% 7.10/6.66 (ALL X97.
% 7.10/6.66 bnd_ndr1_1 bnd_a85 -->
% 7.10/6.66 (bnd_c3_2 bnd_a85 X97 | ~ bnd_c1_2 bnd_a85 X97) |
% 7.10/6.66 ~ bnd_c5_2 bnd_a85 X97))) &
% 7.10/6.66 ((~ bnd_c2_0 |
% 7.10/6.66 ((bnd_ndr1_0 & bnd_c4_1 bnd_a86) & bnd_c5_1 bnd_a86) &
% 7.10/6.66 ~ bnd_c1_1 bnd_a86) |
% 7.10/6.66 ((((((((bnd_ndr1_0 & ~ bnd_c4_1 bnd_a87) & bnd_ndr1_1 bnd_a87) &
% 7.10/6.66 bnd_c2_2 bnd_a87 bnd_a88) &
% 7.10/6.66 bnd_c3_2 bnd_a87 bnd_a88) &
% 7.10/6.66 bnd_c5_2 bnd_a87 bnd_a88) &
% 7.10/6.66 bnd_ndr1_1 bnd_a87) &
% 7.10/6.66 bnd_c2_2 bnd_a87 bnd_a89) &
% 7.10/6.66 bnd_c3_2 bnd_a87 bnd_a89) &
% 7.10/6.66 ~ bnd_c4_2 bnd_a87 bnd_a89)) &
% 7.10/6.66 (~ bnd_c2_0 |
% 7.10/6.66 (bnd_ndr1_0 & ~ bnd_c3_1 bnd_a90) & ~ bnd_c4_1 bnd_a90)) &
% 7.10/6.66 (~ bnd_c5_0 |
% 7.10/6.66 (((((bnd_ndr1_0 & bnd_c5_1 bnd_a91) &
% 7.10/6.66 ~ bnd_c4_1 bnd_a91) &
% 7.10/6.66 bnd_ndr1_1 bnd_a91) &
% 7.10/6.66 ~ bnd_c1_2 bnd_a91 bnd_a92) &
% 7.10/6.66 ~ bnd_c2_2 bnd_a91 bnd_a92) &
% 7.10/6.66 ~ bnd_c4_2 bnd_a91 bnd_a92)) &
% 7.10/6.66 (ALL X98.
% 7.10/6.66 bnd_ndr1_0 -->
% 7.10/6.66 (bnd_c2_1 X98 | bnd_c3_1 X98) |
% 7.10/6.66 (ALL X99.
% 7.10/6.66 bnd_ndr1_1 X98 -->
% 7.10/6.66 (bnd_c2_2 X98 X99 | bnd_c3_2 X98 X99) | ~ bnd_c5_2 X98 X99))) &
% 7.10/6.66 ((ALL X100.
% 7.10/6.66 bnd_ndr1_0 -->
% 7.10/6.66 (bnd_c2_1 X100 | ~ bnd_c4_1 X100) |
% 7.10/6.66 (ALL X101.
% 7.10/6.66 bnd_ndr1_1 X100 -->
% 7.10/6.66 (bnd_c3_2 X100 X101 | ~ bnd_c1_2 X100 X101) | ~ bnd_c4_2 X100 X101)) |
% 7.10/6.66 (bnd_ndr1_0 & ~ bnd_c3_1 bnd_a93) &
% 7.10/6.66 (ALL X102.
% 7.10/6.66 bnd_ndr1_1 bnd_a93 -->
% 7.10/6.66 (bnd_c1_2 bnd_a93 X102 | bnd_c5_2 bnd_a93 X102) |
% 7.10/6.66 ~ bnd_c3_2 bnd_a93 X102))) &
% 7.10/6.66 ((ALL X103.
% 7.10/6.66 bnd_ndr1_0 -->
% 7.10/6.66 bnd_c2_1 X103 |
% 7.10/6.66 (ALL X104.
% 7.10/6.66 bnd_ndr1_1 X103 -->
% 7.10/6.66 (bnd_c1_2 X103 X104 | ~ bnd_c3_2 X103 X104) | ~ bnd_c5_2 X103 X104)) |
% 7.10/6.66 ((((bnd_ndr1_0 & bnd_c5_1 bnd_a94) &
% 7.10/6.66 (ALL X105.
% 7.10/6.66 bnd_ndr1_1 bnd_a94 -->
% 7.10/6.66 (bnd_c3_2 bnd_a94 X105 | ~ bnd_c2_2 bnd_a94 X105) |
% 7.10/6.66 ~ bnd_c5_2 bnd_a94 X105)) &
% 7.10/6.66 bnd_ndr1_1 bnd_a94) &
% 7.10/6.66 bnd_c2_2 bnd_a94 bnd_a95) &
% 7.10/6.66 ~ bnd_c4_2 bnd_a94 bnd_a95)) &
% 7.10/6.66 ((ALL X106.
% 7.10/6.66 bnd_ndr1_0 -->
% 7.10/6.66 ~ bnd_c1_1 X106 | ~ bnd_c2_1 X106) |
% 7.10/6.66 ((((bnd_ndr1_0 & ~ bnd_c3_1 bnd_a96) &
% 7.10/6.66 (ALL X107.
% 7.10/6.66 bnd_ndr1_1 bnd_a96 -->
% 7.10/6.66 (bnd_c3_2 bnd_a96 X107 | bnd_c5_2 bnd_a96 X107) |
% 7.10/6.66 ~ bnd_c1_2 bnd_a96 X107)) &
% 7.10/6.66 bnd_ndr1_1 bnd_a96) &
% 7.10/6.66 bnd_c3_2 bnd_a96 bnd_a97) &
% 7.10/6.66 ~ bnd_c5_2 bnd_a96 bnd_a97)) &
% 7.10/6.66 ((ALL X108.
% 7.10/6.66 bnd_ndr1_0 -->
% 7.10/6.66 (~ bnd_c1_1 X108 | ~ bnd_c3_1 X108) |
% 7.10/6.66 ((bnd_ndr1_1 X108 &
% 7.10/6.66 bnd_c1_2 X108 bnd_a98) &
% 7.10/6.66 bnd_c4_2 X108 bnd_a98) &
% 7.10/6.66 bnd_c5_2 X108 bnd_a98) |
% 7.10/6.66 ((bnd_ndr1_0 & ~ bnd_c1_1 bnd_a99) &
% 7.10/6.66 (ALL X109.
% 7.10/6.66 bnd_ndr1_1 bnd_a99 -->
% 7.10/6.66 bnd_c4_2 bnd_a99 X109 |
% 7.10/6.66 ~ bnd_c2_2 bnd_a99 X109)) &
% 7.10/6.66 (ALL X110.
% 7.10/6.66 bnd_ndr1_1 bnd_a99 -->
% 7.10/6.66 (~ bnd_c1_2 bnd_a99 X110 |
% 7.10/6.66 ~ bnd_c2_2 bnd_a99 X110) |
% 7.10/6.66 ~ bnd_c3_2 bnd_a99 X110))) &
% 7.10/6.66 (ALL X111.
% 7.10/6.66 bnd_ndr1_0 -->
% 7.10/6.66 (~ bnd_c3_1 X111 |
% 7.10/6.66 ((bnd_ndr1_1 X111 &
% 7.10/6.66 bnd_c1_2 X111 bnd_a100) &
% 7.10/6.66 bnd_c4_2 X111 bnd_a100) &
% 7.10/6.66 ~ bnd_c3_2 X111 bnd_a100) |
% 7.10/6.66 ((bnd_ndr1_1 X111 &
% 7.10/6.66 bnd_c2_2 X111 bnd_a101) &
% 7.10/6.66 ~ bnd_c3_2 X111 bnd_a101) &
% 7.10/6.66 ~ bnd_c5_2 X111 bnd_a101)) &
% 7.10/6.66 ((bnd_ndr1_0 & bnd_c3_1 bnd_a102) &
% 7.10/6.66 bnd_c5_1 bnd_a102 |
% 7.10/6.66 ((((bnd_ndr1_0 & bnd_c4_1 bnd_a103) &
% 7.10/6.66 ~ bnd_c2_1 bnd_a103) &
% 7.10/6.66 bnd_ndr1_1 bnd_a103) &
% 7.10/6.66 bnd_c4_2 bnd_a103 bnd_a104) &
% 7.10/6.66 ~ bnd_c3_2 bnd_a103 bnd_a104)) &
% 7.10/6.66 ((~ bnd_c5_0 |
% 7.10/6.66 (ALL X112.
% 7.10/6.66 bnd_ndr1_0 -->
% 7.10/6.66 (bnd_c1_1 X112 | bnd_c3_1 X112) |
% 7.10/6.66 (bnd_ndr1_1 X112 &
% 7.10/6.66 ~ bnd_c2_2 X112 bnd_a105) &
% 7.10/6.66 ~ bnd_c3_2 X112 bnd_a105)) |
% 7.10/6.66 (ALL X113.
% 7.10/6.66 bnd_ndr1_0 -->
% 7.10/6.66 ~ bnd_c1_1 X113 |
% 7.10/6.66 (bnd_ndr1_1 X113 &
% 7.10/6.66 bnd_c4_2 X113 bnd_a106) &
% 7.10/6.66 ~ bnd_c1_2 X113 bnd_a106))) &
% 7.10/6.66 (~ bnd_c5_0 |
% 7.10/6.66 (ALL X114.
% 7.10/6.66 bnd_ndr1_0 -->
% 7.10/6.66 (bnd_c2_1 X114 | ~ bnd_c4_1 X114) |
% 7.10/6.66 (ALL X115.
% 7.10/6.66 bnd_ndr1_1 X114 -->
% 7.10/6.66 (bnd_c1_2 X114 X115 |
% 7.10/6.66 bnd_c4_2 X114 X115) |
% 7.10/6.66 ~ bnd_c2_2 X114 X115)))) &
% 7.10/6.66 (~ bnd_c5_0 |
% 7.10/6.66 (ALL X116.
% 7.10/6.66 bnd_ndr1_0 -->
% 7.10/6.66 (bnd_c3_1 X116 |
% 7.10/6.66 (ALL X117.
% 7.10/6.66 bnd_ndr1_1 X116 -->
% 7.10/6.66 (bnd_c1_2 X116 X117 |
% 7.10/6.66 bnd_c3_2 X116 X117) |
% 7.10/6.66 ~ bnd_c5_2 X116 X117)) |
% 7.10/6.66 (ALL X118.
% 7.10/6.66 bnd_ndr1_1 X116 -->
% 7.10/6.66 (bnd_c1_2 X116 X118 |
% 7.10/6.66 bnd_c5_2 X116 X118) |
% 7.10/6.66 ~ bnd_c3_2 X116 X118)))) &
% 7.10/6.66 (~ bnd_c5_0 |
% 7.10/6.66 ((((bnd_ndr1_0 &
% 7.10/6.66 (ALL X119.
% 7.10/6.66 bnd_ndr1_1 bnd_a107 -->
% 7.10/6.66 bnd_c1_2 bnd_a107 X119 |
% 7.10/6.66 bnd_c2_2 bnd_a107 X119)) &
% 7.10/6.66 (ALL X120.
% 7.10/6.66 bnd_ndr1_1 bnd_a107 -->
% 7.10/6.66 (~ bnd_c1_2 bnd_a107 X120 |
% 7.10/6.66 ~ bnd_c3_2 bnd_a107 X120) |
% 7.10/6.66 ~ bnd_c4_2 bnd_a107 X120)) &
% 7.10/6.66 bnd_ndr1_1 bnd_a107) &
% 7.10/6.66 bnd_c4_2 bnd_a107 bnd_a108) &
% 7.10/6.66 ~ bnd_c1_2 bnd_a107 bnd_a108)) &
% 7.10/6.66 (((ALL X121.
% 7.10/6.66 bnd_ndr1_0 -->
% 7.10/6.66 bnd_c0_1 X121 & ~ bnd_c0_1 X121) |
% 7.10/6.66 (bnd_ndr1_0 & bnd_c4_1 bnd_a109) &
% 7.10/6.66 ~ bnd_c1_1 bnd_a109) |
% 7.10/6.66 ((((bnd_ndr1_0 & ~ bnd_c5_1 bnd_a110) &
% 7.10/6.66 bnd_ndr1_1 bnd_a110) &
% 7.10/6.66 bnd_c3_2 bnd_a110 bnd_a111) &
% 7.10/6.66 ~ bnd_c2_2 bnd_a110 bnd_a111) &
% 7.10/6.66 ~ bnd_c5_2 bnd_a110 bnd_a111)) &
% 7.10/6.66 (((ALL X122.
% 7.10/6.66 bnd_ndr1_0 -->
% 7.10/6.66 (bnd_c1_1 X122 | ~ bnd_c2_1 X122) |
% 7.10/6.66 (bnd_ndr1_1 X122 & bnd_c3_2 X122 bnd_a112) &
% 7.10/6.66 ~ bnd_c4_2 X122 bnd_a112) |
% 7.10/6.66 (ALL X123.
% 7.10/6.66 bnd_ndr1_0 -->
% 7.10/6.66 bnd_c5_1 X123 |
% 7.10/6.66 ((bnd_ndr1_1 X123 & bnd_c3_2 X123 bnd_a113) &
% 7.10/6.66 ~ bnd_c4_2 X123 bnd_a113) &
% 7.10/6.66 ~ bnd_c5_2 X123 bnd_a113)) |
% 7.10/6.66 ((bnd_ndr1_0 & bnd_c1_1 bnd_a114) &
% 7.10/6.66 ~ bnd_c4_1 bnd_a114) &
% 7.10/6.66 ~ bnd_c5_1 bnd_a114)) &
% 7.10/6.66 ((ALL X124.
% 7.10/6.66 bnd_ndr1_0 -->
% 7.10/6.66 (bnd_c1_1 X124 | ~ bnd_c5_1 X124) |
% 7.10/6.66 (ALL X125.
% 7.10/6.66 bnd_ndr1_1 X124 -->
% 7.10/6.66 (bnd_c2_2 X124 X125 | bnd_c4_2 X124 X125) |
% 7.10/6.66 ~ bnd_c1_2 X124 X125)) |
% 7.10/6.66 (ALL X126.
% 7.10/6.66 bnd_ndr1_0 -->
% 7.10/6.66 (bnd_c5_1 X126 |
% 7.10/6.66 ((bnd_ndr1_1 X126 & bnd_c1_2 X126 bnd_a115) &
% 7.10/6.66 bnd_c2_2 X126 bnd_a115) &
% 7.10/6.66 ~ bnd_c4_2 X126 bnd_a115) |
% 7.10/6.66 ((bnd_ndr1_1 X126 & bnd_c4_2 X126 bnd_a116) &
% 7.10/6.66 ~ bnd_c1_2 X126 bnd_a116) &
% 7.10/6.66 ~ bnd_c5_2 X126 bnd_a116))) &
% 7.10/6.66 (((ALL X127.
% 7.10/6.66 bnd_ndr1_0 -->
% 7.10/6.66 (bnd_c1_1 X127 |
% 7.10/6.66 (ALL X128.
% 7.10/6.66 bnd_ndr1_1 X127 -->
% 7.10/6.66 bnd_c4_2 X127 X128 |
% 7.10/6.66 ~ bnd_c1_2 X127 X128)) |
% 7.10/6.66 (bnd_ndr1_1 X127 & bnd_c1_2 X127 bnd_a117) &
% 7.10/6.66 ~ bnd_c5_2 X127 bnd_a117) |
% 7.10/6.66 (ALL X129.
% 7.10/6.66 bnd_ndr1_0 -->
% 7.10/6.66 (bnd_c2_1 X129 | bnd_c4_1 X129) |
% 7.10/6.66 ~ bnd_c3_1 X129)) |
% 7.10/6.66 (bnd_ndr1_0 & bnd_c5_1 bnd_a118) &
% 7.10/6.66 ~ bnd_c3_1 bnd_a118)) &
% 7.10/6.66 (((ALL X130.
% 7.10/6.66 bnd_ndr1_0 -->
% 7.10/6.66 (bnd_c2_1 X130 | bnd_c3_1 X130) |
% 7.10/6.66 (bnd_ndr1_1 X130 & ~ bnd_c3_2 X130 bnd_a119) &
% 7.10/6.66 ~ bnd_c4_2 X130 bnd_a119) |
% 7.10/6.66 ((bnd_ndr1_0 & ~ bnd_c3_1 bnd_a120) &
% 7.10/6.66 ~ bnd_c4_1 bnd_a120) &
% 7.10/6.66 (ALL X131.
% 7.10/6.66 bnd_ndr1_1 bnd_a120 -->
% 7.10/6.66 (bnd_c1_2 bnd_a120 X131 |
% 7.10/6.66 bnd_c3_2 bnd_a120 X131) |
% 7.10/6.66 bnd_c5_2 bnd_a120 X131)) |
% 7.10/6.66 (bnd_ndr1_0 & ~ bnd_c5_1 bnd_a121) &
% 7.10/6.66 (ALL X132.
% 7.10/6.66 bnd_ndr1_1 bnd_a121 -->
% 7.10/6.66 bnd_c3_2 bnd_a121 X132 |
% 7.10/6.66 ~ bnd_c1_2 bnd_a121 X132))) &
% 7.10/6.66 (((ALL X133.
% 7.10/6.66 bnd_ndr1_0 -->
% 7.10/6.66 bnd_c2_1 X133 |
% 7.10/6.66 (ALL X134.
% 7.10/6.66 bnd_ndr1_1 X133 -->
% 7.10/6.66 (bnd_c4_2 X133 X134 | bnd_c5_2 X133 X134) |
% 7.10/6.66 ~ bnd_c3_2 X133 X134)) |
% 7.10/6.66 (ALL X135.
% 7.10/6.66 bnd_ndr1_0 -->
% 7.10/6.66 bnd_c5_1 X135 |
% 7.10/6.66 (ALL X136.
% 7.10/6.66 bnd_ndr1_1 X135 -->
% 7.10/6.66 bnd_c1_2 X135 X136 | ~ bnd_c2_2 X135 X136))) |
% 7.10/6.66 ((bnd_ndr1_0 & bnd_c3_1 bnd_a122) &
% 7.10/6.66 ~ bnd_c1_1 bnd_a122) &
% 7.10/6.66 ~ bnd_c2_1 bnd_a122)) &
% 7.10/6.66 ((ALL X137.
% 7.10/6.66 bnd_ndr1_0 -->
% 7.10/6.66 (bnd_c3_1 X137 | ~ bnd_c2_1 X137) |
% 7.10/6.66 (ALL X138.
% 7.10/6.66 bnd_ndr1_1 X137 -->
% 7.10/6.66 (bnd_c1_2 X137 X138 | bnd_c4_2 X137 X138) |
% 7.10/6.66 ~ bnd_c2_2 X137 X138)) |
% 7.10/6.66 ((bnd_ndr1_0 & bnd_c5_1 bnd_a123) &
% 7.10/6.66 ~ bnd_c4_1 bnd_a123) &
% 7.10/6.66 (ALL X139.
% 7.10/6.66 bnd_ndr1_1 bnd_a123 -->
% 7.10/6.66 (bnd_c2_2 bnd_a123 X139 | bnd_c4_2 bnd_a123 X139) |
% 7.10/6.66 ~ bnd_c1_2 bnd_a123 X139))) &
% 7.10/6.66 ((ALL X140.
% 7.10/6.66 bnd_ndr1_0 -->
% 7.10/6.66 (bnd_c4_1 X140 | ~ bnd_c2_1 X140) |
% 7.10/6.66 ((bnd_ndr1_1 X140 & bnd_c1_2 X140 bnd_a124) &
% 7.10/6.66 bnd_c3_2 X140 bnd_a124) &
% 7.10/6.66 bnd_c5_2 X140 bnd_a124) |
% 7.10/6.66 ((bnd_ndr1_0 & bnd_ndr1_1 bnd_a125) &
% 7.10/6.66 bnd_c3_2 bnd_a125 bnd_a126) &
% 7.10/6.66 ~ bnd_c4_2 bnd_a125 bnd_a126)) &
% 7.10/6.66 (((ALL X141.
% 7.10/6.66 bnd_ndr1_0 --> bnd_c5_1 X141 | ~ bnd_c1_1 X141) |
% 7.10/6.66 ((bnd_ndr1_0 & bnd_c4_1 bnd_a127) & bnd_c5_1 bnd_a127) &
% 7.10/6.66 ~ bnd_c3_1 bnd_a127) |
% 7.10/6.66 ((bnd_ndr1_0 & bnd_c5_1 bnd_a128) &
% 7.10/6.66 (ALL X142.
% 7.10/6.66 bnd_ndr1_1 bnd_a128 -->
% 7.10/6.66 bnd_c3_2 bnd_a128 X142 | bnd_c4_2 bnd_a128 X142)) &
% 7.10/6.66 (ALL X143.
% 7.10/6.66 bnd_ndr1_1 bnd_a128 -->
% 7.10/6.66 (bnd_c5_2 bnd_a128 X143 | ~ bnd_c3_2 bnd_a128 X143) |
% 7.10/6.66 ~ bnd_c4_2 bnd_a128 X143))) &
% 7.10/6.66 ((ALL X144.
% 7.10/6.66 bnd_ndr1_0 -->
% 7.10/6.66 (bnd_c5_1 X144 | ~ bnd_c4_1 X144) |
% 7.10/6.66 ((bnd_ndr1_1 X144 & ~ bnd_c3_2 X144 bnd_a129) &
% 7.10/6.66 ~ bnd_c4_2 X144 bnd_a129) &
% 7.10/6.66 ~ bnd_c5_2 X144 bnd_a129) |
% 7.10/6.66 ((bnd_ndr1_0 & ~ bnd_c1_1 bnd_a130) & ~ bnd_c5_1 bnd_a130) &
% 7.10/6.66 (ALL X145.
% 7.10/6.66 bnd_ndr1_1 bnd_a130 -->
% 7.10/6.66 (bnd_c1_2 bnd_a130 X145 | bnd_c4_2 bnd_a130 X145) |
% 7.10/6.66 bnd_c5_2 bnd_a130 X145))) &
% 7.10/6.66 (((ALL X146.
% 7.10/6.66 bnd_ndr1_0 --> ~ bnd_c1_1 X146 | ~ bnd_c4_1 X146) |
% 7.10/6.66 (bnd_ndr1_0 & bnd_c1_1 bnd_a131) &
% 7.10/6.66 (ALL X147.
% 7.10/6.66 bnd_ndr1_1 bnd_a131 -->
% 7.10/6.66 (bnd_c1_2 bnd_a131 X147 | bnd_c4_2 bnd_a131 X147) |
% 7.10/6.66 ~ bnd_c3_2 bnd_a131 X147)) |
% 7.10/6.66 (bnd_ndr1_0 & ~ bnd_c1_1 bnd_a132) & ~ bnd_c3_1 bnd_a132)) &
% 7.10/6.66 (((ALL X148.
% 7.10/6.66 bnd_ndr1_0 -->
% 7.10/6.66 (~ bnd_c1_1 X148 |
% 7.10/6.66 (ALL X149.
% 7.10/6.66 bnd_ndr1_1 X148 -->
% 7.10/6.66 (bnd_c1_2 X148 X149 | bnd_c5_2 X148 X149) |
% 7.10/6.66 ~ bnd_c2_2 X148 X149)) |
% 7.10/6.66 ((bnd_ndr1_1 X148 & bnd_c4_2 X148 bnd_a133) &
% 7.10/6.66 bnd_c5_2 X148 bnd_a133) &
% 7.10/6.66 ~ bnd_c1_2 X148 bnd_a133) |
% 7.10/6.66 (ALL X150.
% 7.10/6.66 bnd_ndr1_0 -->
% 7.10/6.66 (ALL X151.
% 7.10/6.66 bnd_ndr1_1 X150 -->
% 7.10/6.66 bnd_c3_2 X150 X151 | ~ bnd_c4_2 X150 X151) |
% 7.10/6.66 (bnd_ndr1_1 X150 & bnd_c2_2 X150 bnd_a134) &
% 7.10/6.66 ~ bnd_c3_2 X150 bnd_a134)) |
% 7.10/6.66 (bnd_ndr1_0 & bnd_c5_1 bnd_a135) & ~ bnd_c3_1 bnd_a135)) &
% 7.10/6.66 (((ALL X152.
% 7.10/6.66 bnd_ndr1_0 -->
% 7.10/6.66 (~ bnd_c1_1 X152 |
% 7.10/6.66 ((bnd_ndr1_1 X152 & bnd_c1_2 X152 bnd_a136) &
% 7.10/6.66 bnd_c5_2 X152 bnd_a136) &
% 7.10/6.66 ~ bnd_c2_2 X152 bnd_a136) |
% 7.10/6.66 ((bnd_ndr1_1 X152 & bnd_c4_2 X152 bnd_a137) &
% 7.10/6.66 ~ bnd_c1_2 X152 bnd_a137) &
% 7.10/6.66 ~ bnd_c5_2 X152 bnd_a137) |
% 7.10/6.66 (ALL X153.
% 7.10/6.66 bnd_ndr1_0 -->
% 7.10/6.66 ~ bnd_c3_1 X153 |
% 7.10/6.66 ((bnd_ndr1_1 X153 & bnd_c5_2 X153 bnd_a138) &
% 7.10/6.66 ~ bnd_c1_2 X153 bnd_a138) &
% 7.10/6.66 ~ bnd_c2_2 X153 bnd_a138)) |
% 7.10/6.66 (bnd_ndr1_0 & bnd_c2_1 bnd_a139) & ~ bnd_c1_1 bnd_a139)) &
% 7.10/6.66 (((ALL X154.
% 7.10/6.66 bnd_ndr1_0 -->
% 7.10/6.66 ~ bnd_c2_1 X154 |
% 7.10/6.66 (ALL X155.
% 7.10/6.66 bnd_ndr1_1 X154 -->
% 7.10/6.66 (bnd_c4_2 X154 X155 | ~ bnd_c1_2 X154 X155) |
% 7.10/6.66 ~ bnd_c3_2 X154 X155)) |
% 7.10/6.66 (ALL X156.
% 7.10/6.66 bnd_ndr1_0 -->
% 7.10/6.66 (ALL X157.
% 7.10/6.66 bnd_ndr1_1 X156 -->
% 7.10/6.66 (bnd_c1_2 X156 X157 | bnd_c2_2 X156 X157) |
% 7.10/6.66 bnd_c3_2 X156 X157) |
% 7.10/6.66 (ALL X158.
% 7.10/6.66 bnd_ndr1_1 X156 -->
% 7.10/6.66 bnd_c3_2 X156 X158 | bnd_c4_2 X156 X158))) |
% 7.10/6.66 ((bnd_ndr1_0 & ~ bnd_c1_1 bnd_a140) & ~ bnd_c5_1 bnd_a140) &
% 7.10/6.66 (ALL X159.
% 7.10/6.66 bnd_ndr1_1 bnd_a140 -->
% 7.10/6.66 bnd_c2_2 bnd_a140 X159 | ~ bnd_c4_2 bnd_a140 X159))) &
% 7.10/6.66 (((ALL X160.
% 7.10/6.66 bnd_ndr1_0 -->
% 7.10/6.67 (~ bnd_c3_1 X160 |
% 7.10/6.67 (ALL X161.
% 7.10/6.67 bnd_ndr1_1 X160 -->
% 7.10/6.67 (bnd_c4_2 X160 X161 | ~ bnd_c1_2 X160 X161) |
% 7.10/6.67 ~ bnd_c3_2 X160 X161)) |
% 7.10/6.67 (ALL X162.
% 7.10/6.67 bnd_ndr1_1 X160 -->
% 7.10/6.67 (bnd_c4_2 X160 X162 | ~ bnd_c2_2 X160 X162) |
% 7.10/6.67 ~ bnd_c5_2 X160 X162)) |
% 7.10/6.67 (ALL X163.
% 7.10/6.67 bnd_ndr1_0 -->
% 7.10/6.67 ((ALL X164.
% 7.10/6.67 bnd_ndr1_1 X163 -->
% 7.10/6.67 ~ bnd_c1_2 X163 X164 | ~ bnd_c3_2 X163 X164) |
% 7.10/6.67 (ALL X165.
% 7.10/6.67 bnd_ndr1_1 X163 -->
% 7.10/6.67 (~ bnd_c2_2 X163 X165 | ~ bnd_c4_2 X163 X165) |
% 7.10/6.67 ~ bnd_c5_2 X163 X165)) |
% 7.10/6.67 (bnd_ndr1_1 X163 & bnd_c1_2 X163 bnd_a141) &
% 7.10/6.67 bnd_c4_2 X163 bnd_a141)) |
% 7.10/6.67 (bnd_ndr1_0 &
% 7.10/6.67 (ALL X166.
% 7.10/6.67 bnd_ndr1_1 bnd_a142 -->
% 7.10/6.67 (bnd_c2_2 bnd_a142 X166 | bnd_c3_2 bnd_a142 X166) |
% 7.10/6.67 bnd_c5_2 bnd_a142 X166)) &
% 7.10/6.67 (ALL X167.
% 7.10/6.67 bnd_ndr1_1 bnd_a142 -->
% 7.10/6.67 (bnd_c4_2 bnd_a142 X167 | ~ bnd_c2_2 bnd_a142 X167) |
% 7.10/6.67 ~ bnd_c3_2 bnd_a142 X167))) &
% 7.10/6.67 (((ALL X168.
% 7.10/6.67 bnd_ndr1_0 -->
% 7.10/6.67 (ALL X169.
% 7.10/6.67 bnd_ndr1_1 X168 -->
% 7.10/6.67 (bnd_c3_2 X168 X169 | bnd_c5_2 X168 X169) |
% 7.10/6.67 ~ bnd_c1_2 X168 X169) |
% 7.10/6.67 ((bnd_ndr1_1 X168 & bnd_c1_2 X168 bnd_a143) &
% 7.10/6.67 bnd_c2_2 X168 bnd_a143) &
% 7.10/6.67 bnd_c4_2 X168 bnd_a143) |
% 7.10/6.67 ((bnd_ndr1_0 & bnd_c4_1 bnd_a144) &
% 7.10/6.67 (ALL X170.
% 7.10/6.67 bnd_ndr1_1 bnd_a144 -->
% 7.10/6.67 (bnd_c2_2 bnd_a144 X170 | bnd_c3_2 bnd_a144 X170) |
% 7.10/6.67 bnd_c4_2 bnd_a144 X170)) &
% 7.10/6.67 (ALL X171.
% 7.10/6.67 bnd_ndr1_1 bnd_a144 -->
% 7.10/6.67 (bnd_c2_2 bnd_a144 X171 | bnd_c4_2 bnd_a144 X171) |
% 7.10/6.67 ~ bnd_c1_2 bnd_a144 X171)) |
% 7.10/6.67 (bnd_ndr1_0 & ~ bnd_c1_1 bnd_a145) &
% 7.10/6.67 (ALL X172.
% 7.10/6.67 bnd_ndr1_1 bnd_a145 -->
% 7.10/6.67 bnd_c3_2 bnd_a145 X172 | ~ bnd_c1_2 bnd_a145 X172))) &
% 7.10/6.67 ((((bnd_ndr1_0 & bnd_c1_1 bnd_a146) & bnd_c3_1 bnd_a146) &
% 7.10/6.67 (ALL X173.
% 7.10/6.67 bnd_ndr1_1 bnd_a146 -->
% 7.10/6.67 (bnd_c2_2 bnd_a146 X173 | ~ bnd_c3_2 bnd_a146 X173) |
% 7.10/6.67 ~ bnd_c4_2 bnd_a146 X173) |
% 7.10/6.67 (((((bnd_ndr1_0 & ~ bnd_c3_1 bnd_a147) & ~ bnd_c4_1 bnd_a147) &
% 7.10/6.67 bnd_ndr1_1 bnd_a147) &
% 7.10/6.67 bnd_c2_2 bnd_a147 bnd_a148) &
% 7.10/6.67 bnd_c4_2 bnd_a147 bnd_a148) &
% 7.10/6.67 ~ bnd_c3_2 bnd_a147 bnd_a148) |
% 7.10/6.67 (((((((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a149) &
% 7.10/6.67 bnd_c2_2 bnd_a149 bnd_a150) &
% 7.10/6.67 bnd_c3_2 bnd_a149 bnd_a150) &
% 7.10/6.67 ~ bnd_c4_2 bnd_a149 bnd_a150) &
% 7.10/6.67 bnd_ndr1_1 bnd_a149) &
% 7.10/6.67 bnd_c3_2 bnd_a149 bnd_a151) &
% 7.10/6.67 ~ bnd_c2_2 bnd_a149 bnd_a151) &
% 7.10/6.67 ~ bnd_c5_2 bnd_a149 bnd_a151) &
% 7.10/6.67 bnd_ndr1_1 bnd_a149) &
% 7.10/6.67 ~ bnd_c1_2 bnd_a149 bnd_a152) &
% 7.10/6.67 ~ bnd_c2_2 bnd_a149 bnd_a152) &
% 7.10/6.67 ~ bnd_c4_2 bnd_a149 bnd_a152)) &
% 7.10/6.67 (((bnd_ndr1_0 & bnd_c1_1 bnd_a153) & bnd_c5_1 bnd_a153 |
% 7.10/6.67 (((((bnd_ndr1_0 & bnd_c1_1 bnd_a154) & ~ bnd_c4_1 bnd_a154) &
% 7.10/6.67 bnd_ndr1_1 bnd_a154) &
% 7.10/6.67 bnd_c4_2 bnd_a154 bnd_a155) &
% 7.10/6.67 ~ bnd_c3_2 bnd_a154 bnd_a155) &
% 7.10/6.67 ~ bnd_c5_2 bnd_a154 bnd_a155) |
% 7.10/6.67 ((((bnd_ndr1_0 & bnd_c2_1 bnd_a156) & ~ bnd_c4_1 bnd_a156) &
% 7.10/6.67 bnd_ndr1_1 bnd_a156) &
% 7.10/6.67 bnd_c2_2 bnd_a156 bnd_a157) &
% 7.10/6.67 ~ bnd_c5_2 bnd_a156 bnd_a157)) &
% 7.10/6.67 (((bnd_ndr1_0 & bnd_c1_1 bnd_a158) & ~ bnd_c2_1 bnd_a158) &
% 7.10/6.67 (ALL X174.
% 7.10/6.67 bnd_ndr1_1 bnd_a158 -->
% 7.10/6.67 (bnd_c1_2 bnd_a158 X174 | bnd_c2_2 bnd_a158 X174) |
% 7.10/6.67 ~ bnd_c3_2 bnd_a158 X174) |
% 7.10/6.67 ((bnd_ndr1_0 & bnd_c3_1 bnd_a159) & bnd_c4_1 bnd_a159) &
% 7.10/6.67 bnd_c5_1 bnd_a159)) &
% 7.10/6.67 (((bnd_ndr1_0 & bnd_c2_1 bnd_a160) & bnd_c3_1 bnd_a160 |
% 7.10/6.67 (((((bnd_ndr1_0 & bnd_c2_1 bnd_a161) & ~ bnd_c4_1 bnd_a161) &
% 7.10/6.67 bnd_ndr1_1 bnd_a161) &
% 7.10/6.67 bnd_c1_2 bnd_a161 bnd_a162) &
% 7.10/6.67 bnd_c2_2 bnd_a161 bnd_a162) &
% 7.10/6.67 bnd_c5_2 bnd_a161 bnd_a162) |
% 7.10/6.67 bnd_ndr1_0 &
% 7.10/6.67 (ALL X175.
% 7.10/6.67 bnd_ndr1_1 bnd_a163 -->
% 7.10/6.67 (bnd_c4_2 bnd_a163 X175 | bnd_c5_2 bnd_a163 X175) |
% 7.10/6.67 ~ bnd_c1_2 bnd_a163 X175))) &
% 7.10/6.67 ((((((((bnd_ndr1_0 & bnd_c3_1 bnd_a164) & bnd_ndr1_1 bnd_a164) &
% 7.10/6.67 bnd_c1_2 bnd_a164 bnd_a165) &
% 7.10/6.67 bnd_c4_2 bnd_a164 bnd_a165) &
% 7.10/6.67 bnd_ndr1_1 bnd_a164) &
% 7.10/6.67 bnd_c3_2 bnd_a164 bnd_a166) &
% 7.10/6.67 bnd_c5_2 bnd_a164 bnd_a166 |
% 7.10/6.67 ((bnd_ndr1_0 & ~ bnd_c1_1 bnd_a167) & ~ bnd_c4_1 bnd_a167) &
% 7.10/6.67 (ALL X176.
% 7.10/6.67 bnd_ndr1_1 bnd_a167 -->
% 7.10/6.67 (bnd_c2_2 bnd_a167 X176 | bnd_c5_2 bnd_a167 X176) |
% 7.10/6.67 ~ bnd_c1_2 bnd_a167 X176)) |
% 7.10/6.67 ((((((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a168) &
% 7.10/6.67 bnd_c1_2 bnd_a168 bnd_a169) &
% 7.10/6.67 ~ bnd_c3_2 bnd_a168 bnd_a169) &
% 7.10/6.67 ~ bnd_c4_2 bnd_a168 bnd_a169) &
% 7.10/6.67 bnd_ndr1_1 bnd_a168) &
% 7.10/6.67 bnd_c3_2 bnd_a168 bnd_a170) &
% 7.10/6.67 bnd_c5_2 bnd_a168 bnd_a170) &
% 7.10/6.67 ~ bnd_c1_2 bnd_a168 bnd_a170) &
% 7.10/6.67 bnd_ndr1_1 bnd_a168) &
% 7.10/6.67 ~ bnd_c2_2 bnd_a168 bnd_a171) &
% 7.10/6.67 ~ bnd_c3_2 bnd_a168 bnd_a171)) &
% 7.10/6.67 (((bnd_ndr1_0 & bnd_c5_1 bnd_a172) &
% 7.10/6.67 (ALL X177.
% 7.10/6.67 bnd_ndr1_1 bnd_a172 -->
% 7.10/6.67 bnd_c2_2 bnd_a172 X177 | bnd_c5_2 bnd_a172 X177)) &
% 7.10/6.67 (ALL X178.
% 7.10/6.67 bnd_ndr1_1 bnd_a172 -->
% 7.10/6.67 (bnd_c2_2 bnd_a172 X178 | bnd_c5_2 bnd_a172 X178) |
% 7.10/6.67 ~ bnd_c4_2 bnd_a172 X178) |
% 7.10/6.67 ((((bnd_ndr1_0 & ~ bnd_c2_1 bnd_a173) & ~ bnd_c5_1 bnd_a173) &
% 7.10/6.67 bnd_ndr1_1 bnd_a173) &
% 7.10/6.67 ~ bnd_c3_2 bnd_a173 bnd_a174) &
% 7.10/6.67 ~ bnd_c5_2 bnd_a173 bnd_a174))
% 15.92/15.46 Unfolded term: ~ (((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((bnd_c1_0 &
% 15.92/15.46 ((bnd_c2_0 | bnd_c3_0) | ~ bnd_c4_0)) &
% 15.92/15.46 ((bnd_c2_0 | bnd_c3_0) |
% 15.92/15.46 (ALL U. bnd_ndr1_0 --> bnd_c2_1 U))) &
% 15.92/15.46 ((bnd_c2_0 | bnd_c3_0) |
% 15.92/15.46 (bnd_ndr1_0 &
% 15.92/15.46 (ALL V.
% 15.92/15.46 bnd_ndr1_1 bnd_a1 -->
% 15.92/15.46 (bnd_c1_2 bnd_a1 V | bnd_c2_2 bnd_a1 V) |
% 15.92/15.46 bnd_c3_2 bnd_a1 V)) &
% 15.92/15.46 (ALL W.
% 15.92/15.46 bnd_ndr1_1 bnd_a1 -->
% 15.92/15.46 bnd_c3_2 bnd_a1 W | ~ bnd_c5_2 bnd_a1 W))) &
% 15.92/15.46 ((bnd_c2_0 | bnd_c5_0) | ~ bnd_c4_0)) &
% 15.92/15.46 (bnd_c2_0 | ~ bnd_c4_0)) &
% 15.92/15.46 (bnd_c2_0 |
% 15.92/15.46 (((bnd_ndr1_0 & bnd_c5_1 bnd_a2) & bnd_ndr1_1 bnd_a2) &
% 15.92/15.46 bnd_c5_2 bnd_a2 bnd_a3) &
% 15.92/15.46 ~ bnd_c4_2 bnd_a2 bnd_a3)) &
% 15.92/15.46 ((bnd_c2_0 | ~ bnd_c3_0) |
% 15.92/15.46 (ALL X.
% 15.92/15.46 bnd_ndr1_0 -->
% 15.92/15.46 (bnd_c1_1 X | bnd_c2_1 X) |
% 15.92/15.46 (bnd_ndr1_1 X & bnd_c2_2 X bnd_a4) &
% 15.92/15.46 ~ bnd_c4_2 X bnd_a4))) &
% 15.92/15.46 ((bnd_c2_0 | ~ bnd_c3_0) |
% 15.92/15.46 (ALL Y.
% 15.92/15.46 bnd_ndr1_0 -->
% 15.92/15.46 (bnd_c2_1 Y | ~ bnd_c1_1 Y) |
% 15.92/15.46 ((bnd_ndr1_1 Y & bnd_c4_2 Y bnd_a5) &
% 15.92/15.46 bnd_c5_2 Y bnd_a5) &
% 15.92/15.46 ~ bnd_c3_2 Y bnd_a5))) &
% 15.92/15.46 ((bnd_c2_0 |
% 15.92/15.46 (ALL Z.
% 15.92/15.46 bnd_ndr1_0 -->
% 15.92/15.46 (bnd_c1_1 Z | ~ bnd_c5_1 Z) |
% 15.92/15.46 ((bnd_ndr1_1 Z & bnd_c2_2 Z bnd_a6) &
% 15.92/15.46 bnd_c4_2 Z bnd_a6) &
% 15.92/15.46 ~ bnd_c1_2 Z bnd_a6)) |
% 15.92/15.46 (((((bnd_ndr1_0 & ~ bnd_c1_1 bnd_a7) &
% 15.92/15.46 (ALL X1.
% 15.92/15.46 bnd_ndr1_1 bnd_a7 -->
% 15.92/15.46 bnd_c2_2 bnd_a7 X1 | bnd_c5_2 bnd_a7 X1)) &
% 15.92/15.46 bnd_ndr1_1 bnd_a7) &
% 15.92/15.46 bnd_c4_2 bnd_a7 bnd_a8) &
% 15.92/15.46 bnd_c5_2 bnd_a7 bnd_a8) &
% 15.92/15.46 ~ bnd_c1_2 bnd_a7 bnd_a8)) &
% 15.92/15.46 ((bnd_c2_0 |
% 15.92/15.46 (ALL X2.
% 15.92/15.46 bnd_ndr1_0 -->
% 15.92/15.46 (~ bnd_c1_1 X2 |
% 15.92/15.46 (ALL X3.
% 15.92/15.46 bnd_ndr1_1 X2 -->
% 15.92/15.46 (bnd_c1_2 X2 X3 | bnd_c3_2 X2 X3) |
% 15.92/15.46 ~ bnd_c5_2 X2 X3)) |
% 15.92/15.46 ((bnd_ndr1_1 X2 & bnd_c1_2 X2 bnd_a9) &
% 15.92/15.46 ~ bnd_c2_2 X2 bnd_a9) &
% 15.92/15.46 ~ bnd_c3_2 X2 bnd_a9)) |
% 15.92/15.46 ((((bnd_ndr1_0 & ~ bnd_c1_1 bnd_a10) &
% 15.92/15.46 (ALL X4.
% 15.92/15.46 bnd_ndr1_1 bnd_a10 -->
% 15.92/15.46 (bnd_c5_2 bnd_a10 X4 | ~ bnd_c1_2 bnd_a10 X4) |
% 15.92/15.46 ~ bnd_c4_2 bnd_a10 X4)) &
% 15.92/15.46 bnd_ndr1_1 bnd_a10) &
% 15.92/15.46 ~ bnd_c3_2 bnd_a10 bnd_a11) &
% 15.92/15.46 ~ bnd_c5_2 bnd_a10 bnd_a11)) &
% 15.92/15.46 ((bnd_c2_0 |
% 15.92/15.46 (ALL X5.
% 15.92/15.46 bnd_ndr1_0 -->
% 15.92/15.46 (~ bnd_c2_1 X5 | ~ bnd_c3_1 X5) | ~ bnd_c5_1 X5)) |
% 15.92/15.46 (ALL X6.
% 15.92/15.46 bnd_ndr1_0 -->
% 15.92/15.46 (~ bnd_c2_1 X6 |
% 15.92/15.46 ((bnd_ndr1_1 X6 & bnd_c1_2 X6 bnd_a12) &
% 15.92/15.46 bnd_c2_2 X6 bnd_a12) &
% 15.92/15.46 ~ bnd_c3_2 X6 bnd_a12) |
% 15.92/15.46 ((bnd_ndr1_1 X6 & ~ bnd_c2_2 X6 bnd_a13) &
% 15.92/15.46 ~ bnd_c4_2 X6 bnd_a13) &
% 15.92/15.46 ~ bnd_c5_2 X6 bnd_a13))) &
% 15.92/15.46 ((bnd_c2_0 |
% 15.92/15.46 (ALL X7.
% 15.92/15.46 bnd_ndr1_0 -->
% 15.92/15.46 (~ bnd_c2_1 X7 |
% 15.92/15.46 (bnd_ndr1_1 X7 & ~ bnd_c2_2 X7 bnd_a14) &
% 15.92/15.46 ~ bnd_c4_2 X7 bnd_a14) |
% 15.92/15.46 (bnd_ndr1_1 X7 & ~ bnd_c4_2 X7 bnd_a15) &
% 15.92/15.46 ~ bnd_c5_2 X7 bnd_a15)) |
% 15.92/15.46 ((((bnd_ndr1_0 & bnd_c5_1 bnd_a16) &
% 15.92/15.46 (ALL X8.
% 15.92/15.46 bnd_ndr1_1 bnd_a16 -->
% 15.92/15.46 bnd_c4_2 bnd_a16 X8 | bnd_c5_2 bnd_a16 X8)) &
% 15.92/15.46 bnd_ndr1_1 bnd_a16) &
% 15.92/15.46 bnd_c5_2 bnd_a16 bnd_a17) &
% 15.92/15.46 ~ bnd_c1_2 bnd_a16 bnd_a17)) &
% 15.92/15.46 ((bnd_c2_0 |
% 15.92/15.46 (ALL X9.
% 15.92/15.46 bnd_ndr1_0 -->
% 15.92/15.46 (~ bnd_c3_1 X9 | ~ bnd_c4_1 X9) |
% 15.92/15.46 (bnd_ndr1_1 X9 & bnd_c2_2 X9 bnd_a18) &
% 15.92/15.46 bnd_c5_2 X9 bnd_a18)) |
% 15.92/15.46 ((bnd_ndr1_0 & bnd_c3_1 bnd_a19) &
% 15.92/15.46 (ALL X10.
% 15.92/15.46 bnd_ndr1_1 bnd_a19 -->
% 15.92/15.46 (bnd_c2_2 bnd_a19 X10 | bnd_c4_2 bnd_a19 X10) |
% 15.92/15.46 ~ bnd_c5_2 bnd_a19 X10)) &
% 15.92/15.46 (ALL X11.
% 15.92/15.46 bnd_ndr1_1 bnd_a19 -->
% 15.92/15.46 (bnd_c3_2 bnd_a19 X11 | ~ bnd_c4_2 bnd_a19 X11) |
% 15.92/15.46 ~ bnd_c5_2 bnd_a19 X11))) &
% 15.92/15.46 ((bnd_c2_0 |
% 15.92/15.46 (ALL X12.
% 15.92/15.46 bnd_ndr1_0 -->
% 15.92/15.46 (~ bnd_c4_1 X12 |
% 15.92/15.46 (ALL X13.
% 15.92/15.46 bnd_ndr1_1 X12 -->
% 15.92/15.46 (bnd_c2_2 X12 X13 | bnd_c4_2 X12 X13) |
% 15.92/15.46 ~ bnd_c5_2 X12 X13)) |
% 15.92/15.46 (ALL X14.
% 15.92/15.46 bnd_ndr1_1 X12 -->
% 15.92/15.46 (bnd_c4_2 X12 X14 | ~ bnd_c1_2 X12 X14) |
% 15.92/15.46 ~ bnd_c3_2 X12 X14))) |
% 15.92/15.46 (((((bnd_ndr1_0 & bnd_c1_1 bnd_a20) & ~ bnd_c2_1 bnd_a20) &
% 15.92/15.46 bnd_ndr1_1 bnd_a20) &
% 15.92/15.46 ~ bnd_c2_2 bnd_a20 bnd_a21) &
% 15.92/15.46 ~ bnd_c3_2 bnd_a20 bnd_a21) &
% 15.92/15.46 ~ bnd_c4_2 bnd_a20 bnd_a21)) &
% 15.92/15.46 (bnd_c2_0 |
% 15.92/15.46 (ALL X15.
% 15.92/15.46 bnd_ndr1_0 -->
% 15.92/15.46 (~ bnd_c4_1 X15 |
% 15.92/15.46 (ALL X16.
% 15.92/15.46 bnd_ndr1_1 X15 -->
% 15.92/15.46 (bnd_c3_2 X15 X16 | bnd_c4_2 X15 X16) |
% 15.92/15.46 bnd_c5_2 X15 X16)) |
% 15.92/15.46 (bnd_ndr1_1 X15 & bnd_c3_2 X15 bnd_a22) &
% 15.92/15.46 ~ bnd_c2_2 X15 bnd_a22))) &
% 15.92/15.46 (bnd_c2_0 |
% 15.92/15.46 (((((bnd_ndr1_0 & ~ bnd_c4_1 bnd_a23) &
% 15.92/15.46 (ALL X17.
% 15.92/15.46 bnd_ndr1_1 bnd_a23 -->
% 15.92/15.46 (bnd_c1_2 bnd_a23 X17 | bnd_c3_2 bnd_a23 X17) |
% 15.92/15.46 bnd_c5_2 bnd_a23 X17)) &
% 15.92/15.46 bnd_ndr1_1 bnd_a23) &
% 15.92/15.46 bnd_c2_2 bnd_a23 bnd_a24) &
% 15.92/15.46 bnd_c3_2 bnd_a23 bnd_a24) &
% 15.92/15.46 ~ bnd_c1_2 bnd_a23 bnd_a24)) &
% 15.92/15.46 ((bnd_c3_0 | bnd_c5_0) |
% 15.92/15.46 (ALL X18.
% 15.92/15.46 bnd_ndr1_0 -->
% 15.92/15.46 ~ bnd_c4_1 X18 |
% 15.92/15.46 ((bnd_ndr1_1 X18 & bnd_c3_2 X18 bnd_a25) &
% 15.92/15.46 ~ bnd_c2_2 X18 bnd_a25) &
% 15.92/15.46 ~ bnd_c4_2 X18 bnd_a25))) &
% 15.92/15.46 ((bnd_c3_0 | bnd_c5_0) |
% 15.92/15.46 (bnd_ndr1_0 & ~ bnd_c1_1 bnd_a26) &
% 15.92/15.46 (ALL X19.
% 15.92/15.46 bnd_ndr1_1 bnd_a26 -->
% 15.92/15.46 (bnd_c2_2 bnd_a26 X19 | bnd_c5_2 bnd_a26 X19) |
% 15.92/15.46 ~ bnd_c3_2 bnd_a26 X19))) &
% 15.92/15.46 (bnd_c3_0 | (bnd_ndr1_0 & bnd_c1_1 bnd_a27) & ~ bnd_c2_1 bnd_a27)) &
% 15.92/15.46 ((bnd_c3_0 | ~ bnd_c2_0) |
% 15.92/15.46 (ALL X20.
% 15.92/15.46 bnd_ndr1_0 -->
% 15.92/15.46 (bnd_c3_1 X20 |
% 15.92/15.46 (ALL X21.
% 15.92/15.46 bnd_ndr1_1 X20 -->
% 15.92/15.46 (bnd_c3_2 X20 X21 | bnd_c4_2 X20 X21) | ~ bnd_c5_2 X20 X21)) |
% 15.92/15.46 ((bnd_ndr1_1 X20 & bnd_c1_2 X20 bnd_a28) &
% 15.92/15.46 ~ bnd_c3_2 X20 bnd_a28) &
% 15.92/15.46 ~ bnd_c4_2 X20 bnd_a28))) &
% 15.92/15.46 ((bnd_c3_0 | ~ bnd_c2_0) |
% 15.92/15.46 (((bnd_ndr1_0 & ~ bnd_c1_1 bnd_a29) & bnd_ndr1_1 bnd_a29) &
% 15.92/15.46 bnd_c3_2 bnd_a29 bnd_a30) &
% 15.92/15.46 ~ bnd_c5_2 bnd_a29 bnd_a30)) &
% 15.92/15.46 ((bnd_c3_0 | ~ bnd_c4_0) |
% 15.92/15.46 (ALL X22.
% 15.92/15.46 bnd_ndr1_0 -->
% 15.92/15.46 ((bnd_ndr1_1 X22 & bnd_c2_2 X22 bnd_a31) & ~ bnd_c4_2 X22 bnd_a31) &
% 15.92/15.46 ~ bnd_c5_2 X22 bnd_a31 |
% 15.92/15.46 (bnd_ndr1_1 X22 & bnd_c4_2 X22 bnd_a32) & bnd_c5_2 X22 bnd_a32))) &
% 15.92/15.46 ((bnd_c3_0 | ~ bnd_c5_0) |
% 15.92/15.46 (ALL X23.
% 15.92/15.46 bnd_ndr1_0 -->
% 15.92/15.46 (bnd_c1_1 X23 | bnd_c2_1 X23) |
% 15.92/15.46 (ALL X24. bnd_ndr1_1 X23 --> bnd_c2_2 X23 X24 | bnd_c5_2 X23 X24)))) &
% 15.92/15.46 ((bnd_c3_0 | ~ bnd_c5_0) |
% 15.92/15.46 ((bnd_ndr1_0 & bnd_c2_1 bnd_a33) & bnd_c5_1 bnd_a33) &
% 15.92/15.46 (ALL X25.
% 15.92/15.46 bnd_ndr1_1 bnd_a33 -->
% 15.92/15.46 (bnd_c3_2 bnd_a33 X25 | bnd_c4_2 bnd_a33 X25) |
% 15.92/15.46 ~ bnd_c1_2 bnd_a33 X25))) &
% 15.92/15.46 ((bnd_c3_0 | ~ bnd_c5_0) |
% 15.92/15.46 (((((bnd_ndr1_0 & ~ bnd_c2_1 bnd_a34) &
% 15.92/15.46 (ALL X26.
% 15.92/15.46 bnd_ndr1_1 bnd_a34 -->
% 15.92/15.46 (bnd_c2_2 bnd_a34 X26 | bnd_c5_2 bnd_a34 X26) |
% 15.92/15.46 ~ bnd_c1_2 bnd_a34 X26)) &
% 15.92/15.46 bnd_ndr1_1 bnd_a34) &
% 15.92/15.46 bnd_c2_2 bnd_a34 bnd_a35) &
% 15.92/15.46 bnd_c5_2 bnd_a34 bnd_a35) &
% 15.92/15.46 ~ bnd_c1_2 bnd_a34 bnd_a35)) &
% 15.92/15.46 (bnd_c3_0 |
% 15.92/15.46 (ALL X27.
% 15.92/15.46 bnd_ndr1_0 --> (bnd_c1_1 X27 | bnd_c2_1 X27) | ~ bnd_c5_1 X27))) &
% 15.92/15.46 ((bnd_c3_0 |
% 15.92/15.46 (ALL X28.
% 15.92/15.46 bnd_ndr1_0 -->
% 15.92/15.46 (bnd_c2_1 X28 | bnd_c4_1 X28) |
% 15.92/15.46 (ALL X29.
% 15.92/15.46 bnd_ndr1_1 X28 -->
% 15.92/15.46 (bnd_c2_2 X28 X29 | bnd_c3_2 X28 X29) | ~ bnd_c1_2 X28 X29))) |
% 15.92/15.46 (ALL X30.
% 15.92/15.46 bnd_ndr1_0 -->
% 15.92/15.46 (ALL X31. bnd_ndr1_1 X30 --> bnd_c1_2 X30 X31 | bnd_c3_2 X30 X31) |
% 15.92/15.46 ((bnd_ndr1_1 X30 & bnd_c3_2 X30 bnd_a36) & ~ bnd_c1_2 X30 bnd_a36) &
% 15.92/15.46 ~ bnd_c2_2 X30 bnd_a36))) &
% 15.92/15.46 ((bnd_c3_0 |
% 15.92/15.46 (ALL X32.
% 15.92/15.46 bnd_ndr1_0 -->
% 15.92/15.46 (bnd_c3_1 X32 | ~ bnd_c5_1 X32) |
% 15.92/15.46 (ALL X33. bnd_ndr1_1 X32 --> ~ bnd_c2_2 X32 X33 | ~ bnd_c5_2 X32 X33))) |
% 15.92/15.46 (ALL X34.
% 15.92/15.46 bnd_ndr1_0 -->
% 15.92/15.46 ((ALL X35.
% 15.92/15.46 bnd_ndr1_1 X34 -->
% 15.92/15.46 (bnd_c2_2 X34 X35 | ~ bnd_c1_2 X34 X35) | ~ bnd_c4_2 X34 X35) |
% 15.92/15.46 (ALL X36.
% 15.92/15.46 bnd_ndr1_1 X34 -->
% 15.92/15.46 (~ bnd_c2_2 X34 X36 | ~ bnd_c3_2 X34 X36) | ~ bnd_c5_2 X34 X36)) |
% 15.92/15.46 (ALL X37.
% 15.92/15.46 bnd_ndr1_1 X34 -->
% 15.92/15.46 (~ bnd_c3_2 X34 X37 | ~ bnd_c4_2 X34 X37) | ~ bnd_c5_2 X34 X37)))) &
% 15.92/15.46 (bnd_c3_0 |
% 15.92/15.46 (ALL X38.
% 15.92/15.46 bnd_ndr1_0 -->
% 15.92/15.46 (bnd_c4_1 X38 | ~ bnd_c2_1 X38) |
% 15.92/15.46 (ALL X39.
% 15.92/15.46 bnd_ndr1_1 X38 -->
% 15.92/15.46 (~ bnd_c2_2 X38 X39 | ~ bnd_c4_2 X38 X39) | ~ bnd_c5_2 X38 X39)))) &
% 15.92/15.46 ((bnd_c3_0 |
% 15.92/15.46 (ALL X40.
% 15.92/15.46 bnd_ndr1_0 -->
% 15.92/15.46 (~ bnd_c4_1 X40 | ~ bnd_c5_1 X40) |
% 15.92/15.46 ((bnd_ndr1_1 X40 & ~ bnd_c2_2 X40 bnd_a37) & ~ bnd_c3_2 X40 bnd_a37) &
% 15.92/15.46 ~ bnd_c4_2 X40 bnd_a37)) |
% 15.92/15.46 ((((bnd_ndr1_0 & ~ bnd_c1_1 bnd_a38) &
% 15.92/15.46 (ALL X41.
% 15.92/15.46 bnd_ndr1_1 bnd_a38 -->
% 15.92/15.46 (bnd_c4_2 bnd_a38 X41 | bnd_c5_2 bnd_a38 X41) | ~ bnd_c3_2 bnd_a38 X41)) &
% 15.92/15.46 bnd_ndr1_1 bnd_a38) &
% 15.92/15.46 bnd_c3_2 bnd_a38 bnd_a39) &
% 15.92/15.46 ~ bnd_c5_2 bnd_a38 bnd_a39)) &
% 15.92/15.46 ((bnd_c3_0 |
% 15.92/15.46 (ALL X42.
% 15.92/15.46 bnd_ndr1_0 -->
% 15.92/15.46 (~ bnd_c4_1 X42 |
% 15.92/15.46 (ALL X43. bnd_ndr1_1 X42 --> ~ bnd_c1_2 X42 X43 | ~ bnd_c4_2 X42 X43)) |
% 15.92/15.46 ((bnd_ndr1_1 X42 &
% 15.92/15.46 bnd_c1_2 X42 bnd_a40) &
% 15.92/15.46 bnd_c4_2 X42 bnd_a40) &
% 15.92/15.46 ~ bnd_c3_2 X42 bnd_a40)) |
% 15.92/15.46 ((bnd_ndr1_0 & bnd_c2_1 bnd_a41) &
% 15.92/15.46 bnd_c5_1 bnd_a41) &
% 15.92/15.46 (ALL X44.
% 15.92/15.46 bnd_ndr1_1 bnd_a41 -->
% 15.92/15.46 ~ bnd_c3_2 bnd_a41 X44 |
% 15.92/15.46 ~ bnd_c5_2 bnd_a41 X44))) &
% 15.92/15.46 ((bnd_c3_0 |
% 15.92/15.46 (ALL X45.
% 15.92/15.46 bnd_ndr1_0 -->
% 15.92/15.46 (ALL X46.
% 15.92/15.46 bnd_ndr1_1 X45 -->
% 15.92/15.46 (bnd_c2_2 X45 X46 | bnd_c4_2 X45 X46) | ~ bnd_c1_2 X45 X46) |
% 15.92/15.46 ((bnd_ndr1_1 X45 &
% 15.92/15.46 bnd_c3_2 X45 bnd_a42) &
% 15.92/15.46 bnd_c4_2 X45 bnd_a42) &
% 15.92/15.46 ~ bnd_c2_2 X45 bnd_a42)) |
% 15.92/15.46 ((bnd_ndr1_0 & bnd_c4_1 bnd_a43) &
% 15.92/15.46 bnd_c5_1 bnd_a43) &
% 15.92/15.46 (ALL X47.
% 15.92/15.46 bnd_ndr1_1 bnd_a43 -->
% 15.92/15.46 (bnd_c1_2 bnd_a43 X47 |
% 15.92/15.46 ~ bnd_c3_2 bnd_a43 X47) |
% 15.92/15.46 ~ bnd_c4_2 bnd_a43 X47))) &
% 15.92/15.46 (bnd_c3_0 |
% 15.92/15.46 (ALL X48.
% 15.92/15.46 bnd_ndr1_0 -->
% 15.92/15.46 ((bnd_ndr1_1 X48 & bnd_c3_2 X48 bnd_a44) &
% 15.92/15.46 ~ bnd_c2_2 X48 bnd_a44) &
% 15.92/15.46 ~ bnd_c4_2 X48 bnd_a44 |
% 15.92/15.46 (bnd_ndr1_1 X48 & bnd_c5_2 X48 bnd_a45) &
% 15.92/15.46 ~ bnd_c4_2 X48 bnd_a45))) &
% 15.92/15.46 (bnd_c3_0 |
% 15.92/15.46 ((bnd_ndr1_0 & bnd_c1_1 bnd_a46) &
% 15.92/15.46 bnd_c2_1 bnd_a46) &
% 15.92/15.46 (ALL X49.
% 15.92/15.46 bnd_ndr1_1 bnd_a46 -->
% 15.92/15.46 bnd_c4_2 bnd_a46 X49 |
% 15.92/15.46 ~ bnd_c2_2 bnd_a46 X49))) &
% 15.92/15.46 (bnd_c3_0 |
% 15.92/15.46 ((bnd_ndr1_0 & ~ bnd_c1_1 bnd_a47) &
% 15.92/15.46 (ALL X50.
% 15.92/15.46 bnd_ndr1_1 bnd_a47 -->
% 15.92/15.46 (bnd_c1_2 bnd_a47 X50 |
% 15.92/15.46 bnd_c4_2 bnd_a47 X50) |
% 15.92/15.46 bnd_c5_2 bnd_a47 X50)) &
% 15.92/15.46 (ALL X51.
% 15.92/15.46 bnd_ndr1_1 bnd_a47 -->
% 15.92/15.46 bnd_c1_2 bnd_a47 X51 |
% 15.92/15.46 ~ bnd_c5_2 bnd_a47 X51))) &
% 15.92/15.46 ((bnd_c3_0 |
% 15.92/15.46 (bnd_ndr1_0 &
% 15.92/15.46 (ALL X52.
% 15.92/15.46 bnd_ndr1_1 bnd_a48 -->
% 15.92/15.46 bnd_c1_2 bnd_a48 X52 |
% 15.92/15.46 ~ bnd_c3_2 bnd_a48 X52)) &
% 15.92/15.46 (ALL X53.
% 15.92/15.46 bnd_ndr1_1 bnd_a48 -->
% 15.92/15.46 bnd_c3_2 bnd_a48 X53 |
% 15.92/15.46 ~ bnd_c2_2 bnd_a48 X53)) |
% 15.92/15.46 bnd_ndr1_0 &
% 15.92/15.46 (ALL X54.
% 15.92/15.46 bnd_ndr1_1 bnd_a49 -->
% 15.92/15.46 (bnd_c1_2 bnd_a49 X54 |
% 15.92/15.46 bnd_c2_2 bnd_a49 X54) |
% 15.92/15.46 bnd_c4_2 bnd_a49 X54))) &
% 15.92/15.46 (bnd_c4_0 | bnd_c5_0)) &
% 15.92/15.46 ((bnd_c4_0 | bnd_c5_0) |
% 15.92/15.46 (ALL X55.
% 15.92/15.46 bnd_ndr1_0 -->
% 15.92/15.46 (bnd_c2_1 X55 | ~ bnd_c1_1 X55) |
% 15.92/15.46 (bnd_ndr1_1 X55 & bnd_c2_2 X55 bnd_a50) &
% 15.92/15.46 bnd_c3_2 X55 bnd_a50))) &
% 15.92/15.46 ((bnd_c4_0 | bnd_c5_0) |
% 15.92/15.46 (ALL X56.
% 15.92/15.46 bnd_ndr1_0 -->
% 15.92/15.46 (~ bnd_c3_1 X56 |
% 15.92/15.46 (ALL X57.
% 15.92/15.46 bnd_ndr1_1 X56 -->
% 15.92/15.46 (bnd_c1_2 X56 X57 | ~ bnd_c2_2 X56 X57) |
% 15.92/15.46 ~ bnd_c5_2 X56 X57)) |
% 15.92/15.46 (ALL X58.
% 15.92/15.46 bnd_ndr1_1 X56 -->
% 15.92/15.46 (bnd_c3_2 X56 X58 | bnd_c4_2 X56 X58) |
% 15.92/15.46 ~ bnd_c5_2 X56 X58)))) &
% 15.92/15.46 bnd_c4_0) &
% 15.92/15.46 (bnd_c5_0 |
% 15.92/15.46 (((((bnd_ndr1_0 & ~ bnd_c4_1 bnd_a51) &
% 15.92/15.46 (ALL X59.
% 15.92/15.46 bnd_ndr1_1 bnd_a51 -->
% 15.92/15.46 (bnd_c2_2 bnd_a51 X59 |
% 15.92/15.46 bnd_c4_2 bnd_a51 X59) |
% 15.92/15.46 ~ bnd_c3_2 bnd_a51 X59)) &
% 15.92/15.46 bnd_ndr1_1 bnd_a51) &
% 15.92/15.46 bnd_c2_2 bnd_a51 bnd_a52) &
% 15.92/15.46 bnd_c3_2 bnd_a51 bnd_a52) &
% 15.92/15.46 ~ bnd_c4_2 bnd_a51 bnd_a52)) &
% 15.92/15.46 (bnd_c5_0 | ~ bnd_c3_0)) &
% 15.92/15.46 ((bnd_c5_0 |
% 15.92/15.46 (ALL X60.
% 15.92/15.46 bnd_ndr1_0 -->
% 15.92/15.46 (bnd_c1_1 X60 |
% 15.92/15.46 (ALL X61.
% 15.92/15.46 bnd_ndr1_1 X60 -->
% 15.92/15.46 bnd_c1_2 X60 X61 | bnd_c3_2 X60 X61)) |
% 15.92/15.47 (ALL X62.
% 15.92/15.47 bnd_ndr1_1 X60 -->
% 15.92/15.47 bnd_c3_2 X60 X62 | bnd_c4_2 X60 X62))) |
% 15.92/15.47 (ALL X63.
% 15.92/15.47 bnd_ndr1_0 -->
% 15.92/15.47 (~ bnd_c2_1 X63 | ~ bnd_c5_1 X63) |
% 15.92/15.47 (bnd_ndr1_1 X63 & bnd_c2_2 X63 bnd_a53) &
% 15.92/15.47 ~ bnd_c4_2 X63 bnd_a53))) &
% 15.92/15.47 ((bnd_c5_0 |
% 15.92/15.47 (ALL X64.
% 15.92/15.47 bnd_ndr1_0 -->
% 15.92/15.47 (bnd_c3_1 X64 | bnd_c4_1 X64) | ~ bnd_c5_1 X64)) |
% 15.92/15.47 (bnd_ndr1_0 & bnd_c3_1 bnd_a54) & bnd_c4_1 bnd_a54)) &
% 15.92/15.47 (~ bnd_c2_0 |
% 15.92/15.47 (ALL X65.
% 15.92/15.47 bnd_ndr1_0 -->
% 15.92/15.47 ((ALL X66.
% 15.92/15.47 bnd_ndr1_1 X65 -->
% 15.92/15.47 (bnd_c5_2 X65 X66 | ~ bnd_c1_2 X65 X66) |
% 15.92/15.47 ~ bnd_c4_2 X65 X66) |
% 15.92/15.47 (ALL X67.
% 15.92/15.47 bnd_ndr1_1 X65 -->
% 15.92/15.47 (~ bnd_c3_2 X65 X67 | ~ bnd_c4_2 X65 X67) |
% 15.92/15.47 ~ bnd_c5_2 X65 X67)) |
% 15.92/15.47 (bnd_ndr1_1 X65 & ~ bnd_c1_2 X65 bnd_a55) &
% 15.92/15.47 ~ bnd_c4_2 X65 bnd_a55))) &
% 15.92/15.47 ~ bnd_c3_0) &
% 15.92/15.47 (ALL X68.
% 15.92/15.47 bnd_ndr1_0 -->
% 15.92/15.47 (bnd_c5_1 X68 | ~ bnd_c4_1 X68) |
% 15.92/15.47 ((bnd_ndr1_1 X68 & bnd_c1_2 X68 bnd_a56) &
% 15.92/15.47 bnd_c5_2 X68 bnd_a56) &
% 15.92/15.47 ~ bnd_c3_2 X68 bnd_a56)) &
% 15.92/15.47 (~ bnd_c5_0 |
% 15.92/15.47 (ALL X69.
% 15.92/15.47 bnd_ndr1_0 -->
% 15.92/15.47 (~ bnd_c3_1 X69 |
% 15.92/15.47 (ALL X70.
% 15.92/15.47 bnd_ndr1_1 X69 -->
% 15.92/15.47 (~ bnd_c2_2 X69 X70 | ~ bnd_c3_2 X69 X70) |
% 15.92/15.47 ~ bnd_c4_2 X69 X70)) |
% 15.92/15.47 ((bnd_ndr1_1 X69 & bnd_c2_2 X69 bnd_a57) &
% 15.92/15.47 bnd_c4_2 X69 bnd_a57) &
% 15.92/15.47 bnd_c5_2 X69 bnd_a57))) &
% 15.92/15.47 ((ALL X71. bnd_ndr1_0 --> bnd_c1_1 X71 | bnd_c3_1 X71) |
% 15.92/15.47 (ALL X72.
% 15.92/15.47 bnd_ndr1_0 -->
% 15.92/15.47 (~ bnd_c2_1 X72 |
% 15.92/15.47 (ALL X73.
% 15.92/15.47 bnd_ndr1_1 X72 -->
% 15.92/15.47 (bnd_c1_2 X72 X73 | bnd_c4_2 X72 X73) |
% 15.92/15.47 ~ bnd_c5_2 X72 X73)) |
% 15.92/15.47 (ALL X74.
% 15.92/15.47 bnd_ndr1_1 X72 -->
% 15.92/15.47 (~ bnd_c1_2 X72 X74 | ~ bnd_c2_2 X72 X74) |
% 15.92/15.47 ~ bnd_c3_2 X72 X74)))) &
% 15.92/15.47 ((ALL X75.
% 15.92/15.47 bnd_ndr1_0 -->
% 15.92/15.47 (bnd_c4_1 X75 | ~ bnd_c5_1 X75) |
% 15.92/15.47 (ALL X76. bnd_ndr1_1 X75 --> ~ bnd_c2_2 X75 X76)) |
% 15.92/15.47 ((bnd_ndr1_0 & bnd_c4_1 bnd_a58) & ~ bnd_c2_1 bnd_a58) &
% 15.92/15.47 (ALL X77.
% 15.92/15.47 bnd_ndr1_1 bnd_a58 -->
% 15.92/15.47 (bnd_c1_2 bnd_a58 X77 | bnd_c2_2 bnd_a58 X77) |
% 15.92/15.47 bnd_c5_2 bnd_a58 X77))) &
% 15.92/15.47 (ALL X78.
% 15.92/15.47 bnd_ndr1_0 -->
% 15.92/15.47 (bnd_c4_1 X78 |
% 15.92/15.47 (bnd_ndr1_1 X78 & bnd_c2_2 X78 bnd_a59) &
% 15.92/15.47 bnd_c3_2 X78 bnd_a59) |
% 15.92/15.47 ((bnd_ndr1_1 X78 & ~ bnd_c2_2 X78 bnd_a60) &
% 15.92/15.47 ~ bnd_c4_2 X78 bnd_a60) &
% 15.92/15.47 ~ bnd_c5_2 X78 bnd_a60)) &
% 15.92/15.47 ((ALL X79.
% 15.92/15.47 bnd_ndr1_0 -->
% 15.92/15.47 (~ bnd_c1_1 X79 |
% 15.92/15.47 (ALL X80.
% 15.92/15.47 bnd_ndr1_1 X79 -->
% 15.92/15.47 bnd_c3_2 X79 X80 | ~ bnd_c1_2 X79 X80)) |
% 15.92/15.47 (ALL X81.
% 15.92/15.47 bnd_ndr1_1 X79 -->
% 15.92/15.47 bnd_c4_2 X79 X81 | ~ bnd_c5_2 X79 X81)) |
% 15.92/15.47 ((((((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a61) &
% 15.92/15.47 bnd_c1_2 bnd_a61 bnd_a62) &
% 15.92/15.47 bnd_c4_2 bnd_a61 bnd_a62) &
% 15.92/15.47 ~ bnd_c2_2 bnd_a61 bnd_a62) &
% 15.92/15.47 bnd_ndr1_1 bnd_a61) &
% 15.92/15.47 bnd_c1_2 bnd_a61 bnd_a63) &
% 15.92/15.47 ~ bnd_c4_2 bnd_a61 bnd_a63) &
% 15.92/15.47 ~ bnd_c5_2 bnd_a61 bnd_a63) &
% 15.92/15.47 bnd_ndr1_1 bnd_a61) &
% 15.92/15.47 ~ bnd_c3_2 bnd_a61 bnd_a64) &
% 15.92/15.47 ~ bnd_c4_2 bnd_a61 bnd_a64)) &
% 15.92/15.47 ((ALL X82.
% 15.92/15.47 bnd_ndr1_0 -->
% 15.92/15.47 ~ bnd_c4_1 X82 |
% 15.92/15.47 (bnd_ndr1_1 X82 & bnd_c1_2 X82 bnd_a65) &
% 15.92/15.47 bnd_c2_2 X82 bnd_a65) |
% 15.92/15.47 ((((bnd_ndr1_0 & bnd_c5_1 bnd_a66) & bnd_ndr1_1 bnd_a66) &
% 15.92/15.47 bnd_c3_2 bnd_a66 bnd_a67) &
% 15.92/15.47 bnd_c5_2 bnd_a66 bnd_a67) &
% 15.92/15.47 ~ bnd_c2_2 bnd_a66 bnd_a67)) &
% 15.92/15.47 ((ALL X83.
% 15.92/15.47 bnd_ndr1_0 -->
% 15.92/15.47 ((ALL X84.
% 15.92/15.47 bnd_ndr1_1 X83 -->
% 15.92/15.47 (bnd_c2_2 X83 X84 | bnd_c4_2 X83 X84) |
% 15.92/15.47 ~ bnd_c5_2 X83 X84) |
% 15.92/15.47 ((bnd_ndr1_1 X83 & bnd_c1_2 X83 bnd_a68) &
% 15.92/15.47 bnd_c3_2 X83 bnd_a68) &
% 15.92/15.47 ~ bnd_c2_2 X83 bnd_a68) |
% 15.92/15.47 ((bnd_ndr1_1 X83 & bnd_c3_2 X83 bnd_a69) &
% 15.92/15.47 ~ bnd_c1_2 X83 bnd_a69) &
% 15.92/15.47 ~ bnd_c2_2 X83 bnd_a69) |
% 15.92/15.47 ((bnd_ndr1_0 & bnd_c2_1 bnd_a70) & ~ bnd_c4_1 bnd_a70) &
% 15.92/15.47 ~ bnd_c5_1 bnd_a70)) &
% 15.92/15.47 (((bnd_ndr1_0 & bnd_c3_1 bnd_a71) & ~ bnd_c2_1 bnd_a71) &
% 15.92/15.47 ~ bnd_c5_1 bnd_a71 |
% 15.92/15.47 ((((bnd_ndr1_0 & ~ bnd_c3_1 bnd_a72) & bnd_ndr1_1 bnd_a72) &
% 15.92/15.47 bnd_c2_2 bnd_a72 bnd_a73) &
% 15.92/15.47 bnd_c3_2 bnd_a72 bnd_a73) &
% 15.92/15.47 ~ bnd_c4_2 bnd_a72 bnd_a73)) &
% 15.92/15.47 ((~ bnd_c2_0 |
% 15.92/15.47 (ALL X85.
% 15.92/15.47 bnd_ndr1_0 -->
% 15.92/15.47 (bnd_c2_1 X85 | bnd_c3_1 X85) | ~ bnd_c1_1 X85)) |
% 15.92/15.47 ((((((((bnd_ndr1_0 & bnd_c2_1 bnd_a74) & bnd_ndr1_1 bnd_a74) &
% 15.92/15.47 bnd_c1_2 bnd_a74 bnd_a75) &
% 15.92/15.47 ~ bnd_c4_2 bnd_a74 bnd_a75) &
% 15.92/15.47 ~ bnd_c5_2 bnd_a74 bnd_a75) &
% 15.92/15.47 bnd_ndr1_1 bnd_a74) &
% 15.92/15.47 bnd_c2_2 bnd_a74 bnd_a76) &
% 15.92/15.47 bnd_c3_2 bnd_a74 bnd_a76) &
% 15.92/15.47 ~ bnd_c1_2 bnd_a74 bnd_a76)) &
% 15.92/15.47 ((~ bnd_c2_0 |
% 15.92/15.47 (ALL X86.
% 15.92/15.47 bnd_ndr1_0 -->
% 15.92/15.47 (bnd_c4_1 X86 | ~ bnd_c3_1 X86) |
% 15.92/15.47 (ALL X87.
% 15.92/15.47 bnd_ndr1_1 X86 -->
% 15.92/15.47 (bnd_c2_2 X86 X87 | bnd_c4_2 X86 X87) | bnd_c5_2 X86 X87))) |
% 15.92/15.47 (ALL X88.
% 15.92/15.47 bnd_ndr1_0 -->
% 15.92/15.47 (bnd_c5_1 X88 | ~ bnd_c2_1 X88) | ~ bnd_c3_1 X88))) &
% 15.92/15.47 ((~ bnd_c2_0 |
% 15.92/15.47 (ALL X89.
% 15.92/15.47 bnd_ndr1_0 -->
% 15.92/15.47 (~ bnd_c2_1 X89 |
% 15.92/15.47 (ALL X90.
% 15.92/15.47 bnd_ndr1_1 X89 -->
% 15.92/15.47 ~ bnd_c2_2 X89 X90 | ~ bnd_c3_2 X89 X90)) |
% 15.92/15.47 (bnd_ndr1_1 X89 & bnd_c2_2 X89 bnd_a77) & bnd_c3_2 X89 bnd_a77)) |
% 15.92/15.47 (ALL X91.
% 15.92/15.47 bnd_ndr1_0 -->
% 15.92/15.47 ~ bnd_c4_1 X91 |
% 15.92/15.47 ((bnd_ndr1_1 X91 & bnd_c4_2 X91 bnd_a78) & bnd_c5_2 X91 bnd_a78) &
% 15.92/15.47 ~ bnd_c3_2 X91 bnd_a78))) &
% 15.92/15.47 ((~ bnd_c2_0 |
% 15.92/15.47 (ALL X92.
% 15.92/15.47 bnd_ndr1_0 -->
% 15.92/15.47 (~ bnd_c5_1 X92 |
% 15.92/15.47 (ALL X93.
% 15.92/15.47 bnd_ndr1_1 X92 --> bnd_c1_2 X92 X93 | ~ bnd_c5_2 X92 X93)) |
% 15.92/15.47 (bnd_ndr1_1 X92 & ~ bnd_c2_2 X92 bnd_a79) &
% 15.92/15.47 ~ bnd_c4_2 X92 bnd_a79)) |
% 15.92/15.47 (bnd_ndr1_0 & ~ bnd_c3_1 bnd_a80) & ~ bnd_c5_1 bnd_a80)) &
% 15.92/15.47 ((~ bnd_c2_0 |
% 15.92/15.47 (ALL X94.
% 15.92/15.47 bnd_ndr1_0 -->
% 15.92/15.47 ((ALL X95.
% 15.92/15.47 bnd_ndr1_1 X94 --> bnd_c5_2 X94 X95 | ~ bnd_c4_2 X94 X95) |
% 15.92/15.47 ((bnd_ndr1_1 X94 & bnd_c2_2 X94 bnd_a81) &
% 15.92/15.47 ~ bnd_c1_2 X94 bnd_a81) &
% 15.92/15.47 ~ bnd_c5_2 X94 bnd_a81) |
% 15.92/15.47 ((bnd_ndr1_1 X94 & bnd_c4_2 X94 bnd_a82) & ~ bnd_c1_2 X94 bnd_a82) &
% 15.92/15.47 ~ bnd_c3_2 X94 bnd_a82)) |
% 15.92/15.47 (((((bnd_ndr1_0 & bnd_c2_1 bnd_a83) & ~ bnd_c4_1 bnd_a83) &
% 15.92/15.47 bnd_ndr1_1 bnd_a83) &
% 15.92/15.47 bnd_c1_2 bnd_a83 bnd_a84) &
% 15.92/15.47 bnd_c2_2 bnd_a83 bnd_a84) &
% 15.92/15.47 bnd_c3_2 bnd_a83 bnd_a84)) &
% 15.92/15.47 (~ bnd_c2_0 |
% 15.92/15.47 ((bnd_ndr1_0 & bnd_c3_1 bnd_a85) &
% 15.92/15.47 (ALL X96.
% 15.92/15.47 bnd_ndr1_1 bnd_a85 -->
% 15.92/15.47 (bnd_c3_2 bnd_a85 X96 | ~ bnd_c1_2 bnd_a85 X96) |
% 15.92/15.47 ~ bnd_c4_2 bnd_a85 X96)) &
% 15.92/15.47 (ALL X97.
% 15.92/15.47 bnd_ndr1_1 bnd_a85 -->
% 15.92/15.47 (bnd_c3_2 bnd_a85 X97 | ~ bnd_c1_2 bnd_a85 X97) |
% 15.92/15.47 ~ bnd_c5_2 bnd_a85 X97))) &
% 15.92/15.47 ((~ bnd_c2_0 |
% 15.92/15.47 ((bnd_ndr1_0 & bnd_c4_1 bnd_a86) & bnd_c5_1 bnd_a86) &
% 15.92/15.47 ~ bnd_c1_1 bnd_a86) |
% 15.92/15.47 ((((((((bnd_ndr1_0 & ~ bnd_c4_1 bnd_a87) & bnd_ndr1_1 bnd_a87) &
% 15.92/15.47 bnd_c2_2 bnd_a87 bnd_a88) &
% 15.92/15.47 bnd_c3_2 bnd_a87 bnd_a88) &
% 15.92/15.47 bnd_c5_2 bnd_a87 bnd_a88) &
% 15.92/15.47 bnd_ndr1_1 bnd_a87) &
% 15.92/15.47 bnd_c2_2 bnd_a87 bnd_a89) &
% 15.92/15.47 bnd_c3_2 bnd_a87 bnd_a89) &
% 15.92/15.47 ~ bnd_c4_2 bnd_a87 bnd_a89)) &
% 15.92/15.47 (~ bnd_c2_0 |
% 15.92/15.47 (bnd_ndr1_0 & ~ bnd_c3_1 bnd_a90) & ~ bnd_c4_1 bnd_a90)) &
% 15.92/15.47 (~ bnd_c5_0 |
% 15.92/15.47 (((((bnd_ndr1_0 & bnd_c5_1 bnd_a91) &
% 15.92/15.47 ~ bnd_c4_1 bnd_a91) &
% 15.92/15.47 bnd_ndr1_1 bnd_a91) &
% 15.92/15.47 ~ bnd_c1_2 bnd_a91 bnd_a92) &
% 15.92/15.47 ~ bnd_c2_2 bnd_a91 bnd_a92) &
% 15.92/15.47 ~ bnd_c4_2 bnd_a91 bnd_a92)) &
% 15.92/15.47 (ALL X98.
% 15.92/15.47 bnd_ndr1_0 -->
% 15.92/15.47 (bnd_c2_1 X98 | bnd_c3_1 X98) |
% 15.92/15.47 (ALL X99.
% 15.92/15.47 bnd_ndr1_1 X98 -->
% 15.92/15.47 (bnd_c2_2 X98 X99 | bnd_c3_2 X98 X99) | ~ bnd_c5_2 X98 X99))) &
% 15.92/15.47 ((ALL X100.
% 15.92/15.47 bnd_ndr1_0 -->
% 15.92/15.47 (bnd_c2_1 X100 | ~ bnd_c4_1 X100) |
% 15.92/15.47 (ALL X101.
% 15.92/15.47 bnd_ndr1_1 X100 -->
% 15.92/15.47 (bnd_c3_2 X100 X101 | ~ bnd_c1_2 X100 X101) | ~ bnd_c4_2 X100 X101)) |
% 15.92/15.47 (bnd_ndr1_0 & ~ bnd_c3_1 bnd_a93) &
% 15.92/15.47 (ALL X102.
% 15.92/15.47 bnd_ndr1_1 bnd_a93 -->
% 15.92/15.47 (bnd_c1_2 bnd_a93 X102 | bnd_c5_2 bnd_a93 X102) |
% 15.92/15.47 ~ bnd_c3_2 bnd_a93 X102))) &
% 15.92/15.47 ((ALL X103.
% 15.92/15.47 bnd_ndr1_0 -->
% 15.92/15.47 bnd_c2_1 X103 |
% 15.92/15.47 (ALL X104.
% 15.92/15.47 bnd_ndr1_1 X103 -->
% 15.92/15.47 (bnd_c1_2 X103 X104 | ~ bnd_c3_2 X103 X104) | ~ bnd_c5_2 X103 X104)) |
% 15.92/15.47 ((((bnd_ndr1_0 & bnd_c5_1 bnd_a94) &
% 15.92/15.47 (ALL X105.
% 15.92/15.47 bnd_ndr1_1 bnd_a94 -->
% 15.92/15.47 (bnd_c3_2 bnd_a94 X105 | ~ bnd_c2_2 bnd_a94 X105) |
% 15.92/15.47 ~ bnd_c5_2 bnd_a94 X105)) &
% 15.92/15.47 bnd_ndr1_1 bnd_a94) &
% 15.92/15.47 bnd_c2_2 bnd_a94 bnd_a95) &
% 15.92/15.47 ~ bnd_c4_2 bnd_a94 bnd_a95)) &
% 15.92/15.47 ((ALL X106.
% 15.92/15.47 bnd_ndr1_0 -->
% 15.92/15.47 ~ bnd_c1_1 X106 | ~ bnd_c2_1 X106) |
% 15.92/15.47 ((((bnd_ndr1_0 & ~ bnd_c3_1 bnd_a96) &
% 15.92/15.47 (ALL X107.
% 15.92/15.47 bnd_ndr1_1 bnd_a96 -->
% 15.92/15.47 (bnd_c3_2 bnd_a96 X107 | bnd_c5_2 bnd_a96 X107) |
% 15.92/15.47 ~ bnd_c1_2 bnd_a96 X107)) &
% 15.92/15.47 bnd_ndr1_1 bnd_a96) &
% 15.92/15.47 bnd_c3_2 bnd_a96 bnd_a97) &
% 15.92/15.47 ~ bnd_c5_2 bnd_a96 bnd_a97)) &
% 15.92/15.47 ((ALL X108.
% 15.92/15.47 bnd_ndr1_0 -->
% 15.92/15.47 (~ bnd_c1_1 X108 | ~ bnd_c3_1 X108) |
% 15.92/15.47 ((bnd_ndr1_1 X108 &
% 15.92/15.47 bnd_c1_2 X108 bnd_a98) &
% 15.92/15.47 bnd_c4_2 X108 bnd_a98) &
% 15.92/15.47 bnd_c5_2 X108 bnd_a98) |
% 15.92/15.47 ((bnd_ndr1_0 & ~ bnd_c1_1 bnd_a99) &
% 15.92/15.47 (ALL X109.
% 15.92/15.47 bnd_ndr1_1 bnd_a99 -->
% 15.92/15.47 bnd_c4_2 bnd_a99 X109 |
% 15.92/15.47 ~ bnd_c2_2 bnd_a99 X109)) &
% 15.92/15.47 (ALL X110.
% 15.92/15.47 bnd_ndr1_1 bnd_a99 -->
% 15.92/15.47 (~ bnd_c1_2 bnd_a99 X110 |
% 15.92/15.47 ~ bnd_c2_2 bnd_a99 X110) |
% 15.92/15.47 ~ bnd_c3_2 bnd_a99 X110))) &
% 15.92/15.47 (ALL X111.
% 15.92/15.47 bnd_ndr1_0 -->
% 15.92/15.47 (~ bnd_c3_1 X111 |
% 15.92/15.47 ((bnd_ndr1_1 X111 &
% 15.92/15.47 bnd_c1_2 X111 bnd_a100) &
% 15.92/15.47 bnd_c4_2 X111 bnd_a100) &
% 15.92/15.47 ~ bnd_c3_2 X111 bnd_a100) |
% 15.92/15.47 ((bnd_ndr1_1 X111 &
% 15.92/15.47 bnd_c2_2 X111 bnd_a101) &
% 15.92/15.47 ~ bnd_c3_2 X111 bnd_a101) &
% 15.92/15.47 ~ bnd_c5_2 X111 bnd_a101)) &
% 15.92/15.47 ((bnd_ndr1_0 & bnd_c3_1 bnd_a102) &
% 15.92/15.47 bnd_c5_1 bnd_a102 |
% 15.92/15.47 ((((bnd_ndr1_0 & bnd_c4_1 bnd_a103) &
% 15.92/15.47 ~ bnd_c2_1 bnd_a103) &
% 15.92/15.47 bnd_ndr1_1 bnd_a103) &
% 15.92/15.47 bnd_c4_2 bnd_a103 bnd_a104) &
% 15.92/15.47 ~ bnd_c3_2 bnd_a103 bnd_a104)) &
% 15.92/15.47 ((~ bnd_c5_0 |
% 15.92/15.47 (ALL X112.
% 15.92/15.47 bnd_ndr1_0 -->
% 15.92/15.47 (bnd_c1_1 X112 | bnd_c3_1 X112) |
% 15.92/15.47 (bnd_ndr1_1 X112 &
% 15.92/15.47 ~ bnd_c2_2 X112 bnd_a105) &
% 15.92/15.47 ~ bnd_c3_2 X112 bnd_a105)) |
% 15.92/15.47 (ALL X113.
% 15.92/15.47 bnd_ndr1_0 -->
% 15.92/15.47 ~ bnd_c1_1 X113 |
% 15.92/15.47 (bnd_ndr1_1 X113 &
% 15.92/15.47 bnd_c4_2 X113 bnd_a106) &
% 15.92/15.47 ~ bnd_c1_2 X113 bnd_a106))) &
% 15.92/15.47 (~ bnd_c5_0 |
% 15.92/15.47 (ALL X114.
% 15.92/15.47 bnd_ndr1_0 -->
% 15.92/15.47 (bnd_c2_1 X114 | ~ bnd_c4_1 X114) |
% 15.92/15.47 (ALL X115.
% 15.92/15.47 bnd_ndr1_1 X114 -->
% 15.92/15.47 (bnd_c1_2 X114 X115 |
% 15.92/15.47 bnd_c4_2 X114 X115) |
% 15.92/15.47 ~ bnd_c2_2 X114 X115)))) &
% 15.92/15.47 (~ bnd_c5_0 |
% 15.92/15.47 (ALL X116.
% 15.92/15.47 bnd_ndr1_0 -->
% 15.92/15.47 (bnd_c3_1 X116 |
% 15.92/15.47 (ALL X117.
% 15.92/15.47 bnd_ndr1_1 X116 -->
% 15.92/15.47 (bnd_c1_2 X116 X117 |
% 15.92/15.47 bnd_c3_2 X116 X117) |
% 15.92/15.47 ~ bnd_c5_2 X116 X117)) |
% 15.92/15.47 (ALL X118.
% 15.92/15.47 bnd_ndr1_1 X116 -->
% 15.92/15.47 (bnd_c1_2 X116 X118 |
% 15.92/15.47 bnd_c5_2 X116 X118) |
% 15.92/15.47 ~ bnd_c3_2 X116 X118)))) &
% 15.92/15.47 (~ bnd_c5_0 |
% 15.92/15.47 ((((bnd_ndr1_0 &
% 15.92/15.47 (ALL X119.
% 15.92/15.47 bnd_ndr1_1 bnd_a107 -->
% 15.92/15.47 bnd_c1_2 bnd_a107 X119 |
% 15.92/15.47 bnd_c2_2 bnd_a107 X119)) &
% 15.92/15.47 (ALL X120.
% 15.92/15.47 bnd_ndr1_1 bnd_a107 -->
% 15.92/15.47 (~ bnd_c1_2 bnd_a107 X120 |
% 15.92/15.47 ~ bnd_c3_2 bnd_a107 X120) |
% 15.92/15.47 ~ bnd_c4_2 bnd_a107 X120)) &
% 15.92/15.47 bnd_ndr1_1 bnd_a107) &
% 15.92/15.47 bnd_c4_2 bnd_a107 bnd_a108) &
% 15.92/15.47 ~ bnd_c1_2 bnd_a107 bnd_a108)) &
% 15.92/15.47 (((ALL X121.
% 15.92/15.47 bnd_ndr1_0 -->
% 15.92/15.47 bnd_c0_1 X121 & ~ bnd_c0_1 X121) |
% 15.92/15.47 (bnd_ndr1_0 & bnd_c4_1 bnd_a109) &
% 15.92/15.47 ~ bnd_c1_1 bnd_a109) |
% 15.92/15.47 ((((bnd_ndr1_0 & ~ bnd_c5_1 bnd_a110) &
% 15.92/15.47 bnd_ndr1_1 bnd_a110) &
% 15.92/15.47 bnd_c3_2 bnd_a110 bnd_a111) &
% 15.92/15.47 ~ bnd_c2_2 bnd_a110 bnd_a111) &
% 15.92/15.47 ~ bnd_c5_2 bnd_a110 bnd_a111)) &
% 15.92/15.47 (((ALL X122.
% 15.92/15.47 bnd_ndr1_0 -->
% 15.92/15.47 (bnd_c1_1 X122 | ~ bnd_c2_1 X122) |
% 15.92/15.47 (bnd_ndr1_1 X122 & bnd_c3_2 X122 bnd_a112) &
% 15.92/15.47 ~ bnd_c4_2 X122 bnd_a112) |
% 15.92/15.47 (ALL X123.
% 15.92/15.47 bnd_ndr1_0 -->
% 15.92/15.47 bnd_c5_1 X123 |
% 15.92/15.47 ((bnd_ndr1_1 X123 & bnd_c3_2 X123 bnd_a113) &
% 15.92/15.47 ~ bnd_c4_2 X123 bnd_a113) &
% 15.92/15.47 ~ bnd_c5_2 X123 bnd_a113)) |
% 15.92/15.47 ((bnd_ndr1_0 & bnd_c1_1 bnd_a114) &
% 15.92/15.47 ~ bnd_c4_1 bnd_a114) &
% 15.92/15.47 ~ bnd_c5_1 bnd_a114)) &
% 15.92/15.47 ((ALL X124.
% 15.92/15.47 bnd_ndr1_0 -->
% 15.92/15.47 (bnd_c1_1 X124 | ~ bnd_c5_1 X124) |
% 15.92/15.47 (ALL X125.
% 15.92/15.47 bnd_ndr1_1 X124 -->
% 15.92/15.47 (bnd_c2_2 X124 X125 | bnd_c4_2 X124 X125) |
% 15.92/15.47 ~ bnd_c1_2 X124 X125)) |
% 15.92/15.47 (ALL X126.
% 15.92/15.47 bnd_ndr1_0 -->
% 15.92/15.47 (bnd_c5_1 X126 |
% 15.92/15.47 ((bnd_ndr1_1 X126 & bnd_c1_2 X126 bnd_a115) &
% 15.92/15.47 bnd_c2_2 X126 bnd_a115) &
% 15.92/15.47 ~ bnd_c4_2 X126 bnd_a115) |
% 15.92/15.47 ((bnd_ndr1_1 X126 & bnd_c4_2 X126 bnd_a116) &
% 15.92/15.47 ~ bnd_c1_2 X126 bnd_a116) &
% 15.92/15.47 ~ bnd_c5_2 X126 bnd_a116))) &
% 15.92/15.47 (((ALL X127.
% 15.92/15.47 bnd_ndr1_0 -->
% 15.92/15.47 (bnd_c1_1 X127 |
% 15.92/15.47 (ALL X128.
% 15.92/15.47 bnd_ndr1_1 X127 -->
% 15.92/15.47 bnd_c4_2 X127 X128 |
% 15.92/15.47 ~ bnd_c1_2 X127 X128)) |
% 15.92/15.47 (bnd_ndr1_1 X127 & bnd_c1_2 X127 bnd_a117) &
% 15.92/15.47 ~ bnd_c5_2 X127 bnd_a117) |
% 15.92/15.47 (ALL X129.
% 15.92/15.47 bnd_ndr1_0 -->
% 15.92/15.47 (bnd_c2_1 X129 | bnd_c4_1 X129) |
% 15.92/15.47 ~ bnd_c3_1 X129)) |
% 15.92/15.47 (bnd_ndr1_0 & bnd_c5_1 bnd_a118) &
% 15.92/15.47 ~ bnd_c3_1 bnd_a118)) &
% 15.92/15.47 (((ALL X130.
% 15.92/15.47 bnd_ndr1_0 -->
% 15.92/15.47 (bnd_c2_1 X130 | bnd_c3_1 X130) |
% 15.92/15.47 (bnd_ndr1_1 X130 & ~ bnd_c3_2 X130 bnd_a119) &
% 15.92/15.47 ~ bnd_c4_2 X130 bnd_a119) |
% 15.92/15.47 ((bnd_ndr1_0 & ~ bnd_c3_1 bnd_a120) &
% 15.92/15.47 ~ bnd_c4_1 bnd_a120) &
% 15.92/15.47 (ALL X131.
% 15.92/15.47 bnd_ndr1_1 bnd_a120 -->
% 15.92/15.47 (bnd_c1_2 bnd_a120 X131 |
% 15.92/15.47 bnd_c3_2 bnd_a120 X131) |
% 15.92/15.47 bnd_c5_2 bnd_a120 X131)) |
% 15.92/15.47 (bnd_ndr1_0 & ~ bnd_c5_1 bnd_a121) &
% 15.92/15.47 (ALL X132.
% 15.92/15.47 bnd_ndr1_1 bnd_a121 -->
% 15.92/15.47 bnd_c3_2 bnd_a121 X132 |
% 15.92/15.47 ~ bnd_c1_2 bnd_a121 X132))) &
% 15.92/15.47 (((ALL X133.
% 15.92/15.47 bnd_ndr1_0 -->
% 15.92/15.47 bnd_c2_1 X133 |
% 15.92/15.47 (ALL X134.
% 15.92/15.47 bnd_ndr1_1 X133 -->
% 15.92/15.47 (bnd_c4_2 X133 X134 | bnd_c5_2 X133 X134) |
% 15.92/15.47 ~ bnd_c3_2 X133 X134)) |
% 15.92/15.47 (ALL X135.
% 15.92/15.47 bnd_ndr1_0 -->
% 15.92/15.47 bnd_c5_1 X135 |
% 15.92/15.47 (ALL X136.
% 15.92/15.47 bnd_ndr1_1 X135 -->
% 15.92/15.47 bnd_c1_2 X135 X136 | ~ bnd_c2_2 X135 X136))) |
% 15.92/15.47 ((bnd_ndr1_0 & bnd_c3_1 bnd_a122) &
% 15.92/15.47 ~ bnd_c1_1 bnd_a122) &
% 15.92/15.47 ~ bnd_c2_1 bnd_a122)) &
% 15.92/15.47 ((ALL X137.
% 15.92/15.47 bnd_ndr1_0 -->
% 15.92/15.47 (bnd_c3_1 X137 | ~ bnd_c2_1 X137) |
% 15.92/15.47 (ALL X138.
% 15.92/15.47 bnd_ndr1_1 X137 -->
% 15.92/15.47 (bnd_c1_2 X137 X138 | bnd_c4_2 X137 X138) |
% 15.92/15.47 ~ bnd_c2_2 X137 X138)) |
% 15.92/15.47 ((bnd_ndr1_0 & bnd_c5_1 bnd_a123) &
% 15.92/15.47 ~ bnd_c4_1 bnd_a123) &
% 15.92/15.47 (ALL X139.
% 15.92/15.47 bnd_ndr1_1 bnd_a123 -->
% 15.92/15.47 (bnd_c2_2 bnd_a123 X139 | bnd_c4_2 bnd_a123 X139) |
% 15.92/15.47 ~ bnd_c1_2 bnd_a123 X139))) &
% 15.92/15.47 ((ALL X140.
% 15.92/15.47 bnd_ndr1_0 -->
% 15.92/15.47 (bnd_c4_1 X140 | ~ bnd_c2_1 X140) |
% 15.92/15.47 ((bnd_ndr1_1 X140 & bnd_c1_2 X140 bnd_a124) &
% 15.92/15.47 bnd_c3_2 X140 bnd_a124) &
% 15.92/15.47 bnd_c5_2 X140 bnd_a124) |
% 15.92/15.47 ((bnd_ndr1_0 & bnd_ndr1_1 bnd_a125) &
% 15.92/15.47 bnd_c3_2 bnd_a125 bnd_a126) &
% 15.92/15.47 ~ bnd_c4_2 bnd_a125 bnd_a126)) &
% 15.92/15.47 (((ALL X141.
% 15.92/15.47 bnd_ndr1_0 --> bnd_c5_1 X141 | ~ bnd_c1_1 X141) |
% 15.92/15.47 ((bnd_ndr1_0 & bnd_c4_1 bnd_a127) & bnd_c5_1 bnd_a127) &
% 15.92/15.47 ~ bnd_c3_1 bnd_a127) |
% 15.92/15.47 ((bnd_ndr1_0 & bnd_c5_1 bnd_a128) &
% 15.92/15.47 (ALL X142.
% 15.92/15.47 bnd_ndr1_1 bnd_a128 -->
% 15.92/15.47 bnd_c3_2 bnd_a128 X142 | bnd_c4_2 bnd_a128 X142)) &
% 15.92/15.47 (ALL X143.
% 15.92/15.47 bnd_ndr1_1 bnd_a128 -->
% 15.92/15.47 (bnd_c5_2 bnd_a128 X143 | ~ bnd_c3_2 bnd_a128 X143) |
% 15.92/15.47 ~ bnd_c4_2 bnd_a128 X143))) &
% 15.92/15.47 ((ALL X144.
% 15.92/15.47 bnd_ndr1_0 -->
% 15.92/15.47 (bnd_c5_1 X144 | ~ bnd_c4_1 X144) |
% 15.92/15.47 ((bnd_ndr1_1 X144 & ~ bnd_c3_2 X144 bnd_a129) &
% 15.92/15.47 ~ bnd_c4_2 X144 bnd_a129) &
% 15.92/15.47 ~ bnd_c5_2 X144 bnd_a129) |
% 15.92/15.47 ((bnd_ndr1_0 & ~ bnd_c1_1 bnd_a130) & ~ bnd_c5_1 bnd_a130) &
% 15.92/15.47 (ALL X145.
% 15.92/15.47 bnd_ndr1_1 bnd_a130 -->
% 15.92/15.47 (bnd_c1_2 bnd_a130 X145 | bnd_c4_2 bnd_a130 X145) |
% 15.92/15.47 bnd_c5_2 bnd_a130 X145))) &
% 15.92/15.47 (((ALL X146.
% 15.92/15.47 bnd_ndr1_0 --> ~ bnd_c1_1 X146 | ~ bnd_c4_1 X146) |
% 15.92/15.47 (bnd_ndr1_0 & bnd_c1_1 bnd_a131) &
% 15.92/15.47 (ALL X147.
% 15.92/15.47 bnd_ndr1_1 bnd_a131 -->
% 15.92/15.47 (bnd_c1_2 bnd_a131 X147 | bnd_c4_2 bnd_a131 X147) |
% 15.92/15.47 ~ bnd_c3_2 bnd_a131 X147)) |
% 15.92/15.47 (bnd_ndr1_0 & ~ bnd_c1_1 bnd_a132) & ~ bnd_c3_1 bnd_a132)) &
% 15.92/15.47 (((ALL X148.
% 15.92/15.47 bnd_ndr1_0 -->
% 15.92/15.47 (~ bnd_c1_1 X148 |
% 15.92/15.47 (ALL X149.
% 15.92/15.47 bnd_ndr1_1 X148 -->
% 15.92/15.47 (bnd_c1_2 X148 X149 | bnd_c5_2 X148 X149) |
% 15.92/15.47 ~ bnd_c2_2 X148 X149)) |
% 15.92/15.47 ((bnd_ndr1_1 X148 & bnd_c4_2 X148 bnd_a133) &
% 15.92/15.47 bnd_c5_2 X148 bnd_a133) &
% 15.92/15.47 ~ bnd_c1_2 X148 bnd_a133) |
% 15.92/15.47 (ALL X150.
% 15.92/15.47 bnd_ndr1_0 -->
% 15.92/15.47 (ALL X151.
% 15.92/15.47 bnd_ndr1_1 X150 -->
% 15.92/15.47 bnd_c3_2 X150 X151 | ~ bnd_c4_2 X150 X151) |
% 15.92/15.47 (bnd_ndr1_1 X150 & bnd_c2_2 X150 bnd_a134) &
% 15.92/15.47 ~ bnd_c3_2 X150 bnd_a134)) |
% 15.92/15.47 (bnd_ndr1_0 & bnd_c5_1 bnd_a135) & ~ bnd_c3_1 bnd_a135)) &
% 15.92/15.47 (((ALL X152.
% 15.92/15.47 bnd_ndr1_0 -->
% 15.92/15.47 (~ bnd_c1_1 X152 |
% 15.92/15.47 ((bnd_ndr1_1 X152 & bnd_c1_2 X152 bnd_a136) &
% 15.92/15.47 bnd_c5_2 X152 bnd_a136) &
% 15.92/15.47 ~ bnd_c2_2 X152 bnd_a136) |
% 15.92/15.47 ((bnd_ndr1_1 X152 & bnd_c4_2 X152 bnd_a137) &
% 15.92/15.47 ~ bnd_c1_2 X152 bnd_a137) &
% 15.92/15.47 ~ bnd_c5_2 X152 bnd_a137) |
% 15.92/15.47 (ALL X153.
% 15.92/15.47 bnd_ndr1_0 -->
% 15.92/15.47 ~ bnd_c3_1 X153 |
% 15.92/15.47 ((bnd_ndr1_1 X153 & bnd_c5_2 X153 bnd_a138) &
% 15.92/15.47 ~ bnd_c1_2 X153 bnd_a138) &
% 15.92/15.47 ~ bnd_c2_2 X153 bnd_a138)) |
% 15.92/15.47 (bnd_ndr1_0 & bnd_c2_1 bnd_a139) & ~ bnd_c1_1 bnd_a139)) &
% 15.92/15.47 (((ALL X154.
% 15.92/15.47 bnd_ndr1_0 -->
% 15.92/15.47 ~ bnd_c2_1 X154 |
% 15.92/15.47 (ALL X155.
% 15.92/15.47 bnd_ndr1_1 X154 -->
% 15.92/15.47 (bnd_c4_2 X154 X155 | ~ bnd_c1_2 X154 X155) |
% 15.92/15.47 ~ bnd_c3_2 X154 X155)) |
% 15.92/15.47 (ALL X156.
% 15.92/15.47 bnd_ndr1_0 -->
% 15.92/15.47 (ALL X157.
% 15.92/15.47 bnd_ndr1_1 X156 -->
% 15.92/15.47 (bnd_c1_2 X156 X157 | bnd_c2_2 X156 X157) |
% 15.92/15.47 bnd_c3_2 X156 X157) |
% 15.92/15.47 (ALL X158.
% 15.92/15.47 bnd_ndr1_1 X156 -->
% 15.92/15.47 bnd_c3_2 X156 X158 | bnd_c4_2 X156 X158))) |
% 15.92/15.47 ((bnd_ndr1_0 & ~ bnd_c1_1 bnd_a140) & ~ bnd_c5_1 bnd_a140) &
% 15.92/15.47 (ALL X159.
% 15.92/15.47 bnd_ndr1_1 bnd_a140 -->
% 15.92/15.47 bnd_c2_2 bnd_a140 X159 | ~ bnd_c4_2 bnd_a140 X159))) &
% 15.92/15.47 (((ALL X160.
% 15.92/15.47 bnd_ndr1_0 -->
% 15.92/15.47 (~ bnd_c3_1 X160 |
% 15.92/15.47 (ALL X161.
% 15.92/15.47 bnd_ndr1_1 X160 -->
% 15.92/15.47 (bnd_c4_2 X160 X161 | ~ bnd_c1_2 X160 X161) |
% 15.92/15.47 ~ bnd_c3_2 X160 X161)) |
% 15.92/15.47 (ALL X162.
% 15.92/15.47 bnd_ndr1_1 X160 -->
% 15.92/15.47 (bnd_c4_2 X160 X162 | ~ bnd_c2_2 X160 X162) |
% 15.92/15.47 ~ bnd_c5_2 X160 X162)) |
% 15.92/15.47 (ALL X163.
% 15.92/15.47 bnd_ndr1_0 -->
% 15.92/15.47 ((ALL X164.
% 15.92/15.47 bnd_ndr1_1 X163 -->
% 15.92/15.47 ~ bnd_c1_2 X163 X164 | ~ bnd_c3_2 X163 X164) |
% 15.92/15.47 (ALL X165.
% 15.92/15.47 bnd_ndr1_1 X163 -->
% 15.92/15.47 (~ bnd_c2_2 X163 X165 | ~ bnd_c4_2 X163 X165) |
% 15.92/15.47 ~ bnd_c5_2 X163 X165)) |
% 15.92/15.47 (bnd_ndr1_1 X163 & bnd_c1_2 X163 bnd_a141) &
% 15.92/15.47 bnd_c4_2 X163 bnd_a141)) |
% 15.92/15.47 (bnd_ndr1_0 &
% 15.92/15.47 (ALL X166.
% 15.92/15.47 bnd_ndr1_1 bnd_a142 -->
% 15.92/15.47 (bnd_c2_2 bnd_a142 X166 | bnd_c3_2 bnd_a142 X166) |
% 15.92/15.47 bnd_c5_2 bnd_a142 X166)) &
% 15.92/15.47 (ALL X167.
% 15.92/15.47 bnd_ndr1_1 bnd_a142 -->
% 15.92/15.47 (bnd_c4_2 bnd_a142 X167 | ~ bnd_c2_2 bnd_a142 X167) |
% 15.92/15.47 ~ bnd_c3_2 bnd_a142 X167))) &
% 15.92/15.47 (((ALL X168.
% 15.92/15.47 bnd_ndr1_0 -->
% 15.92/15.47 (ALL X169.
% 15.92/15.47 bnd_ndr1_1 X168 -->
% 15.92/15.47 (bnd_c3_2 X168 X169 | bnd_c5_2 X168 X169) |
% 15.92/15.47 ~ bnd_c1_2 X168 X169) |
% 15.92/15.47 ((bnd_ndr1_1 X168 & bnd_c1_2 X168 bnd_a143) &
% 15.92/15.47 bnd_c2_2 X168 bnd_a143) &
% 15.92/15.47 bnd_c4_2 X168 bnd_a143) |
% 15.92/15.47 ((bnd_ndr1_0 & bnd_c4_1 bnd_a144) &
% 15.92/15.47 (ALL X170.
% 15.92/15.47 bnd_ndr1_1 bnd_a144 -->
% 15.92/15.47 (bnd_c2_2 bnd_a144 X170 | bnd_c3_2 bnd_a144 X170) |
% 15.92/15.47 bnd_c4_2 bnd_a144 X170)) &
% 15.92/15.47 (ALL X171.
% 15.92/15.47 bnd_ndr1_1 bnd_a144 -->
% 15.92/15.47 (bnd_c2_2 bnd_a144 X171 | bnd_c4_2 bnd_a144 X171) |
% 15.92/15.47 ~ bnd_c1_2 bnd_a144 X171)) |
% 15.92/15.47 (bnd_ndr1_0 & ~ bnd_c1_1 bnd_a145) &
% 15.92/15.47 (ALL X172.
% 15.92/15.47 bnd_ndr1_1 bnd_a145 -->
% 15.92/15.47 bnd_c3_2 bnd_a145 X172 | ~ bnd_c1_2 bnd_a145 X172))) &
% 15.92/15.47 ((((bnd_ndr1_0 & bnd_c1_1 bnd_a146) & bnd_c3_1 bnd_a146) &
% 15.92/15.47 (ALL X173.
% 15.92/15.47 bnd_ndr1_1 bnd_a146 -->
% 15.92/15.47 (bnd_c2_2 bnd_a146 X173 | ~ bnd_c3_2 bnd_a146 X173) |
% 15.92/15.47 ~ bnd_c4_2 bnd_a146 X173) |
% 15.92/15.47 (((((bnd_ndr1_0 & ~ bnd_c3_1 bnd_a147) & ~ bnd_c4_1 bnd_a147) &
% 15.92/15.47 bnd_ndr1_1 bnd_a147) &
% 15.92/15.47 bnd_c2_2 bnd_a147 bnd_a148) &
% 15.92/15.47 bnd_c4_2 bnd_a147 bnd_a148) &
% 15.92/15.47 ~ bnd_c3_2 bnd_a147 bnd_a148) |
% 15.92/15.47 (((((((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a149) &
% 15.92/15.47 bnd_c2_2 bnd_a149 bnd_a150) &
% 15.92/15.47 bnd_c3_2 bnd_a149 bnd_a150) &
% 15.92/15.47 ~ bnd_c4_2 bnd_a149 bnd_a150) &
% 15.92/15.47 bnd_ndr1_1 bnd_a149) &
% 15.92/15.47 bnd_c3_2 bnd_a149 bnd_a151) &
% 15.92/15.47 ~ bnd_c2_2 bnd_a149 bnd_a151) &
% 15.92/15.47 ~ bnd_c5_2 bnd_a149 bnd_a151) &
% 15.92/15.47 bnd_ndr1_1 bnd_a149) &
% 15.92/15.47 ~ bnd_c1_2 bnd_a149 bnd_a152) &
% 15.92/15.47 ~ bnd_c2_2 bnd_a149 bnd_a152) &
% 15.92/15.47 ~ bnd_c4_2 bnd_a149 bnd_a152)) &
% 15.92/15.47 (((bnd_ndr1_0 & bnd_c1_1 bnd_a153) & bnd_c5_1 bnd_a153 |
% 15.92/15.47 (((((bnd_ndr1_0 & bnd_c1_1 bnd_a154) & ~ bnd_c4_1 bnd_a154) &
% 15.92/15.47 bnd_ndr1_1 bnd_a154) &
% 15.92/15.47 bnd_c4_2 bnd_a154 bnd_a155) &
% 15.92/15.47 ~ bnd_c3_2 bnd_a154 bnd_a155) &
% 15.92/15.47 ~ bnd_c5_2 bnd_a154 bnd_a155) |
% 15.92/15.47 ((((bnd_ndr1_0 & bnd_c2_1 bnd_a156) & ~ bnd_c4_1 bnd_a156) &
% 15.92/15.47 bnd_ndr1_1 bnd_a156) &
% 15.92/15.47 bnd_c2_2 bnd_a156 bnd_a157) &
% 15.92/15.47 ~ bnd_c5_2 bnd_a156 bnd_a157)) &
% 15.92/15.47 (((bnd_ndr1_0 & bnd_c1_1 bnd_a158) & ~ bnd_c2_1 bnd_a158) &
% 15.92/15.47 (ALL X174.
% 15.92/15.47 bnd_ndr1_1 bnd_a158 -->
% 15.92/15.47 (bnd_c1_2 bnd_a158 X174 | bnd_c2_2 bnd_a158 X174) |
% 15.92/15.47 ~ bnd_c3_2 bnd_a158 X174) |
% 15.92/15.47 ((bnd_ndr1_0 & bnd_c3_1 bnd_a159) & bnd_c4_1 bnd_a159) &
% 15.92/15.47 bnd_c5_1 bnd_a159)) &
% 15.92/15.47 (((bnd_ndr1_0 & bnd_c2_1 bnd_a160) & bnd_c3_1 bnd_a160 |
% 15.92/15.47 (((((bnd_ndr1_0 & bnd_c2_1 bnd_a161) & ~ bnd_c4_1 bnd_a161) &
% 15.92/15.47 bnd_ndr1_1 bnd_a161) &
% 15.92/15.47 bnd_c1_2 bnd_a161 bnd_a162) &
% 15.92/15.47 bnd_c2_2 bnd_a161 bnd_a162) &
% 15.92/15.47 bnd_c5_2 bnd_a161 bnd_a162) |
% 15.92/15.47 bnd_ndr1_0 &
% 15.92/15.47 (ALL X175.
% 15.92/15.47 bnd_ndr1_1 bnd_a163 -->
% 15.92/15.47 (bnd_c4_2 bnd_a163 X175 | bnd_c5_2 bnd_a163 X175) |
% 15.92/15.47 ~ bnd_c1_2 bnd_a163 X175))) &
% 15.92/15.47 ((((((((bnd_ndr1_0 & bnd_c3_1 bnd_a164) & bnd_ndr1_1 bnd_a164) &
% 15.92/15.47 bnd_c1_2 bnd_a164 bnd_a165) &
% 15.92/15.47 bnd_c4_2 bnd_a164 bnd_a165) &
% 15.92/15.47 bnd_ndr1_1 bnd_a164) &
% 15.92/15.47 bnd_c3_2 bnd_a164 bnd_a166) &
% 15.92/15.47 bnd_c5_2 bnd_a164 bnd_a166 |
% 15.92/15.47 ((bnd_ndr1_0 & ~ bnd_c1_1 bnd_a167) & ~ bnd_c4_1 bnd_a167) &
% 15.92/15.47 (ALL X176.
% 15.92/15.47 bnd_ndr1_1 bnd_a167 -->
% 15.92/15.47 (bnd_c2_2 bnd_a167 X176 | bnd_c5_2 bnd_a167 X176) |
% 15.92/15.47 ~ bnd_c1_2 bnd_a167 X176)) |
% 15.92/15.47 ((((((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a168) &
% 15.92/15.47 bnd_c1_2 bnd_a168 bnd_a169) &
% 15.92/15.47 ~ bnd_c3_2 bnd_a168 bnd_a169) &
% 15.92/15.47 ~ bnd_c4_2 bnd_a168 bnd_a169) &
% 15.92/15.47 bnd_ndr1_1 bnd_a168) &
% 15.92/15.47 bnd_c3_2 bnd_a168 bnd_a170) &
% 15.92/15.47 bnd_c5_2 bnd_a168 bnd_a170) &
% 15.92/15.47 ~ bnd_c1_2 bnd_a168 bnd_a170) &
% 15.92/15.47 bnd_ndr1_1 bnd_a168) &
% 15.92/15.47 ~ bnd_c2_2 bnd_a168 bnd_a171) &
% 15.92/15.47 ~ bnd_c3_2 bnd_a168 bnd_a171)) &
% 15.92/15.47 (((bnd_ndr1_0 & bnd_c5_1 bnd_a172) &
% 15.92/15.47 (ALL X177.
% 15.92/15.47 bnd_ndr1_1 bnd_a172 -->
% 15.92/15.47 bnd_c2_2 bnd_a172 X177 | bnd_c5_2 bnd_a172 X177)) &
% 15.92/15.47 (ALL X178.
% 15.92/15.47 bnd_ndr1_1 bnd_a172 -->
% 15.92/15.47 (bnd_c2_2 bnd_a172 X178 | bnd_c5_2 bnd_a172 X178) |
% 15.92/15.47 ~ bnd_c4_2 bnd_a172 X178) |
% 15.92/15.47 ((((bnd_ndr1_0 & ~ bnd_c2_1 bnd_a173) & ~ bnd_c5_1 bnd_a173) &
% 15.92/15.47 bnd_ndr1_1 bnd_a173) &
% 15.92/15.47 ~ bnd_c3_2 bnd_a173 bnd_a174) &
% 15.92/15.47 ~ bnd_c5_2 bnd_a173 bnd_a174))
% 15.92/15.47 Adding axioms...
% 16.01/15.50 Typedef.type_definition_def
% 44.66/44.12 ...done.
% 44.66/44.15 Ground types: ?'b, TPTP_Interpret.ind
% 44.66/44.15 Translating term (sizes: 1, 1) ...
% 67.51/66.99 Invoking SAT solver...
% 67.51/66.99 No model exists.
% 67.51/66.99 Translating term (sizes: 2, 1) ...
% 91.06/90.50 Invoking SAT solver...
% 91.16/90.50 No model exists.
% 91.16/90.50 Translating term (sizes: 1, 2) ...
% 135.13/134.30 Invoking SAT solver...
% 135.13/134.32 No model exists.
% 135.13/134.32 Translating term (sizes: 3, 1) ...
% 161.46/160.53 Invoking SAT solver...
% 161.46/160.54 No model exists.
% 161.46/160.54 Translating term (sizes: 2, 2) ...
% 213.57/212.36 Invoking SAT solver...
% 213.57/212.39 No model exists.
% 213.57/212.39 Translating term (sizes: 1, 3) ...
% 285.79/284.03 Invoking SAT solver...
% 300.01/298.13 /export/starexec/sandbox2/solver/lib/scripts/run-polyml-5.5.2: line 82: 35538 CPU time limit exceeded (core dumped) "$ISABELLE_HOME/lib/scripts/feeder" -p -h "$MLTEXT" -t "$MLEXIT" $FEEDER_OPTS
% 300.01/298.13 35539 (core dumped) | { read FPID; "$POLY" -q -i $ML_OPTIONS; RC="$?"; kill -TERM "$FPID"; exit "$RC"; }
% 300.01/298.14 /export/starexec/sandbox2/solver/src/HOL/TPTP/lib/Tools/tptp_refute: line 26: 35455 Exit 152 "$ISABELLE_PROCESS" -q -e "use_thy \"/tmp/$SCRATCH\"; exit 1;" HOL-TPTP
% 300.01/298.14 35456 CPU time limit exceeded (core dumped) | grep --line-buffered -v "^###\|^PROOF FAILED for depth\|^Failure node\|inferences so far. Searching to depth\|^val \|^Loading theory\|^Warning-The type of\|^ monotype.$"
%------------------------------------------------------------------------------