TSTP Solution File: SYN513+1 by Refute---2015
View Problem
- Process Solution
%------------------------------------------------------------------------------
% File : Refute---2015
% Problem : SYN513+1 : TPTP v6.4.0. Released v2.1.0.
% Transfm : none
% Format : tptp:raw
% Command : isabelle tptp_refute %d %s
% Computer : n073.star.cs.uiowa.edu
% Model : x86_64 x86_64
% CPU : Intel(R) Xeon(R) CPU E5-2609 0 2.40GHz
% Memory : 32218.75MB
% OS : Linux 3.10.0-327.10.1.el7.x86_64
% CPULimit : 300s
% DateTime : Thu Apr 14 06:42:10 EDT 2016
% Result : CounterSatisfiable 203.15s
% Output : Assurance 0s
% Verified :
% SZS Type : None (Parsing solution fails)
% Syntax : Number of formulae : 0
% Comments :
%------------------------------------------------------------------------------
%----No solution output by system
%------------------------------------------------------------------------------
%----ORIGINAL SYSTEM OUTPUT
% 0.00/0.03 % Problem : SYN513+1 : TPTP v6.4.0. Released v2.1.0.
% 0.00/0.04 % Command : isabelle tptp_refute %d %s
% 0.03/0.23 % Computer : n073.star.cs.uiowa.edu
% 0.03/0.23 % Model : x86_64 x86_64
% 0.03/0.23 % CPU : Intel(R) Xeon(R) CPU E5-2609 0 @ 2.40GHz
% 0.03/0.23 % Memory : 32218.75MB
% 0.03/0.23 % OS : Linux 3.10.0-327.10.1.el7.x86_64
% 0.03/0.23 % CPULimit : 300
% 0.03/0.23 % DateTime : Sat Apr 9 00:11:24 CDT 2016
% 0.03/0.23 % CPUTime:
% 6.31/5.84 > val it = (): unit
% 6.91/6.47 Trying to find a model that refutes: ~ (((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((bnd_ndr1_0 &
% 6.91/6.47 ~ bnd_c5_1 bnd_a775) &
% 6.91/6.47 ~ bnd_c3_1 bnd_a775) &
% 6.91/6.47 bnd_c1_1 bnd_a775 |
% 6.91/6.47 ~ bnd_c4_0) &
% 6.91/6.47 ((bnd_c5_0 |
% 6.91/6.47 (((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a776) &
% 6.91/6.47 ~ bnd_c3_2 bnd_a776 bnd_a777) &
% 6.91/6.47 bnd_c2_2 bnd_a776 bnd_a777) &
% 6.91/6.47 ~ bnd_c1_2 bnd_a776 bnd_a777) &
% 6.91/6.47 ~ bnd_c2_1 bnd_a776) &
% 6.91/6.47 (ALL U.
% 6.91/6.47 bnd_ndr1_1 bnd_a776 -->
% 6.91/6.47 bnd_c5_2 bnd_a776 U | ~ bnd_c3_2 bnd_a776 U)) |
% 6.91/6.47 (ALL V.
% 6.91/6.47 bnd_ndr1_0 -->
% 6.91/6.47 (~ bnd_c2_1 V |
% 6.91/6.47 ((bnd_ndr1_1 V & bnd_c3_2 V bnd_a778) & bnd_c1_2 V bnd_a778) &
% 6.91/6.47 bnd_c4_2 V bnd_a778) |
% 6.91/6.47 (ALL W.
% 6.91/6.47 bnd_ndr1_1 V -->
% 6.91/6.47 (bnd_c1_2 V W | bnd_c3_2 V W) | bnd_c5_2 V W)))) &
% 6.91/6.47 (((bnd_ndr1_0 & ~ bnd_c3_1 bnd_a779) &
% 6.91/6.47 (ALL X.
% 6.91/6.47 bnd_ndr1_1 bnd_a779 -->
% 6.91/6.47 (~ bnd_c1_2 bnd_a779 X | bnd_c2_2 bnd_a779 X) |
% 6.91/6.47 bnd_c3_2 bnd_a779 X) |
% 6.91/6.47 bnd_c3_0) |
% 6.91/6.47 (bnd_ndr1_0 &
% 6.91/6.47 (ALL Y.
% 6.91/6.47 bnd_ndr1_1 bnd_a780 -->
% 6.91/6.47 (bnd_c2_2 bnd_a780 Y | bnd_c3_2 bnd_a780 Y) |
% 6.91/6.47 bnd_c1_2 bnd_a780 Y)) &
% 6.91/6.47 bnd_c3_1 bnd_a780)) &
% 6.91/6.47 (~ bnd_c2_0 | bnd_c4_0)) &
% 6.91/6.47 (((bnd_ndr1_0 & ~ bnd_c4_1 bnd_a781) &
% 6.91/6.47 (ALL Z.
% 6.91/6.47 bnd_ndr1_1 bnd_a781 -->
% 6.91/6.47 (~ bnd_c2_2 bnd_a781 Z | bnd_c4_2 bnd_a781 Z) |
% 6.91/6.47 ~ bnd_c1_2 bnd_a781 Z) |
% 6.91/6.47 ~ bnd_c4_0) |
% 6.91/6.47 (ALL X1.
% 6.91/6.47 bnd_ndr1_0 -->
% 6.91/6.47 ((ALL X2.
% 6.91/6.47 bnd_ndr1_1 X1 -->
% 6.91/6.47 (bnd_c1_2 X1 X2 | ~ bnd_c2_2 X1 X2) | bnd_c4_2 X1 X2) |
% 6.91/6.47 (ALL X3. bnd_ndr1_1 X1 --> ~ bnd_c4_2 X1 X3 | ~ bnd_c2_2 X1 X3)) |
% 6.91/6.47 bnd_c1_1 X1))) &
% 6.91/6.47 ((~ bnd_c1_0 | ~ bnd_c4_0) |
% 6.91/6.47 (ALL X4.
% 6.91/6.47 bnd_ndr1_0 -->
% 6.91/6.47 (~ bnd_c3_1 X4 |
% 6.91/6.47 ((bnd_ndr1_1 X4 & ~ bnd_c2_2 X4 bnd_a782) &
% 6.91/6.47 ~ bnd_c5_2 X4 bnd_a782) &
% 6.91/6.47 ~ bnd_c1_2 X4 bnd_a782) |
% 6.91/6.47 ~ bnd_c1_1 X4))) &
% 6.91/6.47 ((bnd_c4_0 | ~ bnd_c1_0) |
% 6.91/6.47 (ALL X5.
% 6.91/6.47 bnd_ndr1_0 -->
% 6.91/6.47 (~ bnd_c5_1 X5 | bnd_c1_1 X5) |
% 6.91/6.47 ((bnd_ndr1_1 X5 & ~ bnd_c4_2 X5 bnd_a783) & ~ bnd_c2_2 X5 bnd_a783) &
% 6.91/6.47 ~ bnd_c3_2 X5 bnd_a783))) &
% 6.91/6.47 (((ALL X6.
% 6.91/6.47 bnd_ndr1_0 -->
% 6.91/6.47 ((ALL X7.
% 6.91/6.47 bnd_ndr1_1 X6 -->
% 6.91/6.47 (~ bnd_c5_2 X6 X7 | bnd_c3_2 X6 X7) | ~ bnd_c4_2 X6 X7) |
% 6.91/6.47 ~ bnd_c5_1 X6) |
% 6.91/6.47 (ALL X8. bnd_ndr1_1 X6 --> ~ bnd_c5_2 X6 X8 | ~ bnd_c1_2 X6 X8)) |
% 6.91/6.47 (ALL X9.
% 6.91/6.47 bnd_ndr1_0 -->
% 6.91/6.47 ((bnd_ndr1_1 X9 & bnd_c3_2 X9 bnd_a784) & bnd_c2_2 X9 bnd_a784) &
% 6.91/6.47 ~ bnd_c1_2 X9 bnd_a784 |
% 6.91/6.47 ~ bnd_c4_1 X9)) |
% 6.91/6.47 (ALL X10.
% 6.91/6.47 bnd_ndr1_0 -->
% 6.91/6.47 ((bnd_ndr1_1 X10 & bnd_c5_2 X10 bnd_a785) & ~ bnd_c2_2 X10 bnd_a785) &
% 6.91/6.47 ~ bnd_c1_2 X10 bnd_a785 |
% 6.91/6.47 bnd_c2_1 X10))) &
% 6.91/6.47 ((((bnd_ndr1_0 &
% 6.91/6.47 (ALL X11.
% 6.91/6.47 bnd_ndr1_1 bnd_a786 -->
% 6.91/6.47 (bnd_c3_2 bnd_a786 X11 | ~ bnd_c1_2 bnd_a786 X11) |
% 6.91/6.47 bnd_c5_2 bnd_a786 X11)) &
% 6.91/6.47 (ALL X12.
% 6.91/6.47 bnd_ndr1_1 bnd_a786 -->
% 6.91/6.47 (bnd_c5_2 bnd_a786 X12 | bnd_c4_2 bnd_a786 X12) |
% 6.91/6.47 ~ bnd_c2_2 bnd_a786 X12)) &
% 6.91/6.47 ~ bnd_c4_1 bnd_a786 |
% 6.91/6.47 (ALL X13.
% 6.91/6.47 bnd_ndr1_0 -->
% 6.91/6.47 (((bnd_ndr1_1 X13 & ~ bnd_c4_2 X13 bnd_a787) &
% 6.91/6.47 ~ bnd_c3_2 X13 bnd_a787) &
% 6.91/6.47 bnd_c5_2 X13 bnd_a787 |
% 6.91/6.47 ((bnd_ndr1_1 X13 & ~ bnd_c2_2 X13 bnd_a788) & bnd_c3_2 X13 bnd_a788) &
% 6.91/6.47 bnd_c1_2 X13 bnd_a788) |
% 6.91/6.47 bnd_c3_1 X13)) |
% 6.91/6.47 (((((bnd_ndr1_0 & ~ bnd_c5_1 bnd_a789) & bnd_ndr1_1 bnd_a789) &
% 6.91/6.47 bnd_c5_2 bnd_a789 bnd_a790) &
% 6.91/6.47 bnd_c1_2 bnd_a789 bnd_a790) &
% 6.91/6.47 ~ bnd_c4_2 bnd_a789 bnd_a790) &
% 6.91/6.47 bnd_c1_1 bnd_a789)) &
% 6.91/6.47 (((ALL X14.
% 6.91/6.47 bnd_ndr1_0 -->
% 6.91/6.47 ((ALL X15.
% 6.91/6.47 bnd_ndr1_1 X14 -->
% 6.91/6.47 (bnd_c1_2 X14 X15 | bnd_c5_2 X14 X15) | bnd_c3_2 X14 X15) |
% 6.91/6.47 ~ bnd_c2_1 X14) |
% 6.91/6.47 bnd_c5_1 X14) |
% 6.91/6.47 ~ bnd_c3_0) |
% 6.91/6.47 bnd_c2_0)) &
% 6.91/6.47 (((ALL X16.
% 6.91/6.47 bnd_ndr1_0 -->
% 6.91/6.47 ((ALL X17.
% 6.91/6.47 bnd_ndr1_1 X16 -->
% 6.91/6.47 (bnd_c4_2 X16 X17 | ~ bnd_c5_2 X16 X17) | bnd_c2_2 X16 X17) |
% 6.91/6.47 ((bnd_ndr1_1 X16 & bnd_c4_2 X16 bnd_a791) & bnd_c3_2 X16 bnd_a791) &
% 6.91/6.47 bnd_c1_2 X16 bnd_a791) |
% 6.91/6.47 bnd_c5_1 X16) |
% 6.91/6.47 (ALL X18.
% 6.91/6.47 bnd_ndr1_0 --> (~ bnd_c2_1 X18 | bnd_c4_1 X18) | bnd_c1_1 X18)) |
% 6.91/6.47 bnd_c2_0)) &
% 6.91/6.47 ((bnd_c4_0 | ~ bnd_c2_0) | bnd_c1_0)) &
% 6.91/6.47 (((((((((bnd_ndr1_0 &
% 6.91/6.47 bnd_ndr1_1 bnd_a792) &
% 6.91/6.47 ~ bnd_c5_2 bnd_a792 bnd_a793) &
% 6.91/6.47 bnd_c1_2 bnd_a792 bnd_a793) &
% 6.91/6.47 bnd_c4_1 bnd_a792) &
% 6.91/6.47 bnd_ndr1_1 bnd_a792) &
% 6.91/6.47 ~ bnd_c4_2 bnd_a792 bnd_a794) &
% 6.91/6.47 bnd_c3_2 bnd_a792 bnd_a794) &
% 6.91/6.47 ~ bnd_c1_2 bnd_a792 bnd_a794 |
% 6.91/6.47 ((bnd_ndr1_0 &
% 6.91/6.47 (ALL X19.
% 6.91/6.47 bnd_ndr1_1 bnd_a795 -->
% 6.91/6.47 (~ bnd_c2_2 bnd_a795 X19 | bnd_c1_2 bnd_a795 X19) |
% 6.91/6.47 ~ bnd_c5_2 bnd_a795 X19)) &
% 6.91/6.47 (ALL X20.
% 6.91/6.47 bnd_ndr1_1 bnd_a795 -->
% 6.91/6.47 (~ bnd_c1_2 bnd_a795 X20 | bnd_c5_2 bnd_a795 X20) |
% 6.91/6.47 bnd_c3_2 bnd_a795 X20)) &
% 6.91/6.47 ~ bnd_c1_1 bnd_a795) |
% 6.91/6.47 ~ bnd_c3_0)) &
% 6.91/6.47 ((~ bnd_c2_0 | ~ bnd_c4_0) | bnd_c3_0)) &
% 6.91/6.47 ((ALL X21.
% 6.91/6.47 bnd_ndr1_0 -->
% 6.91/6.47 ((ALL X22.
% 6.91/6.47 bnd_ndr1_1 X21 -->
% 6.91/6.47 (bnd_c4_2 X21 X22 | ~ bnd_c5_2 X21 X22) | bnd_c3_2 X21 X22) |
% 6.91/6.47 (ALL X23.
% 6.91/6.47 bnd_ndr1_1 X21 --> bnd_c3_2 X21 X23 | bnd_c2_2 X21 X23)) |
% 6.91/6.47 ~ bnd_c3_1 X21) |
% 6.91/6.47 (((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a796) &
% 6.91/6.47 ~ bnd_c5_2 bnd_a796 bnd_a797) &
% 6.91/6.47 bnd_c2_2 bnd_a796 bnd_a797) &
% 6.91/6.47 bnd_c1_2 bnd_a796 bnd_a797) &
% 6.91/6.47 bnd_ndr1_1 bnd_a796) &
% 6.91/6.47 ~ bnd_c2_2 bnd_a796 bnd_a798) &
% 6.91/6.47 ~ bnd_c3_2 bnd_a796 bnd_a798) &
% 6.91/6.47 ~ bnd_c2_1 bnd_a796)) &
% 6.91/6.47 ((bnd_c5_0 |
% 6.91/6.47 (ALL X24.
% 6.91/6.47 bnd_ndr1_0 -->
% 6.91/6.47 ((bnd_ndr1_1 X24 &
% 6.91/6.47 bnd_c3_2 X24 bnd_a799) &
% 6.91/6.47 bnd_c4_2 X24 bnd_a799) &
% 6.91/6.47 ~ bnd_c1_2 X24 bnd_a799 |
% 6.91/6.47 bnd_c4_1 X24)) |
% 6.91/6.47 bnd_c4_0)) &
% 6.91/6.47 (bnd_c1_0 |
% 6.91/6.47 ((bnd_ndr1_0 & bnd_c2_1 bnd_a800) &
% 6.91/6.47 (ALL X25.
% 6.91/6.47 bnd_ndr1_1 bnd_a800 -->
% 6.91/6.47 (~ bnd_c4_2 bnd_a800 X25 |
% 6.91/6.47 ~ bnd_c1_2 bnd_a800 X25) |
% 6.91/6.47 ~ bnd_c5_2 bnd_a800 X25)) &
% 6.91/6.47 (ALL X26.
% 6.91/6.47 bnd_ndr1_1 bnd_a800 -->
% 6.91/6.47 bnd_c5_2 bnd_a800 X26 |
% 6.91/6.47 bnd_c2_2 bnd_a800 X26))) &
% 6.91/6.47 (((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a801) &
% 6.91/6.47 bnd_c5_2 bnd_a801 bnd_a802) &
% 6.91/6.47 bnd_c1_2 bnd_a801 bnd_a802) &
% 6.91/6.47 bnd_c4_2 bnd_a801 bnd_a802) &
% 6.91/6.47 (ALL X27.
% 6.91/6.47 bnd_ndr1_1 bnd_a801 -->
% 6.91/6.47 (bnd_c5_2 bnd_a801 X27 |
% 6.91/6.47 ~ bnd_c1_2 bnd_a801 X27) |
% 6.91/6.47 ~ bnd_c3_2 bnd_a801 X27)) &
% 6.91/6.47 bnd_c2_1 bnd_a801 |
% 6.91/6.47 (ALL X28.
% 6.91/6.47 bnd_ndr1_0 -->
% 6.91/6.47 ~ bnd_c4_1 X28 | bnd_c2_1 X28)) |
% 6.91/6.47 (ALL X29.
% 6.91/6.47 bnd_ndr1_0 -->
% 6.91/6.47 (((bnd_ndr1_1 X29 &
% 6.91/6.47 bnd_c2_2 X29 bnd_a803) &
% 6.91/6.47 ~ bnd_c5_2 X29 bnd_a803) &
% 6.91/6.47 bnd_c4_2 X29 bnd_a803 |
% 6.91/6.47 ~ bnd_c3_1 X29) |
% 6.91/6.47 (ALL X30.
% 6.91/6.47 bnd_ndr1_1 X29 -->
% 6.91/6.47 (~ bnd_c2_2 X29 X30 |
% 6.91/6.47 ~ bnd_c4_2 X29 X30) |
% 6.91/6.47 ~ bnd_c3_2 X29 X30)))) &
% 6.91/6.47 ((~ bnd_c3_0 |
% 6.91/6.47 (bnd_ndr1_0 &
% 6.91/6.47 (ALL X31.
% 6.91/6.47 bnd_ndr1_1 bnd_a804 -->
% 6.91/6.47 (bnd_c1_2 bnd_a804 X31 |
% 6.91/6.47 bnd_c3_2 bnd_a804 X31) |
% 6.91/6.47 bnd_c4_2 bnd_a804 X31)) &
% 6.91/6.47 bnd_c5_1 bnd_a804) |
% 6.91/6.47 (ALL X32.
% 6.91/6.47 bnd_ndr1_0 -->
% 6.91/6.47 ((bnd_ndr1_1 X32 & bnd_c2_2 X32 bnd_a805) &
% 6.91/6.47 bnd_c4_2 X32 bnd_a805) &
% 6.91/6.47 ~ bnd_c5_2 X32 bnd_a805 |
% 6.91/6.47 ~ bnd_c4_1 X32))) &
% 6.91/6.47 (((ALL X33.
% 6.91/6.47 bnd_ndr1_0 -->
% 6.91/6.47 (((bnd_ndr1_1 X33 & bnd_c5_2 X33 bnd_a806) &
% 6.91/6.47 bnd_c2_2 X33 bnd_a806) &
% 6.91/6.47 bnd_c4_2 X33 bnd_a806 |
% 6.91/6.47 (bnd_ndr1_1 X33 &
% 6.91/6.47 ~ bnd_c3_2 X33 bnd_a807) &
% 6.91/6.47 ~ bnd_c2_2 X33 bnd_a807) |
% 6.91/6.47 ((bnd_ndr1_1 X33 & bnd_c5_2 X33 bnd_a808) &
% 6.91/6.47 ~ bnd_c2_2 X33 bnd_a808) &
% 6.91/6.47 bnd_c4_2 X33 bnd_a808) |
% 6.91/6.47 (ALL X34.
% 6.91/6.47 bnd_ndr1_0 -->
% 6.91/6.47 (~ bnd_c2_1 X34 | ~ bnd_c3_1 X34) |
% 6.91/6.47 ((bnd_ndr1_1 X34 & bnd_c5_2 X34 bnd_a809) &
% 6.91/6.47 bnd_c3_2 X34 bnd_a809) &
% 6.91/6.47 bnd_c1_2 X34 bnd_a809)) |
% 6.91/6.47 bnd_c4_0)) &
% 6.91/6.47 ((ALL X35.
% 6.91/6.47 bnd_ndr1_0 -->
% 6.91/6.47 (~ bnd_c5_1 X35 | bnd_c3_1 X35) |
% 6.91/6.47 ~ bnd_c4_1 X35) |
% 6.91/6.47 ~ bnd_c5_0)) &
% 6.91/6.47 ((bnd_c4_0 |
% 6.91/6.47 (bnd_ndr1_0 & bnd_c2_1 bnd_a810) &
% 6.91/6.47 bnd_c4_1 bnd_a810) |
% 6.91/6.47 bnd_c5_0)) &
% 6.91/6.47 ((ALL X36.
% 6.91/6.47 bnd_ndr1_0 -->
% 6.91/6.47 (~ bnd_c3_1 X36 | bnd_c1_1 X36) |
% 6.91/6.47 (bnd_ndr1_1 X36 & ~ bnd_c2_2 X36 bnd_a811) &
% 6.91/6.47 bnd_c3_2 X36 bnd_a811) |
% 6.91/6.47 ((((bnd_ndr1_0 & ~ bnd_c3_1 bnd_a812) &
% 6.91/6.47 bnd_ndr1_1 bnd_a812) &
% 6.91/6.47 bnd_c3_2 bnd_a812 bnd_a813) &
% 6.91/6.47 bnd_c1_2 bnd_a812 bnd_a813) &
% 6.91/6.47 bnd_c2_2 bnd_a812 bnd_a813)) &
% 6.91/6.47 ((ALL X37.
% 6.91/6.47 bnd_ndr1_0 --> ~ bnd_c5_1 X37 | ~ bnd_c4_1 X37) |
% 6.91/6.47 bnd_c3_0)) &
% 6.91/6.47 ((~ bnd_c1_0 |
% 6.91/6.47 (bnd_ndr1_0 & bnd_c3_1 bnd_a814) &
% 6.91/6.47 bnd_c2_1 bnd_a814) |
% 6.91/6.47 ~ bnd_c2_0)) &
% 6.91/6.47 (((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a815) &
% 6.91/6.47 bnd_c1_2 bnd_a815 bnd_a816) &
% 6.91/6.47 bnd_c3_2 bnd_a815 bnd_a816) &
% 6.91/6.47 ~ bnd_c5_2 bnd_a815 bnd_a816) &
% 6.91/6.47 bnd_c3_1 bnd_a815) &
% 6.91/6.47 ~ bnd_c5_1 bnd_a815 |
% 6.91/6.47 bnd_c2_0) |
% 6.91/6.47 bnd_c5_0)) &
% 6.91/6.47 (((bnd_ndr1_0 & bnd_c4_1 bnd_a817) & bnd_c2_1 bnd_a817 |
% 6.91/6.47 (((((bnd_ndr1_0 & bnd_c3_1 bnd_a818) &
% 6.91/6.47 bnd_ndr1_1 bnd_a818) &
% 6.91/6.47 ~ bnd_c3_2 bnd_a818 bnd_a819) &
% 6.91/6.47 ~ bnd_c2_2 bnd_a818 bnd_a819) &
% 6.91/6.47 ~ bnd_c5_2 bnd_a818 bnd_a819) &
% 6.91/6.47 (ALL X38.
% 6.91/6.47 bnd_ndr1_1 bnd_a818 -->
% 6.91/6.47 (~ bnd_c1_2 bnd_a818 X38 | bnd_c4_2 bnd_a818 X38) |
% 6.91/6.47 bnd_c5_2 bnd_a818 X38)) |
% 6.91/6.47 ((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a820) &
% 6.91/6.47 ~ bnd_c3_2 bnd_a820 bnd_a821) &
% 6.91/6.47 bnd_c1_2 bnd_a820 bnd_a821) &
% 6.91/6.47 ~ bnd_c5_2 bnd_a820 bnd_a821) &
% 6.91/6.47 bnd_ndr1_1 bnd_a820) &
% 6.91/6.47 ~ bnd_c5_2 bnd_a820 bnd_a822) &
% 6.91/6.47 ~ bnd_c2_2 bnd_a820 bnd_a822)) &
% 6.91/6.47 (((bnd_ndr1_0 &
% 6.91/6.47 (ALL X39.
% 6.91/6.47 bnd_ndr1_1 bnd_a823 -->
% 6.91/6.47 (~ bnd_c3_2 bnd_a823 X39 |
% 6.91/6.47 ~ bnd_c2_2 bnd_a823 X39) |
% 6.91/6.47 bnd_c1_2 bnd_a823 X39)) &
% 6.91/6.47 bnd_c5_1 bnd_a823 |
% 6.91/6.47 bnd_c5_0) |
% 6.91/6.47 ~ bnd_c2_0)) &
% 6.91/6.47 ((bnd_c3_0 |
% 6.91/6.47 (ALL X40.
% 6.91/6.47 bnd_ndr1_0 --> ~ bnd_c5_1 X40 | bnd_c4_1 X40)) |
% 6.91/6.47 ((bnd_ndr1_0 & ~ bnd_c2_1 bnd_a824) &
% 6.91/6.47 (ALL X41.
% 6.91/6.47 bnd_ndr1_1 bnd_a824 -->
% 6.91/6.47 ~ bnd_c4_2 bnd_a824 X41 | ~ bnd_c1_2 bnd_a824 X41)) &
% 6.91/6.47 ~ bnd_c4_1 bnd_a824)) &
% 6.91/6.47 (((ALL X42.
% 6.91/6.47 bnd_ndr1_0 -->
% 6.91/6.47 (((bnd_ndr1_1 X42 & bnd_c3_2 X42 bnd_a825) &
% 6.91/6.47 ~ bnd_c2_2 X42 bnd_a825) &
% 6.91/6.47 bnd_c1_2 X42 bnd_a825 |
% 6.91/6.47 bnd_c1_1 X42) |
% 6.91/6.47 ~ bnd_c2_1 X42) |
% 6.91/6.47 ~ bnd_c5_0) |
% 6.91/6.47 (ALL X43.
% 6.91/6.47 bnd_ndr1_0 -->
% 6.91/6.47 (bnd_c1_1 X43 |
% 6.91/6.47 ((bnd_ndr1_1 X43 & ~ bnd_c1_2 X43 bnd_a826) &
% 6.91/6.47 ~ bnd_c2_2 X43 bnd_a826) &
% 6.91/6.47 bnd_c5_2 X43 bnd_a826) |
% 6.91/6.47 (ALL X44.
% 6.91/6.47 bnd_ndr1_1 X43 -->
% 6.91/6.47 (bnd_c5_2 X43 X44 | ~ bnd_c2_2 X43 X44) |
% 6.91/6.47 bnd_c4_2 X43 X44)))) &
% 6.91/6.47 (~ bnd_c1_0 | bnd_c3_0)) &
% 6.91/6.47 (((bnd_ndr1_0 & ~ bnd_c5_1 bnd_a827) &
% 6.91/6.47 (ALL X45.
% 6.91/6.47 bnd_ndr1_1 bnd_a827 -->
% 6.91/6.47 (bnd_c1_2 bnd_a827 X45 | ~ bnd_c2_2 bnd_a827 X45) |
% 6.91/6.47 bnd_c5_2 bnd_a827 X45) |
% 6.91/6.47 (ALL X46.
% 6.91/6.47 bnd_ndr1_0 -->
% 6.91/6.47 (bnd_c4_1 X46 |
% 6.91/6.47 (ALL X47.
% 6.91/6.47 bnd_ndr1_1 X46 -->
% 6.91/6.47 (~ bnd_c3_2 X46 X47 | bnd_c5_2 X46 X47) |
% 6.91/6.47 bnd_c4_2 X46 X47)) |
% 6.91/6.47 (ALL X48.
% 6.91/6.47 bnd_ndr1_1 X46 -->
% 6.91/6.47 (bnd_c4_2 X46 X48 | ~ bnd_c2_2 X46 X48) |
% 6.91/6.47 bnd_c1_2 X46 X48))) |
% 6.91/6.47 bnd_c2_0)) &
% 6.91/6.47 (((ALL X49.
% 6.91/6.47 bnd_ndr1_0 -->
% 6.91/6.47 ((ALL X50.
% 6.91/6.47 bnd_ndr1_1 X49 -->
% 6.91/6.47 (~ bnd_c4_2 X49 X50 | ~ bnd_c1_2 X49 X50) |
% 6.91/6.47 bnd_c2_2 X49 X50) |
% 6.91/6.47 bnd_c2_1 X49) |
% 6.91/6.47 ~ bnd_c4_1 X49) |
% 6.91/6.47 bnd_c3_0) |
% 6.91/6.47 ~ bnd_c2_0)) &
% 6.91/6.47 (~ bnd_c4_0 | ~ bnd_c5_0)) &
% 6.91/6.47 (((ALL X51.
% 6.91/6.47 bnd_ndr1_0 -->
% 6.91/6.47 (bnd_c2_1 X51 | ~ bnd_c1_1 X51) | ~ bnd_c5_1 X51) |
% 6.91/6.47 bnd_c3_0) |
% 6.91/6.47 ((((bnd_ndr1_0 &
% 6.91/6.47 (ALL X52.
% 6.91/6.47 bnd_ndr1_1 bnd_a828 -->
% 6.91/6.47 bnd_c2_2 bnd_a828 X52 | bnd_c4_2 bnd_a828 X52)) &
% 6.91/6.47 bnd_ndr1_1 bnd_a828) &
% 6.91/6.47 ~ bnd_c1_2 bnd_a828 bnd_a829) &
% 6.91/6.47 ~ bnd_c4_2 bnd_a828 bnd_a829) &
% 6.91/6.47 (ALL X53.
% 6.91/6.47 bnd_ndr1_1 bnd_a828 -->
% 6.91/6.47 (bnd_c4_2 bnd_a828 X53 | bnd_c3_2 bnd_a828 X53) |
% 6.91/6.47 ~ bnd_c5_2 bnd_a828 X53))) &
% 6.91/6.47 (bnd_c2_0 |
% 6.91/6.47 ((bnd_ndr1_0 & bnd_c2_1 bnd_a830) &
% 6.91/6.47 (ALL X54.
% 6.91/6.47 bnd_ndr1_1 bnd_a830 -->
% 6.91/6.47 (bnd_c2_2 bnd_a830 X54 | ~ bnd_c1_2 bnd_a830 X54) |
% 6.91/6.47 ~ bnd_c3_2 bnd_a830 X54)) &
% 6.91/6.47 (ALL X55.
% 6.91/6.47 bnd_ndr1_1 bnd_a830 -->
% 6.91/6.47 bnd_c5_2 bnd_a830 X55 | bnd_c1_2 bnd_a830 X55))) &
% 6.91/6.47 ((bnd_c4_0 | ~ bnd_c1_0) |
% 6.91/6.47 (ALL X56.
% 6.91/6.47 bnd_ndr1_0 -->
% 6.91/6.47 ((ALL X57.
% 6.91/6.47 bnd_ndr1_1 X56 --> bnd_c3_2 X56 X57 | bnd_c1_2 X56 X57) |
% 6.91/6.47 ~ bnd_c1_1 X56) |
% 6.91/6.47 (ALL X58.
% 6.91/6.47 bnd_ndr1_1 X56 -->
% 6.91/6.47 (bnd_c4_2 X56 X58 | bnd_c5_2 X56 X58) |
% 6.91/6.47 bnd_c3_2 X56 X58)))) &
% 6.91/6.47 (((bnd_ndr1_0 & bnd_c3_1 bnd_a831) & ~ bnd_c4_1 bnd_a831 |
% 6.91/6.47 (ALL X59.
% 6.91/6.47 bnd_ndr1_0 -->
% 6.91/6.47 (((bnd_ndr1_1 X59 & ~ bnd_c2_2 X59 bnd_a832) &
% 6.91/6.47 ~ bnd_c1_2 X59 bnd_a832) &
% 6.91/6.47 bnd_c3_2 X59 bnd_a832 |
% 6.91/6.47 (ALL X60.
% 6.91/6.47 bnd_ndr1_1 X59 -->
% 6.91/6.47 ~ bnd_c4_2 X59 X60 | bnd_c5_2 X59 X60)) |
% 6.91/6.47 (ALL X61.
% 6.91/6.47 bnd_ndr1_1 X59 -->
% 6.91/6.47 (~ bnd_c5_2 X59 X61 | ~ bnd_c2_2 X59 X61) |
% 6.91/6.47 bnd_c3_2 X59 X61))) |
% 6.91/6.47 bnd_c2_0)) &
% 6.91/6.47 ((ALL X62.
% 6.91/6.47 bnd_ndr1_0 -->
% 6.91/6.47 (((bnd_ndr1_1 X62 & bnd_c1_2 X62 bnd_a833) &
% 6.91/6.47 ~ bnd_c5_2 X62 bnd_a833) &
% 6.91/6.47 bnd_c3_2 X62 bnd_a833 |
% 6.91/6.47 (bnd_ndr1_1 X62 & ~ bnd_c2_2 X62 bnd_a834) &
% 6.91/6.47 ~ bnd_c5_2 X62 bnd_a834) |
% 6.91/6.47 (ALL X63.
% 6.91/6.47 bnd_ndr1_1 X62 -->
% 6.91/6.47 (bnd_c1_2 X62 X63 | ~ bnd_c3_2 X62 X63) |
% 6.91/6.47 ~ bnd_c2_2 X62 X63)) |
% 6.91/6.47 bnd_c3_0)) &
% 6.91/6.47 ((bnd_c5_0 | ~ bnd_c4_0) |
% 6.91/6.47 (ALL X64.
% 6.91/6.47 bnd_ndr1_0 -->
% 6.91/6.47 ~ bnd_c3_1 X64 |
% 6.91/6.47 ((bnd_ndr1_1 X64 & ~ bnd_c5_2 X64 bnd_a835) &
% 6.91/6.47 bnd_c1_2 X64 bnd_a835) &
% 6.91/6.47 ~ bnd_c4_2 X64 bnd_a835))) &
% 6.91/6.47 ((bnd_c5_0 |
% 6.91/6.47 (((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a836) &
% 6.91/6.47 bnd_c4_2 bnd_a836 bnd_a837) &
% 6.91/6.47 ~ bnd_c1_2 bnd_a836 bnd_a837) &
% 6.91/6.47 ~ bnd_c2_2 bnd_a836 bnd_a837) &
% 6.91/6.47 bnd_c5_1 bnd_a836) &
% 6.91/6.47 bnd_c1_1 bnd_a836) |
% 6.91/6.47 (bnd_ndr1_0 &
% 6.91/6.47 (ALL X65.
% 6.91/6.47 bnd_ndr1_1 bnd_a838 -->
% 6.91/6.47 (bnd_c2_2 bnd_a838 X65 | ~ bnd_c4_2 bnd_a838 X65) |
% 6.91/6.47 bnd_c3_2 bnd_a838 X65)) &
% 6.91/6.47 ~ bnd_c4_1 bnd_a838)) &
% 6.91/6.47 (~ bnd_c5_0 |
% 6.91/6.47 (((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a839) &
% 6.91/6.47 bnd_c4_2 bnd_a839 bnd_a840) &
% 6.91/6.47 ~ bnd_c5_2 bnd_a839 bnd_a840) &
% 6.91/6.47 bnd_c2_2 bnd_a839 bnd_a840) &
% 6.91/6.47 bnd_ndr1_1 bnd_a839) &
% 6.91/6.47 ~ bnd_c2_2 bnd_a839 bnd_a841) &
% 6.91/6.47 ~ bnd_c4_2 bnd_a839 bnd_a841) &
% 6.91/6.47 (ALL X66.
% 6.91/6.47 bnd_ndr1_1 bnd_a839 -->
% 6.91/6.47 bnd_c4_2 bnd_a839 X66 | ~ bnd_c5_2 bnd_a839 X66))) &
% 6.91/6.47 ((~ bnd_c2_0 | bnd_c3_0) |
% 6.91/6.47 (ALL X67.
% 6.91/6.47 bnd_ndr1_0 -->
% 6.91/6.47 (~ bnd_c2_1 X67 | bnd_c3_1 X67) |
% 6.91/6.47 ((bnd_ndr1_1 X67 & bnd_c4_2 X67 bnd_a842) & bnd_c5_2 X67 bnd_a842) &
% 6.91/6.47 ~ bnd_c2_2 X67 bnd_a842))) &
% 6.91/6.47 (bnd_c3_0 | (ALL X68. bnd_ndr1_0 --> bnd_c3_1 X68 | bnd_c1_1 X68))) &
% 6.91/6.47 (~ bnd_c5_0 | ~ bnd_c1_0)) &
% 6.91/6.47 ((~ bnd_c3_0 | (bnd_ndr1_0 & bnd_c5_1 bnd_a843) & ~ bnd_c1_1 bnd_a843) |
% 6.91/6.47 bnd_c4_0)) &
% 6.91/6.47 ((~ bnd_c4_0 | bnd_c5_0) |
% 6.91/6.47 ~ bnd_c2_0)) &
% 6.91/6.47 ((~ bnd_c1_0 | ~ bnd_c5_0) |
% 6.91/6.47 bnd_c4_0)) &
% 6.91/6.47 ((~ bnd_c2_0 |
% 6.91/6.47 bnd_ndr1_0 & ~ bnd_c3_1 bnd_a844) |
% 6.91/6.47 ((bnd_ndr1_0 & ~ bnd_c2_1 bnd_a845) &
% 6.91/6.47 ~ bnd_c1_1 bnd_a845) &
% 6.91/6.47 ~ bnd_c3_1 bnd_a845)) &
% 6.91/6.47 ((bnd_c3_0 |
% 6.91/6.47 (ALL X69.
% 6.91/6.47 bnd_ndr1_0 -->
% 6.91/6.47 (~ bnd_c3_1 X69 | ~ bnd_c1_1 X69) |
% 6.91/6.47 (ALL X70.
% 6.91/6.47 bnd_ndr1_1 X69 -->
% 6.91/6.47 (bnd_c3_2 X69 X70 | bnd_c5_2 X69 X70) | bnd_c4_2 X69 X70))) |
% 6.91/6.47 (ALL X71.
% 6.91/6.47 bnd_ndr1_0 -->
% 6.91/6.47 (((bnd_ndr1_1 X71 & bnd_c4_2 X71 bnd_a846) & bnd_c5_2 X71 bnd_a846) &
% 6.91/6.47 bnd_c3_2 X71 bnd_a846 |
% 6.91/6.47 bnd_c3_1 X71) |
% 6.91/6.47 ~ bnd_c1_1 X71))) &
% 6.91/6.47 (((ALL X72.
% 6.91/6.47 bnd_ndr1_0 -->
% 6.91/6.47 ((bnd_ndr1_1 X72 & bnd_c3_2 X72 bnd_a847) & ~ bnd_c4_2 X72 bnd_a847 |
% 6.91/6.47 ((bnd_ndr1_1 X72 & ~ bnd_c5_2 X72 bnd_a848) & bnd_c3_2 X72 bnd_a848) &
% 6.91/6.47 ~ bnd_c4_2 X72 bnd_a848) |
% 6.91/6.47 ~ bnd_c2_1 X72) |
% 6.91/6.47 (ALL X73.
% 6.91/6.47 bnd_ndr1_0 -->
% 6.91/6.47 (ALL X74. bnd_ndr1_1 X73 --> ~ bnd_c4_2 X73 X74 | ~ bnd_c5_2 X73 X74) |
% 6.91/6.47 ~ bnd_c1_1 X73)) |
% 6.91/6.47 ~ bnd_c2_0)) &
% 6.91/6.47 (((((((((bnd_ndr1_0 & ~ bnd_c5_1 bnd_a849) &
% 6.91/6.47 bnd_ndr1_1 bnd_a849) &
% 6.91/6.47 ~ bnd_c3_2 bnd_a849 bnd_a850) &
% 6.91/6.47 ~ bnd_c4_2 bnd_a849 bnd_a850) &
% 6.91/6.47 bnd_c1_2 bnd_a849 bnd_a850) &
% 6.91/6.47 bnd_ndr1_1 bnd_a849) &
% 6.91/6.47 bnd_c1_2 bnd_a849 bnd_a851) &
% 6.91/6.47 ~ bnd_c5_2 bnd_a849 bnd_a851 |
% 6.91/6.47 (bnd_ndr1_0 &
% 6.91/6.47 (ALL X75.
% 6.91/6.47 bnd_ndr1_1 bnd_a852 -->
% 6.91/6.47 (bnd_c1_2 bnd_a852 X75 | ~ bnd_c4_2 bnd_a852 X75) |
% 6.91/6.47 ~ bnd_c5_2 bnd_a852 X75)) &
% 6.91/6.47 bnd_c1_1 bnd_a852) |
% 6.91/6.47 ~ bnd_c5_0)) &
% 6.91/6.47 (((((bnd_ndr1_0 &
% 6.91/6.47 (ALL X76.
% 6.91/6.47 bnd_ndr1_1 bnd_a853 -->
% 6.91/6.47 ~ bnd_c1_2 bnd_a853 X76 | bnd_c2_2 bnd_a853 X76)) &
% 6.91/6.47 bnd_ndr1_1 bnd_a853) &
% 6.91/6.47 bnd_c3_2 bnd_a853 bnd_a854) &
% 6.91/6.47 bnd_c2_2 bnd_a853 bnd_a854) &
% 6.91/6.47 (ALL X77.
% 6.91/6.47 bnd_ndr1_1 bnd_a853 -->
% 6.91/6.47 (~ bnd_c1_2 bnd_a853 X77 |
% 6.91/6.47 bnd_c3_2 bnd_a853 X77) |
% 6.91/6.47 bnd_c5_2 bnd_a853 X77) |
% 6.91/6.47 ~ bnd_c5_0)) &
% 6.91/6.47 (((ALL X78.
% 6.91/6.47 bnd_ndr1_0 -->
% 6.91/6.47 (~ bnd_c2_1 X78 | bnd_c5_1 X78) |
% 6.91/6.47 ~ bnd_c3_1 X78) |
% 6.91/6.47 bnd_c3_0) |
% 6.91/6.47 (((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a855) &
% 6.91/6.47 bnd_c1_2 bnd_a855 bnd_a856) &
% 6.91/6.47 bnd_c5_2 bnd_a855 bnd_a856) &
% 6.91/6.47 bnd_c2_2 bnd_a855 bnd_a856) &
% 6.91/6.47 ~ bnd_c1_1 bnd_a855) &
% 6.91/6.47 (ALL X79.
% 6.91/6.47 bnd_ndr1_1 bnd_a855 -->
% 6.91/6.47 (bnd_c2_2 bnd_a855 X79 |
% 6.91/6.47 ~ bnd_c5_2 bnd_a855 X79) |
% 6.91/6.47 ~ bnd_c1_2 bnd_a855 X79))) &
% 6.91/6.47 ((bnd_c1_0 | ~ bnd_c4_0) |
% 6.91/6.47 (ALL X80.
% 6.91/6.47 bnd_ndr1_0 -->
% 6.91/6.47 (~ bnd_c5_1 X80 |
% 6.91/6.47 ((bnd_ndr1_1 X80 &
% 6.91/6.47 ~ bnd_c4_2 X80 bnd_a857) &
% 6.91/6.47 bnd_c2_2 X80 bnd_a857) &
% 6.91/6.47 ~ bnd_c5_2 X80 bnd_a857) |
% 6.91/6.47 bnd_c2_1 X80))) &
% 6.91/6.47 (((((bnd_ndr1_0 & bnd_c5_1 bnd_a858) &
% 6.91/6.47 bnd_ndr1_1 bnd_a858) &
% 6.91/6.47 ~ bnd_c1_2 bnd_a858 bnd_a859) &
% 6.91/6.47 bnd_c3_2 bnd_a858 bnd_a859) &
% 6.91/6.47 bnd_c2_2 bnd_a858 bnd_a859 |
% 6.91/6.47 bnd_c1_0)) &
% 6.91/6.47 (((bnd_ndr1_0 & bnd_c2_1 bnd_a860) &
% 6.91/6.47 (ALL X81.
% 6.91/6.47 bnd_ndr1_1 bnd_a860 -->
% 6.91/6.47 (~ bnd_c4_2 bnd_a860 X81 |
% 6.91/6.47 ~ bnd_c2_2 bnd_a860 X81) |
% 6.91/6.47 ~ bnd_c1_2 bnd_a860 X81) |
% 6.91/6.47 ((((bnd_ndr1_0 & ~ bnd_c2_1 bnd_a861) &
% 6.91/6.47 ~ bnd_c1_1 bnd_a861) &
% 6.91/6.47 bnd_ndr1_1 bnd_a861) &
% 6.91/6.47 bnd_c3_2 bnd_a861 bnd_a862) &
% 6.91/6.47 bnd_c1_2 bnd_a861 bnd_a862) |
% 6.91/6.47 ~ bnd_c4_0)) &
% 6.91/6.47 (((ALL X82.
% 6.91/6.47 bnd_ndr1_0 -->
% 6.91/6.47 ~ bnd_c5_1 X82 | bnd_c3_1 X82) |
% 6.91/6.47 ((bnd_ndr1_0 &
% 6.91/6.47 (ALL X83.
% 6.91/6.47 bnd_ndr1_1 bnd_a863 -->
% 6.91/6.47 bnd_c3_2 bnd_a863 X83 |
% 6.91/6.47 bnd_c4_2 bnd_a863 X83)) &
% 6.91/6.47 bnd_c5_1 bnd_a863) &
% 6.91/6.47 ~ bnd_c1_1 bnd_a863) |
% 6.91/6.47 (ALL X84.
% 6.91/6.47 bnd_ndr1_0 -->
% 6.91/6.47 (bnd_c3_1 X84 | ~ bnd_c4_1 X84) |
% 6.91/6.47 bnd_c2_1 X84))) &
% 6.91/6.47 (~ bnd_c1_0 |
% 6.91/6.47 ((((bnd_ndr1_0 & ~ bnd_c4_1 bnd_a864) &
% 6.91/6.47 bnd_ndr1_1 bnd_a864) &
% 6.91/6.47 bnd_c1_2 bnd_a864 bnd_a865) &
% 6.91/6.47 bnd_c2_2 bnd_a864 bnd_a865) &
% 6.91/6.47 bnd_c4_2 bnd_a864 bnd_a865)) &
% 6.91/6.47 (~ bnd_c5_0 |
% 6.91/6.47 (ALL X85.
% 6.91/6.47 bnd_ndr1_0 -->
% 6.91/6.47 (~ bnd_c5_1 X85 |
% 6.91/6.47 (bnd_ndr1_1 X85 & bnd_c3_2 X85 bnd_a866) &
% 6.91/6.47 ~ bnd_c2_2 X85 bnd_a866) |
% 6.91/6.47 (ALL X86.
% 6.91/6.47 bnd_ndr1_1 X85 -->
% 6.91/6.47 (~ bnd_c3_2 X85 X86 | bnd_c2_2 X85 X86) |
% 6.91/6.47 bnd_c1_2 X85 X86)))) &
% 6.91/6.47 (bnd_c4_0 | bnd_c5_0)) &
% 6.91/6.47 ((~ bnd_c5_0 | ~ bnd_c3_0) |
% 6.91/6.47 (((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a867) &
% 6.91/6.47 ~ bnd_c3_2 bnd_a867 bnd_a868) &
% 6.91/6.47 bnd_c5_2 bnd_a867 bnd_a868) &
% 6.91/6.47 (ALL X87.
% 6.91/6.47 bnd_ndr1_1 bnd_a867 -->
% 6.91/6.47 (bnd_c5_2 bnd_a867 X87 |
% 6.91/6.47 bnd_c3_2 bnd_a867 X87) |
% 6.91/6.47 ~ bnd_c4_2 bnd_a867 X87)) &
% 6.91/6.47 bnd_ndr1_1 bnd_a867) &
% 6.91/6.47 bnd_c2_2 bnd_a867 bnd_a869) &
% 6.91/6.47 ~ bnd_c4_2 bnd_a867 bnd_a869) &
% 6.91/6.47 bnd_c3_2 bnd_a867 bnd_a869)) &
% 6.91/6.47 ((ALL X88.
% 6.91/6.47 bnd_ndr1_0 -->
% 6.91/6.47 (~ bnd_c1_1 X88 |
% 6.91/6.47 ((bnd_ndr1_1 X88 & bnd_c1_2 X88 bnd_a870) &
% 6.91/6.47 ~ bnd_c4_2 X88 bnd_a870) &
% 6.91/6.47 ~ bnd_c3_2 X88 bnd_a870) |
% 6.91/6.47 ~ bnd_c2_1 X88) |
% 6.91/6.47 ~ bnd_c1_0)) &
% 6.91/6.47 (((ALL X89.
% 6.91/6.47 bnd_ndr1_0 -->
% 6.91/6.47 (bnd_ndr1_1 X89 & bnd_c3_2 X89 bnd_a871) &
% 6.91/6.47 bnd_c5_2 X89 bnd_a871 |
% 6.91/6.47 ((bnd_ndr1_1 X89 & ~ bnd_c5_2 X89 bnd_a872) &
% 6.91/6.47 ~ bnd_c4_2 X89 bnd_a872) &
% 6.91/6.47 bnd_c3_2 X89 bnd_a872) |
% 6.91/6.47 bnd_c4_0) |
% 6.91/6.47 ~ bnd_c5_0)) &
% 6.91/6.47 (~ bnd_c1_0 |
% 6.91/6.47 ((((bnd_ndr1_0 & bnd_c3_1 bnd_a873) &
% 6.91/6.47 bnd_ndr1_1 bnd_a873) &
% 6.91/6.47 ~ bnd_c3_2 bnd_a873 bnd_a874) &
% 6.91/6.47 bnd_c5_2 bnd_a873 bnd_a874) &
% 6.91/6.47 ~ bnd_c1_2 bnd_a873 bnd_a874)) &
% 6.91/6.47 (bnd_c3_0 |
% 6.91/6.47 ((bnd_ndr1_0 & ~ bnd_c4_1 bnd_a875) &
% 6.91/6.47 bnd_c2_1 bnd_a875) &
% 6.91/6.47 (ALL X90.
% 6.91/6.47 bnd_ndr1_1 bnd_a875 -->
% 6.91/6.47 ~ bnd_c1_2 bnd_a875 X90 |
% 6.91/6.47 ~ bnd_c4_2 bnd_a875 X90))) &
% 6.91/6.47 (bnd_c2_0 | ~ bnd_c4_0)) &
% 6.91/6.47 ((~ bnd_c2_0 |
% 6.91/6.47 (ALL X91.
% 6.91/6.47 bnd_ndr1_0 -->
% 6.91/6.47 (((bnd_ndr1_1 X91 & ~ bnd_c2_2 X91 bnd_a876) &
% 6.91/6.47 bnd_c5_2 X91 bnd_a876) &
% 6.91/6.47 bnd_c3_2 X91 bnd_a876 |
% 6.91/6.47 ((bnd_ndr1_1 X91 & bnd_c2_2 X91 bnd_a877) &
% 6.91/6.47 bnd_c4_2 X91 bnd_a877) &
% 6.91/6.47 bnd_c1_2 X91 bnd_a877) |
% 6.91/6.47 bnd_c3_1 X91)) |
% 6.91/6.47 (ALL X92.
% 6.91/6.47 bnd_ndr1_0 -->
% 6.91/6.47 (~ bnd_c5_1 X92 | ~ bnd_c4_1 X92) |
% 6.91/6.47 ((bnd_ndr1_1 X92 & ~ bnd_c3_2 X92 bnd_a878) &
% 6.91/6.47 bnd_c5_2 X92 bnd_a878) &
% 6.91/6.47 bnd_c2_2 X92 bnd_a878))) &
% 6.91/6.47 ((bnd_c3_0 | ~ bnd_c5_0) | ~ bnd_c1_0)) &
% 6.91/6.47 (~ bnd_c2_0 | ~ bnd_c1_0)) &
% 6.91/6.47 ((bnd_c3_0 |
% 6.91/6.47 ((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a879) &
% 6.91/6.47 ~ bnd_c3_2 bnd_a879 bnd_a880) &
% 6.91/6.47 ~ bnd_c4_2 bnd_a879 bnd_a880) &
% 6.91/6.47 bnd_c2_1 bnd_a879) &
% 6.91/6.47 (ALL X93.
% 6.91/6.47 bnd_ndr1_1 bnd_a879 -->
% 6.91/6.47 (bnd_c2_2 bnd_a879 X93 | ~ bnd_c1_2 bnd_a879 X93) |
% 6.91/6.47 ~ bnd_c4_2 bnd_a879 X93)) |
% 6.91/6.47 ~ bnd_c4_0)) &
% 6.91/6.47 (bnd_c1_0 |
% 6.91/6.47 (ALL X94.
% 6.91/6.47 bnd_ndr1_0 -->
% 6.91/6.47 (~ bnd_c4_1 X94 | bnd_c2_1 X94) | ~ bnd_c3_1 X94))) &
% 6.91/6.47 ((bnd_c1_0 | bnd_c5_0) |
% 6.91/6.47 (ALL X95.
% 6.91/6.47 bnd_ndr1_0 -->
% 6.91/6.47 ((bnd_ndr1_1 X95 & bnd_c2_2 X95 bnd_a881) &
% 6.91/6.47 ~ bnd_c5_2 X95 bnd_a881 |
% 6.91/6.47 ((bnd_ndr1_1 X95 & ~ bnd_c3_2 X95 bnd_a882) &
% 6.91/6.47 ~ bnd_c2_2 X95 bnd_a882) &
% 6.91/6.47 bnd_c5_2 X95 bnd_a882) |
% 6.91/6.47 bnd_c1_1 X95))) &
% 6.91/6.47 (((ALL X96.
% 6.91/6.47 bnd_ndr1_0 -->
% 6.91/6.47 ((ALL X97.
% 6.91/6.47 bnd_ndr1_1 X96 -->
% 6.91/6.47 (~ bnd_c3_2 X96 X97 | bnd_c5_2 X96 X97) |
% 6.91/6.47 bnd_c2_2 X96 X97) |
% 6.91/6.47 bnd_c5_1 X96) |
% 6.91/6.47 (ALL X98.
% 6.91/6.47 bnd_ndr1_1 X96 -->
% 6.91/6.47 (bnd_c5_2 X96 X98 | bnd_c3_2 X96 X98) |
% 6.91/6.47 bnd_c1_2 X96 X98)) |
% 6.91/6.47 bnd_c4_0) |
% 6.91/6.47 bnd_c3_0)) &
% 6.91/6.47 (((ALL X99.
% 6.91/6.47 bnd_ndr1_0 -->
% 6.91/6.47 (bnd_c5_1 X99 |
% 6.91/6.47 ((bnd_ndr1_1 X99 & ~ bnd_c2_2 X99 bnd_a883) &
% 6.91/6.47 bnd_c1_2 X99 bnd_a883) &
% 6.91/6.47 bnd_c3_2 X99 bnd_a883) |
% 6.91/6.47 ((bnd_ndr1_1 X99 & bnd_c4_2 X99 bnd_a884) &
% 6.91/6.47 ~ bnd_c2_2 X99 bnd_a884) &
% 6.91/6.47 ~ bnd_c3_2 X99 bnd_a884) |
% 6.91/6.47 (ALL X100.
% 6.91/6.47 bnd_ndr1_0 -->
% 6.91/6.47 (~ bnd_c4_1 X100 |
% 6.91/6.47 (ALL X101.
% 6.91/6.47 bnd_ndr1_1 X100 -->
% 6.91/6.47 (~ bnd_c5_2 X100 X101 | bnd_c1_2 X100 X101) |
% 6.91/6.47 bnd_c4_2 X100 X101)) |
% 6.91/6.47 bnd_c3_1 X100)) |
% 6.91/6.47 bnd_c1_0)) &
% 6.91/6.47 ((~ bnd_c1_0 | bnd_c3_0) |
% 6.91/6.47 (bnd_ndr1_0 &
% 6.91/6.47 (ALL X102.
% 6.91/6.47 bnd_ndr1_1 bnd_a885 -->
% 6.91/6.47 ~ bnd_c1_2 bnd_a885 X102 | ~ bnd_c3_2 bnd_a885 X102)) &
% 6.91/6.47 ~ bnd_c5_1 bnd_a885)) &
% 6.91/6.47 ((ALL X103.
% 6.91/6.47 bnd_ndr1_0 -->
% 6.91/6.47 (ALL X104.
% 6.91/6.47 bnd_ndr1_1 X103 -->
% 6.91/6.47 ~ bnd_c2_2 X103 X104 | bnd_c5_2 X103 X104) |
% 6.91/6.47 (bnd_ndr1_1 X103 & bnd_c4_2 X103 bnd_a886) &
% 6.91/6.47 bnd_c5_2 X103 bnd_a886) |
% 6.91/6.47 ~ bnd_c5_0)) &
% 6.91/6.47 ((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a887) &
% 6.91/6.47 ~ bnd_c4_2 bnd_a887 bnd_a888) &
% 6.91/6.47 bnd_c1_2 bnd_a887 bnd_a888) &
% 6.91/6.47 bnd_c3_2 bnd_a887 bnd_a888) &
% 6.91/6.47 bnd_c5_1 bnd_a887 |
% 6.91/6.47 (ALL X105.
% 6.91/6.47 bnd_ndr1_0 -->
% 6.91/6.47 (~ bnd_c1_1 X105 |
% 6.91/6.47 ((bnd_ndr1_1 X105 & bnd_c2_2 X105 bnd_a889) &
% 6.91/6.47 ~ bnd_c4_2 X105 bnd_a889) &
% 6.91/6.47 bnd_c3_2 X105 bnd_a889) |
% 6.91/6.47 ((bnd_ndr1_1 X105 & bnd_c4_2 X105 bnd_a890) &
% 6.91/6.47 bnd_c2_2 X105 bnd_a890) &
% 6.91/6.47 bnd_c3_2 X105 bnd_a890)) |
% 6.91/6.47 ((bnd_ndr1_0 &
% 6.91/6.47 (ALL X106.
% 6.91/6.47 bnd_ndr1_1 bnd_a891 -->
% 6.91/6.47 (~ bnd_c1_2 bnd_a891 X106 | ~ bnd_c5_2 bnd_a891 X106) |
% 6.91/6.47 ~ bnd_c4_2 bnd_a891 X106)) &
% 6.91/6.47 ~ bnd_c3_1 bnd_a891) &
% 6.91/6.47 (ALL X107.
% 6.91/6.47 bnd_ndr1_1 bnd_a891 -->
% 6.91/6.47 ~ bnd_c5_2 bnd_a891 X107 | bnd_c3_2 bnd_a891 X107))) &
% 6.91/6.47 (bnd_c5_0 |
% 6.91/6.47 (ALL X108. bnd_ndr1_0 --> ~ bnd_c3_1 X108 | bnd_c1_1 X108))) &
% 6.91/6.47 ((((bnd_ndr1_0 &
% 6.91/6.47 (ALL X109.
% 6.91/6.47 bnd_ndr1_1 bnd_a892 -->
% 6.91/6.47 (bnd_c1_2 bnd_a892 X109 | bnd_c3_2 bnd_a892 X109) |
% 6.91/6.47 ~ bnd_c2_2 bnd_a892 X109)) &
% 6.91/6.47 bnd_c5_1 bnd_a892) &
% 6.91/6.47 ~ bnd_c4_1 bnd_a892 |
% 6.91/6.47 ((bnd_ndr1_0 &
% 6.91/6.47 (ALL X110.
% 6.91/6.47 bnd_ndr1_1 bnd_a893 -->
% 6.91/6.47 bnd_c1_2 bnd_a893 X110 | bnd_c4_2 bnd_a893 X110)) &
% 6.91/6.47 ~ bnd_c5_1 bnd_a893) &
% 6.91/6.47 (ALL X111.
% 6.91/6.47 bnd_ndr1_1 bnd_a893 -->
% 6.91/6.47 bnd_c4_2 bnd_a893 X111 | ~ bnd_c5_2 bnd_a893 X111)) |
% 6.91/6.47 (((((bnd_ndr1_0 & ~ bnd_c2_1 bnd_a894) & bnd_c4_1 bnd_a894) &
% 6.91/6.47 bnd_ndr1_1 bnd_a894) &
% 6.91/6.47 ~ bnd_c5_2 bnd_a894 bnd_a895) &
% 6.91/6.47 bnd_c3_2 bnd_a894 bnd_a895) &
% 6.91/6.47 ~ bnd_c1_2 bnd_a894 bnd_a895)) &
% 6.91/6.47 (bnd_c5_0 |
% 6.91/6.47 (ALL X112.
% 6.91/6.47 bnd_ndr1_0 -->
% 6.91/6.47 (((bnd_ndr1_1 X112 & ~ bnd_c5_2 X112 bnd_a896) &
% 6.91/6.47 bnd_c3_2 X112 bnd_a896) &
% 6.91/6.47 ~ bnd_c2_2 X112 bnd_a896 |
% 6.91/6.47 (ALL X113.
% 6.91/6.47 bnd_ndr1_1 X112 -->
% 6.91/6.47 (bnd_c3_2 X112 X113 | ~ bnd_c4_2 X112 X113) |
% 6.91/6.47 bnd_c1_2 X112 X113)) |
% 6.91/6.47 bnd_c5_1 X112)))
% 13.42/12.91 Unfolded term: ~ (((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((bnd_ndr1_0 &
% 13.42/12.91 ~ bnd_c5_1 bnd_a775) &
% 13.42/12.91 ~ bnd_c3_1 bnd_a775) &
% 13.42/12.91 bnd_c1_1 bnd_a775 |
% 13.42/12.91 ~ bnd_c4_0) &
% 13.42/12.91 ((bnd_c5_0 |
% 13.42/12.91 (((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a776) &
% 13.42/12.91 ~ bnd_c3_2 bnd_a776 bnd_a777) &
% 13.42/12.91 bnd_c2_2 bnd_a776 bnd_a777) &
% 13.42/12.91 ~ bnd_c1_2 bnd_a776 bnd_a777) &
% 13.42/12.91 ~ bnd_c2_1 bnd_a776) &
% 13.42/12.91 (ALL U.
% 13.42/12.91 bnd_ndr1_1 bnd_a776 -->
% 13.42/12.91 bnd_c5_2 bnd_a776 U | ~ bnd_c3_2 bnd_a776 U)) |
% 13.42/12.91 (ALL V.
% 13.42/12.91 bnd_ndr1_0 -->
% 13.42/12.91 (~ bnd_c2_1 V |
% 13.42/12.91 ((bnd_ndr1_1 V & bnd_c3_2 V bnd_a778) & bnd_c1_2 V bnd_a778) &
% 13.42/12.91 bnd_c4_2 V bnd_a778) |
% 13.42/12.91 (ALL W.
% 13.42/12.91 bnd_ndr1_1 V -->
% 13.42/12.91 (bnd_c1_2 V W | bnd_c3_2 V W) | bnd_c5_2 V W)))) &
% 13.42/12.91 (((bnd_ndr1_0 & ~ bnd_c3_1 bnd_a779) &
% 13.42/12.91 (ALL X.
% 13.42/12.91 bnd_ndr1_1 bnd_a779 -->
% 13.42/12.91 (~ bnd_c1_2 bnd_a779 X | bnd_c2_2 bnd_a779 X) |
% 13.42/12.91 bnd_c3_2 bnd_a779 X) |
% 13.42/12.91 bnd_c3_0) |
% 13.42/12.91 (bnd_ndr1_0 &
% 13.42/12.91 (ALL Y.
% 13.42/12.91 bnd_ndr1_1 bnd_a780 -->
% 13.42/12.91 (bnd_c2_2 bnd_a780 Y | bnd_c3_2 bnd_a780 Y) |
% 13.42/12.91 bnd_c1_2 bnd_a780 Y)) &
% 13.42/12.91 bnd_c3_1 bnd_a780)) &
% 13.42/12.91 (~ bnd_c2_0 | bnd_c4_0)) &
% 13.42/12.91 (((bnd_ndr1_0 & ~ bnd_c4_1 bnd_a781) &
% 13.42/12.91 (ALL Z.
% 13.42/12.91 bnd_ndr1_1 bnd_a781 -->
% 13.42/12.91 (~ bnd_c2_2 bnd_a781 Z | bnd_c4_2 bnd_a781 Z) |
% 13.42/12.91 ~ bnd_c1_2 bnd_a781 Z) |
% 13.42/12.91 ~ bnd_c4_0) |
% 13.42/12.91 (ALL X1.
% 13.42/12.91 bnd_ndr1_0 -->
% 13.42/12.91 ((ALL X2.
% 13.42/12.91 bnd_ndr1_1 X1 -->
% 13.42/12.91 (bnd_c1_2 X1 X2 | ~ bnd_c2_2 X1 X2) | bnd_c4_2 X1 X2) |
% 13.42/12.91 (ALL X3. bnd_ndr1_1 X1 --> ~ bnd_c4_2 X1 X3 | ~ bnd_c2_2 X1 X3)) |
% 13.42/12.91 bnd_c1_1 X1))) &
% 13.42/12.91 ((~ bnd_c1_0 | ~ bnd_c4_0) |
% 13.42/12.91 (ALL X4.
% 13.42/12.91 bnd_ndr1_0 -->
% 13.42/12.91 (~ bnd_c3_1 X4 |
% 13.42/12.91 ((bnd_ndr1_1 X4 & ~ bnd_c2_2 X4 bnd_a782) &
% 13.42/12.91 ~ bnd_c5_2 X4 bnd_a782) &
% 13.42/12.91 ~ bnd_c1_2 X4 bnd_a782) |
% 13.42/12.91 ~ bnd_c1_1 X4))) &
% 13.42/12.91 ((bnd_c4_0 | ~ bnd_c1_0) |
% 13.42/12.91 (ALL X5.
% 13.42/12.91 bnd_ndr1_0 -->
% 13.42/12.91 (~ bnd_c5_1 X5 | bnd_c1_1 X5) |
% 13.42/12.91 ((bnd_ndr1_1 X5 & ~ bnd_c4_2 X5 bnd_a783) & ~ bnd_c2_2 X5 bnd_a783) &
% 13.42/12.91 ~ bnd_c3_2 X5 bnd_a783))) &
% 13.42/12.91 (((ALL X6.
% 13.42/12.91 bnd_ndr1_0 -->
% 13.42/12.91 ((ALL X7.
% 13.42/12.91 bnd_ndr1_1 X6 -->
% 13.42/12.91 (~ bnd_c5_2 X6 X7 | bnd_c3_2 X6 X7) | ~ bnd_c4_2 X6 X7) |
% 13.42/12.91 ~ bnd_c5_1 X6) |
% 13.42/12.91 (ALL X8. bnd_ndr1_1 X6 --> ~ bnd_c5_2 X6 X8 | ~ bnd_c1_2 X6 X8)) |
% 13.42/12.91 (ALL X9.
% 13.42/12.91 bnd_ndr1_0 -->
% 13.42/12.91 ((bnd_ndr1_1 X9 & bnd_c3_2 X9 bnd_a784) & bnd_c2_2 X9 bnd_a784) &
% 13.42/12.91 ~ bnd_c1_2 X9 bnd_a784 |
% 13.42/12.91 ~ bnd_c4_1 X9)) |
% 13.42/12.91 (ALL X10.
% 13.42/12.91 bnd_ndr1_0 -->
% 13.42/12.91 ((bnd_ndr1_1 X10 & bnd_c5_2 X10 bnd_a785) & ~ bnd_c2_2 X10 bnd_a785) &
% 13.42/12.91 ~ bnd_c1_2 X10 bnd_a785 |
% 13.42/12.91 bnd_c2_1 X10))) &
% 13.42/12.91 ((((bnd_ndr1_0 &
% 13.42/12.91 (ALL X11.
% 13.42/12.91 bnd_ndr1_1 bnd_a786 -->
% 13.42/12.91 (bnd_c3_2 bnd_a786 X11 | ~ bnd_c1_2 bnd_a786 X11) |
% 13.42/12.91 bnd_c5_2 bnd_a786 X11)) &
% 13.42/12.91 (ALL X12.
% 13.42/12.91 bnd_ndr1_1 bnd_a786 -->
% 13.42/12.91 (bnd_c5_2 bnd_a786 X12 | bnd_c4_2 bnd_a786 X12) |
% 13.42/12.91 ~ bnd_c2_2 bnd_a786 X12)) &
% 13.42/12.91 ~ bnd_c4_1 bnd_a786 |
% 13.42/12.91 (ALL X13.
% 13.42/12.91 bnd_ndr1_0 -->
% 13.42/12.91 (((bnd_ndr1_1 X13 & ~ bnd_c4_2 X13 bnd_a787) &
% 13.42/12.91 ~ bnd_c3_2 X13 bnd_a787) &
% 13.42/12.91 bnd_c5_2 X13 bnd_a787 |
% 13.42/12.91 ((bnd_ndr1_1 X13 & ~ bnd_c2_2 X13 bnd_a788) & bnd_c3_2 X13 bnd_a788) &
% 13.42/12.91 bnd_c1_2 X13 bnd_a788) |
% 13.42/12.91 bnd_c3_1 X13)) |
% 13.42/12.91 (((((bnd_ndr1_0 & ~ bnd_c5_1 bnd_a789) & bnd_ndr1_1 bnd_a789) &
% 13.42/12.91 bnd_c5_2 bnd_a789 bnd_a790) &
% 13.42/12.91 bnd_c1_2 bnd_a789 bnd_a790) &
% 13.42/12.91 ~ bnd_c4_2 bnd_a789 bnd_a790) &
% 13.42/12.91 bnd_c1_1 bnd_a789)) &
% 13.42/12.91 (((ALL X14.
% 13.42/12.91 bnd_ndr1_0 -->
% 13.42/12.91 ((ALL X15.
% 13.42/12.91 bnd_ndr1_1 X14 -->
% 13.42/12.91 (bnd_c1_2 X14 X15 | bnd_c5_2 X14 X15) | bnd_c3_2 X14 X15) |
% 13.42/12.91 ~ bnd_c2_1 X14) |
% 13.42/12.91 bnd_c5_1 X14) |
% 13.42/12.91 ~ bnd_c3_0) |
% 13.42/12.91 bnd_c2_0)) &
% 13.42/12.91 (((ALL X16.
% 13.42/12.91 bnd_ndr1_0 -->
% 13.42/12.91 ((ALL X17.
% 13.42/12.91 bnd_ndr1_1 X16 -->
% 13.42/12.91 (bnd_c4_2 X16 X17 | ~ bnd_c5_2 X16 X17) | bnd_c2_2 X16 X17) |
% 13.42/12.91 ((bnd_ndr1_1 X16 & bnd_c4_2 X16 bnd_a791) & bnd_c3_2 X16 bnd_a791) &
% 13.42/12.91 bnd_c1_2 X16 bnd_a791) |
% 13.42/12.92 bnd_c5_1 X16) |
% 13.42/12.92 (ALL X18.
% 13.42/12.92 bnd_ndr1_0 --> (~ bnd_c2_1 X18 | bnd_c4_1 X18) | bnd_c1_1 X18)) |
% 13.42/12.92 bnd_c2_0)) &
% 13.42/12.92 ((bnd_c4_0 | ~ bnd_c2_0) | bnd_c1_0)) &
% 13.42/12.92 (((((((((bnd_ndr1_0 &
% 13.42/12.92 bnd_ndr1_1 bnd_a792) &
% 13.42/12.92 ~ bnd_c5_2 bnd_a792 bnd_a793) &
% 13.42/12.92 bnd_c1_2 bnd_a792 bnd_a793) &
% 13.42/12.92 bnd_c4_1 bnd_a792) &
% 13.42/12.92 bnd_ndr1_1 bnd_a792) &
% 13.42/12.92 ~ bnd_c4_2 bnd_a792 bnd_a794) &
% 13.42/12.92 bnd_c3_2 bnd_a792 bnd_a794) &
% 13.42/12.92 ~ bnd_c1_2 bnd_a792 bnd_a794 |
% 13.42/12.92 ((bnd_ndr1_0 &
% 13.42/12.92 (ALL X19.
% 13.42/12.92 bnd_ndr1_1 bnd_a795 -->
% 13.42/12.92 (~ bnd_c2_2 bnd_a795 X19 | bnd_c1_2 bnd_a795 X19) |
% 13.42/12.92 ~ bnd_c5_2 bnd_a795 X19)) &
% 13.42/12.92 (ALL X20.
% 13.42/12.92 bnd_ndr1_1 bnd_a795 -->
% 13.42/12.92 (~ bnd_c1_2 bnd_a795 X20 | bnd_c5_2 bnd_a795 X20) |
% 13.42/12.92 bnd_c3_2 bnd_a795 X20)) &
% 13.42/12.92 ~ bnd_c1_1 bnd_a795) |
% 13.42/12.92 ~ bnd_c3_0)) &
% 13.42/12.92 ((~ bnd_c2_0 | ~ bnd_c4_0) | bnd_c3_0)) &
% 13.42/12.92 ((ALL X21.
% 13.42/12.92 bnd_ndr1_0 -->
% 13.42/12.92 ((ALL X22.
% 13.42/12.92 bnd_ndr1_1 X21 -->
% 13.42/12.92 (bnd_c4_2 X21 X22 | ~ bnd_c5_2 X21 X22) | bnd_c3_2 X21 X22) |
% 13.42/12.92 (ALL X23.
% 13.42/12.92 bnd_ndr1_1 X21 --> bnd_c3_2 X21 X23 | bnd_c2_2 X21 X23)) |
% 13.42/12.92 ~ bnd_c3_1 X21) |
% 13.42/12.92 (((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a796) &
% 13.42/12.92 ~ bnd_c5_2 bnd_a796 bnd_a797) &
% 13.42/12.92 bnd_c2_2 bnd_a796 bnd_a797) &
% 13.42/12.92 bnd_c1_2 bnd_a796 bnd_a797) &
% 13.42/12.92 bnd_ndr1_1 bnd_a796) &
% 13.42/12.92 ~ bnd_c2_2 bnd_a796 bnd_a798) &
% 13.42/12.92 ~ bnd_c3_2 bnd_a796 bnd_a798) &
% 13.42/12.92 ~ bnd_c2_1 bnd_a796)) &
% 13.42/12.92 ((bnd_c5_0 |
% 13.42/12.92 (ALL X24.
% 13.42/12.92 bnd_ndr1_0 -->
% 13.42/12.92 ((bnd_ndr1_1 X24 &
% 13.42/12.92 bnd_c3_2 X24 bnd_a799) &
% 13.42/12.92 bnd_c4_2 X24 bnd_a799) &
% 13.42/12.92 ~ bnd_c1_2 X24 bnd_a799 |
% 13.42/12.92 bnd_c4_1 X24)) |
% 13.42/12.92 bnd_c4_0)) &
% 13.42/12.92 (bnd_c1_0 |
% 13.42/12.92 ((bnd_ndr1_0 & bnd_c2_1 bnd_a800) &
% 13.42/12.92 (ALL X25.
% 13.42/12.92 bnd_ndr1_1 bnd_a800 -->
% 13.42/12.92 (~ bnd_c4_2 bnd_a800 X25 |
% 13.42/12.92 ~ bnd_c1_2 bnd_a800 X25) |
% 13.42/12.92 ~ bnd_c5_2 bnd_a800 X25)) &
% 13.42/12.92 (ALL X26.
% 13.42/12.92 bnd_ndr1_1 bnd_a800 -->
% 13.42/12.92 bnd_c5_2 bnd_a800 X26 |
% 13.42/12.92 bnd_c2_2 bnd_a800 X26))) &
% 13.42/12.92 (((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a801) &
% 13.42/12.92 bnd_c5_2 bnd_a801 bnd_a802) &
% 13.42/12.92 bnd_c1_2 bnd_a801 bnd_a802) &
% 13.42/12.92 bnd_c4_2 bnd_a801 bnd_a802) &
% 13.42/12.92 (ALL X27.
% 13.42/12.92 bnd_ndr1_1 bnd_a801 -->
% 13.42/12.92 (bnd_c5_2 bnd_a801 X27 |
% 13.42/12.92 ~ bnd_c1_2 bnd_a801 X27) |
% 13.42/12.92 ~ bnd_c3_2 bnd_a801 X27)) &
% 13.42/12.92 bnd_c2_1 bnd_a801 |
% 13.42/12.92 (ALL X28.
% 13.42/12.92 bnd_ndr1_0 -->
% 13.42/12.92 ~ bnd_c4_1 X28 | bnd_c2_1 X28)) |
% 13.42/12.92 (ALL X29.
% 13.42/12.92 bnd_ndr1_0 -->
% 13.42/12.92 (((bnd_ndr1_1 X29 &
% 13.42/12.92 bnd_c2_2 X29 bnd_a803) &
% 13.42/12.92 ~ bnd_c5_2 X29 bnd_a803) &
% 13.42/12.92 bnd_c4_2 X29 bnd_a803 |
% 13.42/12.92 ~ bnd_c3_1 X29) |
% 13.42/12.92 (ALL X30.
% 13.42/12.92 bnd_ndr1_1 X29 -->
% 13.42/12.92 (~ bnd_c2_2 X29 X30 |
% 13.42/12.92 ~ bnd_c4_2 X29 X30) |
% 13.42/12.92 ~ bnd_c3_2 X29 X30)))) &
% 13.42/12.92 ((~ bnd_c3_0 |
% 13.42/12.92 (bnd_ndr1_0 &
% 13.42/12.92 (ALL X31.
% 13.42/12.92 bnd_ndr1_1 bnd_a804 -->
% 13.42/12.92 (bnd_c1_2 bnd_a804 X31 |
% 13.42/12.92 bnd_c3_2 bnd_a804 X31) |
% 13.42/12.92 bnd_c4_2 bnd_a804 X31)) &
% 13.42/12.92 bnd_c5_1 bnd_a804) |
% 13.42/12.92 (ALL X32.
% 13.42/12.92 bnd_ndr1_0 -->
% 13.42/12.92 ((bnd_ndr1_1 X32 & bnd_c2_2 X32 bnd_a805) &
% 13.42/12.92 bnd_c4_2 X32 bnd_a805) &
% 13.42/12.92 ~ bnd_c5_2 X32 bnd_a805 |
% 13.42/12.92 ~ bnd_c4_1 X32))) &
% 13.42/12.92 (((ALL X33.
% 13.42/12.92 bnd_ndr1_0 -->
% 13.42/12.92 (((bnd_ndr1_1 X33 & bnd_c5_2 X33 bnd_a806) &
% 13.42/12.92 bnd_c2_2 X33 bnd_a806) &
% 13.42/12.92 bnd_c4_2 X33 bnd_a806 |
% 13.42/12.92 (bnd_ndr1_1 X33 &
% 13.42/12.92 ~ bnd_c3_2 X33 bnd_a807) &
% 13.42/12.92 ~ bnd_c2_2 X33 bnd_a807) |
% 13.42/12.92 ((bnd_ndr1_1 X33 & bnd_c5_2 X33 bnd_a808) &
% 13.42/12.92 ~ bnd_c2_2 X33 bnd_a808) &
% 13.42/12.92 bnd_c4_2 X33 bnd_a808) |
% 13.42/12.92 (ALL X34.
% 13.42/12.92 bnd_ndr1_0 -->
% 13.42/12.92 (~ bnd_c2_1 X34 | ~ bnd_c3_1 X34) |
% 13.42/12.92 ((bnd_ndr1_1 X34 & bnd_c5_2 X34 bnd_a809) &
% 13.42/12.92 bnd_c3_2 X34 bnd_a809) &
% 13.42/12.92 bnd_c1_2 X34 bnd_a809)) |
% 13.42/12.92 bnd_c4_0)) &
% 13.42/12.92 ((ALL X35.
% 13.42/12.92 bnd_ndr1_0 -->
% 13.42/12.92 (~ bnd_c5_1 X35 | bnd_c3_1 X35) |
% 13.42/12.92 ~ bnd_c4_1 X35) |
% 13.42/12.92 ~ bnd_c5_0)) &
% 13.42/12.92 ((bnd_c4_0 |
% 13.42/12.92 (bnd_ndr1_0 & bnd_c2_1 bnd_a810) &
% 13.42/12.92 bnd_c4_1 bnd_a810) |
% 13.42/12.92 bnd_c5_0)) &
% 13.42/12.92 ((ALL X36.
% 13.42/12.92 bnd_ndr1_0 -->
% 13.42/12.92 (~ bnd_c3_1 X36 | bnd_c1_1 X36) |
% 13.42/12.92 (bnd_ndr1_1 X36 & ~ bnd_c2_2 X36 bnd_a811) &
% 13.42/12.92 bnd_c3_2 X36 bnd_a811) |
% 13.42/12.92 ((((bnd_ndr1_0 & ~ bnd_c3_1 bnd_a812) &
% 13.42/12.92 bnd_ndr1_1 bnd_a812) &
% 13.42/12.92 bnd_c3_2 bnd_a812 bnd_a813) &
% 13.42/12.92 bnd_c1_2 bnd_a812 bnd_a813) &
% 13.42/12.92 bnd_c2_2 bnd_a812 bnd_a813)) &
% 13.42/12.92 ((ALL X37.
% 13.42/12.92 bnd_ndr1_0 --> ~ bnd_c5_1 X37 | ~ bnd_c4_1 X37) |
% 13.42/12.92 bnd_c3_0)) &
% 13.42/12.92 ((~ bnd_c1_0 |
% 13.42/12.92 (bnd_ndr1_0 & bnd_c3_1 bnd_a814) &
% 13.42/12.92 bnd_c2_1 bnd_a814) |
% 13.42/12.92 ~ bnd_c2_0)) &
% 13.42/12.92 (((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a815) &
% 13.42/12.92 bnd_c1_2 bnd_a815 bnd_a816) &
% 13.42/12.92 bnd_c3_2 bnd_a815 bnd_a816) &
% 13.42/12.92 ~ bnd_c5_2 bnd_a815 bnd_a816) &
% 13.42/12.92 bnd_c3_1 bnd_a815) &
% 13.42/12.92 ~ bnd_c5_1 bnd_a815 |
% 13.42/12.92 bnd_c2_0) |
% 13.42/12.92 bnd_c5_0)) &
% 13.42/12.92 (((bnd_ndr1_0 & bnd_c4_1 bnd_a817) & bnd_c2_1 bnd_a817 |
% 13.42/12.92 (((((bnd_ndr1_0 & bnd_c3_1 bnd_a818) &
% 13.42/12.92 bnd_ndr1_1 bnd_a818) &
% 13.42/12.92 ~ bnd_c3_2 bnd_a818 bnd_a819) &
% 13.42/12.92 ~ bnd_c2_2 bnd_a818 bnd_a819) &
% 13.42/12.92 ~ bnd_c5_2 bnd_a818 bnd_a819) &
% 13.42/12.92 (ALL X38.
% 13.42/12.92 bnd_ndr1_1 bnd_a818 -->
% 13.42/12.92 (~ bnd_c1_2 bnd_a818 X38 | bnd_c4_2 bnd_a818 X38) |
% 13.42/12.92 bnd_c5_2 bnd_a818 X38)) |
% 13.42/12.92 ((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a820) &
% 13.42/12.92 ~ bnd_c3_2 bnd_a820 bnd_a821) &
% 13.42/12.92 bnd_c1_2 bnd_a820 bnd_a821) &
% 13.42/12.92 ~ bnd_c5_2 bnd_a820 bnd_a821) &
% 13.42/12.92 bnd_ndr1_1 bnd_a820) &
% 13.42/12.92 ~ bnd_c5_2 bnd_a820 bnd_a822) &
% 13.42/12.92 ~ bnd_c2_2 bnd_a820 bnd_a822)) &
% 13.42/12.92 (((bnd_ndr1_0 &
% 13.42/12.92 (ALL X39.
% 13.42/12.92 bnd_ndr1_1 bnd_a823 -->
% 13.42/12.92 (~ bnd_c3_2 bnd_a823 X39 |
% 13.42/12.92 ~ bnd_c2_2 bnd_a823 X39) |
% 13.42/12.92 bnd_c1_2 bnd_a823 X39)) &
% 13.42/12.92 bnd_c5_1 bnd_a823 |
% 13.42/12.92 bnd_c5_0) |
% 13.42/12.92 ~ bnd_c2_0)) &
% 13.42/12.92 ((bnd_c3_0 |
% 13.42/12.92 (ALL X40.
% 13.42/12.92 bnd_ndr1_0 --> ~ bnd_c5_1 X40 | bnd_c4_1 X40)) |
% 13.42/12.92 ((bnd_ndr1_0 & ~ bnd_c2_1 bnd_a824) &
% 13.42/12.92 (ALL X41.
% 13.42/12.92 bnd_ndr1_1 bnd_a824 -->
% 13.42/12.92 ~ bnd_c4_2 bnd_a824 X41 | ~ bnd_c1_2 bnd_a824 X41)) &
% 13.42/12.92 ~ bnd_c4_1 bnd_a824)) &
% 13.42/12.92 (((ALL X42.
% 13.42/12.92 bnd_ndr1_0 -->
% 13.42/12.92 (((bnd_ndr1_1 X42 & bnd_c3_2 X42 bnd_a825) &
% 13.42/12.92 ~ bnd_c2_2 X42 bnd_a825) &
% 13.42/12.92 bnd_c1_2 X42 bnd_a825 |
% 13.42/12.92 bnd_c1_1 X42) |
% 13.42/12.92 ~ bnd_c2_1 X42) |
% 13.42/12.92 ~ bnd_c5_0) |
% 13.42/12.92 (ALL X43.
% 13.42/12.92 bnd_ndr1_0 -->
% 13.42/12.92 (bnd_c1_1 X43 |
% 13.42/12.92 ((bnd_ndr1_1 X43 & ~ bnd_c1_2 X43 bnd_a826) &
% 13.42/12.92 ~ bnd_c2_2 X43 bnd_a826) &
% 13.42/12.92 bnd_c5_2 X43 bnd_a826) |
% 13.42/12.92 (ALL X44.
% 13.42/12.92 bnd_ndr1_1 X43 -->
% 13.42/12.92 (bnd_c5_2 X43 X44 | ~ bnd_c2_2 X43 X44) |
% 13.42/12.92 bnd_c4_2 X43 X44)))) &
% 13.42/12.92 (~ bnd_c1_0 | bnd_c3_0)) &
% 13.42/12.92 (((bnd_ndr1_0 & ~ bnd_c5_1 bnd_a827) &
% 13.42/12.92 (ALL X45.
% 13.42/12.92 bnd_ndr1_1 bnd_a827 -->
% 13.42/12.92 (bnd_c1_2 bnd_a827 X45 | ~ bnd_c2_2 bnd_a827 X45) |
% 13.42/12.92 bnd_c5_2 bnd_a827 X45) |
% 13.42/12.92 (ALL X46.
% 13.42/12.92 bnd_ndr1_0 -->
% 13.42/12.92 (bnd_c4_1 X46 |
% 13.42/12.92 (ALL X47.
% 13.42/12.92 bnd_ndr1_1 X46 -->
% 13.42/12.92 (~ bnd_c3_2 X46 X47 | bnd_c5_2 X46 X47) |
% 13.42/12.92 bnd_c4_2 X46 X47)) |
% 13.42/12.92 (ALL X48.
% 13.42/12.92 bnd_ndr1_1 X46 -->
% 13.42/12.92 (bnd_c4_2 X46 X48 | ~ bnd_c2_2 X46 X48) |
% 13.42/12.92 bnd_c1_2 X46 X48))) |
% 13.42/12.92 bnd_c2_0)) &
% 13.42/12.92 (((ALL X49.
% 13.42/12.92 bnd_ndr1_0 -->
% 13.42/12.92 ((ALL X50.
% 13.42/12.92 bnd_ndr1_1 X49 -->
% 13.42/12.92 (~ bnd_c4_2 X49 X50 | ~ bnd_c1_2 X49 X50) |
% 13.42/12.92 bnd_c2_2 X49 X50) |
% 13.42/12.92 bnd_c2_1 X49) |
% 13.42/12.92 ~ bnd_c4_1 X49) |
% 13.42/12.92 bnd_c3_0) |
% 13.42/12.92 ~ bnd_c2_0)) &
% 13.42/12.92 (~ bnd_c4_0 | ~ bnd_c5_0)) &
% 13.42/12.92 (((ALL X51.
% 13.42/12.92 bnd_ndr1_0 -->
% 13.42/12.92 (bnd_c2_1 X51 | ~ bnd_c1_1 X51) | ~ bnd_c5_1 X51) |
% 13.42/12.92 bnd_c3_0) |
% 13.42/12.92 ((((bnd_ndr1_0 &
% 13.42/12.92 (ALL X52.
% 13.42/12.92 bnd_ndr1_1 bnd_a828 -->
% 13.42/12.92 bnd_c2_2 bnd_a828 X52 | bnd_c4_2 bnd_a828 X52)) &
% 13.42/12.92 bnd_ndr1_1 bnd_a828) &
% 13.42/12.92 ~ bnd_c1_2 bnd_a828 bnd_a829) &
% 13.42/12.92 ~ bnd_c4_2 bnd_a828 bnd_a829) &
% 13.42/12.92 (ALL X53.
% 13.42/12.92 bnd_ndr1_1 bnd_a828 -->
% 13.42/12.92 (bnd_c4_2 bnd_a828 X53 | bnd_c3_2 bnd_a828 X53) |
% 13.42/12.92 ~ bnd_c5_2 bnd_a828 X53))) &
% 13.42/12.92 (bnd_c2_0 |
% 13.42/12.92 ((bnd_ndr1_0 & bnd_c2_1 bnd_a830) &
% 13.42/12.92 (ALL X54.
% 13.42/12.92 bnd_ndr1_1 bnd_a830 -->
% 13.42/12.92 (bnd_c2_2 bnd_a830 X54 | ~ bnd_c1_2 bnd_a830 X54) |
% 13.42/12.92 ~ bnd_c3_2 bnd_a830 X54)) &
% 13.42/12.92 (ALL X55.
% 13.42/12.92 bnd_ndr1_1 bnd_a830 -->
% 13.42/12.92 bnd_c5_2 bnd_a830 X55 | bnd_c1_2 bnd_a830 X55))) &
% 13.42/12.92 ((bnd_c4_0 | ~ bnd_c1_0) |
% 13.42/12.92 (ALL X56.
% 13.42/12.92 bnd_ndr1_0 -->
% 13.42/12.92 ((ALL X57.
% 13.42/12.92 bnd_ndr1_1 X56 --> bnd_c3_2 X56 X57 | bnd_c1_2 X56 X57) |
% 13.42/12.92 ~ bnd_c1_1 X56) |
% 13.42/12.92 (ALL X58.
% 13.42/12.92 bnd_ndr1_1 X56 -->
% 13.42/12.92 (bnd_c4_2 X56 X58 | bnd_c5_2 X56 X58) |
% 13.42/12.92 bnd_c3_2 X56 X58)))) &
% 13.42/12.92 (((bnd_ndr1_0 & bnd_c3_1 bnd_a831) & ~ bnd_c4_1 bnd_a831 |
% 13.42/12.92 (ALL X59.
% 13.42/12.92 bnd_ndr1_0 -->
% 13.42/12.92 (((bnd_ndr1_1 X59 & ~ bnd_c2_2 X59 bnd_a832) &
% 13.42/12.92 ~ bnd_c1_2 X59 bnd_a832) &
% 13.42/12.92 bnd_c3_2 X59 bnd_a832 |
% 13.42/12.92 (ALL X60.
% 13.42/12.92 bnd_ndr1_1 X59 -->
% 13.42/12.92 ~ bnd_c4_2 X59 X60 | bnd_c5_2 X59 X60)) |
% 13.42/12.92 (ALL X61.
% 13.42/12.92 bnd_ndr1_1 X59 -->
% 13.42/12.92 (~ bnd_c5_2 X59 X61 | ~ bnd_c2_2 X59 X61) |
% 13.42/12.92 bnd_c3_2 X59 X61))) |
% 13.42/12.92 bnd_c2_0)) &
% 13.42/12.92 ((ALL X62.
% 13.42/12.92 bnd_ndr1_0 -->
% 13.42/12.92 (((bnd_ndr1_1 X62 & bnd_c1_2 X62 bnd_a833) &
% 13.42/12.92 ~ bnd_c5_2 X62 bnd_a833) &
% 13.42/12.92 bnd_c3_2 X62 bnd_a833 |
% 13.42/12.92 (bnd_ndr1_1 X62 & ~ bnd_c2_2 X62 bnd_a834) &
% 13.42/12.92 ~ bnd_c5_2 X62 bnd_a834) |
% 13.42/12.92 (ALL X63.
% 13.42/12.92 bnd_ndr1_1 X62 -->
% 13.42/12.92 (bnd_c1_2 X62 X63 | ~ bnd_c3_2 X62 X63) |
% 13.42/12.92 ~ bnd_c2_2 X62 X63)) |
% 13.42/12.92 bnd_c3_0)) &
% 13.42/12.92 ((bnd_c5_0 | ~ bnd_c4_0) |
% 13.42/12.92 (ALL X64.
% 13.42/12.92 bnd_ndr1_0 -->
% 13.42/12.92 ~ bnd_c3_1 X64 |
% 13.42/12.92 ((bnd_ndr1_1 X64 & ~ bnd_c5_2 X64 bnd_a835) &
% 13.42/12.92 bnd_c1_2 X64 bnd_a835) &
% 13.42/12.92 ~ bnd_c4_2 X64 bnd_a835))) &
% 13.42/12.92 ((bnd_c5_0 |
% 13.42/12.92 (((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a836) &
% 13.42/12.92 bnd_c4_2 bnd_a836 bnd_a837) &
% 13.42/12.92 ~ bnd_c1_2 bnd_a836 bnd_a837) &
% 13.42/12.92 ~ bnd_c2_2 bnd_a836 bnd_a837) &
% 13.42/12.92 bnd_c5_1 bnd_a836) &
% 13.42/12.92 bnd_c1_1 bnd_a836) |
% 13.42/12.92 (bnd_ndr1_0 &
% 13.42/12.92 (ALL X65.
% 13.42/12.92 bnd_ndr1_1 bnd_a838 -->
% 13.42/12.92 (bnd_c2_2 bnd_a838 X65 | ~ bnd_c4_2 bnd_a838 X65) |
% 13.42/12.92 bnd_c3_2 bnd_a838 X65)) &
% 13.42/12.92 ~ bnd_c4_1 bnd_a838)) &
% 13.42/12.92 (~ bnd_c5_0 |
% 13.42/12.92 (((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a839) &
% 13.42/12.92 bnd_c4_2 bnd_a839 bnd_a840) &
% 13.42/12.92 ~ bnd_c5_2 bnd_a839 bnd_a840) &
% 13.42/12.92 bnd_c2_2 bnd_a839 bnd_a840) &
% 13.42/12.92 bnd_ndr1_1 bnd_a839) &
% 13.42/12.92 ~ bnd_c2_2 bnd_a839 bnd_a841) &
% 13.42/12.92 ~ bnd_c4_2 bnd_a839 bnd_a841) &
% 13.42/12.92 (ALL X66.
% 13.42/12.92 bnd_ndr1_1 bnd_a839 -->
% 13.42/12.92 bnd_c4_2 bnd_a839 X66 | ~ bnd_c5_2 bnd_a839 X66))) &
% 13.42/12.92 ((~ bnd_c2_0 | bnd_c3_0) |
% 13.42/12.92 (ALL X67.
% 13.42/12.92 bnd_ndr1_0 -->
% 13.42/12.92 (~ bnd_c2_1 X67 | bnd_c3_1 X67) |
% 13.42/12.92 ((bnd_ndr1_1 X67 & bnd_c4_2 X67 bnd_a842) & bnd_c5_2 X67 bnd_a842) &
% 13.42/12.92 ~ bnd_c2_2 X67 bnd_a842))) &
% 13.42/12.92 (bnd_c3_0 | (ALL X68. bnd_ndr1_0 --> bnd_c3_1 X68 | bnd_c1_1 X68))) &
% 13.42/12.92 (~ bnd_c5_0 | ~ bnd_c1_0)) &
% 13.42/12.92 ((~ bnd_c3_0 | (bnd_ndr1_0 & bnd_c5_1 bnd_a843) & ~ bnd_c1_1 bnd_a843) |
% 13.42/12.92 bnd_c4_0)) &
% 13.42/12.92 ((~ bnd_c4_0 | bnd_c5_0) |
% 13.42/12.92 ~ bnd_c2_0)) &
% 13.42/12.92 ((~ bnd_c1_0 | ~ bnd_c5_0) |
% 13.42/12.92 bnd_c4_0)) &
% 13.42/12.92 ((~ bnd_c2_0 |
% 13.42/12.92 bnd_ndr1_0 & ~ bnd_c3_1 bnd_a844) |
% 13.42/12.92 ((bnd_ndr1_0 & ~ bnd_c2_1 bnd_a845) &
% 13.42/12.92 ~ bnd_c1_1 bnd_a845) &
% 13.42/12.92 ~ bnd_c3_1 bnd_a845)) &
% 13.42/12.92 ((bnd_c3_0 |
% 13.42/12.92 (ALL X69.
% 13.42/12.92 bnd_ndr1_0 -->
% 13.42/12.92 (~ bnd_c3_1 X69 | ~ bnd_c1_1 X69) |
% 13.42/12.92 (ALL X70.
% 13.42/12.92 bnd_ndr1_1 X69 -->
% 13.42/12.92 (bnd_c3_2 X69 X70 | bnd_c5_2 X69 X70) | bnd_c4_2 X69 X70))) |
% 13.42/12.92 (ALL X71.
% 13.42/12.92 bnd_ndr1_0 -->
% 13.42/12.92 (((bnd_ndr1_1 X71 & bnd_c4_2 X71 bnd_a846) & bnd_c5_2 X71 bnd_a846) &
% 13.42/12.92 bnd_c3_2 X71 bnd_a846 |
% 13.42/12.92 bnd_c3_1 X71) |
% 13.42/12.92 ~ bnd_c1_1 X71))) &
% 13.42/12.92 (((ALL X72.
% 13.42/12.92 bnd_ndr1_0 -->
% 13.42/12.92 ((bnd_ndr1_1 X72 & bnd_c3_2 X72 bnd_a847) & ~ bnd_c4_2 X72 bnd_a847 |
% 13.42/12.92 ((bnd_ndr1_1 X72 & ~ bnd_c5_2 X72 bnd_a848) & bnd_c3_2 X72 bnd_a848) &
% 13.42/12.92 ~ bnd_c4_2 X72 bnd_a848) |
% 13.42/12.92 ~ bnd_c2_1 X72) |
% 13.42/12.92 (ALL X73.
% 13.42/12.92 bnd_ndr1_0 -->
% 13.42/12.92 (ALL X74. bnd_ndr1_1 X73 --> ~ bnd_c4_2 X73 X74 | ~ bnd_c5_2 X73 X74) |
% 13.42/12.92 ~ bnd_c1_1 X73)) |
% 13.42/12.92 ~ bnd_c2_0)) &
% 13.42/12.92 (((((((((bnd_ndr1_0 & ~ bnd_c5_1 bnd_a849) &
% 13.42/12.92 bnd_ndr1_1 bnd_a849) &
% 13.42/12.92 ~ bnd_c3_2 bnd_a849 bnd_a850) &
% 13.42/12.92 ~ bnd_c4_2 bnd_a849 bnd_a850) &
% 13.42/12.92 bnd_c1_2 bnd_a849 bnd_a850) &
% 13.42/12.92 bnd_ndr1_1 bnd_a849) &
% 13.42/12.92 bnd_c1_2 bnd_a849 bnd_a851) &
% 13.42/12.92 ~ bnd_c5_2 bnd_a849 bnd_a851 |
% 13.42/12.92 (bnd_ndr1_0 &
% 13.42/12.92 (ALL X75.
% 13.42/12.92 bnd_ndr1_1 bnd_a852 -->
% 13.42/12.92 (bnd_c1_2 bnd_a852 X75 | ~ bnd_c4_2 bnd_a852 X75) |
% 13.42/12.92 ~ bnd_c5_2 bnd_a852 X75)) &
% 13.42/12.92 bnd_c1_1 bnd_a852) |
% 13.42/12.92 ~ bnd_c5_0)) &
% 13.42/12.92 (((((bnd_ndr1_0 &
% 13.42/12.92 (ALL X76.
% 13.42/12.92 bnd_ndr1_1 bnd_a853 -->
% 13.42/12.92 ~ bnd_c1_2 bnd_a853 X76 | bnd_c2_2 bnd_a853 X76)) &
% 13.42/12.92 bnd_ndr1_1 bnd_a853) &
% 13.42/12.92 bnd_c3_2 bnd_a853 bnd_a854) &
% 13.42/12.92 bnd_c2_2 bnd_a853 bnd_a854) &
% 13.42/12.92 (ALL X77.
% 13.42/12.92 bnd_ndr1_1 bnd_a853 -->
% 13.42/12.92 (~ bnd_c1_2 bnd_a853 X77 |
% 13.42/12.92 bnd_c3_2 bnd_a853 X77) |
% 13.42/12.92 bnd_c5_2 bnd_a853 X77) |
% 13.42/12.92 ~ bnd_c5_0)) &
% 13.42/12.92 (((ALL X78.
% 13.42/12.92 bnd_ndr1_0 -->
% 13.42/12.92 (~ bnd_c2_1 X78 | bnd_c5_1 X78) |
% 13.42/12.92 ~ bnd_c3_1 X78) |
% 13.42/12.92 bnd_c3_0) |
% 13.42/12.92 (((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a855) &
% 13.42/12.92 bnd_c1_2 bnd_a855 bnd_a856) &
% 13.42/12.92 bnd_c5_2 bnd_a855 bnd_a856) &
% 13.42/12.92 bnd_c2_2 bnd_a855 bnd_a856) &
% 13.42/12.92 ~ bnd_c1_1 bnd_a855) &
% 13.42/12.92 (ALL X79.
% 13.42/12.92 bnd_ndr1_1 bnd_a855 -->
% 13.42/12.92 (bnd_c2_2 bnd_a855 X79 |
% 13.42/12.92 ~ bnd_c5_2 bnd_a855 X79) |
% 13.42/12.92 ~ bnd_c1_2 bnd_a855 X79))) &
% 13.42/12.92 ((bnd_c1_0 | ~ bnd_c4_0) |
% 13.42/12.92 (ALL X80.
% 13.42/12.92 bnd_ndr1_0 -->
% 13.42/12.92 (~ bnd_c5_1 X80 |
% 13.42/12.92 ((bnd_ndr1_1 X80 &
% 13.42/12.92 ~ bnd_c4_2 X80 bnd_a857) &
% 13.42/12.92 bnd_c2_2 X80 bnd_a857) &
% 13.42/12.92 ~ bnd_c5_2 X80 bnd_a857) |
% 13.42/12.92 bnd_c2_1 X80))) &
% 13.42/12.92 (((((bnd_ndr1_0 & bnd_c5_1 bnd_a858) &
% 13.42/12.92 bnd_ndr1_1 bnd_a858) &
% 13.42/12.92 ~ bnd_c1_2 bnd_a858 bnd_a859) &
% 13.42/12.92 bnd_c3_2 bnd_a858 bnd_a859) &
% 13.42/12.92 bnd_c2_2 bnd_a858 bnd_a859 |
% 13.42/12.92 bnd_c1_0)) &
% 13.42/12.92 (((bnd_ndr1_0 & bnd_c2_1 bnd_a860) &
% 13.42/12.92 (ALL X81.
% 13.42/12.92 bnd_ndr1_1 bnd_a860 -->
% 13.42/12.92 (~ bnd_c4_2 bnd_a860 X81 |
% 13.42/12.92 ~ bnd_c2_2 bnd_a860 X81) |
% 13.42/12.92 ~ bnd_c1_2 bnd_a860 X81) |
% 13.42/12.92 ((((bnd_ndr1_0 & ~ bnd_c2_1 bnd_a861) &
% 13.42/12.92 ~ bnd_c1_1 bnd_a861) &
% 13.42/12.92 bnd_ndr1_1 bnd_a861) &
% 13.42/12.92 bnd_c3_2 bnd_a861 bnd_a862) &
% 13.42/12.92 bnd_c1_2 bnd_a861 bnd_a862) |
% 13.42/12.92 ~ bnd_c4_0)) &
% 13.42/12.92 (((ALL X82.
% 13.42/12.92 bnd_ndr1_0 -->
% 13.42/12.92 ~ bnd_c5_1 X82 | bnd_c3_1 X82) |
% 13.42/12.92 ((bnd_ndr1_0 &
% 13.42/12.92 (ALL X83.
% 13.42/12.92 bnd_ndr1_1 bnd_a863 -->
% 13.42/12.92 bnd_c3_2 bnd_a863 X83 |
% 13.42/12.92 bnd_c4_2 bnd_a863 X83)) &
% 13.42/12.92 bnd_c5_1 bnd_a863) &
% 13.42/12.92 ~ bnd_c1_1 bnd_a863) |
% 13.42/12.92 (ALL X84.
% 13.42/12.92 bnd_ndr1_0 -->
% 13.42/12.92 (bnd_c3_1 X84 | ~ bnd_c4_1 X84) |
% 13.42/12.92 bnd_c2_1 X84))) &
% 13.42/12.92 (~ bnd_c1_0 |
% 13.42/12.92 ((((bnd_ndr1_0 & ~ bnd_c4_1 bnd_a864) &
% 13.42/12.92 bnd_ndr1_1 bnd_a864) &
% 13.42/12.92 bnd_c1_2 bnd_a864 bnd_a865) &
% 13.42/12.92 bnd_c2_2 bnd_a864 bnd_a865) &
% 13.42/12.92 bnd_c4_2 bnd_a864 bnd_a865)) &
% 13.42/12.92 (~ bnd_c5_0 |
% 13.42/12.92 (ALL X85.
% 13.42/12.92 bnd_ndr1_0 -->
% 13.42/12.92 (~ bnd_c5_1 X85 |
% 13.42/12.92 (bnd_ndr1_1 X85 & bnd_c3_2 X85 bnd_a866) &
% 13.42/12.92 ~ bnd_c2_2 X85 bnd_a866) |
% 13.42/12.92 (ALL X86.
% 13.42/12.92 bnd_ndr1_1 X85 -->
% 13.42/12.92 (~ bnd_c3_2 X85 X86 | bnd_c2_2 X85 X86) |
% 13.42/12.92 bnd_c1_2 X85 X86)))) &
% 13.42/12.92 (bnd_c4_0 | bnd_c5_0)) &
% 13.42/12.92 ((~ bnd_c5_0 | ~ bnd_c3_0) |
% 13.42/12.92 (((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a867) &
% 13.42/12.92 ~ bnd_c3_2 bnd_a867 bnd_a868) &
% 13.42/12.92 bnd_c5_2 bnd_a867 bnd_a868) &
% 13.42/12.92 (ALL X87.
% 13.42/12.92 bnd_ndr1_1 bnd_a867 -->
% 13.42/12.92 (bnd_c5_2 bnd_a867 X87 |
% 13.42/12.92 bnd_c3_2 bnd_a867 X87) |
% 13.42/12.92 ~ bnd_c4_2 bnd_a867 X87)) &
% 13.42/12.92 bnd_ndr1_1 bnd_a867) &
% 13.42/12.92 bnd_c2_2 bnd_a867 bnd_a869) &
% 13.42/12.92 ~ bnd_c4_2 bnd_a867 bnd_a869) &
% 13.42/12.92 bnd_c3_2 bnd_a867 bnd_a869)) &
% 13.42/12.92 ((ALL X88.
% 13.42/12.92 bnd_ndr1_0 -->
% 13.42/12.92 (~ bnd_c1_1 X88 |
% 13.42/12.92 ((bnd_ndr1_1 X88 & bnd_c1_2 X88 bnd_a870) &
% 13.42/12.92 ~ bnd_c4_2 X88 bnd_a870) &
% 13.42/12.92 ~ bnd_c3_2 X88 bnd_a870) |
% 13.42/12.92 ~ bnd_c2_1 X88) |
% 13.42/12.92 ~ bnd_c1_0)) &
% 13.42/12.92 (((ALL X89.
% 13.42/12.92 bnd_ndr1_0 -->
% 13.42/12.92 (bnd_ndr1_1 X89 & bnd_c3_2 X89 bnd_a871) &
% 13.42/12.92 bnd_c5_2 X89 bnd_a871 |
% 13.42/12.92 ((bnd_ndr1_1 X89 & ~ bnd_c5_2 X89 bnd_a872) &
% 13.42/12.92 ~ bnd_c4_2 X89 bnd_a872) &
% 13.42/12.92 bnd_c3_2 X89 bnd_a872) |
% 13.42/12.92 bnd_c4_0) |
% 13.42/12.92 ~ bnd_c5_0)) &
% 13.42/12.92 (~ bnd_c1_0 |
% 13.42/12.92 ((((bnd_ndr1_0 & bnd_c3_1 bnd_a873) &
% 13.42/12.92 bnd_ndr1_1 bnd_a873) &
% 13.42/12.92 ~ bnd_c3_2 bnd_a873 bnd_a874) &
% 13.42/12.92 bnd_c5_2 bnd_a873 bnd_a874) &
% 13.42/12.92 ~ bnd_c1_2 bnd_a873 bnd_a874)) &
% 13.42/12.92 (bnd_c3_0 |
% 13.42/12.92 ((bnd_ndr1_0 & ~ bnd_c4_1 bnd_a875) &
% 13.42/12.92 bnd_c2_1 bnd_a875) &
% 13.42/12.92 (ALL X90.
% 13.42/12.92 bnd_ndr1_1 bnd_a875 -->
% 13.42/12.92 ~ bnd_c1_2 bnd_a875 X90 |
% 13.42/12.92 ~ bnd_c4_2 bnd_a875 X90))) &
% 13.42/12.92 (bnd_c2_0 | ~ bnd_c4_0)) &
% 13.42/12.92 ((~ bnd_c2_0 |
% 13.42/12.92 (ALL X91.
% 13.42/12.92 bnd_ndr1_0 -->
% 13.42/12.92 (((bnd_ndr1_1 X91 & ~ bnd_c2_2 X91 bnd_a876) &
% 13.42/12.92 bnd_c5_2 X91 bnd_a876) &
% 13.42/12.92 bnd_c3_2 X91 bnd_a876 |
% 13.42/12.92 ((bnd_ndr1_1 X91 & bnd_c2_2 X91 bnd_a877) &
% 13.42/12.92 bnd_c4_2 X91 bnd_a877) &
% 13.42/12.92 bnd_c1_2 X91 bnd_a877) |
% 13.42/12.92 bnd_c3_1 X91)) |
% 13.42/12.92 (ALL X92.
% 13.42/12.92 bnd_ndr1_0 -->
% 13.42/12.92 (~ bnd_c5_1 X92 | ~ bnd_c4_1 X92) |
% 13.42/12.92 ((bnd_ndr1_1 X92 & ~ bnd_c3_2 X92 bnd_a878) &
% 13.42/12.92 bnd_c5_2 X92 bnd_a878) &
% 13.42/12.92 bnd_c2_2 X92 bnd_a878))) &
% 13.42/12.92 ((bnd_c3_0 | ~ bnd_c5_0) | ~ bnd_c1_0)) &
% 13.42/12.92 (~ bnd_c2_0 | ~ bnd_c1_0)) &
% 13.42/12.92 ((bnd_c3_0 |
% 13.42/12.92 ((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a879) &
% 13.42/12.92 ~ bnd_c3_2 bnd_a879 bnd_a880) &
% 13.42/12.92 ~ bnd_c4_2 bnd_a879 bnd_a880) &
% 13.42/12.92 bnd_c2_1 bnd_a879) &
% 13.42/12.92 (ALL X93.
% 13.42/12.92 bnd_ndr1_1 bnd_a879 -->
% 13.42/12.92 (bnd_c2_2 bnd_a879 X93 | ~ bnd_c1_2 bnd_a879 X93) |
% 13.42/12.92 ~ bnd_c4_2 bnd_a879 X93)) |
% 13.42/12.92 ~ bnd_c4_0)) &
% 13.42/12.92 (bnd_c1_0 |
% 13.42/12.92 (ALL X94.
% 13.42/12.92 bnd_ndr1_0 -->
% 13.42/12.92 (~ bnd_c4_1 X94 | bnd_c2_1 X94) | ~ bnd_c3_1 X94))) &
% 13.42/12.92 ((bnd_c1_0 | bnd_c5_0) |
% 13.42/12.92 (ALL X95.
% 13.42/12.92 bnd_ndr1_0 -->
% 13.42/12.92 ((bnd_ndr1_1 X95 & bnd_c2_2 X95 bnd_a881) &
% 13.42/12.92 ~ bnd_c5_2 X95 bnd_a881 |
% 13.42/12.92 ((bnd_ndr1_1 X95 & ~ bnd_c3_2 X95 bnd_a882) &
% 13.42/12.92 ~ bnd_c2_2 X95 bnd_a882) &
% 13.42/12.92 bnd_c5_2 X95 bnd_a882) |
% 13.42/12.92 bnd_c1_1 X95))) &
% 13.42/12.92 (((ALL X96.
% 13.42/12.92 bnd_ndr1_0 -->
% 13.42/12.92 ((ALL X97.
% 13.42/12.92 bnd_ndr1_1 X96 -->
% 13.42/12.92 (~ bnd_c3_2 X96 X97 | bnd_c5_2 X96 X97) |
% 13.42/12.92 bnd_c2_2 X96 X97) |
% 13.42/12.92 bnd_c5_1 X96) |
% 13.42/12.92 (ALL X98.
% 13.42/12.92 bnd_ndr1_1 X96 -->
% 13.42/12.92 (bnd_c5_2 X96 X98 | bnd_c3_2 X96 X98) |
% 13.42/12.92 bnd_c1_2 X96 X98)) |
% 13.42/12.92 bnd_c4_0) |
% 13.42/12.92 bnd_c3_0)) &
% 13.42/12.92 (((ALL X99.
% 13.42/12.92 bnd_ndr1_0 -->
% 13.42/12.92 (bnd_c5_1 X99 |
% 13.42/12.92 ((bnd_ndr1_1 X99 & ~ bnd_c2_2 X99 bnd_a883) &
% 13.42/12.92 bnd_c1_2 X99 bnd_a883) &
% 13.42/12.92 bnd_c3_2 X99 bnd_a883) |
% 13.42/12.92 ((bnd_ndr1_1 X99 & bnd_c4_2 X99 bnd_a884) &
% 13.42/12.92 ~ bnd_c2_2 X99 bnd_a884) &
% 13.42/12.92 ~ bnd_c3_2 X99 bnd_a884) |
% 13.42/12.92 (ALL X100.
% 13.42/12.92 bnd_ndr1_0 -->
% 13.42/12.92 (~ bnd_c4_1 X100 |
% 13.42/12.92 (ALL X101.
% 13.42/12.92 bnd_ndr1_1 X100 -->
% 13.42/12.92 (~ bnd_c5_2 X100 X101 | bnd_c1_2 X100 X101) |
% 13.42/12.92 bnd_c4_2 X100 X101)) |
% 13.42/12.92 bnd_c3_1 X100)) |
% 13.42/12.92 bnd_c1_0)) &
% 13.42/12.92 ((~ bnd_c1_0 | bnd_c3_0) |
% 13.42/12.92 (bnd_ndr1_0 &
% 13.42/12.92 (ALL X102.
% 13.42/12.92 bnd_ndr1_1 bnd_a885 -->
% 13.42/12.92 ~ bnd_c1_2 bnd_a885 X102 | ~ bnd_c3_2 bnd_a885 X102)) &
% 13.42/12.92 ~ bnd_c5_1 bnd_a885)) &
% 13.42/12.92 ((ALL X103.
% 13.42/12.92 bnd_ndr1_0 -->
% 13.42/12.92 (ALL X104.
% 13.42/12.92 bnd_ndr1_1 X103 -->
% 13.42/12.92 ~ bnd_c2_2 X103 X104 | bnd_c5_2 X103 X104) |
% 13.42/12.92 (bnd_ndr1_1 X103 & bnd_c4_2 X103 bnd_a886) &
% 13.42/12.92 bnd_c5_2 X103 bnd_a886) |
% 13.42/12.92 ~ bnd_c5_0)) &
% 13.42/12.92 ((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a887) &
% 13.42/12.92 ~ bnd_c4_2 bnd_a887 bnd_a888) &
% 13.42/12.92 bnd_c1_2 bnd_a887 bnd_a888) &
% 13.42/12.92 bnd_c3_2 bnd_a887 bnd_a888) &
% 13.42/12.92 bnd_c5_1 bnd_a887 |
% 13.42/12.92 (ALL X105.
% 13.42/12.92 bnd_ndr1_0 -->
% 13.42/12.92 (~ bnd_c1_1 X105 |
% 13.42/12.92 ((bnd_ndr1_1 X105 & bnd_c2_2 X105 bnd_a889) &
% 13.42/12.92 ~ bnd_c4_2 X105 bnd_a889) &
% 13.42/12.92 bnd_c3_2 X105 bnd_a889) |
% 13.42/12.92 ((bnd_ndr1_1 X105 & bnd_c4_2 X105 bnd_a890) &
% 13.42/12.92 bnd_c2_2 X105 bnd_a890) &
% 13.42/12.92 bnd_c3_2 X105 bnd_a890)) |
% 13.42/12.92 ((bnd_ndr1_0 &
% 13.42/12.92 (ALL X106.
% 13.42/12.92 bnd_ndr1_1 bnd_a891 -->
% 13.42/12.92 (~ bnd_c1_2 bnd_a891 X106 | ~ bnd_c5_2 bnd_a891 X106) |
% 13.42/12.92 ~ bnd_c4_2 bnd_a891 X106)) &
% 13.42/12.92 ~ bnd_c3_1 bnd_a891) &
% 13.42/12.92 (ALL X107.
% 13.42/12.92 bnd_ndr1_1 bnd_a891 -->
% 13.42/12.92 ~ bnd_c5_2 bnd_a891 X107 | bnd_c3_2 bnd_a891 X107))) &
% 13.42/12.92 (bnd_c5_0 |
% 13.42/12.92 (ALL X108. bnd_ndr1_0 --> ~ bnd_c3_1 X108 | bnd_c1_1 X108))) &
% 13.42/12.92 ((((bnd_ndr1_0 &
% 13.42/12.92 (ALL X109.
% 13.42/12.92 bnd_ndr1_1 bnd_a892 -->
% 13.42/12.92 (bnd_c1_2 bnd_a892 X109 | bnd_c3_2 bnd_a892 X109) |
% 13.42/12.92 ~ bnd_c2_2 bnd_a892 X109)) &
% 13.42/12.92 bnd_c5_1 bnd_a892) &
% 13.42/12.92 ~ bnd_c4_1 bnd_a892 |
% 13.42/12.92 ((bnd_ndr1_0 &
% 13.42/12.92 (ALL X110.
% 13.42/12.92 bnd_ndr1_1 bnd_a893 -->
% 13.42/12.92 bnd_c1_2 bnd_a893 X110 | bnd_c4_2 bnd_a893 X110)) &
% 13.42/12.92 ~ bnd_c5_1 bnd_a893) &
% 13.42/12.92 (ALL X111.
% 13.42/12.92 bnd_ndr1_1 bnd_a893 -->
% 13.42/12.92 bnd_c4_2 bnd_a893 X111 | ~ bnd_c5_2 bnd_a893 X111)) |
% 13.42/12.92 (((((bnd_ndr1_0 & ~ bnd_c2_1 bnd_a894) & bnd_c4_1 bnd_a894) &
% 13.42/12.92 bnd_ndr1_1 bnd_a894) &
% 13.42/12.92 ~ bnd_c5_2 bnd_a894 bnd_a895) &
% 13.42/12.92 bnd_c3_2 bnd_a894 bnd_a895) &
% 13.42/12.92 ~ bnd_c1_2 bnd_a894 bnd_a895)) &
% 13.42/12.92 (bnd_c5_0 |
% 13.42/12.92 (ALL X112.
% 13.42/12.92 bnd_ndr1_0 -->
% 13.42/12.92 (((bnd_ndr1_1 X112 & ~ bnd_c5_2 X112 bnd_a896) &
% 13.42/12.92 bnd_c3_2 X112 bnd_a896) &
% 13.42/12.92 ~ bnd_c2_2 X112 bnd_a896 |
% 13.42/12.92 (ALL X113.
% 13.42/12.92 bnd_ndr1_1 X112 -->
% 13.42/12.92 (bnd_c3_2 X112 X113 | ~ bnd_c4_2 X112 X113) |
% 13.42/12.92 bnd_c1_2 X112 X113)) |
% 13.42/12.92 bnd_c5_1 X112)))
% 13.42/12.92 Adding axioms...
% 13.42/12.93 Typedef.type_definition_def
% 33.75/33.27 ...done.
% 33.75/33.29 Ground types: ?'b, TPTP_Interpret.ind
% 33.75/33.29 Translating term (sizes: 1, 1) ...
% 50.39/49.80 Invoking SAT solver...
% 50.39/49.80 No model exists.
% 50.39/49.80 Translating term (sizes: 2, 1) ...
% 67.64/67.05 Invoking SAT solver...
% 67.64/67.06 No model exists.
% 67.64/67.06 Translating term (sizes: 1, 2) ...
% 97.53/96.86 Invoking SAT solver...
% 97.71/97.02 No model exists.
% 97.71/97.02 Translating term (sizes: 3, 1) ...
% 117.39/116.61 Invoking SAT solver...
% 117.39/116.61 No model exists.
% 117.39/116.61 Translating term (sizes: 2, 2) ...
% 155.25/154.31 Invoking SAT solver...
% 155.35/154.47 No model exists.
% 155.35/154.47 Translating term (sizes: 1, 3) ...
% 202.54/201.32 Invoking SAT solver...
% 203.15/201.96 Model found:
% 203.15/201.96 Size of types: ?'b: 1, TPTP_Interpret.ind: 3
% 203.15/201.96 bnd_a896: ??.TPTP_Interpret.ind0
% 203.15/201.96 bnd_a895: ??.TPTP_Interpret.ind0
% 203.15/201.96 bnd_a894: ??.TPTP_Interpret.ind0
% 203.15/201.96 bnd_a893: ??.TPTP_Interpret.ind0
% 203.15/201.96 bnd_a892: ??.TPTP_Interpret.ind2
% 203.15/201.96 bnd_a891: ??.TPTP_Interpret.ind0
% 203.15/201.96 bnd_a890: ??.TPTP_Interpret.ind0
% 203.15/201.96 bnd_a889: ??.TPTP_Interpret.ind0
% 203.15/201.96 bnd_a888: ??.TPTP_Interpret.ind0
% 203.15/201.96 bnd_a887: ??.TPTP_Interpret.ind0
% 203.15/201.96 bnd_a886: ??.TPTP_Interpret.ind0
% 203.15/201.96 bnd_a885: ??.TPTP_Interpret.ind0
% 203.15/201.96 bnd_a884: ??.TPTP_Interpret.ind0
% 203.15/201.96 bnd_a883: ??.TPTP_Interpret.ind0
% 203.15/201.96 bnd_a882: ??.TPTP_Interpret.ind0
% 203.15/201.96 bnd_a881: ??.TPTP_Interpret.ind0
% 203.15/201.96 bnd_a880: ??.TPTP_Interpret.ind0
% 203.15/201.96 bnd_a879: ??.TPTP_Interpret.ind0
% 203.15/201.96 bnd_a878: ??.TPTP_Interpret.ind0
% 203.15/201.96 bnd_a877: ??.TPTP_Interpret.ind0
% 203.15/201.96 bnd_a876: ??.TPTP_Interpret.ind0
% 203.15/201.96 bnd_a875: ??.TPTP_Interpret.ind0
% 203.15/201.96 bnd_a874: ??.TPTP_Interpret.ind0
% 203.15/201.96 bnd_a873: ??.TPTP_Interpret.ind0
% 203.15/201.96 bnd_a872: ??.TPTP_Interpret.ind0
% 203.15/201.96 bnd_a871: ??.TPTP_Interpret.ind0
% 203.15/201.96 bnd_a870: ??.TPTP_Interpret.ind0
% 203.15/201.96 bnd_a869: ??.TPTP_Interpret.ind0
% 203.15/201.96 bnd_a868: ??.TPTP_Interpret.ind0
% 203.15/201.96 bnd_a867: ??.TPTP_Interpret.ind0
% 203.15/201.96 bnd_a866: ??.TPTP_Interpret.ind0
% 203.15/201.96 bnd_a865: ??.TPTP_Interpret.ind0
% 203.15/201.96 bnd_a864: ??.TPTP_Interpret.ind0
% 203.15/201.96 bnd_a863: ??.TPTP_Interpret.ind0
% 203.15/201.96 bnd_a862: ??.TPTP_Interpret.ind0
% 203.15/201.96 bnd_a861: ??.TPTP_Interpret.ind0
% 203.15/201.96 bnd_a860: ??.TPTP_Interpret.ind0
% 203.15/201.96 bnd_a859: ??.TPTP_Interpret.ind2
% 203.15/201.96 bnd_a858: ??.TPTP_Interpret.ind2
% 203.15/201.96 bnd_a857: ??.TPTP_Interpret.ind0
% 203.15/201.96 bnd_a856: ??.TPTP_Interpret.ind0
% 203.15/201.96 bnd_a855: ??.TPTP_Interpret.ind0
% 203.15/201.96 bnd_a854: ??.TPTP_Interpret.ind0
% 203.15/201.96 bnd_a853: ??.TPTP_Interpret.ind0
% 203.15/201.96 bnd_a852: ??.TPTP_Interpret.ind0
% 203.15/201.96 bnd_a851: ??.TPTP_Interpret.ind0
% 203.15/201.96 bnd_a850: ??.TPTP_Interpret.ind0
% 203.15/201.96 bnd_a849: ??.TPTP_Interpret.ind0
% 203.15/201.96 bnd_a848: ??.TPTP_Interpret.ind0
% 203.15/201.96 bnd_a847: ??.TPTP_Interpret.ind0
% 203.15/201.96 bnd_a846: ??.TPTP_Interpret.ind0
% 203.15/201.96 bnd_a845: ??.TPTP_Interpret.ind0
% 203.15/201.96 bnd_a844: ??.TPTP_Interpret.ind0
% 203.15/201.96 bnd_a843: ??.TPTP_Interpret.ind0
% 203.15/201.96 bnd_a842: ??.TPTP_Interpret.ind0
% 203.15/201.96 bnd_a841: ??.TPTP_Interpret.ind1
% 203.15/201.96 bnd_a840: ??.TPTP_Interpret.ind2
% 203.15/201.96 bnd_a839: ??.TPTP_Interpret.ind1
% 203.15/201.96 bnd_a838: ??.TPTP_Interpret.ind0
% 203.15/201.96 bnd_a837: ??.TPTP_Interpret.ind0
% 203.15/201.96 bnd_a836: ??.TPTP_Interpret.ind0
% 203.15/201.96 bnd_a835: ??.TPTP_Interpret.ind0
% 203.15/201.96 bnd_a834: ??.TPTP_Interpret.ind1
% 203.15/201.96 bnd_a833: ??.TPTP_Interpret.ind0
% 203.15/201.96 bnd_a832: ??.TPTP_Interpret.ind0
% 203.15/201.96 bnd_a831: ??.TPTP_Interpret.ind0
% 203.15/201.96 bnd_a830: ??.TPTP_Interpret.ind0
% 203.15/201.96 bnd_a829: ??.TPTP_Interpret.ind0
% 203.15/201.96 bnd_a828: ??.TPTP_Interpret.ind0
% 203.15/201.96 bnd_a827: ??.TPTP_Interpret.ind0
% 203.15/201.96 bnd_a826: ??.TPTP_Interpret.ind0
% 203.15/201.96 bnd_a825: ??.TPTP_Interpret.ind0
% 203.15/201.96 bnd_a824: ??.TPTP_Interpret.ind2
% 203.15/201.96 bnd_a823: ??.TPTP_Interpret.ind0
% 203.15/201.96 bnd_a822: ??.TPTP_Interpret.ind0
% 203.15/201.96 bnd_a821: ??.TPTP_Interpret.ind0
% 203.15/201.96 bnd_a820: ??.TPTP_Interpret.ind0
% 203.15/201.96 bnd_a819: ??.TPTP_Interpret.ind0
% 203.15/201.96 bnd_a818: ??.TPTP_Interpret.ind0
% 203.15/201.96 bnd_a817: ??.TPTP_Interpret.ind1
% 203.15/201.96 bnd_a816: ??.TPTP_Interpret.ind0
% 203.15/201.96 bnd_a815: ??.TPTP_Interpret.ind0
% 203.15/201.96 bnd_a814: ??.TPTP_Interpret.ind0
% 203.15/201.96 bnd_a813: ??.TPTP_Interpret.ind0
% 203.15/201.96 bnd_a812: ??.TPTP_Interpret.ind0
% 203.15/201.96 bnd_a811: ??.TPTP_Interpret.ind0
% 203.15/201.96 bnd_a810: ??.TPTP_Interpret.ind0
% 203.15/201.96 bnd_a809: ??.TPTP_Interpret.ind0
% 203.15/201.96 bnd_a808: ??.TPTP_Interpret.ind0
% 203.15/201.96 bnd_a807: ??.TPTP_Interpret.ind0
% 203.15/201.96 bnd_a806: ??.TPTP_Interpret.ind0
% 203.15/201.96 bnd_a805: ??.TPTP_Interpret.ind0
% 203.15/201.96 bnd_a804: ??.TPTP_Interpret.ind0
% 203.15/201.96 bnd_a803: ??.TPTP_Interpret.ind0
% 203.15/201.96 bnd_a802: ??.TPTP_Interpret.ind0
% 203.15/201.96 bnd_a801: ??.TPTP_Interpret.ind0
% 203.15/201.96 bnd_a800: ??.TPTP_Interpret.ind0
% 203.15/201.96 bnd_a799: ??.TPTP_Interpret.ind0
% 203.15/201.96 bnd_a798: ??.TPTP_Interpret.ind0
% 203.15/201.96 bnd_a797: ??.TPTP_Interpret.ind0
% 203.15/201.96 bnd_a796: ??.TPTP_Interpret.ind0
% 203.15/201.96 bnd_a795: ??.TPTP_Interpret.ind0
% 203.15/201.96 bnd_a794: ??.TPTP_Interpret.ind0
% 203.15/201.96 bnd_a793: ??.TPTP_Interpret.ind0
% 203.15/201.96 bnd_a792: ??.TPTP_Interpret.ind0
% 203.15/201.96 bnd_a791: ??.TPTP_Interpret.ind0
% 203.15/201.96 bnd_a790: ??.TPTP_Interpret.ind0
% 203.15/201.96 bnd_a789: ??.TPTP_Interpret.ind0
% 203.15/201.96 bnd_a788: ??.TPTP_Interpret.ind0
% 203.15/201.96 bnd_a787: ??.TPTP_Interpret.ind0
% 203.15/201.96 bnd_a786: ??.TPTP_Interpret.ind0
% 203.15/201.96 bnd_a785: ??.TPTP_Interpret.ind0
% 203.15/201.96 bnd_a784: ??.TPTP_Interpret.ind0
% 203.15/201.96 bnd_a783: ??.TPTP_Interpret.ind0
% 203.15/201.96 bnd_a782: ??.TPTP_Interpret.ind0
% 203.15/201.96 bnd_c1_0: False
% 203.15/201.96 bnd_a781: ??.TPTP_Interpret.ind0
% 203.15/201.96 bnd_c4_1: {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, True),
% 203.15/201.96 (??.TPTP_Interpret.ind2, False)}
% 203.15/201.96 bnd_c2_0: False
% 203.15/201.96 bnd_a780: ??.TPTP_Interpret.ind0
% 203.15/201.96 bnd_c3_0: False
% 203.15/201.96 bnd_a779: ??.TPTP_Interpret.ind0
% 203.15/201.96 bnd_c4_2: {(??.TPTP_Interpret.ind0,
% 203.15/201.96 {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, False),
% 203.15/201.96 (??.TPTP_Interpret.ind2, False)}),
% 203.15/201.96 (??.TPTP_Interpret.ind1,
% 203.15/201.96 {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, False),
% 203.15/201.96 (??.TPTP_Interpret.ind2, True)}),
% 203.15/201.96 (??.TPTP_Interpret.ind2,
% 203.15/201.96 {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, False),
% 203.15/201.96 (??.TPTP_Interpret.ind2, True)})}
% 203.15/201.96 bnd_a778: ??.TPTP_Interpret.ind0
% 203.15/201.96 bnd_c5_2: {(??.TPTP_Interpret.ind0,
% 203.15/201.96 {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, True),
% 203.15/201.96 (??.TPTP_Interpret.ind2, True)}),
% 203.15/201.96 (??.TPTP_Interpret.ind1,
% 203.15/201.96 {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, False),
% 203.15/201.96 (??.TPTP_Interpret.ind2, False)}),
% 203.15/201.96 (??.TPTP_Interpret.ind2,
% 203.15/201.96 {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, False),
% 203.15/201.96 (??.TPTP_Interpret.ind2, True)})}
% 203.15/201.96 bnd_c2_1: {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, True),
% 203.15/201.96 (??.TPTP_Interpret.ind2, False)}
% 203.15/201.96 bnd_c1_2: {(??.TPTP_Interpret.ind0,
% 203.15/201.96 {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, True),
% 203.15/201.96 (??.TPTP_Interpret.ind2, True)}),
% 203.15/201.96 (??.TPTP_Interpret.ind1,
% 203.15/201.96 {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, True),
% 203.15/201.96 (??.TPTP_Interpret.ind2, True)}),
% 203.15/201.96 (??.TPTP_Interpret.ind2,
% 203.15/201.96 {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, True),
% 203.15/201.96 (??.TPTP_Interpret.ind2, False)})}
% 203.15/201.96 bnd_c2_2: {(??.TPTP_Interpret.ind0,
% 203.15/201.96 {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, True),
% 203.15/201.96 (??.TPTP_Interpret.ind2, True)}),
% 203.15/201.96 (??.TPTP_Interpret.ind1,
% 203.15/201.96 {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, False),
% 203.15/201.96 (??.TPTP_Interpret.ind2, True)}),
% 203.15/201.96 (??.TPTP_Interpret.ind2,
% 203.15/201.96 {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, False),
% 203.15/201.96 (??.TPTP_Interpret.ind2, True)})}
% 203.15/201.96 bnd_a777: ??.TPTP_Interpret.ind0
% 203.15/201.96 bnd_c3_2: {(??.TPTP_Interpret.ind0,
% 203.15/201.96 {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, True),
% 203.15/201.96 (??.TPTP_Interpret.ind2, True)}),
% 203.15/201.96 (??.TPTP_Interpret.ind1,
% 203.15/201.96 {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, True),
% 203.15/201.96 (??.TPTP_Interpret.ind2, True)}),
% 203.15/201.96 (??.TPTP_Interpret.ind2,
% 203.15/201.96 {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, True),
% 203.15/201.96 (??.TPTP_Interpret.ind2, True)})}
% 203.15/201.96 bnd_a776: ??.TPTP_Interpret.ind0
% 203.15/201.96 bnd_ndr1_1: {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, True),
% 203.15/201.96 (??.TPTP_Interpret.ind2, True)}
% 203.15/201.96 bnd_c5_0: True
% 203.15/201.96 bnd_c4_0: False
% 203.15/201.96 bnd_c1_1: {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, True),
% 203.15/201.96 (??.TPTP_Interpret.ind2, False)}
% 203.15/201.96 bnd_c3_1: {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, False),
% 203.15/201.96 (??.TPTP_Interpret.ind2, True)}
% 203.15/201.96 bnd_a775: ??.TPTP_Interpret.ind0
% 203.15/201.96 bnd_c5_1: {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, False),
% 203.15/201.96 (??.TPTP_Interpret.ind2, True)}
% 203.15/201.96 bnd_ndr1_0: True
% 203.15/201.96
% 203.15/201.96 % SZS status CounterSatisfiable
%------------------------------------------------------------------------------