TSTP Solution File: SYN426+1 by Refute---2015
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%------------------------------------------------------------------------------
% File : Refute---2015
% Problem : SYN426+1 : TPTP v6.4.0. Released v2.1.0.
% Transfm : none
% Format : tptp:raw
% Command : isabelle tptp_refute %d %s
% Computer : n124.star.cs.uiowa.edu
% Model : x86_64 x86_64
% CPU : Intel(R) Xeon(R) CPU E5-2609 0 2.40GHz
% Memory : 32218.75MB
% OS : Linux 3.10.0-327.10.1.el7.x86_64
% CPULimit : 300s
% DateTime : Thu Apr 14 06:41:44 EDT 2016
% Result : CounterSatisfiable 176.08s
% Output : Assurance 0s
% Verified :
% SZS Type : None (Parsing solution fails)
% Syntax : Number of formulae : 0
% Comments :
%------------------------------------------------------------------------------
%----No solution output by system
%------------------------------------------------------------------------------
%----ORIGINAL SYSTEM OUTPUT
% 0.00/0.03 % Problem : SYN426+1 : TPTP v6.4.0. Released v2.1.0.
% 0.00/0.04 % Command : isabelle tptp_refute %d %s
% 0.03/0.23 % Computer : n124.star.cs.uiowa.edu
% 0.03/0.23 % Model : x86_64 x86_64
% 0.03/0.23 % CPU : Intel(R) Xeon(R) CPU E5-2609 0 @ 2.40GHz
% 0.03/0.23 % Memory : 32218.75MB
% 0.03/0.23 % OS : Linux 3.10.0-327.10.1.el7.x86_64
% 0.03/0.23 % CPULimit : 300
% 0.03/0.23 % DateTime : Fri Apr 8 23:50:09 CDT 2016
% 0.03/0.23 % CPUTime:
% 6.31/5.86 > val it = (): unit
% 7.31/6.87 Trying to find a model that refutes: ~ ((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((~ bnd_c5_0 &
% 7.31/6.87 ((bnd_c1_0 | bnd_c3_0) |
% 7.31/6.87 (bnd_ndr1_0 & bnd_c3_1 bnd_a218) & ~ bnd_c7_1 bnd_a218)) &
% 7.31/6.87 ((bnd_c1_0 | bnd_c4_0) | bnd_c8_0)) &
% 7.31/6.87 ((bnd_c1_0 | bnd_c8_0) | ~ bnd_c4_0)) &
% 7.31/6.87 ((bnd_c1_0 | ~ bnd_c10_0) |
% 7.31/6.87 (((((((bnd_ndr1_0 &
% 7.31/6.87 (ALL U.
% 7.31/6.87 bnd_ndr1_1 bnd_a219 -->
% 7.31/6.87 (bnd_c3_2 bnd_a219 U | ~ bnd_c10_2 bnd_a219 U) |
% 7.31/6.87 ~ bnd_c5_2 bnd_a219 U)) &
% 7.31/6.87 bnd_ndr1_1 bnd_a219) &
% 7.31/6.87 bnd_c2_2 bnd_a219 bnd_a220) &
% 7.31/6.87 ~ bnd_c1_2 bnd_a219 bnd_a220) &
% 7.31/6.87 ~ bnd_c3_2 bnd_a219 bnd_a220) &
% 7.31/6.87 bnd_ndr1_1 bnd_a219) &
% 7.31/6.87 bnd_c6_2 bnd_a219 bnd_a221) &
% 7.31/6.87 bnd_c7_2 bnd_a219 bnd_a221)) &
% 7.31/6.87 ((bnd_c1_0 | ~ bnd_c9_0) |
% 7.31/6.87 (ALL V.
% 7.31/6.87 bnd_ndr1_0 -->
% 7.31/6.87 (bnd_c1_1 V |
% 7.31/6.87 (ALL W.
% 7.31/6.87 bnd_ndr1_1 V -->
% 7.31/6.87 (bnd_c1_2 V W | bnd_c8_2 V W) | ~ bnd_c3_2 V W)) |
% 7.31/6.87 (ALL X.
% 7.31/6.87 bnd_ndr1_1 V -->
% 7.31/6.87 (bnd_c8_2 V X | ~ bnd_c3_2 V X) | ~ bnd_c5_2 V X)))) &
% 7.31/6.87 ((bnd_c10_0 | ~ bnd_c7_0) |
% 7.31/6.87 ((bnd_ndr1_0 & ~ bnd_c1_1 bnd_a222) & ~ bnd_c7_1 bnd_a222) &
% 7.31/6.87 (ALL Y.
% 7.31/6.87 bnd_ndr1_1 bnd_a222 -->
% 7.31/6.87 (bnd_c3_2 bnd_a222 Y | ~ bnd_c1_2 bnd_a222 Y) |
% 7.31/6.87 ~ bnd_c2_2 bnd_a222 Y))) &
% 7.31/6.87 ((bnd_c10_0 |
% 7.31/6.87 (ALL Z. bnd_ndr1_0 --> (bnd_c1_1 Z | bnd_c9_1 Z) | ~ bnd_c7_1 Z)) |
% 7.31/6.87 (((((bnd_ndr1_0 & ~ bnd_c7_1 bnd_a223) &
% 7.31/6.87 (ALL X1.
% 7.31/6.87 bnd_ndr1_1 bnd_a223 -->
% 7.31/6.87 (~ bnd_c1_2 bnd_a223 X1 | ~ bnd_c7_2 bnd_a223 X1) |
% 7.31/6.87 ~ bnd_c8_2 bnd_a223 X1)) &
% 7.31/6.87 bnd_ndr1_1 bnd_a223) &
% 7.31/6.87 bnd_c9_2 bnd_a223 bnd_a224) &
% 7.31/6.87 ~ bnd_c1_2 bnd_a223 bnd_a224) &
% 7.31/6.87 ~ bnd_c10_2 bnd_a223 bnd_a224)) &
% 7.31/6.87 ((bnd_c10_0 |
% 7.31/6.87 (ALL X2.
% 7.31/6.87 bnd_ndr1_0 -->
% 7.31/6.87 (~ bnd_c5_1 X2 |
% 7.31/6.87 ((bnd_ndr1_1 X2 & bnd_c6_2 X2 bnd_a225) & bnd_c7_2 X2 bnd_a225) &
% 7.31/6.87 ~ bnd_c3_2 X2 bnd_a225) |
% 7.31/6.87 ((bnd_ndr1_1 X2 & bnd_c6_2 X2 bnd_a226) & ~ bnd_c4_2 X2 bnd_a226) &
% 7.31/6.87 ~ bnd_c7_2 X2 bnd_a226)) |
% 7.31/6.87 ((bnd_ndr1_0 & bnd_c9_1 bnd_a227) & ~ bnd_c1_1 bnd_a227) &
% 7.31/6.87 ~ bnd_c10_1 bnd_a227)) &
% 7.31/6.87 ((bnd_c10_0 |
% 7.31/6.87 (ALL X3.
% 7.31/6.87 bnd_ndr1_0 -->
% 7.31/6.87 (~ bnd_c8_1 X3 |
% 7.31/6.87 (ALL X4. bnd_ndr1_1 X3 --> bnd_c6_2 X3 X4 | ~ bnd_c8_2 X3 X4)) |
% 7.31/6.87 ((bnd_ndr1_1 X3 & bnd_c3_2 X3 bnd_a228) & bnd_c4_2 X3 bnd_a228) &
% 7.31/6.87 ~ bnd_c7_2 X3 bnd_a228)) |
% 7.31/6.87 (((((bnd_ndr1_0 & ~ bnd_c4_1 bnd_a229) &
% 7.31/6.87 (ALL X5.
% 7.31/6.87 bnd_ndr1_1 bnd_a229 -->
% 7.31/6.87 (bnd_c2_2 bnd_a229 X5 | bnd_c4_2 bnd_a229 X5) |
% 7.31/6.87 bnd_c7_2 bnd_a229 X5)) &
% 7.31/6.87 bnd_ndr1_1 bnd_a229) &
% 7.31/6.87 bnd_c1_2 bnd_a229 bnd_a230) &
% 7.31/6.87 bnd_c7_2 bnd_a229 bnd_a230) &
% 7.31/6.87 ~ bnd_c6_2 bnd_a229 bnd_a230)) &
% 7.31/6.87 ((bnd_c2_0 | bnd_c3_0) | bnd_c9_0)) &
% 7.31/6.87 ((bnd_c2_0 | bnd_c3_0) | ~ bnd_c10_0)) &
% 7.31/6.87 ((bnd_c2_0 | bnd_c3_0) | ~ bnd_c8_0)) &
% 7.31/6.87 (bnd_c2_0 |
% 7.31/6.87 (ALL X6.
% 7.31/6.87 bnd_ndr1_0 --> bnd_c9_1 X6 | ~ bnd_c3_1 X6))) &
% 7.31/6.87 ((bnd_c2_0 | ~ bnd_c3_0) |
% 7.31/6.87 (ALL X7.
% 7.31/6.87 bnd_ndr1_0 -->
% 7.31/6.87 (((bnd_ndr1_1 X7 & bnd_c10_2 X7 bnd_a231) & bnd_c8_2 X7 bnd_a231) &
% 7.31/6.87 ~ bnd_c9_2 X7 bnd_a231 |
% 7.31/6.87 ((bnd_ndr1_1 X7 & bnd_c4_2 X7 bnd_a232) & bnd_c8_2 X7 bnd_a232) &
% 7.31/6.87 ~ bnd_c2_2 X7 bnd_a232) |
% 7.31/6.87 ((bnd_ndr1_1 X7 & bnd_c6_2 X7 bnd_a233) & ~ bnd_c10_2 X7 bnd_a233) &
% 7.31/6.87 ~ bnd_c8_2 X7 bnd_a233))) &
% 7.31/6.87 ((bnd_c2_0 |
% 7.31/6.87 (ALL X8.
% 7.31/6.87 bnd_ndr1_0 -->
% 7.31/6.87 (bnd_c6_1 X8 | bnd_c7_1 X8) |
% 7.31/6.87 (ALL X9.
% 7.31/6.87 bnd_ndr1_1 X8 -->
% 7.31/6.87 (bnd_c7_2 X8 X9 | ~ bnd_c3_2 X8 X9) | ~ bnd_c8_2 X8 X9))) |
% 7.31/6.87 ((bnd_ndr1_0 & bnd_c6_1 bnd_a234) &
% 7.31/6.87 (ALL X10.
% 7.31/6.87 bnd_ndr1_1 bnd_a234 -->
% 7.31/6.87 (bnd_c1_2 bnd_a234 X10 | ~ bnd_c2_2 bnd_a234 X10) |
% 7.31/6.87 ~ bnd_c4_2 bnd_a234 X10)) &
% 7.31/6.87 (ALL X11.
% 7.31/6.87 bnd_ndr1_1 bnd_a234 -->
% 7.31/6.87 (bnd_c10_2 bnd_a234 X11 | bnd_c4_2 bnd_a234 X11) |
% 7.31/6.87 ~ bnd_c6_2 bnd_a234 X11))) &
% 7.31/6.87 ((bnd_c2_0 |
% 7.31/6.87 (ALL X12.
% 7.31/6.87 bnd_ndr1_0 -->
% 7.31/6.87 (~ bnd_c5_1 X12 |
% 7.31/6.87 (ALL X13.
% 7.31/6.87 bnd_ndr1_1 X12 -->
% 7.31/6.87 (bnd_c3_2 X12 X13 | bnd_c5_2 X12 X13) | ~ bnd_c10_2 X12 X13)) |
% 7.31/6.87 (ALL X14.
% 7.31/6.87 bnd_ndr1_1 X12 -->
% 7.31/6.87 (bnd_c3_2 X12 X14 | bnd_c7_2 X12 X14) | ~ bnd_c9_2 X12 X14))) |
% 7.31/6.87 (((((bnd_ndr1_0 & bnd_c9_1 bnd_a235) &
% 7.31/6.87 ~ bnd_c5_1 bnd_a235) &
% 7.31/6.87 bnd_ndr1_1 bnd_a235) &
% 7.31/6.87 bnd_c4_2 bnd_a235 bnd_a236) &
% 7.31/6.87 bnd_c7_2 bnd_a235 bnd_a236) &
% 7.31/6.87 ~ bnd_c9_2 bnd_a235 bnd_a236)) &
% 7.31/6.87 ((bnd_c2_0 |
% 7.31/6.87 (ALL X15.
% 7.31/6.87 bnd_ndr1_0 -->
% 7.31/6.87 (ALL X16.
% 7.31/6.87 bnd_ndr1_1 X15 -->
% 7.31/6.87 (bnd_c2_2 X15 X16 | bnd_c7_2 X15 X16) | ~ bnd_c8_2 X15 X16) |
% 7.31/6.87 (ALL X17.
% 7.31/6.87 bnd_ndr1_1 X15 -->
% 7.31/6.87 (bnd_c2_2 X15 X17 | bnd_c8_2 X15 X17) | ~ bnd_c5_2 X15 X17))) |
% 7.31/6.87 (((((bnd_ndr1_0 & bnd_c9_1 bnd_a237) &
% 7.31/6.87 ~ bnd_c4_1 bnd_a237) &
% 7.31/6.87 bnd_ndr1_1 bnd_a237) &
% 7.31/6.87 bnd_c10_2 bnd_a237 bnd_a238) &
% 7.31/6.87 ~ bnd_c5_2 bnd_a237 bnd_a238) &
% 7.31/6.87 ~ bnd_c7_2 bnd_a237 bnd_a238)) &
% 7.31/6.87 (bnd_c2_0 |
% 7.31/6.87 ((((bnd_ndr1_0 & bnd_c2_1 bnd_a239) &
% 7.31/6.87 bnd_ndr1_1 bnd_a239) &
% 7.31/6.87 bnd_c9_2 bnd_a239 bnd_a240) &
% 7.31/6.87 ~ bnd_c4_2 bnd_a239 bnd_a240) &
% 7.31/6.87 ~ bnd_c8_2 bnd_a239 bnd_a240)) &
% 7.31/6.87 ((bnd_c2_0 |
% 7.31/6.87 ((bnd_ndr1_0 & bnd_c7_1 bnd_a241) &
% 7.31/6.87 ~ bnd_c10_1 bnd_a241) &
% 7.31/6.87 ~ bnd_c9_1 bnd_a241) |
% 7.31/6.87 ((bnd_ndr1_0 &
% 7.31/6.87 (ALL X18.
% 7.31/6.87 bnd_ndr1_1 bnd_a242 -->
% 7.31/6.87 (bnd_c10_2 bnd_a242 X18 |
% 7.31/6.87 bnd_c9_2 bnd_a242 X18) |
% 7.31/6.87 ~ bnd_c2_2 bnd_a242 X18)) &
% 7.31/6.87 (ALL X19.
% 7.31/6.87 bnd_ndr1_1 bnd_a242 -->
% 7.31/6.87 (bnd_c10_2 bnd_a242 X19 |
% 7.31/6.87 ~ bnd_c1_2 bnd_a242 X19) |
% 7.31/6.87 ~ bnd_c2_2 bnd_a242 X19)) &
% 7.31/6.87 (ALL X20.
% 7.31/6.87 bnd_ndr1_1 bnd_a242 -->
% 7.31/6.87 (bnd_c8_2 bnd_a242 X20 |
% 7.31/6.87 ~ bnd_c1_2 bnd_a242 X20) |
% 7.31/6.87 ~ bnd_c5_2 bnd_a242 X20))) &
% 7.31/6.87 ((bnd_c3_0 | bnd_c4_0) |
% 7.31/6.87 (ALL X21.
% 7.31/6.87 bnd_ndr1_0 -->
% 7.31/6.87 bnd_c2_1 X21 |
% 7.31/6.87 ((bnd_ndr1_1 X21 &
% 7.31/6.87 bnd_c2_2 X21 bnd_a243) &
% 7.31/6.87 ~ bnd_c3_2 X21 bnd_a243) &
% 7.31/6.87 ~ bnd_c8_2 X21 bnd_a243))) &
% 7.31/6.87 ((bnd_c3_0 | bnd_c7_0) |
% 7.31/6.87 ((bnd_ndr1_0 & bnd_c7_1 bnd_a244) &
% 7.31/6.87 (ALL X22.
% 7.31/6.87 bnd_ndr1_1 bnd_a244 -->
% 7.31/6.87 (bnd_c2_2 bnd_a244 X22 |
% 7.31/6.87 ~ bnd_c1_2 bnd_a244 X22) |
% 7.31/6.87 ~ bnd_c10_2 bnd_a244 X22)) &
% 7.31/6.87 (ALL X23.
% 7.31/6.87 bnd_ndr1_1 bnd_a244 -->
% 7.31/6.87 (bnd_c6_2 bnd_a244 X23 |
% 7.31/6.87 ~ bnd_c7_2 bnd_a244 X23) |
% 7.31/6.87 ~ bnd_c8_2 bnd_a244 X23))) &
% 7.31/6.87 ((bnd_c3_0 | bnd_c8_0) | bnd_c9_0)) &
% 7.31/6.87 ((bnd_c3_0 | bnd_c8_0) |
% 7.31/6.87 ((((bnd_ndr1_0 & bnd_c9_1 bnd_a245) &
% 7.31/6.87 bnd_ndr1_1 bnd_a245) &
% 7.31/6.87 bnd_c5_2 bnd_a245 bnd_a246) &
% 7.31/6.87 bnd_c7_2 bnd_a245 bnd_a246) &
% 7.31/6.87 ~ bnd_c9_2 bnd_a245 bnd_a246)) &
% 7.31/6.87 ((bnd_c3_0 | ~ bnd_c4_0) | ~ bnd_c7_0)) &
% 7.31/6.87 ((bnd_c3_0 | ~ bnd_c9_0) |
% 7.31/6.87 (ALL X24.
% 7.31/6.87 bnd_ndr1_0 -->
% 7.31/6.87 (~ bnd_c3_1 X24 | ~ bnd_c4_1 X24) |
% 7.31/6.87 (ALL X25.
% 7.31/6.87 bnd_ndr1_1 X24 -->
% 7.31/6.87 (bnd_c4_2 X24 X25 | ~ bnd_c10_2 X24 X25) |
% 7.31/6.87 ~ bnd_c9_2 X24 X25)))) &
% 7.31/6.87 (bnd_c4_0 |
% 7.31/6.87 ((((((((bnd_ndr1_0 &
% 7.31/6.87 (ALL X26.
% 7.31/6.87 bnd_ndr1_1 bnd_a247 -->
% 7.31/6.87 (bnd_c9_2 bnd_a247 X26 |
% 7.31/6.87 ~ bnd_c3_2 bnd_a247 X26) |
% 7.31/6.87 ~ bnd_c6_2 bnd_a247 X26)) &
% 7.31/6.87 bnd_ndr1_1 bnd_a247) &
% 7.31/6.87 bnd_c10_2 bnd_a247 bnd_a248) &
% 7.31/6.87 bnd_c9_2 bnd_a247 bnd_a248) &
% 7.31/6.87 ~ bnd_c1_2 bnd_a247 bnd_a248) &
% 7.31/6.87 bnd_ndr1_1 bnd_a247) &
% 7.31/6.87 bnd_c2_2 bnd_a247 bnd_a249) &
% 7.31/6.87 bnd_c9_2 bnd_a247 bnd_a249) &
% 7.31/6.87 ~ bnd_c10_2 bnd_a247 bnd_a249)) &
% 7.31/6.87 ((bnd_c4_0 | bnd_c6_0) | bnd_c8_0)) &
% 7.31/6.87 ((bnd_c4_0 | bnd_c9_0) |
% 7.31/6.87 bnd_ndr1_0 & ~ bnd_c7_1 bnd_a250)) &
% 7.31/6.87 ((bnd_c4_0 | ~ bnd_c1_0) |
% 7.31/6.87 (ALL X27.
% 7.31/6.87 bnd_ndr1_0 -->
% 7.31/6.87 (bnd_c5_1 X27 | ~ bnd_c6_1 X27) |
% 7.31/6.87 ((bnd_ndr1_1 X27 & bnd_c10_2 X27 bnd_a251) &
% 7.31/6.87 bnd_c8_2 X27 bnd_a251) &
% 7.31/6.87 ~ bnd_c1_2 X27 bnd_a251))) &
% 7.31/6.87 ((bnd_c4_0 | ~ bnd_c10_0) |
% 7.31/6.87 (((((bnd_ndr1_0 & bnd_c1_1 bnd_a252) &
% 7.31/6.87 bnd_c6_1 bnd_a252) &
% 7.31/6.87 bnd_ndr1_1 bnd_a252) &
% 7.31/6.87 bnd_c8_2 bnd_a252 bnd_a253) &
% 7.31/6.87 ~ bnd_c1_2 bnd_a252 bnd_a253) &
% 7.31/6.87 ~ bnd_c2_2 bnd_a252 bnd_a253)) &
% 7.31/6.87 ((bnd_c4_0 | ~ bnd_c7_0) |
% 7.31/6.87 (ALL X28.
% 7.31/6.87 bnd_ndr1_0 -->
% 7.31/6.87 ((ALL X29.
% 7.31/6.87 bnd_ndr1_1 X28 -->
% 7.31/6.87 ~ bnd_c2_2 X28 X29 | ~ bnd_c3_2 X28 X29) |
% 7.31/6.87 ((bnd_ndr1_1 X28 & bnd_c1_2 X28 bnd_a254) &
% 7.31/6.87 bnd_c2_2 X28 bnd_a254) &
% 7.31/6.87 ~ bnd_c3_2 X28 bnd_a254) |
% 7.31/6.87 (bnd_ndr1_1 X28 & ~ bnd_c5_2 X28 bnd_a255) &
% 7.31/6.87 ~ bnd_c8_2 X28 bnd_a255))) &
% 7.31/6.87 ((bnd_c4_0 | ~ bnd_c9_0) |
% 7.31/6.87 ((bnd_ndr1_0 & bnd_c10_1 bnd_a256) &
% 7.31/6.87 ~ bnd_c9_1 bnd_a256) &
% 7.31/6.87 (ALL X30.
% 7.31/6.87 bnd_ndr1_1 bnd_a256 -->
% 7.31/6.87 bnd_c3_2 bnd_a256 X30 | ~ bnd_c5_2 bnd_a256 X30))) &
% 7.31/6.87 ((bnd_c4_0 |
% 7.31/6.87 (ALL X31.
% 7.31/6.87 bnd_ndr1_0 -->
% 7.31/6.87 (bnd_c10_1 X31 |
% 7.31/6.87 (ALL X32.
% 7.31/6.87 bnd_ndr1_1 X31 -->
% 7.31/6.87 (bnd_c2_2 X31 X32 | bnd_c3_2 X31 X32) |
% 7.31/6.87 bnd_c4_2 X31 X32)) |
% 7.31/6.87 (ALL X33.
% 7.31/6.87 bnd_ndr1_1 X31 -->
% 7.31/6.87 (bnd_c2_2 X31 X33 | bnd_c4_2 X31 X33) |
% 7.31/6.87 bnd_c8_2 X31 X33))) |
% 7.31/6.87 ((bnd_ndr1_0 & bnd_c3_1 bnd_a257) & bnd_c4_1 bnd_a257) &
% 7.31/6.87 bnd_c5_1 bnd_a257)) &
% 7.31/6.87 (bnd_c4_0 |
% 7.31/6.87 (ALL X34.
% 7.31/6.87 bnd_ndr1_0 -->
% 7.31/6.87 (bnd_c5_1 X34 | bnd_c8_1 X34) |
% 7.31/6.87 (ALL X35.
% 7.31/6.87 bnd_ndr1_1 X34 -->
% 7.31/6.87 (bnd_c2_2 X34 X35 | ~ bnd_c3_2 X34 X35) |
% 7.31/6.87 ~ bnd_c8_2 X34 X35)))) &
% 7.31/6.87 (bnd_c4_0 |
% 7.31/6.87 (ALL X36.
% 7.31/6.87 bnd_ndr1_0 -->
% 7.31/6.87 ((ALL X37.
% 7.31/6.87 bnd_ndr1_1 X36 -->
% 7.31/6.87 bnd_c8_2 X36 X37 | bnd_c9_2 X36 X37) |
% 7.31/6.87 (ALL X38.
% 7.31/6.87 bnd_ndr1_1 X36 -->
% 7.31/6.87 (~ bnd_c1_2 X36 X38 | ~ bnd_c7_2 X36 X38) |
% 7.31/6.87 ~ bnd_c9_2 X36 X38)) |
% 7.31/6.87 ((bnd_ndr1_1 X36 & bnd_c4_2 X36 bnd_a258) &
% 7.31/6.87 ~ bnd_c2_2 X36 bnd_a258) &
% 7.31/6.87 ~ bnd_c3_2 X36 bnd_a258))) &
% 7.31/6.87 (bnd_c6_0 |
% 7.31/6.87 (bnd_ndr1_0 & ~ bnd_c4_1 bnd_a259) & ~ bnd_c5_1 bnd_a259)) &
% 7.31/6.87 (bnd_c7_0 |
% 7.31/6.87 (ALL X39.
% 7.31/6.87 bnd_ndr1_0 -->
% 7.31/6.87 (bnd_c5_1 X39 |
% 7.31/6.87 ((bnd_ndr1_1 X39 & bnd_c10_2 X39 bnd_a260) &
% 7.31/6.87 bnd_c4_2 X39 bnd_a260) &
% 7.31/6.87 ~ bnd_c3_2 X39 bnd_a260) |
% 7.31/6.87 ((bnd_ndr1_1 X39 & bnd_c7_2 X39 bnd_a261) &
% 7.31/6.87 ~ bnd_c1_2 X39 bnd_a261) &
% 7.31/6.87 ~ bnd_c4_2 X39 bnd_a261))) &
% 7.31/6.87 (bnd_c7_0 |
% 7.31/6.87 ((bnd_ndr1_0 & bnd_c1_1 bnd_a262) & ~ bnd_c6_1 bnd_a262) &
% 7.31/6.87 (ALL X40.
% 7.31/6.87 bnd_ndr1_1 bnd_a262 -->
% 7.31/6.87 bnd_c5_2 bnd_a262 X40 | ~ bnd_c4_2 bnd_a262 X40))) &
% 7.31/6.87 (~ bnd_c1_0 | ~ bnd_c6_0)) &
% 7.31/6.87 (~ bnd_c10_0 |
% 7.31/6.87 (ALL X41.
% 7.31/6.87 bnd_ndr1_0 -->
% 7.31/6.87 (bnd_c7_1 X41 |
% 7.31/6.87 (ALL X42.
% 7.31/6.87 bnd_ndr1_1 X41 -->
% 7.31/6.87 (bnd_c10_2 X41 X42 | ~ bnd_c5_2 X41 X42) |
% 7.31/6.87 ~ bnd_c7_2 X41 X42)) |
% 7.31/6.87 ((bnd_ndr1_1 X41 & bnd_c3_2 X41 bnd_a263) &
% 7.31/6.87 bnd_c8_2 X41 bnd_a263) &
% 7.31/6.87 ~ bnd_c4_2 X41 bnd_a263))) &
% 7.31/6.87 (~ bnd_c4_0 |
% 7.31/6.87 (ALL X43.
% 7.31/6.87 bnd_ndr1_0 -->
% 7.31/6.87 (bnd_c3_1 X43 |
% 7.31/6.87 (ALL X44.
% 7.31/6.87 bnd_ndr1_1 X43 -->
% 7.31/6.87 bnd_c5_2 X43 X44 | ~ bnd_c9_2 X43 X44)) |
% 7.31/6.87 (ALL X45.
% 7.31/6.87 bnd_ndr1_1 X43 -->
% 7.31/6.87 (~ bnd_c10_2 X43 X45 | ~ bnd_c3_2 X43 X45) |
% 7.31/6.87 ~ bnd_c5_2 X43 X45)))) &
% 7.31/6.87 (~ bnd_c6_0 |
% 7.31/6.87 ((bnd_ndr1_0 & bnd_c6_1 bnd_a264) & bnd_c8_1 bnd_a264) &
% 7.31/6.87 ~ bnd_c1_1 bnd_a264)) &
% 7.31/6.87 (~ bnd_c9_0 |
% 7.31/6.87 (((((bnd_ndr1_0 & bnd_c8_1 bnd_a265) & ~ bnd_c10_1 bnd_a265) &
% 7.31/6.87 bnd_ndr1_1 bnd_a265) &
% 7.31/6.87 bnd_c4_2 bnd_a265 bnd_a266) &
% 7.31/6.87 bnd_c7_2 bnd_a265 bnd_a266) &
% 7.31/6.87 ~ bnd_c5_2 bnd_a265 bnd_a266)) &
% 7.31/6.87 ((ALL X46.
% 7.31/6.87 bnd_ndr1_0 -->
% 7.31/6.87 bnd_c4_1 X46 |
% 7.31/6.87 (ALL X47.
% 7.31/6.87 bnd_ndr1_1 X46 -->
% 7.31/6.87 (bnd_c2_2 X46 X47 | bnd_c3_2 X46 X47) | bnd_c6_2 X46 X47)) |
% 7.31/6.87 (ALL X48.
% 7.31/6.87 bnd_ndr1_0 -->
% 7.31/6.87 ~ bnd_c1_1 X48 |
% 7.31/6.87 ((bnd_ndr1_1 X48 & bnd_c8_2 X48 bnd_a267) &
% 7.31/6.87 ~ bnd_c3_2 X48 bnd_a267) &
% 7.31/6.87 ~ bnd_c9_2 X48 bnd_a267))) &
% 7.31/6.87 (ALL X49.
% 7.31/6.87 bnd_ndr1_0 -->
% 7.31/6.87 (~ bnd_c2_1 X49 | ~ bnd_c3_1 X49) |
% 7.31/6.87 (ALL X50.
% 7.31/6.87 bnd_ndr1_1 X49 -->
% 7.31/6.87 (bnd_c10_2 X49 X50 | bnd_c9_2 X49 X50) | ~ bnd_c6_2 X49 X50))) &
% 7.31/6.87 ((ALL X51.
% 7.31/6.87 bnd_ndr1_0 -->
% 7.31/6.87 ((bnd_ndr1_1 X51 & bnd_c4_2 X51 bnd_a268) &
% 7.31/6.87 ~ bnd_c2_2 X51 bnd_a268) &
% 7.31/6.87 ~ bnd_c3_2 X51 bnd_a268) |
% 7.31/6.87 (bnd_ndr1_0 & bnd_c5_1 bnd_a269) &
% 7.31/6.87 (ALL X52.
% 7.31/6.87 bnd_ndr1_1 bnd_a269 -->
% 7.31/6.87 (bnd_c5_2 bnd_a269 X52 | bnd_c6_2 bnd_a269 X52) |
% 7.31/6.87 ~ bnd_c9_2 bnd_a269 X52))) &
% 7.31/6.87 ((bnd_c6_0 | ~ bnd_c9_0) |
% 7.31/6.87 (ALL X53.
% 7.31/6.87 bnd_ndr1_0 -->
% 7.31/6.87 (ALL X54.
% 7.31/6.87 bnd_ndr1_1 X53 -->
% 7.31/6.87 (bnd_c1_2 X53 X54 | ~ bnd_c10_2 X53 X54) | ~ bnd_c2_2 X53 X54) |
% 7.31/6.87 (ALL X55.
% 7.31/6.87 bnd_ndr1_1 X53 -->
% 7.31/6.87 (~ bnd_c5_2 X53 X55 | ~ bnd_c6_2 X53 X55) |
% 7.31/6.87 ~ bnd_c8_2 X53 X55)))) &
% 7.31/6.87 ((bnd_c6_0 |
% 7.31/6.87 (ALL X56.
% 7.31/6.87 bnd_ndr1_0 -->
% 7.31/6.87 (bnd_c10_1 X56 |
% 7.31/6.87 (ALL X57.
% 7.31/6.87 bnd_ndr1_1 X56 -->
% 7.31/6.87 (bnd_c8_2 X56 X57 | ~ bnd_c6_2 X56 X57) | ~ bnd_c7_2 X56 X57)) |
% 7.31/6.87 ((bnd_ndr1_1 X56 & bnd_c1_2 X56 bnd_a270) & bnd_c3_2 X56 bnd_a270) &
% 7.31/6.87 ~ bnd_c10_2 X56 bnd_a270)) |
% 7.31/6.87 (ALL X58.
% 7.31/6.87 bnd_ndr1_0 -->
% 7.31/6.87 (bnd_c6_1 X58 |
% 7.31/6.87 ((bnd_ndr1_1 X58 & bnd_c3_2 X58 bnd_a271) & bnd_c8_2 X58 bnd_a271) &
% 7.31/6.87 ~ bnd_c10_2 X58 bnd_a271) |
% 7.31/6.87 ((bnd_ndr1_1 X58 & bnd_c6_2 X58 bnd_a272) & bnd_c8_2 X58 bnd_a272) &
% 7.31/6.87 ~ bnd_c2_2 X58 bnd_a272))) &
% 7.31/6.87 (bnd_c6_0 |
% 7.31/6.87 (ALL X59.
% 7.31/6.87 bnd_ndr1_0 -->
% 7.31/6.87 (bnd_c3_1 X59 | ~ bnd_c2_1 X59) |
% 7.31/6.87 ((bnd_ndr1_1 X59 & bnd_c2_2 X59 bnd_a273) & bnd_c5_2 X59 bnd_a273) &
% 7.31/6.87 bnd_c6_2 X59 bnd_a273))) &
% 7.31/6.87 ((bnd_c6_0 |
% 7.31/6.87 (ALL X60.
% 7.31/6.87 bnd_ndr1_0 -->
% 7.31/6.87 (bnd_c3_1 X60 | ~ bnd_c4_1 X60) |
% 7.31/6.87 ((bnd_ndr1_1 X60 & bnd_c2_2 X60 bnd_a274) & bnd_c3_2 X60 bnd_a274) &
% 7.31/6.87 ~ bnd_c4_2 X60 bnd_a274)) |
% 7.31/6.87 (ALL X61.
% 7.31/6.87 bnd_ndr1_0 -->
% 7.31/6.87 (bnd_c6_1 X61 |
% 7.31/6.87 (bnd_ndr1_1 X61 & bnd_c2_2 X61 bnd_a275) & bnd_c7_2 X61 bnd_a275) |
% 7.31/6.87 ((bnd_ndr1_1 X61 & bnd_c5_2 X61 bnd_a276) & ~ bnd_c10_2 X61 bnd_a276) &
% 7.31/6.87 ~ bnd_c4_2 X61 bnd_a276))) &
% 7.31/6.87 ((bnd_c6_0 |
% 7.31/6.87 (ALL X62.
% 7.31/6.87 bnd_ndr1_0 -->
% 7.31/6.87 (~ bnd_c2_1 X62 |
% 7.31/6.87 ((bnd_ndr1_1 X62 & bnd_c1_2 X62 bnd_a277) & bnd_c9_2 X62 bnd_a277) &
% 7.31/6.87 ~ bnd_c10_2 X62 bnd_a277) |
% 7.31/6.87 ((bnd_ndr1_1 X62 & bnd_c7_2 X62 bnd_a278) & bnd_c8_2 X62 bnd_a278) &
% 7.31/6.87 ~ bnd_c9_2 X62 bnd_a278)) |
% 7.31/6.87 (ALL X63.
% 7.31/6.87 bnd_ndr1_0 -->
% 7.31/6.87 ((ALL X64. bnd_ndr1_1 X63 --> bnd_c3_2 X63 X64 | ~ bnd_c7_2 X63 X64) |
% 7.31/6.87 ((bnd_ndr1_1 X63 & ~ bnd_c2_2 X63 bnd_a279) & ~ bnd_c8_2 X63 bnd_a279) &
% 7.31/6.87 ~ bnd_c9_2 X63 bnd_a279) |
% 7.31/6.87 (bnd_ndr1_1 X63 & ~ bnd_c4_2 X63 bnd_a280) & ~ bnd_c5_2 X63 bnd_a280))) &
% 7.31/6.87 (bnd_c6_0 |
% 7.31/6.87 ((((bnd_ndr1_0 & ~ bnd_c5_1 bnd_a281) &
% 7.31/6.87 (ALL X65.
% 7.31/6.87 bnd_ndr1_1 bnd_a281 -->
% 7.31/6.87 (bnd_c7_2 bnd_a281 X65 | ~ bnd_c2_2 bnd_a281 X65) |
% 7.31/6.87 ~ bnd_c3_2 bnd_a281 X65)) &
% 7.31/6.87 bnd_ndr1_1 bnd_a281) &
% 7.31/6.87 bnd_c8_2 bnd_a281 bnd_a282) &
% 7.31/6.87 ~ bnd_c4_2 bnd_a281 bnd_a282)) &
% 7.31/6.87 ((bnd_c7_0 | bnd_c8_0) | ~ bnd_c9_0)) &
% 7.31/6.87 ((bnd_c7_0 | bnd_c8_0) |
% 7.31/6.87 ((((((((bnd_ndr1_0 &
% 7.31/6.87 ~ bnd_c9_1 bnd_a283) &
% 7.31/6.87 bnd_ndr1_1 bnd_a283) &
% 7.31/6.87 bnd_c1_2 bnd_a283 bnd_a284) &
% 7.31/6.87 bnd_c7_2 bnd_a283 bnd_a284) &
% 7.31/6.87 ~ bnd_c6_2 bnd_a283 bnd_a284) &
% 7.31/6.87 bnd_ndr1_1 bnd_a283) &
% 7.31/6.87 bnd_c10_2 bnd_a283 bnd_a285) &
% 7.31/6.87 bnd_c2_2 bnd_a283 bnd_a285) &
% 7.31/6.87 bnd_c8_2 bnd_a283 bnd_a285)) &
% 7.31/6.87 ((bnd_c7_0 | bnd_c9_0) |
% 7.31/6.87 (ALL X66.
% 7.31/6.87 bnd_ndr1_0 -->
% 7.31/6.87 ((ALL X67.
% 7.31/6.87 bnd_ndr1_1 X66 -->
% 7.31/6.87 (bnd_c10_2 X66 X67 | bnd_c8_2 X66 X67) | ~ bnd_c3_2 X66 X67) |
% 7.31/6.87 (ALL X68.
% 7.31/6.87 bnd_ndr1_1 X66 -->
% 7.31/6.87 (bnd_c6_2 X66 X68 | bnd_c9_2 X66 X68) | ~ bnd_c1_2 X66 X68)) |
% 7.31/6.87 ((bnd_ndr1_1 X66 &
% 7.31/6.87 bnd_c2_2 X66 bnd_a286) &
% 7.31/6.87 ~ bnd_c1_2 X66 bnd_a286) &
% 7.31/6.87 ~ bnd_c4_2 X66 bnd_a286))) &
% 7.31/6.87 ((bnd_c7_0 | ~ bnd_c10_0) |
% 7.31/6.87 (((((bnd_ndr1_0 & bnd_c10_1 bnd_a287) &
% 7.31/6.87 (ALL X69.
% 7.31/6.87 bnd_ndr1_1 bnd_a287 -->
% 7.31/6.87 (bnd_c6_2 bnd_a287 X69 | bnd_c9_2 bnd_a287 X69) |
% 7.31/6.87 ~ bnd_c7_2 bnd_a287 X69)) &
% 7.31/6.87 bnd_ndr1_1 bnd_a287) &
% 7.31/6.87 bnd_c3_2 bnd_a287 bnd_a288) &
% 7.31/6.87 bnd_c8_2 bnd_a287 bnd_a288) &
% 7.31/6.87 ~ bnd_c9_2 bnd_a287 bnd_a288)) &
% 7.31/6.87 ((bnd_c7_0 | ~ bnd_c10_0) |
% 7.31/6.87 ((bnd_ndr1_0 & ~ bnd_c1_1 bnd_a289) &
% 7.31/6.87 ~ bnd_c9_1 bnd_a289) &
% 7.31/6.87 (ALL X70.
% 7.31/6.87 bnd_ndr1_1 bnd_a289 -->
% 7.31/6.87 (bnd_c2_2 bnd_a289 X70 |
% 7.31/6.87 bnd_c6_2 bnd_a289 X70) |
% 7.31/6.87 ~ bnd_c10_2 bnd_a289 X70))) &
% 7.31/6.87 ((bnd_c7_0 | ~ bnd_c4_0) |
% 7.31/6.87 (ALL X71.
% 7.31/6.87 bnd_ndr1_0 -->
% 7.31/6.87 (bnd_c5_1 X71 |
% 7.31/6.87 ((bnd_ndr1_1 X71 &
% 7.31/6.87 bnd_c1_2 X71 bnd_a290) &
% 7.31/6.87 bnd_c5_2 X71 bnd_a290) &
% 7.31/6.87 bnd_c7_2 X71 bnd_a290) |
% 7.31/6.87 ((bnd_ndr1_1 X71 &
% 7.31/6.87 ~ bnd_c5_2 X71 bnd_a291) &
% 7.31/6.87 ~ bnd_c6_2 X71 bnd_a291) &
% 7.31/6.87 ~ bnd_c9_2 X71 bnd_a291))) &
% 7.31/6.87 ((bnd_c7_0 |
% 7.31/6.87 (ALL X72.
% 7.31/6.87 bnd_ndr1_0 -->
% 7.31/6.87 (~ bnd_c5_1 X72 | ~ bnd_c6_1 X72) |
% 7.31/6.87 ((bnd_ndr1_1 X72 &
% 7.31/6.87 bnd_c7_2 X72 bnd_a292) &
% 7.31/6.87 ~ bnd_c1_2 X72 bnd_a292) &
% 7.31/6.87 ~ bnd_c9_2 X72 bnd_a292)) |
% 7.31/6.87 ((bnd_ndr1_0 & bnd_c7_1 bnd_a293) &
% 7.31/6.87 bnd_c9_1 bnd_a293) &
% 7.31/6.87 ~ bnd_c1_1 bnd_a293)) &
% 7.31/6.87 ((bnd_c8_0 | ~ bnd_c10_0) |
% 7.31/6.87 (ALL X73.
% 7.31/6.87 bnd_ndr1_0 -->
% 7.31/6.87 (~ bnd_c7_1 X73 | ~ bnd_c8_1 X73) |
% 7.31/6.87 ((bnd_ndr1_1 X73 & bnd_c9_2 X73 bnd_a294) &
% 7.31/6.87 ~ bnd_c2_2 X73 bnd_a294) &
% 7.31/6.87 ~ bnd_c8_2 X73 bnd_a294))) &
% 7.31/6.87 ((bnd_c8_0 | ~ bnd_c4_0) |
% 7.31/6.87 (ALL X74.
% 7.31/6.87 bnd_ndr1_0 -->
% 7.31/6.87 (bnd_c9_1 X74 |
% 7.31/6.87 (ALL X75.
% 7.31/6.87 bnd_ndr1_1 X74 -->
% 7.31/6.87 (bnd_c10_2 X74 X75 |
% 7.31/6.87 ~ bnd_c1_2 X74 X75) |
% 7.31/6.87 ~ bnd_c9_2 X74 X75)) |
% 7.31/6.87 (ALL X76.
% 7.31/6.87 bnd_ndr1_1 X74 -->
% 7.31/6.87 (bnd_c5_2 X74 X76 | bnd_c6_2 X74 X76) |
% 7.31/6.87 ~ bnd_c4_2 X74 X76)))) &
% 7.31/6.87 ((bnd_c8_0 | ~ bnd_c9_0) |
% 7.31/6.87 ((((bnd_ndr1_0 & bnd_c1_1 bnd_a295) &
% 7.31/6.87 bnd_ndr1_1 bnd_a295) &
% 7.31/6.87 bnd_c10_2 bnd_a295 bnd_a296) &
% 7.31/6.87 bnd_c3_2 bnd_a295 bnd_a296) &
% 7.31/6.87 ~ bnd_c9_2 bnd_a295 bnd_a296)) &
% 7.31/6.87 ((bnd_c8_0 |
% 7.31/6.87 (ALL X77.
% 7.31/6.87 bnd_ndr1_0 -->
% 7.31/6.87 (bnd_c4_1 X77 | ~ bnd_c1_1 X77) |
% 7.31/6.87 ((bnd_ndr1_1 X77 & ~ bnd_c2_2 X77 bnd_a297) &
% 7.31/6.87 ~ bnd_c6_2 X77 bnd_a297) &
% 7.31/6.87 ~ bnd_c7_2 X77 bnd_a297)) |
% 7.31/6.87 (ALL X78.
% 7.31/6.87 bnd_ndr1_0 -->
% 7.31/6.87 ((ALL X79.
% 7.31/6.87 bnd_ndr1_1 X78 -->
% 7.31/6.87 (bnd_c3_2 X78 X79 | ~ bnd_c1_2 X78 X79) |
% 7.31/6.87 ~ bnd_c7_2 X78 X79) |
% 7.31/6.87 ((bnd_ndr1_1 X78 & ~ bnd_c1_2 X78 bnd_a298) &
% 7.31/6.87 ~ bnd_c5_2 X78 bnd_a298) &
% 7.31/6.87 ~ bnd_c9_2 X78 bnd_a298) |
% 7.31/6.87 ((bnd_ndr1_1 X78 & ~ bnd_c3_2 X78 bnd_a299) &
% 7.31/6.87 ~ bnd_c4_2 X78 bnd_a299) &
% 7.31/6.87 ~ bnd_c8_2 X78 bnd_a299))) &
% 7.31/6.87 ((bnd_c8_0 |
% 7.31/6.87 (ALL X80.
% 7.31/6.87 bnd_ndr1_0 -->
% 7.31/6.87 (bnd_c4_1 X80 |
% 7.31/6.87 ((bnd_ndr1_1 X80 & bnd_c2_2 X80 bnd_a300) &
% 7.31/6.87 bnd_c4_2 X80 bnd_a300) &
% 7.31/6.87 ~ bnd_c3_2 X80 bnd_a300) |
% 7.31/6.87 ((bnd_ndr1_1 X80 & ~ bnd_c1_2 X80 bnd_a301) &
% 7.31/6.87 ~ bnd_c4_2 X80 bnd_a301) &
% 7.31/6.87 ~ bnd_c9_2 X80 bnd_a301)) |
% 7.31/6.87 (ALL X81.
% 7.31/6.87 bnd_ndr1_0 -->
% 7.31/6.87 (~ bnd_c8_1 X81 |
% 7.31/6.87 ((bnd_ndr1_1 X81 & bnd_c5_2 X81 bnd_a302) &
% 7.31/6.87 bnd_c9_2 X81 bnd_a302) &
% 7.31/6.87 ~ bnd_c8_2 X81 bnd_a302) |
% 7.31/6.87 (bnd_ndr1_1 X81 & bnd_c5_2 X81 bnd_a303) &
% 7.31/6.87 ~ bnd_c8_2 X81 bnd_a303))) &
% 7.31/6.87 ((bnd_c8_0 |
% 7.31/6.87 (ALL X82.
% 7.31/6.87 bnd_ndr1_0 -->
% 7.31/6.87 ~ bnd_c10_1 X82 | ~ bnd_c3_1 X82)) |
% 7.31/6.87 ((bnd_ndr1_0 & ~ bnd_c4_1 bnd_a304) &
% 7.31/6.87 ~ bnd_c5_1 bnd_a304) &
% 7.31/6.87 (ALL X83.
% 7.31/6.87 bnd_ndr1_1 bnd_a304 -->
% 7.31/6.87 (bnd_c4_2 bnd_a304 X83 |
% 7.31/6.87 ~ bnd_c5_2 bnd_a304 X83) |
% 7.31/6.87 ~ bnd_c8_2 bnd_a304 X83))) &
% 7.31/6.87 ((bnd_c8_0 |
% 7.31/6.87 (ALL X84.
% 7.31/6.87 bnd_ndr1_0 -->
% 7.31/6.87 ((ALL X85.
% 7.31/6.87 bnd_ndr1_1 X84 -->
% 7.31/6.87 (bnd_c1_2 X84 X85 | ~ bnd_c10_2 X84 X85) |
% 7.31/6.87 ~ bnd_c7_2 X84 X85) |
% 7.31/6.87 ((bnd_ndr1_1 X84 & bnd_c5_2 X84 bnd_a305) &
% 7.31/6.87 bnd_c6_2 X84 bnd_a305) &
% 7.31/6.87 bnd_c8_2 X84 bnd_a305) |
% 7.31/6.87 ((bnd_ndr1_1 X84 & bnd_c5_2 X84 bnd_a306) &
% 7.31/6.87 ~ bnd_c4_2 X84 bnd_a306) &
% 7.31/6.87 ~ bnd_c9_2 X84 bnd_a306)) |
% 7.31/6.87 (ALL X86.
% 7.31/6.87 bnd_ndr1_0 -->
% 7.31/6.87 ((bnd_ndr1_1 X86 & bnd_c1_2 X86 bnd_a307) &
% 7.31/6.87 bnd_c6_2 X86 bnd_a307) &
% 7.31/6.87 ~ bnd_c9_2 X86 bnd_a307 |
% 7.31/6.87 ((bnd_ndr1_1 X86 & bnd_c7_2 X86 bnd_a308) &
% 7.31/6.87 ~ bnd_c4_2 X86 bnd_a308) &
% 7.31/6.87 ~ bnd_c5_2 X86 bnd_a308))) &
% 7.31/6.87 ((bnd_c9_0 | ~ bnd_c1_0) |
% 7.31/6.87 (ALL X87.
% 7.31/6.87 bnd_ndr1_0 -->
% 7.31/6.87 (bnd_c1_1 X87 | bnd_c6_1 X87) | ~ bnd_c8_1 X87))) &
% 7.31/6.87 ((bnd_c9_0 | ~ bnd_c4_0) |
% 7.31/6.87 ((bnd_ndr1_0 & ~ bnd_c6_1 bnd_a309) &
% 7.31/6.87 (ALL X88.
% 7.31/6.87 bnd_ndr1_1 bnd_a309 -->
% 7.31/6.87 (bnd_c10_2 bnd_a309 X88 | bnd_c9_2 bnd_a309 X88) |
% 7.31/6.87 ~ bnd_c6_2 bnd_a309 X88)) &
% 7.31/6.87 (ALL X89.
% 7.31/6.87 bnd_ndr1_1 bnd_a309 -->
% 7.31/6.87 (bnd_c5_2 bnd_a309 X89 | ~ bnd_c10_2 bnd_a309 X89) |
% 7.31/6.87 ~ bnd_c4_2 bnd_a309 X89))) &
% 7.31/6.87 (bnd_c9_0 | ~ bnd_c6_0)) &
% 7.31/6.87 ((bnd_c9_0 | ~ bnd_c6_0) |
% 7.31/6.87 ((bnd_ndr1_0 & bnd_c6_1 bnd_a310) & ~ bnd_c1_1 bnd_a310) &
% 7.31/6.87 (ALL X90.
% 7.31/6.87 bnd_ndr1_1 bnd_a310 -->
% 7.31/6.87 (bnd_c2_2 bnd_a310 X90 | ~ bnd_c6_2 bnd_a310 X90) |
% 7.31/6.87 ~ bnd_c9_2 bnd_a310 X90))) &
% 7.31/6.87 ((bnd_c9_0 | ~ bnd_c7_0) |
% 7.31/6.87 (ALL X91.
% 7.31/6.87 bnd_ndr1_0 -->
% 7.31/6.87 (bnd_c9_1 X91 |
% 7.31/6.87 ((bnd_ndr1_1 X91 & bnd_c4_2 X91 bnd_a311) &
% 7.31/6.87 ~ bnd_c2_2 X91 bnd_a311) &
% 7.31/6.87 ~ bnd_c9_2 X91 bnd_a311) |
% 7.31/6.87 ((bnd_ndr1_1 X91 & bnd_c8_2 X91 bnd_a312) &
% 7.31/6.87 bnd_c9_2 X91 bnd_a312) &
% 7.31/6.87 ~ bnd_c6_2 X91 bnd_a312))) &
% 7.31/6.87 ((bnd_c9_0 |
% 7.31/6.87 (ALL X92.
% 7.31/6.87 bnd_ndr1_0 -->
% 7.31/6.87 (~ bnd_c5_1 X92 | ~ bnd_c6_1 X92) |
% 7.31/6.87 (bnd_ndr1_1 X92 & bnd_c3_2 X92 bnd_a313) &
% 7.31/6.87 ~ bnd_c9_2 X92 bnd_a313)) |
% 7.31/6.87 (((((bnd_ndr1_0 & ~ bnd_c4_1 bnd_a314) &
% 7.31/6.87 (ALL X93.
% 7.31/6.87 bnd_ndr1_1 bnd_a314 -->
% 7.31/6.87 (bnd_c7_2 bnd_a314 X93 | ~ bnd_c4_2 bnd_a314 X93) |
% 7.31/6.87 ~ bnd_c8_2 bnd_a314 X93)) &
% 7.31/6.87 bnd_ndr1_1 bnd_a314) &
% 7.31/6.87 bnd_c4_2 bnd_a314 bnd_a315) &
% 7.31/6.87 bnd_c7_2 bnd_a314 bnd_a315) &
% 7.31/6.87 ~ bnd_c5_2 bnd_a314 bnd_a315)) &
% 7.31/6.87 ((bnd_c9_0 |
% 7.31/6.87 (((((bnd_ndr1_0 & bnd_c8_1 bnd_a316) &
% 7.31/6.87 (ALL X94.
% 7.31/6.87 bnd_ndr1_1 bnd_a316 -->
% 7.31/6.87 ~ bnd_c6_2 bnd_a316 X94 |
% 7.31/6.87 ~ bnd_c9_2 bnd_a316 X94)) &
% 7.31/6.87 bnd_ndr1_1 bnd_a316) &
% 7.31/6.87 bnd_c2_2 bnd_a316 bnd_a317) &
% 7.31/6.87 bnd_c7_2 bnd_a316 bnd_a317) &
% 7.31/6.87 ~ bnd_c8_2 bnd_a316 bnd_a317) |
% 7.31/6.87 ((bnd_ndr1_0 & ~ bnd_c10_1 bnd_a318) & ~ bnd_c8_1 bnd_a318) &
% 7.31/6.87 (ALL X95.
% 7.31/6.87 bnd_ndr1_1 bnd_a318 -->
% 7.31/6.87 (~ bnd_c10_2 bnd_a318 X95 | ~ bnd_c4_2 bnd_a318 X95) |
% 7.31/6.87 ~ bnd_c7_2 bnd_a318 X95))) &
% 7.31/6.87 ((~ bnd_c1_0 | ~ bnd_c10_0) |
% 7.31/6.87 ((((((bnd_ndr1_0 & ~ bnd_c8_1 bnd_a319) &
% 7.31/6.87 bnd_ndr1_1 bnd_a319) &
% 7.31/6.87 bnd_c4_2 bnd_a319 bnd_a320) &
% 7.31/6.87 bnd_c5_2 bnd_a319 bnd_a320) &
% 7.31/6.87 bnd_c6_2 bnd_a319 bnd_a320) &
% 7.31/6.87 bnd_ndr1_1 bnd_a319) &
% 7.31/6.87 ~ bnd_c2_2 bnd_a319 bnd_a321)) &
% 7.31/6.87 ((~ bnd_c1_0 | ~ bnd_c4_0) |
% 7.31/6.87 (ALL X96.
% 7.31/6.87 bnd_ndr1_0 -->
% 7.31/6.87 ~ bnd_c2_1 X96 |
% 7.31/6.87 ((bnd_ndr1_1 X96 & bnd_c4_2 X96 bnd_a322) &
% 7.31/6.87 ~ bnd_c10_2 X96 bnd_a322) &
% 7.31/6.87 ~ bnd_c9_2 X96 bnd_a322))) &
% 7.31/6.87 ((~ bnd_c1_0 |
% 7.31/6.87 (ALL X97.
% 7.31/6.87 bnd_ndr1_0 -->
% 7.31/6.87 (bnd_c1_1 X97 | bnd_c4_1 X97) |
% 7.31/6.87 (ALL X98.
% 7.31/6.87 bnd_ndr1_1 X97 -->
% 7.31/6.87 (bnd_c1_2 X97 X98 | bnd_c2_2 X97 X98) |
% 7.31/6.87 ~ bnd_c6_2 X97 X98))) |
% 7.31/6.87 (((((bnd_ndr1_0 & bnd_c7_1 bnd_a323) &
% 7.31/6.87 (ALL X99.
% 7.31/6.87 bnd_ndr1_1 bnd_a323 -->
% 7.31/6.87 (bnd_c6_2 bnd_a323 X99 | ~ bnd_c10_2 bnd_a323 X99) |
% 7.31/6.87 ~ bnd_c9_2 bnd_a323 X99)) &
% 7.31/6.87 bnd_ndr1_1 bnd_a323) &
% 7.31/6.87 bnd_c1_2 bnd_a323 bnd_a324) &
% 7.31/6.87 bnd_c2_2 bnd_a323 bnd_a324) &
% 7.31/6.87 ~ bnd_c3_2 bnd_a323 bnd_a324)) &
% 7.31/6.87 ((~ bnd_c1_0 |
% 7.31/6.87 (ALL X100.
% 7.31/6.87 bnd_ndr1_0 -->
% 7.31/6.87 (~ bnd_c2_1 X100 |
% 7.31/6.87 (ALL X101.
% 7.31/6.87 bnd_ndr1_1 X100 -->
% 7.31/6.87 (bnd_c10_2 X100 X101 | ~ bnd_c1_2 X100 X101) |
% 7.31/6.88 ~ bnd_c5_2 X100 X101)) |
% 7.31/6.88 (bnd_ndr1_1 X100 & bnd_c3_2 X100 bnd_a325) &
% 7.31/6.88 bnd_c4_2 X100 bnd_a325)) |
% 7.31/6.88 (bnd_ndr1_0 &
% 7.31/6.88 (ALL X102.
% 7.31/6.88 bnd_ndr1_1 bnd_a326 -->
% 7.31/6.88 (bnd_c4_2 bnd_a326 X102 | bnd_c6_2 bnd_a326 X102) |
% 7.31/6.88 ~ bnd_c7_2 bnd_a326 X102)) &
% 7.31/6.88 (ALL X103.
% 7.31/6.88 bnd_ndr1_1 bnd_a326 -->
% 7.31/6.88 (~ bnd_c10_2 bnd_a326 X103 | ~ bnd_c5_2 bnd_a326 X103) |
% 7.31/6.88 ~ bnd_c9_2 bnd_a326 X103))) &
% 7.31/6.88 (~ bnd_c1_0 |
% 7.31/6.88 ((bnd_ndr1_0 & bnd_c10_1 bnd_a327) & bnd_c6_1 bnd_a327) &
% 7.31/6.88 ~ bnd_c3_1 bnd_a327)) &
% 7.31/6.88 ((~ bnd_c1_0 |
% 7.31/6.88 (((((bnd_ndr1_0 & bnd_c2_1 bnd_a328) &
% 7.31/6.88 (ALL X104.
% 7.31/6.88 bnd_ndr1_1 bnd_a328 --> ~ bnd_c8_2 bnd_a328 X104)) &
% 7.31/6.88 bnd_ndr1_1 bnd_a328) &
% 7.31/6.88 bnd_c10_2 bnd_a328 bnd_a329) &
% 7.31/6.88 bnd_c6_2 bnd_a328 bnd_a329) &
% 7.31/6.88 ~ bnd_c8_2 bnd_a328 bnd_a329) |
% 7.31/6.88 ((bnd_ndr1_0 & ~ bnd_c10_1 bnd_a330) & ~ bnd_c8_1 bnd_a330) &
% 7.31/6.88 ~ bnd_c9_1 bnd_a330)) &
% 7.31/6.88 ((~ bnd_c10_0 | ~ bnd_c3_0) |
% 7.31/6.88 (ALL X105.
% 7.31/6.88 bnd_ndr1_0 -->
% 7.31/6.88 bnd_c5_1 X105 |
% 7.31/6.88 ((bnd_ndr1_1 X105 & bnd_c6_2 X105 bnd_a331) &
% 7.31/6.88 bnd_c8_2 X105 bnd_a331) &
% 7.31/6.88 ~ bnd_c7_2 X105 bnd_a331))) &
% 7.31/6.88 ((~ bnd_c10_0 | ~ bnd_c6_0) |
% 7.31/6.88 (ALL X106. bnd_ndr1_0 --> bnd_c6_1 X106 | ~ bnd_c8_1 X106))) &
% 7.31/6.88 ((~ bnd_c10_0 | ~ bnd_c8_0) |
% 7.31/6.88 ((bnd_ndr1_0 & ~ bnd_c1_1 bnd_a332) & ~ bnd_c4_1 bnd_a332) &
% 7.31/6.88 (ALL X107.
% 7.31/6.88 bnd_ndr1_1 bnd_a332 -->
% 7.31/6.88 (bnd_c10_2 bnd_a332 X107 | bnd_c9_2 bnd_a332 X107) |
% 7.31/6.88 ~ bnd_c1_2 bnd_a332 X107))) &
% 7.31/6.88 ((~ bnd_c10_0 |
% 7.31/6.88 (ALL X108.
% 7.31/6.88 bnd_ndr1_0 -->
% 7.31/6.88 (bnd_c5_1 X108 | ~ bnd_c7_1 X108) |
% 7.31/6.88 (ALL X109.
% 7.31/6.88 bnd_ndr1_1 X108 -->
% 7.31/6.88 (bnd_c8_2 X108 X109 | bnd_c9_2 X108 X109) |
% 7.31/6.88 ~ bnd_c2_2 X108 X109))) |
% 7.31/6.88 (((((bnd_ndr1_0 & bnd_c7_1 bnd_a333) & ~ bnd_c10_1 bnd_a333) &
% 7.31/6.88 bnd_ndr1_1 bnd_a333) &
% 7.31/6.88 bnd_c10_2 bnd_a333 bnd_a334) &
% 7.31/6.88 ~ bnd_c7_2 bnd_a333 bnd_a334) &
% 7.31/6.88 ~ bnd_c9_2 bnd_a333 bnd_a334)) &
% 7.31/6.88 ((~ bnd_c10_0 |
% 7.31/6.88 (((((bnd_ndr1_0 & bnd_c3_1 bnd_a335) & ~ bnd_c7_1 bnd_a335) &
% 7.31/6.88 bnd_ndr1_1 bnd_a335) &
% 7.31/6.88 bnd_c2_2 bnd_a335 bnd_a336) &
% 7.31/6.88 bnd_c8_2 bnd_a335 bnd_a336) &
% 7.31/6.88 ~ bnd_c4_2 bnd_a335 bnd_a336) |
% 7.31/6.88 ((bnd_ndr1_0 & ~ bnd_c5_1 bnd_a337) & ~ bnd_c9_1 bnd_a337) &
% 7.31/6.88 (ALL X110.
% 7.31/6.88 bnd_ndr1_1 bnd_a337 -->
% 7.31/6.88 bnd_c9_2 bnd_a337 X110 | ~ bnd_c10_2 bnd_a337 X110))) &
% 7.31/6.88 ((~ bnd_c2_0 | ~ bnd_c8_0) |
% 7.31/6.88 (ALL X111.
% 7.31/6.88 bnd_ndr1_0 -->
% 7.31/6.88 (bnd_c8_1 X111 |
% 7.31/6.88 (ALL X112.
% 7.31/6.88 bnd_ndr1_1 X111 -->
% 7.31/6.88 (bnd_c10_2 X111 X112 | ~ bnd_c8_2 X111 X112) |
% 7.31/6.88 ~ bnd_c9_2 X111 X112)) |
% 7.31/6.88 ((bnd_ndr1_1 X111 & bnd_c10_2 X111 bnd_a338) &
% 7.31/6.88 bnd_c2_2 X111 bnd_a338) &
% 7.31/6.88 ~ bnd_c7_2 X111 bnd_a338))) &
% 7.31/6.88 ((~ bnd_c2_0 | ~ bnd_c9_0) |
% 7.31/6.88 (ALL X113.
% 7.31/6.88 bnd_ndr1_0 -->
% 7.31/6.88 (bnd_c1_1 X113 |
% 7.31/6.88 (ALL X114.
% 7.31/6.88 bnd_ndr1_1 X113 -->
% 7.31/6.88 (bnd_c1_2 X113 X114 | bnd_c7_2 X113 X114) |
% 7.31/6.88 ~ bnd_c2_2 X113 X114)) |
% 7.31/6.88 (ALL X115.
% 7.31/6.88 bnd_ndr1_1 X113 -->
% 7.31/6.88 (~ bnd_c1_2 X113 X115 | ~ bnd_c10_2 X113 X115) |
% 7.31/6.88 ~ bnd_c8_2 X113 X115)))) &
% 7.31/6.88 ((~ bnd_c2_0 | (bnd_ndr1_0 & bnd_c3_1 bnd_a339) & ~ bnd_c6_1 bnd_a339) |
% 7.31/6.88 ((((bnd_ndr1_0 & ~ bnd_c8_1 bnd_a340) & bnd_ndr1_1 bnd_a340) &
% 7.31/6.88 bnd_c1_2 bnd_a340 bnd_a341) &
% 7.31/6.88 bnd_c7_2 bnd_a340 bnd_a341) &
% 7.31/6.88 bnd_c9_2 bnd_a340 bnd_a341)) &
% 7.31/6.88 ((~ bnd_c3_0 | ~ bnd_c7_0) |
% 7.31/6.88 ((bnd_ndr1_0 & ~ bnd_c2_1 bnd_a342) & ~ bnd_c3_1 bnd_a342) &
% 7.31/6.88 (ALL X116.
% 7.31/6.88 bnd_ndr1_1 bnd_a342 -->
% 7.31/6.88 (bnd_c6_2 bnd_a342 X116 | bnd_c8_2 bnd_a342 X116) |
% 7.31/6.88 ~ bnd_c3_2 bnd_a342 X116))) &
% 7.31/6.88 ((~ bnd_c3_0 |
% 7.31/6.88 (ALL X117.
% 7.31/6.88 bnd_ndr1_0 -->
% 7.31/6.88 (bnd_c10_1 X117 | bnd_c2_1 X117) |
% 7.31/6.88 (ALL X118.
% 7.31/6.88 bnd_ndr1_1 X117 -->
% 7.31/6.88 (bnd_c6_2 X117 X118 | bnd_c8_2 X117 X118) |
% 7.31/6.88 ~ bnd_c3_2 X117 X118))) |
% 7.31/6.88 (ALL X119.
% 7.31/6.88 bnd_ndr1_0 -->
% 7.31/6.88 ((ALL X120.
% 7.31/6.88 bnd_ndr1_1 X119 -->
% 7.31/6.88 (bnd_c1_2 X119 X120 | ~ bnd_c4_2 X119 X120) |
% 7.31/6.88 ~ bnd_c9_2 X119 X120) |
% 7.31/6.88 (ALL X121.
% 7.31/6.88 bnd_ndr1_1 X119 -->
% 7.31/6.88 (bnd_c6_2 X119 X121 | ~ bnd_c2_2 X119 X121) |
% 7.31/6.88 ~ bnd_c3_2 X119 X121)) |
% 7.31/6.88 ((bnd_ndr1_1 X119 & bnd_c9_2 X119 bnd_a343) & ~ bnd_c3_2 X119 bnd_a343) &
% 7.31/6.88 ~ bnd_c4_2 X119 bnd_a343))) &
% 7.31/6.88 ((~ bnd_c3_0 |
% 7.31/6.88 (ALL X122.
% 7.31/6.88 bnd_ndr1_0 -->
% 7.31/6.88 bnd_c4_1 X122 |
% 7.31/6.88 ((bnd_ndr1_1 X122 & bnd_c1_2 X122 bnd_a344) & bnd_c6_2 X122 bnd_a344) &
% 7.31/6.88 ~ bnd_c9_2 X122 bnd_a344)) |
% 7.31/6.88 (ALL X123.
% 7.31/6.88 bnd_ndr1_0 -->
% 7.31/6.88 (bnd_c7_1 X123 | bnd_c9_1 X123) |
% 7.31/6.88 ((bnd_ndr1_1 X123 & bnd_c3_2 X123 bnd_a345) & bnd_c7_2 X123 bnd_a345) &
% 7.31/6.88 ~ bnd_c9_2 X123 bnd_a345))) &
% 7.31/6.88 ((~ bnd_c3_0 |
% 7.31/6.88 (ALL X124.
% 7.31/6.88 bnd_ndr1_0 -->
% 7.31/6.88 ((ALL X125.
% 7.31/6.88 bnd_ndr1_1 X124 -->
% 7.31/6.88 (bnd_c10_2 X124 X125 | bnd_c8_2 X124 X125) | ~ bnd_c6_2 X124 X125) |
% 7.31/6.88 (ALL X126.
% 7.31/6.88 bnd_ndr1_1 X124 -->
% 7.31/6.88 (bnd_c10_2 X124 X126 | ~ bnd_c3_2 X124 X126) |
% 7.31/6.88 ~ bnd_c8_2 X124 X126)) |
% 7.31/6.88 (ALL X127.
% 7.31/6.88 bnd_ndr1_1 X124 -->
% 7.31/6.88 (bnd_c4_2 X124 X127 | ~ bnd_c3_2 X124 X127) |
% 7.31/6.88 ~ bnd_c7_2 X124 X127))) |
% 7.31/6.88 (bnd_ndr1_0 & bnd_c5_1 bnd_a346) &
% 7.31/6.88 (ALL X128.
% 7.31/6.88 bnd_ndr1_1 bnd_a346 -->
% 7.31/6.88 (~ bnd_c3_2 bnd_a346 X128 | ~ bnd_c6_2 bnd_a346 X128) |
% 7.31/6.88 ~ bnd_c7_2 bnd_a346 X128))) &
% 7.31/6.88 ((~ bnd_c4_0 | ~ bnd_c7_0) |
% 7.31/6.88 (ALL X129.
% 7.31/6.88 bnd_ndr1_0 -->
% 7.31/6.88 (bnd_c1_1 X129 | bnd_c7_1 X129) |
% 7.31/6.88 ((bnd_ndr1_1 X129 & bnd_c2_2 X129 bnd_a347) & bnd_c8_2 X129 bnd_a347) &
% 7.31/6.88 ~ bnd_c7_2 X129 bnd_a347))) &
% 7.31/6.88 ((~ bnd_c4_0 |
% 7.31/6.88 (ALL X130.
% 7.31/6.88 bnd_ndr1_0 -->
% 7.31/6.88 (bnd_c7_1 X130 |
% 7.31/6.88 ((bnd_ndr1_1 X130 & bnd_c9_2 X130 bnd_a348) & ~ bnd_c3_2 X130 bnd_a348) &
% 7.31/6.88 ~ bnd_c4_2 X130 bnd_a348) |
% 7.31/6.88 ((bnd_ndr1_1 X130 & ~ bnd_c1_2 X130 bnd_a349) & ~ bnd_c2_2 X130 bnd_a349) &
% 7.31/6.88 ~ bnd_c5_2 X130 bnd_a349)) |
% 7.31/6.88 (((((((bnd_ndr1_0 &
% 7.31/6.88 (ALL X131.
% 7.31/6.88 bnd_ndr1_1 bnd_a350 -->
% 7.31/6.88 (bnd_c8_2 bnd_a350 X131 | ~ bnd_c1_2 bnd_a350 X131) |
% 7.31/6.88 ~ bnd_c5_2 bnd_a350 X131)) &
% 7.31/6.88 bnd_ndr1_1 bnd_a350) &
% 7.31/6.88 bnd_c5_2 bnd_a350 bnd_a351) &
% 7.31/6.88 ~ bnd_c6_2 bnd_a350 bnd_a351) &
% 7.31/6.88 bnd_ndr1_1 bnd_a350) &
% 7.31/6.88 bnd_c7_2 bnd_a350 bnd_a352) &
% 7.31/6.88 ~ bnd_c4_2 bnd_a350 bnd_a352) &
% 7.31/6.88 ~ bnd_c5_2 bnd_a350 bnd_a352)) &
% 7.31/6.88 (~ bnd_c6_0 | ~ bnd_c9_0)) &
% 7.31/6.88 ((~ bnd_c7_0 |
% 7.31/6.88 (ALL X132.
% 7.31/6.88 bnd_ndr1_0 -->
% 7.31/6.88 (bnd_c1_1 X132 | bnd_c4_1 X132) |
% 7.31/6.88 bnd_c8_1 X132)) |
% 7.31/6.88 (ALL X133.
% 7.31/6.88 bnd_ndr1_0 -->
% 7.31/6.88 (bnd_c3_1 X133 | ~ bnd_c8_1 X133) |
% 7.31/6.88 (ALL X134.
% 7.31/6.88 bnd_ndr1_1 X133 -->
% 7.31/6.88 (bnd_c1_2 X133 X134 | bnd_c2_2 X133 X134) | ~ bnd_c7_2 X133 X134)))) &
% 7.31/6.88 ((~ bnd_c7_0 |
% 7.31/6.88 (ALL X135.
% 7.31/6.88 bnd_ndr1_0 -->
% 7.31/6.88 (bnd_c3_1 X135 | ~ bnd_c4_1 X135) |
% 7.31/6.88 ~ bnd_c5_1 X135)) |
% 7.31/6.88 (ALL X136.
% 7.31/6.88 bnd_ndr1_0 -->
% 7.31/6.88 (~ bnd_c7_1 X136 |
% 7.31/6.88 (ALL X137.
% 7.31/6.88 bnd_ndr1_1 X136 -->
% 7.31/6.88 (bnd_c1_2 X136 X137 | bnd_c2_2 X136 X137) | bnd_c3_2 X136 X137)) |
% 7.31/6.88 ((bnd_ndr1_1 X136 &
% 7.31/6.88 bnd_c4_2 X136 bnd_a353) &
% 7.31/6.88 ~ bnd_c1_2 X136 bnd_a353) &
% 7.31/6.88 ~ bnd_c9_2 X136 bnd_a353))) &
% 7.31/6.88 ((~ bnd_c7_0 |
% 7.31/6.88 (ALL X138.
% 7.31/6.88 bnd_ndr1_0 -->
% 7.31/6.88 (bnd_c4_1 X138 | ~ bnd_c8_1 X138) |
% 7.31/6.88 (ALL X139.
% 7.31/6.88 bnd_ndr1_1 X138 -->
% 7.31/6.88 (bnd_c3_2 X138 X139 | bnd_c5_2 X138 X139) | ~ bnd_c1_2 X138 X139))) |
% 7.31/6.88 (ALL X140.
% 7.31/6.88 bnd_ndr1_0 -->
% 7.31/6.88 (~ bnd_c3_1 X140 | ~ bnd_c5_1 X140) |
% 7.31/6.88 ~ bnd_c9_1 X140))) &
% 7.31/6.88 (~ bnd_c7_0 |
% 7.31/6.88 (ALL X141.
% 7.31/6.88 bnd_ndr1_0 -->
% 7.31/6.88 (bnd_c8_1 X141 | ~ bnd_c9_1 X141) |
% 7.31/6.88 ((bnd_ndr1_1 X141 &
% 7.31/6.88 bnd_c1_2 X141 bnd_a354) &
% 7.31/6.88 bnd_c10_2 X141 bnd_a354) &
% 7.31/6.88 ~ bnd_c2_2 X141 bnd_a354))) &
% 7.31/6.88 ((~ bnd_c7_0 |
% 7.31/6.88 (((((bnd_ndr1_0 & bnd_c3_1 bnd_a355) &
% 7.31/6.88 (ALL X142.
% 7.31/6.88 bnd_ndr1_1 bnd_a355 -->
% 7.31/6.88 (~ bnd_c4_2 bnd_a355 X142 |
% 7.31/6.88 ~ bnd_c6_2 bnd_a355 X142) |
% 7.31/6.88 ~ bnd_c8_2 bnd_a355 X142)) &
% 7.31/6.88 bnd_ndr1_1 bnd_a355) &
% 7.31/6.88 ~ bnd_c10_2 bnd_a355 bnd_a356) &
% 7.31/6.88 ~ bnd_c7_2 bnd_a355 bnd_a356) &
% 7.31/6.88 ~ bnd_c9_2 bnd_a355 bnd_a356) |
% 7.31/6.88 ((bnd_ndr1_0 & bnd_c9_1 bnd_a357) &
% 7.31/6.88 (ALL X143.
% 7.31/6.88 bnd_ndr1_1 bnd_a357 -->
% 7.31/6.88 (bnd_c10_2 bnd_a357 X143 |
% 7.31/6.88 bnd_c4_2 bnd_a357 X143) |
% 7.31/6.88 ~ bnd_c9_2 bnd_a357 X143)) &
% 7.31/6.88 (ALL X144.
% 7.31/6.88 bnd_ndr1_1 bnd_a357 -->
% 7.31/6.88 (bnd_c4_2 bnd_a357 X144 |
% 7.31/6.88 bnd_c5_2 bnd_a357 X144) |
% 7.31/6.88 ~ bnd_c8_2 bnd_a357 X144))) &
% 7.31/6.88 ((~ bnd_c8_0 |
% 7.31/6.88 (ALL X145.
% 7.31/6.88 bnd_ndr1_0 -->
% 7.31/6.88 (bnd_c3_1 X145 | bnd_c9_1 X145) |
% 7.31/6.88 ((bnd_ndr1_1 X145 & bnd_c1_2 X145 bnd_a358) &
% 7.31/6.88 bnd_c8_2 X145 bnd_a358) &
% 7.31/6.88 ~ bnd_c3_2 X145 bnd_a358)) |
% 7.31/6.88 (ALL X146.
% 7.31/6.88 bnd_ndr1_0 -->
% 7.31/6.88 (bnd_c8_1 X146 |
% 7.31/6.88 (ALL X147.
% 7.31/6.88 bnd_ndr1_1 X146 -->
% 7.31/6.88 (bnd_c3_2 X146 X147 |
% 7.31/6.88 ~ bnd_c2_2 X146 X147) |
% 7.31/6.88 ~ bnd_c5_2 X146 X147)) |
% 7.31/6.88 ((bnd_ndr1_1 X146 &
% 7.31/6.88 ~ bnd_c10_2 X146 bnd_a359) &
% 7.31/6.88 ~ bnd_c2_2 X146 bnd_a359) &
% 7.31/6.88 ~ bnd_c6_2 X146 bnd_a359))) &
% 7.31/6.88 ((~ bnd_c9_0 |
% 7.31/6.88 (ALL X148.
% 7.31/6.88 bnd_ndr1_0 -->
% 7.31/6.88 (bnd_c1_1 X148 | ~ bnd_c10_1 X148) |
% 7.31/6.88 ((bnd_ndr1_1 X148 & bnd_c6_2 X148 bnd_a360) &
% 7.31/6.88 bnd_c9_2 X148 bnd_a360) &
% 7.31/6.88 ~ bnd_c10_2 X148 bnd_a360)) |
% 7.31/6.88 (ALL X149.
% 7.31/6.88 bnd_ndr1_0 -->
% 7.31/6.88 (~ bnd_c9_1 X149 |
% 7.31/6.88 (ALL X150.
% 7.31/6.88 bnd_ndr1_1 X149 -->
% 7.31/6.88 (bnd_c2_2 X149 X150 |
% 7.31/6.88 ~ bnd_c4_2 X149 X150) |
% 7.31/6.88 ~ bnd_c6_2 X149 X150)) |
% 7.31/6.88 ((bnd_ndr1_1 X149 & bnd_c9_2 X149 bnd_a361) &
% 7.31/6.88 ~ bnd_c2_2 X149 bnd_a361) &
% 7.31/6.88 ~ bnd_c8_2 X149 bnd_a361))) &
% 7.31/6.88 ((~ bnd_c9_0 |
% 7.31/6.88 (ALL X151.
% 7.31/6.88 bnd_ndr1_0 -->
% 7.31/6.88 (bnd_c3_1 X151 | ~ bnd_c5_1 X151) |
% 7.31/6.88 ~ bnd_c7_1 X151)) |
% 7.31/6.88 (((((bnd_ndr1_0 & bnd_c3_1 bnd_a362) &
% 7.31/6.88 ~ bnd_c8_1 bnd_a362) &
% 7.31/6.88 bnd_ndr1_1 bnd_a362) &
% 7.31/6.88 bnd_c3_2 bnd_a362 bnd_a363) &
% 7.31/6.88 ~ bnd_c1_2 bnd_a362 bnd_a363) &
% 7.31/6.88 ~ bnd_c4_2 bnd_a362 bnd_a363)) &
% 7.31/6.88 ((~ bnd_c9_0 |
% 7.31/6.88 (ALL X152.
% 7.31/6.88 bnd_ndr1_0 -->
% 7.31/6.88 (~ bnd_c2_1 X152 | ~ bnd_c5_1 X152) |
% 7.31/6.88 (ALL X153.
% 7.31/6.88 bnd_ndr1_1 X152 -->
% 7.31/6.88 ~ bnd_c4_2 X152 X153 |
% 7.31/6.88 ~ bnd_c5_2 X152 X153))) |
% 7.31/6.88 ((bnd_ndr1_0 & ~ bnd_c1_1 bnd_a364) &
% 7.31/6.88 (ALL X154.
% 7.31/6.88 bnd_ndr1_1 bnd_a364 -->
% 7.31/6.88 (bnd_c3_2 bnd_a364 X154 |
% 7.31/6.88 bnd_c8_2 bnd_a364 X154) |
% 7.31/6.88 ~ bnd_c4_2 bnd_a364 X154)) &
% 7.31/6.88 (ALL X155.
% 7.31/6.88 bnd_ndr1_1 bnd_a364 -->
% 7.31/6.88 (~ bnd_c10_2 bnd_a364 X155 |
% 7.31/6.88 ~ bnd_c6_2 bnd_a364 X155) |
% 7.31/6.88 ~ bnd_c8_2 bnd_a364 X155))) &
% 7.31/6.88 (~ bnd_c9_0 |
% 7.31/6.88 (ALL X156.
% 7.31/6.88 bnd_ndr1_0 -->
% 7.31/6.88 (~ bnd_c2_1 X156 |
% 7.31/6.88 ((bnd_ndr1_1 X156 & bnd_c2_2 X156 bnd_a365) &
% 7.31/6.88 bnd_c4_2 X156 bnd_a365) &
% 7.31/6.88 ~ bnd_c3_2 X156 bnd_a365) |
% 7.31/6.88 ((bnd_ndr1_1 X156 & ~ bnd_c1_2 X156 bnd_a366) &
% 7.31/6.88 ~ bnd_c7_2 X156 bnd_a366) &
% 7.31/6.88 ~ bnd_c9_2 X156 bnd_a366))) &
% 7.31/6.88 ((~ bnd_c9_0 |
% 7.31/6.88 (ALL X157.
% 7.31/6.88 bnd_ndr1_0 -->
% 7.31/6.88 ((ALL X158.
% 7.31/6.88 bnd_ndr1_1 X157 -->
% 7.31/6.88 (bnd_c7_2 X157 X158 | ~ bnd_c4_2 X157 X158) |
% 7.31/6.88 ~ bnd_c6_2 X157 X158) |
% 7.31/6.88 ((bnd_ndr1_1 X157 & ~ bnd_c1_2 X157 bnd_a367) &
% 7.31/6.88 ~ bnd_c2_2 X157 bnd_a367) &
% 7.31/6.88 ~ bnd_c6_2 X157 bnd_a367) |
% 7.31/6.88 ((bnd_ndr1_1 X157 & ~ bnd_c1_2 X157 bnd_a368) &
% 7.31/6.88 ~ bnd_c4_2 X157 bnd_a368) &
% 7.31/6.88 ~ bnd_c5_2 X157 bnd_a368)) |
% 7.31/6.88 (((((((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a369) &
% 7.31/6.88 bnd_c3_2 bnd_a369 bnd_a370) &
% 7.31/6.88 bnd_c8_2 bnd_a369 bnd_a370) &
% 7.31/6.88 ~ bnd_c9_2 bnd_a369 bnd_a370) &
% 7.31/6.88 bnd_ndr1_1 bnd_a369) &
% 7.31/6.88 bnd_c5_2 bnd_a369 bnd_a371) &
% 7.31/6.88 bnd_c7_2 bnd_a369 bnd_a371) &
% 7.31/6.88 ~ bnd_c9_2 bnd_a369 bnd_a371) &
% 7.31/6.88 bnd_ndr1_1 bnd_a369) &
% 7.31/6.88 bnd_c7_2 bnd_a369 bnd_a372) &
% 7.31/6.88 bnd_c9_2 bnd_a369 bnd_a372) &
% 7.31/6.88 ~ bnd_c4_2 bnd_a369 bnd_a372)) &
% 7.31/6.88 (((ALL X159.
% 7.31/6.88 bnd_ndr1_0 -->
% 7.31/6.88 (bnd_c1_1 X159 | ~ bnd_c8_1 X159) |
% 7.31/6.88 ((bnd_ndr1_1 X159 & bnd_c3_2 X159 bnd_a373) &
% 7.31/6.88 ~ bnd_c1_2 X159 bnd_a373) &
% 7.31/6.88 ~ bnd_c8_2 X159 bnd_a373) |
% 7.31/6.88 (((((bnd_ndr1_0 & bnd_c10_1 bnd_a374) &
% 7.31/6.88 bnd_c2_1 bnd_a374) &
% 7.31/6.88 bnd_ndr1_1 bnd_a374) &
% 7.31/6.88 bnd_c10_2 bnd_a374 bnd_a375) &
% 7.31/6.88 bnd_c3_2 bnd_a374 bnd_a375) &
% 7.31/6.88 ~ bnd_c9_2 bnd_a374 bnd_a375) |
% 7.31/6.88 ((bnd_ndr1_0 & bnd_c8_1 bnd_a376) &
% 7.31/6.88 ~ bnd_c6_1 bnd_a376) &
% 7.31/6.88 (ALL X160.
% 7.31/6.88 bnd_ndr1_1 bnd_a376 -->
% 7.31/6.88 (bnd_c2_2 bnd_a376 X160 |
% 7.31/6.88 ~ bnd_c3_2 bnd_a376 X160) |
% 7.31/6.88 ~ bnd_c5_2 bnd_a376 X160))) &
% 7.31/6.88 (((ALL X161.
% 7.31/6.88 bnd_ndr1_0 -->
% 7.31/6.88 (bnd_c10_1 X161 | ~ bnd_c6_1 X161) |
% 7.31/6.88 (ALL X162.
% 7.31/6.88 bnd_ndr1_1 X161 -->
% 7.31/6.88 (bnd_c10_2 X161 X162 | bnd_c6_2 X161 X162) |
% 7.31/6.88 ~ bnd_c2_2 X161 X162)) |
% 7.31/6.88 (ALL X163.
% 7.31/6.88 bnd_ndr1_0 -->
% 7.31/6.88 (~ bnd_c4_1 X163 |
% 7.31/6.88 (ALL X164.
% 7.31/6.88 bnd_ndr1_1 X163 -->
% 7.31/6.88 (bnd_c1_2 X163 X164 | bnd_c4_2 X163 X164) |
% 7.31/6.88 ~ bnd_c6_2 X163 X164)) |
% 7.31/6.88 (ALL X165.
% 7.31/6.88 bnd_ndr1_1 X163 -->
% 7.31/6.88 (bnd_c10_2 X163 X165 | bnd_c4_2 X163 X165) |
% 7.31/6.88 ~ bnd_c9_2 X163 X165))) |
% 7.31/6.88 (ALL X166.
% 7.31/6.88 bnd_ndr1_0 -->
% 7.31/6.88 (~ bnd_c5_1 X166 |
% 7.31/6.88 (ALL X167.
% 7.31/6.88 bnd_ndr1_1 X166 -->
% 7.31/6.88 (bnd_c3_2 X166 X167 | ~ bnd_c2_2 X166 X167) |
% 7.31/6.88 ~ bnd_c6_2 X166 X167)) |
% 7.31/6.88 (ALL X168.
% 7.31/6.88 bnd_ndr1_1 X166 -->
% 7.31/6.88 (bnd_c7_2 X166 X168 | bnd_c9_2 X166 X168) |
% 7.31/6.88 ~ bnd_c8_2 X166 X168)))) &
% 7.31/6.88 (((ALL X169.
% 7.31/6.88 bnd_ndr1_0 -->
% 7.31/6.88 (bnd_c2_1 X169 | ~ bnd_c4_1 X169) |
% 7.31/6.88 ((bnd_ndr1_1 X169 & bnd_c4_2 X169 bnd_a377) &
% 7.31/6.88 bnd_c5_2 X169 bnd_a377) &
% 7.31/6.88 bnd_c6_2 X169 bnd_a377) |
% 7.31/6.88 (ALL X170.
% 7.31/6.88 bnd_ndr1_0 -->
% 7.31/6.88 (bnd_c7_1 X170 | ~ bnd_c9_1 X170) |
% 7.31/6.88 (ALL X171.
% 7.31/6.88 bnd_ndr1_1 X170 -->
% 7.31/6.88 ~ bnd_c2_2 X170 X171 | ~ bnd_c9_2 X170 X171))) |
% 7.31/6.88 (ALL X172.
% 7.31/6.88 bnd_ndr1_0 -->
% 7.31/6.88 (~ bnd_c3_1 X172 |
% 7.31/6.88 ((bnd_ndr1_1 X172 & bnd_c2_2 X172 bnd_a378) &
% 7.31/6.88 bnd_c7_2 X172 bnd_a378) &
% 7.31/6.88 ~ bnd_c8_2 X172 bnd_a378) |
% 7.31/6.88 ((bnd_ndr1_1 X172 & bnd_c3_2 X172 bnd_a379) &
% 7.31/6.88 ~ bnd_c1_2 X172 bnd_a379) &
% 7.31/6.88 ~ bnd_c10_2 X172 bnd_a379))) &
% 7.31/6.88 (((ALL X173.
% 7.31/6.88 bnd_ndr1_0 -->
% 7.31/6.88 (bnd_c2_1 X173 | ~ bnd_c7_1 X173) |
% 7.31/6.88 (ALL X174.
% 7.31/6.88 bnd_ndr1_1 X173 -->
% 7.31/6.88 (bnd_c9_2 X173 X174 | ~ bnd_c3_2 X173 X174) |
% 7.31/6.88 ~ bnd_c8_2 X173 X174)) |
% 7.31/6.88 (((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a380) &
% 7.31/6.88 bnd_c1_2 bnd_a380 bnd_a381) &
% 7.31/6.88 bnd_c7_2 bnd_a380 bnd_a381) &
% 7.31/6.88 ~ bnd_c5_2 bnd_a380 bnd_a381) &
% 7.31/6.88 bnd_ndr1_1 bnd_a380) &
% 7.31/6.88 bnd_c7_2 bnd_a380 bnd_a382) &
% 7.31/6.88 ~ bnd_c1_2 bnd_a380 bnd_a382) &
% 7.31/6.88 ~ bnd_c8_2 bnd_a380 bnd_a382) |
% 7.31/6.88 ((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a383) &
% 7.31/6.88 ~ bnd_c1_2 bnd_a383 bnd_a384) &
% 7.31/6.88 ~ bnd_c6_2 bnd_a383 bnd_a384) &
% 7.31/6.88 bnd_ndr1_1 bnd_a383) &
% 7.31/6.88 ~ bnd_c10_2 bnd_a383 bnd_a385) &
% 7.31/6.88 ~ bnd_c3_2 bnd_a383 bnd_a385) &
% 7.31/6.88 ~ bnd_c5_2 bnd_a383 bnd_a385)) &
% 7.31/6.88 (((ALL X175.
% 7.31/6.88 bnd_ndr1_0 -->
% 7.31/6.88 (bnd_c3_1 X175 | bnd_c7_1 X175) |
% 7.31/6.88 ((bnd_ndr1_1 X175 & bnd_c6_2 X175 bnd_a386) &
% 7.31/6.88 ~ bnd_c7_2 X175 bnd_a386) &
% 7.31/6.88 ~ bnd_c8_2 X175 bnd_a386) |
% 7.31/6.88 (ALL X176.
% 7.31/6.88 bnd_ndr1_0 -->
% 7.31/6.88 (bnd_c3_1 X176 |
% 7.31/6.88 (ALL X177.
% 7.31/6.88 bnd_ndr1_1 X176 -->
% 7.31/6.88 (bnd_c3_2 X176 X177 | bnd_c8_2 X176 X177) |
% 7.31/6.88 ~ bnd_c7_2 X176 X177)) |
% 7.31/6.88 (ALL X178.
% 7.31/6.88 bnd_ndr1_1 X176 -->
% 7.31/6.88 (~ bnd_c10_2 X176 X178 | ~ bnd_c6_2 X176 X178) |
% 7.31/6.88 ~ bnd_c8_2 X176 X178))) |
% 7.31/6.88 ((((bnd_ndr1_0 &
% 7.31/6.88 (ALL X179.
% 7.31/6.88 bnd_ndr1_1 bnd_a387 -->
% 7.31/6.88 (bnd_c2_2 bnd_a387 X179 | bnd_c4_2 bnd_a387 X179) |
% 7.31/6.88 ~ bnd_c9_2 bnd_a387 X179)) &
% 7.31/6.88 bnd_ndr1_1 bnd_a387) &
% 7.31/6.88 bnd_c1_2 bnd_a387 bnd_a388) &
% 7.31/6.88 bnd_c6_2 bnd_a387 bnd_a388) &
% 7.31/6.88 bnd_c7_2 bnd_a387 bnd_a388)) &
% 7.31/6.88 (((ALL X180.
% 7.31/6.88 bnd_ndr1_0 -->
% 7.31/6.88 (bnd_c4_1 X180 | ~ bnd_c10_1 X180) | ~ bnd_c3_1 X180) |
% 7.31/6.88 (ALL X181.
% 7.31/6.88 bnd_ndr1_0 -->
% 7.31/6.88 (bnd_c6_1 X181 | bnd_c9_1 X181) |
% 7.31/6.88 (ALL X182.
% 7.31/6.88 bnd_ndr1_1 X181 -->
% 7.31/6.88 (bnd_c6_2 X181 X182 | bnd_c8_2 X181 X182) |
% 7.31/6.88 ~ bnd_c5_2 X181 X182))) |
% 7.31/6.88 ((((bnd_ndr1_0 & ~ bnd_c3_1 bnd_a389) &
% 7.31/6.88 (ALL X183.
% 7.31/6.88 bnd_ndr1_1 bnd_a389 -->
% 7.31/6.88 (bnd_c2_2 bnd_a389 X183 | bnd_c5_2 bnd_a389 X183) |
% 7.31/6.88 ~ bnd_c8_2 bnd_a389 X183)) &
% 7.31/6.88 bnd_ndr1_1 bnd_a389) &
% 7.31/6.88 bnd_c2_2 bnd_a389 bnd_a390) &
% 7.31/6.88 bnd_c4_2 bnd_a389 bnd_a390)) &
% 7.31/6.88 (((ALL X184.
% 7.31/6.88 bnd_ndr1_0 -->
% 7.31/6.88 (bnd_c5_1 X184 | ~ bnd_c1_1 X184) |
% 7.31/6.88 ((bnd_ndr1_1 X184 & bnd_c5_2 X184 bnd_a391) &
% 7.31/6.88 bnd_c7_2 X184 bnd_a391) &
% 7.31/6.88 ~ bnd_c6_2 X184 bnd_a391) |
% 7.31/6.88 (ALL X185.
% 7.31/6.88 bnd_ndr1_0 -->
% 7.31/6.88 (~ bnd_c7_1 X185 |
% 7.31/6.88 (ALL X186.
% 7.31/6.88 bnd_ndr1_1 X185 -->
% 7.31/6.88 (bnd_c2_2 X185 X186 | bnd_c7_2 X185 X186) |
% 7.31/6.88 ~ bnd_c6_2 X185 X186)) |
% 7.31/6.88 ((bnd_ndr1_1 X185 & bnd_c2_2 X185 bnd_a392) &
% 7.31/6.88 bnd_c3_2 X185 bnd_a392) &
% 7.31/6.88 ~ bnd_c9_2 X185 bnd_a392)) |
% 7.31/6.88 (ALL X187.
% 7.31/6.88 bnd_ndr1_0 -->
% 7.31/6.88 (~ bnd_c9_1 X187 |
% 7.31/6.88 ((bnd_ndr1_1 X187 & bnd_c1_2 X187 bnd_a393) &
% 7.31/6.88 bnd_c7_2 X187 bnd_a393) &
% 7.31/6.88 ~ bnd_c3_2 X187 bnd_a393) |
% 7.31/6.88 (bnd_ndr1_1 X187 & bnd_c1_2 X187 bnd_a394) &
% 7.31/6.88 ~ bnd_c9_2 X187 bnd_a394))) &
% 7.31/6.88 (((ALL X188.
% 7.31/6.88 bnd_ndr1_0 -->
% 7.31/6.88 (bnd_c5_1 X188 | ~ bnd_c9_1 X188) |
% 7.31/6.88 ((bnd_ndr1_1 X188 & bnd_c10_2 X188 bnd_a395) &
% 7.31/6.88 bnd_c3_2 X188 bnd_a395) &
% 7.31/6.88 ~ bnd_c9_2 X188 bnd_a395) |
% 7.31/6.88 (ALL X189.
% 7.31/6.88 bnd_ndr1_0 -->
% 7.31/6.88 (~ bnd_c8_1 X189 |
% 7.31/6.88 (ALL X190.
% 7.31/6.88 bnd_ndr1_1 X189 -->
% 7.31/6.88 bnd_c6_2 X189 X190 | ~ bnd_c7_2 X189 X190)) |
% 7.31/6.88 ((bnd_ndr1_1 X189 & bnd_c2_2 X189 bnd_a396) &
% 7.31/6.88 bnd_c6_2 X189 bnd_a396) &
% 7.31/6.88 ~ bnd_c8_2 X189 bnd_a396)) |
% 7.31/6.88 ((((((((bnd_ndr1_0 & ~ bnd_c8_1 bnd_a397) &
% 7.31/6.88 bnd_ndr1_1 bnd_a397) &
% 7.31/6.88 bnd_c10_2 bnd_a397 bnd_a398) &
% 7.31/6.88 bnd_c4_2 bnd_a397 bnd_a398) &
% 7.31/6.88 ~ bnd_c6_2 bnd_a397 bnd_a398) &
% 7.31/6.88 bnd_ndr1_1 bnd_a397) &
% 7.31/6.88 bnd_c8_2 bnd_a397 bnd_a399) &
% 7.31/6.88 ~ bnd_c1_2 bnd_a397 bnd_a399) &
% 7.31/6.88 ~ bnd_c10_2 bnd_a397 bnd_a399)) &
% 7.31/6.88 (((ALL X191.
% 7.31/6.88 bnd_ndr1_0 -->
% 7.31/6.88 (bnd_c6_1 X191 | bnd_c8_1 X191) | ~ bnd_c4_1 X191) |
% 7.31/6.88 ((bnd_ndr1_0 & ~ bnd_c3_1 bnd_a400) &
% 7.31/6.88 (ALL X192.
% 7.31/6.88 bnd_ndr1_1 bnd_a400 -->
% 7.31/6.88 (bnd_c1_2 bnd_a400 X192 | bnd_c10_2 bnd_a400 X192) |
% 7.31/6.88 ~ bnd_c3_2 bnd_a400 X192)) &
% 7.31/6.88 (ALL X193.
% 7.31/6.88 bnd_ndr1_1 bnd_a400 -->
% 7.31/6.88 (~ bnd_c1_2 bnd_a400 X193 | ~ bnd_c7_2 bnd_a400 X193) |
% 7.31/6.88 ~ bnd_c9_2 bnd_a400 X193)) |
% 7.31/6.88 ((bnd_ndr1_0 &
% 7.31/6.88 (ALL X194.
% 7.31/6.88 bnd_ndr1_1 bnd_a401 -->
% 7.31/6.88 bnd_c5_2 bnd_a401 X194 | ~ bnd_c8_2 bnd_a401 X194)) &
% 7.31/6.88 (ALL X195.
% 7.31/6.88 bnd_ndr1_1 bnd_a401 -->
% 7.31/6.88 (bnd_c8_2 bnd_a401 X195 | ~ bnd_c2_2 bnd_a401 X195) |
% 7.31/6.88 ~ bnd_c4_2 bnd_a401 X195)) &
% 7.31/6.88 (ALL X196.
% 7.31/6.88 bnd_ndr1_1 bnd_a401 -->
% 7.31/6.88 (~ bnd_c1_2 bnd_a401 X196 | ~ bnd_c10_2 bnd_a401 X196) |
% 7.31/6.88 ~ bnd_c2_2 bnd_a401 X196))) &
% 7.31/6.88 ((ALL X197.
% 7.31/6.88 bnd_ndr1_0 -->
% 7.31/6.88 bnd_c8_1 X197 |
% 7.31/6.88 ((bnd_ndr1_1 X197 & bnd_c2_2 X197 bnd_a402) &
% 7.31/6.88 ~ bnd_c1_2 X197 bnd_a402) &
% 7.31/6.88 ~ bnd_c3_2 X197 bnd_a402) |
% 7.31/6.88 (((((bnd_ndr1_0 & bnd_c2_1 bnd_a403) & ~ bnd_c4_1 bnd_a403) &
% 7.31/6.88 bnd_ndr1_1 bnd_a403) &
% 7.31/6.88 bnd_c10_2 bnd_a403 bnd_a404) &
% 7.31/6.88 bnd_c5_2 bnd_a403 bnd_a404) &
% 7.31/6.88 bnd_c8_2 bnd_a403 bnd_a404)) &
% 7.31/6.88 (((ALL X198.
% 7.31/6.88 bnd_ndr1_0 -->
% 7.31/6.88 (bnd_c9_1 X198 | ~ bnd_c2_1 X198) |
% 7.31/6.88 (bnd_ndr1_1 X198 & bnd_c4_2 X198 bnd_a405) &
% 7.31/6.88 ~ bnd_c5_2 X198 bnd_a405) |
% 7.31/6.88 (((((bnd_ndr1_0 & bnd_c4_1 bnd_a406) & bnd_c9_1 bnd_a406) &
% 7.31/6.88 bnd_ndr1_1 bnd_a406) &
% 7.31/6.88 ~ bnd_c2_2 bnd_a406 bnd_a407) &
% 7.31/6.88 ~ bnd_c7_2 bnd_a406 bnd_a407) &
% 7.31/6.88 ~ bnd_c8_2 bnd_a406 bnd_a407) |
% 7.31/6.88 (((((bnd_ndr1_0 & ~ bnd_c2_1 bnd_a408) &
% 7.31/6.88 (ALL X199.
% 7.31/6.88 bnd_ndr1_1 bnd_a408 -->
% 7.31/6.88 (bnd_c8_2 bnd_a408 X199 | bnd_c9_2 bnd_a408 X199) |
% 7.31/6.88 ~ bnd_c4_2 bnd_a408 X199)) &
% 7.31/6.88 bnd_ndr1_1 bnd_a408) &
% 7.31/6.88 bnd_c1_2 bnd_a408 bnd_a409) &
% 7.31/6.88 bnd_c4_2 bnd_a408 bnd_a409) &
% 7.31/6.88 ~ bnd_c5_2 bnd_a408 bnd_a409)) &
% 7.31/6.88 (((ALL X200.
% 7.31/6.88 bnd_ndr1_0 -->
% 7.31/6.88 (bnd_c9_1 X200 |
% 7.31/6.88 (ALL X201.
% 7.31/6.88 bnd_ndr1_1 X200 -->
% 7.31/6.88 bnd_c3_2 X200 X201 | bnd_c6_2 X200 X201)) |
% 7.31/6.88 ((bnd_ndr1_1 X200 & bnd_c1_2 X200 bnd_a410) &
% 7.31/6.88 bnd_c5_2 X200 bnd_a410) &
% 7.31/6.88 bnd_c6_2 X200 bnd_a410) |
% 7.31/6.88 (ALL X202.
% 7.31/6.88 bnd_ndr1_0 -->
% 7.31/6.88 (~ bnd_c3_1 X202 | ~ bnd_c7_1 X202) | ~ bnd_c8_1 X202)) |
% 7.31/6.88 (((((((bnd_ndr1_0 &
% 7.31/6.88 (ALL X203.
% 7.31/6.88 bnd_ndr1_1 bnd_a411 -->
% 7.31/6.88 (bnd_c3_2 bnd_a411 X203 | bnd_c8_2 bnd_a411 X203) |
% 7.31/6.88 ~ bnd_c2_2 bnd_a411 X203)) &
% 7.31/6.88 bnd_ndr1_1 bnd_a411) &
% 7.31/6.88 bnd_c3_2 bnd_a411 bnd_a412) &
% 7.31/6.88 ~ bnd_c6_2 bnd_a411 bnd_a412) &
% 7.31/6.88 bnd_ndr1_1 bnd_a411) &
% 7.31/6.88 ~ bnd_c4_2 bnd_a411 bnd_a413) &
% 7.31/6.88 ~ bnd_c8_2 bnd_a411 bnd_a413) &
% 7.31/6.88 ~ bnd_c9_2 bnd_a411 bnd_a413)) &
% 7.31/6.88 ((ALL X204.
% 7.31/6.88 bnd_ndr1_0 -->
% 7.31/6.88 (~ bnd_c1_1 X204 | ~ bnd_c5_1 X204) | ~ bnd_c8_1 X204) |
% 7.31/6.88 (((((bnd_ndr1_0 & bnd_c10_1 bnd_a414) & bnd_c9_1 bnd_a414) &
% 7.31/6.88 bnd_ndr1_1 bnd_a414) &
% 7.31/6.88 ~ bnd_c10_2 bnd_a414 bnd_a415) &
% 7.31/6.88 ~ bnd_c4_2 bnd_a414 bnd_a415) &
% 7.31/6.88 ~ bnd_c7_2 bnd_a414 bnd_a415)) &
% 7.31/6.88 (((ALL X205.
% 7.31/6.88 bnd_ndr1_0 -->
% 7.31/6.88 (~ bnd_c1_1 X205 | ~ bnd_c5_1 X205) |
% 7.31/6.88 (bnd_ndr1_1 X205 & bnd_c9_2 X205 bnd_a416) &
% 7.31/6.88 ~ bnd_c6_2 X205 bnd_a416) |
% 7.31/6.88 ((bnd_ndr1_0 & bnd_c2_1 bnd_a417) & bnd_c3_1 bnd_a417) &
% 7.31/6.88 bnd_c5_1 bnd_a417) |
% 7.31/6.88 (((((bnd_ndr1_0 & bnd_c7_1 bnd_a418) & bnd_c8_1 bnd_a418) &
% 7.31/6.88 bnd_ndr1_1 bnd_a418) &
% 7.31/6.88 bnd_c10_2 bnd_a418 bnd_a419) &
% 7.31/6.88 bnd_c5_2 bnd_a418 bnd_a419) &
% 7.31/6.88 ~ bnd_c4_2 bnd_a418 bnd_a419)) &
% 7.31/6.88 (((ALL X206.
% 7.31/6.88 bnd_ndr1_0 -->
% 7.31/6.88 (~ bnd_c2_1 X206 | ~ bnd_c6_1 X206) |
% 7.31/6.88 (ALL X207.
% 7.31/6.88 bnd_ndr1_1 X206 -->
% 7.31/6.88 (bnd_c1_2 X206 X207 | bnd_c4_2 X206 X207) |
% 7.31/6.88 bnd_c5_2 X206 X207)) |
% 7.31/6.88 ((((bnd_ndr1_0 & bnd_c1_1 bnd_a420) & bnd_c5_1 bnd_a420) &
% 7.31/6.88 bnd_ndr1_1 bnd_a420) &
% 7.31/6.88 ~ bnd_c1_2 bnd_a420 bnd_a421) &
% 7.31/6.88 ~ bnd_c8_2 bnd_a420 bnd_a421) |
% 7.31/6.88 ((bnd_ndr1_0 & ~ bnd_c1_1 bnd_a422) & ~ bnd_c10_1 bnd_a422) &
% 7.31/6.88 (ALL X208.
% 7.31/6.88 bnd_ndr1_1 bnd_a422 -->
% 7.31/6.88 (bnd_c3_2 bnd_a422 X208 | bnd_c4_2 bnd_a422 X208) |
% 7.31/6.88 ~ bnd_c6_2 bnd_a422 X208))) &
% 7.31/6.88 ((((bnd_ndr1_0 & bnd_c10_1 bnd_a423) & ~ bnd_c5_1 bnd_a423) &
% 7.31/6.88 ~ bnd_c6_1 bnd_a423 |
% 7.31/6.88 ((bnd_ndr1_0 & bnd_c5_1 bnd_a424) &
% 7.31/6.88 (ALL X209.
% 7.31/6.88 bnd_ndr1_1 bnd_a424 -->
% 7.31/6.88 (~ bnd_c1_2 bnd_a424 X209 | ~ bnd_c2_2 bnd_a424 X209) |
% 7.31/6.88 ~ bnd_c5_2 bnd_a424 X209)) &
% 7.31/6.88 (ALL X210.
% 7.31/6.88 bnd_ndr1_1 bnd_a424 -->
% 7.31/6.88 (~ bnd_c3_2 bnd_a424 X210 | ~ bnd_c6_2 bnd_a424 X210) |
% 7.31/6.88 ~ bnd_c8_2 bnd_a424 X210)) |
% 7.31/6.88 ((((bnd_ndr1_0 & bnd_c7_1 bnd_a425) & ~ bnd_c8_1 bnd_a425) &
% 7.31/6.88 bnd_ndr1_1 bnd_a425) &
% 7.31/6.88 bnd_c5_2 bnd_a425 bnd_a426) &
% 7.31/6.88 bnd_c6_2 bnd_a425 bnd_a426)) &
% 7.31/6.88 (((((bnd_ndr1_0 & bnd_c10_1 bnd_a427) & bnd_ndr1_1 bnd_a427) &
% 7.31/6.88 bnd_c9_2 bnd_a427 bnd_a428) &
% 7.31/6.88 ~ bnd_c10_2 bnd_a427 bnd_a428) &
% 7.31/6.88 ~ bnd_c7_2 bnd_a427 bnd_a428 |
% 7.31/6.88 (((((bnd_ndr1_0 & bnd_c2_1 bnd_a429) & ~ bnd_c8_1 bnd_a429) &
% 7.31/6.88 bnd_ndr1_1 bnd_a429) &
% 7.31/6.88 bnd_c1_2 bnd_a429 bnd_a430) &
% 7.31/6.88 bnd_c2_2 bnd_a429 bnd_a430) &
% 7.31/6.88 bnd_c5_2 bnd_a429 bnd_a430))
% 19.04/18.60 Unfolded term: ~ ((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((~ bnd_c5_0 &
% 19.04/18.60 ((bnd_c1_0 | bnd_c3_0) |
% 19.04/18.60 (bnd_ndr1_0 & bnd_c3_1 bnd_a218) & ~ bnd_c7_1 bnd_a218)) &
% 19.04/18.60 ((bnd_c1_0 | bnd_c4_0) | bnd_c8_0)) &
% 19.04/18.60 ((bnd_c1_0 | bnd_c8_0) | ~ bnd_c4_0)) &
% 19.04/18.60 ((bnd_c1_0 | ~ bnd_c10_0) |
% 19.04/18.60 (((((((bnd_ndr1_0 &
% 19.04/18.60 (ALL U.
% 19.04/18.60 bnd_ndr1_1 bnd_a219 -->
% 19.04/18.60 (bnd_c3_2 bnd_a219 U | ~ bnd_c10_2 bnd_a219 U) |
% 19.04/18.60 ~ bnd_c5_2 bnd_a219 U)) &
% 19.04/18.60 bnd_ndr1_1 bnd_a219) &
% 19.04/18.60 bnd_c2_2 bnd_a219 bnd_a220) &
% 19.04/18.60 ~ bnd_c1_2 bnd_a219 bnd_a220) &
% 19.04/18.60 ~ bnd_c3_2 bnd_a219 bnd_a220) &
% 19.04/18.60 bnd_ndr1_1 bnd_a219) &
% 19.04/18.60 bnd_c6_2 bnd_a219 bnd_a221) &
% 19.04/18.60 bnd_c7_2 bnd_a219 bnd_a221)) &
% 19.04/18.60 ((bnd_c1_0 | ~ bnd_c9_0) |
% 19.04/18.60 (ALL V.
% 19.04/18.60 bnd_ndr1_0 -->
% 19.04/18.60 (bnd_c1_1 V |
% 19.04/18.60 (ALL W.
% 19.04/18.60 bnd_ndr1_1 V -->
% 19.04/18.60 (bnd_c1_2 V W | bnd_c8_2 V W) | ~ bnd_c3_2 V W)) |
% 19.04/18.60 (ALL X.
% 19.04/18.60 bnd_ndr1_1 V -->
% 19.04/18.60 (bnd_c8_2 V X | ~ bnd_c3_2 V X) | ~ bnd_c5_2 V X)))) &
% 19.04/18.60 ((bnd_c10_0 | ~ bnd_c7_0) |
% 19.04/18.60 ((bnd_ndr1_0 & ~ bnd_c1_1 bnd_a222) & ~ bnd_c7_1 bnd_a222) &
% 19.04/18.60 (ALL Y.
% 19.04/18.60 bnd_ndr1_1 bnd_a222 -->
% 19.04/18.60 (bnd_c3_2 bnd_a222 Y | ~ bnd_c1_2 bnd_a222 Y) |
% 19.04/18.60 ~ bnd_c2_2 bnd_a222 Y))) &
% 19.04/18.60 ((bnd_c10_0 |
% 19.04/18.60 (ALL Z. bnd_ndr1_0 --> (bnd_c1_1 Z | bnd_c9_1 Z) | ~ bnd_c7_1 Z)) |
% 19.04/18.60 (((((bnd_ndr1_0 & ~ bnd_c7_1 bnd_a223) &
% 19.04/18.60 (ALL X1.
% 19.04/18.60 bnd_ndr1_1 bnd_a223 -->
% 19.04/18.60 (~ bnd_c1_2 bnd_a223 X1 | ~ bnd_c7_2 bnd_a223 X1) |
% 19.04/18.60 ~ bnd_c8_2 bnd_a223 X1)) &
% 19.04/18.60 bnd_ndr1_1 bnd_a223) &
% 19.04/18.60 bnd_c9_2 bnd_a223 bnd_a224) &
% 19.04/18.60 ~ bnd_c1_2 bnd_a223 bnd_a224) &
% 19.04/18.60 ~ bnd_c10_2 bnd_a223 bnd_a224)) &
% 19.04/18.60 ((bnd_c10_0 |
% 19.04/18.60 (ALL X2.
% 19.04/18.60 bnd_ndr1_0 -->
% 19.04/18.60 (~ bnd_c5_1 X2 |
% 19.04/18.60 ((bnd_ndr1_1 X2 & bnd_c6_2 X2 bnd_a225) & bnd_c7_2 X2 bnd_a225) &
% 19.04/18.60 ~ bnd_c3_2 X2 bnd_a225) |
% 19.04/18.60 ((bnd_ndr1_1 X2 & bnd_c6_2 X2 bnd_a226) & ~ bnd_c4_2 X2 bnd_a226) &
% 19.04/18.60 ~ bnd_c7_2 X2 bnd_a226)) |
% 19.04/18.60 ((bnd_ndr1_0 & bnd_c9_1 bnd_a227) & ~ bnd_c1_1 bnd_a227) &
% 19.04/18.60 ~ bnd_c10_1 bnd_a227)) &
% 19.04/18.60 ((bnd_c10_0 |
% 19.04/18.60 (ALL X3.
% 19.04/18.60 bnd_ndr1_0 -->
% 19.04/18.60 (~ bnd_c8_1 X3 |
% 19.04/18.60 (ALL X4. bnd_ndr1_1 X3 --> bnd_c6_2 X3 X4 | ~ bnd_c8_2 X3 X4)) |
% 19.04/18.60 ((bnd_ndr1_1 X3 & bnd_c3_2 X3 bnd_a228) & bnd_c4_2 X3 bnd_a228) &
% 19.04/18.60 ~ bnd_c7_2 X3 bnd_a228)) |
% 19.04/18.60 (((((bnd_ndr1_0 & ~ bnd_c4_1 bnd_a229) &
% 19.04/18.60 (ALL X5.
% 19.04/18.60 bnd_ndr1_1 bnd_a229 -->
% 19.04/18.60 (bnd_c2_2 bnd_a229 X5 | bnd_c4_2 bnd_a229 X5) |
% 19.04/18.60 bnd_c7_2 bnd_a229 X5)) &
% 19.04/18.60 bnd_ndr1_1 bnd_a229) &
% 19.04/18.60 bnd_c1_2 bnd_a229 bnd_a230) &
% 19.04/18.60 bnd_c7_2 bnd_a229 bnd_a230) &
% 19.04/18.60 ~ bnd_c6_2 bnd_a229 bnd_a230)) &
% 19.04/18.60 ((bnd_c2_0 | bnd_c3_0) | bnd_c9_0)) &
% 19.04/18.60 ((bnd_c2_0 | bnd_c3_0) | ~ bnd_c10_0)) &
% 19.04/18.60 ((bnd_c2_0 | bnd_c3_0) | ~ bnd_c8_0)) &
% 19.04/18.60 (bnd_c2_0 |
% 19.04/18.60 (ALL X6.
% 19.04/18.60 bnd_ndr1_0 --> bnd_c9_1 X6 | ~ bnd_c3_1 X6))) &
% 19.04/18.60 ((bnd_c2_0 | ~ bnd_c3_0) |
% 19.04/18.60 (ALL X7.
% 19.04/18.60 bnd_ndr1_0 -->
% 19.04/18.60 (((bnd_ndr1_1 X7 & bnd_c10_2 X7 bnd_a231) & bnd_c8_2 X7 bnd_a231) &
% 19.04/18.60 ~ bnd_c9_2 X7 bnd_a231 |
% 19.04/18.60 ((bnd_ndr1_1 X7 & bnd_c4_2 X7 bnd_a232) & bnd_c8_2 X7 bnd_a232) &
% 19.04/18.60 ~ bnd_c2_2 X7 bnd_a232) |
% 19.04/18.60 ((bnd_ndr1_1 X7 & bnd_c6_2 X7 bnd_a233) & ~ bnd_c10_2 X7 bnd_a233) &
% 19.04/18.60 ~ bnd_c8_2 X7 bnd_a233))) &
% 19.04/18.60 ((bnd_c2_0 |
% 19.04/18.60 (ALL X8.
% 19.04/18.60 bnd_ndr1_0 -->
% 19.04/18.60 (bnd_c6_1 X8 | bnd_c7_1 X8) |
% 19.04/18.60 (ALL X9.
% 19.04/18.60 bnd_ndr1_1 X8 -->
% 19.04/18.60 (bnd_c7_2 X8 X9 | ~ bnd_c3_2 X8 X9) | ~ bnd_c8_2 X8 X9))) |
% 19.04/18.60 ((bnd_ndr1_0 & bnd_c6_1 bnd_a234) &
% 19.04/18.60 (ALL X10.
% 19.04/18.60 bnd_ndr1_1 bnd_a234 -->
% 19.04/18.60 (bnd_c1_2 bnd_a234 X10 | ~ bnd_c2_2 bnd_a234 X10) |
% 19.04/18.60 ~ bnd_c4_2 bnd_a234 X10)) &
% 19.04/18.60 (ALL X11.
% 19.04/18.60 bnd_ndr1_1 bnd_a234 -->
% 19.04/18.60 (bnd_c10_2 bnd_a234 X11 | bnd_c4_2 bnd_a234 X11) |
% 19.04/18.60 ~ bnd_c6_2 bnd_a234 X11))) &
% 19.04/18.60 ((bnd_c2_0 |
% 19.04/18.60 (ALL X12.
% 19.04/18.60 bnd_ndr1_0 -->
% 19.04/18.60 (~ bnd_c5_1 X12 |
% 19.04/18.60 (ALL X13.
% 19.04/18.60 bnd_ndr1_1 X12 -->
% 19.04/18.60 (bnd_c3_2 X12 X13 | bnd_c5_2 X12 X13) | ~ bnd_c10_2 X12 X13)) |
% 19.04/18.60 (ALL X14.
% 19.04/18.60 bnd_ndr1_1 X12 -->
% 19.04/18.60 (bnd_c3_2 X12 X14 | bnd_c7_2 X12 X14) | ~ bnd_c9_2 X12 X14))) |
% 19.04/18.60 (((((bnd_ndr1_0 & bnd_c9_1 bnd_a235) &
% 19.04/18.60 ~ bnd_c5_1 bnd_a235) &
% 19.04/18.60 bnd_ndr1_1 bnd_a235) &
% 19.04/18.60 bnd_c4_2 bnd_a235 bnd_a236) &
% 19.04/18.60 bnd_c7_2 bnd_a235 bnd_a236) &
% 19.04/18.60 ~ bnd_c9_2 bnd_a235 bnd_a236)) &
% 19.04/18.60 ((bnd_c2_0 |
% 19.04/18.60 (ALL X15.
% 19.04/18.60 bnd_ndr1_0 -->
% 19.04/18.60 (ALL X16.
% 19.04/18.60 bnd_ndr1_1 X15 -->
% 19.04/18.60 (bnd_c2_2 X15 X16 | bnd_c7_2 X15 X16) | ~ bnd_c8_2 X15 X16) |
% 19.04/18.60 (ALL X17.
% 19.04/18.60 bnd_ndr1_1 X15 -->
% 19.04/18.60 (bnd_c2_2 X15 X17 | bnd_c8_2 X15 X17) | ~ bnd_c5_2 X15 X17))) |
% 19.04/18.60 (((((bnd_ndr1_0 & bnd_c9_1 bnd_a237) &
% 19.04/18.60 ~ bnd_c4_1 bnd_a237) &
% 19.04/18.60 bnd_ndr1_1 bnd_a237) &
% 19.04/18.60 bnd_c10_2 bnd_a237 bnd_a238) &
% 19.04/18.60 ~ bnd_c5_2 bnd_a237 bnd_a238) &
% 19.04/18.60 ~ bnd_c7_2 bnd_a237 bnd_a238)) &
% 19.04/18.60 (bnd_c2_0 |
% 19.04/18.60 ((((bnd_ndr1_0 & bnd_c2_1 bnd_a239) &
% 19.04/18.60 bnd_ndr1_1 bnd_a239) &
% 19.04/18.60 bnd_c9_2 bnd_a239 bnd_a240) &
% 19.04/18.60 ~ bnd_c4_2 bnd_a239 bnd_a240) &
% 19.04/18.60 ~ bnd_c8_2 bnd_a239 bnd_a240)) &
% 19.04/18.60 ((bnd_c2_0 |
% 19.04/18.60 ((bnd_ndr1_0 & bnd_c7_1 bnd_a241) &
% 19.04/18.60 ~ bnd_c10_1 bnd_a241) &
% 19.04/18.60 ~ bnd_c9_1 bnd_a241) |
% 19.04/18.60 ((bnd_ndr1_0 &
% 19.04/18.60 (ALL X18.
% 19.04/18.60 bnd_ndr1_1 bnd_a242 -->
% 19.04/18.60 (bnd_c10_2 bnd_a242 X18 |
% 19.04/18.60 bnd_c9_2 bnd_a242 X18) |
% 19.04/18.60 ~ bnd_c2_2 bnd_a242 X18)) &
% 19.04/18.60 (ALL X19.
% 19.04/18.60 bnd_ndr1_1 bnd_a242 -->
% 19.04/18.60 (bnd_c10_2 bnd_a242 X19 |
% 19.04/18.60 ~ bnd_c1_2 bnd_a242 X19) |
% 19.04/18.60 ~ bnd_c2_2 bnd_a242 X19)) &
% 19.04/18.60 (ALL X20.
% 19.04/18.60 bnd_ndr1_1 bnd_a242 -->
% 19.04/18.60 (bnd_c8_2 bnd_a242 X20 |
% 19.04/18.60 ~ bnd_c1_2 bnd_a242 X20) |
% 19.04/18.60 ~ bnd_c5_2 bnd_a242 X20))) &
% 19.04/18.60 ((bnd_c3_0 | bnd_c4_0) |
% 19.04/18.60 (ALL X21.
% 19.04/18.60 bnd_ndr1_0 -->
% 19.04/18.60 bnd_c2_1 X21 |
% 19.04/18.60 ((bnd_ndr1_1 X21 &
% 19.04/18.60 bnd_c2_2 X21 bnd_a243) &
% 19.04/18.60 ~ bnd_c3_2 X21 bnd_a243) &
% 19.04/18.60 ~ bnd_c8_2 X21 bnd_a243))) &
% 19.04/18.60 ((bnd_c3_0 | bnd_c7_0) |
% 19.04/18.60 ((bnd_ndr1_0 & bnd_c7_1 bnd_a244) &
% 19.04/18.60 (ALL X22.
% 19.04/18.60 bnd_ndr1_1 bnd_a244 -->
% 19.04/18.60 (bnd_c2_2 bnd_a244 X22 |
% 19.04/18.60 ~ bnd_c1_2 bnd_a244 X22) |
% 19.04/18.60 ~ bnd_c10_2 bnd_a244 X22)) &
% 19.04/18.60 (ALL X23.
% 19.04/18.60 bnd_ndr1_1 bnd_a244 -->
% 19.04/18.60 (bnd_c6_2 bnd_a244 X23 |
% 19.04/18.60 ~ bnd_c7_2 bnd_a244 X23) |
% 19.04/18.60 ~ bnd_c8_2 bnd_a244 X23))) &
% 19.04/18.60 ((bnd_c3_0 | bnd_c8_0) | bnd_c9_0)) &
% 19.04/18.60 ((bnd_c3_0 | bnd_c8_0) |
% 19.04/18.60 ((((bnd_ndr1_0 & bnd_c9_1 bnd_a245) &
% 19.04/18.60 bnd_ndr1_1 bnd_a245) &
% 19.04/18.60 bnd_c5_2 bnd_a245 bnd_a246) &
% 19.04/18.60 bnd_c7_2 bnd_a245 bnd_a246) &
% 19.04/18.60 ~ bnd_c9_2 bnd_a245 bnd_a246)) &
% 19.04/18.60 ((bnd_c3_0 | ~ bnd_c4_0) | ~ bnd_c7_0)) &
% 19.04/18.60 ((bnd_c3_0 | ~ bnd_c9_0) |
% 19.04/18.60 (ALL X24.
% 19.04/18.60 bnd_ndr1_0 -->
% 19.04/18.60 (~ bnd_c3_1 X24 | ~ bnd_c4_1 X24) |
% 19.04/18.60 (ALL X25.
% 19.04/18.60 bnd_ndr1_1 X24 -->
% 19.04/18.60 (bnd_c4_2 X24 X25 | ~ bnd_c10_2 X24 X25) |
% 19.04/18.60 ~ bnd_c9_2 X24 X25)))) &
% 19.04/18.60 (bnd_c4_0 |
% 19.04/18.60 ((((((((bnd_ndr1_0 &
% 19.04/18.60 (ALL X26.
% 19.04/18.60 bnd_ndr1_1 bnd_a247 -->
% 19.04/18.60 (bnd_c9_2 bnd_a247 X26 |
% 19.04/18.60 ~ bnd_c3_2 bnd_a247 X26) |
% 19.04/18.60 ~ bnd_c6_2 bnd_a247 X26)) &
% 19.04/18.60 bnd_ndr1_1 bnd_a247) &
% 19.04/18.60 bnd_c10_2 bnd_a247 bnd_a248) &
% 19.04/18.60 bnd_c9_2 bnd_a247 bnd_a248) &
% 19.04/18.60 ~ bnd_c1_2 bnd_a247 bnd_a248) &
% 19.04/18.60 bnd_ndr1_1 bnd_a247) &
% 19.04/18.60 bnd_c2_2 bnd_a247 bnd_a249) &
% 19.04/18.60 bnd_c9_2 bnd_a247 bnd_a249) &
% 19.04/18.60 ~ bnd_c10_2 bnd_a247 bnd_a249)) &
% 19.04/18.60 ((bnd_c4_0 | bnd_c6_0) | bnd_c8_0)) &
% 19.04/18.60 ((bnd_c4_0 | bnd_c9_0) |
% 19.04/18.60 bnd_ndr1_0 & ~ bnd_c7_1 bnd_a250)) &
% 19.04/18.60 ((bnd_c4_0 | ~ bnd_c1_0) |
% 19.04/18.60 (ALL X27.
% 19.04/18.60 bnd_ndr1_0 -->
% 19.04/18.60 (bnd_c5_1 X27 | ~ bnd_c6_1 X27) |
% 19.04/18.60 ((bnd_ndr1_1 X27 & bnd_c10_2 X27 bnd_a251) &
% 19.04/18.60 bnd_c8_2 X27 bnd_a251) &
% 19.04/18.60 ~ bnd_c1_2 X27 bnd_a251))) &
% 19.04/18.60 ((bnd_c4_0 | ~ bnd_c10_0) |
% 19.04/18.60 (((((bnd_ndr1_0 & bnd_c1_1 bnd_a252) &
% 19.04/18.60 bnd_c6_1 bnd_a252) &
% 19.04/18.60 bnd_ndr1_1 bnd_a252) &
% 19.04/18.60 bnd_c8_2 bnd_a252 bnd_a253) &
% 19.04/18.60 ~ bnd_c1_2 bnd_a252 bnd_a253) &
% 19.04/18.60 ~ bnd_c2_2 bnd_a252 bnd_a253)) &
% 19.04/18.60 ((bnd_c4_0 | ~ bnd_c7_0) |
% 19.04/18.60 (ALL X28.
% 19.04/18.60 bnd_ndr1_0 -->
% 19.04/18.60 ((ALL X29.
% 19.04/18.60 bnd_ndr1_1 X28 -->
% 19.04/18.60 ~ bnd_c2_2 X28 X29 | ~ bnd_c3_2 X28 X29) |
% 19.04/18.60 ((bnd_ndr1_1 X28 & bnd_c1_2 X28 bnd_a254) &
% 19.04/18.60 bnd_c2_2 X28 bnd_a254) &
% 19.04/18.60 ~ bnd_c3_2 X28 bnd_a254) |
% 19.04/18.60 (bnd_ndr1_1 X28 & ~ bnd_c5_2 X28 bnd_a255) &
% 19.04/18.60 ~ bnd_c8_2 X28 bnd_a255))) &
% 19.04/18.60 ((bnd_c4_0 | ~ bnd_c9_0) |
% 19.04/18.60 ((bnd_ndr1_0 & bnd_c10_1 bnd_a256) &
% 19.04/18.60 ~ bnd_c9_1 bnd_a256) &
% 19.04/18.60 (ALL X30.
% 19.04/18.60 bnd_ndr1_1 bnd_a256 -->
% 19.04/18.60 bnd_c3_2 bnd_a256 X30 | ~ bnd_c5_2 bnd_a256 X30))) &
% 19.04/18.60 ((bnd_c4_0 |
% 19.04/18.60 (ALL X31.
% 19.04/18.60 bnd_ndr1_0 -->
% 19.04/18.60 (bnd_c10_1 X31 |
% 19.04/18.60 (ALL X32.
% 19.04/18.60 bnd_ndr1_1 X31 -->
% 19.04/18.60 (bnd_c2_2 X31 X32 | bnd_c3_2 X31 X32) |
% 19.04/18.60 bnd_c4_2 X31 X32)) |
% 19.04/18.60 (ALL X33.
% 19.04/18.60 bnd_ndr1_1 X31 -->
% 19.04/18.60 (bnd_c2_2 X31 X33 | bnd_c4_2 X31 X33) |
% 19.04/18.60 bnd_c8_2 X31 X33))) |
% 19.04/18.60 ((bnd_ndr1_0 & bnd_c3_1 bnd_a257) & bnd_c4_1 bnd_a257) &
% 19.04/18.60 bnd_c5_1 bnd_a257)) &
% 19.04/18.60 (bnd_c4_0 |
% 19.04/18.60 (ALL X34.
% 19.04/18.60 bnd_ndr1_0 -->
% 19.04/18.60 (bnd_c5_1 X34 | bnd_c8_1 X34) |
% 19.04/18.60 (ALL X35.
% 19.04/18.60 bnd_ndr1_1 X34 -->
% 19.04/18.60 (bnd_c2_2 X34 X35 | ~ bnd_c3_2 X34 X35) |
% 19.04/18.60 ~ bnd_c8_2 X34 X35)))) &
% 19.04/18.60 (bnd_c4_0 |
% 19.04/18.60 (ALL X36.
% 19.04/18.60 bnd_ndr1_0 -->
% 19.04/18.60 ((ALL X37.
% 19.04/18.60 bnd_ndr1_1 X36 -->
% 19.04/18.60 bnd_c8_2 X36 X37 | bnd_c9_2 X36 X37) |
% 19.04/18.60 (ALL X38.
% 19.04/18.60 bnd_ndr1_1 X36 -->
% 19.04/18.60 (~ bnd_c1_2 X36 X38 | ~ bnd_c7_2 X36 X38) |
% 19.04/18.60 ~ bnd_c9_2 X36 X38)) |
% 19.04/18.60 ((bnd_ndr1_1 X36 & bnd_c4_2 X36 bnd_a258) &
% 19.04/18.60 ~ bnd_c2_2 X36 bnd_a258) &
% 19.04/18.60 ~ bnd_c3_2 X36 bnd_a258))) &
% 19.04/18.60 (bnd_c6_0 |
% 19.04/18.60 (bnd_ndr1_0 & ~ bnd_c4_1 bnd_a259) & ~ bnd_c5_1 bnd_a259)) &
% 19.04/18.60 (bnd_c7_0 |
% 19.04/18.60 (ALL X39.
% 19.04/18.60 bnd_ndr1_0 -->
% 19.04/18.60 (bnd_c5_1 X39 |
% 19.04/18.60 ((bnd_ndr1_1 X39 & bnd_c10_2 X39 bnd_a260) &
% 19.04/18.60 bnd_c4_2 X39 bnd_a260) &
% 19.04/18.60 ~ bnd_c3_2 X39 bnd_a260) |
% 19.04/18.60 ((bnd_ndr1_1 X39 & bnd_c7_2 X39 bnd_a261) &
% 19.04/18.60 ~ bnd_c1_2 X39 bnd_a261) &
% 19.04/18.60 ~ bnd_c4_2 X39 bnd_a261))) &
% 19.04/18.60 (bnd_c7_0 |
% 19.04/18.60 ((bnd_ndr1_0 & bnd_c1_1 bnd_a262) & ~ bnd_c6_1 bnd_a262) &
% 19.04/18.60 (ALL X40.
% 19.04/18.60 bnd_ndr1_1 bnd_a262 -->
% 19.04/18.60 bnd_c5_2 bnd_a262 X40 | ~ bnd_c4_2 bnd_a262 X40))) &
% 19.04/18.60 (~ bnd_c1_0 | ~ bnd_c6_0)) &
% 19.04/18.60 (~ bnd_c10_0 |
% 19.04/18.60 (ALL X41.
% 19.04/18.60 bnd_ndr1_0 -->
% 19.04/18.60 (bnd_c7_1 X41 |
% 19.04/18.60 (ALL X42.
% 19.04/18.60 bnd_ndr1_1 X41 -->
% 19.04/18.60 (bnd_c10_2 X41 X42 | ~ bnd_c5_2 X41 X42) |
% 19.04/18.60 ~ bnd_c7_2 X41 X42)) |
% 19.04/18.60 ((bnd_ndr1_1 X41 & bnd_c3_2 X41 bnd_a263) &
% 19.04/18.60 bnd_c8_2 X41 bnd_a263) &
% 19.04/18.60 ~ bnd_c4_2 X41 bnd_a263))) &
% 19.04/18.60 (~ bnd_c4_0 |
% 19.04/18.60 (ALL X43.
% 19.04/18.60 bnd_ndr1_0 -->
% 19.04/18.60 (bnd_c3_1 X43 |
% 19.04/18.60 (ALL X44.
% 19.04/18.60 bnd_ndr1_1 X43 -->
% 19.04/18.60 bnd_c5_2 X43 X44 | ~ bnd_c9_2 X43 X44)) |
% 19.04/18.60 (ALL X45.
% 19.04/18.60 bnd_ndr1_1 X43 -->
% 19.04/18.60 (~ bnd_c10_2 X43 X45 | ~ bnd_c3_2 X43 X45) |
% 19.04/18.60 ~ bnd_c5_2 X43 X45)))) &
% 19.04/18.60 (~ bnd_c6_0 |
% 19.04/18.60 ((bnd_ndr1_0 & bnd_c6_1 bnd_a264) & bnd_c8_1 bnd_a264) &
% 19.04/18.60 ~ bnd_c1_1 bnd_a264)) &
% 19.04/18.60 (~ bnd_c9_0 |
% 19.04/18.60 (((((bnd_ndr1_0 & bnd_c8_1 bnd_a265) & ~ bnd_c10_1 bnd_a265) &
% 19.04/18.60 bnd_ndr1_1 bnd_a265) &
% 19.04/18.60 bnd_c4_2 bnd_a265 bnd_a266) &
% 19.04/18.60 bnd_c7_2 bnd_a265 bnd_a266) &
% 19.04/18.60 ~ bnd_c5_2 bnd_a265 bnd_a266)) &
% 19.04/18.60 ((ALL X46.
% 19.04/18.60 bnd_ndr1_0 -->
% 19.04/18.60 bnd_c4_1 X46 |
% 19.04/18.60 (ALL X47.
% 19.04/18.60 bnd_ndr1_1 X46 -->
% 19.04/18.60 (bnd_c2_2 X46 X47 | bnd_c3_2 X46 X47) | bnd_c6_2 X46 X47)) |
% 19.04/18.60 (ALL X48.
% 19.04/18.60 bnd_ndr1_0 -->
% 19.04/18.60 ~ bnd_c1_1 X48 |
% 19.04/18.60 ((bnd_ndr1_1 X48 & bnd_c8_2 X48 bnd_a267) &
% 19.04/18.60 ~ bnd_c3_2 X48 bnd_a267) &
% 19.04/18.60 ~ bnd_c9_2 X48 bnd_a267))) &
% 19.04/18.60 (ALL X49.
% 19.04/18.60 bnd_ndr1_0 -->
% 19.04/18.60 (~ bnd_c2_1 X49 | ~ bnd_c3_1 X49) |
% 19.04/18.60 (ALL X50.
% 19.04/18.60 bnd_ndr1_1 X49 -->
% 19.04/18.60 (bnd_c10_2 X49 X50 | bnd_c9_2 X49 X50) | ~ bnd_c6_2 X49 X50))) &
% 19.04/18.60 ((ALL X51.
% 19.04/18.60 bnd_ndr1_0 -->
% 19.04/18.60 ((bnd_ndr1_1 X51 & bnd_c4_2 X51 bnd_a268) &
% 19.04/18.60 ~ bnd_c2_2 X51 bnd_a268) &
% 19.04/18.60 ~ bnd_c3_2 X51 bnd_a268) |
% 19.04/18.60 (bnd_ndr1_0 & bnd_c5_1 bnd_a269) &
% 19.04/18.60 (ALL X52.
% 19.04/18.60 bnd_ndr1_1 bnd_a269 -->
% 19.04/18.60 (bnd_c5_2 bnd_a269 X52 | bnd_c6_2 bnd_a269 X52) |
% 19.04/18.60 ~ bnd_c9_2 bnd_a269 X52))) &
% 19.04/18.60 ((bnd_c6_0 | ~ bnd_c9_0) |
% 19.04/18.60 (ALL X53.
% 19.04/18.60 bnd_ndr1_0 -->
% 19.04/18.60 (ALL X54.
% 19.04/18.60 bnd_ndr1_1 X53 -->
% 19.04/18.60 (bnd_c1_2 X53 X54 | ~ bnd_c10_2 X53 X54) | ~ bnd_c2_2 X53 X54) |
% 19.04/18.60 (ALL X55.
% 19.04/18.60 bnd_ndr1_1 X53 -->
% 19.04/18.60 (~ bnd_c5_2 X53 X55 | ~ bnd_c6_2 X53 X55) |
% 19.04/18.60 ~ bnd_c8_2 X53 X55)))) &
% 19.04/18.60 ((bnd_c6_0 |
% 19.04/18.60 (ALL X56.
% 19.04/18.60 bnd_ndr1_0 -->
% 19.04/18.60 (bnd_c10_1 X56 |
% 19.04/18.60 (ALL X57.
% 19.04/18.60 bnd_ndr1_1 X56 -->
% 19.04/18.60 (bnd_c8_2 X56 X57 | ~ bnd_c6_2 X56 X57) | ~ bnd_c7_2 X56 X57)) |
% 19.04/18.60 ((bnd_ndr1_1 X56 & bnd_c1_2 X56 bnd_a270) & bnd_c3_2 X56 bnd_a270) &
% 19.04/18.60 ~ bnd_c10_2 X56 bnd_a270)) |
% 19.04/18.60 (ALL X58.
% 19.04/18.60 bnd_ndr1_0 -->
% 19.04/18.60 (bnd_c6_1 X58 |
% 19.04/18.60 ((bnd_ndr1_1 X58 & bnd_c3_2 X58 bnd_a271) & bnd_c8_2 X58 bnd_a271) &
% 19.04/18.60 ~ bnd_c10_2 X58 bnd_a271) |
% 19.04/18.60 ((bnd_ndr1_1 X58 & bnd_c6_2 X58 bnd_a272) & bnd_c8_2 X58 bnd_a272) &
% 19.04/18.60 ~ bnd_c2_2 X58 bnd_a272))) &
% 19.04/18.60 (bnd_c6_0 |
% 19.04/18.60 (ALL X59.
% 19.04/18.60 bnd_ndr1_0 -->
% 19.04/18.60 (bnd_c3_1 X59 | ~ bnd_c2_1 X59) |
% 19.04/18.60 ((bnd_ndr1_1 X59 & bnd_c2_2 X59 bnd_a273) & bnd_c5_2 X59 bnd_a273) &
% 19.04/18.60 bnd_c6_2 X59 bnd_a273))) &
% 19.04/18.60 ((bnd_c6_0 |
% 19.04/18.60 (ALL X60.
% 19.04/18.60 bnd_ndr1_0 -->
% 19.04/18.60 (bnd_c3_1 X60 | ~ bnd_c4_1 X60) |
% 19.04/18.60 ((bnd_ndr1_1 X60 & bnd_c2_2 X60 bnd_a274) & bnd_c3_2 X60 bnd_a274) &
% 19.04/18.60 ~ bnd_c4_2 X60 bnd_a274)) |
% 19.04/18.60 (ALL X61.
% 19.04/18.60 bnd_ndr1_0 -->
% 19.04/18.60 (bnd_c6_1 X61 |
% 19.04/18.60 (bnd_ndr1_1 X61 & bnd_c2_2 X61 bnd_a275) & bnd_c7_2 X61 bnd_a275) |
% 19.04/18.60 ((bnd_ndr1_1 X61 & bnd_c5_2 X61 bnd_a276) & ~ bnd_c10_2 X61 bnd_a276) &
% 19.04/18.60 ~ bnd_c4_2 X61 bnd_a276))) &
% 19.04/18.60 ((bnd_c6_0 |
% 19.04/18.60 (ALL X62.
% 19.04/18.60 bnd_ndr1_0 -->
% 19.04/18.60 (~ bnd_c2_1 X62 |
% 19.04/18.60 ((bnd_ndr1_1 X62 & bnd_c1_2 X62 bnd_a277) & bnd_c9_2 X62 bnd_a277) &
% 19.04/18.60 ~ bnd_c10_2 X62 bnd_a277) |
% 19.04/18.60 ((bnd_ndr1_1 X62 & bnd_c7_2 X62 bnd_a278) & bnd_c8_2 X62 bnd_a278) &
% 19.04/18.60 ~ bnd_c9_2 X62 bnd_a278)) |
% 19.04/18.60 (ALL X63.
% 19.04/18.60 bnd_ndr1_0 -->
% 19.04/18.60 ((ALL X64. bnd_ndr1_1 X63 --> bnd_c3_2 X63 X64 | ~ bnd_c7_2 X63 X64) |
% 19.04/18.60 ((bnd_ndr1_1 X63 & ~ bnd_c2_2 X63 bnd_a279) & ~ bnd_c8_2 X63 bnd_a279) &
% 19.04/18.60 ~ bnd_c9_2 X63 bnd_a279) |
% 19.04/18.60 (bnd_ndr1_1 X63 & ~ bnd_c4_2 X63 bnd_a280) & ~ bnd_c5_2 X63 bnd_a280))) &
% 19.04/18.60 (bnd_c6_0 |
% 19.04/18.60 ((((bnd_ndr1_0 & ~ bnd_c5_1 bnd_a281) &
% 19.04/18.60 (ALL X65.
% 19.04/18.60 bnd_ndr1_1 bnd_a281 -->
% 19.04/18.60 (bnd_c7_2 bnd_a281 X65 | ~ bnd_c2_2 bnd_a281 X65) |
% 19.04/18.60 ~ bnd_c3_2 bnd_a281 X65)) &
% 19.04/18.60 bnd_ndr1_1 bnd_a281) &
% 19.04/18.60 bnd_c8_2 bnd_a281 bnd_a282) &
% 19.04/18.60 ~ bnd_c4_2 bnd_a281 bnd_a282)) &
% 19.04/18.60 ((bnd_c7_0 | bnd_c8_0) | ~ bnd_c9_0)) &
% 19.04/18.60 ((bnd_c7_0 | bnd_c8_0) |
% 19.04/18.60 ((((((((bnd_ndr1_0 &
% 19.04/18.60 ~ bnd_c9_1 bnd_a283) &
% 19.04/18.60 bnd_ndr1_1 bnd_a283) &
% 19.04/18.60 bnd_c1_2 bnd_a283 bnd_a284) &
% 19.04/18.60 bnd_c7_2 bnd_a283 bnd_a284) &
% 19.04/18.60 ~ bnd_c6_2 bnd_a283 bnd_a284) &
% 19.04/18.60 bnd_ndr1_1 bnd_a283) &
% 19.04/18.60 bnd_c10_2 bnd_a283 bnd_a285) &
% 19.04/18.60 bnd_c2_2 bnd_a283 bnd_a285) &
% 19.04/18.60 bnd_c8_2 bnd_a283 bnd_a285)) &
% 19.04/18.60 ((bnd_c7_0 | bnd_c9_0) |
% 19.04/18.60 (ALL X66.
% 19.04/18.60 bnd_ndr1_0 -->
% 19.04/18.60 ((ALL X67.
% 19.04/18.60 bnd_ndr1_1 X66 -->
% 19.04/18.60 (bnd_c10_2 X66 X67 | bnd_c8_2 X66 X67) | ~ bnd_c3_2 X66 X67) |
% 19.04/18.60 (ALL X68.
% 19.04/18.60 bnd_ndr1_1 X66 -->
% 19.04/18.60 (bnd_c6_2 X66 X68 | bnd_c9_2 X66 X68) | ~ bnd_c1_2 X66 X68)) |
% 19.04/18.60 ((bnd_ndr1_1 X66 &
% 19.04/18.60 bnd_c2_2 X66 bnd_a286) &
% 19.04/18.60 ~ bnd_c1_2 X66 bnd_a286) &
% 19.04/18.60 ~ bnd_c4_2 X66 bnd_a286))) &
% 19.04/18.60 ((bnd_c7_0 | ~ bnd_c10_0) |
% 19.04/18.60 (((((bnd_ndr1_0 & bnd_c10_1 bnd_a287) &
% 19.04/18.60 (ALL X69.
% 19.04/18.60 bnd_ndr1_1 bnd_a287 -->
% 19.04/18.60 (bnd_c6_2 bnd_a287 X69 | bnd_c9_2 bnd_a287 X69) |
% 19.04/18.60 ~ bnd_c7_2 bnd_a287 X69)) &
% 19.04/18.60 bnd_ndr1_1 bnd_a287) &
% 19.04/18.60 bnd_c3_2 bnd_a287 bnd_a288) &
% 19.04/18.60 bnd_c8_2 bnd_a287 bnd_a288) &
% 19.04/18.60 ~ bnd_c9_2 bnd_a287 bnd_a288)) &
% 19.04/18.60 ((bnd_c7_0 | ~ bnd_c10_0) |
% 19.04/18.60 ((bnd_ndr1_0 & ~ bnd_c1_1 bnd_a289) &
% 19.04/18.60 ~ bnd_c9_1 bnd_a289) &
% 19.04/18.60 (ALL X70.
% 19.04/18.60 bnd_ndr1_1 bnd_a289 -->
% 19.04/18.60 (bnd_c2_2 bnd_a289 X70 |
% 19.04/18.60 bnd_c6_2 bnd_a289 X70) |
% 19.04/18.60 ~ bnd_c10_2 bnd_a289 X70))) &
% 19.04/18.60 ((bnd_c7_0 | ~ bnd_c4_0) |
% 19.04/18.60 (ALL X71.
% 19.04/18.60 bnd_ndr1_0 -->
% 19.04/18.60 (bnd_c5_1 X71 |
% 19.04/18.60 ((bnd_ndr1_1 X71 &
% 19.04/18.60 bnd_c1_2 X71 bnd_a290) &
% 19.04/18.60 bnd_c5_2 X71 bnd_a290) &
% 19.04/18.60 bnd_c7_2 X71 bnd_a290) |
% 19.04/18.60 ((bnd_ndr1_1 X71 &
% 19.04/18.60 ~ bnd_c5_2 X71 bnd_a291) &
% 19.04/18.60 ~ bnd_c6_2 X71 bnd_a291) &
% 19.04/18.60 ~ bnd_c9_2 X71 bnd_a291))) &
% 19.04/18.60 ((bnd_c7_0 |
% 19.04/18.60 (ALL X72.
% 19.04/18.60 bnd_ndr1_0 -->
% 19.04/18.60 (~ bnd_c5_1 X72 | ~ bnd_c6_1 X72) |
% 19.04/18.60 ((bnd_ndr1_1 X72 &
% 19.04/18.60 bnd_c7_2 X72 bnd_a292) &
% 19.04/18.60 ~ bnd_c1_2 X72 bnd_a292) &
% 19.04/18.60 ~ bnd_c9_2 X72 bnd_a292)) |
% 19.04/18.60 ((bnd_ndr1_0 & bnd_c7_1 bnd_a293) &
% 19.04/18.60 bnd_c9_1 bnd_a293) &
% 19.04/18.60 ~ bnd_c1_1 bnd_a293)) &
% 19.04/18.60 ((bnd_c8_0 | ~ bnd_c10_0) |
% 19.04/18.60 (ALL X73.
% 19.04/18.60 bnd_ndr1_0 -->
% 19.04/18.60 (~ bnd_c7_1 X73 | ~ bnd_c8_1 X73) |
% 19.04/18.60 ((bnd_ndr1_1 X73 & bnd_c9_2 X73 bnd_a294) &
% 19.04/18.60 ~ bnd_c2_2 X73 bnd_a294) &
% 19.04/18.60 ~ bnd_c8_2 X73 bnd_a294))) &
% 19.04/18.60 ((bnd_c8_0 | ~ bnd_c4_0) |
% 19.04/18.60 (ALL X74.
% 19.04/18.60 bnd_ndr1_0 -->
% 19.04/18.60 (bnd_c9_1 X74 |
% 19.04/18.60 (ALL X75.
% 19.04/18.60 bnd_ndr1_1 X74 -->
% 19.04/18.60 (bnd_c10_2 X74 X75 |
% 19.04/18.60 ~ bnd_c1_2 X74 X75) |
% 19.04/18.60 ~ bnd_c9_2 X74 X75)) |
% 19.04/18.60 (ALL X76.
% 19.04/18.60 bnd_ndr1_1 X74 -->
% 19.04/18.60 (bnd_c5_2 X74 X76 | bnd_c6_2 X74 X76) |
% 19.04/18.60 ~ bnd_c4_2 X74 X76)))) &
% 19.04/18.60 ((bnd_c8_0 | ~ bnd_c9_0) |
% 19.04/18.60 ((((bnd_ndr1_0 & bnd_c1_1 bnd_a295) &
% 19.04/18.60 bnd_ndr1_1 bnd_a295) &
% 19.04/18.60 bnd_c10_2 bnd_a295 bnd_a296) &
% 19.04/18.60 bnd_c3_2 bnd_a295 bnd_a296) &
% 19.04/18.60 ~ bnd_c9_2 bnd_a295 bnd_a296)) &
% 19.04/18.60 ((bnd_c8_0 |
% 19.04/18.60 (ALL X77.
% 19.04/18.60 bnd_ndr1_0 -->
% 19.04/18.60 (bnd_c4_1 X77 | ~ bnd_c1_1 X77) |
% 19.04/18.60 ((bnd_ndr1_1 X77 & ~ bnd_c2_2 X77 bnd_a297) &
% 19.04/18.60 ~ bnd_c6_2 X77 bnd_a297) &
% 19.04/18.60 ~ bnd_c7_2 X77 bnd_a297)) |
% 19.04/18.60 (ALL X78.
% 19.04/18.60 bnd_ndr1_0 -->
% 19.04/18.60 ((ALL X79.
% 19.04/18.60 bnd_ndr1_1 X78 -->
% 19.04/18.60 (bnd_c3_2 X78 X79 | ~ bnd_c1_2 X78 X79) |
% 19.04/18.60 ~ bnd_c7_2 X78 X79) |
% 19.04/18.60 ((bnd_ndr1_1 X78 & ~ bnd_c1_2 X78 bnd_a298) &
% 19.04/18.60 ~ bnd_c5_2 X78 bnd_a298) &
% 19.04/18.60 ~ bnd_c9_2 X78 bnd_a298) |
% 19.04/18.60 ((bnd_ndr1_1 X78 & ~ bnd_c3_2 X78 bnd_a299) &
% 19.04/18.60 ~ bnd_c4_2 X78 bnd_a299) &
% 19.04/18.60 ~ bnd_c8_2 X78 bnd_a299))) &
% 19.04/18.60 ((bnd_c8_0 |
% 19.04/18.60 (ALL X80.
% 19.04/18.60 bnd_ndr1_0 -->
% 19.04/18.60 (bnd_c4_1 X80 |
% 19.04/18.60 ((bnd_ndr1_1 X80 & bnd_c2_2 X80 bnd_a300) &
% 19.04/18.60 bnd_c4_2 X80 bnd_a300) &
% 19.04/18.60 ~ bnd_c3_2 X80 bnd_a300) |
% 19.04/18.60 ((bnd_ndr1_1 X80 & ~ bnd_c1_2 X80 bnd_a301) &
% 19.04/18.60 ~ bnd_c4_2 X80 bnd_a301) &
% 19.04/18.60 ~ bnd_c9_2 X80 bnd_a301)) |
% 19.04/18.60 (ALL X81.
% 19.04/18.60 bnd_ndr1_0 -->
% 19.04/18.60 (~ bnd_c8_1 X81 |
% 19.04/18.60 ((bnd_ndr1_1 X81 & bnd_c5_2 X81 bnd_a302) &
% 19.04/18.60 bnd_c9_2 X81 bnd_a302) &
% 19.04/18.60 ~ bnd_c8_2 X81 bnd_a302) |
% 19.04/18.60 (bnd_ndr1_1 X81 & bnd_c5_2 X81 bnd_a303) &
% 19.04/18.60 ~ bnd_c8_2 X81 bnd_a303))) &
% 19.04/18.60 ((bnd_c8_0 |
% 19.04/18.60 (ALL X82.
% 19.04/18.60 bnd_ndr1_0 -->
% 19.04/18.60 ~ bnd_c10_1 X82 | ~ bnd_c3_1 X82)) |
% 19.04/18.60 ((bnd_ndr1_0 & ~ bnd_c4_1 bnd_a304) &
% 19.04/18.60 ~ bnd_c5_1 bnd_a304) &
% 19.04/18.60 (ALL X83.
% 19.04/18.60 bnd_ndr1_1 bnd_a304 -->
% 19.04/18.60 (bnd_c4_2 bnd_a304 X83 |
% 19.04/18.60 ~ bnd_c5_2 bnd_a304 X83) |
% 19.04/18.60 ~ bnd_c8_2 bnd_a304 X83))) &
% 19.04/18.60 ((bnd_c8_0 |
% 19.04/18.60 (ALL X84.
% 19.04/18.60 bnd_ndr1_0 -->
% 19.04/18.60 ((ALL X85.
% 19.04/18.60 bnd_ndr1_1 X84 -->
% 19.04/18.60 (bnd_c1_2 X84 X85 | ~ bnd_c10_2 X84 X85) |
% 19.04/18.60 ~ bnd_c7_2 X84 X85) |
% 19.04/18.60 ((bnd_ndr1_1 X84 & bnd_c5_2 X84 bnd_a305) &
% 19.04/18.60 bnd_c6_2 X84 bnd_a305) &
% 19.04/18.60 bnd_c8_2 X84 bnd_a305) |
% 19.04/18.60 ((bnd_ndr1_1 X84 & bnd_c5_2 X84 bnd_a306) &
% 19.04/18.60 ~ bnd_c4_2 X84 bnd_a306) &
% 19.04/18.60 ~ bnd_c9_2 X84 bnd_a306)) |
% 19.04/18.60 (ALL X86.
% 19.04/18.60 bnd_ndr1_0 -->
% 19.04/18.60 ((bnd_ndr1_1 X86 & bnd_c1_2 X86 bnd_a307) &
% 19.04/18.60 bnd_c6_2 X86 bnd_a307) &
% 19.04/18.60 ~ bnd_c9_2 X86 bnd_a307 |
% 19.04/18.60 ((bnd_ndr1_1 X86 & bnd_c7_2 X86 bnd_a308) &
% 19.04/18.60 ~ bnd_c4_2 X86 bnd_a308) &
% 19.04/18.60 ~ bnd_c5_2 X86 bnd_a308))) &
% 19.04/18.60 ((bnd_c9_0 | ~ bnd_c1_0) |
% 19.04/18.60 (ALL X87.
% 19.04/18.60 bnd_ndr1_0 -->
% 19.04/18.60 (bnd_c1_1 X87 | bnd_c6_1 X87) | ~ bnd_c8_1 X87))) &
% 19.04/18.60 ((bnd_c9_0 | ~ bnd_c4_0) |
% 19.04/18.60 ((bnd_ndr1_0 & ~ bnd_c6_1 bnd_a309) &
% 19.04/18.60 (ALL X88.
% 19.04/18.60 bnd_ndr1_1 bnd_a309 -->
% 19.04/18.60 (bnd_c10_2 bnd_a309 X88 | bnd_c9_2 bnd_a309 X88) |
% 19.04/18.60 ~ bnd_c6_2 bnd_a309 X88)) &
% 19.04/18.60 (ALL X89.
% 19.04/18.60 bnd_ndr1_1 bnd_a309 -->
% 19.04/18.60 (bnd_c5_2 bnd_a309 X89 | ~ bnd_c10_2 bnd_a309 X89) |
% 19.04/18.60 ~ bnd_c4_2 bnd_a309 X89))) &
% 19.04/18.60 (bnd_c9_0 | ~ bnd_c6_0)) &
% 19.04/18.60 ((bnd_c9_0 | ~ bnd_c6_0) |
% 19.04/18.60 ((bnd_ndr1_0 & bnd_c6_1 bnd_a310) & ~ bnd_c1_1 bnd_a310) &
% 19.04/18.60 (ALL X90.
% 19.04/18.60 bnd_ndr1_1 bnd_a310 -->
% 19.04/18.60 (bnd_c2_2 bnd_a310 X90 | ~ bnd_c6_2 bnd_a310 X90) |
% 19.04/18.60 ~ bnd_c9_2 bnd_a310 X90))) &
% 19.04/18.60 ((bnd_c9_0 | ~ bnd_c7_0) |
% 19.04/18.60 (ALL X91.
% 19.04/18.60 bnd_ndr1_0 -->
% 19.04/18.60 (bnd_c9_1 X91 |
% 19.04/18.60 ((bnd_ndr1_1 X91 & bnd_c4_2 X91 bnd_a311) &
% 19.04/18.60 ~ bnd_c2_2 X91 bnd_a311) &
% 19.04/18.60 ~ bnd_c9_2 X91 bnd_a311) |
% 19.04/18.60 ((bnd_ndr1_1 X91 & bnd_c8_2 X91 bnd_a312) &
% 19.04/18.60 bnd_c9_2 X91 bnd_a312) &
% 19.04/18.60 ~ bnd_c6_2 X91 bnd_a312))) &
% 19.04/18.60 ((bnd_c9_0 |
% 19.04/18.60 (ALL X92.
% 19.04/18.60 bnd_ndr1_0 -->
% 19.04/18.60 (~ bnd_c5_1 X92 | ~ bnd_c6_1 X92) |
% 19.04/18.60 (bnd_ndr1_1 X92 & bnd_c3_2 X92 bnd_a313) &
% 19.04/18.60 ~ bnd_c9_2 X92 bnd_a313)) |
% 19.04/18.60 (((((bnd_ndr1_0 & ~ bnd_c4_1 bnd_a314) &
% 19.04/18.60 (ALL X93.
% 19.04/18.60 bnd_ndr1_1 bnd_a314 -->
% 19.04/18.60 (bnd_c7_2 bnd_a314 X93 | ~ bnd_c4_2 bnd_a314 X93) |
% 19.04/18.60 ~ bnd_c8_2 bnd_a314 X93)) &
% 19.04/18.60 bnd_ndr1_1 bnd_a314) &
% 19.04/18.60 bnd_c4_2 bnd_a314 bnd_a315) &
% 19.04/18.60 bnd_c7_2 bnd_a314 bnd_a315) &
% 19.04/18.60 ~ bnd_c5_2 bnd_a314 bnd_a315)) &
% 19.04/18.60 ((bnd_c9_0 |
% 19.04/18.60 (((((bnd_ndr1_0 & bnd_c8_1 bnd_a316) &
% 19.04/18.60 (ALL X94.
% 19.04/18.60 bnd_ndr1_1 bnd_a316 -->
% 19.04/18.60 ~ bnd_c6_2 bnd_a316 X94 |
% 19.04/18.60 ~ bnd_c9_2 bnd_a316 X94)) &
% 19.04/18.60 bnd_ndr1_1 bnd_a316) &
% 19.04/18.60 bnd_c2_2 bnd_a316 bnd_a317) &
% 19.04/18.60 bnd_c7_2 bnd_a316 bnd_a317) &
% 19.04/18.60 ~ bnd_c8_2 bnd_a316 bnd_a317) |
% 19.04/18.60 ((bnd_ndr1_0 & ~ bnd_c10_1 bnd_a318) & ~ bnd_c8_1 bnd_a318) &
% 19.04/18.60 (ALL X95.
% 19.04/18.60 bnd_ndr1_1 bnd_a318 -->
% 19.04/18.60 (~ bnd_c10_2 bnd_a318 X95 | ~ bnd_c4_2 bnd_a318 X95) |
% 19.04/18.60 ~ bnd_c7_2 bnd_a318 X95))) &
% 19.04/18.60 ((~ bnd_c1_0 | ~ bnd_c10_0) |
% 19.04/18.60 ((((((bnd_ndr1_0 & ~ bnd_c8_1 bnd_a319) &
% 19.04/18.60 bnd_ndr1_1 bnd_a319) &
% 19.04/18.60 bnd_c4_2 bnd_a319 bnd_a320) &
% 19.04/18.60 bnd_c5_2 bnd_a319 bnd_a320) &
% 19.04/18.60 bnd_c6_2 bnd_a319 bnd_a320) &
% 19.04/18.60 bnd_ndr1_1 bnd_a319) &
% 19.04/18.60 ~ bnd_c2_2 bnd_a319 bnd_a321)) &
% 19.04/18.60 ((~ bnd_c1_0 | ~ bnd_c4_0) |
% 19.04/18.60 (ALL X96.
% 19.04/18.60 bnd_ndr1_0 -->
% 19.04/18.60 ~ bnd_c2_1 X96 |
% 19.04/18.60 ((bnd_ndr1_1 X96 & bnd_c4_2 X96 bnd_a322) &
% 19.04/18.60 ~ bnd_c10_2 X96 bnd_a322) &
% 19.04/18.60 ~ bnd_c9_2 X96 bnd_a322))) &
% 19.04/18.60 ((~ bnd_c1_0 |
% 19.04/18.60 (ALL X97.
% 19.04/18.60 bnd_ndr1_0 -->
% 19.04/18.60 (bnd_c1_1 X97 | bnd_c4_1 X97) |
% 19.04/18.60 (ALL X98.
% 19.04/18.60 bnd_ndr1_1 X97 -->
% 19.04/18.60 (bnd_c1_2 X97 X98 | bnd_c2_2 X97 X98) |
% 19.04/18.60 ~ bnd_c6_2 X97 X98))) |
% 19.04/18.60 (((((bnd_ndr1_0 & bnd_c7_1 bnd_a323) &
% 19.04/18.60 (ALL X99.
% 19.04/18.60 bnd_ndr1_1 bnd_a323 -->
% 19.04/18.60 (bnd_c6_2 bnd_a323 X99 | ~ bnd_c10_2 bnd_a323 X99) |
% 19.04/18.60 ~ bnd_c9_2 bnd_a323 X99)) &
% 19.04/18.60 bnd_ndr1_1 bnd_a323) &
% 19.04/18.60 bnd_c1_2 bnd_a323 bnd_a324) &
% 19.04/18.60 bnd_c2_2 bnd_a323 bnd_a324) &
% 19.04/18.60 ~ bnd_c3_2 bnd_a323 bnd_a324)) &
% 19.04/18.60 ((~ bnd_c1_0 |
% 19.04/18.60 (ALL X100.
% 19.04/18.60 bnd_ndr1_0 -->
% 19.04/18.60 (~ bnd_c2_1 X100 |
% 19.04/18.60 (ALL X101.
% 19.04/18.60 bnd_ndr1_1 X100 -->
% 19.04/18.60 (bnd_c10_2 X100 X101 | ~ bnd_c1_2 X100 X101) |
% 19.04/18.60 ~ bnd_c5_2 X100 X101)) |
% 19.04/18.60 (bnd_ndr1_1 X100 & bnd_c3_2 X100 bnd_a325) &
% 19.04/18.60 bnd_c4_2 X100 bnd_a325)) |
% 19.04/18.60 (bnd_ndr1_0 &
% 19.04/18.60 (ALL X102.
% 19.04/18.60 bnd_ndr1_1 bnd_a326 -->
% 19.04/18.60 (bnd_c4_2 bnd_a326 X102 | bnd_c6_2 bnd_a326 X102) |
% 19.04/18.60 ~ bnd_c7_2 bnd_a326 X102)) &
% 19.04/18.60 (ALL X103.
% 19.04/18.60 bnd_ndr1_1 bnd_a326 -->
% 19.04/18.60 (~ bnd_c10_2 bnd_a326 X103 | ~ bnd_c5_2 bnd_a326 X103) |
% 19.04/18.60 ~ bnd_c9_2 bnd_a326 X103))) &
% 19.04/18.60 (~ bnd_c1_0 |
% 19.04/18.60 ((bnd_ndr1_0 & bnd_c10_1 bnd_a327) & bnd_c6_1 bnd_a327) &
% 19.04/18.60 ~ bnd_c3_1 bnd_a327)) &
% 19.04/18.60 ((~ bnd_c1_0 |
% 19.04/18.60 (((((bnd_ndr1_0 & bnd_c2_1 bnd_a328) &
% 19.04/18.60 (ALL X104.
% 19.04/18.60 bnd_ndr1_1 bnd_a328 --> ~ bnd_c8_2 bnd_a328 X104)) &
% 19.04/18.60 bnd_ndr1_1 bnd_a328) &
% 19.04/18.60 bnd_c10_2 bnd_a328 bnd_a329) &
% 19.04/18.60 bnd_c6_2 bnd_a328 bnd_a329) &
% 19.04/18.60 ~ bnd_c8_2 bnd_a328 bnd_a329) |
% 19.04/18.60 ((bnd_ndr1_0 & ~ bnd_c10_1 bnd_a330) & ~ bnd_c8_1 bnd_a330) &
% 19.04/18.60 ~ bnd_c9_1 bnd_a330)) &
% 19.04/18.60 ((~ bnd_c10_0 | ~ bnd_c3_0) |
% 19.04/18.60 (ALL X105.
% 19.04/18.60 bnd_ndr1_0 -->
% 19.04/18.60 bnd_c5_1 X105 |
% 19.04/18.60 ((bnd_ndr1_1 X105 & bnd_c6_2 X105 bnd_a331) &
% 19.04/18.60 bnd_c8_2 X105 bnd_a331) &
% 19.04/18.60 ~ bnd_c7_2 X105 bnd_a331))) &
% 19.04/18.60 ((~ bnd_c10_0 | ~ bnd_c6_0) |
% 19.04/18.60 (ALL X106. bnd_ndr1_0 --> bnd_c6_1 X106 | ~ bnd_c8_1 X106))) &
% 19.04/18.60 ((~ bnd_c10_0 | ~ bnd_c8_0) |
% 19.04/18.60 ((bnd_ndr1_0 & ~ bnd_c1_1 bnd_a332) & ~ bnd_c4_1 bnd_a332) &
% 19.04/18.60 (ALL X107.
% 19.04/18.60 bnd_ndr1_1 bnd_a332 -->
% 19.04/18.60 (bnd_c10_2 bnd_a332 X107 | bnd_c9_2 bnd_a332 X107) |
% 19.04/18.60 ~ bnd_c1_2 bnd_a332 X107))) &
% 19.04/18.60 ((~ bnd_c10_0 |
% 19.04/18.60 (ALL X108.
% 19.04/18.60 bnd_ndr1_0 -->
% 19.04/18.60 (bnd_c5_1 X108 | ~ bnd_c7_1 X108) |
% 19.04/18.60 (ALL X109.
% 19.04/18.60 bnd_ndr1_1 X108 -->
% 19.04/18.60 (bnd_c8_2 X108 X109 | bnd_c9_2 X108 X109) |
% 19.04/18.60 ~ bnd_c2_2 X108 X109))) |
% 19.04/18.60 (((((bnd_ndr1_0 & bnd_c7_1 bnd_a333) & ~ bnd_c10_1 bnd_a333) &
% 19.04/18.60 bnd_ndr1_1 bnd_a333) &
% 19.04/18.60 bnd_c10_2 bnd_a333 bnd_a334) &
% 19.04/18.60 ~ bnd_c7_2 bnd_a333 bnd_a334) &
% 19.04/18.60 ~ bnd_c9_2 bnd_a333 bnd_a334)) &
% 19.04/18.60 ((~ bnd_c10_0 |
% 19.04/18.60 (((((bnd_ndr1_0 & bnd_c3_1 bnd_a335) & ~ bnd_c7_1 bnd_a335) &
% 19.04/18.60 bnd_ndr1_1 bnd_a335) &
% 19.04/18.60 bnd_c2_2 bnd_a335 bnd_a336) &
% 19.04/18.60 bnd_c8_2 bnd_a335 bnd_a336) &
% 19.04/18.60 ~ bnd_c4_2 bnd_a335 bnd_a336) |
% 19.04/18.60 ((bnd_ndr1_0 & ~ bnd_c5_1 bnd_a337) & ~ bnd_c9_1 bnd_a337) &
% 19.04/18.60 (ALL X110.
% 19.04/18.60 bnd_ndr1_1 bnd_a337 -->
% 19.04/18.60 bnd_c9_2 bnd_a337 X110 | ~ bnd_c10_2 bnd_a337 X110))) &
% 19.04/18.60 ((~ bnd_c2_0 | ~ bnd_c8_0) |
% 19.04/18.60 (ALL X111.
% 19.04/18.60 bnd_ndr1_0 -->
% 19.04/18.60 (bnd_c8_1 X111 |
% 19.04/18.60 (ALL X112.
% 19.04/18.60 bnd_ndr1_1 X111 -->
% 19.04/18.60 (bnd_c10_2 X111 X112 | ~ bnd_c8_2 X111 X112) |
% 19.04/18.60 ~ bnd_c9_2 X111 X112)) |
% 19.04/18.60 ((bnd_ndr1_1 X111 & bnd_c10_2 X111 bnd_a338) &
% 19.04/18.60 bnd_c2_2 X111 bnd_a338) &
% 19.04/18.60 ~ bnd_c7_2 X111 bnd_a338))) &
% 19.04/18.60 ((~ bnd_c2_0 | ~ bnd_c9_0) |
% 19.04/18.60 (ALL X113.
% 19.04/18.60 bnd_ndr1_0 -->
% 19.04/18.60 (bnd_c1_1 X113 |
% 19.04/18.60 (ALL X114.
% 19.04/18.60 bnd_ndr1_1 X113 -->
% 19.04/18.60 (bnd_c1_2 X113 X114 | bnd_c7_2 X113 X114) |
% 19.04/18.60 ~ bnd_c2_2 X113 X114)) |
% 19.04/18.60 (ALL X115.
% 19.04/18.60 bnd_ndr1_1 X113 -->
% 19.04/18.60 (~ bnd_c1_2 X113 X115 | ~ bnd_c10_2 X113 X115) |
% 19.04/18.60 ~ bnd_c8_2 X113 X115)))) &
% 19.04/18.60 ((~ bnd_c2_0 | (bnd_ndr1_0 & bnd_c3_1 bnd_a339) & ~ bnd_c6_1 bnd_a339) |
% 19.04/18.60 ((((bnd_ndr1_0 & ~ bnd_c8_1 bnd_a340) & bnd_ndr1_1 bnd_a340) &
% 19.04/18.60 bnd_c1_2 bnd_a340 bnd_a341) &
% 19.04/18.60 bnd_c7_2 bnd_a340 bnd_a341) &
% 19.04/18.60 bnd_c9_2 bnd_a340 bnd_a341)) &
% 19.04/18.60 ((~ bnd_c3_0 | ~ bnd_c7_0) |
% 19.04/18.60 ((bnd_ndr1_0 & ~ bnd_c2_1 bnd_a342) & ~ bnd_c3_1 bnd_a342) &
% 19.04/18.60 (ALL X116.
% 19.04/18.60 bnd_ndr1_1 bnd_a342 -->
% 19.04/18.60 (bnd_c6_2 bnd_a342 X116 | bnd_c8_2 bnd_a342 X116) |
% 19.04/18.60 ~ bnd_c3_2 bnd_a342 X116))) &
% 19.04/18.60 ((~ bnd_c3_0 |
% 19.04/18.60 (ALL X117.
% 19.04/18.60 bnd_ndr1_0 -->
% 19.04/18.60 (bnd_c10_1 X117 | bnd_c2_1 X117) |
% 19.04/18.60 (ALL X118.
% 19.04/18.60 bnd_ndr1_1 X117 -->
% 19.04/18.60 (bnd_c6_2 X117 X118 | bnd_c8_2 X117 X118) |
% 19.04/18.60 ~ bnd_c3_2 X117 X118))) |
% 19.04/18.60 (ALL X119.
% 19.04/18.60 bnd_ndr1_0 -->
% 19.04/18.60 ((ALL X120.
% 19.04/18.60 bnd_ndr1_1 X119 -->
% 19.04/18.60 (bnd_c1_2 X119 X120 | ~ bnd_c4_2 X119 X120) |
% 19.04/18.60 ~ bnd_c9_2 X119 X120) |
% 19.04/18.60 (ALL X121.
% 19.04/18.60 bnd_ndr1_1 X119 -->
% 19.04/18.60 (bnd_c6_2 X119 X121 | ~ bnd_c2_2 X119 X121) |
% 19.04/18.60 ~ bnd_c3_2 X119 X121)) |
% 19.04/18.60 ((bnd_ndr1_1 X119 & bnd_c9_2 X119 bnd_a343) & ~ bnd_c3_2 X119 bnd_a343) &
% 19.04/18.60 ~ bnd_c4_2 X119 bnd_a343))) &
% 19.04/18.60 ((~ bnd_c3_0 |
% 19.04/18.60 (ALL X122.
% 19.04/18.60 bnd_ndr1_0 -->
% 19.04/18.60 bnd_c4_1 X122 |
% 19.04/18.60 ((bnd_ndr1_1 X122 & bnd_c1_2 X122 bnd_a344) & bnd_c6_2 X122 bnd_a344) &
% 19.04/18.60 ~ bnd_c9_2 X122 bnd_a344)) |
% 19.04/18.60 (ALL X123.
% 19.04/18.60 bnd_ndr1_0 -->
% 19.04/18.60 (bnd_c7_1 X123 | bnd_c9_1 X123) |
% 19.04/18.60 ((bnd_ndr1_1 X123 & bnd_c3_2 X123 bnd_a345) & bnd_c7_2 X123 bnd_a345) &
% 19.04/18.60 ~ bnd_c9_2 X123 bnd_a345))) &
% 19.04/18.60 ((~ bnd_c3_0 |
% 19.04/18.60 (ALL X124.
% 19.04/18.60 bnd_ndr1_0 -->
% 19.04/18.60 ((ALL X125.
% 19.04/18.60 bnd_ndr1_1 X124 -->
% 19.04/18.60 (bnd_c10_2 X124 X125 | bnd_c8_2 X124 X125) | ~ bnd_c6_2 X124 X125) |
% 19.04/18.60 (ALL X126.
% 19.04/18.60 bnd_ndr1_1 X124 -->
% 19.04/18.60 (bnd_c10_2 X124 X126 | ~ bnd_c3_2 X124 X126) |
% 19.04/18.60 ~ bnd_c8_2 X124 X126)) |
% 19.04/18.60 (ALL X127.
% 19.04/18.60 bnd_ndr1_1 X124 -->
% 19.04/18.60 (bnd_c4_2 X124 X127 | ~ bnd_c3_2 X124 X127) |
% 19.04/18.60 ~ bnd_c7_2 X124 X127))) |
% 19.04/18.60 (bnd_ndr1_0 & bnd_c5_1 bnd_a346) &
% 19.04/18.60 (ALL X128.
% 19.04/18.60 bnd_ndr1_1 bnd_a346 -->
% 19.04/18.60 (~ bnd_c3_2 bnd_a346 X128 | ~ bnd_c6_2 bnd_a346 X128) |
% 19.04/18.60 ~ bnd_c7_2 bnd_a346 X128))) &
% 19.04/18.60 ((~ bnd_c4_0 | ~ bnd_c7_0) |
% 19.04/18.60 (ALL X129.
% 19.04/18.60 bnd_ndr1_0 -->
% 19.04/18.60 (bnd_c1_1 X129 | bnd_c7_1 X129) |
% 19.04/18.60 ((bnd_ndr1_1 X129 & bnd_c2_2 X129 bnd_a347) & bnd_c8_2 X129 bnd_a347) &
% 19.04/18.60 ~ bnd_c7_2 X129 bnd_a347))) &
% 19.04/18.60 ((~ bnd_c4_0 |
% 19.04/18.60 (ALL X130.
% 19.04/18.60 bnd_ndr1_0 -->
% 19.04/18.60 (bnd_c7_1 X130 |
% 19.04/18.60 ((bnd_ndr1_1 X130 & bnd_c9_2 X130 bnd_a348) & ~ bnd_c3_2 X130 bnd_a348) &
% 19.04/18.60 ~ bnd_c4_2 X130 bnd_a348) |
% 19.04/18.60 ((bnd_ndr1_1 X130 & ~ bnd_c1_2 X130 bnd_a349) & ~ bnd_c2_2 X130 bnd_a349) &
% 19.04/18.60 ~ bnd_c5_2 X130 bnd_a349)) |
% 19.04/18.60 (((((((bnd_ndr1_0 &
% 19.04/18.60 (ALL X131.
% 19.04/18.60 bnd_ndr1_1 bnd_a350 -->
% 19.04/18.60 (bnd_c8_2 bnd_a350 X131 | ~ bnd_c1_2 bnd_a350 X131) |
% 19.04/18.60 ~ bnd_c5_2 bnd_a350 X131)) &
% 19.04/18.60 bnd_ndr1_1 bnd_a350) &
% 19.04/18.60 bnd_c5_2 bnd_a350 bnd_a351) &
% 19.04/18.60 ~ bnd_c6_2 bnd_a350 bnd_a351) &
% 19.04/18.60 bnd_ndr1_1 bnd_a350) &
% 19.04/18.60 bnd_c7_2 bnd_a350 bnd_a352) &
% 19.04/18.60 ~ bnd_c4_2 bnd_a350 bnd_a352) &
% 19.04/18.60 ~ bnd_c5_2 bnd_a350 bnd_a352)) &
% 19.04/18.60 (~ bnd_c6_0 | ~ bnd_c9_0)) &
% 19.04/18.60 ((~ bnd_c7_0 |
% 19.04/18.60 (ALL X132.
% 19.04/18.60 bnd_ndr1_0 -->
% 19.04/18.60 (bnd_c1_1 X132 | bnd_c4_1 X132) |
% 19.04/18.60 bnd_c8_1 X132)) |
% 19.04/18.60 (ALL X133.
% 19.04/18.60 bnd_ndr1_0 -->
% 19.04/18.60 (bnd_c3_1 X133 | ~ bnd_c8_1 X133) |
% 19.04/18.60 (ALL X134.
% 19.04/18.60 bnd_ndr1_1 X133 -->
% 19.04/18.60 (bnd_c1_2 X133 X134 | bnd_c2_2 X133 X134) | ~ bnd_c7_2 X133 X134)))) &
% 19.04/18.60 ((~ bnd_c7_0 |
% 19.04/18.60 (ALL X135.
% 19.04/18.60 bnd_ndr1_0 -->
% 19.04/18.60 (bnd_c3_1 X135 | ~ bnd_c4_1 X135) |
% 19.04/18.60 ~ bnd_c5_1 X135)) |
% 19.04/18.60 (ALL X136.
% 19.04/18.60 bnd_ndr1_0 -->
% 19.04/18.60 (~ bnd_c7_1 X136 |
% 19.04/18.60 (ALL X137.
% 19.04/18.60 bnd_ndr1_1 X136 -->
% 19.04/18.60 (bnd_c1_2 X136 X137 | bnd_c2_2 X136 X137) | bnd_c3_2 X136 X137)) |
% 19.04/18.60 ((bnd_ndr1_1 X136 &
% 19.04/18.60 bnd_c4_2 X136 bnd_a353) &
% 19.04/18.60 ~ bnd_c1_2 X136 bnd_a353) &
% 19.04/18.60 ~ bnd_c9_2 X136 bnd_a353))) &
% 19.04/18.60 ((~ bnd_c7_0 |
% 19.04/18.60 (ALL X138.
% 19.04/18.60 bnd_ndr1_0 -->
% 19.04/18.60 (bnd_c4_1 X138 | ~ bnd_c8_1 X138) |
% 19.04/18.60 (ALL X139.
% 19.04/18.60 bnd_ndr1_1 X138 -->
% 19.04/18.60 (bnd_c3_2 X138 X139 | bnd_c5_2 X138 X139) | ~ bnd_c1_2 X138 X139))) |
% 19.04/18.60 (ALL X140.
% 19.04/18.60 bnd_ndr1_0 -->
% 19.04/18.60 (~ bnd_c3_1 X140 | ~ bnd_c5_1 X140) |
% 19.04/18.60 ~ bnd_c9_1 X140))) &
% 19.04/18.60 (~ bnd_c7_0 |
% 19.04/18.60 (ALL X141.
% 19.04/18.60 bnd_ndr1_0 -->
% 19.04/18.60 (bnd_c8_1 X141 | ~ bnd_c9_1 X141) |
% 19.04/18.60 ((bnd_ndr1_1 X141 &
% 19.04/18.60 bnd_c1_2 X141 bnd_a354) &
% 19.04/18.60 bnd_c10_2 X141 bnd_a354) &
% 19.04/18.60 ~ bnd_c2_2 X141 bnd_a354))) &
% 19.04/18.60 ((~ bnd_c7_0 |
% 19.04/18.60 (((((bnd_ndr1_0 & bnd_c3_1 bnd_a355) &
% 19.04/18.60 (ALL X142.
% 19.04/18.60 bnd_ndr1_1 bnd_a355 -->
% 19.04/18.60 (~ bnd_c4_2 bnd_a355 X142 |
% 19.04/18.60 ~ bnd_c6_2 bnd_a355 X142) |
% 19.04/18.60 ~ bnd_c8_2 bnd_a355 X142)) &
% 19.04/18.60 bnd_ndr1_1 bnd_a355) &
% 19.04/18.60 ~ bnd_c10_2 bnd_a355 bnd_a356) &
% 19.04/18.60 ~ bnd_c7_2 bnd_a355 bnd_a356) &
% 19.04/18.60 ~ bnd_c9_2 bnd_a355 bnd_a356) |
% 19.04/18.60 ((bnd_ndr1_0 & bnd_c9_1 bnd_a357) &
% 19.04/18.60 (ALL X143.
% 19.04/18.60 bnd_ndr1_1 bnd_a357 -->
% 19.04/18.60 (bnd_c10_2 bnd_a357 X143 |
% 19.04/18.60 bnd_c4_2 bnd_a357 X143) |
% 19.04/18.60 ~ bnd_c9_2 bnd_a357 X143)) &
% 19.04/18.60 (ALL X144.
% 19.04/18.60 bnd_ndr1_1 bnd_a357 -->
% 19.04/18.60 (bnd_c4_2 bnd_a357 X144 |
% 19.04/18.60 bnd_c5_2 bnd_a357 X144) |
% 19.04/18.60 ~ bnd_c8_2 bnd_a357 X144))) &
% 19.04/18.60 ((~ bnd_c8_0 |
% 19.04/18.60 (ALL X145.
% 19.04/18.60 bnd_ndr1_0 -->
% 19.04/18.60 (bnd_c3_1 X145 | bnd_c9_1 X145) |
% 19.04/18.60 ((bnd_ndr1_1 X145 & bnd_c1_2 X145 bnd_a358) &
% 19.04/18.60 bnd_c8_2 X145 bnd_a358) &
% 19.04/18.60 ~ bnd_c3_2 X145 bnd_a358)) |
% 19.04/18.60 (ALL X146.
% 19.04/18.60 bnd_ndr1_0 -->
% 19.04/18.60 (bnd_c8_1 X146 |
% 19.04/18.60 (ALL X147.
% 19.04/18.60 bnd_ndr1_1 X146 -->
% 19.04/18.60 (bnd_c3_2 X146 X147 |
% 19.04/18.60 ~ bnd_c2_2 X146 X147) |
% 19.04/18.60 ~ bnd_c5_2 X146 X147)) |
% 19.04/18.60 ((bnd_ndr1_1 X146 &
% 19.04/18.60 ~ bnd_c10_2 X146 bnd_a359) &
% 19.04/18.60 ~ bnd_c2_2 X146 bnd_a359) &
% 19.04/18.60 ~ bnd_c6_2 X146 bnd_a359))) &
% 19.04/18.60 ((~ bnd_c9_0 |
% 19.04/18.60 (ALL X148.
% 19.04/18.60 bnd_ndr1_0 -->
% 19.04/18.60 (bnd_c1_1 X148 | ~ bnd_c10_1 X148) |
% 19.04/18.60 ((bnd_ndr1_1 X148 & bnd_c6_2 X148 bnd_a360) &
% 19.04/18.60 bnd_c9_2 X148 bnd_a360) &
% 19.04/18.60 ~ bnd_c10_2 X148 bnd_a360)) |
% 19.04/18.60 (ALL X149.
% 19.04/18.60 bnd_ndr1_0 -->
% 19.04/18.60 (~ bnd_c9_1 X149 |
% 19.04/18.60 (ALL X150.
% 19.04/18.60 bnd_ndr1_1 X149 -->
% 19.04/18.60 (bnd_c2_2 X149 X150 |
% 19.04/18.60 ~ bnd_c4_2 X149 X150) |
% 19.04/18.60 ~ bnd_c6_2 X149 X150)) |
% 19.04/18.60 ((bnd_ndr1_1 X149 & bnd_c9_2 X149 bnd_a361) &
% 19.04/18.60 ~ bnd_c2_2 X149 bnd_a361) &
% 19.04/18.60 ~ bnd_c8_2 X149 bnd_a361))) &
% 19.04/18.60 ((~ bnd_c9_0 |
% 19.04/18.60 (ALL X151.
% 19.04/18.60 bnd_ndr1_0 -->
% 19.04/18.60 (bnd_c3_1 X151 | ~ bnd_c5_1 X151) |
% 19.04/18.60 ~ bnd_c7_1 X151)) |
% 19.04/18.60 (((((bnd_ndr1_0 & bnd_c3_1 bnd_a362) &
% 19.04/18.60 ~ bnd_c8_1 bnd_a362) &
% 19.04/18.60 bnd_ndr1_1 bnd_a362) &
% 19.04/18.60 bnd_c3_2 bnd_a362 bnd_a363) &
% 19.04/18.60 ~ bnd_c1_2 bnd_a362 bnd_a363) &
% 19.04/18.60 ~ bnd_c4_2 bnd_a362 bnd_a363)) &
% 19.04/18.60 ((~ bnd_c9_0 |
% 19.04/18.60 (ALL X152.
% 19.04/18.60 bnd_ndr1_0 -->
% 19.04/18.60 (~ bnd_c2_1 X152 | ~ bnd_c5_1 X152) |
% 19.04/18.60 (ALL X153.
% 19.04/18.60 bnd_ndr1_1 X152 -->
% 19.04/18.60 ~ bnd_c4_2 X152 X153 |
% 19.04/18.60 ~ bnd_c5_2 X152 X153))) |
% 19.04/18.60 ((bnd_ndr1_0 & ~ bnd_c1_1 bnd_a364) &
% 19.04/18.60 (ALL X154.
% 19.04/18.60 bnd_ndr1_1 bnd_a364 -->
% 19.04/18.60 (bnd_c3_2 bnd_a364 X154 |
% 19.04/18.60 bnd_c8_2 bnd_a364 X154) |
% 19.04/18.60 ~ bnd_c4_2 bnd_a364 X154)) &
% 19.04/18.60 (ALL X155.
% 19.04/18.60 bnd_ndr1_1 bnd_a364 -->
% 19.04/18.60 (~ bnd_c10_2 bnd_a364 X155 |
% 19.04/18.60 ~ bnd_c6_2 bnd_a364 X155) |
% 19.04/18.60 ~ bnd_c8_2 bnd_a364 X155))) &
% 19.04/18.60 (~ bnd_c9_0 |
% 19.04/18.60 (ALL X156.
% 19.04/18.60 bnd_ndr1_0 -->
% 19.04/18.60 (~ bnd_c2_1 X156 |
% 19.04/18.60 ((bnd_ndr1_1 X156 & bnd_c2_2 X156 bnd_a365) &
% 19.04/18.60 bnd_c4_2 X156 bnd_a365) &
% 19.04/18.60 ~ bnd_c3_2 X156 bnd_a365) |
% 19.04/18.60 ((bnd_ndr1_1 X156 & ~ bnd_c1_2 X156 bnd_a366) &
% 19.04/18.60 ~ bnd_c7_2 X156 bnd_a366) &
% 19.04/18.60 ~ bnd_c9_2 X156 bnd_a366))) &
% 19.04/18.60 ((~ bnd_c9_0 |
% 19.04/18.60 (ALL X157.
% 19.04/18.60 bnd_ndr1_0 -->
% 19.04/18.60 ((ALL X158.
% 19.04/18.60 bnd_ndr1_1 X157 -->
% 19.04/18.60 (bnd_c7_2 X157 X158 | ~ bnd_c4_2 X157 X158) |
% 19.04/18.60 ~ bnd_c6_2 X157 X158) |
% 19.04/18.60 ((bnd_ndr1_1 X157 & ~ bnd_c1_2 X157 bnd_a367) &
% 19.04/18.60 ~ bnd_c2_2 X157 bnd_a367) &
% 19.04/18.60 ~ bnd_c6_2 X157 bnd_a367) |
% 19.04/18.60 ((bnd_ndr1_1 X157 & ~ bnd_c1_2 X157 bnd_a368) &
% 19.04/18.60 ~ bnd_c4_2 X157 bnd_a368) &
% 19.04/18.60 ~ bnd_c5_2 X157 bnd_a368)) |
% 19.04/18.60 (((((((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a369) &
% 19.04/18.60 bnd_c3_2 bnd_a369 bnd_a370) &
% 19.04/18.60 bnd_c8_2 bnd_a369 bnd_a370) &
% 19.04/18.60 ~ bnd_c9_2 bnd_a369 bnd_a370) &
% 19.04/18.60 bnd_ndr1_1 bnd_a369) &
% 19.04/18.60 bnd_c5_2 bnd_a369 bnd_a371) &
% 19.04/18.60 bnd_c7_2 bnd_a369 bnd_a371) &
% 19.04/18.60 ~ bnd_c9_2 bnd_a369 bnd_a371) &
% 19.04/18.60 bnd_ndr1_1 bnd_a369) &
% 19.04/18.60 bnd_c7_2 bnd_a369 bnd_a372) &
% 19.04/18.60 bnd_c9_2 bnd_a369 bnd_a372) &
% 19.04/18.60 ~ bnd_c4_2 bnd_a369 bnd_a372)) &
% 19.04/18.60 (((ALL X159.
% 19.04/18.60 bnd_ndr1_0 -->
% 19.04/18.60 (bnd_c1_1 X159 | ~ bnd_c8_1 X159) |
% 19.04/18.60 ((bnd_ndr1_1 X159 & bnd_c3_2 X159 bnd_a373) &
% 19.04/18.60 ~ bnd_c1_2 X159 bnd_a373) &
% 19.04/18.60 ~ bnd_c8_2 X159 bnd_a373) |
% 19.04/18.60 (((((bnd_ndr1_0 & bnd_c10_1 bnd_a374) &
% 19.04/18.60 bnd_c2_1 bnd_a374) &
% 19.04/18.60 bnd_ndr1_1 bnd_a374) &
% 19.04/18.60 bnd_c10_2 bnd_a374 bnd_a375) &
% 19.04/18.60 bnd_c3_2 bnd_a374 bnd_a375) &
% 19.04/18.60 ~ bnd_c9_2 bnd_a374 bnd_a375) |
% 19.04/18.60 ((bnd_ndr1_0 & bnd_c8_1 bnd_a376) &
% 19.04/18.60 ~ bnd_c6_1 bnd_a376) &
% 19.04/18.60 (ALL X160.
% 19.04/18.60 bnd_ndr1_1 bnd_a376 -->
% 19.04/18.60 (bnd_c2_2 bnd_a376 X160 |
% 19.04/18.60 ~ bnd_c3_2 bnd_a376 X160) |
% 19.04/18.60 ~ bnd_c5_2 bnd_a376 X160))) &
% 19.04/18.60 (((ALL X161.
% 19.04/18.60 bnd_ndr1_0 -->
% 19.04/18.60 (bnd_c10_1 X161 | ~ bnd_c6_1 X161) |
% 19.04/18.60 (ALL X162.
% 19.04/18.60 bnd_ndr1_1 X161 -->
% 19.04/18.60 (bnd_c10_2 X161 X162 | bnd_c6_2 X161 X162) |
% 19.04/18.60 ~ bnd_c2_2 X161 X162)) |
% 19.04/18.60 (ALL X163.
% 19.04/18.60 bnd_ndr1_0 -->
% 19.04/18.60 (~ bnd_c4_1 X163 |
% 19.04/18.60 (ALL X164.
% 19.04/18.60 bnd_ndr1_1 X163 -->
% 19.04/18.60 (bnd_c1_2 X163 X164 | bnd_c4_2 X163 X164) |
% 19.04/18.60 ~ bnd_c6_2 X163 X164)) |
% 19.04/18.60 (ALL X165.
% 19.04/18.60 bnd_ndr1_1 X163 -->
% 19.04/18.60 (bnd_c10_2 X163 X165 | bnd_c4_2 X163 X165) |
% 19.04/18.60 ~ bnd_c9_2 X163 X165))) |
% 19.04/18.60 (ALL X166.
% 19.04/18.60 bnd_ndr1_0 -->
% 19.04/18.60 (~ bnd_c5_1 X166 |
% 19.04/18.60 (ALL X167.
% 19.04/18.60 bnd_ndr1_1 X166 -->
% 19.04/18.60 (bnd_c3_2 X166 X167 | ~ bnd_c2_2 X166 X167) |
% 19.04/18.60 ~ bnd_c6_2 X166 X167)) |
% 19.04/18.60 (ALL X168.
% 19.04/18.60 bnd_ndr1_1 X166 -->
% 19.04/18.60 (bnd_c7_2 X166 X168 | bnd_c9_2 X166 X168) |
% 19.04/18.60 ~ bnd_c8_2 X166 X168)))) &
% 19.04/18.60 (((ALL X169.
% 19.04/18.60 bnd_ndr1_0 -->
% 19.04/18.60 (bnd_c2_1 X169 | ~ bnd_c4_1 X169) |
% 19.04/18.60 ((bnd_ndr1_1 X169 & bnd_c4_2 X169 bnd_a377) &
% 19.04/18.60 bnd_c5_2 X169 bnd_a377) &
% 19.04/18.60 bnd_c6_2 X169 bnd_a377) |
% 19.04/18.60 (ALL X170.
% 19.04/18.60 bnd_ndr1_0 -->
% 19.04/18.60 (bnd_c7_1 X170 | ~ bnd_c9_1 X170) |
% 19.04/18.60 (ALL X171.
% 19.04/18.60 bnd_ndr1_1 X170 -->
% 19.04/18.60 ~ bnd_c2_2 X170 X171 | ~ bnd_c9_2 X170 X171))) |
% 19.04/18.60 (ALL X172.
% 19.04/18.60 bnd_ndr1_0 -->
% 19.04/18.60 (~ bnd_c3_1 X172 |
% 19.04/18.60 ((bnd_ndr1_1 X172 & bnd_c2_2 X172 bnd_a378) &
% 19.04/18.60 bnd_c7_2 X172 bnd_a378) &
% 19.04/18.60 ~ bnd_c8_2 X172 bnd_a378) |
% 19.04/18.60 ((bnd_ndr1_1 X172 & bnd_c3_2 X172 bnd_a379) &
% 19.04/18.60 ~ bnd_c1_2 X172 bnd_a379) &
% 19.04/18.60 ~ bnd_c10_2 X172 bnd_a379))) &
% 19.04/18.60 (((ALL X173.
% 19.04/18.60 bnd_ndr1_0 -->
% 19.04/18.60 (bnd_c2_1 X173 | ~ bnd_c7_1 X173) |
% 19.04/18.60 (ALL X174.
% 19.04/18.60 bnd_ndr1_1 X173 -->
% 19.04/18.60 (bnd_c9_2 X173 X174 | ~ bnd_c3_2 X173 X174) |
% 19.04/18.60 ~ bnd_c8_2 X173 X174)) |
% 19.04/18.60 (((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a380) &
% 19.04/18.60 bnd_c1_2 bnd_a380 bnd_a381) &
% 19.04/18.60 bnd_c7_2 bnd_a380 bnd_a381) &
% 19.04/18.60 ~ bnd_c5_2 bnd_a380 bnd_a381) &
% 19.04/18.60 bnd_ndr1_1 bnd_a380) &
% 19.04/18.60 bnd_c7_2 bnd_a380 bnd_a382) &
% 19.04/18.60 ~ bnd_c1_2 bnd_a380 bnd_a382) &
% 19.04/18.60 ~ bnd_c8_2 bnd_a380 bnd_a382) |
% 19.04/18.60 ((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a383) &
% 19.04/18.60 ~ bnd_c1_2 bnd_a383 bnd_a384) &
% 19.04/18.60 ~ bnd_c6_2 bnd_a383 bnd_a384) &
% 19.04/18.60 bnd_ndr1_1 bnd_a383) &
% 19.04/18.60 ~ bnd_c10_2 bnd_a383 bnd_a385) &
% 19.04/18.60 ~ bnd_c3_2 bnd_a383 bnd_a385) &
% 19.04/18.60 ~ bnd_c5_2 bnd_a383 bnd_a385)) &
% 19.04/18.60 (((ALL X175.
% 19.04/18.60 bnd_ndr1_0 -->
% 19.04/18.60 (bnd_c3_1 X175 | bnd_c7_1 X175) |
% 19.04/18.60 ((bnd_ndr1_1 X175 & bnd_c6_2 X175 bnd_a386) &
% 19.04/18.60 ~ bnd_c7_2 X175 bnd_a386) &
% 19.04/18.60 ~ bnd_c8_2 X175 bnd_a386) |
% 19.04/18.60 (ALL X176.
% 19.04/18.60 bnd_ndr1_0 -->
% 19.04/18.60 (bnd_c3_1 X176 |
% 19.04/18.60 (ALL X177.
% 19.04/18.60 bnd_ndr1_1 X176 -->
% 19.04/18.60 (bnd_c3_2 X176 X177 | bnd_c8_2 X176 X177) |
% 19.04/18.60 ~ bnd_c7_2 X176 X177)) |
% 19.04/18.60 (ALL X178.
% 19.04/18.60 bnd_ndr1_1 X176 -->
% 19.04/18.60 (~ bnd_c10_2 X176 X178 | ~ bnd_c6_2 X176 X178) |
% 19.04/18.60 ~ bnd_c8_2 X176 X178))) |
% 19.04/18.60 ((((bnd_ndr1_0 &
% 19.04/18.60 (ALL X179.
% 19.04/18.60 bnd_ndr1_1 bnd_a387 -->
% 19.04/18.60 (bnd_c2_2 bnd_a387 X179 | bnd_c4_2 bnd_a387 X179) |
% 19.04/18.60 ~ bnd_c9_2 bnd_a387 X179)) &
% 19.04/18.60 bnd_ndr1_1 bnd_a387) &
% 19.04/18.60 bnd_c1_2 bnd_a387 bnd_a388) &
% 19.04/18.60 bnd_c6_2 bnd_a387 bnd_a388) &
% 19.04/18.60 bnd_c7_2 bnd_a387 bnd_a388)) &
% 19.04/18.60 (((ALL X180.
% 19.04/18.60 bnd_ndr1_0 -->
% 19.04/18.60 (bnd_c4_1 X180 | ~ bnd_c10_1 X180) | ~ bnd_c3_1 X180) |
% 19.04/18.60 (ALL X181.
% 19.04/18.60 bnd_ndr1_0 -->
% 19.04/18.60 (bnd_c6_1 X181 | bnd_c9_1 X181) |
% 19.04/18.60 (ALL X182.
% 19.04/18.60 bnd_ndr1_1 X181 -->
% 19.04/18.60 (bnd_c6_2 X181 X182 | bnd_c8_2 X181 X182) |
% 19.04/18.60 ~ bnd_c5_2 X181 X182))) |
% 19.04/18.60 ((((bnd_ndr1_0 & ~ bnd_c3_1 bnd_a389) &
% 19.04/18.60 (ALL X183.
% 19.04/18.60 bnd_ndr1_1 bnd_a389 -->
% 19.04/18.60 (bnd_c2_2 bnd_a389 X183 | bnd_c5_2 bnd_a389 X183) |
% 19.04/18.60 ~ bnd_c8_2 bnd_a389 X183)) &
% 19.04/18.60 bnd_ndr1_1 bnd_a389) &
% 19.04/18.60 bnd_c2_2 bnd_a389 bnd_a390) &
% 19.04/18.60 bnd_c4_2 bnd_a389 bnd_a390)) &
% 19.04/18.60 (((ALL X184.
% 19.04/18.60 bnd_ndr1_0 -->
% 19.04/18.60 (bnd_c5_1 X184 | ~ bnd_c1_1 X184) |
% 19.04/18.60 ((bnd_ndr1_1 X184 & bnd_c5_2 X184 bnd_a391) &
% 19.04/18.60 bnd_c7_2 X184 bnd_a391) &
% 19.04/18.60 ~ bnd_c6_2 X184 bnd_a391) |
% 19.04/18.60 (ALL X185.
% 19.04/18.60 bnd_ndr1_0 -->
% 19.04/18.60 (~ bnd_c7_1 X185 |
% 19.04/18.60 (ALL X186.
% 19.04/18.60 bnd_ndr1_1 X185 -->
% 19.04/18.60 (bnd_c2_2 X185 X186 | bnd_c7_2 X185 X186) |
% 19.04/18.60 ~ bnd_c6_2 X185 X186)) |
% 19.04/18.60 ((bnd_ndr1_1 X185 & bnd_c2_2 X185 bnd_a392) &
% 19.04/18.60 bnd_c3_2 X185 bnd_a392) &
% 19.04/18.60 ~ bnd_c9_2 X185 bnd_a392)) |
% 19.04/18.60 (ALL X187.
% 19.04/18.60 bnd_ndr1_0 -->
% 19.04/18.60 (~ bnd_c9_1 X187 |
% 19.04/18.60 ((bnd_ndr1_1 X187 & bnd_c1_2 X187 bnd_a393) &
% 19.04/18.60 bnd_c7_2 X187 bnd_a393) &
% 19.04/18.60 ~ bnd_c3_2 X187 bnd_a393) |
% 19.04/18.60 (bnd_ndr1_1 X187 & bnd_c1_2 X187 bnd_a394) &
% 19.04/18.60 ~ bnd_c9_2 X187 bnd_a394))) &
% 19.04/18.60 (((ALL X188.
% 19.04/18.60 bnd_ndr1_0 -->
% 19.04/18.60 (bnd_c5_1 X188 | ~ bnd_c9_1 X188) |
% 19.04/18.60 ((bnd_ndr1_1 X188 & bnd_c10_2 X188 bnd_a395) &
% 19.04/18.60 bnd_c3_2 X188 bnd_a395) &
% 19.04/18.60 ~ bnd_c9_2 X188 bnd_a395) |
% 19.04/18.60 (ALL X189.
% 19.04/18.60 bnd_ndr1_0 -->
% 19.04/18.60 (~ bnd_c8_1 X189 |
% 19.04/18.60 (ALL X190.
% 19.04/18.60 bnd_ndr1_1 X189 -->
% 19.04/18.60 bnd_c6_2 X189 X190 | ~ bnd_c7_2 X189 X190)) |
% 19.04/18.60 ((bnd_ndr1_1 X189 & bnd_c2_2 X189 bnd_a396) &
% 19.04/18.60 bnd_c6_2 X189 bnd_a396) &
% 19.04/18.60 ~ bnd_c8_2 X189 bnd_a396)) |
% 19.04/18.60 ((((((((bnd_ndr1_0 & ~ bnd_c8_1 bnd_a397) &
% 19.04/18.60 bnd_ndr1_1 bnd_a397) &
% 19.04/18.60 bnd_c10_2 bnd_a397 bnd_a398) &
% 19.04/18.60 bnd_c4_2 bnd_a397 bnd_a398) &
% 19.04/18.60 ~ bnd_c6_2 bnd_a397 bnd_a398) &
% 19.04/18.60 bnd_ndr1_1 bnd_a397) &
% 19.04/18.60 bnd_c8_2 bnd_a397 bnd_a399) &
% 19.04/18.60 ~ bnd_c1_2 bnd_a397 bnd_a399) &
% 19.04/18.60 ~ bnd_c10_2 bnd_a397 bnd_a399)) &
% 19.04/18.60 (((ALL X191.
% 19.04/18.60 bnd_ndr1_0 -->
% 19.04/18.60 (bnd_c6_1 X191 | bnd_c8_1 X191) | ~ bnd_c4_1 X191) |
% 19.04/18.60 ((bnd_ndr1_0 & ~ bnd_c3_1 bnd_a400) &
% 19.04/18.60 (ALL X192.
% 19.04/18.60 bnd_ndr1_1 bnd_a400 -->
% 19.04/18.60 (bnd_c1_2 bnd_a400 X192 | bnd_c10_2 bnd_a400 X192) |
% 19.04/18.60 ~ bnd_c3_2 bnd_a400 X192)) &
% 19.04/18.60 (ALL X193.
% 19.04/18.60 bnd_ndr1_1 bnd_a400 -->
% 19.04/18.60 (~ bnd_c1_2 bnd_a400 X193 | ~ bnd_c7_2 bnd_a400 X193) |
% 19.04/18.60 ~ bnd_c9_2 bnd_a400 X193)) |
% 19.04/18.60 ((bnd_ndr1_0 &
% 19.04/18.60 (ALL X194.
% 19.04/18.60 bnd_ndr1_1 bnd_a401 -->
% 19.04/18.60 bnd_c5_2 bnd_a401 X194 | ~ bnd_c8_2 bnd_a401 X194)) &
% 19.04/18.60 (ALL X195.
% 19.04/18.60 bnd_ndr1_1 bnd_a401 -->
% 19.04/18.60 (bnd_c8_2 bnd_a401 X195 | ~ bnd_c2_2 bnd_a401 X195) |
% 19.04/18.60 ~ bnd_c4_2 bnd_a401 X195)) &
% 19.04/18.60 (ALL X196.
% 19.04/18.60 bnd_ndr1_1 bnd_a401 -->
% 19.04/18.60 (~ bnd_c1_2 bnd_a401 X196 | ~ bnd_c10_2 bnd_a401 X196) |
% 19.04/18.60 ~ bnd_c2_2 bnd_a401 X196))) &
% 19.04/18.60 ((ALL X197.
% 19.04/18.60 bnd_ndr1_0 -->
% 19.04/18.60 bnd_c8_1 X197 |
% 19.04/18.60 ((bnd_ndr1_1 X197 & bnd_c2_2 X197 bnd_a402) &
% 19.04/18.60 ~ bnd_c1_2 X197 bnd_a402) &
% 19.04/18.60 ~ bnd_c3_2 X197 bnd_a402) |
% 19.04/18.60 (((((bnd_ndr1_0 & bnd_c2_1 bnd_a403) & ~ bnd_c4_1 bnd_a403) &
% 19.04/18.60 bnd_ndr1_1 bnd_a403) &
% 19.04/18.60 bnd_c10_2 bnd_a403 bnd_a404) &
% 19.04/18.60 bnd_c5_2 bnd_a403 bnd_a404) &
% 19.04/18.60 bnd_c8_2 bnd_a403 bnd_a404)) &
% 19.04/18.60 (((ALL X198.
% 19.04/18.60 bnd_ndr1_0 -->
% 19.04/18.60 (bnd_c9_1 X198 | ~ bnd_c2_1 X198) |
% 19.04/18.60 (bnd_ndr1_1 X198 & bnd_c4_2 X198 bnd_a405) &
% 19.04/18.60 ~ bnd_c5_2 X198 bnd_a405) |
% 19.04/18.60 (((((bnd_ndr1_0 & bnd_c4_1 bnd_a406) & bnd_c9_1 bnd_a406) &
% 19.04/18.60 bnd_ndr1_1 bnd_a406) &
% 19.04/18.60 ~ bnd_c2_2 bnd_a406 bnd_a407) &
% 19.04/18.60 ~ bnd_c7_2 bnd_a406 bnd_a407) &
% 19.04/18.60 ~ bnd_c8_2 bnd_a406 bnd_a407) |
% 19.04/18.60 (((((bnd_ndr1_0 & ~ bnd_c2_1 bnd_a408) &
% 19.04/18.60 (ALL X199.
% 19.04/18.60 bnd_ndr1_1 bnd_a408 -->
% 19.04/18.60 (bnd_c8_2 bnd_a408 X199 | bnd_c9_2 bnd_a408 X199) |
% 19.04/18.60 ~ bnd_c4_2 bnd_a408 X199)) &
% 19.04/18.60 bnd_ndr1_1 bnd_a408) &
% 19.04/18.60 bnd_c1_2 bnd_a408 bnd_a409) &
% 19.04/18.60 bnd_c4_2 bnd_a408 bnd_a409) &
% 19.04/18.60 ~ bnd_c5_2 bnd_a408 bnd_a409)) &
% 19.04/18.60 (((ALL X200.
% 19.04/18.60 bnd_ndr1_0 -->
% 19.04/18.60 (bnd_c9_1 X200 |
% 19.04/18.60 (ALL X201.
% 19.04/18.60 bnd_ndr1_1 X200 -->
% 19.04/18.60 bnd_c3_2 X200 X201 | bnd_c6_2 X200 X201)) |
% 19.04/18.60 ((bnd_ndr1_1 X200 & bnd_c1_2 X200 bnd_a410) &
% 19.04/18.60 bnd_c5_2 X200 bnd_a410) &
% 19.04/18.60 bnd_c6_2 X200 bnd_a410) |
% 19.04/18.60 (ALL X202.
% 19.04/18.60 bnd_ndr1_0 -->
% 19.04/18.60 (~ bnd_c3_1 X202 | ~ bnd_c7_1 X202) | ~ bnd_c8_1 X202)) |
% 19.04/18.60 (((((((bnd_ndr1_0 &
% 19.04/18.60 (ALL X203.
% 19.04/18.60 bnd_ndr1_1 bnd_a411 -->
% 19.04/18.60 (bnd_c3_2 bnd_a411 X203 | bnd_c8_2 bnd_a411 X203) |
% 19.04/18.60 ~ bnd_c2_2 bnd_a411 X203)) &
% 19.04/18.60 bnd_ndr1_1 bnd_a411) &
% 19.04/18.60 bnd_c3_2 bnd_a411 bnd_a412) &
% 19.04/18.60 ~ bnd_c6_2 bnd_a411 bnd_a412) &
% 19.04/18.60 bnd_ndr1_1 bnd_a411) &
% 19.04/18.60 ~ bnd_c4_2 bnd_a411 bnd_a413) &
% 19.04/18.60 ~ bnd_c8_2 bnd_a411 bnd_a413) &
% 19.04/18.60 ~ bnd_c9_2 bnd_a411 bnd_a413)) &
% 19.04/18.60 ((ALL X204.
% 19.04/18.60 bnd_ndr1_0 -->
% 19.04/18.60 (~ bnd_c1_1 X204 | ~ bnd_c5_1 X204) | ~ bnd_c8_1 X204) |
% 19.04/18.60 (((((bnd_ndr1_0 & bnd_c10_1 bnd_a414) & bnd_c9_1 bnd_a414) &
% 19.04/18.60 bnd_ndr1_1 bnd_a414) &
% 19.04/18.60 ~ bnd_c10_2 bnd_a414 bnd_a415) &
% 19.04/18.60 ~ bnd_c4_2 bnd_a414 bnd_a415) &
% 19.04/18.60 ~ bnd_c7_2 bnd_a414 bnd_a415)) &
% 19.04/18.60 (((ALL X205.
% 19.04/18.60 bnd_ndr1_0 -->
% 19.04/18.60 (~ bnd_c1_1 X205 | ~ bnd_c5_1 X205) |
% 19.04/18.60 (bnd_ndr1_1 X205 & bnd_c9_2 X205 bnd_a416) &
% 19.04/18.60 ~ bnd_c6_2 X205 bnd_a416) |
% 19.04/18.60 ((bnd_ndr1_0 & bnd_c2_1 bnd_a417) & bnd_c3_1 bnd_a417) &
% 19.04/18.60 bnd_c5_1 bnd_a417) |
% 19.04/18.60 (((((bnd_ndr1_0 & bnd_c7_1 bnd_a418) & bnd_c8_1 bnd_a418) &
% 19.04/18.60 bnd_ndr1_1 bnd_a418) &
% 19.04/18.60 bnd_c10_2 bnd_a418 bnd_a419) &
% 19.04/18.60 bnd_c5_2 bnd_a418 bnd_a419) &
% 19.04/18.60 ~ bnd_c4_2 bnd_a418 bnd_a419)) &
% 19.04/18.60 (((ALL X206.
% 19.04/18.60 bnd_ndr1_0 -->
% 19.04/18.60 (~ bnd_c2_1 X206 | ~ bnd_c6_1 X206) |
% 19.04/18.60 (ALL X207.
% 19.04/18.60 bnd_ndr1_1 X206 -->
% 19.04/18.60 (bnd_c1_2 X206 X207 | bnd_c4_2 X206 X207) |
% 19.04/18.60 bnd_c5_2 X206 X207)) |
% 19.04/18.60 ((((bnd_ndr1_0 & bnd_c1_1 bnd_a420) & bnd_c5_1 bnd_a420) &
% 19.04/18.60 bnd_ndr1_1 bnd_a420) &
% 19.04/18.60 ~ bnd_c1_2 bnd_a420 bnd_a421) &
% 19.04/18.60 ~ bnd_c8_2 bnd_a420 bnd_a421) |
% 19.04/18.60 ((bnd_ndr1_0 & ~ bnd_c1_1 bnd_a422) & ~ bnd_c10_1 bnd_a422) &
% 19.04/18.60 (ALL X208.
% 19.04/18.60 bnd_ndr1_1 bnd_a422 -->
% 19.04/18.60 (bnd_c3_2 bnd_a422 X208 | bnd_c4_2 bnd_a422 X208) |
% 19.04/18.60 ~ bnd_c6_2 bnd_a422 X208))) &
% 19.04/18.60 ((((bnd_ndr1_0 & bnd_c10_1 bnd_a423) & ~ bnd_c5_1 bnd_a423) &
% 19.04/18.60 ~ bnd_c6_1 bnd_a423 |
% 19.04/18.60 ((bnd_ndr1_0 & bnd_c5_1 bnd_a424) &
% 19.04/18.60 (ALL X209.
% 19.04/18.60 bnd_ndr1_1 bnd_a424 -->
% 19.04/18.60 (~ bnd_c1_2 bnd_a424 X209 | ~ bnd_c2_2 bnd_a424 X209) |
% 19.04/18.60 ~ bnd_c5_2 bnd_a424 X209)) &
% 19.04/18.60 (ALL X210.
% 19.04/18.60 bnd_ndr1_1 bnd_a424 -->
% 19.04/18.60 (~ bnd_c3_2 bnd_a424 X210 | ~ bnd_c6_2 bnd_a424 X210) |
% 19.04/18.60 ~ bnd_c8_2 bnd_a424 X210)) |
% 19.04/18.60 ((((bnd_ndr1_0 & bnd_c7_1 bnd_a425) & ~ bnd_c8_1 bnd_a425) &
% 19.04/18.60 bnd_ndr1_1 bnd_a425) &
% 19.04/18.60 bnd_c5_2 bnd_a425 bnd_a426) &
% 19.04/18.60 bnd_c6_2 bnd_a425 bnd_a426)) &
% 19.04/18.60 (((((bnd_ndr1_0 & bnd_c10_1 bnd_a427) & bnd_ndr1_1 bnd_a427) &
% 19.04/18.60 bnd_c9_2 bnd_a427 bnd_a428) &
% 19.04/18.60 ~ bnd_c10_2 bnd_a427 bnd_a428) &
% 19.04/18.60 ~ bnd_c7_2 bnd_a427 bnd_a428 |
% 19.04/18.60 (((((bnd_ndr1_0 & bnd_c2_1 bnd_a429) & ~ bnd_c8_1 bnd_a429) &
% 19.04/18.60 bnd_ndr1_1 bnd_a429) &
% 19.04/18.60 bnd_c1_2 bnd_a429 bnd_a430) &
% 19.04/18.60 bnd_c2_2 bnd_a429 bnd_a430) &
% 19.04/18.60 bnd_c5_2 bnd_a429 bnd_a430))
% 19.04/18.60 Adding axioms...
% 19.15/18.63 Typedef.type_definition_def
% 55.90/55.37 ...done.
% 56.00/55.41 Ground types: ?'b, TPTP_Interpret.ind
% 56.00/55.41 Translating term (sizes: 1, 1) ...
% 86.30/85.67 Invoking SAT solver...
% 86.30/85.67 No model exists.
% 86.30/85.67 Translating term (sizes: 2, 1) ...
% 117.43/116.66 Invoking SAT solver...
% 117.43/116.66 No model exists.
% 117.43/116.66 Translating term (sizes: 1, 2) ...
% 175.38/174.40 Invoking SAT solver...
% 176.08/175.05 Model found:
% 176.08/175.05 Size of types: ?'b: 1, TPTP_Interpret.ind: 2
% 176.08/175.05 bnd_a430: ??.TPTP_Interpret.ind1
% 176.08/175.05 bnd_a429: ??.TPTP_Interpret.ind1
% 176.08/175.05 bnd_a428: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a427: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a426: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a425: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a424: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a423: ??.TPTP_Interpret.ind1
% 176.08/175.05 bnd_a422: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a421: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a420: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a419: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a418: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a417: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a416: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a415: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a414: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a413: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a412: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a411: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a410: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a409: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a408: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a407: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a406: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a405: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a404: ??.TPTP_Interpret.ind1
% 176.08/175.05 bnd_a403: ??.TPTP_Interpret.ind1
% 176.08/175.05 bnd_a402: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a401: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a400: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a399: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a398: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a397: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a396: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a395: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a394: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a393: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a392: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a391: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a390: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a389: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a388: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a387: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a386: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a385: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a384: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a383: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a382: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a381: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a380: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a379: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a378: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a377: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a376: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a375: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a374: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a373: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a372: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a371: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a370: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a369: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a368: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a367: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a366: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a365: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a364: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a363: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a362: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a361: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a360: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a359: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a358: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a357: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a356: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a355: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a354: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a353: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a352: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a351: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a350: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a349: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a348: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a347: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a346: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a345: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a344: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a343: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a342: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a341: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a340: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a339: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a338: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a337: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a336: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a335: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a334: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a333: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a332: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a331: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a330: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a329: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a328: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a327: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a326: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a325: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a324: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a323: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a322: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a321: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a320: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a319: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a318: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a317: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a316: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a315: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a314: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a313: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a312: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a311: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a310: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a309: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a308: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a307: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a306: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a305: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a304: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a303: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a302: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a301: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a300: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a299: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a298: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a297: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a296: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a295: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a294: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a293: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a292: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a291: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a290: ??.TPTP_Interpret.ind1
% 176.08/175.05 bnd_a289: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a288: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a287: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a286: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a285: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a284: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a283: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a282: ??.TPTP_Interpret.ind1
% 176.08/175.05 bnd_a281: ??.TPTP_Interpret.ind1
% 176.08/175.05 bnd_a280: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a279: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a278: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a277: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a276: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a275: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a274: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a273: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a272: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a271: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a270: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a269: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a268: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a267: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a266: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a265: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a264: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a263: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a262: ??.TPTP_Interpret.ind1
% 176.08/175.05 bnd_a261: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a260: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a259: ??.TPTP_Interpret.ind1
% 176.08/175.05 bnd_a258: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a257: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a256: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a255: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a254: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a253: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a252: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a251: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a250: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_c6_0: False
% 176.08/175.05 bnd_a249: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a248: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a247: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a246: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a245: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a244: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a243: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a242: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a241: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a240: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a239: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_c2_1: {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, True)}
% 176.08/175.05 bnd_a238: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a237: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a236: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a235: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a234: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_c6_1: {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, False)}
% 176.08/175.05 bnd_a233: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a232: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a231: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_c2_0: True
% 176.08/175.05 bnd_a230: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a229: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_c4_1: {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, False)}
% 176.08/175.05 bnd_a228: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_c8_1: {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, False)}
% 176.08/175.05 bnd_c10_1: {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, True)}
% 176.08/175.05 bnd_a227: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_c4_2: {(??.TPTP_Interpret.ind0,
% 176.08/175.05 {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, False)}),
% 176.08/175.05 (??.TPTP_Interpret.ind1,
% 176.08/175.05 {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, False)})}
% 176.08/175.05 bnd_a226: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_a225: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_c5_1: {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, False)}
% 176.08/175.05 bnd_a224: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_c9_2: {(??.TPTP_Interpret.ind0,
% 176.08/175.05 {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, False)}),
% 176.08/175.05 (??.TPTP_Interpret.ind1,
% 176.08/175.05 {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, False)})}
% 176.08/175.05 bnd_a223: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_c9_1: {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, True)}
% 176.08/175.05 bnd_a222: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_c7_0: False
% 176.08/175.05 bnd_c8_2: {(??.TPTP_Interpret.ind0,
% 176.08/175.05 {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, False)}),
% 176.08/175.05 (??.TPTP_Interpret.ind1,
% 176.08/175.05 {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, True)})}
% 176.08/175.05 bnd_c1_1: {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, True)}
% 176.08/175.05 bnd_c9_0: False
% 176.08/175.05 bnd_c7_2: {(??.TPTP_Interpret.ind0,
% 176.08/175.05 {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, True)}),
% 176.08/175.05 (??.TPTP_Interpret.ind1,
% 176.08/175.05 {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, True)})}
% 176.08/175.05 bnd_a221: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_c6_2: {(??.TPTP_Interpret.ind0,
% 176.08/175.05 {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, True)}),
% 176.08/175.05 (??.TPTP_Interpret.ind1,
% 176.08/175.05 {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, True)})}
% 176.08/175.05 bnd_c1_2: {(??.TPTP_Interpret.ind0,
% 176.08/175.05 {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, False)}),
% 176.08/175.05 (??.TPTP_Interpret.ind1,
% 176.08/175.05 {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, True)})}
% 176.08/175.05 bnd_a220: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_c2_2: {(??.TPTP_Interpret.ind0,
% 176.08/175.05 {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, True)}),
% 176.08/175.05 (??.TPTP_Interpret.ind1,
% 176.08/175.05 {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, True)})}
% 176.08/175.05 bnd_c5_2: {(??.TPTP_Interpret.ind0,
% 176.08/175.05 {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, False)}),
% 176.08/175.05 (??.TPTP_Interpret.ind1,
% 176.08/175.05 {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, True)})}
% 176.08/175.05 bnd_c10_2: {(??.TPTP_Interpret.ind0,
% 176.08/175.05 {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, True)}),
% 176.08/175.05 (??.TPTP_Interpret.ind1,
% 176.08/175.05 {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, True)})}
% 176.08/175.05 bnd_c3_2: {(??.TPTP_Interpret.ind0,
% 176.08/175.05 {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, False)}),
% 176.08/175.05 (??.TPTP_Interpret.ind1,
% 176.08/175.05 {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, False)})}
% 176.08/175.05 bnd_a219: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_ndr1_1: {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, True)}
% 176.08/175.05 bnd_c10_0: False
% 176.08/175.05 bnd_c8_0: True
% 176.08/175.05 bnd_c4_0: True
% 176.08/175.05 bnd_c7_1: {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, True)}
% 176.08/175.05 bnd_a218: ??.TPTP_Interpret.ind0
% 176.08/175.05 bnd_c3_1: {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, True)}
% 176.08/175.05 bnd_ndr1_0: True
% 176.08/175.05 bnd_c3_0: True
% 176.08/175.05 bnd_c1_0: False
% 176.08/175.05 bnd_c5_0: False
% 176.08/175.05
% 176.08/175.05 % SZS status CounterSatisfiable
%------------------------------------------------------------------------------