TSTP Solution File: SYN424+1 by Refute---2015
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%------------------------------------------------------------------------------
% File : Refute---2015
% Problem : SYN424+1 : TPTP v6.4.0. Released v2.1.0.
% Transfm : none
% Format : tptp:raw
% Command : isabelle tptp_refute %d %s
% Computer : n071.star.cs.uiowa.edu
% Model : x86_64 x86_64
% CPU : Intel(R) Xeon(R) CPU E5-2609 0 2.40GHz
% Memory : 32218.75MB
% OS : Linux 3.10.0-327.10.1.el7.x86_64
% CPULimit : 300s
% DateTime : Thu Apr 14 06:41:43 EDT 2016
% Result : CounterSatisfiable 192.45s
% Output : Assurance 0s
% Verified :
% SZS Type : None (Parsing solution fails)
% Syntax : Number of formulae : 0
% Comments :
%------------------------------------------------------------------------------
%----No solution output by system
%------------------------------------------------------------------------------
%----ORIGINAL SYSTEM OUTPUT
% 0.00/0.03 % Problem : SYN424+1 : TPTP v6.4.0. Released v2.1.0.
% 0.00/0.04 % Command : isabelle tptp_refute %d %s
% 0.03/0.23 % Computer : n071.star.cs.uiowa.edu
% 0.03/0.23 % Model : x86_64 x86_64
% 0.03/0.23 % CPU : Intel(R) Xeon(R) CPU E5-2609 0 @ 2.40GHz
% 0.03/0.23 % Memory : 32218.75MB
% 0.03/0.23 % OS : Linux 3.10.0-327.10.1.el7.x86_64
% 0.03/0.23 % CPULimit : 300
% 0.03/0.23 % DateTime : Fri Apr 8 23:49:54 CDT 2016
% 0.03/0.23 % CPUTime:
% 6.30/5.83 > val it = (): unit
% 7.40/6.93 Trying to find a model that refutes: ~ ((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((bnd_ndr1_0 &
% 7.40/6.93 bnd_ndr1_1 bnd_a960) &
% 7.40/6.93 ~ bnd_c10_2 bnd_a960 bnd_a961) &
% 7.40/6.93 ~ bnd_c1_2 bnd_a960 bnd_a961) &
% 7.40/6.93 ~ bnd_c5_2 bnd_a960 bnd_a961) &
% 7.40/6.93 ~ bnd_c6_1 bnd_a960 |
% 7.40/6.93 ((bnd_ndr1_0 &
% 7.40/6.93 (ALL U.
% 7.40/6.93 bnd_ndr1_1 bnd_a962 -->
% 7.40/6.93 (~ bnd_c7_2 bnd_a962 U | ~ bnd_c5_2 bnd_a962 U) |
% 7.40/6.93 bnd_c8_2 bnd_a962 U)) &
% 7.40/6.93 (ALL V.
% 7.40/6.93 bnd_ndr1_1 bnd_a962 -->
% 7.40/6.93 (~ bnd_c7_2 bnd_a962 V | bnd_c1_2 bnd_a962 V) |
% 7.40/6.93 ~ bnd_c3_2 bnd_a962 V)) &
% 7.40/6.93 (ALL W.
% 7.40/6.93 bnd_ndr1_1 bnd_a962 -->
% 7.40/6.93 (bnd_c7_2 bnd_a962 W | bnd_c9_2 bnd_a962 W) |
% 7.40/6.93 bnd_c10_2 bnd_a962 W)) |
% 7.40/6.93 ~ bnd_c5_0) &
% 7.40/6.93 ((((((bnd_ndr1_0 & ~ bnd_c6_1 bnd_a963) &
% 7.40/6.93 (ALL X.
% 7.40/6.93 bnd_ndr1_1 bnd_a963 -->
% 7.40/6.93 (bnd_c9_2 bnd_a963 X | bnd_c10_2 bnd_a963 X) |
% 7.40/6.93 bnd_c3_2 bnd_a963 X)) &
% 7.40/6.93 bnd_ndr1_1 bnd_a963) &
% 7.40/6.93 bnd_c1_2 bnd_a963 bnd_a964) &
% 7.40/6.93 bnd_c4_2 bnd_a963 bnd_a964) &
% 7.40/6.93 ~ bnd_c5_2 bnd_a963 bnd_a964 |
% 7.40/6.93 ~ bnd_c2_0)) &
% 7.40/6.93 ((~ bnd_c3_0 |
% 7.40/6.93 (ALL Y.
% 7.40/6.93 bnd_ndr1_0 -->
% 7.40/6.93 ((ALL Z.
% 7.40/6.93 bnd_ndr1_1 Y -->
% 7.40/6.93 (~ bnd_c4_2 Y Z | ~ bnd_c2_2 Y Z) | bnd_c6_2 Y Z) |
% 7.40/6.93 (ALL X1.
% 7.40/6.93 bnd_ndr1_1 Y -->
% 7.40/6.93 bnd_c10_2 Y X1 | ~ bnd_c6_2 Y X1)) |
% 7.40/6.93 ((bnd_ndr1_1 Y & ~ bnd_c4_2 Y bnd_a965) &
% 7.40/6.93 bnd_c10_2 Y bnd_a965) &
% 7.40/6.93 ~ bnd_c1_2 Y bnd_a965)) |
% 7.40/6.93 ~ bnd_c9_0)) &
% 7.40/6.93 ((((bnd_ndr1_0 & ~ bnd_c9_1 bnd_a966) & ~ bnd_c4_1 bnd_a966) &
% 7.40/6.93 bnd_c6_1 bnd_a966 |
% 7.40/6.93 bnd_c7_0) |
% 7.40/6.93 (((((bnd_ndr1_0 & ~ bnd_c3_1 bnd_a967) & bnd_c4_1 bnd_a967) &
% 7.40/6.93 bnd_ndr1_1 bnd_a967) &
% 7.40/6.93 bnd_c1_2 bnd_a967 bnd_a968) &
% 7.40/6.93 ~ bnd_c8_2 bnd_a967 bnd_a968) &
% 7.40/6.93 bnd_c6_2 bnd_a967 bnd_a968)) &
% 7.40/6.93 ((~ bnd_c6_0 | bnd_c3_0) |
% 7.40/6.93 (ALL X2.
% 7.40/6.93 bnd_ndr1_0 -->
% 7.40/6.93 (bnd_c9_1 X2 | ~ bnd_c3_1 X2) |
% 7.40/6.93 ((bnd_ndr1_1 X2 & ~ bnd_c5_2 X2 bnd_a969) &
% 7.40/6.93 bnd_c8_2 X2 bnd_a969) &
% 7.40/6.93 bnd_c10_2 X2 bnd_a969))) &
% 7.40/6.93 ((((bnd_ndr1_0 &
% 7.40/6.93 (ALL X3.
% 7.40/6.93 bnd_ndr1_1 bnd_a970 -->
% 7.40/6.93 (bnd_c10_2 bnd_a970 X3 | ~ bnd_c1_2 bnd_a970 X3) |
% 7.40/6.93 bnd_c5_2 bnd_a970 X3)) &
% 7.40/6.93 bnd_c5_1 bnd_a970) &
% 7.40/6.93 ~ bnd_c2_1 bnd_a970 |
% 7.40/6.93 ((bnd_ndr1_0 & ~ bnd_c9_1 bnd_a971) &
% 7.40/6.93 (ALL X4.
% 7.40/6.93 bnd_ndr1_1 bnd_a971 -->
% 7.40/6.93 (bnd_c8_2 bnd_a971 X4 | bnd_c1_2 bnd_a971 X4) |
% 7.40/6.93 ~ bnd_c7_2 bnd_a971 X4)) &
% 7.40/6.93 ~ bnd_c4_1 bnd_a971) |
% 7.40/6.93 (ALL X5.
% 7.40/6.93 bnd_ndr1_0 -->
% 7.40/6.93 bnd_c9_1 X5 |
% 7.40/6.93 (ALL X6.
% 7.40/6.93 bnd_ndr1_1 X5 -->
% 7.40/6.93 (bnd_c6_2 X5 X6 | ~ bnd_c5_2 X5 X6) |
% 7.40/6.93 ~ bnd_c4_2 X5 X6)))) &
% 7.40/6.93 ((~ bnd_c5_0 |
% 7.40/6.93 (bnd_ndr1_0 & bnd_c7_1 bnd_a972) &
% 7.40/6.93 (ALL X7.
% 7.40/6.93 bnd_ndr1_1 bnd_a972 -->
% 7.40/6.93 (bnd_c7_2 bnd_a972 X7 | bnd_c8_2 bnd_a972 X7) |
% 7.40/6.93 ~ bnd_c4_2 bnd_a972 X7)) |
% 7.40/6.93 ((bnd_ndr1_0 & ~ bnd_c1_1 bnd_a973) &
% 7.40/6.93 (ALL X8.
% 7.40/6.93 bnd_ndr1_1 bnd_a973 -->
% 7.40/6.93 ~ bnd_c7_2 bnd_a973 X8 | ~ bnd_c1_2 bnd_a973 X8)) &
% 7.40/6.93 bnd_c9_1 bnd_a973)) &
% 7.40/6.93 ((~ bnd_c8_0 |
% 7.40/6.93 (ALL X9.
% 7.40/6.93 bnd_ndr1_0 -->
% 7.40/6.93 (bnd_c6_1 X9 | bnd_c1_1 X9) |
% 7.40/6.93 ((bnd_ndr1_1 X9 & ~ bnd_c9_2 X9 bnd_a974) &
% 7.40/6.93 ~ bnd_c4_2 X9 bnd_a974) &
% 7.40/6.93 bnd_c1_2 X9 bnd_a974)) |
% 7.40/6.93 (ALL X10.
% 7.40/6.93 bnd_ndr1_0 -->
% 7.40/6.93 (((bnd_ndr1_1 X10 & ~ bnd_c9_2 X10 bnd_a975) &
% 7.40/6.93 bnd_c8_2 X10 bnd_a975) &
% 7.40/6.93 ~ bnd_c7_2 X10 bnd_a975 |
% 7.40/6.93 ~ bnd_c1_1 X10) |
% 7.40/6.93 bnd_c6_1 X10))) &
% 7.40/6.93 ((~ bnd_c3_0 |
% 7.40/6.93 (ALL X11.
% 7.40/6.93 bnd_ndr1_0 -->
% 7.40/6.93 (((bnd_ndr1_1 X11 & ~ bnd_c1_2 X11 bnd_a976) &
% 7.40/6.93 bnd_c8_2 X11 bnd_a976) &
% 7.40/6.93 ~ bnd_c6_2 X11 bnd_a976 |
% 7.40/6.93 bnd_c2_1 X11) |
% 7.40/6.93 bnd_c7_1 X11)) |
% 7.40/6.93 ((bnd_ndr1_0 & bnd_c9_1 bnd_a977) & ~ bnd_c1_1 bnd_a977) &
% 7.40/6.93 (ALL X12.
% 7.40/6.93 bnd_ndr1_1 bnd_a977 -->
% 7.40/6.93 (bnd_c5_2 bnd_a977 X12 | ~ bnd_c1_2 bnd_a977 X12) |
% 7.40/6.93 ~ bnd_c9_2 bnd_a977 X12))) &
% 7.40/6.93 ((bnd_c1_0 |
% 7.40/6.93 ((bnd_ndr1_0 & ~ bnd_c3_1 bnd_a978) & bnd_c8_1 bnd_a978) &
% 7.40/6.93 (ALL X13.
% 7.40/6.93 bnd_ndr1_1 bnd_a978 -->
% 7.40/6.93 ~ bnd_c6_2 bnd_a978 X13 | bnd_c4_2 bnd_a978 X13)) |
% 7.40/6.93 bnd_c6_0)) &
% 7.40/6.93 ((bnd_c6_0 |
% 7.40/6.93 (ALL X14.
% 7.40/6.93 bnd_ndr1_0 -->
% 7.40/6.93 (bnd_c2_1 X14 | ~ bnd_c3_1 X14) |
% 7.40/6.93 ((bnd_ndr1_1 X14 & ~ bnd_c5_2 X14 bnd_a979) &
% 7.40/6.93 bnd_c7_2 X14 bnd_a979) &
% 7.40/6.93 ~ bnd_c2_2 X14 bnd_a979)) |
% 7.40/6.93 ~ bnd_c4_0)) &
% 7.40/6.93 (~ bnd_c5_0 |
% 7.40/6.93 (((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a980) & bnd_c6_2 bnd_a980 bnd_a981) &
% 7.40/6.93 ~ bnd_c4_2 bnd_a980 bnd_a981) &
% 7.40/6.93 bnd_c5_2 bnd_a980 bnd_a981) &
% 7.40/6.93 ~ bnd_c7_1 bnd_a980) &
% 7.40/6.93 (ALL X15.
% 7.40/6.93 bnd_ndr1_1 bnd_a980 -->
% 7.40/6.93 bnd_c1_2 bnd_a980 X15 | bnd_c3_2 bnd_a980 X15))) &
% 7.40/6.93 (((ALL X16.
% 7.40/6.93 bnd_ndr1_0 -->
% 7.40/6.93 ((ALL X17.
% 7.40/6.93 bnd_ndr1_1 X16 --> bnd_c2_2 X16 X17 | bnd_c5_2 X16 X17) |
% 7.40/6.93 ((bnd_ndr1_1 X16 & ~ bnd_c6_2 X16 bnd_a982) &
% 7.40/6.93 ~ bnd_c10_2 X16 bnd_a982) &
% 7.40/6.93 bnd_c2_2 X16 bnd_a982) |
% 7.40/6.93 ~ bnd_c1_1 X16) |
% 7.40/6.93 bnd_c3_0) |
% 7.40/6.93 ~ bnd_c8_0)) &
% 7.40/6.93 (((ALL X18.
% 7.40/6.93 bnd_ndr1_0 -->
% 7.40/6.93 (~ bnd_c2_1 X18 | bnd_c1_1 X18) |
% 7.40/6.93 ((bnd_ndr1_1 X18 & ~ bnd_c2_2 X18 bnd_a983) &
% 7.40/6.93 ~ bnd_c4_2 X18 bnd_a983) &
% 7.40/6.93 bnd_c10_2 X18 bnd_a983) |
% 7.40/6.93 ~ bnd_c5_0) |
% 7.40/6.93 bnd_c9_0)) &
% 7.40/6.93 ((bnd_c4_0 | bnd_c8_0) | bnd_c5_0)) &
% 7.40/6.93 ((ALL X19.
% 7.40/6.93 bnd_ndr1_0 -->
% 7.40/6.93 (bnd_c3_1 X19 |
% 7.40/6.93 ((bnd_ndr1_1 X19 & bnd_c10_2 X19 bnd_a984) & bnd_c6_2 X19 bnd_a984) &
% 7.40/6.93 ~ bnd_c7_2 X19 bnd_a984) |
% 7.40/6.93 bnd_c6_1 X19) |
% 7.40/6.93 (ALL X20.
% 7.40/6.93 bnd_ndr1_0 -->
% 7.40/6.93 ~ bnd_c6_1 X20 |
% 7.40/6.93 (ALL X21.
% 7.40/6.93 bnd_ndr1_1 X20 -->
% 7.40/6.93 (bnd_c2_2 X20 X21 | ~ bnd_c5_2 X20 X21) | bnd_c6_2 X20 X21)))) &
% 7.40/6.93 ((~ bnd_c10_0 |
% 7.40/6.93 (ALL X22.
% 7.40/6.93 bnd_ndr1_0 -->
% 7.40/6.93 (bnd_c5_1 X22 |
% 7.40/6.93 (ALL X23.
% 7.40/6.93 bnd_ndr1_1 X22 -->
% 7.40/6.93 (bnd_c10_2 X22 X23 | bnd_c7_2 X22 X23) | ~ bnd_c8_2 X22 X23)) |
% 7.40/6.93 bnd_c9_1 X22)) |
% 7.40/6.93 (ALL X24.
% 7.40/6.93 bnd_ndr1_0 -->
% 7.40/6.93 ((ALL X25.
% 7.40/6.93 bnd_ndr1_1 X24 -->
% 7.40/6.93 (~ bnd_c4_2 X24 X25 | bnd_c10_2 X24 X25) | bnd_c3_2 X24 X25) |
% 7.40/6.93 ((bnd_ndr1_1 X24 & bnd_c5_2 X24 bnd_a985) & ~ bnd_c3_2 X24 bnd_a985) &
% 7.40/6.93 bnd_c4_2 X24 bnd_a985) |
% 7.40/6.93 bnd_c10_1 X24))) &
% 7.40/6.93 (bnd_c5_0 | ~ bnd_c8_0)) &
% 7.40/6.93 ((~ bnd_c10_0 |
% 7.40/6.93 (((((bnd_ndr1_0 &
% 7.40/6.93 bnd_ndr1_1 bnd_a986) &
% 7.40/6.93 ~ bnd_c1_2 bnd_a986 bnd_a987) &
% 7.40/6.93 ~ bnd_c9_2 bnd_a986 bnd_a987) &
% 7.40/6.93 bnd_c3_2 bnd_a986 bnd_a987) &
% 7.40/6.93 ~ bnd_c5_1 bnd_a986) &
% 7.40/6.93 ~ bnd_c2_1 bnd_a986) |
% 7.40/6.93 ~ bnd_c5_0)) &
% 7.40/6.93 (((ALL X26.
% 7.40/6.93 bnd_ndr1_0 -->
% 7.40/6.93 (((bnd_ndr1_1 X26 & ~ bnd_c5_2 X26 bnd_a988) & bnd_c10_2 X26 bnd_a988) &
% 7.40/6.93 bnd_c1_2 X26 bnd_a988 |
% 7.40/6.93 ((bnd_ndr1_1 X26 & ~ bnd_c6_2 X26 bnd_a989) & ~ bnd_c8_2 X26 bnd_a989) &
% 7.40/6.93 bnd_c9_2 X26 bnd_a989) |
% 7.40/6.93 ~ bnd_c6_1 X26) |
% 7.40/6.93 bnd_c3_0) |
% 7.40/6.93 bnd_c5_0)) &
% 7.40/6.93 (((ALL X27.
% 7.40/6.93 bnd_ndr1_0 -->
% 7.40/6.93 ((ALL X28.
% 7.40/6.93 bnd_ndr1_1 X27 -->
% 7.40/6.93 (~ bnd_c7_2 X27 X28 | bnd_c3_2 X27 X28) | ~ bnd_c2_2 X27 X28) |
% 7.40/6.93 ~ bnd_c1_1 X27) |
% 7.40/6.93 ((bnd_ndr1_1 X27 & ~ bnd_c8_2 X27 bnd_a990) & ~ bnd_c7_2 X27 bnd_a990) &
% 7.40/6.93 ~ bnd_c10_2 X27 bnd_a990) |
% 7.40/6.93 ~ bnd_c2_0) |
% 7.40/6.93 (ALL X29.
% 7.40/6.93 bnd_ndr1_0 -->
% 7.40/6.93 ((ALL X30.
% 7.40/6.93 bnd_ndr1_1 X29 -->
% 7.40/6.93 (~ bnd_c1_2 X29 X30 | ~ bnd_c8_2 X29 X30) | bnd_c3_2 X29 X30) |
% 7.40/6.93 (ALL X31.
% 7.40/6.93 bnd_ndr1_1 X29 -->
% 7.40/6.93 (bnd_c3_2 X29 X31 | bnd_c7_2 X29 X31) | bnd_c1_2 X29 X31)) |
% 7.40/6.93 ~ bnd_c8_1 X29))) &
% 7.40/6.93 (((ALL X32.
% 7.40/6.93 bnd_ndr1_0 -->
% 7.40/6.93 (~ bnd_c10_1 X32 | ~ bnd_c3_1 X32) |
% 7.40/6.93 (ALL X33.
% 7.40/6.93 bnd_ndr1_1 X32 -->
% 7.40/6.93 (bnd_c6_2 X32 X33 | bnd_c1_2 X32 X33) | bnd_c10_2 X32 X33)) |
% 7.40/6.93 ~ bnd_c4_0) |
% 7.40/6.93 bnd_c9_0)) &
% 7.40/6.93 ((bnd_c3_0 |
% 7.40/6.93 (ALL X34.
% 7.40/6.93 bnd_ndr1_0 -->
% 7.40/6.93 ((ALL X35.
% 7.40/6.93 bnd_ndr1_1 X34 -->
% 7.40/6.93 (~ bnd_c8_2 X34 X35 | ~ bnd_c7_2 X34 X35) | bnd_c2_2 X34 X35) |
% 7.40/6.93 ~ bnd_c9_1 X34) |
% 7.40/6.93 bnd_c3_1 X34)) |
% 7.40/6.93 ~ bnd_c1_0)) &
% 7.40/6.93 ((bnd_c9_0 |
% 7.40/6.93 (ALL X36.
% 7.40/6.93 bnd_ndr1_0 -->
% 7.40/6.93 ((ALL X37.
% 7.40/6.93 bnd_ndr1_1 X36 -->
% 7.40/6.93 (~ bnd_c7_2 X36 X37 | ~ bnd_c6_2 X36 X37) | bnd_c5_2 X36 X37) |
% 7.40/6.93 bnd_c5_1 X36) |
% 7.40/6.93 bnd_c4_1 X36)) |
% 7.40/6.93 (ALL X38.
% 7.40/6.93 bnd_ndr1_0 -->
% 7.40/6.93 (~ bnd_c9_1 X38 | bnd_c2_1 X38) |
% 7.40/6.93 bnd_c6_1 X38))) &
% 7.40/6.93 (~ bnd_c3_0 | bnd_c7_0)) &
% 7.40/6.93 (((ALL X39.
% 7.40/6.93 bnd_ndr1_0 -->
% 7.40/6.93 (~ bnd_c6_1 X39 |
% 7.40/6.93 (ALL X40.
% 7.40/6.93 bnd_ndr1_1 X39 -->
% 7.40/6.93 (~ bnd_c7_2 X39 X40 | ~ bnd_c3_2 X39 X40) | ~ bnd_c5_2 X39 X40)) |
% 7.40/6.93 ~ bnd_c7_1 X39) |
% 7.40/6.93 ~ bnd_c8_0) |
% 7.40/6.93 (ALL X41.
% 7.40/6.93 bnd_ndr1_0 -->
% 7.40/6.93 ((ALL X42.
% 7.40/6.93 bnd_ndr1_1 X41 --> bnd_c10_2 X41 X42 | bnd_c9_2 X41 X42) |
% 7.40/6.93 ~ bnd_c8_1 X41) |
% 7.40/6.93 (ALL X43.
% 7.40/6.93 bnd_ndr1_1 X41 -->
% 7.40/6.93 (bnd_c2_2 X41 X43 |
% 7.40/6.93 ~ bnd_c7_2 X41 X43) |
% 7.40/6.93 bnd_c4_2 X41 X43)))) &
% 7.40/6.93 ((((bnd_ndr1_0 & ~ bnd_c3_1 bnd_a991) &
% 7.40/6.93 ~ bnd_c1_1 bnd_a991) &
% 7.40/6.93 ~ bnd_c7_1 bnd_a991 |
% 7.40/6.93 (((((((bnd_ndr1_0 &
% 7.40/6.93 (ALL X44.
% 7.40/6.93 bnd_ndr1_1 bnd_a992 -->
% 7.40/6.93 (bnd_c9_2 bnd_a992 X44 | bnd_c6_2 bnd_a992 X44) |
% 7.40/6.93 bnd_c4_2 bnd_a992 X44)) &
% 7.40/6.93 bnd_ndr1_1 bnd_a992) &
% 7.40/6.93 bnd_c6_2 bnd_a992 bnd_a993) &
% 7.40/6.93 ~ bnd_c7_2 bnd_a992 bnd_a993) &
% 7.40/6.93 ~ bnd_c9_2 bnd_a992 bnd_a993) &
% 7.40/6.93 bnd_ndr1_1 bnd_a992) &
% 7.40/6.93 bnd_c7_2 bnd_a992 bnd_a994) &
% 7.40/6.93 ~ bnd_c8_2 bnd_a992 bnd_a994) |
% 7.40/6.93 (bnd_ndr1_0 &
% 7.40/6.93 (ALL X45.
% 7.40/6.93 bnd_ndr1_1 bnd_a995 -->
% 7.40/6.93 bnd_c1_2 bnd_a995 X45 |
% 7.40/6.93 ~ bnd_c9_2 bnd_a995 X45)) &
% 7.40/6.93 (ALL X46.
% 7.40/6.93 bnd_ndr1_1 bnd_a995 -->
% 7.40/6.93 (~ bnd_c9_2 bnd_a995 X46 |
% 7.40/6.93 ~ bnd_c7_2 bnd_a995 X46) |
% 7.40/6.93 ~ bnd_c8_2 bnd_a995 X46))) &
% 7.40/6.93 (((ALL X47.
% 7.40/6.93 bnd_ndr1_0 -->
% 7.40/6.93 ((bnd_ndr1_1 X47 & bnd_c6_2 X47 bnd_a996) &
% 7.40/6.93 bnd_c3_2 X47 bnd_a996 |
% 7.40/6.93 (ALL X48.
% 7.40/6.93 bnd_ndr1_1 X47 -->
% 7.40/6.93 (bnd_c6_2 X47 X48 |
% 7.40/6.93 ~ bnd_c1_2 X47 X48) |
% 7.40/6.93 bnd_c7_2 X47 X48)) |
% 7.40/6.93 (ALL X49.
% 7.40/6.93 bnd_ndr1_1 X47 -->
% 7.40/6.93 (bnd_c4_2 X47 X49 | bnd_c1_2 X47 X49) |
% 7.40/6.93 ~ bnd_c9_2 X47 X49)) |
% 7.40/6.93 ~ bnd_c8_0) |
% 7.40/6.93 ~ bnd_c5_0)) &
% 7.40/6.93 (((ALL X50.
% 7.40/6.93 bnd_ndr1_0 -->
% 7.40/6.93 (bnd_c4_1 X50 | ~ bnd_c2_1 X50) |
% 7.40/6.93 ~ bnd_c7_1 X50) |
% 7.40/6.93 (((((bnd_ndr1_0 &
% 7.40/6.93 (ALL X51.
% 7.40/6.93 bnd_ndr1_1 bnd_a997 -->
% 7.40/6.93 (~ bnd_c3_2 bnd_a997 X51 |
% 7.40/6.93 bnd_c4_2 bnd_a997 X51) |
% 7.40/6.93 bnd_c6_2 bnd_a997 X51)) &
% 7.40/6.93 bnd_c5_1 bnd_a997) &
% 7.40/6.93 bnd_ndr1_1 bnd_a997) &
% 7.40/6.93 bnd_c3_2 bnd_a997 bnd_a998) &
% 7.40/6.93 ~ bnd_c5_2 bnd_a997 bnd_a998) &
% 7.40/6.93 bnd_c9_2 bnd_a997 bnd_a998) |
% 7.40/6.93 (ALL X52.
% 7.40/6.93 bnd_ndr1_0 -->
% 7.40/6.93 ((bnd_ndr1_1 X52 & ~ bnd_c2_2 X52 bnd_a999) &
% 7.40/6.93 bnd_c3_2 X52 bnd_a999 |
% 7.40/6.93 ~ bnd_c9_1 X52) |
% 7.40/6.93 (ALL X53.
% 7.40/6.93 bnd_ndr1_1 X52 -->
% 7.40/6.93 (bnd_c6_2 X52 X53 | ~ bnd_c5_2 X52 X53) |
% 7.40/6.93 ~ bnd_c3_2 X52 X53)))) &
% 7.40/6.93 (((ALL X54.
% 7.40/6.93 bnd_ndr1_0 -->
% 7.40/6.93 ((bnd_ndr1_1 X54 & ~ bnd_c6_2 X54 bnd_a1000) &
% 7.40/6.93 ~ bnd_c2_2 X54 bnd_a1000 |
% 7.40/6.93 (ALL X55.
% 7.40/6.93 bnd_ndr1_1 X54 -->
% 7.40/6.93 (bnd_c10_2 X54 X55 |
% 7.40/6.93 ~ bnd_c6_2 X54 X55) |
% 7.40/6.93 ~ bnd_c7_2 X54 X55)) |
% 7.40/6.93 bnd_c4_1 X54) |
% 7.40/6.93 ~ bnd_c10_0) |
% 7.40/6.93 (ALL X56.
% 7.40/6.93 bnd_ndr1_0 -->
% 7.40/6.93 ((ALL X57.
% 7.40/6.93 bnd_ndr1_1 X56 -->
% 7.40/6.93 (bnd_c9_2 X56 X57 | bnd_c10_2 X56 X57) |
% 7.40/6.93 ~ bnd_c6_2 X56 X57) |
% 7.40/6.93 ((bnd_ndr1_1 X56 & bnd_c8_2 X56 bnd_a1001) &
% 7.40/6.93 bnd_c4_2 X56 bnd_a1001) &
% 7.40/6.93 bnd_c10_2 X56 bnd_a1001) |
% 7.40/6.93 ~ bnd_c8_1 X56))) &
% 7.40/6.93 ((bnd_c3_0 |
% 7.40/6.93 (ALL X58.
% 7.40/6.93 bnd_ndr1_0 -->
% 7.40/6.93 (((bnd_ndr1_1 X58 & bnd_c1_2 X58 bnd_a1002) &
% 7.40/6.93 ~ bnd_c5_2 X58 bnd_a1002) &
% 7.40/6.93 bnd_c7_2 X58 bnd_a1002 |
% 7.40/6.93 ~ bnd_c2_1 X58) |
% 7.40/6.93 ~ bnd_c6_1 X58)) |
% 7.40/6.93 (ALL X59.
% 7.40/6.93 bnd_ndr1_0 -->
% 7.40/6.93 ~ bnd_c1_1 X59 | bnd_c3_1 X59))) &
% 7.40/6.93 ((((((bnd_ndr1_0 & bnd_c2_1 bnd_a1003) &
% 7.40/6.93 bnd_ndr1_1 bnd_a1003) &
% 7.40/6.93 ~ bnd_c6_2 bnd_a1003 bnd_a1004) &
% 7.40/6.93 bnd_c1_2 bnd_a1003 bnd_a1004) &
% 7.40/6.93 ~ bnd_c1_1 bnd_a1003 |
% 7.40/6.93 ((((bnd_ndr1_0 & ~ bnd_c1_1 bnd_a1005) &
% 7.40/6.93 bnd_c6_1 bnd_a1005) &
% 7.40/6.93 bnd_ndr1_1 bnd_a1005) &
% 7.40/6.93 bnd_c2_2 bnd_a1005 bnd_a1006) &
% 7.40/6.93 bnd_c5_2 bnd_a1005 bnd_a1006) |
% 7.40/6.93 bnd_ndr1_0 & bnd_c10_1 bnd_a1007)) &
% 7.40/6.93 ((~ bnd_c3_0 | bnd_c4_0) | ~ bnd_c8_0)) &
% 7.40/6.93 ((~ bnd_c7_0 |
% 7.40/6.93 (((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a1008) &
% 7.40/6.93 bnd_c3_2 bnd_a1008 bnd_a1009) &
% 7.40/6.93 bnd_c8_2 bnd_a1008 bnd_a1009) &
% 7.40/6.93 bnd_ndr1_1 bnd_a1008) &
% 7.40/6.93 ~ bnd_c1_2 bnd_a1008 bnd_a1010) &
% 7.40/6.93 ~ bnd_c6_2 bnd_a1008 bnd_a1010) &
% 7.40/6.93 ~ bnd_c2_2 bnd_a1008 bnd_a1010) &
% 7.40/6.93 (ALL X60.
% 7.40/6.93 bnd_ndr1_1 bnd_a1008 -->
% 7.40/6.93 (bnd_c7_2 bnd_a1008 X60 |
% 7.40/6.93 ~ bnd_c4_2 bnd_a1008 X60) |
% 7.40/6.93 bnd_c10_2 bnd_a1008 X60)) |
% 7.40/6.93 ~ bnd_c1_0)) &
% 7.40/6.93 ((bnd_c2_0 | bnd_c7_0) | bnd_c8_0)) &
% 7.40/6.93 (((ALL X61.
% 7.40/6.93 bnd_ndr1_0 -->
% 7.40/6.93 ((ALL X62.
% 7.40/6.93 bnd_ndr1_1 X61 -->
% 7.40/6.93 (bnd_c9_2 X61 X62 | bnd_c1_2 X61 X62) |
% 7.40/6.93 bnd_c4_2 X61 X62) |
% 7.40/6.93 (ALL X63.
% 7.40/6.93 bnd_ndr1_1 X61 -->
% 7.40/6.93 (bnd_c6_2 X61 X63 | ~ bnd_c8_2 X61 X63) |
% 7.40/6.93 bnd_c2_2 X61 X63)) |
% 7.40/6.93 ~ bnd_c5_1 X61) |
% 7.40/6.93 bnd_c1_0) |
% 7.40/6.93 ~ bnd_c5_0)) &
% 7.40/6.93 (((ALL X64.
% 7.40/6.93 bnd_ndr1_0 -->
% 7.40/6.93 (~ bnd_c5_1 X64 |
% 7.40/6.93 (ALL X65.
% 7.40/6.93 bnd_ndr1_1 X64 -->
% 7.40/6.93 (~ bnd_c4_2 X64 X65 | bnd_c9_2 X64 X65) |
% 7.40/6.93 bnd_c6_2 X64 X65)) |
% 7.40/6.93 ~ bnd_c2_1 X64) |
% 7.40/6.93 (ALL X66.
% 7.40/6.93 bnd_ndr1_0 -->
% 7.40/6.93 ((ALL X67.
% 7.40/6.93 bnd_ndr1_1 X66 -->
% 7.40/6.93 (bnd_c8_2 X66 X67 | bnd_c1_2 X66 X67) |
% 7.40/6.93 bnd_c4_2 X66 X67) |
% 7.40/6.93 ~ bnd_c5_1 X66) |
% 7.40/6.93 ~ bnd_c3_1 X66)) |
% 7.40/6.93 bnd_c10_0)) &
% 7.40/6.93 (((ALL X68.
% 7.40/6.93 bnd_ndr1_0 -->
% 7.40/6.93 (((bnd_ndr1_1 X68 & ~ bnd_c1_2 X68 bnd_a1011) &
% 7.40/6.93 bnd_c3_2 X68 bnd_a1011) &
% 7.40/6.93 ~ bnd_c7_2 X68 bnd_a1011 |
% 7.40/6.93 ((bnd_ndr1_1 X68 & bnd_c6_2 X68 bnd_a1012) &
% 7.40/6.93 bnd_c7_2 X68 bnd_a1012) &
% 7.40/6.93 ~ bnd_c2_2 X68 bnd_a1012) |
% 7.40/6.93 bnd_c4_1 X68) |
% 7.40/6.93 ((((bnd_ndr1_0 & ~ bnd_c5_1 bnd_a1013) &
% 7.40/6.93 bnd_c6_1 bnd_a1013) &
% 7.40/6.93 bnd_ndr1_1 bnd_a1013) &
% 7.40/6.93 bnd_c8_2 bnd_a1013 bnd_a1014) &
% 7.40/6.93 ~ bnd_c1_2 bnd_a1013 bnd_a1014) |
% 7.40/6.93 ((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a1015) &
% 7.40/6.93 bnd_c3_2 bnd_a1015 bnd_a1016) &
% 7.40/6.93 ~ bnd_c7_2 bnd_a1015 bnd_a1016) &
% 7.40/6.93 bnd_ndr1_1 bnd_a1015) &
% 7.40/6.93 bnd_c9_2 bnd_a1015 bnd_a1017) &
% 7.40/6.93 bnd_c3_2 bnd_a1015 bnd_a1017) &
% 7.40/6.93 ~ bnd_c1_2 bnd_a1015 bnd_a1017)) &
% 7.40/6.93 (((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a1018) &
% 7.40/6.93 ~ bnd_c7_2 bnd_a1018 bnd_a1019) &
% 7.40/6.93 ~ bnd_c3_2 bnd_a1018 bnd_a1019) &
% 7.40/6.93 ~ bnd_c10_2 bnd_a1018 bnd_a1019) &
% 7.40/6.93 ~ bnd_c10_1 bnd_a1018) &
% 7.40/6.93 bnd_c3_1 bnd_a1018 |
% 7.40/6.93 ~ bnd_c7_0) |
% 7.40/6.93 ((bnd_ndr1_0 & bnd_c3_1 bnd_a1020) &
% 7.40/6.93 (ALL X69.
% 7.40/6.93 bnd_ndr1_1 bnd_a1020 -->
% 7.40/6.93 ~ bnd_c2_2 bnd_a1020 X69 | ~ bnd_c1_2 bnd_a1020 X69)) &
% 7.40/6.93 bnd_c9_1 bnd_a1020)) &
% 7.40/6.93 ((~ bnd_c7_0 | ~ bnd_c9_0) |
% 7.40/6.93 (ALL X70.
% 7.40/6.93 bnd_ndr1_0 -->
% 7.40/6.93 (bnd_c8_1 X70 |
% 7.40/6.93 ((bnd_ndr1_1 X70 & ~ bnd_c9_2 X70 bnd_a1021) &
% 7.40/6.93 ~ bnd_c1_2 X70 bnd_a1021) &
% 7.40/6.93 bnd_c5_2 X70 bnd_a1021) |
% 7.40/6.93 ~ bnd_c10_1 X70))) &
% 7.40/6.93 ((~ bnd_c8_0 | ~ bnd_c5_0) | bnd_c3_0)) &
% 7.40/6.93 (((((((bnd_ndr1_0 & ~ bnd_c9_1 bnd_a1022) &
% 7.40/6.93 (ALL X71.
% 7.40/6.93 bnd_ndr1_1 bnd_a1022 -->
% 7.40/6.93 (bnd_c10_2 bnd_a1022 X71 | ~ bnd_c2_2 bnd_a1022 X71) |
% 7.40/6.93 bnd_c8_2 bnd_a1022 X71)) &
% 7.40/6.93 bnd_ndr1_1 bnd_a1022) &
% 7.40/6.93 ~ bnd_c3_2 bnd_a1022 bnd_a1023) &
% 7.40/6.93 ~ bnd_c8_2 bnd_a1022 bnd_a1023) &
% 7.40/6.93 ~ bnd_c4_2 bnd_a1022 bnd_a1023 |
% 7.40/6.93 bnd_c2_0) |
% 7.40/6.93 ((bnd_ndr1_0 & ~ bnd_c8_1 bnd_a1024) & ~ bnd_c4_1 bnd_a1024) &
% 7.40/6.93 (ALL X72.
% 7.40/6.93 bnd_ndr1_1 bnd_a1024 -->
% 7.40/6.93 (bnd_c3_2 bnd_a1024 X72 | ~ bnd_c7_2 bnd_a1024 X72) |
% 7.40/6.93 bnd_c4_2 bnd_a1024 X72))) &
% 7.40/6.93 ((bnd_c3_0 | bnd_c8_0) | bnd_c1_0)) &
% 7.40/6.93 ((ALL X73.
% 7.40/6.93 bnd_ndr1_0 -->
% 7.40/6.93 (bnd_c2_1 X73 | ~ bnd_c5_1 X73) |
% 7.40/6.93 ((bnd_ndr1_1 X73 & bnd_c4_2 X73 bnd_a1025) &
% 7.40/6.93 bnd_c9_2 X73 bnd_a1025) &
% 7.40/6.93 ~ bnd_c5_2 X73 bnd_a1025) |
% 7.40/6.93 ~ bnd_c10_0)) &
% 7.40/6.93 ((bnd_c10_0 |
% 7.40/6.93 (((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a1026) &
% 7.40/6.93 ~ bnd_c5_2 bnd_a1026 bnd_a1027) &
% 7.40/6.93 ~ bnd_c4_2 bnd_a1026 bnd_a1027) &
% 7.40/6.93 ~ bnd_c3_2 bnd_a1026 bnd_a1027) &
% 7.40/6.93 (ALL X74.
% 7.40/6.93 bnd_ndr1_1 bnd_a1026 -->
% 7.40/6.93 (~ bnd_c6_2 bnd_a1026 X74 | bnd_c3_2 bnd_a1026 X74) |
% 7.40/6.93 bnd_c5_2 bnd_a1026 X74)) &
% 7.40/6.93 bnd_c5_1 bnd_a1026) |
% 7.40/6.93 (ALL X75.
% 7.40/6.93 bnd_ndr1_0 -->
% 7.40/6.93 (bnd_c5_1 X75 | bnd_c8_1 X75) |
% 7.40/6.93 (ALL X76.
% 7.40/6.93 bnd_ndr1_1 X75 -->
% 7.40/6.93 (bnd_c10_2 X75 X76 | ~ bnd_c4_2 X75 X76) |
% 7.40/6.93 bnd_c6_2 X75 X76)))) &
% 7.40/6.93 ((bnd_c6_0 |
% 7.40/6.93 ((((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a1028) &
% 7.40/6.93 ~ bnd_c9_2 bnd_a1028 bnd_a1029) &
% 7.40/6.93 ~ bnd_c8_2 bnd_a1028 bnd_a1029) &
% 7.40/6.93 ~ bnd_c4_2 bnd_a1028 bnd_a1029) &
% 7.40/6.93 (ALL X77.
% 7.40/6.93 bnd_ndr1_1 bnd_a1028 -->
% 7.40/6.93 (bnd_c9_2 bnd_a1028 X77 | ~ bnd_c3_2 bnd_a1028 X77) |
% 7.40/6.93 bnd_c5_2 bnd_a1028 X77)) &
% 7.40/6.93 bnd_ndr1_1 bnd_a1028) &
% 7.40/6.93 ~ bnd_c9_2 bnd_a1028 bnd_a1030) &
% 7.40/6.93 bnd_c4_2 bnd_a1028 bnd_a1030) &
% 7.40/6.93 ~ bnd_c8_2 bnd_a1028 bnd_a1030) |
% 7.40/6.93 ((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a1031) &
% 7.40/6.93 bnd_c6_2 bnd_a1031 bnd_a1032) &
% 7.40/6.93 ~ bnd_c8_2 bnd_a1031 bnd_a1032) &
% 7.40/6.93 ~ bnd_c7_2 bnd_a1031 bnd_a1032) &
% 7.40/6.93 (ALL X78.
% 7.40/6.93 bnd_ndr1_1 bnd_a1031 -->
% 7.40/6.93 (~ bnd_c6_2 bnd_a1031 X78 | ~ bnd_c2_2 bnd_a1031 X78) |
% 7.40/6.93 bnd_c4_2 bnd_a1031 X78))) &
% 7.40/6.93 ((bnd_c9_0 |
% 7.40/6.93 (((((bnd_ndr1_0 &
% 7.40/6.93 (ALL X79.
% 7.40/6.93 bnd_ndr1_1 bnd_a1033 -->
% 7.40/6.93 (~ bnd_c4_2 bnd_a1033 X79 | bnd_c7_2 bnd_a1033 X79) |
% 7.40/6.93 bnd_c2_2 bnd_a1033 X79)) &
% 7.40/6.93 ~ bnd_c7_1 bnd_a1033) &
% 7.40/6.93 bnd_ndr1_1 bnd_a1033) &
% 7.40/6.93 bnd_c10_2 bnd_a1033 bnd_a1034) &
% 7.40/6.93 bnd_c5_2 bnd_a1033 bnd_a1034) &
% 7.40/6.93 bnd_c8_2 bnd_a1033 bnd_a1034) |
% 7.40/6.93 bnd_c4_0)) &
% 7.40/6.93 (((((((((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a1035) &
% 7.40/6.93 bnd_c2_2 bnd_a1035 bnd_a1036) &
% 7.40/6.93 bnd_c8_2 bnd_a1035 bnd_a1036) &
% 7.40/6.93 ~ bnd_c9_2 bnd_a1035 bnd_a1036) &
% 7.40/6.93 bnd_ndr1_1 bnd_a1035) &
% 7.40/6.93 bnd_c3_2 bnd_a1035 bnd_a1037) &
% 7.40/6.93 bnd_c4_2 bnd_a1035 bnd_a1037) &
% 7.40/6.93 ~ bnd_c7_2 bnd_a1035 bnd_a1037) &
% 7.40/6.93 bnd_ndr1_1 bnd_a1035) &
% 7.40/6.93 ~ bnd_c9_2 bnd_a1035 bnd_a1038) &
% 7.40/6.93 ~ bnd_c1_2 bnd_a1035 bnd_a1038) &
% 7.40/6.93 ~ bnd_c10_2 bnd_a1035 bnd_a1038 |
% 7.40/6.93 bnd_c8_0) |
% 7.40/6.93 (ALL X80.
% 7.40/6.93 bnd_ndr1_0 -->
% 7.40/6.93 ((ALL X81.
% 7.40/6.93 bnd_ndr1_1 X80 -->
% 7.40/6.93 (~ bnd_c5_2 X80 X81 | bnd_c4_2 X80 X81) |
% 7.40/6.93 ~ bnd_c8_2 X80 X81) |
% 7.40/6.93 ((bnd_ndr1_1 X80 & ~ bnd_c5_2 X80 bnd_a1039) &
% 7.40/6.93 ~ bnd_c8_2 X80 bnd_a1039) &
% 7.40/6.93 bnd_c6_2 X80 bnd_a1039) |
% 7.40/6.93 bnd_c1_1 X80))) &
% 7.40/6.93 (bnd_c10_0 | ~ bnd_c8_0)) &
% 7.40/6.93 (((bnd_ndr1_0 &
% 7.40/6.93 (ALL X82.
% 7.40/6.93 bnd_ndr1_1 bnd_a1040 -->
% 7.40/6.93 (~ bnd_c7_2 bnd_a1040 X82 | bnd_c4_2 bnd_a1040 X82) |
% 7.40/6.93 bnd_c8_2 bnd_a1040 X82)) &
% 7.40/6.93 bnd_c3_1 bnd_a1040 |
% 7.40/6.93 (ALL X83.
% 7.40/6.93 bnd_ndr1_0 -->
% 7.40/6.93 (~ bnd_c1_1 X83 | ~ bnd_c7_1 X83) | bnd_c10_1 X83)) |
% 7.40/6.93 (bnd_ndr1_0 &
% 7.40/6.93 (ALL X84.
% 7.40/6.93 bnd_ndr1_1 bnd_a1041 -->
% 7.40/6.93 (~ bnd_c8_2 bnd_a1041 X84 | ~ bnd_c1_2 bnd_a1041 X84) |
% 7.40/6.93 bnd_c5_2 bnd_a1041 X84)) &
% 7.40/6.93 ~ bnd_c3_1 bnd_a1041)) &
% 7.40/6.93 ((((bnd_ndr1_0 &
% 7.40/6.93 (ALL X85.
% 7.40/6.93 bnd_ndr1_1 bnd_a1042 -->
% 7.40/6.93 (~ bnd_c7_2 bnd_a1042 X85 | ~ bnd_c10_2 bnd_a1042 X85) |
% 7.40/6.93 bnd_c3_2 bnd_a1042 X85)) &
% 7.40/6.93 (ALL X86.
% 7.40/6.93 bnd_ndr1_1 bnd_a1042 -->
% 7.40/6.93 (bnd_c4_2 bnd_a1042 X86 | ~ bnd_c3_2 bnd_a1042 X86) |
% 7.40/6.93 bnd_c6_2 bnd_a1042 X86)) &
% 7.40/6.93 ~ bnd_c9_1 bnd_a1042 |
% 7.40/6.93 bnd_c7_0) |
% 7.40/6.93 ~ bnd_c1_0)) &
% 7.40/6.93 (((ALL X87.
% 7.40/6.93 bnd_ndr1_0 -->
% 7.40/6.93 (bnd_c2_1 X87 |
% 7.40/6.93 (ALL X88.
% 7.40/6.93 bnd_ndr1_1 X87 --> bnd_c5_2 X87 X88 | ~ bnd_c4_2 X87 X88)) |
% 7.40/6.93 bnd_c5_1 X87) |
% 7.40/6.93 ~ bnd_c6_0) |
% 7.40/6.93 (((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a1043) & bnd_c4_2 bnd_a1043 bnd_a1044) &
% 7.40/6.93 ~ bnd_c6_2 bnd_a1043 bnd_a1044) &
% 7.40/6.93 ~ bnd_c1_2 bnd_a1043 bnd_a1044) &
% 7.40/6.93 bnd_c8_1 bnd_a1043) &
% 7.40/6.93 bnd_c5_1 bnd_a1043)) &
% 7.40/6.93 (((ALL X89.
% 7.40/6.93 bnd_ndr1_0 -->
% 7.40/6.93 ((ALL X90.
% 7.40/6.93 bnd_ndr1_1 X89 --> ~ bnd_c8_2 X89 X90 | ~ bnd_c2_2 X89 X90) |
% 7.40/6.93 bnd_c10_1 X89) |
% 7.40/6.93 ((bnd_ndr1_1 X89 & bnd_c8_2 X89 bnd_a1045) &
% 7.40/6.93 bnd_c4_2 X89 bnd_a1045) &
% 7.40/6.93 ~ bnd_c2_2 X89 bnd_a1045) |
% 7.40/6.93 bnd_c8_0) |
% 7.40/6.93 (bnd_ndr1_0 &
% 7.40/6.93 (ALL X91.
% 7.40/6.93 bnd_ndr1_1 bnd_a1046 -->
% 7.40/6.93 (~ bnd_c3_2 bnd_a1046 X91 | ~ bnd_c8_2 bnd_a1046 X91) |
% 7.40/6.93 bnd_c10_2 bnd_a1046 X91)) &
% 7.40/6.93 ~ bnd_c9_1 bnd_a1046)) &
% 7.40/6.93 (((((((bnd_ndr1_0 & bnd_c7_1 bnd_a1047) & ~ bnd_c1_1 bnd_a1047) &
% 7.40/6.93 bnd_ndr1_1 bnd_a1047) &
% 7.40/6.93 bnd_c6_2 bnd_a1047 bnd_a1048) &
% 7.40/6.93 ~ bnd_c3_2 bnd_a1047 bnd_a1048) &
% 7.40/6.93 bnd_c9_2 bnd_a1047 bnd_a1048 |
% 7.40/6.93 (ALL X92.
% 7.40/6.93 bnd_ndr1_0 -->
% 7.40/6.93 ((ALL X93.
% 7.40/6.93 bnd_ndr1_1 X92 -->
% 7.40/6.93 (~ bnd_c7_2 X92 X93 | bnd_c4_2 X92 X93) | bnd_c3_2 X92 X93) |
% 7.40/6.93 ((bnd_ndr1_1 X92 & ~ bnd_c10_2 X92 bnd_a1049) &
% 7.40/6.93 ~ bnd_c9_2 X92 bnd_a1049) &
% 7.40/6.93 bnd_c8_2 X92 bnd_a1049) |
% 7.40/6.93 bnd_c8_1 X92)) |
% 7.40/6.93 ((bnd_ndr1_0 &
% 7.40/6.93 (ALL X94.
% 7.40/6.93 bnd_ndr1_1 bnd_a1050 -->
% 7.40/6.93 (~ bnd_c8_2 bnd_a1050 X94 | bnd_c10_2 bnd_a1050 X94) |
% 7.40/6.93 ~ bnd_c4_2 bnd_a1050 X94)) &
% 7.40/6.93 (ALL X95.
% 7.40/6.93 bnd_ndr1_1 bnd_a1050 -->
% 7.40/6.93 (bnd_c4_2 bnd_a1050 X95 | ~ bnd_c9_2 bnd_a1050 X95) |
% 7.40/6.93 bnd_c8_2 bnd_a1050 X95)) &
% 7.40/6.93 bnd_c5_1 bnd_a1050)) &
% 7.40/6.93 ((~ bnd_c8_0 |
% 7.40/6.93 (((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a1051) & ~ bnd_c8_2 bnd_a1051 bnd_a1052) &
% 7.40/6.93 ~ bnd_c2_2 bnd_a1051 bnd_a1052) &
% 7.40/6.93 ~ bnd_c9_2 bnd_a1051 bnd_a1052) &
% 7.40/6.93 ~ bnd_c4_1 bnd_a1051) &
% 7.40/6.93 bnd_c7_1 bnd_a1051) |
% 7.40/6.93 bnd_c10_0)) &
% 7.40/6.93 (((((((bnd_ndr1_0 &
% 7.40/6.93 (ALL X96.
% 7.40/6.93 bnd_ndr1_1 bnd_a1053 -->
% 7.40/6.93 (bnd_c8_2 bnd_a1053 X96 | bnd_c2_2 bnd_a1053 X96) |
% 7.40/6.93 ~ bnd_c3_2 bnd_a1053 X96)) &
% 7.40/6.93 bnd_c1_1 bnd_a1053) &
% 7.40/6.93 bnd_ndr1_1 bnd_a1053) &
% 7.40/6.93 bnd_c10_2 bnd_a1053 bnd_a1054) &
% 7.40/6.93 bnd_c3_2 bnd_a1053 bnd_a1054) &
% 7.40/6.93 ~ bnd_c2_2 bnd_a1053 bnd_a1054 |
% 7.40/6.93 bnd_c7_0) |
% 7.40/6.93 (ALL X97.
% 7.40/6.93 bnd_ndr1_0 -->
% 7.40/6.93 (bnd_c5_1 X97 | bnd_c1_1 X97) |
% 7.40/6.93 (ALL X98.
% 7.40/6.93 bnd_ndr1_1 X97 --> ~ bnd_c1_2 X97 X98 | ~ bnd_c3_2 X97 X98)))) &
% 7.40/6.93 ((bnd_c6_0 | ~ bnd_c8_0) |
% 7.40/6.93 ((((((((bnd_ndr1_0 &
% 7.40/6.93 (ALL X99.
% 7.40/6.93 bnd_ndr1_1 bnd_a1055 -->
% 7.40/6.93 (~ bnd_c4_2 bnd_a1055 X99 | ~ bnd_c6_2 bnd_a1055 X99) |
% 7.40/6.93 ~ bnd_c8_2 bnd_a1055 X99)) &
% 7.40/6.93 bnd_ndr1_1 bnd_a1055) &
% 7.40/6.93 bnd_c4_2 bnd_a1055 bnd_a1056) &
% 7.40/6.93 bnd_c10_2 bnd_a1055 bnd_a1056) &
% 7.40/6.93 bnd_c5_2 bnd_a1055 bnd_a1056) &
% 7.40/6.93 bnd_ndr1_1 bnd_a1055) &
% 7.40/6.93 ~ bnd_c2_2 bnd_a1055 bnd_a1057) &
% 7.40/6.93 bnd_c3_2 bnd_a1055 bnd_a1057) &
% 7.40/6.93 ~ bnd_c9_2 bnd_a1055 bnd_a1057)) &
% 7.40/6.93 ((((bnd_ndr1_0 & ~ bnd_c1_1 bnd_a1058) &
% 7.40/6.93 ~ bnd_c10_1 bnd_a1058) &
% 7.40/6.93 ~ bnd_c5_1 bnd_a1058 |
% 7.40/6.93 (((((bnd_ndr1_0 &
% 7.40/6.93 (ALL X100.
% 7.40/6.93 bnd_ndr1_1 bnd_a1059 -->
% 7.40/6.93 (~ bnd_c2_2 bnd_a1059 X100 | bnd_c1_2 bnd_a1059 X100) |
% 7.40/6.93 bnd_c8_2 bnd_a1059 X100)) &
% 7.40/6.93 bnd_ndr1_1 bnd_a1059) &
% 7.40/6.93 bnd_c4_2 bnd_a1059 bnd_a1060) &
% 7.40/6.93 ~ bnd_c9_2 bnd_a1059 bnd_a1060) &
% 7.40/6.93 ~ bnd_c5_2 bnd_a1059 bnd_a1060) &
% 7.40/6.93 ~ bnd_c9_1 bnd_a1059) |
% 7.40/6.93 ((bnd_ndr1_0 & bnd_c1_1 bnd_a1061) &
% 7.40/6.93 ~ bnd_c9_1 bnd_a1061) &
% 7.40/6.93 bnd_c8_1 bnd_a1061)) &
% 7.40/6.93 ((~ bnd_c4_0 |
% 7.40/6.93 (bnd_ndr1_0 & bnd_c10_1 bnd_a1062) &
% 7.40/6.93 ~ bnd_c5_1 bnd_a1062) |
% 7.40/6.93 (ALL X101.
% 7.40/6.93 bnd_ndr1_0 -->
% 7.40/6.93 (ALL X102.
% 7.40/6.93 bnd_ndr1_1 X101 -->
% 7.40/6.93 (bnd_c1_2 X101 X102 | bnd_c6_2 X101 X102) | bnd_c9_2 X101 X102) |
% 7.40/6.93 ((bnd_ndr1_1 X101 & bnd_c6_2 X101 bnd_a1063) & ~ bnd_c9_2 X101 bnd_a1063) &
% 7.40/6.93 ~ bnd_c5_2 X101 bnd_a1063))) &
% 7.40/6.93 (((((((bnd_ndr1_0 &
% 7.40/6.93 (ALL X103.
% 7.40/6.93 bnd_ndr1_1 bnd_a1064 -->
% 7.40/6.93 (bnd_c1_2 bnd_a1064 X103 | bnd_c8_2 bnd_a1064 X103) |
% 7.40/6.93 bnd_c3_2 bnd_a1064 X103)) &
% 7.40/6.93 bnd_ndr1_1 bnd_a1064) &
% 7.40/6.93 bnd_c8_2 bnd_a1064 bnd_a1065) &
% 7.40/6.93 ~ bnd_c1_2 bnd_a1064 bnd_a1065) &
% 7.40/6.93 ~ bnd_c2_2 bnd_a1064 bnd_a1065) &
% 7.40/6.93 (ALL X104.
% 7.40/6.93 bnd_ndr1_1 bnd_a1064 -->
% 7.40/6.93 (bnd_c10_2 bnd_a1064 X104 | ~ bnd_c6_2 bnd_a1064 X104) |
% 7.40/6.93 ~ bnd_c7_2 bnd_a1064 X104) |
% 7.40/6.93 (ALL X105.
% 7.40/6.93 bnd_ndr1_0 -->
% 7.40/6.93 (bnd_c7_1 X105 |
% 7.40/6.93 (ALL X106.
% 7.40/6.93 bnd_ndr1_1 X105 -->
% 7.40/6.93 (bnd_c10_2 X105 X106 | ~ bnd_c6_2 X105 X106) | ~ bnd_c8_2 X105 X106)) |
% 7.40/6.93 ~ bnd_c9_1 X105)) |
% 7.40/6.93 ~ bnd_c10_0)) &
% 7.40/6.93 ((~ bnd_c4_0 | bnd_c3_0) | ~ bnd_c5_0)) &
% 7.40/6.93 (((((((bnd_ndr1_0 & bnd_c7_1 bnd_a1066) &
% 7.40/6.93 ~ bnd_c8_1 bnd_a1066) &
% 7.40/6.93 bnd_ndr1_1 bnd_a1066) &
% 7.40/6.93 bnd_c6_2 bnd_a1066 bnd_a1067) &
% 7.40/6.93 bnd_c1_2 bnd_a1066 bnd_a1067) &
% 7.40/6.93 ~ bnd_c4_2 bnd_a1066 bnd_a1067 |
% 7.40/6.93 (((((((bnd_ndr1_0 & ~ bnd_c3_1 bnd_a1068) &
% 7.40/6.93 bnd_ndr1_1 bnd_a1068) &
% 7.40/6.93 ~ bnd_c2_2 bnd_a1068 bnd_a1069) &
% 7.40/6.93 ~ bnd_c5_2 bnd_a1068 bnd_a1069) &
% 7.40/6.93 bnd_ndr1_1 bnd_a1068) &
% 7.40/6.93 bnd_c8_2 bnd_a1068 bnd_a1070) &
% 7.40/6.93 ~ bnd_c2_2 bnd_a1068 bnd_a1070) &
% 7.40/6.93 bnd_c1_2 bnd_a1068 bnd_a1070) |
% 7.40/6.93 ~ bnd_c6_0)) &
% 7.40/6.93 (((ALL X107.
% 7.40/6.93 bnd_ndr1_0 -->
% 7.40/6.93 (~ bnd_c1_1 X107 |
% 7.40/6.93 (ALL X108.
% 7.40/6.93 bnd_ndr1_1 X107 -->
% 7.40/6.93 (~ bnd_c3_2 X107 X108 | ~ bnd_c5_2 X107 X108) | bnd_c7_2 X107 X108)) |
% 7.40/6.93 ((bnd_ndr1_1 X107 &
% 7.40/6.93 ~ bnd_c6_2 X107 bnd_a1071) &
% 7.40/6.93 bnd_c9_2 X107 bnd_a1071) &
% 7.40/6.93 ~ bnd_c7_2 X107 bnd_a1071) |
% 7.40/6.93 bnd_c1_0) |
% 7.40/6.93 ((bnd_ndr1_0 & bnd_c9_1 bnd_a1072) &
% 7.40/6.93 ~ bnd_c5_1 bnd_a1072) &
% 7.40/6.93 bnd_c2_1 bnd_a1072)) &
% 7.40/6.93 (((ALL X109.
% 7.40/6.93 bnd_ndr1_0 -->
% 7.40/6.93 (~ bnd_c4_1 X109 |
% 7.40/6.93 (ALL X110.
% 7.40/6.93 bnd_ndr1_1 X109 -->
% 7.40/6.93 (bnd_c9_2 X109 X110 | bnd_c10_2 X109 X110) | ~ bnd_c1_2 X109 X110)) |
% 7.40/6.93 (bnd_ndr1_1 X109 &
% 7.40/6.93 bnd_c3_2 X109 bnd_a1073) &
% 7.40/6.93 bnd_c10_2 X109 bnd_a1073) |
% 7.40/6.93 bnd_c3_0) |
% 7.40/6.93 (ALL X111.
% 7.40/6.93 bnd_ndr1_0 -->
% 7.40/6.93 (bnd_c10_1 X111 |
% 7.40/6.93 (ALL X112.
% 7.40/6.93 bnd_ndr1_1 X111 -->
% 7.40/6.93 (~ bnd_c1_2 X111 X112 | ~ bnd_c5_2 X111 X112) | bnd_c2_2 X111 X112)) |
% 7.40/6.93 bnd_c3_1 X111))) &
% 7.40/6.93 ((bnd_c4_0 |
% 7.40/6.93 (((((bnd_ndr1_0 & bnd_c7_1 bnd_a1074) &
% 7.40/6.93 (ALL X113.
% 7.40/6.93 bnd_ndr1_1 bnd_a1074 -->
% 7.40/6.93 bnd_c5_2 bnd_a1074 X113 |
% 7.40/6.93 bnd_c8_2 bnd_a1074 X113)) &
% 7.40/6.93 bnd_ndr1_1 bnd_a1074) &
% 7.40/6.93 ~ bnd_c4_2 bnd_a1074 bnd_a1075) &
% 7.40/6.93 ~ bnd_c3_2 bnd_a1074 bnd_a1075) &
% 7.40/6.93 ~ bnd_c6_2 bnd_a1074 bnd_a1075) |
% 7.40/6.93 bnd_c7_0)) &
% 7.40/6.93 ((ALL X114.
% 7.40/6.93 bnd_ndr1_0 -->
% 7.40/6.93 (~ bnd_c2_1 X114 |
% 7.40/6.93 ((bnd_ndr1_1 X114 &
% 7.40/6.93 ~ bnd_c9_2 X114 bnd_a1076) &
% 7.40/6.93 ~ bnd_c6_2 X114 bnd_a1076) &
% 7.40/6.93 bnd_c8_2 X114 bnd_a1076) |
% 7.40/6.93 ((bnd_ndr1_1 X114 &
% 7.40/6.93 ~ bnd_c6_2 X114 bnd_a1077) &
% 7.40/6.93 bnd_c4_2 X114 bnd_a1077) &
% 7.40/6.93 ~ bnd_c5_2 X114 bnd_a1077) |
% 7.40/6.93 ((bnd_ndr1_0 & ~ bnd_c10_1 bnd_a1078) &
% 7.40/6.93 (ALL X115.
% 7.40/6.93 bnd_ndr1_1 bnd_a1078 -->
% 7.40/6.93 (bnd_c1_2 bnd_a1078 X115 |
% 7.40/6.93 bnd_c10_2 bnd_a1078 X115) |
% 7.40/6.93 ~ bnd_c6_2 bnd_a1078 X115)) &
% 7.40/6.93 (ALL X116.
% 7.40/6.93 bnd_ndr1_1 bnd_a1078 -->
% 7.40/6.93 (~ bnd_c6_2 bnd_a1078 X116 |
% 7.40/6.93 ~ bnd_c10_2 bnd_a1078 X116) |
% 7.40/6.93 bnd_c2_2 bnd_a1078 X116))) &
% 7.40/6.93 ((bnd_c5_0 |
% 7.40/6.93 (ALL X117.
% 7.40/6.93 bnd_ndr1_0 -->
% 7.40/6.93 ((ALL X118.
% 7.40/6.93 bnd_ndr1_1 X117 -->
% 7.40/6.93 (bnd_c10_2 X117 X118 |
% 7.40/6.93 ~ bnd_c6_2 X117 X118) |
% 7.40/6.93 bnd_c3_2 X117 X118) |
% 7.40/6.93 bnd_c4_1 X117) |
% 7.40/6.93 bnd_c7_1 X117)) |
% 7.40/6.93 ~ bnd_c3_0)) &
% 7.40/6.93 (((ALL X119.
% 7.40/6.93 bnd_ndr1_0 -->
% 7.40/6.93 ((ALL X120.
% 7.40/6.93 bnd_ndr1_1 X119 -->
% 7.40/6.93 (bnd_c9_2 X119 X120 |
% 7.40/6.93 bnd_c5_2 X119 X120) |
% 7.40/6.93 ~ bnd_c8_2 X119 X120) |
% 7.40/6.93 bnd_c4_1 X119) |
% 7.40/6.93 (ALL X121.
% 7.40/6.93 bnd_ndr1_1 X119 -->
% 7.40/6.93 (bnd_c10_2 X119 X121 |
% 7.40/6.93 ~ bnd_c2_2 X119 X121) |
% 7.40/6.93 ~ bnd_c9_2 X119 X121)) |
% 7.40/6.93 ((bnd_ndr1_0 & bnd_c1_1 bnd_a1079) &
% 7.40/6.93 ~ bnd_c9_1 bnd_a1079) &
% 7.40/6.93 ~ bnd_c8_1 bnd_a1079) |
% 7.40/6.93 ((bnd_ndr1_0 &
% 7.40/6.93 (ALL X122.
% 7.40/6.93 bnd_ndr1_1 bnd_a1080 -->
% 7.40/6.93 (~ bnd_c1_2 bnd_a1080 X122 |
% 7.40/6.93 bnd_c10_2 bnd_a1080 X122) |
% 7.40/6.93 ~ bnd_c9_2 bnd_a1080 X122)) &
% 7.40/6.93 bnd_c3_1 bnd_a1080) &
% 7.40/6.93 (ALL X123.
% 7.40/6.93 bnd_ndr1_1 bnd_a1080 -->
% 7.40/6.93 (~ bnd_c6_2 bnd_a1080 X123 |
% 7.40/6.93 ~ bnd_c7_2 bnd_a1080 X123) |
% 7.40/6.93 ~ bnd_c9_2 bnd_a1080 X123))) &
% 7.40/6.93 ((((((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a1081) &
% 7.40/6.93 bnd_c8_2 bnd_a1081 bnd_a1082) &
% 7.40/6.93 ~ bnd_c9_2 bnd_a1081 bnd_a1082) &
% 7.40/6.93 ~ bnd_c1_2 bnd_a1081 bnd_a1082) &
% 7.40/6.93 bnd_ndr1_1 bnd_a1081) &
% 7.40/6.93 bnd_c7_2 bnd_a1081 bnd_a1083) &
% 7.40/6.93 ~ bnd_c6_2 bnd_a1081 bnd_a1083) &
% 7.40/6.93 bnd_c3_2 bnd_a1081 bnd_a1083) &
% 7.40/6.93 (ALL X124.
% 7.40/6.93 bnd_ndr1_1 bnd_a1081 -->
% 7.40/6.93 (bnd_c6_2 bnd_a1081 X124 |
% 7.40/6.93 bnd_c1_2 bnd_a1081 X124) |
% 7.40/6.93 ~ bnd_c3_2 bnd_a1081 X124) |
% 7.40/6.93 ~ bnd_c8_0) |
% 7.40/6.93 ~ bnd_c5_0)) &
% 7.40/6.93 (((ALL X125.
% 7.40/6.93 bnd_ndr1_0 -->
% 7.40/6.93 (((bnd_ndr1_1 X125 &
% 7.40/6.93 ~ bnd_c2_2 X125 bnd_a1084) &
% 7.40/6.93 ~ bnd_c9_2 X125 bnd_a1084) &
% 7.40/6.93 ~ bnd_c5_2 X125 bnd_a1084 |
% 7.40/6.93 ~ bnd_c2_1 X125) |
% 7.40/6.93 (ALL X126.
% 7.40/6.93 bnd_ndr1_1 X125 -->
% 7.40/6.93 ~ bnd_c1_2 X125 X126 |
% 7.40/6.93 bnd_c6_2 X125 X126)) |
% 7.40/6.93 (ALL X127.
% 7.40/6.93 bnd_ndr1_0 -->
% 7.40/6.93 (((bnd_ndr1_1 X127 & bnd_c3_2 X127 bnd_a1085) &
% 7.40/6.93 ~ bnd_c2_2 X127 bnd_a1085) &
% 7.40/6.93 ~ bnd_c9_2 X127 bnd_a1085 |
% 7.40/6.93 bnd_c6_1 X127) |
% 7.40/6.93 ((bnd_ndr1_1 X127 & ~ bnd_c2_2 X127 bnd_a1086) &
% 7.40/6.93 bnd_c9_2 X127 bnd_a1086) &
% 7.40/6.93 bnd_c4_2 X127 bnd_a1086)) |
% 7.40/6.93 ~ bnd_c7_0)) &
% 7.40/6.93 (~ bnd_c2_0 |
% 7.40/6.93 (((((bnd_ndr1_0 &
% 7.40/6.93 (ALL X128.
% 7.40/6.93 bnd_ndr1_1 bnd_a1087 -->
% 7.40/6.93 (bnd_c6_2 bnd_a1087 X128 |
% 7.40/6.93 ~ bnd_c8_2 bnd_a1087 X128) |
% 7.40/6.93 ~ bnd_c3_2 bnd_a1087 X128)) &
% 7.40/6.93 bnd_ndr1_1 bnd_a1087) &
% 7.40/6.93 ~ bnd_c5_2 bnd_a1087 bnd_a1088) &
% 7.40/6.93 ~ bnd_c4_2 bnd_a1087 bnd_a1088) &
% 7.40/6.93 ~ bnd_c10_2 bnd_a1087 bnd_a1088) &
% 7.40/6.93 (ALL X129.
% 7.40/6.93 bnd_ndr1_1 bnd_a1087 -->
% 7.40/6.93 (bnd_c9_2 bnd_a1087 X129 |
% 7.40/6.93 bnd_c5_2 bnd_a1087 X129) |
% 7.40/6.93 bnd_c6_2 bnd_a1087 X129))) &
% 7.40/6.93 (((((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a1089) &
% 7.40/6.93 bnd_c10_2 bnd_a1089 bnd_a1090) &
% 7.40/6.93 bnd_c9_2 bnd_a1089 bnd_a1090) &
% 7.40/6.93 bnd_c7_2 bnd_a1089 bnd_a1090) &
% 7.40/6.93 bnd_ndr1_1 bnd_a1089) &
% 7.40/6.93 bnd_c1_2 bnd_a1089 bnd_a1091) &
% 7.40/6.93 ~ bnd_c7_2 bnd_a1089 bnd_a1091) &
% 7.40/6.93 bnd_c5_1 bnd_a1089 |
% 7.40/6.93 (ALL X130.
% 7.40/6.93 bnd_ndr1_0 -->
% 7.40/6.93 (~ bnd_c2_1 X130 | bnd_c7_1 X130) |
% 7.40/6.93 bnd_c10_1 X130)) |
% 7.40/6.93 ((((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a1092) &
% 7.40/6.93 ~ bnd_c4_2 bnd_a1092 bnd_a1093) &
% 7.40/6.93 ~ bnd_c10_2 bnd_a1092 bnd_a1093) &
% 7.40/6.93 ~ bnd_c7_2 bnd_a1092 bnd_a1093) &
% 7.40/6.93 bnd_ndr1_1 bnd_a1092) &
% 7.40/6.93 bnd_c10_2 bnd_a1092 bnd_a1094) &
% 7.40/6.93 ~ bnd_c5_2 bnd_a1092 bnd_a1094) &
% 7.40/6.93 ~ bnd_c3_2 bnd_a1092 bnd_a1094) &
% 7.40/6.93 ~ bnd_c10_1 bnd_a1092)) &
% 7.40/6.93 ((bnd_c6_0 |
% 7.40/6.93 ((bnd_ndr1_0 &
% 7.40/6.93 (ALL X131.
% 7.40/6.93 bnd_ndr1_1 bnd_a1095 -->
% 7.40/6.93 (~ bnd_c9_2 bnd_a1095 X131 |
% 7.40/6.93 ~ bnd_c5_2 bnd_a1095 X131) |
% 7.40/6.93 bnd_c2_2 bnd_a1095 X131)) &
% 7.40/6.93 ~ bnd_c9_1 bnd_a1095) &
% 7.40/6.93 (ALL X132.
% 7.40/6.93 bnd_ndr1_1 bnd_a1095 -->
% 7.40/6.93 (bnd_c8_2 bnd_a1095 X132 |
% 7.40/6.93 bnd_c2_2 bnd_a1095 X132) |
% 7.40/6.93 ~ bnd_c9_2 bnd_a1095 X132)) |
% 7.40/6.93 bnd_c5_0)) &
% 7.40/6.93 ((~ bnd_c4_0 | bnd_c2_0) |
% 7.40/6.93 (ALL X133.
% 7.40/6.93 bnd_ndr1_0 -->
% 7.40/6.93 ((ALL X134.
% 7.40/6.93 bnd_ndr1_1 X133 -->
% 7.40/6.93 ~ bnd_c3_2 X133 X134 | ~ bnd_c7_2 X133 X134) |
% 7.40/6.93 ~ bnd_c6_1 X133) |
% 7.40/6.93 ((bnd_ndr1_1 X133 & ~ bnd_c4_2 X133 bnd_a1096) &
% 7.40/6.93 ~ bnd_c7_2 X133 bnd_a1096) &
% 7.40/6.93 bnd_c6_2 X133 bnd_a1096))) &
% 7.40/6.93 (((ALL X135.
% 7.40/6.93 bnd_ndr1_0 -->
% 7.40/6.93 (bnd_c7_1 X135 | bnd_c3_1 X135) |
% 7.40/6.93 (ALL X136.
% 7.40/6.93 bnd_ndr1_1 X135 -->
% 7.40/6.93 (bnd_c7_2 X135 X136 | ~ bnd_c6_2 X135 X136) |
% 7.40/6.93 bnd_c9_2 X135 X136)) |
% 7.40/6.93 bnd_c6_0) |
% 7.40/6.93 (ALL X137.
% 7.40/6.93 bnd_ndr1_0 -->
% 7.40/6.93 ((ALL X138.
% 7.40/6.93 bnd_ndr1_1 X137 -->
% 7.40/6.93 (~ bnd_c1_2 X137 X138 | ~ bnd_c9_2 X137 X138) |
% 7.40/6.93 bnd_c6_2 X137 X138) |
% 7.40/6.93 (bnd_ndr1_1 X137 & ~ bnd_c6_2 X137 bnd_a1097) &
% 7.40/6.93 bnd_c9_2 X137 bnd_a1097) |
% 7.40/6.93 ~ bnd_c4_1 X137))) &
% 7.40/6.93 ((bnd_c6_0 | bnd_c9_0) | bnd_c7_0)) &
% 7.40/6.93 ((bnd_c4_0 | ~ bnd_c7_0) |
% 7.40/6.93 (ALL X139.
% 7.40/6.93 bnd_ndr1_0 -->
% 7.40/6.93 (~ bnd_c6_1 X139 |
% 7.40/6.93 (ALL X140.
% 7.40/6.93 bnd_ndr1_1 X139 -->
% 7.40/6.93 bnd_c5_2 X139 X140 | bnd_c9_2 X139 X140)) |
% 7.40/6.93 ~ bnd_c3_1 X139))) &
% 7.40/6.93 ((ALL X141.
% 7.40/6.93 bnd_ndr1_0 -->
% 7.40/6.93 (~ bnd_c1_1 X141 | ~ bnd_c2_1 X141) |
% 7.40/6.93 (ALL X142.
% 7.40/6.93 bnd_ndr1_1 X141 -->
% 7.40/6.93 (bnd_c8_2 X141 X142 | ~ bnd_c4_2 X141 X142) |
% 7.40/6.93 bnd_c7_2 X141 X142)) |
% 7.40/6.93 ((bnd_ndr1_0 & ~ bnd_c8_1 bnd_a1098) &
% 7.40/6.93 (ALL X143.
% 7.40/6.93 bnd_ndr1_1 bnd_a1098 -->
% 7.40/6.93 (~ bnd_c9_2 bnd_a1098 X143 |
% 7.40/6.93 ~ bnd_c2_2 bnd_a1098 X143) |
% 7.40/6.93 bnd_c3_2 bnd_a1098 X143)) &
% 7.40/6.93 ~ bnd_c5_1 bnd_a1098)) &
% 7.40/6.93 ((~ bnd_c9_0 | bnd_c4_0) |
% 7.40/6.93 ((bnd_ndr1_0 &
% 7.40/6.93 (ALL X144.
% 7.40/6.93 bnd_ndr1_1 bnd_a1099 -->
% 7.40/6.93 (bnd_c7_2 bnd_a1099 X144 | bnd_c8_2 bnd_a1099 X144) |
% 7.40/6.93 bnd_c3_2 bnd_a1099 X144)) &
% 7.40/6.93 bnd_c5_1 bnd_a1099) &
% 7.40/6.93 ~ bnd_c8_1 bnd_a1099)) &
% 7.40/6.93 (((ALL X145.
% 7.40/6.93 bnd_ndr1_0 -->
% 7.40/6.93 ((bnd_ndr1_1 X145 & ~ bnd_c10_2 X145 bnd_a1100) &
% 7.40/6.93 bnd_c8_2 X145 bnd_a1100 |
% 7.40/6.93 ~ bnd_c2_1 X145) |
% 7.40/6.93 ~ bnd_c5_1 X145) |
% 7.40/6.93 ~ bnd_c2_0) |
% 7.40/6.93 bnd_c5_0)) &
% 7.40/6.93 (ALL X146.
% 7.40/6.93 bnd_ndr1_0 -->
% 7.40/6.93 (~ bnd_c10_1 X146 | ~ bnd_c2_1 X146) |
% 7.40/6.93 (ALL X147.
% 7.40/6.93 bnd_ndr1_1 X146 -->
% 7.40/6.93 bnd_c3_2 X146 X147 | bnd_c2_2 X146 X147))) &
% 7.40/6.93 ((bnd_c3_0 |
% 7.40/6.93 (ALL X148.
% 7.40/6.93 bnd_ndr1_0 -->
% 7.40/6.93 (bnd_c8_1 X148 | bnd_c1_1 X148) |
% 7.40/6.93 ((bnd_ndr1_1 X148 & bnd_c4_2 X148 bnd_a1101) &
% 7.40/6.93 bnd_c5_2 X148 bnd_a1101) &
% 7.40/6.93 bnd_c3_2 X148 bnd_a1101)) |
% 7.40/6.93 (ALL X149.
% 7.40/6.93 bnd_ndr1_0 -->
% 7.40/6.93 ((ALL X150.
% 7.40/6.93 bnd_ndr1_1 X149 -->
% 7.40/6.93 (~ bnd_c2_2 X149 X150 | ~ bnd_c1_2 X149 X150) |
% 7.40/6.93 bnd_c10_2 X149 X150) |
% 7.40/6.93 ((bnd_ndr1_1 X149 & ~ bnd_c4_2 X149 bnd_a1102) &
% 7.40/6.93 ~ bnd_c5_2 X149 bnd_a1102) &
% 7.40/6.93 bnd_c8_2 X149 bnd_a1102) |
% 7.40/6.93 bnd_c3_1 X149))) &
% 7.40/6.93 ((bnd_c9_0 | bnd_c6_0) |
% 7.40/6.93 (ALL X151.
% 7.40/6.93 bnd_ndr1_0 -->
% 7.40/6.93 (bnd_c4_1 X151 | ~ bnd_c1_1 X151) |
% 7.40/6.93 (bnd_ndr1_1 X151 & ~ bnd_c2_2 X151 bnd_a1103) &
% 7.40/6.93 ~ bnd_c7_2 X151 bnd_a1103))) &
% 7.40/6.93 ((ALL X152.
% 7.40/6.93 bnd_ndr1_0 -->
% 7.40/6.93 (((bnd_ndr1_1 X152 & ~ bnd_c3_2 X152 bnd_a1104) &
% 7.40/6.93 bnd_c9_2 X152 bnd_a1104) &
% 7.40/6.93 ~ bnd_c2_2 X152 bnd_a1104 |
% 7.40/6.93 ~ bnd_c2_1 X152) |
% 7.40/6.93 bnd_c3_1 X152) |
% 7.40/6.93 (ALL X153.
% 7.40/6.93 bnd_ndr1_0 -->
% 7.40/6.93 (bnd_c6_1 X153 | bnd_c3_1 X153) |
% 7.40/6.93 ((bnd_ndr1_1 X153 & bnd_c1_2 X153 bnd_a1105) &
% 7.40/6.93 ~ bnd_c5_2 X153 bnd_a1105) &
% 7.40/6.93 ~ bnd_c8_2 X153 bnd_a1105))) &
% 7.40/6.93 ((bnd_c3_0 | bnd_c4_0) | bnd_c6_0)) &
% 7.40/6.93 (((ALL X154. bnd_ndr1_0 --> ~ bnd_c3_1 X154 | ~ bnd_c8_1 X154) |
% 7.40/6.93 (((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a1106) &
% 7.40/6.93 ~ bnd_c6_2 bnd_a1106 bnd_a1107) &
% 7.40/6.93 bnd_c4_2 bnd_a1106 bnd_a1107) &
% 7.40/6.93 bnd_c9_2 bnd_a1106 bnd_a1107) &
% 7.40/6.93 bnd_ndr1_1 bnd_a1106) &
% 7.40/6.93 ~ bnd_c10_2 bnd_a1106 bnd_a1108) &
% 7.40/6.93 ~ bnd_c3_2 bnd_a1106 bnd_a1108) &
% 7.40/6.93 ~ bnd_c8_2 bnd_a1106 bnd_a1108) |
% 7.40/6.93 ~ bnd_c1_0)) &
% 7.40/6.93 (((ALL X155.
% 7.40/6.93 bnd_ndr1_0 -->
% 7.40/6.93 (((bnd_ndr1_1 X155 & ~ bnd_c1_2 X155 bnd_a1109) &
% 7.40/6.93 bnd_c4_2 X155 bnd_a1109) &
% 7.40/6.93 ~ bnd_c2_2 X155 bnd_a1109 |
% 7.40/6.93 (ALL X156.
% 7.40/6.93 bnd_ndr1_1 X155 -->
% 7.40/6.93 bnd_c10_2 X155 X156 | bnd_c2_2 X155 X156)) |
% 7.40/6.93 (ALL X157.
% 7.40/6.93 bnd_ndr1_1 X155 -->
% 7.40/6.93 (~ bnd_c3_2 X155 X157 | bnd_c10_2 X155 X157) |
% 7.40/6.93 bnd_c8_2 X155 X157)) |
% 7.40/6.93 bnd_c9_0) |
% 7.40/6.93 bnd_c4_0)) &
% 7.40/6.93 (((ALL X158.
% 7.40/6.93 bnd_ndr1_0 -->
% 7.40/6.93 bnd_c10_1 X158 |
% 7.40/6.93 ((bnd_ndr1_1 X158 & ~ bnd_c10_2 X158 bnd_a1110) &
% 7.40/6.93 ~ bnd_c7_2 X158 bnd_a1110) &
% 7.40/6.93 ~ bnd_c2_2 X158 bnd_a1110) |
% 7.40/6.93 (ALL X159.
% 7.40/6.93 bnd_ndr1_0 -->
% 7.40/6.93 (((bnd_ndr1_1 X159 & bnd_c10_2 X159 bnd_a1111) &
% 7.40/6.93 bnd_c9_2 X159 bnd_a1111) &
% 7.40/6.93 ~ bnd_c3_2 X159 bnd_a1111 |
% 7.40/6.93 ~ bnd_c6_1 X159) |
% 7.40/6.93 ((bnd_ndr1_1 X159 & ~ bnd_c9_2 X159 bnd_a1112) &
% 7.40/6.93 bnd_c7_2 X159 bnd_a1112) &
% 7.40/6.93 bnd_c5_2 X159 bnd_a1112)) |
% 7.40/6.93 (ALL X160.
% 7.40/6.93 bnd_ndr1_0 -->
% 7.40/6.93 ((bnd_ndr1_1 X160 & bnd_c6_2 X160 bnd_a1113) &
% 7.40/6.93 bnd_c3_2 X160 bnd_a1113) &
% 7.40/6.93 bnd_c1_2 X160 bnd_a1113 |
% 7.40/6.93 ~ bnd_c7_1 X160))) &
% 7.40/6.93 ((~ bnd_c5_0 |
% 7.40/6.93 ((bnd_ndr1_0 & bnd_c9_1 bnd_a1114) & bnd_c2_1 bnd_a1114) &
% 7.40/6.93 ~ bnd_c1_1 bnd_a1114) |
% 7.40/6.93 (ALL X161.
% 7.40/6.93 bnd_ndr1_0 -->
% 7.40/6.93 (bnd_c4_1 X161 | ~ bnd_c5_1 X161) | ~ bnd_c1_1 X161))) &
% 7.40/6.93 (~ bnd_c10_0 | ~ bnd_c1_0)) &
% 7.40/6.93 ((~ bnd_c10_0 |
% 7.40/6.93 (((((bnd_ndr1_0 &
% 7.40/6.93 (ALL X162.
% 7.40/6.93 bnd_ndr1_1 bnd_a1115 -->
% 7.40/6.93 (bnd_c9_2 bnd_a1115 X162 | bnd_c2_2 bnd_a1115 X162) |
% 7.40/6.93 bnd_c7_2 bnd_a1115 X162)) &
% 7.40/6.93 bnd_ndr1_1 bnd_a1115) &
% 7.40/6.93 ~ bnd_c10_2 bnd_a1115 bnd_a1116) &
% 7.40/6.93 bnd_c9_2 bnd_a1115 bnd_a1116) &
% 7.40/6.93 ~ bnd_c6_2 bnd_a1115 bnd_a1116) &
% 7.40/6.93 (ALL X163.
% 7.40/6.93 bnd_ndr1_1 bnd_a1115 -->
% 7.40/6.93 (~ bnd_c8_2 bnd_a1115 X163 | bnd_c9_2 bnd_a1115 X163) |
% 7.40/6.93 ~ bnd_c5_2 bnd_a1115 X163)) |
% 7.40/6.93 (ALL X164.
% 7.40/6.93 bnd_ndr1_0 -->
% 7.40/6.93 (bnd_c6_1 X164 | bnd_c3_1 X164) |
% 7.40/6.93 (bnd_ndr1_1 X164 & ~ bnd_c10_2 X164 bnd_a1117) &
% 7.40/6.93 ~ bnd_c1_2 X164 bnd_a1117))) &
% 7.40/6.93 (((((((bnd_ndr1_0 & bnd_c7_1 bnd_a1118) & bnd_c6_1 bnd_a1118) &
% 7.40/6.93 bnd_ndr1_1 bnd_a1118) &
% 7.40/6.93 ~ bnd_c5_2 bnd_a1118 bnd_a1119) &
% 7.40/6.93 bnd_c4_2 bnd_a1118 bnd_a1119) &
% 7.40/6.93 ~ bnd_c2_2 bnd_a1118 bnd_a1119 |
% 7.40/6.93 (((((bnd_ndr1_0 & ~ bnd_c1_1 bnd_a1120) & bnd_c4_1 bnd_a1120) &
% 7.40/6.93 bnd_ndr1_1 bnd_a1120) &
% 7.40/6.93 bnd_c2_2 bnd_a1120 bnd_a1121) &
% 7.40/6.93 bnd_c1_2 bnd_a1120 bnd_a1121) &
% 7.40/6.93 bnd_c9_2 bnd_a1120 bnd_a1121) |
% 7.40/6.93 bnd_c8_0)) &
% 7.40/6.93 (((ALL X165.
% 7.40/6.93 bnd_ndr1_0 -->
% 7.40/6.93 (bnd_c10_1 X165 |
% 7.40/6.93 ((bnd_ndr1_1 X165 & ~ bnd_c9_2 X165 bnd_a1122) &
% 7.40/6.93 ~ bnd_c2_2 X165 bnd_a1122) &
% 7.40/6.93 bnd_c10_2 X165 bnd_a1122) |
% 7.40/6.93 bnd_c8_1 X165) |
% 7.40/6.93 ~ bnd_c7_0) |
% 7.40/6.93 ((bnd_ndr1_0 & bnd_c5_1 bnd_a1123) &
% 7.40/6.93 (ALL X166.
% 7.40/6.93 bnd_ndr1_1 bnd_a1123 -->
% 7.40/6.93 (bnd_c7_2 bnd_a1123 X166 | bnd_c1_2 bnd_a1123 X166) |
% 7.40/6.93 bnd_c6_2 bnd_a1123 X166)) &
% 7.40/6.93 (ALL X167.
% 7.40/6.93 bnd_ndr1_1 bnd_a1123 -->
% 7.40/6.93 (bnd_c6_2 bnd_a1123 X167 | ~ bnd_c1_2 bnd_a1123 X167) |
% 7.40/6.93 ~ bnd_c10_2 bnd_a1123 X167))) &
% 7.40/6.93 (((ALL X168.
% 7.40/6.93 bnd_ndr1_0 --> (~ bnd_c7_1 X168 | bnd_c6_1 X168) | bnd_c10_1 X168) |
% 7.40/6.93 ~ bnd_c4_0) |
% 7.40/6.93 ((bnd_ndr1_0 &
% 7.40/6.93 (ALL X169.
% 7.40/6.93 bnd_ndr1_1 bnd_a1124 -->
% 7.40/6.93 (bnd_c6_2 bnd_a1124 X169 | ~ bnd_c4_2 bnd_a1124 X169) |
% 7.40/6.93 ~ bnd_c8_2 bnd_a1124 X169)) &
% 7.40/6.93 bnd_c7_1 bnd_a1124) &
% 7.40/6.93 ~ bnd_c2_1 bnd_a1124)) &
% 7.40/6.93 ((bnd_c8_0 |
% 7.40/6.93 ((((((((bnd_ndr1_0 &
% 7.40/6.93 bnd_ndr1_1 bnd_a1125) &
% 7.40/6.93 bnd_c8_2 bnd_a1125 bnd_a1126) &
% 7.40/6.93 ~ bnd_c3_2 bnd_a1125 bnd_a1126) &
% 7.40/6.93 ~ bnd_c10_2 bnd_a1125 bnd_a1126) &
% 7.40/6.93 ~ bnd_c4_1 bnd_a1125) &
% 7.40/6.93 bnd_ndr1_1 bnd_a1125) &
% 7.40/6.93 bnd_c5_2 bnd_a1125 bnd_a1127) &
% 7.40/6.93 ~ bnd_c1_2 bnd_a1125 bnd_a1127) &
% 7.40/6.93 bnd_c4_2 bnd_a1125 bnd_a1127) |
% 7.40/6.93 ~ bnd_c6_0)) &
% 7.40/6.93 ((~ bnd_c6_0 | bnd_c5_0) | bnd_c1_0)) &
% 7.40/6.93 (((ALL X170.
% 7.40/6.93 bnd_ndr1_0 -->
% 7.40/6.93 ((ALL X171.
% 7.40/6.93 bnd_ndr1_1 X170 -->
% 7.40/6.93 (~ bnd_c7_2 X170 X171 | ~ bnd_c3_2 X170 X171) |
% 7.40/6.93 ~ bnd_c1_2 X170 X171) |
% 7.40/6.93 (bnd_ndr1_1 X170 & ~ bnd_c7_2 X170 bnd_a1128) &
% 7.40/6.93 ~ bnd_c10_2 X170 bnd_a1128) |
% 7.40/6.93 ((bnd_ndr1_1 X170 & ~ bnd_c4_2 X170 bnd_a1129) & bnd_c1_2 X170 bnd_a1129) &
% 7.40/6.93 ~ bnd_c6_2 X170 bnd_a1129) |
% 7.40/6.93 bnd_c10_0) |
% 7.40/6.93 ((bnd_ndr1_0 & ~ bnd_c10_1 bnd_a1130) &
% 7.40/6.93 (ALL X172.
% 7.40/6.93 bnd_ndr1_1 bnd_a1130 -->
% 7.40/6.93 (bnd_c9_2 bnd_a1130 X172 | bnd_c1_2 bnd_a1130 X172) |
% 7.40/6.93 bnd_c10_2 bnd_a1130 X172)) &
% 7.40/6.93 ~ bnd_c8_1 bnd_a1130)) &
% 7.40/6.93 ((((((bnd_ndr1_0 &
% 7.40/6.93 (ALL X173.
% 7.40/6.93 bnd_ndr1_1 bnd_a1131 -->
% 7.40/6.93 (bnd_c4_2 bnd_a1131 X173 | bnd_c6_2 bnd_a1131 X173) |
% 7.40/6.93 bnd_c3_2 bnd_a1131 X173)) &
% 7.40/6.93 bnd_ndr1_1 bnd_a1131) &
% 7.40/6.93 ~ bnd_c4_2 bnd_a1131 bnd_a1132) &
% 7.40/6.93 bnd_c2_2 bnd_a1131 bnd_a1132) &
% 7.40/6.93 (ALL X174.
% 7.40/6.93 bnd_ndr1_1 bnd_a1131 -->
% 7.40/6.93 (bnd_c4_2 bnd_a1131 X174 | ~ bnd_c3_2 bnd_a1131 X174) |
% 7.40/6.93 ~ bnd_c1_2 bnd_a1131 X174) |
% 7.40/6.93 (((((bnd_ndr1_0 & bnd_c7_1 bnd_a1133) &
% 7.40/6.93 ~ bnd_c2_1 bnd_a1133) &
% 7.40/6.93 bnd_ndr1_1 bnd_a1133) &
% 7.40/6.93 ~ bnd_c2_2 bnd_a1133 bnd_a1134) &
% 7.40/6.93 bnd_c5_2 bnd_a1133 bnd_a1134) &
% 7.40/6.93 ~ bnd_c6_2 bnd_a1133 bnd_a1134) |
% 7.40/6.93 ~ bnd_c9_0)) &
% 7.40/6.93 ((bnd_c6_0 |
% 7.40/6.93 ((bnd_ndr1_0 & bnd_c9_1 bnd_a1135) &
% 7.40/6.93 bnd_c4_1 bnd_a1135) &
% 7.40/6.93 ~ bnd_c3_1 bnd_a1135) |
% 7.40/6.93 (((((bnd_ndr1_0 & ~ bnd_c9_1 bnd_a1136) &
% 7.40/6.93 bnd_ndr1_1 bnd_a1136) &
% 7.40/6.93 ~ bnd_c3_2 bnd_a1136 bnd_a1137) &
% 7.40/6.93 bnd_c1_2 bnd_a1136 bnd_a1137) &
% 7.40/6.93 ~ bnd_c6_2 bnd_a1136 bnd_a1137) &
% 7.40/6.93 bnd_c1_1 bnd_a1136)) &
% 7.40/6.94 (((ALL X175.
% 7.40/6.94 bnd_ndr1_0 -->
% 7.40/6.94 ((bnd_ndr1_1 X175 &
% 7.40/6.94 bnd_c10_2 X175 bnd_a1138) &
% 7.40/6.94 bnd_c2_2 X175 bnd_a1138) &
% 7.40/6.94 bnd_c9_2 X175 bnd_a1138 |
% 7.40/6.94 bnd_c3_1 X175) |
% 7.40/6.94 ~ bnd_c9_0) |
% 7.40/6.94 bnd_c4_0)) &
% 7.40/6.94 ((~ bnd_c9_0 |
% 7.40/6.94 (ALL X176.
% 7.40/6.94 bnd_ndr1_0 -->
% 7.40/6.94 ~ bnd_c10_1 X176 |
% 7.40/6.94 (ALL X177.
% 7.40/6.94 bnd_ndr1_1 X176 -->
% 7.40/6.94 (~ bnd_c10_2 X176 X177 | ~ bnd_c9_2 X176 X177) | ~ bnd_c8_2 X176 X177))) |
% 7.40/6.94 ~ bnd_c1_0)) &
% 7.40/6.94 ((((bnd_ndr1_0 & ~ bnd_c1_1 bnd_a1139) &
% 7.40/6.94 (ALL X178.
% 7.40/6.94 bnd_ndr1_1 bnd_a1139 -->
% 7.40/6.94 (bnd_c7_2 bnd_a1139 X178 |
% 7.40/6.94 ~ bnd_c6_2 bnd_a1139 X178) |
% 7.40/6.94 bnd_c5_2 bnd_a1139 X178)) &
% 7.40/6.94 ~ bnd_c10_1 bnd_a1139 |
% 7.40/6.94 ((((bnd_ndr1_0 & bnd_c6_1 bnd_a1140) &
% 7.40/6.94 bnd_ndr1_1 bnd_a1140) &
% 7.40/6.94 bnd_c9_2 bnd_a1140 bnd_a1141) &
% 7.40/6.94 ~ bnd_c1_2 bnd_a1140 bnd_a1141) &
% 7.40/6.94 ~ bnd_c4_2 bnd_a1140 bnd_a1141) |
% 7.40/6.94 ~ bnd_c1_0)) &
% 7.40/6.94 (((ALL X179.
% 7.40/6.94 bnd_ndr1_0 -->
% 7.40/6.94 (~ bnd_c2_1 X179 |
% 7.40/6.94 ((bnd_ndr1_1 X179 &
% 7.40/6.94 ~ bnd_c1_2 X179 bnd_a1142) &
% 7.40/6.94 ~ bnd_c8_2 X179 bnd_a1142) &
% 7.40/6.94 ~ bnd_c4_2 X179 bnd_a1142) |
% 7.40/6.94 bnd_c5_1 X179) |
% 7.40/6.94 bnd_c4_0) |
% 7.40/6.94 (bnd_ndr1_0 & bnd_c8_1 bnd_a1143) &
% 7.40/6.94 ~ bnd_c7_1 bnd_a1143)) &
% 7.40/6.94 ((bnd_c9_0 | ~ bnd_c4_0) |
% 7.40/6.94 (((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a1144) &
% 7.40/6.94 bnd_c4_2 bnd_a1144 bnd_a1145) &
% 7.40/6.94 ~ bnd_c1_2 bnd_a1144 bnd_a1145) &
% 7.40/6.94 bnd_c3_2 bnd_a1144 bnd_a1145) &
% 7.40/6.94 ~ bnd_c5_1 bnd_a1144) &
% 7.40/6.94 ~ bnd_c10_1 bnd_a1144)) &
% 7.40/6.94 ((bnd_c8_0 | ~ bnd_c7_0) |
% 7.40/6.94 (ALL X180.
% 7.40/6.94 bnd_ndr1_0 -->
% 7.40/6.94 (~ bnd_c5_1 X180 |
% 7.40/6.94 (ALL X181.
% 7.40/6.94 bnd_ndr1_1 X180 -->
% 7.40/6.94 ~ bnd_c1_2 X180 X181 |
% 7.40/6.94 ~ bnd_c8_2 X180 X181)) |
% 7.40/6.94 (ALL X182.
% 7.40/6.94 bnd_ndr1_1 X180 -->
% 7.40/6.94 (~ bnd_c2_2 X180 X182 |
% 7.40/6.94 ~ bnd_c6_2 X180 X182) |
% 7.40/6.94 ~ bnd_c1_2 X180 X182)))) &
% 7.40/6.94 ((~ bnd_c8_0 |
% 7.40/6.94 ((bnd_ndr1_0 &
% 7.40/6.94 (ALL X183.
% 7.40/6.94 bnd_ndr1_1 bnd_a1146 -->
% 7.40/6.94 (bnd_c9_2 bnd_a1146 X183 |
% 7.40/6.94 bnd_c8_2 bnd_a1146 X183) |
% 7.40/6.94 bnd_c10_2 bnd_a1146 X183)) &
% 7.40/6.94 ~ bnd_c2_1 bnd_a1146) &
% 7.40/6.94 ~ bnd_c1_1 bnd_a1146) |
% 7.40/6.94 (ALL X184.
% 7.40/6.94 bnd_ndr1_0 -->
% 7.40/6.94 (((bnd_ndr1_1 X184 &
% 7.40/6.94 ~ bnd_c9_2 X184 bnd_a1147) &
% 7.40/6.94 ~ bnd_c3_2 X184 bnd_a1147) &
% 7.40/6.94 ~ bnd_c6_2 X184 bnd_a1147 |
% 7.40/6.94 bnd_c7_1 X184) |
% 7.40/6.94 bnd_c8_1 X184))) &
% 7.40/6.94 ((~ bnd_c5_0 |
% 7.40/6.94 (ALL X185.
% 7.40/6.94 bnd_ndr1_0 -->
% 7.40/6.94 ((bnd_ndr1_1 X185 &
% 7.40/6.94 ~ bnd_c8_2 X185 bnd_a1148) &
% 7.40/6.94 bnd_c4_2 X185 bnd_a1148 |
% 7.40/6.94 ~ bnd_c2_1 X185) |
% 7.40/6.94 bnd_c9_1 X185)) |
% 7.40/6.94 (ALL X186.
% 7.40/6.94 bnd_ndr1_0 -->
% 7.40/6.94 (~ bnd_c5_1 X186 |
% 7.40/6.94 (ALL X187.
% 7.40/6.94 bnd_ndr1_1 X186 -->
% 7.40/6.94 ~ bnd_c8_2 X186 X187 |
% 7.40/6.94 bnd_c2_2 X186 X187)) |
% 7.40/6.94 bnd_c10_1 X186))) &
% 7.40/6.94 ((~ bnd_c4_0 |
% 7.40/6.94 (ALL X188.
% 7.40/6.94 bnd_ndr1_0 -->
% 7.40/6.94 (~ bnd_c5_1 X188 |
% 7.40/6.94 (bnd_ndr1_1 X188 & ~ bnd_c7_2 X188 bnd_a1149) &
% 7.40/6.94 bnd_c9_2 X188 bnd_a1149) |
% 7.40/6.94 (ALL X189.
% 7.40/6.94 bnd_ndr1_1 X188 -->
% 7.40/6.94 (bnd_c7_2 X188 X189 | bnd_c9_2 X188 X189) |
% 7.40/6.94 bnd_c6_2 X188 X189))) |
% 7.40/6.94 ~ bnd_c2_0)) &
% 7.40/6.94 ((((bnd_ndr1_0 & bnd_c10_1 bnd_a1150) &
% 7.40/6.94 bnd_c5_1 bnd_a1150) &
% 7.40/6.94 bnd_c1_1 bnd_a1150 |
% 7.40/6.94 (ALL X190.
% 7.40/6.94 bnd_ndr1_0 -->
% 7.40/6.94 ((ALL X191.
% 7.40/6.94 bnd_ndr1_1 X190 -->
% 7.40/6.94 (bnd_c4_2 X190 X191 | bnd_c8_2 X190 X191) |
% 7.40/6.94 ~ bnd_c5_2 X190 X191) |
% 7.40/6.94 ~ bnd_c7_1 X190) |
% 7.40/6.94 ~ bnd_c2_1 X190)) |
% 7.40/6.94 bnd_c2_0)) &
% 7.40/6.94 (bnd_c2_0 |
% 7.40/6.94 (ALL X192.
% 7.40/6.94 bnd_ndr1_0 -->
% 7.40/6.94 (~ bnd_c1_1 X192 |
% 7.40/6.94 ((bnd_ndr1_1 X192 & ~ bnd_c3_2 X192 bnd_a1151) &
% 7.40/6.94 bnd_c2_2 X192 bnd_a1151) &
% 7.40/6.94 ~ bnd_c5_2 X192 bnd_a1151) |
% 7.40/6.94 ((bnd_ndr1_1 X192 & ~ bnd_c10_2 X192 bnd_a1152) &
% 7.40/6.94 bnd_c8_2 X192 bnd_a1152) &
% 7.40/6.94 ~ bnd_c4_2 X192 bnd_a1152))) &
% 7.40/6.94 ((bnd_c8_0 | bnd_c9_0) |
% 7.40/6.94 (ALL X193.
% 7.40/6.94 bnd_ndr1_0 -->
% 7.40/6.94 (~ bnd_c5_1 X193 | ~ bnd_c7_1 X193) |
% 7.40/6.94 (ALL X194.
% 7.40/6.94 bnd_ndr1_1 X193 -->
% 7.40/6.94 (~ bnd_c6_2 X193 X194 | ~ bnd_c2_2 X193 X194) |
% 7.40/6.94 ~ bnd_c3_2 X193 X194)))) &
% 7.40/6.94 ((((bnd_ndr1_0 & bnd_c4_1 bnd_a1153) &
% 7.40/6.94 (ALL X195.
% 7.40/6.94 bnd_ndr1_1 bnd_a1153 -->
% 7.40/6.94 (bnd_c6_2 bnd_a1153 X195 |
% 7.40/6.94 ~ bnd_c10_2 bnd_a1153 X195) |
% 7.40/6.94 bnd_c9_2 bnd_a1153 X195)) &
% 7.40/6.94 ~ bnd_c9_1 bnd_a1153 |
% 7.40/6.94 bnd_c7_0) |
% 7.40/6.94 ((bnd_ndr1_0 & ~ bnd_c6_1 bnd_a1154) &
% 7.40/6.94 bnd_c9_1 bnd_a1154) &
% 7.40/6.94 (ALL X196.
% 7.40/6.94 bnd_ndr1_1 bnd_a1154 -->
% 7.40/6.94 (bnd_c4_2 bnd_a1154 X196 |
% 7.40/6.94 ~ bnd_c9_2 bnd_a1154 X196) |
% 7.40/6.94 bnd_c7_2 bnd_a1154 X196))) &
% 7.40/6.94 ((((bnd_ndr1_0 & bnd_c6_1 bnd_a1155) &
% 7.40/6.94 (ALL X197.
% 7.40/6.94 bnd_ndr1_1 bnd_a1155 -->
% 7.40/6.94 (bnd_c9_2 bnd_a1155 X197 |
% 7.40/6.94 bnd_c4_2 bnd_a1155 X197) |
% 7.40/6.94 bnd_c8_2 bnd_a1155 X197)) &
% 7.40/6.94 (ALL X198.
% 7.40/6.94 bnd_ndr1_1 bnd_a1155 -->
% 7.40/6.94 (bnd_c3_2 bnd_a1155 X198 | bnd_c1_2 bnd_a1155 X198) |
% 7.40/6.94 ~ bnd_c9_2 bnd_a1155 X198) |
% 7.40/6.94 ~ bnd_c10_0) |
% 7.40/6.94 (ALL X199.
% 7.40/6.94 bnd_ndr1_0 -->
% 7.40/6.94 (((bnd_ndr1_1 X199 & ~ bnd_c10_2 X199 bnd_a1156) &
% 7.40/6.94 bnd_c6_2 X199 bnd_a1156) &
% 7.40/6.94 ~ bnd_c9_2 X199 bnd_a1156 |
% 7.40/6.94 ((bnd_ndr1_1 X199 & bnd_c4_2 X199 bnd_a1157) &
% 7.40/6.94 bnd_c6_2 X199 bnd_a1157) &
% 7.40/6.94 ~ bnd_c10_2 X199 bnd_a1157) |
% 7.40/6.94 ((bnd_ndr1_1 X199 & ~ bnd_c7_2 X199 bnd_a1158) &
% 7.40/6.94 bnd_c6_2 X199 bnd_a1158) &
% 7.40/6.94 ~ bnd_c8_2 X199 bnd_a1158))) &
% 7.40/6.94 (((ALL X200.
% 7.40/6.94 bnd_ndr1_0 -->
% 7.40/6.94 ((ALL X201.
% 7.40/6.94 bnd_ndr1_1 X200 -->
% 7.40/6.94 (~ bnd_c8_2 X200 X201 | bnd_c9_2 X200 X201) |
% 7.40/6.94 ~ bnd_c5_2 X200 X201) |
% 7.40/6.94 ((bnd_ndr1_1 X200 & bnd_c2_2 X200 bnd_a1159) &
% 7.40/6.94 ~ bnd_c9_2 X200 bnd_a1159) &
% 7.40/6.94 bnd_c10_2 X200 bnd_a1159) |
% 7.40/6.94 bnd_c9_1 X200) |
% 7.40/6.94 (((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a1160) &
% 7.40/6.94 ~ bnd_c10_2 bnd_a1160 bnd_a1161) &
% 7.40/6.94 bnd_c7_2 bnd_a1160 bnd_a1161) &
% 7.40/6.94 bnd_c2_2 bnd_a1160 bnd_a1161) &
% 7.40/6.94 (ALL X202.
% 7.40/6.94 bnd_ndr1_1 bnd_a1160 -->
% 7.40/6.94 ~ bnd_c9_2 bnd_a1160 X202 |
% 7.40/6.94 bnd_c10_2 bnd_a1160 X202)) &
% 7.40/6.94 ~ bnd_c6_1 bnd_a1160) |
% 7.40/6.94 ~ bnd_c7_0)) &
% 7.40/6.94 ((~ bnd_c5_0 |
% 7.40/6.94 ((((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a1162) &
% 7.40/6.94 ~ bnd_c8_2 bnd_a1162 bnd_a1163) &
% 7.40/6.94 ~ bnd_c10_2 bnd_a1162 bnd_a1163) &
% 7.40/6.94 ~ bnd_c3_2 bnd_a1162 bnd_a1163) &
% 7.40/6.94 ~ bnd_c6_1 bnd_a1162) &
% 7.40/6.94 bnd_ndr1_1 bnd_a1162) &
% 7.40/6.94 ~ bnd_c5_2 bnd_a1162 bnd_a1164) &
% 7.40/6.94 bnd_c4_2 bnd_a1162 bnd_a1164) &
% 7.40/6.94 bnd_c8_2 bnd_a1162 bnd_a1164) |
% 7.40/6.94 bnd_c4_0)) &
% 7.40/6.94 ((ALL X203.
% 7.40/6.94 bnd_ndr1_0 -->
% 7.40/6.94 ((ALL X204.
% 7.40/6.94 bnd_ndr1_1 X203 -->
% 7.40/6.94 (~ bnd_c3_2 X203 X204 | ~ bnd_c7_2 X203 X204) |
% 7.40/6.94 ~ bnd_c9_2 X203 X204) |
% 7.40/6.94 (ALL X205.
% 7.40/6.94 bnd_ndr1_1 X203 -->
% 7.40/6.94 (bnd_c2_2 X203 X205 | bnd_c8_2 X203 X205) |
% 7.40/6.94 ~ bnd_c6_2 X203 X205)) |
% 7.40/6.94 bnd_c7_1 X203) |
% 7.40/6.94 bnd_c7_0)) &
% 7.40/6.94 ((bnd_c2_0 |
% 7.40/6.94 (((((bnd_ndr1_0 & ~ bnd_c4_1 bnd_a1165) &
% 7.40/6.94 bnd_c10_1 bnd_a1165) &
% 7.40/6.94 bnd_ndr1_1 bnd_a1165) &
% 7.40/6.94 ~ bnd_c5_2 bnd_a1165 bnd_a1166) &
% 7.40/6.94 bnd_c6_2 bnd_a1165 bnd_a1166) &
% 7.40/6.94 bnd_c9_2 bnd_a1165 bnd_a1166) |
% 7.40/6.94 ((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a1167) &
% 7.40/6.94 ~ bnd_c10_2 bnd_a1167 bnd_a1168) &
% 7.40/6.94 ~ bnd_c7_2 bnd_a1167 bnd_a1168) &
% 7.40/6.94 ~ bnd_c3_2 bnd_a1167 bnd_a1168) &
% 7.40/6.94 ~ bnd_c7_1 bnd_a1167)) &
% 7.40/6.94 ((bnd_c2_0 |
% 7.40/6.94 (ALL X206.
% 7.40/6.94 bnd_ndr1_0 -->
% 7.40/6.94 (((bnd_ndr1_1 X206 & ~ bnd_c10_2 X206 bnd_a1169) &
% 7.40/6.94 bnd_c7_2 X206 bnd_a1169) &
% 7.40/6.94 ~ bnd_c1_2 X206 bnd_a1169 |
% 7.40/6.94 (ALL X207.
% 7.40/6.94 bnd_ndr1_1 X206 -->
% 7.40/6.94 (bnd_c2_2 X206 X207 | ~ bnd_c9_2 X206 X207) |
% 7.40/6.94 ~ bnd_c8_2 X206 X207)) |
% 7.40/6.94 (ALL X208.
% 7.40/6.94 bnd_ndr1_1 X206 -->
% 7.40/6.94 (~ bnd_c9_2 X206 X208 | bnd_c2_2 X206 X208) |
% 7.40/6.94 bnd_c3_2 X206 X208))) |
% 7.40/6.94 (ALL X209.
% 7.40/6.94 bnd_ndr1_0 -->
% 7.40/6.94 (~ bnd_c8_1 X209 |
% 7.40/6.94 (ALL X210.
% 7.40/6.94 bnd_ndr1_1 X209 -->
% 7.40/6.94 (~ bnd_c6_2 X209 X210 | ~ bnd_c1_2 X209 X210) |
% 7.40/6.94 ~ bnd_c8_2 X209 X210)) |
% 7.40/6.94 ~ bnd_c10_1 X209))) &
% 7.40/6.94 (((((((bnd_ndr1_0 & bnd_c2_1 bnd_a1170) &
% 7.40/6.94 (ALL X211.
% 7.40/6.94 bnd_ndr1_1 bnd_a1170 -->
% 7.40/6.94 (bnd_c8_2 bnd_a1170 X211 | ~ bnd_c6_2 bnd_a1170 X211) |
% 7.40/6.94 bnd_c10_2 bnd_a1170 X211)) &
% 7.40/6.94 bnd_ndr1_1 bnd_a1170) &
% 7.40/6.94 bnd_c6_2 bnd_a1170 bnd_a1171) &
% 7.40/6.94 ~ bnd_c9_2 bnd_a1170 bnd_a1171) &
% 7.40/6.94 bnd_c10_2 bnd_a1170 bnd_a1171 |
% 7.40/6.94 bnd_c8_0) |
% 7.40/6.94 bnd_c4_0)) &
% 7.40/6.94 (((ALL X212.
% 7.40/6.94 bnd_ndr1_0 -->
% 7.40/6.94 (bnd_c3_1 X212 | bnd_c10_1 X212) | ~ bnd_c7_1 X212) |
% 7.40/6.94 bnd_c8_0) |
% 7.40/6.94 ~ bnd_c5_0)) &
% 7.40/6.94 (((ALL X213.
% 7.40/6.94 bnd_ndr1_0 -->
% 7.40/6.94 (~ bnd_c7_1 X213 | bnd_c4_1 X213) |
% 7.40/6.94 ((bnd_ndr1_1 X213 & bnd_c4_2 X213 bnd_a1172) &
% 7.40/6.94 bnd_c1_2 X213 bnd_a1172) &
% 7.40/6.94 bnd_c10_2 X213 bnd_a1172) |
% 7.40/6.94 ~ bnd_c2_0) |
% 7.40/6.94 ((((bnd_ndr1_0 & bnd_c3_1 bnd_a1173) &
% 7.40/6.94 (ALL X214.
% 7.40/6.94 bnd_ndr1_1 bnd_a1173 -->
% 7.40/6.94 (bnd_c5_2 bnd_a1173 X214 | bnd_c4_2 bnd_a1173 X214) |
% 7.40/6.94 ~ bnd_c9_2 bnd_a1173 X214)) &
% 7.40/6.94 bnd_ndr1_1 bnd_a1173) &
% 7.40/6.94 bnd_c4_2 bnd_a1173 bnd_a1174) &
% 7.40/6.94 ~ bnd_c5_2 bnd_a1173 bnd_a1174)) &
% 7.40/6.94 ((~ bnd_c3_0 | bnd_c7_0) |
% 7.40/6.94 (ALL X215.
% 7.40/6.94 bnd_ndr1_0 -->
% 7.40/6.94 (bnd_ndr1_1 X215 & ~ bnd_c7_2 X215 bnd_a1175 |
% 7.40/6.94 ~ bnd_c5_1 X215) |
% 7.40/6.94 (ALL X216.
% 7.40/6.94 bnd_ndr1_1 X215 -->
% 7.40/6.94 (~ bnd_c3_2 X215 X216 | bnd_c5_2 X215 X216) |
% 7.40/6.94 bnd_c6_2 X215 X216)))) &
% 7.40/6.94 (bnd_c1_0 | ~ bnd_c7_0)) &
% 7.40/6.94 (((ALL X217.
% 7.40/6.94 bnd_ndr1_0 -->
% 7.40/6.94 ((ALL X218.
% 7.40/6.94 bnd_ndr1_1 X217 -->
% 7.40/6.94 (bnd_c3_2 X217 X218 | bnd_c4_2 X217 X218) |
% 7.40/6.94 bnd_c7_2 X217 X218) |
% 7.40/6.94 bnd_c9_1 X217) |
% 7.40/6.94 ((bnd_ndr1_1 X217 & bnd_c6_2 X217 bnd_a1176) &
% 7.40/6.94 bnd_c7_2 X217 bnd_a1176) &
% 7.40/6.94 ~ bnd_c1_2 X217 bnd_a1176) |
% 7.40/6.94 (ALL X219.
% 7.40/6.94 bnd_ndr1_0 -->
% 7.40/6.94 (~ bnd_c1_1 X219 |
% 7.40/6.94 ((bnd_ndr1_1 X219 & bnd_c9_2 X219 bnd_a1177) &
% 7.40/6.94 bnd_c8_2 X219 bnd_a1177) &
% 7.40/6.94 bnd_c6_2 X219 bnd_a1177) |
% 7.40/6.94 ((bnd_ndr1_1 X219 & ~ bnd_c4_2 X219 bnd_a1178) &
% 7.40/6.94 bnd_c2_2 X219 bnd_a1178) &
% 7.40/6.94 bnd_c1_2 X219 bnd_a1178)) |
% 7.40/6.94 (ALL X220.
% 7.40/6.94 bnd_ndr1_0 -->
% 7.40/6.94 (((bnd_ndr1_1 X220 & ~ bnd_c2_2 X220 bnd_a1179) &
% 7.40/6.94 bnd_c8_2 X220 bnd_a1179) &
% 7.40/6.94 ~ bnd_c1_2 X220 bnd_a1179 |
% 7.40/6.94 ((bnd_ndr1_1 X220 & bnd_c10_2 X220 bnd_a1180) &
% 7.40/6.94 ~ bnd_c5_2 X220 bnd_a1180) &
% 7.40/6.94 ~ bnd_c1_2 X220 bnd_a1180) |
% 7.40/6.94 bnd_c5_1 X220))) &
% 7.40/6.94 (((ALL X221.
% 7.40/6.94 bnd_ndr1_0 -->
% 7.40/6.94 ((ALL X222.
% 7.40/6.94 bnd_ndr1_1 X221 -->
% 7.40/6.94 (bnd_c10_2 X221 X222 | bnd_c1_2 X221 X222) |
% 7.40/6.94 ~ bnd_c8_2 X221 X222) |
% 7.40/6.94 ((bnd_ndr1_1 X221 & bnd_c9_2 X221 bnd_a1181) &
% 7.40/6.94 ~ bnd_c1_2 X221 bnd_a1181) &
% 7.40/6.94 bnd_c3_2 X221 bnd_a1181) |
% 7.40/6.94 ((bnd_ndr1_1 X221 & bnd_c8_2 X221 bnd_a1182) &
% 7.40/6.94 ~ bnd_c9_2 X221 bnd_a1182) &
% 7.40/6.94 ~ bnd_c4_2 X221 bnd_a1182) |
% 7.40/6.94 ((((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a1183) &
% 7.40/6.94 ~ bnd_c9_2 bnd_a1183 bnd_a1184) &
% 7.40/6.94 bnd_c8_2 bnd_a1183 bnd_a1184) &
% 7.40/6.94 bnd_c3_2 bnd_a1183 bnd_a1184) &
% 7.40/6.94 ~ bnd_c10_1 bnd_a1183) &
% 7.40/6.94 bnd_ndr1_1 bnd_a1183) &
% 7.40/6.94 bnd_c5_2 bnd_a1183 bnd_a1185) &
% 7.40/6.94 bnd_c10_2 bnd_a1183 bnd_a1185) &
% 7.40/6.94 ~ bnd_c7_2 bnd_a1183 bnd_a1185) |
% 7.40/6.94 (ALL X223.
% 7.40/6.94 bnd_ndr1_0 -->
% 7.40/6.94 ~ bnd_c10_1 X223 |
% 7.40/6.94 (ALL X224.
% 7.40/6.94 bnd_ndr1_1 X223 -->
% 7.40/6.94 bnd_c8_2 X223 X224 | bnd_c1_2 X223 X224)))) &
% 7.40/6.94 (((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a1186) &
% 7.40/6.94 bnd_c3_2 bnd_a1186 bnd_a1187) &
% 7.40/6.94 ~ bnd_c6_2 bnd_a1186 bnd_a1187) &
% 7.40/6.94 bnd_ndr1_1 bnd_a1186) &
% 7.40/6.94 ~ bnd_c1_2 bnd_a1186 bnd_a1188) &
% 7.40/6.94 bnd_c3_2 bnd_a1186 bnd_a1188) &
% 7.40/6.94 bnd_c3_1 bnd_a1186 |
% 7.40/6.94 bnd_c2_0)) &
% 7.40/6.94 ((~ bnd_c6_0 | bnd_c1_0) |
% 7.40/6.94 (ALL X225.
% 7.40/6.94 bnd_ndr1_0 -->
% 7.40/6.94 (~ bnd_c9_1 X225 |
% 7.40/6.94 (ALL X226.
% 7.40/6.94 bnd_ndr1_1 X225 -->
% 7.40/6.94 (bnd_c3_2 X225 X226 | ~ bnd_c1_2 X225 X226) |
% 7.40/6.94 bnd_c5_2 X225 X226)) |
% 7.40/6.94 ((bnd_ndr1_1 X225 & bnd_c1_2 X225 bnd_a1189) &
% 7.40/6.94 ~ bnd_c6_2 X225 bnd_a1189) &
% 7.40/6.94 bnd_c2_2 X225 bnd_a1189)))
% 20.23/19.74 Unfolded term: ~ ((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((bnd_ndr1_0 &
% 20.23/19.74 bnd_ndr1_1 bnd_a960) &
% 20.23/19.74 ~ bnd_c10_2 bnd_a960 bnd_a961) &
% 20.23/19.74 ~ bnd_c1_2 bnd_a960 bnd_a961) &
% 20.23/19.74 ~ bnd_c5_2 bnd_a960 bnd_a961) &
% 20.23/19.74 ~ bnd_c6_1 bnd_a960 |
% 20.23/19.74 ((bnd_ndr1_0 &
% 20.23/19.74 (ALL U.
% 20.23/19.74 bnd_ndr1_1 bnd_a962 -->
% 20.23/19.74 (~ bnd_c7_2 bnd_a962 U | ~ bnd_c5_2 bnd_a962 U) |
% 20.23/19.74 bnd_c8_2 bnd_a962 U)) &
% 20.23/19.74 (ALL V.
% 20.23/19.74 bnd_ndr1_1 bnd_a962 -->
% 20.23/19.74 (~ bnd_c7_2 bnd_a962 V | bnd_c1_2 bnd_a962 V) |
% 20.23/19.74 ~ bnd_c3_2 bnd_a962 V)) &
% 20.23/19.74 (ALL W.
% 20.23/19.74 bnd_ndr1_1 bnd_a962 -->
% 20.23/19.74 (bnd_c7_2 bnd_a962 W | bnd_c9_2 bnd_a962 W) |
% 20.23/19.74 bnd_c10_2 bnd_a962 W)) |
% 20.23/19.74 ~ bnd_c5_0) &
% 20.23/19.74 ((((((bnd_ndr1_0 & ~ bnd_c6_1 bnd_a963) &
% 20.23/19.74 (ALL X.
% 20.23/19.74 bnd_ndr1_1 bnd_a963 -->
% 20.23/19.74 (bnd_c9_2 bnd_a963 X | bnd_c10_2 bnd_a963 X) |
% 20.23/19.74 bnd_c3_2 bnd_a963 X)) &
% 20.23/19.74 bnd_ndr1_1 bnd_a963) &
% 20.23/19.74 bnd_c1_2 bnd_a963 bnd_a964) &
% 20.23/19.74 bnd_c4_2 bnd_a963 bnd_a964) &
% 20.23/19.74 ~ bnd_c5_2 bnd_a963 bnd_a964 |
% 20.23/19.74 ~ bnd_c2_0)) &
% 20.23/19.74 ((~ bnd_c3_0 |
% 20.23/19.74 (ALL Y.
% 20.23/19.74 bnd_ndr1_0 -->
% 20.23/19.74 ((ALL Z.
% 20.23/19.74 bnd_ndr1_1 Y -->
% 20.23/19.74 (~ bnd_c4_2 Y Z | ~ bnd_c2_2 Y Z) | bnd_c6_2 Y Z) |
% 20.23/19.74 (ALL X1.
% 20.23/19.74 bnd_ndr1_1 Y -->
% 20.23/19.74 bnd_c10_2 Y X1 | ~ bnd_c6_2 Y X1)) |
% 20.23/19.74 ((bnd_ndr1_1 Y & ~ bnd_c4_2 Y bnd_a965) &
% 20.23/19.74 bnd_c10_2 Y bnd_a965) &
% 20.23/19.74 ~ bnd_c1_2 Y bnd_a965)) |
% 20.23/19.74 ~ bnd_c9_0)) &
% 20.23/19.74 ((((bnd_ndr1_0 & ~ bnd_c9_1 bnd_a966) & ~ bnd_c4_1 bnd_a966) &
% 20.23/19.74 bnd_c6_1 bnd_a966 |
% 20.23/19.74 bnd_c7_0) |
% 20.23/19.74 (((((bnd_ndr1_0 & ~ bnd_c3_1 bnd_a967) & bnd_c4_1 bnd_a967) &
% 20.23/19.74 bnd_ndr1_1 bnd_a967) &
% 20.23/19.74 bnd_c1_2 bnd_a967 bnd_a968) &
% 20.23/19.74 ~ bnd_c8_2 bnd_a967 bnd_a968) &
% 20.23/19.74 bnd_c6_2 bnd_a967 bnd_a968)) &
% 20.23/19.74 ((~ bnd_c6_0 | bnd_c3_0) |
% 20.23/19.74 (ALL X2.
% 20.23/19.74 bnd_ndr1_0 -->
% 20.23/19.74 (bnd_c9_1 X2 | ~ bnd_c3_1 X2) |
% 20.23/19.74 ((bnd_ndr1_1 X2 & ~ bnd_c5_2 X2 bnd_a969) &
% 20.23/19.74 bnd_c8_2 X2 bnd_a969) &
% 20.23/19.74 bnd_c10_2 X2 bnd_a969))) &
% 20.23/19.74 ((((bnd_ndr1_0 &
% 20.23/19.74 (ALL X3.
% 20.23/19.74 bnd_ndr1_1 bnd_a970 -->
% 20.23/19.74 (bnd_c10_2 bnd_a970 X3 | ~ bnd_c1_2 bnd_a970 X3) |
% 20.23/19.74 bnd_c5_2 bnd_a970 X3)) &
% 20.23/19.74 bnd_c5_1 bnd_a970) &
% 20.23/19.74 ~ bnd_c2_1 bnd_a970 |
% 20.23/19.74 ((bnd_ndr1_0 & ~ bnd_c9_1 bnd_a971) &
% 20.23/19.74 (ALL X4.
% 20.23/19.74 bnd_ndr1_1 bnd_a971 -->
% 20.23/19.74 (bnd_c8_2 bnd_a971 X4 | bnd_c1_2 bnd_a971 X4) |
% 20.23/19.74 ~ bnd_c7_2 bnd_a971 X4)) &
% 20.23/19.74 ~ bnd_c4_1 bnd_a971) |
% 20.23/19.74 (ALL X5.
% 20.23/19.74 bnd_ndr1_0 -->
% 20.23/19.74 bnd_c9_1 X5 |
% 20.23/19.74 (ALL X6.
% 20.23/19.74 bnd_ndr1_1 X5 -->
% 20.23/19.74 (bnd_c6_2 X5 X6 | ~ bnd_c5_2 X5 X6) |
% 20.23/19.74 ~ bnd_c4_2 X5 X6)))) &
% 20.23/19.74 ((~ bnd_c5_0 |
% 20.23/19.74 (bnd_ndr1_0 & bnd_c7_1 bnd_a972) &
% 20.23/19.74 (ALL X7.
% 20.23/19.74 bnd_ndr1_1 bnd_a972 -->
% 20.23/19.74 (bnd_c7_2 bnd_a972 X7 | bnd_c8_2 bnd_a972 X7) |
% 20.23/19.74 ~ bnd_c4_2 bnd_a972 X7)) |
% 20.23/19.74 ((bnd_ndr1_0 & ~ bnd_c1_1 bnd_a973) &
% 20.23/19.74 (ALL X8.
% 20.23/19.74 bnd_ndr1_1 bnd_a973 -->
% 20.23/19.74 ~ bnd_c7_2 bnd_a973 X8 | ~ bnd_c1_2 bnd_a973 X8)) &
% 20.23/19.74 bnd_c9_1 bnd_a973)) &
% 20.23/19.74 ((~ bnd_c8_0 |
% 20.23/19.74 (ALL X9.
% 20.23/19.74 bnd_ndr1_0 -->
% 20.23/19.74 (bnd_c6_1 X9 | bnd_c1_1 X9) |
% 20.23/19.74 ((bnd_ndr1_1 X9 & ~ bnd_c9_2 X9 bnd_a974) &
% 20.23/19.74 ~ bnd_c4_2 X9 bnd_a974) &
% 20.23/19.74 bnd_c1_2 X9 bnd_a974)) |
% 20.23/19.74 (ALL X10.
% 20.23/19.74 bnd_ndr1_0 -->
% 20.23/19.74 (((bnd_ndr1_1 X10 & ~ bnd_c9_2 X10 bnd_a975) &
% 20.23/19.74 bnd_c8_2 X10 bnd_a975) &
% 20.23/19.74 ~ bnd_c7_2 X10 bnd_a975 |
% 20.23/19.74 ~ bnd_c1_1 X10) |
% 20.23/19.74 bnd_c6_1 X10))) &
% 20.23/19.74 ((~ bnd_c3_0 |
% 20.23/19.74 (ALL X11.
% 20.23/19.74 bnd_ndr1_0 -->
% 20.23/19.74 (((bnd_ndr1_1 X11 & ~ bnd_c1_2 X11 bnd_a976) &
% 20.23/19.74 bnd_c8_2 X11 bnd_a976) &
% 20.23/19.74 ~ bnd_c6_2 X11 bnd_a976 |
% 20.23/19.74 bnd_c2_1 X11) |
% 20.23/19.74 bnd_c7_1 X11)) |
% 20.23/19.74 ((bnd_ndr1_0 & bnd_c9_1 bnd_a977) & ~ bnd_c1_1 bnd_a977) &
% 20.23/19.74 (ALL X12.
% 20.23/19.74 bnd_ndr1_1 bnd_a977 -->
% 20.23/19.74 (bnd_c5_2 bnd_a977 X12 | ~ bnd_c1_2 bnd_a977 X12) |
% 20.23/19.74 ~ bnd_c9_2 bnd_a977 X12))) &
% 20.23/19.74 ((bnd_c1_0 |
% 20.23/19.74 ((bnd_ndr1_0 & ~ bnd_c3_1 bnd_a978) & bnd_c8_1 bnd_a978) &
% 20.23/19.74 (ALL X13.
% 20.23/19.74 bnd_ndr1_1 bnd_a978 -->
% 20.23/19.74 ~ bnd_c6_2 bnd_a978 X13 | bnd_c4_2 bnd_a978 X13)) |
% 20.23/19.74 bnd_c6_0)) &
% 20.23/19.74 ((bnd_c6_0 |
% 20.23/19.74 (ALL X14.
% 20.23/19.74 bnd_ndr1_0 -->
% 20.23/19.74 (bnd_c2_1 X14 | ~ bnd_c3_1 X14) |
% 20.23/19.74 ((bnd_ndr1_1 X14 & ~ bnd_c5_2 X14 bnd_a979) &
% 20.23/19.74 bnd_c7_2 X14 bnd_a979) &
% 20.23/19.74 ~ bnd_c2_2 X14 bnd_a979)) |
% 20.23/19.74 ~ bnd_c4_0)) &
% 20.23/19.74 (~ bnd_c5_0 |
% 20.23/19.74 (((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a980) & bnd_c6_2 bnd_a980 bnd_a981) &
% 20.23/19.74 ~ bnd_c4_2 bnd_a980 bnd_a981) &
% 20.23/19.74 bnd_c5_2 bnd_a980 bnd_a981) &
% 20.23/19.74 ~ bnd_c7_1 bnd_a980) &
% 20.23/19.74 (ALL X15.
% 20.23/19.74 bnd_ndr1_1 bnd_a980 -->
% 20.23/19.74 bnd_c1_2 bnd_a980 X15 | bnd_c3_2 bnd_a980 X15))) &
% 20.23/19.74 (((ALL X16.
% 20.23/19.74 bnd_ndr1_0 -->
% 20.23/19.74 ((ALL X17.
% 20.23/19.74 bnd_ndr1_1 X16 --> bnd_c2_2 X16 X17 | bnd_c5_2 X16 X17) |
% 20.23/19.74 ((bnd_ndr1_1 X16 & ~ bnd_c6_2 X16 bnd_a982) &
% 20.23/19.74 ~ bnd_c10_2 X16 bnd_a982) &
% 20.23/19.74 bnd_c2_2 X16 bnd_a982) |
% 20.23/19.74 ~ bnd_c1_1 X16) |
% 20.23/19.74 bnd_c3_0) |
% 20.23/19.74 ~ bnd_c8_0)) &
% 20.23/19.74 (((ALL X18.
% 20.23/19.74 bnd_ndr1_0 -->
% 20.23/19.74 (~ bnd_c2_1 X18 | bnd_c1_1 X18) |
% 20.23/19.74 ((bnd_ndr1_1 X18 & ~ bnd_c2_2 X18 bnd_a983) &
% 20.23/19.74 ~ bnd_c4_2 X18 bnd_a983) &
% 20.23/19.74 bnd_c10_2 X18 bnd_a983) |
% 20.23/19.74 ~ bnd_c5_0) |
% 20.23/19.74 bnd_c9_0)) &
% 20.23/19.74 ((bnd_c4_0 | bnd_c8_0) | bnd_c5_0)) &
% 20.23/19.74 ((ALL X19.
% 20.23/19.74 bnd_ndr1_0 -->
% 20.23/19.74 (bnd_c3_1 X19 |
% 20.23/19.74 ((bnd_ndr1_1 X19 & bnd_c10_2 X19 bnd_a984) & bnd_c6_2 X19 bnd_a984) &
% 20.23/19.74 ~ bnd_c7_2 X19 bnd_a984) |
% 20.23/19.74 bnd_c6_1 X19) |
% 20.23/19.74 (ALL X20.
% 20.23/19.74 bnd_ndr1_0 -->
% 20.23/19.74 ~ bnd_c6_1 X20 |
% 20.23/19.74 (ALL X21.
% 20.23/19.74 bnd_ndr1_1 X20 -->
% 20.23/19.74 (bnd_c2_2 X20 X21 | ~ bnd_c5_2 X20 X21) | bnd_c6_2 X20 X21)))) &
% 20.23/19.74 ((~ bnd_c10_0 |
% 20.23/19.74 (ALL X22.
% 20.23/19.74 bnd_ndr1_0 -->
% 20.23/19.74 (bnd_c5_1 X22 |
% 20.23/19.74 (ALL X23.
% 20.23/19.74 bnd_ndr1_1 X22 -->
% 20.23/19.74 (bnd_c10_2 X22 X23 | bnd_c7_2 X22 X23) | ~ bnd_c8_2 X22 X23)) |
% 20.23/19.74 bnd_c9_1 X22)) |
% 20.23/19.74 (ALL X24.
% 20.23/19.74 bnd_ndr1_0 -->
% 20.23/19.74 ((ALL X25.
% 20.23/19.74 bnd_ndr1_1 X24 -->
% 20.23/19.74 (~ bnd_c4_2 X24 X25 | bnd_c10_2 X24 X25) | bnd_c3_2 X24 X25) |
% 20.23/19.74 ((bnd_ndr1_1 X24 & bnd_c5_2 X24 bnd_a985) & ~ bnd_c3_2 X24 bnd_a985) &
% 20.23/19.74 bnd_c4_2 X24 bnd_a985) |
% 20.23/19.74 bnd_c10_1 X24))) &
% 20.23/19.74 (bnd_c5_0 | ~ bnd_c8_0)) &
% 20.23/19.74 ((~ bnd_c10_0 |
% 20.23/19.74 (((((bnd_ndr1_0 &
% 20.23/19.74 bnd_ndr1_1 bnd_a986) &
% 20.23/19.74 ~ bnd_c1_2 bnd_a986 bnd_a987) &
% 20.23/19.74 ~ bnd_c9_2 bnd_a986 bnd_a987) &
% 20.23/19.74 bnd_c3_2 bnd_a986 bnd_a987) &
% 20.23/19.74 ~ bnd_c5_1 bnd_a986) &
% 20.23/19.74 ~ bnd_c2_1 bnd_a986) |
% 20.23/19.74 ~ bnd_c5_0)) &
% 20.23/19.74 (((ALL X26.
% 20.23/19.74 bnd_ndr1_0 -->
% 20.23/19.74 (((bnd_ndr1_1 X26 & ~ bnd_c5_2 X26 bnd_a988) & bnd_c10_2 X26 bnd_a988) &
% 20.23/19.74 bnd_c1_2 X26 bnd_a988 |
% 20.23/19.74 ((bnd_ndr1_1 X26 & ~ bnd_c6_2 X26 bnd_a989) & ~ bnd_c8_2 X26 bnd_a989) &
% 20.23/19.74 bnd_c9_2 X26 bnd_a989) |
% 20.23/19.74 ~ bnd_c6_1 X26) |
% 20.23/19.74 bnd_c3_0) |
% 20.23/19.74 bnd_c5_0)) &
% 20.23/19.74 (((ALL X27.
% 20.23/19.74 bnd_ndr1_0 -->
% 20.23/19.74 ((ALL X28.
% 20.23/19.74 bnd_ndr1_1 X27 -->
% 20.23/19.74 (~ bnd_c7_2 X27 X28 | bnd_c3_2 X27 X28) | ~ bnd_c2_2 X27 X28) |
% 20.23/19.74 ~ bnd_c1_1 X27) |
% 20.23/19.74 ((bnd_ndr1_1 X27 & ~ bnd_c8_2 X27 bnd_a990) & ~ bnd_c7_2 X27 bnd_a990) &
% 20.23/19.74 ~ bnd_c10_2 X27 bnd_a990) |
% 20.23/19.74 ~ bnd_c2_0) |
% 20.23/19.74 (ALL X29.
% 20.23/19.74 bnd_ndr1_0 -->
% 20.23/19.74 ((ALL X30.
% 20.23/19.74 bnd_ndr1_1 X29 -->
% 20.23/19.74 (~ bnd_c1_2 X29 X30 | ~ bnd_c8_2 X29 X30) | bnd_c3_2 X29 X30) |
% 20.23/19.74 (ALL X31.
% 20.23/19.74 bnd_ndr1_1 X29 -->
% 20.23/19.74 (bnd_c3_2 X29 X31 | bnd_c7_2 X29 X31) | bnd_c1_2 X29 X31)) |
% 20.23/19.74 ~ bnd_c8_1 X29))) &
% 20.23/19.74 (((ALL X32.
% 20.23/19.74 bnd_ndr1_0 -->
% 20.23/19.74 (~ bnd_c10_1 X32 | ~ bnd_c3_1 X32) |
% 20.23/19.74 (ALL X33.
% 20.23/19.74 bnd_ndr1_1 X32 -->
% 20.23/19.74 (bnd_c6_2 X32 X33 | bnd_c1_2 X32 X33) | bnd_c10_2 X32 X33)) |
% 20.23/19.74 ~ bnd_c4_0) |
% 20.23/19.74 bnd_c9_0)) &
% 20.23/19.74 ((bnd_c3_0 |
% 20.23/19.74 (ALL X34.
% 20.23/19.74 bnd_ndr1_0 -->
% 20.23/19.74 ((ALL X35.
% 20.23/19.74 bnd_ndr1_1 X34 -->
% 20.23/19.74 (~ bnd_c8_2 X34 X35 | ~ bnd_c7_2 X34 X35) | bnd_c2_2 X34 X35) |
% 20.23/19.74 ~ bnd_c9_1 X34) |
% 20.23/19.74 bnd_c3_1 X34)) |
% 20.23/19.75 ~ bnd_c1_0)) &
% 20.23/19.75 ((bnd_c9_0 |
% 20.23/19.75 (ALL X36.
% 20.23/19.75 bnd_ndr1_0 -->
% 20.23/19.75 ((ALL X37.
% 20.23/19.75 bnd_ndr1_1 X36 -->
% 20.23/19.75 (~ bnd_c7_2 X36 X37 | ~ bnd_c6_2 X36 X37) | bnd_c5_2 X36 X37) |
% 20.23/19.75 bnd_c5_1 X36) |
% 20.23/19.75 bnd_c4_1 X36)) |
% 20.23/19.75 (ALL X38.
% 20.23/19.75 bnd_ndr1_0 -->
% 20.23/19.75 (~ bnd_c9_1 X38 | bnd_c2_1 X38) |
% 20.23/19.75 bnd_c6_1 X38))) &
% 20.23/19.75 (~ bnd_c3_0 | bnd_c7_0)) &
% 20.23/19.75 (((ALL X39.
% 20.23/19.75 bnd_ndr1_0 -->
% 20.23/19.75 (~ bnd_c6_1 X39 |
% 20.23/19.75 (ALL X40.
% 20.23/19.75 bnd_ndr1_1 X39 -->
% 20.23/19.75 (~ bnd_c7_2 X39 X40 | ~ bnd_c3_2 X39 X40) | ~ bnd_c5_2 X39 X40)) |
% 20.23/19.75 ~ bnd_c7_1 X39) |
% 20.23/19.75 ~ bnd_c8_0) |
% 20.23/19.75 (ALL X41.
% 20.23/19.75 bnd_ndr1_0 -->
% 20.23/19.75 ((ALL X42.
% 20.23/19.75 bnd_ndr1_1 X41 --> bnd_c10_2 X41 X42 | bnd_c9_2 X41 X42) |
% 20.23/19.75 ~ bnd_c8_1 X41) |
% 20.23/19.75 (ALL X43.
% 20.23/19.75 bnd_ndr1_1 X41 -->
% 20.23/19.75 (bnd_c2_2 X41 X43 |
% 20.23/19.75 ~ bnd_c7_2 X41 X43) |
% 20.23/19.75 bnd_c4_2 X41 X43)))) &
% 20.23/19.75 ((((bnd_ndr1_0 & ~ bnd_c3_1 bnd_a991) &
% 20.23/19.75 ~ bnd_c1_1 bnd_a991) &
% 20.23/19.75 ~ bnd_c7_1 bnd_a991 |
% 20.23/19.75 (((((((bnd_ndr1_0 &
% 20.23/19.75 (ALL X44.
% 20.23/19.75 bnd_ndr1_1 bnd_a992 -->
% 20.23/19.75 (bnd_c9_2 bnd_a992 X44 | bnd_c6_2 bnd_a992 X44) |
% 20.23/19.75 bnd_c4_2 bnd_a992 X44)) &
% 20.23/19.75 bnd_ndr1_1 bnd_a992) &
% 20.23/19.75 bnd_c6_2 bnd_a992 bnd_a993) &
% 20.23/19.75 ~ bnd_c7_2 bnd_a992 bnd_a993) &
% 20.23/19.75 ~ bnd_c9_2 bnd_a992 bnd_a993) &
% 20.23/19.75 bnd_ndr1_1 bnd_a992) &
% 20.23/19.75 bnd_c7_2 bnd_a992 bnd_a994) &
% 20.23/19.75 ~ bnd_c8_2 bnd_a992 bnd_a994) |
% 20.23/19.75 (bnd_ndr1_0 &
% 20.23/19.75 (ALL X45.
% 20.23/19.75 bnd_ndr1_1 bnd_a995 -->
% 20.23/19.75 bnd_c1_2 bnd_a995 X45 |
% 20.23/19.75 ~ bnd_c9_2 bnd_a995 X45)) &
% 20.23/19.75 (ALL X46.
% 20.23/19.75 bnd_ndr1_1 bnd_a995 -->
% 20.23/19.75 (~ bnd_c9_2 bnd_a995 X46 |
% 20.23/19.75 ~ bnd_c7_2 bnd_a995 X46) |
% 20.23/19.75 ~ bnd_c8_2 bnd_a995 X46))) &
% 20.23/19.75 (((ALL X47.
% 20.23/19.75 bnd_ndr1_0 -->
% 20.23/19.75 ((bnd_ndr1_1 X47 & bnd_c6_2 X47 bnd_a996) &
% 20.23/19.75 bnd_c3_2 X47 bnd_a996 |
% 20.23/19.75 (ALL X48.
% 20.23/19.75 bnd_ndr1_1 X47 -->
% 20.23/19.75 (bnd_c6_2 X47 X48 |
% 20.23/19.75 ~ bnd_c1_2 X47 X48) |
% 20.23/19.75 bnd_c7_2 X47 X48)) |
% 20.23/19.75 (ALL X49.
% 20.23/19.75 bnd_ndr1_1 X47 -->
% 20.23/19.75 (bnd_c4_2 X47 X49 | bnd_c1_2 X47 X49) |
% 20.23/19.75 ~ bnd_c9_2 X47 X49)) |
% 20.23/19.75 ~ bnd_c8_0) |
% 20.23/19.75 ~ bnd_c5_0)) &
% 20.23/19.75 (((ALL X50.
% 20.23/19.75 bnd_ndr1_0 -->
% 20.23/19.75 (bnd_c4_1 X50 | ~ bnd_c2_1 X50) |
% 20.23/19.75 ~ bnd_c7_1 X50) |
% 20.23/19.75 (((((bnd_ndr1_0 &
% 20.23/19.75 (ALL X51.
% 20.23/19.75 bnd_ndr1_1 bnd_a997 -->
% 20.23/19.75 (~ bnd_c3_2 bnd_a997 X51 |
% 20.23/19.75 bnd_c4_2 bnd_a997 X51) |
% 20.23/19.75 bnd_c6_2 bnd_a997 X51)) &
% 20.23/19.75 bnd_c5_1 bnd_a997) &
% 20.23/19.75 bnd_ndr1_1 bnd_a997) &
% 20.23/19.75 bnd_c3_2 bnd_a997 bnd_a998) &
% 20.23/19.75 ~ bnd_c5_2 bnd_a997 bnd_a998) &
% 20.23/19.75 bnd_c9_2 bnd_a997 bnd_a998) |
% 20.23/19.75 (ALL X52.
% 20.23/19.75 bnd_ndr1_0 -->
% 20.23/19.75 ((bnd_ndr1_1 X52 & ~ bnd_c2_2 X52 bnd_a999) &
% 20.23/19.75 bnd_c3_2 X52 bnd_a999 |
% 20.23/19.75 ~ bnd_c9_1 X52) |
% 20.23/19.75 (ALL X53.
% 20.23/19.75 bnd_ndr1_1 X52 -->
% 20.23/19.75 (bnd_c6_2 X52 X53 | ~ bnd_c5_2 X52 X53) |
% 20.23/19.75 ~ bnd_c3_2 X52 X53)))) &
% 20.23/19.75 (((ALL X54.
% 20.23/19.75 bnd_ndr1_0 -->
% 20.23/19.75 ((bnd_ndr1_1 X54 & ~ bnd_c6_2 X54 bnd_a1000) &
% 20.23/19.75 ~ bnd_c2_2 X54 bnd_a1000 |
% 20.23/19.75 (ALL X55.
% 20.23/19.75 bnd_ndr1_1 X54 -->
% 20.23/19.75 (bnd_c10_2 X54 X55 |
% 20.23/19.75 ~ bnd_c6_2 X54 X55) |
% 20.23/19.75 ~ bnd_c7_2 X54 X55)) |
% 20.23/19.75 bnd_c4_1 X54) |
% 20.23/19.75 ~ bnd_c10_0) |
% 20.23/19.75 (ALL X56.
% 20.23/19.75 bnd_ndr1_0 -->
% 20.23/19.75 ((ALL X57.
% 20.23/19.75 bnd_ndr1_1 X56 -->
% 20.23/19.75 (bnd_c9_2 X56 X57 | bnd_c10_2 X56 X57) |
% 20.23/19.75 ~ bnd_c6_2 X56 X57) |
% 20.23/19.75 ((bnd_ndr1_1 X56 & bnd_c8_2 X56 bnd_a1001) &
% 20.23/19.75 bnd_c4_2 X56 bnd_a1001) &
% 20.23/19.75 bnd_c10_2 X56 bnd_a1001) |
% 20.23/19.75 ~ bnd_c8_1 X56))) &
% 20.23/19.75 ((bnd_c3_0 |
% 20.23/19.75 (ALL X58.
% 20.23/19.75 bnd_ndr1_0 -->
% 20.23/19.75 (((bnd_ndr1_1 X58 & bnd_c1_2 X58 bnd_a1002) &
% 20.23/19.75 ~ bnd_c5_2 X58 bnd_a1002) &
% 20.23/19.75 bnd_c7_2 X58 bnd_a1002 |
% 20.23/19.75 ~ bnd_c2_1 X58) |
% 20.23/19.75 ~ bnd_c6_1 X58)) |
% 20.23/19.75 (ALL X59.
% 20.23/19.75 bnd_ndr1_0 -->
% 20.23/19.75 ~ bnd_c1_1 X59 | bnd_c3_1 X59))) &
% 20.23/19.75 ((((((bnd_ndr1_0 & bnd_c2_1 bnd_a1003) &
% 20.23/19.75 bnd_ndr1_1 bnd_a1003) &
% 20.23/19.75 ~ bnd_c6_2 bnd_a1003 bnd_a1004) &
% 20.23/19.75 bnd_c1_2 bnd_a1003 bnd_a1004) &
% 20.23/19.75 ~ bnd_c1_1 bnd_a1003 |
% 20.23/19.75 ((((bnd_ndr1_0 & ~ bnd_c1_1 bnd_a1005) &
% 20.23/19.75 bnd_c6_1 bnd_a1005) &
% 20.23/19.75 bnd_ndr1_1 bnd_a1005) &
% 20.23/19.75 bnd_c2_2 bnd_a1005 bnd_a1006) &
% 20.23/19.75 bnd_c5_2 bnd_a1005 bnd_a1006) |
% 20.23/19.75 bnd_ndr1_0 & bnd_c10_1 bnd_a1007)) &
% 20.23/19.75 ((~ bnd_c3_0 | bnd_c4_0) | ~ bnd_c8_0)) &
% 20.23/19.75 ((~ bnd_c7_0 |
% 20.23/19.75 (((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a1008) &
% 20.23/19.75 bnd_c3_2 bnd_a1008 bnd_a1009) &
% 20.23/19.75 bnd_c8_2 bnd_a1008 bnd_a1009) &
% 20.23/19.75 bnd_ndr1_1 bnd_a1008) &
% 20.23/19.75 ~ bnd_c1_2 bnd_a1008 bnd_a1010) &
% 20.23/19.75 ~ bnd_c6_2 bnd_a1008 bnd_a1010) &
% 20.23/19.75 ~ bnd_c2_2 bnd_a1008 bnd_a1010) &
% 20.23/19.75 (ALL X60.
% 20.23/19.75 bnd_ndr1_1 bnd_a1008 -->
% 20.23/19.75 (bnd_c7_2 bnd_a1008 X60 |
% 20.23/19.75 ~ bnd_c4_2 bnd_a1008 X60) |
% 20.23/19.75 bnd_c10_2 bnd_a1008 X60)) |
% 20.23/19.75 ~ bnd_c1_0)) &
% 20.23/19.75 ((bnd_c2_0 | bnd_c7_0) | bnd_c8_0)) &
% 20.23/19.75 (((ALL X61.
% 20.23/19.75 bnd_ndr1_0 -->
% 20.23/19.75 ((ALL X62.
% 20.23/19.75 bnd_ndr1_1 X61 -->
% 20.23/19.75 (bnd_c9_2 X61 X62 | bnd_c1_2 X61 X62) |
% 20.23/19.75 bnd_c4_2 X61 X62) |
% 20.23/19.75 (ALL X63.
% 20.23/19.75 bnd_ndr1_1 X61 -->
% 20.23/19.75 (bnd_c6_2 X61 X63 | ~ bnd_c8_2 X61 X63) |
% 20.23/19.75 bnd_c2_2 X61 X63)) |
% 20.23/19.75 ~ bnd_c5_1 X61) |
% 20.23/19.75 bnd_c1_0) |
% 20.23/19.75 ~ bnd_c5_0)) &
% 20.23/19.75 (((ALL X64.
% 20.23/19.75 bnd_ndr1_0 -->
% 20.23/19.75 (~ bnd_c5_1 X64 |
% 20.23/19.75 (ALL X65.
% 20.23/19.75 bnd_ndr1_1 X64 -->
% 20.23/19.75 (~ bnd_c4_2 X64 X65 | bnd_c9_2 X64 X65) |
% 20.23/19.75 bnd_c6_2 X64 X65)) |
% 20.23/19.75 ~ bnd_c2_1 X64) |
% 20.23/19.75 (ALL X66.
% 20.23/19.75 bnd_ndr1_0 -->
% 20.23/19.75 ((ALL X67.
% 20.23/19.75 bnd_ndr1_1 X66 -->
% 20.23/19.75 (bnd_c8_2 X66 X67 | bnd_c1_2 X66 X67) |
% 20.23/19.75 bnd_c4_2 X66 X67) |
% 20.23/19.75 ~ bnd_c5_1 X66) |
% 20.23/19.75 ~ bnd_c3_1 X66)) |
% 20.23/19.75 bnd_c10_0)) &
% 20.23/19.75 (((ALL X68.
% 20.23/19.75 bnd_ndr1_0 -->
% 20.23/19.75 (((bnd_ndr1_1 X68 & ~ bnd_c1_2 X68 bnd_a1011) &
% 20.23/19.75 bnd_c3_2 X68 bnd_a1011) &
% 20.23/19.75 ~ bnd_c7_2 X68 bnd_a1011 |
% 20.23/19.75 ((bnd_ndr1_1 X68 & bnd_c6_2 X68 bnd_a1012) &
% 20.23/19.75 bnd_c7_2 X68 bnd_a1012) &
% 20.23/19.75 ~ bnd_c2_2 X68 bnd_a1012) |
% 20.23/19.75 bnd_c4_1 X68) |
% 20.23/19.75 ((((bnd_ndr1_0 & ~ bnd_c5_1 bnd_a1013) &
% 20.23/19.75 bnd_c6_1 bnd_a1013) &
% 20.23/19.75 bnd_ndr1_1 bnd_a1013) &
% 20.23/19.75 bnd_c8_2 bnd_a1013 bnd_a1014) &
% 20.23/19.75 ~ bnd_c1_2 bnd_a1013 bnd_a1014) |
% 20.23/19.75 ((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a1015) &
% 20.23/19.75 bnd_c3_2 bnd_a1015 bnd_a1016) &
% 20.23/19.75 ~ bnd_c7_2 bnd_a1015 bnd_a1016) &
% 20.23/19.75 bnd_ndr1_1 bnd_a1015) &
% 20.23/19.75 bnd_c9_2 bnd_a1015 bnd_a1017) &
% 20.23/19.75 bnd_c3_2 bnd_a1015 bnd_a1017) &
% 20.23/19.75 ~ bnd_c1_2 bnd_a1015 bnd_a1017)) &
% 20.23/19.75 (((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a1018) &
% 20.23/19.75 ~ bnd_c7_2 bnd_a1018 bnd_a1019) &
% 20.23/19.75 ~ bnd_c3_2 bnd_a1018 bnd_a1019) &
% 20.23/19.75 ~ bnd_c10_2 bnd_a1018 bnd_a1019) &
% 20.23/19.75 ~ bnd_c10_1 bnd_a1018) &
% 20.23/19.75 bnd_c3_1 bnd_a1018 |
% 20.23/19.75 ~ bnd_c7_0) |
% 20.23/19.75 ((bnd_ndr1_0 & bnd_c3_1 bnd_a1020) &
% 20.23/19.75 (ALL X69.
% 20.23/19.75 bnd_ndr1_1 bnd_a1020 -->
% 20.23/19.75 ~ bnd_c2_2 bnd_a1020 X69 | ~ bnd_c1_2 bnd_a1020 X69)) &
% 20.23/19.75 bnd_c9_1 bnd_a1020)) &
% 20.23/19.75 ((~ bnd_c7_0 | ~ bnd_c9_0) |
% 20.23/19.75 (ALL X70.
% 20.23/19.75 bnd_ndr1_0 -->
% 20.23/19.75 (bnd_c8_1 X70 |
% 20.23/19.75 ((bnd_ndr1_1 X70 & ~ bnd_c9_2 X70 bnd_a1021) &
% 20.23/19.75 ~ bnd_c1_2 X70 bnd_a1021) &
% 20.23/19.75 bnd_c5_2 X70 bnd_a1021) |
% 20.23/19.75 ~ bnd_c10_1 X70))) &
% 20.23/19.75 ((~ bnd_c8_0 | ~ bnd_c5_0) | bnd_c3_0)) &
% 20.23/19.75 (((((((bnd_ndr1_0 & ~ bnd_c9_1 bnd_a1022) &
% 20.23/19.75 (ALL X71.
% 20.23/19.75 bnd_ndr1_1 bnd_a1022 -->
% 20.23/19.75 (bnd_c10_2 bnd_a1022 X71 | ~ bnd_c2_2 bnd_a1022 X71) |
% 20.23/19.75 bnd_c8_2 bnd_a1022 X71)) &
% 20.23/19.75 bnd_ndr1_1 bnd_a1022) &
% 20.23/19.75 ~ bnd_c3_2 bnd_a1022 bnd_a1023) &
% 20.23/19.75 ~ bnd_c8_2 bnd_a1022 bnd_a1023) &
% 20.23/19.75 ~ bnd_c4_2 bnd_a1022 bnd_a1023 |
% 20.23/19.75 bnd_c2_0) |
% 20.23/19.75 ((bnd_ndr1_0 & ~ bnd_c8_1 bnd_a1024) & ~ bnd_c4_1 bnd_a1024) &
% 20.23/19.75 (ALL X72.
% 20.23/19.75 bnd_ndr1_1 bnd_a1024 -->
% 20.23/19.75 (bnd_c3_2 bnd_a1024 X72 | ~ bnd_c7_2 bnd_a1024 X72) |
% 20.23/19.75 bnd_c4_2 bnd_a1024 X72))) &
% 20.23/19.75 ((bnd_c3_0 | bnd_c8_0) | bnd_c1_0)) &
% 20.23/19.75 ((ALL X73.
% 20.23/19.75 bnd_ndr1_0 -->
% 20.23/19.75 (bnd_c2_1 X73 | ~ bnd_c5_1 X73) |
% 20.23/19.75 ((bnd_ndr1_1 X73 & bnd_c4_2 X73 bnd_a1025) &
% 20.23/19.75 bnd_c9_2 X73 bnd_a1025) &
% 20.23/19.75 ~ bnd_c5_2 X73 bnd_a1025) |
% 20.23/19.75 ~ bnd_c10_0)) &
% 20.23/19.75 ((bnd_c10_0 |
% 20.23/19.75 (((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a1026) &
% 20.23/19.75 ~ bnd_c5_2 bnd_a1026 bnd_a1027) &
% 20.23/19.75 ~ bnd_c4_2 bnd_a1026 bnd_a1027) &
% 20.23/19.75 ~ bnd_c3_2 bnd_a1026 bnd_a1027) &
% 20.23/19.75 (ALL X74.
% 20.23/19.75 bnd_ndr1_1 bnd_a1026 -->
% 20.23/19.75 (~ bnd_c6_2 bnd_a1026 X74 | bnd_c3_2 bnd_a1026 X74) |
% 20.23/19.75 bnd_c5_2 bnd_a1026 X74)) &
% 20.23/19.75 bnd_c5_1 bnd_a1026) |
% 20.23/19.75 (ALL X75.
% 20.23/19.75 bnd_ndr1_0 -->
% 20.23/19.75 (bnd_c5_1 X75 | bnd_c8_1 X75) |
% 20.23/19.75 (ALL X76.
% 20.23/19.75 bnd_ndr1_1 X75 -->
% 20.23/19.75 (bnd_c10_2 X75 X76 | ~ bnd_c4_2 X75 X76) |
% 20.23/19.75 bnd_c6_2 X75 X76)))) &
% 20.23/19.75 ((bnd_c6_0 |
% 20.23/19.75 ((((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a1028) &
% 20.23/19.75 ~ bnd_c9_2 bnd_a1028 bnd_a1029) &
% 20.23/19.75 ~ bnd_c8_2 bnd_a1028 bnd_a1029) &
% 20.23/19.75 ~ bnd_c4_2 bnd_a1028 bnd_a1029) &
% 20.23/19.75 (ALL X77.
% 20.23/19.75 bnd_ndr1_1 bnd_a1028 -->
% 20.23/19.75 (bnd_c9_2 bnd_a1028 X77 | ~ bnd_c3_2 bnd_a1028 X77) |
% 20.23/19.75 bnd_c5_2 bnd_a1028 X77)) &
% 20.23/19.75 bnd_ndr1_1 bnd_a1028) &
% 20.23/19.75 ~ bnd_c9_2 bnd_a1028 bnd_a1030) &
% 20.23/19.75 bnd_c4_2 bnd_a1028 bnd_a1030) &
% 20.23/19.75 ~ bnd_c8_2 bnd_a1028 bnd_a1030) |
% 20.23/19.75 ((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a1031) &
% 20.23/19.75 bnd_c6_2 bnd_a1031 bnd_a1032) &
% 20.23/19.75 ~ bnd_c8_2 bnd_a1031 bnd_a1032) &
% 20.23/19.75 ~ bnd_c7_2 bnd_a1031 bnd_a1032) &
% 20.23/19.75 (ALL X78.
% 20.23/19.75 bnd_ndr1_1 bnd_a1031 -->
% 20.23/19.75 (~ bnd_c6_2 bnd_a1031 X78 | ~ bnd_c2_2 bnd_a1031 X78) |
% 20.23/19.75 bnd_c4_2 bnd_a1031 X78))) &
% 20.23/19.75 ((bnd_c9_0 |
% 20.23/19.75 (((((bnd_ndr1_0 &
% 20.23/19.75 (ALL X79.
% 20.23/19.75 bnd_ndr1_1 bnd_a1033 -->
% 20.23/19.75 (~ bnd_c4_2 bnd_a1033 X79 | bnd_c7_2 bnd_a1033 X79) |
% 20.23/19.75 bnd_c2_2 bnd_a1033 X79)) &
% 20.23/19.75 ~ bnd_c7_1 bnd_a1033) &
% 20.23/19.75 bnd_ndr1_1 bnd_a1033) &
% 20.23/19.75 bnd_c10_2 bnd_a1033 bnd_a1034) &
% 20.23/19.75 bnd_c5_2 bnd_a1033 bnd_a1034) &
% 20.23/19.75 bnd_c8_2 bnd_a1033 bnd_a1034) |
% 20.23/19.75 bnd_c4_0)) &
% 20.23/19.75 (((((((((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a1035) &
% 20.23/19.75 bnd_c2_2 bnd_a1035 bnd_a1036) &
% 20.23/19.75 bnd_c8_2 bnd_a1035 bnd_a1036) &
% 20.23/19.75 ~ bnd_c9_2 bnd_a1035 bnd_a1036) &
% 20.23/19.75 bnd_ndr1_1 bnd_a1035) &
% 20.23/19.75 bnd_c3_2 bnd_a1035 bnd_a1037) &
% 20.23/19.75 bnd_c4_2 bnd_a1035 bnd_a1037) &
% 20.23/19.75 ~ bnd_c7_2 bnd_a1035 bnd_a1037) &
% 20.23/19.75 bnd_ndr1_1 bnd_a1035) &
% 20.23/19.75 ~ bnd_c9_2 bnd_a1035 bnd_a1038) &
% 20.23/19.75 ~ bnd_c1_2 bnd_a1035 bnd_a1038) &
% 20.23/19.75 ~ bnd_c10_2 bnd_a1035 bnd_a1038 |
% 20.23/19.75 bnd_c8_0) |
% 20.23/19.75 (ALL X80.
% 20.23/19.75 bnd_ndr1_0 -->
% 20.23/19.75 ((ALL X81.
% 20.23/19.75 bnd_ndr1_1 X80 -->
% 20.23/19.75 (~ bnd_c5_2 X80 X81 | bnd_c4_2 X80 X81) |
% 20.23/19.75 ~ bnd_c8_2 X80 X81) |
% 20.23/19.75 ((bnd_ndr1_1 X80 & ~ bnd_c5_2 X80 bnd_a1039) &
% 20.23/19.75 ~ bnd_c8_2 X80 bnd_a1039) &
% 20.23/19.75 bnd_c6_2 X80 bnd_a1039) |
% 20.23/19.75 bnd_c1_1 X80))) &
% 20.23/19.75 (bnd_c10_0 | ~ bnd_c8_0)) &
% 20.23/19.75 (((bnd_ndr1_0 &
% 20.23/19.75 (ALL X82.
% 20.23/19.75 bnd_ndr1_1 bnd_a1040 -->
% 20.23/19.75 (~ bnd_c7_2 bnd_a1040 X82 | bnd_c4_2 bnd_a1040 X82) |
% 20.23/19.75 bnd_c8_2 bnd_a1040 X82)) &
% 20.23/19.75 bnd_c3_1 bnd_a1040 |
% 20.23/19.75 (ALL X83.
% 20.23/19.75 bnd_ndr1_0 -->
% 20.23/19.75 (~ bnd_c1_1 X83 | ~ bnd_c7_1 X83) | bnd_c10_1 X83)) |
% 20.23/19.75 (bnd_ndr1_0 &
% 20.23/19.75 (ALL X84.
% 20.23/19.75 bnd_ndr1_1 bnd_a1041 -->
% 20.23/19.75 (~ bnd_c8_2 bnd_a1041 X84 | ~ bnd_c1_2 bnd_a1041 X84) |
% 20.23/19.75 bnd_c5_2 bnd_a1041 X84)) &
% 20.23/19.75 ~ bnd_c3_1 bnd_a1041)) &
% 20.23/19.75 ((((bnd_ndr1_0 &
% 20.23/19.75 (ALL X85.
% 20.23/19.75 bnd_ndr1_1 bnd_a1042 -->
% 20.23/19.75 (~ bnd_c7_2 bnd_a1042 X85 | ~ bnd_c10_2 bnd_a1042 X85) |
% 20.23/19.75 bnd_c3_2 bnd_a1042 X85)) &
% 20.23/19.75 (ALL X86.
% 20.23/19.75 bnd_ndr1_1 bnd_a1042 -->
% 20.23/19.75 (bnd_c4_2 bnd_a1042 X86 | ~ bnd_c3_2 bnd_a1042 X86) |
% 20.23/19.75 bnd_c6_2 bnd_a1042 X86)) &
% 20.23/19.75 ~ bnd_c9_1 bnd_a1042 |
% 20.23/19.75 bnd_c7_0) |
% 20.23/19.75 ~ bnd_c1_0)) &
% 20.23/19.75 (((ALL X87.
% 20.23/19.75 bnd_ndr1_0 -->
% 20.23/19.75 (bnd_c2_1 X87 |
% 20.23/19.75 (ALL X88.
% 20.23/19.75 bnd_ndr1_1 X87 --> bnd_c5_2 X87 X88 | ~ bnd_c4_2 X87 X88)) |
% 20.23/19.75 bnd_c5_1 X87) |
% 20.23/19.75 ~ bnd_c6_0) |
% 20.23/19.75 (((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a1043) & bnd_c4_2 bnd_a1043 bnd_a1044) &
% 20.23/19.75 ~ bnd_c6_2 bnd_a1043 bnd_a1044) &
% 20.23/19.75 ~ bnd_c1_2 bnd_a1043 bnd_a1044) &
% 20.23/19.75 bnd_c8_1 bnd_a1043) &
% 20.23/19.75 bnd_c5_1 bnd_a1043)) &
% 20.23/19.75 (((ALL X89.
% 20.23/19.75 bnd_ndr1_0 -->
% 20.23/19.75 ((ALL X90.
% 20.23/19.75 bnd_ndr1_1 X89 --> ~ bnd_c8_2 X89 X90 | ~ bnd_c2_2 X89 X90) |
% 20.23/19.75 bnd_c10_1 X89) |
% 20.23/19.75 ((bnd_ndr1_1 X89 & bnd_c8_2 X89 bnd_a1045) &
% 20.23/19.75 bnd_c4_2 X89 bnd_a1045) &
% 20.23/19.75 ~ bnd_c2_2 X89 bnd_a1045) |
% 20.23/19.75 bnd_c8_0) |
% 20.23/19.75 (bnd_ndr1_0 &
% 20.23/19.75 (ALL X91.
% 20.23/19.75 bnd_ndr1_1 bnd_a1046 -->
% 20.23/19.75 (~ bnd_c3_2 bnd_a1046 X91 | ~ bnd_c8_2 bnd_a1046 X91) |
% 20.23/19.75 bnd_c10_2 bnd_a1046 X91)) &
% 20.23/19.75 ~ bnd_c9_1 bnd_a1046)) &
% 20.23/19.75 (((((((bnd_ndr1_0 & bnd_c7_1 bnd_a1047) & ~ bnd_c1_1 bnd_a1047) &
% 20.23/19.75 bnd_ndr1_1 bnd_a1047) &
% 20.23/19.75 bnd_c6_2 bnd_a1047 bnd_a1048) &
% 20.23/19.75 ~ bnd_c3_2 bnd_a1047 bnd_a1048) &
% 20.23/19.75 bnd_c9_2 bnd_a1047 bnd_a1048 |
% 20.23/19.75 (ALL X92.
% 20.23/19.75 bnd_ndr1_0 -->
% 20.23/19.75 ((ALL X93.
% 20.23/19.75 bnd_ndr1_1 X92 -->
% 20.23/19.75 (~ bnd_c7_2 X92 X93 | bnd_c4_2 X92 X93) | bnd_c3_2 X92 X93) |
% 20.23/19.75 ((bnd_ndr1_1 X92 & ~ bnd_c10_2 X92 bnd_a1049) &
% 20.23/19.75 ~ bnd_c9_2 X92 bnd_a1049) &
% 20.23/19.75 bnd_c8_2 X92 bnd_a1049) |
% 20.23/19.75 bnd_c8_1 X92)) |
% 20.23/19.75 ((bnd_ndr1_0 &
% 20.23/19.75 (ALL X94.
% 20.23/19.75 bnd_ndr1_1 bnd_a1050 -->
% 20.23/19.75 (~ bnd_c8_2 bnd_a1050 X94 | bnd_c10_2 bnd_a1050 X94) |
% 20.23/19.75 ~ bnd_c4_2 bnd_a1050 X94)) &
% 20.23/19.75 (ALL X95.
% 20.23/19.75 bnd_ndr1_1 bnd_a1050 -->
% 20.23/19.75 (bnd_c4_2 bnd_a1050 X95 | ~ bnd_c9_2 bnd_a1050 X95) |
% 20.23/19.75 bnd_c8_2 bnd_a1050 X95)) &
% 20.23/19.75 bnd_c5_1 bnd_a1050)) &
% 20.23/19.75 ((~ bnd_c8_0 |
% 20.23/19.75 (((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a1051) & ~ bnd_c8_2 bnd_a1051 bnd_a1052) &
% 20.23/19.75 ~ bnd_c2_2 bnd_a1051 bnd_a1052) &
% 20.23/19.75 ~ bnd_c9_2 bnd_a1051 bnd_a1052) &
% 20.23/19.75 ~ bnd_c4_1 bnd_a1051) &
% 20.23/19.75 bnd_c7_1 bnd_a1051) |
% 20.23/19.75 bnd_c10_0)) &
% 20.23/19.75 (((((((bnd_ndr1_0 &
% 20.23/19.75 (ALL X96.
% 20.23/19.75 bnd_ndr1_1 bnd_a1053 -->
% 20.23/19.75 (bnd_c8_2 bnd_a1053 X96 | bnd_c2_2 bnd_a1053 X96) |
% 20.23/19.75 ~ bnd_c3_2 bnd_a1053 X96)) &
% 20.23/19.75 bnd_c1_1 bnd_a1053) &
% 20.23/19.75 bnd_ndr1_1 bnd_a1053) &
% 20.23/19.75 bnd_c10_2 bnd_a1053 bnd_a1054) &
% 20.23/19.75 bnd_c3_2 bnd_a1053 bnd_a1054) &
% 20.23/19.75 ~ bnd_c2_2 bnd_a1053 bnd_a1054 |
% 20.23/19.75 bnd_c7_0) |
% 20.23/19.75 (ALL X97.
% 20.23/19.75 bnd_ndr1_0 -->
% 20.23/19.75 (bnd_c5_1 X97 | bnd_c1_1 X97) |
% 20.23/19.75 (ALL X98.
% 20.23/19.75 bnd_ndr1_1 X97 --> ~ bnd_c1_2 X97 X98 | ~ bnd_c3_2 X97 X98)))) &
% 20.23/19.75 ((bnd_c6_0 | ~ bnd_c8_0) |
% 20.23/19.75 ((((((((bnd_ndr1_0 &
% 20.23/19.75 (ALL X99.
% 20.23/19.75 bnd_ndr1_1 bnd_a1055 -->
% 20.23/19.75 (~ bnd_c4_2 bnd_a1055 X99 | ~ bnd_c6_2 bnd_a1055 X99) |
% 20.23/19.75 ~ bnd_c8_2 bnd_a1055 X99)) &
% 20.23/19.75 bnd_ndr1_1 bnd_a1055) &
% 20.23/19.75 bnd_c4_2 bnd_a1055 bnd_a1056) &
% 20.23/19.75 bnd_c10_2 bnd_a1055 bnd_a1056) &
% 20.23/19.75 bnd_c5_2 bnd_a1055 bnd_a1056) &
% 20.23/19.75 bnd_ndr1_1 bnd_a1055) &
% 20.23/19.75 ~ bnd_c2_2 bnd_a1055 bnd_a1057) &
% 20.23/19.75 bnd_c3_2 bnd_a1055 bnd_a1057) &
% 20.23/19.75 ~ bnd_c9_2 bnd_a1055 bnd_a1057)) &
% 20.23/19.75 ((((bnd_ndr1_0 & ~ bnd_c1_1 bnd_a1058) &
% 20.23/19.75 ~ bnd_c10_1 bnd_a1058) &
% 20.23/19.75 ~ bnd_c5_1 bnd_a1058 |
% 20.23/19.75 (((((bnd_ndr1_0 &
% 20.23/19.75 (ALL X100.
% 20.23/19.75 bnd_ndr1_1 bnd_a1059 -->
% 20.23/19.75 (~ bnd_c2_2 bnd_a1059 X100 | bnd_c1_2 bnd_a1059 X100) |
% 20.23/19.75 bnd_c8_2 bnd_a1059 X100)) &
% 20.23/19.75 bnd_ndr1_1 bnd_a1059) &
% 20.23/19.75 bnd_c4_2 bnd_a1059 bnd_a1060) &
% 20.23/19.75 ~ bnd_c9_2 bnd_a1059 bnd_a1060) &
% 20.23/19.75 ~ bnd_c5_2 bnd_a1059 bnd_a1060) &
% 20.23/19.75 ~ bnd_c9_1 bnd_a1059) |
% 20.23/19.75 ((bnd_ndr1_0 & bnd_c1_1 bnd_a1061) &
% 20.23/19.75 ~ bnd_c9_1 bnd_a1061) &
% 20.23/19.75 bnd_c8_1 bnd_a1061)) &
% 20.23/19.75 ((~ bnd_c4_0 |
% 20.23/19.75 (bnd_ndr1_0 & bnd_c10_1 bnd_a1062) &
% 20.23/19.75 ~ bnd_c5_1 bnd_a1062) |
% 20.23/19.75 (ALL X101.
% 20.23/19.75 bnd_ndr1_0 -->
% 20.23/19.75 (ALL X102.
% 20.23/19.75 bnd_ndr1_1 X101 -->
% 20.23/19.75 (bnd_c1_2 X101 X102 | bnd_c6_2 X101 X102) | bnd_c9_2 X101 X102) |
% 20.23/19.75 ((bnd_ndr1_1 X101 & bnd_c6_2 X101 bnd_a1063) & ~ bnd_c9_2 X101 bnd_a1063) &
% 20.23/19.75 ~ bnd_c5_2 X101 bnd_a1063))) &
% 20.23/19.75 (((((((bnd_ndr1_0 &
% 20.23/19.75 (ALL X103.
% 20.23/19.75 bnd_ndr1_1 bnd_a1064 -->
% 20.23/19.75 (bnd_c1_2 bnd_a1064 X103 | bnd_c8_2 bnd_a1064 X103) |
% 20.23/19.75 bnd_c3_2 bnd_a1064 X103)) &
% 20.23/19.75 bnd_ndr1_1 bnd_a1064) &
% 20.23/19.75 bnd_c8_2 bnd_a1064 bnd_a1065) &
% 20.23/19.75 ~ bnd_c1_2 bnd_a1064 bnd_a1065) &
% 20.23/19.75 ~ bnd_c2_2 bnd_a1064 bnd_a1065) &
% 20.23/19.75 (ALL X104.
% 20.23/19.75 bnd_ndr1_1 bnd_a1064 -->
% 20.23/19.75 (bnd_c10_2 bnd_a1064 X104 | ~ bnd_c6_2 bnd_a1064 X104) |
% 20.23/19.75 ~ bnd_c7_2 bnd_a1064 X104) |
% 20.23/19.75 (ALL X105.
% 20.23/19.75 bnd_ndr1_0 -->
% 20.23/19.75 (bnd_c7_1 X105 |
% 20.23/19.75 (ALL X106.
% 20.23/19.75 bnd_ndr1_1 X105 -->
% 20.23/19.75 (bnd_c10_2 X105 X106 | ~ bnd_c6_2 X105 X106) | ~ bnd_c8_2 X105 X106)) |
% 20.23/19.75 ~ bnd_c9_1 X105)) |
% 20.23/19.75 ~ bnd_c10_0)) &
% 20.23/19.75 ((~ bnd_c4_0 | bnd_c3_0) | ~ bnd_c5_0)) &
% 20.23/19.75 (((((((bnd_ndr1_0 & bnd_c7_1 bnd_a1066) &
% 20.23/19.75 ~ bnd_c8_1 bnd_a1066) &
% 20.23/19.75 bnd_ndr1_1 bnd_a1066) &
% 20.23/19.75 bnd_c6_2 bnd_a1066 bnd_a1067) &
% 20.23/19.75 bnd_c1_2 bnd_a1066 bnd_a1067) &
% 20.23/19.75 ~ bnd_c4_2 bnd_a1066 bnd_a1067 |
% 20.23/19.75 (((((((bnd_ndr1_0 & ~ bnd_c3_1 bnd_a1068) &
% 20.23/19.75 bnd_ndr1_1 bnd_a1068) &
% 20.23/19.75 ~ bnd_c2_2 bnd_a1068 bnd_a1069) &
% 20.23/19.75 ~ bnd_c5_2 bnd_a1068 bnd_a1069) &
% 20.23/19.75 bnd_ndr1_1 bnd_a1068) &
% 20.23/19.75 bnd_c8_2 bnd_a1068 bnd_a1070) &
% 20.23/19.75 ~ bnd_c2_2 bnd_a1068 bnd_a1070) &
% 20.23/19.75 bnd_c1_2 bnd_a1068 bnd_a1070) |
% 20.23/19.75 ~ bnd_c6_0)) &
% 20.23/19.75 (((ALL X107.
% 20.23/19.75 bnd_ndr1_0 -->
% 20.23/19.75 (~ bnd_c1_1 X107 |
% 20.23/19.75 (ALL X108.
% 20.23/19.75 bnd_ndr1_1 X107 -->
% 20.23/19.75 (~ bnd_c3_2 X107 X108 | ~ bnd_c5_2 X107 X108) | bnd_c7_2 X107 X108)) |
% 20.23/19.75 ((bnd_ndr1_1 X107 &
% 20.23/19.75 ~ bnd_c6_2 X107 bnd_a1071) &
% 20.23/19.75 bnd_c9_2 X107 bnd_a1071) &
% 20.23/19.75 ~ bnd_c7_2 X107 bnd_a1071) |
% 20.23/19.75 bnd_c1_0) |
% 20.23/19.75 ((bnd_ndr1_0 & bnd_c9_1 bnd_a1072) &
% 20.23/19.75 ~ bnd_c5_1 bnd_a1072) &
% 20.23/19.75 bnd_c2_1 bnd_a1072)) &
% 20.23/19.75 (((ALL X109.
% 20.23/19.75 bnd_ndr1_0 -->
% 20.23/19.75 (~ bnd_c4_1 X109 |
% 20.23/19.75 (ALL X110.
% 20.23/19.75 bnd_ndr1_1 X109 -->
% 20.23/19.75 (bnd_c9_2 X109 X110 | bnd_c10_2 X109 X110) | ~ bnd_c1_2 X109 X110)) |
% 20.23/19.75 (bnd_ndr1_1 X109 &
% 20.23/19.75 bnd_c3_2 X109 bnd_a1073) &
% 20.23/19.75 bnd_c10_2 X109 bnd_a1073) |
% 20.23/19.75 bnd_c3_0) |
% 20.23/19.75 (ALL X111.
% 20.23/19.75 bnd_ndr1_0 -->
% 20.23/19.75 (bnd_c10_1 X111 |
% 20.23/19.75 (ALL X112.
% 20.23/19.75 bnd_ndr1_1 X111 -->
% 20.23/19.75 (~ bnd_c1_2 X111 X112 | ~ bnd_c5_2 X111 X112) | bnd_c2_2 X111 X112)) |
% 20.23/19.75 bnd_c3_1 X111))) &
% 20.23/19.75 ((bnd_c4_0 |
% 20.23/19.75 (((((bnd_ndr1_0 & bnd_c7_1 bnd_a1074) &
% 20.23/19.75 (ALL X113.
% 20.23/19.75 bnd_ndr1_1 bnd_a1074 -->
% 20.23/19.75 bnd_c5_2 bnd_a1074 X113 |
% 20.23/19.75 bnd_c8_2 bnd_a1074 X113)) &
% 20.23/19.75 bnd_ndr1_1 bnd_a1074) &
% 20.23/19.75 ~ bnd_c4_2 bnd_a1074 bnd_a1075) &
% 20.23/19.75 ~ bnd_c3_2 bnd_a1074 bnd_a1075) &
% 20.23/19.75 ~ bnd_c6_2 bnd_a1074 bnd_a1075) |
% 20.23/19.75 bnd_c7_0)) &
% 20.23/19.75 ((ALL X114.
% 20.23/19.75 bnd_ndr1_0 -->
% 20.23/19.75 (~ bnd_c2_1 X114 |
% 20.23/19.75 ((bnd_ndr1_1 X114 &
% 20.23/19.75 ~ bnd_c9_2 X114 bnd_a1076) &
% 20.23/19.75 ~ bnd_c6_2 X114 bnd_a1076) &
% 20.23/19.75 bnd_c8_2 X114 bnd_a1076) |
% 20.23/19.75 ((bnd_ndr1_1 X114 &
% 20.23/19.75 ~ bnd_c6_2 X114 bnd_a1077) &
% 20.23/19.75 bnd_c4_2 X114 bnd_a1077) &
% 20.23/19.75 ~ bnd_c5_2 X114 bnd_a1077) |
% 20.23/19.75 ((bnd_ndr1_0 & ~ bnd_c10_1 bnd_a1078) &
% 20.23/19.75 (ALL X115.
% 20.23/19.75 bnd_ndr1_1 bnd_a1078 -->
% 20.23/19.75 (bnd_c1_2 bnd_a1078 X115 |
% 20.23/19.75 bnd_c10_2 bnd_a1078 X115) |
% 20.23/19.75 ~ bnd_c6_2 bnd_a1078 X115)) &
% 20.23/19.75 (ALL X116.
% 20.23/19.75 bnd_ndr1_1 bnd_a1078 -->
% 20.23/19.75 (~ bnd_c6_2 bnd_a1078 X116 |
% 20.23/19.75 ~ bnd_c10_2 bnd_a1078 X116) |
% 20.23/19.75 bnd_c2_2 bnd_a1078 X116))) &
% 20.23/19.75 ((bnd_c5_0 |
% 20.23/19.75 (ALL X117.
% 20.23/19.75 bnd_ndr1_0 -->
% 20.23/19.75 ((ALL X118.
% 20.23/19.75 bnd_ndr1_1 X117 -->
% 20.23/19.75 (bnd_c10_2 X117 X118 |
% 20.23/19.75 ~ bnd_c6_2 X117 X118) |
% 20.23/19.75 bnd_c3_2 X117 X118) |
% 20.23/19.75 bnd_c4_1 X117) |
% 20.23/19.75 bnd_c7_1 X117)) |
% 20.23/19.75 ~ bnd_c3_0)) &
% 20.23/19.75 (((ALL X119.
% 20.23/19.75 bnd_ndr1_0 -->
% 20.23/19.75 ((ALL X120.
% 20.23/19.75 bnd_ndr1_1 X119 -->
% 20.23/19.75 (bnd_c9_2 X119 X120 |
% 20.23/19.75 bnd_c5_2 X119 X120) |
% 20.23/19.75 ~ bnd_c8_2 X119 X120) |
% 20.23/19.75 bnd_c4_1 X119) |
% 20.23/19.75 (ALL X121.
% 20.23/19.75 bnd_ndr1_1 X119 -->
% 20.23/19.75 (bnd_c10_2 X119 X121 |
% 20.23/19.75 ~ bnd_c2_2 X119 X121) |
% 20.23/19.75 ~ bnd_c9_2 X119 X121)) |
% 20.23/19.75 ((bnd_ndr1_0 & bnd_c1_1 bnd_a1079) &
% 20.23/19.75 ~ bnd_c9_1 bnd_a1079) &
% 20.23/19.75 ~ bnd_c8_1 bnd_a1079) |
% 20.23/19.75 ((bnd_ndr1_0 &
% 20.23/19.75 (ALL X122.
% 20.23/19.75 bnd_ndr1_1 bnd_a1080 -->
% 20.23/19.75 (~ bnd_c1_2 bnd_a1080 X122 |
% 20.23/19.75 bnd_c10_2 bnd_a1080 X122) |
% 20.23/19.75 ~ bnd_c9_2 bnd_a1080 X122)) &
% 20.23/19.75 bnd_c3_1 bnd_a1080) &
% 20.23/19.75 (ALL X123.
% 20.23/19.75 bnd_ndr1_1 bnd_a1080 -->
% 20.23/19.75 (~ bnd_c6_2 bnd_a1080 X123 |
% 20.23/19.75 ~ bnd_c7_2 bnd_a1080 X123) |
% 20.23/19.75 ~ bnd_c9_2 bnd_a1080 X123))) &
% 20.23/19.75 ((((((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a1081) &
% 20.23/19.75 bnd_c8_2 bnd_a1081 bnd_a1082) &
% 20.23/19.75 ~ bnd_c9_2 bnd_a1081 bnd_a1082) &
% 20.23/19.75 ~ bnd_c1_2 bnd_a1081 bnd_a1082) &
% 20.23/19.75 bnd_ndr1_1 bnd_a1081) &
% 20.23/19.75 bnd_c7_2 bnd_a1081 bnd_a1083) &
% 20.23/19.75 ~ bnd_c6_2 bnd_a1081 bnd_a1083) &
% 20.23/19.75 bnd_c3_2 bnd_a1081 bnd_a1083) &
% 20.23/19.75 (ALL X124.
% 20.23/19.75 bnd_ndr1_1 bnd_a1081 -->
% 20.23/19.75 (bnd_c6_2 bnd_a1081 X124 |
% 20.23/19.75 bnd_c1_2 bnd_a1081 X124) |
% 20.23/19.75 ~ bnd_c3_2 bnd_a1081 X124) |
% 20.23/19.75 ~ bnd_c8_0) |
% 20.23/19.75 ~ bnd_c5_0)) &
% 20.23/19.75 (((ALL X125.
% 20.23/19.75 bnd_ndr1_0 -->
% 20.23/19.75 (((bnd_ndr1_1 X125 &
% 20.23/19.75 ~ bnd_c2_2 X125 bnd_a1084) &
% 20.23/19.75 ~ bnd_c9_2 X125 bnd_a1084) &
% 20.23/19.75 ~ bnd_c5_2 X125 bnd_a1084 |
% 20.23/19.75 ~ bnd_c2_1 X125) |
% 20.23/19.75 (ALL X126.
% 20.23/19.75 bnd_ndr1_1 X125 -->
% 20.23/19.75 ~ bnd_c1_2 X125 X126 |
% 20.23/19.75 bnd_c6_2 X125 X126)) |
% 20.23/19.75 (ALL X127.
% 20.23/19.75 bnd_ndr1_0 -->
% 20.23/19.75 (((bnd_ndr1_1 X127 & bnd_c3_2 X127 bnd_a1085) &
% 20.23/19.75 ~ bnd_c2_2 X127 bnd_a1085) &
% 20.23/19.75 ~ bnd_c9_2 X127 bnd_a1085 |
% 20.23/19.75 bnd_c6_1 X127) |
% 20.23/19.75 ((bnd_ndr1_1 X127 & ~ bnd_c2_2 X127 bnd_a1086) &
% 20.23/19.75 bnd_c9_2 X127 bnd_a1086) &
% 20.23/19.75 bnd_c4_2 X127 bnd_a1086)) |
% 20.23/19.75 ~ bnd_c7_0)) &
% 20.23/19.75 (~ bnd_c2_0 |
% 20.23/19.75 (((((bnd_ndr1_0 &
% 20.23/19.75 (ALL X128.
% 20.23/19.75 bnd_ndr1_1 bnd_a1087 -->
% 20.23/19.75 (bnd_c6_2 bnd_a1087 X128 |
% 20.23/19.75 ~ bnd_c8_2 bnd_a1087 X128) |
% 20.23/19.75 ~ bnd_c3_2 bnd_a1087 X128)) &
% 20.23/19.75 bnd_ndr1_1 bnd_a1087) &
% 20.23/19.75 ~ bnd_c5_2 bnd_a1087 bnd_a1088) &
% 20.23/19.75 ~ bnd_c4_2 bnd_a1087 bnd_a1088) &
% 20.23/19.75 ~ bnd_c10_2 bnd_a1087 bnd_a1088) &
% 20.23/19.75 (ALL X129.
% 20.23/19.75 bnd_ndr1_1 bnd_a1087 -->
% 20.23/19.75 (bnd_c9_2 bnd_a1087 X129 |
% 20.23/19.75 bnd_c5_2 bnd_a1087 X129) |
% 20.23/19.75 bnd_c6_2 bnd_a1087 X129))) &
% 20.23/19.75 (((((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a1089) &
% 20.23/19.75 bnd_c10_2 bnd_a1089 bnd_a1090) &
% 20.23/19.75 bnd_c9_2 bnd_a1089 bnd_a1090) &
% 20.23/19.75 bnd_c7_2 bnd_a1089 bnd_a1090) &
% 20.23/19.75 bnd_ndr1_1 bnd_a1089) &
% 20.23/19.75 bnd_c1_2 bnd_a1089 bnd_a1091) &
% 20.23/19.75 ~ bnd_c7_2 bnd_a1089 bnd_a1091) &
% 20.23/19.75 bnd_c5_1 bnd_a1089 |
% 20.23/19.75 (ALL X130.
% 20.23/19.75 bnd_ndr1_0 -->
% 20.23/19.75 (~ bnd_c2_1 X130 | bnd_c7_1 X130) |
% 20.23/19.75 bnd_c10_1 X130)) |
% 20.23/19.75 ((((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a1092) &
% 20.23/19.75 ~ bnd_c4_2 bnd_a1092 bnd_a1093) &
% 20.23/19.75 ~ bnd_c10_2 bnd_a1092 bnd_a1093) &
% 20.23/19.75 ~ bnd_c7_2 bnd_a1092 bnd_a1093) &
% 20.23/19.75 bnd_ndr1_1 bnd_a1092) &
% 20.23/19.75 bnd_c10_2 bnd_a1092 bnd_a1094) &
% 20.23/19.75 ~ bnd_c5_2 bnd_a1092 bnd_a1094) &
% 20.23/19.75 ~ bnd_c3_2 bnd_a1092 bnd_a1094) &
% 20.23/19.75 ~ bnd_c10_1 bnd_a1092)) &
% 20.23/19.75 ((bnd_c6_0 |
% 20.23/19.75 ((bnd_ndr1_0 &
% 20.23/19.75 (ALL X131.
% 20.23/19.75 bnd_ndr1_1 bnd_a1095 -->
% 20.23/19.75 (~ bnd_c9_2 bnd_a1095 X131 |
% 20.23/19.75 ~ bnd_c5_2 bnd_a1095 X131) |
% 20.23/19.75 bnd_c2_2 bnd_a1095 X131)) &
% 20.23/19.75 ~ bnd_c9_1 bnd_a1095) &
% 20.23/19.75 (ALL X132.
% 20.23/19.75 bnd_ndr1_1 bnd_a1095 -->
% 20.23/19.75 (bnd_c8_2 bnd_a1095 X132 |
% 20.23/19.75 bnd_c2_2 bnd_a1095 X132) |
% 20.23/19.75 ~ bnd_c9_2 bnd_a1095 X132)) |
% 20.23/19.75 bnd_c5_0)) &
% 20.23/19.75 ((~ bnd_c4_0 | bnd_c2_0) |
% 20.23/19.75 (ALL X133.
% 20.23/19.75 bnd_ndr1_0 -->
% 20.23/19.75 ((ALL X134.
% 20.23/19.75 bnd_ndr1_1 X133 -->
% 20.23/19.75 ~ bnd_c3_2 X133 X134 | ~ bnd_c7_2 X133 X134) |
% 20.23/19.75 ~ bnd_c6_1 X133) |
% 20.23/19.75 ((bnd_ndr1_1 X133 & ~ bnd_c4_2 X133 bnd_a1096) &
% 20.23/19.75 ~ bnd_c7_2 X133 bnd_a1096) &
% 20.23/19.75 bnd_c6_2 X133 bnd_a1096))) &
% 20.23/19.75 (((ALL X135.
% 20.23/19.75 bnd_ndr1_0 -->
% 20.23/19.75 (bnd_c7_1 X135 | bnd_c3_1 X135) |
% 20.23/19.75 (ALL X136.
% 20.23/19.75 bnd_ndr1_1 X135 -->
% 20.23/19.75 (bnd_c7_2 X135 X136 | ~ bnd_c6_2 X135 X136) |
% 20.23/19.75 bnd_c9_2 X135 X136)) |
% 20.23/19.75 bnd_c6_0) |
% 20.23/19.75 (ALL X137.
% 20.23/19.75 bnd_ndr1_0 -->
% 20.23/19.75 ((ALL X138.
% 20.23/19.75 bnd_ndr1_1 X137 -->
% 20.23/19.75 (~ bnd_c1_2 X137 X138 | ~ bnd_c9_2 X137 X138) |
% 20.23/19.75 bnd_c6_2 X137 X138) |
% 20.23/19.75 (bnd_ndr1_1 X137 & ~ bnd_c6_2 X137 bnd_a1097) &
% 20.23/19.75 bnd_c9_2 X137 bnd_a1097) |
% 20.23/19.75 ~ bnd_c4_1 X137))) &
% 20.23/19.75 ((bnd_c6_0 | bnd_c9_0) | bnd_c7_0)) &
% 20.23/19.75 ((bnd_c4_0 | ~ bnd_c7_0) |
% 20.23/19.75 (ALL X139.
% 20.23/19.75 bnd_ndr1_0 -->
% 20.23/19.75 (~ bnd_c6_1 X139 |
% 20.23/19.75 (ALL X140.
% 20.23/19.75 bnd_ndr1_1 X139 -->
% 20.23/19.75 bnd_c5_2 X139 X140 | bnd_c9_2 X139 X140)) |
% 20.23/19.75 ~ bnd_c3_1 X139))) &
% 20.23/19.75 ((ALL X141.
% 20.23/19.75 bnd_ndr1_0 -->
% 20.23/19.75 (~ bnd_c1_1 X141 | ~ bnd_c2_1 X141) |
% 20.23/19.75 (ALL X142.
% 20.23/19.75 bnd_ndr1_1 X141 -->
% 20.23/19.75 (bnd_c8_2 X141 X142 | ~ bnd_c4_2 X141 X142) |
% 20.23/19.75 bnd_c7_2 X141 X142)) |
% 20.23/19.75 ((bnd_ndr1_0 & ~ bnd_c8_1 bnd_a1098) &
% 20.23/19.75 (ALL X143.
% 20.23/19.75 bnd_ndr1_1 bnd_a1098 -->
% 20.23/19.75 (~ bnd_c9_2 bnd_a1098 X143 |
% 20.23/19.75 ~ bnd_c2_2 bnd_a1098 X143) |
% 20.23/19.75 bnd_c3_2 bnd_a1098 X143)) &
% 20.23/19.75 ~ bnd_c5_1 bnd_a1098)) &
% 20.23/19.75 ((~ bnd_c9_0 | bnd_c4_0) |
% 20.23/19.75 ((bnd_ndr1_0 &
% 20.23/19.75 (ALL X144.
% 20.23/19.75 bnd_ndr1_1 bnd_a1099 -->
% 20.23/19.75 (bnd_c7_2 bnd_a1099 X144 | bnd_c8_2 bnd_a1099 X144) |
% 20.23/19.75 bnd_c3_2 bnd_a1099 X144)) &
% 20.23/19.75 bnd_c5_1 bnd_a1099) &
% 20.23/19.75 ~ bnd_c8_1 bnd_a1099)) &
% 20.23/19.75 (((ALL X145.
% 20.23/19.75 bnd_ndr1_0 -->
% 20.23/19.75 ((bnd_ndr1_1 X145 & ~ bnd_c10_2 X145 bnd_a1100) &
% 20.23/19.75 bnd_c8_2 X145 bnd_a1100 |
% 20.23/19.75 ~ bnd_c2_1 X145) |
% 20.23/19.75 ~ bnd_c5_1 X145) |
% 20.23/19.75 ~ bnd_c2_0) |
% 20.23/19.75 bnd_c5_0)) &
% 20.23/19.75 (ALL X146.
% 20.23/19.75 bnd_ndr1_0 -->
% 20.23/19.75 (~ bnd_c10_1 X146 | ~ bnd_c2_1 X146) |
% 20.23/19.75 (ALL X147.
% 20.23/19.75 bnd_ndr1_1 X146 -->
% 20.23/19.75 bnd_c3_2 X146 X147 | bnd_c2_2 X146 X147))) &
% 20.23/19.75 ((bnd_c3_0 |
% 20.23/19.75 (ALL X148.
% 20.23/19.75 bnd_ndr1_0 -->
% 20.23/19.75 (bnd_c8_1 X148 | bnd_c1_1 X148) |
% 20.23/19.75 ((bnd_ndr1_1 X148 & bnd_c4_2 X148 bnd_a1101) &
% 20.23/19.75 bnd_c5_2 X148 bnd_a1101) &
% 20.23/19.75 bnd_c3_2 X148 bnd_a1101)) |
% 20.23/19.75 (ALL X149.
% 20.23/19.75 bnd_ndr1_0 -->
% 20.23/19.75 ((ALL X150.
% 20.23/19.75 bnd_ndr1_1 X149 -->
% 20.23/19.75 (~ bnd_c2_2 X149 X150 | ~ bnd_c1_2 X149 X150) |
% 20.23/19.75 bnd_c10_2 X149 X150) |
% 20.23/19.75 ((bnd_ndr1_1 X149 & ~ bnd_c4_2 X149 bnd_a1102) &
% 20.23/19.75 ~ bnd_c5_2 X149 bnd_a1102) &
% 20.23/19.75 bnd_c8_2 X149 bnd_a1102) |
% 20.23/19.75 bnd_c3_1 X149))) &
% 20.23/19.75 ((bnd_c9_0 | bnd_c6_0) |
% 20.23/19.75 (ALL X151.
% 20.23/19.75 bnd_ndr1_0 -->
% 20.23/19.75 (bnd_c4_1 X151 | ~ bnd_c1_1 X151) |
% 20.23/19.75 (bnd_ndr1_1 X151 & ~ bnd_c2_2 X151 bnd_a1103) &
% 20.23/19.75 ~ bnd_c7_2 X151 bnd_a1103))) &
% 20.23/19.75 ((ALL X152.
% 20.23/19.75 bnd_ndr1_0 -->
% 20.23/19.75 (((bnd_ndr1_1 X152 & ~ bnd_c3_2 X152 bnd_a1104) &
% 20.23/19.75 bnd_c9_2 X152 bnd_a1104) &
% 20.23/19.75 ~ bnd_c2_2 X152 bnd_a1104 |
% 20.23/19.75 ~ bnd_c2_1 X152) |
% 20.23/19.75 bnd_c3_1 X152) |
% 20.23/19.75 (ALL X153.
% 20.23/19.75 bnd_ndr1_0 -->
% 20.23/19.75 (bnd_c6_1 X153 | bnd_c3_1 X153) |
% 20.23/19.75 ((bnd_ndr1_1 X153 & bnd_c1_2 X153 bnd_a1105) &
% 20.23/19.75 ~ bnd_c5_2 X153 bnd_a1105) &
% 20.23/19.75 ~ bnd_c8_2 X153 bnd_a1105))) &
% 20.23/19.75 ((bnd_c3_0 | bnd_c4_0) | bnd_c6_0)) &
% 20.23/19.75 (((ALL X154. bnd_ndr1_0 --> ~ bnd_c3_1 X154 | ~ bnd_c8_1 X154) |
% 20.23/19.75 (((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a1106) &
% 20.23/19.75 ~ bnd_c6_2 bnd_a1106 bnd_a1107) &
% 20.23/19.75 bnd_c4_2 bnd_a1106 bnd_a1107) &
% 20.23/19.75 bnd_c9_2 bnd_a1106 bnd_a1107) &
% 20.23/19.75 bnd_ndr1_1 bnd_a1106) &
% 20.23/19.75 ~ bnd_c10_2 bnd_a1106 bnd_a1108) &
% 20.23/19.75 ~ bnd_c3_2 bnd_a1106 bnd_a1108) &
% 20.23/19.75 ~ bnd_c8_2 bnd_a1106 bnd_a1108) |
% 20.23/19.75 ~ bnd_c1_0)) &
% 20.23/19.75 (((ALL X155.
% 20.23/19.75 bnd_ndr1_0 -->
% 20.23/19.75 (((bnd_ndr1_1 X155 & ~ bnd_c1_2 X155 bnd_a1109) &
% 20.23/19.75 bnd_c4_2 X155 bnd_a1109) &
% 20.23/19.75 ~ bnd_c2_2 X155 bnd_a1109 |
% 20.23/19.75 (ALL X156.
% 20.23/19.75 bnd_ndr1_1 X155 -->
% 20.23/19.75 bnd_c10_2 X155 X156 | bnd_c2_2 X155 X156)) |
% 20.23/19.75 (ALL X157.
% 20.23/19.75 bnd_ndr1_1 X155 -->
% 20.23/19.75 (~ bnd_c3_2 X155 X157 | bnd_c10_2 X155 X157) |
% 20.23/19.75 bnd_c8_2 X155 X157)) |
% 20.23/19.75 bnd_c9_0) |
% 20.23/19.75 bnd_c4_0)) &
% 20.23/19.75 (((ALL X158.
% 20.23/19.75 bnd_ndr1_0 -->
% 20.23/19.75 bnd_c10_1 X158 |
% 20.23/19.75 ((bnd_ndr1_1 X158 & ~ bnd_c10_2 X158 bnd_a1110) &
% 20.23/19.75 ~ bnd_c7_2 X158 bnd_a1110) &
% 20.23/19.75 ~ bnd_c2_2 X158 bnd_a1110) |
% 20.23/19.75 (ALL X159.
% 20.23/19.75 bnd_ndr1_0 -->
% 20.23/19.75 (((bnd_ndr1_1 X159 & bnd_c10_2 X159 bnd_a1111) &
% 20.23/19.75 bnd_c9_2 X159 bnd_a1111) &
% 20.23/19.75 ~ bnd_c3_2 X159 bnd_a1111 |
% 20.23/19.75 ~ bnd_c6_1 X159) |
% 20.23/19.75 ((bnd_ndr1_1 X159 & ~ bnd_c9_2 X159 bnd_a1112) &
% 20.23/19.75 bnd_c7_2 X159 bnd_a1112) &
% 20.23/19.75 bnd_c5_2 X159 bnd_a1112)) |
% 20.23/19.75 (ALL X160.
% 20.23/19.75 bnd_ndr1_0 -->
% 20.23/19.75 ((bnd_ndr1_1 X160 & bnd_c6_2 X160 bnd_a1113) &
% 20.23/19.75 bnd_c3_2 X160 bnd_a1113) &
% 20.23/19.75 bnd_c1_2 X160 bnd_a1113 |
% 20.23/19.75 ~ bnd_c7_1 X160))) &
% 20.23/19.75 ((~ bnd_c5_0 |
% 20.23/19.75 ((bnd_ndr1_0 & bnd_c9_1 bnd_a1114) & bnd_c2_1 bnd_a1114) &
% 20.23/19.75 ~ bnd_c1_1 bnd_a1114) |
% 20.23/19.75 (ALL X161.
% 20.23/19.75 bnd_ndr1_0 -->
% 20.23/19.75 (bnd_c4_1 X161 | ~ bnd_c5_1 X161) | ~ bnd_c1_1 X161))) &
% 20.23/19.75 (~ bnd_c10_0 | ~ bnd_c1_0)) &
% 20.23/19.75 ((~ bnd_c10_0 |
% 20.23/19.75 (((((bnd_ndr1_0 &
% 20.23/19.75 (ALL X162.
% 20.23/19.75 bnd_ndr1_1 bnd_a1115 -->
% 20.23/19.75 (bnd_c9_2 bnd_a1115 X162 | bnd_c2_2 bnd_a1115 X162) |
% 20.23/19.75 bnd_c7_2 bnd_a1115 X162)) &
% 20.23/19.75 bnd_ndr1_1 bnd_a1115) &
% 20.23/19.75 ~ bnd_c10_2 bnd_a1115 bnd_a1116) &
% 20.23/19.75 bnd_c9_2 bnd_a1115 bnd_a1116) &
% 20.23/19.75 ~ bnd_c6_2 bnd_a1115 bnd_a1116) &
% 20.23/19.75 (ALL X163.
% 20.23/19.75 bnd_ndr1_1 bnd_a1115 -->
% 20.23/19.75 (~ bnd_c8_2 bnd_a1115 X163 | bnd_c9_2 bnd_a1115 X163) |
% 20.23/19.75 ~ bnd_c5_2 bnd_a1115 X163)) |
% 20.23/19.75 (ALL X164.
% 20.23/19.75 bnd_ndr1_0 -->
% 20.23/19.75 (bnd_c6_1 X164 | bnd_c3_1 X164) |
% 20.23/19.75 (bnd_ndr1_1 X164 & ~ bnd_c10_2 X164 bnd_a1117) &
% 20.23/19.75 ~ bnd_c1_2 X164 bnd_a1117))) &
% 20.23/19.75 (((((((bnd_ndr1_0 & bnd_c7_1 bnd_a1118) & bnd_c6_1 bnd_a1118) &
% 20.23/19.75 bnd_ndr1_1 bnd_a1118) &
% 20.23/19.75 ~ bnd_c5_2 bnd_a1118 bnd_a1119) &
% 20.23/19.75 bnd_c4_2 bnd_a1118 bnd_a1119) &
% 20.23/19.75 ~ bnd_c2_2 bnd_a1118 bnd_a1119 |
% 20.23/19.75 (((((bnd_ndr1_0 & ~ bnd_c1_1 bnd_a1120) & bnd_c4_1 bnd_a1120) &
% 20.23/19.75 bnd_ndr1_1 bnd_a1120) &
% 20.23/19.75 bnd_c2_2 bnd_a1120 bnd_a1121) &
% 20.23/19.75 bnd_c1_2 bnd_a1120 bnd_a1121) &
% 20.23/19.75 bnd_c9_2 bnd_a1120 bnd_a1121) |
% 20.23/19.75 bnd_c8_0)) &
% 20.23/19.75 (((ALL X165.
% 20.23/19.75 bnd_ndr1_0 -->
% 20.23/19.75 (bnd_c10_1 X165 |
% 20.23/19.75 ((bnd_ndr1_1 X165 & ~ bnd_c9_2 X165 bnd_a1122) &
% 20.23/19.75 ~ bnd_c2_2 X165 bnd_a1122) &
% 20.23/19.75 bnd_c10_2 X165 bnd_a1122) |
% 20.23/19.75 bnd_c8_1 X165) |
% 20.23/19.75 ~ bnd_c7_0) |
% 20.23/19.75 ((bnd_ndr1_0 & bnd_c5_1 bnd_a1123) &
% 20.23/19.75 (ALL X166.
% 20.23/19.75 bnd_ndr1_1 bnd_a1123 -->
% 20.23/19.75 (bnd_c7_2 bnd_a1123 X166 | bnd_c1_2 bnd_a1123 X166) |
% 20.23/19.75 bnd_c6_2 bnd_a1123 X166)) &
% 20.23/19.75 (ALL X167.
% 20.23/19.75 bnd_ndr1_1 bnd_a1123 -->
% 20.23/19.75 (bnd_c6_2 bnd_a1123 X167 | ~ bnd_c1_2 bnd_a1123 X167) |
% 20.23/19.75 ~ bnd_c10_2 bnd_a1123 X167))) &
% 20.23/19.75 (((ALL X168.
% 20.23/19.75 bnd_ndr1_0 --> (~ bnd_c7_1 X168 | bnd_c6_1 X168) | bnd_c10_1 X168) |
% 20.23/19.75 ~ bnd_c4_0) |
% 20.23/19.75 ((bnd_ndr1_0 &
% 20.23/19.75 (ALL X169.
% 20.23/19.75 bnd_ndr1_1 bnd_a1124 -->
% 20.23/19.75 (bnd_c6_2 bnd_a1124 X169 | ~ bnd_c4_2 bnd_a1124 X169) |
% 20.23/19.75 ~ bnd_c8_2 bnd_a1124 X169)) &
% 20.23/19.75 bnd_c7_1 bnd_a1124) &
% 20.23/19.75 ~ bnd_c2_1 bnd_a1124)) &
% 20.23/19.75 ((bnd_c8_0 |
% 20.23/19.75 ((((((((bnd_ndr1_0 &
% 20.23/19.75 bnd_ndr1_1 bnd_a1125) &
% 20.23/19.75 bnd_c8_2 bnd_a1125 bnd_a1126) &
% 20.23/19.75 ~ bnd_c3_2 bnd_a1125 bnd_a1126) &
% 20.23/19.75 ~ bnd_c10_2 bnd_a1125 bnd_a1126) &
% 20.23/19.75 ~ bnd_c4_1 bnd_a1125) &
% 20.23/19.75 bnd_ndr1_1 bnd_a1125) &
% 20.23/19.75 bnd_c5_2 bnd_a1125 bnd_a1127) &
% 20.23/19.75 ~ bnd_c1_2 bnd_a1125 bnd_a1127) &
% 20.23/19.75 bnd_c4_2 bnd_a1125 bnd_a1127) |
% 20.23/19.75 ~ bnd_c6_0)) &
% 20.23/19.75 ((~ bnd_c6_0 | bnd_c5_0) | bnd_c1_0)) &
% 20.23/19.75 (((ALL X170.
% 20.23/19.75 bnd_ndr1_0 -->
% 20.23/19.75 ((ALL X171.
% 20.23/19.75 bnd_ndr1_1 X170 -->
% 20.23/19.75 (~ bnd_c7_2 X170 X171 | ~ bnd_c3_2 X170 X171) |
% 20.23/19.75 ~ bnd_c1_2 X170 X171) |
% 20.23/19.75 (bnd_ndr1_1 X170 & ~ bnd_c7_2 X170 bnd_a1128) &
% 20.23/19.75 ~ bnd_c10_2 X170 bnd_a1128) |
% 20.23/19.75 ((bnd_ndr1_1 X170 & ~ bnd_c4_2 X170 bnd_a1129) & bnd_c1_2 X170 bnd_a1129) &
% 20.23/19.75 ~ bnd_c6_2 X170 bnd_a1129) |
% 20.23/19.75 bnd_c10_0) |
% 20.23/19.75 ((bnd_ndr1_0 & ~ bnd_c10_1 bnd_a1130) &
% 20.23/19.75 (ALL X172.
% 20.23/19.75 bnd_ndr1_1 bnd_a1130 -->
% 20.23/19.75 (bnd_c9_2 bnd_a1130 X172 | bnd_c1_2 bnd_a1130 X172) |
% 20.23/19.75 bnd_c10_2 bnd_a1130 X172)) &
% 20.23/19.75 ~ bnd_c8_1 bnd_a1130)) &
% 20.23/19.75 ((((((bnd_ndr1_0 &
% 20.23/19.75 (ALL X173.
% 20.23/19.75 bnd_ndr1_1 bnd_a1131 -->
% 20.23/19.75 (bnd_c4_2 bnd_a1131 X173 | bnd_c6_2 bnd_a1131 X173) |
% 20.23/19.75 bnd_c3_2 bnd_a1131 X173)) &
% 20.23/19.75 bnd_ndr1_1 bnd_a1131) &
% 20.23/19.75 ~ bnd_c4_2 bnd_a1131 bnd_a1132) &
% 20.23/19.75 bnd_c2_2 bnd_a1131 bnd_a1132) &
% 20.23/19.75 (ALL X174.
% 20.23/19.75 bnd_ndr1_1 bnd_a1131 -->
% 20.23/19.75 (bnd_c4_2 bnd_a1131 X174 | ~ bnd_c3_2 bnd_a1131 X174) |
% 20.23/19.75 ~ bnd_c1_2 bnd_a1131 X174) |
% 20.23/19.75 (((((bnd_ndr1_0 & bnd_c7_1 bnd_a1133) &
% 20.23/19.75 ~ bnd_c2_1 bnd_a1133) &
% 20.23/19.75 bnd_ndr1_1 bnd_a1133) &
% 20.23/19.75 ~ bnd_c2_2 bnd_a1133 bnd_a1134) &
% 20.23/19.75 bnd_c5_2 bnd_a1133 bnd_a1134) &
% 20.23/19.75 ~ bnd_c6_2 bnd_a1133 bnd_a1134) |
% 20.23/19.75 ~ bnd_c9_0)) &
% 20.23/19.75 ((bnd_c6_0 |
% 20.23/19.75 ((bnd_ndr1_0 & bnd_c9_1 bnd_a1135) &
% 20.23/19.75 bnd_c4_1 bnd_a1135) &
% 20.23/19.75 ~ bnd_c3_1 bnd_a1135) |
% 20.23/19.75 (((((bnd_ndr1_0 & ~ bnd_c9_1 bnd_a1136) &
% 20.23/19.75 bnd_ndr1_1 bnd_a1136) &
% 20.23/19.75 ~ bnd_c3_2 bnd_a1136 bnd_a1137) &
% 20.23/19.75 bnd_c1_2 bnd_a1136 bnd_a1137) &
% 20.23/19.75 ~ bnd_c6_2 bnd_a1136 bnd_a1137) &
% 20.23/19.75 bnd_c1_1 bnd_a1136)) &
% 20.23/19.75 (((ALL X175.
% 20.23/19.75 bnd_ndr1_0 -->
% 20.23/19.75 ((bnd_ndr1_1 X175 &
% 20.23/19.75 bnd_c10_2 X175 bnd_a1138) &
% 20.23/19.75 bnd_c2_2 X175 bnd_a1138) &
% 20.23/19.75 bnd_c9_2 X175 bnd_a1138 |
% 20.23/19.75 bnd_c3_1 X175) |
% 20.23/19.75 ~ bnd_c9_0) |
% 20.23/19.75 bnd_c4_0)) &
% 20.23/19.75 ((~ bnd_c9_0 |
% 20.23/19.75 (ALL X176.
% 20.23/19.75 bnd_ndr1_0 -->
% 20.23/19.75 ~ bnd_c10_1 X176 |
% 20.23/19.75 (ALL X177.
% 20.23/19.75 bnd_ndr1_1 X176 -->
% 20.23/19.75 (~ bnd_c10_2 X176 X177 | ~ bnd_c9_2 X176 X177) | ~ bnd_c8_2 X176 X177))) |
% 20.23/19.75 ~ bnd_c1_0)) &
% 20.23/19.75 ((((bnd_ndr1_0 & ~ bnd_c1_1 bnd_a1139) &
% 20.23/19.75 (ALL X178.
% 20.23/19.75 bnd_ndr1_1 bnd_a1139 -->
% 20.23/19.75 (bnd_c7_2 bnd_a1139 X178 |
% 20.23/19.75 ~ bnd_c6_2 bnd_a1139 X178) |
% 20.23/19.75 bnd_c5_2 bnd_a1139 X178)) &
% 20.23/19.75 ~ bnd_c10_1 bnd_a1139 |
% 20.23/19.75 ((((bnd_ndr1_0 & bnd_c6_1 bnd_a1140) &
% 20.23/19.75 bnd_ndr1_1 bnd_a1140) &
% 20.23/19.75 bnd_c9_2 bnd_a1140 bnd_a1141) &
% 20.23/19.75 ~ bnd_c1_2 bnd_a1140 bnd_a1141) &
% 20.23/19.75 ~ bnd_c4_2 bnd_a1140 bnd_a1141) |
% 20.23/19.75 ~ bnd_c1_0)) &
% 20.23/19.75 (((ALL X179.
% 20.23/19.75 bnd_ndr1_0 -->
% 20.23/19.75 (~ bnd_c2_1 X179 |
% 20.23/19.75 ((bnd_ndr1_1 X179 &
% 20.23/19.75 ~ bnd_c1_2 X179 bnd_a1142) &
% 20.23/19.75 ~ bnd_c8_2 X179 bnd_a1142) &
% 20.23/19.75 ~ bnd_c4_2 X179 bnd_a1142) |
% 20.23/19.75 bnd_c5_1 X179) |
% 20.23/19.75 bnd_c4_0) |
% 20.23/19.75 (bnd_ndr1_0 & bnd_c8_1 bnd_a1143) &
% 20.23/19.75 ~ bnd_c7_1 bnd_a1143)) &
% 20.23/19.75 ((bnd_c9_0 | ~ bnd_c4_0) |
% 20.23/19.75 (((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a1144) &
% 20.23/19.75 bnd_c4_2 bnd_a1144 bnd_a1145) &
% 20.23/19.75 ~ bnd_c1_2 bnd_a1144 bnd_a1145) &
% 20.23/19.75 bnd_c3_2 bnd_a1144 bnd_a1145) &
% 20.23/19.75 ~ bnd_c5_1 bnd_a1144) &
% 20.23/19.75 ~ bnd_c10_1 bnd_a1144)) &
% 20.23/19.75 ((bnd_c8_0 | ~ bnd_c7_0) |
% 20.23/19.75 (ALL X180.
% 20.23/19.75 bnd_ndr1_0 -->
% 20.23/19.75 (~ bnd_c5_1 X180 |
% 20.23/19.75 (ALL X181.
% 20.23/19.75 bnd_ndr1_1 X180 -->
% 20.23/19.75 ~ bnd_c1_2 X180 X181 |
% 20.23/19.75 ~ bnd_c8_2 X180 X181)) |
% 20.23/19.75 (ALL X182.
% 20.23/19.75 bnd_ndr1_1 X180 -->
% 20.23/19.75 (~ bnd_c2_2 X180 X182 |
% 20.23/19.75 ~ bnd_c6_2 X180 X182) |
% 20.23/19.75 ~ bnd_c1_2 X180 X182)))) &
% 20.23/19.75 ((~ bnd_c8_0 |
% 20.23/19.75 ((bnd_ndr1_0 &
% 20.23/19.75 (ALL X183.
% 20.23/19.75 bnd_ndr1_1 bnd_a1146 -->
% 20.23/19.75 (bnd_c9_2 bnd_a1146 X183 |
% 20.23/19.75 bnd_c8_2 bnd_a1146 X183) |
% 20.23/19.75 bnd_c10_2 bnd_a1146 X183)) &
% 20.23/19.75 ~ bnd_c2_1 bnd_a1146) &
% 20.23/19.75 ~ bnd_c1_1 bnd_a1146) |
% 20.23/19.75 (ALL X184.
% 20.23/19.75 bnd_ndr1_0 -->
% 20.23/19.75 (((bnd_ndr1_1 X184 &
% 20.23/19.75 ~ bnd_c9_2 X184 bnd_a1147) &
% 20.23/19.75 ~ bnd_c3_2 X184 bnd_a1147) &
% 20.23/19.75 ~ bnd_c6_2 X184 bnd_a1147 |
% 20.23/19.75 bnd_c7_1 X184) |
% 20.23/19.75 bnd_c8_1 X184))) &
% 20.23/19.75 ((~ bnd_c5_0 |
% 20.23/19.75 (ALL X185.
% 20.23/19.75 bnd_ndr1_0 -->
% 20.23/19.75 ((bnd_ndr1_1 X185 &
% 20.23/19.75 ~ bnd_c8_2 X185 bnd_a1148) &
% 20.23/19.75 bnd_c4_2 X185 bnd_a1148 |
% 20.23/19.75 ~ bnd_c2_1 X185) |
% 20.23/19.75 bnd_c9_1 X185)) |
% 20.23/19.75 (ALL X186.
% 20.23/19.75 bnd_ndr1_0 -->
% 20.23/19.75 (~ bnd_c5_1 X186 |
% 20.23/19.75 (ALL X187.
% 20.23/19.75 bnd_ndr1_1 X186 -->
% 20.23/19.75 ~ bnd_c8_2 X186 X187 |
% 20.23/19.75 bnd_c2_2 X186 X187)) |
% 20.23/19.75 bnd_c10_1 X186))) &
% 20.23/19.75 ((~ bnd_c4_0 |
% 20.23/19.75 (ALL X188.
% 20.23/19.75 bnd_ndr1_0 -->
% 20.23/19.75 (~ bnd_c5_1 X188 |
% 20.23/19.75 (bnd_ndr1_1 X188 & ~ bnd_c7_2 X188 bnd_a1149) &
% 20.23/19.75 bnd_c9_2 X188 bnd_a1149) |
% 20.23/19.75 (ALL X189.
% 20.23/19.75 bnd_ndr1_1 X188 -->
% 20.23/19.75 (bnd_c7_2 X188 X189 | bnd_c9_2 X188 X189) |
% 20.23/19.75 bnd_c6_2 X188 X189))) |
% 20.23/19.75 ~ bnd_c2_0)) &
% 20.23/19.75 ((((bnd_ndr1_0 & bnd_c10_1 bnd_a1150) &
% 20.23/19.75 bnd_c5_1 bnd_a1150) &
% 20.23/19.75 bnd_c1_1 bnd_a1150 |
% 20.23/19.75 (ALL X190.
% 20.23/19.75 bnd_ndr1_0 -->
% 20.23/19.75 ((ALL X191.
% 20.23/19.75 bnd_ndr1_1 X190 -->
% 20.23/19.75 (bnd_c4_2 X190 X191 | bnd_c8_2 X190 X191) |
% 20.23/19.75 ~ bnd_c5_2 X190 X191) |
% 20.23/19.75 ~ bnd_c7_1 X190) |
% 20.23/19.75 ~ bnd_c2_1 X190)) |
% 20.23/19.75 bnd_c2_0)) &
% 20.23/19.75 (bnd_c2_0 |
% 20.23/19.75 (ALL X192.
% 20.23/19.75 bnd_ndr1_0 -->
% 20.23/19.75 (~ bnd_c1_1 X192 |
% 20.23/19.75 ((bnd_ndr1_1 X192 & ~ bnd_c3_2 X192 bnd_a1151) &
% 20.23/19.75 bnd_c2_2 X192 bnd_a1151) &
% 20.23/19.75 ~ bnd_c5_2 X192 bnd_a1151) |
% 20.23/19.75 ((bnd_ndr1_1 X192 & ~ bnd_c10_2 X192 bnd_a1152) &
% 20.23/19.75 bnd_c8_2 X192 bnd_a1152) &
% 20.23/19.75 ~ bnd_c4_2 X192 bnd_a1152))) &
% 20.23/19.75 ((bnd_c8_0 | bnd_c9_0) |
% 20.23/19.75 (ALL X193.
% 20.23/19.75 bnd_ndr1_0 -->
% 20.23/19.75 (~ bnd_c5_1 X193 | ~ bnd_c7_1 X193) |
% 20.23/19.75 (ALL X194.
% 20.23/19.75 bnd_ndr1_1 X193 -->
% 20.23/19.75 (~ bnd_c6_2 X193 X194 | ~ bnd_c2_2 X193 X194) |
% 20.23/19.75 ~ bnd_c3_2 X193 X194)))) &
% 20.23/19.75 ((((bnd_ndr1_0 & bnd_c4_1 bnd_a1153) &
% 20.23/19.75 (ALL X195.
% 20.23/19.75 bnd_ndr1_1 bnd_a1153 -->
% 20.23/19.75 (bnd_c6_2 bnd_a1153 X195 |
% 20.23/19.75 ~ bnd_c10_2 bnd_a1153 X195) |
% 20.23/19.75 bnd_c9_2 bnd_a1153 X195)) &
% 20.23/19.75 ~ bnd_c9_1 bnd_a1153 |
% 20.23/19.75 bnd_c7_0) |
% 20.23/19.75 ((bnd_ndr1_0 & ~ bnd_c6_1 bnd_a1154) &
% 20.23/19.75 bnd_c9_1 bnd_a1154) &
% 20.23/19.75 (ALL X196.
% 20.23/19.75 bnd_ndr1_1 bnd_a1154 -->
% 20.23/19.75 (bnd_c4_2 bnd_a1154 X196 |
% 20.23/19.75 ~ bnd_c9_2 bnd_a1154 X196) |
% 20.23/19.75 bnd_c7_2 bnd_a1154 X196))) &
% 20.23/19.75 ((((bnd_ndr1_0 & bnd_c6_1 bnd_a1155) &
% 20.23/19.75 (ALL X197.
% 20.23/19.75 bnd_ndr1_1 bnd_a1155 -->
% 20.23/19.75 (bnd_c9_2 bnd_a1155 X197 |
% 20.23/19.75 bnd_c4_2 bnd_a1155 X197) |
% 20.23/19.75 bnd_c8_2 bnd_a1155 X197)) &
% 20.23/19.75 (ALL X198.
% 20.23/19.75 bnd_ndr1_1 bnd_a1155 -->
% 20.23/19.75 (bnd_c3_2 bnd_a1155 X198 | bnd_c1_2 bnd_a1155 X198) |
% 20.23/19.75 ~ bnd_c9_2 bnd_a1155 X198) |
% 20.23/19.75 ~ bnd_c10_0) |
% 20.23/19.75 (ALL X199.
% 20.23/19.75 bnd_ndr1_0 -->
% 20.23/19.75 (((bnd_ndr1_1 X199 & ~ bnd_c10_2 X199 bnd_a1156) &
% 20.23/19.75 bnd_c6_2 X199 bnd_a1156) &
% 20.23/19.75 ~ bnd_c9_2 X199 bnd_a1156 |
% 20.23/19.75 ((bnd_ndr1_1 X199 & bnd_c4_2 X199 bnd_a1157) &
% 20.23/19.75 bnd_c6_2 X199 bnd_a1157) &
% 20.23/19.75 ~ bnd_c10_2 X199 bnd_a1157) |
% 20.23/19.75 ((bnd_ndr1_1 X199 & ~ bnd_c7_2 X199 bnd_a1158) &
% 20.23/19.75 bnd_c6_2 X199 bnd_a1158) &
% 20.23/19.75 ~ bnd_c8_2 X199 bnd_a1158))) &
% 20.23/19.75 (((ALL X200.
% 20.23/19.75 bnd_ndr1_0 -->
% 20.23/19.75 ((ALL X201.
% 20.23/19.75 bnd_ndr1_1 X200 -->
% 20.23/19.75 (~ bnd_c8_2 X200 X201 | bnd_c9_2 X200 X201) |
% 20.23/19.75 ~ bnd_c5_2 X200 X201) |
% 20.23/19.75 ((bnd_ndr1_1 X200 & bnd_c2_2 X200 bnd_a1159) &
% 20.23/19.75 ~ bnd_c9_2 X200 bnd_a1159) &
% 20.23/19.75 bnd_c10_2 X200 bnd_a1159) |
% 20.23/19.75 bnd_c9_1 X200) |
% 20.23/19.75 (((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a1160) &
% 20.23/19.75 ~ bnd_c10_2 bnd_a1160 bnd_a1161) &
% 20.23/19.75 bnd_c7_2 bnd_a1160 bnd_a1161) &
% 20.23/19.75 bnd_c2_2 bnd_a1160 bnd_a1161) &
% 20.23/19.75 (ALL X202.
% 20.23/19.75 bnd_ndr1_1 bnd_a1160 -->
% 20.23/19.75 ~ bnd_c9_2 bnd_a1160 X202 |
% 20.23/19.75 bnd_c10_2 bnd_a1160 X202)) &
% 20.23/19.75 ~ bnd_c6_1 bnd_a1160) |
% 20.23/19.75 ~ bnd_c7_0)) &
% 20.23/19.75 ((~ bnd_c5_0 |
% 20.23/19.75 ((((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a1162) &
% 20.23/19.75 ~ bnd_c8_2 bnd_a1162 bnd_a1163) &
% 20.23/19.75 ~ bnd_c10_2 bnd_a1162 bnd_a1163) &
% 20.23/19.75 ~ bnd_c3_2 bnd_a1162 bnd_a1163) &
% 20.23/19.75 ~ bnd_c6_1 bnd_a1162) &
% 20.23/19.75 bnd_ndr1_1 bnd_a1162) &
% 20.23/19.75 ~ bnd_c5_2 bnd_a1162 bnd_a1164) &
% 20.23/19.75 bnd_c4_2 bnd_a1162 bnd_a1164) &
% 20.23/19.75 bnd_c8_2 bnd_a1162 bnd_a1164) |
% 20.23/19.75 bnd_c4_0)) &
% 20.23/19.75 ((ALL X203.
% 20.23/19.75 bnd_ndr1_0 -->
% 20.23/19.75 ((ALL X204.
% 20.23/19.75 bnd_ndr1_1 X203 -->
% 20.23/19.75 (~ bnd_c3_2 X203 X204 | ~ bnd_c7_2 X203 X204) |
% 20.23/19.75 ~ bnd_c9_2 X203 X204) |
% 20.23/19.75 (ALL X205.
% 20.23/19.75 bnd_ndr1_1 X203 -->
% 20.23/19.75 (bnd_c2_2 X203 X205 | bnd_c8_2 X203 X205) |
% 20.23/19.75 ~ bnd_c6_2 X203 X205)) |
% 20.23/19.75 bnd_c7_1 X203) |
% 20.23/19.75 bnd_c7_0)) &
% 20.23/19.75 ((bnd_c2_0 |
% 20.23/19.75 (((((bnd_ndr1_0 & ~ bnd_c4_1 bnd_a1165) &
% 20.23/19.75 bnd_c10_1 bnd_a1165) &
% 20.23/19.75 bnd_ndr1_1 bnd_a1165) &
% 20.23/19.75 ~ bnd_c5_2 bnd_a1165 bnd_a1166) &
% 20.23/19.75 bnd_c6_2 bnd_a1165 bnd_a1166) &
% 20.23/19.75 bnd_c9_2 bnd_a1165 bnd_a1166) |
% 20.23/19.75 ((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a1167) &
% 20.23/19.75 ~ bnd_c10_2 bnd_a1167 bnd_a1168) &
% 20.23/19.75 ~ bnd_c7_2 bnd_a1167 bnd_a1168) &
% 20.23/19.75 ~ bnd_c3_2 bnd_a1167 bnd_a1168) &
% 20.23/19.75 ~ bnd_c7_1 bnd_a1167)) &
% 20.23/19.75 ((bnd_c2_0 |
% 20.23/19.75 (ALL X206.
% 20.23/19.75 bnd_ndr1_0 -->
% 20.23/19.75 (((bnd_ndr1_1 X206 & ~ bnd_c10_2 X206 bnd_a1169) &
% 20.23/19.75 bnd_c7_2 X206 bnd_a1169) &
% 20.23/19.75 ~ bnd_c1_2 X206 bnd_a1169 |
% 20.23/19.75 (ALL X207.
% 20.23/19.75 bnd_ndr1_1 X206 -->
% 20.23/19.75 (bnd_c2_2 X206 X207 | ~ bnd_c9_2 X206 X207) |
% 20.23/19.75 ~ bnd_c8_2 X206 X207)) |
% 20.23/19.75 (ALL X208.
% 20.23/19.75 bnd_ndr1_1 X206 -->
% 20.23/19.75 (~ bnd_c9_2 X206 X208 | bnd_c2_2 X206 X208) |
% 20.23/19.75 bnd_c3_2 X206 X208))) |
% 20.23/19.75 (ALL X209.
% 20.23/19.75 bnd_ndr1_0 -->
% 20.23/19.75 (~ bnd_c8_1 X209 |
% 20.23/19.75 (ALL X210.
% 20.23/19.75 bnd_ndr1_1 X209 -->
% 20.23/19.75 (~ bnd_c6_2 X209 X210 | ~ bnd_c1_2 X209 X210) |
% 20.23/19.75 ~ bnd_c8_2 X209 X210)) |
% 20.23/19.75 ~ bnd_c10_1 X209))) &
% 20.23/19.75 (((((((bnd_ndr1_0 & bnd_c2_1 bnd_a1170) &
% 20.23/19.75 (ALL X211.
% 20.23/19.75 bnd_ndr1_1 bnd_a1170 -->
% 20.23/19.75 (bnd_c8_2 bnd_a1170 X211 | ~ bnd_c6_2 bnd_a1170 X211) |
% 20.23/19.75 bnd_c10_2 bnd_a1170 X211)) &
% 20.23/19.75 bnd_ndr1_1 bnd_a1170) &
% 20.23/19.75 bnd_c6_2 bnd_a1170 bnd_a1171) &
% 20.23/19.75 ~ bnd_c9_2 bnd_a1170 bnd_a1171) &
% 20.23/19.75 bnd_c10_2 bnd_a1170 bnd_a1171 |
% 20.23/19.75 bnd_c8_0) |
% 20.23/19.75 bnd_c4_0)) &
% 20.23/19.75 (((ALL X212.
% 20.23/19.75 bnd_ndr1_0 -->
% 20.23/19.75 (bnd_c3_1 X212 | bnd_c10_1 X212) | ~ bnd_c7_1 X212) |
% 20.23/19.75 bnd_c8_0) |
% 20.23/19.75 ~ bnd_c5_0)) &
% 20.23/19.75 (((ALL X213.
% 20.23/19.75 bnd_ndr1_0 -->
% 20.23/19.75 (~ bnd_c7_1 X213 | bnd_c4_1 X213) |
% 20.23/19.75 ((bnd_ndr1_1 X213 & bnd_c4_2 X213 bnd_a1172) &
% 20.23/19.75 bnd_c1_2 X213 bnd_a1172) &
% 20.23/19.75 bnd_c10_2 X213 bnd_a1172) |
% 20.23/19.75 ~ bnd_c2_0) |
% 20.23/19.75 ((((bnd_ndr1_0 & bnd_c3_1 bnd_a1173) &
% 20.23/19.75 (ALL X214.
% 20.23/19.75 bnd_ndr1_1 bnd_a1173 -->
% 20.23/19.75 (bnd_c5_2 bnd_a1173 X214 | bnd_c4_2 bnd_a1173 X214) |
% 20.23/19.75 ~ bnd_c9_2 bnd_a1173 X214)) &
% 20.23/19.75 bnd_ndr1_1 bnd_a1173) &
% 20.23/19.75 bnd_c4_2 bnd_a1173 bnd_a1174) &
% 20.23/19.75 ~ bnd_c5_2 bnd_a1173 bnd_a1174)) &
% 20.23/19.75 ((~ bnd_c3_0 | bnd_c7_0) |
% 20.23/19.75 (ALL X215.
% 20.23/19.75 bnd_ndr1_0 -->
% 20.23/19.75 (bnd_ndr1_1 X215 & ~ bnd_c7_2 X215 bnd_a1175 |
% 20.23/19.75 ~ bnd_c5_1 X215) |
% 20.23/19.75 (ALL X216.
% 20.23/19.75 bnd_ndr1_1 X215 -->
% 20.23/19.75 (~ bnd_c3_2 X215 X216 | bnd_c5_2 X215 X216) |
% 20.23/19.75 bnd_c6_2 X215 X216)))) &
% 20.23/19.75 (bnd_c1_0 | ~ bnd_c7_0)) &
% 20.23/19.75 (((ALL X217.
% 20.23/19.75 bnd_ndr1_0 -->
% 20.23/19.75 ((ALL X218.
% 20.23/19.75 bnd_ndr1_1 X217 -->
% 20.23/19.75 (bnd_c3_2 X217 X218 | bnd_c4_2 X217 X218) |
% 20.23/19.75 bnd_c7_2 X217 X218) |
% 20.23/19.75 bnd_c9_1 X217) |
% 20.23/19.75 ((bnd_ndr1_1 X217 & bnd_c6_2 X217 bnd_a1176) &
% 20.23/19.75 bnd_c7_2 X217 bnd_a1176) &
% 20.23/19.75 ~ bnd_c1_2 X217 bnd_a1176) |
% 20.23/19.75 (ALL X219.
% 20.23/19.75 bnd_ndr1_0 -->
% 20.23/19.75 (~ bnd_c1_1 X219 |
% 20.23/19.75 ((bnd_ndr1_1 X219 & bnd_c9_2 X219 bnd_a1177) &
% 20.23/19.75 bnd_c8_2 X219 bnd_a1177) &
% 20.23/19.75 bnd_c6_2 X219 bnd_a1177) |
% 20.23/19.75 ((bnd_ndr1_1 X219 & ~ bnd_c4_2 X219 bnd_a1178) &
% 20.23/19.75 bnd_c2_2 X219 bnd_a1178) &
% 20.23/19.75 bnd_c1_2 X219 bnd_a1178)) |
% 20.23/19.75 (ALL X220.
% 20.23/19.75 bnd_ndr1_0 -->
% 20.23/19.75 (((bnd_ndr1_1 X220 & ~ bnd_c2_2 X220 bnd_a1179) &
% 20.23/19.75 bnd_c8_2 X220 bnd_a1179) &
% 20.23/19.75 ~ bnd_c1_2 X220 bnd_a1179 |
% 20.23/19.75 ((bnd_ndr1_1 X220 & bnd_c10_2 X220 bnd_a1180) &
% 20.23/19.75 ~ bnd_c5_2 X220 bnd_a1180) &
% 20.23/19.75 ~ bnd_c1_2 X220 bnd_a1180) |
% 20.23/19.75 bnd_c5_1 X220))) &
% 20.23/19.75 (((ALL X221.
% 20.23/19.75 bnd_ndr1_0 -->
% 20.23/19.75 ((ALL X222.
% 20.23/19.75 bnd_ndr1_1 X221 -->
% 20.23/19.75 (bnd_c10_2 X221 X222 | bnd_c1_2 X221 X222) |
% 20.23/19.75 ~ bnd_c8_2 X221 X222) |
% 20.23/19.75 ((bnd_ndr1_1 X221 & bnd_c9_2 X221 bnd_a1181) &
% 20.23/19.75 ~ bnd_c1_2 X221 bnd_a1181) &
% 20.23/19.75 bnd_c3_2 X221 bnd_a1181) |
% 20.23/19.75 ((bnd_ndr1_1 X221 & bnd_c8_2 X221 bnd_a1182) &
% 20.23/19.75 ~ bnd_c9_2 X221 bnd_a1182) &
% 20.23/19.75 ~ bnd_c4_2 X221 bnd_a1182) |
% 20.23/19.75 ((((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a1183) &
% 20.23/19.75 ~ bnd_c9_2 bnd_a1183 bnd_a1184) &
% 20.23/19.75 bnd_c8_2 bnd_a1183 bnd_a1184) &
% 20.23/19.75 bnd_c3_2 bnd_a1183 bnd_a1184) &
% 20.23/19.75 ~ bnd_c10_1 bnd_a1183) &
% 20.23/19.75 bnd_ndr1_1 bnd_a1183) &
% 20.23/19.75 bnd_c5_2 bnd_a1183 bnd_a1185) &
% 20.23/19.75 bnd_c10_2 bnd_a1183 bnd_a1185) &
% 20.23/19.75 ~ bnd_c7_2 bnd_a1183 bnd_a1185) |
% 20.23/19.75 (ALL X223.
% 20.23/19.75 bnd_ndr1_0 -->
% 20.23/19.75 ~ bnd_c10_1 X223 |
% 20.23/19.75 (ALL X224.
% 20.23/19.75 bnd_ndr1_1 X223 -->
% 20.23/19.75 bnd_c8_2 X223 X224 | bnd_c1_2 X223 X224)))) &
% 20.23/19.75 (((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a1186) &
% 20.23/19.75 bnd_c3_2 bnd_a1186 bnd_a1187) &
% 20.23/19.75 ~ bnd_c6_2 bnd_a1186 bnd_a1187) &
% 20.23/19.75 bnd_ndr1_1 bnd_a1186) &
% 20.23/19.75 ~ bnd_c1_2 bnd_a1186 bnd_a1188) &
% 20.23/19.75 bnd_c3_2 bnd_a1186 bnd_a1188) &
% 20.23/19.75 bnd_c3_1 bnd_a1186 |
% 20.23/19.75 bnd_c2_0)) &
% 20.23/19.75 ((~ bnd_c6_0 | bnd_c1_0) |
% 20.23/19.75 (ALL X225.
% 20.23/19.75 bnd_ndr1_0 -->
% 20.23/19.75 (~ bnd_c9_1 X225 |
% 20.23/19.75 (ALL X226.
% 20.23/19.75 bnd_ndr1_1 X225 -->
% 20.23/19.75 (bnd_c3_2 X225 X226 | ~ bnd_c1_2 X225 X226) |
% 20.23/19.75 bnd_c5_2 X225 X226)) |
% 20.23/19.75 ((bnd_ndr1_1 X225 & bnd_c1_2 X225 bnd_a1189) &
% 20.23/19.75 ~ bnd_c6_2 X225 bnd_a1189) &
% 20.23/19.75 bnd_c2_2 X225 bnd_a1189)))
% 20.23/19.75 Adding axioms...
% 20.23/19.76 Typedef.type_definition_def
% 60.47/59.90 ...done.
% 60.47/59.95 Ground types: ?'b, TPTP_Interpret.ind
% 60.47/59.95 Translating term (sizes: 1, 1) ...
% 93.25/92.60 Invoking SAT solver...
% 93.25/92.61 No model exists.
% 93.25/92.61 Translating term (sizes: 2, 1) ...
% 126.73/126.03 Invoking SAT solver...
% 126.73/126.04 No model exists.
% 126.73/126.04 Translating term (sizes: 1, 2) ...
% 187.80/186.90 Invoking SAT solver...
% 192.45/191.43 Model found:
% 192.45/191.43 Size of types: ?'b: 1, TPTP_Interpret.ind: 2
% 192.45/191.43 bnd_a1189: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1188: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1187: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1186: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1185: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1184: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1183: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1182: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1181: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1180: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1179: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1178: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1177: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1176: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1175: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1174: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1173: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1172: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1171: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1170: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1169: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1168: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1167: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1166: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1165: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1164: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1163: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1162: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1161: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1160: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1159: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1158: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1157: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1156: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1155: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1154: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1153: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1152: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1151: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1150: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1149: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1148: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1147: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1146: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1145: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1144: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1143: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1142: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1141: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1140: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1139: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1138: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1137: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1136: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1135: ??.TPTP_Interpret.ind1
% 192.45/191.43 bnd_a1134: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1133: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1132: ??.TPTP_Interpret.ind1
% 192.45/191.43 bnd_a1131: ??.TPTP_Interpret.ind1
% 192.45/191.43 bnd_a1130: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1129: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1128: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1127: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1126: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1125: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1124: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1123: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1122: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1121: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1120: ??.TPTP_Interpret.ind1
% 192.45/191.43 bnd_a1119: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1118: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1117: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1116: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1115: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1114: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1113: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1112: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1111: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1110: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1109: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1108: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1107: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1106: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1105: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1104: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1103: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1102: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1101: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1100: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1099: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1098: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1097: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1096: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1095: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1094: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1093: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1092: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1091: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1090: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1089: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1088: ??.TPTP_Interpret.ind1
% 192.45/191.43 bnd_a1087: ??.TPTP_Interpret.ind1
% 192.45/191.43 bnd_a1086: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1085: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1084: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1083: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1082: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1081: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1080: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1079: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1078: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1077: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1076: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1075: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1074: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1073: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1072: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1071: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1070: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1069: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1068: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1067: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1066: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1065: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1064: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1063: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1062: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1061: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1060: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1059: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1058: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1057: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1056: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1055: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1054: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1053: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1052: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1051: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1050: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1049: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1048: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1047: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1046: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1045: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1044: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1043: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1042: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1041: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1040: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1039: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1038: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1037: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1036: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1035: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1034: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1033: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1032: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1031: ??.TPTP_Interpret.ind1
% 192.45/191.43 bnd_a1030: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1029: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1028: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1027: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1026: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1025: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1024: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1023: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1022: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1021: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1020: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1019: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1018: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1017: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1016: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1015: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1014: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1013: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1012: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1011: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1010: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1009: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1008: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1007: ??.TPTP_Interpret.ind1
% 192.45/191.43 bnd_a1006: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1005: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1004: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1003: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1002: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1001: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a1000: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a999: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a998: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a997: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a996: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a995: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a994: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a993: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a992: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a991: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a990: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a989: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a988: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a987: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a986: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_c10_1: {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, True)}
% 192.45/191.43 bnd_a985: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_c10_0: False
% 192.45/191.43 bnd_a984: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a983: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a982: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a981: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a980: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_c4_0: True
% 192.45/191.43 bnd_a979: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_c8_1: {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, False)}
% 192.45/191.43 bnd_a978: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_c1_0: True
% 192.45/191.43 bnd_a977: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a976: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a975: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a974: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_c8_0: False
% 192.45/191.43 bnd_a973: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_c1_1: {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, False)}
% 192.45/191.43 bnd_a972: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_c7_1: {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, True)}
% 192.45/191.43 bnd_a971: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_c2_1: {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, False)}
% 192.45/191.43 bnd_c5_1: {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, True)}
% 192.45/191.43 bnd_a970: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a969: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_c6_0: False
% 192.45/191.43 bnd_a968: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a967: ??.TPTP_Interpret.ind1
% 192.45/191.43 bnd_c3_1: {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, False)}
% 192.45/191.43 bnd_c7_0: False
% 192.45/191.43 bnd_c4_1: {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, True)}
% 192.45/191.43 bnd_a966: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_c9_1: {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, True)}
% 192.45/191.43 bnd_c9_0: True
% 192.45/191.43 bnd_a965: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_c6_2: {(??.TPTP_Interpret.ind0,
% 192.45/191.43 {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, True)}),
% 192.45/191.43 (??.TPTP_Interpret.ind1,
% 192.45/191.43 {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, False)})}
% 192.45/191.43 bnd_c2_2: {(??.TPTP_Interpret.ind0,
% 192.45/191.43 {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, False)}),
% 192.45/191.43 (??.TPTP_Interpret.ind1,
% 192.45/191.43 {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, True)})}
% 192.45/191.43 bnd_c3_0: False
% 192.45/191.43 bnd_c2_0: True
% 192.45/191.43 bnd_c4_2: {(??.TPTP_Interpret.ind0,
% 192.45/191.43 {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, True)}),
% 192.45/191.43 (??.TPTP_Interpret.ind1,
% 192.45/191.43 {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, False)})}
% 192.45/191.43 bnd_a964: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_a963: ??.TPTP_Interpret.ind1
% 192.45/191.43 bnd_c5_0: False
% 192.45/191.43 bnd_c9_2: {(??.TPTP_Interpret.ind0,
% 192.45/191.43 {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, False)}),
% 192.45/191.43 (??.TPTP_Interpret.ind1,
% 192.45/191.43 {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, True)})}
% 192.45/191.43 bnd_c3_2: {(??.TPTP_Interpret.ind0,
% 192.45/191.43 {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, True)}),
% 192.45/191.43 (??.TPTP_Interpret.ind1,
% 192.45/191.43 {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, True)})}
% 192.45/191.43 bnd_c8_2: {(??.TPTP_Interpret.ind0,
% 192.45/191.43 {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, True)}),
% 192.45/191.43 (??.TPTP_Interpret.ind1,
% 192.45/191.43 {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, False)})}
% 192.45/191.43 bnd_c7_2: {(??.TPTP_Interpret.ind0,
% 192.45/191.43 {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, False)}),
% 192.45/191.43 (??.TPTP_Interpret.ind1,
% 192.45/191.43 {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, False)})}
% 192.45/191.43 bnd_a962: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_c6_1: {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, False)}
% 192.45/191.43 bnd_c5_2: {(??.TPTP_Interpret.ind0,
% 192.45/191.43 {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, False)}),
% 192.45/191.43 (??.TPTP_Interpret.ind1,
% 192.45/191.43 {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, False)})}
% 192.45/191.43 bnd_c1_2: {(??.TPTP_Interpret.ind0,
% 192.45/191.43 {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, False)}),
% 192.45/191.43 (??.TPTP_Interpret.ind1,
% 192.45/191.43 {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, False)})}
% 192.45/191.43 bnd_a961: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_c10_2: {(??.TPTP_Interpret.ind0,
% 192.45/191.43 {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, True)}),
% 192.45/191.43 (??.TPTP_Interpret.ind1,
% 192.45/191.43 {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, False)})}
% 192.45/191.43 bnd_a960: ??.TPTP_Interpret.ind0
% 192.45/191.43 bnd_ndr1_1: {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, True)}
% 192.45/191.43 bnd_ndr1_0: True
% 192.45/191.43
% 192.45/191.43 % SZS status CounterSatisfiable
%------------------------------------------------------------------------------