TSTP Solution File: SYN422+1 by Refute---2015
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%------------------------------------------------------------------------------
% File : Refute---2015
% Problem : SYN422+1 : TPTP v6.4.0. Released v2.1.0.
% Transfm : none
% Format : tptp:raw
% Command : isabelle tptp_refute %d %s
% Computer : n136.star.cs.uiowa.edu
% Model : x86_64 x86_64
% CPU : Intel(R) Xeon(R) CPU E5-2609 0 2.40GHz
% Memory : 32218.75MB
% OS : Linux 3.10.0-327.10.1.el7.x86_64
% CPULimit : 300s
% DateTime : Thu Apr 14 06:41:42 EDT 2016
% Result : CounterSatisfiable 130.58s
% Output : Assurance 0s
% Verified :
% SZS Type : None (Parsing solution fails)
% Syntax : Number of formulae : 0
% Comments :
%------------------------------------------------------------------------------
%----No solution output by system
%------------------------------------------------------------------------------
%----ORIGINAL SYSTEM OUTPUT
% 0.00/0.03 % Problem : SYN422+1 : TPTP v6.4.0. Released v2.1.0.
% 0.00/0.04 % Command : isabelle tptp_refute %d %s
% 0.02/0.23 % Computer : n136.star.cs.uiowa.edu
% 0.02/0.23 % Model : x86_64 x86_64
% 0.02/0.23 % CPU : Intel(R) Xeon(R) CPU E5-2609 0 @ 2.40GHz
% 0.02/0.23 % Memory : 32218.75MB
% 0.02/0.23 % OS : Linux 3.10.0-327.10.1.el7.x86_64
% 0.02/0.23 % CPULimit : 300
% 0.02/0.23 % DateTime : Fri Apr 8 23:49:54 CDT 2016
% 0.02/0.23 % CPUTime:
% 6.31/5.82 > val it = (): unit
% 7.12/6.62 Trying to find a model that refutes: ~ ((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((bnd_c9_0 |
% 7.12/6.62 ((bnd_ndr1_0 & ~ bnd_c9_1 bnd_a608) &
% 7.12/6.62 ~ bnd_c10_1 bnd_a608) &
% 7.12/6.62 ~ bnd_c4_1 bnd_a608) |
% 7.12/6.62 bnd_c1_0) &
% 7.12/6.62 ((((bnd_ndr1_0 & ~ bnd_c5_1 bnd_a609) &
% 7.12/6.62 ~ bnd_c10_1 bnd_a609) &
% 7.12/6.62 ~ bnd_c8_1 bnd_a609 |
% 7.12/6.62 ~ bnd_c8_0) |
% 7.12/6.62 (ALL U.
% 7.12/6.62 bnd_ndr1_0 -->
% 7.12/6.62 ((ALL V.
% 7.12/6.62 bnd_ndr1_1 U -->
% 7.12/6.62 (~ bnd_c5_2 U V | ~ bnd_c2_2 U V) |
% 7.12/6.62 ~ bnd_c4_2 U V) |
% 7.12/6.62 ((bnd_ndr1_1 U & bnd_c3_2 U bnd_a610) &
% 7.12/6.62 bnd_c4_2 U bnd_a610) &
% 7.12/6.62 bnd_c9_2 U bnd_a610) |
% 7.12/6.62 (ALL W.
% 7.12/6.62 bnd_ndr1_1 U -->
% 7.12/6.62 (bnd_c9_2 U W | bnd_c6_2 U W) |
% 7.12/6.62 ~ bnd_c1_2 U W)))) &
% 7.12/6.62 (((((((bnd_ndr1_0 & bnd_c3_1 bnd_a611) &
% 7.12/6.62 (ALL X.
% 7.12/6.62 bnd_ndr1_1 bnd_a611 -->
% 7.12/6.62 bnd_c3_2 bnd_a611 X | ~ bnd_c8_2 bnd_a611 X)) &
% 7.12/6.62 bnd_ndr1_1 bnd_a611) &
% 7.12/6.62 ~ bnd_c1_2 bnd_a611 bnd_a612) &
% 7.12/6.62 ~ bnd_c9_2 bnd_a611 bnd_a612) &
% 7.12/6.62 ~ bnd_c8_2 bnd_a611 bnd_a612 |
% 7.12/6.62 (ALL Y.
% 7.12/6.62 bnd_ndr1_0 -->
% 7.12/6.62 (bnd_c2_1 Y | bnd_c10_1 Y) |
% 7.12/6.62 (bnd_ndr1_1 Y & bnd_c9_2 Y bnd_a613) &
% 7.12/6.62 ~ bnd_c2_2 Y bnd_a613)) |
% 7.12/6.62 ~ bnd_c5_0)) &
% 7.12/6.62 ((bnd_c9_0 |
% 7.12/6.62 (((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a614) &
% 7.12/6.62 bnd_c3_2 bnd_a614 bnd_a615) &
% 7.12/6.62 ~ bnd_c5_2 bnd_a614 bnd_a615) &
% 7.12/6.62 bnd_ndr1_1 bnd_a614) &
% 7.12/6.62 bnd_c9_2 bnd_a614 bnd_a616) &
% 7.12/6.62 bnd_c10_2 bnd_a614 bnd_a616) &
% 7.12/6.62 ~ bnd_c1_2 bnd_a614 bnd_a616) &
% 7.12/6.62 (ALL Z.
% 7.12/6.62 bnd_ndr1_1 bnd_a614 -->
% 7.12/6.62 bnd_c9_2 bnd_a614 Z | bnd_c7_2 bnd_a614 Z)) |
% 7.12/6.62 ~ bnd_c2_0)) &
% 7.12/6.62 ((((bnd_ndr1_0 & bnd_c5_1 bnd_a617) & bnd_c9_1 bnd_a617) &
% 7.12/6.62 ~ bnd_c10_1 bnd_a617 |
% 7.12/6.62 ~ bnd_c3_0) |
% 7.12/6.62 ((bnd_ndr1_0 &
% 7.12/6.62 (ALL X1.
% 7.12/6.62 bnd_ndr1_1 bnd_a618 -->
% 7.12/6.62 (~ bnd_c9_2 bnd_a618 X1 | ~ bnd_c8_2 bnd_a618 X1) |
% 7.12/6.62 bnd_c4_2 bnd_a618 X1)) &
% 7.12/6.62 (ALL X2.
% 7.12/6.62 bnd_ndr1_1 bnd_a618 -->
% 7.12/6.62 (bnd_c6_2 bnd_a618 X2 | ~ bnd_c10_2 bnd_a618 X2) |
% 7.12/6.62 bnd_c8_2 bnd_a618 X2)) &
% 7.12/6.62 bnd_c3_1 bnd_a618)) &
% 7.12/6.62 ((bnd_c3_0 |
% 7.12/6.62 (ALL X3.
% 7.12/6.62 bnd_ndr1_0 -->
% 7.12/6.62 ((ALL X4.
% 7.12/6.62 bnd_ndr1_1 X3 -->
% 7.12/6.62 ~ bnd_c9_2 X3 X4 | bnd_c4_2 X3 X4) |
% 7.12/6.62 bnd_c7_1 X3) |
% 7.12/6.62 (bnd_ndr1_1 X3 & ~ bnd_c3_2 X3 bnd_a619) &
% 7.12/6.62 bnd_c7_2 X3 bnd_a619)) |
% 7.12/6.62 (ALL X5.
% 7.12/6.62 bnd_ndr1_0 -->
% 7.12/6.62 (~ bnd_c9_1 X5 | ~ bnd_c5_1 X5) | bnd_c2_1 X5))) &
% 7.12/6.62 (((ALL X6.
% 7.12/6.62 bnd_ndr1_0 -->
% 7.12/6.62 (ALL X7.
% 7.12/6.62 bnd_ndr1_1 X6 -->
% 7.12/6.62 (bnd_c1_2 X6 X7 | ~ bnd_c3_2 X6 X7) |
% 7.12/6.62 bnd_c6_2 X6 X7) |
% 7.12/6.62 ((bnd_ndr1_1 X6 & ~ bnd_c4_2 X6 bnd_a620) &
% 7.12/6.62 bnd_c1_2 X6 bnd_a620) &
% 7.12/6.62 bnd_c5_2 X6 bnd_a620) |
% 7.12/6.62 bnd_c9_0) |
% 7.12/6.62 (ALL X8.
% 7.12/6.62 bnd_ndr1_0 -->
% 7.12/6.62 ((ALL X9.
% 7.12/6.62 bnd_ndr1_1 X8 -->
% 7.12/6.62 (bnd_c9_2 X8 X9 | ~ bnd_c3_2 X8 X9) |
% 7.12/6.62 ~ bnd_c10_2 X8 X9) |
% 7.12/6.62 ~ bnd_c5_1 X8) |
% 7.12/6.62 (ALL X10.
% 7.12/6.62 bnd_ndr1_1 X8 -->
% 7.12/6.62 (~ bnd_c6_2 X8 X10 | bnd_c7_2 X8 X10) |
% 7.12/6.62 ~ bnd_c4_2 X8 X10)))) &
% 7.12/6.62 ((~ bnd_c9_0 | ~ bnd_c5_0) |
% 7.12/6.62 (ALL X11.
% 7.12/6.62 bnd_ndr1_0 -->
% 7.12/6.62 (~ bnd_c8_1 X11 | ~ bnd_c3_1 X11) | bnd_c1_1 X11))) &
% 7.12/6.62 ((((bnd_ndr1_0 & ~ bnd_c3_1 bnd_a621) & bnd_c1_1 bnd_a621) &
% 7.12/6.62 (ALL X12.
% 7.12/6.62 bnd_ndr1_1 bnd_a621 -->
% 7.12/6.62 (~ bnd_c2_2 bnd_a621 X12 | bnd_c1_2 bnd_a621 X12) |
% 7.12/6.62 bnd_c6_2 bnd_a621 X12) |
% 7.12/6.62 ~ bnd_c9_0) |
% 7.12/6.62 (((((bnd_ndr1_0 & bnd_c4_1 bnd_a622) & ~ bnd_c8_1 bnd_a622) &
% 7.12/6.62 bnd_ndr1_1 bnd_a622) &
% 7.12/6.62 bnd_c6_2 bnd_a622 bnd_a623) &
% 7.12/6.62 bnd_c1_2 bnd_a622 bnd_a623) &
% 7.12/6.62 bnd_c2_2 bnd_a622 bnd_a623)) &
% 7.12/6.62 (((ALL X13.
% 7.12/6.62 bnd_ndr1_0 -->
% 7.12/6.62 ((bnd_ndr1_1 X13 & bnd_c5_2 X13 bnd_a624) &
% 7.12/6.62 ~ bnd_c9_2 X13 bnd_a624 |
% 7.12/6.62 bnd_c4_1 X13) |
% 7.12/6.62 bnd_c2_1 X13) |
% 7.12/6.62 bnd_c8_0) |
% 7.12/6.62 ((((bnd_ndr1_0 & bnd_c1_1 bnd_a625) & bnd_ndr1_1 bnd_a625) &
% 7.12/6.62 bnd_c3_2 bnd_a625 bnd_a626) &
% 7.12/6.62 bnd_c6_2 bnd_a625 bnd_a626) &
% 7.12/6.62 bnd_c3_1 bnd_a625)) &
% 7.12/6.62 (((ALL X14.
% 7.12/6.62 bnd_ndr1_0 -->
% 7.12/6.62 (~ bnd_c8_1 X14 |
% 7.12/6.62 ((bnd_ndr1_1 X14 & ~ bnd_c10_2 X14 bnd_a627) &
% 7.12/6.62 ~ bnd_c5_2 X14 bnd_a627) &
% 7.12/6.62 ~ bnd_c2_2 X14 bnd_a627) |
% 7.12/6.62 ~ bnd_c7_1 X14) |
% 7.12/6.62 ~ bnd_c7_0) |
% 7.12/6.62 (((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a628) &
% 7.12/6.62 ~ bnd_c5_2 bnd_a628 bnd_a629) &
% 7.12/6.62 ~ bnd_c8_2 bnd_a628 bnd_a629) &
% 7.12/6.62 bnd_c3_2 bnd_a628 bnd_a629) &
% 7.12/6.62 bnd_c1_1 bnd_a628) &
% 7.12/6.62 ~ bnd_c7_1 bnd_a628)) &
% 7.12/6.62 ((bnd_c8_0 |
% 7.12/6.62 ((bnd_ndr1_0 & bnd_c7_1 bnd_a630) & ~ bnd_c6_1 bnd_a630) &
% 7.12/6.62 bnd_c9_1 bnd_a630) |
% 7.12/6.62 bnd_c2_0)) &
% 7.12/6.62 ((bnd_c9_0 | ~ bnd_c5_0) | ~ bnd_c6_0)) &
% 7.12/6.62 ((bnd_c7_0 | bnd_c2_0) |
% 7.12/6.62 (ALL X15.
% 7.12/6.62 bnd_ndr1_0 -->
% 7.12/6.62 (bnd_c10_1 X15 |
% 7.12/6.62 (ALL X16.
% 7.12/6.62 bnd_ndr1_1 X15 -->
% 7.12/6.62 (~ bnd_c3_2 X15 X16 | bnd_c5_2 X15 X16) |
% 7.12/6.62 ~ bnd_c6_2 X15 X16)) |
% 7.12/6.62 bnd_c3_1 X15))) &
% 7.12/6.62 (((((((bnd_ndr1_0 &
% 7.12/6.62 (ALL X17.
% 7.12/6.62 bnd_ndr1_1 bnd_a631 -->
% 7.12/6.62 (~ bnd_c1_2 bnd_a631 X17 | ~ bnd_c6_2 bnd_a631 X17) |
% 7.12/6.62 bnd_c7_2 bnd_a631 X17)) &
% 7.12/6.62 bnd_ndr1_1 bnd_a631) &
% 7.12/6.62 bnd_c10_2 bnd_a631 bnd_a632) &
% 7.12/6.62 bnd_c8_2 bnd_a631 bnd_a632) &
% 7.12/6.62 ~ bnd_c2_2 bnd_a631 bnd_a632) &
% 7.12/6.62 bnd_c5_1 bnd_a631 |
% 7.12/6.62 ((((bnd_ndr1_0 & bnd_c10_1 bnd_a633) & bnd_ndr1_1 bnd_a633) &
% 7.12/6.62 bnd_c9_2 bnd_a633 bnd_a634) &
% 7.12/6.62 ~ bnd_c10_2 bnd_a633 bnd_a634) &
% 7.12/6.62 ~ bnd_c2_1 bnd_a633) |
% 7.12/6.62 (ALL X18.
% 7.12/6.62 bnd_ndr1_0 -->
% 7.12/6.62 ((ALL X19.
% 7.12/6.62 bnd_ndr1_1 X18 -->
% 7.12/6.62 (~ bnd_c8_2 X18 X19 | bnd_c4_2 X18 X19) |
% 7.12/6.62 bnd_c1_2 X18 X19) |
% 7.12/6.62 ~ bnd_c6_1 X18) |
% 7.12/6.62 ~ bnd_c8_1 X18))) &
% 7.12/6.62 (((ALL X20.
% 7.12/6.62 bnd_ndr1_0 -->
% 7.12/6.62 ((ALL X21.
% 7.12/6.62 bnd_ndr1_1 X20 -->
% 7.12/6.62 (bnd_c2_2 X20 X21 | ~ bnd_c9_2 X20 X21) |
% 7.12/6.62 ~ bnd_c8_2 X20 X21) |
% 7.12/6.62 ~ bnd_c4_1 X20) |
% 7.12/6.62 ~ bnd_c3_1 X20) |
% 7.12/6.62 (ALL X22.
% 7.12/6.62 bnd_ndr1_0 -->
% 7.12/6.62 (((bnd_ndr1_1 X22 & bnd_c8_2 X22 bnd_a635) &
% 7.12/6.62 bnd_c3_2 X22 bnd_a635) &
% 7.12/6.62 ~ bnd_c2_2 X22 bnd_a635 |
% 7.12/6.62 ((bnd_ndr1_1 X22 & ~ bnd_c4_2 X22 bnd_a636) &
% 7.12/6.62 bnd_c10_2 X22 bnd_a636) &
% 7.12/6.62 bnd_c8_2 X22 bnd_a636) |
% 7.12/6.62 (ALL X23.
% 7.12/6.62 bnd_ndr1_1 X22 -->
% 7.12/6.62 (~ bnd_c10_2 X22 X23 | bnd_c5_2 X22 X23) |
% 7.12/6.62 bnd_c8_2 X22 X23))) |
% 7.12/6.62 bnd_c3_0)) &
% 7.12/6.62 (((ALL X24.
% 7.12/6.62 bnd_ndr1_0 -->
% 7.12/6.62 (~ bnd_c4_1 X24 | ~ bnd_c5_1 X24) | ~ bnd_c6_1 X24) |
% 7.12/6.62 ((bnd_ndr1_0 & bnd_c8_1 bnd_a637) & bnd_c5_1 bnd_a637) &
% 7.12/6.62 bnd_c3_1 bnd_a637) |
% 7.12/6.62 ~ bnd_c2_0)) &
% 7.12/6.62 ((bnd_c8_0 | ~ bnd_c2_0) |
% 7.12/6.62 (ALL X25.
% 7.12/6.62 bnd_ndr1_0 -->
% 7.12/6.62 (~ bnd_c1_1 X25 |
% 7.12/6.62 (ALL X26.
% 7.12/6.62 bnd_ndr1_1 X25 --> bnd_c6_2 X25 X26 | ~ bnd_c3_2 X25 X26)) |
% 7.12/6.62 (bnd_ndr1_1 X25 & ~ bnd_c2_2 X25 bnd_a638) &
% 7.12/6.62 bnd_c1_2 X25 bnd_a638))) &
% 7.12/6.62 (bnd_c2_0 | bnd_c9_0)) &
% 7.12/6.62 ((bnd_c5_0 | bnd_c8_0) |
% 7.12/6.62 (ALL X27.
% 7.12/6.62 bnd_ndr1_0 -->
% 7.12/6.62 ((ALL X28.
% 7.12/6.62 bnd_ndr1_1 X27 -->
% 7.12/6.62 (~ bnd_c8_2 X27 X28 | ~ bnd_c9_2 X27 X28) |
% 7.12/6.62 ~ bnd_c1_2 X27 X28) |
% 7.12/6.62 ~ bnd_c3_1 X27) |
% 7.12/6.62 (ALL X29.
% 7.12/6.62 bnd_ndr1_1 X27 --> bnd_c7_2 X27 X29 | ~ bnd_c10_2 X27 X29)))) &
% 7.12/6.62 ((bnd_c2_0 |
% 7.12/6.62 (ALL X30.
% 7.12/6.62 bnd_ndr1_0 -->
% 7.12/6.62 (bnd_c10_1 X30 |
% 7.12/6.62 (ALL X31.
% 7.12/6.62 bnd_ndr1_1 X30 -->
% 7.12/6.62 (~ bnd_c3_2 X30 X31 | ~ bnd_c6_2 X30 X31) |
% 7.12/6.62 ~ bnd_c8_2 X30 X31)) |
% 7.12/6.62 (ALL X32.
% 7.12/6.62 bnd_ndr1_1 X30 -->
% 7.12/6.62 (~ bnd_c10_2 X30 X32 | ~ bnd_c3_2 X30 X32) |
% 7.12/6.62 ~ bnd_c9_2 X30 X32))) |
% 7.12/6.62 (((((bnd_ndr1_0 & ~ bnd_c2_1 bnd_a639) & ~ bnd_c8_1 bnd_a639) &
% 7.12/6.62 bnd_ndr1_1 bnd_a639) &
% 7.12/6.62 ~ bnd_c3_2 bnd_a639 bnd_a640) &
% 7.12/6.62 bnd_c8_2 bnd_a639 bnd_a640) &
% 7.12/6.62 ~ bnd_c1_2 bnd_a639 bnd_a640)) &
% 7.12/6.62 ((((((((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a641) &
% 7.12/6.62 bnd_c8_2 bnd_a641 bnd_a642) &
% 7.12/6.62 bnd_c6_2 bnd_a641 bnd_a642) &
% 7.12/6.62 bnd_c2_2 bnd_a641 bnd_a642) &
% 7.12/6.62 bnd_ndr1_1 bnd_a641) &
% 7.12/6.62 ~ bnd_c5_2 bnd_a641 bnd_a643) &
% 7.12/6.62 ~ bnd_c8_2 bnd_a641 bnd_a643) &
% 7.12/6.62 bnd_ndr1_1 bnd_a641) &
% 7.12/6.62 ~ bnd_c8_2 bnd_a641 bnd_a644) &
% 7.12/6.62 ~ bnd_c5_2 bnd_a641 bnd_a644) &
% 7.12/6.62 ~ bnd_c9_2 bnd_a641 bnd_a644 |
% 7.12/6.62 ((((((((bnd_ndr1_0 &
% 7.12/6.62 (ALL X33.
% 7.12/6.62 bnd_ndr1_1 bnd_a645 -->
% 7.12/6.62 (~ bnd_c2_2 bnd_a645 X33 | ~ bnd_c5_2 bnd_a645 X33) |
% 7.12/6.62 ~ bnd_c9_2 bnd_a645 X33)) &
% 7.12/6.62 bnd_ndr1_1 bnd_a645) &
% 7.12/6.62 ~ bnd_c9_2 bnd_a645 bnd_a646) &
% 7.12/6.62 ~ bnd_c3_2 bnd_a645 bnd_a646) &
% 7.12/6.62 ~ bnd_c5_2 bnd_a645 bnd_a646) &
% 7.12/6.62 bnd_ndr1_1 bnd_a645) &
% 7.12/6.62 ~ bnd_c9_2 bnd_a645 bnd_a647) &
% 7.12/6.62 ~ bnd_c3_2 bnd_a645 bnd_a647) &
% 7.12/6.62 bnd_c5_2 bnd_a645 bnd_a647) |
% 7.12/6.62 bnd_c10_0)) &
% 7.12/6.62 ((((bnd_ndr1_0 &
% 7.12/6.62 (ALL X34.
% 7.12/6.62 bnd_ndr1_1 bnd_a648 -->
% 7.12/6.62 ~ bnd_c7_2 bnd_a648 X34 | ~ bnd_c3_2 bnd_a648 X34)) &
% 7.12/6.62 ~ bnd_c7_1 bnd_a648) &
% 7.12/6.62 bnd_c3_1 bnd_a648 |
% 7.12/6.62 (ALL X35.
% 7.12/6.62 bnd_ndr1_0 -->
% 7.12/6.62 (~ bnd_c9_1 X35 | bnd_c2_1 X35) |
% 7.12/6.62 (ALL X36.
% 7.12/6.62 bnd_ndr1_1 X35 -->
% 7.12/6.62 (~ bnd_c10_2 X35 X36 | bnd_c5_2 X35 X36) | bnd_c2_2 X35 X36))) |
% 7.12/6.62 bnd_c6_0)) &
% 7.12/6.62 ((((bnd_ndr1_0 & ~ bnd_c1_1 bnd_a649) &
% 7.12/6.62 bnd_c9_1 bnd_a649) &
% 7.12/6.62 ~ bnd_c8_1 bnd_a649 |
% 7.12/6.62 (ALL X37.
% 7.12/6.62 bnd_ndr1_0 -->
% 7.12/6.62 (((bnd_ndr1_1 X37 & bnd_c7_2 X37 bnd_a650) & bnd_c1_2 X37 bnd_a650) &
% 7.12/6.62 bnd_c5_2 X37 bnd_a650 |
% 7.12/6.62 ~ bnd_c1_1 X37) |
% 7.12/6.62 bnd_c7_1 X37)) |
% 7.12/6.62 ~ bnd_c5_0)) &
% 7.12/6.62 ((((bnd_ndr1_0 & ~ bnd_c5_1 bnd_a651) &
% 7.12/6.62 ~ bnd_c9_1 bnd_a651) &
% 7.12/6.62 ~ bnd_c7_1 bnd_a651 |
% 7.12/6.62 (((((bnd_ndr1_0 &
% 7.12/6.62 ~ bnd_c2_1 bnd_a652) &
% 7.12/6.62 bnd_ndr1_1 bnd_a652) &
% 7.12/6.62 bnd_c1_2 bnd_a652 bnd_a653) &
% 7.12/6.62 ~ bnd_c5_2 bnd_a652 bnd_a653) &
% 7.12/6.62 ~ bnd_c10_2 bnd_a652 bnd_a653) &
% 7.12/6.62 ~ bnd_c8_1 bnd_a652) |
% 7.12/6.62 (ALL X38.
% 7.12/6.62 bnd_ndr1_0 -->
% 7.12/6.62 ((ALL X39.
% 7.12/6.62 bnd_ndr1_1 X38 -->
% 7.12/6.62 (~ bnd_c10_2 X38 X39 | ~ bnd_c3_2 X38 X39) | bnd_c8_2 X38 X39) |
% 7.12/6.62 (ALL X40.
% 7.12/6.62 bnd_ndr1_1 X38 -->
% 7.12/6.62 (bnd_c6_2 X38 X40 | bnd_c4_2 X38 X40) | ~ bnd_c3_2 X38 X40)) |
% 7.12/6.62 bnd_c8_1 X38))) &
% 7.12/6.62 ((ALL X41.
% 7.12/6.62 bnd_ndr1_0 -->
% 7.12/6.62 (~ bnd_c4_1 X41 |
% 7.12/6.62 (ALL X42.
% 7.12/6.62 bnd_ndr1_1 X41 -->
% 7.12/6.62 (~ bnd_c2_2 X41 X42 | bnd_c10_2 X41 X42) | bnd_c6_2 X41 X42)) |
% 7.12/6.62 ((bnd_ndr1_1 X41 & bnd_c1_2 X41 bnd_a654) & ~ bnd_c9_2 X41 bnd_a654) &
% 7.12/6.62 ~ bnd_c4_2 X41 bnd_a654) |
% 7.12/6.62 bnd_c9_0)) &
% 7.12/6.62 ((((bnd_ndr1_0 & bnd_c2_1 bnd_a655) &
% 7.12/6.62 (ALL X43.
% 7.12/6.62 bnd_ndr1_1 bnd_a655 -->
% 7.12/6.62 (~ bnd_c2_2 bnd_a655 X43 | ~ bnd_c10_2 bnd_a655 X43) |
% 7.12/6.62 bnd_c3_2 bnd_a655 X43)) &
% 7.12/6.62 (ALL X44.
% 7.12/6.62 bnd_ndr1_1 bnd_a655 -->
% 7.12/6.62 (bnd_c9_2 bnd_a655 X44 | bnd_c6_2 bnd_a655 X44) | bnd_c3_2 bnd_a655 X44) |
% 7.12/6.62 ((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a656) &
% 7.12/6.62 bnd_c6_2 bnd_a656 bnd_a657) &
% 7.12/6.62 bnd_c3_2 bnd_a656 bnd_a657) &
% 7.12/6.62 bnd_c7_1 bnd_a656) &
% 7.12/6.62 bnd_c1_1 bnd_a656) |
% 7.12/6.62 ~ bnd_c3_0)) &
% 7.12/6.62 ((bnd_c3_0 | ~ bnd_c6_0) | ~ bnd_c8_0)) &
% 7.12/6.62 (~ bnd_c8_0 |
% 7.12/6.62 (bnd_ndr1_0 & bnd_c7_1 bnd_a658) &
% 7.12/6.62 (ALL X45.
% 7.12/6.62 bnd_ndr1_1 bnd_a658 -->
% 7.12/6.62 (~ bnd_c5_2 bnd_a658 X45 |
% 7.12/6.62 ~ bnd_c3_2 bnd_a658 X45) |
% 7.12/6.62 ~ bnd_c4_2 bnd_a658 X45))) &
% 7.12/6.62 (((ALL X46.
% 7.12/6.62 bnd_ndr1_0 -->
% 7.12/6.62 (bnd_c7_1 X46 |
% 7.12/6.62 ((bnd_ndr1_1 X46 &
% 7.12/6.62 ~ bnd_c8_2 X46 bnd_a659) &
% 7.12/6.62 ~ bnd_c5_2 X46 bnd_a659) &
% 7.12/6.62 ~ bnd_c7_2 X46 bnd_a659) |
% 7.12/6.62 ~ bnd_c4_1 X46) |
% 7.12/6.62 bnd_c6_0) |
% 7.12/6.62 (ALL X47.
% 7.12/6.62 bnd_ndr1_0 -->
% 7.12/6.62 (~ bnd_c1_1 X47 | bnd_c5_1 X47) |
% 7.12/6.62 (ALL X48.
% 7.12/6.62 bnd_ndr1_1 X47 -->
% 7.12/6.62 (bnd_c8_2 X47 X48 | bnd_c6_2 X47 X48) | bnd_c4_2 X47 X48)))) &
% 7.12/6.62 (((ALL X49.
% 7.12/6.62 bnd_ndr1_0 -->
% 7.12/6.62 (ALL X50.
% 7.12/6.62 bnd_ndr1_1 X49 -->
% 7.12/6.62 (bnd_c1_2 X49 X50 | ~ bnd_c10_2 X49 X50) | bnd_c5_2 X49 X50) |
% 7.12/6.62 bnd_c8_1 X49) |
% 7.12/6.62 ~ bnd_c3_0) |
% 7.12/6.62 bnd_c9_0)) &
% 7.12/6.62 (((bnd_ndr1_0 & bnd_c5_1 bnd_a660) &
% 7.12/6.62 ~ bnd_c10_1 bnd_a660) &
% 7.12/6.62 ~ bnd_c6_1 bnd_a660 |
% 7.12/6.62 (ALL X51.
% 7.12/6.62 bnd_ndr1_0 -->
% 7.12/6.62 (((bnd_ndr1_1 X51 &
% 7.12/6.62 ~ bnd_c1_2 X51 bnd_a661) &
% 7.12/6.62 bnd_c5_2 X51 bnd_a661) &
% 7.12/6.62 ~ bnd_c6_2 X51 bnd_a661 |
% 7.12/6.62 ~ bnd_c8_1 X51) |
% 7.12/6.62 ((bnd_ndr1_1 X51 &
% 7.12/6.62 ~ bnd_c6_2 X51 bnd_a662) &
% 7.12/6.62 bnd_c10_2 X51 bnd_a662) &
% 7.12/6.62 ~ bnd_c2_2 X51 bnd_a662))) &
% 7.12/6.62 ((((bnd_ndr1_0 & bnd_c7_1 bnd_a663) &
% 7.12/6.62 bnd_c1_1 bnd_a663) &
% 7.12/6.62 (ALL X52.
% 7.12/6.62 bnd_ndr1_1 bnd_a663 -->
% 7.12/6.62 (bnd_c1_2 bnd_a663 X52 |
% 7.12/6.62 bnd_c4_2 bnd_a663 X52) |
% 7.12/6.62 ~ bnd_c3_2 bnd_a663 X52) |
% 7.12/6.62 (ALL X53.
% 7.12/6.62 bnd_ndr1_0 -->
% 7.12/6.62 (~ bnd_c10_1 X53 |
% 7.12/6.62 (ALL X54.
% 7.12/6.62 bnd_ndr1_1 X53 -->
% 7.12/6.62 (bnd_c1_2 X53 X54 | ~ bnd_c7_2 X53 X54) | ~ bnd_c8_2 X53 X54)) |
% 7.12/6.62 ~ bnd_c9_1 X53)) |
% 7.12/6.62 (ALL X55.
% 7.12/6.62 bnd_ndr1_0 -->
% 7.12/6.62 ~ bnd_c9_1 X55 |
% 7.12/6.62 ((bnd_ndr1_1 X55 & bnd_c5_2 X55 bnd_a664) &
% 7.12/6.62 bnd_c2_2 X55 bnd_a664) &
% 7.12/6.62 bnd_c7_2 X55 bnd_a664))) &
% 7.12/6.62 (~ bnd_c10_0 | bnd_c3_0)) &
% 7.12/6.62 (((ALL X56.
% 7.12/6.62 bnd_ndr1_0 -->
% 7.12/6.62 (bnd_c2_1 X56 |
% 7.12/6.62 (ALL X57.
% 7.12/6.62 bnd_ndr1_1 X56 -->
% 7.12/6.62 (~ bnd_c9_2 X56 X57 |
% 7.12/6.62 ~ bnd_c10_2 X56 X57) |
% 7.12/6.62 ~ bnd_c1_2 X56 X57)) |
% 7.12/6.62 ~ bnd_c6_1 X56) |
% 7.12/6.62 ~ bnd_c4_0) |
% 7.12/6.62 ~ bnd_c3_0)) &
% 7.12/6.62 ((bnd_c6_0 |
% 7.12/6.62 ((bnd_ndr1_0 &
% 7.12/6.62 (ALL X58.
% 7.12/6.62 bnd_ndr1_1 bnd_a665 -->
% 7.12/6.62 (~ bnd_c1_2 bnd_a665 X58 |
% 7.12/6.62 bnd_c7_2 bnd_a665 X58) |
% 7.12/6.62 ~ bnd_c4_2 bnd_a665 X58)) &
% 7.12/6.62 ~ bnd_c2_1 bnd_a665) &
% 7.12/6.62 (ALL X59.
% 7.12/6.62 bnd_ndr1_1 bnd_a665 -->
% 7.12/6.62 bnd_c4_2 bnd_a665 X59 |
% 7.12/6.62 bnd_c9_2 bnd_a665 X59)) |
% 7.12/6.62 (ALL X60.
% 7.12/6.62 bnd_ndr1_0 -->
% 7.12/6.62 (bnd_c7_1 X60 | ~ bnd_c3_1 X60) |
% 7.12/6.62 ((bnd_ndr1_1 X60 & bnd_c8_2 X60 bnd_a666) &
% 7.12/6.62 ~ bnd_c7_2 X60 bnd_a666) &
% 7.12/6.62 bnd_c3_2 X60 bnd_a666))) &
% 7.12/6.62 (((ALL X61.
% 7.12/6.62 bnd_ndr1_0 -->
% 7.12/6.62 (((bnd_ndr1_1 X61 & bnd_c1_2 X61 bnd_a667) &
% 7.12/6.62 ~ bnd_c10_2 X61 bnd_a667) &
% 7.12/6.62 bnd_c6_2 X61 bnd_a667 |
% 7.12/6.62 (ALL X62.
% 7.12/6.62 bnd_ndr1_1 X61 -->
% 7.12/6.62 (bnd_c8_2 X61 X62 | ~ bnd_c2_2 X61 X62) |
% 7.12/6.62 bnd_c3_2 X61 X62)) |
% 7.12/6.62 (ALL X63.
% 7.12/6.62 bnd_ndr1_1 X61 -->
% 7.12/6.62 (bnd_c1_2 X61 X63 | ~ bnd_c8_2 X61 X63) |
% 7.12/6.62 bnd_c5_2 X61 X63)) |
% 7.12/6.62 ~ bnd_c4_0) |
% 7.12/6.62 ~ bnd_c5_0)) &
% 7.12/6.62 ((((bnd_ndr1_0 &
% 7.12/6.62 (ALL X64.
% 7.12/6.62 bnd_ndr1_1 bnd_a668 -->
% 7.12/6.62 ~ bnd_c4_2 bnd_a668 X64 |
% 7.12/6.62 bnd_c1_2 bnd_a668 X64)) &
% 7.12/6.62 (ALL X65.
% 7.12/6.62 bnd_ndr1_1 bnd_a668 -->
% 7.12/6.62 (bnd_c2_2 bnd_a668 X65 |
% 7.12/6.62 ~ bnd_c8_2 bnd_a668 X65) |
% 7.12/6.62 ~ bnd_c3_2 bnd_a668 X65)) &
% 7.12/6.62 ~ bnd_c9_1 bnd_a668 |
% 7.12/6.62 bnd_c5_0) |
% 7.12/6.62 ((bnd_ndr1_0 &
% 7.12/6.62 (ALL X66.
% 7.12/6.62 bnd_ndr1_1 bnd_a669 -->
% 7.12/6.62 bnd_c6_2 bnd_a669 X66 |
% 7.12/6.62 bnd_c1_2 bnd_a669 X66)) &
% 7.12/6.62 ~ bnd_c2_1 bnd_a669) &
% 7.12/6.62 (ALL X67.
% 7.12/6.62 bnd_ndr1_1 bnd_a669 -->
% 7.12/6.62 (bnd_c4_2 bnd_a669 X67 | bnd_c5_2 bnd_a669 X67) |
% 7.12/6.62 bnd_c3_2 bnd_a669 X67))) &
% 7.12/6.62 ((~ bnd_c7_0 | ~ bnd_c2_0) | ~ bnd_c1_0)) &
% 7.12/6.62 ((((bnd_ndr1_0 & ~ bnd_c3_1 bnd_a670) &
% 7.12/6.62 bnd_c9_1 bnd_a670) &
% 7.12/6.62 bnd_c8_1 bnd_a670 |
% 7.12/6.62 (ALL X68.
% 7.12/6.62 bnd_ndr1_0 -->
% 7.12/6.62 (~ bnd_c3_1 X68 |
% 7.12/6.62 ((bnd_ndr1_1 X68 & bnd_c8_2 X68 bnd_a671) &
% 7.12/6.62 ~ bnd_c1_2 X68 bnd_a671) &
% 7.12/6.62 bnd_c2_2 X68 bnd_a671) |
% 7.12/6.62 (ALL X69.
% 7.12/6.62 bnd_ndr1_1 X68 -->
% 7.12/6.62 (bnd_c10_2 X68 X69 | bnd_c7_2 X68 X69) |
% 7.12/6.62 bnd_c3_2 X68 X69))) |
% 7.12/6.62 ~ bnd_c9_0)) &
% 7.12/6.62 ((((bnd_ndr1_0 & bnd_c7_1 bnd_a672) &
% 7.12/6.62 ~ bnd_c6_1 bnd_a672) &
% 7.12/6.62 bnd_c8_1 bnd_a672 |
% 7.12/6.62 bnd_c10_0) |
% 7.12/6.62 ~ bnd_c2_0)) &
% 7.12/6.62 ((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a673) &
% 7.12/6.62 ~ bnd_c4_2 bnd_a673 bnd_a674) &
% 7.12/6.62 bnd_c3_2 bnd_a673 bnd_a674) &
% 7.12/6.62 bnd_c9_1 bnd_a673) &
% 7.12/6.62 (ALL X70.
% 7.12/6.62 bnd_ndr1_1 bnd_a673 -->
% 7.12/6.62 (~ bnd_c6_2 bnd_a673 X70 |
% 7.12/6.62 ~ bnd_c3_2 bnd_a673 X70) |
% 7.12/6.62 bnd_c4_2 bnd_a673 X70) |
% 7.12/6.62 (ALL X71.
% 7.12/6.62 bnd_ndr1_0 -->
% 7.12/6.62 ((ALL X72.
% 7.12/6.62 bnd_ndr1_1 X71 -->
% 7.12/6.62 (bnd_c3_2 X71 X72 | bnd_c6_2 X71 X72) |
% 7.12/6.62 ~ bnd_c2_2 X71 X72) |
% 7.12/6.62 ~ bnd_c3_1 X71) |
% 7.12/6.62 ~ bnd_c6_1 X71)) |
% 7.12/6.62 bnd_c9_0)) &
% 7.12/6.62 ((~ bnd_c9_0 | ~ bnd_c7_0) |
% 7.12/6.62 (ALL X73.
% 7.12/6.62 bnd_ndr1_0 -->
% 7.12/6.62 (((bnd_ndr1_1 X73 & bnd_c5_2 X73 bnd_a675) &
% 7.12/6.62 ~ bnd_c1_2 X73 bnd_a675) &
% 7.12/6.62 bnd_c8_2 X73 bnd_a675 |
% 7.12/6.62 ((bnd_ndr1_1 X73 & ~ bnd_c5_2 X73 bnd_a676) &
% 7.12/6.62 ~ bnd_c9_2 X73 bnd_a676) &
% 7.12/6.62 bnd_c8_2 X73 bnd_a676) |
% 7.12/6.62 ((bnd_ndr1_1 X73 & bnd_c5_2 X73 bnd_a677) &
% 7.12/6.62 ~ bnd_c9_2 X73 bnd_a677) &
% 7.12/6.62 bnd_c2_2 X73 bnd_a677))) &
% 7.12/6.62 ((~ bnd_c3_0 |
% 7.12/6.62 (ALL X74.
% 7.12/6.62 bnd_ndr1_0 -->
% 7.12/6.62 (~ bnd_c6_1 X74 | ~ bnd_c2_1 X74) | bnd_c3_1 X74)) |
% 7.12/6.62 ~ bnd_c10_0)) &
% 7.12/6.62 ((bnd_c10_0 | bnd_c9_0) | bnd_c2_0)) &
% 7.12/6.62 ((~ bnd_c9_0 | bnd_c1_0) | bnd_c8_0)) &
% 7.12/6.62 (bnd_c3_0 | bnd_c7_0)) &
% 7.12/6.62 (bnd_c3_0 |
% 7.12/6.62 (ALL X75.
% 7.12/6.62 bnd_ndr1_0 -->
% 7.12/6.62 (((bnd_ndr1_1 X75 & ~ bnd_c8_2 X75 bnd_a678) &
% 7.12/6.62 bnd_c1_2 X75 bnd_a678) &
% 7.12/6.62 ~ bnd_c6_2 X75 bnd_a678 |
% 7.12/6.62 (ALL X76.
% 7.12/6.62 bnd_ndr1_1 X75 -->
% 7.12/6.62 (~ bnd_c8_2 X75 X76 | ~ bnd_c2_2 X75 X76) |
% 7.12/6.62 bnd_c1_2 X75 X76)) |
% 7.12/6.62 bnd_c7_1 X75))) &
% 7.12/6.62 (~ bnd_c1_0 | bnd_c8_0)) &
% 7.12/6.62 ((bnd_c7_0 | ~ bnd_c6_0) | bnd_c10_0)) &
% 7.12/6.62 ((((((((((bnd_ndr1_0 &
% 7.12/6.62 (ALL X77.
% 7.12/6.62 bnd_ndr1_1 bnd_a679 -->
% 7.12/6.62 (bnd_c10_2 bnd_a679 X77 | bnd_c4_2 bnd_a679 X77) |
% 7.12/6.62 ~ bnd_c9_2 bnd_a679 X77)) &
% 7.12/6.62 bnd_ndr1_1 bnd_a679) &
% 7.12/6.62 ~ bnd_c1_2 bnd_a679 bnd_a680) &
% 7.12/6.62 bnd_c8_2 bnd_a679 bnd_a680) &
% 7.12/6.62 bnd_c9_2 bnd_a679 bnd_a680) &
% 7.12/6.62 bnd_ndr1_1 bnd_a679) &
% 7.12/6.62 bnd_c1_2 bnd_a679 bnd_a681) &
% 7.12/6.62 ~ bnd_c5_2 bnd_a679 bnd_a681) &
% 7.12/6.62 ~ bnd_c9_2 bnd_a679 bnd_a681 |
% 7.12/6.62 bnd_c8_0) |
% 7.12/6.62 ~ bnd_c4_0)) &
% 7.12/6.62 ((bnd_c3_0 |
% 7.12/6.62 (ALL X78. bnd_ndr1_0 --> ~ bnd_c4_1 X78 | bnd_c7_1 X78)) |
% 7.12/6.62 (ALL X79.
% 7.12/6.62 bnd_ndr1_0 -->
% 7.12/6.62 (((bnd_ndr1_1 X79 & ~ bnd_c10_2 X79 bnd_a682) &
% 7.12/6.62 bnd_c3_2 X79 bnd_a682) &
% 7.12/6.62 ~ bnd_c5_2 X79 bnd_a682 |
% 7.12/6.62 ((bnd_ndr1_1 X79 & bnd_c6_2 X79 bnd_a683) &
% 7.12/6.62 ~ bnd_c4_2 X79 bnd_a683) &
% 7.12/6.62 bnd_c5_2 X79 bnd_a683) |
% 7.12/6.62 ~ bnd_c9_1 X79))) &
% 7.12/6.62 (((ALL X80.
% 7.12/6.62 bnd_ndr1_0 -->
% 7.12/6.62 (~ bnd_c3_1 X80 | bnd_c1_1 X80) | bnd_c4_1 X80) |
% 7.12/6.62 bnd_c8_0) |
% 7.12/6.62 ~ bnd_c9_0)) &
% 7.12/6.62 (((ALL X81.
% 7.12/6.62 bnd_ndr1_0 -->
% 7.12/6.62 (((bnd_ndr1_1 X81 & bnd_c6_2 X81 bnd_a684) &
% 7.12/6.62 bnd_c1_2 X81 bnd_a684) &
% 7.12/6.62 bnd_c7_2 X81 bnd_a684 |
% 7.12/6.62 ((bnd_ndr1_1 X81 & bnd_c10_2 X81 bnd_a685) &
% 7.12/6.62 bnd_c3_2 X81 bnd_a685) &
% 7.12/6.62 ~ bnd_c6_2 X81 bnd_a685) |
% 7.12/6.62 ~ bnd_c8_1 X81) |
% 7.12/6.62 bnd_c7_0) |
% 7.12/6.62 ~ bnd_c6_0)) &
% 7.12/6.62 (((((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a686) &
% 7.12/6.62 ~ bnd_c1_2 bnd_a686 bnd_a687) &
% 7.12/6.62 bnd_c4_2 bnd_a686 bnd_a687) &
% 7.12/6.62 ~ bnd_c8_2 bnd_a686 bnd_a687) &
% 7.12/6.62 bnd_c8_1 bnd_a686) &
% 7.12/6.62 bnd_ndr1_1 bnd_a686) &
% 7.12/6.62 bnd_c4_2 bnd_a686 bnd_a688) &
% 7.12/6.62 bnd_c2_2 bnd_a686 bnd_a688 |
% 7.12/6.62 ~ bnd_c8_0) |
% 7.12/6.62 bnd_c1_0)) &
% 7.12/6.62 (bnd_c5_0 | bnd_c8_0)) &
% 7.12/6.62 ((bnd_c2_0 |
% 7.12/6.62 (ALL X82.
% 7.12/6.62 bnd_ndr1_0 -->
% 7.12/6.62 (~ bnd_c10_1 X82 | ~ bnd_c8_1 X82) |
% 7.12/6.62 (ALL X83.
% 7.12/6.62 bnd_ndr1_1 X82 -->
% 7.12/6.62 (~ bnd_c8_2 X82 X83 | bnd_c5_2 X82 X83) |
% 7.12/6.62 ~ bnd_c3_2 X82 X83))) |
% 7.12/6.62 bnd_c1_0)) &
% 7.12/6.62 ((ALL X84.
% 7.12/6.62 bnd_ndr1_0 -->
% 7.12/6.62 ((ALL X85.
% 7.12/6.62 bnd_ndr1_1 X84 -->
% 7.12/6.62 (~ bnd_c9_2 X84 X85 | bnd_c6_2 X84 X85) | ~ bnd_c10_2 X84 X85) |
% 7.12/6.62 ~ bnd_c8_1 X84) |
% 7.12/6.62 ~ bnd_c3_1 X84) |
% 7.12/6.62 bnd_c6_0)) &
% 7.12/6.62 ((((bnd_ndr1_0 & ~ bnd_c5_1 bnd_a689) & bnd_c9_1 bnd_a689) &
% 7.12/6.62 (ALL X86.
% 7.12/6.62 bnd_ndr1_1 bnd_a689 -->
% 7.12/6.62 (bnd_c4_2 bnd_a689 X86 | ~ bnd_c10_2 bnd_a689 X86) |
% 7.12/6.62 bnd_c1_2 bnd_a689 X86) |
% 7.12/6.62 bnd_c2_0) |
% 7.12/6.62 bnd_c9_0)) &
% 7.12/6.62 (((ALL X87. bnd_ndr1_0 --> (bnd_c2_1 X87 | bnd_c5_1 X87) | bnd_c3_1 X87) |
% 7.12/6.62 bnd_c4_0) |
% 7.12/6.62 (((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a690) & ~ bnd_c5_2 bnd_a690 bnd_a691) &
% 7.12/6.62 ~ bnd_c9_2 bnd_a690 bnd_a691) &
% 7.12/6.62 ~ bnd_c10_2 bnd_a690 bnd_a691) &
% 7.12/6.62 bnd_c2_1 bnd_a690) &
% 7.12/6.62 (ALL X88.
% 7.12/6.62 bnd_ndr1_1 bnd_a690 -->
% 7.12/6.62 (bnd_c7_2 bnd_a690 X88 | bnd_c2_2 bnd_a690 X88) |
% 7.12/6.62 bnd_c4_2 bnd_a690 X88))) &
% 7.12/6.62 (((((((((bnd_ndr1_0 &
% 7.12/6.62 bnd_ndr1_1 bnd_a692) &
% 7.12/6.62 ~ bnd_c7_2 bnd_a692 bnd_a693) &
% 7.12/6.62 bnd_c9_2 bnd_a692 bnd_a693) &
% 7.12/6.62 bnd_c2_2 bnd_a692 bnd_a693) &
% 7.12/6.62 bnd_ndr1_1 bnd_a692) &
% 7.12/6.62 ~ bnd_c3_2 bnd_a692 bnd_a694) &
% 7.12/6.62 ~ bnd_c10_2 bnd_a692 bnd_a694) &
% 7.12/6.62 ~ bnd_c5_1 bnd_a692 |
% 7.12/6.62 ((bnd_ndr1_0 & bnd_c5_1 bnd_a695) & ~ bnd_c10_1 bnd_a695) &
% 7.12/6.62 ~ bnd_c8_1 bnd_a695) |
% 7.12/6.62 bnd_c3_0)) &
% 7.12/6.62 ((bnd_c3_0 |
% 7.12/6.62 (bnd_ndr1_0 &
% 7.12/6.62 (ALL X89.
% 7.12/6.62 bnd_ndr1_1 bnd_a696 -->
% 7.12/6.62 (~ bnd_c7_2 bnd_a696 X89 | bnd_c5_2 bnd_a696 X89) |
% 7.12/6.62 ~ bnd_c2_2 bnd_a696 X89)) &
% 7.12/6.62 ~ bnd_c1_1 bnd_a696) |
% 7.12/6.62 ((bnd_ndr1_0 & ~ bnd_c3_1 bnd_a697) &
% 7.12/6.62 (ALL X90.
% 7.12/6.62 bnd_ndr1_1 bnd_a697 -->
% 7.12/6.62 (~ bnd_c3_2 bnd_a697 X90 | bnd_c8_2 bnd_a697 X90) |
% 7.12/6.62 ~ bnd_c6_2 bnd_a697 X90)) &
% 7.12/6.62 bnd_c9_1 bnd_a697)) &
% 7.12/6.62 ((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a698) &
% 7.12/6.62 ~ bnd_c5_2 bnd_a698 bnd_a699) &
% 7.12/6.62 bnd_c1_2 bnd_a698 bnd_a699) &
% 7.12/6.62 bnd_c2_1 bnd_a698) &
% 7.12/6.62 bnd_c9_1 bnd_a698 |
% 7.12/6.62 ~ bnd_c4_0) |
% 7.12/6.62 bnd_c2_0)) &
% 7.12/6.62 ((~ bnd_c1_0 |
% 7.12/6.62 ((bnd_ndr1_0 & ~ bnd_c7_1 bnd_a700) &
% 7.12/6.62 ~ bnd_c9_1 bnd_a700) &
% 7.12/6.62 ~ bnd_c10_1 bnd_a700) |
% 7.12/6.62 (((((bnd_ndr1_0 &
% 7.12/6.62 (ALL X91.
% 7.12/6.62 bnd_ndr1_1 bnd_a701 -->
% 7.12/6.62 (~ bnd_c1_2 bnd_a701 X91 | ~ bnd_c6_2 bnd_a701 X91) |
% 7.12/6.62 bnd_c5_2 bnd_a701 X91)) &
% 7.12/6.62 bnd_ndr1_1 bnd_a701) &
% 7.12/6.62 ~ bnd_c2_2 bnd_a701 bnd_a702) &
% 7.12/6.62 bnd_c10_2 bnd_a701 bnd_a702) &
% 7.12/6.62 bnd_c6_2 bnd_a701 bnd_a702) &
% 7.12/6.62 ~ bnd_c8_1 bnd_a701)) &
% 7.12/6.62 ((((bnd_ndr1_0 & ~ bnd_c10_1 bnd_a703) &
% 7.12/6.62 bnd_c4_1 bnd_a703) &
% 7.12/6.62 ~ bnd_c7_1 bnd_a703 |
% 7.12/6.62 (ALL X92.
% 7.12/6.62 bnd_ndr1_0 -->
% 7.12/6.62 (~ bnd_c7_1 X92 | bnd_c4_1 X92) |
% 7.12/6.62 ((bnd_ndr1_1 X92 & ~ bnd_c5_2 X92 bnd_a704) & ~ bnd_c3_2 X92 bnd_a704) &
% 7.12/6.62 bnd_c9_2 X92 bnd_a704)) |
% 7.12/6.62 (ALL X93.
% 7.12/6.62 bnd_ndr1_0 -->
% 7.12/6.62 ((ALL X94.
% 7.12/6.62 bnd_ndr1_1 X93 -->
% 7.12/6.62 (bnd_c6_2 X93 X94 | bnd_c4_2 X93 X94) | ~ bnd_c8_2 X93 X94) |
% 7.12/6.62 bnd_c1_1 X93) |
% 7.12/6.62 (ALL X95.
% 7.12/6.62 bnd_ndr1_1 X93 -->
% 7.12/6.62 (bnd_c4_2 X93 X95 | ~ bnd_c1_2 X93 X95) | bnd_c10_2 X93 X95)))) &
% 7.12/6.62 ((((bnd_ndr1_0 & ~ bnd_c9_1 bnd_a705) &
% 7.12/6.62 (ALL X96.
% 7.12/6.62 bnd_ndr1_1 bnd_a705 -->
% 7.12/6.62 (~ bnd_c2_2 bnd_a705 X96 | ~ bnd_c6_2 bnd_a705 X96) |
% 7.12/6.62 ~ bnd_c7_2 bnd_a705 X96)) &
% 7.12/6.62 ~ bnd_c3_1 bnd_a705 |
% 7.12/6.62 (ALL X97.
% 7.12/6.62 bnd_ndr1_0 -->
% 7.12/6.62 (((bnd_ndr1_1 X97 & ~ bnd_c9_2 X97 bnd_a706) & bnd_c6_2 X97 bnd_a706) &
% 7.12/6.62 bnd_c5_2 X97 bnd_a706 |
% 7.12/6.62 ~ bnd_c9_1 X97) |
% 7.12/6.62 ~ bnd_c1_1 X97)) |
% 7.12/6.62 bnd_c6_0)) &
% 7.12/6.62 ((bnd_c2_0 |
% 7.12/6.62 ((bnd_ndr1_0 &
% 7.12/6.62 (ALL X98.
% 7.12/6.62 bnd_ndr1_1 bnd_a707 -->
% 7.12/6.62 (bnd_c1_2 bnd_a707 X98 | bnd_c4_2 bnd_a707 X98) |
% 7.12/6.62 ~ bnd_c3_2 bnd_a707 X98)) &
% 7.12/6.62 ~ bnd_c10_1 bnd_a707) &
% 7.12/6.62 bnd_c8_1 bnd_a707) |
% 7.12/6.62 (bnd_ndr1_0 &
% 7.12/6.62 (ALL X99.
% 7.12/6.62 bnd_ndr1_1 bnd_a708 -->
% 7.12/6.62 (~ bnd_c5_2 bnd_a708 X99 |
% 7.12/6.62 bnd_c10_2 bnd_a708 X99) |
% 7.12/6.62 bnd_c7_2 bnd_a708 X99)) &
% 7.12/6.62 ~ bnd_c5_1 bnd_a708)) &
% 7.12/6.62 (~ bnd_c8_0 | ~ bnd_c2_0)) &
% 7.12/6.62 (((((((bnd_ndr1_0 & bnd_c8_1 bnd_a709) &
% 7.12/6.62 ~ bnd_c9_1 bnd_a709) &
% 7.12/6.62 bnd_ndr1_1 bnd_a709) &
% 7.12/6.62 bnd_c9_2 bnd_a709 bnd_a710) &
% 7.12/6.62 ~ bnd_c8_2 bnd_a709 bnd_a710) &
% 7.12/6.62 ~ bnd_c6_2 bnd_a709 bnd_a710 |
% 7.12/6.62 (ALL X100.
% 7.12/6.62 bnd_ndr1_0 -->
% 7.12/6.62 ((ALL X101.
% 7.12/6.62 bnd_ndr1_1 X100 -->
% 7.12/6.62 (~ bnd_c2_2 X100 X101 | bnd_c1_2 X100 X101) | ~ bnd_c9_2 X100 X101) |
% 7.12/6.62 (ALL X102.
% 7.12/6.62 bnd_ndr1_1 X100 -->
% 7.12/6.62 (bnd_c4_2 X100 X102 | ~ bnd_c7_2 X100 X102) | ~ bnd_c5_2 X100 X102)) |
% 7.12/6.62 ~ bnd_c8_1 X100)) |
% 7.12/6.62 ~ bnd_c1_0)) &
% 7.12/6.62 (((ALL X103.
% 7.12/6.62 bnd_ndr1_0 -->
% 7.12/6.62 (bnd_c8_1 X103 |
% 7.12/6.62 (ALL X104.
% 7.12/6.62 bnd_ndr1_1 X103 -->
% 7.12/6.62 (~ bnd_c3_2 X103 X104 | ~ bnd_c5_2 X103 X104) | ~ bnd_c2_2 X103 X104)) |
% 7.12/6.62 (ALL X105.
% 7.12/6.62 bnd_ndr1_1 X103 -->
% 7.12/6.62 (~ bnd_c7_2 X103 X105 | ~ bnd_c2_2 X103 X105) | ~ bnd_c10_2 X103 X105)) |
% 7.12/6.62 ~ bnd_c5_0) |
% 7.12/6.62 (ALL X106.
% 7.12/6.62 bnd_ndr1_0 -->
% 7.12/6.62 (bnd_c5_1 X106 | ~ bnd_c7_1 X106) |
% 7.12/6.62 ((bnd_ndr1_1 X106 &
% 7.12/6.62 ~ bnd_c10_2 X106 bnd_a711) &
% 7.12/6.62 bnd_c8_2 X106 bnd_a711) &
% 7.12/6.62 ~ bnd_c2_2 X106 bnd_a711))) &
% 7.12/6.62 ((bnd_c8_0 | ~ bnd_c2_0) | ~ bnd_c7_0)) &
% 7.12/6.62 (((ALL X107.
% 7.12/6.62 bnd_ndr1_0 -->
% 7.12/6.62 ((bnd_ndr1_1 X107 &
% 7.12/6.62 ~ bnd_c4_2 X107 bnd_a712) &
% 7.12/6.62 bnd_c8_2 X107 bnd_a712) &
% 7.12/6.62 ~ bnd_c9_2 X107 bnd_a712 |
% 7.12/6.62 ((bnd_ndr1_1 X107 &
% 7.12/6.62 ~ bnd_c6_2 X107 bnd_a713) &
% 7.12/6.62 ~ bnd_c10_2 X107 bnd_a713) &
% 7.12/6.62 bnd_c9_2 X107 bnd_a713) |
% 7.12/6.62 ~ bnd_c6_0) |
% 7.12/6.62 (ALL X108.
% 7.12/6.62 bnd_ndr1_0 -->
% 7.12/6.62 ((ALL X109.
% 7.12/6.62 bnd_ndr1_1 X108 -->
% 7.12/6.62 (bnd_c6_2 X108 X109 |
% 7.12/6.62 ~ bnd_c7_2 X108 X109) |
% 7.12/6.62 bnd_c8_2 X108 X109) |
% 7.12/6.62 ((bnd_ndr1_1 X108 &
% 7.12/6.62 bnd_c3_2 X108 bnd_a714) &
% 7.12/6.62 bnd_c7_2 X108 bnd_a714) &
% 7.12/6.62 ~ bnd_c5_2 X108 bnd_a714) |
% 7.12/6.62 ~ bnd_c8_1 X108))) &
% 7.12/6.62 (((ALL X110.
% 7.12/6.62 bnd_ndr1_0 -->
% 7.12/6.62 ((bnd_ndr1_1 X110 &
% 7.12/6.62 bnd_c10_2 X110 bnd_a715) &
% 7.12/6.62 ~ bnd_c3_2 X110 bnd_a715 |
% 7.12/6.62 (ALL X111.
% 7.12/6.62 bnd_ndr1_1 X110 -->
% 7.12/6.62 ~ bnd_c7_2 X110 X111 |
% 7.12/6.62 ~ bnd_c3_2 X110 X111)) |
% 7.12/6.62 ((bnd_ndr1_1 X110 & bnd_c2_2 X110 bnd_a716) &
% 7.12/6.62 bnd_c3_2 X110 bnd_a716) &
% 7.12/6.62 bnd_c1_2 X110 bnd_a716) |
% 7.12/6.62 ~ bnd_c7_0) |
% 7.12/6.62 (ALL X112.
% 7.12/6.62 bnd_ndr1_0 -->
% 7.12/6.62 (~ bnd_c1_1 X112 |
% 7.12/6.62 (ALL X113.
% 7.12/6.62 bnd_ndr1_1 X112 -->
% 7.12/6.62 bnd_c7_2 X112 X113 |
% 7.12/6.62 ~ bnd_c5_2 X112 X113)) |
% 7.12/6.62 ~ bnd_c6_1 X112))) &
% 7.12/6.62 ((~ bnd_c9_0 |
% 7.12/6.62 (ALL X114.
% 7.12/6.62 bnd_ndr1_0 -->
% 7.12/6.62 (((bnd_ndr1_1 X114 & bnd_c5_2 X114 bnd_a717) &
% 7.12/6.62 bnd_c7_2 X114 bnd_a717) &
% 7.12/6.62 bnd_c4_2 X114 bnd_a717 |
% 7.12/6.62 (ALL X115.
% 7.12/6.62 bnd_ndr1_1 X114 -->
% 7.12/6.62 (~ bnd_c3_2 X114 X115 |
% 7.12/6.62 ~ bnd_c6_2 X114 X115) |
% 7.12/6.62 bnd_c4_2 X114 X115)) |
% 7.12/6.62 bnd_c3_1 X114)) |
% 7.12/6.62 bnd_c8_0)) &
% 7.12/6.62 (((ALL X116.
% 7.12/6.62 bnd_ndr1_0 -->
% 7.12/6.62 (~ bnd_c10_1 X116 |
% 7.12/6.62 (bnd_ndr1_1 X116 & ~ bnd_c8_2 X116 bnd_a718) &
% 7.12/6.62 ~ bnd_c7_2 X116 bnd_a718) |
% 7.12/6.62 ((bnd_ndr1_1 X116 & ~ bnd_c7_2 X116 bnd_a719) &
% 7.12/6.62 ~ bnd_c4_2 X116 bnd_a719) &
% 7.12/6.62 bnd_c2_2 X116 bnd_a719) |
% 7.12/6.62 (ALL X117.
% 7.12/6.62 bnd_ndr1_0 -->
% 7.12/6.62 ((bnd_ndr1_1 X117 & bnd_c3_2 X117 bnd_a720) &
% 7.12/6.62 ~ bnd_c10_2 X117 bnd_a720 |
% 7.12/6.62 bnd_c3_1 X117) |
% 7.12/6.62 bnd_c6_1 X117)) |
% 7.12/6.62 ((bnd_ndr1_0 & bnd_c4_1 bnd_a721) &
% 7.12/6.62 ~ bnd_c1_1 bnd_a721) &
% 7.12/6.62 ~ bnd_c5_1 bnd_a721)) &
% 7.12/6.62 (((ALL X118.
% 7.12/6.62 bnd_ndr1_0 -->
% 7.12/6.62 (bnd_c6_1 X118 |
% 7.12/6.62 (ALL X119.
% 7.12/6.62 bnd_ndr1_1 X118 -->
% 7.12/6.62 (bnd_c5_2 X118 X119 |
% 7.12/6.62 ~ bnd_c2_2 X118 X119) |
% 7.12/6.62 bnd_c4_2 X118 X119)) |
% 7.12/6.62 ((bnd_ndr1_1 X118 & ~ bnd_c5_2 X118 bnd_a722) &
% 7.12/6.62 ~ bnd_c9_2 X118 bnd_a722) &
% 7.12/6.62 bnd_c8_2 X118 bnd_a722) |
% 7.12/6.62 ((bnd_ndr1_0 & bnd_c10_1 bnd_a723) &
% 7.12/6.62 bnd_c4_1 bnd_a723) &
% 7.12/6.62 bnd_c7_1 bnd_a723) |
% 7.12/6.62 ~ bnd_c2_0)) &
% 7.12/6.62 ((bnd_c9_0 | ~ bnd_c7_0) |
% 7.12/6.62 ((((bnd_ndr1_0 &
% 7.12/6.62 (ALL X120.
% 7.12/6.62 bnd_ndr1_1 bnd_a724 -->
% 7.12/6.62 (bnd_c6_2 bnd_a724 X120 |
% 7.12/6.62 ~ bnd_c8_2 bnd_a724 X120) |
% 7.12/6.62 ~ bnd_c9_2 bnd_a724 X120)) &
% 7.12/6.62 bnd_ndr1_1 bnd_a724) &
% 7.12/6.62 ~ bnd_c6_2 bnd_a724 bnd_a725) &
% 7.12/6.62 bnd_c4_2 bnd_a724 bnd_a725) &
% 7.12/6.62 (ALL X121.
% 7.12/6.62 bnd_ndr1_1 bnd_a724 -->
% 7.12/6.62 bnd_c4_2 bnd_a724 X121 |
% 7.12/6.62 bnd_c2_2 bnd_a724 X121))) &
% 7.12/6.62 (((ALL X122.
% 7.12/6.62 bnd_ndr1_0 -->
% 7.12/6.62 (bnd_c1_1 X122 |
% 7.12/6.62 (ALL X123.
% 7.12/6.62 bnd_ndr1_1 X122 -->
% 7.12/6.62 (~ bnd_c5_2 X122 X123 | bnd_c3_2 X122 X123) |
% 7.12/6.62 bnd_c10_2 X122 X123)) |
% 7.12/6.62 bnd_c5_1 X122) |
% 7.12/6.62 bnd_c6_0) |
% 7.12/6.62 ~ bnd_c2_0)) &
% 7.12/6.62 (((ALL X124.
% 7.12/6.62 bnd_ndr1_0 -->
% 7.12/6.62 ((ALL X125.
% 7.12/6.62 bnd_ndr1_1 X124 -->
% 7.12/6.62 (~ bnd_c9_2 X124 X125 | bnd_c1_2 X124 X125) |
% 7.12/6.62 bnd_c10_2 X124 X125) |
% 7.12/6.62 bnd_c3_1 X124) |
% 7.12/6.62 (bnd_ndr1_1 X124 & ~ bnd_c4_2 X124 bnd_a726) &
% 7.12/6.62 ~ bnd_c3_2 X124 bnd_a726) |
% 7.12/6.62 (ALL X126.
% 7.12/6.62 bnd_ndr1_0 -->
% 7.12/6.62 (~ bnd_c7_1 X126 |
% 7.12/6.62 ((bnd_ndr1_1 X126 & ~ bnd_c7_2 X126 bnd_a727) &
% 7.12/6.62 bnd_c9_2 X126 bnd_a727) &
% 7.12/6.62 ~ bnd_c6_2 X126 bnd_a727) |
% 7.12/6.62 ~ bnd_c4_1 X126)) |
% 7.12/6.62 (ALL X127.
% 7.12/6.62 bnd_ndr1_0 -->
% 7.12/6.62 ((ALL X128.
% 7.12/6.62 bnd_ndr1_1 X127 -->
% 7.12/6.62 (~ bnd_c8_2 X127 X128 | ~ bnd_c4_2 X127 X128) |
% 7.12/6.62 bnd_c3_2 X127 X128) |
% 7.12/6.62 ~ bnd_c4_1 X127) |
% 7.12/6.62 ~ bnd_c10_1 X127))) &
% 7.12/6.62 ((~ bnd_c7_0 |
% 7.12/6.62 (bnd_ndr1_0 & bnd_c6_1 bnd_a728) & bnd_c1_1 bnd_a728) |
% 7.12/6.62 (((((bnd_ndr1_0 & ~ bnd_c9_1 bnd_a729) &
% 7.12/6.62 bnd_ndr1_1 bnd_a729) &
% 7.12/6.62 ~ bnd_c9_2 bnd_a729 bnd_a730) &
% 7.12/6.62 bnd_c7_2 bnd_a729 bnd_a730) &
% 7.12/6.62 bnd_c8_2 bnd_a729 bnd_a730) &
% 7.12/6.62 bnd_c3_1 bnd_a729)) &
% 7.12/6.62 (((ALL X129.
% 7.12/6.62 bnd_ndr1_0 -->
% 7.12/6.62 ((bnd_ndr1_1 X129 & bnd_c3_2 X129 bnd_a731) &
% 7.12/6.62 bnd_c9_2 X129 bnd_a731 |
% 7.12/6.62 (bnd_ndr1_1 X129 & ~ bnd_c3_2 X129 bnd_a732) &
% 7.12/6.62 bnd_c4_2 X129 bnd_a732) |
% 7.12/6.62 ~ bnd_c9_1 X129) |
% 7.12/6.62 ((bnd_ndr1_0 & ~ bnd_c4_1 bnd_a733) &
% 7.12/6.62 (ALL X130.
% 7.12/6.62 bnd_ndr1_1 bnd_a733 --> ~ bnd_c2_2 bnd_a733 X130)) &
% 7.12/6.62 (ALL X131.
% 7.12/6.62 bnd_ndr1_1 bnd_a733 -->
% 7.12/6.62 (~ bnd_c4_2 bnd_a733 X131 | bnd_c7_2 bnd_a733 X131) |
% 7.12/6.62 ~ bnd_c6_2 bnd_a733 X131)) |
% 7.12/6.62 ~ bnd_c10_0)) &
% 7.12/6.62 ((((((((((bnd_ndr1_0 & ~ bnd_c10_1 bnd_a734) &
% 7.12/6.62 bnd_ndr1_1 bnd_a734) &
% 7.12/6.62 ~ bnd_c7_2 bnd_a734 bnd_a735) &
% 7.12/6.62 bnd_c10_2 bnd_a734 bnd_a735) &
% 7.12/6.62 bnd_c6_2 bnd_a734 bnd_a735) &
% 7.12/6.62 bnd_ndr1_1 bnd_a734) &
% 7.12/6.62 ~ bnd_c3_2 bnd_a734 bnd_a736) &
% 7.12/6.62 bnd_c2_2 bnd_a734 bnd_a736) &
% 7.12/6.62 bnd_c1_2 bnd_a734 bnd_a736 |
% 7.12/6.62 ~ bnd_c7_0) |
% 7.12/6.62 (((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a737) &
% 7.12/6.62 bnd_c9_2 bnd_a737 bnd_a738) &
% 7.12/6.62 ~ bnd_c4_2 bnd_a737 bnd_a738) &
% 7.12/6.62 bnd_c1_2 bnd_a737 bnd_a738) &
% 7.12/6.62 bnd_c9_1 bnd_a737) &
% 7.12/6.62 ~ bnd_c4_1 bnd_a737)) &
% 7.12/6.62 ((((bnd_ndr1_0 & ~ bnd_c2_1 bnd_a739) &
% 7.12/6.62 ~ bnd_c5_1 bnd_a739) &
% 7.12/6.62 ~ bnd_c7_1 bnd_a739 |
% 7.12/6.62 ((bnd_ndr1_0 &
% 7.12/6.62 (ALL X132.
% 7.12/6.62 bnd_ndr1_1 bnd_a740 -->
% 7.12/6.62 ~ bnd_c10_2 bnd_a740 X132 |
% 7.12/6.62 bnd_c6_2 bnd_a740 X132)) &
% 7.12/6.62 ~ bnd_c9_1 bnd_a740) &
% 7.12/6.62 bnd_c4_1 bnd_a740) |
% 7.12/6.62 bnd_c10_0)) &
% 7.12/6.62 ((~ bnd_c10_0 | bnd_c9_0) |
% 7.12/6.62 (ALL X133.
% 7.12/6.62 bnd_ndr1_0 -->
% 7.12/6.62 ((ALL X134.
% 7.12/6.62 bnd_ndr1_1 X133 -->
% 7.12/6.62 (~ bnd_c9_2 X133 X134 | bnd_c6_2 X133 X134) |
% 7.12/6.62 bnd_c8_2 X133 X134) |
% 7.12/6.62 (ALL X135.
% 7.12/6.62 bnd_ndr1_1 X133 -->
% 7.12/6.62 (bnd_c5_2 X133 X135 | ~ bnd_c4_2 X133 X135) |
% 7.12/6.62 ~ bnd_c8_2 X133 X135)) |
% 7.12/6.62 ~ bnd_c4_1 X133))) &
% 7.12/6.62 (((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a741) &
% 7.12/6.62 bnd_c10_2 bnd_a741 bnd_a742) &
% 7.12/6.62 ~ bnd_c4_2 bnd_a741 bnd_a742) &
% 7.12/6.62 ~ bnd_c1_2 bnd_a741 bnd_a742) &
% 7.12/6.62 ~ bnd_c5_1 bnd_a741 |
% 7.12/6.62 (ALL X136.
% 7.12/6.62 bnd_ndr1_0 -->
% 7.12/6.62 ((ALL X137.
% 7.12/6.62 bnd_ndr1_1 X136 -->
% 7.12/6.62 (bnd_c6_2 X136 X137 | ~ bnd_c1_2 X136 X137) |
% 7.12/6.62 ~ bnd_c3_2 X136 X137) |
% 7.12/6.62 (bnd_ndr1_1 X136 & ~ bnd_c9_2 X136 bnd_a743) &
% 7.12/6.62 ~ bnd_c10_2 X136 bnd_a743) |
% 7.12/6.62 ((bnd_ndr1_1 X136 & bnd_c9_2 X136 bnd_a744) &
% 7.12/6.62 bnd_c6_2 X136 bnd_a744) &
% 7.12/6.62 bnd_c8_2 X136 bnd_a744))) &
% 7.12/6.62 ((~ bnd_c7_0 |
% 7.12/6.62 (((((bnd_ndr1_0 & bnd_c2_1 bnd_a745) & bnd_ndr1_1 bnd_a745) &
% 7.12/6.62 bnd_c4_2 bnd_a745 bnd_a746) &
% 7.12/6.62 bnd_c10_2 bnd_a745 bnd_a746) &
% 7.12/6.62 ~ bnd_c1_2 bnd_a745 bnd_a746) &
% 7.12/6.62 (ALL X138.
% 7.12/6.62 bnd_ndr1_1 bnd_a745 -->
% 7.12/6.62 (bnd_c9_2 bnd_a745 X138 | ~ bnd_c3_2 bnd_a745 X138) |
% 7.12/6.62 ~ bnd_c1_2 bnd_a745 X138)) |
% 7.12/6.62 bnd_c8_0)) &
% 7.12/6.62 (bnd_c6_0 |
% 7.12/6.62 (ALL X139.
% 7.12/6.62 bnd_ndr1_0 -->
% 7.12/6.62 (((bnd_ndr1_1 X139 & bnd_c5_2 X139 bnd_a747) &
% 7.12/6.62 ~ bnd_c1_2 X139 bnd_a747) &
% 7.12/6.62 bnd_c9_2 X139 bnd_a747 |
% 7.12/6.62 (ALL X140.
% 7.12/6.62 bnd_ndr1_1 X139 -->
% 7.12/6.62 (~ bnd_c1_2 X139 X140 | bnd_c3_2 X139 X140) |
% 7.12/6.62 bnd_c5_2 X139 X140)) |
% 7.12/6.62 ~ bnd_c2_1 X139))) &
% 7.12/6.62 (((ALL X141.
% 7.12/6.62 bnd_ndr1_0 -->
% 7.12/6.62 (((bnd_ndr1_1 X141 & ~ bnd_c4_2 X141 bnd_a748) &
% 7.12/6.62 bnd_c1_2 X141 bnd_a748) &
% 7.12/6.62 bnd_c10_2 X141 bnd_a748 |
% 7.12/6.62 bnd_c8_1 X141) |
% 7.12/6.62 (ALL X142.
% 7.12/6.62 bnd_ndr1_1 X141 -->
% 7.12/6.62 (bnd_c3_2 X141 X142 | bnd_c5_2 X141 X142) |
% 7.12/6.62 bnd_c10_2 X141 X142)) |
% 7.12/6.62 ~ bnd_c4_0) |
% 7.12/6.62 (ALL X143.
% 7.12/6.62 bnd_ndr1_0 -->
% 7.12/6.62 (((bnd_ndr1_1 X143 & ~ bnd_c5_2 X143 bnd_a749) &
% 7.12/6.62 bnd_c7_2 X143 bnd_a749) &
% 7.12/6.62 bnd_c6_2 X143 bnd_a749 |
% 7.12/6.62 ((bnd_ndr1_1 X143 & bnd_c2_2 X143 bnd_a750) &
% 7.12/6.62 ~ bnd_c8_2 X143 bnd_a750) &
% 7.12/6.62 ~ bnd_c10_2 X143 bnd_a750) |
% 7.12/6.62 (ALL X144.
% 7.12/6.62 bnd_ndr1_1 X143 -->
% 7.12/6.62 (~ bnd_c2_2 X143 X144 | bnd_c9_2 X143 X144) |
% 7.12/6.62 ~ bnd_c4_2 X143 X144)))) &
% 7.12/6.62 (((ALL X145. bnd_ndr1_0 --> bnd_c9_1 X145 | ~ bnd_c2_1 X145) |
% 7.12/6.62 ~ bnd_c10_0) |
% 7.12/6.62 ~ bnd_c1_0)) &
% 7.12/6.62 ((bnd_c4_0 | bnd_c2_0) | bnd_c6_0)) &
% 7.12/6.62 (((ALL X146.
% 7.12/6.62 bnd_ndr1_0 -->
% 7.12/6.62 (bnd_c7_1 X146 |
% 7.12/6.62 (ALL X147.
% 7.12/6.62 bnd_ndr1_1 X146 -->
% 7.12/6.62 (~ bnd_c6_2 X146 X147 | bnd_c9_2 X146 X147) |
% 7.12/6.62 ~ bnd_c8_2 X146 X147)) |
% 7.12/6.62 (bnd_ndr1_1 X146 & bnd_c3_2 X146 bnd_a751) &
% 7.12/6.62 bnd_c2_2 X146 bnd_a751) |
% 7.12/6.62 (ALL X148.
% 7.12/6.62 bnd_ndr1_0 -->
% 7.12/6.62 (bnd_c10_1 X148 |
% 7.12/6.62 (bnd_ndr1_1 X148 & ~ bnd_c4_2 X148 bnd_a752) &
% 7.12/6.62 ~ bnd_c7_2 X148 bnd_a752) |
% 7.12/6.62 bnd_c3_1 X148)) |
% 7.12/6.62 (((((bnd_ndr1_0 & ~ bnd_c9_1 bnd_a753) & bnd_ndr1_1 bnd_a753) &
% 7.12/6.62 ~ bnd_c1_2 bnd_a753 bnd_a754) &
% 7.12/6.62 ~ bnd_c4_2 bnd_a753 bnd_a754) &
% 7.12/6.62 bnd_c10_2 bnd_a753 bnd_a754) &
% 7.12/6.62 (ALL X149.
% 7.12/6.62 bnd_ndr1_1 bnd_a753 -->
% 7.12/6.62 ~ bnd_c4_2 bnd_a753 X149 | ~ bnd_c3_2 bnd_a753 X149))) &
% 7.12/6.62 (((ALL X150.
% 7.12/6.62 bnd_ndr1_0 -->
% 7.12/6.62 ((ALL X151.
% 7.12/6.62 bnd_ndr1_1 X150 -->
% 7.12/6.62 (~ bnd_c10_2 X150 X151 | bnd_c1_2 X150 X151) |
% 7.12/6.62 bnd_c3_2 X150 X151) |
% 7.12/6.62 bnd_c10_1 X150) |
% 7.12/6.62 ~ bnd_c5_1 X150) |
% 7.12/6.62 ~ bnd_c10_0) |
% 7.12/6.62 ((bnd_ndr1_0 & ~ bnd_c7_1 bnd_a755) & ~ bnd_c6_1 bnd_a755) &
% 7.12/6.62 (ALL X152.
% 7.12/6.62 bnd_ndr1_1 bnd_a755 -->
% 7.12/6.62 (bnd_c6_2 bnd_a755 X152 | ~ bnd_c8_2 bnd_a755 X152) |
% 7.12/6.62 ~ bnd_c7_2 bnd_a755 X152))) &
% 7.12/6.62 ((bnd_ndr1_0 & bnd_c6_1 bnd_a756) &
% 7.12/6.62 (ALL X153.
% 7.12/6.62 bnd_ndr1_1 bnd_a756 -->
% 7.12/6.62 (~ bnd_c4_2 bnd_a756 X153 | bnd_c10_2 bnd_a756 X153) |
% 7.12/6.62 bnd_c8_2 bnd_a756 X153) |
% 7.12/6.62 bnd_c7_0)) &
% 7.12/6.62 ((((bnd_ndr1_0 & bnd_c5_1 bnd_a757) & bnd_c10_1 bnd_a757) &
% 7.12/6.62 ~ bnd_c1_1 bnd_a757 |
% 7.12/6.62 bnd_c1_0) |
% 7.12/6.62 ((bnd_ndr1_0 & bnd_c1_1 bnd_a758) & bnd_c8_1 bnd_a758) &
% 7.12/6.62 bnd_c4_1 bnd_a758)) &
% 7.12/6.62 ((~ bnd_c1_0 | bnd_c7_0) |
% 7.12/6.62 (((((bnd_ndr1_0 &
% 7.12/6.62 (ALL X154.
% 7.12/6.62 bnd_ndr1_1 bnd_a759 -->
% 7.12/6.62 (~ bnd_c6_2 bnd_a759 X154 | bnd_c7_2 bnd_a759 X154) |
% 7.12/6.62 bnd_c8_2 bnd_a759 X154)) &
% 7.12/6.62 bnd_ndr1_1 bnd_a759) &
% 7.12/6.62 ~ bnd_c1_2 bnd_a759 bnd_a760) &
% 7.12/6.62 bnd_c2_2 bnd_a759 bnd_a760) &
% 7.12/6.62 ~ bnd_c5_2 bnd_a759 bnd_a760) &
% 7.12/6.62 ~ bnd_c8_1 bnd_a759))
% 15.43/14.98 Unfolded term: ~ ((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((bnd_c9_0 |
% 15.43/14.98 ((bnd_ndr1_0 & ~ bnd_c9_1 bnd_a608) &
% 15.43/14.98 ~ bnd_c10_1 bnd_a608) &
% 15.43/14.98 ~ bnd_c4_1 bnd_a608) |
% 15.43/14.98 bnd_c1_0) &
% 15.43/14.98 ((((bnd_ndr1_0 & ~ bnd_c5_1 bnd_a609) &
% 15.43/14.98 ~ bnd_c10_1 bnd_a609) &
% 15.43/14.98 ~ bnd_c8_1 bnd_a609 |
% 15.43/14.98 ~ bnd_c8_0) |
% 15.43/14.98 (ALL U.
% 15.43/14.98 bnd_ndr1_0 -->
% 15.43/14.98 ((ALL V.
% 15.43/14.98 bnd_ndr1_1 U -->
% 15.43/14.98 (~ bnd_c5_2 U V | ~ bnd_c2_2 U V) |
% 15.43/14.98 ~ bnd_c4_2 U V) |
% 15.43/14.98 ((bnd_ndr1_1 U & bnd_c3_2 U bnd_a610) &
% 15.43/14.98 bnd_c4_2 U bnd_a610) &
% 15.43/14.98 bnd_c9_2 U bnd_a610) |
% 15.43/14.98 (ALL W.
% 15.43/14.98 bnd_ndr1_1 U -->
% 15.43/14.98 (bnd_c9_2 U W | bnd_c6_2 U W) |
% 15.43/14.98 ~ bnd_c1_2 U W)))) &
% 15.43/14.98 (((((((bnd_ndr1_0 & bnd_c3_1 bnd_a611) &
% 15.43/14.98 (ALL X.
% 15.43/14.98 bnd_ndr1_1 bnd_a611 -->
% 15.43/14.98 bnd_c3_2 bnd_a611 X | ~ bnd_c8_2 bnd_a611 X)) &
% 15.43/14.98 bnd_ndr1_1 bnd_a611) &
% 15.43/14.98 ~ bnd_c1_2 bnd_a611 bnd_a612) &
% 15.43/14.98 ~ bnd_c9_2 bnd_a611 bnd_a612) &
% 15.43/14.98 ~ bnd_c8_2 bnd_a611 bnd_a612 |
% 15.43/14.98 (ALL Y.
% 15.43/14.98 bnd_ndr1_0 -->
% 15.43/14.98 (bnd_c2_1 Y | bnd_c10_1 Y) |
% 15.43/14.98 (bnd_ndr1_1 Y & bnd_c9_2 Y bnd_a613) &
% 15.43/14.98 ~ bnd_c2_2 Y bnd_a613)) |
% 15.43/14.98 ~ bnd_c5_0)) &
% 15.43/14.98 ((bnd_c9_0 |
% 15.43/14.98 (((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a614) &
% 15.43/14.98 bnd_c3_2 bnd_a614 bnd_a615) &
% 15.43/14.98 ~ bnd_c5_2 bnd_a614 bnd_a615) &
% 15.43/14.98 bnd_ndr1_1 bnd_a614) &
% 15.43/14.98 bnd_c9_2 bnd_a614 bnd_a616) &
% 15.43/14.98 bnd_c10_2 bnd_a614 bnd_a616) &
% 15.43/14.98 ~ bnd_c1_2 bnd_a614 bnd_a616) &
% 15.43/14.98 (ALL Z.
% 15.43/14.98 bnd_ndr1_1 bnd_a614 -->
% 15.43/14.98 bnd_c9_2 bnd_a614 Z | bnd_c7_2 bnd_a614 Z)) |
% 15.43/14.98 ~ bnd_c2_0)) &
% 15.43/14.98 ((((bnd_ndr1_0 & bnd_c5_1 bnd_a617) & bnd_c9_1 bnd_a617) &
% 15.43/14.98 ~ bnd_c10_1 bnd_a617 |
% 15.43/14.98 ~ bnd_c3_0) |
% 15.43/14.98 ((bnd_ndr1_0 &
% 15.43/14.98 (ALL X1.
% 15.43/14.98 bnd_ndr1_1 bnd_a618 -->
% 15.43/14.98 (~ bnd_c9_2 bnd_a618 X1 | ~ bnd_c8_2 bnd_a618 X1) |
% 15.43/14.98 bnd_c4_2 bnd_a618 X1)) &
% 15.43/14.98 (ALL X2.
% 15.43/14.98 bnd_ndr1_1 bnd_a618 -->
% 15.43/14.98 (bnd_c6_2 bnd_a618 X2 | ~ bnd_c10_2 bnd_a618 X2) |
% 15.43/14.98 bnd_c8_2 bnd_a618 X2)) &
% 15.43/14.98 bnd_c3_1 bnd_a618)) &
% 15.43/14.98 ((bnd_c3_0 |
% 15.43/14.98 (ALL X3.
% 15.43/14.98 bnd_ndr1_0 -->
% 15.43/14.98 ((ALL X4.
% 15.43/14.98 bnd_ndr1_1 X3 -->
% 15.43/14.98 ~ bnd_c9_2 X3 X4 | bnd_c4_2 X3 X4) |
% 15.43/14.98 bnd_c7_1 X3) |
% 15.43/14.98 (bnd_ndr1_1 X3 & ~ bnd_c3_2 X3 bnd_a619) &
% 15.43/14.98 bnd_c7_2 X3 bnd_a619)) |
% 15.43/14.98 (ALL X5.
% 15.43/14.98 bnd_ndr1_0 -->
% 15.43/14.98 (~ bnd_c9_1 X5 | ~ bnd_c5_1 X5) | bnd_c2_1 X5))) &
% 15.43/14.98 (((ALL X6.
% 15.43/14.98 bnd_ndr1_0 -->
% 15.43/14.98 (ALL X7.
% 15.43/14.98 bnd_ndr1_1 X6 -->
% 15.43/14.98 (bnd_c1_2 X6 X7 | ~ bnd_c3_2 X6 X7) |
% 15.43/14.98 bnd_c6_2 X6 X7) |
% 15.43/14.98 ((bnd_ndr1_1 X6 & ~ bnd_c4_2 X6 bnd_a620) &
% 15.43/14.98 bnd_c1_2 X6 bnd_a620) &
% 15.43/14.98 bnd_c5_2 X6 bnd_a620) |
% 15.43/14.98 bnd_c9_0) |
% 15.43/14.98 (ALL X8.
% 15.43/14.98 bnd_ndr1_0 -->
% 15.43/14.98 ((ALL X9.
% 15.43/14.98 bnd_ndr1_1 X8 -->
% 15.43/14.98 (bnd_c9_2 X8 X9 | ~ bnd_c3_2 X8 X9) |
% 15.43/14.98 ~ bnd_c10_2 X8 X9) |
% 15.43/14.98 ~ bnd_c5_1 X8) |
% 15.43/14.98 (ALL X10.
% 15.43/14.98 bnd_ndr1_1 X8 -->
% 15.43/14.98 (~ bnd_c6_2 X8 X10 | bnd_c7_2 X8 X10) |
% 15.43/14.98 ~ bnd_c4_2 X8 X10)))) &
% 15.43/14.98 ((~ bnd_c9_0 | ~ bnd_c5_0) |
% 15.43/14.98 (ALL X11.
% 15.43/14.98 bnd_ndr1_0 -->
% 15.43/14.98 (~ bnd_c8_1 X11 | ~ bnd_c3_1 X11) | bnd_c1_1 X11))) &
% 15.43/14.98 ((((bnd_ndr1_0 & ~ bnd_c3_1 bnd_a621) & bnd_c1_1 bnd_a621) &
% 15.43/14.98 (ALL X12.
% 15.43/14.98 bnd_ndr1_1 bnd_a621 -->
% 15.43/14.98 (~ bnd_c2_2 bnd_a621 X12 | bnd_c1_2 bnd_a621 X12) |
% 15.43/14.98 bnd_c6_2 bnd_a621 X12) |
% 15.43/14.98 ~ bnd_c9_0) |
% 15.43/14.98 (((((bnd_ndr1_0 & bnd_c4_1 bnd_a622) & ~ bnd_c8_1 bnd_a622) &
% 15.43/14.98 bnd_ndr1_1 bnd_a622) &
% 15.43/14.98 bnd_c6_2 bnd_a622 bnd_a623) &
% 15.43/14.98 bnd_c1_2 bnd_a622 bnd_a623) &
% 15.43/14.98 bnd_c2_2 bnd_a622 bnd_a623)) &
% 15.43/14.98 (((ALL X13.
% 15.43/14.98 bnd_ndr1_0 -->
% 15.43/14.98 ((bnd_ndr1_1 X13 & bnd_c5_2 X13 bnd_a624) &
% 15.43/14.98 ~ bnd_c9_2 X13 bnd_a624 |
% 15.43/14.98 bnd_c4_1 X13) |
% 15.43/14.98 bnd_c2_1 X13) |
% 15.43/14.98 bnd_c8_0) |
% 15.43/14.98 ((((bnd_ndr1_0 & bnd_c1_1 bnd_a625) & bnd_ndr1_1 bnd_a625) &
% 15.43/14.98 bnd_c3_2 bnd_a625 bnd_a626) &
% 15.43/14.98 bnd_c6_2 bnd_a625 bnd_a626) &
% 15.43/14.98 bnd_c3_1 bnd_a625)) &
% 15.43/14.98 (((ALL X14.
% 15.43/14.98 bnd_ndr1_0 -->
% 15.43/14.98 (~ bnd_c8_1 X14 |
% 15.43/14.98 ((bnd_ndr1_1 X14 & ~ bnd_c10_2 X14 bnd_a627) &
% 15.43/14.98 ~ bnd_c5_2 X14 bnd_a627) &
% 15.43/14.98 ~ bnd_c2_2 X14 bnd_a627) |
% 15.43/14.98 ~ bnd_c7_1 X14) |
% 15.43/14.98 ~ bnd_c7_0) |
% 15.43/14.98 (((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a628) &
% 15.43/14.98 ~ bnd_c5_2 bnd_a628 bnd_a629) &
% 15.43/14.98 ~ bnd_c8_2 bnd_a628 bnd_a629) &
% 15.43/14.98 bnd_c3_2 bnd_a628 bnd_a629) &
% 15.43/14.98 bnd_c1_1 bnd_a628) &
% 15.43/14.98 ~ bnd_c7_1 bnd_a628)) &
% 15.43/14.98 ((bnd_c8_0 |
% 15.43/14.98 ((bnd_ndr1_0 & bnd_c7_1 bnd_a630) & ~ bnd_c6_1 bnd_a630) &
% 15.43/14.98 bnd_c9_1 bnd_a630) |
% 15.43/14.98 bnd_c2_0)) &
% 15.43/14.98 ((bnd_c9_0 | ~ bnd_c5_0) | ~ bnd_c6_0)) &
% 15.43/14.98 ((bnd_c7_0 | bnd_c2_0) |
% 15.43/14.98 (ALL X15.
% 15.43/14.98 bnd_ndr1_0 -->
% 15.43/14.98 (bnd_c10_1 X15 |
% 15.43/14.98 (ALL X16.
% 15.43/14.98 bnd_ndr1_1 X15 -->
% 15.43/14.98 (~ bnd_c3_2 X15 X16 | bnd_c5_2 X15 X16) |
% 15.43/14.98 ~ bnd_c6_2 X15 X16)) |
% 15.43/14.98 bnd_c3_1 X15))) &
% 15.43/14.98 (((((((bnd_ndr1_0 &
% 15.43/14.98 (ALL X17.
% 15.43/14.98 bnd_ndr1_1 bnd_a631 -->
% 15.43/14.98 (~ bnd_c1_2 bnd_a631 X17 | ~ bnd_c6_2 bnd_a631 X17) |
% 15.43/14.98 bnd_c7_2 bnd_a631 X17)) &
% 15.43/14.98 bnd_ndr1_1 bnd_a631) &
% 15.43/14.98 bnd_c10_2 bnd_a631 bnd_a632) &
% 15.43/14.98 bnd_c8_2 bnd_a631 bnd_a632) &
% 15.43/14.98 ~ bnd_c2_2 bnd_a631 bnd_a632) &
% 15.43/14.98 bnd_c5_1 bnd_a631 |
% 15.43/14.98 ((((bnd_ndr1_0 & bnd_c10_1 bnd_a633) & bnd_ndr1_1 bnd_a633) &
% 15.43/14.98 bnd_c9_2 bnd_a633 bnd_a634) &
% 15.43/14.98 ~ bnd_c10_2 bnd_a633 bnd_a634) &
% 15.43/14.98 ~ bnd_c2_1 bnd_a633) |
% 15.43/14.98 (ALL X18.
% 15.43/14.98 bnd_ndr1_0 -->
% 15.43/14.98 ((ALL X19.
% 15.43/14.98 bnd_ndr1_1 X18 -->
% 15.43/14.98 (~ bnd_c8_2 X18 X19 | bnd_c4_2 X18 X19) |
% 15.43/14.98 bnd_c1_2 X18 X19) |
% 15.43/14.98 ~ bnd_c6_1 X18) |
% 15.43/14.98 ~ bnd_c8_1 X18))) &
% 15.43/14.98 (((ALL X20.
% 15.43/14.98 bnd_ndr1_0 -->
% 15.43/14.98 ((ALL X21.
% 15.43/14.98 bnd_ndr1_1 X20 -->
% 15.43/14.98 (bnd_c2_2 X20 X21 | ~ bnd_c9_2 X20 X21) |
% 15.43/14.98 ~ bnd_c8_2 X20 X21) |
% 15.43/14.98 ~ bnd_c4_1 X20) |
% 15.43/14.98 ~ bnd_c3_1 X20) |
% 15.43/14.98 (ALL X22.
% 15.43/14.98 bnd_ndr1_0 -->
% 15.43/14.98 (((bnd_ndr1_1 X22 & bnd_c8_2 X22 bnd_a635) &
% 15.43/14.98 bnd_c3_2 X22 bnd_a635) &
% 15.43/14.98 ~ bnd_c2_2 X22 bnd_a635 |
% 15.43/14.98 ((bnd_ndr1_1 X22 & ~ bnd_c4_2 X22 bnd_a636) &
% 15.43/14.98 bnd_c10_2 X22 bnd_a636) &
% 15.43/14.98 bnd_c8_2 X22 bnd_a636) |
% 15.43/14.98 (ALL X23.
% 15.43/14.98 bnd_ndr1_1 X22 -->
% 15.43/14.98 (~ bnd_c10_2 X22 X23 | bnd_c5_2 X22 X23) |
% 15.43/14.98 bnd_c8_2 X22 X23))) |
% 15.43/14.98 bnd_c3_0)) &
% 15.43/14.98 (((ALL X24.
% 15.43/14.98 bnd_ndr1_0 -->
% 15.43/14.98 (~ bnd_c4_1 X24 | ~ bnd_c5_1 X24) | ~ bnd_c6_1 X24) |
% 15.43/14.98 ((bnd_ndr1_0 & bnd_c8_1 bnd_a637) & bnd_c5_1 bnd_a637) &
% 15.43/14.98 bnd_c3_1 bnd_a637) |
% 15.43/14.98 ~ bnd_c2_0)) &
% 15.43/14.98 ((bnd_c8_0 | ~ bnd_c2_0) |
% 15.43/14.98 (ALL X25.
% 15.43/14.98 bnd_ndr1_0 -->
% 15.43/14.98 (~ bnd_c1_1 X25 |
% 15.43/14.98 (ALL X26.
% 15.43/14.98 bnd_ndr1_1 X25 --> bnd_c6_2 X25 X26 | ~ bnd_c3_2 X25 X26)) |
% 15.43/14.98 (bnd_ndr1_1 X25 & ~ bnd_c2_2 X25 bnd_a638) &
% 15.43/14.98 bnd_c1_2 X25 bnd_a638))) &
% 15.43/14.98 (bnd_c2_0 | bnd_c9_0)) &
% 15.43/14.98 ((bnd_c5_0 | bnd_c8_0) |
% 15.43/14.98 (ALL X27.
% 15.43/14.98 bnd_ndr1_0 -->
% 15.43/14.98 ((ALL X28.
% 15.43/14.98 bnd_ndr1_1 X27 -->
% 15.43/14.98 (~ bnd_c8_2 X27 X28 | ~ bnd_c9_2 X27 X28) |
% 15.43/14.98 ~ bnd_c1_2 X27 X28) |
% 15.43/14.98 ~ bnd_c3_1 X27) |
% 15.43/14.98 (ALL X29.
% 15.43/14.98 bnd_ndr1_1 X27 --> bnd_c7_2 X27 X29 | ~ bnd_c10_2 X27 X29)))) &
% 15.43/14.98 ((bnd_c2_0 |
% 15.43/14.98 (ALL X30.
% 15.43/14.98 bnd_ndr1_0 -->
% 15.43/14.98 (bnd_c10_1 X30 |
% 15.43/14.98 (ALL X31.
% 15.43/14.98 bnd_ndr1_1 X30 -->
% 15.43/14.98 (~ bnd_c3_2 X30 X31 | ~ bnd_c6_2 X30 X31) |
% 15.43/14.98 ~ bnd_c8_2 X30 X31)) |
% 15.43/14.98 (ALL X32.
% 15.43/14.98 bnd_ndr1_1 X30 -->
% 15.43/14.98 (~ bnd_c10_2 X30 X32 | ~ bnd_c3_2 X30 X32) |
% 15.43/14.98 ~ bnd_c9_2 X30 X32))) |
% 15.43/14.98 (((((bnd_ndr1_0 & ~ bnd_c2_1 bnd_a639) & ~ bnd_c8_1 bnd_a639) &
% 15.43/14.98 bnd_ndr1_1 bnd_a639) &
% 15.43/14.98 ~ bnd_c3_2 bnd_a639 bnd_a640) &
% 15.43/14.98 bnd_c8_2 bnd_a639 bnd_a640) &
% 15.43/14.98 ~ bnd_c1_2 bnd_a639 bnd_a640)) &
% 15.43/14.98 ((((((((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a641) &
% 15.43/14.98 bnd_c8_2 bnd_a641 bnd_a642) &
% 15.43/14.98 bnd_c6_2 bnd_a641 bnd_a642) &
% 15.43/14.98 bnd_c2_2 bnd_a641 bnd_a642) &
% 15.43/14.98 bnd_ndr1_1 bnd_a641) &
% 15.43/14.98 ~ bnd_c5_2 bnd_a641 bnd_a643) &
% 15.43/14.98 ~ bnd_c8_2 bnd_a641 bnd_a643) &
% 15.43/14.98 bnd_ndr1_1 bnd_a641) &
% 15.43/14.98 ~ bnd_c8_2 bnd_a641 bnd_a644) &
% 15.43/14.98 ~ bnd_c5_2 bnd_a641 bnd_a644) &
% 15.43/14.98 ~ bnd_c9_2 bnd_a641 bnd_a644 |
% 15.43/14.98 ((((((((bnd_ndr1_0 &
% 15.43/14.98 (ALL X33.
% 15.43/14.98 bnd_ndr1_1 bnd_a645 -->
% 15.43/14.98 (~ bnd_c2_2 bnd_a645 X33 | ~ bnd_c5_2 bnd_a645 X33) |
% 15.43/14.98 ~ bnd_c9_2 bnd_a645 X33)) &
% 15.43/14.98 bnd_ndr1_1 bnd_a645) &
% 15.43/14.98 ~ bnd_c9_2 bnd_a645 bnd_a646) &
% 15.43/14.98 ~ bnd_c3_2 bnd_a645 bnd_a646) &
% 15.43/14.98 ~ bnd_c5_2 bnd_a645 bnd_a646) &
% 15.43/14.98 bnd_ndr1_1 bnd_a645) &
% 15.43/14.98 ~ bnd_c9_2 bnd_a645 bnd_a647) &
% 15.43/14.98 ~ bnd_c3_2 bnd_a645 bnd_a647) &
% 15.43/14.98 bnd_c5_2 bnd_a645 bnd_a647) |
% 15.43/14.98 bnd_c10_0)) &
% 15.43/14.98 ((((bnd_ndr1_0 &
% 15.43/14.98 (ALL X34.
% 15.43/14.98 bnd_ndr1_1 bnd_a648 -->
% 15.43/14.98 ~ bnd_c7_2 bnd_a648 X34 | ~ bnd_c3_2 bnd_a648 X34)) &
% 15.43/14.98 ~ bnd_c7_1 bnd_a648) &
% 15.43/14.98 bnd_c3_1 bnd_a648 |
% 15.43/14.98 (ALL X35.
% 15.43/14.98 bnd_ndr1_0 -->
% 15.43/14.98 (~ bnd_c9_1 X35 | bnd_c2_1 X35) |
% 15.43/14.98 (ALL X36.
% 15.43/14.98 bnd_ndr1_1 X35 -->
% 15.43/14.98 (~ bnd_c10_2 X35 X36 | bnd_c5_2 X35 X36) | bnd_c2_2 X35 X36))) |
% 15.43/14.98 bnd_c6_0)) &
% 15.43/14.98 ((((bnd_ndr1_0 & ~ bnd_c1_1 bnd_a649) &
% 15.43/14.98 bnd_c9_1 bnd_a649) &
% 15.43/14.98 ~ bnd_c8_1 bnd_a649 |
% 15.43/14.98 (ALL X37.
% 15.43/14.98 bnd_ndr1_0 -->
% 15.43/14.98 (((bnd_ndr1_1 X37 & bnd_c7_2 X37 bnd_a650) & bnd_c1_2 X37 bnd_a650) &
% 15.43/14.98 bnd_c5_2 X37 bnd_a650 |
% 15.43/14.98 ~ bnd_c1_1 X37) |
% 15.43/14.98 bnd_c7_1 X37)) |
% 15.43/14.98 ~ bnd_c5_0)) &
% 15.43/14.98 ((((bnd_ndr1_0 & ~ bnd_c5_1 bnd_a651) &
% 15.43/14.98 ~ bnd_c9_1 bnd_a651) &
% 15.43/14.98 ~ bnd_c7_1 bnd_a651 |
% 15.43/14.98 (((((bnd_ndr1_0 &
% 15.43/14.98 ~ bnd_c2_1 bnd_a652) &
% 15.43/14.98 bnd_ndr1_1 bnd_a652) &
% 15.43/14.98 bnd_c1_2 bnd_a652 bnd_a653) &
% 15.43/14.98 ~ bnd_c5_2 bnd_a652 bnd_a653) &
% 15.43/14.98 ~ bnd_c10_2 bnd_a652 bnd_a653) &
% 15.43/14.98 ~ bnd_c8_1 bnd_a652) |
% 15.43/14.98 (ALL X38.
% 15.43/14.98 bnd_ndr1_0 -->
% 15.43/14.98 ((ALL X39.
% 15.43/14.98 bnd_ndr1_1 X38 -->
% 15.43/14.98 (~ bnd_c10_2 X38 X39 | ~ bnd_c3_2 X38 X39) | bnd_c8_2 X38 X39) |
% 15.43/14.98 (ALL X40.
% 15.43/14.98 bnd_ndr1_1 X38 -->
% 15.43/14.98 (bnd_c6_2 X38 X40 | bnd_c4_2 X38 X40) | ~ bnd_c3_2 X38 X40)) |
% 15.43/14.98 bnd_c8_1 X38))) &
% 15.43/14.98 ((ALL X41.
% 15.43/14.98 bnd_ndr1_0 -->
% 15.43/14.98 (~ bnd_c4_1 X41 |
% 15.43/14.98 (ALL X42.
% 15.43/14.98 bnd_ndr1_1 X41 -->
% 15.43/14.98 (~ bnd_c2_2 X41 X42 | bnd_c10_2 X41 X42) | bnd_c6_2 X41 X42)) |
% 15.43/14.98 ((bnd_ndr1_1 X41 & bnd_c1_2 X41 bnd_a654) & ~ bnd_c9_2 X41 bnd_a654) &
% 15.43/14.98 ~ bnd_c4_2 X41 bnd_a654) |
% 15.43/14.98 bnd_c9_0)) &
% 15.43/14.98 ((((bnd_ndr1_0 & bnd_c2_1 bnd_a655) &
% 15.43/14.98 (ALL X43.
% 15.43/14.98 bnd_ndr1_1 bnd_a655 -->
% 15.43/14.98 (~ bnd_c2_2 bnd_a655 X43 | ~ bnd_c10_2 bnd_a655 X43) |
% 15.43/14.98 bnd_c3_2 bnd_a655 X43)) &
% 15.43/14.98 (ALL X44.
% 15.43/14.98 bnd_ndr1_1 bnd_a655 -->
% 15.43/14.98 (bnd_c9_2 bnd_a655 X44 | bnd_c6_2 bnd_a655 X44) | bnd_c3_2 bnd_a655 X44) |
% 15.43/14.98 ((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a656) &
% 15.43/14.98 bnd_c6_2 bnd_a656 bnd_a657) &
% 15.43/14.98 bnd_c3_2 bnd_a656 bnd_a657) &
% 15.43/14.98 bnd_c7_1 bnd_a656) &
% 15.43/14.98 bnd_c1_1 bnd_a656) |
% 15.43/14.98 ~ bnd_c3_0)) &
% 15.43/14.98 ((bnd_c3_0 | ~ bnd_c6_0) | ~ bnd_c8_0)) &
% 15.43/14.98 (~ bnd_c8_0 |
% 15.43/14.98 (bnd_ndr1_0 & bnd_c7_1 bnd_a658) &
% 15.43/14.98 (ALL X45.
% 15.43/14.98 bnd_ndr1_1 bnd_a658 -->
% 15.43/14.98 (~ bnd_c5_2 bnd_a658 X45 |
% 15.43/14.98 ~ bnd_c3_2 bnd_a658 X45) |
% 15.43/14.98 ~ bnd_c4_2 bnd_a658 X45))) &
% 15.43/14.98 (((ALL X46.
% 15.43/14.98 bnd_ndr1_0 -->
% 15.43/14.98 (bnd_c7_1 X46 |
% 15.43/14.98 ((bnd_ndr1_1 X46 &
% 15.43/14.98 ~ bnd_c8_2 X46 bnd_a659) &
% 15.43/14.98 ~ bnd_c5_2 X46 bnd_a659) &
% 15.43/14.98 ~ bnd_c7_2 X46 bnd_a659) |
% 15.43/14.98 ~ bnd_c4_1 X46) |
% 15.43/14.98 bnd_c6_0) |
% 15.43/14.98 (ALL X47.
% 15.43/14.98 bnd_ndr1_0 -->
% 15.43/14.98 (~ bnd_c1_1 X47 | bnd_c5_1 X47) |
% 15.43/14.98 (ALL X48.
% 15.43/14.98 bnd_ndr1_1 X47 -->
% 15.43/14.98 (bnd_c8_2 X47 X48 | bnd_c6_2 X47 X48) | bnd_c4_2 X47 X48)))) &
% 15.43/14.98 (((ALL X49.
% 15.43/14.98 bnd_ndr1_0 -->
% 15.43/14.98 (ALL X50.
% 15.43/14.98 bnd_ndr1_1 X49 -->
% 15.43/14.98 (bnd_c1_2 X49 X50 | ~ bnd_c10_2 X49 X50) | bnd_c5_2 X49 X50) |
% 15.43/14.98 bnd_c8_1 X49) |
% 15.43/14.98 ~ bnd_c3_0) |
% 15.43/14.98 bnd_c9_0)) &
% 15.43/14.98 (((bnd_ndr1_0 & bnd_c5_1 bnd_a660) &
% 15.43/14.98 ~ bnd_c10_1 bnd_a660) &
% 15.43/14.98 ~ bnd_c6_1 bnd_a660 |
% 15.43/14.98 (ALL X51.
% 15.43/14.98 bnd_ndr1_0 -->
% 15.43/14.98 (((bnd_ndr1_1 X51 &
% 15.43/14.98 ~ bnd_c1_2 X51 bnd_a661) &
% 15.43/14.98 bnd_c5_2 X51 bnd_a661) &
% 15.43/14.98 ~ bnd_c6_2 X51 bnd_a661 |
% 15.43/14.98 ~ bnd_c8_1 X51) |
% 15.43/14.98 ((bnd_ndr1_1 X51 &
% 15.43/14.98 ~ bnd_c6_2 X51 bnd_a662) &
% 15.43/14.98 bnd_c10_2 X51 bnd_a662) &
% 15.43/14.98 ~ bnd_c2_2 X51 bnd_a662))) &
% 15.43/14.98 ((((bnd_ndr1_0 & bnd_c7_1 bnd_a663) &
% 15.43/14.98 bnd_c1_1 bnd_a663) &
% 15.43/14.98 (ALL X52.
% 15.43/14.98 bnd_ndr1_1 bnd_a663 -->
% 15.43/14.98 (bnd_c1_2 bnd_a663 X52 |
% 15.43/14.98 bnd_c4_2 bnd_a663 X52) |
% 15.43/14.98 ~ bnd_c3_2 bnd_a663 X52) |
% 15.43/14.98 (ALL X53.
% 15.43/14.98 bnd_ndr1_0 -->
% 15.43/14.98 (~ bnd_c10_1 X53 |
% 15.43/14.98 (ALL X54.
% 15.43/14.98 bnd_ndr1_1 X53 -->
% 15.43/14.98 (bnd_c1_2 X53 X54 | ~ bnd_c7_2 X53 X54) | ~ bnd_c8_2 X53 X54)) |
% 15.43/14.98 ~ bnd_c9_1 X53)) |
% 15.43/14.98 (ALL X55.
% 15.43/14.98 bnd_ndr1_0 -->
% 15.43/14.98 ~ bnd_c9_1 X55 |
% 15.43/14.98 ((bnd_ndr1_1 X55 & bnd_c5_2 X55 bnd_a664) &
% 15.43/14.98 bnd_c2_2 X55 bnd_a664) &
% 15.43/14.98 bnd_c7_2 X55 bnd_a664))) &
% 15.43/14.98 (~ bnd_c10_0 | bnd_c3_0)) &
% 15.43/14.98 (((ALL X56.
% 15.43/14.98 bnd_ndr1_0 -->
% 15.43/14.98 (bnd_c2_1 X56 |
% 15.43/14.98 (ALL X57.
% 15.43/14.98 bnd_ndr1_1 X56 -->
% 15.43/14.98 (~ bnd_c9_2 X56 X57 |
% 15.43/14.98 ~ bnd_c10_2 X56 X57) |
% 15.43/14.98 ~ bnd_c1_2 X56 X57)) |
% 15.43/14.98 ~ bnd_c6_1 X56) |
% 15.43/14.98 ~ bnd_c4_0) |
% 15.43/14.98 ~ bnd_c3_0)) &
% 15.43/14.98 ((bnd_c6_0 |
% 15.43/14.98 ((bnd_ndr1_0 &
% 15.43/14.98 (ALL X58.
% 15.43/14.98 bnd_ndr1_1 bnd_a665 -->
% 15.43/14.98 (~ bnd_c1_2 bnd_a665 X58 |
% 15.43/14.98 bnd_c7_2 bnd_a665 X58) |
% 15.43/14.98 ~ bnd_c4_2 bnd_a665 X58)) &
% 15.43/14.98 ~ bnd_c2_1 bnd_a665) &
% 15.43/14.98 (ALL X59.
% 15.43/14.98 bnd_ndr1_1 bnd_a665 -->
% 15.43/14.98 bnd_c4_2 bnd_a665 X59 |
% 15.43/14.98 bnd_c9_2 bnd_a665 X59)) |
% 15.43/14.98 (ALL X60.
% 15.43/14.98 bnd_ndr1_0 -->
% 15.43/14.98 (bnd_c7_1 X60 | ~ bnd_c3_1 X60) |
% 15.43/14.98 ((bnd_ndr1_1 X60 & bnd_c8_2 X60 bnd_a666) &
% 15.43/14.98 ~ bnd_c7_2 X60 bnd_a666) &
% 15.43/14.98 bnd_c3_2 X60 bnd_a666))) &
% 15.43/14.98 (((ALL X61.
% 15.43/14.98 bnd_ndr1_0 -->
% 15.43/14.98 (((bnd_ndr1_1 X61 & bnd_c1_2 X61 bnd_a667) &
% 15.43/14.98 ~ bnd_c10_2 X61 bnd_a667) &
% 15.43/14.98 bnd_c6_2 X61 bnd_a667 |
% 15.43/14.98 (ALL X62.
% 15.43/14.98 bnd_ndr1_1 X61 -->
% 15.43/14.98 (bnd_c8_2 X61 X62 | ~ bnd_c2_2 X61 X62) |
% 15.43/14.98 bnd_c3_2 X61 X62)) |
% 15.43/14.98 (ALL X63.
% 15.43/14.98 bnd_ndr1_1 X61 -->
% 15.43/14.98 (bnd_c1_2 X61 X63 | ~ bnd_c8_2 X61 X63) |
% 15.43/14.98 bnd_c5_2 X61 X63)) |
% 15.43/14.98 ~ bnd_c4_0) |
% 15.43/14.98 ~ bnd_c5_0)) &
% 15.43/14.98 ((((bnd_ndr1_0 &
% 15.43/14.98 (ALL X64.
% 15.43/14.98 bnd_ndr1_1 bnd_a668 -->
% 15.43/14.98 ~ bnd_c4_2 bnd_a668 X64 |
% 15.43/14.98 bnd_c1_2 bnd_a668 X64)) &
% 15.43/14.98 (ALL X65.
% 15.43/14.98 bnd_ndr1_1 bnd_a668 -->
% 15.43/14.98 (bnd_c2_2 bnd_a668 X65 |
% 15.43/14.98 ~ bnd_c8_2 bnd_a668 X65) |
% 15.43/14.98 ~ bnd_c3_2 bnd_a668 X65)) &
% 15.43/14.98 ~ bnd_c9_1 bnd_a668 |
% 15.43/14.98 bnd_c5_0) |
% 15.43/14.98 ((bnd_ndr1_0 &
% 15.43/14.98 (ALL X66.
% 15.43/14.98 bnd_ndr1_1 bnd_a669 -->
% 15.43/14.98 bnd_c6_2 bnd_a669 X66 |
% 15.43/14.98 bnd_c1_2 bnd_a669 X66)) &
% 15.43/14.98 ~ bnd_c2_1 bnd_a669) &
% 15.43/14.98 (ALL X67.
% 15.43/14.98 bnd_ndr1_1 bnd_a669 -->
% 15.43/14.98 (bnd_c4_2 bnd_a669 X67 | bnd_c5_2 bnd_a669 X67) |
% 15.43/14.98 bnd_c3_2 bnd_a669 X67))) &
% 15.43/14.98 ((~ bnd_c7_0 | ~ bnd_c2_0) | ~ bnd_c1_0)) &
% 15.43/14.98 ((((bnd_ndr1_0 & ~ bnd_c3_1 bnd_a670) &
% 15.43/14.98 bnd_c9_1 bnd_a670) &
% 15.43/14.98 bnd_c8_1 bnd_a670 |
% 15.43/14.98 (ALL X68.
% 15.43/14.98 bnd_ndr1_0 -->
% 15.43/14.98 (~ bnd_c3_1 X68 |
% 15.43/14.98 ((bnd_ndr1_1 X68 & bnd_c8_2 X68 bnd_a671) &
% 15.43/14.98 ~ bnd_c1_2 X68 bnd_a671) &
% 15.43/14.98 bnd_c2_2 X68 bnd_a671) |
% 15.43/14.98 (ALL X69.
% 15.43/14.98 bnd_ndr1_1 X68 -->
% 15.43/14.98 (bnd_c10_2 X68 X69 | bnd_c7_2 X68 X69) |
% 15.43/14.98 bnd_c3_2 X68 X69))) |
% 15.43/14.98 ~ bnd_c9_0)) &
% 15.43/14.98 ((((bnd_ndr1_0 & bnd_c7_1 bnd_a672) &
% 15.43/14.98 ~ bnd_c6_1 bnd_a672) &
% 15.43/14.98 bnd_c8_1 bnd_a672 |
% 15.43/14.98 bnd_c10_0) |
% 15.43/14.98 ~ bnd_c2_0)) &
% 15.43/14.98 ((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a673) &
% 15.43/14.98 ~ bnd_c4_2 bnd_a673 bnd_a674) &
% 15.43/14.98 bnd_c3_2 bnd_a673 bnd_a674) &
% 15.43/14.98 bnd_c9_1 bnd_a673) &
% 15.43/14.98 (ALL X70.
% 15.43/14.98 bnd_ndr1_1 bnd_a673 -->
% 15.43/14.98 (~ bnd_c6_2 bnd_a673 X70 |
% 15.43/14.98 ~ bnd_c3_2 bnd_a673 X70) |
% 15.43/14.98 bnd_c4_2 bnd_a673 X70) |
% 15.43/14.98 (ALL X71.
% 15.43/14.98 bnd_ndr1_0 -->
% 15.43/14.98 ((ALL X72.
% 15.43/14.98 bnd_ndr1_1 X71 -->
% 15.43/14.98 (bnd_c3_2 X71 X72 | bnd_c6_2 X71 X72) |
% 15.43/14.98 ~ bnd_c2_2 X71 X72) |
% 15.43/14.98 ~ bnd_c3_1 X71) |
% 15.43/14.98 ~ bnd_c6_1 X71)) |
% 15.43/14.98 bnd_c9_0)) &
% 15.43/14.98 ((~ bnd_c9_0 | ~ bnd_c7_0) |
% 15.43/14.98 (ALL X73.
% 15.43/14.98 bnd_ndr1_0 -->
% 15.43/14.98 (((bnd_ndr1_1 X73 & bnd_c5_2 X73 bnd_a675) &
% 15.43/14.98 ~ bnd_c1_2 X73 bnd_a675) &
% 15.43/14.98 bnd_c8_2 X73 bnd_a675 |
% 15.43/14.98 ((bnd_ndr1_1 X73 & ~ bnd_c5_2 X73 bnd_a676) &
% 15.43/14.98 ~ bnd_c9_2 X73 bnd_a676) &
% 15.43/14.98 bnd_c8_2 X73 bnd_a676) |
% 15.43/14.98 ((bnd_ndr1_1 X73 & bnd_c5_2 X73 bnd_a677) &
% 15.43/14.98 ~ bnd_c9_2 X73 bnd_a677) &
% 15.43/14.98 bnd_c2_2 X73 bnd_a677))) &
% 15.43/14.98 ((~ bnd_c3_0 |
% 15.43/14.98 (ALL X74.
% 15.43/14.98 bnd_ndr1_0 -->
% 15.43/14.98 (~ bnd_c6_1 X74 | ~ bnd_c2_1 X74) | bnd_c3_1 X74)) |
% 15.43/14.98 ~ bnd_c10_0)) &
% 15.43/14.98 ((bnd_c10_0 | bnd_c9_0) | bnd_c2_0)) &
% 15.43/14.98 ((~ bnd_c9_0 | bnd_c1_0) | bnd_c8_0)) &
% 15.43/14.98 (bnd_c3_0 | bnd_c7_0)) &
% 15.43/14.98 (bnd_c3_0 |
% 15.43/14.98 (ALL X75.
% 15.43/14.98 bnd_ndr1_0 -->
% 15.43/14.98 (((bnd_ndr1_1 X75 & ~ bnd_c8_2 X75 bnd_a678) &
% 15.43/14.98 bnd_c1_2 X75 bnd_a678) &
% 15.43/14.98 ~ bnd_c6_2 X75 bnd_a678 |
% 15.43/14.98 (ALL X76.
% 15.43/14.98 bnd_ndr1_1 X75 -->
% 15.43/14.98 (~ bnd_c8_2 X75 X76 | ~ bnd_c2_2 X75 X76) |
% 15.43/14.98 bnd_c1_2 X75 X76)) |
% 15.43/14.98 bnd_c7_1 X75))) &
% 15.43/14.98 (~ bnd_c1_0 | bnd_c8_0)) &
% 15.43/14.98 ((bnd_c7_0 | ~ bnd_c6_0) | bnd_c10_0)) &
% 15.43/14.98 ((((((((((bnd_ndr1_0 &
% 15.43/14.98 (ALL X77.
% 15.43/14.98 bnd_ndr1_1 bnd_a679 -->
% 15.43/14.98 (bnd_c10_2 bnd_a679 X77 | bnd_c4_2 bnd_a679 X77) |
% 15.43/14.98 ~ bnd_c9_2 bnd_a679 X77)) &
% 15.43/14.98 bnd_ndr1_1 bnd_a679) &
% 15.43/14.98 ~ bnd_c1_2 bnd_a679 bnd_a680) &
% 15.43/14.98 bnd_c8_2 bnd_a679 bnd_a680) &
% 15.43/14.98 bnd_c9_2 bnd_a679 bnd_a680) &
% 15.43/14.98 bnd_ndr1_1 bnd_a679) &
% 15.43/14.98 bnd_c1_2 bnd_a679 bnd_a681) &
% 15.43/14.98 ~ bnd_c5_2 bnd_a679 bnd_a681) &
% 15.43/14.98 ~ bnd_c9_2 bnd_a679 bnd_a681 |
% 15.43/14.98 bnd_c8_0) |
% 15.43/14.98 ~ bnd_c4_0)) &
% 15.43/14.98 ((bnd_c3_0 |
% 15.43/14.98 (ALL X78. bnd_ndr1_0 --> ~ bnd_c4_1 X78 | bnd_c7_1 X78)) |
% 15.43/14.98 (ALL X79.
% 15.43/14.98 bnd_ndr1_0 -->
% 15.43/14.98 (((bnd_ndr1_1 X79 & ~ bnd_c10_2 X79 bnd_a682) &
% 15.43/14.98 bnd_c3_2 X79 bnd_a682) &
% 15.43/14.98 ~ bnd_c5_2 X79 bnd_a682 |
% 15.43/14.98 ((bnd_ndr1_1 X79 & bnd_c6_2 X79 bnd_a683) &
% 15.43/14.98 ~ bnd_c4_2 X79 bnd_a683) &
% 15.43/14.98 bnd_c5_2 X79 bnd_a683) |
% 15.43/14.98 ~ bnd_c9_1 X79))) &
% 15.43/14.98 (((ALL X80.
% 15.43/14.98 bnd_ndr1_0 -->
% 15.43/14.98 (~ bnd_c3_1 X80 | bnd_c1_1 X80) | bnd_c4_1 X80) |
% 15.43/14.98 bnd_c8_0) |
% 15.43/14.98 ~ bnd_c9_0)) &
% 15.43/14.98 (((ALL X81.
% 15.43/14.98 bnd_ndr1_0 -->
% 15.43/14.98 (((bnd_ndr1_1 X81 & bnd_c6_2 X81 bnd_a684) &
% 15.43/14.98 bnd_c1_2 X81 bnd_a684) &
% 15.43/14.98 bnd_c7_2 X81 bnd_a684 |
% 15.43/14.98 ((bnd_ndr1_1 X81 & bnd_c10_2 X81 bnd_a685) &
% 15.43/14.98 bnd_c3_2 X81 bnd_a685) &
% 15.43/14.98 ~ bnd_c6_2 X81 bnd_a685) |
% 15.43/14.98 ~ bnd_c8_1 X81) |
% 15.43/14.98 bnd_c7_0) |
% 15.43/14.98 ~ bnd_c6_0)) &
% 15.43/14.98 (((((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a686) &
% 15.43/14.98 ~ bnd_c1_2 bnd_a686 bnd_a687) &
% 15.43/14.98 bnd_c4_2 bnd_a686 bnd_a687) &
% 15.43/14.98 ~ bnd_c8_2 bnd_a686 bnd_a687) &
% 15.43/14.98 bnd_c8_1 bnd_a686) &
% 15.43/14.98 bnd_ndr1_1 bnd_a686) &
% 15.43/14.98 bnd_c4_2 bnd_a686 bnd_a688) &
% 15.43/14.98 bnd_c2_2 bnd_a686 bnd_a688 |
% 15.43/14.98 ~ bnd_c8_0) |
% 15.43/14.98 bnd_c1_0)) &
% 15.43/14.98 (bnd_c5_0 | bnd_c8_0)) &
% 15.43/14.98 ((bnd_c2_0 |
% 15.43/14.98 (ALL X82.
% 15.43/14.98 bnd_ndr1_0 -->
% 15.43/14.98 (~ bnd_c10_1 X82 | ~ bnd_c8_1 X82) |
% 15.43/14.98 (ALL X83.
% 15.43/14.98 bnd_ndr1_1 X82 -->
% 15.43/14.98 (~ bnd_c8_2 X82 X83 | bnd_c5_2 X82 X83) |
% 15.43/14.98 ~ bnd_c3_2 X82 X83))) |
% 15.43/14.98 bnd_c1_0)) &
% 15.43/14.98 ((ALL X84.
% 15.43/14.98 bnd_ndr1_0 -->
% 15.43/14.98 ((ALL X85.
% 15.43/14.98 bnd_ndr1_1 X84 -->
% 15.43/14.98 (~ bnd_c9_2 X84 X85 | bnd_c6_2 X84 X85) | ~ bnd_c10_2 X84 X85) |
% 15.43/14.98 ~ bnd_c8_1 X84) |
% 15.43/14.98 ~ bnd_c3_1 X84) |
% 15.43/14.98 bnd_c6_0)) &
% 15.43/14.98 ((((bnd_ndr1_0 & ~ bnd_c5_1 bnd_a689) & bnd_c9_1 bnd_a689) &
% 15.43/14.98 (ALL X86.
% 15.43/14.98 bnd_ndr1_1 bnd_a689 -->
% 15.43/14.98 (bnd_c4_2 bnd_a689 X86 | ~ bnd_c10_2 bnd_a689 X86) |
% 15.43/14.98 bnd_c1_2 bnd_a689 X86) |
% 15.43/14.98 bnd_c2_0) |
% 15.43/14.98 bnd_c9_0)) &
% 15.43/14.98 (((ALL X87. bnd_ndr1_0 --> (bnd_c2_1 X87 | bnd_c5_1 X87) | bnd_c3_1 X87) |
% 15.43/14.98 bnd_c4_0) |
% 15.43/14.98 (((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a690) & ~ bnd_c5_2 bnd_a690 bnd_a691) &
% 15.43/14.98 ~ bnd_c9_2 bnd_a690 bnd_a691) &
% 15.43/14.98 ~ bnd_c10_2 bnd_a690 bnd_a691) &
% 15.43/14.98 bnd_c2_1 bnd_a690) &
% 15.43/14.98 (ALL X88.
% 15.43/14.98 bnd_ndr1_1 bnd_a690 -->
% 15.43/14.98 (bnd_c7_2 bnd_a690 X88 | bnd_c2_2 bnd_a690 X88) |
% 15.43/14.98 bnd_c4_2 bnd_a690 X88))) &
% 15.43/14.98 (((((((((bnd_ndr1_0 &
% 15.43/14.98 bnd_ndr1_1 bnd_a692) &
% 15.43/14.98 ~ bnd_c7_2 bnd_a692 bnd_a693) &
% 15.43/14.98 bnd_c9_2 bnd_a692 bnd_a693) &
% 15.43/14.98 bnd_c2_2 bnd_a692 bnd_a693) &
% 15.43/14.98 bnd_ndr1_1 bnd_a692) &
% 15.43/14.98 ~ bnd_c3_2 bnd_a692 bnd_a694) &
% 15.43/14.98 ~ bnd_c10_2 bnd_a692 bnd_a694) &
% 15.43/14.98 ~ bnd_c5_1 bnd_a692 |
% 15.43/14.98 ((bnd_ndr1_0 & bnd_c5_1 bnd_a695) & ~ bnd_c10_1 bnd_a695) &
% 15.43/14.98 ~ bnd_c8_1 bnd_a695) |
% 15.43/14.98 bnd_c3_0)) &
% 15.43/14.98 ((bnd_c3_0 |
% 15.43/14.98 (bnd_ndr1_0 &
% 15.43/14.98 (ALL X89.
% 15.43/14.98 bnd_ndr1_1 bnd_a696 -->
% 15.43/14.98 (~ bnd_c7_2 bnd_a696 X89 | bnd_c5_2 bnd_a696 X89) |
% 15.43/14.98 ~ bnd_c2_2 bnd_a696 X89)) &
% 15.43/14.98 ~ bnd_c1_1 bnd_a696) |
% 15.43/14.98 ((bnd_ndr1_0 & ~ bnd_c3_1 bnd_a697) &
% 15.43/14.98 (ALL X90.
% 15.43/14.98 bnd_ndr1_1 bnd_a697 -->
% 15.43/14.98 (~ bnd_c3_2 bnd_a697 X90 | bnd_c8_2 bnd_a697 X90) |
% 15.43/14.98 ~ bnd_c6_2 bnd_a697 X90)) &
% 15.43/14.98 bnd_c9_1 bnd_a697)) &
% 15.43/14.98 ((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a698) &
% 15.43/14.98 ~ bnd_c5_2 bnd_a698 bnd_a699) &
% 15.43/14.98 bnd_c1_2 bnd_a698 bnd_a699) &
% 15.43/14.98 bnd_c2_1 bnd_a698) &
% 15.43/14.98 bnd_c9_1 bnd_a698 |
% 15.43/14.98 ~ bnd_c4_0) |
% 15.43/14.98 bnd_c2_0)) &
% 15.43/14.98 ((~ bnd_c1_0 |
% 15.43/14.98 ((bnd_ndr1_0 & ~ bnd_c7_1 bnd_a700) &
% 15.43/14.98 ~ bnd_c9_1 bnd_a700) &
% 15.43/14.98 ~ bnd_c10_1 bnd_a700) |
% 15.43/14.98 (((((bnd_ndr1_0 &
% 15.43/14.98 (ALL X91.
% 15.43/14.98 bnd_ndr1_1 bnd_a701 -->
% 15.43/14.98 (~ bnd_c1_2 bnd_a701 X91 | ~ bnd_c6_2 bnd_a701 X91) |
% 15.43/14.98 bnd_c5_2 bnd_a701 X91)) &
% 15.43/14.98 bnd_ndr1_1 bnd_a701) &
% 15.43/14.98 ~ bnd_c2_2 bnd_a701 bnd_a702) &
% 15.43/14.98 bnd_c10_2 bnd_a701 bnd_a702) &
% 15.43/14.98 bnd_c6_2 bnd_a701 bnd_a702) &
% 15.43/14.98 ~ bnd_c8_1 bnd_a701)) &
% 15.43/14.98 ((((bnd_ndr1_0 & ~ bnd_c10_1 bnd_a703) &
% 15.43/14.98 bnd_c4_1 bnd_a703) &
% 15.43/14.98 ~ bnd_c7_1 bnd_a703 |
% 15.43/14.98 (ALL X92.
% 15.43/14.98 bnd_ndr1_0 -->
% 15.43/14.98 (~ bnd_c7_1 X92 | bnd_c4_1 X92) |
% 15.43/14.98 ((bnd_ndr1_1 X92 & ~ bnd_c5_2 X92 bnd_a704) & ~ bnd_c3_2 X92 bnd_a704) &
% 15.43/14.98 bnd_c9_2 X92 bnd_a704)) |
% 15.43/14.98 (ALL X93.
% 15.43/14.98 bnd_ndr1_0 -->
% 15.43/14.98 ((ALL X94.
% 15.43/14.98 bnd_ndr1_1 X93 -->
% 15.43/14.98 (bnd_c6_2 X93 X94 | bnd_c4_2 X93 X94) | ~ bnd_c8_2 X93 X94) |
% 15.43/14.98 bnd_c1_1 X93) |
% 15.43/14.98 (ALL X95.
% 15.43/14.98 bnd_ndr1_1 X93 -->
% 15.43/14.98 (bnd_c4_2 X93 X95 | ~ bnd_c1_2 X93 X95) | bnd_c10_2 X93 X95)))) &
% 15.43/14.98 ((((bnd_ndr1_0 & ~ bnd_c9_1 bnd_a705) &
% 15.43/14.98 (ALL X96.
% 15.43/14.98 bnd_ndr1_1 bnd_a705 -->
% 15.43/14.98 (~ bnd_c2_2 bnd_a705 X96 | ~ bnd_c6_2 bnd_a705 X96) |
% 15.43/14.98 ~ bnd_c7_2 bnd_a705 X96)) &
% 15.43/14.98 ~ bnd_c3_1 bnd_a705 |
% 15.43/14.98 (ALL X97.
% 15.43/14.98 bnd_ndr1_0 -->
% 15.43/14.98 (((bnd_ndr1_1 X97 & ~ bnd_c9_2 X97 bnd_a706) & bnd_c6_2 X97 bnd_a706) &
% 15.43/14.98 bnd_c5_2 X97 bnd_a706 |
% 15.43/14.98 ~ bnd_c9_1 X97) |
% 15.43/14.98 ~ bnd_c1_1 X97)) |
% 15.43/14.98 bnd_c6_0)) &
% 15.43/14.98 ((bnd_c2_0 |
% 15.43/14.98 ((bnd_ndr1_0 &
% 15.43/14.98 (ALL X98.
% 15.43/14.98 bnd_ndr1_1 bnd_a707 -->
% 15.43/14.98 (bnd_c1_2 bnd_a707 X98 | bnd_c4_2 bnd_a707 X98) |
% 15.43/14.98 ~ bnd_c3_2 bnd_a707 X98)) &
% 15.43/14.98 ~ bnd_c10_1 bnd_a707) &
% 15.43/14.98 bnd_c8_1 bnd_a707) |
% 15.43/14.98 (bnd_ndr1_0 &
% 15.43/14.98 (ALL X99.
% 15.43/14.98 bnd_ndr1_1 bnd_a708 -->
% 15.43/14.98 (~ bnd_c5_2 bnd_a708 X99 |
% 15.43/14.98 bnd_c10_2 bnd_a708 X99) |
% 15.43/14.98 bnd_c7_2 bnd_a708 X99)) &
% 15.43/14.98 ~ bnd_c5_1 bnd_a708)) &
% 15.43/14.98 (~ bnd_c8_0 | ~ bnd_c2_0)) &
% 15.43/14.98 (((((((bnd_ndr1_0 & bnd_c8_1 bnd_a709) &
% 15.43/14.98 ~ bnd_c9_1 bnd_a709) &
% 15.43/14.98 bnd_ndr1_1 bnd_a709) &
% 15.43/14.98 bnd_c9_2 bnd_a709 bnd_a710) &
% 15.43/14.98 ~ bnd_c8_2 bnd_a709 bnd_a710) &
% 15.43/14.98 ~ bnd_c6_2 bnd_a709 bnd_a710 |
% 15.43/14.98 (ALL X100.
% 15.43/14.98 bnd_ndr1_0 -->
% 15.43/14.98 ((ALL X101.
% 15.43/14.98 bnd_ndr1_1 X100 -->
% 15.43/14.98 (~ bnd_c2_2 X100 X101 | bnd_c1_2 X100 X101) | ~ bnd_c9_2 X100 X101) |
% 15.43/14.98 (ALL X102.
% 15.43/14.98 bnd_ndr1_1 X100 -->
% 15.43/14.98 (bnd_c4_2 X100 X102 | ~ bnd_c7_2 X100 X102) | ~ bnd_c5_2 X100 X102)) |
% 15.43/14.98 ~ bnd_c8_1 X100)) |
% 15.43/14.98 ~ bnd_c1_0)) &
% 15.43/14.98 (((ALL X103.
% 15.43/14.98 bnd_ndr1_0 -->
% 15.43/14.98 (bnd_c8_1 X103 |
% 15.43/14.98 (ALL X104.
% 15.43/14.98 bnd_ndr1_1 X103 -->
% 15.43/14.98 (~ bnd_c3_2 X103 X104 | ~ bnd_c5_2 X103 X104) | ~ bnd_c2_2 X103 X104)) |
% 15.43/14.98 (ALL X105.
% 15.43/14.98 bnd_ndr1_1 X103 -->
% 15.43/14.98 (~ bnd_c7_2 X103 X105 | ~ bnd_c2_2 X103 X105) | ~ bnd_c10_2 X103 X105)) |
% 15.43/14.98 ~ bnd_c5_0) |
% 15.43/14.98 (ALL X106.
% 15.43/14.98 bnd_ndr1_0 -->
% 15.43/14.98 (bnd_c5_1 X106 | ~ bnd_c7_1 X106) |
% 15.43/14.98 ((bnd_ndr1_1 X106 &
% 15.43/14.98 ~ bnd_c10_2 X106 bnd_a711) &
% 15.43/14.98 bnd_c8_2 X106 bnd_a711) &
% 15.43/14.98 ~ bnd_c2_2 X106 bnd_a711))) &
% 15.43/14.98 ((bnd_c8_0 | ~ bnd_c2_0) | ~ bnd_c7_0)) &
% 15.43/14.98 (((ALL X107.
% 15.43/14.98 bnd_ndr1_0 -->
% 15.43/14.98 ((bnd_ndr1_1 X107 &
% 15.43/14.98 ~ bnd_c4_2 X107 bnd_a712) &
% 15.43/14.98 bnd_c8_2 X107 bnd_a712) &
% 15.43/14.98 ~ bnd_c9_2 X107 bnd_a712 |
% 15.43/14.98 ((bnd_ndr1_1 X107 &
% 15.43/14.98 ~ bnd_c6_2 X107 bnd_a713) &
% 15.43/14.98 ~ bnd_c10_2 X107 bnd_a713) &
% 15.43/14.98 bnd_c9_2 X107 bnd_a713) |
% 15.43/14.98 ~ bnd_c6_0) |
% 15.43/14.98 (ALL X108.
% 15.43/14.98 bnd_ndr1_0 -->
% 15.43/14.98 ((ALL X109.
% 15.43/14.98 bnd_ndr1_1 X108 -->
% 15.43/14.98 (bnd_c6_2 X108 X109 |
% 15.43/14.98 ~ bnd_c7_2 X108 X109) |
% 15.43/14.98 bnd_c8_2 X108 X109) |
% 15.43/14.98 ((bnd_ndr1_1 X108 &
% 15.43/14.98 bnd_c3_2 X108 bnd_a714) &
% 15.43/14.98 bnd_c7_2 X108 bnd_a714) &
% 15.43/14.98 ~ bnd_c5_2 X108 bnd_a714) |
% 15.43/14.98 ~ bnd_c8_1 X108))) &
% 15.43/14.98 (((ALL X110.
% 15.43/14.98 bnd_ndr1_0 -->
% 15.43/14.98 ((bnd_ndr1_1 X110 &
% 15.43/14.98 bnd_c10_2 X110 bnd_a715) &
% 15.43/14.98 ~ bnd_c3_2 X110 bnd_a715 |
% 15.43/14.98 (ALL X111.
% 15.43/14.98 bnd_ndr1_1 X110 -->
% 15.43/14.98 ~ bnd_c7_2 X110 X111 |
% 15.43/14.98 ~ bnd_c3_2 X110 X111)) |
% 15.43/14.98 ((bnd_ndr1_1 X110 & bnd_c2_2 X110 bnd_a716) &
% 15.43/14.98 bnd_c3_2 X110 bnd_a716) &
% 15.43/14.98 bnd_c1_2 X110 bnd_a716) |
% 15.43/14.98 ~ bnd_c7_0) |
% 15.43/14.98 (ALL X112.
% 15.43/14.98 bnd_ndr1_0 -->
% 15.43/14.98 (~ bnd_c1_1 X112 |
% 15.43/14.98 (ALL X113.
% 15.43/14.98 bnd_ndr1_1 X112 -->
% 15.43/14.98 bnd_c7_2 X112 X113 |
% 15.43/14.98 ~ bnd_c5_2 X112 X113)) |
% 15.43/14.98 ~ bnd_c6_1 X112))) &
% 15.43/14.98 ((~ bnd_c9_0 |
% 15.43/14.98 (ALL X114.
% 15.43/14.98 bnd_ndr1_0 -->
% 15.43/14.98 (((bnd_ndr1_1 X114 & bnd_c5_2 X114 bnd_a717) &
% 15.43/14.98 bnd_c7_2 X114 bnd_a717) &
% 15.43/14.98 bnd_c4_2 X114 bnd_a717 |
% 15.43/14.98 (ALL X115.
% 15.43/14.98 bnd_ndr1_1 X114 -->
% 15.43/14.98 (~ bnd_c3_2 X114 X115 |
% 15.43/14.98 ~ bnd_c6_2 X114 X115) |
% 15.43/14.98 bnd_c4_2 X114 X115)) |
% 15.43/14.98 bnd_c3_1 X114)) |
% 15.43/14.98 bnd_c8_0)) &
% 15.43/14.98 (((ALL X116.
% 15.43/14.98 bnd_ndr1_0 -->
% 15.43/14.98 (~ bnd_c10_1 X116 |
% 15.43/14.98 (bnd_ndr1_1 X116 & ~ bnd_c8_2 X116 bnd_a718) &
% 15.43/14.98 ~ bnd_c7_2 X116 bnd_a718) |
% 15.43/14.98 ((bnd_ndr1_1 X116 & ~ bnd_c7_2 X116 bnd_a719) &
% 15.43/14.98 ~ bnd_c4_2 X116 bnd_a719) &
% 15.43/14.98 bnd_c2_2 X116 bnd_a719) |
% 15.43/14.98 (ALL X117.
% 15.43/14.98 bnd_ndr1_0 -->
% 15.43/14.98 ((bnd_ndr1_1 X117 & bnd_c3_2 X117 bnd_a720) &
% 15.43/14.98 ~ bnd_c10_2 X117 bnd_a720 |
% 15.43/14.98 bnd_c3_1 X117) |
% 15.43/14.98 bnd_c6_1 X117)) |
% 15.43/14.98 ((bnd_ndr1_0 & bnd_c4_1 bnd_a721) &
% 15.43/14.98 ~ bnd_c1_1 bnd_a721) &
% 15.43/14.98 ~ bnd_c5_1 bnd_a721)) &
% 15.43/14.98 (((ALL X118.
% 15.43/14.98 bnd_ndr1_0 -->
% 15.43/14.98 (bnd_c6_1 X118 |
% 15.43/14.98 (ALL X119.
% 15.43/14.98 bnd_ndr1_1 X118 -->
% 15.43/14.98 (bnd_c5_2 X118 X119 |
% 15.43/14.98 ~ bnd_c2_2 X118 X119) |
% 15.43/14.98 bnd_c4_2 X118 X119)) |
% 15.43/14.98 ((bnd_ndr1_1 X118 & ~ bnd_c5_2 X118 bnd_a722) &
% 15.43/14.98 ~ bnd_c9_2 X118 bnd_a722) &
% 15.43/14.98 bnd_c8_2 X118 bnd_a722) |
% 15.43/14.98 ((bnd_ndr1_0 & bnd_c10_1 bnd_a723) &
% 15.43/14.98 bnd_c4_1 bnd_a723) &
% 15.43/14.98 bnd_c7_1 bnd_a723) |
% 15.43/14.98 ~ bnd_c2_0)) &
% 15.43/14.98 ((bnd_c9_0 | ~ bnd_c7_0) |
% 15.43/14.98 ((((bnd_ndr1_0 &
% 15.43/14.98 (ALL X120.
% 15.43/14.98 bnd_ndr1_1 bnd_a724 -->
% 15.43/14.98 (bnd_c6_2 bnd_a724 X120 |
% 15.43/14.98 ~ bnd_c8_2 bnd_a724 X120) |
% 15.43/14.98 ~ bnd_c9_2 bnd_a724 X120)) &
% 15.43/14.98 bnd_ndr1_1 bnd_a724) &
% 15.43/14.98 ~ bnd_c6_2 bnd_a724 bnd_a725) &
% 15.43/14.98 bnd_c4_2 bnd_a724 bnd_a725) &
% 15.43/14.98 (ALL X121.
% 15.43/14.98 bnd_ndr1_1 bnd_a724 -->
% 15.43/14.98 bnd_c4_2 bnd_a724 X121 |
% 15.43/14.98 bnd_c2_2 bnd_a724 X121))) &
% 15.43/14.98 (((ALL X122.
% 15.43/14.98 bnd_ndr1_0 -->
% 15.43/14.98 (bnd_c1_1 X122 |
% 15.43/14.98 (ALL X123.
% 15.43/14.98 bnd_ndr1_1 X122 -->
% 15.43/14.98 (~ bnd_c5_2 X122 X123 | bnd_c3_2 X122 X123) |
% 15.43/14.98 bnd_c10_2 X122 X123)) |
% 15.43/14.98 bnd_c5_1 X122) |
% 15.43/14.98 bnd_c6_0) |
% 15.43/14.98 ~ bnd_c2_0)) &
% 15.43/14.98 (((ALL X124.
% 15.43/14.98 bnd_ndr1_0 -->
% 15.43/14.98 ((ALL X125.
% 15.43/14.98 bnd_ndr1_1 X124 -->
% 15.43/14.98 (~ bnd_c9_2 X124 X125 | bnd_c1_2 X124 X125) |
% 15.43/14.98 bnd_c10_2 X124 X125) |
% 15.43/14.98 bnd_c3_1 X124) |
% 15.43/14.98 (bnd_ndr1_1 X124 & ~ bnd_c4_2 X124 bnd_a726) &
% 15.43/14.98 ~ bnd_c3_2 X124 bnd_a726) |
% 15.43/14.98 (ALL X126.
% 15.43/14.98 bnd_ndr1_0 -->
% 15.43/14.98 (~ bnd_c7_1 X126 |
% 15.43/14.98 ((bnd_ndr1_1 X126 & ~ bnd_c7_2 X126 bnd_a727) &
% 15.43/14.98 bnd_c9_2 X126 bnd_a727) &
% 15.43/14.98 ~ bnd_c6_2 X126 bnd_a727) |
% 15.43/14.98 ~ bnd_c4_1 X126)) |
% 15.43/14.98 (ALL X127.
% 15.43/14.98 bnd_ndr1_0 -->
% 15.43/14.98 ((ALL X128.
% 15.43/14.98 bnd_ndr1_1 X127 -->
% 15.43/14.98 (~ bnd_c8_2 X127 X128 | ~ bnd_c4_2 X127 X128) |
% 15.43/14.98 bnd_c3_2 X127 X128) |
% 15.43/14.98 ~ bnd_c4_1 X127) |
% 15.43/14.98 ~ bnd_c10_1 X127))) &
% 15.43/14.98 ((~ bnd_c7_0 |
% 15.43/14.98 (bnd_ndr1_0 & bnd_c6_1 bnd_a728) & bnd_c1_1 bnd_a728) |
% 15.43/14.98 (((((bnd_ndr1_0 & ~ bnd_c9_1 bnd_a729) &
% 15.43/14.98 bnd_ndr1_1 bnd_a729) &
% 15.43/14.98 ~ bnd_c9_2 bnd_a729 bnd_a730) &
% 15.43/14.98 bnd_c7_2 bnd_a729 bnd_a730) &
% 15.43/14.98 bnd_c8_2 bnd_a729 bnd_a730) &
% 15.43/14.98 bnd_c3_1 bnd_a729)) &
% 15.43/14.98 (((ALL X129.
% 15.43/14.98 bnd_ndr1_0 -->
% 15.43/14.98 ((bnd_ndr1_1 X129 & bnd_c3_2 X129 bnd_a731) &
% 15.43/14.98 bnd_c9_2 X129 bnd_a731 |
% 15.43/14.98 (bnd_ndr1_1 X129 & ~ bnd_c3_2 X129 bnd_a732) &
% 15.43/14.98 bnd_c4_2 X129 bnd_a732) |
% 15.43/14.98 ~ bnd_c9_1 X129) |
% 15.43/14.98 ((bnd_ndr1_0 & ~ bnd_c4_1 bnd_a733) &
% 15.43/14.98 (ALL X130.
% 15.43/14.98 bnd_ndr1_1 bnd_a733 --> ~ bnd_c2_2 bnd_a733 X130)) &
% 15.43/14.98 (ALL X131.
% 15.43/14.98 bnd_ndr1_1 bnd_a733 -->
% 15.43/14.98 (~ bnd_c4_2 bnd_a733 X131 | bnd_c7_2 bnd_a733 X131) |
% 15.43/14.98 ~ bnd_c6_2 bnd_a733 X131)) |
% 15.43/14.98 ~ bnd_c10_0)) &
% 15.43/14.98 ((((((((((bnd_ndr1_0 & ~ bnd_c10_1 bnd_a734) &
% 15.43/14.98 bnd_ndr1_1 bnd_a734) &
% 15.43/14.98 ~ bnd_c7_2 bnd_a734 bnd_a735) &
% 15.43/14.98 bnd_c10_2 bnd_a734 bnd_a735) &
% 15.43/14.98 bnd_c6_2 bnd_a734 bnd_a735) &
% 15.43/14.98 bnd_ndr1_1 bnd_a734) &
% 15.43/14.98 ~ bnd_c3_2 bnd_a734 bnd_a736) &
% 15.43/14.98 bnd_c2_2 bnd_a734 bnd_a736) &
% 15.43/14.98 bnd_c1_2 bnd_a734 bnd_a736 |
% 15.43/14.98 ~ bnd_c7_0) |
% 15.43/14.98 (((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a737) &
% 15.43/14.98 bnd_c9_2 bnd_a737 bnd_a738) &
% 15.43/14.98 ~ bnd_c4_2 bnd_a737 bnd_a738) &
% 15.43/14.98 bnd_c1_2 bnd_a737 bnd_a738) &
% 15.43/14.98 bnd_c9_1 bnd_a737) &
% 15.43/14.98 ~ bnd_c4_1 bnd_a737)) &
% 15.43/14.98 ((((bnd_ndr1_0 & ~ bnd_c2_1 bnd_a739) &
% 15.43/14.98 ~ bnd_c5_1 bnd_a739) &
% 15.43/14.98 ~ bnd_c7_1 bnd_a739 |
% 15.43/14.98 ((bnd_ndr1_0 &
% 15.43/14.98 (ALL X132.
% 15.43/14.98 bnd_ndr1_1 bnd_a740 -->
% 15.43/14.98 ~ bnd_c10_2 bnd_a740 X132 |
% 15.43/14.98 bnd_c6_2 bnd_a740 X132)) &
% 15.43/14.98 ~ bnd_c9_1 bnd_a740) &
% 15.43/14.98 bnd_c4_1 bnd_a740) |
% 15.43/14.98 bnd_c10_0)) &
% 15.43/14.98 ((~ bnd_c10_0 | bnd_c9_0) |
% 15.43/14.98 (ALL X133.
% 15.43/14.98 bnd_ndr1_0 -->
% 15.43/14.98 ((ALL X134.
% 15.43/14.98 bnd_ndr1_1 X133 -->
% 15.43/14.98 (~ bnd_c9_2 X133 X134 | bnd_c6_2 X133 X134) |
% 15.43/14.98 bnd_c8_2 X133 X134) |
% 15.43/14.98 (ALL X135.
% 15.43/14.98 bnd_ndr1_1 X133 -->
% 15.43/14.98 (bnd_c5_2 X133 X135 | ~ bnd_c4_2 X133 X135) |
% 15.43/14.98 ~ bnd_c8_2 X133 X135)) |
% 15.43/14.98 ~ bnd_c4_1 X133))) &
% 15.43/14.98 (((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a741) &
% 15.43/14.98 bnd_c10_2 bnd_a741 bnd_a742) &
% 15.43/14.98 ~ bnd_c4_2 bnd_a741 bnd_a742) &
% 15.43/14.98 ~ bnd_c1_2 bnd_a741 bnd_a742) &
% 15.43/14.98 ~ bnd_c5_1 bnd_a741 |
% 15.43/14.98 (ALL X136.
% 15.43/14.98 bnd_ndr1_0 -->
% 15.43/14.98 ((ALL X137.
% 15.43/14.98 bnd_ndr1_1 X136 -->
% 15.43/14.98 (bnd_c6_2 X136 X137 | ~ bnd_c1_2 X136 X137) |
% 15.43/14.98 ~ bnd_c3_2 X136 X137) |
% 15.43/14.98 (bnd_ndr1_1 X136 & ~ bnd_c9_2 X136 bnd_a743) &
% 15.43/14.98 ~ bnd_c10_2 X136 bnd_a743) |
% 15.43/14.98 ((bnd_ndr1_1 X136 & bnd_c9_2 X136 bnd_a744) &
% 15.43/14.98 bnd_c6_2 X136 bnd_a744) &
% 15.43/14.98 bnd_c8_2 X136 bnd_a744))) &
% 15.43/14.98 ((~ bnd_c7_0 |
% 15.43/14.98 (((((bnd_ndr1_0 & bnd_c2_1 bnd_a745) & bnd_ndr1_1 bnd_a745) &
% 15.43/14.98 bnd_c4_2 bnd_a745 bnd_a746) &
% 15.43/14.98 bnd_c10_2 bnd_a745 bnd_a746) &
% 15.43/14.98 ~ bnd_c1_2 bnd_a745 bnd_a746) &
% 15.43/14.98 (ALL X138.
% 15.43/14.98 bnd_ndr1_1 bnd_a745 -->
% 15.43/14.98 (bnd_c9_2 bnd_a745 X138 | ~ bnd_c3_2 bnd_a745 X138) |
% 15.43/14.98 ~ bnd_c1_2 bnd_a745 X138)) |
% 15.43/14.98 bnd_c8_0)) &
% 15.43/14.98 (bnd_c6_0 |
% 15.43/14.98 (ALL X139.
% 15.43/14.98 bnd_ndr1_0 -->
% 15.43/14.98 (((bnd_ndr1_1 X139 & bnd_c5_2 X139 bnd_a747) &
% 15.43/14.98 ~ bnd_c1_2 X139 bnd_a747) &
% 15.43/14.98 bnd_c9_2 X139 bnd_a747 |
% 15.43/14.98 (ALL X140.
% 15.43/14.98 bnd_ndr1_1 X139 -->
% 15.43/14.98 (~ bnd_c1_2 X139 X140 | bnd_c3_2 X139 X140) |
% 15.43/14.98 bnd_c5_2 X139 X140)) |
% 15.43/14.98 ~ bnd_c2_1 X139))) &
% 15.43/14.98 (((ALL X141.
% 15.43/14.98 bnd_ndr1_0 -->
% 15.43/14.98 (((bnd_ndr1_1 X141 & ~ bnd_c4_2 X141 bnd_a748) &
% 15.43/14.98 bnd_c1_2 X141 bnd_a748) &
% 15.43/14.98 bnd_c10_2 X141 bnd_a748 |
% 15.43/14.98 bnd_c8_1 X141) |
% 15.43/14.98 (ALL X142.
% 15.43/14.98 bnd_ndr1_1 X141 -->
% 15.43/14.98 (bnd_c3_2 X141 X142 | bnd_c5_2 X141 X142) |
% 15.43/14.98 bnd_c10_2 X141 X142)) |
% 15.43/14.98 ~ bnd_c4_0) |
% 15.43/14.98 (ALL X143.
% 15.43/14.98 bnd_ndr1_0 -->
% 15.43/14.98 (((bnd_ndr1_1 X143 & ~ bnd_c5_2 X143 bnd_a749) &
% 15.43/14.98 bnd_c7_2 X143 bnd_a749) &
% 15.43/14.98 bnd_c6_2 X143 bnd_a749 |
% 15.43/14.98 ((bnd_ndr1_1 X143 & bnd_c2_2 X143 bnd_a750) &
% 15.43/14.98 ~ bnd_c8_2 X143 bnd_a750) &
% 15.43/14.98 ~ bnd_c10_2 X143 bnd_a750) |
% 15.43/14.98 (ALL X144.
% 15.43/14.98 bnd_ndr1_1 X143 -->
% 15.43/14.98 (~ bnd_c2_2 X143 X144 | bnd_c9_2 X143 X144) |
% 15.43/14.98 ~ bnd_c4_2 X143 X144)))) &
% 15.43/14.98 (((ALL X145. bnd_ndr1_0 --> bnd_c9_1 X145 | ~ bnd_c2_1 X145) |
% 15.43/14.98 ~ bnd_c10_0) |
% 15.43/14.98 ~ bnd_c1_0)) &
% 15.43/14.98 ((bnd_c4_0 | bnd_c2_0) | bnd_c6_0)) &
% 15.43/14.98 (((ALL X146.
% 15.43/14.98 bnd_ndr1_0 -->
% 15.43/14.98 (bnd_c7_1 X146 |
% 15.43/14.98 (ALL X147.
% 15.43/14.98 bnd_ndr1_1 X146 -->
% 15.43/14.98 (~ bnd_c6_2 X146 X147 | bnd_c9_2 X146 X147) |
% 15.43/14.98 ~ bnd_c8_2 X146 X147)) |
% 15.43/14.98 (bnd_ndr1_1 X146 & bnd_c3_2 X146 bnd_a751) &
% 15.43/14.98 bnd_c2_2 X146 bnd_a751) |
% 15.43/14.98 (ALL X148.
% 15.43/14.98 bnd_ndr1_0 -->
% 15.43/14.98 (bnd_c10_1 X148 |
% 15.43/14.98 (bnd_ndr1_1 X148 & ~ bnd_c4_2 X148 bnd_a752) &
% 15.43/14.98 ~ bnd_c7_2 X148 bnd_a752) |
% 15.43/14.98 bnd_c3_1 X148)) |
% 15.43/14.98 (((((bnd_ndr1_0 & ~ bnd_c9_1 bnd_a753) & bnd_ndr1_1 bnd_a753) &
% 15.43/14.98 ~ bnd_c1_2 bnd_a753 bnd_a754) &
% 15.43/14.98 ~ bnd_c4_2 bnd_a753 bnd_a754) &
% 15.43/14.98 bnd_c10_2 bnd_a753 bnd_a754) &
% 15.43/14.98 (ALL X149.
% 15.43/14.98 bnd_ndr1_1 bnd_a753 -->
% 15.43/14.98 ~ bnd_c4_2 bnd_a753 X149 | ~ bnd_c3_2 bnd_a753 X149))) &
% 15.43/14.98 (((ALL X150.
% 15.43/14.98 bnd_ndr1_0 -->
% 15.43/14.98 ((ALL X151.
% 15.43/14.98 bnd_ndr1_1 X150 -->
% 15.43/14.98 (~ bnd_c10_2 X150 X151 | bnd_c1_2 X150 X151) |
% 15.43/14.98 bnd_c3_2 X150 X151) |
% 15.43/14.98 bnd_c10_1 X150) |
% 15.43/14.98 ~ bnd_c5_1 X150) |
% 15.43/14.98 ~ bnd_c10_0) |
% 15.43/14.98 ((bnd_ndr1_0 & ~ bnd_c7_1 bnd_a755) & ~ bnd_c6_1 bnd_a755) &
% 15.43/14.98 (ALL X152.
% 15.43/14.98 bnd_ndr1_1 bnd_a755 -->
% 15.43/14.98 (bnd_c6_2 bnd_a755 X152 | ~ bnd_c8_2 bnd_a755 X152) |
% 15.43/14.98 ~ bnd_c7_2 bnd_a755 X152))) &
% 15.43/14.98 ((bnd_ndr1_0 & bnd_c6_1 bnd_a756) &
% 15.43/14.98 (ALL X153.
% 15.43/14.98 bnd_ndr1_1 bnd_a756 -->
% 15.43/14.98 (~ bnd_c4_2 bnd_a756 X153 | bnd_c10_2 bnd_a756 X153) |
% 15.43/14.98 bnd_c8_2 bnd_a756 X153) |
% 15.43/14.98 bnd_c7_0)) &
% 15.43/14.98 ((((bnd_ndr1_0 & bnd_c5_1 bnd_a757) & bnd_c10_1 bnd_a757) &
% 15.43/14.98 ~ bnd_c1_1 bnd_a757 |
% 15.43/14.98 bnd_c1_0) |
% 15.43/14.98 ((bnd_ndr1_0 & bnd_c1_1 bnd_a758) & bnd_c8_1 bnd_a758) &
% 15.43/14.98 bnd_c4_1 bnd_a758)) &
% 15.43/14.98 ((~ bnd_c1_0 | bnd_c7_0) |
% 15.43/14.98 (((((bnd_ndr1_0 &
% 15.43/14.98 (ALL X154.
% 15.43/14.98 bnd_ndr1_1 bnd_a759 -->
% 15.43/14.98 (~ bnd_c6_2 bnd_a759 X154 | bnd_c7_2 bnd_a759 X154) |
% 15.43/14.98 bnd_c8_2 bnd_a759 X154)) &
% 15.43/14.98 bnd_ndr1_1 bnd_a759) &
% 15.43/14.98 ~ bnd_c1_2 bnd_a759 bnd_a760) &
% 15.43/14.98 bnd_c2_2 bnd_a759 bnd_a760) &
% 15.43/14.98 ~ bnd_c5_2 bnd_a759 bnd_a760) &
% 15.43/14.98 ~ bnd_c8_1 bnd_a759))
% 15.43/14.98 Adding axioms...
% 15.53/15.00 Typedef.type_definition_def
% 42.17/41.66 ...done.
% 42.17/41.68 Ground types: ?'b, TPTP_Interpret.ind
% 42.17/41.68 Translating term (sizes: 1, 1) ...
% 64.35/63.80 Invoking SAT solver...
% 64.45/63.81 No model exists.
% 64.45/63.81 Translating term (sizes: 2, 1) ...
% 87.30/86.63 Invoking SAT solver...
% 87.30/86.64 No model exists.
% 87.30/86.64 Translating term (sizes: 1, 2) ...
% 129.87/129.08 Invoking SAT solver...
% 130.58/129.71 Model found:
% 130.58/129.71 Size of types: ?'b: 1, TPTP_Interpret.ind: 2
% 130.58/129.71 bnd_a760: ??.TPTP_Interpret.ind1
% 130.58/129.71 bnd_a759: ??.TPTP_Interpret.ind1
% 130.58/129.71 bnd_a758: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a757: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a756: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a755: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a754: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a753: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a752: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a751: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a750: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a749: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a748: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a747: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a746: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a745: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a744: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a743: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a742: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a741: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a740: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a739: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a738: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a737: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a736: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a735: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a734: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a733: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a732: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a731: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a730: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a729: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a728: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a727: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a726: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a725: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a724: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a723: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a722: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a721: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a720: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a719: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a718: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a717: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a716: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a715: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a714: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a713: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a712: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a711: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a710: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a709: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a708: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a707: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a706: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a705: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a704: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a703: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a702: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a701: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a700: ??.TPTP_Interpret.ind1
% 130.58/129.71 bnd_a699: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a698: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a697: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a696: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a695: ??.TPTP_Interpret.ind1
% 130.58/129.71 bnd_a694: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a693: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a692: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a691: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a690: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a689: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a688: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a687: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a686: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a685: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a684: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a683: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a682: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a681: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a680: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a679: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a678: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a677: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a676: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a675: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a674: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a673: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a672: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a671: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a670: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a669: ??.TPTP_Interpret.ind1
% 130.58/129.71 bnd_a668: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a667: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a666: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a665: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_c4_0: False
% 130.58/129.71 bnd_a664: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a663: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a662: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a661: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a660: ??.TPTP_Interpret.ind1
% 130.58/129.71 bnd_a659: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a658: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a657: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a656: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a655: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a654: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a653: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a652: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a651: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a650: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a649: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a648: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_c10_0: True
% 130.58/129.71 bnd_a647: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a646: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a645: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a644: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a643: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a642: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a641: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a640: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a639: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a638: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a637: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a636: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a635: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a634: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a633: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a632: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a631: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_c6_0: True
% 130.58/129.71 bnd_c6_1: {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, False)}
% 130.58/129.71 bnd_a630: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a629: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a628: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_c7_0: False
% 130.58/129.71 bnd_a627: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a626: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a625: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a624: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a623: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a622: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a621: ??.TPTP_Interpret.ind1
% 130.58/129.71 bnd_c1_1: {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, True)}
% 130.58/129.71 bnd_a620: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a619: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_c7_1: {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, False)}
% 130.58/129.71 bnd_a618: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_c3_0: True
% 130.58/129.71 bnd_a617: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_c2_0: False
% 130.58/129.71 bnd_c7_2: {(??.TPTP_Interpret.ind0,
% 130.58/129.71 {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, True)}),
% 130.58/129.71 (??.TPTP_Interpret.ind1,
% 130.58/129.71 {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, True)})}
% 130.58/129.71 bnd_c10_2: {(??.TPTP_Interpret.ind0,
% 130.58/129.71 {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, False)}),
% 130.58/129.71 (??.TPTP_Interpret.ind1,
% 130.58/129.71 {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, False)})}
% 130.58/129.71 bnd_a616: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a615: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_a614: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_c5_0: False
% 130.58/129.71 bnd_a613: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_c2_1: {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, False)}
% 130.58/129.71 bnd_a612: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_c8_2: {(??.TPTP_Interpret.ind0,
% 130.58/129.71 {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, False)}),
% 130.58/129.71 (??.TPTP_Interpret.ind1,
% 130.58/129.71 {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, False)})}
% 130.58/129.71 bnd_a611: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_c3_1: {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, False)}
% 130.58/129.71 bnd_c1_2: {(??.TPTP_Interpret.ind0,
% 130.58/129.71 {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, True)}),
% 130.58/129.71 (??.TPTP_Interpret.ind1,
% 130.58/129.71 {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, False)})}
% 130.58/129.71 bnd_c6_2: {(??.TPTP_Interpret.ind0,
% 130.58/129.71 {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, True)}),
% 130.58/129.71 (??.TPTP_Interpret.ind1,
% 130.58/129.71 {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, True)})}
% 130.58/129.71 bnd_c9_2: {(??.TPTP_Interpret.ind0,
% 130.58/129.71 {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, False)}),
% 130.58/129.71 (??.TPTP_Interpret.ind1,
% 130.58/129.71 {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, False)})}
% 130.58/129.71 bnd_a610: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_c3_2: {(??.TPTP_Interpret.ind0,
% 130.58/129.71 {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, False)}),
% 130.58/129.71 (??.TPTP_Interpret.ind1,
% 130.58/129.71 {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, False)})}
% 130.58/129.71 bnd_c4_2: {(??.TPTP_Interpret.ind0,
% 130.58/129.71 {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, True)}),
% 130.58/129.71 (??.TPTP_Interpret.ind1,
% 130.58/129.71 {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, True)})}
% 130.58/129.71 bnd_c2_2: {(??.TPTP_Interpret.ind0,
% 130.58/129.71 {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, False)}),
% 130.58/129.71 (??.TPTP_Interpret.ind1,
% 130.58/129.71 {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, True)})}
% 130.58/129.71 bnd_c5_2: {(??.TPTP_Interpret.ind0,
% 130.58/129.71 {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, False)}),
% 130.58/129.71 (??.TPTP_Interpret.ind1,
% 130.58/129.71 {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, False)})}
% 130.58/129.71 bnd_ndr1_1: {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, True)}
% 130.58/129.71 bnd_c8_0: True
% 130.58/129.71 bnd_c8_1: {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, False)}
% 130.58/129.71 bnd_a609: ??.TPTP_Interpret.ind0
% 130.58/129.71 bnd_c5_1: {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, True)}
% 130.58/129.71 bnd_c1_0: True
% 130.58/129.71 bnd_c4_1: {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, False)}
% 130.58/129.71 bnd_c10_1: {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, False)}
% 130.58/129.71 bnd_a608: ??.TPTP_Interpret.ind1
% 130.58/129.71 bnd_c9_1: {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, False)}
% 130.58/129.71 bnd_ndr1_0: True
% 130.58/129.71 bnd_c9_0: True
% 130.58/129.71
% 130.58/129.71 % SZS status CounterSatisfiable
%------------------------------------------------------------------------------