TSTP Solution File: SYN421+1 by Refute---2015
View Problem
- Process Solution
%------------------------------------------------------------------------------
% File : Refute---2015
% Problem : SYN421+1 : TPTP v6.4.0. Released v2.1.0.
% Transfm : none
% Format : tptp:raw
% Command : isabelle tptp_refute %d %s
% Computer : n064.star.cs.uiowa.edu
% Model : x86_64 x86_64
% CPU : Intel(R) Xeon(R) CPU E5-2609 0 2.40GHz
% Memory : 32218.75MB
% OS : Linux 3.10.0-327.10.1.el7.x86_64
% CPULimit : 300s
% DateTime : Thu Apr 14 06:41:42 EDT 2016
% Result : CounterSatisfiable 120.78s
% Output : Assurance 0s
% Verified :
% SZS Type : None (Parsing solution fails)
% Syntax : Number of formulae : 0
% Comments :
%------------------------------------------------------------------------------
%----No solution output by system
%------------------------------------------------------------------------------
%----ORIGINAL SYSTEM OUTPUT
% 0.00/0.03 % Problem : SYN421+1 : TPTP v6.4.0. Released v2.1.0.
% 0.02/0.04 % Command : isabelle tptp_refute %d %s
% 0.03/0.23 % Computer : n064.star.cs.uiowa.edu
% 0.03/0.23 % Model : x86_64 x86_64
% 0.03/0.23 % CPU : Intel(R) Xeon(R) CPU E5-2609 0 @ 2.40GHz
% 0.03/0.23 % Memory : 32218.75MB
% 0.03/0.23 % OS : Linux 3.10.0-327.10.1.el7.x86_64
% 0.03/0.23 % CPULimit : 300
% 0.03/0.23 % DateTime : Fri Apr 8 23:49:09 CDT 2016
% 0.03/0.23 % CPUTime:
% 6.28/5.85 > val it = (): unit
% 7.10/6.64 Trying to find a model that refutes: ~ ((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((bnd_ndr1_0 &
% 7.10/6.64 bnd_c3_1 bnd_a449) &
% 7.10/6.64 bnd_c8_1 bnd_a449) &
% 7.10/6.64 (ALL U.
% 7.10/6.64 bnd_ndr1_1 bnd_a449 -->
% 7.10/6.64 bnd_c9_2 bnd_a449 U | bnd_c4_2 bnd_a449 U) |
% 7.10/6.64 (ALL V.
% 7.10/6.64 bnd_ndr1_0 -->
% 7.10/6.64 (((bnd_ndr1_1 V & bnd_c9_2 V bnd_a450) &
% 7.10/6.64 ~ bnd_c8_2 V bnd_a450) &
% 7.10/6.64 ~ bnd_c6_2 V bnd_a450 |
% 7.10/6.64 ~ bnd_c5_1 V) |
% 7.10/6.64 ~ bnd_c1_1 V)) |
% 7.10/6.64 bnd_c6_0) &
% 7.10/6.64 ((~ bnd_c9_0 | ~ bnd_c2_0) |
% 7.10/6.64 (ALL W.
% 7.10/6.64 bnd_ndr1_0 -->
% 7.10/6.64 ((bnd_ndr1_1 W & bnd_c4_2 W bnd_a451) &
% 7.10/6.64 bnd_c7_2 W bnd_a451 |
% 7.10/6.64 ((bnd_ndr1_1 W & ~ bnd_c2_2 W bnd_a452) &
% 7.10/6.64 bnd_c1_2 W bnd_a452) &
% 7.10/6.64 bnd_c9_2 W bnd_a452) |
% 7.10/6.64 (bnd_ndr1_1 W & ~ bnd_c1_2 W bnd_a453) &
% 7.10/6.64 bnd_c4_2 W bnd_a453))) &
% 7.10/6.64 ((bnd_c7_0 | bnd_c4_0) |
% 7.10/6.64 ((bnd_ndr1_0 & ~ bnd_c4_1 bnd_a454) &
% 7.10/6.64 bnd_c5_1 bnd_a454) &
% 7.10/6.64 ~ bnd_c9_1 bnd_a454)) &
% 7.10/6.64 ((((bnd_ndr1_0 & bnd_c1_1 bnd_a455) &
% 7.10/6.64 ~ bnd_c8_1 bnd_a455) &
% 7.10/6.64 bnd_c9_1 bnd_a455 |
% 7.10/6.64 (ALL X.
% 7.10/6.64 bnd_ndr1_0 -->
% 7.10/6.64 (~ bnd_c4_1 X |
% 7.10/6.64 ((bnd_ndr1_1 X & ~ bnd_c1_2 X bnd_a456) &
% 7.10/6.64 ~ bnd_c6_2 X bnd_a456) &
% 7.10/6.64 ~ bnd_c7_2 X bnd_a456) |
% 7.10/6.64 ~ bnd_c3_1 X)) |
% 7.10/6.64 bnd_c4_0)) &
% 7.10/6.64 ((((((bnd_ndr1_0 & ~ bnd_c2_1 bnd_a457) &
% 7.10/6.64 bnd_c5_1 bnd_a457) &
% 7.10/6.64 bnd_ndr1_1 bnd_a457) &
% 7.10/6.64 ~ bnd_c10_2 bnd_a457 bnd_a458) &
% 7.10/6.64 ~ bnd_c9_2 bnd_a457 bnd_a458 |
% 7.10/6.64 ~ bnd_c2_0) |
% 7.10/6.64 ~ bnd_c9_0)) &
% 7.10/6.64 (~ bnd_c4_0 |
% 7.10/6.64 (ALL Y.
% 7.10/6.64 bnd_ndr1_0 -->
% 7.10/6.64 (bnd_c10_1 Y |
% 7.10/6.64 (ALL Z.
% 7.10/6.64 bnd_ndr1_1 Y -->
% 7.10/6.64 (bnd_c10_2 Y Z | bnd_c2_2 Y Z) |
% 7.10/6.64 bnd_c7_2 Y Z)) |
% 7.10/6.64 ((bnd_ndr1_1 Y & ~ bnd_c9_2 Y bnd_a459) &
% 7.10/6.64 bnd_c2_2 Y bnd_a459) &
% 7.10/6.64 bnd_c8_2 Y bnd_a459))) &
% 7.10/6.64 (((ALL X1.
% 7.10/6.64 bnd_ndr1_0 -->
% 7.10/6.64 ((ALL X2.
% 7.10/6.64 bnd_ndr1_1 X1 -->
% 7.10/6.64 (~ bnd_c7_2 X1 X2 | ~ bnd_c8_2 X1 X2) |
% 7.10/6.64 bnd_c3_2 X1 X2) |
% 7.10/6.64 bnd_c7_1 X1) |
% 7.10/6.64 ~ bnd_c6_1 X1) |
% 7.10/6.64 bnd_c1_0) |
% 7.10/6.64 bnd_c3_0)) &
% 7.10/6.64 (((((((bnd_ndr1_0 & ~ bnd_c7_1 bnd_a460) &
% 7.10/6.64 bnd_c6_1 bnd_a460) &
% 7.10/6.64 bnd_ndr1_1 bnd_a460) &
% 7.10/6.64 bnd_c4_2 bnd_a460 bnd_a461) &
% 7.10/6.64 bnd_c3_2 bnd_a460 bnd_a461) &
% 7.10/6.64 ~ bnd_c10_2 bnd_a460 bnd_a461 |
% 7.10/6.64 ~ bnd_c9_0) |
% 7.10/6.64 ~ bnd_c7_0)) &
% 7.10/6.64 ((bnd_c5_0 |
% 7.10/6.64 (ALL X3.
% 7.10/6.64 bnd_ndr1_0 -->
% 7.10/6.64 ((ALL X4.
% 7.10/6.64 bnd_ndr1_1 X3 -->
% 7.10/6.64 (bnd_c6_2 X3 X4 | ~ bnd_c9_2 X3 X4) |
% 7.10/6.64 bnd_c8_2 X3 X4) |
% 7.10/6.64 ((bnd_ndr1_1 X3 & ~ bnd_c1_2 X3 bnd_a462) &
% 7.10/6.64 bnd_c10_2 X3 bnd_a462) &
% 7.10/6.64 bnd_c2_2 X3 bnd_a462) |
% 7.10/6.64 (ALL X5.
% 7.10/6.64 bnd_ndr1_1 X3 -->
% 7.10/6.64 (bnd_c7_2 X3 X5 | ~ bnd_c1_2 X3 X5) |
% 7.10/6.64 bnd_c6_2 X3 X5))) |
% 7.10/6.64 ((bnd_ndr1_0 &
% 7.10/6.64 (ALL X6.
% 7.10/6.64 bnd_ndr1_1 bnd_a463 -->
% 7.10/6.64 (bnd_c6_2 bnd_a463 X6 | ~ bnd_c3_2 bnd_a463 X6) |
% 7.10/6.64 bnd_c5_2 bnd_a463 X6)) &
% 7.10/6.64 ~ bnd_c9_1 bnd_a463) &
% 7.10/6.64 ~ bnd_c7_1 bnd_a463)) &
% 7.10/6.64 ((~ bnd_c1_0 |
% 7.10/6.64 (((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a464) &
% 7.10/6.64 bnd_c10_2 bnd_a464 bnd_a465) &
% 7.10/6.64 ~ bnd_c6_2 bnd_a464 bnd_a465) &
% 7.10/6.64 ~ bnd_c2_2 bnd_a464 bnd_a465) &
% 7.10/6.64 bnd_c3_1 bnd_a464) &
% 7.10/6.64 bnd_ndr1_1 bnd_a464) &
% 7.10/6.64 bnd_c5_2 bnd_a464 bnd_a466) &
% 7.10/6.64 ~ bnd_c7_2 bnd_a464 bnd_a466) |
% 7.10/6.64 ~ bnd_c9_0)) &
% 7.10/6.64 ((bnd_c4_0 |
% 7.10/6.64 (((((bnd_ndr1_0 & bnd_c4_1 bnd_a467) & bnd_ndr1_1 bnd_a467) &
% 7.10/6.64 bnd_c3_2 bnd_a467 bnd_a468) &
% 7.10/6.64 bnd_c6_2 bnd_a467 bnd_a468) &
% 7.10/6.64 ~ bnd_c10_2 bnd_a467 bnd_a468) &
% 7.10/6.64 bnd_c2_1 bnd_a467) |
% 7.10/6.64 (ALL X7.
% 7.10/6.64 bnd_ndr1_0 -->
% 7.10/6.64 (~ bnd_c8_1 X7 | ~ bnd_c2_1 X7) | ~ bnd_c7_1 X7))) &
% 7.10/6.64 ((bnd_c10_0 |
% 7.10/6.64 ((bnd_ndr1_0 &
% 7.10/6.64 (ALL X8.
% 7.10/6.64 bnd_ndr1_1 bnd_a469 -->
% 7.10/6.64 (~ bnd_c8_2 bnd_a469 X8 | ~ bnd_c6_2 bnd_a469 X8) |
% 7.10/6.64 bnd_c1_2 bnd_a469 X8)) &
% 7.10/6.64 bnd_c6_1 bnd_a469) &
% 7.10/6.64 bnd_c10_1 bnd_a469) |
% 7.10/6.64 ((bnd_ndr1_0 & ~ bnd_c2_1 bnd_a470) &
% 7.10/6.64 (ALL X9.
% 7.10/6.64 bnd_ndr1_1 bnd_a470 -->
% 7.10/6.64 (bnd_c8_2 bnd_a470 X9 | ~ bnd_c4_2 bnd_a470 X9) |
% 7.10/6.64 ~ bnd_c5_2 bnd_a470 X9)) &
% 7.10/6.64 bnd_c8_1 bnd_a470)) &
% 7.10/6.64 ((~ bnd_c2_0 |
% 7.10/6.64 (((((bnd_ndr1_0 & bnd_c9_1 bnd_a471) & bnd_ndr1_1 bnd_a471) &
% 7.10/6.64 bnd_c6_2 bnd_a471 bnd_a472) &
% 7.10/6.64 ~ bnd_c4_2 bnd_a471 bnd_a472) &
% 7.10/6.64 bnd_c3_2 bnd_a471 bnd_a472) &
% 7.10/6.64 ~ bnd_c3_1 bnd_a471) |
% 7.10/6.64 ((bnd_ndr1_0 & bnd_c7_1 bnd_a473) & bnd_c9_1 bnd_a473) &
% 7.10/6.64 (ALL X10.
% 7.10/6.64 bnd_ndr1_1 bnd_a473 -->
% 7.10/6.64 (bnd_c3_2 bnd_a473 X10 | bnd_c8_2 bnd_a473 X10) |
% 7.10/6.64 ~ bnd_c6_2 bnd_a473 X10))) &
% 7.10/6.64 (((ALL X11.
% 7.10/6.64 bnd_ndr1_0 -->
% 7.10/6.64 (bnd_c7_1 X11 |
% 7.10/6.64 (ALL X12.
% 7.10/6.64 bnd_ndr1_1 X11 -->
% 7.10/6.64 (bnd_c5_2 X11 X12 | ~ bnd_c9_2 X11 X12) |
% 7.10/6.64 bnd_c6_2 X11 X12)) |
% 7.10/6.64 bnd_c1_1 X11) |
% 7.10/6.64 bnd_c9_0) |
% 7.10/6.64 ~ bnd_c2_0)) &
% 7.10/6.64 ((bnd_c6_0 |
% 7.10/6.64 (ALL X13.
% 7.10/6.64 bnd_ndr1_0 -->
% 7.10/6.64 (bnd_c10_1 X13 | bnd_c9_1 X13) |
% 7.10/6.64 ((bnd_ndr1_1 X13 & bnd_c8_2 X13 bnd_a474) &
% 7.10/6.64 bnd_c7_2 X13 bnd_a474) &
% 7.10/6.64 ~ bnd_c6_2 X13 bnd_a474)) |
% 7.10/6.64 (((bnd_ndr1_0 & bnd_ndr1_1 bnd_a475) &
% 7.10/6.64 bnd_c9_2 bnd_a475 bnd_a476) &
% 7.10/6.64 ~ bnd_c10_2 bnd_a475 bnd_a476) &
% 7.10/6.64 ~ bnd_c7_2 bnd_a475 bnd_a476)) &
% 7.10/6.64 ((((bnd_ndr1_0 & ~ bnd_c5_1 bnd_a477) & bnd_c1_1 bnd_a477) &
% 7.10/6.64 bnd_c6_1 bnd_a477 |
% 7.10/6.64 ~ bnd_c5_0) |
% 7.10/6.64 ~ bnd_c8_0)) &
% 7.10/6.64 ((((((((((bnd_ndr1_0 & bnd_c7_1 bnd_a478) & bnd_ndr1_1 bnd_a478) &
% 7.10/6.64 bnd_c3_2 bnd_a478 bnd_a479) &
% 7.10/6.64 ~ bnd_c1_2 bnd_a478 bnd_a479) &
% 7.10/6.64 ~ bnd_c8_2 bnd_a478 bnd_a479) &
% 7.10/6.64 bnd_ndr1_1 bnd_a478) &
% 7.10/6.64 bnd_c7_2 bnd_a478 bnd_a480) &
% 7.10/6.64 ~ bnd_c4_2 bnd_a478 bnd_a480) &
% 7.10/6.64 bnd_c2_2 bnd_a478 bnd_a480 |
% 7.10/6.64 bnd_c3_0) |
% 7.10/6.64 ((((((((bnd_ndr1_0 &
% 7.10/6.64 (ALL X14.
% 7.10/6.64 bnd_ndr1_1 bnd_a481 -->
% 7.10/6.64 (~ bnd_c7_2 bnd_a481 X14 | ~ bnd_c3_2 bnd_a481 X14) |
% 7.10/6.64 ~ bnd_c5_2 bnd_a481 X14)) &
% 7.10/6.64 bnd_ndr1_1 bnd_a481) &
% 7.10/6.64 bnd_c4_2 bnd_a481 bnd_a482) &
% 7.10/6.64 bnd_c10_2 bnd_a481 bnd_a482) &
% 7.10/6.64 bnd_c6_2 bnd_a481 bnd_a482) &
% 7.10/6.64 bnd_ndr1_1 bnd_a481) &
% 7.10/6.64 bnd_c5_2 bnd_a481 bnd_a483) &
% 7.10/6.64 bnd_c10_2 bnd_a481 bnd_a483) &
% 7.10/6.64 ~ bnd_c7_2 bnd_a481 bnd_a483)) &
% 7.10/6.64 (~ bnd_c4_0 | ~ bnd_c8_0)) &
% 7.10/6.64 (((((((bnd_ndr1_0 &
% 7.10/6.64 (ALL X15.
% 7.10/6.64 bnd_ndr1_1 bnd_a484 -->
% 7.10/6.64 ~ bnd_c5_2 bnd_a484 X15 | bnd_c7_2 bnd_a484 X15)) &
% 7.10/6.64 (ALL X16.
% 7.10/6.64 bnd_ndr1_1 bnd_a484 -->
% 7.10/6.64 bnd_c10_2 bnd_a484 X16 | bnd_c8_2 bnd_a484 X16)) &
% 7.10/6.64 bnd_ndr1_1 bnd_a484) &
% 7.10/6.64 ~ bnd_c4_2 bnd_a484 bnd_a485) &
% 7.10/6.64 ~ bnd_c8_2 bnd_a484 bnd_a485) &
% 7.10/6.64 ~ bnd_c3_2 bnd_a484 bnd_a485 |
% 7.10/6.64 bnd_c1_0) |
% 7.10/6.64 bnd_c5_0)) &
% 7.10/6.64 (~ bnd_c3_0 |
% 7.10/6.64 (ALL X17.
% 7.10/6.64 bnd_ndr1_0 -->
% 7.10/6.64 (((bnd_ndr1_1 X17 & ~ bnd_c1_2 X17 bnd_a486) &
% 7.10/6.64 ~ bnd_c2_2 X17 bnd_a486) &
% 7.10/6.64 ~ bnd_c9_2 X17 bnd_a486 |
% 7.10/6.64 (ALL X18.
% 7.10/6.64 bnd_ndr1_1 X17 -->
% 7.10/6.64 (~ bnd_c8_2 X17 X18 | bnd_c6_2 X17 X18) |
% 7.10/6.64 ~ bnd_c4_2 X17 X18)) |
% 7.10/6.64 (bnd_ndr1_1 X17 & ~ bnd_c10_2 X17 bnd_a487) &
% 7.10/6.64 bnd_c9_2 X17 bnd_a487))) &
% 7.10/6.64 (((bnd_ndr1_0 & ~ bnd_c9_1 bnd_a488) & bnd_c2_1 bnd_a488 | bnd_c6_0) |
% 7.10/6.64 (((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a489) & ~ bnd_c2_2 bnd_a489 bnd_a490) &
% 7.10/6.64 ~ bnd_c1_2 bnd_a489 bnd_a490) &
% 7.10/6.64 ~ bnd_c5_2 bnd_a489 bnd_a490) &
% 7.10/6.64 ~ bnd_c6_1 bnd_a489) &
% 7.10/6.64 ~ bnd_c10_1 bnd_a489)) &
% 7.10/6.64 ((bnd_c4_0 | (ALL X19. bnd_ndr1_0 --> ~ bnd_c1_1 X19 | bnd_c7_1 X19)) |
% 7.10/6.64 bnd_c3_0)) &
% 7.10/6.64 ((~ bnd_c2_0 | ~ bnd_c9_0) | bnd_c8_0)) &
% 7.10/6.64 (((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a491) & ~ bnd_c6_2 bnd_a491 bnd_a492) &
% 7.10/6.64 bnd_c7_2 bnd_a491 bnd_a492) &
% 7.10/6.64 ~ bnd_c2_2 bnd_a491 bnd_a492) &
% 7.10/6.64 (ALL X20.
% 7.10/6.64 bnd_ndr1_1 bnd_a491 -->
% 7.10/6.64 (~ bnd_c4_2 bnd_a491 X20 | bnd_c10_2 bnd_a491 X20) |
% 7.10/6.64 ~ bnd_c9_2 bnd_a491 X20)) &
% 7.10/6.64 bnd_c1_1 bnd_a491 |
% 7.10/6.64 ~ bnd_c4_0) |
% 7.10/6.64 (ALL X21.
% 7.10/6.64 bnd_ndr1_0 -->
% 7.10/6.64 (bnd_c3_1 X21 |
% 7.10/6.64 (ALL X22.
% 7.10/6.64 bnd_ndr1_1 X21 -->
% 7.10/6.64 (bnd_c6_2 X21 X22 | bnd_c10_2 X21 X22) | bnd_c1_2 X21 X22)) |
% 7.10/6.64 bnd_c1_1 X21))) &
% 7.10/6.64 ((~ bnd_c1_0 |
% 7.10/6.64 (bnd_ndr1_0 & bnd_c9_1 bnd_a493) &
% 7.10/6.64 (ALL X23.
% 7.10/6.64 bnd_ndr1_1 bnd_a493 -->
% 7.10/6.64 ~ bnd_c6_2 bnd_a493 X23 | bnd_c5_2 bnd_a493 X23)) |
% 7.10/6.64 (((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a494) & ~ bnd_c9_2 bnd_a494 bnd_a495) &
% 7.10/6.64 bnd_c10_2 bnd_a494 bnd_a495) &
% 7.10/6.64 ~ bnd_c6_2 bnd_a494 bnd_a495) &
% 7.10/6.64 ~ bnd_c4_1 bnd_a494) &
% 7.10/6.64 ~ bnd_c1_1 bnd_a494)) &
% 7.10/6.64 ((bnd_c1_0 |
% 7.10/6.64 (ALL X24.
% 7.10/6.64 bnd_ndr1_0 -->
% 7.10/6.64 (((bnd_ndr1_1 X24 & bnd_c2_2 X24 bnd_a496) & ~ bnd_c10_2 X24 bnd_a496) &
% 7.10/6.64 bnd_c6_2 X24 bnd_a496 |
% 7.10/6.64 ~ bnd_c1_1 X24) |
% 7.10/6.64 (ALL X25.
% 7.10/6.64 bnd_ndr1_1 X24 -->
% 7.10/6.64 (bnd_c5_2 X24 X25 | bnd_c2_2 X24 X25) | bnd_c8_2 X24 X25))) |
% 7.10/6.64 (ALL X26.
% 7.10/6.64 bnd_ndr1_0 -->
% 7.10/6.64 (((bnd_ndr1_1 X26 & ~ bnd_c4_2 X26 bnd_a497) & bnd_c2_2 X26 bnd_a497) &
% 7.10/6.64 bnd_c9_2 X26 bnd_a497 |
% 7.10/6.64 (bnd_ndr1_1 X26 & bnd_c10_2 X26 bnd_a498) & bnd_c1_2 X26 bnd_a498) |
% 7.10/6.64 (ALL X27.
% 7.10/6.64 bnd_ndr1_1 X26 -->
% 7.10/6.64 (~ bnd_c6_2 X26 X27 | ~ bnd_c1_2 X26 X27) | bnd_c8_2 X26 X27)))) &
% 7.10/6.64 ((bnd_c5_0 | bnd_c6_0) |
% 7.10/6.64 (ALL X28.
% 7.10/6.64 bnd_ndr1_0 -->
% 7.10/6.64 (bnd_c7_1 X28 |
% 7.10/6.64 (ALL X29.
% 7.10/6.64 bnd_ndr1_1 X28 -->
% 7.10/6.64 (~ bnd_c4_2 X28 X29 | bnd_c7_2 X28 X29) | ~ bnd_c9_2 X28 X29)) |
% 7.10/6.64 bnd_c5_1 X28))) &
% 7.10/6.64 ((~ bnd_c5_0 | ~ bnd_c8_0) |
% 7.10/6.64 ((((((((bnd_ndr1_0 &
% 7.10/6.64 ~ bnd_c4_1 bnd_a499) &
% 7.10/6.64 bnd_ndr1_1 bnd_a499) &
% 7.10/6.64 bnd_c10_2 bnd_a499 bnd_a500) &
% 7.10/6.64 ~ bnd_c7_2 bnd_a499 bnd_a500) &
% 7.10/6.64 bnd_c2_2 bnd_a499 bnd_a500) &
% 7.10/6.64 bnd_ndr1_1 bnd_a499) &
% 7.10/6.64 bnd_c10_2 bnd_a499 bnd_a501) &
% 7.10/6.64 bnd_c6_2 bnd_a499 bnd_a501) &
% 7.10/6.64 ~ bnd_c9_2 bnd_a499 bnd_a501)) &
% 7.10/6.64 ((bnd_c8_0 |
% 7.10/6.64 ((((bnd_ndr1_0 & ~ bnd_c5_1 bnd_a502) &
% 7.10/6.64 ~ bnd_c9_1 bnd_a502) &
% 7.10/6.64 bnd_ndr1_1 bnd_a502) &
% 7.10/6.64 ~ bnd_c1_2 bnd_a502 bnd_a503) &
% 7.10/6.64 bnd_c8_2 bnd_a502 bnd_a503) |
% 7.10/6.64 (ALL X30.
% 7.10/6.64 bnd_ndr1_0 -->
% 7.10/6.64 ((ALL X31.
% 7.10/6.64 bnd_ndr1_1 X30 -->
% 7.10/6.64 (bnd_c10_2 X30 X31 | ~ bnd_c7_2 X30 X31) | ~ bnd_c9_2 X30 X31) |
% 7.10/6.64 bnd_c9_1 X30) |
% 7.10/6.64 bnd_c1_1 X30))) &
% 7.10/6.64 (((((((bnd_ndr1_0 & bnd_c10_1 bnd_a504) &
% 7.10/6.64 (ALL X32.
% 7.10/6.64 bnd_ndr1_1 bnd_a504 -->
% 7.10/6.64 (bnd_c1_2 bnd_a504 X32 | ~ bnd_c9_2 bnd_a504 X32) |
% 7.10/6.64 bnd_c7_2 bnd_a504 X32)) &
% 7.10/6.64 bnd_ndr1_1 bnd_a504) &
% 7.10/6.64 ~ bnd_c3_2 bnd_a504 bnd_a505) &
% 7.10/6.64 ~ bnd_c9_2 bnd_a504 bnd_a505) &
% 7.10/6.64 ~ bnd_c2_2 bnd_a504 bnd_a505 |
% 7.10/6.64 ~ bnd_c10_0) |
% 7.10/6.64 (ALL X33.
% 7.10/6.64 bnd_ndr1_0 -->
% 7.10/6.64 (bnd_c3_1 X33 | ~ bnd_c6_1 X33) |
% 7.10/6.64 bnd_c10_1 X33))) &
% 7.10/6.64 (((ALL X34.
% 7.10/6.64 bnd_ndr1_0 -->
% 7.10/6.64 (bnd_c5_1 X34 | bnd_c7_1 X34) |
% 7.10/6.64 ~ bnd_c6_1 X34) |
% 7.10/6.64 bnd_c6_0) |
% 7.10/6.64 bnd_c9_0)) &
% 7.10/6.64 (((ALL X35.
% 7.10/6.64 bnd_ndr1_0 -->
% 7.10/6.64 (((bnd_ndr1_1 X35 &
% 7.10/6.64 bnd_c10_2 X35 bnd_a506) &
% 7.10/6.64 ~ bnd_c3_2 X35 bnd_a506) &
% 7.10/6.64 bnd_c9_2 X35 bnd_a506 |
% 7.10/6.64 (ALL X36.
% 7.10/6.64 bnd_ndr1_1 X35 -->
% 7.10/6.64 (bnd_c7_2 X35 X36 | bnd_c2_2 X35 X36) | ~ bnd_c5_2 X35 X36)) |
% 7.10/6.64 bnd_c1_1 X35) |
% 7.10/6.64 (ALL X37.
% 7.10/6.64 bnd_ndr1_0 -->
% 7.10/6.64 (((bnd_ndr1_1 X37 &
% 7.10/6.64 bnd_c6_2 X37 bnd_a507) &
% 7.10/6.64 ~ bnd_c4_2 X37 bnd_a507) &
% 7.10/6.64 bnd_c3_2 X37 bnd_a507 |
% 7.10/6.64 (ALL X38.
% 7.10/6.64 bnd_ndr1_1 X37 -->
% 7.10/6.64 (bnd_c4_2 X37 X38 | ~ bnd_c6_2 X37 X38) | ~ bnd_c3_2 X37 X38)) |
% 7.10/6.64 ((bnd_ndr1_1 X37 &
% 7.10/6.64 bnd_c7_2 X37 bnd_a508) &
% 7.10/6.64 bnd_c2_2 X37 bnd_a508) &
% 7.10/6.64 bnd_c3_2 X37 bnd_a508)) |
% 7.10/6.64 (((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a509) &
% 7.10/6.64 ~ bnd_c2_2 bnd_a509 bnd_a510) &
% 7.10/6.64 ~ bnd_c10_2 bnd_a509 bnd_a510) &
% 7.10/6.64 bnd_c3_2 bnd_a509 bnd_a510) &
% 7.10/6.64 bnd_c6_1 bnd_a509) &
% 7.10/6.64 ~ bnd_c3_1 bnd_a509)) &
% 7.10/6.64 (((ALL X39.
% 7.10/6.64 bnd_ndr1_0 -->
% 7.10/6.64 ((bnd_ndr1_1 X39 &
% 7.10/6.64 bnd_c6_2 X39 bnd_a511) &
% 7.10/6.64 ~ bnd_c5_2 X39 bnd_a511 |
% 7.10/6.64 (ALL X40.
% 7.10/6.64 bnd_ndr1_1 X39 --> ~ bnd_c4_2 X39 X40 | bnd_c10_2 X39 X40)) |
% 7.10/6.64 ((bnd_ndr1_1 X39 &
% 7.10/6.64 bnd_c7_2 X39 bnd_a512) &
% 7.10/6.64 bnd_c1_2 X39 bnd_a512) &
% 7.10/6.64 bnd_c2_2 X39 bnd_a512) |
% 7.10/6.64 ((bnd_ndr1_0 & bnd_c9_1 bnd_a513) &
% 7.10/6.64 ~ bnd_c6_1 bnd_a513) &
% 7.10/6.64 (ALL X41.
% 7.10/6.64 bnd_ndr1_1 bnd_a513 -->
% 7.10/6.64 (bnd_c10_2 bnd_a513 X41 |
% 7.10/6.64 bnd_c1_2 bnd_a513 X41) |
% 7.10/6.64 bnd_c9_2 bnd_a513 X41)) |
% 7.10/6.64 ~ bnd_c5_0)) &
% 7.10/6.64 ((~ bnd_c7_0 |
% 7.10/6.64 ((bnd_ndr1_0 & bnd_c1_1 bnd_a514) &
% 7.10/6.64 ~ bnd_c2_1 bnd_a514) &
% 7.10/6.64 bnd_c10_1 bnd_a514) |
% 7.10/6.64 ~ bnd_c6_0)) &
% 7.10/6.64 ((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a515) &
% 7.10/6.64 ~ bnd_c6_2 bnd_a515 bnd_a516) &
% 7.10/6.64 ~ bnd_c10_2 bnd_a515 bnd_a516) &
% 7.10/6.64 bnd_c8_1 bnd_a515) &
% 7.10/6.64 (ALL X42.
% 7.10/6.64 bnd_ndr1_1 bnd_a515 -->
% 7.10/6.64 (bnd_c5_2 bnd_a515 X42 |
% 7.10/6.64 ~ bnd_c10_2 bnd_a515 X42) |
% 7.10/6.64 ~ bnd_c1_2 bnd_a515 X42) |
% 7.10/6.64 (ALL X43.
% 7.10/6.64 bnd_ndr1_0 -->
% 7.10/6.64 bnd_c5_1 X43 | bnd_c9_1 X43)) |
% 7.10/6.64 ~ bnd_c9_0)) &
% 7.10/6.64 ((ALL X44.
% 7.10/6.64 bnd_ndr1_0 -->
% 7.10/6.64 (bnd_c7_1 X44 |
% 7.10/6.64 (ALL X45.
% 7.10/6.64 bnd_ndr1_1 X44 -->
% 7.10/6.64 (~ bnd_c4_2 X44 X45 |
% 7.10/6.64 bnd_c10_2 X44 X45) |
% 7.10/6.64 bnd_c2_2 X44 X45)) |
% 7.10/6.64 (ALL X46.
% 7.10/6.64 bnd_ndr1_1 X44 -->
% 7.10/6.64 (bnd_c3_2 X44 X46 | bnd_c4_2 X44 X46) |
% 7.10/6.64 ~ bnd_c2_2 X44 X46)) |
% 7.10/6.64 ~ bnd_c1_0)) &
% 7.10/6.64 (((((((bnd_ndr1_0 &
% 7.10/6.64 (ALL X47.
% 7.10/6.64 bnd_ndr1_1 bnd_a517 -->
% 7.10/6.64 ~ bnd_c10_2 bnd_a517 X47 |
% 7.10/6.64 bnd_c4_2 bnd_a517 X47)) &
% 7.10/6.64 bnd_c9_1 bnd_a517) &
% 7.10/6.64 bnd_ndr1_1 bnd_a517) &
% 7.10/6.64 bnd_c8_2 bnd_a517 bnd_a518) &
% 7.10/6.64 bnd_c9_2 bnd_a517 bnd_a518) &
% 7.10/6.64 ~ bnd_c1_2 bnd_a517 bnd_a518 |
% 7.10/6.64 (((((bnd_ndr1_0 & bnd_c9_1 bnd_a519) &
% 7.10/6.64 bnd_ndr1_1 bnd_a519) &
% 7.10/6.64 ~ bnd_c5_2 bnd_a519 bnd_a520) &
% 7.10/6.64 ~ bnd_c7_2 bnd_a519 bnd_a520) &
% 7.10/6.64 bnd_c9_2 bnd_a519 bnd_a520) &
% 7.10/6.64 ~ bnd_c8_1 bnd_a519) |
% 7.10/6.64 bnd_c3_0)) &
% 7.10/6.64 ((bnd_c5_0 | bnd_c9_0) |
% 7.10/6.64 (((((bnd_ndr1_0 & ~ bnd_c10_1 bnd_a521) &
% 7.10/6.64 bnd_ndr1_1 bnd_a521) &
% 7.10/6.64 bnd_c1_2 bnd_a521 bnd_a522) &
% 7.10/6.64 bnd_c6_2 bnd_a521 bnd_a522) &
% 7.10/6.64 ~ bnd_c9_2 bnd_a521 bnd_a522) &
% 7.10/6.64 bnd_c7_1 bnd_a521)) &
% 7.10/6.64 (((ALL X48.
% 7.10/6.64 bnd_ndr1_0 -->
% 7.10/6.64 ((ALL X49.
% 7.10/6.64 bnd_ndr1_1 X48 -->
% 7.10/6.64 (~ bnd_c7_2 X48 X49 | bnd_c2_2 X48 X49) |
% 7.10/6.64 bnd_c8_2 X48 X49) |
% 7.10/6.64 (ALL X50.
% 7.10/6.64 bnd_ndr1_1 X48 -->
% 7.10/6.64 (bnd_c9_2 X48 X50 | ~ bnd_c4_2 X48 X50) |
% 7.10/6.64 bnd_c1_2 X48 X50)) |
% 7.10/6.64 ~ bnd_c7_1 X48) |
% 7.10/6.64 ~ bnd_c8_0) |
% 7.10/6.64 ~ bnd_c10_0)) &
% 7.10/6.64 ((bnd_c1_0 |
% 7.10/6.64 (((((bnd_ndr1_0 & ~ bnd_c3_1 bnd_a523) &
% 7.10/6.64 bnd_c4_1 bnd_a523) &
% 7.10/6.64 bnd_ndr1_1 bnd_a523) &
% 7.10/6.64 ~ bnd_c2_2 bnd_a523 bnd_a524) &
% 7.10/6.64 bnd_c4_2 bnd_a523 bnd_a524) &
% 7.10/6.64 bnd_c8_2 bnd_a523 bnd_a524) |
% 7.10/6.64 ((bnd_ndr1_0 & ~ bnd_c7_1 bnd_a525) &
% 7.10/6.64 bnd_c8_1 bnd_a525) &
% 7.10/6.64 ~ bnd_c6_1 bnd_a525)) &
% 7.10/6.64 (((ALL X51.
% 7.10/6.64 bnd_ndr1_0 -->
% 7.10/6.64 (~ bnd_c4_1 X51 | ~ bnd_c1_1 X51) |
% 7.10/6.64 ((bnd_ndr1_1 X51 & ~ bnd_c9_2 X51 bnd_a526) &
% 7.10/6.64 ~ bnd_c2_2 X51 bnd_a526) &
% 7.10/6.64 bnd_c6_2 X51 bnd_a526) |
% 7.10/6.64 ~ bnd_c10_0) |
% 7.10/6.64 bnd_c9_0)) &
% 7.10/6.64 ((~ bnd_c5_0 |
% 7.10/6.64 (ALL X52.
% 7.10/6.64 bnd_ndr1_0 -->
% 7.10/6.64 (~ bnd_c6_1 X52 | ~ bnd_c9_1 X52) |
% 7.10/6.64 ((bnd_ndr1_1 X52 & bnd_c8_2 X52 bnd_a527) &
% 7.10/6.64 bnd_c9_2 X52 bnd_a527) &
% 7.10/6.64 bnd_c7_2 X52 bnd_a527)) |
% 7.10/6.64 (ALL X53.
% 7.10/6.64 bnd_ndr1_0 -->
% 7.10/6.64 (~ bnd_c5_1 X53 |
% 7.10/6.64 ((bnd_ndr1_1 X53 & ~ bnd_c4_2 X53 bnd_a528) &
% 7.10/6.64 ~ bnd_c2_2 X53 bnd_a528) &
% 7.10/6.64 ~ bnd_c3_2 X53 bnd_a528) |
% 7.10/6.64 ~ bnd_c2_1 X53))) &
% 7.10/6.64 (bnd_c5_0 | bnd_c4_0)) &
% 7.10/6.64 (bnd_c10_0 |
% 7.10/6.64 (ALL X54.
% 7.10/6.64 bnd_ndr1_0 -->
% 7.10/6.64 ((ALL X55.
% 7.10/6.64 bnd_ndr1_1 X54 -->
% 7.10/6.64 bnd_c1_2 X54 X55 | ~ bnd_c10_2 X54 X55) |
% 7.10/6.64 ((bnd_ndr1_1 X54 & bnd_c3_2 X54 bnd_a529) &
% 7.10/6.64 bnd_c2_2 X54 bnd_a529) &
% 7.10/6.64 bnd_c7_2 X54 bnd_a529) |
% 7.10/6.64 ((bnd_ndr1_1 X54 & bnd_c9_2 X54 bnd_a530) &
% 7.10/6.64 ~ bnd_c1_2 X54 bnd_a530) &
% 7.10/6.64 bnd_c6_2 X54 bnd_a530))) &
% 7.10/6.64 ((bnd_c8_0 | ~ bnd_c10_0) | ~ bnd_c3_0)) &
% 7.10/6.64 ((~ bnd_c3_0 |
% 7.10/6.64 (ALL X56.
% 7.10/6.64 bnd_ndr1_0 -->
% 7.10/6.64 (((bnd_ndr1_1 X56 & ~ bnd_c10_2 X56 bnd_a531) &
% 7.10/6.64 bnd_c5_2 X56 bnd_a531) &
% 7.10/6.64 ~ bnd_c6_2 X56 bnd_a531 |
% 7.10/6.64 ~ bnd_c1_1 X56) |
% 7.10/6.64 ((bnd_ndr1_1 X56 & ~ bnd_c4_2 X56 bnd_a532) &
% 7.10/6.64 bnd_c9_2 X56 bnd_a532) &
% 7.10/6.64 ~ bnd_c1_2 X56 bnd_a532)) |
% 7.10/6.64 ((((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a533) &
% 7.10/6.64 bnd_c8_2 bnd_a533 bnd_a534) &
% 7.10/6.64 ~ bnd_c3_2 bnd_a533 bnd_a534) &
% 7.10/6.64 ~ bnd_c7_2 bnd_a533 bnd_a534) &
% 7.10/6.64 ~ bnd_c1_1 bnd_a533) &
% 7.10/6.64 bnd_ndr1_1 bnd_a533) &
% 7.10/6.64 ~ bnd_c1_2 bnd_a533 bnd_a535) &
% 7.10/6.64 ~ bnd_c3_2 bnd_a533 bnd_a535) &
% 7.10/6.64 ~ bnd_c4_2 bnd_a533 bnd_a535)) &
% 7.10/6.64 (((ALL X57.
% 7.10/6.64 bnd_ndr1_0 -->
% 7.10/6.64 (bnd_c2_1 X57 |
% 7.10/6.64 ((bnd_ndr1_1 X57 & ~ bnd_c4_2 X57 bnd_a536) &
% 7.10/6.64 bnd_c9_2 X57 bnd_a536) &
% 7.10/6.64 ~ bnd_c3_2 X57 bnd_a536) |
% 7.10/6.64 bnd_c6_1 X57) |
% 7.10/6.64 ((bnd_ndr1_0 & bnd_c5_1 bnd_a537) & ~ bnd_c9_1 bnd_a537) &
% 7.10/6.64 ~ bnd_c8_1 bnd_a537) |
% 7.10/6.64 ((((((((bnd_ndr1_0 &
% 7.10/6.64 (ALL X58.
% 7.10/6.64 bnd_ndr1_1 bnd_a538 -->
% 7.10/6.64 (~ bnd_c2_2 bnd_a538 X58 |
% 7.10/6.64 bnd_c10_2 bnd_a538 X58) |
% 7.10/6.64 bnd_c9_2 bnd_a538 X58)) &
% 7.10/6.64 bnd_ndr1_1 bnd_a538) &
% 7.10/6.64 bnd_c3_2 bnd_a538 bnd_a539) &
% 7.10/6.64 ~ bnd_c6_2 bnd_a538 bnd_a539) &
% 7.10/6.64 ~ bnd_c5_2 bnd_a538 bnd_a539) &
% 7.10/6.64 bnd_ndr1_1 bnd_a538) &
% 7.10/6.64 bnd_c9_2 bnd_a538 bnd_a540) &
% 7.10/6.64 ~ bnd_c4_2 bnd_a538 bnd_a540) &
% 7.10/6.64 bnd_c6_2 bnd_a538 bnd_a540)) &
% 7.10/6.64 ((bnd_c3_0 |
% 7.10/6.64 ((bnd_ndr1_0 & ~ bnd_c9_1 bnd_a541) & bnd_c10_1 bnd_a541) &
% 7.10/6.64 ~ bnd_c1_1 bnd_a541) |
% 7.10/6.64 bnd_c10_0)) &
% 7.10/6.64 ((~ bnd_c10_0 |
% 7.10/6.64 (ALL X59.
% 7.10/6.64 bnd_ndr1_0 -->
% 7.10/6.64 (((bnd_ndr1_1 X59 & bnd_c1_2 X59 bnd_a542) &
% 7.10/6.64 bnd_c5_2 X59 bnd_a542) &
% 7.10/6.64 ~ bnd_c6_2 X59 bnd_a542 |
% 7.10/6.64 ((bnd_ndr1_1 X59 & ~ bnd_c5_2 X59 bnd_a543) &
% 7.10/6.64 bnd_c1_2 X59 bnd_a543) &
% 7.10/6.64 bnd_c4_2 X59 bnd_a543) |
% 7.10/6.64 (ALL X60.
% 7.10/6.64 bnd_ndr1_1 X59 -->
% 7.10/6.64 (~ bnd_c7_2 X59 X60 | bnd_c6_2 X59 X60) |
% 7.10/6.64 ~ bnd_c2_2 X59 X60))) |
% 7.10/6.64 bnd_c9_0)) &
% 7.10/6.64 (((ALL X61.
% 7.10/6.64 bnd_ndr1_0 -->
% 7.10/6.64 bnd_c5_1 X61 |
% 7.10/6.64 ((bnd_ndr1_1 X61 & bnd_c9_2 X61 bnd_a544) &
% 7.10/6.64 bnd_c4_2 X61 bnd_a544) &
% 7.10/6.64 ~ bnd_c8_2 X61 bnd_a544) |
% 7.10/6.64 bnd_c8_0) |
% 7.10/6.64 (ALL X62.
% 7.10/6.64 bnd_ndr1_0 -->
% 7.10/6.64 (bnd_c7_1 X62 |
% 7.10/6.64 (bnd_ndr1_1 X62 & ~ bnd_c4_2 X62 bnd_a545) &
% 7.10/6.64 ~ bnd_c10_2 X62 bnd_a545) |
% 7.10/6.64 bnd_c2_1 X62))) &
% 7.10/6.64 (~ bnd_c7_0 | ~ bnd_c2_0)) &
% 7.10/6.64 (((ALL X63.
% 7.10/6.64 bnd_ndr1_0 -->
% 7.10/6.64 (~ bnd_c2_1 X63 |
% 7.10/6.64 ((bnd_ndr1_1 X63 & bnd_c7_2 X63 bnd_a546) &
% 7.10/6.64 ~ bnd_c4_2 X63 bnd_a546) &
% 7.10/6.64 ~ bnd_c1_2 X63 bnd_a546) |
% 7.10/6.64 bnd_c1_1 X63) |
% 7.10/6.64 (bnd_ndr1_0 & bnd_c6_1 bnd_a547) & bnd_c5_1 bnd_a547) |
% 7.10/6.64 ~ bnd_c10_0)) &
% 7.10/6.64 (((ALL X64.
% 7.10/6.64 bnd_ndr1_0 -->
% 7.10/6.64 (~ bnd_c5_1 X64 |
% 7.10/6.64 (ALL X65.
% 7.10/6.64 bnd_ndr1_1 X64 -->
% 7.10/6.64 (bnd_c3_2 X64 X65 | bnd_c10_2 X64 X65) |
% 7.10/6.64 bnd_c2_2 X64 X65)) |
% 7.10/6.64 ((bnd_ndr1_1 X64 & ~ bnd_c6_2 X64 bnd_a548) &
% 7.10/6.64 bnd_c9_2 X64 bnd_a548) &
% 7.10/6.64 ~ bnd_c2_2 X64 bnd_a548) |
% 7.10/6.64 bnd_c10_0) |
% 7.10/6.64 ((bnd_ndr1_0 & ~ bnd_c10_1 bnd_a549) & bnd_c2_1 bnd_a549) &
% 7.10/6.64 (ALL X66.
% 7.10/6.64 bnd_ndr1_1 bnd_a549 -->
% 7.10/6.64 (~ bnd_c8_2 bnd_a549 X66 | ~ bnd_c4_2 bnd_a549 X66) |
% 7.10/6.64 ~ bnd_c1_2 bnd_a549 X66))) &
% 7.10/6.64 ((bnd_c10_0 | bnd_c2_0) | ~ bnd_c3_0)) &
% 7.10/6.64 ((bnd_c2_0 | bnd_c9_0) |
% 7.10/6.64 ((bnd_ndr1_0 &
% 7.10/6.64 (ALL X67.
% 7.10/6.64 bnd_ndr1_1 bnd_a550 -->
% 7.10/6.64 (bnd_c5_2 bnd_a550 X67 | ~ bnd_c8_2 bnd_a550 X67) |
% 7.10/6.64 ~ bnd_c3_2 bnd_a550 X67)) &
% 7.10/6.64 (ALL X68.
% 7.10/6.64 bnd_ndr1_1 bnd_a550 -->
% 7.10/6.64 (~ bnd_c6_2 bnd_a550 X68 | bnd_c1_2 bnd_a550 X68) |
% 7.10/6.64 ~ bnd_c8_2 bnd_a550 X68)) &
% 7.10/6.64 bnd_c9_1 bnd_a550)) &
% 7.10/6.64 ((~ bnd_c8_0 | ~ bnd_c10_0) | ~ bnd_c1_0)) &
% 7.10/6.64 ((~ bnd_c3_0 | bnd_c2_0) | bnd_c8_0)) &
% 7.10/6.64 ((bnd_c1_0 | ~ bnd_c7_0) |
% 7.10/6.64 (((((bnd_ndr1_0 & bnd_c8_1 bnd_a551) & ~ bnd_c9_1 bnd_a551) &
% 7.10/6.64 bnd_ndr1_1 bnd_a551) &
% 7.10/6.64 bnd_c2_2 bnd_a551 bnd_a552) &
% 7.10/6.64 bnd_c6_2 bnd_a551 bnd_a552) &
% 7.10/6.64 ~ bnd_c3_2 bnd_a551 bnd_a552)) &
% 7.10/6.64 ((bnd_c5_0 | bnd_c6_0) | ~ bnd_c8_0)) &
% 7.10/6.64 ((ALL X69.
% 7.10/6.64 bnd_ndr1_0 -->
% 7.10/6.64 (~ bnd_c8_1 X69 |
% 7.10/6.64 ((bnd_ndr1_1 X69 & bnd_c7_2 X69 bnd_a553) &
% 7.10/6.64 bnd_c10_2 X69 bnd_a553) &
% 7.10/6.64 bnd_c8_2 X69 bnd_a553) |
% 7.10/6.64 (ALL X70.
% 7.10/6.64 bnd_ndr1_1 X69 -->
% 7.10/6.64 (~ bnd_c9_2 X69 X70 | ~ bnd_c5_2 X69 X70) | bnd_c8_2 X69 X70)) |
% 7.10/6.64 bnd_c4_0)) &
% 7.10/6.64 ((~ bnd_c7_0 | ~ bnd_c1_0) |
% 7.10/6.64 (ALL X71.
% 7.10/6.64 bnd_ndr1_0 --> (~ bnd_c4_1 X71 | bnd_c5_1 X71) | bnd_c6_1 X71))) &
% 7.10/6.64 ((bnd_c8_0 | ~ bnd_c2_0) |
% 7.10/6.64 ((bnd_ndr1_0 & ~ bnd_c2_1 bnd_a554) & bnd_c8_1 bnd_a554) &
% 7.10/6.64 ~ bnd_c3_1 bnd_a554)) &
% 7.10/6.64 ((bnd_c4_0 | ~ bnd_c5_0) |
% 7.10/6.64 ~ bnd_c3_0)) &
% 7.10/6.64 (((ALL X72.
% 7.10/6.64 bnd_ndr1_0 -->
% 7.10/6.64 (~ bnd_c4_1 X72 |
% 7.10/6.64 (ALL X73.
% 7.10/6.64 bnd_ndr1_1 X72 --> ~ bnd_c2_2 X72 X73 | ~ bnd_c8_2 X72 X73)) |
% 7.10/6.64 ((bnd_ndr1_1 X72 & ~ bnd_c4_2 X72 bnd_a555) & bnd_c3_2 X72 bnd_a555) &
% 7.10/6.64 ~ bnd_c9_2 X72 bnd_a555) |
% 7.10/6.64 (ALL X74.
% 7.10/6.64 bnd_ndr1_0 -->
% 7.10/6.64 ((ALL X75.
% 7.10/6.64 bnd_ndr1_1 X74 -->
% 7.10/6.64 (~ bnd_c6_2 X74 X75 | bnd_c5_2 X74 X75) | bnd_c2_2 X74 X75) |
% 7.10/6.64 ~ bnd_c6_1 X74) |
% 7.10/6.64 (ALL X76.
% 7.10/6.64 bnd_ndr1_1 X74 -->
% 7.10/6.64 (~ bnd_c3_2 X74 X76 | bnd_c4_2 X74 X76) | bnd_c1_2 X74 X76))) |
% 7.10/6.64 ~ bnd_c6_0)) &
% 7.10/6.64 (((ALL X77.
% 7.10/6.64 bnd_ndr1_0 --> (~ bnd_c1_1 X77 | bnd_c9_1 X77) | bnd_c5_1 X77) |
% 7.10/6.64 bnd_c4_0) |
% 7.10/6.64 bnd_c8_0)) &
% 7.10/6.64 (((bnd_ndr1_0 &
% 7.10/6.64 (ALL X78.
% 7.10/6.64 bnd_ndr1_1 bnd_a556 -->
% 7.10/6.64 (bnd_c8_2 bnd_a556 X78 | bnd_c5_2 bnd_a556 X78) |
% 7.10/6.64 ~ bnd_c1_2 bnd_a556 X78)) &
% 7.10/6.64 ~ bnd_c5_1 bnd_a556) &
% 7.10/6.64 ~ bnd_c8_1 bnd_a556 |
% 7.10/6.64 ~ bnd_c3_0)) &
% 7.10/6.64 (bnd_c4_0 |
% 7.10/6.64 (ALL X79.
% 7.10/6.64 bnd_ndr1_0 -->
% 7.10/6.64 (bnd_c8_1 X79 | bnd_c10_1 X79) |
% 7.10/6.64 ((bnd_ndr1_1 X79 & ~ bnd_c8_2 X79 bnd_a557) & bnd_c1_2 X79 bnd_a557) &
% 7.10/6.64 ~ bnd_c6_2 X79 bnd_a557))) &
% 7.10/6.64 (((ALL X80.
% 7.10/6.64 bnd_ndr1_0 -->
% 7.10/6.64 (~ bnd_c3_1 X80 | ~ bnd_c9_1 X80) |
% 7.10/6.64 ((bnd_ndr1_1 X80 & ~ bnd_c9_2 X80 bnd_a558) & ~ bnd_c3_2 X80 bnd_a558) &
% 7.10/6.64 ~ bnd_c4_2 X80 bnd_a558) |
% 7.10/6.64 (ALL X81.
% 7.10/6.64 bnd_ndr1_0 -->
% 7.10/6.64 ((bnd_ndr1_1 X81 & ~ bnd_c8_2 X81 bnd_a559) & ~ bnd_c7_2 X81 bnd_a559) &
% 7.10/6.64 ~ bnd_c4_2 X81 bnd_a559)) |
% 7.10/6.64 (ALL X82.
% 7.10/6.64 bnd_ndr1_0 -->
% 7.10/6.64 (~ bnd_c2_1 X82 | bnd_c7_1 X82) |
% 7.10/6.64 (ALL X83.
% 7.10/6.64 bnd_ndr1_1 X82 -->
% 7.10/6.64 (~ bnd_c3_2 X82 X83 | ~ bnd_c6_2 X82 X83) | ~ bnd_c4_2 X82 X83)))) &
% 7.10/6.64 ((bnd_c1_0 | bnd_c4_0) | bnd_c10_0)) &
% 7.10/6.64 (((((bnd_ndr1_0 &
% 7.10/6.64 (ALL X84.
% 7.10/6.64 bnd_ndr1_1 bnd_a560 -->
% 7.10/6.64 (bnd_c10_2 bnd_a560 X84 | bnd_c3_2 bnd_a560 X84) |
% 7.10/6.64 ~ bnd_c8_2 bnd_a560 X84)) &
% 7.10/6.64 bnd_ndr1_1 bnd_a560) &
% 7.10/6.64 bnd_c2_2 bnd_a560 bnd_a561) &
% 7.10/6.64 bnd_c1_2 bnd_a560 bnd_a561 |
% 7.10/6.64 ~ bnd_c10_0) |
% 7.10/6.64 (ALL X85.
% 7.10/6.64 bnd_ndr1_0 -->
% 7.10/6.64 (bnd_c5_1 X85 | bnd_c9_1 X85) |
% 7.10/6.64 bnd_c7_1 X85))) &
% 7.10/6.64 (((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a562) &
% 7.10/6.64 bnd_c10_2 bnd_a562 bnd_a563) &
% 7.10/6.64 bnd_c4_2 bnd_a562 bnd_a563) &
% 7.10/6.64 ~ bnd_c1_2 bnd_a562 bnd_a563) &
% 7.10/6.64 (ALL X86.
% 7.10/6.64 bnd_ndr1_1 bnd_a562 -->
% 7.10/6.64 bnd_c9_2 bnd_a562 X86 |
% 7.10/6.64 bnd_c6_2 bnd_a562 X86)) &
% 7.10/6.64 bnd_c6_1 bnd_a562 |
% 7.10/6.64 bnd_c9_0) |
% 7.10/6.64 ~ bnd_c8_0)) &
% 7.10/6.64 (((ALL X87.
% 7.10/6.64 bnd_ndr1_0 -->
% 7.10/6.64 (~ bnd_c5_1 X87 |
% 7.10/6.64 (ALL X88.
% 7.10/6.64 bnd_ndr1_1 X87 -->
% 7.10/6.64 (~ bnd_c8_2 X87 X88 | ~ bnd_c5_2 X87 X88) | ~ bnd_c10_2 X87 X88)) |
% 7.10/6.64 (ALL X89.
% 7.10/6.64 bnd_ndr1_1 X87 -->
% 7.10/6.64 (~ bnd_c5_2 X87 X89 | ~ bnd_c3_2 X87 X89) | bnd_c10_2 X87 X89)) |
% 7.10/6.64 (ALL X90.
% 7.10/6.64 bnd_ndr1_0 -->
% 7.10/6.64 ((bnd_ndr1_1 X90 &
% 7.10/6.64 ~ bnd_c9_2 X90 bnd_a564) &
% 7.10/6.64 ~ bnd_c2_2 X90 bnd_a564 |
% 7.10/6.64 ~ bnd_c7_1 X90) |
% 7.10/6.64 ((bnd_ndr1_1 X90 &
% 7.10/6.64 bnd_c4_2 X90 bnd_a565) &
% 7.10/6.64 ~ bnd_c3_2 X90 bnd_a565) &
% 7.10/6.64 ~ bnd_c5_2 X90 bnd_a565)) |
% 7.10/6.64 ((bnd_ndr1_0 &
% 7.10/6.64 (ALL X91.
% 7.10/6.64 bnd_ndr1_1 bnd_a566 -->
% 7.10/6.64 (bnd_c5_2 bnd_a566 X91 |
% 7.10/6.64 bnd_c6_2 bnd_a566 X91) |
% 7.10/6.64 ~ bnd_c9_2 bnd_a566 X91)) &
% 7.10/6.64 ~ bnd_c3_1 bnd_a566) &
% 7.10/6.64 (ALL X92.
% 7.10/6.64 bnd_ndr1_1 bnd_a566 -->
% 7.10/6.64 (~ bnd_c7_2 bnd_a566 X92 |
% 7.10/6.64 bnd_c3_2 bnd_a566 X92) |
% 7.10/6.64 ~ bnd_c5_2 bnd_a566 X92))) &
% 7.10/6.64 ((~ bnd_c10_0 | ~ bnd_c1_0) | ~ bnd_c2_0)) &
% 7.10/6.64 (((ALL X93.
% 7.10/6.64 bnd_ndr1_0 -->
% 7.10/6.64 (((bnd_ndr1_1 X93 &
% 7.10/6.64 ~ bnd_c2_2 X93 bnd_a567) &
% 7.10/6.64 bnd_c6_2 X93 bnd_a567) &
% 7.10/6.64 ~ bnd_c3_2 X93 bnd_a567 |
% 7.10/6.64 (ALL X94.
% 7.10/6.64 bnd_ndr1_1 X93 -->
% 7.10/6.64 (~ bnd_c5_2 X93 X94 |
% 7.10/6.64 ~ bnd_c1_2 X93 X94) |
% 7.10/6.64 ~ bnd_c7_2 X93 X94)) |
% 7.10/6.64 (bnd_ndr1_1 X93 & bnd_c9_2 X93 bnd_a568) &
% 7.10/6.64 ~ bnd_c10_2 X93 bnd_a568) |
% 7.10/6.64 ~ bnd_c4_0) |
% 7.10/6.64 ((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a569) &
% 7.10/6.64 bnd_c5_2 bnd_a569 bnd_a570) &
% 7.10/6.64 ~ bnd_c7_2 bnd_a569 bnd_a570) &
% 7.10/6.64 ~ bnd_c1_2 bnd_a569 bnd_a570) &
% 7.10/6.64 bnd_c3_1 bnd_a569)) &
% 7.10/6.64 (((((bnd_ndr1_0 & bnd_c5_1 bnd_a571) &
% 7.10/6.64 bnd_ndr1_1 bnd_a571) &
% 7.10/6.64 bnd_c9_2 bnd_a571 bnd_a572) &
% 7.10/6.64 ~ bnd_c8_2 bnd_a571 bnd_a572) &
% 7.10/6.64 ~ bnd_c3_1 bnd_a571 |
% 7.10/6.64 bnd_c1_0)) &
% 7.10/6.64 ((bnd_c3_0 | bnd_c6_0) | ~ bnd_c2_0)) &
% 7.10/6.64 ((~ bnd_c9_0 | ~ bnd_c5_0) | bnd_c10_0)) &
% 7.10/6.64 ((~ bnd_c1_0 | ~ bnd_c8_0) |
% 7.10/6.64 ((bnd_ndr1_0 & bnd_c9_1 bnd_a573) &
% 7.10/6.64 (ALL X95.
% 7.10/6.64 bnd_ndr1_1 bnd_a573 -->
% 7.10/6.64 (bnd_c9_2 bnd_a573 X95 |
% 7.10/6.64 ~ bnd_c7_2 bnd_a573 X95) |
% 7.10/6.64 bnd_c8_2 bnd_a573 X95)) &
% 7.10/6.64 (ALL X96.
% 7.10/6.64 bnd_ndr1_1 bnd_a573 -->
% 7.10/6.64 ~ bnd_c7_2 bnd_a573 X96 |
% 7.10/6.64 bnd_c8_2 bnd_a573 X96))) &
% 7.10/6.64 ((~ bnd_c6_0 | ~ bnd_c10_0) | ~ bnd_c3_0)) &
% 7.10/6.64 ((~ bnd_c4_0 |
% 7.10/6.64 (ALL X97.
% 7.10/6.64 bnd_ndr1_0 -->
% 7.10/6.64 (~ bnd_c6_1 X97 | ~ bnd_c8_1 X97) |
% 7.10/6.64 ((bnd_ndr1_1 X97 & bnd_c6_2 X97 bnd_a574) &
% 7.10/6.64 bnd_c4_2 X97 bnd_a574) &
% 7.10/6.64 bnd_c7_2 X97 bnd_a574)) |
% 7.10/6.64 bnd_c2_0)) &
% 7.10/6.64 (((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a575) &
% 7.10/6.64 ~ bnd_c8_2 bnd_a575 bnd_a576) &
% 7.10/6.64 bnd_c9_2 bnd_a575 bnd_a576) &
% 7.10/6.64 bnd_c5_2 bnd_a575 bnd_a576) &
% 7.10/6.64 bnd_c7_1 bnd_a575) &
% 7.10/6.64 bnd_c5_1 bnd_a575 |
% 7.10/6.64 bnd_c7_0) |
% 7.10/6.64 ((bnd_ndr1_0 & ~ bnd_c1_1 bnd_a577) &
% 7.10/6.64 ~ bnd_c8_1 bnd_a577) &
% 7.10/6.64 ~ bnd_c6_1 bnd_a577)) &
% 7.10/6.64 (((((((bnd_ndr1_0 & ~ bnd_c8_1 bnd_a578) &
% 7.10/6.64 bnd_c1_1 bnd_a578) &
% 7.10/6.64 bnd_ndr1_1 bnd_a578) &
% 7.10/6.64 bnd_c7_2 bnd_a578 bnd_a579) &
% 7.10/6.64 bnd_c2_2 bnd_a578 bnd_a579) &
% 7.10/6.64 ~ bnd_c8_2 bnd_a578 bnd_a579 |
% 7.10/6.64 bnd_c10_0) |
% 7.10/6.64 bnd_c9_0)) &
% 7.10/6.64 (((ALL X98.
% 7.10/6.64 bnd_ndr1_0 -->
% 7.10/6.64 (~ bnd_c3_1 X98 | bnd_c7_1 X98) |
% 7.10/6.64 ((bnd_ndr1_1 X98 & bnd_c6_2 X98 bnd_a580) &
% 7.10/6.64 ~ bnd_c1_2 X98 bnd_a580) &
% 7.10/6.64 ~ bnd_c9_2 X98 bnd_a580) |
% 7.10/6.64 (ALL X99.
% 7.10/6.64 bnd_ndr1_0 -->
% 7.10/6.64 (bnd_c6_1 X99 |
% 7.10/6.64 (ALL X100.
% 7.10/6.64 bnd_ndr1_1 X99 -->
% 7.10/6.64 ~ bnd_c6_2 X99 X100 | ~ bnd_c5_2 X99 X100)) |
% 7.10/6.64 ~ bnd_c4_1 X99)) |
% 7.10/6.64 ~ bnd_c8_0)) &
% 7.10/6.64 ((~ bnd_c8_0 | bnd_c4_0) |
% 7.10/6.64 ((bnd_ndr1_0 & ~ bnd_c7_1 bnd_a581) &
% 7.10/6.64 (ALL X101.
% 7.10/6.64 bnd_ndr1_1 bnd_a581 -->
% 7.10/6.64 (bnd_c3_2 bnd_a581 X101 | bnd_c6_2 bnd_a581 X101) |
% 7.10/6.64 ~ bnd_c5_2 bnd_a581 X101)) &
% 7.10/6.64 bnd_c8_1 bnd_a581)) &
% 7.10/6.64 ((bnd_c1_0 |
% 7.10/6.64 ((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a582) &
% 7.10/6.64 bnd_c6_2 bnd_a582 bnd_a583) &
% 7.10/6.64 ~ bnd_c5_2 bnd_a582 bnd_a583) &
% 7.10/6.64 ~ bnd_c10_2 bnd_a582 bnd_a583) &
% 7.10/6.64 ~ bnd_c1_1 bnd_a582) |
% 7.10/6.64 (ALL X102.
% 7.10/6.64 bnd_ndr1_0 -->
% 7.10/6.64 (bnd_c5_1 X102 | ~ bnd_c10_1 X102) | bnd_c9_1 X102))) &
% 7.10/6.64 (((bnd_ndr1_0 & ~ bnd_c6_1 bnd_a584) & bnd_c8_1 bnd_a584) &
% 7.10/6.64 (ALL X103.
% 7.10/6.64 bnd_ndr1_1 bnd_a584 -->
% 7.10/6.64 (bnd_c10_2 bnd_a584 X103 | ~ bnd_c8_2 bnd_a584 X103) |
% 7.10/6.64 bnd_c3_2 bnd_a584 X103) |
% 7.10/6.64 ~ bnd_c3_0)) &
% 7.10/6.64 (((bnd_ndr1_0 & ~ bnd_c5_1 bnd_a585) & bnd_c9_1 bnd_a585 |
% 7.10/6.64 bnd_c8_0) |
% 7.10/6.64 ((((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a586) &
% 7.10/6.64 ~ bnd_c4_2 bnd_a586 bnd_a587) &
% 7.10/6.64 ~ bnd_c5_2 bnd_a586 bnd_a587) &
% 7.10/6.64 ~ bnd_c1_2 bnd_a586 bnd_a587) &
% 7.10/6.64 bnd_ndr1_1 bnd_a586) &
% 7.10/6.64 ~ bnd_c1_2 bnd_a586 bnd_a588) &
% 7.10/6.64 ~ bnd_c8_2 bnd_a586 bnd_a588) &
% 7.10/6.64 bnd_c3_2 bnd_a586 bnd_a588) &
% 7.10/6.64 bnd_c8_1 bnd_a586)) &
% 7.10/6.64 ((bnd_c4_0 | bnd_c3_0) | bnd_c5_0)) &
% 7.10/6.64 ((bnd_c3_0 |
% 7.10/6.64 (ALL X104.
% 7.10/6.64 bnd_ndr1_0 -->
% 7.10/6.64 (((bnd_ndr1_1 X104 & ~ bnd_c2_2 X104 bnd_a589) &
% 7.10/6.64 ~ bnd_c10_2 X104 bnd_a589) &
% 7.10/6.64 ~ bnd_c7_2 X104 bnd_a589 |
% 7.10/6.64 bnd_c10_1 X104) |
% 7.10/6.64 (ALL X105.
% 7.10/6.64 bnd_ndr1_1 X104 -->
% 7.10/6.64 ~ bnd_c1_2 X104 X105 | ~ bnd_c3_2 X104 X105))) |
% 7.10/6.64 (ALL X106.
% 7.10/6.64 bnd_ndr1_0 -->
% 7.10/6.64 ((bnd_ndr1_1 X106 & ~ bnd_c1_2 X106 bnd_a590) &
% 7.10/6.64 ~ bnd_c2_2 X106 bnd_a590) &
% 7.10/6.64 ~ bnd_c7_2 X106 bnd_a590 |
% 7.10/6.64 bnd_c8_1 X106))) &
% 7.10/6.64 (((ALL X107.
% 7.10/6.64 bnd_ndr1_0 -->
% 7.10/6.64 (~ bnd_c9_1 X107 | ~ bnd_c1_1 X107) |
% 7.10/6.64 (bnd_ndr1_1 X107 & ~ bnd_c1_2 X107 bnd_a591) &
% 7.10/6.64 bnd_c7_2 X107 bnd_a591) |
% 7.10/6.64 (bnd_ndr1_0 & bnd_c9_1 bnd_a592) & ~ bnd_c8_1 bnd_a592) |
% 7.10/6.64 (ALL X108.
% 7.10/6.64 bnd_ndr1_0 -->
% 7.10/6.64 ((ALL X109.
% 7.10/6.64 bnd_ndr1_1 X108 -->
% 7.10/6.64 (bnd_c3_2 X108 X109 | ~ bnd_c2_2 X108 X109) |
% 7.10/6.64 bnd_c1_2 X108 X109) |
% 7.10/6.64 ~ bnd_c3_1 X108) |
% 7.10/6.64 ((bnd_ndr1_1 X108 & ~ bnd_c5_2 X108 bnd_a593) &
% 7.10/6.64 ~ bnd_c6_2 X108 bnd_a593) &
% 7.10/6.64 ~ bnd_c8_2 X108 bnd_a593))) &
% 7.10/6.64 ((bnd_c1_0 |
% 7.10/6.64 (((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a594) &
% 7.10/6.65 ~ bnd_c3_2 bnd_a594 bnd_a595) &
% 7.10/6.65 ~ bnd_c4_2 bnd_a594 bnd_a595) &
% 7.10/6.65 bnd_c6_2 bnd_a594 bnd_a595) &
% 7.10/6.65 ~ bnd_c6_1 bnd_a594) &
% 7.10/6.65 bnd_ndr1_1 bnd_a594) &
% 7.10/6.65 bnd_c6_2 bnd_a594 bnd_a596) &
% 7.10/6.65 bnd_c3_2 bnd_a594 bnd_a596) |
% 7.10/6.65 bnd_c9_0)) &
% 7.10/6.65 ((bnd_c4_0 |
% 7.10/6.65 (((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a597) &
% 7.10/6.65 ~ bnd_c1_2 bnd_a597 bnd_a598) &
% 7.10/6.65 ~ bnd_c9_2 bnd_a597 bnd_a598) &
% 7.10/6.65 ~ bnd_c4_2 bnd_a597 bnd_a598) &
% 7.10/6.65 ~ bnd_c7_1 bnd_a597) &
% 7.10/6.65 (ALL X110.
% 7.10/6.65 bnd_ndr1_1 bnd_a597 -->
% 7.10/6.65 (~ bnd_c1_2 bnd_a597 X110 | ~ bnd_c3_2 bnd_a597 X110) |
% 7.10/6.65 bnd_c7_2 bnd_a597 X110)) |
% 7.10/6.65 ((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a599) &
% 7.10/6.65 bnd_c3_2 bnd_a599 bnd_a600) &
% 7.10/6.65 ~ bnd_c2_2 bnd_a599 bnd_a600) &
% 7.10/6.65 ~ bnd_c5_2 bnd_a599 bnd_a600) &
% 7.10/6.65 ~ bnd_c4_1 bnd_a599)) &
% 7.10/6.65 ((((bnd_ndr1_0 & bnd_c5_1 bnd_a601) & ~ bnd_c10_1 bnd_a601) &
% 7.10/6.65 (ALL X111.
% 7.10/6.65 bnd_ndr1_1 bnd_a601 -->
% 7.10/6.65 (bnd_c4_2 bnd_a601 X111 | bnd_c6_2 bnd_a601 X111) |
% 7.10/6.65 bnd_c7_2 bnd_a601 X111) |
% 7.10/6.65 (((((bnd_ndr1_0 &
% 7.10/6.65 (ALL X112.
% 7.10/6.65 bnd_ndr1_1 bnd_a602 -->
% 7.10/6.65 (bnd_c7_2 bnd_a602 X112 | ~ bnd_c2_2 bnd_a602 X112) |
% 7.10/6.65 ~ bnd_c4_2 bnd_a602 X112)) &
% 7.10/6.65 bnd_c7_1 bnd_a602) &
% 7.10/6.65 bnd_ndr1_1 bnd_a602) &
% 7.10/6.65 ~ bnd_c6_2 bnd_a602 bnd_a603) &
% 7.10/6.65 ~ bnd_c7_2 bnd_a602 bnd_a603) &
% 7.10/6.65 ~ bnd_c8_2 bnd_a602 bnd_a603) |
% 7.10/6.65 (ALL X113.
% 7.10/6.65 bnd_ndr1_0 -->
% 7.10/6.65 (((bnd_ndr1_1 X113 & bnd_c3_2 X113 bnd_a604) &
% 7.10/6.65 bnd_c10_2 X113 bnd_a604) &
% 7.10/6.65 ~ bnd_c6_2 X113 bnd_a604 |
% 7.10/6.65 ~ bnd_c6_1 X113) |
% 7.10/6.65 (ALL X114.
% 7.10/6.65 bnd_ndr1_1 X113 -->
% 7.10/6.65 (~ bnd_c2_2 X113 X114 | bnd_c4_2 X113 X114) |
% 7.10/6.65 bnd_c6_2 X113 X114)))) &
% 7.10/6.65 (((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a605) &
% 7.10/6.65 ~ bnd_c3_2 bnd_a605 bnd_a606) &
% 7.10/6.65 ~ bnd_c1_2 bnd_a605 bnd_a606) &
% 7.10/6.65 bnd_c2_2 bnd_a605 bnd_a606) &
% 7.10/6.65 ~ bnd_c5_1 bnd_a605) &
% 7.10/6.65 ~ bnd_c4_1 bnd_a605 |
% 7.10/6.65 ~ bnd_c9_0) |
% 7.10/6.65 (ALL X115.
% 7.10/6.65 bnd_ndr1_0 -->
% 7.10/6.65 ((ALL X116.
% 7.10/6.65 bnd_ndr1_1 X115 -->
% 7.10/6.65 (~ bnd_c3_2 X115 X116 | ~ bnd_c6_2 X115 X116) |
% 7.10/6.65 bnd_c2_2 X115 X116) |
% 7.10/6.65 bnd_c1_1 X115) |
% 7.10/6.65 ~ bnd_c10_1 X115))) &
% 7.10/6.65 (bnd_c9_0 | bnd_c4_0)) &
% 7.10/6.65 (((ALL X117.
% 7.10/6.65 bnd_ndr1_0 -->
% 7.10/6.65 (bnd_c2_1 X117 | ~ bnd_c6_1 X117) | ~ bnd_c7_1 X117) |
% 7.10/6.65 ~ bnd_c7_0) |
% 7.10/6.65 (ALL X118.
% 7.10/6.65 bnd_ndr1_0 -->
% 7.10/6.65 ((ALL X119.
% 7.10/6.65 bnd_ndr1_1 X118 --> bnd_c1_2 X118 X119 | bnd_c4_2 X118 X119) |
% 7.10/6.65 ~ bnd_c5_1 X118) |
% 7.10/6.65 ((bnd_ndr1_1 X118 & ~ bnd_c5_2 X118 bnd_a607) &
% 7.10/6.65 bnd_c4_2 X118 bnd_a607) &
% 7.10/6.65 ~ bnd_c2_2 X118 bnd_a607))) &
% 7.10/6.65 (((ALL X120.
% 7.10/6.65 bnd_ndr1_0 -->
% 7.10/6.65 (bnd_c5_1 X120 | bnd_c10_1 X120) |
% 7.10/6.65 (ALL X121.
% 7.10/6.65 bnd_ndr1_1 X120 -->
% 7.10/6.65 bnd_c3_2 X120 X121 | ~ bnd_c6_2 X120 X121)) |
% 7.10/6.65 bnd_c10_0) |
% 7.10/6.65 ~ bnd_c2_0))
% 15.39/14.98 Unfolded term: ~ ((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((bnd_ndr1_0 &
% 15.39/14.98 bnd_c3_1 bnd_a449) &
% 15.39/14.98 bnd_c8_1 bnd_a449) &
% 15.39/14.98 (ALL U.
% 15.39/14.98 bnd_ndr1_1 bnd_a449 -->
% 15.39/14.98 bnd_c9_2 bnd_a449 U | bnd_c4_2 bnd_a449 U) |
% 15.39/14.98 (ALL V.
% 15.39/14.98 bnd_ndr1_0 -->
% 15.39/14.98 (((bnd_ndr1_1 V & bnd_c9_2 V bnd_a450) &
% 15.39/14.98 ~ bnd_c8_2 V bnd_a450) &
% 15.39/14.98 ~ bnd_c6_2 V bnd_a450 |
% 15.39/14.98 ~ bnd_c5_1 V) |
% 15.39/14.98 ~ bnd_c1_1 V)) |
% 15.39/14.98 bnd_c6_0) &
% 15.39/14.98 ((~ bnd_c9_0 | ~ bnd_c2_0) |
% 15.39/14.98 (ALL W.
% 15.39/14.98 bnd_ndr1_0 -->
% 15.39/14.98 ((bnd_ndr1_1 W & bnd_c4_2 W bnd_a451) &
% 15.39/14.98 bnd_c7_2 W bnd_a451 |
% 15.39/14.98 ((bnd_ndr1_1 W & ~ bnd_c2_2 W bnd_a452) &
% 15.39/14.98 bnd_c1_2 W bnd_a452) &
% 15.39/14.98 bnd_c9_2 W bnd_a452) |
% 15.39/14.98 (bnd_ndr1_1 W & ~ bnd_c1_2 W bnd_a453) &
% 15.39/14.98 bnd_c4_2 W bnd_a453))) &
% 15.39/14.98 ((bnd_c7_0 | bnd_c4_0) |
% 15.39/14.98 ((bnd_ndr1_0 & ~ bnd_c4_1 bnd_a454) &
% 15.39/14.98 bnd_c5_1 bnd_a454) &
% 15.39/14.98 ~ bnd_c9_1 bnd_a454)) &
% 15.39/14.98 ((((bnd_ndr1_0 & bnd_c1_1 bnd_a455) &
% 15.39/14.98 ~ bnd_c8_1 bnd_a455) &
% 15.39/14.98 bnd_c9_1 bnd_a455 |
% 15.39/14.98 (ALL X.
% 15.39/14.98 bnd_ndr1_0 -->
% 15.39/14.98 (~ bnd_c4_1 X |
% 15.39/14.98 ((bnd_ndr1_1 X & ~ bnd_c1_2 X bnd_a456) &
% 15.39/14.98 ~ bnd_c6_2 X bnd_a456) &
% 15.39/14.98 ~ bnd_c7_2 X bnd_a456) |
% 15.39/14.98 ~ bnd_c3_1 X)) |
% 15.39/14.98 bnd_c4_0)) &
% 15.39/14.98 ((((((bnd_ndr1_0 & ~ bnd_c2_1 bnd_a457) &
% 15.39/14.98 bnd_c5_1 bnd_a457) &
% 15.39/14.98 bnd_ndr1_1 bnd_a457) &
% 15.39/14.98 ~ bnd_c10_2 bnd_a457 bnd_a458) &
% 15.39/14.98 ~ bnd_c9_2 bnd_a457 bnd_a458 |
% 15.39/14.98 ~ bnd_c2_0) |
% 15.39/14.98 ~ bnd_c9_0)) &
% 15.39/14.98 (~ bnd_c4_0 |
% 15.39/14.98 (ALL Y.
% 15.39/14.98 bnd_ndr1_0 -->
% 15.39/14.98 (bnd_c10_1 Y |
% 15.39/14.98 (ALL Z.
% 15.39/14.98 bnd_ndr1_1 Y -->
% 15.39/14.98 (bnd_c10_2 Y Z | bnd_c2_2 Y Z) |
% 15.39/14.98 bnd_c7_2 Y Z)) |
% 15.39/14.98 ((bnd_ndr1_1 Y & ~ bnd_c9_2 Y bnd_a459) &
% 15.39/14.98 bnd_c2_2 Y bnd_a459) &
% 15.39/14.98 bnd_c8_2 Y bnd_a459))) &
% 15.39/14.98 (((ALL X1.
% 15.39/14.98 bnd_ndr1_0 -->
% 15.39/14.98 ((ALL X2.
% 15.39/14.98 bnd_ndr1_1 X1 -->
% 15.39/14.98 (~ bnd_c7_2 X1 X2 | ~ bnd_c8_2 X1 X2) |
% 15.39/14.98 bnd_c3_2 X1 X2) |
% 15.39/14.98 bnd_c7_1 X1) |
% 15.39/14.98 ~ bnd_c6_1 X1) |
% 15.39/14.98 bnd_c1_0) |
% 15.39/14.98 bnd_c3_0)) &
% 15.39/14.98 (((((((bnd_ndr1_0 & ~ bnd_c7_1 bnd_a460) &
% 15.39/14.98 bnd_c6_1 bnd_a460) &
% 15.39/14.98 bnd_ndr1_1 bnd_a460) &
% 15.39/14.98 bnd_c4_2 bnd_a460 bnd_a461) &
% 15.39/14.98 bnd_c3_2 bnd_a460 bnd_a461) &
% 15.39/14.98 ~ bnd_c10_2 bnd_a460 bnd_a461 |
% 15.39/14.98 ~ bnd_c9_0) |
% 15.39/14.98 ~ bnd_c7_0)) &
% 15.39/14.98 ((bnd_c5_0 |
% 15.39/14.98 (ALL X3.
% 15.39/14.98 bnd_ndr1_0 -->
% 15.39/14.98 ((ALL X4.
% 15.39/14.98 bnd_ndr1_1 X3 -->
% 15.39/14.98 (bnd_c6_2 X3 X4 | ~ bnd_c9_2 X3 X4) |
% 15.39/14.98 bnd_c8_2 X3 X4) |
% 15.39/14.98 ((bnd_ndr1_1 X3 & ~ bnd_c1_2 X3 bnd_a462) &
% 15.39/14.98 bnd_c10_2 X3 bnd_a462) &
% 15.39/14.98 bnd_c2_2 X3 bnd_a462) |
% 15.39/14.98 (ALL X5.
% 15.39/14.98 bnd_ndr1_1 X3 -->
% 15.39/14.98 (bnd_c7_2 X3 X5 | ~ bnd_c1_2 X3 X5) |
% 15.39/14.98 bnd_c6_2 X3 X5))) |
% 15.39/14.98 ((bnd_ndr1_0 &
% 15.39/14.98 (ALL X6.
% 15.39/14.98 bnd_ndr1_1 bnd_a463 -->
% 15.39/14.98 (bnd_c6_2 bnd_a463 X6 | ~ bnd_c3_2 bnd_a463 X6) |
% 15.39/14.98 bnd_c5_2 bnd_a463 X6)) &
% 15.39/14.98 ~ bnd_c9_1 bnd_a463) &
% 15.39/14.98 ~ bnd_c7_1 bnd_a463)) &
% 15.39/14.98 ((~ bnd_c1_0 |
% 15.39/14.98 (((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a464) &
% 15.39/14.98 bnd_c10_2 bnd_a464 bnd_a465) &
% 15.39/14.98 ~ bnd_c6_2 bnd_a464 bnd_a465) &
% 15.39/14.98 ~ bnd_c2_2 bnd_a464 bnd_a465) &
% 15.39/14.98 bnd_c3_1 bnd_a464) &
% 15.39/14.98 bnd_ndr1_1 bnd_a464) &
% 15.39/14.98 bnd_c5_2 bnd_a464 bnd_a466) &
% 15.39/14.98 ~ bnd_c7_2 bnd_a464 bnd_a466) |
% 15.39/14.98 ~ bnd_c9_0)) &
% 15.39/14.98 ((bnd_c4_0 |
% 15.39/14.98 (((((bnd_ndr1_0 & bnd_c4_1 bnd_a467) & bnd_ndr1_1 bnd_a467) &
% 15.39/14.98 bnd_c3_2 bnd_a467 bnd_a468) &
% 15.39/14.98 bnd_c6_2 bnd_a467 bnd_a468) &
% 15.39/14.98 ~ bnd_c10_2 bnd_a467 bnd_a468) &
% 15.39/14.98 bnd_c2_1 bnd_a467) |
% 15.39/14.98 (ALL X7.
% 15.39/14.98 bnd_ndr1_0 -->
% 15.39/14.98 (~ bnd_c8_1 X7 | ~ bnd_c2_1 X7) | ~ bnd_c7_1 X7))) &
% 15.39/14.98 ((bnd_c10_0 |
% 15.39/14.98 ((bnd_ndr1_0 &
% 15.39/14.98 (ALL X8.
% 15.39/14.98 bnd_ndr1_1 bnd_a469 -->
% 15.39/14.98 (~ bnd_c8_2 bnd_a469 X8 | ~ bnd_c6_2 bnd_a469 X8) |
% 15.39/14.98 bnd_c1_2 bnd_a469 X8)) &
% 15.39/14.98 bnd_c6_1 bnd_a469) &
% 15.39/14.98 bnd_c10_1 bnd_a469) |
% 15.39/14.98 ((bnd_ndr1_0 & ~ bnd_c2_1 bnd_a470) &
% 15.39/14.98 (ALL X9.
% 15.39/14.98 bnd_ndr1_1 bnd_a470 -->
% 15.39/14.98 (bnd_c8_2 bnd_a470 X9 | ~ bnd_c4_2 bnd_a470 X9) |
% 15.39/14.98 ~ bnd_c5_2 bnd_a470 X9)) &
% 15.39/14.98 bnd_c8_1 bnd_a470)) &
% 15.39/14.98 ((~ bnd_c2_0 |
% 15.39/14.98 (((((bnd_ndr1_0 & bnd_c9_1 bnd_a471) & bnd_ndr1_1 bnd_a471) &
% 15.39/14.98 bnd_c6_2 bnd_a471 bnd_a472) &
% 15.39/14.98 ~ bnd_c4_2 bnd_a471 bnd_a472) &
% 15.39/14.98 bnd_c3_2 bnd_a471 bnd_a472) &
% 15.39/14.98 ~ bnd_c3_1 bnd_a471) |
% 15.39/14.98 ((bnd_ndr1_0 & bnd_c7_1 bnd_a473) & bnd_c9_1 bnd_a473) &
% 15.39/14.98 (ALL X10.
% 15.39/14.98 bnd_ndr1_1 bnd_a473 -->
% 15.39/14.98 (bnd_c3_2 bnd_a473 X10 | bnd_c8_2 bnd_a473 X10) |
% 15.39/14.98 ~ bnd_c6_2 bnd_a473 X10))) &
% 15.39/14.98 (((ALL X11.
% 15.39/14.98 bnd_ndr1_0 -->
% 15.39/14.98 (bnd_c7_1 X11 |
% 15.39/14.98 (ALL X12.
% 15.39/14.98 bnd_ndr1_1 X11 -->
% 15.39/14.98 (bnd_c5_2 X11 X12 | ~ bnd_c9_2 X11 X12) |
% 15.39/14.98 bnd_c6_2 X11 X12)) |
% 15.39/14.98 bnd_c1_1 X11) |
% 15.39/14.98 bnd_c9_0) |
% 15.39/14.98 ~ bnd_c2_0)) &
% 15.39/14.98 ((bnd_c6_0 |
% 15.39/14.98 (ALL X13.
% 15.39/14.98 bnd_ndr1_0 -->
% 15.39/14.98 (bnd_c10_1 X13 | bnd_c9_1 X13) |
% 15.39/14.98 ((bnd_ndr1_1 X13 & bnd_c8_2 X13 bnd_a474) &
% 15.39/14.98 bnd_c7_2 X13 bnd_a474) &
% 15.39/14.98 ~ bnd_c6_2 X13 bnd_a474)) |
% 15.39/14.98 (((bnd_ndr1_0 & bnd_ndr1_1 bnd_a475) &
% 15.39/14.98 bnd_c9_2 bnd_a475 bnd_a476) &
% 15.39/14.98 ~ bnd_c10_2 bnd_a475 bnd_a476) &
% 15.39/14.98 ~ bnd_c7_2 bnd_a475 bnd_a476)) &
% 15.39/14.98 ((((bnd_ndr1_0 & ~ bnd_c5_1 bnd_a477) & bnd_c1_1 bnd_a477) &
% 15.39/14.98 bnd_c6_1 bnd_a477 |
% 15.39/14.98 ~ bnd_c5_0) |
% 15.39/14.98 ~ bnd_c8_0)) &
% 15.39/14.98 ((((((((((bnd_ndr1_0 & bnd_c7_1 bnd_a478) & bnd_ndr1_1 bnd_a478) &
% 15.39/14.98 bnd_c3_2 bnd_a478 bnd_a479) &
% 15.39/14.98 ~ bnd_c1_2 bnd_a478 bnd_a479) &
% 15.39/14.98 ~ bnd_c8_2 bnd_a478 bnd_a479) &
% 15.39/14.98 bnd_ndr1_1 bnd_a478) &
% 15.39/14.98 bnd_c7_2 bnd_a478 bnd_a480) &
% 15.39/14.98 ~ bnd_c4_2 bnd_a478 bnd_a480) &
% 15.39/14.98 bnd_c2_2 bnd_a478 bnd_a480 |
% 15.39/14.98 bnd_c3_0) |
% 15.39/14.98 ((((((((bnd_ndr1_0 &
% 15.39/14.98 (ALL X14.
% 15.39/14.98 bnd_ndr1_1 bnd_a481 -->
% 15.39/14.98 (~ bnd_c7_2 bnd_a481 X14 | ~ bnd_c3_2 bnd_a481 X14) |
% 15.39/14.98 ~ bnd_c5_2 bnd_a481 X14)) &
% 15.39/14.98 bnd_ndr1_1 bnd_a481) &
% 15.39/14.98 bnd_c4_2 bnd_a481 bnd_a482) &
% 15.39/14.98 bnd_c10_2 bnd_a481 bnd_a482) &
% 15.39/14.98 bnd_c6_2 bnd_a481 bnd_a482) &
% 15.39/14.98 bnd_ndr1_1 bnd_a481) &
% 15.39/14.98 bnd_c5_2 bnd_a481 bnd_a483) &
% 15.39/14.98 bnd_c10_2 bnd_a481 bnd_a483) &
% 15.39/14.98 ~ bnd_c7_2 bnd_a481 bnd_a483)) &
% 15.39/14.98 (~ bnd_c4_0 | ~ bnd_c8_0)) &
% 15.39/14.98 (((((((bnd_ndr1_0 &
% 15.39/14.98 (ALL X15.
% 15.39/14.98 bnd_ndr1_1 bnd_a484 -->
% 15.39/14.98 ~ bnd_c5_2 bnd_a484 X15 | bnd_c7_2 bnd_a484 X15)) &
% 15.39/14.98 (ALL X16.
% 15.39/14.98 bnd_ndr1_1 bnd_a484 -->
% 15.39/14.98 bnd_c10_2 bnd_a484 X16 | bnd_c8_2 bnd_a484 X16)) &
% 15.39/14.98 bnd_ndr1_1 bnd_a484) &
% 15.39/14.98 ~ bnd_c4_2 bnd_a484 bnd_a485) &
% 15.39/14.98 ~ bnd_c8_2 bnd_a484 bnd_a485) &
% 15.39/14.98 ~ bnd_c3_2 bnd_a484 bnd_a485 |
% 15.39/14.98 bnd_c1_0) |
% 15.39/14.98 bnd_c5_0)) &
% 15.39/14.98 (~ bnd_c3_0 |
% 15.39/14.98 (ALL X17.
% 15.39/14.98 bnd_ndr1_0 -->
% 15.39/14.98 (((bnd_ndr1_1 X17 & ~ bnd_c1_2 X17 bnd_a486) &
% 15.39/14.98 ~ bnd_c2_2 X17 bnd_a486) &
% 15.39/14.98 ~ bnd_c9_2 X17 bnd_a486 |
% 15.39/14.98 (ALL X18.
% 15.39/14.98 bnd_ndr1_1 X17 -->
% 15.39/14.98 (~ bnd_c8_2 X17 X18 | bnd_c6_2 X17 X18) |
% 15.39/14.98 ~ bnd_c4_2 X17 X18)) |
% 15.39/14.98 (bnd_ndr1_1 X17 & ~ bnd_c10_2 X17 bnd_a487) &
% 15.39/14.98 bnd_c9_2 X17 bnd_a487))) &
% 15.39/14.99 (((bnd_ndr1_0 & ~ bnd_c9_1 bnd_a488) & bnd_c2_1 bnd_a488 | bnd_c6_0) |
% 15.39/14.99 (((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a489) & ~ bnd_c2_2 bnd_a489 bnd_a490) &
% 15.39/14.99 ~ bnd_c1_2 bnd_a489 bnd_a490) &
% 15.39/14.99 ~ bnd_c5_2 bnd_a489 bnd_a490) &
% 15.39/14.99 ~ bnd_c6_1 bnd_a489) &
% 15.39/14.99 ~ bnd_c10_1 bnd_a489)) &
% 15.39/14.99 ((bnd_c4_0 | (ALL X19. bnd_ndr1_0 --> ~ bnd_c1_1 X19 | bnd_c7_1 X19)) |
% 15.39/14.99 bnd_c3_0)) &
% 15.39/14.99 ((~ bnd_c2_0 | ~ bnd_c9_0) | bnd_c8_0)) &
% 15.39/14.99 (((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a491) & ~ bnd_c6_2 bnd_a491 bnd_a492) &
% 15.39/14.99 bnd_c7_2 bnd_a491 bnd_a492) &
% 15.39/14.99 ~ bnd_c2_2 bnd_a491 bnd_a492) &
% 15.39/14.99 (ALL X20.
% 15.39/14.99 bnd_ndr1_1 bnd_a491 -->
% 15.39/14.99 (~ bnd_c4_2 bnd_a491 X20 | bnd_c10_2 bnd_a491 X20) |
% 15.39/14.99 ~ bnd_c9_2 bnd_a491 X20)) &
% 15.39/14.99 bnd_c1_1 bnd_a491 |
% 15.39/14.99 ~ bnd_c4_0) |
% 15.39/14.99 (ALL X21.
% 15.39/14.99 bnd_ndr1_0 -->
% 15.39/14.99 (bnd_c3_1 X21 |
% 15.39/14.99 (ALL X22.
% 15.39/14.99 bnd_ndr1_1 X21 -->
% 15.39/14.99 (bnd_c6_2 X21 X22 | bnd_c10_2 X21 X22) | bnd_c1_2 X21 X22)) |
% 15.39/14.99 bnd_c1_1 X21))) &
% 15.39/14.99 ((~ bnd_c1_0 |
% 15.39/14.99 (bnd_ndr1_0 & bnd_c9_1 bnd_a493) &
% 15.39/14.99 (ALL X23.
% 15.39/14.99 bnd_ndr1_1 bnd_a493 -->
% 15.39/14.99 ~ bnd_c6_2 bnd_a493 X23 | bnd_c5_2 bnd_a493 X23)) |
% 15.39/14.99 (((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a494) & ~ bnd_c9_2 bnd_a494 bnd_a495) &
% 15.39/14.99 bnd_c10_2 bnd_a494 bnd_a495) &
% 15.39/14.99 ~ bnd_c6_2 bnd_a494 bnd_a495) &
% 15.39/14.99 ~ bnd_c4_1 bnd_a494) &
% 15.39/14.99 ~ bnd_c1_1 bnd_a494)) &
% 15.39/14.99 ((bnd_c1_0 |
% 15.39/14.99 (ALL X24.
% 15.39/14.99 bnd_ndr1_0 -->
% 15.39/14.99 (((bnd_ndr1_1 X24 & bnd_c2_2 X24 bnd_a496) & ~ bnd_c10_2 X24 bnd_a496) &
% 15.39/14.99 bnd_c6_2 X24 bnd_a496 |
% 15.39/14.99 ~ bnd_c1_1 X24) |
% 15.39/14.99 (ALL X25.
% 15.39/14.99 bnd_ndr1_1 X24 -->
% 15.39/14.99 (bnd_c5_2 X24 X25 | bnd_c2_2 X24 X25) | bnd_c8_2 X24 X25))) |
% 15.39/14.99 (ALL X26.
% 15.39/14.99 bnd_ndr1_0 -->
% 15.39/14.99 (((bnd_ndr1_1 X26 & ~ bnd_c4_2 X26 bnd_a497) & bnd_c2_2 X26 bnd_a497) &
% 15.39/14.99 bnd_c9_2 X26 bnd_a497 |
% 15.39/14.99 (bnd_ndr1_1 X26 & bnd_c10_2 X26 bnd_a498) & bnd_c1_2 X26 bnd_a498) |
% 15.39/14.99 (ALL X27.
% 15.39/14.99 bnd_ndr1_1 X26 -->
% 15.39/14.99 (~ bnd_c6_2 X26 X27 | ~ bnd_c1_2 X26 X27) | bnd_c8_2 X26 X27)))) &
% 15.39/14.99 ((bnd_c5_0 | bnd_c6_0) |
% 15.39/14.99 (ALL X28.
% 15.39/14.99 bnd_ndr1_0 -->
% 15.39/14.99 (bnd_c7_1 X28 |
% 15.39/14.99 (ALL X29.
% 15.39/14.99 bnd_ndr1_1 X28 -->
% 15.39/14.99 (~ bnd_c4_2 X28 X29 | bnd_c7_2 X28 X29) | ~ bnd_c9_2 X28 X29)) |
% 15.39/14.99 bnd_c5_1 X28))) &
% 15.39/14.99 ((~ bnd_c5_0 | ~ bnd_c8_0) |
% 15.39/14.99 ((((((((bnd_ndr1_0 &
% 15.39/14.99 ~ bnd_c4_1 bnd_a499) &
% 15.39/14.99 bnd_ndr1_1 bnd_a499) &
% 15.39/14.99 bnd_c10_2 bnd_a499 bnd_a500) &
% 15.39/14.99 ~ bnd_c7_2 bnd_a499 bnd_a500) &
% 15.39/14.99 bnd_c2_2 bnd_a499 bnd_a500) &
% 15.39/14.99 bnd_ndr1_1 bnd_a499) &
% 15.39/14.99 bnd_c10_2 bnd_a499 bnd_a501) &
% 15.39/14.99 bnd_c6_2 bnd_a499 bnd_a501) &
% 15.39/14.99 ~ bnd_c9_2 bnd_a499 bnd_a501)) &
% 15.39/14.99 ((bnd_c8_0 |
% 15.39/14.99 ((((bnd_ndr1_0 & ~ bnd_c5_1 bnd_a502) &
% 15.39/14.99 ~ bnd_c9_1 bnd_a502) &
% 15.39/14.99 bnd_ndr1_1 bnd_a502) &
% 15.39/14.99 ~ bnd_c1_2 bnd_a502 bnd_a503) &
% 15.39/14.99 bnd_c8_2 bnd_a502 bnd_a503) |
% 15.39/14.99 (ALL X30.
% 15.39/14.99 bnd_ndr1_0 -->
% 15.39/14.99 ((ALL X31.
% 15.39/14.99 bnd_ndr1_1 X30 -->
% 15.39/14.99 (bnd_c10_2 X30 X31 | ~ bnd_c7_2 X30 X31) | ~ bnd_c9_2 X30 X31) |
% 15.39/14.99 bnd_c9_1 X30) |
% 15.39/14.99 bnd_c1_1 X30))) &
% 15.39/14.99 (((((((bnd_ndr1_0 & bnd_c10_1 bnd_a504) &
% 15.39/14.99 (ALL X32.
% 15.39/14.99 bnd_ndr1_1 bnd_a504 -->
% 15.39/14.99 (bnd_c1_2 bnd_a504 X32 | ~ bnd_c9_2 bnd_a504 X32) |
% 15.39/14.99 bnd_c7_2 bnd_a504 X32)) &
% 15.39/14.99 bnd_ndr1_1 bnd_a504) &
% 15.39/14.99 ~ bnd_c3_2 bnd_a504 bnd_a505) &
% 15.39/14.99 ~ bnd_c9_2 bnd_a504 bnd_a505) &
% 15.39/14.99 ~ bnd_c2_2 bnd_a504 bnd_a505 |
% 15.39/14.99 ~ bnd_c10_0) |
% 15.39/14.99 (ALL X33.
% 15.39/14.99 bnd_ndr1_0 -->
% 15.39/14.99 (bnd_c3_1 X33 | ~ bnd_c6_1 X33) |
% 15.39/14.99 bnd_c10_1 X33))) &
% 15.39/14.99 (((ALL X34.
% 15.39/14.99 bnd_ndr1_0 -->
% 15.39/14.99 (bnd_c5_1 X34 | bnd_c7_1 X34) |
% 15.39/14.99 ~ bnd_c6_1 X34) |
% 15.39/14.99 bnd_c6_0) |
% 15.39/14.99 bnd_c9_0)) &
% 15.39/14.99 (((ALL X35.
% 15.39/14.99 bnd_ndr1_0 -->
% 15.39/14.99 (((bnd_ndr1_1 X35 &
% 15.39/14.99 bnd_c10_2 X35 bnd_a506) &
% 15.39/14.99 ~ bnd_c3_2 X35 bnd_a506) &
% 15.39/14.99 bnd_c9_2 X35 bnd_a506 |
% 15.39/14.99 (ALL X36.
% 15.39/14.99 bnd_ndr1_1 X35 -->
% 15.39/14.99 (bnd_c7_2 X35 X36 | bnd_c2_2 X35 X36) | ~ bnd_c5_2 X35 X36)) |
% 15.39/14.99 bnd_c1_1 X35) |
% 15.39/14.99 (ALL X37.
% 15.39/14.99 bnd_ndr1_0 -->
% 15.39/14.99 (((bnd_ndr1_1 X37 &
% 15.39/14.99 bnd_c6_2 X37 bnd_a507) &
% 15.39/14.99 ~ bnd_c4_2 X37 bnd_a507) &
% 15.39/14.99 bnd_c3_2 X37 bnd_a507 |
% 15.39/14.99 (ALL X38.
% 15.39/14.99 bnd_ndr1_1 X37 -->
% 15.39/14.99 (bnd_c4_2 X37 X38 | ~ bnd_c6_2 X37 X38) | ~ bnd_c3_2 X37 X38)) |
% 15.39/14.99 ((bnd_ndr1_1 X37 &
% 15.39/14.99 bnd_c7_2 X37 bnd_a508) &
% 15.39/14.99 bnd_c2_2 X37 bnd_a508) &
% 15.39/14.99 bnd_c3_2 X37 bnd_a508)) |
% 15.39/14.99 (((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a509) &
% 15.39/14.99 ~ bnd_c2_2 bnd_a509 bnd_a510) &
% 15.39/14.99 ~ bnd_c10_2 bnd_a509 bnd_a510) &
% 15.39/14.99 bnd_c3_2 bnd_a509 bnd_a510) &
% 15.39/14.99 bnd_c6_1 bnd_a509) &
% 15.39/14.99 ~ bnd_c3_1 bnd_a509)) &
% 15.39/14.99 (((ALL X39.
% 15.39/14.99 bnd_ndr1_0 -->
% 15.39/14.99 ((bnd_ndr1_1 X39 &
% 15.39/14.99 bnd_c6_2 X39 bnd_a511) &
% 15.39/14.99 ~ bnd_c5_2 X39 bnd_a511 |
% 15.39/14.99 (ALL X40.
% 15.39/14.99 bnd_ndr1_1 X39 --> ~ bnd_c4_2 X39 X40 | bnd_c10_2 X39 X40)) |
% 15.39/14.99 ((bnd_ndr1_1 X39 &
% 15.39/14.99 bnd_c7_2 X39 bnd_a512) &
% 15.39/14.99 bnd_c1_2 X39 bnd_a512) &
% 15.39/14.99 bnd_c2_2 X39 bnd_a512) |
% 15.39/14.99 ((bnd_ndr1_0 & bnd_c9_1 bnd_a513) &
% 15.39/14.99 ~ bnd_c6_1 bnd_a513) &
% 15.39/14.99 (ALL X41.
% 15.39/14.99 bnd_ndr1_1 bnd_a513 -->
% 15.39/14.99 (bnd_c10_2 bnd_a513 X41 |
% 15.39/14.99 bnd_c1_2 bnd_a513 X41) |
% 15.39/14.99 bnd_c9_2 bnd_a513 X41)) |
% 15.39/14.99 ~ bnd_c5_0)) &
% 15.39/14.99 ((~ bnd_c7_0 |
% 15.39/14.99 ((bnd_ndr1_0 & bnd_c1_1 bnd_a514) &
% 15.39/14.99 ~ bnd_c2_1 bnd_a514) &
% 15.39/14.99 bnd_c10_1 bnd_a514) |
% 15.39/14.99 ~ bnd_c6_0)) &
% 15.39/14.99 ((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a515) &
% 15.39/14.99 ~ bnd_c6_2 bnd_a515 bnd_a516) &
% 15.39/14.99 ~ bnd_c10_2 bnd_a515 bnd_a516) &
% 15.39/14.99 bnd_c8_1 bnd_a515) &
% 15.39/14.99 (ALL X42.
% 15.39/14.99 bnd_ndr1_1 bnd_a515 -->
% 15.39/14.99 (bnd_c5_2 bnd_a515 X42 |
% 15.39/14.99 ~ bnd_c10_2 bnd_a515 X42) |
% 15.39/14.99 ~ bnd_c1_2 bnd_a515 X42) |
% 15.39/14.99 (ALL X43.
% 15.39/14.99 bnd_ndr1_0 -->
% 15.39/14.99 bnd_c5_1 X43 | bnd_c9_1 X43)) |
% 15.39/14.99 ~ bnd_c9_0)) &
% 15.39/14.99 ((ALL X44.
% 15.39/14.99 bnd_ndr1_0 -->
% 15.39/14.99 (bnd_c7_1 X44 |
% 15.39/14.99 (ALL X45.
% 15.39/14.99 bnd_ndr1_1 X44 -->
% 15.39/14.99 (~ bnd_c4_2 X44 X45 |
% 15.39/14.99 bnd_c10_2 X44 X45) |
% 15.39/14.99 bnd_c2_2 X44 X45)) |
% 15.39/14.99 (ALL X46.
% 15.39/14.99 bnd_ndr1_1 X44 -->
% 15.39/14.99 (bnd_c3_2 X44 X46 | bnd_c4_2 X44 X46) |
% 15.39/14.99 ~ bnd_c2_2 X44 X46)) |
% 15.39/14.99 ~ bnd_c1_0)) &
% 15.39/14.99 (((((((bnd_ndr1_0 &
% 15.39/14.99 (ALL X47.
% 15.39/14.99 bnd_ndr1_1 bnd_a517 -->
% 15.39/14.99 ~ bnd_c10_2 bnd_a517 X47 |
% 15.39/14.99 bnd_c4_2 bnd_a517 X47)) &
% 15.39/14.99 bnd_c9_1 bnd_a517) &
% 15.39/14.99 bnd_ndr1_1 bnd_a517) &
% 15.39/14.99 bnd_c8_2 bnd_a517 bnd_a518) &
% 15.39/14.99 bnd_c9_2 bnd_a517 bnd_a518) &
% 15.39/14.99 ~ bnd_c1_2 bnd_a517 bnd_a518 |
% 15.39/14.99 (((((bnd_ndr1_0 & bnd_c9_1 bnd_a519) &
% 15.39/14.99 bnd_ndr1_1 bnd_a519) &
% 15.39/14.99 ~ bnd_c5_2 bnd_a519 bnd_a520) &
% 15.39/14.99 ~ bnd_c7_2 bnd_a519 bnd_a520) &
% 15.39/14.99 bnd_c9_2 bnd_a519 bnd_a520) &
% 15.39/14.99 ~ bnd_c8_1 bnd_a519) |
% 15.39/14.99 bnd_c3_0)) &
% 15.39/14.99 ((bnd_c5_0 | bnd_c9_0) |
% 15.39/14.99 (((((bnd_ndr1_0 & ~ bnd_c10_1 bnd_a521) &
% 15.39/14.99 bnd_ndr1_1 bnd_a521) &
% 15.39/14.99 bnd_c1_2 bnd_a521 bnd_a522) &
% 15.39/14.99 bnd_c6_2 bnd_a521 bnd_a522) &
% 15.39/14.99 ~ bnd_c9_2 bnd_a521 bnd_a522) &
% 15.39/14.99 bnd_c7_1 bnd_a521)) &
% 15.39/14.99 (((ALL X48.
% 15.39/14.99 bnd_ndr1_0 -->
% 15.39/14.99 ((ALL X49.
% 15.39/14.99 bnd_ndr1_1 X48 -->
% 15.39/14.99 (~ bnd_c7_2 X48 X49 | bnd_c2_2 X48 X49) |
% 15.39/14.99 bnd_c8_2 X48 X49) |
% 15.39/14.99 (ALL X50.
% 15.39/14.99 bnd_ndr1_1 X48 -->
% 15.39/14.99 (bnd_c9_2 X48 X50 | ~ bnd_c4_2 X48 X50) |
% 15.39/14.99 bnd_c1_2 X48 X50)) |
% 15.39/14.99 ~ bnd_c7_1 X48) |
% 15.39/14.99 ~ bnd_c8_0) |
% 15.39/14.99 ~ bnd_c10_0)) &
% 15.39/14.99 ((bnd_c1_0 |
% 15.39/14.99 (((((bnd_ndr1_0 & ~ bnd_c3_1 bnd_a523) &
% 15.39/14.99 bnd_c4_1 bnd_a523) &
% 15.39/14.99 bnd_ndr1_1 bnd_a523) &
% 15.39/14.99 ~ bnd_c2_2 bnd_a523 bnd_a524) &
% 15.39/14.99 bnd_c4_2 bnd_a523 bnd_a524) &
% 15.39/14.99 bnd_c8_2 bnd_a523 bnd_a524) |
% 15.39/14.99 ((bnd_ndr1_0 & ~ bnd_c7_1 bnd_a525) &
% 15.39/14.99 bnd_c8_1 bnd_a525) &
% 15.39/14.99 ~ bnd_c6_1 bnd_a525)) &
% 15.39/14.99 (((ALL X51.
% 15.39/14.99 bnd_ndr1_0 -->
% 15.39/14.99 (~ bnd_c4_1 X51 | ~ bnd_c1_1 X51) |
% 15.39/14.99 ((bnd_ndr1_1 X51 & ~ bnd_c9_2 X51 bnd_a526) &
% 15.39/14.99 ~ bnd_c2_2 X51 bnd_a526) &
% 15.39/14.99 bnd_c6_2 X51 bnd_a526) |
% 15.39/14.99 ~ bnd_c10_0) |
% 15.39/14.99 bnd_c9_0)) &
% 15.39/14.99 ((~ bnd_c5_0 |
% 15.39/14.99 (ALL X52.
% 15.39/14.99 bnd_ndr1_0 -->
% 15.39/14.99 (~ bnd_c6_1 X52 | ~ bnd_c9_1 X52) |
% 15.39/14.99 ((bnd_ndr1_1 X52 & bnd_c8_2 X52 bnd_a527) &
% 15.39/14.99 bnd_c9_2 X52 bnd_a527) &
% 15.39/14.99 bnd_c7_2 X52 bnd_a527)) |
% 15.39/14.99 (ALL X53.
% 15.39/14.99 bnd_ndr1_0 -->
% 15.39/14.99 (~ bnd_c5_1 X53 |
% 15.39/14.99 ((bnd_ndr1_1 X53 & ~ bnd_c4_2 X53 bnd_a528) &
% 15.39/14.99 ~ bnd_c2_2 X53 bnd_a528) &
% 15.39/14.99 ~ bnd_c3_2 X53 bnd_a528) |
% 15.39/14.99 ~ bnd_c2_1 X53))) &
% 15.39/14.99 (bnd_c5_0 | bnd_c4_0)) &
% 15.39/14.99 (bnd_c10_0 |
% 15.39/14.99 (ALL X54.
% 15.39/14.99 bnd_ndr1_0 -->
% 15.39/14.99 ((ALL X55.
% 15.39/14.99 bnd_ndr1_1 X54 -->
% 15.39/14.99 bnd_c1_2 X54 X55 | ~ bnd_c10_2 X54 X55) |
% 15.39/14.99 ((bnd_ndr1_1 X54 & bnd_c3_2 X54 bnd_a529) &
% 15.39/14.99 bnd_c2_2 X54 bnd_a529) &
% 15.39/14.99 bnd_c7_2 X54 bnd_a529) |
% 15.39/14.99 ((bnd_ndr1_1 X54 & bnd_c9_2 X54 bnd_a530) &
% 15.39/14.99 ~ bnd_c1_2 X54 bnd_a530) &
% 15.39/14.99 bnd_c6_2 X54 bnd_a530))) &
% 15.39/14.99 ((bnd_c8_0 | ~ bnd_c10_0) | ~ bnd_c3_0)) &
% 15.39/14.99 ((~ bnd_c3_0 |
% 15.39/14.99 (ALL X56.
% 15.39/14.99 bnd_ndr1_0 -->
% 15.39/14.99 (((bnd_ndr1_1 X56 & ~ bnd_c10_2 X56 bnd_a531) &
% 15.39/14.99 bnd_c5_2 X56 bnd_a531) &
% 15.39/14.99 ~ bnd_c6_2 X56 bnd_a531 |
% 15.39/14.99 ~ bnd_c1_1 X56) |
% 15.39/14.99 ((bnd_ndr1_1 X56 & ~ bnd_c4_2 X56 bnd_a532) &
% 15.39/14.99 bnd_c9_2 X56 bnd_a532) &
% 15.39/14.99 ~ bnd_c1_2 X56 bnd_a532)) |
% 15.39/14.99 ((((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a533) &
% 15.39/14.99 bnd_c8_2 bnd_a533 bnd_a534) &
% 15.39/14.99 ~ bnd_c3_2 bnd_a533 bnd_a534) &
% 15.39/14.99 ~ bnd_c7_2 bnd_a533 bnd_a534) &
% 15.39/14.99 ~ bnd_c1_1 bnd_a533) &
% 15.39/14.99 bnd_ndr1_1 bnd_a533) &
% 15.39/14.99 ~ bnd_c1_2 bnd_a533 bnd_a535) &
% 15.39/14.99 ~ bnd_c3_2 bnd_a533 bnd_a535) &
% 15.39/14.99 ~ bnd_c4_2 bnd_a533 bnd_a535)) &
% 15.39/14.99 (((ALL X57.
% 15.39/14.99 bnd_ndr1_0 -->
% 15.39/14.99 (bnd_c2_1 X57 |
% 15.39/14.99 ((bnd_ndr1_1 X57 & ~ bnd_c4_2 X57 bnd_a536) &
% 15.39/14.99 bnd_c9_2 X57 bnd_a536) &
% 15.39/14.99 ~ bnd_c3_2 X57 bnd_a536) |
% 15.39/14.99 bnd_c6_1 X57) |
% 15.39/14.99 ((bnd_ndr1_0 & bnd_c5_1 bnd_a537) & ~ bnd_c9_1 bnd_a537) &
% 15.39/14.99 ~ bnd_c8_1 bnd_a537) |
% 15.39/14.99 ((((((((bnd_ndr1_0 &
% 15.39/14.99 (ALL X58.
% 15.39/14.99 bnd_ndr1_1 bnd_a538 -->
% 15.39/14.99 (~ bnd_c2_2 bnd_a538 X58 |
% 15.39/14.99 bnd_c10_2 bnd_a538 X58) |
% 15.39/14.99 bnd_c9_2 bnd_a538 X58)) &
% 15.39/14.99 bnd_ndr1_1 bnd_a538) &
% 15.39/14.99 bnd_c3_2 bnd_a538 bnd_a539) &
% 15.39/14.99 ~ bnd_c6_2 bnd_a538 bnd_a539) &
% 15.39/14.99 ~ bnd_c5_2 bnd_a538 bnd_a539) &
% 15.39/14.99 bnd_ndr1_1 bnd_a538) &
% 15.39/14.99 bnd_c9_2 bnd_a538 bnd_a540) &
% 15.39/14.99 ~ bnd_c4_2 bnd_a538 bnd_a540) &
% 15.39/14.99 bnd_c6_2 bnd_a538 bnd_a540)) &
% 15.39/14.99 ((bnd_c3_0 |
% 15.39/14.99 ((bnd_ndr1_0 & ~ bnd_c9_1 bnd_a541) & bnd_c10_1 bnd_a541) &
% 15.39/14.99 ~ bnd_c1_1 bnd_a541) |
% 15.39/14.99 bnd_c10_0)) &
% 15.39/14.99 ((~ bnd_c10_0 |
% 15.39/14.99 (ALL X59.
% 15.39/14.99 bnd_ndr1_0 -->
% 15.39/14.99 (((bnd_ndr1_1 X59 & bnd_c1_2 X59 bnd_a542) &
% 15.39/14.99 bnd_c5_2 X59 bnd_a542) &
% 15.39/14.99 ~ bnd_c6_2 X59 bnd_a542 |
% 15.39/14.99 ((bnd_ndr1_1 X59 & ~ bnd_c5_2 X59 bnd_a543) &
% 15.39/14.99 bnd_c1_2 X59 bnd_a543) &
% 15.39/14.99 bnd_c4_2 X59 bnd_a543) |
% 15.39/14.99 (ALL X60.
% 15.39/14.99 bnd_ndr1_1 X59 -->
% 15.39/14.99 (~ bnd_c7_2 X59 X60 | bnd_c6_2 X59 X60) |
% 15.39/14.99 ~ bnd_c2_2 X59 X60))) |
% 15.39/14.99 bnd_c9_0)) &
% 15.39/14.99 (((ALL X61.
% 15.39/14.99 bnd_ndr1_0 -->
% 15.39/14.99 bnd_c5_1 X61 |
% 15.39/14.99 ((bnd_ndr1_1 X61 & bnd_c9_2 X61 bnd_a544) &
% 15.39/14.99 bnd_c4_2 X61 bnd_a544) &
% 15.39/14.99 ~ bnd_c8_2 X61 bnd_a544) |
% 15.39/14.99 bnd_c8_0) |
% 15.39/14.99 (ALL X62.
% 15.39/14.99 bnd_ndr1_0 -->
% 15.39/14.99 (bnd_c7_1 X62 |
% 15.39/14.99 (bnd_ndr1_1 X62 & ~ bnd_c4_2 X62 bnd_a545) &
% 15.39/14.99 ~ bnd_c10_2 X62 bnd_a545) |
% 15.39/14.99 bnd_c2_1 X62))) &
% 15.39/14.99 (~ bnd_c7_0 | ~ bnd_c2_0)) &
% 15.39/14.99 (((ALL X63.
% 15.39/14.99 bnd_ndr1_0 -->
% 15.39/14.99 (~ bnd_c2_1 X63 |
% 15.39/14.99 ((bnd_ndr1_1 X63 & bnd_c7_2 X63 bnd_a546) &
% 15.39/14.99 ~ bnd_c4_2 X63 bnd_a546) &
% 15.39/14.99 ~ bnd_c1_2 X63 bnd_a546) |
% 15.39/14.99 bnd_c1_1 X63) |
% 15.39/14.99 (bnd_ndr1_0 & bnd_c6_1 bnd_a547) & bnd_c5_1 bnd_a547) |
% 15.39/14.99 ~ bnd_c10_0)) &
% 15.39/14.99 (((ALL X64.
% 15.39/14.99 bnd_ndr1_0 -->
% 15.39/14.99 (~ bnd_c5_1 X64 |
% 15.39/14.99 (ALL X65.
% 15.39/14.99 bnd_ndr1_1 X64 -->
% 15.39/14.99 (bnd_c3_2 X64 X65 | bnd_c10_2 X64 X65) |
% 15.39/14.99 bnd_c2_2 X64 X65)) |
% 15.39/14.99 ((bnd_ndr1_1 X64 & ~ bnd_c6_2 X64 bnd_a548) &
% 15.39/14.99 bnd_c9_2 X64 bnd_a548) &
% 15.39/14.99 ~ bnd_c2_2 X64 bnd_a548) |
% 15.39/14.99 bnd_c10_0) |
% 15.39/14.99 ((bnd_ndr1_0 & ~ bnd_c10_1 bnd_a549) & bnd_c2_1 bnd_a549) &
% 15.39/14.99 (ALL X66.
% 15.39/14.99 bnd_ndr1_1 bnd_a549 -->
% 15.39/14.99 (~ bnd_c8_2 bnd_a549 X66 | ~ bnd_c4_2 bnd_a549 X66) |
% 15.39/14.99 ~ bnd_c1_2 bnd_a549 X66))) &
% 15.39/14.99 ((bnd_c10_0 | bnd_c2_0) | ~ bnd_c3_0)) &
% 15.39/14.99 ((bnd_c2_0 | bnd_c9_0) |
% 15.39/14.99 ((bnd_ndr1_0 &
% 15.39/14.99 (ALL X67.
% 15.39/14.99 bnd_ndr1_1 bnd_a550 -->
% 15.39/14.99 (bnd_c5_2 bnd_a550 X67 | ~ bnd_c8_2 bnd_a550 X67) |
% 15.39/14.99 ~ bnd_c3_2 bnd_a550 X67)) &
% 15.39/14.99 (ALL X68.
% 15.39/14.99 bnd_ndr1_1 bnd_a550 -->
% 15.39/14.99 (~ bnd_c6_2 bnd_a550 X68 | bnd_c1_2 bnd_a550 X68) |
% 15.39/14.99 ~ bnd_c8_2 bnd_a550 X68)) &
% 15.39/14.99 bnd_c9_1 bnd_a550)) &
% 15.39/14.99 ((~ bnd_c8_0 | ~ bnd_c10_0) | ~ bnd_c1_0)) &
% 15.39/14.99 ((~ bnd_c3_0 | bnd_c2_0) | bnd_c8_0)) &
% 15.39/14.99 ((bnd_c1_0 | ~ bnd_c7_0) |
% 15.39/14.99 (((((bnd_ndr1_0 & bnd_c8_1 bnd_a551) & ~ bnd_c9_1 bnd_a551) &
% 15.39/14.99 bnd_ndr1_1 bnd_a551) &
% 15.39/14.99 bnd_c2_2 bnd_a551 bnd_a552) &
% 15.39/14.99 bnd_c6_2 bnd_a551 bnd_a552) &
% 15.39/14.99 ~ bnd_c3_2 bnd_a551 bnd_a552)) &
% 15.39/14.99 ((bnd_c5_0 | bnd_c6_0) | ~ bnd_c8_0)) &
% 15.39/14.99 ((ALL X69.
% 15.39/14.99 bnd_ndr1_0 -->
% 15.39/14.99 (~ bnd_c8_1 X69 |
% 15.39/14.99 ((bnd_ndr1_1 X69 & bnd_c7_2 X69 bnd_a553) &
% 15.39/14.99 bnd_c10_2 X69 bnd_a553) &
% 15.39/14.99 bnd_c8_2 X69 bnd_a553) |
% 15.39/14.99 (ALL X70.
% 15.39/14.99 bnd_ndr1_1 X69 -->
% 15.39/14.99 (~ bnd_c9_2 X69 X70 | ~ bnd_c5_2 X69 X70) | bnd_c8_2 X69 X70)) |
% 15.39/14.99 bnd_c4_0)) &
% 15.39/14.99 ((~ bnd_c7_0 | ~ bnd_c1_0) |
% 15.39/14.99 (ALL X71.
% 15.39/14.99 bnd_ndr1_0 --> (~ bnd_c4_1 X71 | bnd_c5_1 X71) | bnd_c6_1 X71))) &
% 15.39/14.99 ((bnd_c8_0 | ~ bnd_c2_0) |
% 15.39/14.99 ((bnd_ndr1_0 & ~ bnd_c2_1 bnd_a554) & bnd_c8_1 bnd_a554) &
% 15.39/14.99 ~ bnd_c3_1 bnd_a554)) &
% 15.39/14.99 ((bnd_c4_0 | ~ bnd_c5_0) |
% 15.39/14.99 ~ bnd_c3_0)) &
% 15.39/14.99 (((ALL X72.
% 15.39/14.99 bnd_ndr1_0 -->
% 15.39/14.99 (~ bnd_c4_1 X72 |
% 15.39/14.99 (ALL X73.
% 15.39/14.99 bnd_ndr1_1 X72 --> ~ bnd_c2_2 X72 X73 | ~ bnd_c8_2 X72 X73)) |
% 15.39/14.99 ((bnd_ndr1_1 X72 & ~ bnd_c4_2 X72 bnd_a555) & bnd_c3_2 X72 bnd_a555) &
% 15.39/14.99 ~ bnd_c9_2 X72 bnd_a555) |
% 15.39/14.99 (ALL X74.
% 15.39/14.99 bnd_ndr1_0 -->
% 15.39/14.99 ((ALL X75.
% 15.39/14.99 bnd_ndr1_1 X74 -->
% 15.39/14.99 (~ bnd_c6_2 X74 X75 | bnd_c5_2 X74 X75) | bnd_c2_2 X74 X75) |
% 15.39/14.99 ~ bnd_c6_1 X74) |
% 15.39/14.99 (ALL X76.
% 15.39/14.99 bnd_ndr1_1 X74 -->
% 15.39/14.99 (~ bnd_c3_2 X74 X76 | bnd_c4_2 X74 X76) | bnd_c1_2 X74 X76))) |
% 15.39/14.99 ~ bnd_c6_0)) &
% 15.39/14.99 (((ALL X77.
% 15.39/14.99 bnd_ndr1_0 --> (~ bnd_c1_1 X77 | bnd_c9_1 X77) | bnd_c5_1 X77) |
% 15.39/14.99 bnd_c4_0) |
% 15.39/14.99 bnd_c8_0)) &
% 15.39/14.99 (((bnd_ndr1_0 &
% 15.39/14.99 (ALL X78.
% 15.39/14.99 bnd_ndr1_1 bnd_a556 -->
% 15.39/14.99 (bnd_c8_2 bnd_a556 X78 | bnd_c5_2 bnd_a556 X78) |
% 15.39/14.99 ~ bnd_c1_2 bnd_a556 X78)) &
% 15.39/14.99 ~ bnd_c5_1 bnd_a556) &
% 15.39/14.99 ~ bnd_c8_1 bnd_a556 |
% 15.39/14.99 ~ bnd_c3_0)) &
% 15.39/14.99 (bnd_c4_0 |
% 15.39/14.99 (ALL X79.
% 15.39/14.99 bnd_ndr1_0 -->
% 15.39/14.99 (bnd_c8_1 X79 | bnd_c10_1 X79) |
% 15.39/14.99 ((bnd_ndr1_1 X79 & ~ bnd_c8_2 X79 bnd_a557) & bnd_c1_2 X79 bnd_a557) &
% 15.39/14.99 ~ bnd_c6_2 X79 bnd_a557))) &
% 15.39/14.99 (((ALL X80.
% 15.39/14.99 bnd_ndr1_0 -->
% 15.39/14.99 (~ bnd_c3_1 X80 | ~ bnd_c9_1 X80) |
% 15.39/14.99 ((bnd_ndr1_1 X80 & ~ bnd_c9_2 X80 bnd_a558) & ~ bnd_c3_2 X80 bnd_a558) &
% 15.39/14.99 ~ bnd_c4_2 X80 bnd_a558) |
% 15.39/14.99 (ALL X81.
% 15.39/14.99 bnd_ndr1_0 -->
% 15.39/14.99 ((bnd_ndr1_1 X81 & ~ bnd_c8_2 X81 bnd_a559) & ~ bnd_c7_2 X81 bnd_a559) &
% 15.39/14.99 ~ bnd_c4_2 X81 bnd_a559)) |
% 15.39/14.99 (ALL X82.
% 15.39/14.99 bnd_ndr1_0 -->
% 15.39/14.99 (~ bnd_c2_1 X82 | bnd_c7_1 X82) |
% 15.39/14.99 (ALL X83.
% 15.39/14.99 bnd_ndr1_1 X82 -->
% 15.39/14.99 (~ bnd_c3_2 X82 X83 | ~ bnd_c6_2 X82 X83) | ~ bnd_c4_2 X82 X83)))) &
% 15.39/14.99 ((bnd_c1_0 | bnd_c4_0) | bnd_c10_0)) &
% 15.39/14.99 (((((bnd_ndr1_0 &
% 15.39/14.99 (ALL X84.
% 15.39/14.99 bnd_ndr1_1 bnd_a560 -->
% 15.39/14.99 (bnd_c10_2 bnd_a560 X84 | bnd_c3_2 bnd_a560 X84) |
% 15.39/14.99 ~ bnd_c8_2 bnd_a560 X84)) &
% 15.39/14.99 bnd_ndr1_1 bnd_a560) &
% 15.39/14.99 bnd_c2_2 bnd_a560 bnd_a561) &
% 15.39/14.99 bnd_c1_2 bnd_a560 bnd_a561 |
% 15.39/14.99 ~ bnd_c10_0) |
% 15.39/14.99 (ALL X85.
% 15.39/14.99 bnd_ndr1_0 -->
% 15.39/14.99 (bnd_c5_1 X85 | bnd_c9_1 X85) |
% 15.39/14.99 bnd_c7_1 X85))) &
% 15.39/14.99 (((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a562) &
% 15.39/14.99 bnd_c10_2 bnd_a562 bnd_a563) &
% 15.39/14.99 bnd_c4_2 bnd_a562 bnd_a563) &
% 15.39/14.99 ~ bnd_c1_2 bnd_a562 bnd_a563) &
% 15.39/14.99 (ALL X86.
% 15.39/14.99 bnd_ndr1_1 bnd_a562 -->
% 15.39/14.99 bnd_c9_2 bnd_a562 X86 |
% 15.39/14.99 bnd_c6_2 bnd_a562 X86)) &
% 15.39/14.99 bnd_c6_1 bnd_a562 |
% 15.39/14.99 bnd_c9_0) |
% 15.39/14.99 ~ bnd_c8_0)) &
% 15.39/14.99 (((ALL X87.
% 15.39/14.99 bnd_ndr1_0 -->
% 15.39/14.99 (~ bnd_c5_1 X87 |
% 15.39/14.99 (ALL X88.
% 15.39/14.99 bnd_ndr1_1 X87 -->
% 15.39/14.99 (~ bnd_c8_2 X87 X88 | ~ bnd_c5_2 X87 X88) | ~ bnd_c10_2 X87 X88)) |
% 15.39/14.99 (ALL X89.
% 15.39/14.99 bnd_ndr1_1 X87 -->
% 15.39/14.99 (~ bnd_c5_2 X87 X89 | ~ bnd_c3_2 X87 X89) | bnd_c10_2 X87 X89)) |
% 15.39/14.99 (ALL X90.
% 15.39/14.99 bnd_ndr1_0 -->
% 15.39/14.99 ((bnd_ndr1_1 X90 &
% 15.39/14.99 ~ bnd_c9_2 X90 bnd_a564) &
% 15.39/14.99 ~ bnd_c2_2 X90 bnd_a564 |
% 15.39/14.99 ~ bnd_c7_1 X90) |
% 15.39/14.99 ((bnd_ndr1_1 X90 &
% 15.39/14.99 bnd_c4_2 X90 bnd_a565) &
% 15.39/14.99 ~ bnd_c3_2 X90 bnd_a565) &
% 15.39/14.99 ~ bnd_c5_2 X90 bnd_a565)) |
% 15.39/14.99 ((bnd_ndr1_0 &
% 15.39/14.99 (ALL X91.
% 15.39/14.99 bnd_ndr1_1 bnd_a566 -->
% 15.39/14.99 (bnd_c5_2 bnd_a566 X91 |
% 15.39/14.99 bnd_c6_2 bnd_a566 X91) |
% 15.39/14.99 ~ bnd_c9_2 bnd_a566 X91)) &
% 15.39/14.99 ~ bnd_c3_1 bnd_a566) &
% 15.39/14.99 (ALL X92.
% 15.39/14.99 bnd_ndr1_1 bnd_a566 -->
% 15.39/14.99 (~ bnd_c7_2 bnd_a566 X92 |
% 15.39/14.99 bnd_c3_2 bnd_a566 X92) |
% 15.39/14.99 ~ bnd_c5_2 bnd_a566 X92))) &
% 15.39/14.99 ((~ bnd_c10_0 | ~ bnd_c1_0) | ~ bnd_c2_0)) &
% 15.39/14.99 (((ALL X93.
% 15.39/14.99 bnd_ndr1_0 -->
% 15.39/14.99 (((bnd_ndr1_1 X93 &
% 15.39/14.99 ~ bnd_c2_2 X93 bnd_a567) &
% 15.39/14.99 bnd_c6_2 X93 bnd_a567) &
% 15.39/14.99 ~ bnd_c3_2 X93 bnd_a567 |
% 15.39/14.99 (ALL X94.
% 15.39/14.99 bnd_ndr1_1 X93 -->
% 15.39/14.99 (~ bnd_c5_2 X93 X94 |
% 15.39/14.99 ~ bnd_c1_2 X93 X94) |
% 15.39/14.99 ~ bnd_c7_2 X93 X94)) |
% 15.39/14.99 (bnd_ndr1_1 X93 & bnd_c9_2 X93 bnd_a568) &
% 15.39/14.99 ~ bnd_c10_2 X93 bnd_a568) |
% 15.39/14.99 ~ bnd_c4_0) |
% 15.39/14.99 ((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a569) &
% 15.39/14.99 bnd_c5_2 bnd_a569 bnd_a570) &
% 15.39/14.99 ~ bnd_c7_2 bnd_a569 bnd_a570) &
% 15.39/14.99 ~ bnd_c1_2 bnd_a569 bnd_a570) &
% 15.39/14.99 bnd_c3_1 bnd_a569)) &
% 15.39/14.99 (((((bnd_ndr1_0 & bnd_c5_1 bnd_a571) &
% 15.39/14.99 bnd_ndr1_1 bnd_a571) &
% 15.39/14.99 bnd_c9_2 bnd_a571 bnd_a572) &
% 15.39/14.99 ~ bnd_c8_2 bnd_a571 bnd_a572) &
% 15.39/14.99 ~ bnd_c3_1 bnd_a571 |
% 15.39/14.99 bnd_c1_0)) &
% 15.39/14.99 ((bnd_c3_0 | bnd_c6_0) | ~ bnd_c2_0)) &
% 15.39/14.99 ((~ bnd_c9_0 | ~ bnd_c5_0) | bnd_c10_0)) &
% 15.39/14.99 ((~ bnd_c1_0 | ~ bnd_c8_0) |
% 15.39/14.99 ((bnd_ndr1_0 & bnd_c9_1 bnd_a573) &
% 15.39/14.99 (ALL X95.
% 15.39/14.99 bnd_ndr1_1 bnd_a573 -->
% 15.39/14.99 (bnd_c9_2 bnd_a573 X95 |
% 15.39/14.99 ~ bnd_c7_2 bnd_a573 X95) |
% 15.39/14.99 bnd_c8_2 bnd_a573 X95)) &
% 15.39/14.99 (ALL X96.
% 15.39/14.99 bnd_ndr1_1 bnd_a573 -->
% 15.39/14.99 ~ bnd_c7_2 bnd_a573 X96 |
% 15.39/14.99 bnd_c8_2 bnd_a573 X96))) &
% 15.39/14.99 ((~ bnd_c6_0 | ~ bnd_c10_0) | ~ bnd_c3_0)) &
% 15.39/14.99 ((~ bnd_c4_0 |
% 15.39/14.99 (ALL X97.
% 15.39/14.99 bnd_ndr1_0 -->
% 15.39/14.99 (~ bnd_c6_1 X97 | ~ bnd_c8_1 X97) |
% 15.39/14.99 ((bnd_ndr1_1 X97 & bnd_c6_2 X97 bnd_a574) &
% 15.39/14.99 bnd_c4_2 X97 bnd_a574) &
% 15.39/14.99 bnd_c7_2 X97 bnd_a574)) |
% 15.39/14.99 bnd_c2_0)) &
% 15.39/14.99 (((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a575) &
% 15.39/14.99 ~ bnd_c8_2 bnd_a575 bnd_a576) &
% 15.39/14.99 bnd_c9_2 bnd_a575 bnd_a576) &
% 15.39/14.99 bnd_c5_2 bnd_a575 bnd_a576) &
% 15.39/14.99 bnd_c7_1 bnd_a575) &
% 15.39/14.99 bnd_c5_1 bnd_a575 |
% 15.39/14.99 bnd_c7_0) |
% 15.39/14.99 ((bnd_ndr1_0 & ~ bnd_c1_1 bnd_a577) &
% 15.39/14.99 ~ bnd_c8_1 bnd_a577) &
% 15.39/14.99 ~ bnd_c6_1 bnd_a577)) &
% 15.39/14.99 (((((((bnd_ndr1_0 & ~ bnd_c8_1 bnd_a578) &
% 15.39/14.99 bnd_c1_1 bnd_a578) &
% 15.39/14.99 bnd_ndr1_1 bnd_a578) &
% 15.39/14.99 bnd_c7_2 bnd_a578 bnd_a579) &
% 15.39/14.99 bnd_c2_2 bnd_a578 bnd_a579) &
% 15.39/14.99 ~ bnd_c8_2 bnd_a578 bnd_a579 |
% 15.39/14.99 bnd_c10_0) |
% 15.39/14.99 bnd_c9_0)) &
% 15.39/14.99 (((ALL X98.
% 15.39/14.99 bnd_ndr1_0 -->
% 15.39/14.99 (~ bnd_c3_1 X98 | bnd_c7_1 X98) |
% 15.39/14.99 ((bnd_ndr1_1 X98 & bnd_c6_2 X98 bnd_a580) &
% 15.39/14.99 ~ bnd_c1_2 X98 bnd_a580) &
% 15.39/14.99 ~ bnd_c9_2 X98 bnd_a580) |
% 15.39/14.99 (ALL X99.
% 15.39/14.99 bnd_ndr1_0 -->
% 15.39/14.99 (bnd_c6_1 X99 |
% 15.39/14.99 (ALL X100.
% 15.39/14.99 bnd_ndr1_1 X99 -->
% 15.39/14.99 ~ bnd_c6_2 X99 X100 | ~ bnd_c5_2 X99 X100)) |
% 15.39/14.99 ~ bnd_c4_1 X99)) |
% 15.39/14.99 ~ bnd_c8_0)) &
% 15.39/14.99 ((~ bnd_c8_0 | bnd_c4_0) |
% 15.39/14.99 ((bnd_ndr1_0 & ~ bnd_c7_1 bnd_a581) &
% 15.39/14.99 (ALL X101.
% 15.39/14.99 bnd_ndr1_1 bnd_a581 -->
% 15.39/14.99 (bnd_c3_2 bnd_a581 X101 | bnd_c6_2 bnd_a581 X101) |
% 15.39/14.99 ~ bnd_c5_2 bnd_a581 X101)) &
% 15.39/14.99 bnd_c8_1 bnd_a581)) &
% 15.39/14.99 ((bnd_c1_0 |
% 15.39/14.99 ((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a582) &
% 15.39/14.99 bnd_c6_2 bnd_a582 bnd_a583) &
% 15.39/14.99 ~ bnd_c5_2 bnd_a582 bnd_a583) &
% 15.39/14.99 ~ bnd_c10_2 bnd_a582 bnd_a583) &
% 15.39/14.99 ~ bnd_c1_1 bnd_a582) |
% 15.39/14.99 (ALL X102.
% 15.39/14.99 bnd_ndr1_0 -->
% 15.39/14.99 (bnd_c5_1 X102 | ~ bnd_c10_1 X102) | bnd_c9_1 X102))) &
% 15.39/14.99 (((bnd_ndr1_0 & ~ bnd_c6_1 bnd_a584) & bnd_c8_1 bnd_a584) &
% 15.39/14.99 (ALL X103.
% 15.39/14.99 bnd_ndr1_1 bnd_a584 -->
% 15.39/14.99 (bnd_c10_2 bnd_a584 X103 | ~ bnd_c8_2 bnd_a584 X103) |
% 15.39/14.99 bnd_c3_2 bnd_a584 X103) |
% 15.39/14.99 ~ bnd_c3_0)) &
% 15.39/14.99 (((bnd_ndr1_0 & ~ bnd_c5_1 bnd_a585) & bnd_c9_1 bnd_a585 |
% 15.39/14.99 bnd_c8_0) |
% 15.39/14.99 ((((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a586) &
% 15.39/14.99 ~ bnd_c4_2 bnd_a586 bnd_a587) &
% 15.39/14.99 ~ bnd_c5_2 bnd_a586 bnd_a587) &
% 15.39/14.99 ~ bnd_c1_2 bnd_a586 bnd_a587) &
% 15.39/14.99 bnd_ndr1_1 bnd_a586) &
% 15.39/14.99 ~ bnd_c1_2 bnd_a586 bnd_a588) &
% 15.39/14.99 ~ bnd_c8_2 bnd_a586 bnd_a588) &
% 15.39/14.99 bnd_c3_2 bnd_a586 bnd_a588) &
% 15.39/14.99 bnd_c8_1 bnd_a586)) &
% 15.39/14.99 ((bnd_c4_0 | bnd_c3_0) | bnd_c5_0)) &
% 15.39/14.99 ((bnd_c3_0 |
% 15.39/14.99 (ALL X104.
% 15.39/14.99 bnd_ndr1_0 -->
% 15.39/14.99 (((bnd_ndr1_1 X104 & ~ bnd_c2_2 X104 bnd_a589) &
% 15.39/14.99 ~ bnd_c10_2 X104 bnd_a589) &
% 15.39/14.99 ~ bnd_c7_2 X104 bnd_a589 |
% 15.39/14.99 bnd_c10_1 X104) |
% 15.39/14.99 (ALL X105.
% 15.39/14.99 bnd_ndr1_1 X104 -->
% 15.39/14.99 ~ bnd_c1_2 X104 X105 | ~ bnd_c3_2 X104 X105))) |
% 15.39/14.99 (ALL X106.
% 15.39/14.99 bnd_ndr1_0 -->
% 15.39/14.99 ((bnd_ndr1_1 X106 & ~ bnd_c1_2 X106 bnd_a590) &
% 15.39/14.99 ~ bnd_c2_2 X106 bnd_a590) &
% 15.39/14.99 ~ bnd_c7_2 X106 bnd_a590 |
% 15.39/14.99 bnd_c8_1 X106))) &
% 15.39/14.99 (((ALL X107.
% 15.39/14.99 bnd_ndr1_0 -->
% 15.39/14.99 (~ bnd_c9_1 X107 | ~ bnd_c1_1 X107) |
% 15.39/14.99 (bnd_ndr1_1 X107 & ~ bnd_c1_2 X107 bnd_a591) &
% 15.39/14.99 bnd_c7_2 X107 bnd_a591) |
% 15.39/14.99 (bnd_ndr1_0 & bnd_c9_1 bnd_a592) & ~ bnd_c8_1 bnd_a592) |
% 15.39/14.99 (ALL X108.
% 15.39/14.99 bnd_ndr1_0 -->
% 15.39/14.99 ((ALL X109.
% 15.39/14.99 bnd_ndr1_1 X108 -->
% 15.39/14.99 (bnd_c3_2 X108 X109 | ~ bnd_c2_2 X108 X109) |
% 15.39/14.99 bnd_c1_2 X108 X109) |
% 15.39/14.99 ~ bnd_c3_1 X108) |
% 15.39/14.99 ((bnd_ndr1_1 X108 & ~ bnd_c5_2 X108 bnd_a593) &
% 15.39/14.99 ~ bnd_c6_2 X108 bnd_a593) &
% 15.39/14.99 ~ bnd_c8_2 X108 bnd_a593))) &
% 15.39/14.99 ((bnd_c1_0 |
% 15.39/14.99 (((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a594) &
% 15.39/14.99 ~ bnd_c3_2 bnd_a594 bnd_a595) &
% 15.39/14.99 ~ bnd_c4_2 bnd_a594 bnd_a595) &
% 15.39/14.99 bnd_c6_2 bnd_a594 bnd_a595) &
% 15.39/14.99 ~ bnd_c6_1 bnd_a594) &
% 15.39/14.99 bnd_ndr1_1 bnd_a594) &
% 15.39/14.99 bnd_c6_2 bnd_a594 bnd_a596) &
% 15.39/14.99 bnd_c3_2 bnd_a594 bnd_a596) |
% 15.39/14.99 bnd_c9_0)) &
% 15.39/14.99 ((bnd_c4_0 |
% 15.39/14.99 (((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a597) &
% 15.39/14.99 ~ bnd_c1_2 bnd_a597 bnd_a598) &
% 15.39/14.99 ~ bnd_c9_2 bnd_a597 bnd_a598) &
% 15.39/14.99 ~ bnd_c4_2 bnd_a597 bnd_a598) &
% 15.39/14.99 ~ bnd_c7_1 bnd_a597) &
% 15.39/14.99 (ALL X110.
% 15.39/14.99 bnd_ndr1_1 bnd_a597 -->
% 15.39/14.99 (~ bnd_c1_2 bnd_a597 X110 | ~ bnd_c3_2 bnd_a597 X110) |
% 15.39/14.99 bnd_c7_2 bnd_a597 X110)) |
% 15.39/14.99 ((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a599) &
% 15.39/14.99 bnd_c3_2 bnd_a599 bnd_a600) &
% 15.39/14.99 ~ bnd_c2_2 bnd_a599 bnd_a600) &
% 15.39/14.99 ~ bnd_c5_2 bnd_a599 bnd_a600) &
% 15.39/14.99 ~ bnd_c4_1 bnd_a599)) &
% 15.39/14.99 ((((bnd_ndr1_0 & bnd_c5_1 bnd_a601) & ~ bnd_c10_1 bnd_a601) &
% 15.39/14.99 (ALL X111.
% 15.39/14.99 bnd_ndr1_1 bnd_a601 -->
% 15.39/14.99 (bnd_c4_2 bnd_a601 X111 | bnd_c6_2 bnd_a601 X111) |
% 15.39/14.99 bnd_c7_2 bnd_a601 X111) |
% 15.39/14.99 (((((bnd_ndr1_0 &
% 15.39/14.99 (ALL X112.
% 15.39/14.99 bnd_ndr1_1 bnd_a602 -->
% 15.39/14.99 (bnd_c7_2 bnd_a602 X112 | ~ bnd_c2_2 bnd_a602 X112) |
% 15.39/14.99 ~ bnd_c4_2 bnd_a602 X112)) &
% 15.39/14.99 bnd_c7_1 bnd_a602) &
% 15.39/14.99 bnd_ndr1_1 bnd_a602) &
% 15.39/14.99 ~ bnd_c6_2 bnd_a602 bnd_a603) &
% 15.39/14.99 ~ bnd_c7_2 bnd_a602 bnd_a603) &
% 15.39/14.99 ~ bnd_c8_2 bnd_a602 bnd_a603) |
% 15.39/14.99 (ALL X113.
% 15.39/14.99 bnd_ndr1_0 -->
% 15.39/14.99 (((bnd_ndr1_1 X113 & bnd_c3_2 X113 bnd_a604) &
% 15.39/14.99 bnd_c10_2 X113 bnd_a604) &
% 15.39/14.99 ~ bnd_c6_2 X113 bnd_a604 |
% 15.39/14.99 ~ bnd_c6_1 X113) |
% 15.39/14.99 (ALL X114.
% 15.39/14.99 bnd_ndr1_1 X113 -->
% 15.39/14.99 (~ bnd_c2_2 X113 X114 | bnd_c4_2 X113 X114) |
% 15.39/14.99 bnd_c6_2 X113 X114)))) &
% 15.39/14.99 (((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a605) &
% 15.39/14.99 ~ bnd_c3_2 bnd_a605 bnd_a606) &
% 15.39/14.99 ~ bnd_c1_2 bnd_a605 bnd_a606) &
% 15.39/14.99 bnd_c2_2 bnd_a605 bnd_a606) &
% 15.39/14.99 ~ bnd_c5_1 bnd_a605) &
% 15.39/14.99 ~ bnd_c4_1 bnd_a605 |
% 15.39/14.99 ~ bnd_c9_0) |
% 15.39/14.99 (ALL X115.
% 15.39/14.99 bnd_ndr1_0 -->
% 15.39/14.99 ((ALL X116.
% 15.39/14.99 bnd_ndr1_1 X115 -->
% 15.39/14.99 (~ bnd_c3_2 X115 X116 | ~ bnd_c6_2 X115 X116) |
% 15.39/14.99 bnd_c2_2 X115 X116) |
% 15.39/14.99 bnd_c1_1 X115) |
% 15.39/14.99 ~ bnd_c10_1 X115))) &
% 15.39/14.99 (bnd_c9_0 | bnd_c4_0)) &
% 15.39/14.99 (((ALL X117.
% 15.39/14.99 bnd_ndr1_0 -->
% 15.39/14.99 (bnd_c2_1 X117 | ~ bnd_c6_1 X117) | ~ bnd_c7_1 X117) |
% 15.39/14.99 ~ bnd_c7_0) |
% 15.39/14.99 (ALL X118.
% 15.39/14.99 bnd_ndr1_0 -->
% 15.39/14.99 ((ALL X119.
% 15.39/14.99 bnd_ndr1_1 X118 --> bnd_c1_2 X118 X119 | bnd_c4_2 X118 X119) |
% 15.39/14.99 ~ bnd_c5_1 X118) |
% 15.39/14.99 ((bnd_ndr1_1 X118 & ~ bnd_c5_2 X118 bnd_a607) &
% 15.39/14.99 bnd_c4_2 X118 bnd_a607) &
% 15.39/14.99 ~ bnd_c2_2 X118 bnd_a607))) &
% 15.39/14.99 (((ALL X120.
% 15.39/14.99 bnd_ndr1_0 -->
% 15.39/14.99 (bnd_c5_1 X120 | bnd_c10_1 X120) |
% 15.39/14.99 (ALL X121.
% 15.39/14.99 bnd_ndr1_1 X120 -->
% 15.39/14.99 bnd_c3_2 X120 X121 | ~ bnd_c6_2 X120 X121)) |
% 15.39/14.99 bnd_c10_0) |
% 15.39/14.99 ~ bnd_c2_0))
% 15.39/14.99 Adding axioms...
% 15.49/15.00 Typedef.type_definition_def
% 40.63/40.19 ...done.
% 40.73/40.22 Ground types: ?'b, TPTP_Interpret.ind
% 40.73/40.22 Translating term (sizes: 1, 1) ...
% 61.69/61.14 Invoking SAT solver...
% 61.69/61.15 No model exists.
% 61.69/61.15 Translating term (sizes: 2, 1) ...
% 83.35/82.77 Invoking SAT solver...
% 83.35/82.78 No model exists.
% 83.35/82.78 Translating term (sizes: 1, 2) ...
% 120.17/119.48 Invoking SAT solver...
% 120.78/120.04 Model found:
% 120.78/120.04 Size of types: ?'b: 1, TPTP_Interpret.ind: 2
% 120.78/120.04 bnd_a607: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a606: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a605: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a604: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a603: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a602: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a601: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a600: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a599: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a598: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a597: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a596: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a595: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a594: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a593: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a592: ??.TPTP_Interpret.ind1
% 120.78/120.04 bnd_a591: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a590: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a589: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a588: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a587: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a586: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a585: ??.TPTP_Interpret.ind1
% 120.78/120.04 bnd_a584: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a583: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a582: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a581: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a580: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a579: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a578: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a577: ??.TPTP_Interpret.ind1
% 120.78/120.04 bnd_a576: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a575: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a574: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a573: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a572: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a571: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a570: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a569: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a568: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a567: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a566: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a565: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a564: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a563: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a562: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a561: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a560: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a559: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a558: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a557: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a556: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a555: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a554: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a553: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a552: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a551: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a550: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a549: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a548: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a547: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a546: ??.TPTP_Interpret.ind1
% 120.78/120.04 bnd_a545: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a544: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a543: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a542: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a541: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a540: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a539: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a538: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a537: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a536: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a535: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a534: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a533: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a532: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a531: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a530: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a529: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a528: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a527: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a526: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a525: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a524: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a523: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a522: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a521: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a520: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a519: ??.TPTP_Interpret.ind1
% 120.78/120.04 bnd_a518: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a517: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a516: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a515: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a514: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a513: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a512: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a511: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a510: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a509: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a508: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a507: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a506: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a505: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a504: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a503: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a502: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a501: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a500: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a499: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a498: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a497: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a496: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a495: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a494: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a493: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a492: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a491: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a490: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a489: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a488: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a487: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a486: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a485: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a484: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a483: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a482: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a481: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a480: ??.TPTP_Interpret.ind1
% 120.78/120.04 bnd_a479: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a478: ??.TPTP_Interpret.ind1
% 120.78/120.04 bnd_c8_0: False
% 120.78/120.04 bnd_a477: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a476: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a475: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a474: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a473: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a472: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a471: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a470: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a469: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_c10_0: True
% 120.78/120.04 bnd_a468: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a467: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a466: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a465: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a464: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_c5_2: {(??.TPTP_Interpret.ind0,
% 120.78/120.04 {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, False)}),
% 120.78/120.04 (??.TPTP_Interpret.ind1,
% 120.78/120.04 {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, False)})}
% 120.78/120.04 bnd_a463: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a462: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_c5_0: True
% 120.78/120.04 bnd_a461: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a460: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_c3_0: False
% 120.78/120.04 bnd_c1_0: True
% 120.78/120.04 bnd_c6_1: {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, False)}
% 120.78/120.04 bnd_c7_1: {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, True)}
% 120.78/120.04 bnd_c3_2: {(??.TPTP_Interpret.ind0,
% 120.78/120.04 {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, True)}),
% 120.78/120.04 (??.TPTP_Interpret.ind1,
% 120.78/120.04 {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, True)})}
% 120.78/120.04 bnd_a459: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_c10_1: {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, True)}
% 120.78/120.04 bnd_a458: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_c10_2: {(??.TPTP_Interpret.ind0,
% 120.78/120.04 {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, True)}),
% 120.78/120.04 (??.TPTP_Interpret.ind1,
% 120.78/120.04 {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, True)})}
% 120.78/120.04 bnd_a457: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_c2_1: {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, True)}
% 120.78/120.04 bnd_a456: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_a455: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_c9_1: {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, True)}
% 120.78/120.04 bnd_a454: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_c4_1: {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, False)}
% 120.78/120.04 bnd_c4_0: True
% 120.78/120.04 bnd_c7_0: False
% 120.78/120.04 bnd_a453: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_c1_2: {(??.TPTP_Interpret.ind0,
% 120.78/120.04 {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, False)}),
% 120.78/120.04 (??.TPTP_Interpret.ind1,
% 120.78/120.04 {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, False)})}
% 120.78/120.04 bnd_a452: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_c2_2: {(??.TPTP_Interpret.ind0,
% 120.78/120.04 {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, False)}),
% 120.78/120.04 (??.TPTP_Interpret.ind1,
% 120.78/120.04 {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, True)})}
% 120.78/120.04 bnd_c7_2: {(??.TPTP_Interpret.ind0,
% 120.78/120.04 {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, True)}),
% 120.78/120.04 (??.TPTP_Interpret.ind1,
% 120.78/120.04 {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, True)})}
% 120.78/120.04 bnd_a451: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_c2_0: False
% 120.78/120.04 bnd_c9_0: False
% 120.78/120.04 bnd_c6_0: True
% 120.78/120.04 bnd_c1_1: {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, False)}
% 120.78/120.04 bnd_c5_1: {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, False)}
% 120.78/120.04 bnd_c6_2: {(??.TPTP_Interpret.ind0,
% 120.78/120.04 {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, True)}),
% 120.78/120.04 (??.TPTP_Interpret.ind1,
% 120.78/120.04 {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, True)})}
% 120.78/120.04 bnd_c8_2: {(??.TPTP_Interpret.ind0,
% 120.78/120.04 {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, False)}),
% 120.78/120.04 (??.TPTP_Interpret.ind1,
% 120.78/120.04 {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, False)})}
% 120.78/120.04 bnd_a450: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_c4_2: {(??.TPTP_Interpret.ind0,
% 120.78/120.04 {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, False)}),
% 120.78/120.04 (??.TPTP_Interpret.ind1,
% 120.78/120.04 {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, False)})}
% 120.78/120.04 bnd_c9_2: {(??.TPTP_Interpret.ind0,
% 120.78/120.04 {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, True)}),
% 120.78/120.04 (??.TPTP_Interpret.ind1,
% 120.78/120.04 {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, True)})}
% 120.78/120.04 bnd_ndr1_1: {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, True)}
% 120.78/120.04 bnd_c8_1: {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, False)}
% 120.78/120.04 bnd_a449: ??.TPTP_Interpret.ind0
% 120.78/120.04 bnd_c3_1: {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, False)}
% 120.78/120.04 bnd_ndr1_0: True
% 120.78/120.04
% 120.78/120.04 % SZS status CounterSatisfiable
%------------------------------------------------------------------------------