TSTP Solution File: SYN418+1 by Refute---2015
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%------------------------------------------------------------------------------
% File : Refute---2015
% Problem : SYN418+1 : TPTP v6.4.0. Released v2.1.0.
% Transfm : none
% Format : tptp:raw
% Command : isabelle tptp_refute %d %s
% Computer : n143.star.cs.uiowa.edu
% Model : x86_64 x86_64
% CPU : Intel(R) Xeon(R) CPU E5-2609 0 2.40GHz
% Memory : 32218.75MB
% OS : Linux 3.10.0-327.10.1.el7.x86_64
% CPULimit : 300s
% DateTime : Thu Apr 14 06:41:40 EDT 2016
% Result : CounterSatisfiable 123.83s
% Output : Assurance 0s
% Verified :
% SZS Type : None (Parsing solution fails)
% Syntax : Number of formulae : 0
% Comments :
%------------------------------------------------------------------------------
%----No solution output by system
%------------------------------------------------------------------------------
%----ORIGINAL SYSTEM OUTPUT
% 0.00/0.03 % Problem : SYN418+1 : TPTP v6.4.0. Released v2.1.0.
% 0.00/0.04 % Command : isabelle tptp_refute %d %s
% 0.03/0.22 % Computer : n143.star.cs.uiowa.edu
% 0.03/0.22 % Model : x86_64 x86_64
% 0.03/0.22 % CPU : Intel(R) Xeon(R) CPU E5-2609 0 @ 2.40GHz
% 0.03/0.22 % Memory : 32218.75MB
% 0.03/0.22 % OS : Linux 3.10.0-327.10.1.el7.x86_64
% 0.03/0.22 % CPULimit : 300
% 0.03/0.22 % DateTime : Fri Apr 8 23:48:54 CDT 2016
% 0.03/0.23 % CPUTime:
% 6.31/5.86 > val it = (): unit
% 7.13/6.62 Trying to find a model that refutes: ~ (((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((bnd_ndr1_0 &
% 7.13/6.62 bnd_ndr1_1 bnd_a1) &
% 7.13/6.62 ~ bnd_c3_2 bnd_a1 bnd_a2) &
% 7.13/6.62 ~ bnd_c5_2 bnd_a1 bnd_a2) &
% 7.13/6.62 bnd_c6_2 bnd_a1 bnd_a2) &
% 7.13/6.62 bnd_c9_1 bnd_a1) &
% 7.13/6.62 bnd_c6_1 bnd_a1 |
% 7.13/6.62 ((((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a3) &
% 7.13/6.62 ~ bnd_c3_2 bnd_a3 bnd_a4) &
% 7.13/6.62 bnd_c1_2 bnd_a3 bnd_a4) &
% 7.13/6.62 bnd_c5_2 bnd_a3 bnd_a4) &
% 7.13/6.62 ~ bnd_c1_1 bnd_a3) &
% 7.13/6.62 bnd_ndr1_1 bnd_a3) &
% 7.13/6.62 ~ bnd_c1_2 bnd_a3 bnd_a5) &
% 7.13/6.62 bnd_c7_2 bnd_a3 bnd_a5) &
% 7.13/6.62 ~ bnd_c3_2 bnd_a3 bnd_a5) |
% 7.13/6.62 (ALL U. bnd_ndr1_0 --> bnd_c6_1 U | ~ bnd_c7_1 U)) &
% 7.13/6.62 (((bnd_ndr1_0 & bnd_c10_1 bnd_a6) & ~ bnd_c6_1 bnd_a6) &
% 7.13/6.62 ~ bnd_c4_1 bnd_a6 |
% 7.13/6.62 (((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a7) &
% 7.13/6.62 ~ bnd_c1_2 bnd_a7 bnd_a8) &
% 7.13/6.62 ~ bnd_c9_2 bnd_a7 bnd_a8) &
% 7.13/6.62 bnd_c2_2 bnd_a7 bnd_a8) &
% 7.13/6.62 bnd_c10_1 bnd_a7) &
% 7.13/6.62 bnd_c8_1 bnd_a7)) &
% 7.13/6.62 ((~ bnd_c7_0 |
% 7.13/6.62 (ALL V.
% 7.13/6.62 bnd_ndr1_0 -->
% 7.13/6.62 (~ bnd_c3_1 V | bnd_c6_1 V) |
% 7.13/6.62 (ALL W.
% 7.13/6.62 bnd_ndr1_1 V -->
% 7.13/6.62 (~ bnd_c6_2 V W | bnd_c1_2 V W) | ~ bnd_c8_2 V W))) |
% 7.13/6.62 ~ bnd_c10_0)) &
% 7.13/6.62 (((ALL X.
% 7.13/6.62 bnd_ndr1_0 -->
% 7.13/6.62 (bnd_c10_1 X | ~ bnd_c7_1 X) |
% 7.13/6.62 (ALL Y.
% 7.13/6.62 bnd_ndr1_1 X -->
% 7.13/6.62 (bnd_c3_2 X Y | ~ bnd_c10_2 X Y) | ~ bnd_c1_2 X Y)) |
% 7.13/6.62 (((((bnd_ndr1_0 & ~ bnd_c8_1 bnd_a9) &
% 7.13/6.62 (ALL Z.
% 7.13/6.62 bnd_ndr1_1 bnd_a9 -->
% 7.13/6.62 bnd_c4_2 bnd_a9 Z | bnd_c5_2 bnd_a9 Z)) &
% 7.13/6.62 bnd_ndr1_1 bnd_a9) &
% 7.13/6.62 ~ bnd_c3_2 bnd_a9 bnd_a10) &
% 7.13/6.62 ~ bnd_c6_2 bnd_a9 bnd_a10) &
% 7.13/6.62 bnd_c2_2 bnd_a9 bnd_a10) |
% 7.13/6.62 (ALL X1.
% 7.13/6.62 bnd_ndr1_0 -->
% 7.13/6.62 (((bnd_ndr1_1 X1 & bnd_c1_2 X1 bnd_a11) &
% 7.13/6.62 ~ bnd_c9_2 X1 bnd_a11) &
% 7.13/6.62 bnd_c2_2 X1 bnd_a11 |
% 7.13/6.62 ~ bnd_c3_1 X1) |
% 7.13/6.62 (ALL X2.
% 7.13/6.62 bnd_ndr1_1 X1 -->
% 7.13/6.62 (bnd_c4_2 X1 X2 | ~ bnd_c8_2 X1 X2) |
% 7.13/6.62 ~ bnd_c1_2 X1 X2)))) &
% 7.13/6.62 ((((((bnd_ndr1_0 & ~ bnd_c3_1 bnd_a12) & bnd_ndr1_1 bnd_a12) &
% 7.13/6.62 bnd_c6_2 bnd_a12 bnd_a13) &
% 7.13/6.62 bnd_c4_2 bnd_a12 bnd_a13) &
% 7.13/6.62 ~ bnd_c9_2 bnd_a12 bnd_a13 |
% 7.13/6.62 bnd_c8_0) |
% 7.13/6.62 (ALL X3.
% 7.13/6.62 bnd_ndr1_0 -->
% 7.13/6.62 ((ALL X4.
% 7.13/6.62 bnd_ndr1_1 X3 -->
% 7.13/6.62 (~ bnd_c2_2 X3 X4 | bnd_c1_2 X3 X4) | ~ bnd_c7_2 X3 X4) |
% 7.13/6.62 ~ bnd_c6_1 X3) |
% 7.13/6.62 ((bnd_ndr1_1 X3 & bnd_c2_2 X3 bnd_a14) & bnd_c10_2 X3 bnd_a14) &
% 7.13/6.62 ~ bnd_c7_2 X3 bnd_a14))) &
% 7.13/6.62 ((~ bnd_c3_0 | bnd_c1_0) | ~ bnd_c2_0)) &
% 7.13/6.62 ((~ bnd_c2_0 | ~ bnd_c3_0) | bnd_c4_0)) &
% 7.13/6.62 ((bnd_c8_0 |
% 7.13/6.62 (ALL X5.
% 7.13/6.62 bnd_ndr1_0 -->
% 7.13/6.62 (bnd_c3_1 X5 |
% 7.13/6.62 (ALL X6.
% 7.13/6.62 bnd_ndr1_1 X5 -->
% 7.13/6.62 (bnd_c7_2 X5 X6 | ~ bnd_c10_2 X5 X6) | bnd_c6_2 X5 X6)) |
% 7.13/6.62 ~ bnd_c10_1 X5)) |
% 7.13/6.62 ((bnd_ndr1_0 &
% 7.13/6.62 (ALL X7.
% 7.13/6.62 bnd_ndr1_1 bnd_a15 -->
% 7.13/6.62 (~ bnd_c2_2 bnd_a15 X7 | bnd_c5_2 bnd_a15 X7) |
% 7.13/6.62 ~ bnd_c4_2 bnd_a15 X7)) &
% 7.13/6.62 bnd_c3_1 bnd_a15) &
% 7.13/6.62 (ALL X8.
% 7.13/6.62 bnd_ndr1_1 bnd_a15 -->
% 7.13/6.62 (~ bnd_c9_2 bnd_a15 X8 | ~ bnd_c4_2 bnd_a15 X8) |
% 7.13/6.62 ~ bnd_c6_2 bnd_a15 X8))) &
% 7.13/6.62 ((~ bnd_c1_0 |
% 7.13/6.62 (((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a16) & ~ bnd_c8_2 bnd_a16 bnd_a17) &
% 7.13/6.62 ~ bnd_c2_2 bnd_a16 bnd_a17) &
% 7.13/6.62 bnd_c9_2 bnd_a16 bnd_a17) &
% 7.13/6.62 (ALL X9.
% 7.13/6.62 bnd_ndr1_1 bnd_a16 -->
% 7.13/6.62 (~ bnd_c4_2 bnd_a16 X9 | ~ bnd_c7_2 bnd_a16 X9) |
% 7.13/6.62 ~ bnd_c10_2 bnd_a16 X9)) &
% 7.13/6.62 ~ bnd_c3_1 bnd_a16) |
% 7.13/6.62 ((bnd_ndr1_0 & bnd_c6_1 bnd_a18) &
% 7.13/6.62 (ALL X10.
% 7.13/6.62 bnd_ndr1_1 bnd_a18 -->
% 7.13/6.62 (bnd_c8_2 bnd_a18 X10 | bnd_c4_2 bnd_a18 X10) |
% 7.13/6.62 bnd_c7_2 bnd_a18 X10)) &
% 7.13/6.62 bnd_c3_1 bnd_a18)) &
% 7.13/6.62 (((ALL X11. bnd_ndr1_0 --> ~ bnd_c6_1 X11) |
% 7.13/6.62 (((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a19) & bnd_c2_2 bnd_a19 bnd_a20) &
% 7.13/6.62 bnd_c9_2 bnd_a19 bnd_a20) &
% 7.13/6.62 ~ bnd_c4_2 bnd_a19 bnd_a20) &
% 7.13/6.62 bnd_ndr1_1 bnd_a19) &
% 7.13/6.62 bnd_c2_2 bnd_a19 bnd_a21) &
% 7.13/6.62 ~ bnd_c8_2 bnd_a19 bnd_a21) &
% 7.13/6.62 bnd_c7_1 bnd_a19) |
% 7.13/6.62 ((((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a22) & bnd_c2_2 bnd_a22 bnd_a23) &
% 7.13/6.62 bnd_c7_2 bnd_a22 bnd_a23) &
% 7.13/6.62 bnd_c10_2 bnd_a22 bnd_a23) &
% 7.13/6.62 bnd_ndr1_1 bnd_a22) &
% 7.13/6.62 ~ bnd_c6_2 bnd_a22 bnd_a24) &
% 7.13/6.62 ~ bnd_c1_2 bnd_a22 bnd_a24) &
% 7.13/6.62 ~ bnd_c2_2 bnd_a22 bnd_a24) &
% 7.13/6.62 bnd_c8_1 bnd_a22)) &
% 7.13/6.62 (~ bnd_c4_0 |
% 7.13/6.62 (ALL X12.
% 7.13/6.62 bnd_ndr1_0 -->
% 7.13/6.62 ((bnd_ndr1_1 X12 & bnd_c8_2 X12 bnd_a25) & bnd_c5_2 X12 bnd_a25) &
% 7.13/6.62 bnd_c3_2 X12 bnd_a25 |
% 7.13/6.62 ~ bnd_c3_1 X12))) &
% 7.13/6.62 ((bnd_c10_0 | ~ bnd_c9_0) |
% 7.13/6.62 (((((bnd_ndr1_0 & bnd_c8_1 bnd_a26) & bnd_ndr1_1 bnd_a26) &
% 7.13/6.62 bnd_c9_2 bnd_a26 bnd_a27) &
% 7.13/6.62 bnd_c6_2 bnd_a26 bnd_a27) &
% 7.13/6.62 ~ bnd_c5_2 bnd_a26 bnd_a27) &
% 7.13/6.62 (ALL X13.
% 7.13/6.62 bnd_ndr1_1 bnd_a26 -->
% 7.13/6.62 (~ bnd_c7_2 bnd_a26 X13 | bnd_c8_2 bnd_a26 X13) |
% 7.13/6.62 ~ bnd_c4_2 bnd_a26 X13))) &
% 7.13/6.62 ((bnd_c10_0 |
% 7.13/6.62 (ALL X14.
% 7.13/6.62 bnd_ndr1_0 -->
% 7.13/6.62 ((ALL X15.
% 7.13/6.62 bnd_ndr1_1 X14 -->
% 7.13/6.62 (~ bnd_c1_2 X14 X15 | bnd_c10_2 X14 X15) | ~ bnd_c9_2 X14 X15) |
% 7.13/6.62 (ALL X16.
% 7.13/6.62 bnd_ndr1_1 X14 -->
% 7.13/6.62 (bnd_c9_2 X14 X16 | bnd_c3_2 X14 X16) | bnd_c1_2 X14 X16)) |
% 7.13/6.62 (ALL X17.
% 7.13/6.62 bnd_ndr1_1 X14 -->
% 7.13/6.62 (bnd_c9_2 X14 X17 | ~ bnd_c1_2 X14 X17) | ~ bnd_c10_2 X14 X17))) |
% 7.13/6.62 bnd_c6_0)) &
% 7.13/6.62 ((~ bnd_c4_0 |
% 7.13/6.62 ((bnd_ndr1_0 &
% 7.13/6.62 (ALL X18.
% 7.13/6.62 bnd_ndr1_1 bnd_a28 -->
% 7.13/6.62 (bnd_c7_2 bnd_a28 X18 | bnd_c3_2 bnd_a28 X18) |
% 7.13/6.62 ~ bnd_c6_2 bnd_a28 X18)) &
% 7.13/6.62 ~ bnd_c10_1 bnd_a28) &
% 7.13/6.62 (ALL X19.
% 7.13/6.62 bnd_ndr1_1 bnd_a28 -->
% 7.13/6.62 (~ bnd_c1_2 bnd_a28 X19 | ~ bnd_c8_2 bnd_a28 X19) |
% 7.13/6.62 bnd_c5_2 bnd_a28 X19)) |
% 7.13/6.62 ~ bnd_c8_0)) &
% 7.13/6.62 ((bnd_c10_0 | ~ bnd_c7_0) | bnd_c8_0)) &
% 7.13/6.62 ((~ bnd_c6_0 | bnd_c7_0) | ~ bnd_c2_0)) &
% 7.13/6.62 ((bnd_c10_0 | bnd_c8_0) |
% 7.13/6.62 (ALL X20.
% 7.13/6.62 bnd_ndr1_0 -->
% 7.13/6.62 (bnd_c8_1 X20 | ~ bnd_c6_1 X20) |
% 7.13/6.62 (ALL X21. bnd_ndr1_1 X20 --> ~ bnd_c4_2 X20 X21 | ~ bnd_c7_2 X20 X21)))) &
% 7.13/6.62 ((~ bnd_c10_0 | ~ bnd_c5_0) |
% 7.13/6.62 (((((bnd_ndr1_0 & ~ bnd_c7_1 bnd_a29) &
% 7.13/6.62 bnd_c9_1 bnd_a29) &
% 7.13/6.62 bnd_ndr1_1 bnd_a29) &
% 7.13/6.62 bnd_c8_2 bnd_a29 bnd_a30) &
% 7.13/6.62 ~ bnd_c5_2 bnd_a29 bnd_a30) &
% 7.13/6.62 ~ bnd_c4_2 bnd_a29 bnd_a30)) &
% 7.13/6.62 (bnd_c5_0 | bnd_c10_0)) &
% 7.13/6.62 (((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a31) &
% 7.13/6.62 ~ bnd_c7_2 bnd_a31 bnd_a32) &
% 7.13/6.62 bnd_c3_2 bnd_a31 bnd_a32) &
% 7.13/6.62 bnd_c8_2 bnd_a31 bnd_a32) &
% 7.13/6.62 ~ bnd_c5_1 bnd_a31) &
% 7.13/6.62 (ALL X22.
% 7.13/6.62 bnd_ndr1_1 bnd_a31 -->
% 7.13/6.62 (~ bnd_c2_2 bnd_a31 X22 |
% 7.13/6.62 bnd_c1_2 bnd_a31 X22) |
% 7.13/6.62 bnd_c6_2 bnd_a31 X22) |
% 7.13/6.62 (((((bnd_ndr1_0 & bnd_c3_1 bnd_a33) &
% 7.13/6.62 bnd_ndr1_1 bnd_a33) &
% 7.13/6.62 ~ bnd_c6_2 bnd_a33 bnd_a34) &
% 7.13/6.62 bnd_c10_2 bnd_a33 bnd_a34) &
% 7.13/6.62 ~ bnd_c5_2 bnd_a33 bnd_a34) &
% 7.13/6.62 bnd_c6_1 bnd_a33) |
% 7.13/6.62 (((((bnd_ndr1_0 & ~ bnd_c8_1 bnd_a35) &
% 7.13/6.62 bnd_c2_1 bnd_a35) &
% 7.13/6.62 bnd_ndr1_1 bnd_a35) &
% 7.13/6.62 ~ bnd_c4_2 bnd_a35 bnd_a36) &
% 7.13/6.62 bnd_c7_2 bnd_a35 bnd_a36) &
% 7.13/6.62 bnd_c8_2 bnd_a35 bnd_a36)) &
% 7.13/6.62 (((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a37) &
% 7.13/6.62 bnd_c4_2 bnd_a37 bnd_a38) &
% 7.13/6.62 bnd_c6_2 bnd_a37 bnd_a38) &
% 7.13/6.62 ~ bnd_c3_2 bnd_a37 bnd_a38) &
% 7.13/6.62 (ALL X23.
% 7.13/6.62 bnd_ndr1_1 bnd_a37 -->
% 7.13/6.62 ~ bnd_c7_2 bnd_a37 X23 |
% 7.13/6.62 bnd_c10_2 bnd_a37 X23)) &
% 7.13/6.62 ~ bnd_c5_1 bnd_a37 |
% 7.13/6.62 (ALL X24.
% 7.13/6.62 bnd_ndr1_0 -->
% 7.13/6.62 ((ALL X25.
% 7.13/6.62 bnd_ndr1_1 X24 -->
% 7.13/6.62 (~ bnd_c2_2 X24 X25 | bnd_c10_2 X24 X25) | ~ bnd_c5_2 X24 X25) |
% 7.13/6.62 ((bnd_ndr1_1 X24 &
% 7.13/6.62 bnd_c2_2 X24 bnd_a39) &
% 7.13/6.62 ~ bnd_c9_2 X24 bnd_a39) &
% 7.13/6.62 ~ bnd_c3_2 X24 bnd_a39) |
% 7.13/6.62 (ALL X26.
% 7.13/6.62 bnd_ndr1_1 X24 -->
% 7.13/6.62 (~ bnd_c4_2 X24 X26 | bnd_c5_2 X24 X26) | bnd_c3_2 X24 X26))) |
% 7.13/6.62 (ALL X27.
% 7.13/6.62 bnd_ndr1_0 -->
% 7.13/6.62 (((bnd_ndr1_1 X27 &
% 7.13/6.62 ~ bnd_c3_2 X27 bnd_a40) &
% 7.13/6.62 ~ bnd_c4_2 X27 bnd_a40) &
% 7.13/6.62 bnd_c9_2 X27 bnd_a40 |
% 7.13/6.62 (ALL X28.
% 7.13/6.62 bnd_ndr1_1 X27 -->
% 7.13/6.62 (~ bnd_c8_2 X27 X28 | ~ bnd_c6_2 X27 X28) | ~ bnd_c3_2 X27 X28)) |
% 7.13/6.62 (ALL X29.
% 7.13/6.62 bnd_ndr1_1 X27 -->
% 7.13/6.62 (~ bnd_c9_2 X27 X29 | ~ bnd_c2_2 X27 X29) | bnd_c7_2 X27 X29)))) &
% 7.13/6.62 ((bnd_c9_0 |
% 7.13/6.62 (bnd_ndr1_0 &
% 7.13/6.62 (ALL X30.
% 7.13/6.62 bnd_ndr1_1 bnd_a41 -->
% 7.13/6.62 (bnd_c8_2 bnd_a41 X30 |
% 7.13/6.62 bnd_c3_2 bnd_a41 X30) |
% 7.13/6.62 bnd_c6_2 bnd_a41 X30)) &
% 7.13/6.62 ~ bnd_c10_1 bnd_a41) |
% 7.13/6.62 (ALL X31.
% 7.13/6.62 bnd_ndr1_0 -->
% 7.13/6.62 (((bnd_ndr1_1 X31 & bnd_c5_2 X31 bnd_a42) &
% 7.13/6.62 bnd_c4_2 X31 bnd_a42) &
% 7.13/6.62 ~ bnd_c10_2 X31 bnd_a42 |
% 7.13/6.62 (ALL X32.
% 7.13/6.62 bnd_ndr1_1 X31 -->
% 7.13/6.62 (bnd_c2_2 X31 X32 | ~ bnd_c7_2 X31 X32) | bnd_c3_2 X31 X32)) |
% 7.13/6.62 (ALL X33.
% 7.13/6.62 bnd_ndr1_1 X31 -->
% 7.13/6.62 ~ bnd_c9_2 X31 X33 |
% 7.13/6.62 ~ bnd_c8_2 X31 X33)))) &
% 7.13/6.62 ((~ bnd_c5_0 |
% 7.13/6.62 (ALL X34.
% 7.13/6.62 bnd_ndr1_0 -->
% 7.13/6.62 (((bnd_ndr1_1 X34 & bnd_c1_2 X34 bnd_a43) &
% 7.13/6.62 ~ bnd_c8_2 X34 bnd_a43) &
% 7.13/6.62 bnd_c10_2 X34 bnd_a43 |
% 7.13/6.62 (ALL X35.
% 7.13/6.62 bnd_ndr1_1 X34 -->
% 7.13/6.62 (~ bnd_c3_2 X34 X35 | bnd_c4_2 X34 X35) | bnd_c2_2 X34 X35)) |
% 7.13/6.62 (ALL X36.
% 7.13/6.62 bnd_ndr1_1 X34 -->
% 7.13/6.62 (~ bnd_c4_2 X34 X36 |
% 7.13/6.62 ~ bnd_c9_2 X34 X36) |
% 7.13/6.62 ~ bnd_c3_2 X34 X36))) |
% 7.13/6.62 bnd_c3_0)) &
% 7.13/6.62 ((~ bnd_c10_0 |
% 7.13/6.62 ((bnd_ndr1_0 &
% 7.13/6.62 (ALL X37.
% 7.13/6.62 bnd_ndr1_1 bnd_a44 -->
% 7.13/6.62 (~ bnd_c5_2 bnd_a44 X37 |
% 7.13/6.62 bnd_c4_2 bnd_a44 X37) |
% 7.13/6.62 bnd_c3_2 bnd_a44 X37)) &
% 7.13/6.62 bnd_c4_1 bnd_a44) &
% 7.13/6.62 bnd_c3_1 bnd_a44) |
% 7.13/6.62 ~ bnd_c1_0)) &
% 7.13/6.62 (((ALL X38.
% 7.13/6.62 bnd_ndr1_0 -->
% 7.13/6.62 ~ bnd_c8_1 X38 | bnd_c1_1 X38) |
% 7.13/6.62 (((((((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a45) &
% 7.13/6.62 ~ bnd_c10_2 bnd_a45 bnd_a46) &
% 7.13/6.62 ~ bnd_c8_2 bnd_a45 bnd_a46) &
% 7.13/6.62 ~ bnd_c4_2 bnd_a45 bnd_a46) &
% 7.13/6.62 bnd_ndr1_1 bnd_a45) &
% 7.13/6.62 bnd_c3_2 bnd_a45 bnd_a47) &
% 7.13/6.62 ~ bnd_c4_2 bnd_a45 bnd_a47) &
% 7.13/6.62 ~ bnd_c1_2 bnd_a45 bnd_a47) &
% 7.13/6.62 bnd_ndr1_1 bnd_a45) &
% 7.13/6.62 bnd_c7_2 bnd_a45 bnd_a48) &
% 7.13/6.62 ~ bnd_c2_2 bnd_a45 bnd_a48) &
% 7.13/6.62 bnd_c9_2 bnd_a45 bnd_a48) |
% 7.13/6.62 (ALL X39.
% 7.13/6.62 bnd_ndr1_0 -->
% 7.13/6.62 (bnd_c1_1 X39 |
% 7.13/6.62 ((bnd_ndr1_1 X39 & bnd_c5_2 X39 bnd_a49) &
% 7.13/6.62 ~ bnd_c3_2 X39 bnd_a49) &
% 7.13/6.62 bnd_c7_2 X39 bnd_a49) |
% 7.13/6.62 ((bnd_ndr1_1 X39 & bnd_c1_2 X39 bnd_a50) &
% 7.13/6.62 bnd_c8_2 X39 bnd_a50) &
% 7.13/6.62 bnd_c10_2 X39 bnd_a50))) &
% 7.13/6.62 (((ALL X40.
% 7.13/6.62 bnd_ndr1_0 -->
% 7.13/6.62 bnd_c10_1 X40 | ~ bnd_c4_1 X40) |
% 7.13/6.62 (ALL X41.
% 7.13/6.62 bnd_ndr1_0 -->
% 7.13/6.62 (bnd_c3_1 X41 | ~ bnd_c8_1 X41) |
% 7.13/6.62 ~ bnd_c2_1 X41)) |
% 7.13/6.62 bnd_c2_0)) &
% 7.13/6.62 ((ALL X42.
% 7.13/6.62 bnd_ndr1_0 -->
% 7.13/6.62 (ALL X43.
% 7.13/6.62 bnd_ndr1_1 X42 -->
% 7.13/6.62 (bnd_c6_2 X42 X43 | ~ bnd_c7_2 X42 X43) |
% 7.13/6.62 bnd_c1_2 X42 X43) |
% 7.13/6.62 bnd_c10_1 X42) |
% 7.13/6.62 bnd_c8_0)) &
% 7.13/6.62 ((~ bnd_c7_0 | ~ bnd_c9_0) | bnd_c4_0)) &
% 7.13/6.62 ((~ bnd_c6_0 |
% 7.13/6.62 ((bnd_ndr1_0 &
% 7.13/6.62 (ALL X44.
% 7.13/6.62 bnd_ndr1_1 bnd_a51 -->
% 7.13/6.62 (~ bnd_c9_2 bnd_a51 X44 |
% 7.13/6.62 ~ bnd_c1_2 bnd_a51 X44) |
% 7.13/6.62 ~ bnd_c4_2 bnd_a51 X44)) &
% 7.13/6.62 bnd_c6_1 bnd_a51) &
% 7.13/6.62 bnd_c2_1 bnd_a51) |
% 7.13/6.62 bnd_c4_0)) &
% 7.13/6.62 ((~ bnd_c10_0 | bnd_c3_0) |
% 7.13/6.62 (ALL X45.
% 7.13/6.62 bnd_ndr1_0 -->
% 7.13/6.62 ((ALL X46.
% 7.13/6.62 bnd_ndr1_1 X45 -->
% 7.13/6.62 bnd_c10_2 X45 X46 | ~ bnd_c7_2 X45 X46) |
% 7.13/6.62 bnd_c10_1 X45) |
% 7.13/6.62 ((bnd_ndr1_1 X45 & bnd_c8_2 X45 bnd_a52) &
% 7.13/6.62 ~ bnd_c9_2 X45 bnd_a52) &
% 7.13/6.62 bnd_c3_2 X45 bnd_a52))) &
% 7.13/6.62 ((~ bnd_c1_0 | ~ bnd_c5_0) |
% 7.13/6.62 ((((bnd_ndr1_0 &
% 7.13/6.62 (ALL X47.
% 7.13/6.62 bnd_ndr1_1 bnd_a53 -->
% 7.13/6.62 (bnd_c1_2 bnd_a53 X47 |
% 7.13/6.62 ~ bnd_c3_2 bnd_a53 X47) |
% 7.13/6.62 bnd_c6_2 bnd_a53 X47)) &
% 7.13/6.62 bnd_ndr1_1 bnd_a53) &
% 7.13/6.62 ~ bnd_c3_2 bnd_a53 bnd_a54) &
% 7.13/6.62 bnd_c9_2 bnd_a53 bnd_a54) &
% 7.13/6.62 (ALL X48.
% 7.13/6.62 bnd_ndr1_1 bnd_a53 -->
% 7.13/6.62 (bnd_c4_2 bnd_a53 X48 | ~ bnd_c10_2 bnd_a53 X48) |
% 7.13/6.62 bnd_c7_2 bnd_a53 X48))) &
% 7.13/6.62 (((bnd_ndr1_0 & ~ bnd_c6_1 bnd_a55) &
% 7.13/6.62 ~ bnd_c10_1 bnd_a55 |
% 7.13/6.62 (bnd_ndr1_0 & ~ bnd_c1_1 bnd_a56) &
% 7.13/6.62 ~ bnd_c8_1 bnd_a56) |
% 7.13/6.62 (ALL X49.
% 7.13/6.62 bnd_ndr1_0 -->
% 7.13/6.62 (bnd_c6_1 X49 |
% 7.13/6.62 (ALL X50.
% 7.13/6.62 bnd_ndr1_1 X49 -->
% 7.13/6.62 (bnd_c2_2 X49 X50 | bnd_c6_2 X49 X50) |
% 7.13/6.62 bnd_c4_2 X49 X50)) |
% 7.13/6.62 bnd_c1_1 X49))) &
% 7.13/6.62 ((~ bnd_c6_0 | ~ bnd_c5_0) |
% 7.13/6.62 (ALL X51. bnd_ndr1_0 --> bnd_c10_1 X51 | bnd_c4_1 X51))) &
% 7.13/6.62 ((bnd_c4_0 | bnd_c6_0) | bnd_c2_0)) &
% 7.13/6.62 ((~ bnd_c2_0 |
% 7.13/6.62 (ALL X52.
% 7.13/6.62 bnd_ndr1_0 -->
% 7.13/6.62 (bnd_c9_1 X52 |
% 7.13/6.62 ((bnd_ndr1_1 X52 & ~ bnd_c5_2 X52 bnd_a57) &
% 7.13/6.62 bnd_c7_2 X52 bnd_a57) &
% 7.13/6.62 ~ bnd_c4_2 X52 bnd_a57) |
% 7.13/6.62 ((bnd_ndr1_1 X52 & bnd_c3_2 X52 bnd_a58) &
% 7.13/6.62 ~ bnd_c4_2 X52 bnd_a58) &
% 7.13/6.62 bnd_c2_2 X52 bnd_a58)) |
% 7.13/6.62 (bnd_ndr1_0 &
% 7.13/6.62 (ALL X53.
% 7.13/6.62 bnd_ndr1_1 bnd_a59 -->
% 7.13/6.62 (~ bnd_c7_2 bnd_a59 X53 | bnd_c8_2 bnd_a59 X53) |
% 7.13/6.62 bnd_c9_2 bnd_a59 X53)) &
% 7.13/6.62 ~ bnd_c9_1 bnd_a59)) &
% 7.13/6.62 (((ALL X54. bnd_ndr1_0 --> ~ bnd_c3_1 X54 | bnd_c8_1 X54) |
% 7.13/6.62 (ALL X55.
% 7.13/6.62 bnd_ndr1_0 -->
% 7.13/6.62 ((ALL X56.
% 7.13/6.62 bnd_ndr1_1 X55 -->
% 7.13/6.62 (bnd_c7_2 X55 X56 | bnd_c5_2 X55 X56) |
% 7.13/6.62 ~ bnd_c1_2 X55 X56) |
% 7.13/6.62 ((bnd_ndr1_1 X55 & bnd_c7_2 X55 bnd_a60) &
% 7.13/6.62 ~ bnd_c9_2 X55 bnd_a60) &
% 7.13/6.62 bnd_c5_2 X55 bnd_a60) |
% 7.13/6.62 (bnd_ndr1_1 X55 & bnd_c9_2 X55 bnd_a61) &
% 7.13/6.62 ~ bnd_c5_2 X55 bnd_a61)) |
% 7.13/6.62 (ALL X57.
% 7.13/6.62 bnd_ndr1_0 -->
% 7.13/6.62 (((bnd_ndr1_1 X57 & ~ bnd_c9_2 X57 bnd_a62) &
% 7.13/6.62 bnd_c3_2 X57 bnd_a62) &
% 7.13/6.62 bnd_c5_2 X57 bnd_a62 |
% 7.13/6.62 ((bnd_ndr1_1 X57 & ~ bnd_c7_2 X57 bnd_a63) &
% 7.13/6.62 ~ bnd_c8_2 X57 bnd_a63) &
% 7.13/6.62 bnd_c3_2 X57 bnd_a63) |
% 7.13/6.62 ~ bnd_c5_1 X57))) &
% 7.13/6.62 (((ALL X58.
% 7.13/6.62 bnd_ndr1_0 -->
% 7.13/6.62 ((bnd_ndr1_1 X58 & ~ bnd_c6_2 X58 bnd_a64) &
% 7.13/6.62 ~ bnd_c9_2 X58 bnd_a64 |
% 7.13/6.62 ((bnd_ndr1_1 X58 & bnd_c4_2 X58 bnd_a65) &
% 7.13/6.62 bnd_c5_2 X58 bnd_a65) &
% 7.13/6.62 ~ bnd_c6_2 X58 bnd_a65) |
% 7.13/6.62 ~ bnd_c4_1 X58) |
% 7.13/6.62 ~ bnd_c3_0) |
% 7.13/6.62 ~ bnd_c10_0)) &
% 7.13/6.62 ((((bnd_ndr1_0 &
% 7.13/6.62 (ALL X59.
% 7.13/6.62 bnd_ndr1_1 bnd_a66 -->
% 7.13/6.62 bnd_c3_2 bnd_a66 X59 | bnd_c1_2 bnd_a66 X59)) &
% 7.13/6.62 ~ bnd_c9_1 bnd_a66) &
% 7.13/6.62 bnd_c4_1 bnd_a66 |
% 7.13/6.62 (ALL X60.
% 7.13/6.62 bnd_ndr1_0 -->
% 7.13/6.62 (~ bnd_c10_1 X60 | ~ bnd_c8_1 X60) |
% 7.13/6.62 ((bnd_ndr1_1 X60 & bnd_c4_2 X60 bnd_a67) &
% 7.13/6.62 ~ bnd_c2_2 X60 bnd_a67) &
% 7.13/6.62 ~ bnd_c1_2 X60 bnd_a67)) |
% 7.13/6.62 bnd_c7_0)) &
% 7.13/6.62 ((bnd_c3_0 |
% 7.13/6.62 (((((bnd_ndr1_0 & bnd_c2_1 bnd_a68) & bnd_ndr1_1 bnd_a68) &
% 7.13/6.62 ~ bnd_c3_2 bnd_a68 bnd_a69) &
% 7.13/6.62 ~ bnd_c5_2 bnd_a68 bnd_a69) &
% 7.13/6.62 ~ bnd_c7_2 bnd_a68 bnd_a69) &
% 7.13/6.62 bnd_c4_1 bnd_a68) |
% 7.13/6.62 (ALL X61.
% 7.13/6.62 bnd_ndr1_0 -->
% 7.13/6.62 (((bnd_ndr1_1 X61 & ~ bnd_c5_2 X61 bnd_a70) &
% 7.13/6.62 ~ bnd_c4_2 X61 bnd_a70) &
% 7.13/6.62 ~ bnd_c3_2 X61 bnd_a70 |
% 7.13/6.62 (ALL X62.
% 7.13/6.62 bnd_ndr1_1 X61 -->
% 7.13/6.62 (~ bnd_c5_2 X61 X62 | bnd_c3_2 X61 X62) |
% 7.13/6.62 bnd_c2_2 X61 X62)) |
% 7.13/6.62 ~ bnd_c1_1 X61))) &
% 7.13/6.62 (((ALL X63.
% 7.13/6.62 bnd_ndr1_0 -->
% 7.13/6.62 ((ALL X64.
% 7.13/6.62 bnd_ndr1_1 X63 -->
% 7.13/6.62 (bnd_c2_2 X63 X64 | ~ bnd_c7_2 X63 X64) |
% 7.13/6.62 ~ bnd_c3_2 X63 X64) |
% 7.13/6.62 bnd_c5_1 X63) |
% 7.13/6.62 (ALL X65.
% 7.13/6.62 bnd_ndr1_1 X63 -->
% 7.13/6.62 (bnd_c1_2 X63 X65 | ~ bnd_c8_2 X63 X65) |
% 7.13/6.62 ~ bnd_c5_2 X63 X65)) |
% 7.13/6.62 (ALL X66.
% 7.13/6.62 bnd_ndr1_0 -->
% 7.13/6.62 (bnd_c1_1 X66 |
% 7.13/6.62 (ALL X67.
% 7.13/6.62 bnd_ndr1_1 X66 -->
% 7.13/6.62 (~ bnd_c8_2 X66 X67 | bnd_c10_2 X66 X67) |
% 7.13/6.62 ~ bnd_c7_2 X66 X67)) |
% 7.13/6.62 bnd_c10_1 X66)) |
% 7.13/6.62 (((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a71) &
% 7.13/6.62 bnd_c4_2 bnd_a71 bnd_a72) &
% 7.13/6.62 ~ bnd_c10_2 bnd_a71 bnd_a72) &
% 7.13/6.62 bnd_c7_2 bnd_a71 bnd_a72) &
% 7.13/6.62 ~ bnd_c8_1 bnd_a71) &
% 7.13/6.62 ~ bnd_c2_1 bnd_a71)) &
% 7.13/6.62 (((bnd_ndr1_0 &
% 7.13/6.62 (ALL X68.
% 7.13/6.62 bnd_ndr1_1 bnd_a73 -->
% 7.13/6.62 (bnd_c5_2 bnd_a73 X68 | ~ bnd_c10_2 bnd_a73 X68) |
% 7.13/6.62 ~ bnd_c7_2 bnd_a73 X68)) &
% 7.13/6.62 ~ bnd_c4_1 bnd_a73) &
% 7.13/6.62 ~ bnd_c7_1 bnd_a73 |
% 7.13/6.62 (ALL X69.
% 7.13/6.62 bnd_ndr1_0 -->
% 7.13/6.62 ((ALL X70.
% 7.13/6.62 bnd_ndr1_1 X69 -->
% 7.13/6.62 (bnd_c9_2 X69 X70 | bnd_c2_2 X69 X70) |
% 7.13/6.62 ~ bnd_c8_2 X69 X70) |
% 7.13/6.62 bnd_c8_1 X69) |
% 7.13/6.62 (ALL X71.
% 7.13/6.62 bnd_ndr1_1 X69 -->
% 7.13/6.62 (bnd_c7_2 X69 X71 | bnd_c6_2 X69 X71) |
% 7.13/6.62 ~ bnd_c5_2 X69 X71)))) &
% 7.13/6.62 ((bnd_c8_0 | bnd_c7_0) | bnd_c4_0)) &
% 7.13/6.62 ((bnd_c8_0 |
% 7.13/6.62 (ALL X72.
% 7.13/6.62 bnd_ndr1_0 -->
% 7.13/6.62 (ALL X73.
% 7.13/6.62 bnd_ndr1_1 X72 -->
% 7.13/6.62 (~ bnd_c10_2 X72 X73 | bnd_c6_2 X72 X73) |
% 7.13/6.62 ~ bnd_c1_2 X72 X73) |
% 7.13/6.62 ~ bnd_c1_1 X72)) |
% 7.13/6.62 (ALL X74.
% 7.13/6.62 bnd_ndr1_0 -->
% 7.13/6.62 ((bnd_ndr1_1 X74 & ~ bnd_c2_2 X74 bnd_a74) &
% 7.13/6.62 ~ bnd_c8_2 X74 bnd_a74) &
% 7.13/6.62 bnd_c3_2 X74 bnd_a74))) &
% 7.13/6.62 ((~ bnd_c10_0 |
% 7.13/6.62 ((bnd_ndr1_0 &
% 7.13/6.62 (ALL X75.
% 7.13/6.62 bnd_ndr1_1 bnd_a75 -->
% 7.13/6.62 (~ bnd_c5_2 bnd_a75 X75 | ~ bnd_c6_2 bnd_a75 X75) |
% 7.13/6.62 bnd_c4_2 bnd_a75 X75)) &
% 7.13/6.62 ~ bnd_c9_1 bnd_a75) &
% 7.13/6.62 ~ bnd_c2_1 bnd_a75) |
% 7.13/6.62 (ALL X76.
% 7.13/6.62 bnd_ndr1_0 -->
% 7.13/6.62 (~ bnd_c5_1 X76 |
% 7.13/6.62 ((bnd_ndr1_1 X76 & bnd_c7_2 X76 bnd_a76) &
% 7.13/6.62 bnd_c6_2 X76 bnd_a76) &
% 7.13/6.62 bnd_c8_2 X76 bnd_a76) |
% 7.13/6.62 (ALL X77.
% 7.13/6.62 bnd_ndr1_1 X76 -->
% 7.13/6.62 (bnd_c7_2 X76 X77 | ~ bnd_c5_2 X76 X77) |
% 7.13/6.62 ~ bnd_c1_2 X76 X77)))) &
% 7.13/6.62 ((bnd_c4_0 | bnd_c1_0) |
% 7.13/6.62 (((((bnd_ndr1_0 & ~ bnd_c2_1 bnd_a77) & bnd_ndr1_1 bnd_a77) &
% 7.13/6.62 ~ bnd_c1_2 bnd_a77 bnd_a78) &
% 7.13/6.62 ~ bnd_c8_2 bnd_a77 bnd_a78) &
% 7.13/6.62 bnd_c5_2 bnd_a77 bnd_a78) &
% 7.13/6.62 bnd_c4_1 bnd_a77)) &
% 7.13/6.62 (~ bnd_c7_0 |
% 7.13/6.62 (ALL X78.
% 7.13/6.62 bnd_ndr1_0 -->
% 7.13/6.62 (bnd_c7_1 X78 |
% 7.13/6.62 (bnd_ndr1_1 X78 & ~ bnd_c8_2 X78 bnd_a79) &
% 7.13/6.62 bnd_c2_2 X78 bnd_a79) |
% 7.13/6.62 ((bnd_ndr1_1 X78 & bnd_c10_2 X78 bnd_a80) &
% 7.13/6.62 ~ bnd_c4_2 X78 bnd_a80) &
% 7.13/6.62 bnd_c3_2 X78 bnd_a80))) &
% 7.13/6.62 (bnd_c2_0 | bnd_c10_0)) &
% 7.13/6.62 ((bnd_c9_0 |
% 7.13/6.62 (ALL X79.
% 7.13/6.62 bnd_ndr1_0 -->
% 7.13/6.62 ((ALL X80.
% 7.13/6.62 bnd_ndr1_1 X79 -->
% 7.13/6.62 (~ bnd_c5_2 X79 X80 | bnd_c8_2 X79 X80) | ~ bnd_c3_2 X79 X80) |
% 7.13/6.62 bnd_c10_1 X79) |
% 7.13/6.62 bnd_c7_1 X79)) |
% 7.13/6.62 (((((bnd_ndr1_0 & ~ bnd_c1_1 bnd_a81) & ~ bnd_c9_1 bnd_a81) &
% 7.13/6.62 bnd_ndr1_1 bnd_a81) &
% 7.13/6.62 ~ bnd_c10_2 bnd_a81 bnd_a82) &
% 7.13/6.62 bnd_c3_2 bnd_a81 bnd_a82) &
% 7.13/6.62 ~ bnd_c1_2 bnd_a81 bnd_a82)) &
% 7.13/6.62 (((ALL X81.
% 7.13/6.62 bnd_ndr1_0 -->
% 7.13/6.62 ((ALL X82.
% 7.13/6.62 bnd_ndr1_1 X81 -->
% 7.13/6.62 (~ bnd_c2_2 X81 X82 | ~ bnd_c3_2 X81 X82) |
% 7.13/6.62 ~ bnd_c5_2 X81 X82) |
% 7.13/6.62 bnd_ndr1_1 X81 & bnd_c6_2 X81 bnd_a83) |
% 7.13/6.62 ~ bnd_c3_1 X81) |
% 7.13/6.62 bnd_c3_0) |
% 7.13/6.62 bnd_c5_0)) &
% 7.13/6.62 (((ALL X83.
% 7.13/6.62 bnd_ndr1_0 -->
% 7.13/6.62 (((bnd_ndr1_1 X83 & bnd_c9_2 X83 bnd_a84) & bnd_c5_2 X83 bnd_a84) &
% 7.13/6.62 ~ bnd_c8_2 X83 bnd_a84 |
% 7.13/6.62 ((bnd_ndr1_1 X83 & bnd_c6_2 X83 bnd_a85) & bnd_c3_2 X83 bnd_a85) &
% 7.13/6.62 ~ bnd_c9_2 X83 bnd_a85) |
% 7.13/6.62 ((bnd_ndr1_1 X83 & ~ bnd_c10_2 X83 bnd_a86) &
% 7.13/6.62 ~ bnd_c2_2 X83 bnd_a86) &
% 7.13/6.62 ~ bnd_c8_2 X83 bnd_a86) |
% 7.13/6.62 bnd_c2_0) |
% 7.13/6.62 bnd_c3_0)) &
% 7.13/6.62 ((((((bnd_ndr1_0 &
% 7.13/6.62 bnd_ndr1_1 bnd_a87) &
% 7.13/6.62 ~ bnd_c6_2 bnd_a87 bnd_a88) &
% 7.13/6.62 ~ bnd_c9_2 bnd_a87 bnd_a88) &
% 7.13/6.62 (ALL X84.
% 7.13/6.62 bnd_ndr1_1 bnd_a87 -->
% 7.13/6.62 (~ bnd_c1_2 bnd_a87 X84 | bnd_c6_2 bnd_a87 X84) |
% 7.13/6.62 ~ bnd_c5_2 bnd_a87 X84)) &
% 7.13/6.62 ~ bnd_c1_1 bnd_a87 |
% 7.13/6.62 (ALL X85.
% 7.13/6.62 bnd_ndr1_0 -->
% 7.13/6.62 (((bnd_ndr1_1 X85 & ~ bnd_c9_2 X85 bnd_a89) & bnd_c10_2 X85 bnd_a89) &
% 7.13/6.62 bnd_c4_2 X85 bnd_a89 |
% 7.13/6.62 bnd_c4_1 X85) |
% 7.13/6.62 ~ bnd_c6_1 X85)) |
% 7.13/6.62 bnd_c4_0)) &
% 7.13/6.62 ((~ bnd_c8_0 |
% 7.13/6.62 ((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a90) & ~ bnd_c2_2 bnd_a90 bnd_a91) &
% 7.13/6.62 bnd_c4_2 bnd_a90 bnd_a91) &
% 7.13/6.62 bnd_c7_2 bnd_a90 bnd_a91) &
% 7.13/6.62 ~ bnd_c4_1 bnd_a90) |
% 7.13/6.62 (ALL X86.
% 7.13/6.62 bnd_ndr1_0 -->
% 7.13/6.62 (~ bnd_c8_1 X86 |
% 7.13/6.62 ((bnd_ndr1_1 X86 & bnd_c8_2 X86 bnd_a92) & bnd_c9_2 X86 bnd_a92) &
% 7.13/6.62 bnd_c10_2 X86 bnd_a92) |
% 7.13/6.62 (ALL X87.
% 7.13/6.62 bnd_ndr1_1 X86 -->
% 7.13/6.62 (~ bnd_c4_2 X86 X87 | ~ bnd_c6_2 X86 X87) | ~ bnd_c8_2 X86 X87)))) &
% 7.13/6.62 (((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a93) &
% 7.13/6.62 bnd_c4_2 bnd_a93 bnd_a94) &
% 7.13/6.62 ~ bnd_c7_2 bnd_a93 bnd_a94) &
% 7.13/6.62 ~ bnd_c2_2 bnd_a93 bnd_a94) &
% 7.13/6.62 ~ bnd_c8_1 bnd_a93) &
% 7.13/6.62 ~ bnd_c2_1 bnd_a93 |
% 7.13/6.62 bnd_c7_0) |
% 7.13/6.62 bnd_c1_0)) &
% 7.13/6.62 ((~ bnd_c4_0 |
% 7.13/6.62 ((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a95) &
% 7.13/6.62 bnd_c8_2 bnd_a95 bnd_a96) &
% 7.13/6.62 ~ bnd_c2_2 bnd_a95 bnd_a96) &
% 7.13/6.62 ~ bnd_c4_2 bnd_a95 bnd_a96) &
% 7.13/6.62 bnd_c4_1 bnd_a95) |
% 7.13/6.62 ~ bnd_c3_0)) &
% 7.13/6.62 ((((bnd_ndr1_0 &
% 7.13/6.62 (ALL X88.
% 7.13/6.62 bnd_ndr1_1 bnd_a97 --> bnd_c9_2 bnd_a97 X88 | ~ bnd_c6_2 bnd_a97 X88)) &
% 7.13/6.62 bnd_c8_1 bnd_a97) &
% 7.13/6.62 bnd_c5_1 bnd_a97 |
% 7.13/6.62 bnd_c8_0) |
% 7.13/6.62 (((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a98) &
% 7.13/6.62 bnd_c1_2 bnd_a98 bnd_a99) &
% 7.13/6.62 ~ bnd_c6_2 bnd_a98 bnd_a99) &
% 7.13/6.62 bnd_c9_2 bnd_a98 bnd_a99) &
% 7.13/6.62 ~ bnd_c8_1 bnd_a98) &
% 7.13/6.62 bnd_c2_1 bnd_a98)) &
% 7.13/6.62 ((bnd_c4_0 |
% 7.13/6.62 (((((bnd_ndr1_0 &
% 7.13/6.62 (ALL X89.
% 7.13/6.62 bnd_ndr1_1 bnd_a100 -->
% 7.13/6.62 (bnd_c2_2 bnd_a100 X89 | ~ bnd_c3_2 bnd_a100 X89) |
% 7.13/6.62 ~ bnd_c7_2 bnd_a100 X89)) &
% 7.13/6.62 bnd_c9_1 bnd_a100) &
% 7.13/6.62 bnd_ndr1_1 bnd_a100) &
% 7.13/6.62 ~ bnd_c6_2 bnd_a100 bnd_a101) &
% 7.13/6.62 ~ bnd_c5_2 bnd_a100 bnd_a101) &
% 7.13/6.62 bnd_c9_2 bnd_a100 bnd_a101) |
% 7.13/6.62 (((((bnd_ndr1_0 & bnd_c10_1 bnd_a102) &
% 7.13/6.62 bnd_ndr1_1 bnd_a102) &
% 7.13/6.62 ~ bnd_c2_2 bnd_a102 bnd_a103) &
% 7.13/6.62 ~ bnd_c4_2 bnd_a102 bnd_a103) &
% 7.13/6.62 ~ bnd_c6_2 bnd_a102 bnd_a103) &
% 7.13/6.62 bnd_c4_1 bnd_a102)) &
% 7.13/6.62 ((~ bnd_c6_0 |
% 7.13/6.62 (ALL X90.
% 7.13/6.62 bnd_ndr1_0 -->
% 7.13/6.62 ((ALL X91.
% 7.13/6.62 bnd_ndr1_1 X90 -->
% 7.13/6.62 (bnd_c3_2 X90 X91 | bnd_c10_2 X90 X91) | ~ bnd_c5_2 X90 X91) |
% 7.13/6.62 bnd_c9_1 X90) |
% 7.13/6.62 ~ bnd_c5_1 X90)) |
% 7.13/6.62 (ALL X92.
% 7.13/6.62 bnd_ndr1_0 -->
% 7.13/6.62 (~ bnd_c6_1 X92 |
% 7.13/6.62 ((bnd_ndr1_1 X92 &
% 7.13/6.62 ~ bnd_c4_2 X92 bnd_a104) &
% 7.13/6.62 ~ bnd_c1_2 X92 bnd_a104) &
% 7.13/6.62 bnd_c8_2 X92 bnd_a104) |
% 7.13/6.62 (ALL X93.
% 7.13/6.62 bnd_ndr1_1 X92 --> ~ bnd_c1_2 X92 X93 | bnd_c4_2 X92 X93)))) &
% 7.13/6.62 ((((((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a105) &
% 7.13/6.62 ~ bnd_c6_2 bnd_a105 bnd_a106) &
% 7.13/6.62 bnd_c4_2 bnd_a105 bnd_a106) &
% 7.13/6.62 ~ bnd_c2_2 bnd_a105 bnd_a106) &
% 7.13/6.62 bnd_ndr1_1 bnd_a105) &
% 7.13/6.62 ~ bnd_c9_2 bnd_a105 bnd_a107) &
% 7.13/6.62 bnd_c6_2 bnd_a105 bnd_a107) &
% 7.13/6.62 ~ bnd_c5_2 bnd_a105 bnd_a107) &
% 7.13/6.62 bnd_c7_1 bnd_a105 |
% 7.13/6.62 bnd_c2_0) |
% 7.13/6.62 (((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a108) &
% 7.13/6.62 ~ bnd_c7_2 bnd_a108 bnd_a109) &
% 7.13/6.62 bnd_c1_2 bnd_a108 bnd_a109) &
% 7.13/6.62 ~ bnd_c2_2 bnd_a108 bnd_a109) &
% 7.13/6.62 (ALL X94.
% 7.13/6.62 bnd_ndr1_1 bnd_a108 -->
% 7.13/6.62 ~ bnd_c2_2 bnd_a108 X94 | ~ bnd_c7_2 bnd_a108 X94)) &
% 7.13/6.62 bnd_ndr1_1 bnd_a108) &
% 7.13/6.62 bnd_c3_2 bnd_a108 bnd_a110) &
% 7.13/6.62 ~ bnd_c2_2 bnd_a108 bnd_a110)) &
% 7.13/6.62 ((~ bnd_c8_0 | ~ bnd_c5_0) |
% 7.13/6.62 (ALL X95.
% 7.13/6.62 bnd_ndr1_0 -->
% 7.13/6.62 (~ bnd_c8_1 X95 | bnd_c5_1 X95) |
% 7.13/6.62 bnd_c7_1 X95))) &
% 7.13/6.62 ((ALL X96.
% 7.13/6.62 bnd_ndr1_0 -->
% 7.13/6.62 ((ALL X97.
% 7.13/6.62 bnd_ndr1_1 X96 -->
% 7.13/6.62 (bnd_c9_2 X96 X97 | bnd_c6_2 X96 X97) | ~ bnd_c8_2 X96 X97) |
% 7.13/6.62 (ALL X98.
% 7.13/6.62 bnd_ndr1_1 X96 -->
% 7.13/6.62 (~ bnd_c3_2 X96 X98 | bnd_c8_2 X96 X98) | bnd_c7_2 X96 X98)) |
% 7.13/6.62 ~ bnd_c7_1 X96) |
% 7.13/6.62 ~ bnd_c4_0)) &
% 7.13/6.62 (((ALL X99.
% 7.13/6.62 bnd_ndr1_0 -->
% 7.13/6.62 (~ bnd_c3_1 X99 | bnd_c8_1 X99) |
% 7.13/6.62 (ALL X100.
% 7.13/6.62 bnd_ndr1_1 X99 -->
% 7.13/6.62 (~ bnd_c7_2 X99 X100 |
% 7.13/6.62 ~ bnd_c3_2 X99 X100) |
% 7.13/6.62 ~ bnd_c6_2 X99 X100)) |
% 7.13/6.63 bnd_c3_0) |
% 7.13/6.63 bnd_c1_0)) &
% 7.13/6.63 ((~ bnd_c1_0 |
% 7.13/6.63 (ALL X101.
% 7.13/6.63 bnd_ndr1_0 -->
% 7.13/6.63 ((bnd_ndr1_1 X101 &
% 7.13/6.63 bnd_c5_2 X101 bnd_a111) &
% 7.13/6.63 bnd_c4_2 X101 bnd_a111) &
% 7.13/6.63 ~ bnd_c3_2 X101 bnd_a111 |
% 7.13/6.63 (ALL X102.
% 7.13/6.63 bnd_ndr1_1 X101 -->
% 7.13/6.63 (bnd_c10_2 X101 X102 |
% 7.13/6.63 ~ bnd_c4_2 X101 X102) |
% 7.13/6.63 bnd_c8_2 X101 X102))) |
% 7.13/6.63 ((((bnd_ndr1_0 & bnd_c6_1 bnd_a112) &
% 7.13/6.63 ~ bnd_c3_1 bnd_a112) &
% 7.13/6.63 bnd_ndr1_1 bnd_a112) &
% 7.13/6.63 ~ bnd_c4_2 bnd_a112 bnd_a113) &
% 7.13/6.63 ~ bnd_c9_2 bnd_a112 bnd_a113)) &
% 7.13/6.63 ((~ bnd_c10_0 |
% 7.13/6.63 (((((bnd_ndr1_0 & ~ bnd_c1_1 bnd_a114) &
% 7.13/6.63 bnd_ndr1_1 bnd_a114) &
% 7.13/6.63 ~ bnd_c5_2 bnd_a114 bnd_a115) &
% 7.13/6.63 bnd_c2_2 bnd_a114 bnd_a115) &
% 7.13/6.63 ~ bnd_c4_2 bnd_a114 bnd_a115) &
% 7.13/6.63 (ALL X103.
% 7.13/6.63 bnd_ndr1_1 bnd_a114 -->
% 7.13/6.63 (bnd_c10_2 bnd_a114 X103 |
% 7.13/6.63 ~ bnd_c8_2 bnd_a114 X103) |
% 7.13/6.63 bnd_c1_2 bnd_a114 X103)) |
% 7.13/6.63 bnd_c2_0)) &
% 7.13/6.63 ((~ bnd_c9_0 | bnd_c8_0) |
% 7.13/6.63 (((bnd_ndr1_0 & bnd_ndr1_1 bnd_a116) &
% 7.13/6.63 ~ bnd_c10_2 bnd_a116 bnd_a117) &
% 7.13/6.63 bnd_c3_2 bnd_a116 bnd_a117) &
% 7.13/6.63 ~ bnd_c7_1 bnd_a116)) &
% 7.13/6.63 (((ALL X104.
% 7.13/6.63 bnd_ndr1_0 -->
% 7.13/6.63 (((bnd_ndr1_1 X104 &
% 7.13/6.63 ~ bnd_c2_2 X104 bnd_a118) &
% 7.13/6.63 ~ bnd_c9_2 X104 bnd_a118) &
% 7.13/6.63 bnd_c5_2 X104 bnd_a118 |
% 7.13/6.63 ~ bnd_c4_1 X104) |
% 7.13/6.63 ~ bnd_c2_1 X104) |
% 7.13/6.63 ((((bnd_ndr1_0 & ~ bnd_c6_1 bnd_a119) &
% 7.13/6.63 bnd_c10_1 bnd_a119) &
% 7.13/6.63 bnd_ndr1_1 bnd_a119) &
% 7.13/6.63 ~ bnd_c1_2 bnd_a119 bnd_a120) &
% 7.13/6.63 bnd_c5_2 bnd_a119 bnd_a120) |
% 7.13/6.63 bnd_c6_0)) &
% 7.13/6.63 ((((bnd_ndr1_0 & ~ bnd_c9_1 bnd_a121) &
% 7.13/6.63 ~ bnd_c6_1 bnd_a121) &
% 7.13/6.63 ~ bnd_c10_1 bnd_a121 |
% 7.13/6.63 bnd_c3_0) |
% 7.13/6.63 ((bnd_ndr1_0 & bnd_c9_1 bnd_a122) &
% 7.13/6.63 bnd_c4_1 bnd_a122) &
% 7.13/6.63 (ALL X105.
% 7.13/6.63 bnd_ndr1_1 bnd_a122 -->
% 7.13/6.63 (bnd_c10_2 bnd_a122 X105 |
% 7.13/6.63 bnd_c3_2 bnd_a122 X105) |
% 7.13/6.63 bnd_c1_2 bnd_a122 X105))) &
% 7.13/6.63 ((~ bnd_c4_0 | ~ bnd_c10_0) | ~ bnd_c2_0)) &
% 7.13/6.63 (((ALL X106.
% 7.13/6.63 bnd_ndr1_0 -->
% 7.13/6.63 ((ALL X107.
% 7.13/6.63 bnd_ndr1_1 X106 -->
% 7.13/6.63 (~ bnd_c2_2 X106 X107 | bnd_c4_2 X106 X107) |
% 7.13/6.63 bnd_c10_2 X106 X107) |
% 7.13/6.63 bnd_c7_1 X106) |
% 7.13/6.63 bnd_c5_1 X106) |
% 7.13/6.63 ~ bnd_c8_0) |
% 7.13/6.63 ~ bnd_c1_0)) &
% 7.13/6.63 ((((((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a123) &
% 7.13/6.63 bnd_c2_2 bnd_a123 bnd_a124) &
% 7.13/6.63 ~ bnd_c4_2 bnd_a123 bnd_a124) &
% 7.13/6.63 ~ bnd_c9_2 bnd_a123 bnd_a124) &
% 7.13/6.63 bnd_ndr1_1 bnd_a123) &
% 7.13/6.63 ~ bnd_c9_2 bnd_a123 bnd_a125) &
% 7.13/6.63 bnd_c3_2 bnd_a123 bnd_a125) &
% 7.13/6.63 ~ bnd_c4_2 bnd_a123 bnd_a125) &
% 7.13/6.63 ~ bnd_c9_1 bnd_a123 |
% 7.13/6.63 bnd_c10_0) |
% 7.13/6.63 (bnd_ndr1_0 & bnd_c4_1 bnd_a126) & bnd_c6_1 bnd_a126)) &
% 7.13/6.63 (((ALL X108.
% 7.13/6.63 bnd_ndr1_0 -->
% 7.13/6.63 (bnd_c7_1 X108 | bnd_c3_1 X108) | ~ bnd_c1_1 X108) |
% 7.13/6.63 bnd_c6_0) |
% 7.13/6.63 ~ bnd_c4_0)) &
% 7.13/6.63 ((((bnd_ndr1_0 & bnd_c4_1 bnd_a127) &
% 7.13/6.63 ~ bnd_c2_1 bnd_a127) &
% 7.13/6.63 (ALL X109.
% 7.13/6.63 bnd_ndr1_1 bnd_a127 -->
% 7.13/6.63 (~ bnd_c7_2 bnd_a127 X109 |
% 7.13/6.63 bnd_c10_2 bnd_a127 X109) |
% 7.13/6.63 ~ bnd_c4_2 bnd_a127 X109) |
% 7.13/6.63 ~ bnd_c1_0) |
% 7.13/6.63 bnd_c3_0)) &
% 7.13/6.63 ((((bnd_ndr1_0 &
% 7.13/6.63 (ALL X110.
% 7.13/6.63 bnd_ndr1_1 bnd_a128 -->
% 7.13/6.63 (~ bnd_c1_2 bnd_a128 X110 |
% 7.13/6.63 ~ bnd_c4_2 bnd_a128 X110) |
% 7.13/6.63 bnd_c6_2 bnd_a128 X110)) &
% 7.13/6.63 ~ bnd_c1_1 bnd_a128) &
% 7.13/6.63 ~ bnd_c4_1 bnd_a128 |
% 7.13/6.63 bnd_c5_0) |
% 7.13/6.63 ~ bnd_c9_0)) &
% 7.13/6.63 (((ALL X111.
% 7.13/6.63 bnd_ndr1_0 -->
% 7.13/6.63 ((ALL X112.
% 7.13/6.63 bnd_ndr1_1 X111 -->
% 7.13/6.63 (~ bnd_c9_2 X111 X112 | bnd_c1_2 X111 X112) |
% 7.13/6.63 bnd_c2_2 X111 X112) |
% 7.13/6.63 bnd_c4_1 X111) |
% 7.13/6.63 (ALL X113.
% 7.13/6.63 bnd_ndr1_1 X111 -->
% 7.13/6.63 (bnd_c8_2 X111 X113 | ~ bnd_c9_2 X111 X113) |
% 7.13/6.63 bnd_c7_2 X111 X113)) |
% 7.13/6.63 (ALL X114. bnd_ndr1_0 --> bnd_c1_1 X114 | bnd_c5_1 X114)) |
% 7.13/6.63 (ALL X115.
% 7.13/6.63 bnd_ndr1_0 -->
% 7.13/6.63 ((ALL X116.
% 7.13/6.63 bnd_ndr1_1 X115 -->
% 7.13/6.63 (bnd_c9_2 X115 X116 | bnd_c7_2 X115 X116) |
% 7.13/6.63 bnd_c4_2 X115 X116) |
% 7.13/6.63 ~ bnd_c9_1 X115) |
% 7.13/6.63 ((bnd_ndr1_1 X115 & ~ bnd_c5_2 X115 bnd_a129) &
% 7.13/6.63 bnd_c6_2 X115 bnd_a129) &
% 7.13/6.63 bnd_c1_2 X115 bnd_a129))) &
% 7.13/6.63 ((bnd_c9_0 |
% 7.13/6.63 (ALL X117.
% 7.13/6.63 bnd_ndr1_0 -->
% 7.13/6.63 (bnd_c5_1 X117 |
% 7.13/6.63 (bnd_ndr1_1 X117 & ~ bnd_c7_2 X117 bnd_a130) &
% 7.13/6.63 bnd_c1_2 X117 bnd_a130) |
% 7.13/6.63 (ALL X118.
% 7.13/6.63 bnd_ndr1_1 X117 -->
% 7.13/6.63 (bnd_c8_2 X117 X118 | bnd_c10_2 X117 X118) |
% 7.13/6.63 ~ bnd_c6_2 X117 X118))) |
% 7.13/6.63 bnd_c2_0)) &
% 7.13/6.63 (((ALL X119.
% 7.13/6.63 bnd_ndr1_0 -->
% 7.13/6.63 ((ALL X120.
% 7.13/6.63 bnd_ndr1_1 X119 -->
% 7.13/6.63 (~ bnd_c7_2 X119 X120 | bnd_c9_2 X119 X120) |
% 7.13/6.63 ~ bnd_c6_2 X119 X120) |
% 7.13/6.63 (ALL X121.
% 7.13/6.63 bnd_ndr1_1 X119 -->
% 7.13/6.63 (~ bnd_c6_2 X119 X121 | bnd_c9_2 X119 X121) |
% 7.13/6.63 bnd_c2_2 X119 X121)) |
% 7.13/6.63 ((bnd_ndr1_1 X119 & ~ bnd_c10_2 X119 bnd_a131) &
% 7.13/6.63 ~ bnd_c1_2 X119 bnd_a131) &
% 7.13/6.63 bnd_c2_2 X119 bnd_a131) |
% 7.13/6.63 (ALL X122.
% 7.13/6.63 bnd_ndr1_0 -->
% 7.13/6.63 ~ bnd_c3_1 X122 |
% 7.13/6.63 ((bnd_ndr1_1 X122 & ~ bnd_c4_2 X122 bnd_a132) &
% 7.13/6.63 ~ bnd_c8_2 X122 bnd_a132) &
% 7.13/6.63 bnd_c5_2 X122 bnd_a132)) |
% 7.13/6.63 (ALL X123.
% 7.13/6.63 bnd_ndr1_0 -->
% 7.13/6.63 (~ bnd_c6_1 X123 |
% 7.13/6.63 ((bnd_ndr1_1 X123 & ~ bnd_c4_2 X123 bnd_a133) &
% 7.13/6.63 bnd_c7_2 X123 bnd_a133) &
% 7.13/6.63 ~ bnd_c8_2 X123 bnd_a133) |
% 7.13/6.63 ~ bnd_c10_1 X123))) &
% 7.13/6.63 ((~ bnd_c1_0 | ~ bnd_c10_0) |
% 7.13/6.63 (((((bnd_ndr1_0 &
% 7.13/6.63 (ALL X124.
% 7.13/6.63 bnd_ndr1_1 bnd_a134 -->
% 7.13/6.63 (~ bnd_c7_2 bnd_a134 X124 |
% 7.13/6.63 ~ bnd_c2_2 bnd_a134 X124) |
% 7.13/6.63 ~ bnd_c5_2 bnd_a134 X124)) &
% 7.13/6.63 bnd_c10_1 bnd_a134) &
% 7.13/6.63 bnd_ndr1_1 bnd_a134) &
% 7.13/6.63 ~ bnd_c8_2 bnd_a134 bnd_a135) &
% 7.13/6.63 ~ bnd_c6_2 bnd_a134 bnd_a135) &
% 7.13/6.63 bnd_c3_2 bnd_a134 bnd_a135)) &
% 7.13/6.63 (((((((bnd_ndr1_0 & bnd_c7_1 bnd_a136) & bnd_ndr1_1 bnd_a136) &
% 7.13/6.63 bnd_c2_2 bnd_a136 bnd_a137) &
% 7.13/6.63 ~ bnd_c5_2 bnd_a136 bnd_a137) &
% 7.13/6.63 ~ bnd_c10_2 bnd_a136 bnd_a137) &
% 7.13/6.63 ~ bnd_c8_1 bnd_a136 |
% 7.13/6.63 ~ bnd_c8_0) |
% 7.13/6.63 ~ bnd_c2_0)) &
% 7.13/6.63 ((bnd_c10_0 |
% 7.13/6.63 (ALL X125.
% 7.13/6.63 bnd_ndr1_0 -->
% 7.13/6.63 (~ bnd_c4_1 X125 | bnd_c5_1 X125) |
% 7.13/6.63 ((bnd_ndr1_1 X125 & ~ bnd_c6_2 X125 bnd_a138) &
% 7.13/6.63 bnd_c4_2 X125 bnd_a138) &
% 7.13/6.63 ~ bnd_c1_2 X125 bnd_a138)) |
% 7.13/6.63 (((((((bnd_ndr1_0 & ~ bnd_c2_1 bnd_a139) & bnd_ndr1_1 bnd_a139) &
% 7.13/6.63 bnd_c9_2 bnd_a139 bnd_a140) &
% 7.13/6.63 ~ bnd_c3_2 bnd_a139 bnd_a140) &
% 7.13/6.63 ~ bnd_c8_2 bnd_a139 bnd_a140) &
% 7.13/6.63 bnd_ndr1_1 bnd_a139) &
% 7.13/6.63 bnd_c1_2 bnd_a139 bnd_a141) &
% 7.13/6.63 ~ bnd_c9_2 bnd_a139 bnd_a141)) &
% 7.13/6.63 (((ALL X126. bnd_ndr1_0 --> bnd_c3_1 X126 | ~ bnd_c4_1 X126) |
% 7.13/6.63 (ALL X127.
% 7.13/6.63 bnd_ndr1_0 -->
% 7.13/6.63 (bnd_c1_1 X127 | ~ bnd_c3_1 X127) |
% 7.13/6.63 ((bnd_ndr1_1 X127 & bnd_c7_2 X127 bnd_a142) &
% 7.13/6.63 ~ bnd_c6_2 X127 bnd_a142) &
% 7.13/6.63 ~ bnd_c9_2 X127 bnd_a142)) |
% 7.13/6.63 bnd_c8_0)) &
% 7.13/6.63 ((bnd_c10_0 | bnd_c4_0) |
% 7.13/6.63 ((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a143) &
% 7.13/6.63 bnd_c9_2 bnd_a143 bnd_a144) &
% 7.13/6.63 ~ bnd_c5_2 bnd_a143 bnd_a144) &
% 7.13/6.63 ~ bnd_c10_2 bnd_a143 bnd_a144) &
% 7.13/6.63 bnd_c1_1 bnd_a143)) &
% 7.13/6.63 ((bnd_c9_0 |
% 7.13/6.63 (ALL X128.
% 7.13/6.63 bnd_ndr1_0 -->
% 7.13/6.63 ((ALL X129.
% 7.13/6.63 bnd_ndr1_1 X128 -->
% 7.13/6.63 (bnd_c2_2 X128 X129 | ~ bnd_c8_2 X128 X129) |
% 7.13/6.63 bnd_c7_2 X128 X129) |
% 7.13/6.63 ~ bnd_c8_1 X128) |
% 7.13/6.63 ~ bnd_c4_1 X128)) |
% 7.13/6.63 ~ bnd_c6_0)) &
% 7.13/6.63 ((~ bnd_c2_0 | bnd_c1_0) | bnd_c3_0)) &
% 7.13/6.63 (((ALL X130.
% 7.13/6.63 bnd_ndr1_0 -->
% 7.13/6.63 (ALL X131.
% 7.13/6.63 bnd_ndr1_1 X130 -->
% 7.13/6.63 (bnd_c7_2 X130 X131 | ~ bnd_c6_2 X130 X131) |
% 7.13/6.63 bnd_c8_2 X130 X131) |
% 7.13/6.63 bnd_c7_1 X130) |
% 7.13/6.63 (ALL X132.
% 7.13/6.63 bnd_ndr1_0 -->
% 7.13/6.63 (ALL X133.
% 7.13/6.63 bnd_ndr1_1 X132 -->
% 7.13/6.63 (bnd_c8_2 X132 X133 | bnd_c7_2 X132 X133) |
% 7.13/6.63 ~ bnd_c3_2 X132 X133) |
% 7.13/6.63 bnd_c2_1 X132)) |
% 7.13/6.63 bnd_c2_0)) &
% 7.13/6.63 (((ALL X134. bnd_ndr1_0 --> bnd_c6_1 X134 | bnd_c7_1 X134) |
% 7.13/6.63 (ALL X135.
% 7.13/6.63 bnd_ndr1_0 -->
% 7.13/6.63 (bnd_c9_1 X135 |
% 7.13/6.63 ((bnd_ndr1_1 X135 & bnd_c3_2 X135 bnd_a145) &
% 7.13/6.63 bnd_c1_2 X135 bnd_a145) &
% 7.13/6.63 ~ bnd_c5_2 X135 bnd_a145) |
% 7.13/6.63 ~ bnd_c1_1 X135)) |
% 7.13/6.63 (ALL X136.
% 7.13/6.63 bnd_ndr1_0 -->
% 7.13/6.63 (((bnd_ndr1_1 X136 & ~ bnd_c9_2 X136 bnd_a146) &
% 7.13/6.63 ~ bnd_c1_2 X136 bnd_a146) &
% 7.13/6.63 bnd_c7_2 X136 bnd_a146 |
% 7.13/6.63 ~ bnd_c7_1 X136) |
% 7.13/6.63 ~ bnd_c10_1 X136))) &
% 7.13/6.63 (((ALL X137.
% 7.13/6.63 bnd_ndr1_0 -->
% 7.13/6.63 (bnd_c5_1 X137 |
% 7.13/6.63 (ALL X138.
% 7.13/6.63 bnd_ndr1_1 X137 -->
% 7.13/6.63 (bnd_c8_2 X137 X138 | bnd_c6_2 X137 X138) |
% 7.13/6.63 ~ bnd_c2_2 X137 X138)) |
% 7.13/6.63 ~ bnd_c1_1 X137) |
% 7.13/6.63 (ALL X139.
% 7.13/6.63 bnd_ndr1_0 -->
% 7.13/6.63 ((ALL X140.
% 7.13/6.63 bnd_ndr1_1 X139 -->
% 7.13/6.63 (~ bnd_c1_2 X139 X140 | ~ bnd_c2_2 X139 X140) |
% 7.13/6.63 ~ bnd_c7_2 X139 X140) |
% 7.13/6.63 (ALL X141.
% 7.13/6.63 bnd_ndr1_1 X139 -->
% 7.13/6.63 (~ bnd_c7_2 X139 X141 | bnd_c10_2 X139 X141) |
% 7.13/6.63 bnd_c2_2 X139 X141)) |
% 7.13/6.63 bnd_c3_1 X139)) |
% 7.13/6.63 bnd_c5_0))
% 15.14/14.62 Unfolded term: ~ (((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((bnd_ndr1_0 &
% 15.14/14.62 bnd_ndr1_1 bnd_a1) &
% 15.14/14.62 ~ bnd_c3_2 bnd_a1 bnd_a2) &
% 15.14/14.62 ~ bnd_c5_2 bnd_a1 bnd_a2) &
% 15.14/14.62 bnd_c6_2 bnd_a1 bnd_a2) &
% 15.14/14.62 bnd_c9_1 bnd_a1) &
% 15.14/14.62 bnd_c6_1 bnd_a1 |
% 15.14/14.62 ((((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a3) &
% 15.14/14.62 ~ bnd_c3_2 bnd_a3 bnd_a4) &
% 15.14/14.62 bnd_c1_2 bnd_a3 bnd_a4) &
% 15.14/14.62 bnd_c5_2 bnd_a3 bnd_a4) &
% 15.14/14.62 ~ bnd_c1_1 bnd_a3) &
% 15.14/14.62 bnd_ndr1_1 bnd_a3) &
% 15.14/14.62 ~ bnd_c1_2 bnd_a3 bnd_a5) &
% 15.14/14.62 bnd_c7_2 bnd_a3 bnd_a5) &
% 15.14/14.62 ~ bnd_c3_2 bnd_a3 bnd_a5) |
% 15.14/14.62 (ALL U. bnd_ndr1_0 --> bnd_c6_1 U | ~ bnd_c7_1 U)) &
% 15.14/14.62 (((bnd_ndr1_0 & bnd_c10_1 bnd_a6) & ~ bnd_c6_1 bnd_a6) &
% 15.14/14.62 ~ bnd_c4_1 bnd_a6 |
% 15.14/14.62 (((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a7) &
% 15.14/14.62 ~ bnd_c1_2 bnd_a7 bnd_a8) &
% 15.14/14.62 ~ bnd_c9_2 bnd_a7 bnd_a8) &
% 15.14/14.62 bnd_c2_2 bnd_a7 bnd_a8) &
% 15.14/14.62 bnd_c10_1 bnd_a7) &
% 15.14/14.62 bnd_c8_1 bnd_a7)) &
% 15.14/14.62 ((~ bnd_c7_0 |
% 15.14/14.62 (ALL V.
% 15.14/14.62 bnd_ndr1_0 -->
% 15.14/14.62 (~ bnd_c3_1 V | bnd_c6_1 V) |
% 15.14/14.62 (ALL W.
% 15.14/14.62 bnd_ndr1_1 V -->
% 15.14/14.62 (~ bnd_c6_2 V W | bnd_c1_2 V W) | ~ bnd_c8_2 V W))) |
% 15.14/14.62 ~ bnd_c10_0)) &
% 15.14/14.62 (((ALL X.
% 15.14/14.62 bnd_ndr1_0 -->
% 15.14/14.62 (bnd_c10_1 X | ~ bnd_c7_1 X) |
% 15.14/14.62 (ALL Y.
% 15.14/14.62 bnd_ndr1_1 X -->
% 15.14/14.62 (bnd_c3_2 X Y | ~ bnd_c10_2 X Y) | ~ bnd_c1_2 X Y)) |
% 15.14/14.62 (((((bnd_ndr1_0 & ~ bnd_c8_1 bnd_a9) &
% 15.14/14.62 (ALL Z.
% 15.14/14.62 bnd_ndr1_1 bnd_a9 -->
% 15.14/14.62 bnd_c4_2 bnd_a9 Z | bnd_c5_2 bnd_a9 Z)) &
% 15.14/14.62 bnd_ndr1_1 bnd_a9) &
% 15.14/14.62 ~ bnd_c3_2 bnd_a9 bnd_a10) &
% 15.14/14.62 ~ bnd_c6_2 bnd_a9 bnd_a10) &
% 15.14/14.62 bnd_c2_2 bnd_a9 bnd_a10) |
% 15.14/14.62 (ALL X1.
% 15.14/14.62 bnd_ndr1_0 -->
% 15.14/14.62 (((bnd_ndr1_1 X1 & bnd_c1_2 X1 bnd_a11) &
% 15.14/14.62 ~ bnd_c9_2 X1 bnd_a11) &
% 15.14/14.62 bnd_c2_2 X1 bnd_a11 |
% 15.14/14.62 ~ bnd_c3_1 X1) |
% 15.14/14.62 (ALL X2.
% 15.14/14.62 bnd_ndr1_1 X1 -->
% 15.14/14.62 (bnd_c4_2 X1 X2 | ~ bnd_c8_2 X1 X2) |
% 15.14/14.62 ~ bnd_c1_2 X1 X2)))) &
% 15.14/14.62 ((((((bnd_ndr1_0 & ~ bnd_c3_1 bnd_a12) & bnd_ndr1_1 bnd_a12) &
% 15.14/14.62 bnd_c6_2 bnd_a12 bnd_a13) &
% 15.14/14.62 bnd_c4_2 bnd_a12 bnd_a13) &
% 15.14/14.62 ~ bnd_c9_2 bnd_a12 bnd_a13 |
% 15.14/14.62 bnd_c8_0) |
% 15.14/14.62 (ALL X3.
% 15.14/14.62 bnd_ndr1_0 -->
% 15.14/14.62 ((ALL X4.
% 15.14/14.62 bnd_ndr1_1 X3 -->
% 15.14/14.62 (~ bnd_c2_2 X3 X4 | bnd_c1_2 X3 X4) | ~ bnd_c7_2 X3 X4) |
% 15.14/14.62 ~ bnd_c6_1 X3) |
% 15.14/14.62 ((bnd_ndr1_1 X3 & bnd_c2_2 X3 bnd_a14) & bnd_c10_2 X3 bnd_a14) &
% 15.14/14.62 ~ bnd_c7_2 X3 bnd_a14))) &
% 15.14/14.62 ((~ bnd_c3_0 | bnd_c1_0) | ~ bnd_c2_0)) &
% 15.14/14.62 ((~ bnd_c2_0 | ~ bnd_c3_0) | bnd_c4_0)) &
% 15.14/14.62 ((bnd_c8_0 |
% 15.14/14.62 (ALL X5.
% 15.14/14.62 bnd_ndr1_0 -->
% 15.14/14.62 (bnd_c3_1 X5 |
% 15.14/14.62 (ALL X6.
% 15.14/14.62 bnd_ndr1_1 X5 -->
% 15.14/14.62 (bnd_c7_2 X5 X6 | ~ bnd_c10_2 X5 X6) | bnd_c6_2 X5 X6)) |
% 15.14/14.62 ~ bnd_c10_1 X5)) |
% 15.14/14.62 ((bnd_ndr1_0 &
% 15.14/14.62 (ALL X7.
% 15.14/14.62 bnd_ndr1_1 bnd_a15 -->
% 15.14/14.62 (~ bnd_c2_2 bnd_a15 X7 | bnd_c5_2 bnd_a15 X7) |
% 15.14/14.62 ~ bnd_c4_2 bnd_a15 X7)) &
% 15.14/14.62 bnd_c3_1 bnd_a15) &
% 15.14/14.62 (ALL X8.
% 15.14/14.62 bnd_ndr1_1 bnd_a15 -->
% 15.14/14.62 (~ bnd_c9_2 bnd_a15 X8 | ~ bnd_c4_2 bnd_a15 X8) |
% 15.14/14.62 ~ bnd_c6_2 bnd_a15 X8))) &
% 15.14/14.62 ((~ bnd_c1_0 |
% 15.14/14.62 (((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a16) & ~ bnd_c8_2 bnd_a16 bnd_a17) &
% 15.14/14.62 ~ bnd_c2_2 bnd_a16 bnd_a17) &
% 15.14/14.62 bnd_c9_2 bnd_a16 bnd_a17) &
% 15.14/14.62 (ALL X9.
% 15.14/14.62 bnd_ndr1_1 bnd_a16 -->
% 15.14/14.62 (~ bnd_c4_2 bnd_a16 X9 | ~ bnd_c7_2 bnd_a16 X9) |
% 15.14/14.62 ~ bnd_c10_2 bnd_a16 X9)) &
% 15.14/14.62 ~ bnd_c3_1 bnd_a16) |
% 15.14/14.62 ((bnd_ndr1_0 & bnd_c6_1 bnd_a18) &
% 15.14/14.62 (ALL X10.
% 15.14/14.62 bnd_ndr1_1 bnd_a18 -->
% 15.14/14.62 (bnd_c8_2 bnd_a18 X10 | bnd_c4_2 bnd_a18 X10) |
% 15.14/14.62 bnd_c7_2 bnd_a18 X10)) &
% 15.14/14.62 bnd_c3_1 bnd_a18)) &
% 15.14/14.62 (((ALL X11. bnd_ndr1_0 --> ~ bnd_c6_1 X11) |
% 15.14/14.62 (((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a19) & bnd_c2_2 bnd_a19 bnd_a20) &
% 15.14/14.62 bnd_c9_2 bnd_a19 bnd_a20) &
% 15.14/14.62 ~ bnd_c4_2 bnd_a19 bnd_a20) &
% 15.14/14.62 bnd_ndr1_1 bnd_a19) &
% 15.14/14.62 bnd_c2_2 bnd_a19 bnd_a21) &
% 15.14/14.62 ~ bnd_c8_2 bnd_a19 bnd_a21) &
% 15.14/14.62 bnd_c7_1 bnd_a19) |
% 15.14/14.62 ((((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a22) & bnd_c2_2 bnd_a22 bnd_a23) &
% 15.14/14.62 bnd_c7_2 bnd_a22 bnd_a23) &
% 15.14/14.62 bnd_c10_2 bnd_a22 bnd_a23) &
% 15.14/14.62 bnd_ndr1_1 bnd_a22) &
% 15.14/14.62 ~ bnd_c6_2 bnd_a22 bnd_a24) &
% 15.14/14.62 ~ bnd_c1_2 bnd_a22 bnd_a24) &
% 15.14/14.62 ~ bnd_c2_2 bnd_a22 bnd_a24) &
% 15.14/14.62 bnd_c8_1 bnd_a22)) &
% 15.14/14.62 (~ bnd_c4_0 |
% 15.14/14.62 (ALL X12.
% 15.14/14.62 bnd_ndr1_0 -->
% 15.14/14.62 ((bnd_ndr1_1 X12 & bnd_c8_2 X12 bnd_a25) & bnd_c5_2 X12 bnd_a25) &
% 15.14/14.62 bnd_c3_2 X12 bnd_a25 |
% 15.14/14.62 ~ bnd_c3_1 X12))) &
% 15.14/14.62 ((bnd_c10_0 | ~ bnd_c9_0) |
% 15.14/14.62 (((((bnd_ndr1_0 & bnd_c8_1 bnd_a26) & bnd_ndr1_1 bnd_a26) &
% 15.14/14.62 bnd_c9_2 bnd_a26 bnd_a27) &
% 15.14/14.62 bnd_c6_2 bnd_a26 bnd_a27) &
% 15.14/14.62 ~ bnd_c5_2 bnd_a26 bnd_a27) &
% 15.14/14.62 (ALL X13.
% 15.14/14.62 bnd_ndr1_1 bnd_a26 -->
% 15.14/14.62 (~ bnd_c7_2 bnd_a26 X13 | bnd_c8_2 bnd_a26 X13) |
% 15.14/14.62 ~ bnd_c4_2 bnd_a26 X13))) &
% 15.14/14.62 ((bnd_c10_0 |
% 15.14/14.62 (ALL X14.
% 15.14/14.62 bnd_ndr1_0 -->
% 15.14/14.62 ((ALL X15.
% 15.14/14.62 bnd_ndr1_1 X14 -->
% 15.14/14.62 (~ bnd_c1_2 X14 X15 | bnd_c10_2 X14 X15) | ~ bnd_c9_2 X14 X15) |
% 15.14/14.62 (ALL X16.
% 15.14/14.62 bnd_ndr1_1 X14 -->
% 15.14/14.62 (bnd_c9_2 X14 X16 | bnd_c3_2 X14 X16) | bnd_c1_2 X14 X16)) |
% 15.14/14.62 (ALL X17.
% 15.14/14.62 bnd_ndr1_1 X14 -->
% 15.14/14.62 (bnd_c9_2 X14 X17 | ~ bnd_c1_2 X14 X17) | ~ bnd_c10_2 X14 X17))) |
% 15.14/14.62 bnd_c6_0)) &
% 15.14/14.62 ((~ bnd_c4_0 |
% 15.14/14.62 ((bnd_ndr1_0 &
% 15.14/14.62 (ALL X18.
% 15.14/14.62 bnd_ndr1_1 bnd_a28 -->
% 15.14/14.62 (bnd_c7_2 bnd_a28 X18 | bnd_c3_2 bnd_a28 X18) |
% 15.14/14.62 ~ bnd_c6_2 bnd_a28 X18)) &
% 15.14/14.62 ~ bnd_c10_1 bnd_a28) &
% 15.14/14.62 (ALL X19.
% 15.14/14.62 bnd_ndr1_1 bnd_a28 -->
% 15.14/14.62 (~ bnd_c1_2 bnd_a28 X19 | ~ bnd_c8_2 bnd_a28 X19) |
% 15.14/14.62 bnd_c5_2 bnd_a28 X19)) |
% 15.14/14.62 ~ bnd_c8_0)) &
% 15.14/14.62 ((bnd_c10_0 | ~ bnd_c7_0) | bnd_c8_0)) &
% 15.14/14.62 ((~ bnd_c6_0 | bnd_c7_0) | ~ bnd_c2_0)) &
% 15.14/14.62 ((bnd_c10_0 | bnd_c8_0) |
% 15.14/14.62 (ALL X20.
% 15.14/14.62 bnd_ndr1_0 -->
% 15.14/14.62 (bnd_c8_1 X20 | ~ bnd_c6_1 X20) |
% 15.14/14.62 (ALL X21. bnd_ndr1_1 X20 --> ~ bnd_c4_2 X20 X21 | ~ bnd_c7_2 X20 X21)))) &
% 15.14/14.62 ((~ bnd_c10_0 | ~ bnd_c5_0) |
% 15.14/14.62 (((((bnd_ndr1_0 & ~ bnd_c7_1 bnd_a29) &
% 15.14/14.62 bnd_c9_1 bnd_a29) &
% 15.14/14.62 bnd_ndr1_1 bnd_a29) &
% 15.14/14.62 bnd_c8_2 bnd_a29 bnd_a30) &
% 15.14/14.62 ~ bnd_c5_2 bnd_a29 bnd_a30) &
% 15.14/14.62 ~ bnd_c4_2 bnd_a29 bnd_a30)) &
% 15.14/14.62 (bnd_c5_0 | bnd_c10_0)) &
% 15.14/14.62 (((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a31) &
% 15.14/14.62 ~ bnd_c7_2 bnd_a31 bnd_a32) &
% 15.14/14.62 bnd_c3_2 bnd_a31 bnd_a32) &
% 15.14/14.62 bnd_c8_2 bnd_a31 bnd_a32) &
% 15.14/14.62 ~ bnd_c5_1 bnd_a31) &
% 15.14/14.62 (ALL X22.
% 15.14/14.62 bnd_ndr1_1 bnd_a31 -->
% 15.14/14.62 (~ bnd_c2_2 bnd_a31 X22 |
% 15.14/14.62 bnd_c1_2 bnd_a31 X22) |
% 15.14/14.62 bnd_c6_2 bnd_a31 X22) |
% 15.14/14.62 (((((bnd_ndr1_0 & bnd_c3_1 bnd_a33) &
% 15.14/14.62 bnd_ndr1_1 bnd_a33) &
% 15.14/14.62 ~ bnd_c6_2 bnd_a33 bnd_a34) &
% 15.14/14.62 bnd_c10_2 bnd_a33 bnd_a34) &
% 15.14/14.62 ~ bnd_c5_2 bnd_a33 bnd_a34) &
% 15.14/14.62 bnd_c6_1 bnd_a33) |
% 15.14/14.62 (((((bnd_ndr1_0 & ~ bnd_c8_1 bnd_a35) &
% 15.14/14.62 bnd_c2_1 bnd_a35) &
% 15.14/14.62 bnd_ndr1_1 bnd_a35) &
% 15.14/14.62 ~ bnd_c4_2 bnd_a35 bnd_a36) &
% 15.14/14.62 bnd_c7_2 bnd_a35 bnd_a36) &
% 15.14/14.62 bnd_c8_2 bnd_a35 bnd_a36)) &
% 15.14/14.62 (((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a37) &
% 15.14/14.62 bnd_c4_2 bnd_a37 bnd_a38) &
% 15.14/14.62 bnd_c6_2 bnd_a37 bnd_a38) &
% 15.14/14.62 ~ bnd_c3_2 bnd_a37 bnd_a38) &
% 15.14/14.62 (ALL X23.
% 15.14/14.62 bnd_ndr1_1 bnd_a37 -->
% 15.14/14.62 ~ bnd_c7_2 bnd_a37 X23 |
% 15.14/14.62 bnd_c10_2 bnd_a37 X23)) &
% 15.14/14.62 ~ bnd_c5_1 bnd_a37 |
% 15.14/14.62 (ALL X24.
% 15.14/14.62 bnd_ndr1_0 -->
% 15.14/14.62 ((ALL X25.
% 15.14/14.62 bnd_ndr1_1 X24 -->
% 15.14/14.62 (~ bnd_c2_2 X24 X25 | bnd_c10_2 X24 X25) | ~ bnd_c5_2 X24 X25) |
% 15.14/14.62 ((bnd_ndr1_1 X24 &
% 15.14/14.62 bnd_c2_2 X24 bnd_a39) &
% 15.14/14.62 ~ bnd_c9_2 X24 bnd_a39) &
% 15.14/14.62 ~ bnd_c3_2 X24 bnd_a39) |
% 15.14/14.62 (ALL X26.
% 15.14/14.62 bnd_ndr1_1 X24 -->
% 15.14/14.62 (~ bnd_c4_2 X24 X26 | bnd_c5_2 X24 X26) | bnd_c3_2 X24 X26))) |
% 15.14/14.62 (ALL X27.
% 15.14/14.62 bnd_ndr1_0 -->
% 15.14/14.62 (((bnd_ndr1_1 X27 &
% 15.14/14.62 ~ bnd_c3_2 X27 bnd_a40) &
% 15.14/14.62 ~ bnd_c4_2 X27 bnd_a40) &
% 15.14/14.62 bnd_c9_2 X27 bnd_a40 |
% 15.14/14.62 (ALL X28.
% 15.14/14.62 bnd_ndr1_1 X27 -->
% 15.14/14.62 (~ bnd_c8_2 X27 X28 | ~ bnd_c6_2 X27 X28) | ~ bnd_c3_2 X27 X28)) |
% 15.14/14.62 (ALL X29.
% 15.14/14.62 bnd_ndr1_1 X27 -->
% 15.14/14.62 (~ bnd_c9_2 X27 X29 | ~ bnd_c2_2 X27 X29) | bnd_c7_2 X27 X29)))) &
% 15.14/14.62 ((bnd_c9_0 |
% 15.14/14.62 (bnd_ndr1_0 &
% 15.14/14.62 (ALL X30.
% 15.14/14.62 bnd_ndr1_1 bnd_a41 -->
% 15.14/14.62 (bnd_c8_2 bnd_a41 X30 |
% 15.14/14.62 bnd_c3_2 bnd_a41 X30) |
% 15.14/14.62 bnd_c6_2 bnd_a41 X30)) &
% 15.14/14.62 ~ bnd_c10_1 bnd_a41) |
% 15.14/14.62 (ALL X31.
% 15.14/14.62 bnd_ndr1_0 -->
% 15.14/14.62 (((bnd_ndr1_1 X31 & bnd_c5_2 X31 bnd_a42) &
% 15.14/14.62 bnd_c4_2 X31 bnd_a42) &
% 15.14/14.62 ~ bnd_c10_2 X31 bnd_a42 |
% 15.14/14.62 (ALL X32.
% 15.14/14.62 bnd_ndr1_1 X31 -->
% 15.14/14.62 (bnd_c2_2 X31 X32 | ~ bnd_c7_2 X31 X32) | bnd_c3_2 X31 X32)) |
% 15.14/14.62 (ALL X33.
% 15.14/14.62 bnd_ndr1_1 X31 -->
% 15.14/14.62 ~ bnd_c9_2 X31 X33 |
% 15.14/14.62 ~ bnd_c8_2 X31 X33)))) &
% 15.14/14.62 ((~ bnd_c5_0 |
% 15.14/14.62 (ALL X34.
% 15.14/14.62 bnd_ndr1_0 -->
% 15.14/14.62 (((bnd_ndr1_1 X34 & bnd_c1_2 X34 bnd_a43) &
% 15.14/14.62 ~ bnd_c8_2 X34 bnd_a43) &
% 15.14/14.62 bnd_c10_2 X34 bnd_a43 |
% 15.14/14.62 (ALL X35.
% 15.14/14.62 bnd_ndr1_1 X34 -->
% 15.14/14.62 (~ bnd_c3_2 X34 X35 | bnd_c4_2 X34 X35) | bnd_c2_2 X34 X35)) |
% 15.14/14.62 (ALL X36.
% 15.14/14.62 bnd_ndr1_1 X34 -->
% 15.14/14.62 (~ bnd_c4_2 X34 X36 |
% 15.14/14.62 ~ bnd_c9_2 X34 X36) |
% 15.14/14.62 ~ bnd_c3_2 X34 X36))) |
% 15.14/14.62 bnd_c3_0)) &
% 15.14/14.62 ((~ bnd_c10_0 |
% 15.14/14.62 ((bnd_ndr1_0 &
% 15.14/14.62 (ALL X37.
% 15.14/14.62 bnd_ndr1_1 bnd_a44 -->
% 15.14/14.62 (~ bnd_c5_2 bnd_a44 X37 |
% 15.14/14.62 bnd_c4_2 bnd_a44 X37) |
% 15.14/14.62 bnd_c3_2 bnd_a44 X37)) &
% 15.14/14.62 bnd_c4_1 bnd_a44) &
% 15.14/14.62 bnd_c3_1 bnd_a44) |
% 15.14/14.62 ~ bnd_c1_0)) &
% 15.14/14.62 (((ALL X38.
% 15.14/14.62 bnd_ndr1_0 -->
% 15.14/14.62 ~ bnd_c8_1 X38 | bnd_c1_1 X38) |
% 15.14/14.62 (((((((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a45) &
% 15.14/14.62 ~ bnd_c10_2 bnd_a45 bnd_a46) &
% 15.14/14.62 ~ bnd_c8_2 bnd_a45 bnd_a46) &
% 15.14/14.62 ~ bnd_c4_2 bnd_a45 bnd_a46) &
% 15.14/14.62 bnd_ndr1_1 bnd_a45) &
% 15.14/14.62 bnd_c3_2 bnd_a45 bnd_a47) &
% 15.14/14.62 ~ bnd_c4_2 bnd_a45 bnd_a47) &
% 15.14/14.62 ~ bnd_c1_2 bnd_a45 bnd_a47) &
% 15.14/14.62 bnd_ndr1_1 bnd_a45) &
% 15.14/14.62 bnd_c7_2 bnd_a45 bnd_a48) &
% 15.14/14.62 ~ bnd_c2_2 bnd_a45 bnd_a48) &
% 15.14/14.62 bnd_c9_2 bnd_a45 bnd_a48) |
% 15.14/14.62 (ALL X39.
% 15.14/14.62 bnd_ndr1_0 -->
% 15.14/14.62 (bnd_c1_1 X39 |
% 15.14/14.62 ((bnd_ndr1_1 X39 & bnd_c5_2 X39 bnd_a49) &
% 15.14/14.62 ~ bnd_c3_2 X39 bnd_a49) &
% 15.14/14.62 bnd_c7_2 X39 bnd_a49) |
% 15.14/14.62 ((bnd_ndr1_1 X39 & bnd_c1_2 X39 bnd_a50) &
% 15.14/14.62 bnd_c8_2 X39 bnd_a50) &
% 15.14/14.62 bnd_c10_2 X39 bnd_a50))) &
% 15.14/14.62 (((ALL X40.
% 15.14/14.62 bnd_ndr1_0 -->
% 15.14/14.62 bnd_c10_1 X40 | ~ bnd_c4_1 X40) |
% 15.14/14.62 (ALL X41.
% 15.14/14.62 bnd_ndr1_0 -->
% 15.14/14.62 (bnd_c3_1 X41 | ~ bnd_c8_1 X41) |
% 15.14/14.62 ~ bnd_c2_1 X41)) |
% 15.14/14.62 bnd_c2_0)) &
% 15.14/14.62 ((ALL X42.
% 15.14/14.62 bnd_ndr1_0 -->
% 15.14/14.62 (ALL X43.
% 15.14/14.62 bnd_ndr1_1 X42 -->
% 15.14/14.62 (bnd_c6_2 X42 X43 | ~ bnd_c7_2 X42 X43) |
% 15.14/14.62 bnd_c1_2 X42 X43) |
% 15.14/14.62 bnd_c10_1 X42) |
% 15.14/14.62 bnd_c8_0)) &
% 15.14/14.62 ((~ bnd_c7_0 | ~ bnd_c9_0) | bnd_c4_0)) &
% 15.14/14.62 ((~ bnd_c6_0 |
% 15.14/14.62 ((bnd_ndr1_0 &
% 15.14/14.62 (ALL X44.
% 15.14/14.62 bnd_ndr1_1 bnd_a51 -->
% 15.14/14.62 (~ bnd_c9_2 bnd_a51 X44 |
% 15.14/14.62 ~ bnd_c1_2 bnd_a51 X44) |
% 15.14/14.62 ~ bnd_c4_2 bnd_a51 X44)) &
% 15.14/14.62 bnd_c6_1 bnd_a51) &
% 15.14/14.62 bnd_c2_1 bnd_a51) |
% 15.14/14.62 bnd_c4_0)) &
% 15.14/14.62 ((~ bnd_c10_0 | bnd_c3_0) |
% 15.14/14.62 (ALL X45.
% 15.14/14.62 bnd_ndr1_0 -->
% 15.14/14.62 ((ALL X46.
% 15.14/14.62 bnd_ndr1_1 X45 -->
% 15.14/14.62 bnd_c10_2 X45 X46 | ~ bnd_c7_2 X45 X46) |
% 15.14/14.62 bnd_c10_1 X45) |
% 15.14/14.62 ((bnd_ndr1_1 X45 & bnd_c8_2 X45 bnd_a52) &
% 15.14/14.62 ~ bnd_c9_2 X45 bnd_a52) &
% 15.14/14.62 bnd_c3_2 X45 bnd_a52))) &
% 15.14/14.62 ((~ bnd_c1_0 | ~ bnd_c5_0) |
% 15.14/14.62 ((((bnd_ndr1_0 &
% 15.14/14.62 (ALL X47.
% 15.14/14.62 bnd_ndr1_1 bnd_a53 -->
% 15.14/14.62 (bnd_c1_2 bnd_a53 X47 |
% 15.14/14.62 ~ bnd_c3_2 bnd_a53 X47) |
% 15.14/14.62 bnd_c6_2 bnd_a53 X47)) &
% 15.14/14.62 bnd_ndr1_1 bnd_a53) &
% 15.14/14.62 ~ bnd_c3_2 bnd_a53 bnd_a54) &
% 15.14/14.62 bnd_c9_2 bnd_a53 bnd_a54) &
% 15.14/14.62 (ALL X48.
% 15.14/14.62 bnd_ndr1_1 bnd_a53 -->
% 15.14/14.62 (bnd_c4_2 bnd_a53 X48 | ~ bnd_c10_2 bnd_a53 X48) |
% 15.14/14.62 bnd_c7_2 bnd_a53 X48))) &
% 15.14/14.62 (((bnd_ndr1_0 & ~ bnd_c6_1 bnd_a55) &
% 15.14/14.62 ~ bnd_c10_1 bnd_a55 |
% 15.14/14.62 (bnd_ndr1_0 & ~ bnd_c1_1 bnd_a56) &
% 15.14/14.62 ~ bnd_c8_1 bnd_a56) |
% 15.14/14.62 (ALL X49.
% 15.14/14.62 bnd_ndr1_0 -->
% 15.14/14.62 (bnd_c6_1 X49 |
% 15.14/14.62 (ALL X50.
% 15.14/14.62 bnd_ndr1_1 X49 -->
% 15.14/14.62 (bnd_c2_2 X49 X50 | bnd_c6_2 X49 X50) |
% 15.14/14.62 bnd_c4_2 X49 X50)) |
% 15.14/14.62 bnd_c1_1 X49))) &
% 15.14/14.62 ((~ bnd_c6_0 | ~ bnd_c5_0) |
% 15.14/14.62 (ALL X51. bnd_ndr1_0 --> bnd_c10_1 X51 | bnd_c4_1 X51))) &
% 15.14/14.62 ((bnd_c4_0 | bnd_c6_0) | bnd_c2_0)) &
% 15.14/14.62 ((~ bnd_c2_0 |
% 15.14/14.62 (ALL X52.
% 15.14/14.62 bnd_ndr1_0 -->
% 15.14/14.62 (bnd_c9_1 X52 |
% 15.14/14.62 ((bnd_ndr1_1 X52 & ~ bnd_c5_2 X52 bnd_a57) &
% 15.14/14.62 bnd_c7_2 X52 bnd_a57) &
% 15.14/14.62 ~ bnd_c4_2 X52 bnd_a57) |
% 15.14/14.62 ((bnd_ndr1_1 X52 & bnd_c3_2 X52 bnd_a58) &
% 15.14/14.62 ~ bnd_c4_2 X52 bnd_a58) &
% 15.14/14.62 bnd_c2_2 X52 bnd_a58)) |
% 15.14/14.62 (bnd_ndr1_0 &
% 15.14/14.62 (ALL X53.
% 15.14/14.62 bnd_ndr1_1 bnd_a59 -->
% 15.14/14.62 (~ bnd_c7_2 bnd_a59 X53 | bnd_c8_2 bnd_a59 X53) |
% 15.14/14.62 bnd_c9_2 bnd_a59 X53)) &
% 15.14/14.62 ~ bnd_c9_1 bnd_a59)) &
% 15.14/14.62 (((ALL X54. bnd_ndr1_0 --> ~ bnd_c3_1 X54 | bnd_c8_1 X54) |
% 15.14/14.62 (ALL X55.
% 15.14/14.62 bnd_ndr1_0 -->
% 15.14/14.62 ((ALL X56.
% 15.14/14.62 bnd_ndr1_1 X55 -->
% 15.14/14.62 (bnd_c7_2 X55 X56 | bnd_c5_2 X55 X56) |
% 15.14/14.62 ~ bnd_c1_2 X55 X56) |
% 15.14/14.62 ((bnd_ndr1_1 X55 & bnd_c7_2 X55 bnd_a60) &
% 15.14/14.62 ~ bnd_c9_2 X55 bnd_a60) &
% 15.14/14.62 bnd_c5_2 X55 bnd_a60) |
% 15.14/14.62 (bnd_ndr1_1 X55 & bnd_c9_2 X55 bnd_a61) &
% 15.14/14.62 ~ bnd_c5_2 X55 bnd_a61)) |
% 15.14/14.62 (ALL X57.
% 15.14/14.62 bnd_ndr1_0 -->
% 15.14/14.62 (((bnd_ndr1_1 X57 & ~ bnd_c9_2 X57 bnd_a62) &
% 15.14/14.62 bnd_c3_2 X57 bnd_a62) &
% 15.14/14.62 bnd_c5_2 X57 bnd_a62 |
% 15.14/14.62 ((bnd_ndr1_1 X57 & ~ bnd_c7_2 X57 bnd_a63) &
% 15.14/14.62 ~ bnd_c8_2 X57 bnd_a63) &
% 15.14/14.62 bnd_c3_2 X57 bnd_a63) |
% 15.14/14.62 ~ bnd_c5_1 X57))) &
% 15.14/14.62 (((ALL X58.
% 15.14/14.62 bnd_ndr1_0 -->
% 15.14/14.62 ((bnd_ndr1_1 X58 & ~ bnd_c6_2 X58 bnd_a64) &
% 15.14/14.62 ~ bnd_c9_2 X58 bnd_a64 |
% 15.14/14.62 ((bnd_ndr1_1 X58 & bnd_c4_2 X58 bnd_a65) &
% 15.14/14.62 bnd_c5_2 X58 bnd_a65) &
% 15.14/14.62 ~ bnd_c6_2 X58 bnd_a65) |
% 15.14/14.62 ~ bnd_c4_1 X58) |
% 15.14/14.62 ~ bnd_c3_0) |
% 15.14/14.62 ~ bnd_c10_0)) &
% 15.14/14.62 ((((bnd_ndr1_0 &
% 15.14/14.62 (ALL X59.
% 15.14/14.62 bnd_ndr1_1 bnd_a66 -->
% 15.14/14.62 bnd_c3_2 bnd_a66 X59 | bnd_c1_2 bnd_a66 X59)) &
% 15.14/14.62 ~ bnd_c9_1 bnd_a66) &
% 15.14/14.62 bnd_c4_1 bnd_a66 |
% 15.14/14.62 (ALL X60.
% 15.14/14.62 bnd_ndr1_0 -->
% 15.14/14.62 (~ bnd_c10_1 X60 | ~ bnd_c8_1 X60) |
% 15.14/14.62 ((bnd_ndr1_1 X60 & bnd_c4_2 X60 bnd_a67) &
% 15.14/14.62 ~ bnd_c2_2 X60 bnd_a67) &
% 15.14/14.62 ~ bnd_c1_2 X60 bnd_a67)) |
% 15.14/14.62 bnd_c7_0)) &
% 15.14/14.62 ((bnd_c3_0 |
% 15.14/14.62 (((((bnd_ndr1_0 & bnd_c2_1 bnd_a68) & bnd_ndr1_1 bnd_a68) &
% 15.14/14.62 ~ bnd_c3_2 bnd_a68 bnd_a69) &
% 15.14/14.62 ~ bnd_c5_2 bnd_a68 bnd_a69) &
% 15.14/14.62 ~ bnd_c7_2 bnd_a68 bnd_a69) &
% 15.14/14.62 bnd_c4_1 bnd_a68) |
% 15.14/14.62 (ALL X61.
% 15.14/14.62 bnd_ndr1_0 -->
% 15.14/14.62 (((bnd_ndr1_1 X61 & ~ bnd_c5_2 X61 bnd_a70) &
% 15.14/14.62 ~ bnd_c4_2 X61 bnd_a70) &
% 15.14/14.62 ~ bnd_c3_2 X61 bnd_a70 |
% 15.14/14.62 (ALL X62.
% 15.14/14.62 bnd_ndr1_1 X61 -->
% 15.14/14.62 (~ bnd_c5_2 X61 X62 | bnd_c3_2 X61 X62) |
% 15.14/14.62 bnd_c2_2 X61 X62)) |
% 15.14/14.62 ~ bnd_c1_1 X61))) &
% 15.14/14.62 (((ALL X63.
% 15.14/14.62 bnd_ndr1_0 -->
% 15.14/14.62 ((ALL X64.
% 15.14/14.62 bnd_ndr1_1 X63 -->
% 15.14/14.62 (bnd_c2_2 X63 X64 | ~ bnd_c7_2 X63 X64) |
% 15.14/14.62 ~ bnd_c3_2 X63 X64) |
% 15.14/14.62 bnd_c5_1 X63) |
% 15.14/14.62 (ALL X65.
% 15.14/14.62 bnd_ndr1_1 X63 -->
% 15.14/14.62 (bnd_c1_2 X63 X65 | ~ bnd_c8_2 X63 X65) |
% 15.14/14.62 ~ bnd_c5_2 X63 X65)) |
% 15.14/14.62 (ALL X66.
% 15.14/14.62 bnd_ndr1_0 -->
% 15.14/14.62 (bnd_c1_1 X66 |
% 15.14/14.62 (ALL X67.
% 15.14/14.62 bnd_ndr1_1 X66 -->
% 15.14/14.62 (~ bnd_c8_2 X66 X67 | bnd_c10_2 X66 X67) |
% 15.14/14.62 ~ bnd_c7_2 X66 X67)) |
% 15.14/14.62 bnd_c10_1 X66)) |
% 15.14/14.62 (((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a71) &
% 15.14/14.62 bnd_c4_2 bnd_a71 bnd_a72) &
% 15.14/14.62 ~ bnd_c10_2 bnd_a71 bnd_a72) &
% 15.14/14.62 bnd_c7_2 bnd_a71 bnd_a72) &
% 15.14/14.62 ~ bnd_c8_1 bnd_a71) &
% 15.14/14.62 ~ bnd_c2_1 bnd_a71)) &
% 15.14/14.62 (((bnd_ndr1_0 &
% 15.14/14.62 (ALL X68.
% 15.14/14.62 bnd_ndr1_1 bnd_a73 -->
% 15.14/14.62 (bnd_c5_2 bnd_a73 X68 | ~ bnd_c10_2 bnd_a73 X68) |
% 15.14/14.62 ~ bnd_c7_2 bnd_a73 X68)) &
% 15.14/14.62 ~ bnd_c4_1 bnd_a73) &
% 15.14/14.62 ~ bnd_c7_1 bnd_a73 |
% 15.14/14.62 (ALL X69.
% 15.14/14.62 bnd_ndr1_0 -->
% 15.14/14.62 ((ALL X70.
% 15.14/14.62 bnd_ndr1_1 X69 -->
% 15.14/14.62 (bnd_c9_2 X69 X70 | bnd_c2_2 X69 X70) |
% 15.14/14.62 ~ bnd_c8_2 X69 X70) |
% 15.14/14.62 bnd_c8_1 X69) |
% 15.14/14.62 (ALL X71.
% 15.14/14.62 bnd_ndr1_1 X69 -->
% 15.14/14.62 (bnd_c7_2 X69 X71 | bnd_c6_2 X69 X71) |
% 15.14/14.62 ~ bnd_c5_2 X69 X71)))) &
% 15.14/14.62 ((bnd_c8_0 | bnd_c7_0) | bnd_c4_0)) &
% 15.14/14.62 ((bnd_c8_0 |
% 15.14/14.62 (ALL X72.
% 15.14/14.62 bnd_ndr1_0 -->
% 15.14/14.62 (ALL X73.
% 15.14/14.62 bnd_ndr1_1 X72 -->
% 15.14/14.62 (~ bnd_c10_2 X72 X73 | bnd_c6_2 X72 X73) |
% 15.14/14.62 ~ bnd_c1_2 X72 X73) |
% 15.14/14.62 ~ bnd_c1_1 X72)) |
% 15.14/14.62 (ALL X74.
% 15.14/14.62 bnd_ndr1_0 -->
% 15.14/14.62 ((bnd_ndr1_1 X74 & ~ bnd_c2_2 X74 bnd_a74) &
% 15.14/14.62 ~ bnd_c8_2 X74 bnd_a74) &
% 15.14/14.62 bnd_c3_2 X74 bnd_a74))) &
% 15.14/14.62 ((~ bnd_c10_0 |
% 15.14/14.62 ((bnd_ndr1_0 &
% 15.14/14.62 (ALL X75.
% 15.14/14.62 bnd_ndr1_1 bnd_a75 -->
% 15.14/14.62 (~ bnd_c5_2 bnd_a75 X75 | ~ bnd_c6_2 bnd_a75 X75) |
% 15.14/14.62 bnd_c4_2 bnd_a75 X75)) &
% 15.14/14.62 ~ bnd_c9_1 bnd_a75) &
% 15.14/14.62 ~ bnd_c2_1 bnd_a75) |
% 15.14/14.62 (ALL X76.
% 15.14/14.62 bnd_ndr1_0 -->
% 15.14/14.62 (~ bnd_c5_1 X76 |
% 15.14/14.62 ((bnd_ndr1_1 X76 & bnd_c7_2 X76 bnd_a76) &
% 15.14/14.62 bnd_c6_2 X76 bnd_a76) &
% 15.14/14.62 bnd_c8_2 X76 bnd_a76) |
% 15.14/14.62 (ALL X77.
% 15.14/14.62 bnd_ndr1_1 X76 -->
% 15.14/14.62 (bnd_c7_2 X76 X77 | ~ bnd_c5_2 X76 X77) |
% 15.14/14.62 ~ bnd_c1_2 X76 X77)))) &
% 15.14/14.62 ((bnd_c4_0 | bnd_c1_0) |
% 15.14/14.62 (((((bnd_ndr1_0 & ~ bnd_c2_1 bnd_a77) & bnd_ndr1_1 bnd_a77) &
% 15.14/14.62 ~ bnd_c1_2 bnd_a77 bnd_a78) &
% 15.14/14.62 ~ bnd_c8_2 bnd_a77 bnd_a78) &
% 15.14/14.62 bnd_c5_2 bnd_a77 bnd_a78) &
% 15.14/14.62 bnd_c4_1 bnd_a77)) &
% 15.14/14.62 (~ bnd_c7_0 |
% 15.14/14.62 (ALL X78.
% 15.14/14.62 bnd_ndr1_0 -->
% 15.14/14.62 (bnd_c7_1 X78 |
% 15.14/14.62 (bnd_ndr1_1 X78 & ~ bnd_c8_2 X78 bnd_a79) &
% 15.14/14.62 bnd_c2_2 X78 bnd_a79) |
% 15.14/14.62 ((bnd_ndr1_1 X78 & bnd_c10_2 X78 bnd_a80) &
% 15.14/14.62 ~ bnd_c4_2 X78 bnd_a80) &
% 15.14/14.62 bnd_c3_2 X78 bnd_a80))) &
% 15.14/14.62 (bnd_c2_0 | bnd_c10_0)) &
% 15.14/14.62 ((bnd_c9_0 |
% 15.14/14.62 (ALL X79.
% 15.14/14.62 bnd_ndr1_0 -->
% 15.14/14.62 ((ALL X80.
% 15.14/14.62 bnd_ndr1_1 X79 -->
% 15.14/14.62 (~ bnd_c5_2 X79 X80 | bnd_c8_2 X79 X80) | ~ bnd_c3_2 X79 X80) |
% 15.14/14.62 bnd_c10_1 X79) |
% 15.14/14.62 bnd_c7_1 X79)) |
% 15.14/14.62 (((((bnd_ndr1_0 & ~ bnd_c1_1 bnd_a81) & ~ bnd_c9_1 bnd_a81) &
% 15.14/14.62 bnd_ndr1_1 bnd_a81) &
% 15.14/14.62 ~ bnd_c10_2 bnd_a81 bnd_a82) &
% 15.14/14.62 bnd_c3_2 bnd_a81 bnd_a82) &
% 15.14/14.62 ~ bnd_c1_2 bnd_a81 bnd_a82)) &
% 15.14/14.62 (((ALL X81.
% 15.14/14.62 bnd_ndr1_0 -->
% 15.14/14.62 ((ALL X82.
% 15.14/14.62 bnd_ndr1_1 X81 -->
% 15.14/14.62 (~ bnd_c2_2 X81 X82 | ~ bnd_c3_2 X81 X82) |
% 15.14/14.62 ~ bnd_c5_2 X81 X82) |
% 15.14/14.62 bnd_ndr1_1 X81 & bnd_c6_2 X81 bnd_a83) |
% 15.14/14.62 ~ bnd_c3_1 X81) |
% 15.14/14.62 bnd_c3_0) |
% 15.14/14.62 bnd_c5_0)) &
% 15.14/14.62 (((ALL X83.
% 15.14/14.62 bnd_ndr1_0 -->
% 15.14/14.62 (((bnd_ndr1_1 X83 & bnd_c9_2 X83 bnd_a84) & bnd_c5_2 X83 bnd_a84) &
% 15.14/14.62 ~ bnd_c8_2 X83 bnd_a84 |
% 15.14/14.62 ((bnd_ndr1_1 X83 & bnd_c6_2 X83 bnd_a85) & bnd_c3_2 X83 bnd_a85) &
% 15.14/14.62 ~ bnd_c9_2 X83 bnd_a85) |
% 15.14/14.62 ((bnd_ndr1_1 X83 & ~ bnd_c10_2 X83 bnd_a86) &
% 15.14/14.62 ~ bnd_c2_2 X83 bnd_a86) &
% 15.14/14.62 ~ bnd_c8_2 X83 bnd_a86) |
% 15.14/14.62 bnd_c2_0) |
% 15.14/14.62 bnd_c3_0)) &
% 15.14/14.62 ((((((bnd_ndr1_0 &
% 15.14/14.62 bnd_ndr1_1 bnd_a87) &
% 15.14/14.62 ~ bnd_c6_2 bnd_a87 bnd_a88) &
% 15.14/14.62 ~ bnd_c9_2 bnd_a87 bnd_a88) &
% 15.14/14.62 (ALL X84.
% 15.14/14.62 bnd_ndr1_1 bnd_a87 -->
% 15.14/14.62 (~ bnd_c1_2 bnd_a87 X84 | bnd_c6_2 bnd_a87 X84) |
% 15.14/14.62 ~ bnd_c5_2 bnd_a87 X84)) &
% 15.14/14.62 ~ bnd_c1_1 bnd_a87 |
% 15.14/14.62 (ALL X85.
% 15.14/14.62 bnd_ndr1_0 -->
% 15.14/14.62 (((bnd_ndr1_1 X85 & ~ bnd_c9_2 X85 bnd_a89) & bnd_c10_2 X85 bnd_a89) &
% 15.14/14.62 bnd_c4_2 X85 bnd_a89 |
% 15.14/14.62 bnd_c4_1 X85) |
% 15.14/14.62 ~ bnd_c6_1 X85)) |
% 15.14/14.62 bnd_c4_0)) &
% 15.14/14.62 ((~ bnd_c8_0 |
% 15.14/14.62 ((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a90) & ~ bnd_c2_2 bnd_a90 bnd_a91) &
% 15.14/14.62 bnd_c4_2 bnd_a90 bnd_a91) &
% 15.14/14.62 bnd_c7_2 bnd_a90 bnd_a91) &
% 15.14/14.62 ~ bnd_c4_1 bnd_a90) |
% 15.14/14.62 (ALL X86.
% 15.14/14.62 bnd_ndr1_0 -->
% 15.14/14.62 (~ bnd_c8_1 X86 |
% 15.14/14.62 ((bnd_ndr1_1 X86 & bnd_c8_2 X86 bnd_a92) & bnd_c9_2 X86 bnd_a92) &
% 15.14/14.62 bnd_c10_2 X86 bnd_a92) |
% 15.14/14.62 (ALL X87.
% 15.14/14.62 bnd_ndr1_1 X86 -->
% 15.14/14.62 (~ bnd_c4_2 X86 X87 | ~ bnd_c6_2 X86 X87) | ~ bnd_c8_2 X86 X87)))) &
% 15.14/14.62 (((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a93) &
% 15.14/14.62 bnd_c4_2 bnd_a93 bnd_a94) &
% 15.14/14.62 ~ bnd_c7_2 bnd_a93 bnd_a94) &
% 15.14/14.62 ~ bnd_c2_2 bnd_a93 bnd_a94) &
% 15.14/14.62 ~ bnd_c8_1 bnd_a93) &
% 15.14/14.62 ~ bnd_c2_1 bnd_a93 |
% 15.14/14.62 bnd_c7_0) |
% 15.14/14.62 bnd_c1_0)) &
% 15.14/14.62 ((~ bnd_c4_0 |
% 15.14/14.62 ((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a95) &
% 15.14/14.62 bnd_c8_2 bnd_a95 bnd_a96) &
% 15.14/14.62 ~ bnd_c2_2 bnd_a95 bnd_a96) &
% 15.14/14.62 ~ bnd_c4_2 bnd_a95 bnd_a96) &
% 15.14/14.62 bnd_c4_1 bnd_a95) |
% 15.14/14.62 ~ bnd_c3_0)) &
% 15.14/14.62 ((((bnd_ndr1_0 &
% 15.14/14.62 (ALL X88.
% 15.14/14.62 bnd_ndr1_1 bnd_a97 --> bnd_c9_2 bnd_a97 X88 | ~ bnd_c6_2 bnd_a97 X88)) &
% 15.14/14.62 bnd_c8_1 bnd_a97) &
% 15.14/14.62 bnd_c5_1 bnd_a97 |
% 15.14/14.62 bnd_c8_0) |
% 15.14/14.62 (((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a98) &
% 15.14/14.62 bnd_c1_2 bnd_a98 bnd_a99) &
% 15.14/14.62 ~ bnd_c6_2 bnd_a98 bnd_a99) &
% 15.14/14.62 bnd_c9_2 bnd_a98 bnd_a99) &
% 15.14/14.62 ~ bnd_c8_1 bnd_a98) &
% 15.14/14.62 bnd_c2_1 bnd_a98)) &
% 15.14/14.62 ((bnd_c4_0 |
% 15.14/14.62 (((((bnd_ndr1_0 &
% 15.14/14.62 (ALL X89.
% 15.14/14.62 bnd_ndr1_1 bnd_a100 -->
% 15.14/14.62 (bnd_c2_2 bnd_a100 X89 | ~ bnd_c3_2 bnd_a100 X89) |
% 15.14/14.62 ~ bnd_c7_2 bnd_a100 X89)) &
% 15.14/14.62 bnd_c9_1 bnd_a100) &
% 15.14/14.62 bnd_ndr1_1 bnd_a100) &
% 15.14/14.62 ~ bnd_c6_2 bnd_a100 bnd_a101) &
% 15.14/14.62 ~ bnd_c5_2 bnd_a100 bnd_a101) &
% 15.14/14.62 bnd_c9_2 bnd_a100 bnd_a101) |
% 15.14/14.62 (((((bnd_ndr1_0 & bnd_c10_1 bnd_a102) &
% 15.14/14.62 bnd_ndr1_1 bnd_a102) &
% 15.14/14.62 ~ bnd_c2_2 bnd_a102 bnd_a103) &
% 15.14/14.62 ~ bnd_c4_2 bnd_a102 bnd_a103) &
% 15.14/14.62 ~ bnd_c6_2 bnd_a102 bnd_a103) &
% 15.14/14.62 bnd_c4_1 bnd_a102)) &
% 15.14/14.62 ((~ bnd_c6_0 |
% 15.14/14.62 (ALL X90.
% 15.14/14.62 bnd_ndr1_0 -->
% 15.14/14.62 ((ALL X91.
% 15.14/14.62 bnd_ndr1_1 X90 -->
% 15.14/14.62 (bnd_c3_2 X90 X91 | bnd_c10_2 X90 X91) | ~ bnd_c5_2 X90 X91) |
% 15.14/14.62 bnd_c9_1 X90) |
% 15.14/14.62 ~ bnd_c5_1 X90)) |
% 15.14/14.62 (ALL X92.
% 15.14/14.62 bnd_ndr1_0 -->
% 15.14/14.62 (~ bnd_c6_1 X92 |
% 15.14/14.62 ((bnd_ndr1_1 X92 &
% 15.14/14.62 ~ bnd_c4_2 X92 bnd_a104) &
% 15.14/14.62 ~ bnd_c1_2 X92 bnd_a104) &
% 15.14/14.62 bnd_c8_2 X92 bnd_a104) |
% 15.14/14.62 (ALL X93.
% 15.14/14.62 bnd_ndr1_1 X92 --> ~ bnd_c1_2 X92 X93 | bnd_c4_2 X92 X93)))) &
% 15.14/14.62 ((((((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a105) &
% 15.14/14.62 ~ bnd_c6_2 bnd_a105 bnd_a106) &
% 15.14/14.62 bnd_c4_2 bnd_a105 bnd_a106) &
% 15.14/14.62 ~ bnd_c2_2 bnd_a105 bnd_a106) &
% 15.14/14.62 bnd_ndr1_1 bnd_a105) &
% 15.14/14.62 ~ bnd_c9_2 bnd_a105 bnd_a107) &
% 15.14/14.62 bnd_c6_2 bnd_a105 bnd_a107) &
% 15.14/14.62 ~ bnd_c5_2 bnd_a105 bnd_a107) &
% 15.14/14.62 bnd_c7_1 bnd_a105 |
% 15.14/14.62 bnd_c2_0) |
% 15.14/14.62 (((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a108) &
% 15.14/14.62 ~ bnd_c7_2 bnd_a108 bnd_a109) &
% 15.14/14.62 bnd_c1_2 bnd_a108 bnd_a109) &
% 15.14/14.62 ~ bnd_c2_2 bnd_a108 bnd_a109) &
% 15.14/14.62 (ALL X94.
% 15.14/14.62 bnd_ndr1_1 bnd_a108 -->
% 15.14/14.62 ~ bnd_c2_2 bnd_a108 X94 | ~ bnd_c7_2 bnd_a108 X94)) &
% 15.14/14.62 bnd_ndr1_1 bnd_a108) &
% 15.14/14.62 bnd_c3_2 bnd_a108 bnd_a110) &
% 15.14/14.62 ~ bnd_c2_2 bnd_a108 bnd_a110)) &
% 15.14/14.62 ((~ bnd_c8_0 | ~ bnd_c5_0) |
% 15.14/14.62 (ALL X95.
% 15.14/14.62 bnd_ndr1_0 -->
% 15.14/14.62 (~ bnd_c8_1 X95 | bnd_c5_1 X95) |
% 15.14/14.62 bnd_c7_1 X95))) &
% 15.14/14.62 ((ALL X96.
% 15.14/14.62 bnd_ndr1_0 -->
% 15.14/14.62 ((ALL X97.
% 15.14/14.62 bnd_ndr1_1 X96 -->
% 15.14/14.62 (bnd_c9_2 X96 X97 | bnd_c6_2 X96 X97) | ~ bnd_c8_2 X96 X97) |
% 15.14/14.62 (ALL X98.
% 15.14/14.62 bnd_ndr1_1 X96 -->
% 15.14/14.62 (~ bnd_c3_2 X96 X98 | bnd_c8_2 X96 X98) | bnd_c7_2 X96 X98)) |
% 15.14/14.62 ~ bnd_c7_1 X96) |
% 15.14/14.62 ~ bnd_c4_0)) &
% 15.14/14.62 (((ALL X99.
% 15.14/14.62 bnd_ndr1_0 -->
% 15.14/14.62 (~ bnd_c3_1 X99 | bnd_c8_1 X99) |
% 15.14/14.62 (ALL X100.
% 15.14/14.62 bnd_ndr1_1 X99 -->
% 15.14/14.62 (~ bnd_c7_2 X99 X100 |
% 15.14/14.62 ~ bnd_c3_2 X99 X100) |
% 15.14/14.62 ~ bnd_c6_2 X99 X100)) |
% 15.14/14.62 bnd_c3_0) |
% 15.14/14.62 bnd_c1_0)) &
% 15.14/14.62 ((~ bnd_c1_0 |
% 15.14/14.62 (ALL X101.
% 15.14/14.62 bnd_ndr1_0 -->
% 15.14/14.62 ((bnd_ndr1_1 X101 &
% 15.14/14.62 bnd_c5_2 X101 bnd_a111) &
% 15.14/14.62 bnd_c4_2 X101 bnd_a111) &
% 15.14/14.62 ~ bnd_c3_2 X101 bnd_a111 |
% 15.14/14.62 (ALL X102.
% 15.14/14.62 bnd_ndr1_1 X101 -->
% 15.14/14.62 (bnd_c10_2 X101 X102 |
% 15.14/14.62 ~ bnd_c4_2 X101 X102) |
% 15.14/14.62 bnd_c8_2 X101 X102))) |
% 15.14/14.62 ((((bnd_ndr1_0 & bnd_c6_1 bnd_a112) &
% 15.14/14.62 ~ bnd_c3_1 bnd_a112) &
% 15.14/14.62 bnd_ndr1_1 bnd_a112) &
% 15.14/14.62 ~ bnd_c4_2 bnd_a112 bnd_a113) &
% 15.14/14.62 ~ bnd_c9_2 bnd_a112 bnd_a113)) &
% 15.14/14.62 ((~ bnd_c10_0 |
% 15.14/14.62 (((((bnd_ndr1_0 & ~ bnd_c1_1 bnd_a114) &
% 15.14/14.62 bnd_ndr1_1 bnd_a114) &
% 15.14/14.62 ~ bnd_c5_2 bnd_a114 bnd_a115) &
% 15.14/14.62 bnd_c2_2 bnd_a114 bnd_a115) &
% 15.14/14.62 ~ bnd_c4_2 bnd_a114 bnd_a115) &
% 15.14/14.62 (ALL X103.
% 15.14/14.62 bnd_ndr1_1 bnd_a114 -->
% 15.14/14.62 (bnd_c10_2 bnd_a114 X103 |
% 15.14/14.62 ~ bnd_c8_2 bnd_a114 X103) |
% 15.14/14.62 bnd_c1_2 bnd_a114 X103)) |
% 15.14/14.62 bnd_c2_0)) &
% 15.14/14.62 ((~ bnd_c9_0 | bnd_c8_0) |
% 15.14/14.62 (((bnd_ndr1_0 & bnd_ndr1_1 bnd_a116) &
% 15.14/14.62 ~ bnd_c10_2 bnd_a116 bnd_a117) &
% 15.14/14.62 bnd_c3_2 bnd_a116 bnd_a117) &
% 15.14/14.62 ~ bnd_c7_1 bnd_a116)) &
% 15.14/14.62 (((ALL X104.
% 15.14/14.62 bnd_ndr1_0 -->
% 15.14/14.62 (((bnd_ndr1_1 X104 &
% 15.14/14.62 ~ bnd_c2_2 X104 bnd_a118) &
% 15.14/14.62 ~ bnd_c9_2 X104 bnd_a118) &
% 15.14/14.62 bnd_c5_2 X104 bnd_a118 |
% 15.14/14.62 ~ bnd_c4_1 X104) |
% 15.14/14.62 ~ bnd_c2_1 X104) |
% 15.14/14.62 ((((bnd_ndr1_0 & ~ bnd_c6_1 bnd_a119) &
% 15.14/14.62 bnd_c10_1 bnd_a119) &
% 15.14/14.62 bnd_ndr1_1 bnd_a119) &
% 15.14/14.62 ~ bnd_c1_2 bnd_a119 bnd_a120) &
% 15.14/14.62 bnd_c5_2 bnd_a119 bnd_a120) |
% 15.14/14.62 bnd_c6_0)) &
% 15.14/14.62 ((((bnd_ndr1_0 & ~ bnd_c9_1 bnd_a121) &
% 15.14/14.62 ~ bnd_c6_1 bnd_a121) &
% 15.14/14.62 ~ bnd_c10_1 bnd_a121 |
% 15.14/14.62 bnd_c3_0) |
% 15.14/14.62 ((bnd_ndr1_0 & bnd_c9_1 bnd_a122) &
% 15.14/14.62 bnd_c4_1 bnd_a122) &
% 15.14/14.62 (ALL X105.
% 15.14/14.62 bnd_ndr1_1 bnd_a122 -->
% 15.14/14.62 (bnd_c10_2 bnd_a122 X105 |
% 15.14/14.62 bnd_c3_2 bnd_a122 X105) |
% 15.14/14.62 bnd_c1_2 bnd_a122 X105))) &
% 15.14/14.62 ((~ bnd_c4_0 | ~ bnd_c10_0) | ~ bnd_c2_0)) &
% 15.14/14.62 (((ALL X106.
% 15.14/14.62 bnd_ndr1_0 -->
% 15.14/14.62 ((ALL X107.
% 15.14/14.62 bnd_ndr1_1 X106 -->
% 15.14/14.62 (~ bnd_c2_2 X106 X107 | bnd_c4_2 X106 X107) |
% 15.14/14.62 bnd_c10_2 X106 X107) |
% 15.14/14.62 bnd_c7_1 X106) |
% 15.14/14.62 bnd_c5_1 X106) |
% 15.14/14.62 ~ bnd_c8_0) |
% 15.14/14.62 ~ bnd_c1_0)) &
% 15.14/14.62 ((((((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a123) &
% 15.14/14.62 bnd_c2_2 bnd_a123 bnd_a124) &
% 15.14/14.62 ~ bnd_c4_2 bnd_a123 bnd_a124) &
% 15.14/14.62 ~ bnd_c9_2 bnd_a123 bnd_a124) &
% 15.14/14.62 bnd_ndr1_1 bnd_a123) &
% 15.14/14.62 ~ bnd_c9_2 bnd_a123 bnd_a125) &
% 15.14/14.62 bnd_c3_2 bnd_a123 bnd_a125) &
% 15.14/14.62 ~ bnd_c4_2 bnd_a123 bnd_a125) &
% 15.14/14.62 ~ bnd_c9_1 bnd_a123 |
% 15.14/14.62 bnd_c10_0) |
% 15.14/14.62 (bnd_ndr1_0 & bnd_c4_1 bnd_a126) & bnd_c6_1 bnd_a126)) &
% 15.14/14.62 (((ALL X108.
% 15.14/14.62 bnd_ndr1_0 -->
% 15.14/14.62 (bnd_c7_1 X108 | bnd_c3_1 X108) | ~ bnd_c1_1 X108) |
% 15.14/14.62 bnd_c6_0) |
% 15.14/14.62 ~ bnd_c4_0)) &
% 15.14/14.62 ((((bnd_ndr1_0 & bnd_c4_1 bnd_a127) &
% 15.14/14.62 ~ bnd_c2_1 bnd_a127) &
% 15.14/14.62 (ALL X109.
% 15.14/14.62 bnd_ndr1_1 bnd_a127 -->
% 15.14/14.62 (~ bnd_c7_2 bnd_a127 X109 |
% 15.14/14.62 bnd_c10_2 bnd_a127 X109) |
% 15.14/14.62 ~ bnd_c4_2 bnd_a127 X109) |
% 15.14/14.62 ~ bnd_c1_0) |
% 15.14/14.62 bnd_c3_0)) &
% 15.14/14.62 ((((bnd_ndr1_0 &
% 15.14/14.62 (ALL X110.
% 15.14/14.62 bnd_ndr1_1 bnd_a128 -->
% 15.14/14.62 (~ bnd_c1_2 bnd_a128 X110 |
% 15.14/14.62 ~ bnd_c4_2 bnd_a128 X110) |
% 15.14/14.62 bnd_c6_2 bnd_a128 X110)) &
% 15.14/14.62 ~ bnd_c1_1 bnd_a128) &
% 15.14/14.62 ~ bnd_c4_1 bnd_a128 |
% 15.14/14.62 bnd_c5_0) |
% 15.14/14.62 ~ bnd_c9_0)) &
% 15.14/14.62 (((ALL X111.
% 15.14/14.62 bnd_ndr1_0 -->
% 15.14/14.62 ((ALL X112.
% 15.14/14.62 bnd_ndr1_1 X111 -->
% 15.14/14.62 (~ bnd_c9_2 X111 X112 | bnd_c1_2 X111 X112) |
% 15.14/14.62 bnd_c2_2 X111 X112) |
% 15.14/14.62 bnd_c4_1 X111) |
% 15.14/14.62 (ALL X113.
% 15.14/14.62 bnd_ndr1_1 X111 -->
% 15.14/14.62 (bnd_c8_2 X111 X113 | ~ bnd_c9_2 X111 X113) |
% 15.14/14.62 bnd_c7_2 X111 X113)) |
% 15.14/14.62 (ALL X114. bnd_ndr1_0 --> bnd_c1_1 X114 | bnd_c5_1 X114)) |
% 15.14/14.62 (ALL X115.
% 15.14/14.62 bnd_ndr1_0 -->
% 15.14/14.62 ((ALL X116.
% 15.14/14.62 bnd_ndr1_1 X115 -->
% 15.14/14.62 (bnd_c9_2 X115 X116 | bnd_c7_2 X115 X116) |
% 15.14/14.62 bnd_c4_2 X115 X116) |
% 15.14/14.62 ~ bnd_c9_1 X115) |
% 15.14/14.62 ((bnd_ndr1_1 X115 & ~ bnd_c5_2 X115 bnd_a129) &
% 15.14/14.62 bnd_c6_2 X115 bnd_a129) &
% 15.14/14.62 bnd_c1_2 X115 bnd_a129))) &
% 15.14/14.62 ((bnd_c9_0 |
% 15.14/14.62 (ALL X117.
% 15.14/14.62 bnd_ndr1_0 -->
% 15.14/14.62 (bnd_c5_1 X117 |
% 15.14/14.62 (bnd_ndr1_1 X117 & ~ bnd_c7_2 X117 bnd_a130) &
% 15.14/14.62 bnd_c1_2 X117 bnd_a130) |
% 15.14/14.62 (ALL X118.
% 15.14/14.62 bnd_ndr1_1 X117 -->
% 15.14/14.62 (bnd_c8_2 X117 X118 | bnd_c10_2 X117 X118) |
% 15.14/14.62 ~ bnd_c6_2 X117 X118))) |
% 15.14/14.62 bnd_c2_0)) &
% 15.14/14.62 (((ALL X119.
% 15.14/14.62 bnd_ndr1_0 -->
% 15.14/14.62 ((ALL X120.
% 15.14/14.62 bnd_ndr1_1 X119 -->
% 15.14/14.62 (~ bnd_c7_2 X119 X120 | bnd_c9_2 X119 X120) |
% 15.14/14.62 ~ bnd_c6_2 X119 X120) |
% 15.14/14.62 (ALL X121.
% 15.14/14.62 bnd_ndr1_1 X119 -->
% 15.14/14.62 (~ bnd_c6_2 X119 X121 | bnd_c9_2 X119 X121) |
% 15.14/14.62 bnd_c2_2 X119 X121)) |
% 15.14/14.62 ((bnd_ndr1_1 X119 & ~ bnd_c10_2 X119 bnd_a131) &
% 15.14/14.62 ~ bnd_c1_2 X119 bnd_a131) &
% 15.14/14.62 bnd_c2_2 X119 bnd_a131) |
% 15.14/14.62 (ALL X122.
% 15.14/14.62 bnd_ndr1_0 -->
% 15.14/14.62 ~ bnd_c3_1 X122 |
% 15.14/14.62 ((bnd_ndr1_1 X122 & ~ bnd_c4_2 X122 bnd_a132) &
% 15.14/14.62 ~ bnd_c8_2 X122 bnd_a132) &
% 15.14/14.62 bnd_c5_2 X122 bnd_a132)) |
% 15.14/14.62 (ALL X123.
% 15.14/14.62 bnd_ndr1_0 -->
% 15.14/14.62 (~ bnd_c6_1 X123 |
% 15.14/14.62 ((bnd_ndr1_1 X123 & ~ bnd_c4_2 X123 bnd_a133) &
% 15.14/14.62 bnd_c7_2 X123 bnd_a133) &
% 15.14/14.62 ~ bnd_c8_2 X123 bnd_a133) |
% 15.14/14.62 ~ bnd_c10_1 X123))) &
% 15.14/14.62 ((~ bnd_c1_0 | ~ bnd_c10_0) |
% 15.14/14.62 (((((bnd_ndr1_0 &
% 15.14/14.62 (ALL X124.
% 15.14/14.62 bnd_ndr1_1 bnd_a134 -->
% 15.14/14.62 (~ bnd_c7_2 bnd_a134 X124 |
% 15.14/14.62 ~ bnd_c2_2 bnd_a134 X124) |
% 15.14/14.62 ~ bnd_c5_2 bnd_a134 X124)) &
% 15.14/14.62 bnd_c10_1 bnd_a134) &
% 15.14/14.62 bnd_ndr1_1 bnd_a134) &
% 15.14/14.62 ~ bnd_c8_2 bnd_a134 bnd_a135) &
% 15.14/14.62 ~ bnd_c6_2 bnd_a134 bnd_a135) &
% 15.14/14.62 bnd_c3_2 bnd_a134 bnd_a135)) &
% 15.14/14.62 (((((((bnd_ndr1_0 & bnd_c7_1 bnd_a136) & bnd_ndr1_1 bnd_a136) &
% 15.14/14.62 bnd_c2_2 bnd_a136 bnd_a137) &
% 15.14/14.62 ~ bnd_c5_2 bnd_a136 bnd_a137) &
% 15.14/14.62 ~ bnd_c10_2 bnd_a136 bnd_a137) &
% 15.14/14.62 ~ bnd_c8_1 bnd_a136 |
% 15.14/14.62 ~ bnd_c8_0) |
% 15.14/14.62 ~ bnd_c2_0)) &
% 15.14/14.62 ((bnd_c10_0 |
% 15.14/14.62 (ALL X125.
% 15.14/14.62 bnd_ndr1_0 -->
% 15.14/14.62 (~ bnd_c4_1 X125 | bnd_c5_1 X125) |
% 15.14/14.62 ((bnd_ndr1_1 X125 & ~ bnd_c6_2 X125 bnd_a138) &
% 15.14/14.62 bnd_c4_2 X125 bnd_a138) &
% 15.14/14.62 ~ bnd_c1_2 X125 bnd_a138)) |
% 15.14/14.62 (((((((bnd_ndr1_0 & ~ bnd_c2_1 bnd_a139) & bnd_ndr1_1 bnd_a139) &
% 15.14/14.62 bnd_c9_2 bnd_a139 bnd_a140) &
% 15.14/14.62 ~ bnd_c3_2 bnd_a139 bnd_a140) &
% 15.14/14.62 ~ bnd_c8_2 bnd_a139 bnd_a140) &
% 15.14/14.62 bnd_ndr1_1 bnd_a139) &
% 15.14/14.62 bnd_c1_2 bnd_a139 bnd_a141) &
% 15.14/14.62 ~ bnd_c9_2 bnd_a139 bnd_a141)) &
% 15.14/14.62 (((ALL X126. bnd_ndr1_0 --> bnd_c3_1 X126 | ~ bnd_c4_1 X126) |
% 15.14/14.62 (ALL X127.
% 15.14/14.62 bnd_ndr1_0 -->
% 15.14/14.62 (bnd_c1_1 X127 | ~ bnd_c3_1 X127) |
% 15.14/14.62 ((bnd_ndr1_1 X127 & bnd_c7_2 X127 bnd_a142) &
% 15.14/14.62 ~ bnd_c6_2 X127 bnd_a142) &
% 15.14/14.62 ~ bnd_c9_2 X127 bnd_a142)) |
% 15.14/14.62 bnd_c8_0)) &
% 15.14/14.62 ((bnd_c10_0 | bnd_c4_0) |
% 15.14/14.62 ((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a143) &
% 15.14/14.62 bnd_c9_2 bnd_a143 bnd_a144) &
% 15.14/14.62 ~ bnd_c5_2 bnd_a143 bnd_a144) &
% 15.14/14.62 ~ bnd_c10_2 bnd_a143 bnd_a144) &
% 15.14/14.62 bnd_c1_1 bnd_a143)) &
% 15.14/14.62 ((bnd_c9_0 |
% 15.14/14.62 (ALL X128.
% 15.14/14.62 bnd_ndr1_0 -->
% 15.14/14.62 ((ALL X129.
% 15.14/14.62 bnd_ndr1_1 X128 -->
% 15.14/14.62 (bnd_c2_2 X128 X129 | ~ bnd_c8_2 X128 X129) |
% 15.14/14.62 bnd_c7_2 X128 X129) |
% 15.14/14.62 ~ bnd_c8_1 X128) |
% 15.14/14.62 ~ bnd_c4_1 X128)) |
% 15.14/14.62 ~ bnd_c6_0)) &
% 15.14/14.62 ((~ bnd_c2_0 | bnd_c1_0) | bnd_c3_0)) &
% 15.14/14.62 (((ALL X130.
% 15.14/14.62 bnd_ndr1_0 -->
% 15.14/14.62 (ALL X131.
% 15.14/14.62 bnd_ndr1_1 X130 -->
% 15.14/14.62 (bnd_c7_2 X130 X131 | ~ bnd_c6_2 X130 X131) |
% 15.14/14.62 bnd_c8_2 X130 X131) |
% 15.14/14.62 bnd_c7_1 X130) |
% 15.14/14.62 (ALL X132.
% 15.14/14.62 bnd_ndr1_0 -->
% 15.14/14.62 (ALL X133.
% 15.14/14.62 bnd_ndr1_1 X132 -->
% 15.14/14.62 (bnd_c8_2 X132 X133 | bnd_c7_2 X132 X133) |
% 15.14/14.62 ~ bnd_c3_2 X132 X133) |
% 15.14/14.62 bnd_c2_1 X132)) |
% 15.14/14.62 bnd_c2_0)) &
% 15.14/14.62 (((ALL X134. bnd_ndr1_0 --> bnd_c6_1 X134 | bnd_c7_1 X134) |
% 15.14/14.62 (ALL X135.
% 15.14/14.62 bnd_ndr1_0 -->
% 15.14/14.62 (bnd_c9_1 X135 |
% 15.14/14.62 ((bnd_ndr1_1 X135 & bnd_c3_2 X135 bnd_a145) &
% 15.14/14.62 bnd_c1_2 X135 bnd_a145) &
% 15.14/14.62 ~ bnd_c5_2 X135 bnd_a145) |
% 15.14/14.62 ~ bnd_c1_1 X135)) |
% 15.14/14.62 (ALL X136.
% 15.14/14.62 bnd_ndr1_0 -->
% 15.14/14.62 (((bnd_ndr1_1 X136 & ~ bnd_c9_2 X136 bnd_a146) &
% 15.14/14.62 ~ bnd_c1_2 X136 bnd_a146) &
% 15.14/14.62 bnd_c7_2 X136 bnd_a146 |
% 15.14/14.62 ~ bnd_c7_1 X136) |
% 15.14/14.62 ~ bnd_c10_1 X136))) &
% 15.14/14.62 (((ALL X137.
% 15.14/14.62 bnd_ndr1_0 -->
% 15.14/14.62 (bnd_c5_1 X137 |
% 15.14/14.62 (ALL X138.
% 15.14/14.62 bnd_ndr1_1 X137 -->
% 15.14/14.62 (bnd_c8_2 X137 X138 | bnd_c6_2 X137 X138) |
% 15.14/14.62 ~ bnd_c2_2 X137 X138)) |
% 15.14/14.62 ~ bnd_c1_1 X137) |
% 15.14/14.62 (ALL X139.
% 15.14/14.62 bnd_ndr1_0 -->
% 15.14/14.62 ((ALL X140.
% 15.14/14.62 bnd_ndr1_1 X139 -->
% 15.14/14.62 (~ bnd_c1_2 X139 X140 | ~ bnd_c2_2 X139 X140) |
% 15.14/14.62 ~ bnd_c7_2 X139 X140) |
% 15.14/14.62 (ALL X141.
% 15.14/14.62 bnd_ndr1_1 X139 -->
% 15.14/14.62 (~ bnd_c7_2 X139 X141 | bnd_c10_2 X139 X141) |
% 15.14/14.62 bnd_c2_2 X139 X141)) |
% 15.14/14.62 bnd_c3_1 X139)) |
% 15.14/14.62 bnd_c5_0))
% 15.14/14.62 Adding axioms...
% 15.14/14.63 Typedef.type_definition_def
% 40.87/40.36 ...done.
% 40.87/40.38 Ground types: ?'b, TPTP_Interpret.ind
% 40.87/40.38 Translating term (sizes: 1, 1) ...
% 61.92/61.36 Invoking SAT solver...
% 61.92/61.37 No model exists.
% 61.92/61.37 Translating term (sizes: 2, 1) ...
% 83.59/82.91 Invoking SAT solver...
% 83.59/82.92 No model exists.
% 83.59/82.92 Translating term (sizes: 1, 2) ...
% 123.23/122.43 Invoking SAT solver...
% 123.83/123.00 Model found:
% 123.83/123.00 Size of types: ?'b: 1, TPTP_Interpret.ind: 2
% 123.83/123.00 bnd_a146: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_a145: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_a144: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_a143: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_a142: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_a141: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_a140: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_a139: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_a138: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_a137: ??.TPTP_Interpret.ind1
% 123.83/123.00 bnd_a136: ??.TPTP_Interpret.ind1
% 123.83/123.00 bnd_a135: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_a134: ??.TPTP_Interpret.ind1
% 123.83/123.00 bnd_a133: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_a132: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_a131: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_a130: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_a129: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_a128: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_a127: ??.TPTP_Interpret.ind1
% 123.83/123.00 bnd_a126: ??.TPTP_Interpret.ind1
% 123.83/123.00 bnd_a125: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_a124: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_a123: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_a122: ??.TPTP_Interpret.ind1
% 123.83/123.00 bnd_a121: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_a120: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_a119: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_a118: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_a117: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_a116: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_a115: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_a114: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_a113: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_a112: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_a111: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_a110: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_a109: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_a108: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_a107: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_a106: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_a105: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_a104: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_a103: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_a102: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_a101: ??.TPTP_Interpret.ind1
% 123.83/123.00 bnd_a100: ??.TPTP_Interpret.ind1
% 123.83/123.00 bnd_a99: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_a98: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_a97: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_a96: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_a95: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_a94: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_a93: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_a92: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_a91: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_a90: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_a89: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_a88: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_a87: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_a86: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_a85: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_a84: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_a83: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_a82: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_a81: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_a80: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_a79: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_a78: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_a77: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_a76: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_a75: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_a74: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_a73: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_a72: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_a71: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_a70: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_a69: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_a68: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_a67: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_a66: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_a65: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_a64: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_a63: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_a62: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_a61: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_a60: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_a59: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_a58: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_a57: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_a56: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_a55: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_a54: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_a53: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_a52: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_a51: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_a50: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_a49: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_a48: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_a47: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_a46: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_a45: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_a44: ??.TPTP_Interpret.ind1
% 123.83/123.00 bnd_a43: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_a42: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_a41: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_a40: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_a39: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_a38: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_a37: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_a36: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_c2_1: {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, False)}
% 123.83/123.00 bnd_a35: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_a34: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_a33: ??.TPTP_Interpret.ind1
% 123.83/123.00 bnd_c5_1: {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, True)}
% 123.83/123.00 bnd_a32: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_a31: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_a30: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_a29: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_c5_0: False
% 123.83/123.00 bnd_a28: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_c6_0: False
% 123.83/123.00 bnd_a27: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_a26: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_c9_0: True
% 123.83/123.00 bnd_a25: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_a24: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_a23: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_a22: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_a21: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_a20: ??.TPTP_Interpret.ind1
% 123.83/123.00 bnd_a19: ??.TPTP_Interpret.ind1
% 123.83/123.00 bnd_a18: ??.TPTP_Interpret.ind1
% 123.83/123.00 bnd_a17: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_a16: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_a15: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_c4_0: False
% 123.83/123.00 bnd_c2_0: True
% 123.83/123.00 bnd_c1_0: True
% 123.83/123.00 bnd_c3_0: False
% 123.83/123.00 bnd_a14: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_c8_0: True
% 123.83/123.00 bnd_a13: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_a12: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_a11: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_a10: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_c4_2: {(??.TPTP_Interpret.ind0,
% 123.83/123.00 {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, False)}),
% 123.83/123.00 (??.TPTP_Interpret.ind1,
% 123.83/123.00 {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, False)})}
% 123.83/123.00 bnd_a9: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_c10_2: {(??.TPTP_Interpret.ind0,
% 123.83/123.00 {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, True)}),
% 123.83/123.00 (??.TPTP_Interpret.ind1,
% 123.83/123.00 {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, False)})}
% 123.83/123.00 bnd_c10_0: True
% 123.83/123.00 bnd_c8_2: {(??.TPTP_Interpret.ind0,
% 123.83/123.00 {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, False)}),
% 123.83/123.00 (??.TPTP_Interpret.ind1,
% 123.83/123.00 {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, False)})}
% 123.83/123.00 bnd_c3_1: {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, True)}
% 123.83/123.00 bnd_c7_0: False
% 123.83/123.00 bnd_c8_1: {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, False)}
% 123.83/123.00 bnd_c2_2: {(??.TPTP_Interpret.ind0,
% 123.83/123.00 {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, True)}),
% 123.83/123.00 (??.TPTP_Interpret.ind1,
% 123.83/123.00 {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, True)})}
% 123.83/123.00 bnd_c9_2: {(??.TPTP_Interpret.ind0,
% 123.83/123.00 {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, False)}),
% 123.83/123.00 (??.TPTP_Interpret.ind1,
% 123.83/123.00 {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, True)})}
% 123.83/123.00 bnd_a8: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_a7: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_c4_1: {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, True)}
% 123.83/123.00 bnd_a6: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_c10_1: {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, True)}
% 123.83/123.00 bnd_c7_1: {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, True)}
% 123.83/123.00 bnd_c7_2: {(??.TPTP_Interpret.ind0,
% 123.83/123.00 {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, True)}),
% 123.83/123.00 (??.TPTP_Interpret.ind1,
% 123.83/123.00 {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, True)})}
% 123.83/123.00 bnd_a5: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_c1_1: {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, False)}
% 123.83/123.00 bnd_c1_2: {(??.TPTP_Interpret.ind0,
% 123.83/123.00 {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, False)}),
% 123.83/123.00 (??.TPTP_Interpret.ind1,
% 123.83/123.00 {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, False)})}
% 123.83/123.00 bnd_a4: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_a3: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_c6_1: {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, True)}
% 123.83/123.00 bnd_c9_1: {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, True)}
% 123.83/123.00 bnd_c6_2: {(??.TPTP_Interpret.ind0,
% 123.83/123.00 {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, False)}),
% 123.83/123.00 (??.TPTP_Interpret.ind1,
% 123.83/123.00 {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, False)})}
% 123.83/123.00 bnd_c5_2: {(??.TPTP_Interpret.ind0,
% 123.83/123.00 {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, False)}),
% 123.83/123.00 (??.TPTP_Interpret.ind1,
% 123.83/123.00 {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, False)})}
% 123.83/123.00 bnd_a2: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_c3_2: {(??.TPTP_Interpret.ind0,
% 123.83/123.00 {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, True)}),
% 123.83/123.00 (??.TPTP_Interpret.ind1,
% 123.83/123.00 {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, True)})}
% 123.83/123.00 bnd_a1: ??.TPTP_Interpret.ind0
% 123.83/123.00 bnd_ndr1_1: {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, True)}
% 123.83/123.00 bnd_ndr1_0: True
% 123.83/123.00
% 123.83/123.00 % SZS status CounterSatisfiable
%------------------------------------------------------------------------------