TSTP Solution File: NUM540+1 by SuperZenon---0.0.1
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- Process Solution
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% File : SuperZenon---0.0.1
% Problem : NUM540+1 : TPTP v8.1.0. Released v4.0.0.
% Transfm : none
% Format : tptp:raw
% Command : run_super_zenon -p0 -itptp -om -max-time %d %s
% Computer : n026.cluster.edu
% Model : x86_64 x86_64
% CPU : Intel(R) Xeon(R) CPU E5-2620 v4 2.10GHz
% Memory : 8042.1875MB
% OS : Linux 3.10.0-693.el7.x86_64
% CPULimit : 300s
% WCLimit : 600s
% DateTime : Mon Jul 18 14:43:25 EDT 2022
% Result : Theorem 0.74s 0.96s
% Output : Proof 0.74s
% Verified :
% SZS Type : -
% Comments :
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%----WARNING: Could not form TPTP format derivation
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%----ORIGINAL SYSTEM OUTPUT
% 0.11/0.12 % Problem : NUM540+1 : TPTP v8.1.0. Released v4.0.0.
% 0.11/0.12 % Command : run_super_zenon -p0 -itptp -om -max-time %d %s
% 0.12/0.33 % Computer : n026.cluster.edu
% 0.12/0.33 % Model : x86_64 x86_64
% 0.12/0.33 % CPU : Intel(R) Xeon(R) CPU E5-2620 v4 @ 2.10GHz
% 0.12/0.33 % Memory : 8042.1875MB
% 0.12/0.33 % OS : Linux 3.10.0-693.el7.x86_64
% 0.12/0.33 % CPULimit : 300
% 0.12/0.33 % WCLimit : 600
% 0.12/0.33 % DateTime : Tue Jul 5 21:59:53 EDT 2022
% 0.12/0.33 % CPUTime :
% 0.74/0.96 % SZS status Theorem
% 0.74/0.96 (* PROOF-FOUND *)
% 0.74/0.96 (* BEGIN-PROOF *)
% 0.74/0.96 % SZS output start Proof
% 0.74/0.96 1. ((slcrc0) != (slcrc0)) ### NotEqual
% 0.74/0.96 2. (aElementOf0 (sz00) (szNzAzT0)) (-. (aElementOf0 (sz00) (szNzAzT0))) ### Axiom
% 0.74/0.96 3. (aSet0 (slcrc0)) (-. (aSet0 (slcrc0))) ### Axiom
% 0.74/0.96 4. (aElementOf0 T_0 (szNzAzT0)) (-. (aElementOf0 T_0 (szNzAzT0))) ### Axiom
% 0.74/0.96 5. (sdtlseqdt0 (szszuzczcdt0 T_0) (sz00)) (aElementOf0 T_0 (szNzAzT0)) ### Extension/test/mNoScLessZrctrp 4
% 0.74/0.96 6. ((aElementOf0 T_0 (szNzAzT0)) /\ (sdtlseqdt0 (szszuzczcdt0 T_0) (sz00))) ### And 5
% 0.74/0.96 7. (aElementOf0 T_0 (slcrc0)) (-. (aElementOf0 T_0 (slcrc0))) ### Axiom
% 0.74/0.96 8. (-. (Ex W1, (aElementOf0 W1 (slcrc0)))) (aElementOf0 T_0 (slcrc0)) ### NotExists 7
% 0.74/0.96 9. (-. ((aElementOf0 T_0 (slcrc0)) <=> ((aElementOf0 T_0 (szNzAzT0)) /\ (sdtlseqdt0 (szszuzczcdt0 T_0) (sz00))))) (-. (Ex W1, (aElementOf0 W1 (slcrc0)))) ### NotEquiv 6 8
% 0.74/0.96 10. (-. (All W2, ((aElementOf0 W2 (slcrc0)) <=> ((aElementOf0 W2 (szNzAzT0)) /\ (sdtlseqdt0 (szszuzczcdt0 W2) (sz00)))))) (-. (Ex W1, (aElementOf0 W1 (slcrc0)))) ### NotAllEx 9
% 0.74/0.96 11. (-. ((aSet0 (slcrc0)) /\ (All W2, ((aElementOf0 W2 (slcrc0)) <=> ((aElementOf0 W2 (szNzAzT0)) /\ (sdtlseqdt0 (szszuzczcdt0 W2) (sz00))))))) (-. (Ex W1, (aElementOf0 W1 (slcrc0)))) (aSet0 (slcrc0)) ### NotAnd 3 10
% 0.74/0.96 12. ((slbdtrb0 (sz00)) != (slcrc0)) ((slcrc0) = (slbdtrb0 (sz00))) ### Sym(=)
% 0.74/0.96 13. (((slcrc0) = (slbdtrb0 (sz00))) <=> ((aSet0 (slcrc0)) /\ (All W2, ((aElementOf0 W2 (slcrc0)) <=> ((aElementOf0 W2 (szNzAzT0)) /\ (sdtlseqdt0 (szszuzczcdt0 W2) (sz00))))))) ((slbdtrb0 (sz00)) != (slcrc0)) (aSet0 (slcrc0)) (-. (Ex W1, (aElementOf0 W1 (slcrc0)))) ### Equiv 11 12
% 0.74/0.96 14. (All W1, ((W1 = (slbdtrb0 (sz00))) <=> ((aSet0 W1) /\ (All W2, ((aElementOf0 W2 W1) <=> ((aElementOf0 W2 (szNzAzT0)) /\ (sdtlseqdt0 (szszuzczcdt0 W2) (sz00)))))))) (-. (Ex W1, (aElementOf0 W1 (slcrc0)))) (aSet0 (slcrc0)) ((slbdtrb0 (sz00)) != (slcrc0)) ### All 13
% 0.74/0.96 15. ((aElementOf0 (sz00) (szNzAzT0)) => (All W1, ((W1 = (slbdtrb0 (sz00))) <=> ((aSet0 W1) /\ (All W2, ((aElementOf0 W2 W1) <=> ((aElementOf0 W2 (szNzAzT0)) /\ (sdtlseqdt0 (szszuzczcdt0 W2) (sz00))))))))) ((slbdtrb0 (sz00)) != (slcrc0)) (aSet0 (slcrc0)) (-. (Ex W1, (aElementOf0 W1 (slcrc0)))) (aElementOf0 (sz00) (szNzAzT0)) ### Imply 2 14
% 0.74/0.96 16. (All W0, ((aElementOf0 W0 (szNzAzT0)) => (All W1, ((W1 = (slbdtrb0 W0)) <=> ((aSet0 W1) /\ (All W2, ((aElementOf0 W2 W1) <=> ((aElementOf0 W2 (szNzAzT0)) /\ (sdtlseqdt0 (szszuzczcdt0 W2) W0))))))))) (aElementOf0 (sz00) (szNzAzT0)) (-. (Ex W1, (aElementOf0 W1 (slcrc0)))) (aSet0 (slcrc0)) ((slbdtrb0 (sz00)) != (slcrc0)) ### All 15
% 0.74/0.96 17. ((aSet0 (slcrc0)) /\ (-. (Ex W1, (aElementOf0 W1 (slcrc0))))) ((slbdtrb0 (sz00)) != (slcrc0)) (aElementOf0 (sz00) (szNzAzT0)) (All W0, ((aElementOf0 W0 (szNzAzT0)) => (All W1, ((W1 = (slbdtrb0 W0)) <=> ((aSet0 W1) /\ (All W2, ((aElementOf0 W2 W1) <=> ((aElementOf0 W2 (szNzAzT0)) /\ (sdtlseqdt0 (szszuzczcdt0 W2) W0))))))))) ### And 16
% 0.74/0.96 18. (((slcrc0) = (slcrc0)) <=> ((aSet0 (slcrc0)) /\ (-. (Ex W1, (aElementOf0 W1 (slcrc0)))))) (All W0, ((aElementOf0 W0 (szNzAzT0)) => (All W1, ((W1 = (slbdtrb0 W0)) <=> ((aSet0 W1) /\ (All W2, ((aElementOf0 W2 W1) <=> ((aElementOf0 W2 (szNzAzT0)) /\ (sdtlseqdt0 (szszuzczcdt0 W2) W0))))))))) (aElementOf0 (sz00) (szNzAzT0)) ((slbdtrb0 (sz00)) != (slcrc0)) ### Equiv 1 17
% 0.74/0.96 19. (All W0, ((W0 = (slcrc0)) <=> ((aSet0 W0) /\ (-. (Ex W1, (aElementOf0 W1 W0)))))) ((slbdtrb0 (sz00)) != (slcrc0)) (aElementOf0 (sz00) (szNzAzT0)) (All W0, ((aElementOf0 W0 (szNzAzT0)) => (All W1, ((W1 = (slbdtrb0 W0)) <=> ((aSet0 W1) /\ (All W2, ((aElementOf0 W2 W1) <=> ((aElementOf0 W2 (szNzAzT0)) /\ (sdtlseqdt0 (szszuzczcdt0 W2) W0))))))))) ### All 18
% 0.74/0.96 % SZS output end Proof
% 0.74/0.96 (* END-PROOF *)
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