TSTP Solution File: HWV095+1 by SuperZenon---0.0.1
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- Process Solution
%------------------------------------------------------------------------------
% File : SuperZenon---0.0.1
% Problem : HWV095+1 : TPTP v8.1.0. Released v6.1.0.
% Transfm : none
% Format : tptp:raw
% Command : run_super_zenon -p0 -itptp -om -max-time %d %s
% Computer : n013.cluster.edu
% Model : x86_64 x86_64
% CPU : Intel(R) Xeon(R) CPU E5-2620 v4 2.10GHz
% Memory : 8042.1875MB
% OS : Linux 3.10.0-693.el7.x86_64
% CPULimit : 300s
% WCLimit : 600s
% DateTime : Sat Jul 16 19:19:30 EDT 2022
% Result : Theorem 31.04s 31.26s
% Output : Proof 31.04s
% Verified :
% SZS Type : -
% Comments :
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%----WARNING: Could not form TPTP format derivation
%------------------------------------------------------------------------------
%----ORIGINAL SYSTEM OUTPUT
% 0.04/0.13 % Problem : HWV095+1 : TPTP v8.1.0. Released v6.1.0.
% 0.04/0.14 % Command : run_super_zenon -p0 -itptp -om -max-time %d %s
% 0.14/0.35 % Computer : n013.cluster.edu
% 0.14/0.35 % Model : x86_64 x86_64
% 0.14/0.35 % CPU : Intel(R) Xeon(R) CPU E5-2620 v4 @ 2.10GHz
% 0.14/0.35 % Memory : 8042.1875MB
% 0.14/0.35 % OS : Linux 3.10.0-693.el7.x86_64
% 0.14/0.35 % CPULimit : 300
% 0.14/0.35 % WCLimit : 600
% 0.14/0.35 % DateTime : Fri Jun 17 09:44:59 EDT 2022
% 0.14/0.35 % CPUTime :
% 31.04/31.26 % SZS status Theorem
% 31.04/31.26 (* PROOF-FOUND *)
% 31.04/31.26 (* BEGIN-PROOF *)
% 31.04/31.26 % SZS output start Proof
% 31.04/31.26 1. (-. (v998 T_0)) (v998 T_0) ### Axiom
% 31.04/31.26 2. (-. (-. (v998 T_0))) (-. (v998 T_0)) ### NotNot 1
% 31.04/31.26 3. (v999 T_0) (-. (v999 T_0)) ### Axiom
% 31.04/31.26 4. (v1000 T_0 (bitIndex0)) (-. (v1000 T_0 (bitIndex0))) ### Axiom
% 31.04/31.26 5. (v1007 T_0 (bitIndex5)) (-. (v1007 T_0 (bitIndex5))) ### Axiom
% 31.04/31.26 6. (All VarCurr, (-. (v1007 VarCurr (bitIndex5)))) (v1007 T_0 (bitIndex5)) ### All 5
% 31.04/31.26 7. ((v1003 T_0) /\ (v1007 T_0 (bitIndex5))) (All VarCurr, (-. (v1007 VarCurr (bitIndex5)))) ### And 6
% 31.04/31.26 8. (v1001 T_0) (All VarCurr, (-. (v1007 VarCurr (bitIndex5)))) ### Definition-Pseudo(v1001) 7
% 31.04/31.26 9. ((v1000 T_0 (bitIndex0)) <=> (v1001 T_0)) (All VarCurr, (-. (v1007 VarCurr (bitIndex5)))) (v1000 T_0 (bitIndex0)) ### Equiv 4 8
% 31.04/31.26 10. (All VarCurr, ((v1000 VarCurr (bitIndex0)) <=> (v1001 VarCurr))) (v1000 T_0 (bitIndex0)) (All VarCurr, (-. (v1007 VarCurr (bitIndex5)))) ### All 9
% 31.04/31.26 11. ((v1000 T_0 (bitIndex0)) /\ (v1000 T_0 (bitIndex1))) (All VarCurr, (-. (v1007 VarCurr (bitIndex5)))) (All VarCurr, ((v1000 VarCurr (bitIndex0)) <=> (v1001 VarCurr))) ### And 10
% 31.04/31.26 12. ((v999 T_0) <=> ((v1000 T_0 (bitIndex0)) /\ (v1000 T_0 (bitIndex1)))) (All VarCurr, ((v1000 VarCurr (bitIndex0)) <=> (v1001 VarCurr))) (All VarCurr, (-. (v1007 VarCurr (bitIndex5)))) (v999 T_0) ### Equiv 3 11
% 31.04/31.26 13. (All VarCurr, ((v999 VarCurr) <=> ((v1000 VarCurr (bitIndex0)) /\ (v1000 VarCurr (bitIndex1))))) (v999 T_0) (All VarCurr, (-. (v1007 VarCurr (bitIndex5)))) (All VarCurr, ((v1000 VarCurr (bitIndex0)) <=> (v1001 VarCurr))) ### All 12
% 31.04/31.26 14. ((-. (v998 T_0)) <=> (v999 T_0)) (All VarCurr, ((v1000 VarCurr (bitIndex0)) <=> (v1001 VarCurr))) (All VarCurr, (-. (v1007 VarCurr (bitIndex5)))) (All VarCurr, ((v999 VarCurr) <=> ((v1000 VarCurr (bitIndex0)) /\ (v1000 VarCurr (bitIndex1))))) (-. (v998 T_0)) ### Equiv 2 13
% 31.04/31.26 15. (All VarCurr, ((-. (v998 VarCurr)) <=> (v999 VarCurr))) (-. (v998 T_0)) (All VarCurr, ((v999 VarCurr) <=> ((v1000 VarCurr (bitIndex0)) /\ (v1000 VarCurr (bitIndex1))))) (All VarCurr, (-. (v1007 VarCurr (bitIndex5)))) (All VarCurr, ((v1000 VarCurr (bitIndex0)) <=> (v1001 VarCurr))) ### All 14
% 31.04/31.26 16. (-. True) ### NotTrue
% 31.04/31.26 17. (-. (v1000 T_0 (bitIndex1))) (v1000 T_0 (bitIndex1)) ### Axiom
% 31.04/31.26 18. ((v1000 T_0 (bitIndex1)) <=> True) (-. (v1000 T_0 (bitIndex1))) ### Equiv 16 17
% 31.04/31.26 19. (All VarCurr, ((v1000 VarCurr (bitIndex1)) <=> True)) (-. (v1000 T_0 (bitIndex1))) ### All 18
% 31.04/31.26 20. (-. ((v1000 T_0 (bitIndex0)) \/ (v1000 T_0 (bitIndex1)))) (All VarCurr, ((v1000 VarCurr (bitIndex1)) <=> True)) ### NotOr 19
% 31.04/31.26 21. (-. (v1010 T_0)) (All VarCurr, ((v1000 VarCurr (bitIndex1)) <=> True)) ### Definition-Pseudo(v1010) 20
% 31.04/31.26 22. (-. ((v998 T_0) /\ (v1010 T_0))) (All VarCurr, ((v1000 VarCurr (bitIndex1)) <=> True)) (All VarCurr, ((v1000 VarCurr (bitIndex0)) <=> (v1001 VarCurr))) (All VarCurr, (-. (v1007 VarCurr (bitIndex5)))) (All VarCurr, ((v999 VarCurr) <=> ((v1000 VarCurr (bitIndex0)) /\ (v1000 VarCurr (bitIndex1))))) (All VarCurr, ((-. (v998 VarCurr)) <=> (v999 VarCurr))) ### NotAnd 15 21
% 31.04/31.26 23. (-. (v996 T_0)) (v996 T_0) ### Axiom
% 31.04/31.26 24. ((v996 T_0) <=> ((v998 T_0) /\ (v1010 T_0))) (-. (v996 T_0)) (All VarCurr, ((-. (v998 VarCurr)) <=> (v999 VarCurr))) (All VarCurr, ((v999 VarCurr) <=> ((v1000 VarCurr (bitIndex0)) /\ (v1000 VarCurr (bitIndex1))))) (All VarCurr, (-. (v1007 VarCurr (bitIndex5)))) (All VarCurr, ((v1000 VarCurr (bitIndex0)) <=> (v1001 VarCurr))) (All VarCurr, ((v1000 VarCurr (bitIndex1)) <=> True)) ### Equiv 22 23
% 31.04/31.26 25. (All VarCurr, ((v996 VarCurr) <=> ((v998 VarCurr) /\ (v1010 VarCurr)))) (All VarCurr, ((v1000 VarCurr (bitIndex1)) <=> True)) (All VarCurr, ((v1000 VarCurr (bitIndex0)) <=> (v1001 VarCurr))) (All VarCurr, (-. (v1007 VarCurr (bitIndex5)))) (All VarCurr, ((v999 VarCurr) <=> ((v1000 VarCurr (bitIndex0)) /\ (v1000 VarCurr (bitIndex1))))) (All VarCurr, ((-. (v998 VarCurr)) <=> (v999 VarCurr))) (-. (v996 T_0)) ### All 24
% 31.04/31.26 26. (-. (v4 T_0)) (v4 T_0) ### Axiom
% 31.04/31.26 27. (-. (-. (v4 T_0))) (-. (v4 T_0)) ### NotNot 26
% 31.04/31.26 28. (-. (v995 T_0)) (-. (v4 T_0)) ### Definition-Pseudo(v995) 27
% 31.04/31.26 29. ((-. (v995 T_0)) <=> (v996 T_0)) (-. (v4 T_0)) (All VarCurr, ((-. (v998 VarCurr)) <=> (v999 VarCurr))) (All VarCurr, ((v999 VarCurr) <=> ((v1000 VarCurr (bitIndex0)) /\ (v1000 VarCurr (bitIndex1))))) (All VarCurr, (-. (v1007 VarCurr (bitIndex5)))) (All VarCurr, ((v1000 VarCurr (bitIndex0)) <=> (v1001 VarCurr))) (All VarCurr, ((v1000 VarCurr (bitIndex1)) <=> True)) (All VarCurr, ((v996 VarCurr) <=> ((v998 VarCurr) /\ (v1010 VarCurr)))) ### Equiv 25 28
% 31.04/31.26 30. (All VarCurr, ((-. (v995 VarCurr)) <=> (v996 VarCurr))) (All VarCurr, ((v996 VarCurr) <=> ((v998 VarCurr) /\ (v1010 VarCurr)))) (All VarCurr, ((v1000 VarCurr (bitIndex1)) <=> True)) (All VarCurr, ((v1000 VarCurr (bitIndex0)) <=> (v1001 VarCurr))) (All VarCurr, (-. (v1007 VarCurr (bitIndex5)))) (All VarCurr, ((v999 VarCurr) <=> ((v1000 VarCurr (bitIndex0)) /\ (v1000 VarCurr (bitIndex1))))) (All VarCurr, ((-. (v998 VarCurr)) <=> (v999 VarCurr))) (-. (v4 T_0)) ### All 29
% 31.04/31.26 31. (-. ((reachableState T_0) => (v4 T_0))) (All VarCurr, ((-. (v998 VarCurr)) <=> (v999 VarCurr))) (All VarCurr, ((v999 VarCurr) <=> ((v1000 VarCurr (bitIndex0)) /\ (v1000 VarCurr (bitIndex1))))) (All VarCurr, (-. (v1007 VarCurr (bitIndex5)))) (All VarCurr, ((v1000 VarCurr (bitIndex0)) <=> (v1001 VarCurr))) (All VarCurr, ((v1000 VarCurr (bitIndex1)) <=> True)) (All VarCurr, ((v996 VarCurr) <=> ((v998 VarCurr) /\ (v1010 VarCurr)))) (All VarCurr, ((-. (v995 VarCurr)) <=> (v996 VarCurr))) ### NotImply 30
% 31.04/31.26 32. (-. (All VarCurr, ((reachableState VarCurr) => (v4 VarCurr)))) (All VarCurr, ((-. (v995 VarCurr)) <=> (v996 VarCurr))) (All VarCurr, ((v996 VarCurr) <=> ((v998 VarCurr) /\ (v1010 VarCurr)))) (All VarCurr, ((v1000 VarCurr (bitIndex1)) <=> True)) (All VarCurr, ((v1000 VarCurr (bitIndex0)) <=> (v1001 VarCurr))) (All VarCurr, (-. (v1007 VarCurr (bitIndex5)))) (All VarCurr, ((v999 VarCurr) <=> ((v1000 VarCurr (bitIndex0)) /\ (v1000 VarCurr (bitIndex1))))) (All VarCurr, ((-. (v998 VarCurr)) <=> (v999 VarCurr))) ### NotAllEx 31
% 31.04/31.26 % SZS output end Proof
% 31.04/31.26 (* END-PROOF *)
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