TSTP Solution File: HWV048_1 by Refute---2015
View Problem
- Process Solution
%------------------------------------------------------------------------------
% File : Refute---2015
% Problem : HWV048_1 : TPTP v6.4.0. Released v5.3.0.
% Transfm : none
% Format : tptp:raw
% Command : isabelle tptp_refute %d %s
% Computer : n058.star.cs.uiowa.edu
% Model : x86_64 x86_64
% CPU : Intel(R) Xeon(R) CPU E5-2609 0 2.40GHz
% Memory : 32218.75MB
% OS : Linux 3.10.0-327.10.1.el7.x86_64
% CPULimit : 300s
% DateTime : Tue Apr 12 15:34:40 EDT 2016
% Result : Timeout 300.07s
% Output : None
% Verified :
% SZS Type : None (Parsing solution fails)
% Syntax : Number of formulae : 0
% Comments :
%------------------------------------------------------------------------------
%----No solution output by system
%------------------------------------------------------------------------------
%----ORIGINAL SYSTEM OUTPUT
% 0.00/0.03 % Problem : HWV048_1 : TPTP v6.4.0. Released v5.3.0.
% 0.00/0.04 % Command : isabelle tptp_refute %d %s
% 0.03/0.23 % Computer : n058.star.cs.uiowa.edu
% 0.03/0.23 % Model : x86_64 x86_64
% 0.03/0.23 % CPU : Intel(R) Xeon(R) CPU E5-2609 0 @ 2.40GHz
% 0.03/0.23 % Memory : 32218.75MB
% 0.03/0.23 % OS : Linux 3.10.0-327.10.1.el7.x86_64
% 0.03/0.23 % CPULimit : 300
% 0.03/0.23 % DateTime : Sat Apr 9 23:41:09 CDT 2016
% 0.03/0.23 % CPUTime :
% 6.33/5.90 > val it = (): unit
% 7.53/7.16 Trying to find a model that refutes: bnd_reachableState VarCurr --> bnd_v82 VarCurr
% 18.65/18.27 Unfolded term: [| ALL VarNext VarCurr.
% 18.65/18.27 bnd_nextState (VarCurr, VarNext) --> bnd_v13 VarNext = bnd_v9 VarCurr;
% 18.65/18.27 ALL VarNext. True --> bnd_v6 VarNext = bnd_v13 VarNext;
% 18.65/18.27 ALL VarNext VarCurr.
% 18.65/18.27 bnd_nextState (VarCurr, VarNext) -->
% 18.65/18.27 ~ True --> bnd_v6 VarNext = bnd_v6 VarCurr;
% 18.65/18.27 ALL VarCurr. (~ bnd_v20 VarCurr) = bnd_v1 VarCurr;
% 18.65/18.27 ALL VarCurr. (~ bnd_v21 VarCurr) = bnd_v6 VarCurr;
% 18.65/18.27 ALL VarCurr. bnd_v19 VarCurr = (bnd_v20 VarCurr | bnd_v21 VarCurr);
% 18.65/18.27 ALL VarCurr. bnd_v22 VarCurr = (bnd_v1 VarCurr | bnd_v6 VarCurr);
% 18.65/18.27 ALL VarCurr. bnd_v18 VarCurr = (bnd_v19 VarCurr & bnd_v22 VarCurr);
% 18.65/18.27 ALL VarCurr. (~ bnd_v4 VarCurr) = bnd_v18 VarCurr;
% 18.65/18.27 ALL VarCurr. bnd_v26 VarCurr = False; bnd_v31 bnd_constB0;
% 18.65/18.27 ALL VarCurr. (~ bnd_v39 VarCurr) = bnd_v1 VarCurr;
% 18.65/18.27 ALL VarCurr. bnd_v38 VarCurr = (bnd_v39 VarCurr & bnd_v9 VarCurr);
% 18.65/18.27 ALL VarCurr. (~ bnd_v37 VarCurr) = bnd_v38 VarCurr;
% 18.65/18.27 ALL VarCurr. bnd_v34 VarCurr = (bnd_v37 VarCurr & bnd_v31 VarCurr);
% 18.65/18.27 ALL VarNext VarCurr.
% 18.65/18.27 bnd_nextState (VarCurr, VarNext) -->
% 18.65/18.27 bnd_v36 VarNext = bnd_v34 VarCurr;
% 18.65/18.27 ALL VarNext. True --> bnd_v31 VarNext = bnd_v36 VarNext;
% 18.65/18.27 ALL VarNext VarCurr.
% 18.65/18.27 bnd_nextState (VarCurr, VarNext) -->
% 18.65/18.27 ~ True --> bnd_v31 VarNext = bnd_v31 VarCurr;
% 18.65/18.27 ~ bnd_v29 bnd_constB0;
% 18.65/18.27 ALL VarCurr. bnd_v47 VarCurr = (bnd_v37 VarCurr & bnd_v29 VarCurr);
% 18.65/18.27 ALL VarCurr. bnd_v49 VarCurr = (bnd_v38 VarCurr & bnd_v26 VarCurr);
% 18.65/18.27 ALL VarCurr. bnd_v48 VarCurr = (bnd_v49 VarCurr & bnd_v31 VarCurr);
% 18.65/18.27 ALL VarCurr. bnd_v44 VarCurr = (bnd_v47 VarCurr | bnd_v48 VarCurr);
% 18.65/18.27 ALL VarNext VarCurr.
% 18.65/18.27 bnd_nextState (VarCurr, VarNext) -->
% 18.65/18.27 bnd_v46 VarNext = bnd_v44 VarCurr;
% 18.65/18.27 ALL VarNext. True --> bnd_v29 VarNext = bnd_v46 VarNext;
% 18.65/18.27 ALL VarNext VarCurr.
% 18.65/18.27 bnd_nextState (VarCurr, VarNext) -->
% 18.65/18.27 ~ True --> bnd_v29 VarNext = bnd_v29 VarCurr;
% 18.65/18.27 ALL VarCurr. (~ bnd_v56 VarCurr) = bnd_v26 VarCurr;
% 18.65/18.27 ALL VarCurr. (~ bnd_v55 VarCurr) = bnd_v56 VarCurr;
% 18.65/18.27 ALL VarCurr. bnd_v54 VarCurr = (bnd_v55 VarCurr & bnd_v38 VarCurr);
% 18.65/18.27 ALL VarCurr. bnd_v53 VarCurr = (bnd_v54 VarCurr & bnd_v29 VarCurr);
% 18.65/18.28 ALL VarCurr. (~ bnd_v24 VarCurr) = bnd_v53 VarCurr;
% 18.65/18.28 ALL VarCurr. bnd_v64 VarCurr = (~ bnd_v9 VarCurr = bnd_v1 VarCurr);
% 18.65/18.28 ALL VarCurr. bnd_v63 VarCurr = (True & bnd_v64 VarCurr);
% 18.65/18.28 ALL VarNext VarCurr.
% 18.65/18.28 bnd_nextState (VarCurr, VarNext) -->
% 18.65/18.28 bnd_v66 VarNext = bnd_v26 VarCurr;
% 18.65/18.28 ALL VarNext. bnd_v63 VarNext --> bnd_v60 VarNext = bnd_v66 VarNext;
% 18.65/18.28 ALL VarNext VarCurr.
% 18.65/18.28 bnd_nextState (VarCurr, VarNext) -->
% 18.65/18.28 ~ bnd_v63 VarNext --> bnd_v60 VarNext = bnd_v60 VarCurr;
% 18.65/18.28 ALL VarCurr. bnd_v74 VarCurr = (bnd_v26 VarCurr = bnd_v60 VarCurr);
% 18.65/18.28 ALL VarCurr. (~ bnd_v73 VarCurr) = bnd_v74 VarCurr;
% 18.65/18.28 ALL VarCurr. (~ bnd_v75 VarCurr) = bnd_v1 VarCurr;
% 18.65/18.28 ALL VarCurr. bnd_v72 VarCurr = (bnd_v73 VarCurr & bnd_v75 VarCurr);
% 18.65/18.28 ALL VarCurr. (~ bnd_v79 VarCurr) = bnd_v9 VarCurr;
% 18.65/18.28 ALL VarCurr. bnd_v78 VarCurr = (bnd_v20 VarCurr | bnd_v79 VarCurr);
% 18.65/18.28 ALL VarCurr. bnd_v80 VarCurr = (bnd_v1 VarCurr | bnd_v9 VarCurr);
% 18.65/18.28 ALL VarCurr. bnd_v76 VarCurr = (bnd_v78 VarCurr & bnd_v80 VarCurr);
% 18.65/18.28 ALL VarCurr. bnd_v71 VarCurr = (bnd_v72 VarCurr & bnd_v76 VarCurr);
% 18.65/18.28 ALL VarCurr. (~ bnd_v58 VarCurr) = bnd_v71 VarCurr;
% 18.65/18.28 ~ bnd_v90 (bnd_constB0, bnd_bitIndex0);
% 18.65/18.28 ~ bnd_v90 (bnd_constB0, bnd_bitIndex1);
% 18.65/18.28 ~ bnd_v90 (bnd_constB0, bnd_bitIndex2);
% 18.65/18.28 ALL VarNext VarCurr.
% 18.65/18.28 bnd_nextState (VarCurr, VarNext) -->
% 18.65/18.28 bnd_v104 VarNext = bnd_v1 VarCurr;
% 18.65/18.28 ALL VarNext VarCurr.
% 18.65/18.28 bnd_nextState (VarCurr, VarNext) -->
% 18.65/18.28 (~ bnd_v102 VarNext) = bnd_v104 VarNext;
% 18.65/18.28 ALL VarNext VarCurr.
% 18.65/18.28 bnd_nextState (VarCurr, VarNext) -->
% 18.65/18.28 bnd_v101 VarNext = (bnd_v102 VarNext & bnd_v1 VarNext);
% 18.65/18.28 ALL VarCurr. bnd_v111 VarCurr = (bnd_v26 VarCurr = True);
% 18.65/18.28 ALL VarCurr.
% 18.65/18.28 bnd_v119 VarCurr =
% 18.65/18.28 ((bnd_v90 (VarCurr, bnd_bitIndex2) = False &
% 18.65/18.28 bnd_v90 (VarCurr, bnd_bitIndex1) = False) &
% 18.65/18.28 bnd_v90 (VarCurr, bnd_bitIndex0) = False);
% 18.65/18.28 ALL VarCurr.
% 18.65/18.28 bnd_v120 VarCurr =
% 18.65/18.28 ((bnd_v90 (VarCurr, bnd_bitIndex2) = False &
% 18.65/18.28 bnd_v90 (VarCurr, bnd_bitIndex1) = False) &
% 18.65/18.28 bnd_v90 (VarCurr, bnd_bitIndex0) = True);
% 18.65/18.28 ALL VarCurr. bnd_v118 VarCurr = (bnd_v119 VarCurr | bnd_v120 VarCurr);
% 18.65/18.28 ALL VarCurr.
% 18.65/18.28 bnd_v121 VarCurr =
% 18.65/18.28 ((bnd_v90 (VarCurr, bnd_bitIndex2) = False &
% 18.65/18.28 bnd_v90 (VarCurr, bnd_bitIndex1) = True) &
% 18.65/18.28 bnd_v90 (VarCurr, bnd_bitIndex0) = False);
% 18.65/18.28 ALL VarCurr. bnd_v117 VarCurr = (bnd_v118 VarCurr | bnd_v121 VarCurr);
% 18.65/18.28 ALL VarCurr.
% 18.65/18.28 bnd_v122 VarCurr =
% 18.65/18.28 ((bnd_v90 (VarCurr, bnd_bitIndex2) = False &
% 18.65/18.28 bnd_v90 (VarCurr, bnd_bitIndex1) = True) &
% 18.65/18.28 bnd_v90 (VarCurr, bnd_bitIndex0) = True);
% 18.65/18.28 ALL VarCurr. bnd_v116 VarCurr = (bnd_v117 VarCurr | bnd_v122 VarCurr);
% 18.65/18.28 ALL VarCurr.
% 18.65/18.28 bnd_v123 VarCurr =
% 18.65/18.28 ((bnd_v90 (VarCurr, bnd_bitIndex2) = True &
% 18.65/18.28 bnd_v90 (VarCurr, bnd_bitIndex1) = False) &
% 18.65/18.28 bnd_v90 (VarCurr, bnd_bitIndex0) = False);
% 18.65/18.28 ALL VarCurr. bnd_v115 VarCurr = (bnd_v116 VarCurr | bnd_v123 VarCurr);
% 18.65/18.28 ALL VarCurr.
% 18.65/18.28 bnd_v124 VarCurr =
% 18.65/18.28 ((bnd_v90 (VarCurr, bnd_bitIndex2) = True &
% 18.65/18.28 bnd_v90 (VarCurr, bnd_bitIndex1) = False) &
% 18.65/18.28 bnd_v90 (VarCurr, bnd_bitIndex0) = True);
% 18.65/18.28 ALL VarCurr. bnd_v114 VarCurr = (bnd_v115 VarCurr | bnd_v124 VarCurr);
% 18.65/18.28 ALL VarCurr.
% 18.65/18.28 bnd_v125 VarCurr =
% 18.65/18.28 ((bnd_v90 (VarCurr, bnd_bitIndex2) = True &
% 18.65/18.28 bnd_v90 (VarCurr, bnd_bitIndex1) = True) &
% 18.65/18.28 bnd_v90 (VarCurr, bnd_bitIndex0) = False);
% 18.65/18.28 ALL VarCurr. bnd_v113 VarCurr = (bnd_v114 VarCurr | bnd_v125 VarCurr);
% 18.65/18.28 ALL VarCurr. (~ bnd_v126 VarCurr) = bnd_v111 VarCurr;
% 18.65/18.28 ALL VarCurr. bnd_v112 VarCurr = (bnd_v113 VarCurr & bnd_v126 VarCurr);
% 18.65/18.28 ALL VarCurr. bnd_v108 VarCurr = (bnd_v111 VarCurr | bnd_v112 VarCurr);
% 18.65/18.28 ALL VarNext VarCurr.
% 18.65/18.28 bnd_nextState (VarCurr, VarNext) -->
% 18.65/18.28 bnd_v110 VarNext = bnd_v108 VarCurr;
% 18.65/18.28 ALL VarNext VarCurr.
% 18.65/18.28 bnd_nextState (VarCurr, VarNext) -->
% 18.65/18.28 bnd_v100 VarNext = (bnd_v101 VarNext & bnd_v110 VarNext);
% 18.65/18.28 ALL VarCurr.
% 18.65/18.28 bnd_v119 VarCurr -->
% 18.65/18.28 (bnd_v130 (VarCurr, bnd_bitIndex2) = True &
% 18.65/18.28 bnd_v130 (VarCurr, bnd_bitIndex1) = False) &
% 18.65/18.28 bnd_v130 (VarCurr, bnd_bitIndex0) = False;
% 18.65/18.28 ALL VarCurr.
% 18.65/18.28 bnd_v120 VarCurr -->
% 18.65/18.28 (bnd_v130 (VarCurr, bnd_bitIndex2) = False &
% 18.65/18.28 bnd_v130 (VarCurr, bnd_bitIndex1) = True) &
% 18.65/18.28 bnd_v130 (VarCurr, bnd_bitIndex0) = False;
% 18.65/18.28 ALL VarCurr.
% 18.65/18.28 bnd_v121 VarCurr -->
% 18.65/18.28 (bnd_v130 (VarCurr, bnd_bitIndex2) = False &
% 18.65/18.28 bnd_v130 (VarCurr, bnd_bitIndex1) = True) &
% 18.65/18.28 bnd_v130 (VarCurr, bnd_bitIndex0) = True;
% 18.65/18.28 ALL VarCurr.
% 18.65/18.28 bnd_v122 VarCurr -->
% 18.65/18.28 (bnd_v130 (VarCurr, bnd_bitIndex2) = True &
% 18.65/18.28 bnd_v130 (VarCurr, bnd_bitIndex1) = False) &
% 18.65/18.28 bnd_v130 (VarCurr, bnd_bitIndex0) = False;
% 18.65/18.28 ALL VarCurr.
% 18.65/18.28 bnd_v123 VarCurr -->
% 18.65/18.28 (bnd_v130 (VarCurr, bnd_bitIndex2) = True &
% 18.65/18.28 bnd_v130 (VarCurr, bnd_bitIndex1) = True) &
% 18.65/18.28 bnd_v130 (VarCurr, bnd_bitIndex0) = False;
% 18.65/18.28 ALL VarCurr.
% 18.65/18.28 bnd_v124 VarCurr -->
% 18.65/18.28 (bnd_v130 (VarCurr, bnd_bitIndex2) = False &
% 18.65/18.28 bnd_v130 (VarCurr, bnd_bitIndex1) = True) &
% 18.65/18.28 bnd_v130 (VarCurr, bnd_bitIndex0) = True;
% 18.65/18.28 ALL VarCurr.
% 18.65/18.28 ((((~ bnd_v119 VarCurr & ~ bnd_v120 VarCurr) & ~ bnd_v121 VarCurr) &
% 18.65/18.28 ~ bnd_v122 VarCurr) &
% 18.65/18.28 ~ bnd_v123 VarCurr) &
% 18.65/18.28 ~ bnd_v124 VarCurr -->
% 18.65/18.28 (bnd_v130 (VarCurr, bnd_bitIndex2) = False &
% 18.65/18.28 bnd_v130 (VarCurr, bnd_bitIndex1) = False) &
% 18.65/18.28 bnd_v130 (VarCurr, bnd_bitIndex0) = True;
% 18.65/18.28 ALL VarCurr.
% 18.65/18.28 bnd_v111 VarCurr -->
% 18.65/18.28 (bnd_v127 (VarCurr, bnd_bitIndex2) = False &
% 18.65/18.28 bnd_v127 (VarCurr, bnd_bitIndex1) = False) &
% 18.65/18.28 bnd_v127 (VarCurr, bnd_bitIndex0) = False;
% 18.65/18.28 ALL VarCurr.
% 18.65/18.28 ~ bnd_v111 VarCurr -->
% 18.65/18.28 (bnd_v127 (VarCurr, bnd_bitIndex2) =
% 18.65/18.28 bnd_v130 (VarCurr, bnd_bitIndex2) &
% 18.65/18.28 bnd_v127 (VarCurr, bnd_bitIndex1) =
% 18.65/18.28 bnd_v130 (VarCurr, bnd_bitIndex1)) &
% 18.65/18.28 bnd_v127 (VarCurr, bnd_bitIndex0) = bnd_v130 (VarCurr, bnd_bitIndex0);
% 18.65/18.28 ALL VarNext VarCurr.
% 18.65/18.28 bnd_nextState (VarCurr, VarNext) -->
% 18.65/18.28 (bnd_v129 (VarNext, bnd_bitIndex2) =
% 18.65/18.28 bnd_v127 (VarCurr, bnd_bitIndex2) &
% 18.65/18.28 bnd_v129 (VarNext, bnd_bitIndex1) =
% 18.65/18.28 bnd_v127 (VarCurr, bnd_bitIndex1)) &
% 18.65/18.28 bnd_v129 (VarNext, bnd_bitIndex0) = bnd_v127 (VarCurr, bnd_bitIndex0);
% 18.65/18.28 ALL VarNext.
% 18.65/18.28 bnd_v100 VarNext -->
% 18.65/18.28 (bnd_v90 (VarNext, bnd_bitIndex2) =
% 18.65/18.28 bnd_v129 (VarNext, bnd_bitIndex2) &
% 18.65/18.28 bnd_v90 (VarNext, bnd_bitIndex1) =
% 18.65/18.28 bnd_v129 (VarNext, bnd_bitIndex1)) &
% 18.65/18.28 bnd_v90 (VarNext, bnd_bitIndex0) = bnd_v129 (VarNext, bnd_bitIndex0);
% 18.65/18.28 ALL VarNext VarCurr.
% 18.65/18.28 bnd_nextState (VarCurr, VarNext) -->
% 18.65/18.28 ~ bnd_v100 VarNext -->
% 18.65/18.28 (bnd_v90 (VarNext, bnd_bitIndex2) = bnd_v90 (VarCurr, bnd_bitIndex2) &
% 18.65/18.28 bnd_v90 (VarNext, bnd_bitIndex1) =
% 18.65/18.28 bnd_v90 (VarCurr, bnd_bitIndex1)) &
% 18.65/18.28 bnd_v90 (VarNext, bnd_bitIndex0) = bnd_v90 (VarCurr, bnd_bitIndex0);
% 18.65/18.28 ALL VarCurr.
% 18.65/18.28 (bnd_v88 (VarCurr, bnd_bitIndex2) = bnd_v90 (VarCurr, bnd_bitIndex2) &
% 18.65/18.28 bnd_v88 (VarCurr, bnd_bitIndex1) =
% 18.65/18.28 bnd_v90 (VarCurr, bnd_bitIndex1)) &
% 18.65/18.28 bnd_v88 (VarCurr, bnd_bitIndex0) = bnd_v90 (VarCurr, bnd_bitIndex0);
% 18.65/18.28 ~ bnd_v86 bnd_constB0;
% 18.65/18.28 ALL VarCurr.
% 18.65/18.28 bnd_v139 VarCurr =
% 18.65/18.28 ((bnd_v88 (VarCurr, bnd_bitIndex2) = False &
% 18.65/18.28 bnd_v88 (VarCurr, bnd_bitIndex1) = False) &
% 18.65/18.28 bnd_v88 (VarCurr, bnd_bitIndex0) = False);
% 18.65/18.28 ALL VarCurr.
% 18.65/18.28 bnd_v140 VarCurr =
% 18.65/18.28 ((bnd_v88 (VarCurr, bnd_bitIndex2) = False &
% 18.65/18.28 bnd_v88 (VarCurr, bnd_bitIndex1) = False) &
% 18.65/18.28 bnd_v88 (VarCurr, bnd_bitIndex0) = True);
% 18.65/18.28 ALL VarCurr. bnd_v138 VarCurr = (bnd_v139 VarCurr | bnd_v140 VarCurr);
% 18.65/18.28 ALL VarCurr.
% 18.65/18.28 bnd_v141 VarCurr =
% 18.65/18.28 ((bnd_v88 (VarCurr, bnd_bitIndex2) = False &
% 18.65/18.28 bnd_v88 (VarCurr, bnd_bitIndex1) = True) &
% 18.65/18.28 bnd_v88 (VarCurr, bnd_bitIndex0) = True);
% 18.65/18.28 ALL VarCurr. bnd_v137 VarCurr = (bnd_v138 VarCurr | bnd_v141 VarCurr);
% 18.65/18.28 ALL VarCurr.
% 18.65/18.28 bnd_v143 VarCurr =
% 18.65/18.28 ((bnd_v88 (VarCurr, bnd_bitIndex2) = False &
% 18.65/18.28 bnd_v88 (VarCurr, bnd_bitIndex1) = True) &
% 18.65/18.28 bnd_v88 (VarCurr, bnd_bitIndex0) = False);
% 18.65/18.28 ALL VarCurr.
% 18.65/18.28 bnd_v144 VarCurr =
% 18.65/18.28 ((bnd_v88 (VarCurr, bnd_bitIndex2) = True &
% 18.65/18.28 bnd_v88 (VarCurr, bnd_bitIndex1) = True) &
% 18.65/18.28 bnd_v88 (VarCurr, bnd_bitIndex0) = False);
% 18.65/18.28 ALL VarCurr. bnd_v142 VarCurr = (bnd_v143 VarCurr | bnd_v144 VarCurr);
% 18.65/18.28 ALL VarCurr. bnd_v136 VarCurr = (bnd_v137 VarCurr | bnd_v142 VarCurr);
% 18.65/18.28 ALL VarCurr.
% 18.65/18.28 bnd_v146 VarCurr =
% 18.65/18.28 ((bnd_v88 (VarCurr, bnd_bitIndex2) = True &
% 18.65/18.28 bnd_v88 (VarCurr, bnd_bitIndex1) = False) &
% 18.65/18.28 bnd_v88 (VarCurr, bnd_bitIndex0) = False);
% 18.65/18.28 ALL VarCurr.
% 18.65/18.28 bnd_v147 VarCurr =
% 18.65/18.28 ((bnd_v88 (VarCurr, bnd_bitIndex2) = True &
% 18.65/18.28 bnd_v88 (VarCurr, bnd_bitIndex1) = False) &
% 18.65/18.28 bnd_v88 (VarCurr, bnd_bitIndex0) = True);
% 18.65/18.28 ALL VarCurr. bnd_v145 VarCurr = (bnd_v146 VarCurr | bnd_v147 VarCurr);
% 18.65/18.28 ALL VarCurr. bnd_v135 VarCurr = (bnd_v136 VarCurr | bnd_v145 VarCurr);
% 18.65/18.28 ALL VarCurr. bnd_v151 VarCurr = (bnd_v139 VarCurr | bnd_v140 VarCurr);
% 18.65/18.28 ALL VarCurr. bnd_v149 VarCurr = (bnd_v151 VarCurr | bnd_v141 VarCurr);
% 18.65/18.28 ALL VarCurr. bnd_v149 VarCurr --> bnd_v148 VarCurr = False;
% 18.65/18.28 ALL VarCurr. bnd_v142 VarCurr --> bnd_v148 VarCurr = True;
% 18.65/18.28 ALL VarCurr.
% 18.65/18.28 ~ bnd_v149 VarCurr & ~ bnd_v142 VarCurr --> bnd_v148 VarCurr = False;
% 18.65/18.28 ALL VarNext. bnd_v135 VarNext --> bnd_v86 VarNext = bnd_v148 VarNext;
% 18.65/18.28 ALL VarNext VarCurr.
% 18.65/18.28 bnd_nextState (VarCurr, VarNext) -->
% 18.65/18.28 ~ bnd_v135 VarNext --> bnd_v86 VarNext = bnd_v86 VarCurr;
% 18.65/18.28 ALL VarCurr. bnd_v84 VarCurr = bnd_v86 VarCurr; ~ bnd_v161 bnd_constB0;
% 18.65/18.28 ALL VarCurr. bnd_v167 VarCurr = (bnd_v139 VarCurr | bnd_v140 VarCurr);
% 18.65/18.28 ALL VarCurr. bnd_v166 VarCurr = (bnd_v167 VarCurr | bnd_v141 VarCurr);
% 18.65/18.28 ALL VarCurr. bnd_v165 VarCurr = (bnd_v166 VarCurr | bnd_v142 VarCurr);
% 18.65/18.28 ALL VarCurr. bnd_v164 VarCurr = (bnd_v165 VarCurr | bnd_v145 VarCurr);
% 18.65/18.28 ALL VarCurr. bnd_v171 VarCurr = (bnd_v141 VarCurr | bnd_v142 VarCurr);
% 18.65/18.28 ALL VarCurr. bnd_v169 VarCurr = (bnd_v171 VarCurr | bnd_v145 VarCurr);
% 18.65/18.28 ALL VarCurr. bnd_v139 VarCurr --> bnd_v168 VarCurr = False;
% 18.65/18.28 ALL VarCurr. bnd_v140 VarCurr --> bnd_v168 VarCurr = True;
% 18.65/18.28 ALL VarCurr.
% 18.65/18.28 ~ bnd_v139 VarCurr & ~ bnd_v140 VarCurr --> bnd_v168 VarCurr = False;
% 18.65/18.28 ALL VarNext. bnd_v164 VarNext --> bnd_v161 VarNext = bnd_v168 VarNext;
% 18.65/18.28 ALL VarNext VarCurr.
% 18.65/18.28 bnd_nextState (VarCurr, VarNext) -->
% 18.65/18.28 ~ bnd_v164 VarNext --> bnd_v161 VarNext = bnd_v161 VarCurr;
% 18.65/18.28 ALL VarCurr. bnd_v159 VarCurr = bnd_v161 VarCurr; ~ bnd_v157 bnd_constB0;
% 18.65/18.28 ALL VarCurr. bnd_v184 VarCurr = (bnd_v39 VarCurr & bnd_v9 VarCurr);
% 18.65/18.28 ALL VarCurr. bnd_v183 VarCurr = (bnd_v184 VarCurr | bnd_v26 VarCurr);
% 18.65/18.28 ALL VarCurr. (~ bnd_v182 VarCurr) = bnd_v183 VarCurr;
% 18.65/18.28 ALL VarCurr. bnd_v181 VarCurr = (bnd_v182 VarCurr & bnd_v157 VarCurr);
% 18.65/18.28 ALL VarCurr. (~ bnd_v186 VarCurr) = bnd_v26 VarCurr;
% 18.65/18.28 ALL VarCurr. bnd_v187 VarCurr = (bnd_v184 VarCurr & bnd_v159 VarCurr);
% 18.65/18.28 ALL VarCurr. bnd_v185 VarCurr = (bnd_v186 VarCurr & bnd_v187 VarCurr);
% 18.65/18.28 ALL VarCurr. bnd_v178 VarCurr = (bnd_v181 VarCurr | bnd_v185 VarCurr);
% 18.65/18.28 ALL VarNext VarCurr.
% 18.65/18.28 bnd_nextState (VarCurr, VarNext) -->
% 18.65/18.28 bnd_v180 VarNext = bnd_v178 VarCurr;
% 18.65/18.28 ALL VarNext. True --> bnd_v157 VarNext = bnd_v180 VarNext;
% 18.65/18.28 ALL VarNext VarCurr.
% 18.65/18.28 bnd_nextState (VarCurr, VarNext) -->
% 18.65/18.28 ~ True --> bnd_v157 VarNext = bnd_v157 VarCurr;
% 18.65/18.28 ~ bnd_v193 bnd_constB0;
% 18.65/18.28 ALL VarCurr. bnd_v199 VarCurr = (bnd_v139 VarCurr | bnd_v140 VarCurr);
% 18.65/18.28 ALL VarCurr. bnd_v198 VarCurr = (bnd_v199 VarCurr | bnd_v141 VarCurr);
% 18.65/18.28 ALL VarCurr. bnd_v197 VarCurr = (bnd_v198 VarCurr | bnd_v142 VarCurr);
% 18.65/18.28 ALL VarCurr. bnd_v196 VarCurr = (bnd_v197 VarCurr | bnd_v145 VarCurr);
% 18.65/18.28 ALL VarCurr. bnd_v201 VarCurr = (bnd_v139 VarCurr | bnd_v140 VarCurr);
% 18.65/18.28 ALL VarCurr. bnd_v202 VarCurr = (bnd_v142 VarCurr | bnd_v145 VarCurr);
% 18.65/18.28 ALL VarCurr. bnd_v201 VarCurr --> bnd_v200 VarCurr = False;
% 18.65/18.28 ALL VarCurr. bnd_v141 VarCurr --> bnd_v200 VarCurr = True;
% 18.65/18.28 ALL VarCurr.
% 18.65/18.28 ~ bnd_v201 VarCurr & ~ bnd_v141 VarCurr --> bnd_v200 VarCurr = False;
% 18.65/18.28 ALL VarNext. bnd_v196 VarNext --> bnd_v193 VarNext = bnd_v200 VarNext;
% 18.65/18.28 ALL VarNext VarCurr.
% 18.65/18.28 bnd_nextState (VarCurr, VarNext) -->
% 18.65/18.28 ~ bnd_v196 VarNext --> bnd_v193 VarNext = bnd_v193 VarCurr;
% 18.65/18.28 ALL VarCurr. bnd_v191 VarCurr = bnd_v193 VarCurr; ~ bnd_v208 bnd_constB0;
% 18.65/18.28 ALL VarCurr. bnd_v214 VarCurr = (bnd_v182 VarCurr & bnd_v208 VarCurr);
% 18.65/18.28 ALL VarCurr. bnd_v217 VarCurr = (bnd_v184 VarCurr & bnd_v84 VarCurr);
% 18.65/18.28 ALL VarCurr. bnd_v216 VarCurr = (bnd_v186 VarCurr & bnd_v217 VarCurr);
% 18.65/18.28 ALL VarCurr. bnd_v215 VarCurr = (bnd_v216 VarCurr & bnd_v157 VarCurr);
% 18.65/18.28 ALL VarCurr. bnd_v211 VarCurr = (bnd_v214 VarCurr | bnd_v215 VarCurr);
% 18.65/18.28 ALL VarNext VarCurr.
% 18.65/18.28 bnd_nextState (VarCurr, VarNext) -->
% 18.65/18.28 bnd_v213 VarNext = bnd_v211 VarCurr;
% 18.65/18.28 ALL VarNext. True --> bnd_v208 VarNext = bnd_v213 VarNext;
% 18.65/18.28 ALL VarNext VarCurr.
% 18.65/18.28 bnd_nextState (VarCurr, VarNext) -->
% 18.65/18.28 ~ True --> bnd_v208 VarNext = bnd_v208 VarCurr;
% 18.65/18.28 ~ bnd_v223 bnd_constB0;
% 18.65/18.28 ALL VarCurr. bnd_v229 VarCurr = (bnd_v139 VarCurr | bnd_v140 VarCurr);
% 18.65/18.28 ALL VarCurr. bnd_v228 VarCurr = (bnd_v229 VarCurr | bnd_v141 VarCurr);
% 18.65/18.28 ALL VarCurr. bnd_v227 VarCurr = (bnd_v228 VarCurr | bnd_v142 VarCurr);
% 18.65/18.28 ALL VarCurr. bnd_v226 VarCurr = (bnd_v227 VarCurr | bnd_v145 VarCurr);
% 18.65/18.28 ALL VarCurr. bnd_v150 VarCurr = (bnd_v151 VarCurr | bnd_v141 VarCurr);
% 18.65/18.28 ALL VarCurr. bnd_v231 VarCurr = (bnd_v150 VarCurr | bnd_v142 VarCurr);
% 18.65/18.28 ALL VarCurr. bnd_v231 VarCurr --> bnd_v230 VarCurr = False;
% 18.65/18.28 ALL VarCurr. ~ bnd_v231 VarCurr --> bnd_v230 VarCurr = True;
% 18.65/18.28 ALL VarNext. bnd_v226 VarNext --> bnd_v223 VarNext = bnd_v230 VarNext;
% 18.65/18.28 ALL VarNext VarCurr.
% 18.65/18.28 bnd_nextState (VarCurr, VarNext) -->
% 18.65/18.28 ~ bnd_v226 VarNext --> bnd_v223 VarNext = bnd_v223 VarCurr;
% 18.65/18.28 ALL VarCurr. bnd_v221 VarCurr = bnd_v223 VarCurr; ~ bnd_v238 bnd_constB0;
% 18.65/18.28 ALL VarCurr. bnd_v244 VarCurr = (bnd_v182 VarCurr & bnd_v238 VarCurr);
% 18.65/18.28 ALL VarCurr. bnd_v247 VarCurr = (bnd_v184 VarCurr & bnd_v191 VarCurr);
% 18.65/18.28 ALL VarCurr. bnd_v246 VarCurr = (bnd_v186 VarCurr & bnd_v247 VarCurr);
% 18.65/18.28 ALL VarCurr. bnd_v245 VarCurr = (bnd_v246 VarCurr & bnd_v208 VarCurr);
% 18.65/18.28 ALL VarCurr. bnd_v241 VarCurr = (bnd_v244 VarCurr | bnd_v245 VarCurr);
% 18.65/18.28 ALL VarNext VarCurr.
% 18.65/18.28 bnd_nextState (VarCurr, VarNext) -->
% 18.65/18.28 bnd_v243 VarNext = bnd_v241 VarCurr;
% 18.65/18.28 ALL VarNext. True --> bnd_v238 VarNext = bnd_v243 VarNext;
% 18.65/18.28 ALL VarNext VarCurr.
% 18.65/18.28 bnd_nextState (VarCurr, VarNext) -->
% 18.65/18.28 ~ True --> bnd_v238 VarNext = bnd_v238 VarCurr;
% 18.65/18.28 ~ bnd_v253 bnd_constB0;
% 18.65/18.28 ALL VarCurr. bnd_v259 VarCurr = (bnd_v182 VarCurr & bnd_v253 VarCurr);
% 18.65/18.28 ALL VarCurr. bnd_v262 VarCurr = (bnd_v184 VarCurr & bnd_v221 VarCurr);
% 18.65/18.28 ALL VarCurr. bnd_v261 VarCurr = (bnd_v186 VarCurr & bnd_v262 VarCurr);
% 18.65/18.28 ALL VarCurr. bnd_v260 VarCurr = (bnd_v261 VarCurr & bnd_v238 VarCurr);
% 18.65/18.28 ALL VarCurr. bnd_v256 VarCurr = (bnd_v259 VarCurr | bnd_v260 VarCurr);
% 18.65/18.28 ALL VarNext VarCurr.
% 18.65/18.28 bnd_nextState (VarCurr, VarNext) -->
% 18.65/18.28 bnd_v258 VarNext = bnd_v256 VarCurr;
% 18.65/18.28 ALL VarNext. True --> bnd_v253 VarNext = bnd_v258 VarNext;
% 18.65/18.28 ALL VarNext VarCurr.
% 18.65/18.28 bnd_nextState (VarCurr, VarNext) -->
% 18.65/18.28 ~ True --> bnd_v253 VarNext = bnd_v253 VarCurr;
% 18.65/18.28 ~ bnd_v251 bnd_constB0;
% 18.65/18.28 ALL VarCurr. bnd_v270 VarCurr = (bnd_v182 VarCurr & bnd_v251 VarCurr);
% 18.65/18.28 ALL VarCurr. bnd_v271 VarCurr = (bnd_v261 VarCurr & bnd_v253 VarCurr);
% 18.65/18.28 ALL VarCurr. bnd_v267 VarCurr = (bnd_v270 VarCurr | bnd_v271 VarCurr);
% 18.65/18.28 ALL VarNext VarCurr.
% 18.65/18.28 bnd_nextState (VarCurr, VarNext) -->
% 18.65/18.28 bnd_v269 VarNext = bnd_v267 VarCurr;
% 18.65/18.28 ALL VarNext. True --> bnd_v251 VarNext = bnd_v269 VarNext;
% 18.65/18.28 ALL VarNext VarCurr.
% 18.65/18.28 bnd_nextState (VarCurr, VarNext) -->
% 18.65/18.28 ~ True --> bnd_v251 VarNext = bnd_v251 VarCurr;
% 18.65/18.28 ~ bnd_v275 bnd_constB0;
% 18.65/18.28 ALL VarCurr. bnd_v281 VarCurr = (bnd_v182 VarCurr & bnd_v275 VarCurr);
% 18.65/18.28 ALL VarCurr. bnd_v282 VarCurr = (bnd_v216 VarCurr & bnd_v251 VarCurr);
% 18.65/18.28 ALL VarCurr. bnd_v278 VarCurr = (bnd_v281 VarCurr | bnd_v282 VarCurr);
% 18.65/18.28 ALL VarNext VarCurr.
% 18.65/18.28 bnd_nextState (VarCurr, VarNext) -->
% 18.65/18.28 bnd_v280 VarNext = bnd_v278 VarCurr;
% 18.65/18.28 ALL VarNext. True --> bnd_v275 VarNext = bnd_v280 VarNext;
% 18.65/18.28 ALL VarNext VarCurr.
% 18.65/18.28 bnd_nextState (VarCurr, VarNext) -->
% 18.65/18.28 ~ True --> bnd_v275 VarNext = bnd_v275 VarCurr;
% 18.65/18.28 ALL VarCurr. (~ bnd_v296 VarCurr) = bnd_v84 VarCurr;
% 18.65/18.28 ALL VarCurr. bnd_v295 VarCurr = (bnd_v184 VarCurr & bnd_v296 VarCurr);
% 18.65/18.28 ALL VarCurr. bnd_v294 VarCurr = (bnd_v186 VarCurr & bnd_v295 VarCurr);
% 18.65/18.28 ALL VarCurr. bnd_v293 VarCurr = (bnd_v294 VarCurr & bnd_v157 VarCurr);
% 18.65/18.28 ALL VarCurr. (~ bnd_v300 VarCurr) = bnd_v191 VarCurr;
% 18.65/18.28 ALL VarCurr. bnd_v299 VarCurr = (bnd_v184 VarCurr & bnd_v300 VarCurr);
% 18.65/18.28 ALL VarCurr. bnd_v298 VarCurr = (bnd_v186 VarCurr & bnd_v299 VarCurr);
% 18.65/18.28 ALL VarCurr. bnd_v297 VarCurr = (bnd_v298 VarCurr & bnd_v208 VarCurr);
% 18.65/18.28 ALL VarCurr. bnd_v292 VarCurr = (bnd_v293 VarCurr | bnd_v297 VarCurr);
% 18.65/18.28 ALL VarCurr. (~ bnd_v291 VarCurr) = bnd_v292 VarCurr;
% 18.65/18.28 ALL VarCurr. (~ bnd_v305 VarCurr) = bnd_v221 VarCurr;
% 18.65/18.28 ALL VarCurr. bnd_v304 VarCurr = (bnd_v184 VarCurr & bnd_v305 VarCurr);
% 18.65/18.28 ALL VarCurr. bnd_v303 VarCurr = (bnd_v186 VarCurr & bnd_v304 VarCurr);
% 18.65/18.28 ALL VarCurr. bnd_v302 VarCurr = (bnd_v303 VarCurr & bnd_v238 VarCurr);
% 18.65/18.28 ALL VarCurr. (~ bnd_v301 VarCurr) = bnd_v302 VarCurr;
% 18.65/18.28 ALL VarCurr. bnd_v290 VarCurr = (bnd_v291 VarCurr & bnd_v301 VarCurr);
% 18.65/18.28 ALL VarCurr. bnd_v307 VarCurr = (bnd_v294 VarCurr & bnd_v251 VarCurr);
% 18.65/18.28 ALL VarCurr. (~ bnd_v306 VarCurr) = bnd_v307 VarCurr;
% 18.65/18.28 ALL VarCurr. bnd_v289 VarCurr = (bnd_v290 VarCurr & bnd_v306 VarCurr);
% 18.65/18.28 ALL VarCurr. (~ bnd_v312 VarCurr) = bnd_v159 VarCurr;
% 18.65/18.28 ALL VarCurr. bnd_v311 VarCurr = (bnd_v184 VarCurr & bnd_v312 VarCurr);
% 18.65/18.28 ALL VarCurr. bnd_v310 VarCurr = (bnd_v186 VarCurr & bnd_v311 VarCurr);
% 18.65/18.28 ALL VarCurr. bnd_v309 VarCurr = (bnd_v310 VarCurr & bnd_v275 VarCurr);
% 18.65/18.28 ALL VarCurr. (~ bnd_v308 VarCurr) = bnd_v309 VarCurr;
% 18.65/18.28 ALL VarCurr. bnd_v288 VarCurr = (bnd_v289 VarCurr & bnd_v308 VarCurr);
% 18.65/18.28 ALL VarCurr. bnd_v314 VarCurr = (bnd_v303 VarCurr & bnd_v253 VarCurr);
% 18.65/18.28 ALL VarCurr. (~ bnd_v313 VarCurr) = bnd_v314 VarCurr;
% 18.65/18.28 ALL VarCurr. bnd_v287 VarCurr = (bnd_v288 VarCurr & bnd_v313 VarCurr);
% 18.65/18.28 ALL VarCurr. (~ bnd_v286 VarCurr) = bnd_v287 VarCurr;
% 18.65/18.28 ALL VarCurr. (~ bnd_v82 VarCurr) = bnd_v286 VarCurr; All bnd_v4;
% 18.65/18.28 All bnd_v58; All bnd_v24; bnd_reachableState bnd_constB0;
% 18.65/18.28 bnd_reachableState bnd_constB1; bnd_reachableState bnd_constB2;
% 18.65/18.28 bnd_reachableState bnd_constB3; bnd_reachableState bnd_constB4;
% 18.65/18.28 bnd_reachableState bnd_constB5; bnd_reachableState bnd_constB6;
% 18.65/18.28 bnd_reachableState bnd_constB7; bnd_reachableState bnd_constB8;
% 18.65/18.28 bnd_reachableState bnd_constB9; bnd_reachableState bnd_constB10;
% 18.65/18.28 bnd_reachableState bnd_constB11; bnd_reachableState bnd_constB12;
% 18.65/18.28 bnd_reachableState bnd_constB13; bnd_reachableState bnd_constB14;
% 18.65/18.28 bnd_reachableState bnd_constB15; bnd_reachableState bnd_constB16;
% 18.65/18.28 bnd_reachableState bnd_constB17; bnd_reachableState bnd_constB18;
% 18.65/18.28 bnd_reachableState bnd_constB19; bnd_reachableState bnd_constB20;
% 18.65/18.28 bnd_reachableState bnd_constB21; bnd_reachableState bnd_constB22;
% 18.65/18.28 bnd_reachableState bnd_constB23; bnd_reachableState bnd_constB24;
% 18.65/18.28 bnd_reachableState bnd_constB25; bnd_reachableState bnd_constB26;
% 18.65/18.28 bnd_reachableState bnd_constB27; bnd_reachableState bnd_constB28;
% 18.65/18.28 bnd_reachableState bnd_constB29; bnd_reachableState bnd_constB30;
% 18.65/18.28 bnd_reachableState bnd_constB31; bnd_reachableState bnd_constB32;
% 18.65/18.28 bnd_reachableState bnd_constB33; bnd_reachableState bnd_constB34;
% 18.65/18.28 bnd_reachableState bnd_constB35; bnd_reachableState bnd_constB36;
% 18.65/18.28 bnd_reachableState bnd_constB37; bnd_reachableState bnd_constB38;
% 18.65/18.28 bnd_reachableState bnd_constB39; bnd_reachableState bnd_constB40;
% 18.65/18.28 bnd_reachableState bnd_constB41; bnd_reachableState bnd_constB42;
% 18.65/18.28 bnd_reachableState bnd_constB43; bnd_reachableState bnd_constB44;
% 18.65/18.28 bnd_reachableState bnd_constB45; bnd_reachableState bnd_constB46;
% 18.65/18.28 bnd_reachableState bnd_constB47; bnd_reachableState bnd_constB48;
% 18.65/18.28 bnd_reachableState bnd_constB49; bnd_reachableState bnd_constB50;
% 18.65/18.28 bnd_reachableState bnd_constB51; bnd_reachableState bnd_constB52;
% 18.65/18.28 bnd_reachableState bnd_constB53; bnd_reachableState bnd_constB54;
% 18.65/18.28 bnd_reachableState bnd_constB55; bnd_reachableState bnd_constB56;
% 18.65/18.28 bnd_reachableState bnd_constB57; bnd_reachableState bnd_constB58;
% 18.65/18.28 bnd_reachableState bnd_constB59; bnd_reachableState bnd_constB60;
% 18.65/18.28 bnd_reachableState bnd_constB61; bnd_reachableState bnd_constB62;
% 18.65/18.28 bnd_reachableState bnd_constB63; bnd_reachableState bnd_constB64;
% 18.65/18.28 bnd_reachableState bnd_constB65; bnd_reachableState bnd_constB66;
% 18.65/18.28 bnd_reachableState bnd_constB67; bnd_reachableState bnd_constB68;
% 18.65/18.28 bnd_reachableState bnd_constB69; bnd_reachableState bnd_constB70;
% 18.65/18.28 bnd_reachableState bnd_constB71; bnd_reachableState bnd_constB72;
% 18.65/18.28 bnd_reachableState bnd_constB73; bnd_reachableState bnd_constB74;
% 18.65/18.28 bnd_reachableState bnd_constB75; bnd_reachableState bnd_constB76;
% 18.65/18.28 bnd_reachableState bnd_constB77; bnd_reachableState bnd_constB78;
% 18.65/18.28 bnd_reachableState bnd_constB79; bnd_reachableState bnd_constB80;
% 18.65/18.28 bnd_reachableState bnd_constB81; bnd_reachableState bnd_constB82;
% 18.65/18.28 bnd_reachableState bnd_constB83; bnd_reachableState bnd_constB84;
% 18.65/18.28 bnd_reachableState bnd_constB85; bnd_reachableState bnd_constB86;
% 18.65/18.28 bnd_reachableState bnd_constB87; bnd_reachableState bnd_constB88;
% 18.65/18.28 bnd_reachableState bnd_constB89; bnd_reachableState bnd_constB90;
% 18.65/18.28 bnd_reachableState bnd_constB91; bnd_reachableState bnd_constB92;
% 18.65/18.28 bnd_reachableState bnd_constB93; bnd_reachableState bnd_constB94;
% 18.65/18.28 bnd_reachableState bnd_constB95; bnd_reachableState bnd_constB96;
% 18.65/18.28 bnd_reachableState bnd_constB97; bnd_reachableState bnd_constB98;
% 18.65/18.28 bnd_reachableState bnd_constB99; bnd_reachableState bnd_constB100;
% 18.65/18.28 bnd_reachableState bnd_constB101; bnd_reachableState bnd_constB102;
% 18.65/18.28 bnd_reachableState bnd_constB103; bnd_reachableState bnd_constB104;
% 18.65/18.28 bnd_reachableState bnd_constB105; bnd_reachableState bnd_constB106;
% 18.65/18.28 bnd_reachableState bnd_constB107; bnd_reachableState bnd_constB108;
% 18.65/18.28 bnd_reachableState bnd_constB109; bnd_reachableState bnd_constB110;
% 18.65/18.28 bnd_reachableState bnd_constB111; bnd_reachableState bnd_constB112;
% 18.65/18.28 bnd_reachableState bnd_constB113; bnd_reachableState bnd_constB114;
% 18.65/18.28 bnd_reachableState bnd_constB115; bnd_reachableState bnd_constB116;
% 18.65/18.28 bnd_reachableState bnd_constB117; bnd_reachableState bnd_constB118;
% 18.65/18.28 bnd_reachableState bnd_constB119; bnd_reachableState bnd_constB120;
% 18.65/18.28 bnd_reachableState bnd_constB121; bnd_reachableState bnd_constB122;
% 18.65/18.28 bnd_reachableState bnd_constB123; bnd_reachableState bnd_constB124;
% 18.65/18.28 bnd_reachableState bnd_constB125; bnd_reachableState bnd_constB126;
% 18.65/18.28 bnd_reachableState bnd_constB127; bnd_reachableState bnd_constB128;
% 18.65/18.28 bnd_reachableState bnd_constB129; bnd_reachableState bnd_constB130;
% 18.65/18.28 bnd_reachableState bnd_constB131; bnd_reachableState bnd_constB132;
% 18.65/18.28 bnd_reachableState bnd_constB133; bnd_reachableState bnd_constB134;
% 18.65/18.28 bnd_reachableState bnd_constB135; bnd_reachableState bnd_constB136;
% 18.65/18.28 bnd_reachableState bnd_constB137; bnd_reachableState bnd_constB138;
% 18.65/18.28 bnd_reachableState bnd_constB139; bnd_reachableState bnd_constB140;
% 18.65/18.28 bnd_reachableState bnd_constB141; bnd_reachableState bnd_constB142;
% 18.65/18.28 bnd_reachableState bnd_constB143; bnd_reachableState bnd_constB144;
% 18.65/18.28 bnd_reachableState bnd_constB145; bnd_reachableState bnd_constB146;
% 18.65/18.28 bnd_reachableState bnd_constB147; bnd_reachableState bnd_constB148;
% 18.65/18.28 bnd_reachableState bnd_constB149; bnd_reachableState bnd_constB150;
% 18.65/18.28 bnd_reachableState bnd_constB151; bnd_reachableState bnd_constB152;
% 18.65/18.28 bnd_reachableState bnd_constB153; bnd_reachableState bnd_constB154;
% 18.65/18.28 bnd_reachableState bnd_constB155; bnd_reachableState bnd_constB156;
% 18.65/18.28 bnd_reachableState bnd_constB157; bnd_reachableState bnd_constB158;
% 18.65/18.28 bnd_reachableState bnd_constB159; bnd_reachableState bnd_constB160;
% 18.65/18.28 bnd_reachableState bnd_constB161; bnd_reachableState bnd_constB162;
% 18.65/18.28 bnd_reachableState bnd_constB163; bnd_reachableState bnd_constB164;
% 18.65/18.28 bnd_reachableState bnd_constB165; bnd_reachableState bnd_constB166;
% 18.65/18.28 bnd_reachableState bnd_constB167; bnd_reachableState bnd_constB168;
% 18.65/18.28 bnd_reachableState bnd_constB169; bnd_reachableState bnd_constB170;
% 18.65/18.28 bnd_reachableState bnd_constB171; bnd_reachableState bnd_constB172;
% 18.65/18.28 bnd_reachableState bnd_constB173; bnd_reachableState bnd_constB174;
% 18.65/18.28 bnd_reachableState bnd_constB175; bnd_reachableState bnd_constB176;
% 18.65/18.28 bnd_reachableState bnd_constB177; bnd_reachableState bnd_constB178;
% 18.65/18.28 bnd_reachableState bnd_constB179; bnd_reachableState bnd_constB180;
% 18.65/18.28 bnd_reachableState bnd_constB181; bnd_reachableState bnd_constB182;
% 18.65/18.28 bnd_reachableState bnd_constB183; bnd_reachableState bnd_constB184;
% 18.65/18.28 bnd_reachableState bnd_constB185; bnd_reachableState bnd_constB186;
% 18.65/18.28 bnd_reachableState bnd_constB187; bnd_reachableState bnd_constB188;
% 18.65/18.28 bnd_reachableState bnd_constB189; bnd_reachableState bnd_constB190;
% 18.65/18.28 bnd_reachableState bnd_constB191; bnd_reachableState bnd_constB192;
% 18.65/18.28 bnd_reachableState bnd_constB193; bnd_reachableState bnd_constB194;
% 18.65/18.28 bnd_reachableState bnd_constB195; bnd_reachableState bnd_constB196;
% 18.65/18.28 bnd_reachableState bnd_constB197; bnd_reachableState bnd_constB198;
% 18.65/18.28 bnd_reachableState bnd_constB199; bnd_reachableState bnd_constB200;
% 18.65/18.28 ALL VarState.
% 18.65/18.28 bnd_reachableState VarState -->
% 18.65/18.28 (((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((bnd_constB0 =
% 18.65/18.28 VarState |
% 18.65/18.28 bnd_constB1 = VarState) |
% 18.65/18.28 bnd_constB2 = VarState) |
% 18.65/18.28 bnd_constB3 = VarState) |
% 18.65/18.28 bnd_constB4 = VarState) |
% 18.65/18.28 bnd_constB5 = VarState) |
% 18.65/18.28 bnd_constB6 = VarState) |
% 18.65/18.28 bnd_constB7 = VarState) |
% 18.65/18.28 bnd_constB8 = VarState) |
% 18.65/18.28 bnd_constB9 = VarState) |
% 18.65/18.28 bnd_constB10 = VarState) |
% 18.65/18.28 bnd_constB11 = VarState) |
% 18.65/18.28 bnd_constB12 = VarState) |
% 18.65/18.28 bnd_constB13 = VarState) |
% 18.65/18.28 bnd_constB14 = VarState) |
% 18.65/18.28 bnd_constB15 = VarState) |
% 18.65/18.28 bnd_constB16 = VarState) |
% 18.65/18.28 bnd_constB17 = VarState) |
% 18.65/18.28 bnd_constB18 = VarState) |
% 18.65/18.28 bnd_constB19 = VarState) |
% 18.65/18.28 bnd_constB20 = VarState) |
% 18.65/18.28 bnd_constB21 = VarState) |
% 18.65/18.28 bnd_constB22 = VarState) |
% 18.65/18.28 bnd_constB23 = VarState) |
% 18.65/18.28 bnd_constB24 = VarState) |
% 18.65/18.28 bnd_constB25 = VarState) |
% 18.65/18.28 bnd_constB26 = VarState) |
% 18.65/18.28 bnd_constB27 = VarState) |
% 18.65/18.28 bnd_constB28 = VarState) |
% 18.65/18.28 bnd_constB29 = VarState) |
% 18.65/18.28 bnd_constB30 = VarState) |
% 18.65/18.28 bnd_constB31 = VarState) |
% 18.65/18.28 bnd_constB32 = VarState) |
% 18.65/18.28 bnd_constB33 = VarState) |
% 18.65/18.28 bnd_constB34 = VarState) |
% 18.65/18.28 bnd_constB35 = VarState) |
% 18.65/18.28 bnd_constB36 = VarState) |
% 18.65/18.28 bnd_constB37 = VarState) |
% 18.65/18.28 bnd_constB38 = VarState) |
% 18.65/18.28 bnd_constB39 = VarState) |
% 18.65/18.28 bnd_constB40 = VarState) |
% 18.65/18.28 bnd_constB41 = VarState) |
% 18.65/18.28 bnd_constB42 = VarState) |
% 18.65/18.28 bnd_constB43 = VarState) |
% 18.65/18.28 bnd_constB44 = VarState) |
% 18.65/18.28 bnd_constB45 = VarState) |
% 18.65/18.28 bnd_constB46 = VarState) |
% 18.65/18.28 bnd_constB47 = VarState) |
% 18.65/18.28 bnd_constB48 = VarState) |
% 18.65/18.28 bnd_constB49 = VarState) |
% 18.65/18.28 bnd_constB50 = VarState) |
% 18.65/18.28 bnd_constB51 = VarState) |
% 18.65/18.28 bnd_constB52 = VarState) |
% 18.65/18.28 bnd_constB53 = VarState) |
% 18.65/18.28 bnd_constB54 = VarState) |
% 18.65/18.28 bnd_constB55 = VarState) |
% 18.65/18.28 bnd_constB56 = VarState) |
% 18.65/18.28 bnd_constB57 = VarState) |
% 18.65/18.28 bnd_constB58 = VarState) |
% 18.65/18.28 bnd_constB59 = VarState) |
% 18.65/18.28 bnd_constB60 = VarState) |
% 18.65/18.28 bnd_constB61 = VarState) |
% 18.65/18.28 bnd_constB62 = VarState) |
% 18.65/18.28 bnd_constB63 = VarState) |
% 18.65/18.28 bnd_constB64 = VarState) |
% 18.65/18.28 bnd_constB65 = VarState) |
% 18.65/18.28 bnd_constB66 = VarState) |
% 18.65/18.28 bnd_constB67 = VarState) |
% 18.65/18.28 bnd_constB68 = VarState) |
% 18.65/18.28 bnd_constB69 = VarState) |
% 18.65/18.28 bnd_constB70 = VarState) |
% 18.65/18.28 bnd_constB71 = VarState) |
% 18.65/18.28 bnd_constB72 = VarState) |
% 18.65/18.28 bnd_constB73 = VarState) |
% 18.65/18.28 bnd_constB74 = VarState) |
% 18.65/18.28 bnd_constB75 = VarState) |
% 18.65/18.28 bnd_constB76 = VarState) |
% 18.65/18.28 bnd_constB77 = VarState) |
% 18.65/18.28 bnd_constB78 = VarState) |
% 18.65/18.28 bnd_constB79 = VarState) |
% 18.65/18.28 bnd_constB80 = VarState) |
% 18.65/18.28 bnd_constB81 = VarState) |
% 18.65/18.28 bnd_constB82 = VarState) |
% 18.65/18.28 bnd_constB83 = VarState) |
% 18.65/18.28 bnd_constB84 = VarState) |
% 18.65/18.28 bnd_constB85 = VarState) |
% 18.65/18.28 bnd_constB86 = VarState) |
% 18.65/18.28 bnd_constB87 = VarState) |
% 18.65/18.28 bnd_constB88 = VarState) |
% 18.65/18.28 bnd_constB89 = VarState) |
% 18.65/18.28 bnd_constB90 = VarState) |
% 18.65/18.28 bnd_constB91 = VarState) |
% 18.65/18.28 bnd_constB92 = VarState) |
% 18.65/18.28 bnd_constB93 = VarState) |
% 18.65/18.28 bnd_constB94 = VarState) |
% 18.65/18.28 bnd_constB95 = VarState) |
% 18.65/18.28 bnd_constB96 = VarState) |
% 18.65/18.28 bnd_constB97 = VarState) |
% 18.65/18.28 bnd_constB98 = VarState) |
% 18.65/18.28 bnd_constB99 = VarState) |
% 18.65/18.28 bnd_constB100 = VarState) |
% 18.65/18.28 bnd_constB101 = VarState) |
% 18.65/18.28 bnd_constB102 = VarState) |
% 18.65/18.28 bnd_constB103 = VarState) |
% 18.65/18.28 bnd_constB104 = VarState) |
% 18.65/18.28 bnd_constB105 = VarState) |
% 18.65/18.28 bnd_constB106 = VarState) |
% 18.65/18.28 bnd_constB107 = VarState) |
% 18.65/18.28 bnd_constB108 = VarState) |
% 18.65/18.28 bnd_constB109 = VarState) |
% 18.65/18.28 bnd_constB110 = VarState) |
% 18.65/18.28 bnd_constB111 = VarState) |
% 18.65/18.28 bnd_constB112 = VarState) |
% 18.65/18.28 bnd_constB113 = VarState) |
% 18.65/18.28 bnd_constB114 = VarState) |
% 18.65/18.28 bnd_constB115 = VarState) |
% 18.65/18.28 bnd_constB116 = VarState) |
% 18.65/18.28 bnd_constB117 = VarState) |
% 18.65/18.28 bnd_constB118 = VarState) |
% 18.65/18.28 bnd_constB119 = VarState) |
% 18.65/18.28 bnd_constB120 = VarState) |
% 18.65/18.28 bnd_constB121 = VarState) |
% 18.65/18.28 bnd_constB122 = VarState) |
% 18.65/18.28 bnd_constB123 = VarState) |
% 18.65/18.28 bnd_constB124 = VarState) |
% 18.65/18.28 bnd_constB125 = VarState) |
% 18.65/18.28 bnd_constB126 = VarState) |
% 18.65/18.28 bnd_constB127 = VarState) |
% 18.65/18.28 bnd_constB128 = VarState) |
% 18.65/18.28 bnd_constB129 = VarState) |
% 18.65/18.28 bnd_constB130 = VarState) |
% 18.65/18.28 bnd_constB131 = VarState) |
% 18.65/18.28 bnd_constB132 = VarState) |
% 18.65/18.28 bnd_constB133 = VarState) |
% 18.65/18.28 bnd_constB134 = VarState) |
% 18.65/18.28 bnd_constB135 = VarState) |
% 18.65/18.28 bnd_constB136 = VarState) |
% 18.65/18.28 bnd_constB137 = VarState) |
% 18.65/18.28 bnd_constB138 = VarState) |
% 18.65/18.28 bnd_constB139 = VarState) |
% 18.65/18.28 bnd_constB140 = VarState) |
% 18.65/18.28 bnd_constB141 = VarState) |
% 18.65/18.28 bnd_constB142 = VarState) |
% 18.65/18.28 bnd_constB143 = VarState) |
% 18.65/18.28 bnd_constB144 = VarState) |
% 18.65/18.28 bnd_constB145 = VarState) |
% 18.65/18.28 bnd_constB146 = VarState) |
% 18.65/18.28 bnd_constB147 = VarState) |
% 18.65/18.28 bnd_constB148 = VarState) |
% 18.65/18.28 bnd_constB149 = VarState) |
% 18.65/18.28 bnd_constB150 = VarState) |
% 18.65/18.28 bnd_constB151 = VarState) |
% 18.65/18.28 bnd_constB152 = VarState) |
% 18.65/18.28 bnd_constB153 = VarState) |
% 18.65/18.28 bnd_constB154 = VarState) |
% 18.65/18.28 bnd_constB155 = VarState) |
% 18.65/18.28 bnd_constB156 = VarState) |
% 18.65/18.28 bnd_constB157 = VarState) |
% 18.65/18.28 bnd_constB158 = VarState) |
% 18.65/18.28 bnd_constB159 = VarState) |
% 18.65/18.28 bnd_constB160 = VarState) |
% 18.65/18.28 bnd_constB161 = VarState) |
% 18.65/18.28 bnd_constB162 = VarState) |
% 18.65/18.28 bnd_constB163 = VarState) |
% 18.65/18.28 bnd_constB164 = VarState) |
% 18.65/18.28 bnd_constB165 = VarState) |
% 18.65/18.28 bnd_constB166 = VarState) |
% 18.65/18.28 bnd_constB167 = VarState) |
% 18.65/18.28 bnd_constB168 = VarState) |
% 18.65/18.28 bnd_constB169 = VarState) |
% 18.65/18.28 bnd_constB170 = VarState) |
% 18.65/18.28 bnd_constB171 = VarState) |
% 18.65/18.28 bnd_constB172 = VarState) |
% 18.65/18.28 bnd_constB173 = VarState) |
% 18.65/18.28 bnd_constB174 = VarState) |
% 18.65/18.28 bnd_constB175 = VarState) |
% 18.65/18.28 bnd_constB176 = VarState) |
% 18.65/18.28 bnd_constB177 = VarState) |
% 18.65/18.28 bnd_constB178 = VarState) |
% 18.65/18.28 bnd_constB179 = VarState) |
% 18.65/18.28 bnd_constB180 = VarState) |
% 18.65/18.28 bnd_constB181 = VarState) |
% 18.65/18.28 bnd_constB182 = VarState) |
% 18.65/18.28 bnd_constB183 = VarState) |
% 18.65/18.28 bnd_constB184 = VarState) |
% 18.65/18.28 bnd_constB185 = VarState) |
% 18.65/18.28 bnd_constB186 = VarState) |
% 18.65/18.28 bnd_constB187 = VarState) |
% 18.65/18.28 bnd_constB188 = VarState) |
% 18.65/18.28 bnd_constB189 = VarState) |
% 18.65/18.28 bnd_constB190 = VarState) |
% 18.65/18.28 bnd_constB191 = VarState) |
% 18.65/18.28 bnd_constB192 = VarState) |
% 18.65/18.28 bnd_constB193 = VarState) |
% 18.65/18.28 bnd_constB194 = VarState) |
% 18.65/18.28 bnd_constB195 = VarState) |
% 18.65/18.28 bnd_constB196 = VarState) |
% 18.65/18.28 bnd_constB197 = VarState) |
% 18.65/18.28 bnd_constB198 = VarState) |
% 18.65/18.28 bnd_constB199 = VarState) |
% 18.65/18.28 bnd_constB200 = VarState;
% 18.65/18.28 ALL VarNext VarCurr.
% 18.65/18.28 bnd_nextState (VarCurr, VarNext) -->
% 18.65/18.28 bnd_reachableState VarCurr & bnd_reachableState VarNext;
% 18.65/18.28 bnd_nextState (bnd_constB0, bnd_constB1);
% 18.65/18.28 bnd_nextState (bnd_constB1, bnd_constB2);
% 18.65/18.28 bnd_nextState (bnd_constB2, bnd_constB3);
% 18.65/18.28 bnd_nextState (bnd_constB3, bnd_constB4);
% 18.65/18.28 bnd_nextState (bnd_constB4, bnd_constB5);
% 18.65/18.28 bnd_nextState (bnd_constB5, bnd_constB6);
% 18.65/18.28 bnd_nextState (bnd_constB6, bnd_constB7);
% 18.65/18.28 bnd_nextState (bnd_constB7, bnd_constB8);
% 18.65/18.28 bnd_nextState (bnd_constB8, bnd_constB9);
% 18.65/18.28 bnd_nextState (bnd_constB9, bnd_constB10);
% 18.65/18.28 bnd_nextState (bnd_constB10, bnd_constB11);
% 18.65/18.28 bnd_nextState (bnd_constB11, bnd_constB12);
% 18.65/18.28 bnd_nextState (bnd_constB12, bnd_constB13);
% 18.65/18.28 bnd_nextState (bnd_constB13, bnd_constB14);
% 18.65/18.28 bnd_nextState (bnd_constB14, bnd_constB15);
% 18.65/18.28 bnd_nextState (bnd_constB15, bnd_constB16);
% 18.65/18.28 bnd_nextState (bnd_constB16, bnd_constB17);
% 18.65/18.28 bnd_nextState (bnd_constB17, bnd_constB18);
% 18.65/18.28 bnd_nextState (bnd_constB18, bnd_constB19);
% 18.65/18.28 bnd_nextState (bnd_constB19, bnd_constB20);
% 18.65/18.28 bnd_nextState (bnd_constB20, bnd_constB21);
% 18.65/18.28 bnd_nextState (bnd_constB21, bnd_constB22);
% 18.65/18.28 bnd_nextState (bnd_constB22, bnd_constB23);
% 18.65/18.28 bnd_nextState (bnd_constB23, bnd_constB24);
% 18.65/18.28 bnd_nextState (bnd_constB24, bnd_constB25);
% 18.65/18.28 bnd_nextState (bnd_constB25, bnd_constB26);
% 18.65/18.28 bnd_nextState (bnd_constB26, bnd_constB27);
% 18.65/18.28 bnd_nextState (bnd_constB27, bnd_constB28);
% 18.65/18.28 bnd_nextState (bnd_constB28, bnd_constB29);
% 18.65/18.28 bnd_nextState (bnd_constB29, bnd_constB30);
% 18.65/18.28 bnd_nextState (bnd_constB30, bnd_constB31);
% 18.65/18.28 bnd_nextState (bnd_constB31, bnd_constB32);
% 18.65/18.28 bnd_nextState (bnd_constB32, bnd_constB33);
% 18.65/18.28 bnd_nextState (bnd_constB33, bnd_constB34);
% 18.65/18.28 bnd_nextState (bnd_constB34, bnd_constB35);
% 18.65/18.28 bnd_nextState (bnd_constB35, bnd_constB36);
% 18.65/18.28 bnd_nextState (bnd_constB36, bnd_constB37);
% 18.65/18.28 bnd_nextState (bnd_constB37, bnd_constB38);
% 18.65/18.28 bnd_nextState (bnd_constB38, bnd_constB39);
% 18.65/18.28 bnd_nextState (bnd_constB39, bnd_constB40);
% 18.65/18.28 bnd_nextState (bnd_constB40, bnd_constB41);
% 18.65/18.28 bnd_nextState (bnd_constB41, bnd_constB42);
% 18.65/18.28 bnd_nextState (bnd_constB42, bnd_constB43);
% 18.65/18.28 bnd_nextState (bnd_constB43, bnd_constB44);
% 18.65/18.28 bnd_nextState (bnd_constB44, bnd_constB45);
% 18.65/18.28 bnd_nextState (bnd_constB45, bnd_constB46);
% 18.65/18.28 bnd_nextState (bnd_constB46, bnd_constB47);
% 18.65/18.28 bnd_nextState (bnd_constB47, bnd_constB48);
% 18.65/18.28 bnd_nextState (bnd_constB48, bnd_constB49);
% 18.65/18.28 bnd_nextState (bnd_constB49, bnd_constB50);
% 18.65/18.28 bnd_nextState (bnd_constB50, bnd_constB51);
% 18.65/18.28 bnd_nextState (bnd_constB51, bnd_constB52);
% 18.65/18.28 bnd_nextState (bnd_constB52, bnd_constB53);
% 18.65/18.28 bnd_nextState (bnd_constB53, bnd_constB54);
% 18.65/18.28 bnd_nextState (bnd_constB54, bnd_constB55);
% 18.65/18.28 bnd_nextState (bnd_constB55, bnd_constB56);
% 18.65/18.28 bnd_nextState (bnd_constB56, bnd_constB57);
% 18.65/18.28 bnd_nextState (bnd_constB57, bnd_constB58);
% 18.65/18.28 bnd_nextState (bnd_constB58, bnd_constB59);
% 18.65/18.28 bnd_nextState (bnd_constB59, bnd_constB60);
% 18.65/18.28 bnd_nextState (bnd_constB60, bnd_constB61);
% 18.65/18.28 bnd_nextState (bnd_constB61, bnd_constB62);
% 18.65/18.28 bnd_nextState (bnd_constB62, bnd_constB63);
% 18.65/18.28 bnd_nextState (bnd_constB63, bnd_constB64);
% 18.65/18.28 bnd_nextState (bnd_constB64, bnd_constB65);
% 18.65/18.28 bnd_nextState (bnd_constB65, bnd_constB66);
% 18.65/18.28 bnd_nextState (bnd_constB66, bnd_constB67);
% 18.65/18.28 bnd_nextState (bnd_constB67, bnd_constB68);
% 18.65/18.28 bnd_nextState (bnd_constB68, bnd_constB69);
% 18.65/18.28 bnd_nextState (bnd_constB69, bnd_constB70);
% 18.65/18.28 bnd_nextState (bnd_constB70, bnd_constB71);
% 18.65/18.28 bnd_nextState (bnd_constB71, bnd_constB72);
% 18.65/18.28 bnd_nextState (bnd_constB72, bnd_constB73);
% 18.65/18.28 bnd_nextState (bnd_constB73, bnd_constB74);
% 18.65/18.28 bnd_nextState (bnd_constB74, bnd_constB75);
% 18.65/18.28 bnd_nextState (bnd_constB75, bnd_constB76);
% 18.65/18.28 bnd_nextState (bnd_constB76, bnd_constB77);
% 18.65/18.28 bnd_nextState (bnd_constB77, bnd_constB78);
% 18.65/18.28 bnd_nextState (bnd_constB78, bnd_constB79);
% 18.65/18.28 bnd_nextState (bnd_constB79, bnd_constB80);
% 18.65/18.28 bnd_nextState (bnd_constB80, bnd_constB81);
% 18.65/18.28 bnd_nextState (bnd_constB81, bnd_constB82);
% 18.65/18.28 bnd_nextState (bnd_constB82, bnd_constB83);
% 18.65/18.28 bnd_nextState (bnd_constB83, bnd_constB84);
% 18.65/18.28 bnd_nextState (bnd_constB84, bnd_constB85);
% 18.65/18.28 bnd_nextState (bnd_constB85, bnd_constB86);
% 18.65/18.28 bnd_nextState (bnd_constB86, bnd_constB87);
% 18.65/18.28 bnd_nextState (bnd_constB87, bnd_constB88);
% 18.65/18.28 bnd_nextState (bnd_constB88, bnd_constB89);
% 18.65/18.28 bnd_nextState (bnd_constB89, bnd_constB90);
% 18.65/18.28 bnd_nextState (bnd_constB90, bnd_constB91);
% 18.65/18.28 bnd_nextState (bnd_constB91, bnd_constB92);
% 18.65/18.28 bnd_nextState (bnd_constB92, bnd_constB93);
% 18.65/18.28 bnd_nextState (bnd_constB93, bnd_constB94);
% 18.65/18.28 bnd_nextState (bnd_constB94, bnd_constB95);
% 18.65/18.28 bnd_nextState (bnd_constB95, bnd_constB96);
% 18.65/18.28 bnd_nextState (bnd_constB96, bnd_constB97);
% 18.65/18.28 bnd_nextState (bnd_constB97, bnd_constB98);
% 18.65/18.28 bnd_nextState (bnd_constB98, bnd_constB99);
% 18.65/18.28 bnd_nextState (bnd_constB99, bnd_constB100);
% 18.65/18.28 bnd_nextState (bnd_constB100, bnd_constB101);
% 18.65/18.28 bnd_nextState (bnd_constB101, bnd_constB102);
% 18.65/18.28 bnd_nextState (bnd_constB102, bnd_constB103);
% 18.65/18.28 bnd_nextState (bnd_constB103, bnd_constB104);
% 18.65/18.28 bnd_nextState (bnd_constB104, bnd_constB105);
% 18.65/18.28 bnd_nextState (bnd_constB105, bnd_constB106);
% 18.65/18.28 bnd_nextState (bnd_constB106, bnd_constB107);
% 18.65/18.28 bnd_nextState (bnd_constB107, bnd_constB108);
% 18.65/18.28 bnd_nextState (bnd_constB108, bnd_constB109);
% 18.65/18.28 bnd_nextState (bnd_constB109, bnd_constB110);
% 18.65/18.28 bnd_nextState (bnd_constB110, bnd_constB111);
% 18.65/18.28 bnd_nextState (bnd_constB111, bnd_constB112);
% 18.65/18.28 bnd_nextState (bnd_constB112, bnd_constB113);
% 18.65/18.28 bnd_nextState (bnd_constB113, bnd_constB114);
% 18.65/18.28 bnd_nextState (bnd_constB114, bnd_constB115);
% 18.65/18.28 bnd_nextState (bnd_constB115, bnd_constB116);
% 18.65/18.28 bnd_nextState (bnd_constB116, bnd_constB117);
% 18.65/18.28 bnd_nextState (bnd_constB117, bnd_constB118);
% 18.65/18.28 bnd_nextState (bnd_constB118, bnd_constB119);
% 18.65/18.28 bnd_nextState (bnd_constB119, bnd_constB120);
% 18.65/18.28 bnd_nextState (bnd_constB120, bnd_constB121);
% 18.65/18.28 bnd_nextState (bnd_constB121, bnd_constB122);
% 18.65/18.28 bnd_nextState (bnd_constB122, bnd_constB123);
% 18.65/18.28 bnd_nextState (bnd_constB123, bnd_constB124);
% 18.65/18.28 bnd_nextState (bnd_constB124, bnd_constB125);
% 18.65/18.28 bnd_nextState (bnd_constB125, bnd_constB126);
% 18.65/18.28 bnd_nextState (bnd_constB126, bnd_constB127);
% 18.65/18.28 bnd_nextState (bnd_constB127, bnd_constB128);
% 18.65/18.28 bnd_nextState (bnd_constB128, bnd_constB129);
% 18.65/18.28 bnd_nextState (bnd_constB129, bnd_constB130);
% 18.65/18.28 bnd_nextState (bnd_constB130, bnd_constB131);
% 18.65/18.28 bnd_nextState (bnd_constB131, bnd_constB132);
% 18.65/18.28 bnd_nextState (bnd_constB132, bnd_constB133);
% 18.65/18.28 bnd_nextState (bnd_constB133, bnd_constB134);
% 18.65/18.28 bnd_nextState (bnd_constB134, bnd_constB135);
% 18.65/18.28 bnd_nextState (bnd_constB135, bnd_constB136);
% 18.65/18.28 bnd_nextState (bnd_constB136, bnd_constB137);
% 18.65/18.28 bnd_nextState (bnd_constB137, bnd_constB138);
% 18.65/18.28 bnd_nextState (bnd_constB138, bnd_constB139);
% 18.65/18.28 bnd_nextState (bnd_constB139, bnd_constB140);
% 18.65/18.28 bnd_nextState (bnd_constB140, bnd_constB141);
% 18.65/18.28 bnd_nextState (bnd_constB141, bnd_constB142);
% 18.65/18.28 bnd_nextState (bnd_constB142, bnd_constB143);
% 18.65/18.28 bnd_nextState (bnd_constB143, bnd_constB144);
% 18.65/18.28 bnd_nextState (bnd_constB144, bnd_constB145);
% 18.65/18.28 bnd_nextState (bnd_constB145, bnd_constB146);
% 18.65/18.28 bnd_nextState (bnd_constB146, bnd_constB147);
% 18.65/18.28 bnd_nextState (bnd_constB147, bnd_constB148);
% 18.65/18.28 bnd_nextState (bnd_constB148, bnd_constB149);
% 18.65/18.28 bnd_nextState (bnd_constB149, bnd_constB150);
% 18.65/18.28 bnd_nextState (bnd_constB150, bnd_constB151);
% 18.65/18.28 bnd_nextState (bnd_constB151, bnd_constB152);
% 18.65/18.28 bnd_nextState (bnd_constB152, bnd_constB153);
% 18.65/18.28 bnd_nextState (bnd_constB153, bnd_constB154);
% 18.65/18.28 bnd_nextState (bnd_constB154, bnd_constB155);
% 18.65/18.28 bnd_nextState (bnd_constB155, bnd_constB156);
% 18.65/18.28 bnd_nextState (bnd_constB156, bnd_constB157);
% 18.65/18.28 bnd_nextState (bnd_constB157, bnd_constB158);
% 18.65/18.28 bnd_nextState (bnd_constB158, bnd_constB159);
% 18.65/18.28 bnd_nextState (bnd_constB159, bnd_constB160);
% 18.65/18.28 bnd_nextState (bnd_constB160, bnd_constB161);
% 18.65/18.28 bnd_nextState (bnd_constB161, bnd_constB162);
% 18.65/18.28 bnd_nextState (bnd_constB162, bnd_constB163);
% 18.65/18.28 bnd_nextState (bnd_constB163, bnd_constB164);
% 18.65/18.28 bnd_nextState (bnd_constB164, bnd_constB165);
% 18.65/18.28 bnd_nextState (bnd_constB165, bnd_constB166);
% 18.65/18.28 bnd_nextState (bnd_constB166, bnd_constB167);
% 18.65/18.28 bnd_nextState (bnd_constB167, bnd_constB168);
% 18.65/18.28 bnd_nextState (bnd_constB168, bnd_constB169);
% 18.65/18.28 bnd_nextState (bnd_constB169, bnd_constB170);
% 18.65/18.28 bnd_nextState (bnd_constB170, bnd_constB171);
% 18.65/18.28 bnd_nextState (bnd_constB171, bnd_constB172);
% 18.65/18.28 bnd_nextState (bnd_constB172, bnd_constB173);
% 18.65/18.28 bnd_nextState (bnd_constB173, bnd_constB174);
% 18.65/18.28 bnd_nextState (bnd_constB174, bnd_constB175);
% 18.65/18.28 bnd_nextState (bnd_constB175, bnd_constB176);
% 18.65/18.28 bnd_nextState (bnd_constB176, bnd_constB177);
% 18.65/18.28 bnd_nextState (bnd_constB177, bnd_constB178);
% 18.65/18.28 bnd_nextState (bnd_constB178, bnd_constB179);
% 18.65/18.28 bnd_nextState (bnd_constB179, bnd_constB180);
% 18.65/18.28 bnd_nextState (bnd_constB180, bnd_constB181);
% 18.65/18.28 bnd_nextState (bnd_constB181, bnd_constB182);
% 18.65/18.28 bnd_nextState (bnd_constB182, bnd_constB183);
% 18.65/18.28 bnd_nextState (bnd_constB183, bnd_constB184);
% 18.65/18.28 bnd_nextState (bnd_constB184, bnd_constB185);
% 18.65/18.28 bnd_nextState (bnd_constB185, bnd_constB186);
% 18.65/18.28 bnd_nextState (bnd_constB186, bnd_constB187);
% 18.65/18.28 bnd_nextState (bnd_constB187, bnd_constB188);
% 18.65/18.28 bnd_nextState (bnd_constB188, bnd_constB189);
% 18.65/18.28 bnd_nextState (bnd_constB189, bnd_constB190);
% 18.65/18.28 bnd_nextState (bnd_constB190, bnd_constB191);
% 18.65/18.28 bnd_nextState (bnd_constB191, bnd_constB192);
% 18.65/18.28 bnd_nextState (bnd_constB192, bnd_constB193);
% 18.65/18.28 bnd_nextState (bnd_constB193, bnd_constB194);
% 18.65/18.28 bnd_nextState (bnd_constB194, bnd_constB195);
% 18.65/18.28 bnd_nextState (bnd_constB195, bnd_constB196);
% 18.65/18.28 bnd_nextState (bnd_constB196, bnd_constB197);
% 18.65/18.28 bnd_nextState (bnd_constB197, bnd_constB198);
% 18.65/18.28 bnd_nextState (bnd_constB198, bnd_constB199);
% 18.65/18.28 bnd_nextState (bnd_constB199, bnd_constB200); bnd_v1 bnd_constB0;
% 18.65/18.28 ~ bnd_v1 bnd_constB1; bnd_v1 bnd_constB2; ~ bnd_v1 bnd_constB3;
% 18.65/18.28 bnd_v1 bnd_constB4; ~ bnd_v1 bnd_constB5; bnd_v1 bnd_constB6;
% 18.65/18.28 ~ bnd_v1 bnd_constB7; bnd_v1 bnd_constB8; ~ bnd_v1 bnd_constB9;
% 18.65/18.28 bnd_v1 bnd_constB10; ~ bnd_v1 bnd_constB11; bnd_v1 bnd_constB12;
% 18.65/18.28 ~ bnd_v1 bnd_constB13; bnd_v1 bnd_constB14; ~ bnd_v1 bnd_constB15;
% 18.65/18.28 bnd_v1 bnd_constB16; ~ bnd_v1 bnd_constB17; bnd_v1 bnd_constB18;
% 18.65/18.28 ~ bnd_v1 bnd_constB19; bnd_v1 bnd_constB20; ~ bnd_v1 bnd_constB21;
% 18.65/18.28 bnd_v1 bnd_constB22; ~ bnd_v1 bnd_constB23; bnd_v1 bnd_constB24;
% 18.65/18.28 ~ bnd_v1 bnd_constB25; bnd_v1 bnd_constB26; ~ bnd_v1 bnd_constB27;
% 18.65/18.28 bnd_v1 bnd_constB28; ~ bnd_v1 bnd_constB29; bnd_v1 bnd_constB30;
% 18.65/18.28 ~ bnd_v1 bnd_constB31; bnd_v1 bnd_constB32; ~ bnd_v1 bnd_constB33;
% 18.65/18.28 bnd_v1 bnd_constB34; ~ bnd_v1 bnd_constB35; bnd_v1 bnd_constB36;
% 18.65/18.28 ~ bnd_v1 bnd_constB37; bnd_v1 bnd_constB38; ~ bnd_v1 bnd_constB39;
% 18.65/18.28 bnd_v1 bnd_constB40; ~ bnd_v1 bnd_constB41; bnd_v1 bnd_constB42;
% 18.65/18.28 ~ bnd_v1 bnd_constB43; bnd_v1 bnd_constB44; ~ bnd_v1 bnd_constB45;
% 18.65/18.28 bnd_v1 bnd_constB46; ~ bnd_v1 bnd_constB47; bnd_v1 bnd_constB48;
% 18.65/18.28 ~ bnd_v1 bnd_constB49; bnd_v1 bnd_constB50; ~ bnd_v1 bnd_constB51;
% 18.65/18.28 bnd_v1 bnd_constB52; ~ bnd_v1 bnd_constB53; bnd_v1 bnd_constB54;
% 18.65/18.28 ~ bnd_v1 bnd_constB55; bnd_v1 bnd_constB56; ~ bnd_v1 bnd_constB57;
% 18.65/18.28 bnd_v1 bnd_constB58; ~ bnd_v1 bnd_constB59; bnd_v1 bnd_constB60;
% 18.65/18.28 ~ bnd_v1 bnd_constB61; bnd_v1 bnd_constB62; ~ bnd_v1 bnd_constB63;
% 18.65/18.28 bnd_v1 bnd_constB64; ~ bnd_v1 bnd_constB65; bnd_v1 bnd_constB66;
% 18.65/18.28 ~ bnd_v1 bnd_constB67; bnd_v1 bnd_constB68; ~ bnd_v1 bnd_constB69;
% 18.65/18.28 bnd_v1 bnd_constB70; ~ bnd_v1 bnd_constB71; bnd_v1 bnd_constB72;
% 18.65/18.28 ~ bnd_v1 bnd_constB73; bnd_v1 bnd_constB74; ~ bnd_v1 bnd_constB75;
% 18.65/18.28 bnd_v1 bnd_constB76; ~ bnd_v1 bnd_constB77; bnd_v1 bnd_constB78;
% 18.65/18.28 ~ bnd_v1 bnd_constB79; bnd_v1 bnd_constB80; ~ bnd_v1 bnd_constB81;
% 18.65/18.28 bnd_v1 bnd_constB82; ~ bnd_v1 bnd_constB83; bnd_v1 bnd_constB84;
% 18.65/18.28 ~ bnd_v1 bnd_constB85; bnd_v1 bnd_constB86; ~ bnd_v1 bnd_constB87;
% 18.65/18.28 bnd_v1 bnd_constB88; ~ bnd_v1 bnd_constB89; bnd_v1 bnd_constB90;
% 18.65/18.28 ~ bnd_v1 bnd_constB91; bnd_v1 bnd_constB92; ~ bnd_v1 bnd_constB93;
% 18.65/18.28 bnd_v1 bnd_constB94; ~ bnd_v1 bnd_constB95; bnd_v1 bnd_constB96;
% 18.65/18.28 ~ bnd_v1 bnd_constB97; bnd_v1 bnd_constB98; ~ bnd_v1 bnd_constB99;
% 18.65/18.28 bnd_v1 bnd_constB100; ~ bnd_v1 bnd_constB101; bnd_v1 bnd_constB102;
% 18.65/18.28 ~ bnd_v1 bnd_constB103; bnd_v1 bnd_constB104; ~ bnd_v1 bnd_constB105;
% 18.65/18.28 bnd_v1 bnd_constB106; ~ bnd_v1 bnd_constB107; bnd_v1 bnd_constB108;
% 18.65/18.28 ~ bnd_v1 bnd_constB109; bnd_v1 bnd_constB110; ~ bnd_v1 bnd_constB111;
% 18.65/18.28 bnd_v1 bnd_constB112; ~ bnd_v1 bnd_constB113; bnd_v1 bnd_constB114;
% 18.65/18.28 ~ bnd_v1 bnd_constB115; bnd_v1 bnd_constB116; ~ bnd_v1 bnd_constB117;
% 18.65/18.28 bnd_v1 bnd_constB118; ~ bnd_v1 bnd_constB119; bnd_v1 bnd_constB120;
% 18.65/18.28 ~ bnd_v1 bnd_constB121; bnd_v1 bnd_constB122; ~ bnd_v1 bnd_constB123;
% 18.65/18.28 bnd_v1 bnd_constB124; ~ bnd_v1 bnd_constB125; bnd_v1 bnd_constB126;
% 18.65/18.28 ~ bnd_v1 bnd_constB127; bnd_v1 bnd_constB128; ~ bnd_v1 bnd_constB129;
% 18.65/18.28 bnd_v1 bnd_constB130; ~ bnd_v1 bnd_constB131; bnd_v1 bnd_constB132;
% 18.65/18.28 ~ bnd_v1 bnd_constB133; bnd_v1 bnd_constB134; ~ bnd_v1 bnd_constB135;
% 18.65/18.28 bnd_v1 bnd_constB136; ~ bnd_v1 bnd_constB137; bnd_v1 bnd_constB138;
% 18.65/18.28 ~ bnd_v1 bnd_constB139; bnd_v1 bnd_constB140; ~ bnd_v1 bnd_constB141;
% 18.65/18.28 bnd_v1 bnd_constB142; ~ bnd_v1 bnd_constB143; bnd_v1 bnd_constB144;
% 18.65/18.28 ~ bnd_v1 bnd_constB145; bnd_v1 bnd_constB146; ~ bnd_v1 bnd_constB147;
% 18.65/18.28 bnd_v1 bnd_constB148; ~ bnd_v1 bnd_constB149; bnd_v1 bnd_constB150;
% 18.65/18.28 ~ bnd_v1 bnd_constB151; bnd_v1 bnd_constB152; ~ bnd_v1 bnd_constB153;
% 18.65/18.28 bnd_v1 bnd_constB154; ~ bnd_v1 bnd_constB155; bnd_v1 bnd_constB156;
% 18.65/18.28 ~ bnd_v1 bnd_constB157; bnd_v1 bnd_constB158; ~ bnd_v1 bnd_constB159;
% 18.65/18.28 bnd_v1 bnd_constB160; ~ bnd_v1 bnd_constB161; bnd_v1 bnd_constB162;
% 18.65/18.28 ~ bnd_v1 bnd_constB163; bnd_v1 bnd_constB164; ~ bnd_v1 bnd_constB165;
% 18.65/18.28 bnd_v1 bnd_constB166; ~ bnd_v1 bnd_constB167; bnd_v1 bnd_constB168;
% 18.65/18.28 ~ bnd_v1 bnd_constB169; bnd_v1 bnd_constB170; ~ bnd_v1 bnd_constB171;
% 18.65/18.28 bnd_v1 bnd_constB172; ~ bnd_v1 bnd_constB173; bnd_v1 bnd_constB174;
% 18.65/18.28 ~ bnd_v1 bnd_constB175; bnd_v1 bnd_constB176; ~ bnd_v1 bnd_constB177;
% 18.65/18.28 bnd_v1 bnd_constB178; ~ bnd_v1 bnd_constB179; bnd_v1 bnd_constB180;
% 18.65/18.28 ~ bnd_v1 bnd_constB181; bnd_v1 bnd_constB182; ~ bnd_v1 bnd_constB183;
% 18.65/18.28 bnd_v1 bnd_constB184; ~ bnd_v1 bnd_constB185; bnd_v1 bnd_constB186;
% 18.65/18.28 ~ bnd_v1 bnd_constB187; bnd_v1 bnd_constB188; ~ bnd_v1 bnd_constB189;
% 18.65/18.28 bnd_v1 bnd_constB190; ~ bnd_v1 bnd_constB191; bnd_v1 bnd_constB192;
% 18.65/18.28 ~ bnd_v1 bnd_constB193; bnd_v1 bnd_constB194; ~ bnd_v1 bnd_constB195;
% 18.65/18.28 bnd_v1 bnd_constB196; ~ bnd_v1 bnd_constB197; bnd_v1 bnd_constB198;
% 18.65/18.28 ~ bnd_v1 bnd_constB199; bnd_v1 bnd_constB200 |]
% 18.65/18.28 ==> bnd_reachableState VarCurr --> bnd_v82 VarCurr
% 18.65/18.28 Adding axioms...
% 18.65/18.28 Typedef.type_definition_def
% 21.46/21.09 Typedef.type_definition_def
% 68.12/67.62 ...done.
% 68.12/67.69 Ground types: ?'b, bnd_state_type, bnd_bitindex_type
% 68.12/67.69 Translating term (sizes: 1, 1, 1) ...
% 104.81/104.25 Invoking SAT solver...
% 104.81/104.25 No model exists.
% 104.81/104.25 Translating term (sizes: 2, 1, 1) ...
% 142.91/142.25 Invoking SAT solver...
% 142.91/142.26 No model exists.
% 142.91/142.26 Translating term (sizes: 1, 2, 1) ...
% 196.91/196.06 Invoking SAT solver...
% 197.01/196.16 No model exists.
% 197.01/196.16 Translating term (sizes: 1, 1, 2) ...
% 234.00/232.96 Invoking SAT solver...
% 234.00/232.97 No model exists.
% 234.00/232.97 Translating term (sizes: 3, 1, 1) ...
% 277.18/275.87 Invoking SAT solver...
% 277.18/275.88 No model exists.
% 277.18/275.88 Translating term (sizes: 2, 2, 1) ...
% 300.07/298.52 /export/starexec/sandbox/solver/lib/scripts/run-polyml-5.5.2: line 82: 30723 CPU time limit exceeded (core dumped) "$ISABELLE_HOME/lib/scripts/feeder" -p -h "$MLTEXT" -t "$MLEXIT" $FEEDER_OPTS
% 300.07/298.52 30724 (core dumped) | { read FPID; "$POLY" -q -i $ML_OPTIONS; RC="$?"; kill -TERM "$FPID"; exit "$RC"; }
% 300.07/298.53 /export/starexec/sandbox/solver/src/HOL/TPTP/lib/Tools/tptp_refute: line 26: 30669 Exit 152 "$ISABELLE_PROCESS" -q -e "use_thy \"/tmp/$SCRATCH\"; exit 1;" HOL-TPTP
% 300.07/298.53 30670 CPU time limit exceeded (core dumped) | grep --line-buffered -v "^###\|^PROOF FAILED for depth\|^Failure node\|inferences so far. Searching to depth\|^val \|^Loading theory\|^Warning-The type of\|^ monotype.$"
%------------------------------------------------------------------------------