%--------------------------------------------------------------------------
% File     : HWV033-1 : TPTP v8.2.0. Released v2.5.0.
% Domain   : Hardware Verification
% Problem  : Safelogic VHDL design verification obligation
% Version  : [Mar02] axioms : Especial.
% English  :

% Refs     : [CHM02] Claessen et al. (2002), Verification of Hardware Systems
%          : [Mar02] Martensson (2002), Email to G. Sutcliffe
% Source   : [Mar02]
% Names    :

% Status   : Unsatisfiable
% Rating   : 0.25 v8.2.0, 0.24 v8.1.0, 0.37 v7.4.0, 0.35 v7.3.0, 0.33 v7.1.0, 0.25 v7.0.0, 0.40 v6.4.0, 0.47 v6.3.0, 0.36 v6.2.0, 0.30 v6.1.0, 0.50 v5.5.0, 0.70 v5.3.0, 0.78 v5.2.0, 0.69 v5.1.0, 0.71 v5.0.0, 0.57 v4.1.0, 0.62 v4.0.1, 0.45 v4.0.0, 0.36 v3.7.0, 0.20 v3.5.0, 0.27 v3.4.0, 0.42 v3.3.0, 0.57 v3.2.0, 0.69 v3.1.0, 0.64 v2.7.0, 0.67 v2.6.0, 0.88 v2.5.0
% Syntax   : Number of clauses     :   93 (   9 unt;  64 nHn;  84 RR)
%            Number of literals    :  372 (  50 equ; 156 neg)
%            Maximal clause size   :    7 (   4 avg)
%            Maximal term depth    :    3 (   1 avg)
%            Number of predicates  :   13 (  12 usr;   0 prp; 1-3 aty)
%            Number of functors    :   11 (  11 usr;   4 con; 0-2 aty)
%            Number of variables   :  139 (   5 sgn)
% SPC      : CNF_UNS_RFO_SEQ_NHN

% Comments :
%--------------------------------------------------------------------------
%----Include equality
%----Include VHDL design axioms
include('Axioms/HWV003-0.ax').
%--------------------------------------------------------------------------
cnf(quest_1,negated_conjecture,
    ~ gt(rd_level(t_139),minus(fifo_length,n1)) ).

cnf(quest_2,negated_conjecture,
    gt(rd_level(plus(t_139,n1)),minus(fifo_length,n1)) ).

cnf(quest_3,negated_conjecture,
    gt(fifo_length,n0) ).

%--------------------------------------------------------------------------