%--------------------------------------------------------------------------
% File     : HWV009-3 : TPTP v9.0.0. Released v2.5.0.
% Domain   : Hardware Verification
% Problem  : Safelogic VHDL design verification obligation
% Version  : [Mar02] axioms : Especial.
% English  :

% Refs     : [CHM02] Claessen et al. (2002), Verification of Hardware Systems
%          : [Mar02] Martensson (2002), Email to G. Sutcliffe
% Source   : [Mar02]
% Names    :

% Status   : Unsatisfiable
% Rating   : 0.05 v7.4.0, 0.06 v7.3.0, 0.00 v7.0.0, 0.07 v6.4.0, 0.00 v5.5.0, 0.10 v5.3.0, 0.06 v5.0.0, 0.00 v3.4.0, 0.08 v3.3.0, 0.21 v3.2.0, 0.08 v3.1.0, 0.09 v2.7.0, 0.08 v2.6.0, 0.00 v2.5.0
% Syntax   : Number of clauses     :  135 (  27 unt;  62 nHn;  94 RR)
%            Number of literals    :  417 (  80 equ; 186 neg)
%            Maximal clause size   :   10 (   3 avg)
%            Maximal term depth    :    5 (   2 avg)
%            Number of predicates  :    4 (   3 usr;   0 prp; 1-2 aty)
%            Number of functors    :   46 (  46 usr;   8 con; 0-3 aty)
%            Number of variables   :  225 (  20 sgn)
% SPC      : CNF_UNS_RFO_SEQ_NHN

% Comments :
%--------------------------------------------------------------------------
%----Include equality
%----Include VHDL design axioms
include('Axioms/HWV004-0.ax').
%--------------------------------------------------------------------------
cnf(quest_1,negated_conjecture,
    p__pred_(fwork_DOTfifo_DOTrtl_DOTreset_(t_206)) ).

cnf(quest_2,negated_conjecture,
    p__pred_(fwork_DOTfifo_DOTrtl_DOTwr__error_(f_ADD_(t_206,n1))) ).

%--------------------------------------------------------------------------