164.88/140.63	cp: cannot stat ‘/export/starexec/sandbox/benchmark/Problems/Axioms’: No such file or directory
1742.31/1380.49	% SZS status Started for HL400003+4.p
1742.31/1380.49	% SZS status Theorem for HL400003+4.p
1742.31/1380.49	% SZS status Ended for HL400003+4.p
1742.34/1380.56	% SZS status Started for HL400004+4.p
1742.34/1380.56	% SZS status Theorem for HL400004+4.p
1742.34/1380.56	% SZS status Ended for HL400004+4.p
1742.34/1380.57	% SZS status Started for HL400005+5.p
1742.34/1380.57	% SZS status Theorem for HL400005+5.p
1742.34/1380.57	% SZS status Ended for HL400005+5.p
1742.34/1380.57	% SZS status Started for HL400006+4.p
1742.34/1380.57	% SZS status Theorem for HL400006+4.p
1742.34/1380.57	% SZS status Ended for HL400006+4.p
1742.73/1380.59	% SZS status Started for HL400007+4.p
1742.73/1380.59	% SZS status Theorem for HL400007+4.p
1742.73/1380.59	% SZS status Ended for HL400007+4.p
1742.73/1380.61	% SZS status Started for HL400003+5.p
1742.73/1380.61	% SZS status Theorem for HL400003+5.p
1742.73/1380.61	% SZS status Ended for HL400003+5.p
1742.73/1380.61	% SZS status Started for HL400005+4.p
1742.73/1380.61	% SZS status Theorem for HL400005+4.p
1742.73/1380.61	% SZS status Ended for HL400005+4.p
1742.73/1380.61	% SZS status Started for HL400006+5.p
1742.73/1380.61	% SZS status Theorem for HL400006+5.p
1742.73/1380.61	% SZS status Ended for HL400006+5.p
1742.93/1380.68	% SZS status Started for HL400007+5.p
1742.93/1380.68	% SZS status Theorem for HL400007+5.p
1742.93/1380.68	% SZS status Ended for HL400007+5.p
1742.93/1380.68	% SZS status Started for HL400010+5.p
1742.93/1380.68	% SZS status Theorem for HL400010+5.p
1742.93/1380.68	% SZS status Ended for HL400010+5.p
1742.93/1380.70	% SZS status Started for HL400010+4.p
1742.93/1380.70	% SZS status Theorem for HL400010+4.p
1742.93/1380.70	% SZS status Ended for HL400010+4.p
1742.93/1380.70	% SZS status Started for HL400008+5.p
1742.93/1380.70	% SZS status Theorem for HL400008+5.p
1742.93/1380.70	% SZS status Ended for HL400008+5.p
1742.93/1380.71	% SZS status Started for HL400009+5.p
1742.93/1380.71	% SZS status Theorem for HL400009+5.p
1742.93/1380.71	% SZS status Ended for HL400009+5.p
1743.45/1380.72	% SZS status Started for HL400011+4.p
1743.45/1380.72	% SZS status Theorem for HL400011+4.p
1743.45/1380.72	% SZS status Ended for HL400011+4.p
1743.45/1380.73	% SZS status Started for HL400011+5.p
1743.45/1380.73	% SZS status Theorem for HL400011+5.p
1743.45/1380.73	% SZS status Ended for HL400011+5.p
1743.45/1380.74	% SZS status Started for HL400012+4.p
1743.45/1380.74	% SZS status Theorem for HL400012+4.p
1743.45/1380.74	% SZS status Ended for HL400012+4.p
1743.45/1380.74	% SZS status Started for HL400008+4.p
1743.45/1380.74	% SZS status Theorem for HL400008+4.p
1743.45/1380.74	% SZS status Ended for HL400008+4.p
1743.45/1380.74	% SZS status Started for HL400012+5.p
1743.45/1380.74	% SZS status Theorem for HL400012+5.p
1743.45/1380.74	% SZS status Ended for HL400012+5.p
1743.45/1380.76	% SZS status Started for HL400013+5.p
1743.45/1380.76	% SZS status Theorem for HL400013+5.p
1743.45/1380.76	% SZS status Ended for HL400013+5.p
1743.45/1380.76	% SZS status Started for HL400013+4.p
1743.45/1380.76	% SZS status Theorem for HL400013+4.p
1743.45/1380.76	% SZS status Ended for HL400013+4.p
1743.45/1380.77	% SZS status Started for HL400014+4.p
1743.45/1380.77	% SZS status Theorem for HL400014+4.p
1743.45/1380.77	% SZS status Ended for HL400014+4.p
1743.97/1380.78	% SZS status Started for HL400009+4.p
1743.97/1380.78	% SZS status Theorem for HL400009+4.p
1743.97/1380.78	% SZS status Ended for HL400009+4.p
1743.97/1380.78	% SZS status Started for HL400014+5.p
1743.97/1380.78	% SZS status Theorem for HL400014+5.p
1743.97/1380.78	% SZS status Ended for HL400014+5.p
1743.97/1380.78	% SZS status Started for HL400015+4.p
1743.97/1380.78	% SZS status Theorem for HL400015+4.p
1743.97/1380.78	% SZS status Ended for HL400015+4.p
1743.97/1380.78	% SZS status Started for HL400015+5.p
1743.97/1380.78	% SZS status Theorem for HL400015+5.p
1743.97/1380.78	% SZS status Ended for HL400015+5.p
1743.97/1380.79	% SZS status Started for HL400017+4.p
1743.97/1380.79	% SZS status Theorem for HL400017+4.p
1743.97/1380.79	% SZS status Ended for HL400017+4.p
1743.97/1380.80	% SZS status Started for HL400017+5.p
1743.97/1380.80	% SZS status Theorem for HL400017+5.p
1743.97/1380.80	% SZS status Ended for HL400017+5.p
1743.97/1380.81	% SZS status Started for HL400018+4.p
1743.97/1380.81	% SZS status Theorem for HL400018+4.p
1743.97/1380.81	% SZS status Ended for HL400018+4.p
1743.97/1380.82	% SZS status Started for HL400018+5.p
1743.97/1380.82	% SZS status Theorem for HL400018+5.p
1743.97/1380.82	% SZS status Ended for HL400018+5.p
1743.97/1380.82	% SZS status Started for HL400019+4.p
1743.97/1380.82	% SZS status Theorem for HL400019+4.p
1743.97/1380.82	% SZS status Ended for HL400019+4.p
1743.97/1380.82	% SZS status Started for HL400019+5.p
1743.97/1380.82	% SZS status Theorem for HL400019+5.p
1743.97/1380.82	% SZS status Ended for HL400019+5.p
1743.97/1380.83	% SZS status Started for HL400020+4.p
1743.97/1380.83	% SZS status Theorem for HL400020+4.p
1743.97/1380.83	% SZS status Ended for HL400020+4.p
1743.97/1380.84	% SZS status Started for HL400020+5.p
1743.97/1380.84	% SZS status Theorem for HL400020+5.p
1743.97/1380.84	% SZS status Ended for HL400020+5.p
1743.97/1380.84	% SZS status Started for HL400021+4.p
1743.97/1380.84	% SZS status Theorem for HL400021+4.p
1743.97/1380.84	% SZS status Ended for HL400021+4.p
1743.97/1380.85	% SZS status Started for HL400021+5.p
1743.97/1380.85	% SZS status Theorem for HL400021+5.p
1743.97/1380.85	% SZS status Ended for HL400021+5.p
1743.97/1380.85	% SZS status Started for HL400022+4.p
1743.97/1380.85	% SZS status Theorem for HL400022+4.p
1743.97/1380.85	% SZS status Ended for HL400022+4.p
1744.79/1380.86	% SZS status Started for HL400022+5.p
1744.79/1380.86	% SZS status Theorem for HL400022+5.p
1744.79/1380.86	% SZS status Ended for HL400022+5.p
1744.79/1380.87	% SZS status Started for HL400024+5.p
1744.79/1380.87	% SZS status Theorem for HL400024+5.p
1744.79/1380.87	% SZS status Ended for HL400024+5.p
1744.79/1380.87	% SZS status Started for HL400024+4.p
1744.79/1380.87	% SZS status Theorem for HL400024+4.p
1744.79/1380.87	% SZS status Ended for HL400024+4.p
1744.93/1380.88	% SZS status Started for HL400025+4.p
1744.93/1380.88	% SZS status Theorem for HL400025+4.p
1744.93/1380.88	% SZS status Ended for HL400025+4.p
1744.93/1380.88	% SZS status Started for HL400025+5.p
1744.93/1380.88	% SZS status Theorem for HL400025+5.p
1744.93/1380.88	% SZS status Ended for HL400025+5.p
1744.93/1380.89	% SZS status Started for HL400027+4.p
1744.93/1380.89	% SZS status Theorem for HL400027+4.p
1744.93/1380.89	% SZS status Ended for HL400027+4.p
1744.93/1380.89	% SZS status Started for HL400027+5.p
1744.93/1380.89	% SZS status Theorem for HL400027+5.p
1744.93/1380.89	% SZS status Ended for HL400027+5.p
1744.93/1380.91	% SZS status Started for HL400028+4.p
1744.93/1380.91	% SZS status Theorem for HL400028+4.p
1744.93/1380.91	% SZS status Ended for HL400028+4.p
1744.93/1380.91	% SZS status Started for HL400028+5.p
1744.93/1380.91	% SZS status Theorem for HL400028+5.p
1744.93/1380.91	% SZS status Ended for HL400028+5.p
1745.21/1380.92	% SZS status Started for HL400029+4.p
1745.21/1380.92	% SZS status Theorem for HL400029+4.p
1745.21/1380.92	% SZS status Ended for HL400029+4.p
1745.21/1380.92	% SZS status Started for HL400029+5.p
1745.21/1380.92	% SZS status Theorem for HL400029+5.p
1745.21/1380.92	% SZS status Ended for HL400029+5.p
1745.21/1380.92	% SZS status Started for HL400031+4.p
1745.21/1380.92	% SZS status Theorem for HL400031+4.p
1745.21/1380.92	% SZS status Ended for HL400031+4.p
1745.21/1380.93	% SZS status Started for HL400031+5.p
1745.21/1380.93	% SZS status Theorem for HL400031+5.p
1745.21/1380.93	% SZS status Ended for HL400031+5.p
1745.21/1380.93	% SZS status Started for HL400032+4.p
1745.21/1380.93	% SZS status Theorem for HL400032+4.p
1745.21/1380.93	% SZS status Ended for HL400032+4.p
1745.43/1380.95	% SZS status Started for HL400032+5.p
1745.43/1380.95	% SZS status Theorem for HL400032+5.p
1745.43/1380.95	% SZS status Ended for HL400032+5.p
1745.43/1380.95	% SZS status Started for HL400033+4.p
1745.43/1380.95	% SZS status Theorem for HL400033+4.p
1745.43/1380.95	% SZS status Ended for HL400033+4.p
1745.43/1380.96	% SZS status Started for HL400033+5.p
1745.43/1380.96	% SZS status Theorem for HL400033+5.p
1745.43/1380.96	% SZS status Ended for HL400033+5.p
1745.43/1380.99	% SZS status Started for HL400036+5.p
1745.43/1380.99	% SZS status Theorem for HL400036+5.p
1745.43/1380.99	% SZS status Ended for HL400036+5.p
1745.43/1381.00	% SZS status Started for HL400037+4.p
1745.43/1381.00	% SZS status Theorem for HL400037+4.p
1745.43/1381.00	% SZS status Ended for HL400037+4.p
1745.70/1381.03	% SZS status Started for HL400037+5.p
1745.70/1381.03	% SZS status Theorem for HL400037+5.p
1745.70/1381.03	% SZS status Ended for HL400037+5.p
1745.70/1381.08	% SZS status Started for HL400038+5.p
1745.70/1381.08	% SZS status Theorem for HL400038+5.p
1745.70/1381.08	% SZS status Ended for HL400038+5.p
1745.70/1381.09	% SZS status Started for HL400034+4.p
1745.70/1381.09	% SZS status Theorem for HL400034+4.p
1745.70/1381.09	% SZS status Ended for HL400034+4.p
1746.55/1381.12	% SZS status Started for HL400035+4.p
1746.55/1381.12	% SZS status Theorem for HL400035+4.p
1746.55/1381.12	% SZS status Ended for HL400035+4.p
1746.55/1381.14	% SZS status Started for HL400036+4.p
1746.55/1381.14	% SZS status Theorem for HL400036+4.p
1746.55/1381.14	% SZS status Ended for HL400036+4.p
1747.05/1381.18	% SZS status Started for HL400038+4.p
1747.05/1381.18	% SZS status Theorem for HL400038+4.p
1747.05/1381.18	% SZS status Ended for HL400038+4.p
1747.15/1381.20	% SZS status Started for HL400040+5.p
1747.15/1381.20	% SZS status Theorem for HL400040+5.p
1747.15/1381.20	% SZS status Ended for HL400040+5.p
1747.56/1381.33	% SZS status Started for HL400040+4.p
1747.56/1381.33	% SZS status Theorem for HL400040+4.p
1747.56/1381.33	% SZS status Ended for HL400040+4.p
1748.46/1381.54	% SZS status Started for HL400034+5.p
1748.46/1381.54	% SZS status Theorem for HL400034+5.p
1748.46/1381.54	% SZS status Ended for HL400034+5.p
1753.71/1382.02	% SZS status Started for HL400035+5.p
1753.71/1382.02	% SZS status Theorem for HL400035+5.p
1753.71/1382.02	% SZS status Ended for HL400035+5.p
1806.18/1388.65	% SZS status Started for HL400004+5.p
1806.18/1388.65	% SZS status GaveUp for HL400004+5.p
1806.18/1388.65	% SZS status Ended for HL400004+5.p
1810.27/1389.14	% SZS status Started for HL400039+5.p
1810.27/1389.14	% SZS status GaveUp for HL400039+5.p
1810.27/1389.14	% SZS status Ended for HL400039+5.p
1811.57/1389.30	% SZS status Started for HL400041+5.p
1811.57/1389.30	% SZS status GaveUp for HL400041+5.p
1811.57/1389.30	% SZS status Ended for HL400041+5.p
1811.73/1389.37	% SZS status Started for HL400039+4.p
1811.73/1389.37	% SZS status GaveUp for HL400039+4.p
1811.73/1389.37	% SZS status Ended for HL400039+4.p
1811.73/1389.39	% SZS status Started for HL400044+4.p
1811.73/1389.39	% SZS status Theorem for HL400044+4.p
1811.73/1389.39	% SZS status Ended for HL400044+4.p
1811.73/1389.40	% SZS status Started for HL400044+5.p
1811.73/1389.40	% SZS status Theorem for HL400044+5.p
1811.73/1389.40	% SZS status Ended for HL400044+5.p
1812.49/1389.43	% SZS status Started for HL400041+4.p
1812.49/1389.43	% SZS status GaveUp for HL400041+4.p
1812.49/1389.43	% SZS status Ended for HL400041+4.p
1812.49/1389.44	% SZS status Started for HL400042+4.p
1812.49/1389.44	% SZS status GaveUp for HL400042+4.p
1812.49/1389.44	% SZS status Ended for HL400042+4.p
1812.49/1389.48	% SZS status Started for HL400045+5.p
1812.49/1389.48	% SZS status Theorem for HL400045+5.p
1812.49/1389.48	% SZS status Ended for HL400045+5.p
1812.87/1389.51	% SZS status Started for HL400046+5.p
1812.87/1389.51	% SZS status Theorem for HL400046+5.p
1812.87/1389.51	% SZS status Ended for HL400046+5.p
1812.87/1389.55	% SZS status Started for HL400047+5.p
1812.87/1389.55	% SZS status Theorem for HL400047+5.p
1812.87/1389.55	% SZS status Ended for HL400047+5.p
1814.28/1389.61	% SZS status Started for HL400042+5.p
1814.28/1389.61	% SZS status GaveUp for HL400042+5.p
1814.28/1389.61	% SZS status Ended for HL400042+5.p
1814.51/1389.63	% SZS status Started for HL400046+4.p
1814.51/1389.63	% SZS status Theorem for HL400046+4.p
1814.51/1389.63	% SZS status Ended for HL400046+4.p
1814.54/1389.65	% SZS status Started for HL400049+5.p
1814.54/1389.65	% SZS status Theorem for HL400049+5.p
1814.54/1389.65	% SZS status Ended for HL400049+5.p
1814.54/1389.67	% SZS status Started for HL400045+4.p
1814.54/1389.67	% SZS status Theorem for HL400045+4.p
1814.54/1389.67	% SZS status Ended for HL400045+4.p
1814.54/1389.69	% SZS status Started for HL400047+4.p
1814.54/1389.69	% SZS status Theorem for HL400047+4.p
1814.54/1389.69	% SZS status Ended for HL400047+4.p
1814.94/1389.73	% SZS status Started for HL400050+5.p
1814.94/1389.73	% SZS status Theorem for HL400050+5.p
1814.94/1389.73	% SZS status Ended for HL400050+5.p
1814.94/1389.76	% SZS status Started for HL400049+4.p
1814.94/1389.76	% SZS status Theorem for HL400049+4.p
1814.94/1389.76	% SZS status Ended for HL400049+4.p
1815.20/1389.78	% SZS status Started for HL400051+5.p
1815.20/1389.78	% SZS status Theorem for HL400051+5.p
1815.20/1389.78	% SZS status Ended for HL400051+5.p
1815.20/1389.86	% SZS status Started for HL400052+5.p
1815.20/1389.86	% SZS status Theorem for HL400052+5.p
1815.20/1389.86	% SZS status Ended for HL400052+5.p
1815.53/1389.87	% SZS status Started for HL400050+4.p
1815.53/1389.87	% SZS status Theorem for HL400050+4.p
1815.53/1389.87	% SZS status Ended for HL400050+4.p
1815.81/1389.90	% SZS status Started for HL400054+4.p
1815.81/1389.90	% SZS status Theorem for HL400054+4.p
1815.81/1389.90	% SZS status Ended for HL400054+4.p
1815.81/1389.91	% SZS status Started for HL400053+5.p
1815.81/1389.91	% SZS status Theorem for HL400053+5.p
1815.81/1389.91	% SZS status Ended for HL400053+5.p
1816.01/1389.99	% SZS status Started for HL400054+5.p
1816.01/1389.99	% SZS status Theorem for HL400054+5.p
1816.01/1389.99	% SZS status Ended for HL400054+5.p
1816.01/1390.00	% SZS status Started for HL400052+4.p
1816.01/1390.00	% SZS status Theorem for HL400052+4.p
1816.01/1390.00	% SZS status Ended for HL400052+4.p
1816.51/1390.03	% SZS status Started for HL400057+4.p
1816.51/1390.03	% SZS status Theorem for HL400057+4.p
1816.51/1390.03	% SZS status Ended for HL400057+4.p
1816.51/1390.04	% SZS status Started for HL400056+5.p
1816.51/1390.04	% SZS status Theorem for HL400056+5.p
1816.51/1390.04	% SZS status Ended for HL400056+5.p
1816.75/1390.07	% SZS status Started for HL400053+4.p
1816.75/1390.07	% SZS status Theorem for HL400053+4.p
1816.75/1390.07	% SZS status Ended for HL400053+4.p
1816.75/1390.08	% SZS status Started for HL400051+4.p
1816.75/1390.08	% SZS status Theorem for HL400051+4.p
1816.75/1390.08	% SZS status Ended for HL400051+4.p
1816.75/1390.11	% SZS status Started for HL400060+4.p
1816.75/1390.11	% SZS status Theorem for HL400060+4.p
1816.75/1390.11	% SZS status Ended for HL400060+4.p
1816.75/1390.14	% SZS status Started for HL400057+5.p
1816.75/1390.14	% SZS status Theorem for HL400057+5.p
1816.75/1390.14	% SZS status Ended for HL400057+5.p
1818.78/1390.19	% SZS status Started for HL400043+4.p
1818.78/1390.19	% SZS status GaveUp for HL400043+4.p
1818.78/1390.19	% SZS status Ended for HL400043+4.p
1818.78/1390.20	% SZS status Started for HL400056+4.p
1818.78/1390.20	% SZS status Theorem for HL400056+4.p
1818.78/1390.20	% SZS status Ended for HL400056+4.p
1818.78/1390.20	% SZS status Started for HL400059+5.p
1818.78/1390.20	% SZS status Theorem for HL400059+5.p
1818.78/1390.20	% SZS status Ended for HL400059+5.p
1819.09/1390.23	% SZS status Started for HL400060+5.p
1819.09/1390.23	% SZS status Theorem for HL400060+5.p
1819.09/1390.23	% SZS status Ended for HL400060+5.p
1819.29/1390.24	% SZS status Started for HL400063+4.p
1819.29/1390.24	% SZS status Theorem for HL400063+4.p
1819.29/1390.24	% SZS status Ended for HL400063+4.p
1819.29/1390.30	% SZS status Started for HL400061+5.p
1819.29/1390.30	% SZS status Theorem for HL400061+5.p
1819.29/1390.30	% SZS status Ended for HL400061+5.p
1819.29/1390.33	% SZS status Started for HL400059+4.p
1819.29/1390.33	% SZS status Theorem for HL400059+4.p
1819.29/1390.33	% SZS status Ended for HL400059+4.p
1819.71/1390.36	% SZS status Started for HL400062+5.p
1819.71/1390.36	% SZS status Theorem for HL400062+5.p
1819.71/1390.36	% SZS status Ended for HL400062+5.p
1819.71/1390.38	% SZS status Started for HL400066+4.p
1819.71/1390.38	% SZS status Theorem for HL400066+4.p
1819.71/1390.38	% SZS status Ended for HL400066+4.p
1819.71/1390.38	% SZS status Started for HL400063+5.p
1819.71/1390.38	% SZS status Theorem for HL400063+5.p
1819.71/1390.38	% SZS status Ended for HL400063+5.p
1820.20/1390.41	% SZS status Started for HL400066+5.p
1820.20/1390.41	% SZS status Theorem for HL400066+5.p
1820.20/1390.41	% SZS status Ended for HL400066+5.p
1820.20/1390.42	% SZS status Started for HL400068+4.p
1820.20/1390.42	% SZS status Theorem for HL400068+4.p
1820.20/1390.42	% SZS status Ended for HL400068+4.p
1820.20/1390.43	% SZS status Started for HL400061+4.p
1820.20/1390.43	% SZS status Theorem for HL400061+4.p
1820.20/1390.43	% SZS status Ended for HL400061+4.p
1820.20/1390.44	% SZS status Started for HL400068+5.p
1820.20/1390.44	% SZS status Theorem for HL400068+5.p
1820.20/1390.44	% SZS status Ended for HL400068+5.p
1820.46/1390.45	% SZS status Started for HL400069+4.p
1820.46/1390.45	% SZS status Theorem for HL400069+4.p
1820.46/1390.45	% SZS status Ended for HL400069+4.p
1820.52/1390.47	% SZS status Started for HL400070+4.p
1820.52/1390.47	% SZS status Theorem for HL400070+4.p
1820.52/1390.47	% SZS status Ended for HL400070+4.p
1820.52/1390.47	% SZS status Started for HL400069+5.p
1820.52/1390.47	% SZS status Theorem for HL400069+5.p
1820.52/1390.47	% SZS status Ended for HL400069+5.p
1820.52/1390.48	% SZS status Started for HL400065+5.p
1820.52/1390.48	% SZS status Theorem for HL400065+5.p
1820.52/1390.48	% SZS status Ended for HL400065+5.p
1820.52/1390.49	% SZS status Started for HL400070+5.p
1820.52/1390.49	% SZS status Theorem for HL400070+5.p
1820.52/1390.49	% SZS status Ended for HL400070+5.p
1820.52/1390.50	% SZS status Started for HL400062+4.p
1820.52/1390.50	% SZS status Theorem for HL400062+4.p
1820.52/1390.50	% SZS status Ended for HL400062+4.p
1821.21/1390.54	% SZS status Started for HL400074+4.p
1821.21/1390.54	% SZS status Theorem for HL400074+4.p
1821.21/1390.54	% SZS status Ended for HL400074+4.p
1821.21/1390.54	% SZS status Started for HL400074+5.p
1821.21/1390.54	% SZS status Theorem for HL400074+5.p
1821.21/1390.54	% SZS status Ended for HL400074+5.p
1821.21/1390.55	% SZS status Started for HL400065+4.p
1821.21/1390.55	% SZS status Theorem for HL400065+4.p
1821.21/1390.55	% SZS status Ended for HL400065+4.p
1821.21/1390.59	% SZS status Started for HL400075+4.p
1821.21/1390.59	% SZS status Theorem for HL400075+4.p
1821.21/1390.59	% SZS status Ended for HL400075+4.p
1821.21/1390.59	% SZS status Started for HL400075+5.p
1821.21/1390.59	% SZS status Theorem for HL400075+5.p
1821.21/1390.59	% SZS status Ended for HL400075+5.p
1821.21/1390.60	% SZS status Started for HL400076+4.p
1821.21/1390.60	% SZS status Theorem for HL400076+4.p
1821.21/1390.60	% SZS status Ended for HL400076+4.p
1821.86/1390.63	% SZS status Started for HL400072+5.p
1821.86/1390.63	% SZS status Theorem for HL400072+5.p
1821.86/1390.63	% SZS status Ended for HL400072+5.p
1821.86/1390.64	% SZS status Started for HL400076+5.p
1821.86/1390.64	% SZS status Theorem for HL400076+5.p
1821.86/1390.64	% SZS status Ended for HL400076+5.p
1821.86/1390.64	% SZS status Started for HL400073+5.p
1821.86/1390.64	% SZS status Theorem for HL400073+5.p
1821.86/1390.64	% SZS status Ended for HL400073+5.p
1822.27/1390.69	% SZS status Started for HL400080+4.p
1822.27/1390.69	% SZS status Theorem for HL400080+4.p
1822.27/1390.69	% SZS status Ended for HL400080+4.p
1822.27/1390.74	% SZS status Started for HL400080+5.p
1822.27/1390.74	% SZS status Theorem for HL400080+5.p
1822.27/1390.74	% SZS status Ended for HL400080+5.p
1822.27/1390.76	% SZS status Started for HL400072+4.p
1822.27/1390.76	% SZS status Theorem for HL400072+4.p
1822.27/1390.76	% SZS status Ended for HL400072+4.p
1823.50/1390.77	% SZS status Started for HL400077+5.p
1823.50/1390.77	% SZS status Theorem for HL400077+5.p
1823.50/1390.77	% SZS status Ended for HL400077+5.p
1823.50/1390.77	% SZS status Started for HL400073+4.p
1823.50/1390.77	% SZS status Theorem for HL400073+4.p
1823.50/1390.77	% SZS status Ended for HL400073+4.p
1823.59/1390.80	% SZS status Started for HL400078+5.p
1823.59/1390.80	% SZS status Theorem for HL400078+5.p
1823.59/1390.80	% SZS status Ended for HL400078+5.p
1823.86/1390.89	% SZS status Started for HL400077+4.p
1823.86/1390.89	% SZS status Theorem for HL400077+4.p
1823.86/1390.89	% SZS status Ended for HL400077+4.p
1824.10/1390.93	% SZS status Started for HL400078+4.p
1824.10/1390.93	% SZS status Theorem for HL400078+4.p
1824.10/1390.93	% SZS status Ended for HL400078+4.p
1824.10/1390.93	% SZS status Started for HL400081+5.p
1824.10/1390.93	% SZS status Theorem for HL400081+5.p
1824.10/1390.93	% SZS status Ended for HL400081+5.p
1824.10/1390.94	% SZS status Started for HL400082+5.p
1824.10/1390.94	% SZS status Theorem for HL400082+5.p
1824.10/1390.94	% SZS status Ended for HL400082+5.p
1824.53/1391.02	% SZS status Started for HL400085+4.p
1824.53/1391.02	% SZS status Theorem for HL400085+4.p
1824.53/1391.02	% SZS status Ended for HL400085+4.p
1824.68/1391.07	% SZS status Started for HL400081+4.p
1824.68/1391.07	% SZS status Theorem for HL400081+4.p
1824.68/1391.07	% SZS status Ended for HL400081+4.p
1825.02/1391.08	% SZS status Started for HL400083+5.p
1825.02/1391.08	% SZS status Theorem for HL400083+5.p
1825.02/1391.08	% SZS status Ended for HL400083+5.p
1825.02/1391.09	% SZS status Started for HL400082+4.p
1825.02/1391.09	% SZS status Theorem for HL400082+4.p
1825.02/1391.09	% SZS status Ended for HL400082+4.p
1825.56/1391.13	% SZS status Started for HL400084+5.p
1825.56/1391.13	% SZS status Theorem for HL400084+5.p
1825.56/1391.13	% SZS status Ended for HL400084+5.p
1825.79/1391.16	% SZS status Started for HL400083+4.p
1825.79/1391.16	% SZS status Theorem for HL400083+4.p
1825.79/1391.16	% SZS status Ended for HL400083+4.p
1827.61/1391.30	% SZS status Started for HL400084+4.p
1827.61/1391.30	% SZS status Theorem for HL400084+4.p
1827.61/1391.30	% SZS status Ended for HL400084+4.p
1827.61/1391.34	% SZS status Started for HL400087+5.p
1827.61/1391.34	% SZS status Theorem for HL400087+5.p
1827.61/1391.34	% SZS status Ended for HL400087+5.p
1828.60/1391.47	% SZS status Started for HL400087+4.p
1828.60/1391.47	% SZS status Theorem for HL400087+4.p
1828.60/1391.47	% SZS status Ended for HL400087+4.p
1829.06/1391.51	% SZS status Started for HL400086+5.p
1829.06/1391.51	% SZS status Theorem for HL400086+5.p
1829.06/1391.51	% SZS status Ended for HL400086+5.p
1829.06/1391.54	% SZS status Started for HL400086+4.p
1829.06/1391.54	% SZS status Theorem for HL400086+4.p
1829.06/1391.54	% SZS status Ended for HL400086+4.p
1829.80/1391.77	% SZS status Started for HL400090+4.p
1829.80/1391.77	% SZS status Theorem for HL400090+4.p
1829.80/1391.77	% SZS status Ended for HL400090+4.p
1870.52/1396.76	% SZS status Started for HL400043+5.p
1870.52/1396.76	% SZS status GaveUp for HL400043+5.p
1870.52/1396.76	% SZS status Ended for HL400043+5.p
1889.95/1399.15	% SZS status Started for HL400085+5.p
1889.95/1399.15	% SZS status GaveUp for HL400085+5.p
1889.95/1399.15	% SZS status Ended for HL400085+5.p
1890.67/1399.24	% SZS status Started for HL400089+4.p
1890.67/1399.24	% SZS status GaveUp for HL400089+4.p
1890.67/1399.24	% SZS status Ended for HL400089+4.p
1891.67/1399.39	% SZS status Started for HL400089+5.p
1891.67/1399.39	% SZS status GaveUp for HL400089+5.p
1891.67/1399.39	% SZS status Ended for HL400089+5.p
1892.41/1399.57	% SZS status Started for HL400090+5.p
1892.41/1399.57	% SZS status GaveUp for HL400090+5.p
1892.41/1399.57	% SZS status Ended for HL400090+5.p
1892.83/1399.63	% SZS status Started for HL400093+4.p
1892.83/1399.63	% SZS status Theorem for HL400093+4.p
1892.83/1399.63	% SZS status Ended for HL400093+4.p
1892.83/1399.65	% SZS status Started for HL400091+4.p
1892.83/1399.65	% SZS status GaveUp for HL400091+4.p
1892.83/1399.65	% SZS status Ended for HL400091+4.p
1892.83/1399.67	% SZS status Started for HL400091+5.p
1892.83/1399.67	% SZS status GaveUp for HL400091+5.p
1892.83/1399.67	% SZS status Ended for HL400091+5.p
1896.14/1399.93	% SZS status Started for HL400096+5.p
1896.14/1399.93	% SZS status Theorem for HL400096+5.p
1896.14/1399.93	% SZS status Ended for HL400096+5.p
1896.14/1399.94	% SZS status Started for HL400094+4.p
1896.14/1399.94	% SZS status Theorem for HL400094+4.p
1896.14/1399.94	% SZS status Ended for HL400094+4.p
1896.58/1400.02	% SZS status Started for HL400092+4.p
1896.58/1400.02	% SZS status GaveUp for HL400092+4.p
1896.58/1400.02	% SZS status Ended for HL400092+4.p
1897.62/1400.25	% SZS status Started for HL400096+4.p
1897.62/1400.25	% SZS status Theorem for HL400096+4.p
1897.62/1400.25	% SZS status Ended for HL400096+4.p
1897.89/1400.30	% SZS status Started for HL400100+5.p
1897.89/1400.30	% SZS status Theorem for HL400100+5.p
1897.89/1400.30	% SZS status Ended for HL400100+5.p
1901.22/1400.59	% SZS status Started for HL400101+5.p
1901.22/1400.59	% SZS status Theorem for HL400101+5.p
1901.22/1400.59	% SZS status Ended for HL400101+5.p
1902.55/1400.74	% SZS status Started for HL400100+4.p
1902.55/1400.74	% SZS status Theorem for HL400100+4.p
1902.55/1400.74	% SZS status Ended for HL400100+4.p
1902.55/1400.81	% SZS status Started for HL400103+5.p
1902.55/1400.81	% SZS status Theorem for HL400103+5.p
1902.55/1400.81	% SZS status Ended for HL400103+5.p
1903.03/1400.84	% SZS status Started for HL400101+4.p
1903.03/1400.84	% SZS status Theorem for HL400101+4.p
1903.03/1400.84	% SZS status Ended for HL400101+4.p
1905.72/1401.16	% SZS status Started for HL400104+5.p
1905.72/1401.16	% SZS status Theorem for HL400104+5.p
1905.72/1401.16	% SZS status Ended for HL400104+5.p
1906.10/1401.19	% SZS status Started for HL400103+4.p
1906.10/1401.19	% SZS status Theorem for HL400103+4.p
1906.10/1401.19	% SZS status Ended for HL400103+4.p
1907.21/1401.45	% SZS status Started for HL400104+4.p
1907.21/1401.45	% SZS status Theorem for HL400104+4.p
1907.21/1401.45	% SZS status Ended for HL400104+4.p
1934.79/1404.88	% SZS status Started for HL400092+5.p
1934.79/1404.88	% SZS status GaveUp for HL400092+5.p
1934.79/1404.88	% SZS status Ended for HL400092+5.p
1954.61/1407.31	% SZS status Started for HL400093+5.p
1954.61/1407.31	% SZS status GaveUp for HL400093+5.p
1954.61/1407.31	% SZS status Ended for HL400093+5.p
1956.84/1407.70	% SZS status Started for HL400094+5.p
1956.84/1407.70	% SZS status GaveUp for HL400094+5.p
1956.84/1407.70	% SZS status Ended for HL400094+5.p
1959.12/1407.85	% SZS status Started for HL400097+4.p
1959.12/1407.85	% SZS status GaveUp for HL400097+4.p
1959.12/1407.85	% SZS status Ended for HL400097+4.p
1959.37/1407.93	% SZS status Started for HL400107+4.p
1959.37/1407.93	% SZS status Theorem for HL400107+4.p
1959.37/1407.93	% SZS status Ended for HL400107+4.p
1960.63/1408.08	% SZS status Started for HL400097+5.p
1960.63/1408.08	% SZS status GaveUp for HL400097+5.p
1960.63/1408.08	% SZS status Ended for HL400097+5.p
1960.84/1408.12	% SZS status Started for HL400107+5.p
1960.84/1408.12	% SZS status Theorem for HL400107+5.p
1960.84/1408.12	% SZS status Ended for HL400107+5.p
1960.84/1408.14	% SZS status Started for HL400109+4.p
1960.84/1408.14	% SZS status Theorem for HL400109+4.p
1960.84/1408.14	% SZS status Ended for HL400109+4.p
1961.01/1408.19	% SZS status Started for HL400110+4.p
1961.01/1408.19	% SZS status Theorem for HL400110+4.p
1961.01/1408.19	% SZS status Ended for HL400110+4.p
1961.01/1408.23	% SZS status Started for HL400108+5.p
1961.01/1408.23	% SZS status Theorem for HL400108+5.p
1961.01/1408.23	% SZS status Ended for HL400108+5.p
1961.32/1408.28	% SZS status Started for HL400109+5.p
1961.32/1408.28	% SZS status Theorem for HL400109+5.p
1961.32/1408.28	% SZS status Ended for HL400109+5.p
1961.32/1408.28	% SZS status Started for HL400111+4.p
1961.32/1408.28	% SZS status Theorem for HL400111+4.p
1961.32/1408.28	% SZS status Ended for HL400111+4.p
1962.70/1408.33	% SZS status Started for HL400110+5.p
1962.70/1408.33	% SZS status Theorem for HL400110+5.p
1962.70/1408.33	% SZS status Ended for HL400110+5.p
1962.70/1408.34	% SZS status Started for HL400112+4.p
1962.70/1408.34	% SZS status Theorem for HL400112+4.p
1962.70/1408.34	% SZS status Ended for HL400112+4.p
1963.13/1408.40	% SZS status Started for HL400113+4.p
1963.13/1408.40	% SZS status Theorem for HL400113+4.p
1963.13/1408.40	% SZS status Ended for HL400113+4.p
1963.45/1408.47	% SZS status Started for HL400111+5.p
1963.45/1408.47	% SZS status Theorem for HL400111+5.p
1963.45/1408.47	% SZS status Ended for HL400111+5.p
1963.45/1408.47	% SZS status Started for HL400112+5.p
1963.45/1408.47	% SZS status Theorem for HL400112+5.p
1963.45/1408.47	% SZS status Ended for HL400112+5.p
1963.85/1408.54	% SZS status Started for HL400108+4.p
1963.85/1408.54	% SZS status Theorem for HL400108+4.p
1963.85/1408.54	% SZS status Ended for HL400108+4.p
1963.85/1408.54	% SZS status Started for HL400113+5.p
1963.85/1408.54	% SZS status Theorem for HL400113+5.p
1963.85/1408.54	% SZS status Ended for HL400113+5.p
1966.58/1408.83	% SZS status Started for HL400114+5.p
1966.58/1408.83	% SZS status Theorem for HL400114+5.p
1966.58/1408.83	% SZS status Ended for HL400114+5.p
1968.50/1409.18	% SZS status Started for HL400114+4.p
1968.50/1409.18	% SZS status Theorem for HL400114+4.p
1968.50/1409.18	% SZS status Ended for HL400114+4.p
1969.33/1409.28	% SZS status Started for HL400105+5.p
1969.33/1409.28	% SZS status GaveUp for HL400105+5.p
1969.33/1409.28	% SZS status Ended for HL400105+5.p
1969.46/1409.31	% SZS status Started for HL400105+4.p
1969.46/1409.31	% SZS status GaveUp for HL400105+4.p
1969.46/1409.31	% SZS status Ended for HL400105+4.p
1971.72/1409.51	% SZS status Started for HL400117+5.p
1971.72/1409.51	% SZS status Theorem for HL400117+5.p
1971.72/1409.51	% SZS status Ended for HL400117+5.p
1972.13/1409.59	% SZS status Started for HL400106+4.p
1972.13/1409.59	% SZS status GaveUp for HL400106+4.p
1972.13/1409.59	% SZS status Ended for HL400106+4.p
1972.13/1409.65	% SZS status Started for HL400117+4.p
1972.13/1409.65	% SZS status Theorem for HL400117+4.p
1972.13/1409.65	% SZS status Ended for HL400117+4.p
1972.13/1409.66	% SZS status Started for HL400118+5.p
1972.13/1409.66	% SZS status Theorem for HL400118+5.p
1972.13/1409.66	% SZS status Ended for HL400118+5.p
1973.18/1409.93	% SZS status Started for HL400119+5.p
1973.18/1409.93	% SZS status Theorem for HL400119+5.p
1973.18/1409.93	% SZS status Ended for HL400119+5.p
1975.71/1410.01	% SZS status Started for HL400120+5.p
1975.71/1410.01	% SZS status Theorem for HL400120+5.p
1975.71/1410.01	% SZS status Ended for HL400120+5.p
1976.34/1410.10	% SZS status Started for HL400118+4.p
1976.34/1410.10	% SZS status Theorem for HL400118+4.p
1976.34/1410.10	% SZS status Ended for HL400118+4.p
1977.43/1410.32	% SZS status Started for HL400119+4.p
1977.43/1410.32	% SZS status Theorem for HL400119+4.p
1977.43/1410.32	% SZS status Ended for HL400119+4.p
1977.96/1410.45	% SZS status Started for HL400120+4.p
1977.96/1410.45	% SZS status Theorem for HL400120+4.p
1977.96/1410.45	% SZS status Ended for HL400120+4.p
1978.22/1410.52	% SZS status Started for HL400123+4.p
1978.22/1410.52	% SZS status Theorem for HL400123+4.p
1978.22/1410.52	% SZS status Ended for HL400123+4.p
1980.39/1410.68	% SZS status Started for HL400122+5.p
1980.39/1410.68	% SZS status Theorem for HL400122+5.p
1980.39/1410.68	% SZS status Ended for HL400122+5.p
1980.39/1410.73	% SZS status Started for HL400123+5.p
1980.39/1410.73	% SZS status Theorem for HL400123+5.p
1980.39/1410.73	% SZS status Ended for HL400123+5.p
1981.41/1410.94	% SZS status Started for HL400122+4.p
1981.41/1410.94	% SZS status Theorem for HL400122+4.p
1981.41/1410.94	% SZS status Ended for HL400122+4.p
1988.54/1411.74	% SZS status Started for HL400125+4.p
1988.54/1411.74	% SZS status Theorem for HL400125+4.p
1988.54/1411.74	% SZS status Ended for HL400125+4.p
1990.64/1412.18	% SZS status Started for HL400125+5.p
1990.64/1412.18	% SZS status Theorem for HL400125+5.p
1990.64/1412.18	% SZS status Ended for HL400125+5.p
1998.00/1412.94	% SZS status Started for HL400126+4.p
1998.00/1412.94	% SZS status Theorem for HL400126+4.p
1998.00/1412.94	% SZS status Ended for HL400126+4.p
1998.50/1413.00	% SZS status Started for HL400106+5.p
1998.50/1413.00	% SZS status GaveUp for HL400106+5.p
1998.50/1413.00	% SZS status Ended for HL400106+5.p
2009.44/1413.42	% SZS status Started for HL400126+5.p
2009.44/1413.42	% SZS status Theorem for HL400126+5.p
2009.44/1413.42	% SZS status Ended for HL400126+5.p
2011.96/1413.78	% SZS status Started for HL400127+5.p
2011.96/1413.78	% SZS status Theorem for HL400127+5.p
2011.96/1413.78	% SZS status Ended for HL400127+5.p
2013.00/1413.97	% SZS status Started for HL400127+4.p
2013.00/1413.97	% SZS status Theorem for HL400127+4.p
2013.00/1413.97	% SZS status Ended for HL400127+4.p
2035.16/1416.60	% SZS status Started for HL400116+5.p
2035.16/1416.60	% SZS status GaveUp for HL400116+5.p
2035.16/1416.60	% SZS status Ended for HL400116+5.p
2035.42/1416.65	% SZS status Started for HL400116+4.p
2035.42/1416.65	% SZS status GaveUp for HL400116+4.p
2035.42/1416.65	% SZS status Ended for HL400116+4.p
2046.86/1418.07	% SZS status Started for HL400121+4.p
2046.86/1418.07	% SZS status GaveUp for HL400121+4.p
2046.86/1418.07	% SZS status Ended for HL400121+4.p
2046.86/1418.11	% SZS status Started for HL400121+5.p
2046.86/1418.11	% SZS status GaveUp for HL400121+5.p
2046.86/1418.11	% SZS status Ended for HL400121+5.p
2052.12/1418.78	% SZS status Started for HL400124+4.p
2052.12/1418.78	% SZS status GaveUp for HL400124+4.p
2052.12/1418.78	% SZS status Ended for HL400124+4.p
2052.86/1418.88	% SZS status Started for HL400124+5.p
2052.86/1418.88	% SZS status GaveUp for HL400124+5.p
2052.86/1418.88	% SZS status Ended for HL400124+5.p
2068.19/1420.79	% SZS status Started for HL400131+4.p
2068.19/1420.79	% SZS status Theorem for HL400131+4.p
2068.19/1420.79	% SZS status Ended for HL400131+4.p
2077.84/1421.98	% SZS status Started for HL400128+4.p
2077.84/1421.98	% SZS status GaveUp for HL400128+4.p
2077.84/1421.98	% SZS status Ended for HL400128+4.p
2078.61/1422.13	% SZS status Started for HL400128+5.p
2078.61/1422.13	% SZS status GaveUp for HL400128+5.p
2078.61/1422.13	% SZS status Ended for HL400128+5.p
2092.92/1423.90	% SZS status Started for HL400135+4.p
2092.92/1423.90	% SZS status Theorem for HL400135+4.p
2092.92/1423.90	% SZS status Ended for HL400135+4.p
2098.39/1424.68	% SZS status Started for HL400129+4.p
2098.39/1424.68	% SZS status GaveUp for HL400129+4.p
2098.39/1424.68	% SZS status Ended for HL400129+4.p
2098.76/1424.73	% SZS status Started for HL400129+5.p
2098.76/1424.73	% SZS status GaveUp for HL400129+5.p
2098.76/1424.73	% SZS status Ended for HL400129+5.p
2110.94/1426.19	% SZS status Started for HL400130+5.p
2110.94/1426.19	% SZS status GaveUp for HL400130+5.p
2110.94/1426.19	% SZS status Ended for HL400130+5.p
2111.39/1426.25	% SZS status Started for HL400138+4.p
2111.39/1426.25	% SZS status Theorem for HL400138+4.p
2111.39/1426.25	% SZS status Ended for HL400138+4.p
2111.75/1426.28	% SZS status Started for HL400130+4.p
2111.75/1426.28	% SZS status GaveUp for HL400130+4.p
2111.75/1426.28	% SZS status Ended for HL400130+4.p
2114.25/1426.54	% SZS status Started for HL400136+4.p
2114.25/1426.54	% SZS status Theorem for HL400136+4.p
2114.25/1426.54	% SZS status Ended for HL400136+4.p
2116.18/1426.83	% SZS status Started for HL400138+5.p
2116.18/1426.83	% SZS status Theorem for HL400138+5.p
2116.18/1426.83	% SZS status Ended for HL400138+5.p
2116.56/1426.95	% SZS status Started for HL400131+5.p
2116.56/1426.95	% SZS status GaveUp for HL400131+5.p
2116.56/1426.95	% SZS status Ended for HL400131+5.p
2120.50/1427.39	% SZS status Started for HL400139+4.p
2120.50/1427.39	% SZS status Theorem for HL400139+4.p
2120.50/1427.39	% SZS status Ended for HL400139+4.p
2121.93/1427.61	% SZS status Started for HL400140+5.p
2121.93/1427.61	% SZS status Theorem for HL400140+5.p
2121.93/1427.61	% SZS status Ended for HL400140+5.p
2125.86/1428.06	% SZS status Started for HL400141+5.p
2125.86/1428.06	% SZS status Theorem for HL400141+5.p
2125.86/1428.06	% SZS status Ended for HL400141+5.p
2125.86/1428.07	% SZS status Started for HL400140+4.p
2125.86/1428.07	% SZS status Theorem for HL400140+4.p
2125.86/1428.07	% SZS status Ended for HL400140+4.p
2130.48/1428.65	% SZS status Started for HL400141+4.p
2130.48/1428.65	% SZS status Theorem for HL400141+4.p
2130.48/1428.65	% SZS status Ended for HL400141+4.p
2130.74/1428.71	% SZS status Started for HL400145+4.p
2130.74/1428.71	% SZS status Theorem for HL400145+4.p
2130.74/1428.71	% SZS status Ended for HL400145+4.p
2132.52/1428.98	% SZS status Started for HL400132+4.p
2132.52/1428.98	% SZS status GaveUp for HL400132+4.p
2132.52/1428.98	% SZS status Ended for HL400132+4.p
2132.90/1429.08	% SZS status Started for HL400146+4.p
2132.90/1429.08	% SZS status Theorem for HL400146+4.p
2132.90/1429.08	% SZS status Ended for HL400146+4.p
2135.52/1429.29	% SZS status Started for HL400145+5.p
2135.52/1429.29	% SZS status Theorem for HL400145+5.p
2135.52/1429.29	% SZS status Ended for HL400145+5.p
2140.06/1429.87	% SZS status Started for HL400146+5.p
2140.06/1429.87	% SZS status Theorem for HL400146+5.p
2140.06/1429.87	% SZS status Ended for HL400146+5.p
2141.39/1430.06	% SZS status Started for HL400132+5.p
2141.39/1430.06	% SZS status GaveUp for HL400132+5.p
2141.39/1430.06	% SZS status Ended for HL400132+5.p
2149.71/1431.15	% SZS status Started for HL400149+4.p
2149.71/1431.15	% SZS status Theorem for HL400149+4.p
2149.71/1431.15	% SZS status Ended for HL400149+4.p
2154.69/1431.75	% SZS status Started for HL400149+5.p
2154.69/1431.75	% SZS status Theorem for HL400149+5.p
2154.69/1431.75	% SZS status Ended for HL400149+5.p
2155.04/1431.83	% SZS status Started for HL400150+4.p
2155.04/1431.83	% SZS status Theorem for HL400150+4.p
2155.04/1431.83	% SZS status Ended for HL400150+4.p
2156.58/1432.06	% SZS status Started for HL400135+5.p
2156.58/1432.06	% SZS status GaveUp for HL400135+5.p
2156.58/1432.06	% SZS status Ended for HL400135+5.p
2159.57/1432.33	% SZS status Started for HL400150+5.p
2159.57/1432.33	% SZS status Theorem for HL400150+5.p
2159.57/1432.33	% SZS status Ended for HL400150+5.p
2162.42/1432.85	% SZS status Started for HL400151+5.p
2162.42/1432.85	% SZS status Theorem for HL400151+5.p
2162.42/1432.85	% SZS status Ended for HL400151+5.p
2162.42/1432.85	% SZS status Started for HL400136+5.p
2162.42/1432.85	% SZS status GaveUp for HL400136+5.p
2162.42/1432.85	% SZS status Ended for HL400136+5.p
2165.54/1433.15	% SZS status Started for HL400151+4.p
2165.54/1433.15	% SZS status Theorem for HL400151+4.p
2165.54/1433.15	% SZS status Ended for HL400151+4.p
2177.83/1434.61	% SZS status Started for HL400139+5.p
2177.83/1434.61	% SZS status GaveUp for HL400139+5.p
2177.83/1434.61	% SZS status Ended for HL400139+5.p
2189.60/1436.15	% SZS status Started for HL400142+5.p
2189.60/1436.15	% SZS status GaveUp for HL400142+5.p
2189.60/1436.15	% SZS status Ended for HL400142+5.p
2189.82/1436.19	% SZS status Started for HL400142+4.p
2189.82/1436.19	% SZS status GaveUp for HL400142+4.p
2189.82/1436.19	% SZS status Ended for HL400142+4.p
2194.45/1436.77	% SZS status Started for HL400155+5.p
2194.45/1436.77	% SZS status Theorem for HL400155+5.p
2194.45/1436.77	% SZS status Ended for HL400155+5.p
2195.24/1436.83	% SZS status Started for HL400156+4.p
2195.24/1436.83	% SZS status Theorem for HL400156+4.p
2195.24/1436.83	% SZS status Ended for HL400156+4.p
2195.90/1436.91	% SZS status Started for HL400156+5.p
2195.90/1436.91	% SZS status Theorem for HL400156+5.p
2195.90/1436.91	% SZS status Ended for HL400156+5.p
2200.03/1437.45	% SZS status Started for HL400147+4.p
2200.03/1437.45	% SZS status GaveUp for HL400147+4.p
2200.03/1437.45	% SZS status Ended for HL400147+4.p
2205.13/1438.06	% SZS status Started for HL400157+5.p
2205.13/1438.06	% SZS status Theorem for HL400157+5.p
2205.13/1438.06	% SZS status Ended for HL400157+5.p
2205.13/1438.11	% SZS status Started for HL400147+5.p
2205.13/1438.11	% SZS status GaveUp for HL400147+5.p
2205.13/1438.11	% SZS status Ended for HL400147+5.p
2210.10/1438.72	% SZS status Started for HL400155+4.p
2210.10/1438.72	% SZS status Theorem for HL400155+4.p
2210.10/1438.72	% SZS status Ended for HL400155+4.p
2210.10/1438.74	% SZS status Started for HL400158+5.p
2210.10/1438.74	% SZS status Theorem for HL400158+5.p
2210.10/1438.74	% SZS status Ended for HL400158+5.p
2210.81/1438.79	% SZS status Started for HL400159+4.p
2210.81/1438.79	% SZS status Theorem for HL400159+4.p
2210.81/1438.79	% SZS status Ended for HL400159+4.p
2211.09/1438.82	% SZS status Started for HL400159+5.p
2211.09/1438.82	% SZS status Theorem for HL400159+5.p
2211.09/1438.82	% SZS status Ended for HL400159+5.p
2211.44/1438.86	% SZS status Started for HL400160+4.p
2211.44/1438.86	% SZS status Theorem for HL400160+4.p
2211.44/1438.86	% SZS status Ended for HL400160+4.p
2211.80/1438.91	% SZS status Started for HL400160+5.p
2211.80/1438.91	% SZS status Theorem for HL400160+5.p
2211.80/1438.91	% SZS status Ended for HL400160+5.p
2211.80/1438.93	% SZS status Started for HL400161+4.p
2211.80/1438.93	% SZS status Theorem for HL400161+4.p
2211.80/1438.93	% SZS status Ended for HL400161+4.p
2212.19/1438.99	% SZS status Started for HL400161+5.p
2212.19/1438.99	% SZS status Theorem for HL400161+5.p
2212.19/1438.99	% SZS status Ended for HL400161+5.p
2212.19/1439.01	% SZS status Started for HL400162+4.p
2212.19/1439.01	% SZS status Theorem for HL400162+4.p
2212.19/1439.01	% SZS status Ended for HL400162+4.p
2213.33/1439.07	% SZS status Started for HL400162+5.p
2213.33/1439.07	% SZS status Theorem for HL400162+5.p
2213.33/1439.07	% SZS status Ended for HL400162+5.p
2213.33/1439.08	% SZS status Started for HL400163+4.p
2213.33/1439.08	% SZS status Theorem for HL400163+4.p
2213.33/1439.08	% SZS status Ended for HL400163+4.p
2213.70/1439.15	% SZS status Started for HL400165+4.p
2213.70/1439.15	% SZS status Theorem for HL400165+4.p
2213.70/1439.15	% SZS status Ended for HL400165+4.p
2213.70/1439.15	% SZS status Started for HL400163+5.p
2213.70/1439.15	% SZS status Theorem for HL400163+5.p
2213.70/1439.15	% SZS status Ended for HL400163+5.p
2214.02/1439.23	% SZS status Started for HL400165+5.p
2214.02/1439.23	% SZS status Theorem for HL400165+5.p
2214.02/1439.23	% SZS status Ended for HL400165+5.p
2214.83/1439.31	% SZS status Started for HL400167+5.p
2214.83/1439.31	% SZS status Theorem for HL400167+5.p
2214.83/1439.31	% SZS status Ended for HL400167+5.p
2215.19/1439.38	% SZS status Started for HL400168+4.p
2215.19/1439.38	% SZS status Theorem for HL400168+4.p
2215.19/1439.38	% SZS status Ended for HL400168+4.p
2215.19/1439.40	% SZS status Started for HL400157+4.p
2215.19/1439.40	% SZS status Theorem for HL400157+4.p
2215.19/1439.40	% SZS status Ended for HL400157+4.p
2215.68/1439.47	% SZS status Started for HL400168+5.p
2215.68/1439.47	% SZS status Theorem for HL400168+5.p
2215.68/1439.47	% SZS status Ended for HL400168+5.p
2215.68/1439.47	% SZS status Started for HL400169+4.p
2215.68/1439.47	% SZS status Theorem for HL400169+4.p
2215.68/1439.47	% SZS status Ended for HL400169+4.p
2216.17/1439.54	% SZS status Started for HL400170+4.p
2216.17/1439.54	% SZS status Theorem for HL400170+4.p
2216.17/1439.54	% SZS status Ended for HL400170+4.p
2216.17/1439.55	% SZS status Started for HL400169+5.p
2216.17/1439.55	% SZS status Theorem for HL400169+5.p
2216.17/1439.55	% SZS status Ended for HL400169+5.p
2216.37/1439.62	% SZS status Started for HL400170+5.p
2216.37/1439.62	% SZS status Theorem for HL400170+5.p
2216.37/1439.62	% SZS status Ended for HL400170+5.p
2222.32/1440.23	% SZS status Started for HL400158+4.p
2222.32/1440.23	% SZS status Theorem for HL400158+4.p
2222.32/1440.23	% SZS status Ended for HL400158+4.p
2222.32/1440.23	% SZS status Started for HL400167+4.p
2222.32/1440.23	% SZS status Theorem for HL400167+4.p
2222.32/1440.23	% SZS status Ended for HL400167+4.p
2222.32/1440.24	% SZS status Started for HL400171+5.p
2222.32/1440.24	% SZS status Theorem for HL400171+5.p
2222.32/1440.24	% SZS status Ended for HL400171+5.p
2222.98/1440.31	% SZS status Started for HL400172+5.p
2222.98/1440.31	% SZS status Theorem for HL400172+5.p
2222.98/1440.31	% SZS status Ended for HL400172+5.p
2223.27/1440.32	% SZS status Started for HL400174+4.p
2223.27/1440.32	% SZS status Theorem for HL400174+4.p
2223.27/1440.32	% SZS status Ended for HL400174+4.p
2223.44/1440.39	% SZS status Started for HL400176+4.p
2223.44/1440.39	% SZS status Theorem for HL400176+4.p
2223.44/1440.39	% SZS status Ended for HL400176+4.p
2223.44/1440.40	% SZS status Started for HL400174+5.p
2223.44/1440.40	% SZS status Theorem for HL400174+5.p
2223.44/1440.40	% SZS status Ended for HL400174+5.p
2223.90/1440.47	% SZS status Started for HL400178+4.p
2223.90/1440.47	% SZS status Theorem for HL400178+4.p
2223.90/1440.47	% SZS status Ended for HL400178+4.p
2223.90/1440.47	% SZS status Started for HL400176+5.p
2223.90/1440.47	% SZS status Theorem for HL400176+5.p
2223.90/1440.47	% SZS status Ended for HL400176+5.p
2224.29/1440.55	% SZS status Started for HL400178+5.p
2224.29/1440.55	% SZS status Theorem for HL400178+5.p
2224.29/1440.55	% SZS status Ended for HL400178+5.p
2224.89/1440.63	% SZS status Started for HL400171+4.p
2224.89/1440.63	% SZS status Theorem for HL400171+4.p
2224.89/1440.63	% SZS status Ended for HL400171+4.p
2225.04/1440.70	% SZS status Started for HL400181+4.p
2225.04/1440.70	% SZS status Theorem for HL400181+4.p
2225.04/1440.70	% SZS status Ended for HL400181+4.p
2227.10/1440.79	% SZS status Started for HL400181+5.p
2227.10/1440.79	% SZS status Theorem for HL400181+5.p
2227.10/1440.79	% SZS status Ended for HL400181+5.p
2227.66/1440.87	% SZS status Started for HL400183+4.p
2227.66/1440.87	% SZS status Theorem for HL400183+4.p
2227.66/1440.87	% SZS status Ended for HL400183+4.p
2228.20/1440.96	% SZS status Started for HL400183+5.p
2228.20/1440.96	% SZS status Theorem for HL400183+5.p
2228.20/1440.96	% SZS status Ended for HL400183+5.p
2228.20/1440.96	% SZS status Started for HL400152+5.p
2228.20/1440.96	% SZS status GaveUp for HL400152+5.p
2228.20/1440.96	% SZS status Ended for HL400152+5.p
2228.88/1441.03	% SZS status Started for HL400184+4.p
2228.88/1441.03	% SZS status Theorem for HL400184+4.p
2228.88/1441.03	% SZS status Ended for HL400184+4.p
2228.88/1441.04	% SZS status Started for HL400152+4.p
2228.88/1441.04	% SZS status GaveUp for HL400152+4.p
2228.88/1441.04	% SZS status Ended for HL400152+4.p
2228.88/1441.05	% SZS status Started for HL400184+5.p
2228.88/1441.05	% SZS status Theorem for HL400184+5.p
2228.88/1441.05	% SZS status Ended for HL400184+5.p
2229.45/1441.10	% SZS status Started for HL400185+4.p
2229.45/1441.10	% SZS status Theorem for HL400185+4.p
2229.45/1441.10	% SZS status Ended for HL400185+4.p
2229.45/1441.12	% SZS status Started for HL400186+4.p
2229.45/1441.12	% SZS status Theorem for HL400186+4.p
2229.45/1441.12	% SZS status Ended for HL400186+4.p
2229.45/1441.14	% SZS status Started for HL400185+5.p
2229.45/1441.14	% SZS status Theorem for HL400185+5.p
2229.45/1441.14	% SZS status Ended for HL400185+5.p
2230.12/1441.18	% SZS status Started for HL400179+5.p
2230.12/1441.18	% SZS status Theorem for HL400179+5.p
2230.12/1441.18	% SZS status Ended for HL400179+5.p
2230.12/1441.19	% SZS status Started for HL400186+5.p
2230.12/1441.19	% SZS status Theorem for HL400186+5.p
2230.12/1441.19	% SZS status Ended for HL400186+5.p
2230.68/1441.26	% SZS status Started for HL400189+4.p
2230.68/1441.26	% SZS status Theorem for HL400189+4.p
2230.68/1441.26	% SZS status Ended for HL400189+4.p
2230.68/1441.28	% SZS status Started for HL400189+5.p
2230.68/1441.28	% SZS status Theorem for HL400189+5.p
2230.68/1441.28	% SZS status Ended for HL400189+5.p
2230.68/1441.30	% SZS status Started for HL400172+4.p
2230.68/1441.30	% SZS status Theorem for HL400172+4.p
2230.68/1441.30	% SZS status Ended for HL400172+4.p
2230.68/1441.32	% SZS status Started for HL400153+4.p
2230.68/1441.32	% SZS status GaveUp for HL400153+4.p
2230.68/1441.32	% SZS status Ended for HL400153+4.p
2231.42/1441.34	% SZS status Started for HL400190+4.p
2231.42/1441.34	% SZS status Theorem for HL400190+4.p
2231.42/1441.34	% SZS status Ended for HL400190+4.p
2231.42/1441.37	% SZS status Started for HL400190+5.p
2231.42/1441.37	% SZS status Theorem for HL400190+5.p
2231.42/1441.37	% SZS status Ended for HL400190+5.p
2231.42/1441.38	% SZS status Started for HL400191+4.p
2231.42/1441.38	% SZS status Theorem for HL400191+4.p
2231.42/1441.38	% SZS status Ended for HL400191+4.p
2231.90/1441.41	% SZS status Started for HL400191+5.p
2231.90/1441.41	% SZS status Theorem for HL400191+5.p
2231.90/1441.41	% SZS status Ended for HL400191+5.p
2232.60/1441.57	% SZS status Started for HL400179+4.p
2232.60/1441.57	% SZS status Theorem for HL400179+4.p
2232.60/1441.57	% SZS status Ended for HL400179+4.p
2233.24/1441.82	% SZS status Started for HL400188+5.p
2233.24/1441.82	% SZS status Theorem for HL400188+5.p
2233.24/1441.82	% SZS status Ended for HL400188+5.p
2236.76/1442.01	% SZS status Started for HL400192+5.p
2236.76/1442.01	% SZS status Theorem for HL400192+5.p
2236.76/1442.01	% SZS status Ended for HL400192+5.p
2237.18/1442.08	% SZS status Started for HL400194+5.p
2237.18/1442.08	% SZS status Theorem for HL400194+5.p
2237.18/1442.08	% SZS status Ended for HL400194+5.p
2237.18/1442.09	% SZS status Started for HL400196+4.p
2237.18/1442.09	% SZS status Theorem for HL400196+4.p
2237.18/1442.09	% SZS status Ended for HL400196+4.p
2237.89/1442.18	% SZS status Started for HL400197+4.p
2237.89/1442.18	% SZS status Theorem for HL400197+4.p
2237.89/1442.18	% SZS status Ended for HL400197+4.p
2238.43/1442.27	% SZS status Started for HL400197+5.p
2238.43/1442.27	% SZS status Theorem for HL400197+5.p
2238.43/1442.27	% SZS status Ended for HL400197+5.p
2238.82/1442.35	% SZS status Started for HL400198+4.p
2238.82/1442.35	% SZS status Theorem for HL400198+4.p
2238.82/1442.35	% SZS status Ended for HL400198+4.p
2239.17/1442.44	% SZS status Started for HL400198+5.p
2239.17/1442.44	% SZS status Theorem for HL400198+5.p
2239.17/1442.44	% SZS status Ended for HL400198+5.p
2240.40/1442.49	% SZS status Started for HL400195+5.p
2240.40/1442.49	% SZS status Theorem for HL400195+5.p
2240.40/1442.49	% SZS status Ended for HL400195+5.p
2241.01/1442.58	% SZS status Started for HL400201+5.p
2241.01/1442.58	% SZS status Theorem for HL400201+5.p
2241.01/1442.58	% SZS status Ended for HL400201+5.p
2241.85/1442.74	% SZS status Started for HL400153+5.p
2241.85/1442.74	% SZS status GaveUp for HL400153+5.p
2241.85/1442.74	% SZS status Ended for HL400153+5.p
2242.38/1442.83	% SZS status Started for HL400202+5.p
2242.38/1442.83	% SZS status Theorem for HL400202+5.p
2242.38/1442.83	% SZS status Ended for HL400202+5.p
2242.38/1442.84	% SZS status Started for HL400196+5.p
2242.38/1442.84	% SZS status Theorem for HL400196+5.p
2242.38/1442.84	% SZS status Ended for HL400196+5.p
2242.70/1442.91	% SZS status Started for HL400203+4.p
2242.70/1442.91	% SZS status Theorem for HL400203+4.p
2242.70/1442.91	% SZS status Ended for HL400203+4.p
2242.70/1442.94	% SZS status Started for HL400203+5.p
2242.70/1442.94	% SZS status Theorem for HL400203+5.p
2242.70/1442.94	% SZS status Ended for HL400203+5.p
2243.27/1442.99	% SZS status Started for HL400204+4.p
2243.27/1442.99	% SZS status Theorem for HL400204+4.p
2243.27/1442.99	% SZS status Ended for HL400204+4.p
2243.27/1443.02	% SZS status Started for HL400204+5.p
2243.27/1443.02	% SZS status Theorem for HL400204+5.p
2243.27/1443.02	% SZS status Ended for HL400204+5.p
2245.22/1443.08	% SZS status Started for HL400205+4.p
2245.22/1443.08	% SZS status Theorem for HL400205+4.p
2245.22/1443.08	% SZS status Ended for HL400205+4.p
2245.22/1443.11	% SZS status Started for HL400205+5.p
2245.22/1443.11	% SZS status Theorem for HL400205+5.p
2245.22/1443.11	% SZS status Ended for HL400205+5.p
2245.83/1443.17	% SZS status Started for HL400206+4.p
2245.83/1443.17	% SZS status Theorem for HL400206+4.p
2245.83/1443.17	% SZS status Ended for HL400206+4.p
2245.83/1443.20	% SZS status Started for HL400206+5.p
2245.83/1443.20	% SZS status Theorem for HL400206+5.p
2245.83/1443.20	% SZS status Ended for HL400206+5.p
2246.45/1443.25	% SZS status Started for HL400207+4.p
2246.45/1443.25	% SZS status Theorem for HL400207+4.p
2246.45/1443.25	% SZS status Ended for HL400207+4.p
2246.76/1443.29	% SZS status Started for HL400207+5.p
2246.76/1443.29	% SZS status Theorem for HL400207+5.p
2246.76/1443.29	% SZS status Ended for HL400207+5.p
2247.69/1443.50	% SZS status Started for HL400192+4.p
2247.69/1443.50	% SZS status Theorem for HL400192+4.p
2247.69/1443.50	% SZS status Ended for HL400192+4.p
2248.00/1443.53	% SZS status Started for HL400201+4.p
2248.00/1443.53	% SZS status Theorem for HL400201+4.p
2248.00/1443.53	% SZS status Ended for HL400201+4.p
2248.00/1443.54	% SZS status Started for HL400194+4.p
2248.00/1443.54	% SZS status Theorem for HL400194+4.p
2248.00/1443.54	% SZS status Ended for HL400194+4.p
2249.35/1443.63	% SZS status Started for HL400211+4.p
2249.35/1443.63	% SZS status Theorem for HL400211+4.p
2249.35/1443.63	% SZS status Ended for HL400211+4.p
2249.99/1443.67	% SZS status Started for HL400202+4.p
2249.99/1443.67	% SZS status Theorem for HL400202+4.p
2249.99/1443.67	% SZS status Ended for HL400202+4.p
2249.99/1443.71	% SZS status Started for HL400195+4.p
2249.99/1443.71	% SZS status Theorem for HL400195+4.p
2249.99/1443.71	% SZS status Ended for HL400195+4.p
2250.35/1443.72	% SZS status Started for HL400211+5.p
2250.35/1443.72	% SZS status Theorem for HL400211+5.p
2250.35/1443.72	% SZS status Ended for HL400211+5.p
2250.55/1443.81	% SZS status Started for HL400214+4.p
2250.55/1443.81	% SZS status Theorem for HL400214+4.p
2250.55/1443.81	% SZS status Ended for HL400214+4.p
2251.32/1443.91	% SZS status Started for HL400214+5.p
2251.32/1443.91	% SZS status Theorem for HL400214+5.p
2251.32/1443.91	% SZS status Ended for HL400214+5.p
2251.32/1443.95	% SZS status Started for HL400208+5.p
2251.32/1443.95	% SZS status Theorem for HL400208+5.p
2251.32/1443.95	% SZS status Ended for HL400208+5.p
2251.92/1443.99	% SZS status Started for HL400215+4.p
2251.92/1443.99	% SZS status Theorem for HL400215+4.p
2251.92/1443.99	% SZS status Ended for HL400215+4.p
2252.28/1444.05	% SZS status Started for HL400215+5.p
2252.28/1444.05	% SZS status Theorem for HL400215+5.p
2252.28/1444.05	% SZS status Ended for HL400215+5.p
2252.28/1444.08	% SZS status Started for HL400216+4.p
2252.28/1444.08	% SZS status Theorem for HL400216+4.p
2252.28/1444.08	% SZS status Ended for HL400216+4.p
2253.65/1444.15	% SZS status Started for HL400216+5.p
2253.65/1444.15	% SZS status Theorem for HL400216+5.p
2253.65/1444.15	% SZS status Ended for HL400216+5.p
2253.65/1444.18	% SZS status Started for HL400217+4.p
2253.65/1444.18	% SZS status Theorem for HL400217+4.p
2253.65/1444.18	% SZS status Ended for HL400217+4.p
2254.16/1444.20	% SZS status Started for HL400210+5.p
2254.16/1444.20	% SZS status Theorem for HL400210+5.p
2254.16/1444.20	% SZS status Ended for HL400210+5.p
2254.16/1444.25	% SZS status Started for HL400217+5.p
2254.16/1444.25	% SZS status Theorem for HL400217+5.p
2254.16/1444.25	% SZS status Ended for HL400217+5.p
2254.16/1444.26	% SZS status Started for HL400218+4.p
2254.16/1444.26	% SZS status Theorem for HL400218+4.p
2254.16/1444.26	% SZS status Ended for HL400218+4.p
2254.74/1444.30	% SZS status Started for HL400218+5.p
2254.74/1444.30	% SZS status Theorem for HL400218+5.p
2254.74/1444.30	% SZS status Ended for HL400218+5.p
2255.02/1444.33	% SZS status Started for HL400219+4.p
2255.02/1444.33	% SZS status Theorem for HL400219+4.p
2255.02/1444.33	% SZS status Ended for HL400219+4.p
2255.02/1444.36	% SZS status Started for HL400219+5.p
2255.02/1444.36	% SZS status Theorem for HL400219+5.p
2255.02/1444.36	% SZS status Ended for HL400219+5.p
2255.45/1444.48	% SZS status Started for HL400213+5.p
2255.45/1444.48	% SZS status Theorem for HL400213+5.p
2255.45/1444.48	% SZS status Ended for HL400213+5.p
2255.92/1444.61	% SZS status Started for HL400210+4.p
2255.92/1444.61	% SZS status Theorem for HL400210+4.p
2255.92/1444.61	% SZS status Ended for HL400210+4.p
2260.14/1445.04	% SZS status Started for HL400223+5.p
2260.14/1445.04	% SZS status Theorem for HL400223+5.p
2260.14/1445.04	% SZS status Ended for HL400223+5.p
2260.52/1445.14	% SZS status Started for HL400225+5.p
2260.52/1445.14	% SZS status Theorem for HL400225+5.p
2260.52/1445.14	% SZS status Ended for HL400225+5.p
2260.96/1445.19	% SZS status Started for HL400224+5.p
2260.96/1445.19	% SZS status Theorem for HL400224+5.p
2260.96/1445.19	% SZS status Ended for HL400224+5.p
2260.96/1445.25	% SZS status Started for HL400227+4.p
2260.96/1445.25	% SZS status Theorem for HL400227+4.p
2260.96/1445.25	% SZS status Ended for HL400227+4.p
2263.64/1445.40	% SZS status Started for HL400223+4.p
2263.64/1445.40	% SZS status Theorem for HL400223+4.p
2263.64/1445.40	% SZS status Ended for HL400223+4.p
2264.03/1445.47	% SZS status Started for HL400224+4.p
2264.03/1445.47	% SZS status Theorem for HL400224+4.p
2264.03/1445.47	% SZS status Ended for HL400224+4.p
2265.28/1445.74	% SZS status Started for HL400225+4.p
2265.28/1445.74	% SZS status Theorem for HL400225+4.p
2265.28/1445.74	% SZS status Ended for HL400225+4.p
2268.14/1446.02	% SZS status Started for HL400227+5.p
2268.14/1446.02	% SZS status Theorem for HL400227+5.p
2268.14/1446.02	% SZS status Ended for HL400227+5.p
2269.19/1446.12	% SZS status Started for HL400231+4.p
2269.19/1446.12	% SZS status Theorem for HL400231+4.p
2269.19/1446.12	% SZS status Ended for HL400231+4.p
2272.80/1446.62	% SZS status Started for HL400229+4.p
2272.80/1446.62	% SZS status Theorem for HL400229+4.p
2272.80/1446.62	% SZS status Ended for HL400229+4.p
2281.71/1447.67	% SZS status Started for HL400188+4.p
2281.71/1447.67	% SZS status Theorem for HL400188+4.p
2281.71/1447.67	% SZS status Ended for HL400188+4.p
2282.13/1447.77	% SZS status Started for HL400231+5.p
2282.13/1447.77	% SZS status Theorem for HL400231+5.p
2282.13/1447.77	% SZS status Ended for HL400231+5.p
2297.38/1449.81	% SZS status Started for HL400208+4.p
2297.38/1449.81	% SZS status Theorem for HL400208+4.p
2297.38/1449.81	% SZS status Ended for HL400208+4.p
2304.11/1450.51	% SZS status Started for HL400213+4.p
2304.11/1450.51	% SZS status Theorem for HL400213+4.p
2304.11/1450.51	% SZS status Ended for HL400213+4.p
2305.13/1450.63	% SZS status Started for HL400235+4.p
2305.13/1450.63	% SZS status Theorem for HL400235+4.p
2305.13/1450.63	% SZS status Ended for HL400235+4.p
2319.76/1452.50	% SZS status Started for HL400235+5.p
2319.76/1452.50	% SZS status Theorem for HL400235+5.p
2319.76/1452.50	% SZS status Ended for HL400235+5.p
2323.61/1453.00	% SZS status Started for HL400236+4.p
2323.61/1453.00	% SZS status Theorem for HL400236+4.p
2323.61/1453.00	% SZS status Ended for HL400236+4.p
2327.53/1453.43	% SZS status Started for HL400228+4.p
2327.53/1453.43	% SZS status GaveUp for HL400228+4.p
2327.53/1453.43	% SZS status Ended for HL400228+4.p
2328.34/1453.55	% SZS status Started for HL400237+4.p
2328.34/1453.55	% SZS status Theorem for HL400237+4.p
2328.34/1453.55	% SZS status Ended for HL400237+4.p
2329.44/1453.66	% SZS status Started for HL400228+5.p
2329.44/1453.66	% SZS status GaveUp for HL400228+5.p
2329.44/1453.66	% SZS status Ended for HL400228+5.p
2331.27/1453.95	% SZS status Started for HL400229+5.p
2331.27/1453.95	% SZS status GaveUp for HL400229+5.p
2331.27/1453.95	% SZS status Ended for HL400229+5.p
2336.08/1454.51	% SZS status Started for HL400237+5.p
2336.08/1454.51	% SZS status Theorem for HL400237+5.p
2336.08/1454.51	% SZS status Ended for HL400237+5.p
2338.18/1454.80	% SZS status Started for HL400233+4.p
2338.18/1454.80	% SZS status GaveUp for HL400233+4.p
2338.18/1454.80	% SZS status Ended for HL400233+4.p
2346.17/1455.76	% SZS status Started for HL400233+5.p
2346.17/1455.76	% SZS status GaveUp for HL400233+5.p
2346.17/1455.76	% SZS status Ended for HL400233+5.p
2347.04/1455.89	% SZS status Started for HL400234+4.p
2347.04/1455.89	% SZS status GaveUp for HL400234+4.p
2347.04/1455.89	% SZS status Ended for HL400234+4.p
2363.08/1457.90	% SZS status Started for HL400234+5.p
2363.08/1457.90	% SZS status GaveUp for HL400234+5.p
2363.08/1457.90	% SZS status Ended for HL400234+5.p
2387.82/1461.08	% SZS status Started for HL400236+5.p
2387.82/1461.08	% SZS status GaveUp for HL400236+5.p
2387.82/1461.08	% SZS status Ended for HL400236+5.p
2395.06/1461.93	% SZS status Started for HL400238+4.p
2395.06/1461.93	% SZS status GaveUp for HL400238+4.p
2395.06/1461.93	% SZS status Ended for HL400238+4.p
2395.89/1462.08	% SZS status Started for HL400238+5.p
2395.89/1462.08	% SZS status GaveUp for HL400238+5.p
2395.89/1462.08	% SZS status Ended for HL400238+5.p
2400.28/1462.64	% SZS status Started for HL400240+4.p
2400.28/1462.64	% SZS status GaveUp for HL400240+4.p
2400.28/1462.64	% SZS status Ended for HL400240+4.p
2403.52/1463.00	% SZS status Started for HL400240+5.p
2403.52/1463.00	% SZS status GaveUp for HL400240+5.p
2403.52/1463.00	% SZS status Ended for HL400240+5.p
2410.89/1463.93	% SZS status Started for HL400241+4.p
2410.89/1463.93	% SZS status GaveUp for HL400241+4.p
2410.89/1463.93	% SZS status Ended for HL400241+4.p
2411.18/1464.01	% SZS status Started for HL400241+5.p
2411.18/1464.01	% SZS status GaveUp for HL400241+5.p
2411.18/1464.01	% SZS status Ended for HL400241+5.p
2411.65/1464.04	% SZS status Started for HL400246+4.p
2411.65/1464.04	% SZS status Theorem for HL400246+4.p
2411.65/1464.04	% SZS status Ended for HL400246+4.p
2412.50/1464.14	% SZS status Started for HL400246+5.p
2412.50/1464.14	% SZS status Theorem for HL400246+5.p
2412.50/1464.14	% SZS status Ended for HL400246+5.p
2413.04/1464.16	% SZS status Started for HL400247+4.p
2413.04/1464.16	% SZS status Theorem for HL400247+4.p
2413.04/1464.16	% SZS status Ended for HL400247+4.p
2420.85/1465.14	% SZS status Started for HL400247+5.p
2420.85/1465.14	% SZS status Theorem for HL400247+5.p
2420.85/1465.14	% SZS status Ended for HL400247+5.p
2427.37/1466.03	% SZS status Started for HL400242+4.p
2427.37/1466.03	% SZS status GaveUp for HL400242+4.p
2427.37/1466.03	% SZS status Ended for HL400242+4.p
2453.17/1469.22	% SZS status Started for HL400242+5.p
2453.17/1469.22	% SZS status GaveUp for HL400242+5.p
2453.17/1469.22	% SZS status Ended for HL400242+5.p
2453.49/1469.30	% SZS status Started for HL400249+4.p
2453.49/1469.30	% SZS status Theorem for HL400249+4.p
2453.49/1469.30	% SZS status Ended for HL400249+4.p
2459.74/1470.06	% SZS status Started for HL400244+4.p
2459.74/1470.06	% SZS status GaveUp for HL400244+4.p
2459.74/1470.06	% SZS status Ended for HL400244+4.p
2460.33/1470.17	% SZS status Started for HL400244+5.p
2460.33/1470.17	% SZS status GaveUp for HL400244+5.p
2460.33/1470.17	% SZS status Ended for HL400244+5.p
2460.33/1470.24	% SZS status Started for HL400249+5.p
2460.33/1470.24	% SZS status Theorem for HL400249+5.p
2460.33/1470.24	% SZS status Ended for HL400249+5.p
2466.66/1470.90	% SZS status Started for HL400245+4.p
2466.66/1470.90	% SZS status GaveUp for HL400245+4.p
2466.66/1470.90	% SZS status Ended for HL400245+4.p
2467.76/1471.07	% SZS status Started for HL400250+5.p
2467.76/1471.07	% SZS status Theorem for HL400250+5.p
2467.76/1471.07	% SZS status Ended for HL400250+5.p
2467.76/1471.08	% SZS status Started for HL400245+5.p
2467.76/1471.08	% SZS status GaveUp for HL400245+5.p
2467.76/1471.08	% SZS status Ended for HL400245+5.p
2472.48/1471.72	% SZS status Started for HL400252+4.p
2472.48/1471.72	% SZS status Theorem for HL400252+4.p
2472.48/1471.72	% SZS status Ended for HL400252+4.p
2473.77/1471.84	% SZS status Started for HL400253+4.p
2473.77/1471.84	% SZS status Theorem for HL400253+4.p
2473.77/1471.84	% SZS status Ended for HL400253+4.p
2477.46/1472.32	% SZS status Started for HL400248+4.p
2477.46/1472.32	% SZS status GaveUp for HL400248+4.p
2477.46/1472.32	% SZS status Ended for HL400248+4.p
2477.88/1472.43	% SZS status Started for HL400250+4.p
2477.88/1472.43	% SZS status Theorem for HL400250+4.p
2477.88/1472.43	% SZS status Ended for HL400250+4.p
2485.35/1473.24	% SZS status Started for HL400248+5.p
2485.35/1473.24	% SZS status GaveUp for HL400248+5.p
2485.35/1473.24	% SZS status Ended for HL400248+5.p
2485.35/1473.27	% SZS status Started for HL400256+4.p
2485.35/1473.27	% SZS status Theorem for HL400256+4.p
2485.35/1473.27	% SZS status Ended for HL400256+4.p
2485.35/1473.34	% SZS status Started for HL400251+4.p
2485.35/1473.34	% SZS status Theorem for HL400251+4.p
2485.35/1473.34	% SZS status Ended for HL400251+4.p
2494.50/1474.44	% SZS status Started for HL400257+4.p
2494.50/1474.44	% SZS status Theorem for HL400257+4.p
2494.50/1474.44	% SZS status Ended for HL400257+4.p
2525.50/1478.34	% SZS status Started for HL400251+5.p
2525.50/1478.34	% SZS status GaveUp for HL400251+5.p
2525.50/1478.34	% SZS status Ended for HL400251+5.p
2531.89/1479.16	% SZS status Started for HL400252+5.p
2531.89/1479.16	% SZS status GaveUp for HL400252+5.p
2531.89/1479.16	% SZS status Ended for HL400252+5.p
2536.96/1479.86	% SZS status Started for HL400253+5.p
2536.96/1479.86	% SZS status GaveUp for HL400253+5.p
2536.96/1479.86	% SZS status Ended for HL400253+5.p
2539.50/1480.08	% SZS status Started for HL400254+4.p
2539.50/1480.08	% SZS status GaveUp for HL400254+4.p
2539.50/1480.08	% SZS status Ended for HL400254+4.p
2541.55/1480.44	% SZS status Started for HL400254+5.p
2541.55/1480.44	% SZS status GaveUp for HL400254+5.p
2541.55/1480.44	% SZS status Ended for HL400254+5.p
2549.38/1481.37	% SZS status Started for HL400256+5.p
2549.38/1481.37	% SZS status GaveUp for HL400256+5.p
2549.38/1481.37	% SZS status Ended for HL400256+5.p
2550.32/1481.52	% SZS status Started for HL400257+5.p
2550.32/1481.52	% SZS status GaveUp for HL400257+5.p
2550.32/1481.52	% SZS status Ended for HL400257+5.p
2558.58/1482.61	% SZS status Started for HL400258+4.p
2558.58/1482.61	% SZS status GaveUp for HL400258+4.p
2558.58/1482.61	% SZS status Ended for HL400258+4.p
2589.70/1486.43	% SZS status Started for HL400258+5.p
2589.70/1486.43	% SZS status GaveUp for HL400258+5.p
2589.70/1486.43	% SZS status Ended for HL400258+5.p
2598.42/1487.48	% SZS status Started for HL400259+4.p
2598.42/1487.48	% SZS status GaveUp for HL400259+4.p
2598.42/1487.48	% SZS status Ended for HL400259+4.p
2602.97/1488.02	% SZS status Started for HL400259+5.p
2602.97/1488.02	% SZS status GaveUp for HL400259+5.p
2602.97/1488.02	% SZS status Ended for HL400259+5.p
2604.83/1488.29	% SZS status Started for HL400260+4.p
2604.83/1488.29	% SZS status GaveUp for HL400260+4.p
2604.83/1488.29	% SZS status Ended for HL400260+4.p
2605.23/1488.40	% SZS status Started for HL400264+4.p
2605.23/1488.40	% SZS status Theorem for HL400264+4.p
2605.23/1488.40	% SZS status Ended for HL400264+4.p
2606.67/1488.51	% SZS status Started for HL400264+5.p
2606.67/1488.51	% SZS status Theorem for HL400264+5.p
2606.67/1488.51	% SZS status Ended for HL400264+5.p
2606.67/1488.54	% SZS status Started for HL400260+5.p
2606.67/1488.54	% SZS status GaveUp for HL400260+5.p
2606.67/1488.54	% SZS status Ended for HL400260+5.p
2614.74/1489.58	% SZS status Started for HL400261+4.p
2614.74/1489.58	% SZS status GaveUp for HL400261+4.p
2614.74/1489.58	% SZS status Ended for HL400261+4.p
2615.86/1489.66	% SZS status Started for HL400261+5.p
2615.86/1489.66	% SZS status GaveUp for HL400261+5.p
2615.86/1489.66	% SZS status Ended for HL400261+5.p
2625.51/1490.84	% SZS status Started for HL400262+4.p
2625.51/1490.84	% SZS status GaveUp for HL400262+4.p
2625.51/1490.84	% SZS status Ended for HL400262+4.p
2626.93/1491.06	% SZS status Started for HL400269+4.p
2626.93/1491.06	% SZS status Theorem for HL400269+4.p
2626.93/1491.06	% SZS status Ended for HL400269+4.p
2627.75/1491.18	% SZS status Started for HL400269+5.p
2627.75/1491.18	% SZS status Theorem for HL400269+5.p
2627.75/1491.18	% SZS status Ended for HL400269+5.p
2654.72/1494.56	% SZS status Started for HL400262+5.p
2654.72/1494.56	% SZS status GaveUp for HL400262+5.p
2654.72/1494.56	% SZS status Ended for HL400262+5.p
2663.66/1495.73	% SZS status Started for HL400263+4.p
2663.66/1495.73	% SZS status GaveUp for HL400263+4.p
2663.66/1495.73	% SZS status Ended for HL400263+4.p
2665.35/1495.94	% SZS status Started for HL400271+4.p
2665.35/1495.94	% SZS status Theorem for HL400271+4.p
2665.35/1495.94	% SZS status Ended for HL400271+4.p
2665.89/1496.06	% SZS status Started for HL400271+5.p
2665.89/1496.06	% SZS status Theorem for HL400271+5.p
2665.89/1496.06	% SZS status Ended for HL400271+5.p
2666.64/1496.10	% SZS status Started for HL400263+5.p
2666.64/1496.10	% SZS status GaveUp for HL400263+5.p
2666.64/1496.10	% SZS status Ended for HL400263+5.p
2666.80/1496.18	% SZS status Started for HL400272+4.p
2666.80/1496.18	% SZS status Theorem for HL400272+4.p
2666.80/1496.18	% SZS status Ended for HL400272+4.p
2667.19/1496.22	% SZS status Started for HL400272+5.p
2667.19/1496.22	% SZS status Theorem for HL400272+5.p
2667.19/1496.22	% SZS status Ended for HL400272+5.p
2667.60/1496.29	% SZS status Started for HL400273+4.p
2667.60/1496.29	% SZS status Theorem for HL400273+4.p
2667.60/1496.29	% SZS status Ended for HL400273+4.p
2667.60/1496.34	% SZS status Started for HL400273+5.p
2667.60/1496.34	% SZS status Theorem for HL400273+5.p
2667.60/1496.34	% SZS status Ended for HL400273+5.p
2668.23/1496.40	% SZS status Started for HL400274+4.p
2668.23/1496.40	% SZS status Theorem for HL400274+4.p
2668.23/1496.40	% SZS status Ended for HL400274+4.p
2670.03/1496.46	% SZS status Started for HL400274+5.p
2670.03/1496.46	% SZS status Theorem for HL400274+5.p
2670.03/1496.46	% SZS status Ended for HL400274+5.p
2670.77/1496.63	% SZS status Started for HL400266+5.p
2670.77/1496.63	% SZS status GaveUp for HL400266+5.p
2670.77/1496.63	% SZS status Ended for HL400266+5.p
2671.82/1496.82	% SZS status Started for HL400266+4.p
2671.82/1496.82	% SZS status GaveUp for HL400266+4.p
2671.82/1496.82	% SZS status Ended for HL400266+4.p
2679.63/1497.73	% SZS status Started for HL400267+5.p
2679.63/1497.73	% SZS status GaveUp for HL400267+5.p
2679.63/1497.73	% SZS status Ended for HL400267+5.p
2680.43/1497.79	% SZS status Started for HL400267+4.p
2680.43/1497.79	% SZS status GaveUp for HL400267+4.p
2680.43/1497.79	% SZS status Ended for HL400267+4.p
2680.84/1497.91	% SZS status Started for HL400277+5.p
2680.84/1497.91	% SZS status Theorem for HL400277+5.p
2680.84/1497.91	% SZS status Ended for HL400277+5.p
2693.32/1499.43	% SZS status Started for HL400270+4.p
2693.32/1499.43	% SZS status GaveUp for HL400270+4.p
2693.32/1499.43	% SZS status Ended for HL400270+4.p
2704.00/1500.89	% SZS status Started for HL400277+4.p
2704.00/1500.89	% SZS status Theorem for HL400277+4.p
2704.00/1500.89	% SZS status Ended for HL400277+4.p
2719.16/1502.69	% SZS status Started for HL400270+5.p
2719.16/1502.69	% SZS status GaveUp for HL400270+5.p
2719.16/1502.69	% SZS status Ended for HL400270+5.p
2734.47/1504.56	% SZS status Started for HL400275+5.p
2734.47/1504.56	% SZS status GaveUp for HL400275+5.p
2734.47/1504.56	% SZS status Ended for HL400275+5.p
2735.26/1504.64	% SZS status Started for HL400275+4.p
2735.26/1504.64	% SZS status GaveUp for HL400275+4.p
2735.26/1504.64	% SZS status Ended for HL400275+4.p
2736.11/1504.85	% SZS status Started for HL400276+4.p
2736.11/1504.85	% SZS status GaveUp for HL400276+4.p
2736.11/1504.85	% SZS status Ended for HL400276+4.p
2737.29/1504.91	% SZS status Started for HL400276+5.p
2737.29/1504.91	% SZS status GaveUp for HL400276+5.p
2737.29/1504.91	% SZS status Ended for HL400276+5.p
2746.77/1506.15	% SZS status Started for HL400278+4.p
2746.77/1506.15	% SZS status GaveUp for HL400278+4.p
2746.77/1506.15	% SZS status Ended for HL400278+4.p
2758.83/1507.66	% SZS status Started for HL400278+5.p
2758.83/1507.66	% SZS status GaveUp for HL400278+5.p
2758.83/1507.66	% SZS status Ended for HL400278+5.p
2770.17/1509.07	% SZS status Started for HL400279+4.p
2770.17/1509.07	% SZS status GaveUp for HL400279+4.p
2770.17/1509.07	% SZS status Ended for HL400279+4.p
2783.87/1510.78	% SZS status Started for HL400279+5.p
2783.87/1510.78	% SZS status GaveUp for HL400279+5.p
2783.87/1510.78	% SZS status Ended for HL400279+5.p
2799.73/1512.78	% SZS status Started for HL400280+4.p
2799.73/1512.78	% SZS status GaveUp for HL400280+4.p
2799.73/1512.78	% SZS status Ended for HL400280+4.p
2799.73/1512.80	% SZS status Started for HL400280+5.p
2799.73/1512.80	% SZS status GaveUp for HL400280+5.p
2799.73/1512.80	% SZS status Ended for HL400280+5.p
2800.70/1512.92	% SZS status Started for HL400285+5.p
2800.70/1512.92	% SZS status Theorem for HL400285+5.p
2800.70/1512.92	% SZS status Ended for HL400285+5.p
2800.70/1512.93	% SZS status Started for HL400285+4.p
2800.70/1512.93	% SZS status Theorem for HL400285+4.p
2800.70/1512.93	% SZS status Ended for HL400285+4.p
2801.24/1513.02	% SZS status Started for HL400281+5.p
2801.24/1513.02	% SZS status GaveUp for HL400281+5.p
2801.24/1513.02	% SZS status Ended for HL400281+5.p
2801.24/1513.04	% SZS status Started for HL400281+4.p
2801.24/1513.04	% SZS status GaveUp for HL400281+4.p
2801.24/1513.04	% SZS status Ended for HL400281+4.p
2801.24/1513.05	% SZS status Started for HL400286+5.p
2801.24/1513.05	% SZS status Theorem for HL400286+5.p
2801.24/1513.05	% SZS status Ended for HL400286+5.p
2801.74/1513.06	% SZS status Started for HL400286+4.p
2801.74/1513.06	% SZS status Theorem for HL400286+4.p
2801.74/1513.06	% SZS status Ended for HL400286+4.p
2811.92/1514.50	% SZS status Started for HL400282+4.p
2811.92/1514.50	% SZS status GaveUp for HL400282+4.p
2811.92/1514.50	% SZS status Ended for HL400282+4.p
2823.92/1515.78	% SZS status Started for HL400282+5.p
2823.92/1515.78	% SZS status GaveUp for HL400282+5.p
2823.92/1515.78	% SZS status Ended for HL400282+5.p
2834.56/1517.28	% SZS status Started for HL400283+4.p
2834.56/1517.28	% SZS status GaveUp for HL400283+4.p
2834.56/1517.28	% SZS status Ended for HL400283+4.p
2848.31/1518.86	% SZS status Started for HL400283+5.p
2848.31/1518.86	% SZS status GaveUp for HL400283+5.p
2848.31/1518.86	% SZS status Ended for HL400283+5.p
2865.85/1521.12	% SZS status Started for HL400287+5.p
2865.85/1521.12	% SZS status GaveUp for HL400287+5.p
2865.85/1521.12	% SZS status Ended for HL400287+5.p
2866.54/1521.25	% SZS status Started for HL400288+4.p
2866.54/1521.25	% SZS status GaveUp for HL400288+4.p
2866.54/1521.25	% SZS status Ended for HL400288+4.p
2867.68/1521.29	% SZS status Started for HL400287+4.p
2867.68/1521.29	% SZS status GaveUp for HL400287+4.p
2867.68/1521.29	% SZS status Ended for HL400287+4.p
2867.68/1521.30	% SZS status Started for HL400288+5.p
2867.68/1521.30	% SZS status GaveUp for HL400288+5.p
2867.68/1521.30	% SZS status Ended for HL400288+5.p
2878.92/1522.68	% SZS status Started for HL400289+4.p
2878.92/1522.68	% SZS status GaveUp for HL400289+4.p
2878.92/1522.68	% SZS status Ended for HL400289+4.p
2888.28/1523.88	% SZS status Started for HL400289+5.p
2888.28/1523.88	% SZS status GaveUp for HL400289+5.p
2888.28/1523.88	% SZS status Ended for HL400289+5.p
2899.60/1525.50	% SZS status Started for HL400291+4.p
2899.60/1525.50	% SZS status GaveUp for HL400291+4.p
2899.60/1525.50	% SZS status Ended for HL400291+4.p
2901.90/1525.64	% SZS status Started for HL400296+4.p
2901.90/1525.64	% SZS status Theorem for HL400296+4.p
2901.90/1525.64	% SZS status Ended for HL400296+4.p
2903.17/1525.77	% SZS status Started for HL400296+5.p
2903.17/1525.77	% SZS status Theorem for HL400296+5.p
2903.17/1525.77	% SZS status Ended for HL400296+5.p
2912.66/1526.97	% SZS status Started for HL400291+5.p
2912.66/1526.97	% SZS status GaveUp for HL400291+5.p
2912.66/1526.97	% SZS status Ended for HL400291+5.p
2931.39/1529.27	% SZS status Started for HL400292+4.p
2931.39/1529.27	% SZS status GaveUp for HL400292+4.p
2931.39/1529.27	% SZS status Ended for HL400292+4.p
2932.12/1529.39	% SZS status Started for HL400292+5.p
2932.12/1529.39	% SZS status GaveUp for HL400292+5.p
2932.12/1529.39	% SZS status Ended for HL400292+5.p
2932.54/1529.44	% SZS status Started for HL400293+5.p
2932.54/1529.44	% SZS status GaveUp for HL400293+5.p
2932.54/1529.44	% SZS status Ended for HL400293+5.p
2932.54/1529.46	% SZS status Started for HL400293+4.p
2932.54/1529.46	% SZS status GaveUp for HL400293+4.p
2932.54/1529.46	% SZS status Ended for HL400293+4.p
2933.06/1529.58	% SZS status Started for HL400299+4.p
2933.06/1529.58	% SZS status Theorem for HL400299+4.p
2933.06/1529.58	% SZS status Ended for HL400299+4.p
2936.76/1529.95	% SZS status Started for HL400299+5.p
2936.76/1529.95	% SZS status Theorem for HL400299+5.p
2936.76/1529.95	% SZS status Ended for HL400299+5.p
2943.73/1530.88	% SZS status Started for HL400294+4.p
2943.73/1530.88	% SZS status GaveUp for HL400294+4.p
2943.73/1530.88	% SZS status Ended for HL400294+4.p
2952.92/1532.04	% SZS status Started for HL400294+5.p
2952.92/1532.04	% SZS status GaveUp for HL400294+5.p
2952.92/1532.04	% SZS status Ended for HL400294+5.p
2969.18/1534.01	% SZS status Started for HL400297+4.p
2969.18/1534.01	% SZS status GaveUp for HL400297+4.p
2969.18/1534.01	% SZS status Ended for HL400297+4.p
2976.57/1535.04	% SZS status Started for HL400297+5.p
2976.57/1535.04	% SZS status GaveUp for HL400297+5.p
2976.57/1535.04	% SZS status Ended for HL400297+5.p
2996.26/1537.43	% SZS status Started for HL400298+4.p
2996.26/1537.43	% SZS status GaveUp for HL400298+4.p
2996.26/1537.43	% SZS status Ended for HL400298+4.p
2996.75/1537.51	% SZS status Started for HL400298+5.p
2996.75/1537.51	% SZS status GaveUp for HL400298+5.p
2996.75/1537.51	% SZS status Ended for HL400298+5.p
2998.24/1537.77	% SZS status Started for HL400300+4.p
2998.24/1537.77	% SZS status GaveUp for HL400300+4.p
2998.24/1537.77	% SZS status Ended for HL400300+4.p
3001.50/1538.09	% SZS status Started for HL400300+5.p
3001.50/1538.09	% SZS status GaveUp for HL400300+5.p
3001.50/1538.09	% SZS status Ended for HL400300+5.p
3009.72/1539.13	% SZS status Started for HL400301+4.p
3009.72/1539.13	% SZS status GaveUp for HL400301+4.p
3009.72/1539.13	% SZS status Ended for HL400301+4.p
3010.34/1539.26	% SZS status Started for HL400305+4.p
3010.34/1539.26	% SZS status Theorem for HL400305+4.p
3010.34/1539.26	% SZS status Ended for HL400305+4.p
3016.86/1540.03	% SZS status Started for HL400305+5.p
3016.86/1540.03	% SZS status Theorem for HL400305+5.p
3016.86/1540.03	% SZS status Ended for HL400305+5.p
3018.34/1540.20	% SZS status Started for HL400301+5.p
3018.34/1540.20	% SZS status GaveUp for HL400301+5.p
3018.34/1540.20	% SZS status Ended for HL400301+5.p
3033.88/1542.20	% SZS status Started for HL400302+4.p
3033.88/1542.20	% SZS status GaveUp for HL400302+4.p
3033.88/1542.20	% SZS status Ended for HL400302+4.p
3041.69/1543.18	% SZS status Started for HL400302+5.p
3041.69/1543.18	% SZS status GaveUp for HL400302+5.p
3041.69/1543.18	% SZS status Ended for HL400302+5.p
3056.42/1545.00	% SZS status Started for HL400306+5.p
3056.42/1545.00	% SZS status Theorem for HL400306+5.p
3056.42/1545.00	% SZS status Ended for HL400306+5.p
3061.44/1545.66	% SZS status Started for HL400303+4.p
3061.44/1545.66	% SZS status GaveUp for HL400303+4.p
3061.44/1545.66	% SZS status Ended for HL400303+4.p
3061.44/1545.66	% SZS status Started for HL400303+5.p
3061.44/1545.66	% SZS status GaveUp for HL400303+5.p
3061.44/1545.66	% SZS status Ended for HL400303+5.p
3063.81/1545.93	% SZS status Started for HL400304+4.p
3063.81/1545.93	% SZS status GaveUp for HL400304+4.p
3063.81/1545.93	% SZS status Ended for HL400304+4.p
3065.97/1546.24	% SZS status Started for HL400304+5.p
3065.97/1546.24	% SZS status GaveUp for HL400304+5.p
3065.97/1546.24	% SZS status Ended for HL400304+5.p
3066.31/1546.37	% SZS status Started for HL400310+4.p
3066.31/1546.37	% SZS status Theorem for HL400310+4.p
3066.31/1546.37	% SZS status Ended for HL400310+4.p
3072.55/1547.02	% SZS status Started for HL400310+5.p
3072.55/1547.02	% SZS status Theorem for HL400310+5.p
3072.55/1547.02	% SZS status Ended for HL400310+5.p
3082.31/1548.28	% SZS status Started for HL400306+4.p
3082.31/1548.28	% SZS status GaveUp for HL400306+4.p
3082.31/1548.28	% SZS status Ended for HL400306+4.p
3099.00/1550.40	% SZS status Started for HL400307+4.p
3099.00/1550.40	% SZS status GaveUp for HL400307+4.p
3099.00/1550.40	% SZS status Ended for HL400307+4.p
3105.89/1551.27	% SZS status Started for HL400307+5.p
3105.89/1551.27	% SZS status GaveUp for HL400307+5.p
3105.89/1551.27	% SZS status Ended for HL400307+5.p
3121.88/1553.27	% SZS status Started for HL400308+4.p
3121.88/1553.27	% SZS status GaveUp for HL400308+4.p
3121.88/1553.27	% SZS status Ended for HL400308+4.p
3122.79/1553.40	% SZS status Started for HL400314+4.p
3122.79/1553.40	% SZS status Theorem for HL400314+4.p
3122.79/1553.40	% SZS status Ended for HL400314+4.p
3126.02/1553.74	% SZS status Started for HL400308+5.p
3126.02/1553.74	% SZS status GaveUp for HL400308+5.p
3126.02/1553.74	% SZS status Ended for HL400308+5.p
3126.64/1553.87	% SZS status Started for HL400309+4.p
3126.64/1553.87	% SZS status GaveUp for HL400309+4.p
3126.64/1553.87	% SZS status Ended for HL400309+4.p
3127.86/1554.01	% SZS status Started for HL400314+5.p
3127.86/1554.01	% SZS status Theorem for HL400314+5.p
3127.86/1554.01	% SZS status Ended for HL400314+5.p
3128.50/1554.03	% SZS status Started for HL400309+5.p
3128.50/1554.03	% SZS status GaveUp for HL400309+5.p
3128.50/1554.03	% SZS status Ended for HL400309+5.p
3137.93/1555.24	% SZS status Started for HL400311+4.p
3137.93/1555.24	% SZS status GaveUp for HL400311+4.p
3137.93/1555.24	% SZS status Ended for HL400311+4.p
3147.28/1556.44	% SZS status Started for HL400311+5.p
3147.28/1556.44	% SZS status GaveUp for HL400311+5.p
3147.28/1556.44	% SZS status Ended for HL400311+5.p
3164.75/1558.60	% SZS status Started for HL400313+4.p
3164.75/1558.60	% SZS status GaveUp for HL400313+4.p
3164.75/1558.60	% SZS status Ended for HL400313+4.p
3172.23/1559.47	% SZS status Started for HL400313+5.p
3172.23/1559.47	% SZS status GaveUp for HL400313+5.p
3172.23/1559.47	% SZS status Ended for HL400313+5.p
3187.76/1561.54	% SZS status Started for HL400317+5.p
3187.76/1561.54	% SZS status Theorem for HL400317+5.p
3187.76/1561.54	% SZS status Ended for HL400317+5.p
3191.24/1561.89	% SZS status Started for HL400315+4.p
3191.24/1561.89	% SZS status GaveUp for HL400315+4.p
3191.24/1561.89	% SZS status Ended for HL400315+4.p
3191.80/1561.96	% SZS status Started for HL400315+5.p
3191.80/1561.96	% SZS status GaveUp for HL400315+5.p
3191.80/1561.96	% SZS status Ended for HL400315+5.p
3192.91/1562.19	% SZS status Started for HL400316+5.p
3192.91/1562.19	% SZS status GaveUp for HL400316+5.p
3192.91/1562.19	% SZS status Ended for HL400316+5.p
3192.91/1562.20	% SZS status Started for HL400316+4.p
3192.91/1562.20	% SZS status GaveUp for HL400316+4.p
3192.91/1562.20	% SZS status Ended for HL400316+4.p
3203.56/1563.45	% SZS status Started for HL400317+4.p
3203.56/1563.45	% SZS status GaveUp for HL400317+4.p
3203.56/1563.45	% SZS status Ended for HL400317+4.p
3210.35/1564.46	% SZS status Started for HL400318+5.p
3210.35/1564.46	% SZS status Theorem for HL400318+5.p
3210.35/1564.46	% SZS status Ended for HL400318+5.p
3230.61/1566.83	% SZS status Started for HL400318+4.p
3230.61/1566.83	% SZS status GaveUp for HL400318+4.p
3230.61/1566.83	% SZS status Ended for HL400318+4.p
3253.32/1569.70	% SZS status Started for HL400320+4.p
3253.32/1569.70	% SZS status GaveUp for HL400320+4.p
3253.32/1569.70	% SZS status Ended for HL400320+4.p
3255.13/1570.04	% SZS status Started for HL400320+5.p
3255.13/1570.04	% SZS status GaveUp for HL400320+5.p
3255.13/1570.04	% SZS status Ended for HL400320+5.p
3255.45/1570.17	% SZS status Started for HL400321+4.p
3255.45/1570.17	% SZS status GaveUp for HL400321+4.p
3255.45/1570.17	% SZS status Ended for HL400321+4.p
3258.21/1570.28	% SZS status Started for HL400321+5.p
3258.21/1570.28	% SZS status GaveUp for HL400321+5.p
3258.21/1570.28	% SZS status Ended for HL400321+5.p
3258.58/1570.38	% SZS status Started for HL400323+4.p
3258.58/1570.38	% SZS status GaveUp for HL400323+4.p
3258.58/1570.38	% SZS status Ended for HL400323+4.p
3268.49/1571.62	% SZS status Started for HL400323+5.p
3268.49/1571.62	% SZS status GaveUp for HL400323+5.p
3268.49/1571.62	% SZS status Ended for HL400323+5.p
3277.09/1572.67	% SZS status Started for HL400324+4.p
3277.09/1572.67	% SZS status GaveUp for HL400324+4.p
3277.09/1572.67	% SZS status Ended for HL400324+4.p
3287.01/1573.99	% SZS status Started for HL400325+4.p
3287.01/1573.99	% SZS status Theorem for HL400325+4.p
3287.01/1573.99	% SZS status Ended for HL400325+4.p
3294.34/1574.85	% SZS status Started for HL400325+5.p
3294.34/1574.85	% SZS status Theorem for HL400325+5.p
3294.34/1574.85	% SZS status Ended for HL400325+5.p
3294.85/1574.93	% SZS status Started for HL400324+5.p
3294.85/1574.93	% SZS status GaveUp for HL400324+5.p
3294.85/1574.93	% SZS status Ended for HL400324+5.p
3322.04/1578.36	% SZS status Started for HL400328+4.p
3322.04/1578.36	% SZS status GaveUp for HL400328+4.p
3322.04/1578.36	% SZS status Ended for HL400328+4.p
3323.15/1578.44	% SZS status Started for HL400328+5.p
3323.15/1578.44	% SZS status GaveUp for HL400328+5.p
3323.15/1578.44	% SZS status Ended for HL400328+5.p
3324.13/1578.59	% SZS status Started for HL400329+4.p
3324.13/1578.59	% SZS status GaveUp for HL400329+4.p
3324.13/1578.59	% SZS status Ended for HL400329+4.p
3332.52/1579.70	% SZS status Started for HL400329+5.p
3332.52/1579.70	% SZS status GaveUp for HL400329+5.p
3332.52/1579.70	% SZS status Ended for HL400329+5.p
3341.31/1580.83	% SZS status Started for HL400330+4.p
3341.31/1580.83	% SZS status GaveUp for HL400330+4.p
3341.31/1580.83	% SZS status Ended for HL400330+4.p
3352.74/1582.17	% SZS status Started for HL400330+5.p
3352.74/1582.17	% SZS status GaveUp for HL400330+5.p
3352.74/1582.17	% SZS status Ended for HL400330+5.p
3358.94/1583.01	% SZS status Started for HL400331+4.p
3358.94/1583.01	% SZS status GaveUp for HL400331+4.p
3358.94/1583.01	% SZS status Ended for HL400331+4.p
3358.94/1583.02	% SZS status Started for HL400331+5.p
3358.94/1583.02	% SZS status GaveUp for HL400331+5.p
3358.94/1583.02	% SZS status Ended for HL400331+5.p
3386.47/1586.55	% SZS status Started for HL400332+5.p
3386.47/1586.55	% SZS status GaveUp for HL400332+5.p
3386.47/1586.55	% SZS status Ended for HL400332+5.p
3387.94/1586.61	% SZS status Started for HL400332+4.p
3387.94/1586.61	% SZS status GaveUp for HL400332+4.p
3387.94/1586.61	% SZS status Ended for HL400332+4.p
3389.06/1586.77	% SZS status Started for HL400333+4.p
3389.06/1586.77	% SZS status GaveUp for HL400333+4.p
3389.06/1586.77	% SZS status Ended for HL400333+4.p
3397.20/1587.78	% SZS status Started for HL400333+5.p
3397.20/1587.78	% SZS status GaveUp for HL400333+5.p
3397.20/1587.78	% SZS status Ended for HL400333+5.p
3407.70/1589.07	% SZS status Started for HL400334+4.p
3407.70/1589.07	% SZS status GaveUp for HL400334+4.p
3407.70/1589.07	% SZS status Ended for HL400334+4.p
3417.34/1590.26	% SZS status Started for HL400334+5.p
3417.34/1590.26	% SZS status GaveUp for HL400334+5.p
3417.34/1590.26	% SZS status Ended for HL400334+5.p
3424.63/1591.15	% SZS status Started for HL400335+4.p
3424.63/1591.15	% SZS status GaveUp for HL400335+4.p
3424.63/1591.15	% SZS status Ended for HL400335+4.p
3425.20/1591.26	% SZS status Started for HL400335+5.p
3425.20/1591.26	% SZS status GaveUp for HL400335+5.p
3425.20/1591.26	% SZS status Ended for HL400335+5.p
3452.95/1594.73	% SZS status Started for HL400336+5.p
3452.95/1594.73	% SZS status GaveUp for HL400336+5.p
3452.95/1594.73	% SZS status Ended for HL400336+5.p
3453.95/1594.82	% SZS status Started for HL400336+4.p
3453.95/1594.82	% SZS status GaveUp for HL400336+4.p
3453.95/1594.82	% SZS status Ended for HL400336+4.p
3454.49/1594.97	% SZS status Started for HL400337+4.p
3454.49/1594.97	% SZS status GaveUp for HL400337+4.p
3454.49/1594.97	% SZS status Ended for HL400337+4.p
3462.34/1595.89	% SZS status Started for HL400337+5.p
3462.34/1595.89	% SZS status GaveUp for HL400337+5.p
3462.34/1595.89	% SZS status Ended for HL400337+5.p
3472.15/1597.27	% SZS status Started for HL400338+4.p
3472.15/1597.27	% SZS status GaveUp for HL400338+4.p
3472.15/1597.27	% SZS status Ended for HL400338+4.p
3481.65/1598.37	% SZS status Started for HL400338+5.p
3481.65/1598.37	% SZS status GaveUp for HL400338+5.p
3481.65/1598.37	% SZS status Ended for HL400338+5.p
3489.99/1599.36	% SZS status Started for HL400340+4.p
3489.99/1599.36	% SZS status GaveUp for HL400340+4.p
3489.99/1599.36	% SZS status Ended for HL400340+4.p
3489.99/1599.37	% SZS status Started for HL400340+5.p
3489.99/1599.37	% SZS status GaveUp for HL400340+5.p
3489.99/1599.37	% SZS status Ended for HL400340+5.p
3518.16/1602.93	% SZS status Started for HL400342+4.p
3518.16/1602.93	% SZS status GaveUp for HL400342+4.p
3518.16/1602.93	% SZS status Ended for HL400342+4.p
3518.77/1602.97	% SZS status Started for HL400342+5.p
3518.77/1602.97	% SZS status GaveUp for HL400342+5.p
3518.77/1602.97	% SZS status Ended for HL400342+5.p
3519.96/1603.20	% SZS status Started for HL400343+4.p
3519.96/1603.20	% SZS status GaveUp for HL400343+4.p
3519.96/1603.20	% SZS status Ended for HL400343+4.p
3526.59/1603.98	% SZS status Started for HL400343+5.p
3526.59/1603.98	% SZS status GaveUp for HL400343+5.p
3526.59/1603.98	% SZS status Ended for HL400343+5.p
3538.50/1605.45	% SZS status Started for HL400344+4.p
3538.50/1605.45	% SZS status GaveUp for HL400344+4.p
3538.50/1605.45	% SZS status Ended for HL400344+4.p
3545.44/1606.48	% SZS status Started for HL400344+5.p
3545.44/1606.48	% SZS status GaveUp for HL400344+5.p
3545.44/1606.48	% SZS status Ended for HL400344+5.p
3553.86/1607.46	% SZS status Started for HL400345+5.p
3553.86/1607.46	% SZS status GaveUp for HL400345+5.p
3553.86/1607.46	% SZS status Ended for HL400345+5.p
3554.72/1607.57	% SZS status Started for HL400345+4.p
3554.72/1607.57	% SZS status GaveUp for HL400345+4.p
3554.72/1607.57	% SZS status Ended for HL400345+4.p
3582.82/1611.06	% SZS status Started for HL400346+5.p
3582.82/1611.06	% SZS status GaveUp for HL400346+5.p
3582.82/1611.06	% SZS status Ended for HL400346+5.p
3583.37/1611.14	% SZS status Started for HL400346+4.p
3583.37/1611.14	% SZS status GaveUp for HL400346+4.p
3583.37/1611.14	% SZS status Ended for HL400346+4.p
3586.63/1611.48	% SZS status Started for HL400347+4.p
3586.63/1611.48	% SZS status GaveUp for HL400347+4.p
3586.63/1611.48	% SZS status Ended for HL400347+4.p
3591.84/1612.15	% SZS status Started for HL400347+5.p
3591.84/1612.15	% SZS status GaveUp for HL400347+5.p
3591.84/1612.15	% SZS status Ended for HL400347+5.p
3603.30/1613.60	% SZS status Started for HL400348+4.p
3603.30/1613.60	% SZS status GaveUp for HL400348+4.p
3603.30/1613.60	% SZS status Ended for HL400348+4.p
3610.89/1614.59	% SZS status Started for HL400348+5.p
3610.89/1614.59	% SZS status GaveUp for HL400348+5.p
3610.89/1614.59	% SZS status Ended for HL400348+5.p
3618.22/1615.67	% SZS status Started for HL400350+4.p
3618.22/1615.67	% SZS status GaveUp for HL400350+4.p
3618.22/1615.67	% SZS status Ended for HL400350+4.p
3618.69/1615.72	% SZS status Started for HL400350+5.p
3618.69/1615.72	% SZS status GaveUp for HL400350+5.p
3618.69/1615.72	% SZS status Ended for HL400350+5.p
3648.11/1619.24	% SZS status Started for HL400351+5.p
3648.11/1619.24	% SZS status GaveUp for HL400351+5.p
3648.11/1619.24	% SZS status Ended for HL400351+5.p
3648.11/1619.24	% SZS status Started for HL400351+4.p
3648.11/1619.24	% SZS status GaveUp for HL400351+4.p
3648.11/1619.24	% SZS status Ended for HL400351+4.p
3651.42/1619.64	% SZS status Started for HL400352+4.p
3651.42/1619.64	% SZS status GaveUp for HL400352+4.p
3651.42/1619.64	% SZS status Ended for HL400352+4.p
3656.29/1620.24	% SZS status Started for HL400352+5.p
3656.29/1620.24	% SZS status GaveUp for HL400352+5.p
3656.29/1620.24	% SZS status Ended for HL400352+5.p
3666.91/1621.78	% SZS status Started for HL400353+4.p
3666.91/1621.78	% SZS status GaveUp for HL400353+4.p
3666.91/1621.78	% SZS status Ended for HL400353+4.p
3676.87/1622.82	% SZS status Started for HL400353+5.p
3676.87/1622.82	% SZS status GaveUp for HL400353+5.p
3676.87/1622.82	% SZS status Ended for HL400353+5.p
3684.60/1623.80	% SZS status Started for HL400355+5.p
3684.60/1623.80	% SZS status GaveUp for HL400355+5.p
3684.60/1623.80	% SZS status Ended for HL400355+5.p
3684.93/1623.87	% SZS status Started for HL400355+4.p
3684.93/1623.87	% SZS status GaveUp for HL400355+4.p
3684.93/1623.87	% SZS status Ended for HL400355+4.p
3711.67/1627.34	% SZS status Started for HL400356+5.p
3711.67/1627.34	% SZS status GaveUp for HL400356+5.p
3711.67/1627.34	% SZS status Ended for HL400356+5.p
3711.98/1627.45	% SZS status Started for HL400356+4.p
3711.98/1627.45	% SZS status GaveUp for HL400356+4.p
3711.98/1627.45	% SZS status Ended for HL400356+4.p
3716.72/1627.83	% SZS status Started for HL400358+4.p
3716.72/1627.83	% SZS status GaveUp for HL400358+4.p
3716.72/1627.83	% SZS status Ended for HL400358+4.p
3720.37/1628.34	% SZS status Started for HL400358+5.p
3720.37/1628.34	% SZS status GaveUp for HL400358+5.p
3720.37/1628.34	% SZS status Ended for HL400358+5.p
3733.27/1629.96	% SZS status Started for HL400359+4.p
3733.27/1629.96	% SZS status GaveUp for HL400359+4.p
3733.27/1629.96	% SZS status Ended for HL400359+4.p
3741.42/1630.92	% SZS status Started for HL400359+5.p
3741.42/1630.92	% SZS status GaveUp for HL400359+5.p
3741.42/1630.92	% SZS status Ended for HL400359+5.p
3749.90/1632.04	% SZS status Started for HL400360+4.p
3749.90/1632.04	% SZS status GaveUp for HL400360+4.p
3749.90/1632.04	% SZS status Ended for HL400360+4.p
3750.77/1632.10	% SZS status Started for HL400360+5.p
3750.77/1632.10	% SZS status GaveUp for HL400360+5.p
3750.77/1632.10	% SZS status Ended for HL400360+5.p
3776.93/1635.47	% SZS status Started for HL400361+4.p
3776.93/1635.47	% SZS status GaveUp for HL400361+4.p
3776.93/1635.47	% SZS status Ended for HL400361+4.p
3785.43/1635.58	% SZS status Started for HL400361+5.p
3785.43/1635.58	% SZS status GaveUp for HL400361+5.p
3785.43/1635.58	% SZS status Ended for HL400361+5.p
3789.26/1636.01	% SZS status Started for HL400362+4.p
3789.26/1636.01	% SZS status GaveUp for HL400362+4.p
3789.26/1636.01	% SZS status Ended for HL400362+4.p
3791.01/1636.52	% SZS status Started for HL400362+5.p
3791.01/1636.52	% SZS status GaveUp for HL400362+5.p
3791.01/1636.52	% SZS status Ended for HL400362+5.p
3811.03/1638.11	% SZS status Started for HL400363+4.p
3811.03/1638.11	% SZS status GaveUp for HL400363+4.p
3811.03/1638.11	% SZS status Ended for HL400363+4.p
3818.19/1639.02	% SZS status Started for HL400363+5.p
3818.19/1639.02	% SZS status GaveUp for HL400363+5.p
3818.19/1639.02	% SZS status Ended for HL400363+5.p
3828.05/1640.23	% SZS status Started for HL400364+5.p
3828.05/1640.23	% SZS status GaveUp for HL400364+5.p
3828.05/1640.23	% SZS status Ended for HL400364+5.p
3828.54/1640.29	% SZS status Started for HL400364+4.p
3828.54/1640.29	% SZS status GaveUp for HL400364+4.p
3828.54/1640.29	% SZS status Ended for HL400364+4.p
3854.54/1643.70	% SZS status Started for HL400366+5.p
3854.54/1643.70	% SZS status GaveUp for HL400366+5.p
3854.54/1643.70	% SZS status Ended for HL400366+5.p
3854.63/1643.72	% SZS status Started for HL400366+4.p
3854.63/1643.72	% SZS status GaveUp for HL400366+4.p
3854.63/1643.72	% SZS status Ended for HL400366+4.p
3860.13/1644.22	% SZS status Started for HL400367+4.p
3860.13/1644.22	% SZS status GaveUp for HL400367+4.p
3860.13/1644.22	% SZS status Ended for HL400367+4.p
3863.58/1644.67	% SZS status Started for HL400367+5.p
3863.58/1644.67	% SZS status GaveUp for HL400367+5.p
3863.58/1644.67	% SZS status Ended for HL400367+5.p
3876.58/1646.30	% SZS status Started for HL400368+4.p
3876.58/1646.30	% SZS status GaveUp for HL400368+4.p
3876.58/1646.30	% SZS status Ended for HL400368+4.p
3881.95/1647.09	% SZS status Started for HL400368+5.p
3881.95/1647.09	% SZS status GaveUp for HL400368+5.p
3881.95/1647.09	% SZS status Ended for HL400368+5.p
3892.31/1648.38	% SZS status Started for HL400369+4.p
3892.31/1648.38	% SZS status GaveUp for HL400369+4.p
3892.31/1648.38	% SZS status Ended for HL400369+4.p
3892.83/1648.47	% SZS status Started for HL400369+5.p
3892.83/1648.47	% SZS status GaveUp for HL400369+5.p
3892.83/1648.47	% SZS status Ended for HL400369+5.p
3919.41/1651.80	% SZS status Started for HL400370+5.p
3919.41/1651.80	% SZS status GaveUp for HL400370+5.p
3919.41/1651.80	% SZS status Ended for HL400370+5.p
3919.41/1651.91	% SZS status Started for HL400370+4.p
3919.41/1651.91	% SZS status GaveUp for HL400370+4.p
3919.41/1651.91	% SZS status Ended for HL400370+4.p
3924.88/1652.45	% SZS status Started for HL400372+4.p
3924.88/1652.45	% SZS status GaveUp for HL400372+4.p
3924.88/1652.45	% SZS status Ended for HL400372+4.p
3927.94/1652.75	% SZS status Started for HL400372+5.p
3927.94/1652.75	% SZS status GaveUp for HL400372+5.p
3927.94/1652.75	% SZS status Ended for HL400372+5.p
3941.52/1654.48	% SZS status Started for HL400373+4.p
3941.52/1654.48	% SZS status GaveUp for HL400373+4.p
3941.52/1654.48	% SZS status Ended for HL400373+4.p
3947.79/1655.20	% SZS status Started for HL400373+5.p
3947.79/1655.20	% SZS status GaveUp for HL400373+5.p
3947.79/1655.20	% SZS status Ended for HL400373+5.p
3958.00/1656.56	% SZS status Started for HL400374+5.p
3958.00/1656.56	% SZS status GaveUp for HL400374+5.p
3958.00/1656.56	% SZS status Ended for HL400374+5.p
3958.78/1656.59	% SZS status Started for HL400374+4.p
3958.78/1656.59	% SZS status GaveUp for HL400374+4.p
3958.78/1656.59	% SZS status Ended for HL400374+4.p
3985.17/1659.99	% SZS status Started for HL400376+4.p
3985.17/1659.99	% SZS status GaveUp for HL400376+4.p
3985.17/1659.99	% SZS status Ended for HL400376+4.p
3985.50/1660.01	% SZS status Started for HL400376+5.p
3985.50/1660.01	% SZS status GaveUp for HL400376+5.p
3985.50/1660.01	% SZS status Ended for HL400376+5.p
3992.38/1660.70	% SZS status Started for HL400377+4.p
3992.38/1660.70	% SZS status GaveUp for HL400377+4.p
3992.38/1660.70	% SZS status Ended for HL400377+4.p
3993.49/1660.94	% SZS status Started for HL400377+5.p
3993.49/1660.94	% SZS status GaveUp for HL400377+5.p
3993.49/1660.94	% SZS status Ended for HL400377+5.p
4007.64/1662.67	% SZS status Started for HL400378+4.p
4007.64/1662.67	% SZS status GaveUp for HL400378+4.p
4007.64/1662.67	% SZS status Ended for HL400378+4.p
4012.54/1663.32	% SZS status Started for HL400378+5.p
4012.54/1663.32	% SZS status GaveUp for HL400378+5.p
4012.54/1663.32	% SZS status Ended for HL400378+5.p
4024.11/1664.73	% SZS status Started for HL400379+4.p
4024.11/1664.73	% SZS status GaveUp for HL400379+4.p
4024.11/1664.73	% SZS status Ended for HL400379+4.p
4024.11/1664.75	% SZS status Started for HL400379+5.p
4024.11/1664.75	% SZS status GaveUp for HL400379+5.p
4024.11/1664.75	% SZS status Ended for HL400379+5.p
4050.83/1668.10	% SZS status Started for HL400380+5.p
4050.83/1668.10	% SZS status GaveUp for HL400380+5.p
4050.83/1668.10	% SZS status Ended for HL400380+5.p
4051.57/1668.18	% SZS status Started for HL400380+4.p
4051.57/1668.18	% SZS status GaveUp for HL400380+4.p
4051.57/1668.18	% SZS status Ended for HL400380+4.p
4057.55/1668.88	% SZS status Started for HL400381+4.p
4057.55/1668.88	% SZS status GaveUp for HL400381+4.p
4057.55/1668.88	% SZS status Ended for HL400381+4.p
4058.16/1669.07	% SZS status Started for HL400381+5.p
4058.16/1669.07	% SZS status GaveUp for HL400381+5.p
4058.16/1669.07	% SZS status Ended for HL400381+5.p
4072.90/1670.87	% SZS status Started for HL400382+4.p
4072.90/1670.87	% SZS status GaveUp for HL400382+4.p
4072.90/1670.87	% SZS status Ended for HL400382+4.p
4077.46/1671.43	% SZS status Started for HL400382+5.p
4077.46/1671.43	% SZS status GaveUp for HL400382+5.p
4077.46/1671.43	% SZS status Ended for HL400382+5.p
4089.57/1672.91	% SZS status Started for HL400383+4.p
4089.57/1672.91	% SZS status GaveUp for HL400383+4.p
4089.57/1672.91	% SZS status Ended for HL400383+4.p
4090.27/1673.00	% SZS status Started for HL400383+5.p
4090.27/1673.00	% SZS status GaveUp for HL400383+5.p
4090.27/1673.00	% SZS status Ended for HL400383+5.p
4115.36/1676.28	% SZS status Started for HL400385+4.p
4115.36/1676.28	% SZS status GaveUp for HL400385+4.p
4115.36/1676.28	% SZS status Ended for HL400385+4.p
4115.36/1676.30	% SZS status Started for HL400385+5.p
4115.36/1676.30	% SZS status GaveUp for HL400385+5.p
4115.36/1676.30	% SZS status Ended for HL400385+5.p
4123.00/1677.11	% SZS status Started for HL400386+4.p
4123.00/1677.11	% SZS status GaveUp for HL400386+4.p
4123.00/1677.11	% SZS status Ended for HL400386+4.p
4123.00/1677.16	% SZS status Started for HL400386+5.p
4123.00/1677.16	% SZS status GaveUp for HL400386+5.p
4123.00/1677.16	% SZS status Ended for HL400386+5.p
4138.13/1679.06	% SZS status Started for HL400387+4.p
4138.13/1679.06	% SZS status GaveUp for HL400387+4.p
4138.13/1679.06	% SZS status Ended for HL400387+4.p
4142.66/1679.64	% SZS status Started for HL400387+5.p
4142.66/1679.64	% SZS status GaveUp for HL400387+5.p
4142.66/1679.64	% SZS status Ended for HL400387+5.p
4154.26/1681.06	% SZS status Started for HL400389+4.p
4154.26/1681.06	% SZS status GaveUp for HL400389+4.p
4154.26/1681.06	% SZS status Ended for HL400389+4.p
4155.57/1681.24	% SZS status Started for HL400389+5.p
4155.57/1681.24	% SZS status GaveUp for HL400389+5.p
4155.57/1681.24	% SZS status Ended for HL400389+5.p
4180.14/1684.37	% SZS status Started for HL400390+5.p
4180.14/1684.37	% SZS status GaveUp for HL400390+5.p
4180.14/1684.37	% SZS status Ended for HL400390+5.p
4182.14/1684.52	% SZS status Started for HL400390+4.p
4182.14/1684.52	% SZS status GaveUp for HL400390+4.p
4182.14/1684.52	% SZS status Ended for HL400390+4.p
4187.75/1685.26	% SZS status Started for HL400391+4.p
4187.75/1685.26	% SZS status GaveUp for HL400391+4.p
4187.75/1685.26	% SZS status Ended for HL400391+4.p
4187.75/1685.28	% SZS status Started for HL400391+5.p
4187.75/1685.28	% SZS status GaveUp for HL400391+5.p
4187.75/1685.28	% SZS status Ended for HL400391+5.p
4203.47/1687.21	% SZS status Started for HL400392+4.p
4203.47/1687.21	% SZS status GaveUp for HL400392+4.p
4203.47/1687.21	% SZS status Ended for HL400392+4.p
4208.06/1687.82	% SZS status Started for HL400392+5.p
4208.06/1687.82	% SZS status GaveUp for HL400392+5.p
4208.06/1687.82	% SZS status Ended for HL400392+5.p
4219.71/1689.29	% SZS status Started for HL400393+4.p
4219.71/1689.29	% SZS status GaveUp for HL400393+4.p
4219.71/1689.29	% SZS status Ended for HL400393+4.p
4220.73/1689.41	% SZS status Started for HL400393+5.p
4220.73/1689.41	% SZS status GaveUp for HL400393+5.p
4220.73/1689.41	% SZS status Ended for HL400393+5.p
4245.37/1692.51	% SZS status Started for HL400394+4.p
4245.37/1692.51	% SZS status GaveUp for HL400394+4.p
4245.37/1692.51	% SZS status Ended for HL400394+4.p
4246.81/1692.67	% SZS status Started for HL400394+5.p
4246.81/1692.67	% SZS status GaveUp for HL400394+5.p
4246.81/1692.67	% SZS status Ended for HL400394+5.p
4253.43/1693.52	% SZS status Started for HL400395+4.p
4253.43/1693.52	% SZS status GaveUp for HL400395+4.p
4253.43/1693.52	% SZS status Ended for HL400395+4.p
4253.66/1693.54	% SZS status Started for HL400395+5.p
4253.66/1693.54	% SZS status GaveUp for HL400395+5.p
4253.66/1693.54	% SZS status Ended for HL400395+5.p
4267.73/1695.35	% SZS status Started for HL400396+4.p
4267.73/1695.35	% SZS status GaveUp for HL400396+4.p
4267.73/1695.35	% SZS status Ended for HL400396+4.p
4273.87/1696.07	% SZS status Started for HL400396+5.p
4273.87/1696.07	% SZS status GaveUp for HL400396+5.p
4273.87/1696.07	% SZS status Ended for HL400396+5.p
4284.47/1697.45	% SZS status Started for HL400397+4.p
4284.47/1697.45	% SZS status GaveUp for HL400397+4.p
4284.47/1697.45	% SZS status Ended for HL400397+4.p
4285.21/1697.60	% SZS status Started for HL400397+5.p
4285.21/1697.60	% SZS status GaveUp for HL400397+5.p
4285.21/1697.60	% SZS status Ended for HL400397+5.p
4310.93/1700.73	% SZS status Started for HL400398+4.p
4310.93/1700.73	% SZS status GaveUp for HL400398+4.p
4310.93/1700.73	% SZS status Ended for HL400398+4.p
4311.58/1700.91	% SZS status Started for HL400398+5.p
4311.58/1700.91	% SZS status GaveUp for HL400398+5.p
4311.58/1700.91	% SZS status Ended for HL400398+5.p
4319.01/1701.72	% SZS status Started for HL400399+4.p
4319.01/1701.72	% SZS status GaveUp for HL400399+4.p
4319.01/1701.72	% SZS status Ended for HL400399+4.p
4319.01/1701.77	% SZS status Started for HL400399+5.p
4319.01/1701.77	% SZS status GaveUp for HL400399+5.p
4319.01/1701.77	% SZS status Ended for HL400399+5.p
4332.74/1703.48	% SZS status Started for HL400400+4.p
4332.74/1703.48	% SZS status GaveUp for HL400400+4.p
4332.74/1703.48	% SZS status Ended for HL400400+4.p
4334.47/1703.71	% SZS status Started for HL400404+4.p
4334.47/1703.71	% SZS status Theorem for HL400404+4.p
4334.47/1703.71	% SZS status Ended for HL400404+4.p
4338.64/1704.26	% SZS status Started for HL400400+5.p
4338.64/1704.26	% SZS status GaveUp for HL400400+5.p
4338.64/1704.26	% SZS status Ended for HL400400+5.p
4349.14/1705.59	% SZS status Started for HL400401+4.p
4349.14/1705.59	% SZS status GaveUp for HL400401+4.p
4349.14/1705.59	% SZS status Ended for HL400401+4.p
4350.80/1705.79	% SZS status Started for HL400401+5.p
4350.80/1705.79	% SZS status GaveUp for HL400401+5.p
4350.80/1705.79	% SZS status Ended for HL400401+5.p
4375.84/1708.93	% SZS status Started for HL400402+4.p
4375.84/1708.93	% SZS status GaveUp for HL400402+4.p
4375.84/1708.93	% SZS status Ended for HL400402+4.p
4377.84/1709.19	% SZS status Started for HL400402+5.p
4377.84/1709.19	% SZS status GaveUp for HL400402+5.p
4377.84/1709.19	% SZS status Ended for HL400402+5.p
4383.16/1709.86	% SZS status Started for HL400403+4.p
4383.16/1709.86	% SZS status GaveUp for HL400403+4.p
4383.16/1709.86	% SZS status Ended for HL400403+4.p
4384.45/1710.05	% SZS status Started for HL400403+5.p
4384.45/1710.05	% SZS status GaveUp for HL400403+5.p
4384.45/1710.05	% SZS status Ended for HL400403+5.p
4400.12/1711.93	% SZS status Started for HL400404+5.p
4400.12/1711.93	% SZS status GaveUp for HL400404+5.p
4400.12/1711.93	% SZS status Ended for HL400404+5.p
4404.21/1712.43	% SZS status Started for HL400405+4.p
4404.21/1712.43	% SZS status GaveUp for HL400405+4.p
4404.21/1712.43	% SZS status Ended for HL400405+4.p
4414.99/1713.80	% SZS status Started for HL400405+5.p
4414.99/1713.80	% SZS status GaveUp for HL400405+5.p
4414.99/1713.80	% SZS status Ended for HL400405+5.p
4416.66/1714.05	% SZS status Started for HL400406+4.p
4416.66/1714.05	% SZS status GaveUp for HL400406+4.p
4416.66/1714.05	% SZS status Ended for HL400406+4.p
4441.38/1717.14	% SZS status Started for HL400406+5.p
4441.38/1717.14	% SZS status GaveUp for HL400406+5.p
4441.38/1717.14	% SZS status Ended for HL400406+5.p
4442.37/1717.36	% SZS status Started for HL400408+4.p
4442.37/1717.36	% SZS status GaveUp for HL400408+4.p
4442.37/1717.36	% SZS status Ended for HL400408+4.p
4448.28/1718.06	% SZS status Started for HL400408+5.p
4448.28/1718.06	% SZS status GaveUp for HL400408+5.p
4448.28/1718.06	% SZS status Ended for HL400408+5.p
4450.22/1718.23	% SZS status Started for HL400409+4.p
4450.22/1718.23	% SZS status GaveUp for HL400409+4.p
4450.22/1718.23	% SZS status Ended for HL400409+4.p
4464.03/1720.12	% SZS status Started for HL400409+5.p
4464.03/1720.12	% SZS status GaveUp for HL400409+5.p
4464.03/1720.12	% SZS status Ended for HL400409+5.p
4468.05/1720.59	% SZS status Started for HL400410+4.p
4468.05/1720.59	% SZS status GaveUp for HL400410+4.p
4468.05/1720.59	% SZS status Ended for HL400410+4.p
4480.59/1722.06	% SZS status Started for HL400410+5.p
4480.59/1722.06	% SZS status GaveUp for HL400410+5.p
4480.59/1722.06	% SZS status Ended for HL400410+5.p
4481.98/1722.28	% SZS status Started for HL400411+4.p
4481.98/1722.28	% SZS status GaveUp for HL400411+4.p
4481.98/1722.28	% SZS status Ended for HL400411+4.p
4506.44/1725.34	% SZS status Started for HL400411+5.p
4506.44/1725.34	% SZS status GaveUp for HL400411+5.p
4506.44/1725.34	% SZS status Ended for HL400411+5.p
4509.26/1725.62	% SZS status Started for HL400412+4.p
4509.26/1725.62	% SZS status GaveUp for HL400412+4.p
4509.26/1725.62	% SZS status Ended for HL400412+4.p
4513.03/1726.25	% SZS status Started for HL400412+5.p
4513.03/1726.25	% SZS status GaveUp for HL400412+5.p
4513.03/1726.25	% SZS status Ended for HL400412+5.p
4514.95/1726.39	% SZS status Started for HL400414+4.p
4514.95/1726.39	% SZS status GaveUp for HL400414+4.p
4514.95/1726.39	% SZS status Ended for HL400414+4.p
4531.14/1728.42	% SZS status Started for HL400414+5.p
4531.14/1728.42	% SZS status GaveUp for HL400414+5.p
4531.14/1728.42	% SZS status Ended for HL400414+5.p
4533.85/1728.77	% SZS status Started for HL400415+4.p
4533.85/1728.77	% SZS status GaveUp for HL400415+4.p
4533.85/1728.77	% SZS status Ended for HL400415+4.p
4545.06/1730.25	% SZS status Started for HL400415+5.p
4545.06/1730.25	% SZS status GaveUp for HL400415+5.p
4545.06/1730.25	% SZS status Ended for HL400415+5.p
4547.70/1730.49	% SZS status Started for HL400416+4.p
4547.70/1730.49	% SZS status GaveUp for HL400416+4.p
4547.70/1730.49	% SZS status Ended for HL400416+4.p
4571.96/1733.52	% SZS status Started for HL400416+5.p
4571.96/1733.52	% SZS status GaveUp for HL400416+5.p
4571.96/1733.52	% SZS status Ended for HL400416+5.p
4574.41/1733.80	% SZS status Started for HL400417+4.p
4574.41/1733.80	% SZS status GaveUp for HL400417+4.p
4574.41/1733.80	% SZS status Ended for HL400417+4.p
4579.49/1734.49	% SZS status Started for HL400417+5.p
4579.49/1734.49	% SZS status GaveUp for HL400417+5.p
4579.49/1734.49	% SZS status Ended for HL400417+5.p
4579.94/1734.54	% SZS status Started for HL400418+4.p
4579.94/1734.54	% SZS status GaveUp for HL400418+4.p
4579.94/1734.54	% SZS status Ended for HL400418+4.p
4596.94/1736.69	% SZS status Started for HL400418+5.p
4596.94/1736.69	% SZS status GaveUp for HL400418+5.p
4596.94/1736.69	% SZS status Ended for HL400418+5.p
4598.54/1736.95	% SZS status Started for HL400419+4.p
4598.54/1736.95	% SZS status GaveUp for HL400419+4.p
4598.54/1736.95	% SZS status Ended for HL400419+4.p
4611.30/1738.48	% SZS status Started for HL400419+5.p
4611.30/1738.48	% SZS status GaveUp for HL400419+5.p
4611.30/1738.48	% SZS status Ended for HL400419+5.p
4612.53/1738.65	% SZS status Started for HL400420+4.p
4612.53/1738.65	% SZS status GaveUp for HL400420+4.p
4612.53/1738.65	% SZS status Ended for HL400420+4.p
4637.07/1741.71	% SZS status Started for HL400420+5.p
4637.07/1741.71	% SZS status GaveUp for HL400420+5.p
4637.07/1741.71	% SZS status Ended for HL400420+5.p
4638.52/1742.02	% SZS status Started for HL400421+4.p
4638.52/1742.02	% SZS status GaveUp for HL400421+4.p
4638.52/1742.02	% SZS status Ended for HL400421+4.p
4645.25/1742.72	% SZS status Started for HL400422+4.p
4645.25/1742.72	% SZS status GaveUp for HL400422+4.p
4645.25/1742.72	% SZS status Ended for HL400422+4.p
4645.46/1742.73	% SZS status Started for HL400421+5.p
4645.46/1742.73	% SZS status GaveUp for HL400421+5.p
4645.46/1742.73	% SZS status Ended for HL400421+5.p
4662.34/1744.98	% SZS status Started for HL400422+5.p
4662.34/1744.98	% SZS status GaveUp for HL400422+5.p
4662.34/1744.98	% SZS status Ended for HL400422+5.p
4664.22/1745.08	% SZS status Started for HL400423+4.p
4664.22/1745.08	% SZS status GaveUp for HL400423+4.p
4664.22/1745.08	% SZS status Ended for HL400423+4.p
4676.37/1746.67	% SZS status Started for HL400423+5.p
4676.37/1746.67	% SZS status GaveUp for HL400423+5.p
4676.37/1746.67	% SZS status Ended for HL400423+5.p
4677.79/1746.80	% SZS status Started for HL400424+4.p
4677.79/1746.80	% SZS status GaveUp for HL400424+4.p
4677.79/1746.80	% SZS status Ended for HL400424+4.p
4679.67/1747.29	% SZS status Started for HL400428+4.p
4679.67/1747.29	% SZS status Theorem for HL400428+4.p
4679.67/1747.29	% SZS status Ended for HL400428+4.p
4702.59/1749.92	% SZS status Started for HL400424+5.p
4702.59/1749.92	% SZS status GaveUp for HL400424+5.p
4702.59/1749.92	% SZS status Ended for HL400424+5.p
4705.26/1750.26	% SZS status Started for HL400425+4.p
4705.26/1750.26	% SZS status GaveUp for HL400425+4.p
4705.26/1750.26	% SZS status Ended for HL400425+4.p
4710.10/1750.88	% SZS status Started for HL400426+4.p
4710.10/1750.88	% SZS status GaveUp for HL400426+4.p
4710.10/1750.88	% SZS status Ended for HL400426+4.p
4710.90/1750.98	% SZS status Started for HL400425+5.p
4710.90/1750.98	% SZS status GaveUp for HL400425+5.p
4710.90/1750.98	% SZS status Ended for HL400425+5.p
4728.10/1753.17	% SZS status Started for HL400426+5.p
4728.10/1753.17	% SZS status GaveUp for HL400426+5.p
4728.10/1753.17	% SZS status Ended for HL400426+5.p
4742.51/1754.94	% SZS status Started for HL400428+5.p
4742.51/1754.94	% SZS status GaveUp for HL400428+5.p
4742.51/1754.94	% SZS status Ended for HL400428+5.p
4742.91/1754.97	% SZS status Started for HL400429+4.p
4742.91/1754.97	% SZS status GaveUp for HL400429+4.p
4742.91/1754.97	% SZS status Ended for HL400429+4.p
4746.71/1755.50	% SZS status Started for HL400429+5.p
4746.71/1755.50	% SZS status GaveUp for HL400429+5.p
4746.71/1755.50	% SZS status Ended for HL400429+5.p
4767.65/1758.12	% SZS status Started for HL400430+4.p
4767.65/1758.12	% SZS status GaveUp for HL400430+4.p
4767.65/1758.12	% SZS status Ended for HL400430+4.p
4770.02/1758.48	% SZS status Started for HL400430+5.p
4770.02/1758.48	% SZS status GaveUp for HL400430+5.p
4770.02/1758.48	% SZS status Ended for HL400430+5.p
4775.89/1759.11	% SZS status Started for HL400432+4.p
4775.89/1759.11	% SZS status GaveUp for HL400432+4.p
4775.89/1759.11	% SZS status Ended for HL400432+4.p
4776.08/1759.17	% SZS status Started for HL400432+5.p
4776.08/1759.17	% SZS status GaveUp for HL400432+5.p
4776.08/1759.17	% SZS status Ended for HL400432+5.p
4792.94/1761.37	% SZS status Started for HL400434+4.p
4792.94/1761.37	% SZS status GaveUp for HL400434+4.p
4792.94/1761.37	% SZS status Ended for HL400434+4.p
4807.88/1763.15	% SZS status Started for HL400435+4.p
4807.88/1763.15	% SZS status GaveUp for HL400435+4.p
4807.88/1763.15	% SZS status Ended for HL400435+4.p
4807.88/1763.19	% SZS status Started for HL400434+5.p
4807.88/1763.19	% SZS status GaveUp for HL400434+5.p
4807.88/1763.19	% SZS status Ended for HL400434+5.p
4810.77/1763.69	% SZS status Started for HL400435+5.p
4810.77/1763.69	% SZS status GaveUp for HL400435+5.p
4810.77/1763.69	% SZS status Ended for HL400435+5.p
4832.57/1766.25	% SZS status Started for HL400436+4.p
4832.57/1766.25	% SZS status GaveUp for HL400436+4.p
4832.57/1766.25	% SZS status Ended for HL400436+4.p
4835.82/1766.67	% SZS status Started for HL400436+5.p
4835.82/1766.67	% SZS status GaveUp for HL400436+5.p
4835.82/1766.67	% SZS status Ended for HL400436+5.p
4841.29/1767.32	% SZS status Started for HL400437+4.p
4841.29/1767.32	% SZS status GaveUp for HL400437+4.p
4841.29/1767.32	% SZS status Ended for HL400437+4.p
4841.29/1767.36	% SZS status Started for HL400437+5.p
4841.29/1767.36	% SZS status GaveUp for HL400437+5.p
4841.29/1767.36	% SZS status Ended for HL400437+5.p
4859.47/1769.61	% SZS status Started for HL400438+4.p
4859.47/1769.61	% SZS status GaveUp for HL400438+4.p
4859.47/1769.61	% SZS status Ended for HL400438+4.p
4873.15/1771.37	% SZS status Started for HL400439+4.p
4873.15/1771.37	% SZS status GaveUp for HL400439+4.p
4873.15/1771.37	% SZS status Ended for HL400439+4.p
4873.66/1771.40	% SZS status Started for HL400438+5.p
4873.66/1771.40	% SZS status GaveUp for HL400438+5.p
4873.66/1771.40	% SZS status Ended for HL400438+5.p
4876.83/1771.88	% SZS status Started for HL400439+5.p
4876.83/1771.88	% SZS status GaveUp for HL400439+5.p
4876.83/1771.88	% SZS status Ended for HL400439+5.p
4897.11/1774.42	% SZS status Started for HL400443+4.p
4897.11/1774.42	% SZS status GaveUp for HL400443+4.p
4897.11/1774.42	% SZS status Ended for HL400443+4.p
4900.93/1774.86	% SZS status Started for HL400443+5.p
4900.93/1774.86	% SZS status GaveUp for HL400443+5.p
4900.93/1774.86	% SZS status Ended for HL400443+5.p
4906.07/1775.49	% SZS status Started for HL400444+4.p
4906.07/1775.49	% SZS status GaveUp for HL400444+4.p
4906.07/1775.49	% SZS status Ended for HL400444+4.p
4906.77/1775.61	% SZS status Started for HL400444+5.p
4906.77/1775.61	% SZS status GaveUp for HL400444+5.p
4906.77/1775.61	% SZS status Ended for HL400444+5.p
4925.80/1777.93	% SZS status Started for HL400445+4.p
4925.80/1777.93	% SZS status GaveUp for HL400445+4.p
4925.80/1777.93	% SZS status Ended for HL400445+4.p
4938.69/1779.56	% SZS status Started for HL400445+5.p
4938.69/1779.56	% SZS status GaveUp for HL400445+5.p
4938.69/1779.56	% SZS status Ended for HL400445+5.p
4938.69/1779.57	% SZS status Started for HL400446+4.p
4938.69/1779.57	% SZS status GaveUp for HL400446+4.p
4938.69/1779.57	% SZS status Ended for HL400446+4.p
4942.76/1780.07	% SZS status Started for HL400446+5.p
4942.76/1780.07	% SZS status GaveUp for HL400446+5.p
4942.76/1780.07	% SZS status Ended for HL400446+5.p
4962.77/1782.61	% SZS status Started for HL400447+4.p
4962.77/1782.61	% SZS status GaveUp for HL400447+4.p
4962.77/1782.61	% SZS status Ended for HL400447+4.p
4965.99/1783.06	% SZS status Started for HL400447+5.p
4965.99/1783.06	% SZS status GaveUp for HL400447+5.p
4965.99/1783.06	% SZS status Ended for HL400447+5.p
4972.06/1783.80	% SZS status Started for HL400449+4.p
4972.06/1783.80	% SZS status GaveUp for HL400449+4.p
4972.06/1783.80	% SZS status Ended for HL400449+4.p
4972.26/1783.83	% SZS status Started for HL400449+5.p
4972.26/1783.83	% SZS status GaveUp for HL400449+5.p
4972.26/1783.83	% SZS status Ended for HL400449+5.p
4990.56/1786.08	% SZS status Started for HL400451+4.p
4990.56/1786.08	% SZS status GaveUp for HL400451+4.p
4990.56/1786.08	% SZS status Ended for HL400451+4.p
5001.93/1787.69	% SZS status Started for HL400452+4.p
5001.93/1787.69	% SZS status GaveUp for HL400452+4.p
5001.93/1787.69	% SZS status Ended for HL400452+4.p
5003.88/1787.75	% SZS status Started for HL400451+5.p
5003.88/1787.75	% SZS status GaveUp for HL400451+5.p
5003.88/1787.75	% SZS status Ended for HL400451+5.p
5006.33/1788.27	% SZS status Started for HL400452+5.p
5006.33/1788.27	% SZS status GaveUp for HL400452+5.p
5006.33/1788.27	% SZS status Ended for HL400452+5.p
5027.66/1790.75	% SZS status Started for HL400454+4.p
5027.66/1790.75	% SZS status GaveUp for HL400454+4.p
5027.66/1790.75	% SZS status Ended for HL400454+4.p
5031.05/1791.25	% SZS status Started for HL400454+5.p
5031.05/1791.25	% SZS status GaveUp for HL400454+5.p
5031.05/1791.25	% SZS status Ended for HL400454+5.p
5037.49/1792.03	% SZS status Started for HL400455+5.p
5037.49/1792.03	% SZS status GaveUp for HL400455+5.p
5037.49/1792.03	% SZS status Ended for HL400455+5.p
5037.68/1792.10	% SZS status Started for HL400455+4.p
5037.68/1792.10	% SZS status GaveUp for HL400455+4.p
5037.68/1792.10	% SZS status Ended for HL400455+4.p
5054.53/1794.27	% SZS status Started for HL400456+4.p
5054.53/1794.27	% SZS status GaveUp for HL400456+4.p
5054.53/1794.27	% SZS status Ended for HL400456+4.p
5068.11/1795.88	% SZS status Started for HL400456+5.p
5068.11/1795.88	% SZS status GaveUp for HL400456+5.p
5068.11/1795.88	% SZS status Ended for HL400456+5.p
5069.42/1796.01	% SZS status Started for HL400457+4.p
5069.42/1796.01	% SZS status GaveUp for HL400457+4.p
5069.42/1796.01	% SZS status Ended for HL400457+4.p
5072.15/1796.49	% SZS status Started for HL400457+5.p
5072.15/1796.49	% SZS status GaveUp for HL400457+5.p
5072.15/1796.49	% SZS status Ended for HL400457+5.p
5092.38/1798.91	% SZS status Started for HL400458+4.p
5092.38/1798.91	% SZS status GaveUp for HL400458+4.p
5092.38/1798.91	% SZS status Ended for HL400458+4.p
5096.56/1799.43	% SZS status Started for HL400458+5.p
5096.56/1799.43	% SZS status GaveUp for HL400458+5.p
5096.56/1799.43	% SZS status Ended for HL400458+5.p
5102.09/1800.15	% SZS status Started for HL400459+4.p
5102.09/1800.15	% SZS status GaveUp for HL400459+4.p
5102.09/1800.15	% SZS status Ended for HL400459+4.p
5104.19/1800.36	% SZS status Started for HL400459+5.p
5104.19/1800.36	% SZS status GaveUp for HL400459+5.p
5104.19/1800.36	% SZS status Ended for HL400459+5.p
5120.84/1802.57	% SZS status Started for HL400460+4.p
5120.84/1802.57	% SZS status GaveUp for HL400460+4.p
5120.84/1802.57	% SZS status Ended for HL400460+4.p
5132.80/1804.08	% SZS status Started for HL400460+5.p
5132.80/1804.08	% SZS status GaveUp for HL400460+5.p
5132.80/1804.08	% SZS status Ended for HL400460+5.p
5133.17/1804.15	% SZS status Started for HL400462+4.p
5133.17/1804.15	% SZS status GaveUp for HL400462+4.p
5133.17/1804.15	% SZS status Ended for HL400462+4.p
5138.08/1804.70	% SZS status Started for HL400462+5.p
5138.08/1804.70	% SZS status GaveUp for HL400462+5.p
5138.08/1804.70	% SZS status Ended for HL400462+5.p
5157.40/1807.06	% SZS status Started for HL400463+4.p
5157.40/1807.06	% SZS status GaveUp for HL400463+4.p
5157.40/1807.06	% SZS status Ended for HL400463+4.p
5161.54/1807.62	% SZS status Started for HL400463+5.p
5161.54/1807.62	% SZS status GaveUp for HL400463+5.p
5161.54/1807.62	% SZS status Ended for HL400463+5.p
5167.68/1808.37	% SZS status Started for HL400464+4.p
5167.68/1808.37	% SZS status GaveUp for HL400464+4.p
5167.68/1808.37	% SZS status Ended for HL400464+4.p
5168.44/1808.57	% SZS status Started for HL400464+5.p
5168.44/1808.57	% SZS status GaveUp for HL400464+5.p
5168.44/1808.57	% SZS status Ended for HL400464+5.p
5185.57/1810.71	% SZS status Started for HL400465+4.p
5185.57/1810.71	% SZS status GaveUp for HL400465+4.p
5185.57/1810.71	% SZS status Ended for HL400465+4.p
5199.15/1812.30	% SZS status Started for HL400466+4.p
5199.15/1812.30	% SZS status GaveUp for HL400466+4.p
5199.15/1812.30	% SZS status Ended for HL400466+4.p
5199.76/1812.36	% SZS status Started for HL400465+5.p
5199.76/1812.36	% SZS status GaveUp for HL400465+5.p
5199.76/1812.36	% SZS status Ended for HL400465+5.p
5203.68/1812.90	% SZS status Started for HL400466+5.p
5203.68/1812.90	% SZS status GaveUp for HL400466+5.p
5203.68/1812.90	% SZS status Ended for HL400466+5.p
5223.08/1815.29	% SZS status Started for HL400467+4.p
5223.08/1815.29	% SZS status GaveUp for HL400467+4.p
5223.08/1815.29	% SZS status Ended for HL400467+4.p
5227.85/1815.92	% SZS status Started for HL400467+5.p
5227.85/1815.92	% SZS status GaveUp for HL400467+5.p
5227.85/1815.92	% SZS status Ended for HL400467+5.p
5232.56/1816.50	% SZS status Started for HL400468+4.p
5232.56/1816.50	% SZS status GaveUp for HL400468+4.p
5232.56/1816.50	% SZS status Ended for HL400468+4.p
5233.81/1816.82	% SZS status Started for HL400468+5.p
5233.81/1816.82	% SZS status GaveUp for HL400468+5.p
5233.81/1816.82	% SZS status Ended for HL400468+5.p
5251.22/1818.87	% SZS status Started for HL400469+4.p
5251.22/1818.87	% SZS status GaveUp for HL400469+4.p
5251.22/1818.87	% SZS status Ended for HL400469+4.p
5264.14/1820.50	% SZS status Started for HL400469+5.p
5264.14/1820.50	% SZS status GaveUp for HL400469+5.p
5264.14/1820.50	% SZS status Ended for HL400469+5.p
5265.14/1820.59	% SZS status Started for HL400470+4.p
5265.14/1820.59	% SZS status GaveUp for HL400470+4.p
5265.14/1820.59	% SZS status Ended for HL400470+4.p
5268.91/1821.10	% SZS status Started for HL400470+5.p
5268.91/1821.10	% SZS status GaveUp for HL400470+5.p
5268.91/1821.10	% SZS status Ended for HL400470+5.p
5286.63/1823.43	% SZS status Started for HL400471+4.p
5286.63/1823.43	% SZS status GaveUp for HL400471+4.p
5286.63/1823.43	% SZS status Ended for HL400471+4.p
5293.42/1824.17	% SZS status Started for HL400471+5.p
5293.42/1824.17	% SZS status GaveUp for HL400471+5.p
5293.42/1824.17	% SZS status Ended for HL400471+5.p
5297.73/1824.69	% SZS status Started for HL400472+4.p
5297.73/1824.69	% SZS status GaveUp for HL400472+4.p
5297.73/1824.69	% SZS status Ended for HL400472+4.p
5299.78/1825.05	% SZS status Started for HL400472+5.p
5299.78/1825.05	% SZS status GaveUp for HL400472+5.p
5299.78/1825.05	% SZS status Ended for HL400472+5.p
5316.24/1827.08	% SZS status Started for HL400473+4.p
5316.24/1827.08	% SZS status GaveUp for HL400473+4.p
5316.24/1827.08	% SZS status Ended for HL400473+4.p
5329.53/1828.69	% SZS status Started for HL400473+5.p
5329.53/1828.69	% SZS status GaveUp for HL400473+5.p
5329.53/1828.69	% SZS status Ended for HL400473+5.p
5330.63/1828.84	% SZS status Started for HL400474+4.p
5330.63/1828.84	% SZS status GaveUp for HL400474+4.p
5330.63/1828.84	% SZS status Ended for HL400474+4.p
5334.76/1829.36	% SZS status Started for HL400474+5.p
5334.76/1829.36	% SZS status GaveUp for HL400474+5.p
5334.76/1829.36	% SZS status Ended for HL400474+5.p
5351.73/1831.58	% SZS status Started for HL400475+4.p
5351.73/1831.58	% SZS status GaveUp for HL400475+4.p
5351.73/1831.58	% SZS status Ended for HL400475+4.p
5359.02/1832.37	% SZS status Started for HL400475+5.p
5359.02/1832.37	% SZS status GaveUp for HL400475+5.p
5359.02/1832.37	% SZS status Ended for HL400475+5.p
5362.71/1832.86	% SZS status Started for HL400478+4.p
5362.71/1832.86	% SZS status GaveUp for HL400478+4.p
5362.71/1832.86	% SZS status Ended for HL400478+4.p
5365.23/1833.28	% SZS status Started for HL400478+5.p
5365.23/1833.28	% SZS status GaveUp for HL400478+5.p
5365.23/1833.28	% SZS status Ended for HL400478+5.p
5382.09/1835.27	% SZS status Started for HL400479+4.p
5382.09/1835.27	% SZS status GaveUp for HL400479+4.p
5382.09/1835.27	% SZS status Ended for HL400479+4.p
5395.92/1837.00	% SZS status Started for HL400479+5.p
5395.92/1837.00	% SZS status GaveUp for HL400479+5.p
5395.92/1837.00	% SZS status Ended for HL400479+5.p
5396.24/1837.08	% SZS status Started for HL400480+4.p
5396.24/1837.08	% SZS status GaveUp for HL400480+4.p
5396.24/1837.08	% SZS status Ended for HL400480+4.p
5399.65/1837.55	% SZS status Started for HL400480+5.p
5399.65/1837.55	% SZS status GaveUp for HL400480+5.p
5399.65/1837.55	% SZS status Ended for HL400480+5.p
5417.35/1839.71	% SZS status Started for HL400482+4.p
5417.35/1839.71	% SZS status GaveUp for HL400482+4.p
5417.35/1839.71	% SZS status Ended for HL400482+4.p
5424.02/1840.61	% SZS status Started for HL400482+5.p
5424.02/1840.61	% SZS status GaveUp for HL400482+5.p
5424.02/1840.61	% SZS status Ended for HL400482+5.p
5427.68/1840.99	% SZS status Started for HL400484+4.p
5427.68/1840.99	% SZS status GaveUp for HL400484+4.p
5427.68/1840.99	% SZS status Ended for HL400484+4.p
5431.50/1841.47	% SZS status Started for HL400484+5.p
5431.50/1841.47	% SZS status GaveUp for HL400484+5.p
5431.50/1841.47	% SZS status Ended for HL400484+5.p
5446.61/1843.52	% SZS status Started for HL400485+4.p
5446.61/1843.52	% SZS status GaveUp for HL400485+4.p
5446.61/1843.52	% SZS status Ended for HL400485+4.p
5461.08/1845.22	% SZS status Started for HL400486+4.p
5461.08/1845.22	% SZS status GaveUp for HL400486+4.p
5461.08/1845.22	% SZS status Ended for HL400486+4.p
5461.48/1845.25	% SZS status Started for HL400485+5.p
5461.48/1845.25	% SZS status GaveUp for HL400485+5.p
5461.48/1845.25	% SZS status Ended for HL400485+5.p
5465.39/1845.75	% SZS status Started for HL400486+5.p
5465.39/1845.75	% SZS status GaveUp for HL400486+5.p
5465.39/1845.75	% SZS status Ended for HL400486+5.p
5482.59/1847.92	% SZS status Started for HL400488+4.p
5482.59/1847.92	% SZS status GaveUp for HL400488+4.p
5482.59/1847.92	% SZS status Ended for HL400488+4.p
5489.88/1848.81	% SZS status Started for HL400488+5.p
5489.88/1848.81	% SZS status GaveUp for HL400488+5.p
5489.88/1848.81	% SZS status Ended for HL400488+5.p
5492.10/1849.16	% SZS status Started for HL400489+4.p
5492.10/1849.16	% SZS status GaveUp for HL400489+4.p
5492.10/1849.16	% SZS status Ended for HL400489+4.p
5496.22/1849.66	% SZS status Started for HL400489+5.p
5496.22/1849.66	% SZS status GaveUp for HL400489+5.p
5496.22/1849.66	% SZS status Ended for HL400489+5.p
5512.71/1851.72	% SZS status Started for HL400490+4.p
5512.71/1851.72	% SZS status GaveUp for HL400490+4.p
5512.71/1851.72	% SZS status Ended for HL400490+4.p
5526.53/1853.43	% SZS status Started for HL400490+5.p
5526.53/1853.43	% SZS status GaveUp for HL400490+5.p
5526.53/1853.43	% SZS status Ended for HL400490+5.p
5526.85/1853.48	% SZS status Started for HL400491+4.p
5526.85/1853.48	% SZS status GaveUp for HL400491+4.p
5526.85/1853.48	% SZS status Ended for HL400491+4.p
5531.17/1854.02	% SZS status Started for HL400491+5.p
5531.17/1854.02	% SZS status GaveUp for HL400491+5.p
5531.17/1854.02	% SZS status Ended for HL400491+5.p
5548.41/1856.17	% SZS status Started for HL400492+4.p
5548.41/1856.17	% SZS status GaveUp for HL400492+4.p
5548.41/1856.17	% SZS status Ended for HL400492+4.p
5548.41/1856.18	% SZS status Started for HL400496+4.p
5548.41/1856.18	% SZS status Theorem for HL400496+4.p
5548.41/1856.18	% SZS status Ended for HL400496+4.p
5555.73/1857.10	% SZS status Started for HL400492+5.p
5555.73/1857.10	% SZS status GaveUp for HL400492+5.p
5555.73/1857.10	% SZS status Ended for HL400492+5.p
5555.91/1857.24	% SZS status Started for HL400500+4.p
5555.91/1857.24	% SZS status Theorem for HL400500+4.p
5555.91/1857.24	% SZS status Ended for HL400500+4.p
5557.91/1857.43	% SZS status Started for HL400493+4.p
5557.91/1857.43	% SZS status GaveUp for HL400493+4.p
5557.91/1857.43	% SZS status Ended for HL400493+4.p
5562.01/1857.87	% SZS status Started for HL400493+5.p
5562.01/1857.87	% SZS status GaveUp for HL400493+5.p
5562.01/1857.87	% SZS status Ended for HL400493+5.p
5567.35/1858.54	% SZS status Started for HL400500+5.p
5567.35/1858.54	% SZS status Theorem for HL400500+5.p
5567.35/1858.54	% SZS status Ended for HL400500+5.p
5573.53/1859.41	% SZS status Started for HL400499+4.p
5573.53/1859.41	% SZS status Theorem for HL400499+4.p
5573.53/1859.41	% SZS status Ended for HL400499+4.p
5577.21/1859.98	% SZS status Started for HL400494+4.p
5577.21/1859.98	% SZS status GaveUp for HL400494+4.p
5577.21/1859.98	% SZS status Ended for HL400494+4.p
5591.54/1861.62	% SZS status Started for HL400494+5.p
5591.54/1861.62	% SZS status GaveUp for HL400494+5.p
5591.54/1861.62	% SZS status Ended for HL400494+5.p
5596.50/1862.24	% SZS status Started for HL400496+5.p
5596.50/1862.24	% SZS status GaveUp for HL400496+5.p
5596.50/1862.24	% SZS status Ended for HL400496+5.p
5613.20/1864.39	% SZS status Started for HL400499+5.p
5613.20/1864.39	% SZS status GaveUp for HL400499+5.p
5613.20/1864.39	% SZS status Ended for HL400499+5.p
5622.10/1865.45	% SZS status Started for HL400506+4.p
5622.10/1865.45	% SZS status Theorem for HL400506+4.p
5622.10/1865.45	% SZS status Ended for HL400506+4.p
5623.28/1865.69	% SZS status Started for HL400501+4.p
5623.28/1865.69	% SZS status GaveUp for HL400501+4.p
5623.28/1865.69	% SZS status Ended for HL400501+4.p
5626.96/1866.12	% SZS status Started for HL400501+5.p
5626.96/1866.12	% SZS status GaveUp for HL400501+5.p
5626.96/1866.12	% SZS status Ended for HL400501+5.p
5632.30/1866.78	% SZS status Started for HL400503+4.p
5632.30/1866.78	% SZS status GaveUp for HL400503+4.p
5632.30/1866.78	% SZS status Ended for HL400503+4.p
5639.31/1867.63	% SZS status Started for HL400503+5.p
5639.31/1867.63	% SZS status GaveUp for HL400503+5.p
5639.31/1867.63	% SZS status Ended for HL400503+5.p
5644.80/1868.25	% SZS status Started for HL400504+4.p
5644.80/1868.25	% SZS status GaveUp for HL400504+4.p
5644.80/1868.25	% SZS status Ended for HL400504+4.p
5657.11/1869.84	% SZS status Started for HL400504+5.p
5657.11/1869.84	% SZS status GaveUp for HL400504+5.p
5657.11/1869.84	% SZS status Ended for HL400504+5.p
5679.34/1872.61	% SZS status Started for HL400506+5.p
5679.34/1872.61	% SZS status GaveUp for HL400506+5.p
5679.34/1872.61	% SZS status Ended for HL400506+5.p
5681.26/1872.92	% SZS status Started for HL400509+4.p
5681.26/1872.92	% SZS status Theorem for HL400509+4.p
5681.26/1872.92	% SZS status Ended for HL400509+4.p
5688.24/1873.73	% SZS status Started for HL400507+4.p
5688.24/1873.73	% SZS status GaveUp for HL400507+4.p
5688.24/1873.73	% SZS status Ended for HL400507+4.p
5689.13/1873.90	% SZS status Started for HL400507+5.p
5689.13/1873.90	% SZS status GaveUp for HL400507+5.p
5689.13/1873.90	% SZS status Ended for HL400507+5.p
5698.74/1875.12	% SZS status Started for HL400509+5.p
5698.74/1875.12	% SZS status GaveUp for HL400509+5.p
5698.74/1875.12	% SZS status Ended for HL400509+5.p
5704.83/1875.88	% SZS status Started for HL400510+4.p
5704.83/1875.88	% SZS status GaveUp for HL400510+4.p
5704.83/1875.88	% SZS status Ended for HL400510+4.p
5707.33/1876.17	% SZS status Started for HL400512+4.p
5707.33/1876.17	% SZS status Theorem for HL400512+4.p
5707.33/1876.17	% SZS status Ended for HL400512+4.p
5710.15/1876.46	% SZS status Started for HL400510+5.p
5710.15/1876.46	% SZS status GaveUp for HL400510+5.p
5710.15/1876.46	% SZS status Ended for HL400510+5.p
5711.56/1876.67	% SZS status Started for HL400513+4.p
5711.56/1876.67	% SZS status Theorem for HL400513+4.p
5711.56/1876.67	% SZS status Ended for HL400513+4.p
5721.50/1878.00	% SZS status Started for HL400511+4.p
5721.50/1878.00	% SZS status GaveUp for HL400511+4.p
5721.50/1878.00	% SZS status Ended for HL400511+4.p
5744.85/1880.90	% SZS status Started for HL400511+5.p
5744.85/1880.90	% SZS status GaveUp for HL400511+5.p
5744.85/1880.90	% SZS status Ended for HL400511+5.p
5753.67/1881.99	% SZS status Started for HL400512+5.p
5753.67/1881.99	% SZS status GaveUp for HL400512+5.p
5753.67/1881.99	% SZS status Ended for HL400512+5.p
5764.31/1883.33	% SZS status Started for HL400516+4.p
5764.31/1883.33	% SZS status Theorem for HL400516+4.p
5764.31/1883.33	% SZS status Ended for HL400516+4.p
5765.35/1883.42	% SZS status Started for HL400513+5.p
5765.35/1883.42	% SZS status GaveUp for HL400513+5.p
5765.35/1883.42	% SZS status Ended for HL400513+5.p
5770.70/1884.08	% SZS status Started for HL400515+4.p
5770.70/1884.08	% SZS status GaveUp for HL400515+4.p
5770.70/1884.08	% SZS status Ended for HL400515+4.p
5771.92/1884.37	% SZS status Started for HL400515+5.p
5771.92/1884.37	% SZS status GaveUp for HL400515+5.p
5771.92/1884.37	% SZS status Ended for HL400515+5.p
5776.66/1884.87	% SZS status Started for HL400516+5.p
5776.66/1884.87	% SZS status GaveUp for HL400516+5.p
5776.66/1884.87	% SZS status Ended for HL400516+5.p
5787.05/1886.15	% SZS status Started for HL400517+4.p
5787.05/1886.15	% SZS status GaveUp for HL400517+4.p
5787.05/1886.15	% SZS status Ended for HL400517+4.p
5811.38/1889.21	% SZS status Started for HL400517+5.p
5811.38/1889.21	% SZS status GaveUp for HL400517+5.p
5811.38/1889.21	% SZS status Ended for HL400517+5.p
5819.96/1890.26	% SZS status Started for HL400518+4.p
5819.96/1890.26	% SZS status GaveUp for HL400518+4.p
5819.96/1890.26	% SZS status Ended for HL400518+4.p
5830.67/1891.61	% SZS status Started for HL400518+5.p
5830.67/1891.61	% SZS status GaveUp for HL400518+5.p
5830.67/1891.61	% SZS status Ended for HL400518+5.p
5830.67/1891.63	% SZS status Started for HL400519+4.p
5830.67/1891.63	% SZS status GaveUp for HL400519+4.p
5830.67/1891.63	% SZS status Ended for HL400519+4.p
5836.11/1892.31	% SZS status Started for HL400519+5.p
5836.11/1892.31	% SZS status GaveUp for HL400519+5.p
5836.11/1892.31	% SZS status Ended for HL400519+5.p
5837.56/1892.58	% SZS status Started for HL400521+4.p
5837.56/1892.58	% SZS status GaveUp for HL400521+4.p
5837.56/1892.58	% SZS status Ended for HL400521+4.p
5842.25/1893.08	% SZS status Started for HL400521+5.p
5842.25/1893.08	% SZS status GaveUp for HL400521+5.p
5842.25/1893.08	% SZS status Ended for HL400521+5.p
5852.13/1894.33	% SZS status Started for HL400522+4.p
5852.13/1894.33	% SZS status GaveUp for HL400522+4.p
5852.13/1894.33	% SZS status Ended for HL400522+4.p
5871.42/1896.87	% SZS status Started for HL400524+4.p
5871.42/1896.87	% SZS status Theorem for HL400524+4.p
5871.42/1896.87	% SZS status Ended for HL400524+4.p
5877.01/1897.53	% SZS status Started for HL400522+5.p
5877.01/1897.53	% SZS status GaveUp for HL400522+5.p
5877.01/1897.53	% SZS status Ended for HL400522+5.p
5884.36/1898.39	% SZS status Started for HL400523+4.p
5884.36/1898.39	% SZS status GaveUp for HL400523+4.p
5884.36/1898.39	% SZS status Ended for HL400523+4.p
5894.88/1899.80	% SZS status Started for HL400526+4.p
5894.88/1899.80	% SZS status Theorem for HL400526+4.p
5894.88/1899.80	% SZS status Ended for HL400526+4.p
5895.58/1899.89	% SZS status Started for HL400523+5.p
5895.58/1899.89	% SZS status GaveUp for HL400523+5.p
5895.58/1899.89	% SZS status Ended for HL400523+5.p
5901.44/1900.52	% SZS status Started for HL400524+5.p
5901.44/1900.52	% SZS status GaveUp for HL400524+5.p
5901.44/1900.52	% SZS status Ended for HL400524+5.p
5903.61/1900.86	% SZS status Started for HL400525+4.p
5903.61/1900.86	% SZS status GaveUp for HL400525+4.p
5903.61/1900.86	% SZS status Ended for HL400525+4.p
5907.59/1901.29	% SZS status Started for HL400525+5.p
5907.59/1901.29	% SZS status GaveUp for HL400525+5.p
5907.59/1901.29	% SZS status Ended for HL400525+5.p
5928.52/1903.98	% SZS status Started for HL400528+4.p
5928.52/1903.98	% SZS status Theorem for HL400528+4.p
5928.52/1903.98	% SZS status Ended for HL400528+4.p
5937.37/1905.07	% SZS status Started for HL400526+5.p
5937.37/1905.07	% SZS status GaveUp for HL400526+5.p
5937.37/1905.07	% SZS status Ended for HL400526+5.p
5950.49/1906.67	% SZS status Started for HL400528+5.p
5950.49/1906.67	% SZS status GaveUp for HL400528+5.p
5950.49/1906.67	% SZS status Ended for HL400528+5.p
5961.42/1908.04	% SZS status Started for HL400530+4.p
5961.42/1908.04	% SZS status GaveUp for HL400530+4.p
5961.42/1908.04	% SZS status Ended for HL400530+4.p
5961.88/1908.14	% SZS status Started for HL400530+5.p
5961.88/1908.14	% SZS status GaveUp for HL400530+5.p
5961.88/1908.14	% SZS status Ended for HL400530+5.p
5962.14/1908.24	% SZS status Started for HL400534+4.p
5962.14/1908.24	% SZS status Theorem for HL400534+4.p
5962.14/1908.24	% SZS status Ended for HL400534+4.p
5967.05/1908.75	% SZS status Started for HL400531+4.p
5967.05/1908.75	% SZS status GaveUp for HL400531+4.p
5967.05/1908.75	% SZS status Ended for HL400531+4.p
5969.58/1909.07	% SZS status Started for HL400531+5.p
5969.58/1909.07	% SZS status GaveUp for HL400531+5.p
5969.58/1909.07	% SZS status Ended for HL400531+5.p
5971.58/1909.52	% SZS status Started for HL400532+4.p
5971.58/1909.52	% SZS status GaveUp for HL400532+4.p
5971.58/1909.52	% SZS status Ended for HL400532+4.p
5994.37/1912.19	% SZS status Started for HL400532+5.p
5994.37/1912.19	% SZS status GaveUp for HL400532+5.p
5994.37/1912.19	% SZS status Ended for HL400532+5.p
6002.47/1913.25	% SZS status Started for HL400533+4.p
6002.47/1913.25	% SZS status GaveUp for HL400533+4.p
6002.47/1913.25	% SZS status Ended for HL400533+4.p
6016.83/1915.00	% SZS status Started for HL400533+5.p
6016.83/1915.00	% SZS status GaveUp for HL400533+5.p
6016.83/1915.00	% SZS status Ended for HL400533+5.p
6028.23/1916.43	% SZS status Started for HL400534+5.p
6028.23/1916.43	% SZS status GaveUp for HL400534+5.p
6028.23/1916.43	% SZS status Ended for HL400534+5.p
6028.23/1916.43	% SZS status Started for HL400535+4.p
6028.23/1916.43	% SZS status GaveUp for HL400535+4.p
6028.23/1916.43	% SZS status Ended for HL400535+4.p
6033.01/1917.06	% SZS status Started for HL400535+5.p
6033.01/1917.06	% SZS status GaveUp for HL400535+5.p
6033.01/1917.06	% SZS status Ended for HL400535+5.p
6034.48/1917.27	% SZS status Started for HL400536+4.p
6034.48/1917.27	% SZS status GaveUp for HL400536+4.p
6034.48/1917.27	% SZS status Ended for HL400536+4.p
6038.64/1917.77	% SZS status Started for HL400536+5.p
6038.64/1917.77	% SZS status GaveUp for HL400536+5.p
6038.64/1917.77	% SZS status Ended for HL400536+5.p
6059.28/1920.37	% SZS status Started for HL400537+4.p
6059.28/1920.37	% SZS status GaveUp for HL400537+4.p
6059.28/1920.37	% SZS status Ended for HL400537+4.p
6068.15/1921.45	% SZS status Started for HL400537+5.p
6068.15/1921.45	% SZS status GaveUp for HL400537+5.p
6068.15/1921.45	% SZS status Ended for HL400537+5.p
6082.23/1923.21	% SZS status Started for HL400538+4.p
6082.23/1923.21	% SZS status GaveUp for HL400538+4.p
6082.23/1923.21	% SZS status Ended for HL400538+4.p
6094.39/1924.73	% SZS status Started for HL400538+5.p
6094.39/1924.73	% SZS status GaveUp for HL400538+5.p
6094.39/1924.73	% SZS status Ended for HL400538+5.p
6094.61/1924.76	% SZS status Started for HL400540+4.p
6094.61/1924.76	% SZS status GaveUp for HL400540+4.p
6094.61/1924.76	% SZS status Ended for HL400540+4.p
6098.82/1925.34	% SZS status Started for HL400540+5.p
6098.82/1925.34	% SZS status GaveUp for HL400540+5.p
6098.82/1925.34	% SZS status Ended for HL400540+5.p
6100.52/1925.55	% SZS status Started for HL400541+4.p
6100.52/1925.55	% SZS status GaveUp for HL400541+4.p
6100.52/1925.55	% SZS status Ended for HL400541+4.p
6103.87/1925.98	% SZS status Started for HL400541+5.p
6103.87/1925.98	% SZS status GaveUp for HL400541+5.p
6103.87/1925.98	% SZS status Ended for HL400541+5.p
6124.85/1928.58	% SZS status Started for HL400543+4.p
6124.85/1928.58	% SZS status GaveUp for HL400543+4.p
6124.85/1928.58	% SZS status Ended for HL400543+4.p
6127.31/1929.01	% SZS status Started for HL400548+4.p
6127.31/1929.01	% SZS status Theorem for HL400548+4.p
6127.31/1929.01	% SZS status Ended for HL400548+4.p
6132.61/1929.68	% SZS status Started for HL400543+5.p
6132.61/1929.68	% SZS status GaveUp for HL400543+5.p
6132.61/1929.68	% SZS status Ended for HL400543+5.p
6147.66/1931.43	% SZS status Started for HL400545+4.p
6147.66/1931.43	% SZS status GaveUp for HL400545+4.p
6147.66/1931.43	% SZS status Ended for HL400545+4.p
6159.54/1932.98	% SZS status Started for HL400546+4.p
6159.54/1932.98	% SZS status GaveUp for HL400546+4.p
6159.54/1932.98	% SZS status Ended for HL400546+4.p
6159.54/1933.01	% SZS status Started for HL400545+5.p
6159.54/1933.01	% SZS status GaveUp for HL400545+5.p
6159.54/1933.01	% SZS status Ended for HL400545+5.p
6164.79/1933.61	% SZS status Started for HL400546+5.p
6164.79/1933.61	% SZS status GaveUp for HL400546+5.p
6164.79/1933.61	% SZS status Ended for HL400546+5.p
6165.82/1933.82	% SZS status Started for HL400547+4.p
6165.82/1933.82	% SZS status GaveUp for HL400547+4.p
6165.82/1933.82	% SZS status Ended for HL400547+4.p
6167.57/1934.20	% SZS status Started for HL400547+5.p
6167.57/1934.20	% SZS status GaveUp for HL400547+5.p
6167.57/1934.20	% SZS status Ended for HL400547+5.p
6181.95/1935.80	% SZS status Started for HL400551+4.p
6181.95/1935.80	% SZS status Theorem for HL400551+4.p
6181.95/1935.80	% SZS status Ended for HL400551+4.p
6186.97/1936.44	% SZS status Started for HL400553+4.p
6186.97/1936.44	% SZS status Theorem for HL400553+4.p
6186.97/1936.44	% SZS status Ended for HL400553+4.p
6194.27/1937.29	% SZS status Started for HL400548+5.p
6194.27/1937.29	% SZS status GaveUp for HL400548+5.p
6194.27/1937.29	% SZS status Ended for HL400548+5.p
6197.69/1937.88	% SZS status Started for HL400550+4.p
6197.69/1937.88	% SZS status GaveUp for HL400550+4.p
6197.69/1937.88	% SZS status Ended for HL400550+4.p
6212.07/1939.62	% SZS status Started for HL400554+4.p
6212.07/1939.62	% SZS status Theorem for HL400554+4.p
6212.07/1939.62	% SZS status Ended for HL400554+4.p
6213.33/1939.65	% SZS status Started for HL400550+5.p
6213.33/1939.65	% SZS status GaveUp for HL400550+5.p
6213.33/1939.65	% SZS status Ended for HL400550+5.p
6223.65/1941.06	% SZS status Started for HL400555+4.p
6223.65/1941.06	% SZS status Theorem for HL400555+4.p
6223.65/1941.06	% SZS status Ended for HL400555+4.p
6225.25/1941.29	% SZS status Started for HL400551+5.p
6225.25/1941.29	% SZS status GaveUp for HL400551+5.p
6225.25/1941.29	% SZS status Ended for HL400551+5.p
6225.86/1941.46	% SZS status Started for HL400557+4.p
6225.86/1941.46	% SZS status Theorem for HL400557+4.p
6225.86/1941.46	% SZS status Ended for HL400557+4.p
6230.12/1941.86	% SZS status Started for HL400552+4.p
6230.12/1941.86	% SZS status GaveUp for HL400552+4.p
6230.12/1941.86	% SZS status Ended for HL400552+4.p
6231.38/1942.03	% SZS status Started for HL400558+4.p
6231.38/1942.03	% SZS status Theorem for HL400558+4.p
6231.38/1942.03	% SZS status Ended for HL400558+4.p
6231.84/1942.11	% SZS status Started for HL400552+5.p
6231.84/1942.11	% SZS status GaveUp for HL400552+5.p
6231.84/1942.11	% SZS status Ended for HL400552+5.p
6238.70/1942.88	% SZS status Started for HL400556+4.p
6238.70/1942.88	% SZS status Theorem for HL400556+4.p
6238.70/1942.88	% SZS status Ended for HL400556+4.p
6247.49/1944.00	% SZS status Started for HL400553+5.p
6247.49/1944.00	% SZS status GaveUp for HL400553+5.p
6247.49/1944.00	% SZS status Ended for HL400553+5.p
6259.62/1945.48	% SZS status Started for HL400559+4.p
6259.62/1945.48	% SZS status Theorem for HL400559+4.p
6259.62/1945.48	% SZS status Ended for HL400559+4.p
6259.62/1945.50	% SZS status Started for HL400554+5.p
6259.62/1945.50	% SZS status GaveUp for HL400554+5.p
6259.62/1945.50	% SZS status Ended for HL400554+5.p
6278.06/1947.95	% SZS status Started for HL400555+5.p
6278.06/1947.95	% SZS status GaveUp for HL400555+5.p
6278.06/1947.95	% SZS status Ended for HL400555+5.p
6289.33/1949.30	% SZS status Started for HL400556+5.p
6289.33/1949.30	% SZS status GaveUp for HL400556+5.p
6289.33/1949.30	% SZS status Ended for HL400556+5.p
6292.53/1949.69	% SZS status Started for HL400557+5.p
6292.53/1949.69	% SZS status GaveUp for HL400557+5.p
6292.53/1949.69	% SZS status Ended for HL400557+5.p
6297.13/1950.24	% SZS status Started for HL400558+5.p
6297.13/1950.24	% SZS status GaveUp for HL400558+5.p
6297.13/1950.24	% SZS status Ended for HL400558+5.p
6304.70/1951.14	% SZS status Started for HL400559+5.p
6304.70/1951.14	% SZS status GaveUp for HL400559+5.p
6304.70/1951.14	% SZS status Ended for HL400559+5.p
6313.18/1952.21	% SZS status Started for HL400560+4.p
6313.18/1952.21	% SZS status GaveUp for HL400560+4.p
6313.18/1952.21	% SZS status Ended for HL400560+4.p
6314.49/1952.50	% SZS status Started for HL400562+4.p
6314.49/1952.50	% SZS status Theorem for HL400562+4.p
6314.49/1952.50	% SZS status Ended for HL400562+4.p
6322.75/1953.44	% SZS status Started for HL400563+4.p
6322.75/1953.44	% SZS status Theorem for HL400563+4.p
6322.75/1953.44	% SZS status Ended for HL400563+4.p
6324.15/1953.69	% SZS status Started for HL400561+4.p
6324.15/1953.69	% SZS status GaveUp for HL400561+4.p
6324.15/1953.69	% SZS status Ended for HL400561+4.p
6324.53/1953.75	% SZS status Started for HL400560+5.p
6324.53/1953.75	% SZS status GaveUp for HL400560+5.p
6324.53/1953.75	% SZS status Ended for HL400560+5.p
6339.68/1955.57	% SZS status Started for HL400565+4.p
6339.68/1955.57	% SZS status Theorem for HL400565+4.p
6339.68/1955.57	% SZS status Ended for HL400565+4.p
6345.09/1956.25	% SZS status Started for HL400561+5.p
6345.09/1956.25	% SZS status GaveUp for HL400561+5.p
6345.09/1956.25	% SZS status Ended for HL400561+5.p
6358.70/1957.99	% SZS status Started for HL400562+5.p
6358.70/1957.99	% SZS status GaveUp for HL400562+5.p
6358.70/1957.99	% SZS status Ended for HL400562+5.p
6369.58/1959.41	% SZS status Started for HL400563+5.p
6369.58/1959.41	% SZS status GaveUp for HL400563+5.p
6369.58/1959.41	% SZS status Ended for HL400563+5.p
6381.15/1960.75	% SZS status Started for HL400565+5.p
6381.15/1960.75	% SZS status GaveUp for HL400565+5.p
6381.15/1960.75	% SZS status Ended for HL400565+5.p
6388.07/1961.66	% SZS status Started for HL400566+4.p
6388.07/1961.66	% SZS status GaveUp for HL400566+4.p
6388.07/1961.66	% SZS status Ended for HL400566+4.p
6389.08/1961.84	% SZS status Started for HL400573+4.p
6389.08/1961.84	% SZS status Theorem for HL400573+4.p
6389.08/1961.84	% SZS status Ended for HL400573+4.p
6390.43/1961.91	% SZS status Started for HL400566+5.p
6390.43/1961.91	% SZS status GaveUp for HL400566+5.p
6390.43/1961.91	% SZS status Ended for HL400566+5.p
6390.88/1962.02	% SZS status Started for HL400567+4.p
6390.88/1962.02	% SZS status GaveUp for HL400567+4.p
6390.88/1962.02	% SZS status Ended for HL400567+4.p
6398.41/1962.93	% SZS status Started for HL400574+4.p
6398.41/1962.93	% SZS status Theorem for HL400574+4.p
6398.41/1962.93	% SZS status Ended for HL400574+4.p
6405.74/1963.83	% SZS status Started for HL400567+5.p
6405.74/1963.83	% SZS status GaveUp for HL400567+5.p
6405.74/1963.83	% SZS status Ended for HL400567+5.p
6410.64/1964.44	% SZS status Started for HL400568+4.p
6410.64/1964.44	% SZS status GaveUp for HL400568+4.p
6410.64/1964.44	% SZS status Ended for HL400568+4.p
6423.44/1966.25	% SZS status Started for HL400568+5.p
6423.44/1966.25	% SZS status GaveUp for HL400568+5.p
6423.44/1966.25	% SZS status Ended for HL400568+5.p
6435.93/1967.64	% SZS status Started for HL400572+4.p
6435.93/1967.64	% SZS status GaveUp for HL400572+4.p
6435.93/1967.64	% SZS status Ended for HL400572+4.p
6446.08/1969.00	% SZS status Started for HL400572+5.p
6446.08/1969.00	% SZS status GaveUp for HL400572+5.p
6446.08/1969.00	% SZS status Ended for HL400572+5.p
6455.20/1970.10	% SZS status Started for HL400573+5.p
6455.20/1970.10	% SZS status GaveUp for HL400573+5.p
6455.20/1970.10	% SZS status Ended for HL400573+5.p
6456.57/1970.27	% SZS status Started for HL400574+5.p
6456.57/1970.27	% SZS status GaveUp for HL400574+5.p
6456.57/1970.27	% SZS status Ended for HL400574+5.p
6464.76/1971.30	% SZS status Started for HL400575+4.p
6464.76/1971.30	% SZS status GaveUp for HL400575+4.p
6464.76/1971.30	% SZS status Ended for HL400575+4.p
6471.52/1972.15	% SZS status Started for HL400575+5.p
6471.52/1972.15	% SZS status GaveUp for HL400575+5.p
6471.52/1972.15	% SZS status Ended for HL400575+5.p
6475.53/1972.71	% SZS status Started for HL400576+4.p
6475.53/1972.71	% SZS status GaveUp for HL400576+4.p
6475.53/1972.71	% SZS status Ended for HL400576+4.p
6482.61/1973.55	% SZS status Started for HL400579+4.p
6482.61/1973.55	% SZS status Theorem for HL400579+4.p
6482.61/1973.55	% SZS status Ended for HL400579+4.p
6490.53/1974.49	% SZS status Started for HL400576+5.p
6490.53/1974.49	% SZS status GaveUp for HL400576+5.p
6490.53/1974.49	% SZS status Ended for HL400576+5.p
6501.06/1975.90	% SZS status Started for HL400577+4.p
6501.06/1975.90	% SZS status GaveUp for HL400577+4.p
6501.06/1975.90	% SZS status Ended for HL400577+4.p
6512.52/1977.25	% SZS status Started for HL400577+5.p
6512.52/1977.25	% SZS status GaveUp for HL400577+5.p
6512.52/1977.25	% SZS status Ended for HL400577+5.p
6519.37/1978.25	% SZS status Started for HL400578+4.p
6519.37/1978.25	% SZS status GaveUp for HL400578+4.p
6519.37/1978.25	% SZS status Ended for HL400578+4.p
6522.90/1978.60	% SZS status Started for HL400578+5.p
6522.90/1978.60	% SZS status GaveUp for HL400578+5.p
6522.90/1978.60	% SZS status Ended for HL400578+5.p
6537.25/1980.45	% SZS status Started for HL400579+5.p
6537.25/1980.45	% SZS status GaveUp for HL400579+5.p
6537.25/1980.45	% SZS status Ended for HL400579+5.p
6540.88/1980.87	% SZS status Started for HL400580+4.p
6540.88/1980.87	% SZS status GaveUp for HL400580+4.p
6540.88/1980.87	% SZS status Ended for HL400580+4.p
6549.03/1981.89	% SZS status Started for HL400580+5.p
6549.03/1981.89	% SZS status GaveUp for HL400580+5.p
6549.03/1981.89	% SZS status Ended for HL400580+5.p
6555.02/1982.69	% SZS status Started for HL400581+4.p
6555.02/1982.69	% SZS status GaveUp for HL400581+4.p
6555.02/1982.69	% SZS status Ended for HL400581+4.p
6567.40/1984.17	% SZS status Started for HL400581+5.p
6567.40/1984.17	% SZS status GaveUp for HL400581+5.p
6567.40/1984.17	% SZS status Ended for HL400581+5.p
6577.81/1985.50	% SZS status Started for HL400582+4.p
6577.81/1985.50	% SZS status GaveUp for HL400582+4.p
6577.81/1985.50	% SZS status Ended for HL400582+4.p
6586.33/1986.52	% SZS status Started for HL400582+5.p
6586.33/1986.52	% SZS status GaveUp for HL400582+5.p
6586.33/1986.52	% SZS status Ended for HL400582+5.p
6587.67/1986.82	% SZS status Started for HL400584+4.p
6587.67/1986.82	% SZS status GaveUp for HL400584+4.p
6587.67/1986.82	% SZS status Ended for HL400584+4.p
6598.67/1988.13	% SZS status Started for HL400589+4.p
6598.67/1988.13	% SZS status Theorem for HL400589+4.p
6598.67/1988.13	% SZS status Ended for HL400589+4.p
6603.10/1988.69	% SZS status Started for HL400584+5.p
6603.10/1988.69	% SZS status GaveUp for HL400584+5.p
6603.10/1988.69	% SZS status Ended for HL400584+5.p
6606.11/1989.04	% SZS status Started for HL400585+4.p
6606.11/1989.04	% SZS status GaveUp for HL400585+4.p
6606.11/1989.04	% SZS status Ended for HL400585+4.p
6613.42/1989.94	% SZS status Started for HL400590+4.p
6613.42/1989.94	% SZS status Theorem for HL400590+4.p
6613.42/1989.94	% SZS status Ended for HL400590+4.p
6614.99/1990.17	% SZS status Started for HL400585+5.p
6614.99/1990.17	% SZS status GaveUp for HL400585+5.p
6614.99/1990.17	% SZS status Ended for HL400585+5.p
6620.79/1990.90	% SZS status Started for HL400587+4.p
6620.79/1990.90	% SZS status GaveUp for HL400587+4.p
6620.79/1990.90	% SZS status Ended for HL400587+4.p
6632.73/1992.44	% SZS status Started for HL400587+5.p
6632.73/1992.44	% SZS status GaveUp for HL400587+5.p
6632.73/1992.44	% SZS status Ended for HL400587+5.p
6633.25/1992.47	% SZS status Started for HL400591+4.p
6633.25/1992.47	% SZS status Theorem for HL400591+4.p
6633.25/1992.47	% SZS status Ended for HL400591+4.p
6633.81/1992.67	% SZS status Started for HL400593+4.p
6633.81/1992.67	% SZS status Theorem for HL400593+4.p
6633.81/1992.67	% SZS status Ended for HL400593+4.p
6642.36/1993.70	% SZS status Started for HL400588+4.p
6642.36/1993.70	% SZS status GaveUp for HL400588+4.p
6642.36/1993.70	% SZS status Ended for HL400588+4.p
6645.45/1994.03	% SZS status Started for HL400593+5.p
6645.45/1994.03	% SZS status Theorem for HL400593+5.p
6645.45/1994.03	% SZS status Ended for HL400593+5.p
6650.99/1994.77	% SZS status Started for HL400588+5.p
6650.99/1994.77	% SZS status GaveUp for HL400588+5.p
6650.99/1994.77	% SZS status Ended for HL400588+5.p
6664.63/1996.50	% SZS status Started for HL400589+5.p
6664.63/1996.50	% SZS status GaveUp for HL400589+5.p
6664.63/1996.50	% SZS status Ended for HL400589+5.p
6672.57/1997.41	% SZS status Started for HL400590+5.p
6672.57/1997.41	% SZS status GaveUp for HL400590+5.p
6672.57/1997.41	% SZS status Ended for HL400590+5.p
6680.58/1998.43	% SZS status Started for HL400591+5.p
6680.58/1998.43	% SZS status GaveUp for HL400591+5.p
6680.58/1998.43	% SZS status Ended for HL400591+5.p
6686.15/1999.10	% SZS status Started for HL400592+4.p
6686.15/1999.10	% SZS status GaveUp for HL400592+4.p
6686.15/1999.10	% SZS status Ended for HL400592+4.p
6699.07/2000.71	% SZS status Started for HL400592+5.p
6699.07/2000.71	% SZS status GaveUp for HL400592+5.p
6699.07/2000.71	% SZS status Ended for HL400592+5.p
6708.22/2002.02	% SZS status Started for HL400594+4.p
6708.22/2002.02	% SZS status GaveUp for HL400594+4.p
6708.22/2002.02	% SZS status Ended for HL400594+4.p
6711.51/2002.27	% SZS status Started for HL400594+5.p
6711.51/2002.27	% SZS status GaveUp for HL400594+5.p
6711.51/2002.27	% SZS status Ended for HL400594+5.p
6716.12/2002.95	% SZS status Started for HL400595+4.p
6716.12/2002.95	% SZS status GaveUp for HL400595+4.p
6716.12/2002.95	% SZS status Ended for HL400595+4.p
6731.08/2004.79	% SZS status Started for HL400595+5.p
6731.08/2004.79	% SZS status GaveUp for HL400595+5.p
6731.08/2004.79	% SZS status Ended for HL400595+5.p
6738.24/2005.62	% SZS status Started for HL400596+4.p
6738.24/2005.62	% SZS status GaveUp for HL400596+4.p
6738.24/2005.62	% SZS status Ended for HL400596+4.p
6746.86/2006.68	% SZS status Started for HL400596+5.p
6746.86/2006.68	% SZS status GaveUp for HL400596+5.p
6746.86/2006.68	% SZS status Ended for HL400596+5.p
6751.60/2007.30	% SZS status Started for HL400597+4.p
6751.60/2007.30	% SZS status GaveUp for HL400597+4.p
6751.60/2007.30	% SZS status Ended for HL400597+4.p
6765.43/2009.04	% SZS status Started for HL400597+5.p
6765.43/2009.04	% SZS status GaveUp for HL400597+5.p
6765.43/2009.04	% SZS status Ended for HL400597+5.p
6774.33/2010.22	% SZS status Started for HL400598+4.p
6774.33/2010.22	% SZS status GaveUp for HL400598+4.p
6774.33/2010.22	% SZS status Ended for HL400598+4.p
6778.19/2010.67	% SZS status Started for HL400598+5.p
6778.19/2010.67	% SZS status GaveUp for HL400598+5.p
6778.19/2010.67	% SZS status Ended for HL400598+5.p
6781.04/2011.12	% SZS status Started for HL400599+4.p
6781.04/2011.12	% SZS status GaveUp for HL400599+4.p
6781.04/2011.12	% SZS status Ended for HL400599+4.p
6797.07/2013.08	% SZS status Started for HL400599+5.p
6797.07/2013.08	% SZS status GaveUp for HL400599+5.p
6797.07/2013.08	% SZS status Ended for HL400599+5.p
6803.93/2013.87	% SZS status Started for HL400600+4.p
6803.93/2013.87	% SZS status GaveUp for HL400600+4.p
6803.93/2013.87	% SZS status Ended for HL400600+4.p
6805.59/2014.14	% SZS status Started for HL400605+4.p
6805.59/2014.14	% SZS status Theorem for HL400605+4.p
6805.59/2014.14	% SZS status Ended for HL400605+4.p
6812.29/2014.97	% SZS status Started for HL400600+5.p
6812.29/2014.97	% SZS status GaveUp for HL400600+5.p
6812.29/2014.97	% SZS status Ended for HL400600+5.p
6815.39/2015.46	% SZS status Started for HL400601+4.p
6815.39/2015.46	% SZS status GaveUp for HL400601+4.p
6815.39/2015.46	% SZS status Ended for HL400601+4.p
6817.58/2015.58	% SZS status Started for HL400605+5.p
6817.58/2015.58	% SZS status Theorem for HL400605+5.p
6817.58/2015.58	% SZS status Ended for HL400605+5.p
6823.62/2016.41	% SZS status Started for HL400604+4.p
6823.62/2016.41	% SZS status Theorem for HL400604+4.p
6823.62/2016.41	% SZS status Ended for HL400604+4.p
6830.80/2017.31	% SZS status Started for HL400601+5.p
6830.80/2017.31	% SZS status GaveUp for HL400601+5.p
6830.80/2017.31	% SZS status Ended for HL400601+5.p
6835.31/2017.83	% SZS status Started for HL400607+5.p
6835.31/2017.83	% SZS status Theorem for HL400607+5.p
6835.31/2017.83	% SZS status Ended for HL400607+5.p
6840.33/2018.46	% SZS status Started for HL400602+4.p
6840.33/2018.46	% SZS status GaveUp for HL400602+4.p
6840.33/2018.46	% SZS status Ended for HL400602+4.p
6844.94/2019.08	% SZS status Started for HL400602+5.p
6844.94/2019.08	% SZS status GaveUp for HL400602+5.p
6844.94/2019.08	% SZS status Ended for HL400602+5.p
6863.35/2021.33	% SZS status Started for HL400604+5.p
6863.35/2021.33	% SZS status GaveUp for HL400604+5.p
6863.35/2021.33	% SZS status Ended for HL400604+5.p
6864.66/2021.50	% SZS status Started for HL400611+4.p
6864.66/2021.50	% SZS status Theorem for HL400611+4.p
6864.66/2021.50	% SZS status Ended for HL400611+4.p
6873.29/2022.63	% SZS status Started for HL400607+4.p
6873.29/2022.63	% SZS status Theorem for HL400607+4.p
6873.29/2022.63	% SZS status Ended for HL400607+4.p
6874.56/2022.92	% SZS status Started for HL400611+5.p
6874.56/2022.92	% SZS status Theorem for HL400611+5.p
6874.56/2022.92	% SZS status Ended for HL400611+5.p
6877.83/2023.17	% SZS status Started for HL400606+4.p
6877.83/2023.17	% SZS status GaveUp for HL400606+4.p
6877.83/2023.17	% SZS status Ended for HL400606+4.p
6882.20/2023.72	% SZS status Started for HL400606+5.p
6882.20/2023.72	% SZS status GaveUp for HL400606+5.p
6882.20/2023.72	% SZS status Ended for HL400606+5.p
6896.16/2025.53	% SZS status Started for HL400608+4.p
6896.16/2025.53	% SZS status GaveUp for HL400608+4.p
6896.16/2025.53	% SZS status Ended for HL400608+4.p
6900.61/2026.15	% SZS status Started for HL400608+5.p
6900.61/2026.15	% SZS status GaveUp for HL400608+5.p
6900.61/2026.15	% SZS status Ended for HL400608+5.p
6905.63/2026.71	% SZS status Started for HL400610+4.p
6905.63/2026.71	% SZS status GaveUp for HL400610+4.p
6905.63/2026.71	% SZS status Ended for HL400610+4.p
6911.63/2027.42	% SZS status Started for HL400610+5.p
6911.63/2027.42	% SZS status GaveUp for HL400610+5.p
6911.63/2027.42	% SZS status Ended for HL400610+5.p
6938.82/2030.89	% SZS status Started for HL400613+4.p
6938.82/2030.89	% SZS status GaveUp for HL400613+4.p
6938.82/2030.89	% SZS status Ended for HL400613+4.p
6942.20/2031.25	% SZS status Started for HL400613+5.p
6942.20/2031.25	% SZS status GaveUp for HL400613+5.p
6942.20/2031.25	% SZS status Ended for HL400613+5.p
6942.72/2031.34	% SZS status Started for HL400615+4.p
6942.72/2031.34	% SZS status GaveUp for HL400615+4.p
6942.72/2031.34	% SZS status Ended for HL400615+4.p
6948.23/2031.98	% SZS status Started for HL400615+5.p
6948.23/2031.98	% SZS status GaveUp for HL400615+5.p
6948.23/2031.98	% SZS status Ended for HL400615+5.p
6961.20/2033.70	% SZS status Started for HL400616+4.p
6961.20/2033.70	% SZS status GaveUp for HL400616+4.p
6961.20/2033.70	% SZS status Ended for HL400616+4.p
6961.92/2033.82	% SZS status Started for HL400619+4.p
6961.92/2033.82	% SZS status Theorem for HL400619+4.p
6961.92/2033.82	% SZS status Ended for HL400619+4.p
6967.90/2034.46	% SZS status Started for HL400616+5.p
6967.90/2034.46	% SZS status GaveUp for HL400616+5.p
6967.90/2034.46	% SZS status Ended for HL400616+5.p
6972.56/2035.03	% SZS status Started for HL400617+4.p
6972.56/2035.03	% SZS status GaveUp for HL400617+4.p
6972.56/2035.03	% SZS status Ended for HL400617+4.p
6973.21/2035.13	% SZS status Started for HL400621+4.p
6973.21/2035.13	% SZS status Theorem for HL400621+4.p
6973.21/2035.13	% SZS status Ended for HL400621+4.p
6978.45/2035.78	% SZS status Started for HL400617+5.p
6978.45/2035.78	% SZS status GaveUp for HL400617+5.p
6978.45/2035.78	% SZS status Ended for HL400617+5.p
6978.99/2035.85	% SZS status Started for HL400622+4.p
6978.99/2035.85	% SZS status Theorem for HL400622+4.p
6978.99/2035.85	% SZS status Ended for HL400622+4.p
6980.05/2036.07	% SZS status Started for HL400624+4.p
6980.05/2036.07	% SZS status Theorem for HL400624+4.p
6980.05/2036.07	% SZS status Ended for HL400624+4.p
6983.54/2036.46	% SZS status Started for HL400621+5.p
6983.54/2036.46	% SZS status Theorem for HL400621+5.p
6983.54/2036.46	% SZS status Ended for HL400621+5.p
6984.49/2036.62	% SZS status Started for HL400626+4.p
6984.49/2036.62	% SZS status Theorem for HL400626+4.p
6984.49/2036.62	% SZS status Ended for HL400626+4.p
6988.26/2037.19	% SZS status Started for HL400622+5.p
6988.26/2037.19	% SZS status Theorem for HL400622+5.p
6988.26/2037.19	% SZS status Ended for HL400622+5.p
6990.98/2037.37	% SZS status Started for HL400627+4.p
6990.98/2037.37	% SZS status Theorem for HL400627+4.p
6990.98/2037.37	% SZS status Ended for HL400627+4.p
6991.65/2037.48	% SZS status Started for HL400624+5.p
6991.65/2037.48	% SZS status Theorem for HL400624+5.p
6991.65/2037.48	% SZS status Ended for HL400624+5.p
6992.46/2037.57	% SZS status Started for HL400619+5.p
6992.46/2037.57	% SZS status Theorem for HL400619+5.p
6992.46/2037.57	% SZS status Ended for HL400619+5.p
6996.07/2038.06	% SZS status Started for HL400626+5.p
6996.07/2038.06	% SZS status Theorem for HL400626+5.p
6996.07/2038.06	% SZS status Ended for HL400626+5.p
7001.57/2038.80	% SZS status Started for HL400627+5.p
7001.57/2038.80	% SZS status Theorem for HL400627+5.p
7001.57/2038.80	% SZS status Ended for HL400627+5.p
7005.44/2039.19	% SZS status Started for HL400618+4.p
7005.44/2039.19	% SZS status GaveUp for HL400618+4.p
7005.44/2039.19	% SZS status Ended for HL400618+4.p
7008.02/2039.49	% SZS status Started for HL400618+5.p
7008.02/2039.49	% SZS status GaveUp for HL400618+5.p
7008.02/2039.49	% SZS status Ended for HL400618+5.p
7026.70/2041.91	% SZS status Started for HL400620+4.p
7026.70/2041.91	% SZS status GaveUp for HL400620+4.p
7026.70/2041.91	% SZS status Ended for HL400620+4.p
7027.73/2042.12	% SZS status Started for HL400620+5.p
7027.73/2042.12	% SZS status GaveUp for HL400620+5.p
7027.73/2042.12	% SZS status Ended for HL400620+5.p
7031.66/2042.62	% SZS status Started for HL400631+4.p
7031.66/2042.62	% SZS status Theorem for HL400631+4.p
7031.66/2042.62	% SZS status Ended for HL400631+4.p
7057.21/2045.68	% SZS status Started for HL400628+4.p
7057.21/2045.68	% SZS status GaveUp for HL400628+4.p
7057.21/2045.68	% SZS status Ended for HL400628+4.p
7058.41/2045.89	% SZS status Started for HL400628+5.p
7058.41/2045.89	% SZS status GaveUp for HL400628+5.p
7058.41/2045.89	% SZS status Ended for HL400628+5.p
7062.28/2046.35	% SZS status Started for HL400629+4.p
7062.28/2046.35	% SZS status GaveUp for HL400629+4.p
7062.28/2046.35	% SZS status Ended for HL400629+4.p
7067.45/2047.09	% SZS status Started for HL400629+5.p
7067.45/2047.09	% SZS status GaveUp for HL400629+5.p
7067.45/2047.09	% SZS status Ended for HL400629+5.p
7070.79/2047.44	% SZS status Started for HL400630+4.p
7070.79/2047.44	% SZS status GaveUp for HL400630+4.p
7070.79/2047.44	% SZS status Ended for HL400630+4.p
7073.57/2047.73	% SZS status Started for HL400631+5.p
7073.57/2047.73	% SZS status Theorem for HL400631+5.p
7073.57/2047.73	% SZS status Ended for HL400631+5.p
7074.03/2047.82	% SZS status Started for HL400630+5.p
7074.03/2047.82	% SZS status GaveUp for HL400630+5.p
7074.03/2047.82	% SZS status Ended for HL400630+5.p
7098.00/2050.88	% SZS status Started for HL400633+4.p
7098.00/2050.88	% SZS status GaveUp for HL400633+4.p
7098.00/2050.88	% SZS status Ended for HL400633+4.p
7123.50/2054.02	% SZS status Started for HL400633+5.p
7123.50/2054.02	% SZS status GaveUp for HL400633+5.p
7123.50/2054.02	% SZS status Ended for HL400633+5.p
7123.94/2054.13	% SZS status Started for HL400634+4.p
7123.94/2054.13	% SZS status GaveUp for HL400634+4.p
7123.94/2054.13	% SZS status Ended for HL400634+4.p
7128.15/2054.63	% SZS status Started for HL400634+5.p
7128.15/2054.63	% SZS status GaveUp for HL400634+5.p
7128.15/2054.63	% SZS status Ended for HL400634+5.p
7132.89/2055.34	% SZS status Started for HL400635+4.p
7132.89/2055.34	% SZS status GaveUp for HL400635+4.p
7132.89/2055.34	% SZS status Ended for HL400635+4.p
7136.60/2055.69	% SZS status Started for HL400635+5.p
7136.60/2055.69	% SZS status GaveUp for HL400635+5.p
7136.60/2055.69	% SZS status Ended for HL400635+5.p
7139.29/2056.01	% SZS status Started for HL400636+4.p
7139.29/2056.01	% SZS status GaveUp for HL400636+4.p
7139.29/2056.01	% SZS status Ended for HL400636+4.p
7140.32/2056.13	% SZS status Started for HL400636+5.p
7140.32/2056.13	% SZS status GaveUp for HL400636+5.p
7140.32/2056.13	% SZS status Ended for HL400636+5.p
7164.07/2059.21	% SZS status Started for HL400637+4.p
7164.07/2059.21	% SZS status GaveUp for HL400637+4.p
7164.07/2059.21	% SZS status Ended for HL400637+4.p
7189.02/2062.31	% SZS status Started for HL400637+5.p
7189.02/2062.31	% SZS status GaveUp for HL400637+5.p
7189.02/2062.31	% SZS status Ended for HL400637+5.p
7189.49/2062.36	% SZS status Started for HL400638+4.p
7189.49/2062.36	% SZS status GaveUp for HL400638+4.p
7189.49/2062.36	% SZS status Ended for HL400638+4.p
7191.49/2062.54	% SZS status Started for HL400643+4.p
7191.49/2062.54	% SZS status Theorem for HL400643+4.p
7191.49/2062.54	% SZS status Ended for HL400643+4.p
7194.12/2063.01	% SZS status Started for HL400638+5.p
7194.12/2063.01	% SZS status GaveUp for HL400638+5.p
7194.12/2063.01	% SZS status Ended for HL400638+5.p
7198.43/2063.60	% SZS status Started for HL400639+4.p
7198.43/2063.60	% SZS status GaveUp for HL400639+4.p
7198.43/2063.60	% SZS status Ended for HL400639+4.p
7201.89/2063.95	% SZS status Started for HL400639+5.p
7201.89/2063.95	% SZS status GaveUp for HL400639+5.p
7201.89/2063.95	% SZS status Ended for HL400639+5.p
7204.33/2064.18	% SZS status Started for HL400645+4.p
7204.33/2064.18	% SZS status Theorem for HL400645+4.p
7204.33/2064.18	% SZS status Ended for HL400645+4.p
7205.23/2064.28	% SZS status Started for HL400644+4.p
7205.23/2064.28	% SZS status Theorem for HL400644+4.p
7205.23/2064.28	% SZS status Ended for HL400644+4.p
7205.23/2064.34	% SZS status Started for HL400641+4.p
7205.23/2064.34	% SZS status GaveUp for HL400641+4.p
7205.23/2064.34	% SZS status Ended for HL400641+4.p
7206.07/2064.44	% SZS status Started for HL400641+5.p
7206.07/2064.44	% SZS status GaveUp for HL400641+5.p
7206.07/2064.44	% SZS status Ended for HL400641+5.p
7230.04/2067.38	% SZS status Started for HL400642+4.p
7230.04/2067.38	% SZS status GaveUp for HL400642+4.p
7230.04/2067.38	% SZS status Ended for HL400642+4.p
7255.13/2070.63	% SZS status Started for HL400642+5.p
7255.13/2070.63	% SZS status GaveUp for HL400642+5.p
7255.13/2070.63	% SZS status Ended for HL400642+5.p
7257.40/2070.86	% SZS status Started for HL400643+5.p
7257.40/2070.86	% SZS status GaveUp for HL400643+5.p
7257.40/2070.86	% SZS status Ended for HL400643+5.p
7257.83/2070.91	% SZS status Started for HL400650+4.p
7257.83/2070.91	% SZS status Theorem for HL400650+4.p
7257.83/2070.91	% SZS status Ended for HL400650+4.p
7264.26/2071.87	% SZS status Started for HL400644+5.p
7264.26/2071.87	% SZS status GaveUp for HL400644+5.p
7264.26/2071.87	% SZS status Ended for HL400644+5.p
7270.25/2072.47	% SZS status Started for HL400646+4.p
7270.25/2072.47	% SZS status GaveUp for HL400646+4.p
7270.25/2072.47	% SZS status Ended for HL400646+4.p
7270.60/2072.52	% SZS status Started for HL400645+5.p
7270.60/2072.52	% SZS status GaveUp for HL400645+5.p
7270.60/2072.52	% SZS status Ended for HL400645+5.p
7271.21/2072.61	% SZS status Started for HL400646+5.p
7271.21/2072.61	% SZS status GaveUp for HL400646+5.p
7271.21/2072.61	% SZS status Ended for HL400646+5.p
7271.99/2072.75	% SZS status Started for HL400647+4.p
7271.99/2072.75	% SZS status GaveUp for HL400647+4.p
7271.99/2072.75	% SZS status Ended for HL400647+4.p
7295.48/2075.72	% SZS status Started for HL400647+5.p
7295.48/2075.72	% SZS status GaveUp for HL400647+5.p
7295.48/2075.72	% SZS status Ended for HL400647+5.p
7323.62/2079.16	% SZS status Started for HL400650+5.p
7323.62/2079.16	% SZS status GaveUp for HL400650+5.p
7323.62/2079.16	% SZS status Ended for HL400650+5.p
7324.34/2079.32	% SZS status Started for HL400651+4.p
7324.34/2079.32	% SZS status GaveUp for HL400651+4.p
7324.34/2079.32	% SZS status Ended for HL400651+4.p
7331.72/2080.21	% SZS status Started for HL400651+5.p
7331.72/2080.21	% SZS status GaveUp for HL400651+5.p
7331.72/2080.21	% SZS status Ended for HL400651+5.p
7336.60/2080.80	% SZS status Started for HL400652+4.p
7336.60/2080.80	% SZS status GaveUp for HL400652+4.p
7336.60/2080.80	% SZS status Ended for HL400652+4.p
7336.60/2080.82	% SZS status Started for HL400653+4.p
7336.60/2080.82	% SZS status GaveUp for HL400653+4.p
7336.60/2080.82	% SZS status Ended for HL400653+4.p
7336.60/2080.85	% SZS status Started for HL400652+5.p
7336.60/2080.85	% SZS status GaveUp for HL400652+5.p
7336.60/2080.85	% SZS status Ended for HL400652+5.p
7338.01/2081.05	% SZS status Started for HL400653+5.p
7338.01/2081.05	% SZS status GaveUp for HL400653+5.p
7338.01/2081.05	% SZS status Ended for HL400653+5.p
7340.31/2081.26	% SZS status Started for HL400658+4.p
7340.31/2081.26	% SZS status Theorem for HL400658+4.p
7340.31/2081.26	% SZS status Ended for HL400658+4.p
7341.14/2081.37	% SZS status Started for HL400660+4.p
7341.14/2081.37	% SZS status Theorem for HL400660+4.p
7341.14/2081.37	% SZS status Ended for HL400660+4.p
7362.56/2084.05	% SZS status Started for HL400654+4.p
7362.56/2084.05	% SZS status GaveUp for HL400654+4.p
7362.56/2084.05	% SZS status Ended for HL400654+4.p
7363.31/2084.17	% SZS status Started for HL400661+4.p
7363.31/2084.17	% SZS status Theorem for HL400661+4.p
7363.31/2084.17	% SZS status Ended for HL400661+4.p
7375.47/2085.66	% SZS status Started for HL400661+5.p
7375.47/2085.66	% SZS status Theorem for HL400661+5.p
7375.47/2085.66	% SZS status Ended for HL400661+5.p
7386.50/2087.11	% SZS status Started for HL400660+5.p
7386.50/2087.11	% SZS status Theorem for HL400660+5.p
7386.50/2087.11	% SZS status Ended for HL400660+5.p
7389.18/2087.44	% SZS status Started for HL400654+5.p
7389.18/2087.44	% SZS status GaveUp for HL400654+5.p
7389.18/2087.44	% SZS status Ended for HL400654+5.p
7390.25/2087.57	% SZS status Started for HL400663+4.p
7390.25/2087.57	% SZS status Theorem for HL400663+4.p
7390.25/2087.57	% SZS status Ended for HL400663+4.p
7390.25/2087.62	% SZS status Started for HL400656+4.p
7390.25/2087.62	% SZS status GaveUp for HL400656+4.p
7390.25/2087.62	% SZS status Ended for HL400656+4.p
7398.06/2088.48	% SZS status Started for HL400656+5.p
7398.06/2088.48	% SZS status GaveUp for HL400656+5.p
7398.06/2088.48	% SZS status Ended for HL400656+5.p
7402.63/2089.07	% SZS status Started for HL400663+5.p
7402.63/2089.07	% SZS status Theorem for HL400663+5.p
7402.63/2089.07	% SZS status Ended for HL400663+5.p
7403.23/2089.13	% SZS status Started for HL400657+4.p
7403.23/2089.13	% SZS status GaveUp for HL400657+4.p
7403.23/2089.13	% SZS status Ended for HL400657+4.p
7403.23/2089.14	% SZS status Started for HL400657+5.p
7403.23/2089.14	% SZS status GaveUp for HL400657+5.p
7403.23/2089.14	% SZS status Ended for HL400657+5.p
7403.84/2089.26	% SZS status Started for HL400666+4.p
7403.84/2089.26	% SZS status Theorem for HL400666+4.p
7403.84/2089.26	% SZS status Ended for HL400666+4.p
7404.19/2089.31	% SZS status Started for HL400658+5.p
7404.19/2089.31	% SZS status GaveUp for HL400658+5.p
7404.19/2089.31	% SZS status Ended for HL400658+5.p
7416.02/2090.76	% SZS status Started for HL400666+5.p
7416.02/2090.76	% SZS status Theorem for HL400666+5.p
7416.02/2090.76	% SZS status Ended for HL400666+5.p
7440.89/2093.88	% SZS status Started for HL400662+4.p
7440.89/2093.88	% SZS status GaveUp for HL400662+4.p
7440.89/2093.88	% SZS status Ended for HL400662+4.p
7441.70/2093.98	% SZS status Started for HL400668+4.p
7441.70/2093.98	% SZS status Theorem for HL400668+4.p
7441.70/2093.98	% SZS status Ended for HL400668+4.p
7452.97/2095.44	% SZS status Started for HL400662+5.p
7452.97/2095.44	% SZS status GaveUp for HL400662+5.p
7452.97/2095.44	% SZS status Ended for HL400662+5.p
7453.15/2095.46	% SZS status Started for HL400668+5.p
7453.15/2095.46	% SZS status Theorem for HL400668+5.p
7453.15/2095.46	% SZS status Ended for HL400668+5.p
7455.81/2095.78	% SZS status Started for HL400664+4.p
7455.81/2095.78	% SZS status GaveUp for HL400664+4.p
7455.81/2095.78	% SZS status Ended for HL400664+4.p
7456.54/2095.92	% SZS status Started for HL400671+4.p
7456.54/2095.92	% SZS status Theorem for HL400671+4.p
7456.54/2095.92	% SZS status Ended for HL400671+4.p
7463.94/2096.75	% SZS status Started for HL400664+5.p
7463.94/2096.75	% SZS status GaveUp for HL400664+5.p
7463.94/2096.75	% SZS status Ended for HL400664+5.p
7468.94/2097.41	% SZS status Started for HL400665+4.p
7468.94/2097.41	% SZS status GaveUp for HL400665+4.p
7468.94/2097.41	% SZS status Ended for HL400665+4.p
7469.34/2097.44	% SZS status Started for HL400665+5.p
7469.34/2097.44	% SZS status GaveUp for HL400665+5.p
7469.34/2097.44	% SZS status Ended for HL400665+5.p
7470.27/2097.58	% SZS status Started for HL400667+4.p
7470.27/2097.58	% SZS status GaveUp for HL400667+4.p
7470.27/2097.58	% SZS status Ended for HL400667+4.p
7482.06/2099.06	% SZS status Started for HL400667+5.p
7482.06/2099.06	% SZS status GaveUp for HL400667+5.p
7482.06/2099.06	% SZS status Ended for HL400667+5.p
7482.80/2099.18	% SZS status Started for HL400678+4.p
7482.80/2099.18	% SZS status Theorem for HL400678+4.p
7482.80/2099.18	% SZS status Ended for HL400678+4.p
7494.88/2100.65	% SZS status Started for HL400678+5.p
7494.88/2100.65	% SZS status Theorem for HL400678+5.p
7494.88/2100.65	% SZS status Ended for HL400678+5.p
7495.26/2100.78	% SZS status Started for HL400679+4.p
7495.26/2100.78	% SZS status Theorem for HL400679+4.p
7495.26/2100.78	% SZS status Ended for HL400679+4.p
7507.61/2102.26	% SZS status Started for HL400679+5.p
7507.61/2102.26	% SZS status Theorem for HL400679+5.p
7507.61/2102.26	% SZS status Ended for HL400679+5.p
7509.58/2102.58	% SZS status Started for HL400680+4.p
7509.58/2102.58	% SZS status Theorem for HL400680+4.p
7509.58/2102.58	% SZS status Ended for HL400680+4.p
7519.40/2103.75	% SZS status Started for HL400669+4.p
7519.40/2103.75	% SZS status GaveUp for HL400669+4.p
7519.40/2103.75	% SZS status Ended for HL400669+4.p
7519.75/2103.76	% SZS status Started for HL400669+5.p
7519.75/2103.76	% SZS status GaveUp for HL400669+5.p
7519.75/2103.76	% SZS status Ended for HL400669+5.p
7520.47/2103.90	% SZS status Started for HL400681+4.p
7520.47/2103.90	% SZS status Theorem for HL400681+4.p
7520.47/2103.90	% SZS status Ended for HL400681+4.p
7521.90/2104.20	% SZS status Started for HL400671+5.p
7521.90/2104.20	% SZS status GaveUp for HL400671+5.p
7521.90/2104.20	% SZS status Ended for HL400671+5.p
7529.03/2104.94	% SZS status Started for HL400673+4.p
7529.03/2104.94	% SZS status GaveUp for HL400673+4.p
7529.03/2104.94	% SZS status Ended for HL400673+4.p
7530.34/2105.25	% SZS status Started for HL400681+5.p
7530.34/2105.25	% SZS status Theorem for HL400681+5.p
7530.34/2105.25	% SZS status Ended for HL400681+5.p
7534.79/2105.67	% SZS status Started for HL400674+4.p
7534.79/2105.67	% SZS status GaveUp for HL400674+4.p
7534.79/2105.67	% SZS status Ended for HL400674+4.p
7535.70/2105.78	% SZS status Started for HL400673+5.p
7535.70/2105.78	% SZS status GaveUp for HL400673+5.p
7535.70/2105.78	% SZS status Ended for HL400673+5.p
7535.70/2105.80	% SZS status Started for HL400684+4.p
7535.70/2105.80	% SZS status Theorem for HL400684+4.p
7535.70/2105.80	% SZS status Ended for HL400684+4.p
7536.63/2105.92	% SZS status Started for HL400674+5.p
7536.63/2105.92	% SZS status GaveUp for HL400674+5.p
7536.63/2105.92	% SZS status Ended for HL400674+5.p
7536.63/2105.93	% SZS status Started for HL400685+4.p
7536.63/2105.93	% SZS status Theorem for HL400685+4.p
7536.63/2105.93	% SZS status Ended for HL400685+4.p
7537.84/2106.05	% SZS status Started for HL400686+4.p
7537.84/2106.05	% SZS status Theorem for HL400686+4.p
7537.84/2106.05	% SZS status Ended for HL400686+4.p
7543.55/2106.77	% SZS status Started for HL400683+5.p
7543.55/2106.77	% SZS status Theorem for HL400683+5.p
7543.55/2106.77	% SZS status Ended for HL400683+5.p
7544.31/2106.89	% SZS status Started for HL400687+4.p
7544.31/2106.89	% SZS status Theorem for HL400687+4.p
7544.31/2106.89	% SZS status Ended for HL400687+4.p
7547.26/2107.28	% SZS status Started for HL400684+5.p
7547.26/2107.28	% SZS status Theorem for HL400684+5.p
7547.26/2107.28	% SZS status Ended for HL400684+5.p
7547.56/2107.41	% SZS status Started for HL400688+4.p
7547.56/2107.41	% SZS status Theorem for HL400688+4.p
7547.56/2107.41	% SZS status Ended for HL400688+4.p
7547.56/2107.41	% SZS status Started for HL400685+5.p
7547.56/2107.41	% SZS status Theorem for HL400685+5.p
7547.56/2107.41	% SZS status Ended for HL400685+5.p
7548.22/2107.57	% SZS status Started for HL400686+5.p
7548.22/2107.57	% SZS status Theorem for HL400686+5.p
7548.22/2107.57	% SZS status Ended for HL400686+5.p
7548.22/2107.57	% SZS status Started for HL400690+4.p
7548.22/2107.57	% SZS status Theorem for HL400690+4.p
7548.22/2107.57	% SZS status Ended for HL400690+4.p
7550.81/2107.71	% SZS status Started for HL400691+4.p
7550.81/2107.71	% SZS status Theorem for HL400691+4.p
7550.81/2107.71	% SZS status Ended for HL400691+4.p
7556.39/2108.38	% SZS status Started for HL400687+5.p
7556.39/2108.38	% SZS status Theorem for HL400687+5.p
7556.39/2108.38	% SZS status Ended for HL400687+5.p
7560.61/2108.93	% SZS status Started for HL400688+5.p
7560.61/2108.93	% SZS status Theorem for HL400688+5.p
7560.61/2108.93	% SZS status Ended for HL400688+5.p
7561.45/2109.08	% SZS status Started for HL400690+5.p
7561.45/2109.08	% SZS status Theorem for HL400690+5.p
7561.45/2109.08	% SZS status Ended for HL400690+5.p
7561.72/2109.21	% SZS status Started for HL400691+5.p
7561.72/2109.21	% SZS status Theorem for HL400691+5.p
7561.72/2109.21	% SZS status Ended for HL400691+5.p
7562.23/2109.23	% SZS status Started for HL400693+4.p
7562.23/2109.23	% SZS status Theorem for HL400693+4.p
7562.23/2109.23	% SZS status Ended for HL400693+4.p
7574.22/2110.70	% SZS status Started for HL400693+5.p
7574.22/2110.70	% SZS status Theorem for HL400693+5.p
7574.22/2110.70	% SZS status Ended for HL400693+5.p
7575.31/2110.87	% SZS status Started for HL400680+5.p
7575.31/2110.87	% SZS status GaveUp for HL400680+5.p
7575.31/2110.87	% SZS status Ended for HL400680+5.p
7577.83/2111.13	% SZS status Started for HL400695+4.p
7577.83/2111.13	% SZS status Theorem for HL400695+4.p
7577.83/2111.13	% SZS status Ended for HL400695+4.p
7586.43/2112.16	% SZS status Started for HL400682+4.p
7586.43/2112.16	% SZS status GaveUp for HL400682+4.p
7586.43/2112.16	% SZS status Ended for HL400682+4.p
7586.99/2112.32	% SZS status Started for HL400696+4.p
7586.99/2112.32	% SZS status Theorem for HL400696+4.p
7586.99/2112.32	% SZS status Ended for HL400696+4.p
7587.96/2112.48	% SZS status Started for HL400682+5.p
7587.96/2112.48	% SZS status GaveUp for HL400682+5.p
7587.96/2112.48	% SZS status Ended for HL400682+5.p
7593.11/2113.11	% SZS status Started for HL400683+4.p
7593.11/2113.11	% SZS status GaveUp for HL400683+4.p
7593.11/2113.11	% SZS status Ended for HL400683+4.p
7598.53/2113.68	% SZS status Started for HL400697+4.p
7598.53/2113.68	% SZS status Theorem for HL400697+4.p
7598.53/2113.68	% SZS status Ended for HL400697+4.p
7599.33/2113.81	% SZS status Started for HL400698+4.p
7599.33/2113.81	% SZS status Theorem for HL400698+4.p
7599.33/2113.81	% SZS status Ended for HL400698+4.p
7621.66/2116.63	% SZS status Started for HL400692+4.p
7621.66/2116.63	% SZS status GaveUp for HL400692+4.p
7621.66/2116.63	% SZS status Ended for HL400692+4.p
7626.48/2117.23	% SZS status Started for HL400692+5.p
7626.48/2117.23	% SZS status GaveUp for HL400692+5.p
7626.48/2117.23	% SZS status Ended for HL400692+5.p
7627.55/2117.51	% SZS status Started for HL400694+4.p
7627.55/2117.51	% SZS status GaveUp for HL400694+4.p
7627.55/2117.51	% SZS status Ended for HL400694+4.p
7630.02/2117.65	% SZS status Started for HL400700+4.p
7630.02/2117.65	% SZS status Theorem for HL400700+4.p
7630.02/2117.65	% SZS status Ended for HL400700+4.p
7640.41/2119.05	% SZS status Started for HL400694+5.p
7640.41/2119.05	% SZS status GaveUp for HL400694+5.p
7640.41/2119.05	% SZS status Ended for HL400694+5.p
7642.22/2119.21	% SZS status Started for HL400701+4.p
7642.22/2119.21	% SZS status Theorem for HL400701+4.p
7642.22/2119.21	% SZS status Ended for HL400701+4.p
7644.19/2119.44	% SZS status Started for HL400695+5.p
7644.19/2119.44	% SZS status GaveUp for HL400695+5.p
7644.19/2119.44	% SZS status Ended for HL400695+5.p
7644.19/2119.51	% SZS status Started for HL400698+5.p
7644.19/2119.51	% SZS status Theorem for HL400698+5.p
7644.19/2119.51	% SZS status Ended for HL400698+5.p
7644.78/2119.60	% SZS status Started for HL400702+4.p
7644.78/2119.60	% SZS status Theorem for HL400702+4.p
7644.78/2119.60	% SZS status Ended for HL400702+4.p
7646.72/2119.74	% SZS status Started for HL400703+4.p
7646.72/2119.74	% SZS status Theorem for HL400703+4.p
7646.72/2119.74	% SZS status Ended for HL400703+4.p
7652.82/2120.60	% SZS status Started for HL400696+5.p
7652.82/2120.60	% SZS status GaveUp for HL400696+5.p
7652.82/2120.60	% SZS status Ended for HL400696+5.p
7653.38/2120.70	% SZS status Started for HL400701+5.p
7653.38/2120.70	% SZS status Theorem for HL400701+5.p
7653.38/2120.70	% SZS status Ended for HL400701+5.p
7656.87/2121.04	% SZS status Started for HL400702+5.p
7656.87/2121.04	% SZS status Theorem for HL400702+5.p
7656.87/2121.04	% SZS status Ended for HL400702+5.p
7657.87/2121.25	% SZS status Started for HL400703+5.p
7657.87/2121.25	% SZS status Theorem for HL400703+5.p
7657.87/2121.25	% SZS status Ended for HL400703+5.p
7659.96/2121.44	% SZS status Started for HL400697+5.p
7659.96/2121.44	% SZS status GaveUp for HL400697+5.p
7659.96/2121.44	% SZS status Ended for HL400697+5.p
7662.76/2121.90	% SZS status Started for HL400707+4.p
7662.76/2121.90	% SZS status Theorem for HL400707+4.p
7662.76/2121.90	% SZS status Ended for HL400707+4.p
7674.70/2123.30	% SZS status Started for HL400700+5.p
7674.70/2123.30	% SZS status Theorem for HL400700+5.p
7674.70/2123.30	% SZS status Ended for HL400700+5.p
7675.43/2123.43	% SZS status Started for HL400708+4.p
7675.43/2123.43	% SZS status Theorem for HL400708+4.p
7675.43/2123.43	% SZS status Ended for HL400708+4.p
7687.99/2124.94	% SZS status Started for HL400699+4.p
7687.99/2124.94	% SZS status GaveUp for HL400699+4.p
7687.99/2124.94	% SZS status Ended for HL400699+4.p
7691.73/2125.39	% SZS status Started for HL400709+4.p
7691.73/2125.39	% SZS status Theorem for HL400709+4.p
7691.73/2125.39	% SZS status Ended for HL400709+4.p
7692.27/2125.51	% SZS status Started for HL400699+5.p
7692.27/2125.51	% SZS status GaveUp for HL400699+5.p
7692.27/2125.51	% SZS status Ended for HL400699+5.p
7718.28/2128.78	% SZS status Started for HL400705+4.p
7718.28/2128.78	% SZS status GaveUp for HL400705+4.p
7718.28/2128.78	% SZS status Ended for HL400705+4.p
7719.43/2129.03	% SZS status Started for HL400705+5.p
7719.43/2129.03	% SZS status GaveUp for HL400705+5.p
7719.43/2129.03	% SZS status Ended for HL400705+5.p
7721.05/2129.10	% SZS status Started for HL400708+5.p
7721.05/2129.10	% SZS status Theorem for HL400708+5.p
7721.05/2129.10	% SZS status Ended for HL400708+5.p
7721.68/2129.19	% SZS status Started for HL400706+4.p
7721.68/2129.19	% SZS status GaveUp for HL400706+4.p
7721.68/2129.19	% SZS status Ended for HL400706+4.p
7722.57/2129.31	% SZS status Started for HL400714+4.p
7722.57/2129.31	% SZS status Theorem for HL400714+4.p
7722.57/2129.31	% SZS status Ended for HL400714+4.p
7723.42/2129.53	% SZS status Started for HL400706+5.p
7723.42/2129.53	% SZS status GaveUp for HL400706+5.p
7723.42/2129.53	% SZS status Ended for HL400706+5.p
7725.80/2129.66	% SZS status Started for HL400715+4.p
7725.80/2129.66	% SZS status Theorem for HL400715+4.p
7725.80/2129.66	% SZS status Ended for HL400715+4.p
7730.34/2130.24	% SZS status Started for HL400707+5.p
7730.34/2130.24	% SZS status GaveUp for HL400707+5.p
7730.34/2130.24	% SZS status Ended for HL400707+5.p
7735.95/2130.99	% SZS status Started for HL400709+5.p
7735.95/2130.99	% SZS status Theorem for HL400709+5.p
7735.95/2130.99	% SZS status Ended for HL400709+5.p
7736.86/2131.16	% SZS status Started for HL400715+5.p
7736.86/2131.16	% SZS status Theorem for HL400715+5.p
7736.86/2131.16	% SZS status Ended for HL400715+5.p
7737.76/2131.27	% SZS status Started for HL400717+4.p
7737.76/2131.27	% SZS status Theorem for HL400717+4.p
7737.76/2131.27	% SZS status Ended for HL400717+4.p
7739.86/2131.48	% SZS status Started for HL400710+4.p
7739.86/2131.48	% SZS status Theorem for HL400710+4.p
7739.86/2131.48	% SZS status Ended for HL400710+4.p
7749.20/2132.76	% SZS status Started for HL400717+5.p
7749.20/2132.76	% SZS status Theorem for HL400717+5.p
7749.20/2132.76	% SZS status Ended for HL400717+5.p
7784.68/2137.06	% SZS status Started for HL400710+5.p
7784.68/2137.06	% SZS status GaveUp for HL400710+5.p
7784.68/2137.06	% SZS status Ended for HL400710+5.p
7785.36/2137.20	% SZS status Started for HL400719+4.p
7785.36/2137.20	% SZS status Theorem for HL400719+4.p
7785.36/2137.20	% SZS status Ended for HL400719+4.p
7785.93/2137.26	% SZS status Started for HL400712+4.p
7785.93/2137.26	% SZS status GaveUp for HL400712+4.p
7785.93/2137.26	% SZS status Ended for HL400712+4.p
7787.86/2137.48	% SZS status Started for HL400712+5.p
7787.86/2137.48	% SZS status GaveUp for HL400712+5.p
7787.86/2137.48	% SZS status Ended for HL400712+5.p
7788.43/2137.58	% SZS status Started for HL400714+5.p
7788.43/2137.58	% SZS status GaveUp for HL400714+5.p
7788.43/2137.58	% SZS status Ended for HL400714+5.p
7795.96/2138.51	% SZS status Started for HL400716+4.p
7795.96/2138.51	% SZS status GaveUp for HL400716+4.p
7795.96/2138.51	% SZS status Ended for HL400716+4.p
7802.49/2139.34	% SZS status Started for HL400716+5.p
7802.49/2139.34	% SZS status GaveUp for HL400716+5.p
7802.49/2139.34	% SZS status Ended for HL400716+5.p
7805.46/2139.69	% SZS status Started for HL400718+4.p
7805.46/2139.69	% SZS status GaveUp for HL400718+4.p
7805.46/2139.69	% SZS status Ended for HL400718+4.p
7815.57/2141.12	% SZS status Started for HL400718+5.p
7815.57/2141.12	% SZS status GaveUp for HL400718+5.p
7815.57/2141.12	% SZS status Ended for HL400718+5.p
7817.97/2141.26	% SZS status Started for HL400723+4.p
7817.97/2141.26	% SZS status Theorem for HL400723+4.p
7817.97/2141.26	% SZS status Ended for HL400723+4.p
7831.74/2142.99	% SZS status Started for HL400719+5.p
7831.74/2142.99	% SZS status Theorem for HL400719+5.p
7831.74/2142.99	% SZS status Ended for HL400719+5.p
7832.79/2143.23	% SZS status Started for HL400724+4.p
7832.79/2143.23	% SZS status Theorem for HL400724+4.p
7832.79/2143.23	% SZS status Ended for HL400724+4.p
7851.60/2145.50	% SZS status Started for HL400720+4.p
7851.60/2145.50	% SZS status GaveUp for HL400720+4.p
7851.60/2145.50	% SZS status Ended for HL400720+4.p
7852.91/2145.65	% SZS status Started for HL400725+4.p
7852.91/2145.65	% SZS status Theorem for HL400725+4.p
7852.91/2145.65	% SZS status Ended for HL400725+4.p
7853.81/2145.75	% SZS status Started for HL400720+5.p
7853.81/2145.75	% SZS status GaveUp for HL400720+5.p
7853.81/2145.75	% SZS status Ended for HL400720+5.p
7854.39/2145.85	% SZS status Started for HL400721+4.p
7854.39/2145.85	% SZS status GaveUp for HL400721+4.p
7854.39/2145.85	% SZS status Ended for HL400721+4.p
7854.39/2145.90	% SZS status Started for HL400726+4.p
7854.39/2145.90	% SZS status Theorem for HL400726+4.p
7854.39/2145.90	% SZS status Ended for HL400726+4.p
7855.08/2146.04	% SZS status Started for HL400727+4.p
7855.08/2146.04	% SZS status Theorem for HL400727+4.p
7855.08/2146.04	% SZS status Ended for HL400727+4.p
7862.01/2146.81	% SZS status Started for HL400721+5.p
7862.01/2146.81	% SZS status GaveUp for HL400721+5.p
7862.01/2146.81	% SZS status Ended for HL400721+5.p
7864.01/2147.16	% SZS status Started for HL400725+5.p
7864.01/2147.16	% SZS status Theorem for HL400725+5.p
7864.01/2147.16	% SZS status Ended for HL400725+5.p
7866.52/2147.36	% SZS status Started for HL400726+5.p
7866.52/2147.36	% SZS status Theorem for HL400726+5.p
7866.52/2147.36	% SZS status Ended for HL400726+5.p
7867.82/2147.54	% SZS status Started for HL400722+4.p
7867.82/2147.54	% SZS status GaveUp for HL400722+4.p
7867.82/2147.54	% SZS status Ended for HL400722+4.p
7871.44/2148.02	% SZS status Started for HL400722+5.p
7871.44/2148.02	% SZS status GaveUp for HL400722+5.p
7871.44/2148.02	% SZS status Ended for HL400722+5.p
7883.37/2149.53	% SZS status Started for HL400723+5.p
7883.37/2149.53	% SZS status GaveUp for HL400723+5.p
7883.37/2149.53	% SZS status Ended for HL400723+5.p
7884.54/2149.68	% SZS status Started for HL400731+4.p
7884.54/2149.68	% SZS status Theorem for HL400731+4.p
7884.54/2149.68	% SZS status Ended for HL400731+4.p
7888.25/2150.08	% SZS status Started for HL400733+4.p
7888.25/2150.08	% SZS status Theorem for HL400733+4.p
7888.25/2150.08	% SZS status Ended for HL400733+4.p
7895.79/2151.07	% SZS status Started for HL400732+5.p
7895.79/2151.07	% SZS status Theorem for HL400732+5.p
7895.79/2151.07	% SZS status Ended for HL400732+5.p
7898.44/2151.61	% SZS status Started for HL400724+5.p
7898.44/2151.61	% SZS status GaveUp for HL400724+5.p
7898.44/2151.61	% SZS status Ended for HL400724+5.p
7900.71/2151.65	% SZS status Started for HL400733+5.p
7900.71/2151.65	% SZS status Theorem for HL400733+5.p
7900.71/2151.65	% SZS status Ended for HL400733+5.p
7901.03/2151.71	% SZS status Started for HL400727+5.p
7901.03/2151.71	% SZS status Theorem for HL400727+5.p
7901.03/2151.71	% SZS status Ended for HL400727+5.p
7902.24/2151.96	% SZS status Started for HL400735+4.p
7902.24/2151.96	% SZS status Theorem for HL400735+4.p
7902.24/2151.96	% SZS status Ended for HL400735+4.p
7911.91/2153.16	% SZS status Started for HL400734+5.p
7911.91/2153.16	% SZS status Theorem for HL400734+5.p
7911.91/2153.16	% SZS status Ended for HL400734+5.p
7913.67/2153.32	% SZS status Started for HL400731+5.p
7913.67/2153.32	% SZS status Theorem for HL400731+5.p
7913.67/2153.32	% SZS status Ended for HL400731+5.p
7915.66/2153.56	% SZS status Started for HL400737+4.p
7915.66/2153.56	% SZS status Theorem for HL400737+4.p
7915.66/2153.56	% SZS status Ended for HL400737+4.p
7928.10/2155.08	% SZS status Started for HL400730+4.p
7928.10/2155.08	% SZS status GaveUp for HL400730+4.p
7928.10/2155.08	% SZS status Ended for HL400730+4.p
7929.25/2155.30	% SZS status Started for HL400738+4.p
7929.25/2155.30	% SZS status Theorem for HL400738+4.p
7929.25/2155.30	% SZS status Ended for HL400738+4.p
7929.94/2155.44	% SZS status Started for HL400730+5.p
7929.94/2155.44	% SZS status GaveUp for HL400730+5.p
7929.94/2155.44	% SZS status Ended for HL400730+5.p
7932.66/2155.67	% SZS status Started for HL400739+4.p
7932.66/2155.67	% SZS status Theorem for HL400739+4.p
7932.66/2155.67	% SZS status Ended for HL400739+4.p
7936.81/2156.23	% SZS status Started for HL400732+4.p
7936.81/2156.23	% SZS status GaveUp for HL400732+4.p
7936.81/2156.23	% SZS status Ended for HL400732+4.p
7941.54/2156.80	% SZS status Started for HL400738+5.p
7941.54/2156.80	% SZS status Theorem for HL400738+5.p
7941.54/2156.80	% SZS status Ended for HL400738+5.p
7944.76/2157.19	% SZS status Started for HL400739+5.p
7944.76/2157.19	% SZS status Theorem for HL400739+5.p
7944.76/2157.19	% SZS status Ended for HL400739+5.p
7945.57/2157.33	% SZS status Started for HL400741+4.p
7945.57/2157.33	% SZS status Theorem for HL400741+4.p
7945.57/2157.33	% SZS status Ended for HL400741+4.p
7957.45/2158.80	% SZS status Started for HL400741+5.p
7957.45/2158.80	% SZS status Theorem for HL400741+5.p
7957.45/2158.80	% SZS status Ended for HL400741+5.p
7959.49/2159.13	% SZS status Started for HL400743+4.p
7959.49/2159.13	% SZS status Theorem for HL400743+4.p
7959.49/2159.13	% SZS status Ended for HL400743+4.p
7960.23/2159.32	% SZS status Started for HL400734+4.p
7960.23/2159.32	% SZS status GaveUp for HL400734+4.p
7960.23/2159.32	% SZS status Ended for HL400734+4.p
7967.11/2160.02	% SZS status Started for HL400735+5.p
7967.11/2160.02	% SZS status GaveUp for HL400735+5.p
7967.11/2160.02	% SZS status Ended for HL400735+5.p
7968.07/2160.12	% SZS status Started for HL400736+4.p
7968.07/2160.12	% SZS status GaveUp for HL400736+4.p
7968.07/2160.12	% SZS status Ended for HL400736+4.p
7968.70/2160.26	% SZS status Started for HL400746+4.p
7968.70/2160.26	% SZS status Theorem for HL400746+4.p
7968.70/2160.26	% SZS status Ended for HL400746+4.p
7977.85/2161.49	% SZS status Started for HL400736+5.p
7977.85/2161.49	% SZS status GaveUp for HL400736+5.p
7977.85/2161.49	% SZS status Ended for HL400736+5.p
7981.07/2161.80	% SZS status Started for HL400747+4.p
7981.07/2161.80	% SZS status Theorem for HL400747+4.p
7981.07/2161.80	% SZS status Ended for HL400747+4.p
7982.08/2161.90	% SZS status Started for HL400737+5.p
7982.08/2161.90	% SZS status GaveUp for HL400737+5.p
7982.08/2161.90	% SZS status Ended for HL400737+5.p
8003.07/2164.54	% SZS status Started for HL400740+4.p
8003.07/2164.54	% SZS status GaveUp for HL400740+4.p
8003.07/2164.54	% SZS status Ended for HL400740+4.p
8007.79/2165.13	% SZS status Started for HL400740+5.p
8007.79/2165.13	% SZS status GaveUp for HL400740+5.p
8007.79/2165.13	% SZS status Ended for HL400740+5.p
8014.76/2165.99	% SZS status Started for HL400746+5.p
8014.76/2165.99	% SZS status Theorem for HL400746+5.p
8014.76/2165.99	% SZS status Ended for HL400746+5.p
8024.91/2167.41	% SZS status Started for HL400743+5.p
8024.91/2167.41	% SZS status GaveUp for HL400743+5.p
8024.91/2167.41	% SZS status Ended for HL400743+5.p
8025.22/2167.50	% SZS status Started for HL400749+4.p
8025.22/2167.50	% SZS status Theorem for HL400749+4.p
8025.22/2167.50	% SZS status Ended for HL400749+4.p
8027.50/2167.60	% SZS status Started for HL400750+4.p
8027.50/2167.60	% SZS status Theorem for HL400750+4.p
8027.50/2167.60	% SZS status Ended for HL400750+4.p
8028.07/2167.63	% SZS status Started for HL400745+4.p
8028.07/2167.63	% SZS status GaveUp for HL400745+4.p
8028.07/2167.63	% SZS status Ended for HL400745+4.p
8028.80/2167.77	% SZS status Started for HL400751+4.p
8028.80/2167.77	% SZS status Theorem for HL400751+4.p
8028.80/2167.77	% SZS status Ended for HL400751+4.p
8029.87/2167.94	% SZS status Started for HL400752+4.p
8029.87/2167.94	% SZS status Theorem for HL400752+4.p
8029.87/2167.94	% SZS status Ended for HL400752+4.p
8033.24/2168.29	% SZS status Started for HL400745+5.p
8033.24/2168.29	% SZS status GaveUp for HL400745+5.p
8033.24/2168.29	% SZS status Ended for HL400745+5.p
8047.08/2170.09	% SZS status Started for HL400748+4.p
8047.08/2170.09	% SZS status GaveUp for HL400748+4.p
8047.08/2170.09	% SZS status Ended for HL400748+4.p
8047.56/2170.15	% SZS status Started for HL400747+5.p
8047.56/2170.15	% SZS status GaveUp for HL400747+5.p
8047.56/2170.15	% SZS status Ended for HL400747+5.p
8069.35/2172.86	% SZS status Started for HL400748+5.p
8069.35/2172.86	% SZS status GaveUp for HL400748+5.p
8069.35/2172.86	% SZS status Ended for HL400748+5.p
8072.18/2173.20	% SZS status Started for HL400750+5.p
8072.18/2173.20	% SZS status Theorem for HL400750+5.p
8072.18/2173.20	% SZS status Ended for HL400750+5.p
8075.79/2173.63	% SZS status Started for HL400752+5.p
8075.79/2173.63	% SZS status Theorem for HL400752+5.p
8075.79/2173.63	% SZS status Ended for HL400752+5.p
8080.99/2174.31	% SZS status Started for HL400749+5.p
8080.99/2174.31	% SZS status GaveUp for HL400749+5.p
8080.99/2174.31	% SZS status Ended for HL400749+5.p
8090.59/2175.70	% SZS status Started for HL400756+4.p
8090.59/2175.70	% SZS status Theorem for HL400756+4.p
8090.59/2175.70	% SZS status Ended for HL400756+4.p
8093.59/2175.92	% SZS status Started for HL400751+5.p
8093.59/2175.92	% SZS status GaveUp for HL400751+5.p
8093.59/2175.92	% SZS status Ended for HL400751+5.p
8098.04/2176.45	% SZS status Started for HL400753+4.p
8098.04/2176.45	% SZS status GaveUp for HL400753+4.p
8098.04/2176.45	% SZS status Ended for HL400753+4.p
8112.89/2178.36	% SZS status Started for HL400755+4.p
8112.89/2178.36	% SZS status Theorem for HL400755+4.p
8112.89/2178.36	% SZS status Ended for HL400755+4.p
8112.89/2178.39	% SZS status Started for HL400754+4.p
8112.89/2178.39	% SZS status GaveUp for HL400754+4.p
8112.89/2178.39	% SZS status Ended for HL400754+4.p
8112.89/2178.44	% SZS status Started for HL400753+5.p
8112.89/2178.44	% SZS status GaveUp for HL400753+5.p
8112.89/2178.44	% SZS status Ended for HL400753+5.p
8116.51/2178.80	% SZS status Started for HL400760+4.p
8116.51/2178.80	% SZS status Theorem for HL400760+4.p
8116.51/2178.80	% SZS status Ended for HL400760+4.p
8135.12/2181.20	% SZS status Started for HL400754+5.p
8135.12/2181.20	% SZS status GaveUp for HL400754+5.p
8135.12/2181.20	% SZS status Ended for HL400754+5.p
8142.14/2182.00	% SZS status Started for HL400755+5.p
8142.14/2182.00	% SZS status GaveUp for HL400755+5.p
8142.14/2182.00	% SZS status Ended for HL400755+5.p
8157.46/2183.97	% SZS status Started for HL400756+5.p
8157.46/2183.97	% SZS status GaveUp for HL400756+5.p
8157.46/2183.97	% SZS status Ended for HL400756+5.p
8159.60/2184.19	% SZS status Started for HL400757+4.p
8159.60/2184.19	% SZS status GaveUp for HL400757+4.p
8159.60/2184.19	% SZS status Ended for HL400757+4.p
8160.52/2184.37	% SZS status Started for HL400759+5.p
8160.52/2184.37	% SZS status Theorem for HL400759+5.p
8160.52/2184.37	% SZS status Ended for HL400759+5.p
8163.64/2184.70	% SZS status Started for HL400762+4.p
8163.64/2184.70	% SZS status Theorem for HL400762+4.p
8163.64/2184.70	% SZS status Ended for HL400762+4.p
8163.64/2184.73	% SZS status Started for HL400757+5.p
8163.64/2184.73	% SZS status GaveUp for HL400757+5.p
8163.64/2184.73	% SZS status Ended for HL400757+5.p
8174.90/2186.19	% SZS status Started for HL400764+4.p
8174.90/2186.19	% SZS status Theorem for HL400764+4.p
8174.90/2186.19	% SZS status Ended for HL400764+4.p
8178.02/2186.52	% SZS status Started for HL400759+4.p
8178.02/2186.52	% SZS status GaveUp for HL400759+4.p
8178.02/2186.52	% SZS status Ended for HL400759+4.p
8181.17/2186.92	% SZS status Started for HL400763+4.p
8181.17/2186.92	% SZS status Theorem for HL400763+4.p
8181.17/2186.92	% SZS status Ended for HL400763+4.p
8182.04/2186.98	% SZS status Started for HL400765+4.p
8182.04/2186.98	% SZS status Theorem for HL400765+4.p
8182.04/2186.98	% SZS status Ended for HL400765+4.p
8182.91/2187.12	% SZS status Started for HL400760+5.p
8182.91/2187.12	% SZS status GaveUp for HL400760+5.p
8182.91/2187.12	% SZS status Ended for HL400760+5.p
8190.77/2188.13	% SZS status Started for HL400761+4.p
8190.77/2188.13	% SZS status Theorem for HL400761+4.p
8190.77/2188.13	% SZS status Ended for HL400761+4.p
8196.20/2188.82	% SZS status Started for HL400766+4.p
8196.20/2188.82	% SZS status Theorem for HL400766+4.p
8196.20/2188.82	% SZS status Ended for HL400766+4.p
8208.63/2190.33	% SZS status Started for HL400761+5.p
8208.63/2190.33	% SZS status GaveUp for HL400761+5.p
8208.63/2190.33	% SZS status Ended for HL400761+5.p
8225.65/2192.48	% SZS status Started for HL400762+5.p
8225.65/2192.48	% SZS status GaveUp for HL400762+5.p
8225.65/2192.48	% SZS status Ended for HL400762+5.p
8229.78/2193.03	% SZS status Started for HL400763+5.p
8229.78/2193.03	% SZS status GaveUp for HL400763+5.p
8229.78/2193.03	% SZS status Ended for HL400763+5.p
8242.12/2194.55	% SZS status Started for HL400764+5.p
8242.12/2194.55	% SZS status GaveUp for HL400764+5.p
8242.12/2194.55	% SZS status Ended for HL400764+5.p
8247.75/2195.28	% SZS status Started for HL400765+5.p
8247.75/2195.28	% SZS status GaveUp for HL400765+5.p
8247.75/2195.28	% SZS status Ended for HL400765+5.p
8248.22/2195.42	% SZS status Started for HL400766+5.p
8248.22/2195.42	% SZS status GaveUp for HL400766+5.p
8248.22/2195.42	% SZS status Ended for HL400766+5.p
8253.61/2196.08	% SZS status Started for HL400769+5.p
8253.61/2196.08	% SZS status Theorem for HL400769+5.p
8253.61/2196.08	% SZS status Ended for HL400769+5.p
8255.16/2196.21	% SZS status Started for HL400771+4.p
8255.16/2196.21	% SZS status Theorem for HL400771+4.p
8255.16/2196.21	% SZS status Ended for HL400771+4.p
8256.35/2196.35	% SZS status Started for HL400767+4.p
8256.35/2196.35	% SZS status GaveUp for HL400767+4.p
8256.35/2196.35	% SZS status Ended for HL400767+4.p
8256.88/2196.51	% SZS status Started for HL400772+4.p
8256.88/2196.51	% SZS status Theorem for HL400772+4.p
8256.88/2196.51	% SZS status Ended for HL400772+4.p
8262.96/2197.16	% SZS status Started for HL400767+5.p
8262.96/2197.16	% SZS status GaveUp for HL400767+5.p
8262.96/2197.16	% SZS status Ended for HL400767+5.p
8265.99/2197.74	% SZS status Started for HL400771+5.p
8265.99/2197.74	% SZS status Theorem for HL400771+5.p
8265.99/2197.74	% SZS status Ended for HL400771+5.p
8268.61/2197.86	% SZS status Started for HL400769+4.p
8268.61/2197.86	% SZS status Theorem for HL400769+4.p
8268.61/2197.86	% SZS status Ended for HL400769+4.p
8269.46/2198.03	% SZS status Started for HL400772+5.p
8269.46/2198.03	% SZS status Theorem for HL400772+5.p
8269.46/2198.03	% SZS status Ended for HL400772+5.p
8269.91/2198.04	% SZS status Started for HL400774+4.p
8269.91/2198.04	% SZS status Theorem for HL400774+4.p
8269.91/2198.04	% SZS status Ended for HL400774+4.p
8274.79/2198.66	% SZS status Started for HL400768+4.p
8274.79/2198.66	% SZS status GaveUp for HL400768+4.p
8274.79/2198.66	% SZS status Ended for HL400768+4.p
8274.79/2198.68	% SZS status Started for HL400773+4.p
8274.79/2198.68	% SZS status Theorem for HL400773+4.p
8274.79/2198.68	% SZS status Ended for HL400773+4.p
8282.35/2199.58	% SZS status Started for HL400774+5.p
8282.35/2199.58	% SZS status Theorem for HL400774+5.p
8282.35/2199.58	% SZS status Ended for HL400774+5.p
8291.32/2200.76	% SZS status Started for HL400768+5.p
8291.32/2200.76	% SZS status GaveUp for HL400768+5.p
8291.32/2200.76	% SZS status Ended for HL400768+5.p
8291.70/2200.92	% SZS status Started for HL400777+4.p
8291.70/2200.92	% SZS status Theorem for HL400777+4.p
8291.70/2200.92	% SZS status Ended for HL400777+4.p
8314.84/2203.68	% SZS status Started for HL400770+4.p
8314.84/2203.68	% SZS status GaveUp for HL400770+4.p
8314.84/2203.68	% SZS status Ended for HL400770+4.p
8314.84/2203.74	% SZS status Started for HL400770+5.p
8314.84/2203.74	% SZS status GaveUp for HL400770+5.p
8314.84/2203.74	% SZS status Ended for HL400770+5.p
8332.89/2206.06	% SZS status Started for HL400773+5.p
8332.89/2206.06	% SZS status GaveUp for HL400773+5.p
8332.89/2206.06	% SZS status Ended for HL400773+5.p
8335.12/2206.25	% SZS status Started for HL400775+4.p
8335.12/2206.25	% SZS status GaveUp for HL400775+4.p
8335.12/2206.25	% SZS status Ended for HL400775+4.p
8336.78/2206.62	% SZS status Started for HL400777+5.p
8336.78/2206.62	% SZS status Theorem for HL400777+5.p
8336.78/2206.62	% SZS status Ended for HL400777+5.p
8340.30/2206.93	% SZS status Started for HL400776+4.p
8340.30/2206.93	% SZS status GaveUp for HL400776+4.p
8340.30/2206.93	% SZS status Ended for HL400776+4.p
8340.48/2207.01	% SZS status Started for HL400775+5.p
8340.48/2207.01	% SZS status GaveUp for HL400775+5.p
8340.48/2207.01	% SZS status Ended for HL400775+5.p
8340.93/2207.16	% SZS status Started for HL400783+4.p
8340.93/2207.16	% SZS status Theorem for HL400783+4.p
8340.93/2207.16	% SZS status Ended for HL400783+4.p
8347.92/2207.86	% SZS status Started for HL400776+5.p
8347.92/2207.86	% SZS status GaveUp for HL400776+5.p
8347.92/2207.86	% SZS status Ended for HL400776+5.p
8351.89/2208.34	% SZS status Started for HL400784+4.p
8351.89/2208.34	% SZS status Theorem for HL400784+4.p
8351.89/2208.34	% SZS status Ended for HL400784+4.p
8354.20/2208.80	% SZS status Started for HL400781+4.p
8354.20/2208.80	% SZS status Theorem for HL400781+4.p
8354.20/2208.80	% SZS status Ended for HL400781+4.p
8361.56/2209.61	% SZS status Started for HL400785+4.p
8361.56/2209.61	% SZS status Theorem for HL400785+4.p
8361.56/2209.61	% SZS status Ended for HL400785+4.p
8379.42/2211.84	% SZS status Started for HL400780+4.p
8379.42/2211.84	% SZS status GaveUp for HL400780+4.p
8379.42/2211.84	% SZS status Ended for HL400780+4.p
8380.32/2212.07	% SZS status Started for HL400780+5.p
8380.32/2212.07	% SZS status GaveUp for HL400780+5.p
8380.32/2212.07	% SZS status Ended for HL400780+5.p
8380.48/2212.12	% SZS status Started for HL400786+4.p
8380.48/2212.12	% SZS status Theorem for HL400786+4.p
8380.48/2212.12	% SZS status Ended for HL400786+4.p
8386.52/2212.70	% SZS status Started for HL400782+5.p
8386.52/2212.70	% SZS status Theorem for HL400782+5.p
8386.52/2212.70	% SZS status Ended for HL400782+5.p
8387.04/2212.77	% SZS status Started for HL400787+4.p
8387.04/2212.77	% SZS status Theorem for HL400787+4.p
8387.04/2212.77	% SZS status Ended for HL400787+4.p
8401.73/2214.63	% SZS status Started for HL400781+5.p
8401.73/2214.63	% SZS status GaveUp for HL400781+5.p
8401.73/2214.63	% SZS status Ended for HL400781+5.p
8402.93/2214.85	% SZS status Started for HL400782+4.p
8402.93/2214.85	% SZS status GaveUp for HL400782+4.p
8402.93/2214.85	% SZS status Ended for HL400782+4.p
8408.54/2215.44	% SZS status Started for HL400783+5.p
8408.54/2215.44	% SZS status GaveUp for HL400783+5.p
8408.54/2215.44	% SZS status Ended for HL400783+5.p
8417.49/2216.61	% SZS status Started for HL400784+5.p
8417.49/2216.61	% SZS status GaveUp for HL400784+5.p
8417.49/2216.61	% SZS status Ended for HL400784+5.p
8418.61/2216.76	% SZS status Started for HL400790+4.p
8418.61/2216.76	% SZS status Theorem for HL400790+4.p
8418.61/2216.76	% SZS status Ended for HL400790+4.p
8425.91/2217.63	% SZS status Started for HL400789+4.p
8425.91/2217.63	% SZS status Theorem for HL400789+4.p
8425.91/2217.63	% SZS status Ended for HL400789+4.p
8427.54/2217.90	% SZS status Started for HL400785+5.p
8427.54/2217.90	% SZS status GaveUp for HL400785+5.p
8427.54/2217.90	% SZS status Ended for HL400785+5.p
8431.06/2218.27	% SZS status Started for HL400790+5.p
8431.06/2218.27	% SZS status Theorem for HL400790+5.p
8431.06/2218.27	% SZS status Ended for HL400790+5.p
8432.16/2218.44	% SZS status Started for HL400792+4.p
8432.16/2218.44	% SZS status Theorem for HL400792+4.p
8432.16/2218.44	% SZS status Ended for HL400792+4.p
8433.14/2218.58	% SZS status Started for HL400787+5.p
8433.14/2218.58	% SZS status Theorem for HL400787+5.p
8433.14/2218.58	% SZS status Ended for HL400787+5.p
8434.81/2218.76	% SZS status Started for HL400793+4.p
8434.81/2218.76	% SZS status Theorem for HL400793+4.p
8434.81/2218.76	% SZS status Ended for HL400793+4.p
8435.76/2218.88	% SZS status Started for HL400791+4.p
8435.76/2218.88	% SZS status Theorem for HL400791+4.p
8435.76/2218.88	% SZS status Ended for HL400791+4.p
8436.75/2219.09	% SZS status Started for HL400794+4.p
8436.75/2219.09	% SZS status Theorem for HL400794+4.p
8436.75/2219.09	% SZS status Ended for HL400794+4.p
8444.80/2220.10	% SZS status Started for HL400792+5.p
8444.80/2220.10	% SZS status Theorem for HL400792+5.p
8444.80/2220.10	% SZS status Ended for HL400792+5.p
8445.70/2220.34	% SZS status Started for HL400795+4.p
8445.70/2220.34	% SZS status Theorem for HL400795+4.p
8445.70/2220.34	% SZS status Ended for HL400795+4.p
8447.67/2220.40	% SZS status Started for HL400786+5.p
8447.67/2220.40	% SZS status GaveUp for HL400786+5.p
8447.67/2220.40	% SZS status Ended for HL400786+5.p
8453.44/2221.12	% SZS status Started for HL400788+4.p
8453.44/2221.12	% SZS status GaveUp for HL400788+4.p
8453.44/2221.12	% SZS status Ended for HL400788+4.p
8458.89/2221.88	% SZS status Started for HL400795+5.p
8458.89/2221.88	% SZS status Theorem for HL400795+5.p
8458.89/2221.88	% SZS status Ended for HL400795+5.p
8461.27/2222.11	% SZS status Started for HL400798+4.p
8461.27/2222.11	% SZS status Theorem for HL400798+4.p
8461.27/2222.11	% SZS status Ended for HL400798+4.p
8467.57/2222.91	% SZS status Started for HL400788+5.p
8467.57/2222.91	% SZS status GaveUp for HL400788+5.p
8467.57/2222.91	% SZS status Ended for HL400788+5.p
8468.77/2223.07	% SZS status Started for HL400800+4.p
8468.77/2223.07	% SZS status Theorem for HL400800+4.p
8468.77/2223.07	% SZS status Ended for HL400800+4.p
8474.94/2223.84	% SZS status Started for HL400789+5.p
8474.94/2223.84	% SZS status GaveUp for HL400789+5.p
8474.94/2223.84	% SZS status Ended for HL400789+5.p
8480.39/2224.63	% SZS status Started for HL400800+5.p
8480.39/2224.63	% SZS status Theorem for HL400800+5.p
8480.39/2224.63	% SZS status Ended for HL400800+5.p
8493.59/2226.20	% SZS status Started for HL400791+5.p
8493.59/2226.20	% SZS status GaveUp for HL400791+5.p
8493.59/2226.20	% SZS status Ended for HL400791+5.p
8501.09/2227.11	% SZS status Started for HL400793+5.p
8501.09/2227.11	% SZS status GaveUp for HL400793+5.p
8501.09/2227.11	% SZS status Ended for HL400793+5.p
8502.90/2227.45	% SZS status Started for HL400794+5.p
8502.90/2227.45	% SZS status GaveUp for HL400794+5.p
8502.90/2227.45	% SZS status Ended for HL400794+5.p
8504.97/2227.59	% SZS status Started for HL400803+4.p
8504.97/2227.59	% SZS status Theorem for HL400803+4.p
8504.97/2227.59	% SZS status Ended for HL400803+4.p
8507.59/2228.00	% SZS status Started for HL400798+5.p
8507.59/2228.00	% SZS status Theorem for HL400798+5.p
8507.59/2228.00	% SZS status Ended for HL400798+5.p
8509.50/2228.14	% SZS status Started for HL400805+4.p
8509.50/2228.14	% SZS status Theorem for HL400805+4.p
8509.50/2228.14	% SZS status Ended for HL400805+4.p
8513.85/2228.69	% SZS status Started for HL400796+4.p
8513.85/2228.69	% SZS status GaveUp for HL400796+4.p
8513.85/2228.69	% SZS status Ended for HL400796+4.p
8516.02/2229.10	% SZS status Started for HL400803+5.p
8516.02/2229.10	% SZS status Theorem for HL400803+5.p
8516.02/2229.10	% SZS status Ended for HL400803+5.p
8519.46/2229.43	% SZS status Started for HL400796+5.p
8519.46/2229.43	% SZS status GaveUp for HL400796+5.p
8519.46/2229.43	% SZS status Ended for HL400796+5.p
8522.65/2229.80	% SZS status Started for HL400805+5.p
8522.65/2229.80	% SZS status Theorem for HL400805+5.p
8522.65/2229.80	% SZS status Ended for HL400805+5.p
8540.08/2232.01	% SZS status Started for HL400801+4.p
8540.08/2232.01	% SZS status GaveUp for HL400801+4.p
8540.08/2232.01	% SZS status Ended for HL400801+4.p
8546.18/2232.84	% SZS status Started for HL400808+4.p
8546.18/2232.84	% SZS status Theorem for HL400808+4.p
8546.18/2232.84	% SZS status Ended for HL400808+4.p
8547.23/2232.92	% SZS status Started for HL400801+5.p
8547.23/2232.92	% SZS status GaveUp for HL400801+5.p
8547.23/2232.92	% SZS status Ended for HL400801+5.p
8552.43/2233.55	% SZS status Started for HL400809+4.p
8552.43/2233.55	% SZS status Theorem for HL400809+4.p
8552.43/2233.55	% SZS status Ended for HL400809+4.p
8559.72/2234.42	% SZS status Started for HL400802+4.p
8559.72/2234.42	% SZS status GaveUp for HL400802+4.p
8559.72/2234.42	% SZS status Ended for HL400802+4.p
8568.52/2235.53	% SZS status Started for HL400802+5.p
8568.52/2235.53	% SZS status GaveUp for HL400802+5.p
8568.52/2235.53	% SZS status Ended for HL400802+5.p
8571.44/2235.90	% SZS status Started for HL400811+4.p
8571.44/2235.90	% SZS status Theorem for HL400811+4.p
8571.44/2235.90	% SZS status Ended for HL400811+4.p
8580.21/2237.00	% SZS status Started for HL400806+4.p
8580.21/2237.00	% SZS status GaveUp for HL400806+4.p
8580.21/2237.00	% SZS status Ended for HL400806+4.p
8583.72/2237.43	% SZS status Started for HL400806+5.p
8583.72/2237.43	% SZS status GaveUp for HL400806+5.p
8583.72/2237.43	% SZS status Ended for HL400806+5.p
8584.88/2237.60	% SZS status Started for HL400807+4.p
8584.88/2237.60	% SZS status GaveUp for HL400807+4.p
8584.88/2237.60	% SZS status Ended for HL400807+4.p
8588.83/2238.12	% SZS status Started for HL400807+5.p
8588.83/2238.12	% SZS status GaveUp for HL400807+5.p
8588.83/2238.12	% SZS status Ended for HL400807+5.p
8589.47/2238.22	% SZS status Started for HL400814+4.p
8589.47/2238.22	% SZS status Theorem for HL400814+4.p
8589.47/2238.22	% SZS status Ended for HL400814+4.p
8597.39/2239.15	% SZS status Started for HL400814+5.p
8597.39/2239.15	% SZS status Theorem for HL400814+5.p
8597.39/2239.15	% SZS status Ended for HL400814+5.p
8598.06/2239.30	% SZS status Started for HL400816+4.p
8598.06/2239.30	% SZS status Theorem for HL400816+4.p
8598.06/2239.30	% SZS status Ended for HL400816+4.p
8610.22/2240.81	% SZS status Started for HL400816+5.p
8610.22/2240.81	% SZS status Theorem for HL400816+5.p
8610.22/2240.81	% SZS status Ended for HL400816+5.p
8612.70/2241.26	% SZS status Started for HL400808+5.p
8612.70/2241.26	% SZS status GaveUp for HL400808+5.p
8612.70/2241.26	% SZS status Ended for HL400808+5.p
8614.95/2241.37	% SZS status Started for HL400811+5.p
8614.95/2241.37	% SZS status Theorem for HL400811+5.p
8614.95/2241.37	% SZS status Ended for HL400811+5.p
8614.95/2241.42	% SZS status Started for HL400817+4.p
8614.95/2241.42	% SZS status Theorem for HL400817+4.p
8614.95/2241.42	% SZS status Ended for HL400817+4.p
8615.29/2241.51	% SZS status Started for HL400818+4.p
8615.29/2241.51	% SZS status Theorem for HL400818+4.p
8615.29/2241.51	% SZS status Ended for HL400818+4.p
8615.83/2241.69	% SZS status Started for HL400819+4.p
8615.83/2241.69	% SZS status Theorem for HL400819+4.p
8615.83/2241.69	% SZS status Ended for HL400819+4.p
8616.23/2241.82	% SZS status Started for HL400809+5.p
8616.23/2241.82	% SZS status GaveUp for HL400809+5.p
8616.23/2241.82	% SZS status Ended for HL400809+5.p
8621.72/2242.30	% SZS status Started for HL400820+4.p
8621.72/2242.30	% SZS status Theorem for HL400820+4.p
8621.72/2242.30	% SZS status Ended for HL400820+4.p
8627.51/2242.94	% SZS status Started for HL400818+5.p
8627.51/2242.94	% SZS status Theorem for HL400818+5.p
8627.51/2242.94	% SZS status Ended for HL400818+5.p
8628.45/2243.07	% SZS status Started for HL400821+4.p
8628.45/2243.07	% SZS status Theorem for HL400821+4.p
8628.45/2243.07	% SZS status Ended for HL400821+4.p
8629.65/2243.22	% SZS status Started for HL400819+5.p
8629.65/2243.22	% SZS status Theorem for HL400819+5.p
8629.65/2243.22	% SZS status Ended for HL400819+5.p
8634.38/2243.85	% SZS status Started for HL400822+4.p
8634.38/2243.85	% SZS status Theorem for HL400822+4.p
8634.38/2243.85	% SZS status Ended for HL400822+4.p
8636.54/2244.07	% SZS status Started for HL400812+4.p
8636.54/2244.07	% SZS status GaveUp for HL400812+4.p
8636.54/2244.07	% SZS status Ended for HL400812+4.p
8637.94/2244.26	% SZS status Started for HL400824+4.p
8637.94/2244.26	% SZS status Theorem for HL400824+4.p
8637.94/2244.26	% SZS status Ended for HL400824+4.p
8637.94/2244.26	% SZS status Started for HL400820+5.p
8637.94/2244.26	% SZS status Theorem for HL400820+5.p
8637.94/2244.26	% SZS status Ended for HL400820+5.p
8638.63/2244.43	% SZS status Started for HL400825+4.p
8638.63/2244.43	% SZS status Theorem for HL400825+4.p
8638.63/2244.43	% SZS status Ended for HL400825+4.p
8644.53/2245.11	% SZS status Started for HL400821+5.p
8644.53/2245.11	% SZS status Theorem for HL400821+5.p
8644.53/2245.11	% SZS status Ended for HL400821+5.p
8646.13/2245.29	% SZS status Started for HL400826+4.p
8646.13/2245.29	% SZS status Theorem for HL400826+4.p
8646.13/2245.29	% SZS status Ended for HL400826+4.p
8646.87/2245.40	% SZS status Started for HL400812+5.p
8646.87/2245.40	% SZS status GaveUp for HL400812+5.p
8646.87/2245.40	% SZS status Ended for HL400812+5.p
8647.65/2245.54	% SZS status Started for HL400827+4.p
8647.65/2245.54	% SZS status Theorem for HL400827+4.p
8647.65/2245.54	% SZS status Ended for HL400827+4.p
8650.28/2245.79	% SZS status Started for HL400824+5.p
8650.28/2245.79	% SZS status Theorem for HL400824+5.p
8650.28/2245.79	% SZS status Ended for HL400824+5.p
8650.70/2245.85	% SZS status Started for HL400822+5.p
8650.70/2245.85	% SZS status Theorem for HL400822+5.p
8650.70/2245.85	% SZS status Ended for HL400822+5.p
8651.25/2245.93	% SZS status Started for HL400828+4.p
8651.25/2245.93	% SZS status Theorem for HL400828+4.p
8651.25/2245.93	% SZS status Ended for HL400828+4.p
8652.79/2246.21	% SZS status Started for HL400831+4.p
8652.79/2246.21	% SZS status Theorem for HL400831+4.p
8652.79/2246.21	% SZS status Ended for HL400831+4.p
8654.15/2246.33	% SZS status Started for HL400815+4.p
8654.15/2246.33	% SZS status GaveUp for HL400815+4.p
8654.15/2246.33	% SZS status Ended for HL400815+4.p
8655.62/2246.52	% SZS status Started for HL400815+5.p
8655.62/2246.52	% SZS status GaveUp for HL400815+5.p
8655.62/2246.52	% SZS status Ended for HL400815+5.p
8655.82/2246.58	% SZS status Started for HL400832+4.p
8655.82/2246.58	% SZS status Theorem for HL400832+4.p
8655.82/2246.58	% SZS status Ended for HL400832+4.p
8658.02/2246.83	% SZS status Started for HL400826+5.p
8658.02/2246.83	% SZS status Theorem for HL400826+5.p
8658.02/2246.83	% SZS status Ended for HL400826+5.p
8662.77/2247.37	% SZS status Started for HL400828+5.p
8662.77/2247.37	% SZS status Theorem for HL400828+5.p
8662.77/2247.37	% SZS status Ended for HL400828+5.p
8677.58/2249.24	% SZS status Started for HL400836+4.p
8677.58/2249.24	% SZS status Theorem for HL400836+4.p
8677.58/2249.24	% SZS status Ended for HL400836+4.p
8680.43/2249.59	% SZS status Started for HL400817+5.p
8680.43/2249.59	% SZS status GaveUp for HL400817+5.p
8680.43/2249.59	% SZS status Ended for HL400817+5.p
8681.55/2249.79	% SZS status Started for HL400837+4.p
8681.55/2249.79	% SZS status Theorem for HL400837+4.p
8681.55/2249.79	% SZS status Ended for HL400837+4.p
8693.94/2251.33	% SZS status Started for HL400827+5.p
8693.94/2251.33	% SZS status Theorem for HL400827+5.p
8693.94/2251.33	% SZS status Ended for HL400827+5.p
8704.43/2252.73	% SZS status Started for HL400825+5.p
8704.43/2252.73	% SZS status GaveUp for HL400825+5.p
8704.43/2252.73	% SZS status Ended for HL400825+5.p
8719.39/2254.50	% SZS status Started for HL400831+5.p
8719.39/2254.50	% SZS status GaveUp for HL400831+5.p
8719.39/2254.50	% SZS status Ended for HL400831+5.p
8721.18/2254.81	% SZS status Started for HL400832+5.p
8721.18/2254.81	% SZS status GaveUp for HL400832+5.p
8721.18/2254.81	% SZS status Ended for HL400832+5.p
8721.86/2254.87	% SZS status Started for HL400835+4.p
8721.86/2254.87	% SZS status GaveUp for HL400835+4.p
8721.86/2254.87	% SZS status Ended for HL400835+4.p
8724.21/2255.10	% SZS status Started for HL400839+4.p
8724.21/2255.10	% SZS status Theorem for HL400839+4.p
8724.21/2255.10	% SZS status Ended for HL400839+4.p
8724.21/2255.12	% SZS status Started for HL400835+5.p
8724.21/2255.12	% SZS status GaveUp for HL400835+5.p
8724.21/2255.12	% SZS status Ended for HL400835+5.p
8726.40/2255.51	% SZS status Started for HL400840+4.p
8726.40/2255.51	% SZS status Theorem for HL400840+4.p
8726.40/2255.51	% SZS status Ended for HL400840+4.p
8729.51/2255.76	% SZS status Started for HL400841+4.p
8729.51/2255.76	% SZS status Theorem for HL400841+4.p
8729.51/2255.76	% SZS status Ended for HL400841+4.p
8729.93/2255.82	% SZS status Started for HL400837+5.p
8729.93/2255.82	% SZS status Theorem for HL400837+5.p
8729.93/2255.82	% SZS status Ended for HL400837+5.p
8730.18/2255.90	% SZS status Started for HL400842+4.p
8730.18/2255.90	% SZS status Theorem for HL400842+4.p
8730.18/2255.90	% SZS status Ended for HL400842+4.p
8735.16/2256.54	% SZS status Started for HL400843+4.p
8735.16/2256.54	% SZS status Theorem for HL400843+4.p
8735.16/2256.54	% SZS status Ended for HL400843+4.p
8742.16/2257.36	% SZS status Started for HL400842+5.p
8742.16/2257.36	% SZS status Theorem for HL400842+5.p
8742.16/2257.36	% SZS status Ended for HL400842+5.p
8743.23/2257.53	% SZS status Started for HL400836+5.p
8743.23/2257.53	% SZS status GaveUp for HL400836+5.p
8743.23/2257.53	% SZS status Ended for HL400836+5.p
8759.78/2259.57	% SZS status Started for HL400838+4.p
8759.78/2259.57	% SZS status GaveUp for HL400838+4.p
8759.78/2259.57	% SZS status Ended for HL400838+4.p
8770.35/2261.02	% SZS status Started for HL400838+5.p
8770.35/2261.02	% SZS status GaveUp for HL400838+5.p
8770.35/2261.02	% SZS status Ended for HL400838+5.p
8786.87/2263.10	% SZS status Started for HL400839+5.p
8786.87/2263.10	% SZS status GaveUp for HL400839+5.p
8786.87/2263.10	% SZS status Ended for HL400839+5.p
8790.37/2263.40	% SZS status Started for HL400840+5.p
8790.37/2263.40	% SZS status GaveUp for HL400840+5.p
8790.37/2263.40	% SZS status Ended for HL400840+5.p
8794.13/2263.89	% SZS status Started for HL400846+4.p
8794.13/2263.89	% SZS status Theorem for HL400846+4.p
8794.13/2263.89	% SZS status Ended for HL400846+4.p
8794.13/2263.91	% SZS status Started for HL400841+5.p
8794.13/2263.91	% SZS status GaveUp for HL400841+5.p
8794.13/2263.91	% SZS status Ended for HL400841+5.p
8801.38/2264.89	% SZS status Started for HL400843+5.p
8801.38/2264.89	% SZS status GaveUp for HL400843+5.p
8801.38/2264.89	% SZS status Ended for HL400843+5.p
8803.52/2265.04	% SZS status Started for HL400848+4.p
8803.52/2265.04	% SZS status Theorem for HL400848+4.p
8803.52/2265.04	% SZS status Ended for HL400848+4.p
8806.94/2265.52	% SZS status Started for HL400844+4.p
8806.94/2265.52	% SZS status GaveUp for HL400844+4.p
8806.94/2265.52	% SZS status Ended for HL400844+4.p
8808.85/2265.83	% SZS status Started for HL400844+5.p
8808.85/2265.83	% SZS status GaveUp for HL400844+5.p
8808.85/2265.83	% SZS status Ended for HL400844+5.p
8811.74/2266.13	% SZS status Started for HL400849+4.p
8811.74/2266.13	% SZS status Theorem for HL400849+4.p
8811.74/2266.13	% SZS status Ended for HL400849+4.p
8818.86/2267.11	% SZS status Started for HL400850+4.p
8818.86/2267.11	% SZS status Theorem for HL400850+4.p
8818.86/2267.11	% SZS status Ended for HL400850+4.p
8825.29/2267.82	% SZS status Started for HL400845+4.p
8825.29/2267.82	% SZS status GaveUp for HL400845+4.p
8825.29/2267.82	% SZS status Ended for HL400845+4.p
8826.70/2267.96	% SZS status Started for HL400851+4.p
8826.70/2267.96	% SZS status Theorem for HL400851+4.p
8826.70/2267.96	% SZS status Ended for HL400851+4.p
8836.48/2269.32	% SZS status Started for HL400845+5.p
8836.48/2269.32	% SZS status GaveUp for HL400845+5.p
8836.48/2269.32	% SZS status Ended for HL400845+5.p
8847.24/2270.56	% SZS status Started for HL400847+4.p
8847.24/2270.56	% SZS status Theorem for HL400847+4.p
8847.24/2270.56	% SZS status Ended for HL400847+4.p
8856.34/2271.70	% SZS status Started for HL400846+5.p
8856.34/2271.70	% SZS status GaveUp for HL400846+5.p
8856.34/2271.70	% SZS status Ended for HL400846+5.p
8860.04/2272.17	% SZS status Started for HL400852+5.p
8860.04/2272.17	% SZS status Theorem for HL400852+5.p
8860.04/2272.17	% SZS status Ended for HL400852+5.p
8860.37/2272.21	% SZS status Started for HL400847+5.p
8860.37/2272.21	% SZS status GaveUp for HL400847+5.p
8860.37/2272.21	% SZS status Ended for HL400847+5.p
8861.20/2272.39	% SZS status Started for HL400854+4.p
8861.20/2272.39	% SZS status Theorem for HL400854+4.p
8861.20/2272.39	% SZS status Ended for HL400854+4.p
8869.92/2273.42	% SZS status Started for HL400848+5.p
8869.92/2273.42	% SZS status GaveUp for HL400848+5.p
8869.92/2273.42	% SZS status Ended for HL400848+5.p
8872.99/2273.79	% SZS status Started for HL400853+5.p
8872.99/2273.79	% SZS status Theorem for HL400853+5.p
8872.99/2273.79	% SZS status Ended for HL400853+5.p
8875.40/2274.15	% SZS status Started for HL400849+5.p
8875.40/2274.15	% SZS status GaveUp for HL400849+5.p
8875.40/2274.15	% SZS status Ended for HL400849+5.p
8879.55/2274.72	% SZS status Started for HL400852+4.p
8879.55/2274.72	% SZS status Theorem for HL400852+4.p
8879.55/2274.72	% SZS status Ended for HL400852+4.p
8885.74/2275.42	% SZS status Started for HL400850+5.p
8885.74/2275.42	% SZS status GaveUp for HL400850+5.p
8885.74/2275.42	% SZS status Ended for HL400850+5.p
8892.63/2276.30	% SZS status Started for HL400851+5.p
8892.63/2276.30	% SZS status GaveUp for HL400851+5.p
8892.63/2276.30	% SZS status Ended for HL400851+5.p
8911.13/2278.65	% SZS status Started for HL400856+4.p
8911.13/2278.65	% SZS status Theorem for HL400856+4.p
8911.13/2278.65	% SZS status Ended for HL400856+4.p
8921.20/2279.87	% SZS status Started for HL400853+4.p
8921.20/2279.87	% SZS status GaveUp for HL400853+4.p
8921.20/2279.87	% SZS status Ended for HL400853+4.p
8927.64/2280.71	% SZS status Started for HL400854+5.p
8927.64/2280.71	% SZS status GaveUp for HL400854+5.p
8927.64/2280.71	% SZS status Ended for HL400854+5.p
8929.57/2280.88	% SZS status Started for HL400864+4.p
8929.57/2280.88	% SZS status Theorem for HL400864+4.p
8929.57/2280.88	% SZS status Ended for HL400864+4.p
8935.12/2281.61	% SZS status Started for HL400855+4.p
8935.12/2281.61	% SZS status GaveUp for HL400855+4.p
8935.12/2281.61	% SZS status Ended for HL400855+4.p
8936.23/2281.84	% SZS status Started for HL400865+4.p
8936.23/2281.84	% SZS status Theorem for HL400865+4.p
8936.23/2281.84	% SZS status Ended for HL400865+4.p
8939.42/2282.17	% SZS status Started for HL400855+5.p
8939.42/2282.17	% SZS status GaveUp for HL400855+5.p
8939.42/2282.17	% SZS status Ended for HL400855+5.p
8940.37/2282.41	% SZS status Started for HL400864+5.p
8940.37/2282.41	% SZS status Theorem for HL400864+5.p
8940.37/2282.41	% SZS status Ended for HL400864+5.p
8946.94/2283.07	% SZS status Started for HL400856+5.p
8946.94/2283.07	% SZS status GaveUp for HL400856+5.p
8946.94/2283.07	% SZS status Ended for HL400856+5.p
8949.81/2283.62	% SZS status Started for HL400860+4.p
8949.81/2283.62	% SZS status GaveUp for HL400860+4.p
8949.81/2283.62	% SZS status Ended for HL400860+4.p
8958.37/2284.61	% SZS status Started for HL400860+5.p
8958.37/2284.61	% SZS status GaveUp for HL400860+5.p
8958.37/2284.61	% SZS status Ended for HL400860+5.p
8977.79/2286.95	% SZS status Started for HL400861+4.p
8977.79/2286.95	% SZS status GaveUp for HL400861+4.p
8977.79/2286.95	% SZS status Ended for HL400861+4.p
8987.93/2288.27	% SZS status Started for HL400861+5.p
8987.93/2288.27	% SZS status GaveUp for HL400861+5.p
8987.93/2288.27	% SZS status Ended for HL400861+5.p
9002.04/2290.12	% SZS status Started for HL400865+5.p
9002.04/2290.12	% SZS status GaveUp for HL400865+5.p
9002.04/2290.12	% SZS status Ended for HL400865+5.p
9005.18/2290.43	% SZS status Started for HL400866+4.p
9005.18/2290.43	% SZS status GaveUp for HL400866+4.p
9005.18/2290.43	% SZS status Ended for HL400866+4.p
9006.77/2290.70	% SZS status Started for HL400866+5.p
9006.77/2290.70	% SZS status GaveUp for HL400866+5.p
9006.77/2290.70	% SZS status Ended for HL400866+5.p
9011.54/2291.31	% SZS status Started for HL400868+4.p
9011.54/2291.31	% SZS status GaveUp for HL400868+4.p
9011.54/2291.31	% SZS status Ended for HL400868+4.p
9017.93/2292.02	% SZS status Started for HL400868+5.p
9017.93/2292.02	% SZS status GaveUp for HL400868+5.p
9017.93/2292.02	% SZS status Ended for HL400868+5.p
9023.71/2292.84	% SZS status Started for HL400869+4.p
9023.71/2292.84	% SZS status GaveUp for HL400869+4.p
9023.71/2292.84	% SZS status Ended for HL400869+4.p
9042.67/2295.15	% SZS status Started for HL400870+4.p
9042.67/2295.15	% SZS status Theorem for HL400870+4.p
9042.67/2295.15	% SZS status Ended for HL400870+4.p
9044.10/2295.28	% SZS status Started for HL400869+5.p
9044.10/2295.28	% SZS status GaveUp for HL400869+5.p
9044.10/2295.28	% SZS status Ended for HL400869+5.p
9068.24/2298.44	% SZS status Started for HL400870+5.p
9068.24/2298.44	% SZS status GaveUp for HL400870+5.p
9068.24/2298.44	% SZS status Ended for HL400870+5.p
9070.78/2298.71	% SZS status Started for HL400871+4.p
9070.78/2298.71	% SZS status GaveUp for HL400871+4.p
9070.78/2298.71	% SZS status Ended for HL400871+4.p
9071.80/2298.84	% SZS status Started for HL400877+4.p
9071.80/2298.84	% SZS status Theorem for HL400877+4.p
9071.80/2298.84	% SZS status Ended for HL400877+4.p
9072.52/2299.00	% SZS status Started for HL400871+5.p
9072.52/2299.00	% SZS status GaveUp for HL400871+5.p
9072.52/2299.00	% SZS status Ended for HL400871+5.p
9077.16/2299.52	% SZS status Started for HL400872+4.p
9077.16/2299.52	% SZS status GaveUp for HL400872+4.p
9077.16/2299.52	% SZS status Ended for HL400872+4.p
9085.38/2300.46	% SZS status Started for HL400872+5.p
9085.38/2300.46	% SZS status GaveUp for HL400872+5.p
9085.38/2300.46	% SZS status Ended for HL400872+5.p
9088.70/2300.89	% SZS status Started for HL400880+4.p
9088.70/2300.89	% SZS status Theorem for HL400880+4.p
9088.70/2300.89	% SZS status Ended for HL400880+4.p
9089.41/2301.02	% SZS status Started for HL400873+4.p
9089.41/2301.02	% SZS status GaveUp for HL400873+4.p
9089.41/2301.02	% SZS status Ended for HL400873+4.p
9101.39/2302.41	% SZS status Started for HL400880+5.p
9101.39/2302.41	% SZS status Theorem for HL400880+5.p
9101.39/2302.41	% SZS status Ended for HL400880+5.p
9109.80/2303.44	% SZS status Started for HL400873+5.p
9109.80/2303.44	% SZS status GaveUp for HL400873+5.p
9109.80/2303.44	% SZS status Ended for HL400873+5.p
9110.04/2303.50	% SZS status Started for HL400875+4.p
9110.04/2303.50	% SZS status GaveUp for HL400875+4.p
9110.04/2303.50	% SZS status Ended for HL400875+4.p
9111.65/2303.80	% SZS status Started for HL400882+4.p
9111.65/2303.80	% SZS status Theorem for HL400882+4.p
9111.65/2303.80	% SZS status Ended for HL400882+4.p
9118.71/2304.55	% SZS status Started for HL400877+5.p
9118.71/2304.55	% SZS status Theorem for HL400877+5.p
9118.71/2304.55	% SZS status Ended for HL400877+5.p
9122.92/2305.08	% SZS status Started for HL400882+5.p
9122.92/2305.08	% SZS status Theorem for HL400882+5.p
9122.92/2305.08	% SZS status Ended for HL400882+5.p
9134.30/2306.73	% SZS status Started for HL400875+5.p
9134.30/2306.73	% SZS status GaveUp for HL400875+5.p
9134.30/2306.73	% SZS status Ended for HL400875+5.p
9138.89/2307.25	% SZS status Started for HL400879+4.p
9138.89/2307.25	% SZS status GaveUp for HL400879+4.p
9138.89/2307.25	% SZS status Ended for HL400879+4.p
9142.22/2307.54	% SZS status Started for HL400884+4.p
9142.22/2307.54	% SZS status Theorem for HL400884+4.p
9142.22/2307.54	% SZS status Ended for HL400884+4.p
9143.67/2307.81	% SZS status Started for HL400879+5.p
9143.67/2307.81	% SZS status GaveUp for HL400879+5.p
9143.67/2307.81	% SZS status Ended for HL400879+5.p
9149.21/2308.43	% SZS status Started for HL400884+5.p
9149.21/2308.43	% SZS status Theorem for HL400884+5.p
9149.21/2308.43	% SZS status Ended for HL400884+5.p
9154.96/2309.20	% SZS status Started for HL400881+4.p
9154.96/2309.20	% SZS status GaveUp for HL400881+4.p
9154.96/2309.20	% SZS status Ended for HL400881+4.p
9155.41/2309.27	% SZS status Started for HL400885+5.p
9155.41/2309.27	% SZS status Theorem for HL400885+5.p
9155.41/2309.27	% SZS status Ended for HL400885+5.p
9159.36/2309.70	% SZS status Started for HL400885+4.p
9159.36/2309.70	% SZS status Theorem for HL400885+4.p
9159.36/2309.70	% SZS status Ended for HL400885+4.p
9168.28/2310.80	% SZS status Started for HL400881+5.p
9168.28/2310.80	% SZS status GaveUp for HL400881+5.p
9168.28/2310.80	% SZS status Ended for HL400881+5.p
9177.54/2311.97	% SZS status Started for HL400883+4.p
9177.54/2311.97	% SZS status GaveUp for HL400883+4.p
9177.54/2311.97	% SZS status Ended for HL400883+4.p
9185.05/2312.92	% SZS status Started for HL400883+5.p
9185.05/2312.92	% SZS status GaveUp for HL400883+5.p
9185.05/2312.92	% SZS status Ended for HL400883+5.p
9209.45/2316.00	% SZS status Started for HL400886+4.p
9209.45/2316.00	% SZS status GaveUp for HL400886+4.p
9209.45/2316.00	% SZS status Ended for HL400886+4.p
9215.78/2316.74	% SZS status Started for HL400886+5.p
9215.78/2316.74	% SZS status GaveUp for HL400886+5.p
9215.78/2316.74	% SZS status Ended for HL400886+5.p
9220.63/2317.42	% SZS status Started for HL400887+4.p
9220.63/2317.42	% SZS status GaveUp for HL400887+4.p
9220.63/2317.42	% SZS status Ended for HL400887+4.p
9221.73/2317.56	% SZS status Started for HL400887+5.p
9221.73/2317.56	% SZS status GaveUp for HL400887+5.p
9221.73/2317.56	% SZS status Ended for HL400887+5.p
9225.40/2318.00	% SZS status Started for HL400888+4.p
9225.40/2318.00	% SZS status GaveUp for HL400888+4.p
9225.40/2318.00	% SZS status Ended for HL400888+4.p
9232.41/2318.86	% SZS status Started for HL400892+4.p
9232.41/2318.86	% SZS status Theorem for HL400892+4.p
9232.41/2318.86	% SZS status Ended for HL400892+4.p
9234.26/2319.13	% SZS status Started for HL400888+5.p
9234.26/2319.13	% SZS status GaveUp for HL400888+5.p
9234.26/2319.13	% SZS status Ended for HL400888+5.p
9242.81/2320.19	% SZS status Started for HL400889+4.p
9242.81/2320.19	% SZS status GaveUp for HL400889+4.p
9242.81/2320.19	% SZS status Ended for HL400889+4.p
9243.80/2320.40	% SZS status Started for HL400892+5.p
9243.80/2320.40	% SZS status Theorem for HL400892+5.p
9243.80/2320.40	% SZS status Ended for HL400892+5.p
9245.99/2320.55	% SZS status Started for HL400894+4.p
9245.99/2320.55	% SZS status Theorem for HL400894+4.p
9245.99/2320.55	% SZS status Ended for HL400894+4.p
9251.67/2321.31	% SZS status Started for HL400889+5.p
9251.67/2321.31	% SZS status GaveUp for HL400889+5.p
9251.67/2321.31	% SZS status Ended for HL400889+5.p
9275.14/2324.28	% SZS status Started for HL400890+4.p
9275.14/2324.28	% SZS status GaveUp for HL400890+4.p
9275.14/2324.28	% SZS status Ended for HL400890+4.p
9281.40/2325.04	% SZS status Started for HL400890+5.p
9281.40/2325.04	% SZS status GaveUp for HL400890+5.p
9281.40/2325.04	% SZS status Ended for HL400890+5.p
9285.87/2325.58	% SZS status Started for HL400891+4.p
9285.87/2325.58	% SZS status GaveUp for HL400891+4.p
9285.87/2325.58	% SZS status Ended for HL400891+4.p
9289.74/2326.03	% SZS status Started for HL400891+5.p
9289.74/2326.03	% SZS status GaveUp for HL400891+5.p
9289.74/2326.03	% SZS status Ended for HL400891+5.p
9299.37/2327.30	% SZS status Started for HL400893+4.p
9299.37/2327.30	% SZS status GaveUp for HL400893+4.p
9299.37/2327.30	% SZS status Ended for HL400893+4.p
9308.45/2328.51	% SZS status Started for HL400893+5.p
9308.45/2328.51	% SZS status GaveUp for HL400893+5.p
9308.45/2328.51	% SZS status Ended for HL400893+5.p
9312.07/2328.86	% SZS status Started for HL400894+5.p
9312.07/2328.86	% SZS status GaveUp for HL400894+5.p
9312.07/2328.86	% SZS status Ended for HL400894+5.p
9317.43/2329.54	% SZS status Started for HL400895+4.p
9317.43/2329.54	% SZS status GaveUp for HL400895+4.p
9317.43/2329.54	% SZS status Ended for HL400895+4.p
9342.26/2332.65	% SZS status Started for HL400895+5.p
9342.26/2332.65	% SZS status GaveUp for HL400895+5.p
9342.26/2332.65	% SZS status Ended for HL400895+5.p
9347.14/2333.25	% SZS status Started for HL400896+4.p
9347.14/2333.25	% SZS status GaveUp for HL400896+4.p
9347.14/2333.25	% SZS status Ended for HL400896+4.p
9351.74/2333.88	% SZS status Started for HL400896+5.p
9351.74/2333.88	% SZS status GaveUp for HL400896+5.p
9351.74/2333.88	% SZS status Ended for HL400896+5.p
9355.29/2334.28	% SZS status Started for HL400898+4.p
9355.29/2334.28	% SZS status GaveUp for HL400898+4.p
9355.29/2334.28	% SZS status Ended for HL400898+4.p
9365.14/2335.59	% SZS status Started for HL400898+5.p
9365.14/2335.59	% SZS status GaveUp for HL400898+5.p
9365.14/2335.59	% SZS status Ended for HL400898+5.p
9374.75/2336.73	% SZS status Started for HL400899+4.p
9374.75/2336.73	% SZS status GaveUp for HL400899+4.p
9374.75/2336.73	% SZS status Ended for HL400899+4.p
9378.05/2337.16	% SZS status Started for HL400899+5.p
9378.05/2337.16	% SZS status GaveUp for HL400899+5.p
9378.05/2337.16	% SZS status Ended for HL400899+5.p
9383.50/2337.85	% SZS status Started for HL400900+4.p
9383.50/2337.85	% SZS status GaveUp for HL400900+4.p
9383.50/2337.85	% SZS status Ended for HL400900+4.p
9386.05/2338.16	% SZS status Started for HL400906+4.p
9386.05/2338.16	% SZS status Theorem for HL400906+4.p
9386.05/2338.16	% SZS status Ended for HL400906+4.p
9408.57/2341.01	% SZS status Started for HL400900+5.p
9408.57/2341.01	% SZS status GaveUp for HL400900+5.p
9408.57/2341.01	% SZS status Ended for HL400900+5.p
9412.28/2341.45	% SZS status Started for HL400901+4.p
9412.28/2341.45	% SZS status GaveUp for HL400901+4.p
9412.28/2341.45	% SZS status Ended for HL400901+4.p
9413.23/2341.68	% SZS status Started for HL400908+4.p
9413.23/2341.68	% SZS status Theorem for HL400908+4.p
9413.23/2341.68	% SZS status Ended for HL400908+4.p
9418.02/2342.17	% SZS status Started for HL400901+5.p
9418.02/2342.17	% SZS status GaveUp for HL400901+5.p
9418.02/2342.17	% SZS status Ended for HL400901+5.p
9420.53/2342.47	% SZS status Started for HL400904+4.p
9420.53/2342.47	% SZS status GaveUp for HL400904+4.p
9420.53/2342.47	% SZS status Ended for HL400904+4.p
9431.08/2343.88	% SZS status Started for HL400904+5.p
9431.08/2343.88	% SZS status GaveUp for HL400904+5.p
9431.08/2343.88	% SZS status Ended for HL400904+5.p
9434.11/2344.18	% SZS status Started for HL400906+5.p
9434.11/2344.18	% SZS status Theorem for HL400906+5.p
9434.11/2344.18	% SZS status Ended for HL400906+5.p
9439.71/2344.94	% SZS status Started for HL400905+4.p
9439.71/2344.94	% SZS status GaveUp for HL400905+4.p
9439.71/2344.94	% SZS status Ended for HL400905+4.p
9444.42/2345.56	% SZS status Started for HL400905+5.p
9444.42/2345.56	% SZS status GaveUp for HL400905+5.p
9444.42/2345.56	% SZS status Ended for HL400905+5.p
9474.45/2349.32	% SZS status Started for HL400910+4.p
9474.45/2349.32	% SZS status Theorem for HL400910+4.p
9474.45/2349.32	% SZS status Ended for HL400910+4.p
9479.11/2349.85	% SZS status Started for HL400908+5.p
9479.11/2349.85	% SZS status GaveUp for HL400908+5.p
9479.11/2349.85	% SZS status Ended for HL400908+5.p
9479.30/2349.86	% SZS status Started for HL400909+4.p
9479.30/2349.86	% SZS status GaveUp for HL400909+4.p
9479.30/2349.86	% SZS status Ended for HL400909+4.p
9483.80/2350.46	% SZS status Started for HL400909+5.p
9483.80/2350.46	% SZS status GaveUp for HL400909+5.p
9483.80/2350.46	% SZS status Ended for HL400909+5.p
9486.67/2350.78	% SZS status Started for HL400911+4.p
9486.67/2350.78	% SZS status Theorem for HL400911+4.p
9486.67/2350.78	% SZS status Ended for HL400911+4.p
9497.10/2352.24	% SZS status Started for HL400910+5.p
9497.10/2352.24	% SZS status GaveUp for HL400910+5.p
9497.10/2352.24	% SZS status Ended for HL400910+5.p
9505.76/2353.23	% SZS status Started for HL400911+5.p
9505.76/2353.23	% SZS status GaveUp for HL400911+5.p
9505.76/2353.23	% SZS status Ended for HL400911+5.p
9510.10/2353.82	% SZS status Started for HL400912+4.p
9510.10/2353.82	% SZS status GaveUp for HL400912+4.p
9510.10/2353.82	% SZS status Ended for HL400912+4.p
9518.27/2354.77	% SZS status Started for HL400916+4.p
9518.27/2354.77	% SZS status Theorem for HL400916+4.p
9518.27/2354.77	% SZS status Ended for HL400916+4.p
9518.27/2354.78	% SZS status Started for HL400915+5.p
9518.27/2354.78	% SZS status Theorem for HL400915+5.p
9518.27/2354.78	% SZS status Ended for HL400915+5.p
9537.15/2357.31	% SZS status Started for HL400915+4.p
9537.15/2357.31	% SZS status Theorem for HL400915+4.p
9537.15/2357.31	% SZS status Ended for HL400915+4.p
9540.42/2357.61	% SZS status Started for HL400912+5.p
9540.42/2357.61	% SZS status GaveUp for HL400912+5.p
9540.42/2357.61	% SZS status Ended for HL400912+5.p
9544.44/2358.11	% SZS status Started for HL400913+4.p
9544.44/2358.11	% SZS status GaveUp for HL400913+4.p
9544.44/2358.11	% SZS status Ended for HL400913+4.p
9544.95/2358.19	% SZS status Started for HL400913+5.p
9544.95/2358.19	% SZS status GaveUp for HL400913+5.p
9544.95/2358.19	% SZS status Ended for HL400913+5.p
9549.56/2358.74	% SZS status Started for HL400914+4.p
9549.56/2358.74	% SZS status GaveUp for HL400914+4.p
9549.56/2358.74	% SZS status Ended for HL400914+4.p
9550.50/2358.90	% SZS status Started for HL400919+4.p
9550.50/2358.90	% SZS status Theorem for HL400919+4.p
9550.50/2358.90	% SZS status Ended for HL400919+4.p
9552.62/2359.13	% SZS status Started for HL400914+5.p
9552.62/2359.13	% SZS status GaveUp for HL400914+5.p
9552.62/2359.13	% SZS status Ended for HL400914+5.p
9553.19/2359.17	% SZS status Started for HL400918+4.p
9553.19/2359.17	% SZS status Theorem for HL400918+4.p
9553.19/2359.17	% SZS status Ended for HL400918+4.p
9583.46/2362.97	% SZS status Started for HL400917+4.p
9583.46/2362.97	% SZS status GaveUp for HL400917+4.p
9583.46/2362.97	% SZS status Ended for HL400917+4.p
9584.36/2363.11	% SZS status Started for HL400916+5.p
9584.36/2363.11	% SZS status GaveUp for HL400916+5.p
9584.36/2363.11	% SZS status Ended for HL400916+5.p
9604.81/2365.66	% SZS status Started for HL400917+5.p
9604.81/2365.66	% SZS status GaveUp for HL400917+5.p
9604.81/2365.66	% SZS status Ended for HL400917+5.p
9610.49/2366.45	% SZS status Started for HL400918+5.p
9610.49/2366.45	% SZS status GaveUp for HL400918+5.p
9610.49/2366.45	% SZS status Ended for HL400918+5.p
9615.79/2367.04	% SZS status Started for HL400925+4.p
9615.79/2367.04	% SZS status Theorem for HL400925+4.p
9615.79/2367.04	% SZS status Ended for HL400925+4.p
9616.05/2367.11	% SZS status Started for HL400920+4.p
9616.05/2367.11	% SZS status GaveUp for HL400920+4.p
9616.05/2367.11	% SZS status Ended for HL400920+4.p
9616.47/2367.16	% SZS status Started for HL400919+5.p
9616.47/2367.16	% SZS status GaveUp for HL400919+5.p
9616.47/2367.16	% SZS status Ended for HL400919+5.p
9618.60/2367.38	% SZS status Started for HL400922+4.p
9618.60/2367.38	% SZS status GaveUp for HL400922+4.p
9618.60/2367.38	% SZS status Ended for HL400922+4.p
9618.91/2367.43	% SZS status Started for HL400920+5.p
9618.91/2367.43	% SZS status GaveUp for HL400920+5.p
9618.91/2367.43	% SZS status Ended for HL400920+5.p
9619.95/2367.72	% SZS status Started for HL400926+4.p
9619.95/2367.72	% SZS status Theorem for HL400926+4.p
9619.95/2367.72	% SZS status Ended for HL400926+4.p
9650.36/2371.36	% SZS status Started for HL400923+4.p
9650.36/2371.36	% SZS status GaveUp for HL400923+4.p
9650.36/2371.36	% SZS status Ended for HL400923+4.p
9650.36/2371.37	% SZS status Started for HL400922+5.p
9650.36/2371.37	% SZS status GaveUp for HL400922+5.p
9650.36/2371.37	% SZS status Ended for HL400922+5.p
9671.27/2374.01	% SZS status Started for HL400923+5.p
9671.27/2374.01	% SZS status GaveUp for HL400923+5.p
9671.27/2374.01	% SZS status Ended for HL400923+5.p
9675.32/2374.50	% SZS status Started for HL400927+4.p
9675.32/2374.50	% SZS status Theorem for HL400927+4.p
9675.32/2374.50	% SZS status Ended for HL400927+4.p
9681.17/2375.33	% SZS status Started for HL400925+5.p
9681.17/2375.33	% SZS status GaveUp for HL400925+5.p
9681.17/2375.33	% SZS status Ended for HL400925+5.p
9682.12/2375.46	% SZS status Started for HL400926+5.p
9682.12/2375.46	% SZS status GaveUp for HL400926+5.p
9682.12/2375.46	% SZS status Ended for HL400926+5.p
9683.63/2375.52	% SZS status Started for HL400930+4.p
9683.63/2375.52	% SZS status Theorem for HL400930+4.p
9683.63/2375.52	% SZS status Ended for HL400930+4.p
9684.61/2375.73	% SZS status Started for HL400927+5.p
9684.61/2375.73	% SZS status GaveUp for HL400927+5.p
9684.61/2375.73	% SZS status Ended for HL400927+5.p
9685.42/2375.99	% SZS status Started for HL400928+4.p
9685.42/2375.99	% SZS status GaveUp for HL400928+4.p
9685.42/2375.99	% SZS status Ended for HL400928+4.p
9705.45/2378.28	% SZS status Started for HL400933+4.p
9705.45/2378.28	% SZS status Theorem for HL400933+4.p
9705.45/2378.28	% SZS status Ended for HL400933+4.p
9716.03/2379.65	% SZS status Started for HL400929+4.p
9716.03/2379.65	% SZS status GaveUp for HL400929+4.p
9716.03/2379.65	% SZS status Ended for HL400929+4.p
9716.25/2379.70	% SZS status Started for HL400928+5.p
9716.25/2379.70	% SZS status GaveUp for HL400928+5.p
9716.25/2379.70	% SZS status Ended for HL400928+5.p
9737.87/2382.37	% SZS status Started for HL400929+5.p
9737.87/2382.37	% SZS status GaveUp for HL400929+5.p
9737.87/2382.37	% SZS status Ended for HL400929+5.p
9747.59/2383.66	% SZS status Started for HL400932+4.p
9747.59/2383.66	% SZS status GaveUp for HL400932+4.p
9747.59/2383.66	% SZS status Ended for HL400932+4.p
9747.77/2383.67	% SZS status Started for HL400930+5.p
9747.77/2383.67	% SZS status GaveUp for HL400930+5.p
9747.77/2383.67	% SZS status Ended for HL400930+5.p
9749.95/2383.88	% SZS status Started for HL400932+5.p
9749.95/2383.88	% SZS status GaveUp for HL400932+5.p
9749.95/2383.88	% SZS status Ended for HL400932+5.p
9753.19/2384.33	% SZS status Started for HL400933+5.p
9753.19/2384.33	% SZS status GaveUp for HL400933+5.p
9753.19/2384.33	% SZS status Ended for HL400933+5.p
9770.75/2386.53	% SZS status Started for HL400934+4.p
9770.75/2386.53	% SZS status GaveUp for HL400934+4.p
9770.75/2386.53	% SZS status Ended for HL400934+4.p
9781.03/2387.89	% SZS status Started for HL400935+4.p
9781.03/2387.89	% SZS status GaveUp for HL400935+4.p
9781.03/2387.89	% SZS status Ended for HL400935+4.p
9781.33/2387.95	% SZS status Started for HL400934+5.p
9781.33/2387.95	% SZS status GaveUp for HL400934+5.p
9781.33/2387.95	% SZS status Ended for HL400934+5.p
9803.80/2390.66	% SZS status Started for HL400935+5.p
9803.80/2390.66	% SZS status GaveUp for HL400935+5.p
9803.80/2390.66	% SZS status Ended for HL400935+5.p
9806.24/2390.98	% SZS status Started for HL400940+4.p
9806.24/2390.98	% SZS status Theorem for HL400940+4.p
9806.24/2390.98	% SZS status Ended for HL400940+4.p
9813.51/2391.91	% SZS status Started for HL400936+4.p
9813.51/2391.91	% SZS status GaveUp for HL400936+4.p
9813.51/2391.91	% SZS status Ended for HL400936+4.p
9814.46/2391.97	% SZS status Started for HL400936+5.p
9814.46/2391.97	% SZS status GaveUp for HL400936+5.p
9814.46/2391.97	% SZS status Ended for HL400936+5.p
9815.23/2392.08	% SZS status Started for HL400937+4.p
9815.23/2392.08	% SZS status GaveUp for HL400937+4.p
9815.23/2392.08	% SZS status Ended for HL400937+4.p
9820.86/2392.78	% SZS status Started for HL400937+5.p
9820.86/2392.78	% SZS status GaveUp for HL400937+5.p
9820.86/2392.78	% SZS status Ended for HL400937+5.p
9823.72/2393.14	% SZS status Started for HL400943+4.p
9823.72/2393.14	% SZS status Theorem for HL400943+4.p
9823.72/2393.14	% SZS status Ended for HL400943+4.p
9836.73/2394.81	% SZS status Started for HL400938+4.p
9836.73/2394.81	% SZS status GaveUp for HL400938+4.p
9836.73/2394.81	% SZS status Ended for HL400938+4.p
9839.32/2395.18	% SZS status Started for HL400945+4.p
9839.32/2395.18	% SZS status Theorem for HL400945+4.p
9839.32/2395.18	% SZS status Ended for HL400945+4.p
9847.63/2396.18	% SZS status Started for HL400938+5.p
9847.63/2396.18	% SZS status GaveUp for HL400938+5.p
9847.63/2396.18	% SZS status Ended for HL400938+5.p
9864.79/2398.43	% SZS status Started for HL400946+4.p
9864.79/2398.43	% SZS status Theorem for HL400946+4.p
9864.79/2398.43	% SZS status Ended for HL400946+4.p
9870.30/2399.01	% SZS status Started for HL400940+5.p
9870.30/2399.01	% SZS status GaveUp for HL400940+5.p
9870.30/2399.01	% SZS status Ended for HL400940+5.p
9871.54/2399.15	% SZS status Started for HL400941+4.p
9871.54/2399.15	% SZS status GaveUp for HL400941+4.p
9871.54/2399.15	% SZS status Ended for HL400941+4.p
9879.73/2400.17	% SZS status Started for HL400942+4.p
9879.73/2400.17	% SZS status GaveUp for HL400942+4.p
9879.73/2400.17	% SZS status Ended for HL400942+4.p
9880.58/2400.31	% SZS status Started for HL400941+5.p
9880.58/2400.31	% SZS status GaveUp for HL400941+5.p
9880.58/2400.31	% SZS status Ended for HL400941+5.p
9881.21/2400.40	% SZS status Started for HL400942+5.p
9881.21/2400.40	% SZS status GaveUp for HL400942+5.p
9881.21/2400.40	% SZS status Ended for HL400942+5.p
9889.89/2401.45	% SZS status Started for HL400943+5.p
9889.89/2401.45	% SZS status GaveUp for HL400943+5.p
9889.89/2401.45	% SZS status Ended for HL400943+5.p
9906.53/2403.55	% SZS status Started for HL400945+5.p
9906.53/2403.55	% SZS status GaveUp for HL400945+5.p
9906.53/2403.55	% SZS status Ended for HL400945+5.p
9907.60/2403.73	% SZS status Started for HL400951+4.p
9907.60/2403.73	% SZS status Theorem for HL400951+4.p
9907.60/2403.73	% SZS status Ended for HL400951+4.p
9931.09/2406.72	% SZS status Started for HL400946+5.p
9931.09/2406.72	% SZS status GaveUp for HL400946+5.p
9931.09/2406.72	% SZS status Ended for HL400946+5.p
9933.11/2406.91	% SZS status Started for HL400952+4.p
9933.11/2406.91	% SZS status Theorem for HL400952+4.p
9933.11/2406.91	% SZS status Ended for HL400952+4.p
9935.05/2407.21	% SZS status Started for HL400947+4.p
9935.05/2407.21	% SZS status GaveUp for HL400947+4.p
9935.05/2407.21	% SZS status Ended for HL400947+4.p
9937.02/2407.37	% SZS status Started for HL400953+4.p
9937.02/2407.37	% SZS status Theorem for HL400953+4.p
9937.02/2407.37	% SZS status Ended for HL400953+4.p
9937.92/2407.51	% SZS status Started for HL400947+5.p
9937.92/2407.51	% SZS status GaveUp for HL400947+5.p
9937.92/2407.51	% SZS status Ended for HL400947+5.p
9945.80/2408.49	% SZS status Started for HL400948+4.p
9945.80/2408.49	% SZS status GaveUp for HL400948+4.p
9945.80/2408.49	% SZS status Ended for HL400948+4.p
9947.07/2408.68	% SZS status Started for HL400950+4.p
9947.07/2408.68	% SZS status GaveUp for HL400950+4.p
9947.07/2408.68	% SZS status Ended for HL400950+4.p
9947.07/2408.68	% SZS status Started for HL400948+5.p
9947.07/2408.68	% SZS status GaveUp for HL400948+5.p
9947.07/2408.68	% SZS status Ended for HL400948+5.p
9947.64/2408.85	% SZS status Started for HL400955+4.p
9947.64/2408.85	% SZS status Theorem for HL400955+4.p
9947.64/2408.85	% SZS status Ended for HL400955+4.p
9948.10/2409.02	% SZS status Started for HL400956+4.p
9948.10/2409.02	% SZS status Theorem for HL400956+4.p
9948.10/2409.02	% SZS status Ended for HL400956+4.p
9955.89/2409.81	% SZS status Started for HL400950+5.p
9955.89/2409.81	% SZS status GaveUp for HL400950+5.p
9955.89/2409.81	% SZS status Ended for HL400950+5.p
9973.88/2412.04	% SZS status Started for HL400951+5.p
9973.88/2412.04	% SZS status GaveUp for HL400951+5.p
9973.88/2412.04	% SZS status Ended for HL400951+5.p
9996.45/2414.87	% SZS status Started for HL400956+5.p
9996.45/2414.87	% SZS status Theorem for HL400956+5.p
9996.45/2414.87	% SZS status Ended for HL400956+5.p
9997.19/2415.04	% SZS status Started for HL400959+4.p
9997.19/2415.04	% SZS status Theorem for HL400959+4.p
9997.19/2415.04	% SZS status Ended for HL400959+4.p
9999.04/2415.20	% SZS status Started for HL400952+5.p
9999.04/2415.20	% SZS status GaveUp for HL400952+5.p
9999.04/2415.20	% SZS status Ended for HL400952+5.p
10003.13/2415.69	% SZS status Started for HL400953+5.p
10003.13/2415.69	% SZS status GaveUp for HL400953+5.p
10003.13/2415.69	% SZS status Ended for HL400953+5.p
10004.88/2415.95	% SZS status Started for HL400954+4.p
10004.88/2415.95	% SZS status GaveUp for HL400954+4.p
10004.88/2415.95	% SZS status Ended for HL400954+4.p
10011.94/2416.79	% SZS status Started for HL400954+5.p
10011.94/2416.79	% SZS status GaveUp for HL400954+5.p
10011.94/2416.79	% SZS status Ended for HL400954+5.p
10013.53/2417.02	% SZS status Started for HL400955+5.p
10013.53/2417.02	% SZS status GaveUp for HL400955+5.p
10013.53/2417.02	% SZS status Ended for HL400955+5.p
10022.45/2418.15	% SZS status Started for HL400957+4.p
10022.45/2418.15	% SZS status GaveUp for HL400957+4.p
10022.45/2418.15	% SZS status Ended for HL400957+4.p
10040.00/2420.42	% SZS status Started for HL400957+5.p
10040.00/2420.42	% SZS status GaveUp for HL400957+5.p
10040.00/2420.42	% SZS status Ended for HL400957+5.p
10064.42/2423.38	% SZS status Started for HL400959+5.p
10064.42/2423.38	% SZS status GaveUp for HL400959+5.p
10064.42/2423.38	% SZS status Ended for HL400959+5.p
10064.42/2423.41	% SZS status Started for HL400961+4.p
10064.42/2423.41	% SZS status GaveUp for HL400961+4.p
10064.42/2423.41	% SZS status Ended for HL400961+4.p
10069.36/2424.04	% SZS status Started for HL400961+5.p
10069.36/2424.04	% SZS status GaveUp for HL400961+5.p
10069.36/2424.04	% SZS status Ended for HL400961+5.p
10070.57/2424.20	% SZS status Started for HL400962+4.p
10070.57/2424.20	% SZS status GaveUp for HL400962+4.p
10070.57/2424.20	% SZS status Ended for HL400962+4.p
10077.98/2425.13	% SZS status Started for HL400962+5.p
10077.98/2425.13	% SZS status GaveUp for HL400962+5.p
10077.98/2425.13	% SZS status Ended for HL400962+5.p
10079.24/2425.26	% SZS status Started for HL400963+4.p
10079.24/2425.26	% SZS status GaveUp for HL400963+4.p
10079.24/2425.26	% SZS status Ended for HL400963+4.p
10087.92/2426.44	% SZS status Started for HL400963+5.p
10087.92/2426.44	% SZS status GaveUp for HL400963+5.p
10087.92/2426.44	% SZS status Ended for HL400963+5.p
10088.61/2426.48	% SZS status Started for HL400966+4.p
10088.61/2426.48	% SZS status Theorem for HL400966+4.p
10088.61/2426.48	% SZS status Ended for HL400966+4.p
10105.44/2428.71	% SZS status Started for HL400964+4.p
10105.44/2428.71	% SZS status GaveUp for HL400964+4.p
10105.44/2428.71	% SZS status Ended for HL400964+4.p
10130.46/2431.69	% SZS status Started for HL400965+4.p
10130.46/2431.69	% SZS status GaveUp for HL400965+4.p
10130.46/2431.69	% SZS status Ended for HL400965+4.p
10130.46/2431.73	% SZS status Started for HL400964+5.p
10130.46/2431.73	% SZS status GaveUp for HL400964+5.p
10130.46/2431.73	% SZS status Ended for HL400964+5.p
10135.76/2432.33	% SZS status Started for HL400965+5.p
10135.76/2432.33	% SZS status GaveUp for HL400965+5.p
10135.76/2432.33	% SZS status Ended for HL400965+5.p
10136.54/2432.46	% SZS status Started for HL400970+4.p
10136.54/2432.46	% SZS status Theorem for HL400970+4.p
10136.54/2432.46	% SZS status Ended for HL400970+4.p
10144.11/2433.42	% SZS status Started for HL400966+5.p
10144.11/2433.42	% SZS status GaveUp for HL400966+5.p
10144.11/2433.42	% SZS status Ended for HL400966+5.p
10145.53/2433.58	% SZS status Started for HL400967+4.p
10145.53/2433.58	% SZS status GaveUp for HL400967+4.p
10145.53/2433.58	% SZS status Ended for HL400967+4.p
10148.71/2434.07	% SZS status Started for HL400970+5.p
10148.71/2434.07	% SZS status Theorem for HL400970+5.p
10148.71/2434.07	% SZS status Ended for HL400970+5.p
10149.49/2434.27	% SZS status Started for HL400973+4.p
10149.49/2434.27	% SZS status Theorem for HL400973+4.p
10149.49/2434.27	% SZS status Ended for HL400973+4.p
10153.85/2434.73	% SZS status Started for HL400967+5.p
10153.85/2434.73	% SZS status GaveUp for HL400967+5.p
10153.85/2434.73	% SZS status Ended for HL400967+5.p
10154.54/2434.81	% SZS status Started for HL400968+4.p
10154.54/2434.81	% SZS status GaveUp for HL400968+4.p
10154.54/2434.81	% SZS status Ended for HL400968+4.p
10172.05/2437.04	% SZS status Started for HL400968+5.p
10172.05/2437.04	% SZS status GaveUp for HL400968+5.p
10172.05/2437.04	% SZS status Ended for HL400968+5.p
10195.70/2439.89	% SZS status Started for HL400969+4.p
10195.70/2439.89	% SZS status GaveUp for HL400969+4.p
10195.70/2439.89	% SZS status Ended for HL400969+4.p
10197.03/2440.12	% SZS status Started for HL400969+5.p
10197.03/2440.12	% SZS status GaveUp for HL400969+5.p
10197.03/2440.12	% SZS status Ended for HL400969+5.p
10201.18/2440.55	% SZS status Started for HL400978+4.p
10201.18/2440.55	% SZS status Theorem for HL400978+4.p
10201.18/2440.55	% SZS status Ended for HL400978+4.p
10209.20/2441.62	% SZS status Started for HL400972+4.p
10209.20/2441.62	% SZS status GaveUp for HL400972+4.p
10209.20/2441.62	% SZS status Ended for HL400972+4.p
10210.99/2441.92	% SZS status Started for HL400972+5.p
10210.99/2441.92	% SZS status GaveUp for HL400972+5.p
10210.99/2441.92	% SZS status Ended for HL400972+5.p
10217.78/2442.67	% SZS status Started for HL400973+5.p
10217.78/2442.67	% SZS status GaveUp for HL400973+5.p
10217.78/2442.67	% SZS status Ended for HL400973+5.p
10219.49/2442.98	% SZS status Started for HL400975+4.p
10219.49/2442.98	% SZS status GaveUp for HL400975+4.p
10219.49/2442.98	% SZS status Ended for HL400975+4.p
10220.01/2443.11	% SZS status Started for HL400975+5.p
10220.01/2443.11	% SZS status GaveUp for HL400975+5.p
10220.01/2443.11	% SZS status Ended for HL400975+5.p
10236.82/2445.29	% SZS status Started for HL400976+4.p
10236.82/2445.29	% SZS status GaveUp for HL400976+4.p
10236.82/2445.29	% SZS status Ended for HL400976+4.p
10261.73/2448.24	% SZS status Started for HL400976+5.p
10261.73/2448.24	% SZS status GaveUp for HL400976+5.p
10261.73/2448.24	% SZS status Ended for HL400976+5.p
10267.23/2448.92	% SZS status Started for HL400978+5.p
10267.23/2448.92	% SZS status GaveUp for HL400978+5.p
10267.23/2448.92	% SZS status Ended for HL400978+5.p
10274.58/2449.82	% SZS status Started for HL400979+4.p
10274.58/2449.82	% SZS status GaveUp for HL400979+4.p
10274.58/2449.82	% SZS status Ended for HL400979+4.p
10276.52/2450.11	% SZS status Started for HL400982+4.p
10276.52/2450.11	% SZS status Theorem for HL400982+4.p
10276.52/2450.11	% SZS status Ended for HL400982+4.p
10277.01/2450.22	% SZS status Started for HL400979+5.p
10277.01/2450.22	% SZS status GaveUp for HL400979+5.p
10277.01/2450.22	% SZS status Ended for HL400979+5.p
10282.94/2450.85	% SZS status Started for HL400980+4.p
10282.94/2450.85	% SZS status GaveUp for HL400980+4.p
10282.94/2450.85	% SZS status Ended for HL400980+4.p
10285.42/2451.28	% SZS status Started for HL400980+5.p
10285.42/2451.28	% SZS status GaveUp for HL400980+5.p
10285.42/2451.28	% SZS status Ended for HL400980+5.p
10305.30/2453.68	% SZS status Started for HL400982+5.p
10305.30/2453.68	% SZS status GaveUp for HL400982+5.p
10305.30/2453.68	% SZS status Ended for HL400982+5.p
10327.70/2456.49	% SZS status Started for HL400983+4.p
10327.70/2456.49	% SZS status GaveUp for HL400983+4.p
10327.70/2456.49	% SZS status Ended for HL400983+4.p
10328.33/2456.63	% SZS status Started for HL400987+4.p
10328.33/2456.63	% SZS status Theorem for HL400987+4.p
10328.33/2456.63	% SZS status Ended for HL400987+4.p
10328.33/2456.63	% SZS status Started for HL400984+4.p
10328.33/2456.63	% SZS status Theorem for HL400984+4.p
10328.33/2456.63	% SZS status Ended for HL400984+4.p
10333.45/2457.23	% SZS status Started for HL400983+5.p
10333.45/2457.23	% SZS status GaveUp for HL400983+5.p
10333.45/2457.23	% SZS status Ended for HL400983+5.p
10342.75/2458.40	% SZS status Started for HL400985+4.p
10342.75/2458.40	% SZS status GaveUp for HL400985+4.p
10342.75/2458.40	% SZS status Ended for HL400985+4.p
10343.21/2458.45	% SZS status Started for HL400984+5.p
10343.21/2458.45	% SZS status GaveUp for HL400984+5.p
10343.21/2458.45	% SZS status Ended for HL400984+5.p
10344.52/2458.57	% SZS status Started for HL400990+4.p
10344.52/2458.57	% SZS status Theorem for HL400990+4.p
10344.52/2458.57	% SZS status Ended for HL400990+4.p
10349.40/2459.20	% SZS status Started for HL400985+5.p
10349.40/2459.20	% SZS status GaveUp for HL400985+5.p
10349.40/2459.20	% SZS status Ended for HL400985+5.p
10351.44/2459.52	% SZS status Started for HL400986+4.p
10351.44/2459.52	% SZS status GaveUp for HL400986+4.p
10351.44/2459.52	% SZS status Ended for HL400986+4.p
10371.97/2462.10	% SZS status Started for HL400986+5.p
10371.97/2462.10	% SZS status GaveUp for HL400986+5.p
10371.97/2462.10	% SZS status Ended for HL400986+5.p
10374.83/2462.38	% SZS status Started for HL400987+5.p
10374.83/2462.38	% SZS status Theorem for HL400987+5.p
10374.83/2462.38	% SZS status Ended for HL400987+5.p
10394.13/2464.88	% SZS status Started for HL400988+4.p
10394.13/2464.88	% SZS status GaveUp for HL400988+4.p
10394.13/2464.88	% SZS status Ended for HL400988+4.p
10399.72/2465.55	% SZS status Started for HL400988+5.p
10399.72/2465.55	% SZS status GaveUp for HL400988+5.p
10399.72/2465.55	% SZS status Ended for HL400988+5.p
10408.67/2466.74	% SZS status Started for HL400991+4.p
10408.67/2466.74	% SZS status GaveUp for HL400991+4.p
10408.67/2466.74	% SZS status Ended for HL400991+4.p
10409.70/2466.77	% SZS status Started for HL400990+5.p
10409.70/2466.77	% SZS status GaveUp for HL400990+5.p
10409.70/2466.77	% SZS status Ended for HL400990+5.p
10415.39/2467.53	% SZS status Started for HL400991+5.p
10415.39/2467.53	% SZS status GaveUp for HL400991+5.p
10415.39/2467.53	% SZS status Ended for HL400991+5.p
10416.42/2467.74	% SZS status Started for HL400992+4.p
10416.42/2467.74	% SZS status GaveUp for HL400992+4.p
10416.42/2467.74	% SZS status Ended for HL400992+4.p
10438.68/2470.44	% SZS status Started for HL400992+5.p
10438.68/2470.44	% SZS status GaveUp for HL400992+5.p
10438.68/2470.44	% SZS status Ended for HL400992+5.p
10440.50/2470.62	% SZS status Started for HL400993+4.p
10440.50/2470.62	% SZS status GaveUp for HL400993+4.p
10440.50/2470.62	% SZS status Ended for HL400993+4.p
10460.19/2473.24	% SZS status Started for HL400993+5.p
10460.19/2473.24	% SZS status GaveUp for HL400993+5.p
10460.19/2473.24	% SZS status Ended for HL400993+5.p
10464.54/2473.72	% SZS status Started for HL400994+4.p
10464.54/2473.72	% SZS status GaveUp for HL400994+4.p
10464.54/2473.72	% SZS status Ended for HL400994+4.p
10474.34/2475.00	% SZS status Started for HL400995+4.p
10474.34/2475.00	% SZS status GaveUp for HL400995+4.p
10474.34/2475.00	% SZS status Ended for HL400995+4.p
10475.79/2475.07	% SZS status Started for HL400994+5.p
10475.79/2475.07	% SZS status GaveUp for HL400994+5.p
10475.79/2475.07	% SZS status Ended for HL400994+5.p
10476.49/2475.23	% SZS status Started for HL400998+4.p
10476.49/2475.23	% SZS status Theorem for HL400998+4.p
10476.49/2475.23	% SZS status Ended for HL400998+4.p
10481.71/2475.83	% SZS status Started for HL400995+5.p
10481.71/2475.83	% SZS status GaveUp for HL400995+5.p
10481.71/2475.83	% SZS status Ended for HL400995+5.p
10482.39/2475.96	% SZS status Started for HL400996+4.p
10482.39/2475.96	% SZS status GaveUp for HL400996+4.p
10482.39/2475.96	% SZS status Ended for HL400996+4.p
10485.28/2476.32	% SZS status Started for HL401000+4.p
10485.28/2476.32	% SZS status Theorem for HL401000+4.p
10485.28/2476.32	% SZS status Ended for HL401000+4.p
10504.19/2478.75	% SZS status Started for HL400996+5.p
10504.19/2478.75	% SZS status GaveUp for HL400996+5.p
10504.19/2478.75	% SZS status Ended for HL400996+5.p
10506.14/2478.91	% SZS status Started for HL400997+4.p
10506.14/2478.91	% SZS status GaveUp for HL400997+4.p
10506.14/2478.91	% SZS status Ended for HL400997+4.p
10526.49/2481.56	% SZS status Started for HL400997+5.p
10526.49/2481.56	% SZS status GaveUp for HL400997+5.p
10526.49/2481.56	% SZS status Ended for HL400997+5.p
10541.00/2483.31	% SZS status Started for HL400998+5.p
10541.00/2483.31	% SZS status GaveUp for HL400998+5.p
10541.00/2483.31	% SZS status Ended for HL400998+5.p
10541.56/2483.35	% SZS status Started for HL400999+4.p
10541.56/2483.35	% SZS status GaveUp for HL400999+4.p
10541.56/2483.35	% SZS status Ended for HL400999+4.p
10542.64/2483.59	% SZS status Started for HL400999+5.p
10542.64/2483.59	% SZS status GaveUp for HL400999+5.p
10542.64/2483.59	% SZS status Ended for HL400999+5.p
10548.51/2484.26	% SZS status Started for HL401000+5.p
10548.51/2484.26	% SZS status GaveUp for HL401000+5.p
10548.51/2484.26	% SZS status Ended for HL401000+5.p
10550.65/2484.51	% SZS status Started for HL401001+4.p
10550.65/2484.51	% SZS status GaveUp for HL401001+4.p
10550.65/2484.51	% SZS status Ended for HL401001+4.p
10569.81/2487.05	% SZS status Started for HL401001+5.p
10569.81/2487.05	% SZS status GaveUp for HL401001+5.p
10569.81/2487.05	% SZS status Ended for HL401001+5.p
10572.02/2487.17	% SZS status Started for HL401002+4.p
10572.02/2487.17	% SZS status GaveUp for HL401002+4.p
10572.02/2487.17	% SZS status Ended for HL401002+4.p
10583.67/2488.77	% SZS status Started for HL401008+4.p
10583.67/2488.77	% SZS status Theorem for HL401008+4.p
10583.67/2488.77	% SZS status Ended for HL401008+4.p
10593.57/2489.89	% SZS status Started for HL401002+5.p
10593.57/2489.89	% SZS status GaveUp for HL401002+5.p
10593.57/2489.89	% SZS status Ended for HL401002+5.p
10605.87/2491.50	% SZS status Started for HL401003+4.p
10605.87/2491.50	% SZS status GaveUp for HL401003+4.p
10605.87/2491.50	% SZS status Ended for HL401003+4.p
10608.17/2491.76	% SZS status Started for HL401003+5.p
10608.17/2491.76	% SZS status GaveUp for HL401003+5.p
10608.17/2491.76	% SZS status Ended for HL401003+5.p
10608.36/2491.79	% SZS status Started for HL401004+4.p
10608.36/2491.79	% SZS status GaveUp for HL401004+4.p
10608.36/2491.79	% SZS status Ended for HL401004+4.p
10614.92/2492.56	% SZS status Started for HL401004+5.p
10614.92/2492.56	% SZS status GaveUp for HL401004+5.p
10614.92/2492.56	% SZS status Ended for HL401004+5.p
10616.00/2492.74	% SZS status Started for HL401006+4.p
10616.00/2492.74	% SZS status GaveUp for HL401006+4.p
10616.00/2492.74	% SZS status Ended for HL401006+4.p
10633.88/2494.96	% SZS status Started for HL401008+5.p
10633.88/2494.96	% SZS status Theorem for HL401008+5.p
10633.88/2494.96	% SZS status Ended for HL401008+5.p
10638.01/2495.45	% SZS status Started for HL401006+5.p
10638.01/2495.45	% SZS status GaveUp for HL401006+5.p
10638.01/2495.45	% SZS status Ended for HL401006+5.p
10657.53/2498.05	% SZS status Started for HL401009+4.p
10657.53/2498.05	% SZS status GaveUp for HL401009+4.p
10657.53/2498.05	% SZS status Ended for HL401009+4.p
10672.33/2499.79	% SZS status Started for HL401009+5.p
10672.33/2499.79	% SZS status GaveUp for HL401009+5.p
10672.33/2499.79	% SZS status Ended for HL401009+5.p
10673.22/2499.93	% SZS status Started for HL401011+4.p
10673.22/2499.93	% SZS status GaveUp for HL401011+4.p
10673.22/2499.93	% SZS status Ended for HL401011+4.p
10674.11/2500.09	% SZS status Started for HL401011+5.p
10674.11/2500.09	% SZS status GaveUp for HL401011+5.p
10674.11/2500.09	% SZS status Ended for HL401011+5.p
10680.54/2500.79	% SZS status Started for HL401012+4.p
10680.54/2500.79	% SZS status GaveUp for HL401012+4.p
10680.54/2500.79	% SZS status Ended for HL401012+4.p
10682.58/2501.08	% SZS status Started for HL401012+5.p
10682.58/2501.08	% SZS status GaveUp for HL401012+5.p
10682.58/2501.08	% SZS status Ended for HL401012+5.p
10700.27/2503.33	% SZS status Started for HL401013+4.p
10700.27/2503.33	% SZS status GaveUp for HL401013+4.p
10700.27/2503.33	% SZS status Ended for HL401013+4.p
10704.87/2503.85	% SZS status Started for HL401013+5.p
10704.87/2503.85	% SZS status GaveUp for HL401013+5.p
10704.87/2503.85	% SZS status Ended for HL401013+5.p
10723.19/2506.27	% SZS status Started for HL401014+4.p
10723.19/2506.27	% SZS status GaveUp for HL401014+4.p
10723.19/2506.27	% SZS status Ended for HL401014+4.p
10738.51/2508.08	% SZS status Started for HL401014+5.p
10738.51/2508.08	% SZS status GaveUp for HL401014+5.p
10738.51/2508.08	% SZS status Ended for HL401014+5.p
10739.19/2508.19	% SZS status Started for HL401015+4.p
10739.19/2508.19	% SZS status GaveUp for HL401015+4.p
10739.19/2508.19	% SZS status Ended for HL401015+4.p
10740.65/2508.50	% SZS status Started for HL401015+5.p
10740.65/2508.50	% SZS status GaveUp for HL401015+5.p
10740.65/2508.50	% SZS status Ended for HL401015+5.p
10745.12/2508.96	% SZS status Started for HL401016+4.p
10745.12/2508.96	% SZS status GaveUp for HL401016+4.p
10745.12/2508.96	% SZS status Ended for HL401016+4.p
10748.52/2509.37	% SZS status Started for HL401016+5.p
10748.52/2509.37	% SZS status GaveUp for HL401016+5.p
10748.52/2509.37	% SZS status Ended for HL401016+5.p
10765.44/2511.51	% SZS status Started for HL401017+4.p
10765.44/2511.51	% SZS status GaveUp for HL401017+4.p
10765.44/2511.51	% SZS status Ended for HL401017+4.p
10771.04/2512.21	% SZS status Started for HL401017+5.p
10771.04/2512.21	% SZS status GaveUp for HL401017+5.p
10771.04/2512.21	% SZS status Ended for HL401017+5.p
10789.15/2514.55	% SZS status Started for HL401018+4.p
10789.15/2514.55	% SZS status GaveUp for HL401018+4.p
10789.15/2514.55	% SZS status Ended for HL401018+4.p
10791.63/2514.79	% SZS status Started for HL401024+4.p
10791.63/2514.79	% SZS status Theorem for HL401024+4.p
10791.63/2514.79	% SZS status Ended for HL401024+4.p
10804.73/2516.42	% SZS status Started for HL401019+4.p
10804.73/2516.42	% SZS status GaveUp for HL401019+4.p
10804.73/2516.42	% SZS status Ended for HL401019+4.p
10805.61/2516.52	% SZS status Started for HL401018+5.p
10805.61/2516.52	% SZS status GaveUp for HL401018+5.p
10805.61/2516.52	% SZS status Ended for HL401018+5.p
10808.20/2516.84	% SZS status Started for HL401019+5.p
10808.20/2516.84	% SZS status GaveUp for HL401019+5.p
10808.20/2516.84	% SZS status Ended for HL401019+5.p
10810.09/2517.14	% SZS status Started for HL401022+4.p
10810.09/2517.14	% SZS status GaveUp for HL401022+4.p
10810.09/2517.14	% SZS status Ended for HL401022+4.p
10814.56/2517.70	% SZS status Started for HL401022+5.p
10814.56/2517.70	% SZS status GaveUp for HL401022+5.p
10814.56/2517.70	% SZS status Ended for HL401022+5.p
10818.51/2518.17	% SZS status Started for HL401023+4.p
10818.51/2518.17	% SZS status Theorem for HL401023+4.p
10818.51/2518.17	% SZS status Ended for HL401023+4.p
10829.93/2519.59	% SZS status Started for HL401027+4.p
10829.93/2519.59	% SZS status Theorem for HL401027+4.p
10829.93/2519.59	% SZS status Ended for HL401027+4.p
10836.88/2520.50	% SZS status Started for HL401023+5.p
10836.88/2520.50	% SZS status GaveUp for HL401023+5.p
10836.88/2520.50	% SZS status Ended for HL401023+5.p
10857.89/2523.08	% SZS status Started for HL401024+5.p
10857.89/2523.08	% SZS status GaveUp for HL401024+5.p
10857.89/2523.08	% SZS status Ended for HL401024+5.p
10869.86/2524.61	% SZS status Started for HL401025+4.p
10869.86/2524.61	% SZS status GaveUp for HL401025+4.p
10869.86/2524.61	% SZS status Ended for HL401025+4.p
10871.63/2524.84	% SZS status Started for HL401025+5.p
10871.63/2524.84	% SZS status GaveUp for HL401025+5.p
10871.63/2524.84	% SZS status Ended for HL401025+5.p
10874.46/2525.15	% SZS status Started for HL401026+4.p
10874.46/2525.15	% SZS status GaveUp for HL401026+4.p
10874.46/2525.15	% SZS status Ended for HL401026+4.p
10876.37/2525.45	% SZS status Started for HL401026+5.p
10876.37/2525.45	% SZS status GaveUp for HL401026+5.p
10876.37/2525.45	% SZS status Ended for HL401026+5.p
10885.26/2526.60	% SZS status Started for HL401027+5.p
10885.26/2526.60	% SZS status GaveUp for HL401027+5.p
10885.26/2526.60	% SZS status Ended for HL401027+5.p
10894.64/2527.79	% SZS status Started for HL401028+4.p
10894.64/2527.79	% SZS status GaveUp for HL401028+4.p
10894.64/2527.79	% SZS status Ended for HL401028+4.p
10903.23/2528.80	% SZS status Started for HL401028+5.p
10903.23/2528.80	% SZS status GaveUp for HL401028+5.p
10903.23/2528.80	% SZS status Ended for HL401028+5.p
10923.20/2531.29	% SZS status Started for HL401029+4.p
10923.20/2531.29	% SZS status GaveUp for HL401029+4.p
10923.20/2531.29	% SZS status Ended for HL401029+4.p
10935.92/2532.90	% SZS status Started for HL401029+5.p
10935.92/2532.90	% SZS status GaveUp for HL401029+5.p
10935.92/2532.90	% SZS status Ended for HL401029+5.p
10936.43/2533.02	% SZS status Started for HL401030+4.p
10936.43/2533.02	% SZS status GaveUp for HL401030+4.p
10936.43/2533.02	% SZS status Ended for HL401030+4.p
10937.29/2533.23	% SZS status Started for HL401037+4.p
10937.29/2533.23	% SZS status Theorem for HL401037+4.p
10937.29/2533.23	% SZS status Ended for HL401037+4.p
10940.71/2533.49	% SZS status Started for HL401030+5.p
10940.71/2533.49	% SZS status GaveUp for HL401030+5.p
10940.71/2533.49	% SZS status Ended for HL401030+5.p
10942.26/2533.79	% SZS status Started for HL401031+4.p
10942.26/2533.79	% SZS status GaveUp for HL401031+4.p
10942.26/2533.79	% SZS status Ended for HL401031+4.p
10952.61/2534.97	% SZS status Started for HL401031+5.p
10952.61/2534.97	% SZS status GaveUp for HL401031+5.p
10952.61/2534.97	% SZS status Ended for HL401031+5.p
10967.35/2536.85	% SZS status Started for HL401033+4.p
10967.35/2536.85	% SZS status GaveUp for HL401033+4.p
10967.35/2536.85	% SZS status Ended for HL401033+4.p
10970.13/2537.18	% SZS status Started for HL401033+5.p
10970.13/2537.18	% SZS status GaveUp for HL401033+5.p
10970.13/2537.18	% SZS status Ended for HL401033+5.p
10977.19/2538.12	% SZS status Started for HL401035+4.p
10977.19/2538.12	% SZS status Theorem for HL401035+4.p
10977.19/2538.12	% SZS status Ended for HL401035+4.p
10985.07/2539.09	% SZS status Started for HL401037+5.p
10985.07/2539.09	% SZS status Theorem for HL401037+5.p
10985.07/2539.09	% SZS status Ended for HL401037+5.p
11002.54/2541.34	% SZS status Started for HL401035+5.p
11002.54/2541.34	% SZS status GaveUp for HL401035+5.p
11002.54/2541.34	% SZS status Ended for HL401035+5.p
11006.74/2541.80	% SZS status Started for HL401038+4.p
11006.74/2541.80	% SZS status GaveUp for HL401038+4.p
11006.74/2541.80	% SZS status Ended for HL401038+4.p
11008.29/2542.03	% SZS status Started for HL401043+4.p
11008.29/2542.03	% SZS status Theorem for HL401043+4.p
11008.29/2542.03	% SZS status Ended for HL401043+4.p
11009.11/2542.12	% SZS status Started for HL401038+5.p
11009.11/2542.12	% SZS status GaveUp for HL401038+5.p
11009.11/2542.12	% SZS status Ended for HL401038+5.p
11010.94/2542.41	% SZS status Started for HL401044+4.p
11010.94/2542.41	% SZS status Theorem for HL401044+4.p
11010.94/2542.41	% SZS status Ended for HL401044+4.p
11017.81/2543.17	% SZS status Started for HL401039+4.p
11017.81/2543.17	% SZS status GaveUp for HL401039+4.p
11017.81/2543.17	% SZS status Ended for HL401039+4.p
11019.39/2543.42	% SZS status Started for HL401045+4.p
11019.39/2543.42	% SZS status Theorem for HL401045+4.p
11019.39/2543.42	% SZS status Ended for HL401045+4.p
11033.74/2545.18	% SZS status Started for HL401039+5.p
11033.74/2545.18	% SZS status GaveUp for HL401039+5.p
11033.74/2545.18	% SZS status Ended for HL401039+5.p
11034.98/2545.42	% SZS status Started for HL401041+4.p
11034.98/2545.42	% SZS status GaveUp for HL401041+4.p
11034.98/2545.42	% SZS status Ended for HL401041+4.p
11035.97/2545.44	% SZS status Started for HL401046+4.p
11035.97/2545.44	% SZS status Theorem for HL401046+4.p
11035.97/2545.44	% SZS status Ended for HL401046+4.p
11043.29/2546.42	% SZS status Started for HL401041+5.p
11043.29/2546.42	% SZS status GaveUp for HL401041+5.p
11043.29/2546.42	% SZS status Ended for HL401041+5.p
11049.38/2547.12	% SZS status Started for HL401046+5.p
11049.38/2547.12	% SZS status Theorem for HL401046+5.p
11049.38/2547.12	% SZS status Ended for HL401046+5.p
11050.46/2547.28	% SZS status Started for HL401042+4.p
11050.46/2547.28	% SZS status GaveUp for HL401042+4.p
11050.46/2547.28	% SZS status Ended for HL401042+4.p
11054.17/2547.74	% SZS status Started for HL401048+4.p
11054.17/2547.74	% SZS status Theorem for HL401048+4.p
11054.17/2547.74	% SZS status Ended for HL401048+4.p
11068.33/2549.60	% SZS status Started for HL401045+5.p
11068.33/2549.60	% SZS status Theorem for HL401045+5.p
11068.33/2549.60	% SZS status Ended for HL401045+5.p
11068.82/2549.64	% SZS status Started for HL401042+5.p
11068.82/2549.64	% SZS status GaveUp for HL401042+5.p
11068.82/2549.64	% SZS status Ended for HL401042+5.p
11075.13/2550.36	% SZS status Started for HL401043+5.p
11075.13/2550.36	% SZS status GaveUp for HL401043+5.p
11075.13/2550.36	% SZS status Ended for HL401043+5.p
11077.48/2550.79	% SZS status Started for HL401044+5.p
11077.48/2550.79	% SZS status GaveUp for HL401044+5.p
11077.48/2550.79	% SZS status Ended for HL401044+5.p
11100.73/2553.62	% SZS status Started for HL401047+4.p
11100.73/2553.62	% SZS status GaveUp for HL401047+4.p
11100.73/2553.62	% SZS status Ended for HL401047+4.p
11110.23/2554.79	% SZS status Started for HL401047+5.p
11110.23/2554.79	% SZS status GaveUp for HL401047+5.p
11110.23/2554.79	% SZS status Ended for HL401047+5.p
11116.44/2555.59	% SZS status Started for HL401048+5.p
11116.44/2555.59	% SZS status GaveUp for HL401048+5.p
11116.44/2555.59	% SZS status Ended for HL401048+5.p
11120.09/2556.05	% SZS status Started for HL401049+4.p
11120.09/2556.05	% SZS status GaveUp for HL401049+4.p
11120.09/2556.05	% SZS status Ended for HL401049+4.p
11135.47/2557.92	% SZS status Started for HL401049+5.p
11135.47/2557.92	% SZS status GaveUp for HL401049+5.p
11135.47/2557.92	% SZS status Ended for HL401049+5.p
11137.43/2558.08	% SZS status Started for HL401050+4.p
11137.43/2558.08	% SZS status GaveUp for HL401050+4.p
11137.43/2558.08	% SZS status Ended for HL401050+4.p
11142.98/2558.78	% SZS status Started for HL401050+5.p
11142.98/2558.78	% SZS status GaveUp for HL401050+5.p
11142.98/2558.78	% SZS status Ended for HL401050+5.p
11146.11/2559.17	% SZS status Started for HL401051+4.p
11146.11/2559.17	% SZS status GaveUp for HL401051+4.p
11146.11/2559.17	% SZS status Ended for HL401051+4.p
11167.52/2561.93	% SZS status Started for HL401051+5.p
11167.52/2561.93	% SZS status GaveUp for HL401051+5.p
11167.52/2561.93	% SZS status Ended for HL401051+5.p
11177.10/2563.14	% SZS status Started for HL401052+4.p
11177.10/2563.14	% SZS status GaveUp for HL401052+4.p
11177.10/2563.14	% SZS status Ended for HL401052+4.p
11183.39/2563.89	% SZS status Started for HL401052+5.p
11183.39/2563.89	% SZS status GaveUp for HL401052+5.p
11183.39/2563.89	% SZS status Ended for HL401052+5.p
11186.73/2564.31	% SZS status Started for HL401053+4.p
11186.73/2564.31	% SZS status GaveUp for HL401053+4.p
11186.73/2564.31	% SZS status Ended for HL401053+4.p
11202.14/2566.28	% SZS status Started for HL401053+5.p
11202.14/2566.28	% SZS status GaveUp for HL401053+5.p
11202.14/2566.28	% SZS status Ended for HL401053+5.p
11203.34/2566.43	% SZS status Started for HL401054+4.p
11203.34/2566.43	% SZS status GaveUp for HL401054+4.p
11203.34/2566.43	% SZS status Ended for HL401054+4.p
11209.51/2567.20	% SZS status Started for HL401054+5.p
11209.51/2567.20	% SZS status GaveUp for HL401054+5.p
11209.51/2567.20	% SZS status Ended for HL401054+5.p
11210.89/2567.41	% SZS status Started for HL401056+4.p
11210.89/2567.41	% SZS status GaveUp for HL401056+4.p
11210.89/2567.41	% SZS status Ended for HL401056+4.p
11234.02/2570.25	% SZS status Started for HL401056+5.p
11234.02/2570.25	% SZS status GaveUp for HL401056+5.p
11234.02/2570.25	% SZS status Ended for HL401056+5.p
11243.21/2571.40	% SZS status Started for HL401057+4.p
11243.21/2571.40	% SZS status GaveUp for HL401057+4.p
11243.21/2571.40	% SZS status Ended for HL401057+4.p
11249.72/2572.20	% SZS status Started for HL401057+5.p
11249.72/2572.20	% SZS status GaveUp for HL401057+5.p
11249.72/2572.20	% SZS status Ended for HL401057+5.p
11251.99/2572.51	% SZS status Started for HL401058+4.p
11251.99/2572.51	% SZS status GaveUp for HL401058+4.p
11251.99/2572.51	% SZS status Ended for HL401058+4.p
11252.51/2572.66	% SZS status Started for HL401061+4.p
11252.51/2572.66	% SZS status Theorem for HL401061+4.p
11252.51/2572.66	% SZS status Ended for HL401061+4.p
11269.37/2574.67	% SZS status Started for HL401058+5.p
11269.37/2574.67	% SZS status GaveUp for HL401058+5.p
11269.37/2574.67	% SZS status Ended for HL401058+5.p
11270.04/2574.80	% SZS status Started for HL401059+4.p
11270.04/2574.80	% SZS status GaveUp for HL401059+4.p
11270.04/2574.80	% SZS status Ended for HL401059+4.p
11275.89/2575.50	% SZS status Started for HL401059+5.p
11275.89/2575.50	% SZS status GaveUp for HL401059+5.p
11275.89/2575.50	% SZS status Ended for HL401059+5.p
11289.12/2577.32	% SZS status Started for HL401060+4.p
11289.12/2577.32	% SZS status GaveUp for HL401060+4.p
11289.12/2577.32	% SZS status Ended for HL401060+4.p
11300.93/2578.68	% SZS status Started for HL401060+5.p
11300.93/2578.68	% SZS status GaveUp for HL401060+5.p
11300.93/2578.68	% SZS status Ended for HL401060+5.p
11315.71/2580.49	% SZS status Started for HL401061+5.p
11315.71/2580.49	% SZS status GaveUp for HL401061+5.p
11315.71/2580.49	% SZS status Ended for HL401061+5.p
11317.16/2580.69	% SZS status Started for HL401062+4.p
11317.16/2580.69	% SZS status GaveUp for HL401062+4.p
11317.16/2580.69	% SZS status Ended for HL401062+4.p
11318.91/2580.97	% SZS status Started for HL401062+5.p
11318.91/2580.97	% SZS status GaveUp for HL401062+5.p
11318.91/2580.97	% SZS status Ended for HL401062+5.p
11334.65/2582.95	% SZS status Started for HL401063+4.p
11334.65/2582.95	% SZS status GaveUp for HL401063+4.p
11334.65/2582.95	% SZS status Ended for HL401063+4.p
11335.99/2583.10	% SZS status Started for HL401063+5.p
11335.99/2583.10	% SZS status GaveUp for HL401063+5.p
11335.99/2583.10	% SZS status Ended for HL401063+5.p
11341.42/2583.74	% SZS status Started for HL401064+4.p
11341.42/2583.74	% SZS status GaveUp for HL401064+4.p
11341.42/2583.74	% SZS status Ended for HL401064+4.p
11357.67/2585.77	% SZS status Started for HL401064+5.p
11357.67/2585.77	% SZS status GaveUp for HL401064+5.p
11357.67/2585.77	% SZS status Ended for HL401064+5.p
11366.47/2586.88	% SZS status Started for HL401067+4.p
11366.47/2586.88	% SZS status GaveUp for HL401067+4.p
11366.47/2586.88	% SZS status Ended for HL401067+4.p
11381.55/2588.78	% SZS status Started for HL401067+5.p
11381.55/2588.78	% SZS status GaveUp for HL401067+5.p
11381.55/2588.78	% SZS status Ended for HL401067+5.p
11382.59/2588.91	% SZS status Started for HL401068+4.p
11382.59/2588.91	% SZS status GaveUp for HL401068+4.p
11382.59/2588.91	% SZS status Ended for HL401068+4.p
11385.49/2589.33	% SZS status Started for HL401068+5.p
11385.49/2589.33	% SZS status GaveUp for HL401068+5.p
11385.49/2589.33	% SZS status Ended for HL401068+5.p
11400.68/2591.21	% SZS status Started for HL401069+4.p
11400.68/2591.21	% SZS status GaveUp for HL401069+4.p
11400.68/2591.21	% SZS status Ended for HL401069+4.p
11402.34/2591.42	% SZS status Started for HL401069+5.p
11402.34/2591.42	% SZS status GaveUp for HL401069+5.p
11402.34/2591.42	% SZS status Ended for HL401069+5.p
11407.26/2592.01	% SZS status Started for HL401070+4.p
11407.26/2592.01	% SZS status GaveUp for HL401070+4.p
11407.26/2592.01	% SZS status Ended for HL401070+4.p
11422.37/2593.97	% SZS status Started for HL401074+4.p
11422.37/2593.97	% SZS status Theorem for HL401074+4.p
11422.37/2593.97	% SZS status Ended for HL401074+4.p
11422.92/2594.09	% SZS status Started for HL401070+5.p
11422.92/2594.09	% SZS status GaveUp for HL401070+5.p
11422.92/2594.09	% SZS status Ended for HL401070+5.p
11431.94/2595.09	% SZS status Started for HL401071+4.p
11431.94/2595.09	% SZS status GaveUp for HL401071+4.p
11431.94/2595.09	% SZS status Ended for HL401071+4.p
11447.73/2597.10	% SZS status Started for HL401071+5.p
11447.73/2597.10	% SZS status GaveUp for HL401071+5.p
11447.73/2597.10	% SZS status Ended for HL401071+5.p
11447.73/2597.11	% SZS status Started for HL401072+4.p
11447.73/2597.11	% SZS status GaveUp for HL401072+4.p
11447.73/2597.11	% SZS status Ended for HL401072+4.p
11453.29/2597.76	% SZS status Started for HL401072+5.p
11453.29/2597.76	% SZS status GaveUp for HL401072+5.p
11453.29/2597.76	% SZS status Ended for HL401072+5.p
11454.65/2598.02	% SZS status Started for HL401077+4.p
11454.65/2598.02	% SZS status Theorem for HL401077+4.p
11454.65/2598.02	% SZS status Ended for HL401077+4.p
11466.16/2599.45	% SZS status Started for HL401073+4.p
11466.16/2599.45	% SZS status GaveUp for HL401073+4.p
11466.16/2599.45	% SZS status Ended for HL401073+4.p
11467.00/2599.72	% SZS status Started for HL401078+4.p
11467.00/2599.72	% SZS status Theorem for HL401078+4.p
11467.00/2599.72	% SZS status Ended for HL401078+4.p
11469.24/2599.83	% SZS status Started for HL401073+5.p
11469.24/2599.83	% SZS status GaveUp for HL401073+5.p
11469.24/2599.83	% SZS status Ended for HL401073+5.p
11489.26/2602.30	% SZS status Started for HL401074+5.p
11489.26/2602.30	% SZS status GaveUp for HL401074+5.p
11489.26/2602.30	% SZS status Ended for HL401074+5.p
11489.84/2602.38	% SZS status Started for HL401075+4.p
11489.84/2602.38	% SZS status GaveUp for HL401075+4.p
11489.84/2602.38	% SZS status Ended for HL401075+4.p
11497.74/2603.42	% SZS status Started for HL401075+5.p
11497.74/2603.42	% SZS status GaveUp for HL401075+5.p
11497.74/2603.42	% SZS status Ended for HL401075+5.p
11500.35/2603.74	% SZS status Started for HL401076+4.p
11500.35/2603.74	% SZS status Theorem for HL401076+4.p
11500.35/2603.74	% SZS status Ended for HL401076+4.p
11502.54/2604.04	% SZS status Started for HL401077+5.p
11502.54/2604.04	% SZS status Theorem for HL401077+5.p
11502.54/2604.04	% SZS status Ended for HL401077+5.p
11514.30/2605.43	% SZS status Started for HL401076+5.p
11514.30/2605.43	% SZS status GaveUp for HL401076+5.p
11514.30/2605.43	% SZS status Ended for HL401076+5.p
11516.14/2605.77	% SZS status Started for HL401078+5.p
11516.14/2605.77	% SZS status Theorem for HL401078+5.p
11516.14/2605.77	% SZS status Ended for HL401078+5.p
11534.70/2608.10	% SZS status Started for HL401079+4.p
11534.70/2608.10	% SZS status GaveUp for HL401079+4.p
11534.70/2608.10	% SZS status Ended for HL401079+4.p
11555.58/2610.65	% SZS status Started for HL401080+4.p
11555.58/2610.65	% SZS status GaveUp for HL401080+4.p
11555.58/2610.65	% SZS status Ended for HL401080+4.p
11556.02/2610.68	% SZS status Started for HL401079+5.p
11556.02/2610.68	% SZS status GaveUp for HL401079+5.p
11556.02/2610.68	% SZS status Ended for HL401079+5.p
11563.94/2611.73	% SZS status Started for HL401080+5.p
11563.94/2611.73	% SZS status GaveUp for HL401080+5.p
11563.94/2611.73	% SZS status Ended for HL401080+5.p
11566.26/2612.01	% SZS status Started for HL401081+4.p
11566.26/2612.01	% SZS status GaveUp for HL401081+4.p
11566.26/2612.01	% SZS status Ended for HL401081+4.p
11568.71/2612.36	% SZS status Started for HL401081+5.p
11568.71/2612.36	% SZS status GaveUp for HL401081+5.p
11568.71/2612.36	% SZS status Ended for HL401081+5.p
11579.10/2613.62	% SZS status Started for HL401082+4.p
11579.10/2613.62	% SZS status GaveUp for HL401082+4.p
11579.10/2613.62	% SZS status Ended for HL401082+4.p
11582.43/2614.15	% SZS status Started for HL401082+5.p
11582.43/2614.15	% SZS status GaveUp for HL401082+5.p
11582.43/2614.15	% SZS status Ended for HL401082+5.p
11601.02/2616.35	% SZS status Started for HL401085+4.p
11601.02/2616.35	% SZS status GaveUp for HL401085+4.p
11601.02/2616.35	% SZS status Ended for HL401085+4.p
11603.18/2616.60	% SZS status Started for HL401091+4.p
11603.18/2616.60	% SZS status Theorem for HL401091+4.p
11603.18/2616.60	% SZS status Ended for HL401091+4.p
11621.32/2618.89	% SZS status Started for HL401086+4.p
11621.32/2618.89	% SZS status GaveUp for HL401086+4.p
11621.32/2618.89	% SZS status Ended for HL401086+4.p
11622.18/2619.05	% SZS status Started for HL401085+5.p
11622.18/2619.05	% SZS status GaveUp for HL401085+5.p
11622.18/2619.05	% SZS status Ended for HL401085+5.p
11622.45/2619.16	% SZS status Started for HL401092+4.p
11622.45/2619.16	% SZS status Theorem for HL401092+4.p
11622.45/2619.16	% SZS status Ended for HL401092+4.p
11625.22/2619.40	% SZS status Started for HL401093+4.p
11625.22/2619.40	% SZS status Theorem for HL401093+4.p
11625.22/2619.40	% SZS status Ended for HL401093+4.p
11630.35/2620.02	% SZS status Started for HL401086+5.p
11630.35/2620.02	% SZS status GaveUp for HL401086+5.p
11630.35/2620.02	% SZS status Ended for HL401086+5.p
11631.44/2620.22	% SZS status Started for HL401087+4.p
11631.44/2620.22	% SZS status GaveUp for HL401087+4.p
11631.44/2620.22	% SZS status Ended for HL401087+4.p
11635.32/2620.67	% SZS status Started for HL401087+5.p
11635.32/2620.67	% SZS status GaveUp for HL401087+5.p
11635.32/2620.67	% SZS status Ended for HL401087+5.p
11638.10/2620.99	% SZS status Started for HL401095+4.p
11638.10/2620.99	% SZS status Theorem for HL401095+4.p
11638.10/2620.99	% SZS status Ended for HL401095+4.p
11644.67/2621.91	% SZS status Started for HL401089+4.p
11644.67/2621.91	% SZS status GaveUp for HL401089+4.p
11644.67/2621.91	% SZS status Ended for HL401089+4.p
11648.97/2622.56	% SZS status Started for HL401089+5.p
11648.97/2622.56	% SZS status GaveUp for HL401089+5.p
11648.97/2622.56	% SZS status Ended for HL401089+5.p
11669.21/2624.92	% SZS status Started for HL401091+5.p
11669.21/2624.92	% SZS status GaveUp for HL401091+5.p
11669.21/2624.92	% SZS status Ended for HL401091+5.p
11681.98/2626.52	% SZS status Started for HL401096+4.p
11681.98/2626.52	% SZS status Theorem for HL401096+4.p
11681.98/2626.52	% SZS status Ended for HL401096+4.p
11688.70/2627.43	% SZS status Started for HL401092+5.p
11688.70/2627.43	% SZS status GaveUp for HL401092+5.p
11688.70/2627.43	% SZS status Ended for HL401092+5.p
11691.52/2627.73	% SZS status Started for HL401093+5.p
11691.52/2627.73	% SZS status GaveUp for HL401093+5.p
11691.52/2627.73	% SZS status Ended for HL401093+5.p
11696.02/2628.28	% SZS status Started for HL401094+4.p
11696.02/2628.28	% SZS status GaveUp for HL401094+4.p
11696.02/2628.28	% SZS status Ended for HL401094+4.p
11697.21/2628.54	% SZS status Started for HL401094+5.p
11697.21/2628.54	% SZS status GaveUp for HL401094+5.p
11697.21/2628.54	% SZS status Ended for HL401094+5.p
11704.65/2629.32	% SZS status Started for HL401095+5.p
11704.65/2629.32	% SZS status GaveUp for HL401095+5.p
11704.65/2629.32	% SZS status Ended for HL401095+5.p
11713.11/2630.40	% SZS status Started for HL401099+4.p
11713.11/2630.40	% SZS status Theorem for HL401099+4.p
11713.11/2630.40	% SZS status Ended for HL401099+4.p
11716.85/2630.91	% SZS status Started for HL401096+5.p
11716.85/2630.91	% SZS status GaveUp for HL401096+5.p
11716.85/2630.91	% SZS status Ended for HL401096+5.p
11721.22/2631.46	% SZS status Started for HL401100+4.p
11721.22/2631.46	% SZS status Theorem for HL401100+4.p
11721.22/2631.46	% SZS status Ended for HL401100+4.p
11726.10/2632.04	% SZS status Started for HL401101+4.p
11726.10/2632.04	% SZS status Theorem for HL401101+4.p
11726.10/2632.04	% SZS status Ended for HL401101+4.p
11735.03/2633.16	% SZS status Started for HL401097+4.p
11735.03/2633.16	% SZS status GaveUp for HL401097+4.p
11735.03/2633.16	% SZS status Ended for HL401097+4.p
11739.94/2633.85	% SZS status Started for HL401103+4.p
11739.94/2633.85	% SZS status Theorem for HL401103+4.p
11739.94/2633.85	% SZS status Ended for HL401103+4.p
11747.75/2634.85	% SZS status Started for HL401097+5.p
11747.75/2634.85	% SZS status GaveUp for HL401097+5.p
11747.75/2634.85	% SZS status Ended for HL401097+5.p
11753.93/2635.61	% SZS status Started for HL401098+4.p
11753.93/2635.61	% SZS status GaveUp for HL401098+4.p
11753.93/2635.61	% SZS status Ended for HL401098+4.p
11758.03/2636.12	% SZS status Started for HL401098+5.p
11758.03/2636.12	% SZS status GaveUp for HL401098+5.p
11758.03/2636.12	% SZS status Ended for HL401098+5.p
11764.60/2636.91	% SZS status Started for HL401099+5.p
11764.60/2636.91	% SZS status GaveUp for HL401099+5.p
11764.60/2636.91	% SZS status Ended for HL401099+5.p
11779.83/2638.79	% SZS status Started for HL401100+5.p
11779.83/2638.79	% SZS status GaveUp for HL401100+5.p
11779.83/2638.79	% SZS status Ended for HL401100+5.p
11787.64/2639.76	% SZS status Started for HL401101+5.p
11787.64/2639.76	% SZS status GaveUp for HL401101+5.p
11787.64/2639.76	% SZS status Ended for HL401101+5.p
11794.92/2640.80	% SZS status Started for HL401109+4.p
11794.92/2640.80	% SZS status Theorem for HL401109+4.p
11794.92/2640.80	% SZS status Ended for HL401109+4.p
11799.57/2641.49	% SZS status Started for HL401103+5.p
11799.57/2641.49	% SZS status GaveUp for HL401103+5.p
11799.57/2641.49	% SZS status Ended for HL401103+5.p
11805.06/2642.08	% SZS status Started for HL401104+4.p
11805.06/2642.08	% SZS status GaveUp for HL401104+4.p
11805.06/2642.08	% SZS status Ended for HL401104+4.p
11808.94/2642.53	% SZS status Started for HL401109+5.p
11808.94/2642.53	% SZS status Theorem for HL401109+5.p
11808.94/2642.53	% SZS status Ended for HL401109+5.p
11814.25/2643.24	% SZS status Started for HL401104+5.p
11814.25/2643.24	% SZS status GaveUp for HL401104+5.p
11814.25/2643.24	% SZS status Ended for HL401104+5.p
11818.16/2643.66	% SZS status Started for HL401112+4.p
11818.16/2643.66	% SZS status Theorem for HL401112+4.p
11818.16/2643.66	% SZS status Ended for HL401112+4.p
11819.56/2643.81	% SZS status Started for HL401105+4.p
11819.56/2643.81	% SZS status GaveUp for HL401105+4.p
11819.56/2643.81	% SZS status Ended for HL401105+4.p
11825.33/2644.50	% SZS status Started for HL401105+5.p
11825.33/2644.50	% SZS status GaveUp for HL401105+5.p
11825.33/2644.50	% SZS status Ended for HL401105+5.p
11827.41/2644.91	% SZS status Started for HL401112+5.p
11827.41/2644.91	% SZS status Theorem for HL401112+5.p
11827.41/2644.91	% SZS status Ended for HL401112+5.p
11830.24/2645.11	% SZS status Started for HL401107+4.p
11830.24/2645.11	% SZS status GaveUp for HL401107+4.p
11830.24/2645.11	% SZS status Ended for HL401107+4.p
11831.93/2645.44	% SZS status Started for HL401113+4.p
11831.93/2645.44	% SZS status Theorem for HL401113+4.p
11831.93/2645.44	% SZS status Ended for HL401113+4.p
11845.87/2647.13	% SZS status Started for HL401107+5.p
11845.87/2647.13	% SZS status GaveUp for HL401107+5.p
11845.87/2647.13	% SZS status Ended for HL401107+5.p
11866.04/2649.63	% SZS status Started for HL401114+4.p
11866.04/2649.63	% SZS status Theorem for HL401114+4.p
11866.04/2649.63	% SZS status Ended for HL401114+4.p
11866.21/2649.71	% SZS status Started for HL401111+4.p
11866.21/2649.71	% SZS status GaveUp for HL401111+4.p
11866.21/2649.71	% SZS status Ended for HL401111+4.p
11872.81/2650.45	% SZS status Started for HL401111+5.p
11872.81/2650.45	% SZS status GaveUp for HL401111+5.p
11872.81/2650.45	% SZS status Ended for HL401111+5.p
11884.86/2652.13	% SZS status Started for HL401113+5.p
11884.86/2652.13	% SZS status GaveUp for HL401113+5.p
11884.86/2652.13	% SZS status Ended for HL401113+5.p
11894.83/2653.22	% SZS status Started for HL401114+5.p
11894.83/2653.22	% SZS status GaveUp for HL401114+5.p
11894.83/2653.22	% SZS status Ended for HL401114+5.p
11895.51/2653.37	% SZS status Started for HL401115+4.p
11895.51/2653.37	% SZS status GaveUp for HL401115+4.p
11895.51/2653.37	% SZS status Ended for HL401115+4.p
11898.89/2653.79	% SZS status Started for HL401115+5.p
11898.89/2653.79	% SZS status GaveUp for HL401115+5.p
11898.89/2653.79	% SZS status Ended for HL401115+5.p
11912.23/2655.44	% SZS status Started for HL401116+4.p
11912.23/2655.44	% SZS status GaveUp for HL401116+4.p
11912.23/2655.44	% SZS status Ended for HL401116+4.p
11931.38/2657.95	% SZS status Started for HL401119+4.p
11931.38/2657.95	% SZS status GaveUp for HL401119+4.p
11931.38/2657.95	% SZS status Ended for HL401119+4.p
11932.63/2658.03	% SZS status Started for HL401116+5.p
11932.63/2658.03	% SZS status GaveUp for HL401116+5.p
11932.63/2658.03	% SZS status Ended for HL401116+5.p
11938.46/2658.76	% SZS status Started for HL401119+5.p
11938.46/2658.76	% SZS status GaveUp for HL401119+5.p
11938.46/2658.76	% SZS status Ended for HL401119+5.p
11952.01/2660.45	% SZS status Started for HL401120+4.p
11952.01/2660.45	% SZS status GaveUp for HL401120+4.p
11952.01/2660.45	% SZS status Ended for HL401120+4.p
11959.87/2661.43	% SZS status Started for HL401126+4.p
11959.87/2661.43	% SZS status Theorem for HL401126+4.p
11959.87/2661.43	% SZS status Ended for HL401126+4.p
11960.69/2661.52	% SZS status Started for HL401120+5.p
11960.69/2661.52	% SZS status GaveUp for HL401120+5.p
11960.69/2661.52	% SZS status Ended for HL401120+5.p
11961.08/2661.64	% SZS status Started for HL401121+4.p
11961.08/2661.64	% SZS status GaveUp for HL401121+4.p
11961.08/2661.64	% SZS status Ended for HL401121+4.p
11964.86/2662.08	% SZS status Started for HL401121+5.p
11964.86/2662.08	% SZS status GaveUp for HL401121+5.p
11964.86/2662.08	% SZS status Ended for HL401121+5.p
11972.14/2662.96	% SZS status Started for HL401128+4.p
11972.14/2662.96	% SZS status Theorem for HL401128+4.p
11972.14/2662.96	% SZS status Ended for HL401128+4.p
11973.08/2663.14	% SZS status Started for HL401126+5.p
11973.08/2663.14	% SZS status Theorem for HL401126+5.p
11973.08/2663.14	% SZS status Ended for HL401126+5.p
11976.80/2663.54	% SZS status Started for HL401127+5.p
11976.80/2663.54	% SZS status Theorem for HL401127+5.p
11976.80/2663.54	% SZS status Ended for HL401127+5.p
11977.85/2663.67	% SZS status Started for HL401124+4.p
11977.85/2663.67	% SZS status GaveUp for HL401124+4.p
11977.85/2663.67	% SZS status Ended for HL401124+4.p
11998.40/2666.31	% SZS status Started for HL401125+4.p
11998.40/2666.31	% SZS status GaveUp for HL401125+4.p
11998.40/2666.31	% SZS status Ended for HL401125+4.p
11999.43/2666.40	% SZS status Started for HL401124+5.p
11999.43/2666.40	% SZS status GaveUp for HL401124+5.p
11999.43/2666.40	% SZS status Ended for HL401124+5.p
12004.57/2667.04	% SZS status Started for HL401125+5.p
12004.57/2667.04	% SZS status GaveUp for HL401125+5.p
12004.57/2667.04	% SZS status Ended for HL401125+5.p
12013.64/2668.20	% SZS status Started for HL401127+4.p
12013.64/2668.20	% SZS status Theorem for HL401127+4.p
12013.64/2668.20	% SZS status Ended for HL401127+4.p
12038.61/2671.31	% SZS status Started for HL401128+5.p
12038.61/2671.31	% SZS status GaveUp for HL401128+5.p
12038.61/2671.31	% SZS status Ended for HL401128+5.p
12039.05/2671.40	% SZS status Started for HL401129+4.p
12039.05/2671.40	% SZS status GaveUp for HL401129+4.p
12039.05/2671.40	% SZS status Ended for HL401129+4.p
12043.15/2671.87	% SZS status Started for HL401129+5.p
12043.15/2671.87	% SZS status GaveUp for HL401129+5.p
12043.15/2671.87	% SZS status Ended for HL401129+5.p
12043.15/2671.88	% SZS status Started for HL401130+4.p
12043.15/2671.88	% SZS status GaveUp for HL401130+4.p
12043.15/2671.88	% SZS status Ended for HL401130+4.p
12044.14/2672.06	% SZS status Started for HL401134+4.p
12044.14/2672.06	% SZS status Theorem for HL401134+4.p
12044.14/2672.06	% SZS status Ended for HL401134+4.p
12064.76/2674.63	% SZS status Started for HL401131+4.p
12064.76/2674.63	% SZS status GaveUp for HL401131+4.p
12064.76/2674.63	% SZS status Ended for HL401131+4.p
12065.09/2674.66	% SZS status Started for HL401130+5.p
12065.09/2674.66	% SZS status GaveUp for HL401130+5.p
12065.09/2674.66	% SZS status Ended for HL401130+5.p
12070.64/2675.41	% SZS status Started for HL401131+5.p
12070.64/2675.41	% SZS status GaveUp for HL401131+5.p
12070.64/2675.41	% SZS status Ended for HL401131+5.p
12079.72/2676.57	% SZS status Started for HL401132+4.p
12079.72/2676.57	% SZS status GaveUp for HL401132+4.p
12079.72/2676.57	% SZS status Ended for HL401132+4.p
12105.21/2679.69	% SZS status Started for HL401132+5.p
12105.21/2679.69	% SZS status GaveUp for HL401132+5.p
12105.21/2679.69	% SZS status Ended for HL401132+5.p
12105.21/2679.72	% SZS status Started for HL401133+4.p
12105.21/2679.72	% SZS status GaveUp for HL401133+4.p
12105.21/2679.72	% SZS status Ended for HL401133+4.p
12109.78/2680.26	% SZS status Started for HL401133+5.p
12109.78/2680.26	% SZS status GaveUp for HL401133+5.p
12109.78/2680.26	% SZS status Ended for HL401133+5.p
12111.15/2680.44	% SZS status Started for HL401134+5.p
12111.15/2680.44	% SZS status GaveUp for HL401134+5.p
12111.15/2680.44	% SZS status Ended for HL401134+5.p
12130.77/2682.90	% SZS status Started for HL401137+4.p
12130.77/2682.90	% SZS status GaveUp for HL401137+4.p
12130.77/2682.90	% SZS status Ended for HL401137+4.p
12131.26/2682.97	% SZS status Started for HL401137+5.p
12131.26/2682.97	% SZS status GaveUp for HL401137+5.p
12131.26/2682.97	% SZS status Ended for HL401137+5.p
12136.24/2683.63	% SZS status Started for HL401138+4.p
12136.24/2683.63	% SZS status GaveUp for HL401138+4.p
12136.24/2683.63	% SZS status Ended for HL401138+4.p
12146.33/2684.96	% SZS status Started for HL401138+5.p
12146.33/2684.96	% SZS status GaveUp for HL401138+5.p
12146.33/2684.96	% SZS status Ended for HL401138+5.p
12170.60/2687.92	% SZS status Started for HL401139+4.p
12170.60/2687.92	% SZS status GaveUp for HL401139+4.p
12170.60/2687.92	% SZS status Ended for HL401139+4.p
12170.89/2688.03	% SZS status Started for HL401139+5.p
12170.89/2688.03	% SZS status GaveUp for HL401139+5.p
12170.89/2688.03	% SZS status Ended for HL401139+5.p
12175.57/2688.52	% SZS status Started for HL401140+4.p
12175.57/2688.52	% SZS status GaveUp for HL401140+4.p
12175.57/2688.52	% SZS status Ended for HL401140+4.p
12177.46/2688.78	% SZS status Started for HL401140+5.p
12177.46/2688.78	% SZS status GaveUp for HL401140+5.p
12177.46/2688.78	% SZS status Ended for HL401140+5.p
12195.49/2691.13	% SZS status Started for HL401141+4.p
12195.49/2691.13	% SZS status GaveUp for HL401141+4.p
12195.49/2691.13	% SZS status Ended for HL401141+4.p
12197.73/2691.40	% SZS status Started for HL401141+5.p
12197.73/2691.40	% SZS status GaveUp for HL401141+5.p
12197.73/2691.40	% SZS status Ended for HL401141+5.p
12201.85/2691.85	% SZS status Started for HL401145+4.p
12201.85/2691.85	% SZS status GaveUp for HL401145+4.p
12201.85/2691.85	% SZS status Ended for HL401145+4.p
12212.88/2693.30	% SZS status Started for HL401145+5.p
12212.88/2693.30	% SZS status GaveUp for HL401145+5.p
12212.88/2693.30	% SZS status Ended for HL401145+5.p
12236.79/2696.27	% SZS status Started for HL401146+4.p
12236.79/2696.27	% SZS status GaveUp for HL401146+4.p
12236.79/2696.27	% SZS status Ended for HL401146+4.p
12237.95/2696.34	% SZS status Started for HL401146+5.p
12237.95/2696.34	% SZS status GaveUp for HL401146+5.p
12237.95/2696.34	% SZS status Ended for HL401146+5.p
12242.85/2696.96	% SZS status Started for HL401147+4.p
12242.85/2696.96	% SZS status GaveUp for HL401147+4.p
12242.85/2696.96	% SZS status Ended for HL401147+4.p
12244.36/2697.20	% SZS status Started for HL401147+5.p
12244.36/2697.20	% SZS status GaveUp for HL401147+5.p
12244.36/2697.20	% SZS status Ended for HL401147+5.p
12261.15/2699.33	% SZS status Started for HL401148+4.p
12261.15/2699.33	% SZS status GaveUp for HL401148+4.p
12261.15/2699.33	% SZS status Ended for HL401148+4.p
12262.94/2699.73	% SZS status Started for HL401148+5.p
12262.94/2699.73	% SZS status GaveUp for HL401148+5.p
12262.94/2699.73	% SZS status Ended for HL401148+5.p
12267.69/2700.15	% SZS status Started for HL401149+4.p
12267.69/2700.15	% SZS status GaveUp for HL401149+4.p
12267.69/2700.15	% SZS status Ended for HL401149+4.p
12269.89/2700.41	% SZS status Started for HL401153+4.p
12269.89/2700.41	% SZS status Theorem for HL401153+4.p
12269.89/2700.41	% SZS status Ended for HL401153+4.p
12271.04/2700.57	% SZS status Started for HL401150+4.p
12271.04/2700.57	% SZS status Theorem for HL401150+4.p
12271.04/2700.57	% SZS status Ended for HL401150+4.p
12274.14/2700.90	% SZS status Started for HL401154+4.p
12274.14/2700.90	% SZS status Theorem for HL401154+4.p
12274.14/2700.90	% SZS status Ended for HL401154+4.p
12279.26/2701.62	% SZS status Started for HL401149+5.p
12279.26/2701.62	% SZS status GaveUp for HL401149+5.p
12279.26/2701.62	% SZS status Ended for HL401149+5.p
12303.54/2704.68	% SZS status Started for HL401150+5.p
12303.54/2704.68	% SZS status GaveUp for HL401150+5.p
12303.54/2704.68	% SZS status Ended for HL401150+5.p
12307.70/2705.31	% SZS status Started for HL401151+4.p
12307.70/2705.31	% SZS status GaveUp for HL401151+4.p
12307.70/2705.31	% SZS status Ended for HL401151+4.p
12311.10/2705.55	% SZS status Started for HL401151+5.p
12311.10/2705.55	% SZS status GaveUp for HL401151+5.p
12311.10/2705.55	% SZS status Ended for HL401151+5.p
12326.60/2707.55	% SZS status Started for HL401152+4.p
12326.60/2707.55	% SZS status GaveUp for HL401152+4.p
12326.60/2707.55	% SZS status Ended for HL401152+4.p
12329.90/2708.07	% SZS status Started for HL401152+5.p
12329.90/2708.07	% SZS status GaveUp for HL401152+5.p
12329.90/2708.07	% SZS status Ended for HL401152+5.p
12335.42/2708.72	% SZS status Started for HL401153+5.p
12335.42/2708.72	% SZS status GaveUp for HL401153+5.p
12335.42/2708.72	% SZS status Ended for HL401153+5.p
12339.71/2709.25	% SZS status Started for HL401154+5.p
12339.71/2709.25	% SZS status GaveUp for HL401154+5.p
12339.71/2709.25	% SZS status Ended for HL401154+5.p
12346.24/2709.98	% SZS status Started for HL401155+4.p
12346.24/2709.98	% SZS status GaveUp for HL401155+4.p
12346.24/2709.98	% SZS status Ended for HL401155+4.p
12370.37/2713.07	% SZS status Started for HL401155+5.p
12370.37/2713.07	% SZS status GaveUp for HL401155+5.p
12370.37/2713.07	% SZS status Ended for HL401155+5.p
12375.12/2713.62	% SZS status Started for HL401156+4.p
12375.12/2713.62	% SZS status GaveUp for HL401156+4.p
12375.12/2713.62	% SZS status Ended for HL401156+4.p
12376.75/2713.86	% SZS status Started for HL401156+5.p
12376.75/2713.86	% SZS status GaveUp for HL401156+5.p
12376.75/2713.86	% SZS status Ended for HL401156+5.p
12392.38/2715.81	% SZS status Started for HL401157+4.p
12392.38/2715.81	% SZS status GaveUp for HL401157+4.p
12392.38/2715.81	% SZS status Ended for HL401157+4.p
12397.20/2716.39	% SZS status Started for HL401157+5.p
12397.20/2716.39	% SZS status GaveUp for HL401157+5.p
12397.20/2716.39	% SZS status Ended for HL401157+5.p
12402.47/2717.10	% SZS status Started for HL401158+4.p
12402.47/2717.10	% SZS status GaveUp for HL401158+4.p
12402.47/2717.10	% SZS status Ended for HL401158+4.p
12406.49/2717.58	% SZS status Started for HL401158+5.p
12406.49/2717.58	% SZS status GaveUp for HL401158+5.p
12406.49/2717.58	% SZS status Ended for HL401158+5.p
12412.26/2718.32	% SZS status Started for HL401159+4.p
12412.26/2718.32	% SZS status GaveUp for HL401159+4.p
12412.26/2718.32	% SZS status Ended for HL401159+4.p
12437.06/2721.40	% SZS status Started for HL401159+5.p
12437.06/2721.40	% SZS status GaveUp for HL401159+5.p
12437.06/2721.40	% SZS status Ended for HL401159+5.p
12441.04/2721.88	% SZS status Started for HL401160+4.p
12441.04/2721.88	% SZS status GaveUp for HL401160+4.p
12441.04/2721.88	% SZS status Ended for HL401160+4.p
12443.07/2722.22	% SZS status Started for HL401160+5.p
12443.07/2722.22	% SZS status GaveUp for HL401160+5.p
12443.07/2722.22	% SZS status Ended for HL401160+5.p
12457.28/2724.03	% SZS status Started for HL401161+4.p
12457.28/2724.03	% SZS status GaveUp for HL401161+4.p
12457.28/2724.03	% SZS status Ended for HL401161+4.p
12464.60/2724.81	% SZS status Started for HL401161+5.p
12464.60/2724.81	% SZS status GaveUp for HL401161+5.p
12464.60/2724.81	% SZS status Ended for HL401161+5.p
12468.75/2725.38	% SZS status Started for HL401163+4.p
12468.75/2725.38	% SZS status GaveUp for HL401163+4.p
12468.75/2725.38	% SZS status Ended for HL401163+4.p
12473.29/2725.93	% SZS status Started for HL401163+5.p
12473.29/2725.93	% SZS status GaveUp for HL401163+5.p
12473.29/2725.93	% SZS status Ended for HL401163+5.p
12477.82/2726.54	% SZS status Started for HL401165+4.p
12477.82/2726.54	% SZS status GaveUp for HL401165+4.p
12477.82/2726.54	% SZS status Ended for HL401165+4.p
12503.91/2729.81	% SZS status Started for HL401165+5.p
12503.91/2729.81	% SZS status GaveUp for HL401165+5.p
12503.91/2729.81	% SZS status Ended for HL401165+5.p
12514.32/2730.16	% SZS status Started for HL401166+4.p
12514.32/2730.16	% SZS status GaveUp for HL401166+4.p
12514.32/2730.16	% SZS status Ended for HL401166+4.p
12517.49/2730.54	% SZS status Started for HL401166+5.p
12517.49/2730.54	% SZS status GaveUp for HL401166+5.p
12517.49/2730.54	% SZS status Ended for HL401166+5.p
12531.52/2732.29	% SZS status Started for HL401167+4.p
12531.52/2732.29	% SZS status GaveUp for HL401167+4.p
12531.52/2732.29	% SZS status Ended for HL401167+4.p
12538.47/2733.17	% SZS status Started for HL401167+5.p
12538.47/2733.17	% SZS status GaveUp for HL401167+5.p
12538.47/2733.17	% SZS status Ended for HL401167+5.p
12541.30/2733.59	% SZS status Started for HL401168+4.p
12541.30/2733.59	% SZS status GaveUp for HL401168+4.p
12541.30/2733.59	% SZS status Ended for HL401168+4.p
12548.34/2734.37	% SZS status Started for HL401168+5.p
12548.34/2734.37	% SZS status GaveUp for HL401168+5.p
12548.34/2734.37	% SZS status Ended for HL401168+5.p
12551.80/2734.81	% SZS status Started for HL401169+4.p
12551.80/2734.81	% SZS status GaveUp for HL401169+4.p
12551.80/2734.81	% SZS status Ended for HL401169+4.p
12578.35/2738.15	% SZS status Started for HL401169+5.p
12578.35/2738.15	% SZS status GaveUp for HL401169+5.p
12578.35/2738.15	% SZS status Ended for HL401169+5.p
12579.75/2738.40	% SZS status Started for HL401170+4.p
12579.75/2738.40	% SZS status GaveUp for HL401170+4.p
12579.75/2738.40	% SZS status Ended for HL401170+4.p
12582.13/2738.64	% SZS status Started for HL401174+4.p
12582.13/2738.64	% SZS status Theorem for HL401174+4.p
12582.13/2738.64	% SZS status Ended for HL401174+4.p
12583.50/2738.85	% SZS status Started for HL401170+5.p
12583.50/2738.85	% SZS status GaveUp for HL401170+5.p
12583.50/2738.85	% SZS status Ended for HL401170+5.p
12594.37/2740.37	% SZS status Started for HL401174+5.p
12594.37/2740.37	% SZS status Theorem for HL401174+5.p
12594.37/2740.37	% SZS status Ended for HL401174+5.p
12597.68/2740.62	% SZS status Started for HL401171+4.p
12597.68/2740.62	% SZS status GaveUp for HL401171+4.p
12597.68/2740.62	% SZS status Ended for HL401171+4.p
12604.50/2741.48	% SZS status Started for HL401171+5.p
12604.50/2741.48	% SZS status GaveUp for HL401171+5.p
12604.50/2741.48	% SZS status Ended for HL401171+5.p
12608.36/2741.95	% SZS status Started for HL401172+4.p
12608.36/2741.95	% SZS status GaveUp for HL401172+4.p
12608.36/2741.95	% SZS status Ended for HL401172+4.p
12615.15/2742.75	% SZS status Started for HL401172+5.p
12615.15/2742.75	% SZS status GaveUp for HL401172+5.p
12615.15/2742.75	% SZS status Ended for HL401172+5.p
12617.11/2743.08	% SZS status Started for HL401173+4.p
12617.11/2743.08	% SZS status GaveUp for HL401173+4.p
12617.11/2743.08	% SZS status Ended for HL401173+4.p
12643.75/2746.36	% SZS status Started for HL401178+4.p
12643.75/2746.36	% SZS status Theorem for HL401178+4.p
12643.75/2746.36	% SZS status Ended for HL401178+4.p
12644.59/2746.53	% SZS status Started for HL401173+5.p
12644.59/2746.53	% SZS status GaveUp for HL401173+5.p
12644.59/2746.53	% SZS status Ended for HL401173+5.p
12649.49/2747.06	% SZS status Started for HL401175+4.p
12649.49/2747.06	% SZS status GaveUp for HL401175+4.p
12649.49/2747.06	% SZS status Ended for HL401175+4.p
12662.01/2748.70	% SZS status Started for HL401175+5.p
12662.01/2748.70	% SZS status GaveUp for HL401175+5.p
12662.01/2748.70	% SZS status Ended for HL401175+5.p
12664.58/2748.96	% SZS status Started for HL401176+4.p
12664.58/2748.96	% SZS status GaveUp for HL401176+4.p
12664.58/2748.96	% SZS status Ended for HL401176+4.p
12671.00/2749.81	% SZS status Started for HL401176+5.p
12671.00/2749.81	% SZS status GaveUp for HL401176+5.p
12671.00/2749.81	% SZS status Ended for HL401176+5.p
12674.01/2750.24	% SZS status Started for HL401177+4.p
12674.01/2750.24	% SZS status GaveUp for HL401177+4.p
12674.01/2750.24	% SZS status Ended for HL401177+4.p
12680.98/2751.11	% SZS status Started for HL401177+5.p
12680.98/2751.11	% SZS status GaveUp for HL401177+5.p
12680.98/2751.11	% SZS status Ended for HL401177+5.p
12709.57/2754.73	% SZS status Started for HL401178+5.p
12709.57/2754.73	% SZS status GaveUp for HL401178+5.p
12709.57/2754.73	% SZS status Ended for HL401178+5.p
12710.22/2754.76	% SZS status Started for HL401179+4.p
12710.22/2754.76	% SZS status GaveUp for HL401179+4.p
12710.22/2754.76	% SZS status Ended for HL401179+4.p
12715.99/2755.48	% SZS status Started for HL401179+5.p
12715.99/2755.48	% SZS status GaveUp for HL401179+5.p
12715.99/2755.48	% SZS status Ended for HL401179+5.p
12727.78/2756.94	% SZS status Started for HL401183+4.p
12727.78/2756.94	% SZS status Theorem for HL401183+4.p
12727.78/2756.94	% SZS status Ended for HL401183+4.p
12728.30/2756.97	% SZS status Started for HL401180+4.p
12728.30/2756.97	% SZS status GaveUp for HL401180+4.p
12728.30/2756.97	% SZS status Ended for HL401180+4.p
12729.40/2757.19	% SZS status Started for HL401183+5.p
12729.40/2757.19	% SZS status Theorem for HL401183+5.p
12729.40/2757.19	% SZS status Ended for HL401183+5.p
12729.65/2757.28	% SZS status Started for HL401180+5.p
12729.65/2757.28	% SZS status GaveUp for HL401180+5.p
12729.65/2757.28	% SZS status Ended for HL401180+5.p
12737.51/2758.12	% SZS status Started for HL401181+4.p
12737.51/2758.12	% SZS status GaveUp for HL401181+4.p
12737.51/2758.12	% SZS status Ended for HL401181+4.p
12739.79/2758.58	% SZS status Started for HL401181+5.p
12739.79/2758.58	% SZS status GaveUp for HL401181+5.p
12739.79/2758.58	% SZS status Ended for HL401181+5.p
12746.65/2759.43	% SZS status Started for HL401182+4.p
12746.65/2759.43	% SZS status GaveUp for HL401182+4.p
12746.65/2759.43	% SZS status Ended for HL401182+4.p
12775.34/2763.04	% SZS status Started for HL401182+5.p
12775.34/2763.04	% SZS status GaveUp for HL401182+5.p
12775.34/2763.04	% SZS status Ended for HL401182+5.p
12791.90/2764.95	% SZS status Started for HL401186+4.p
12791.90/2764.95	% SZS status Theorem for HL401186+4.p
12791.90/2764.95	% SZS status Ended for HL401186+4.p
12793.42/2765.21	% SZS status Started for HL401184+4.p
12793.42/2765.21	% SZS status GaveUp for HL401184+4.p
12793.42/2765.21	% SZS status Ended for HL401184+4.p
12793.65/2765.32	% SZS status Started for HL401184+5.p
12793.65/2765.32	% SZS status GaveUp for HL401184+5.p
12793.65/2765.32	% SZS status Ended for HL401184+5.p
12796.35/2765.51	% SZS status Started for HL401185+4.p
12796.35/2765.51	% SZS status GaveUp for HL401185+4.p
12796.35/2765.51	% SZS status Ended for HL401185+4.p
12796.58/2765.61	% SZS status Started for HL401185+5.p
12796.58/2765.61	% SZS status GaveUp for HL401185+5.p
12796.58/2765.61	% SZS status Ended for HL401185+5.p
12806.70/2766.91	% SZS status Started for HL401186+5.p
12806.70/2766.91	% SZS status GaveUp for HL401186+5.p
12806.70/2766.91	% SZS status Ended for HL401186+5.p
12813.74/2767.73	% SZS status Started for HL401187+4.p
12813.74/2767.73	% SZS status GaveUp for HL401187+4.p
12813.74/2767.73	% SZS status Ended for HL401187+4.p
12814.84/2767.94	% SZS status Started for HL401191+4.p
12814.84/2767.94	% SZS status Theorem for HL401191+4.p
12814.84/2767.94	% SZS status Ended for HL401191+4.p
12829.27/2769.66	% SZS status Started for HL401191+5.p
12829.27/2769.66	% SZS status Theorem for HL401191+5.p
12829.27/2769.66	% SZS status Ended for HL401191+5.p
12841.32/2771.35	% SZS status Started for HL401187+5.p
12841.32/2771.35	% SZS status GaveUp for HL401187+5.p
12841.32/2771.35	% SZS status Ended for HL401187+5.p
12856.27/2773.24	% SZS status Started for HL401188+4.p
12856.27/2773.24	% SZS status GaveUp for HL401188+4.p
12856.27/2773.24	% SZS status Ended for HL401188+4.p
12859.35/2773.46	% SZS status Started for HL401194+4.p
12859.35/2773.46	% SZS status Theorem for HL401194+4.p
12859.35/2773.46	% SZS status Ended for HL401194+4.p
12860.61/2773.59	% SZS status Started for HL401188+5.p
12860.61/2773.59	% SZS status GaveUp for HL401188+5.p
12860.61/2773.59	% SZS status Ended for HL401188+5.p
12860.78/2773.62	% SZS status Started for HL401189+4.p
12860.78/2773.62	% SZS status GaveUp for HL401189+4.p
12860.78/2773.62	% SZS status Ended for HL401189+4.p
12861.53/2773.82	% SZS status Started for HL401189+5.p
12861.53/2773.82	% SZS status GaveUp for HL401189+5.p
12861.53/2773.82	% SZS status Ended for HL401189+5.p
12863.59/2774.01	% SZS status Started for HL401190+4.p
12863.59/2774.01	% SZS status GaveUp for HL401190+4.p
12863.59/2774.01	% SZS status Ended for HL401190+4.p
12870.10/2774.86	% SZS status Started for HL401195+4.p
12870.10/2774.86	% SZS status Theorem for HL401195+4.p
12870.10/2774.86	% SZS status Ended for HL401195+4.p
12872.51/2775.08	% SZS status Started for HL401196+4.p
12872.51/2775.08	% SZS status Theorem for HL401196+4.p
12872.51/2775.08	% SZS status Ended for HL401196+4.p
12873.20/2775.21	% SZS status Started for HL401194+5.p
12873.20/2775.21	% SZS status Theorem for HL401194+5.p
12873.20/2775.21	% SZS status Ended for HL401194+5.p
12873.62/2775.25	% SZS status Started for HL401190+5.p
12873.62/2775.25	% SZS status GaveUp for HL401190+5.p
12873.62/2775.25	% SZS status Ended for HL401190+5.p
12877.81/2775.74	% SZS status Started for HL401196+5.p
12877.81/2775.74	% SZS status Theorem for HL401196+5.p
12877.81/2775.74	% SZS status Ended for HL401196+5.p
12895.32/2777.98	% SZS status Started for HL401193+4.p
12895.32/2777.98	% SZS status GaveUp for HL401193+4.p
12895.32/2777.98	% SZS status Ended for HL401193+4.p
12908.17/2779.66	% SZS status Started for HL401193+5.p
12908.17/2779.66	% SZS status GaveUp for HL401193+5.p
12908.17/2779.66	% SZS status Ended for HL401193+5.p
12909.09/2779.82	% SZS status Started for HL401195+5.p
12909.09/2779.82	% SZS status Theorem for HL401195+5.p
12909.09/2779.82	% SZS status Ended for HL401195+5.p
12935.95/2783.08	% SZS status Started for HL401197+4.p
12935.95/2783.08	% SZS status GaveUp for HL401197+4.p
12935.95/2783.08	% SZS status Ended for HL401197+4.p
12937.45/2783.39	% SZS status Started for HL401197+5.p
12937.45/2783.39	% SZS status GaveUp for HL401197+5.p
12937.45/2783.39	% SZS status Ended for HL401197+5.p
12940.33/2783.59	% SZS status Started for HL401198+4.p
12940.33/2783.59	% SZS status GaveUp for HL401198+4.p
12940.33/2783.59	% SZS status Ended for HL401198+4.p
12940.72/2783.64	% SZS status Started for HL401198+5.p
12940.72/2783.64	% SZS status GaveUp for HL401198+5.p
12940.72/2783.64	% SZS status Ended for HL401198+5.p
12942.51/2784.00	% SZS status Started for HL401199+4.p
12942.51/2784.00	% SZS status GaveUp for HL401199+4.p
12942.51/2784.00	% SZS status Ended for HL401199+4.p
12955.17/2785.54	% SZS status Started for HL401203+4.p
12955.17/2785.54	% SZS status Theorem for HL401203+4.p
12955.17/2785.54	% SZS status Ended for HL401203+4.p
12961.78/2786.29	% SZS status Started for HL401199+5.p
12961.78/2786.29	% SZS status GaveUp for HL401199+5.p
12961.78/2786.29	% SZS status Ended for HL401199+5.p
12973.66/2787.90	% SZS status Started for HL401200+4.p
12973.66/2787.90	% SZS status GaveUp for HL401200+4.p
12973.66/2787.90	% SZS status Ended for HL401200+4.p
12976.46/2788.13	% SZS status Started for HL401200+5.p
12976.46/2788.13	% SZS status GaveUp for HL401200+5.p
12976.46/2788.13	% SZS status Ended for HL401200+5.p
13001.55/2791.38	% SZS status Started for HL401202+4.p
13001.55/2791.38	% SZS status GaveUp for HL401202+4.p
13001.55/2791.38	% SZS status Ended for HL401202+4.p
13004.62/2791.72	% SZS status Started for HL401202+5.p
13004.62/2791.72	% SZS status GaveUp for HL401202+5.p
13004.62/2791.72	% SZS status Ended for HL401202+5.p
13005.46/2791.95	% SZS status Started for HL401203+5.p
13005.46/2791.95	% SZS status GaveUp for HL401203+5.p
13005.46/2791.95	% SZS status Ended for HL401203+5.p
13009.23/2792.30	% SZS status Started for HL401204+4.p
13009.23/2792.30	% SZS status GaveUp for HL401204+4.p
13009.23/2792.30	% SZS status Ended for HL401204+4.p
13021.88/2793.86	% SZS status Started for HL401204+5.p
13021.88/2793.86	% SZS status GaveUp for HL401204+5.p
13021.88/2793.86	% SZS status Ended for HL401204+5.p
13027.17/2794.52	% SZS status Started for HL401205+4.p
13027.17/2794.52	% SZS status GaveUp for HL401205+4.p
13027.17/2794.52	% SZS status Ended for HL401205+4.p
13041.07/2796.32	% SZS status Started for HL401205+5.p
13041.07/2796.32	% SZS status GaveUp for HL401205+5.p
13041.07/2796.32	% SZS status Ended for HL401205+5.p
13041.74/2796.41	% SZS status Started for HL401206+4.p
13041.74/2796.41	% SZS status GaveUp for HL401206+4.p
13041.74/2796.41	% SZS status Ended for HL401206+4.p
13068.15/2799.70	% SZS status Started for HL401206+5.p
13068.15/2799.70	% SZS status GaveUp for HL401206+5.p
13068.15/2799.70	% SZS status Ended for HL401206+5.p
13070.02/2799.96	% SZS status Started for HL401207+4.p
13070.02/2799.96	% SZS status GaveUp for HL401207+4.p
13070.02/2799.96	% SZS status Ended for HL401207+4.p
13072.33/2800.23	% SZS status Started for HL401207+5.p
13072.33/2800.23	% SZS status GaveUp for HL401207+5.p
13072.33/2800.23	% SZS status Ended for HL401207+5.p
13075.10/2800.53	% SZS status Started for HL401208+4.p
13075.10/2800.53	% SZS status GaveUp for HL401208+4.p
13075.10/2800.53	% SZS status Ended for HL401208+4.p
13088.44/2802.20	% SZS status Started for HL401208+5.p
13088.44/2802.20	% SZS status GaveUp for HL401208+5.p
13088.44/2802.20	% SZS status Ended for HL401208+5.p
13093.23/2802.81	% SZS status Started for HL401210+4.p
13093.23/2802.81	% SZS status GaveUp for HL401210+4.p
13093.23/2802.81	% SZS status Ended for HL401210+4.p
13107.54/2804.68	% SZS status Started for HL401211+4.p
13107.54/2804.68	% SZS status GaveUp for HL401211+4.p
13107.54/2804.68	% SZS status Ended for HL401211+4.p
13108.34/2804.69	% SZS status Started for HL401210+5.p
13108.34/2804.69	% SZS status GaveUp for HL401210+5.p
13108.34/2804.69	% SZS status Ended for HL401210+5.p
13134.80/2808.04	% SZS status Started for HL401211+5.p
13134.80/2808.04	% SZS status GaveUp for HL401211+5.p
13134.80/2808.04	% SZS status Ended for HL401211+5.p
13136.07/2808.21	% SZS status Started for HL401212+4.p
13136.07/2808.21	% SZS status GaveUp for HL401212+4.p
13136.07/2808.21	% SZS status Ended for HL401212+4.p
13137.53/2808.49	% SZS status Started for HL401212+5.p
13137.53/2808.49	% SZS status GaveUp for HL401212+5.p
13137.53/2808.49	% SZS status Ended for HL401212+5.p
13140.76/2808.78	% SZS status Started for HL401214+4.p
13140.76/2808.78	% SZS status GaveUp for HL401214+4.p
13140.76/2808.78	% SZS status Ended for HL401214+4.p
13154.69/2810.57	% SZS status Started for HL401214+5.p
13154.69/2810.57	% SZS status GaveUp for HL401214+5.p
13154.69/2810.57	% SZS status Ended for HL401214+5.p
13158.93/2811.09	% SZS status Started for HL401215+4.p
13158.93/2811.09	% SZS status GaveUp for HL401215+4.p
13158.93/2811.09	% SZS status Ended for HL401215+4.p
13173.06/2812.93	% SZS status Started for HL401215+5.p
13173.06/2812.93	% SZS status GaveUp for HL401215+5.p
13173.06/2812.93	% SZS status Ended for HL401215+5.p
13173.35/2813.04	% SZS status Started for HL401216+4.p
13173.35/2813.04	% SZS status GaveUp for HL401216+4.p
13173.35/2813.04	% SZS status Ended for HL401216+4.p
13200.02/2816.31	% SZS status Started for HL401216+5.p
13200.02/2816.31	% SZS status GaveUp for HL401216+5.p
13200.02/2816.31	% SZS status Ended for HL401216+5.p
13202.77/2816.60	% SZS status Started for HL401218+4.p
13202.77/2816.60	% SZS status GaveUp for HL401218+4.p
13202.77/2816.60	% SZS status Ended for HL401218+4.p
13203.73/2816.75	% SZS status Started for HL401218+5.p
13203.73/2816.75	% SZS status GaveUp for HL401218+5.p
13203.73/2816.75	% SZS status Ended for HL401218+5.p
13206.23/2817.01	% SZS status Started for HL401219+4.p
13206.23/2817.01	% SZS status GaveUp for HL401219+4.p
13206.23/2817.01	% SZS status Ended for HL401219+4.p
13220.82/2818.84	% SZS status Started for HL401219+5.p
13220.82/2818.84	% SZS status GaveUp for HL401219+5.p
13220.82/2818.84	% SZS status Ended for HL401219+5.p
13225.03/2819.37	% SZS status Started for HL401220+4.p
13225.03/2819.37	% SZS status GaveUp for HL401220+4.p
13225.03/2819.37	% SZS status Ended for HL401220+4.p
13240.56/2821.30	% SZS status Started for HL401221+4.p
13240.56/2821.30	% SZS status GaveUp for HL401221+4.p
13240.56/2821.30	% SZS status Ended for HL401221+4.p
13240.56/2821.37	% SZS status Started for HL401220+5.p
13240.56/2821.37	% SZS status GaveUp for HL401220+5.p
13240.56/2821.37	% SZS status Ended for HL401220+5.p
13245.11/2821.94	% SZS status Started for HL401225+4.p
13245.11/2821.94	% SZS status Theorem for HL401225+4.p
13245.11/2821.94	% SZS status Ended for HL401225+4.p
13266.26/2824.57	% SZS status Started for HL401221+5.p
13266.26/2824.57	% SZS status GaveUp for HL401221+5.p
13266.26/2824.57	% SZS status Ended for HL401221+5.p
13267.91/2824.86	% SZS status Started for HL401222+4.p
13267.91/2824.86	% SZS status GaveUp for HL401222+4.p
13267.91/2824.86	% SZS status Ended for HL401222+4.p
13271.16/2825.21	% SZS status Started for HL401222+5.p
13271.16/2825.21	% SZS status GaveUp for HL401222+5.p
13271.16/2825.21	% SZS status Ended for HL401222+5.p
13271.34/2825.27	% SZS status Started for HL401223+4.p
13271.34/2825.27	% SZS status GaveUp for HL401223+4.p
13271.34/2825.27	% SZS status Ended for HL401223+4.p
13286.03/2827.11	% SZS status Started for HL401223+5.p
13286.03/2827.11	% SZS status GaveUp for HL401223+5.p
13286.03/2827.11	% SZS status Ended for HL401223+5.p
13306.88/2829.64	% SZS status Started for HL401225+5.p
13306.88/2829.64	% SZS status GaveUp for HL401225+5.p
13306.88/2829.64	% SZS status Ended for HL401225+5.p
13306.88/2829.67	% SZS status Started for HL401226+4.p
13306.88/2829.67	% SZS status GaveUp for HL401226+4.p
13306.88/2829.67	% SZS status Ended for HL401226+4.p
13312.04/2830.28	% SZS status Started for HL401226+5.p
13312.04/2830.28	% SZS status GaveUp for HL401226+5.p
13312.04/2830.28	% SZS status Ended for HL401226+5.p
13312.74/2830.35	% SZS status Started for HL401229+4.p
13312.74/2830.35	% SZS status Theorem for HL401229+4.p
13312.74/2830.35	% SZS status Ended for HL401229+4.p
13331.02/2832.86	% SZS status Started for HL401227+4.p
13331.02/2832.86	% SZS status GaveUp for HL401227+4.p
13331.02/2832.86	% SZS status Ended for HL401227+4.p
13334.07/2833.13	% SZS status Started for HL401227+5.p
13334.07/2833.13	% SZS status GaveUp for HL401227+5.p
13334.07/2833.13	% SZS status Ended for HL401227+5.p
13338.07/2833.55	% SZS status Started for HL401228+5.p
13338.07/2833.55	% SZS status GaveUp for HL401228+5.p
13338.07/2833.55	% SZS status Ended for HL401228+5.p
13338.07/2833.58	% SZS status Started for HL401228+4.p
13338.07/2833.58	% SZS status GaveUp for HL401228+4.p
13338.07/2833.58	% SZS status Ended for HL401228+4.p
13355.71/2835.90	% SZS status Started for HL401234+4.p
13355.71/2835.90	% SZS status Theorem for HL401234+4.p
13355.71/2835.90	% SZS status Ended for HL401234+4.p
13372.87/2837.96	% SZS status Started for HL401229+5.p
13372.87/2837.96	% SZS status GaveUp for HL401229+5.p
13372.87/2837.96	% SZS status Ended for HL401229+5.p
13372.87/2837.99	% SZS status Started for HL401230+4.p
13372.87/2837.99	% SZS status GaveUp for HL401230+4.p
13372.87/2837.99	% SZS status Ended for HL401230+4.p
13377.43/2838.54	% SZS status Started for HL401230+5.p
13377.43/2838.54	% SZS status GaveUp for HL401230+5.p
13377.43/2838.54	% SZS status Ended for HL401230+5.p
13378.50/2838.67	% SZS status Started for HL401231+4.p
13378.50/2838.67	% SZS status GaveUp for HL401231+4.p
13378.50/2838.67	% SZS status Ended for HL401231+4.p
13397.98/2841.12	% SZS status Started for HL401231+5.p
13397.98/2841.12	% SZS status GaveUp for HL401231+5.p
13397.98/2841.12	% SZS status Ended for HL401231+5.p
13400.49/2841.40	% SZS status Started for HL401232+4.p
13400.49/2841.40	% SZS status GaveUp for HL401232+4.p
13400.49/2841.40	% SZS status Ended for HL401232+4.p
13403.24/2841.84	% SZS status Started for HL401232+5.p
13403.24/2841.84	% SZS status GaveUp for HL401232+5.p
13403.24/2841.84	% SZS status Ended for HL401232+5.p
13422.25/2844.17	% SZS status Started for HL401234+5.p
13422.25/2844.17	% SZS status GaveUp for HL401234+5.p
13422.25/2844.17	% SZS status Ended for HL401234+5.p
13439.74/2846.32	% SZS status Started for HL401235+4.p
13439.74/2846.32	% SZS status GaveUp for HL401235+4.p
13439.74/2846.32	% SZS status Ended for HL401235+4.p
13439.74/2846.33	% SZS status Started for HL401235+5.p
13439.74/2846.33	% SZS status GaveUp for HL401235+5.p
13439.74/2846.33	% SZS status Ended for HL401235+5.p
13441.60/2846.78	% SZS status Started for HL401236+4.p
13441.60/2846.78	% SZS status GaveUp for HL401236+4.p
13441.60/2846.78	% SZS status Ended for HL401236+4.p
13443.94/2846.89	% SZS status Started for HL401236+5.p
13443.94/2846.89	% SZS status GaveUp for HL401236+5.p
13443.94/2846.89	% SZS status Ended for HL401236+5.p
13463.86/2849.44	% SZS status Started for HL401238+4.p
13463.86/2849.44	% SZS status GaveUp for HL401238+4.p
13463.86/2849.44	% SZS status Ended for HL401238+4.p
13465.47/2849.54	% SZS status Started for HL401238+5.p
13465.47/2849.54	% SZS status GaveUp for HL401238+5.p
13465.47/2849.54	% SZS status Ended for HL401238+5.p
13467.86/2850.07	% SZS status Started for HL401239+4.p
13467.86/2850.07	% SZS status GaveUp for HL401239+4.p
13467.86/2850.07	% SZS status Ended for HL401239+4.p
13473.15/2850.63	% SZS status Started for HL401242+5.p
13473.15/2850.63	% SZS status Theorem for HL401242+5.p
13473.15/2850.63	% SZS status Ended for HL401242+5.p
13488.10/2852.39	% SZS status Started for HL401239+5.p
13488.10/2852.39	% SZS status GaveUp for HL401239+5.p
13488.10/2852.39	% SZS status Ended for HL401239+5.p
13504.88/2854.52	% SZS status Started for HL401240+5.p
13504.88/2854.52	% SZS status GaveUp for HL401240+5.p
13504.88/2854.52	% SZS status Ended for HL401240+5.p
13505.06/2854.59	% SZS status Started for HL401240+4.p
13505.06/2854.59	% SZS status GaveUp for HL401240+4.p
13505.06/2854.59	% SZS status Ended for HL401240+4.p
13508.19/2854.91	% SZS status Started for HL401247+4.p
13508.19/2854.91	% SZS status Theorem for HL401247+4.p
13508.19/2854.91	% SZS status Ended for HL401247+4.p
13509.06/2855.07	% SZS status Started for HL401241+5.p
13509.06/2855.07	% SZS status GaveUp for HL401241+5.p
13509.06/2855.07	% SZS status Ended for HL401241+5.p
13509.27/2855.09	% SZS status Started for HL401241+4.p
13509.27/2855.09	% SZS status GaveUp for HL401241+4.p
13509.27/2855.09	% SZS status Ended for HL401241+4.p
13509.53/2855.17	% SZS status Started for HL401247+5.p
13509.53/2855.17	% SZS status Theorem for HL401247+5.p
13509.53/2855.17	% SZS status Ended for HL401247+5.p
13511.91/2855.37	% SZS status Started for HL401248+4.p
13511.91/2855.37	% SZS status Theorem for HL401248+4.p
13511.91/2855.37	% SZS status Ended for HL401248+4.p
13512.29/2855.52	% SZS status Started for HL401248+5.p
13512.29/2855.52	% SZS status Theorem for HL401248+5.p
13512.29/2855.52	% SZS status Ended for HL401248+5.p
13513.77/2855.80	% SZS status Started for HL401250+4.p
13513.77/2855.80	% SZS status Theorem for HL401250+4.p
13513.77/2855.80	% SZS status Ended for HL401250+4.p
13517.92/2856.21	% SZS status Started for HL401250+5.p
13517.92/2856.21	% SZS status Theorem for HL401250+5.p
13517.92/2856.21	% SZS status Ended for HL401250+5.p
13519.70/2856.46	% SZS status Started for HL401249+4.p
13519.70/2856.46	% SZS status Theorem for HL401249+4.p
13519.70/2856.46	% SZS status Ended for HL401249+4.p
13520.51/2856.55	% SZS status Started for HL401251+4.p
13520.51/2856.55	% SZS status Theorem for HL401251+4.p
13520.51/2856.55	% SZS status Ended for HL401251+4.p
13529.63/2857.71	% SZS status Started for HL401242+4.p
13529.63/2857.71	% SZS status GaveUp for HL401242+4.p
13529.63/2857.71	% SZS status Ended for HL401242+4.p
13534.16/2858.30	% SZS status Started for HL401243+4.p
13534.16/2858.30	% SZS status GaveUp for HL401243+4.p
13534.16/2858.30	% SZS status Ended for HL401243+4.p
13537.95/2858.80	% SZS status Started for HL401243+5.p
13537.95/2858.80	% SZS status GaveUp for HL401243+5.p
13537.95/2858.80	% SZS status Ended for HL401243+5.p
13545.49/2859.69	% SZS status Started for HL401253+5.p
13545.49/2859.69	% SZS status Theorem for HL401253+5.p
13545.49/2859.69	% SZS status Ended for HL401253+5.p
13550.23/2860.18	% SZS status Started for HL401254+4.p
13550.23/2860.18	% SZS status Theorem for HL401254+4.p
13550.23/2860.18	% SZS status Ended for HL401254+4.p
13554.04/2860.70	% SZS status Started for HL401246+4.p
13554.04/2860.70	% SZS status GaveUp for HL401246+4.p
13554.04/2860.70	% SZS status Ended for HL401246+4.p
13554.96/2861.00	% SZS status Started for HL401255+4.p
13554.96/2861.00	% SZS status Theorem for HL401255+4.p
13554.96/2861.00	% SZS status Ended for HL401255+4.p
13557.82/2861.19	% SZS status Started for HL401254+5.p
13557.82/2861.19	% SZS status Theorem for HL401254+5.p
13557.82/2861.19	% SZS status Ended for HL401254+5.p
13559.71/2861.47	% SZS status Started for HL401252+4.p
13559.71/2861.47	% SZS status Theorem for HL401252+4.p
13559.71/2861.47	% SZS status Ended for HL401252+4.p
13559.71/2861.48	% SZS status Started for HL401256+4.p
13559.71/2861.48	% SZS status Theorem for HL401256+4.p
13559.71/2861.48	% SZS status Ended for HL401256+4.p
13563.44/2861.95	% SZS status Started for HL401256+5.p
13563.44/2861.95	% SZS status Theorem for HL401256+5.p
13563.44/2861.95	% SZS status Ended for HL401256+5.p
13569.56/2862.69	% SZS status Started for HL401246+5.p
13569.56/2862.69	% SZS status GaveUp for HL401246+5.p
13569.56/2862.69	% SZS status Ended for HL401246+5.p
13572.81/2863.13	% SZS status Started for HL401251+5.p
13572.81/2863.13	% SZS status Theorem for HL401251+5.p
13572.81/2863.13	% SZS status Ended for HL401251+5.p
13576.75/2863.51	% SZS status Started for HL401253+4.p
13576.75/2863.51	% SZS status Theorem for HL401253+4.p
13576.75/2863.51	% SZS status Ended for HL401253+4.p
13576.84/2863.57	% SZS status Started for HL401249+5.p
13576.84/2863.57	% SZS status GaveUp for HL401249+5.p
13576.84/2863.57	% SZS status Ended for HL401249+5.p
13586.25/2864.74	% SZS status Started for HL401252+5.p
13586.25/2864.74	% SZS status Theorem for HL401252+5.p
13586.25/2864.74	% SZS status Ended for HL401252+5.p
13620.87/2869.13	% SZS status Started for HL401255+5.p
13620.87/2869.13	% SZS status GaveUp for HL401255+5.p
13620.87/2869.13	% SZS status Ended for HL401255+5.p
13626.57/2869.78	% SZS status Started for HL401257+4.p
13626.57/2869.78	% SZS status GaveUp for HL401257+4.p
13626.57/2869.78	% SZS status Ended for HL401257+4.p
13628.87/2870.15	% SZS status Started for HL401257+5.p
13628.87/2870.15	% SZS status GaveUp for HL401257+5.p
13628.87/2870.15	% SZS status Ended for HL401257+5.p
13637.02/2871.10	% SZS status Started for HL401258+4.p
13637.02/2871.10	% SZS status GaveUp for HL401258+4.p
13637.02/2871.10	% SZS status Ended for HL401258+4.p
13638.35/2871.29	% SZS status Started for HL401258+5.p
13638.35/2871.29	% SZS status GaveUp for HL401258+5.p
13638.35/2871.29	% SZS status Ended for HL401258+5.p
13641.78/2871.72	% SZS status Started for HL401259+4.p
13641.78/2871.72	% SZS status GaveUp for HL401259+4.p
13641.78/2871.72	% SZS status Ended for HL401259+4.p
13642.27/2871.76	% SZS status Started for HL401259+5.p
13642.27/2871.76	% SZS status GaveUp for HL401259+5.p
13642.27/2871.76	% SZS status Ended for HL401259+5.p
13652.08/2873.06	% SZS status Started for HL401260+4.p
13652.08/2873.06	% SZS status GaveUp for HL401260+4.p
13652.08/2873.06	% SZS status Ended for HL401260+4.p
13657.31/2873.70	% SZS status Started for HL401266+4.p
13657.31/2873.70	% SZS status Theorem for HL401266+4.p
13657.31/2873.70	% SZS status Ended for HL401266+4.p
13685.57/2877.30	% SZS status Started for HL401260+5.p
13685.57/2877.30	% SZS status GaveUp for HL401260+5.p
13685.57/2877.30	% SZS status Ended for HL401260+5.p
13692.74/2878.11	% SZS status Started for HL401261+4.p
13692.74/2878.11	% SZS status GaveUp for HL401261+4.p
13692.74/2878.11	% SZS status Ended for HL401261+4.p
13694.58/2878.37	% SZS status Started for HL401261+5.p
13694.58/2878.37	% SZS status GaveUp for HL401261+5.p
13694.58/2878.37	% SZS status Ended for HL401261+5.p
13702.96/2879.42	% SZS status Started for HL401266+5.p
13702.96/2879.42	% SZS status GaveUp for HL401266+5.p
13702.96/2879.42	% SZS status Ended for HL401266+5.p
13706.24/2879.78	% SZS status Started for HL401269+4.p
13706.24/2879.78	% SZS status Theorem for HL401269+4.p
13706.24/2879.78	% SZS status Ended for HL401269+4.p
13707.23/2879.92	% SZS status Started for HL401267+5.p
13707.23/2879.92	% SZS status GaveUp for HL401267+5.p
13707.23/2879.92	% SZS status Ended for HL401267+5.p
13708.07/2880.11	% SZS status Started for HL401267+4.p
13708.07/2880.11	% SZS status GaveUp for HL401267+4.p
13708.07/2880.11	% SZS status Ended for HL401267+4.p
13716.97/2881.27	% SZS status Started for HL401268+4.p
13716.97/2881.27	% SZS status GaveUp for HL401268+4.p
13716.97/2881.27	% SZS status Ended for HL401268+4.p
13720.13/2881.54	% SZS status Started for HL401272+4.p
13720.13/2881.54	% SZS status Theorem for HL401272+4.p
13720.13/2881.54	% SZS status Ended for HL401272+4.p
13721.73/2881.87	% SZS status Started for HL401268+5.p
13721.73/2881.87	% SZS status GaveUp for HL401268+5.p
13721.73/2881.87	% SZS status Ended for HL401268+5.p
13724.16/2882.07	% SZS status Started for HL401272+5.p
13724.16/2882.07	% SZS status Theorem for HL401272+5.p
13724.16/2882.07	% SZS status Ended for HL401272+5.p
13725.34/2882.34	% SZS status Started for HL401275+4.p
13725.34/2882.34	% SZS status Theorem for HL401275+4.p
13725.34/2882.34	% SZS status Ended for HL401275+4.p
13729.58/2882.77	% SZS status Started for HL401275+5.p
13729.58/2882.77	% SZS status Theorem for HL401275+5.p
13729.58/2882.77	% SZS status Ended for HL401275+5.p
13757.51/2886.32	% SZS status Started for HL401269+5.p
13757.51/2886.32	% SZS status GaveUp for HL401269+5.p
13757.51/2886.32	% SZS status Ended for HL401269+5.p
13760.01/2886.65	% SZS status Started for HL401270+4.p
13760.01/2886.65	% SZS status GaveUp for HL401270+4.p
13760.01/2886.65	% SZS status Ended for HL401270+4.p
13767.99/2887.59	% SZS status Started for HL401270+5.p
13767.99/2887.59	% SZS status GaveUp for HL401270+5.p
13767.99/2887.59	% SZS status Ended for HL401270+5.p
13770.94/2888.07	% SZS status Started for HL401271+4.p
13770.94/2888.07	% SZS status GaveUp for HL401271+4.p
13770.94/2888.07	% SZS status Ended for HL401271+4.p
13772.79/2888.15	% SZS status Started for HL401271+5.p
13772.79/2888.15	% SZS status GaveUp for HL401271+5.p
13772.79/2888.15	% SZS status Ended for HL401271+5.p
13775.53/2888.60	% SZS status Started for HL401278+5.p
13775.53/2888.60	% SZS status Theorem for HL401278+5.p
13775.53/2888.60	% SZS status Ended for HL401278+5.p
13785.87/2889.85	% SZS status Started for HL401274+4.p
13785.87/2889.85	% SZS status GaveUp for HL401274+4.p
13785.87/2889.85	% SZS status Ended for HL401274+4.p
13786.83/2890.02	% SZS status Started for HL401274+5.p
13786.83/2890.02	% SZS status GaveUp for HL401274+5.p
13786.83/2890.02	% SZS status Ended for HL401274+5.p
13791.69/2890.52	% SZS status Started for HL401278+4.p
13791.69/2890.52	% SZS status Theorem for HL401278+4.p
13791.69/2890.52	% SZS status Ended for HL401278+4.p
13794.78/2891.08	% SZS status Started for HL401276+4.p
13794.78/2891.08	% SZS status GaveUp for HL401276+4.p
13794.78/2891.08	% SZS status Ended for HL401276+4.p
13822.48/2894.49	% SZS status Started for HL401276+5.p
13822.48/2894.49	% SZS status GaveUp for HL401276+5.p
13822.48/2894.49	% SZS status Ended for HL401276+5.p
13826.90/2894.96	% SZS status Started for HL401277+4.p
13826.90/2894.96	% SZS status GaveUp for HL401277+4.p
13826.90/2894.96	% SZS status Ended for HL401277+4.p
13829.23/2895.33	% SZS status Started for HL401279+5.p
13829.23/2895.33	% SZS status Theorem for HL401279+5.p
13829.23/2895.33	% SZS status Ended for HL401279+5.p
13832.83/2895.75	% SZS status Started for HL401277+5.p
13832.83/2895.75	% SZS status GaveUp for HL401277+5.p
13832.83/2895.75	% SZS status Ended for HL401277+5.p
13841.77/2896.86	% SZS status Started for HL401279+4.p
13841.77/2896.86	% SZS status GaveUp for HL401279+4.p
13841.77/2896.86	% SZS status Ended for HL401279+4.p
13852.78/2898.33	% SZS status Started for HL401280+4.p
13852.78/2898.33	% SZS status GaveUp for HL401280+4.p
13852.78/2898.33	% SZS status Ended for HL401280+4.p
13856.34/2898.69	% SZS status Started for HL401280+5.p
13856.34/2898.69	% SZS status GaveUp for HL401280+5.p
13856.34/2898.69	% SZS status Ended for HL401280+5.p
13861.81/2899.35	% SZS status Started for HL401283+4.p
13861.81/2899.35	% SZS status GaveUp for HL401283+4.p
13861.81/2899.35	% SZS status Ended for HL401283+4.p
13887.98/2902.70	% SZS status Started for HL401283+5.p
13887.98/2902.70	% SZS status GaveUp for HL401283+5.p
13887.98/2902.70	% SZS status Ended for HL401283+5.p
13892.22/2903.20	% SZS status Started for HL401284+4.p
13892.22/2903.20	% SZS status GaveUp for HL401284+4.p
13892.22/2903.20	% SZS status Ended for HL401284+4.p
13893.86/2903.47	% SZS status Started for HL401284+5.p
13893.86/2903.47	% SZS status GaveUp for HL401284+5.p
13893.86/2903.47	% SZS status Ended for HL401284+5.p
13898.97/2904.00	% SZS status Started for HL401286+4.p
13898.97/2904.00	% SZS status GaveUp for HL401286+4.p
13898.97/2904.00	% SZS status Ended for HL401286+4.p
13906.29/2905.01	% SZS status Started for HL401286+5.p
13906.29/2905.01	% SZS status GaveUp for HL401286+5.p
13906.29/2905.01	% SZS status Ended for HL401286+5.p
13919.70/2906.62	% SZS status Started for HL401287+4.p
13919.70/2906.62	% SZS status GaveUp for HL401287+4.p
13919.70/2906.62	% SZS status Ended for HL401287+4.p
13921.58/2906.88	% SZS status Started for HL401287+5.p
13921.58/2906.88	% SZS status GaveUp for HL401287+5.p
13921.58/2906.88	% SZS status Ended for HL401287+5.p
13928.41/2907.74	% SZS status Started for HL401288+4.p
13928.41/2907.74	% SZS status GaveUp for HL401288+4.p
13928.41/2907.74	% SZS status Ended for HL401288+4.p
13947.09/2910.17	% SZS status Started for HL401292+4.p
13947.09/2910.17	% SZS status Theorem for HL401292+4.p
13947.09/2910.17	% SZS status Ended for HL401292+4.p
13952.69/2910.85	% SZS status Started for HL401288+5.p
13952.69/2910.85	% SZS status GaveUp for HL401288+5.p
13952.69/2910.85	% SZS status Ended for HL401288+5.p
13958.85/2911.52	% SZS status Started for HL401289+4.p
13958.85/2911.52	% SZS status GaveUp for HL401289+4.p
13958.85/2911.52	% SZS status Ended for HL401289+4.p
13959.12/2911.61	% SZS status Started for HL401289+5.p
13959.12/2911.61	% SZS status GaveUp for HL401289+5.p
13959.12/2911.61	% SZS status Ended for HL401289+5.p
13965.19/2912.33	% SZS status Started for HL401290+4.p
13965.19/2912.33	% SZS status GaveUp for HL401290+4.p
13965.19/2912.33	% SZS status Ended for HL401290+4.p
13971.42/2913.15	% SZS status Started for HL401290+5.p
13971.42/2913.15	% SZS status GaveUp for HL401290+5.p
13971.42/2913.15	% SZS status Ended for HL401290+5.p
13985.77/2914.94	% SZS status Started for HL401291+4.p
13985.77/2914.94	% SZS status GaveUp for HL401291+4.p
13985.77/2914.94	% SZS status Ended for HL401291+4.p
13987.41/2915.09	% SZS status Started for HL401291+5.p
13987.41/2915.09	% SZS status GaveUp for HL401291+5.p
13987.41/2915.09	% SZS status Ended for HL401291+5.p
14012.82/2918.34	% SZS status Started for HL401292+5.p
14012.82/2918.34	% SZS status GaveUp for HL401292+5.p
14012.82/2918.34	% SZS status Ended for HL401292+5.p
14018.79/2919.17	% SZS status Started for HL401293+4.p
14018.79/2919.17	% SZS status GaveUp for HL401293+4.p
14018.79/2919.17	% SZS status Ended for HL401293+4.p
14022.52/2919.69	% SZS status Started for HL401293+5.p
14022.52/2919.69	% SZS status GaveUp for HL401293+5.p
14022.52/2919.69	% SZS status Ended for HL401293+5.p
14022.86/2919.87	% SZS status Started for HL401294+4.p
14022.86/2919.87	% SZS status GaveUp for HL401294+4.p
14022.86/2919.87	% SZS status Ended for HL401294+4.p
14029.27/2920.50	% SZS status Started for HL401294+5.p
14029.27/2920.50	% SZS status GaveUp for HL401294+5.p
14029.27/2920.50	% SZS status Ended for HL401294+5.p
14036.40/2921.41	% SZS status Started for HL401295+4.p
14036.40/2921.41	% SZS status GaveUp for HL401295+4.p
14036.40/2921.41	% SZS status Ended for HL401295+4.p
14057.51/2923.08	% SZS status Started for HL401295+5.p
14057.51/2923.08	% SZS status GaveUp for HL401295+5.p
14057.51/2923.08	% SZS status Ended for HL401295+5.p
14059.52/2923.36	% SZS status Started for HL401296+4.p
14059.52/2923.36	% SZS status GaveUp for HL401296+4.p
14059.52/2923.36	% SZS status Ended for HL401296+4.p
14084.88/2926.50	% SZS status Started for HL401296+5.p
14084.88/2926.50	% SZS status GaveUp for HL401296+5.p
14084.88/2926.50	% SZS status Ended for HL401296+5.p
14091.36/2927.47	% SZS status Started for HL401297+4.p
14091.36/2927.47	% SZS status GaveUp for HL401297+4.p
14091.36/2927.47	% SZS status Ended for HL401297+4.p
14094.76/2927.86	% SZS status Started for HL401297+5.p
14094.76/2927.86	% SZS status GaveUp for HL401297+5.p
14094.76/2927.86	% SZS status Ended for HL401297+5.p
14095.47/2928.11	% SZS status Started for HL401298+4.p
14095.47/2928.11	% SZS status GaveUp for HL401298+4.p
14095.47/2928.11	% SZS status Ended for HL401298+4.p
14101.72/2928.70	% SZS status Started for HL401298+5.p
14101.72/2928.70	% SZS status GaveUp for HL401298+5.p
14101.72/2928.70	% SZS status Ended for HL401298+5.p
14110.21/2929.67	% SZS status Started for HL401299+4.p
14110.21/2929.67	% SZS status GaveUp for HL401299+4.p
14110.21/2929.67	% SZS status Ended for HL401299+4.p
14112.72/2930.02	% SZS status Started for HL401301+4.p
14112.72/2930.02	% SZS status Theorem for HL401301+4.p
14112.72/2930.02	% SZS status Ended for HL401301+4.p
14123.15/2931.34	% SZS status Started for HL401299+5.p
14123.15/2931.34	% SZS status GaveUp for HL401299+5.p
14123.15/2931.34	% SZS status Ended for HL401299+5.p
14126.76/2931.75	% SZS status Started for HL401300+4.p
14126.76/2931.75	% SZS status GaveUp for HL401300+4.p
14126.76/2931.75	% SZS status Ended for HL401300+4.p
14137.01/2933.10	% SZS status Started for HL401301+5.p
14137.01/2933.10	% SZS status Theorem for HL401301+5.p
14137.01/2933.10	% SZS status Ended for HL401301+5.p
14149.53/2934.66	% SZS status Started for HL401300+5.p
14149.53/2934.66	% SZS status GaveUp for HL401300+5.p
14149.53/2934.66	% SZS status Ended for HL401300+5.p
14158.13/2935.72	% SZS status Started for HL401306+4.p
14158.13/2935.72	% SZS status Theorem for HL401306+4.p
14158.13/2935.72	% SZS status Ended for HL401306+4.p
14163.41/2936.37	% SZS status Started for HL401302+4.p
14163.41/2936.37	% SZS status GaveUp for HL401302+4.p
14163.41/2936.37	% SZS status Ended for HL401302+4.p
14167.39/2936.87	% SZS status Started for HL401302+5.p
14167.39/2936.87	% SZS status GaveUp for HL401302+5.p
14167.39/2936.87	% SZS status Ended for HL401302+5.p
14176.68/2938.04	% SZS status Started for HL401303+4.p
14176.68/2938.04	% SZS status GaveUp for HL401303+4.p
14176.68/2938.04	% SZS status Ended for HL401303+4.p
14177.74/2938.19	% SZS status Started for HL401303+5.p
14177.74/2938.19	% SZS status GaveUp for HL401303+5.p
14177.74/2938.19	% SZS status Ended for HL401303+5.p
14189.93/2939.73	% SZS status Started for HL401304+4.p
14189.93/2939.73	% SZS status GaveUp for HL401304+4.p
14189.93/2939.73	% SZS status Ended for HL401304+4.p
14190.49/2939.79	% SZS status Started for HL401306+5.p
14190.49/2939.79	% SZS status Theorem for HL401306+5.p
14190.49/2939.79	% SZS status Ended for HL401306+5.p
14191.25/2939.88	% SZS status Started for HL401304+5.p
14191.25/2939.88	% SZS status GaveUp for HL401304+5.p
14191.25/2939.88	% SZS status Ended for HL401304+5.p
14224.66/2944.06	% SZS status Started for HL401307+4.p
14224.66/2944.06	% SZS status GaveUp for HL401307+4.p
14224.66/2944.06	% SZS status Ended for HL401307+4.p
14227.15/2944.51	% SZS status Started for HL401307+5.p
14227.15/2944.51	% SZS status GaveUp for HL401307+5.p
14227.15/2944.51	% SZS status Ended for HL401307+5.p
14233.45/2945.17	% SZS status Started for HL401308+4.p
14233.45/2945.17	% SZS status GaveUp for HL401308+4.p
14233.45/2945.17	% SZS status Ended for HL401308+4.p
14240.96/2946.22	% SZS status Started for HL401308+5.p
14240.96/2946.22	% SZS status GaveUp for HL401308+5.p
14240.96/2946.22	% SZS status Ended for HL401308+5.p
14243.21/2946.45	% SZS status Started for HL401309+4.p
14243.21/2946.45	% SZS status GaveUp for HL401309+4.p
14243.21/2946.45	% SZS status Ended for HL401309+4.p
14255.44/2947.98	% SZS status Started for HL401309+5.p
14255.44/2947.98	% SZS status GaveUp for HL401309+5.p
14255.44/2947.98	% SZS status Ended for HL401309+5.p
14256.07/2948.07	% SZS status Started for HL401312+5.p
14256.07/2948.07	% SZS status GaveUp for HL401312+5.p
14256.07/2948.07	% SZS status Ended for HL401312+5.p
14256.61/2948.10	% SZS status Started for HL401312+4.p
14256.61/2948.10	% SZS status GaveUp for HL401312+4.p
14256.61/2948.10	% SZS status Ended for HL401312+4.p
14275.43/2950.70	% SZS status Started for HL401315+5.p
14275.43/2950.70	% SZS status Theorem for HL401315+5.p
14275.43/2950.70	% SZS status Ended for HL401315+5.p
14290.85/2952.49	% SZS status Started for HL401313+4.p
14290.85/2952.49	% SZS status GaveUp for HL401313+4.p
14290.85/2952.49	% SZS status Ended for HL401313+4.p
14293.38/2952.75	% SZS status Started for HL401313+5.p
14293.38/2952.75	% SZS status GaveUp for HL401313+5.p
14293.38/2952.75	% SZS status Ended for HL401313+5.p
14298.65/2953.41	% SZS status Started for HL401314+4.p
14298.65/2953.41	% SZS status GaveUp for HL401314+4.p
14298.65/2953.41	% SZS status Ended for HL401314+4.p
14306.24/2954.40	% SZS status Started for HL401314+5.p
14306.24/2954.40	% SZS status GaveUp for HL401314+5.p
14306.24/2954.40	% SZS status Ended for HL401314+5.p
14309.49/2954.77	% SZS status Started for HL401315+4.p
14309.49/2954.77	% SZS status GaveUp for HL401315+4.p
14309.49/2954.77	% SZS status Ended for HL401315+4.p
14320.77/2956.34	% SZS status Started for HL401316+4.p
14320.77/2956.34	% SZS status GaveUp for HL401316+4.p
14320.77/2956.34	% SZS status Ended for HL401316+4.p
14322.62/2956.49	% SZS status Started for HL401316+5.p
14322.62/2956.49	% SZS status GaveUp for HL401316+5.p
14322.62/2956.49	% SZS status Ended for HL401316+5.p
14346.70/2959.63	% SZS status Started for HL401317+4.p
14346.70/2959.63	% SZS status GaveUp for HL401317+4.p
14346.70/2959.63	% SZS status Ended for HL401317+4.p
14355.67/2960.78	% SZS status Started for HL401317+5.p
14355.67/2960.78	% SZS status GaveUp for HL401317+5.p
14355.67/2960.78	% SZS status Ended for HL401317+5.p
14358.38/2961.08	% SZS status Started for HL401318+4.p
14358.38/2961.08	% SZS status GaveUp for HL401318+4.p
14358.38/2961.08	% SZS status Ended for HL401318+4.p
14362.69/2961.65	% SZS status Started for HL401318+5.p
14362.69/2961.65	% SZS status GaveUp for HL401318+5.p
14362.69/2961.65	% SZS status Ended for HL401318+5.p
14371.45/2962.82	% SZS status Started for HL401319+4.p
14371.45/2962.82	% SZS status GaveUp for HL401319+4.p
14371.45/2962.82	% SZS status Ended for HL401319+4.p
14373.91/2963.06	% SZS status Started for HL401319+5.p
14373.91/2963.06	% SZS status GaveUp for HL401319+5.p
14373.91/2963.06	% SZS status Ended for HL401319+5.p
14386.63/2964.71	% SZS status Started for HL401320+5.p
14386.63/2964.71	% SZS status GaveUp for HL401320+5.p
14386.63/2964.71	% SZS status Ended for HL401320+5.p
14390.44/2965.16	% SZS status Started for HL401320+4.p
14390.44/2965.16	% SZS status GaveUp for HL401320+4.p
14390.44/2965.16	% SZS status Ended for HL401320+4.p
14393.13/2965.74	% SZS status Started for HL401324+4.p
14393.13/2965.74	% SZS status Theorem for HL401324+4.p
14393.13/2965.74	% SZS status Ended for HL401324+4.p
14413.20/2968.11	% SZS status Started for HL401321+4.p
14413.20/2968.11	% SZS status GaveUp for HL401321+4.p
14413.20/2968.11	% SZS status Ended for HL401321+4.p
14421.37/2969.12	% SZS status Started for HL401321+5.p
14421.37/2969.12	% SZS status GaveUp for HL401321+5.p
14421.37/2969.12	% SZS status Ended for HL401321+5.p
14422.79/2969.54	% SZS status Started for HL401322+4.p
14422.79/2969.54	% SZS status GaveUp for HL401322+4.p
14422.79/2969.54	% SZS status Ended for HL401322+4.p
14428.93/2970.15	% SZS status Started for HL401322+5.p
14428.93/2970.15	% SZS status GaveUp for HL401322+5.p
14428.93/2970.15	% SZS status Ended for HL401322+5.p
14440.06/2971.60	% SZS status Started for HL401324+5.p
14440.06/2971.60	% SZS status GaveUp for HL401324+5.p
14440.06/2971.60	% SZS status Ended for HL401324+5.p
14453.19/2973.18	% SZS status Started for HL401325+4.p
14453.19/2973.18	% SZS status GaveUp for HL401325+4.p
14453.19/2973.18	% SZS status Ended for HL401325+4.p
14455.04/2973.39	% SZS status Started for HL401325+5.p
14455.04/2973.39	% SZS status GaveUp for HL401325+5.p
14455.04/2973.39	% SZS status Ended for HL401325+5.p
14465.41/2974.90	% SZS status Started for HL401326+4.p
14465.41/2974.90	% SZS status GaveUp for HL401326+4.p
14465.41/2974.90	% SZS status Ended for HL401326+4.p
14478.15/2976.33	% SZS status Started for HL401326+5.p
14478.15/2976.33	% SZS status GaveUp for HL401326+5.p
14478.15/2976.33	% SZS status Ended for HL401326+5.p
14486.98/2977.50	% SZS status Started for HL401329+4.p
14486.98/2977.50	% SZS status GaveUp for HL401329+4.p
14486.98/2977.50	% SZS status Ended for HL401329+4.p
14490.57/2977.91	% SZS status Started for HL401329+5.p
14490.57/2977.91	% SZS status GaveUp for HL401329+5.p
14490.57/2977.91	% SZS status Ended for HL401329+5.p
14496.32/2978.68	% SZS status Started for HL401330+4.p
14496.32/2978.68	% SZS status GaveUp for HL401330+4.p
14496.32/2978.68	% SZS status Ended for HL401330+4.p
14507.78/2980.10	% SZS status Started for HL401330+5.p
14507.78/2980.10	% SZS status GaveUp for HL401330+5.p
14507.78/2980.10	% SZS status Ended for HL401330+5.p
14518.72/2981.54	% SZS status Started for HL401332+4.p
14518.72/2981.54	% SZS status GaveUp for HL401332+4.p
14518.72/2981.54	% SZS status Ended for HL401332+4.p
14520.26/2981.69	% SZS status Started for HL401332+5.p
14520.26/2981.69	% SZS status GaveUp for HL401332+5.p
14520.26/2981.69	% SZS status Ended for HL401332+5.p
14532.88/2983.36	% SZS status Started for HL401333+4.p
14532.88/2983.36	% SZS status GaveUp for HL401333+4.p
14532.88/2983.36	% SZS status Ended for HL401333+4.p
14543.17/2984.58	% SZS status Started for HL401333+5.p
14543.17/2984.58	% SZS status GaveUp for HL401333+5.p
14543.17/2984.58	% SZS status Ended for HL401333+5.p
14553.46/2985.93	% SZS status Started for HL401335+4.p
14553.46/2985.93	% SZS status Theorem for HL401335+4.p
14553.46/2985.93	% SZS status Ended for HL401335+4.p
14554.05/2985.97	% SZS status Started for HL401334+4.p
14554.05/2985.97	% SZS status GaveUp for HL401334+4.p
14554.05/2985.97	% SZS status Ended for HL401334+4.p
14554.64/2986.12	% SZS status Started for HL401334+5.p
14554.64/2986.12	% SZS status GaveUp for HL401334+5.p
14554.64/2986.12	% SZS status Ended for HL401334+5.p
14573.13/2988.36	% SZS status Started for HL401335+5.p
14573.13/2988.36	% SZS status GaveUp for HL401335+5.p
14573.13/2988.36	% SZS status Ended for HL401335+5.p
14585.76/2989.93	% SZS status Started for HL401338+5.p
14585.76/2989.93	% SZS status GaveUp for HL401338+5.p
14585.76/2989.93	% SZS status Ended for HL401338+5.p
14585.76/2989.94	% SZS status Started for HL401338+4.p
14585.76/2989.94	% SZS status GaveUp for HL401338+4.p
14585.76/2989.94	% SZS status Ended for HL401338+4.p
14600.48/2991.80	% SZS status Started for HL401339+4.p
14600.48/2991.80	% SZS status GaveUp for HL401339+4.p
14600.48/2991.80	% SZS status Ended for HL401339+4.p
14608.53/2992.84	% SZS status Started for HL401339+5.p
14608.53/2992.84	% SZS status GaveUp for HL401339+5.p
14608.53/2992.84	% SZS status Ended for HL401339+5.p
14619.75/2994.24	% SZS status Started for HL401340+5.p
14619.75/2994.24	% SZS status GaveUp for HL401340+5.p
14619.75/2994.24	% SZS status Ended for HL401340+5.p
14619.97/2994.30	% SZS status Started for HL401340+4.p
14619.97/2994.30	% SZS status GaveUp for HL401340+4.p
14619.97/2994.30	% SZS status Ended for HL401340+4.p
14620.66/2994.51	% SZS status Started for HL401341+4.p
14620.66/2994.51	% SZS status GaveUp for HL401341+4.p
14620.66/2994.51	% SZS status Ended for HL401341+4.p
14638.25/2996.64	% SZS status Started for HL401341+5.p
14638.25/2996.64	% SZS status GaveUp for HL401341+5.p
14638.25/2996.64	% SZS status Ended for HL401341+5.p
14641.96/2997.01	% SZS status Started for HL401343+4.p
14641.96/2997.01	% SZS status Theorem for HL401343+4.p
14641.96/2997.01	% SZS status Ended for HL401343+4.p
14650.60/2998.09	% SZS status Started for HL401343+5.p
14650.60/2998.09	% SZS status GaveUp for HL401343+5.p
14650.60/2998.09	% SZS status Ended for HL401343+5.p
14666.72/3000.09	% SZS status Started for HL401344+4.p
14666.72/3000.09	% SZS status GaveUp for HL401344+4.p
14666.72/3000.09	% SZS status Ended for HL401344+4.p
14673.13/3001.04	% SZS status Started for HL401344+5.p
14673.13/3001.04	% SZS status GaveUp for HL401344+5.p
14673.13/3001.04	% SZS status Ended for HL401344+5.p
14685.41/3002.48	% SZS status Started for HL401345+5.p
14685.41/3002.48	% SZS status GaveUp for HL401345+5.p
14685.41/3002.48	% SZS status Ended for HL401345+5.p
14685.97/3002.60	% SZS status Started for HL401345+4.p
14685.97/3002.60	% SZS status GaveUp for HL401345+4.p
14685.97/3002.60	% SZS status Ended for HL401345+4.p
14688.23/3002.78	% SZS status Started for HL401346+4.p
14688.23/3002.78	% SZS status GaveUp for HL401346+4.p
14688.23/3002.78	% SZS status Ended for HL401346+4.p
14704.02/3004.81	% SZS status Started for HL401346+5.p
14704.02/3004.81	% SZS status GaveUp for HL401346+5.p
14704.02/3004.81	% SZS status Ended for HL401346+5.p
14707.99/3005.33	% SZS status Started for HL401348+4.p
14707.99/3005.33	% SZS status GaveUp for HL401348+4.p
14707.99/3005.33	% SZS status Ended for HL401348+4.p
14715.84/3006.24	% SZS status Started for HL401348+5.p
14715.84/3006.24	% SZS status GaveUp for HL401348+5.p
14715.84/3006.24	% SZS status Ended for HL401348+5.p
14732.41/3008.37	% SZS status Started for HL401349+4.p
14732.41/3008.37	% SZS status GaveUp for HL401349+4.p
14732.41/3008.37	% SZS status Ended for HL401349+4.p
14739.24/3009.27	% SZS status Started for HL401349+5.p
14739.24/3009.27	% SZS status GaveUp for HL401349+5.p
14739.24/3009.27	% SZS status Ended for HL401349+5.p
14751.25/3010.74	% SZS status Started for HL401350+5.p
14751.25/3010.74	% SZS status GaveUp for HL401350+5.p
14751.25/3010.74	% SZS status Ended for HL401350+5.p
14751.52/3010.81	% SZS status Started for HL401350+4.p
14751.52/3010.81	% SZS status GaveUp for HL401350+4.p
14751.52/3010.81	% SZS status Ended for HL401350+4.p
14753.96/3011.05	% SZS status Started for HL401351+4.p
14753.96/3011.05	% SZS status GaveUp for HL401351+4.p
14753.96/3011.05	% SZS status Ended for HL401351+4.p
14769.28/3012.98	% SZS status Started for HL401351+5.p
14769.28/3012.98	% SZS status GaveUp for HL401351+5.p
14769.28/3012.98	% SZS status Ended for HL401351+5.p
14774.40/3013.67	% SZS status Started for HL401352+4.p
14774.40/3013.67	% SZS status GaveUp for HL401352+4.p
14774.40/3013.67	% SZS status Ended for HL401352+4.p
14780.58/3014.45	% SZS status Started for HL401352+5.p
14780.58/3014.45	% SZS status GaveUp for HL401352+5.p
14780.58/3014.45	% SZS status Ended for HL401352+5.p
14798.00/3016.60	% SZS status Started for HL401353+4.p
14798.00/3016.60	% SZS status GaveUp for HL401353+4.p
14798.00/3016.60	% SZS status Ended for HL401353+4.p
14799.19/3016.79	% SZS status Started for HL401358+4.p
14799.19/3016.79	% SZS status Theorem for HL401358+4.p
14799.19/3016.79	% SZS status Ended for HL401358+4.p
14804.51/3017.45	% SZS status Started for HL401353+5.p
14804.51/3017.45	% SZS status GaveUp for HL401353+5.p
14804.51/3017.45	% SZS status Ended for HL401353+5.p
14806.45/3017.63	% SZS status Started for HL401360+4.p
14806.45/3017.63	% SZS status Theorem for HL401360+4.p
14806.45/3017.63	% SZS status Ended for HL401360+4.p
14816.74/3019.01	% SZS status Started for HL401354+5.p
14816.74/3019.01	% SZS status GaveUp for HL401354+5.p
14816.74/3019.01	% SZS status Ended for HL401354+5.p
14817.23/3019.09	% SZS status Started for HL401354+4.p
14817.23/3019.09	% SZS status GaveUp for HL401354+4.p
14817.23/3019.09	% SZS status Ended for HL401354+4.p
14817.67/3019.19	% SZS status Started for HL401361+4.p
14817.67/3019.19	% SZS status Theorem for HL401361+4.p
14817.67/3019.19	% SZS status Ended for HL401361+4.p
14819.51/3019.30	% SZS status Started for HL401355+4.p
14819.51/3019.30	% SZS status GaveUp for HL401355+4.p
14819.51/3019.30	% SZS status Ended for HL401355+4.p
14834.27/3021.18	% SZS status Started for HL401355+5.p
14834.27/3021.18	% SZS status GaveUp for HL401355+5.p
14834.27/3021.18	% SZS status Ended for HL401355+5.p
14840.41/3021.96	% SZS status Started for HL401356+4.p
14840.41/3021.96	% SZS status GaveUp for HL401356+4.p
14840.41/3021.96	% SZS status Ended for HL401356+4.p
14846.28/3022.67	% SZS status Started for HL401356+5.p
14846.28/3022.67	% SZS status GaveUp for HL401356+5.p
14846.28/3022.67	% SZS status Ended for HL401356+5.p
14864.09/3024.94	% SZS status Started for HL401358+5.p
14864.09/3024.94	% SZS status GaveUp for HL401358+5.p
14864.09/3024.94	% SZS status Ended for HL401358+5.p
14870.67/3025.87	% SZS status Started for HL401360+5.p
14870.67/3025.87	% SZS status GaveUp for HL401360+5.p
14870.67/3025.87	% SZS status Ended for HL401360+5.p
14882.54/3027.28	% SZS status Started for HL401361+5.p
14882.54/3027.28	% SZS status GaveUp for HL401361+5.p
14882.54/3027.28	% SZS status Ended for HL401361+5.p
14883.40/3027.49	% SZS status Started for HL401362+5.p
14883.40/3027.49	% SZS status GaveUp for HL401362+5.p
14883.40/3027.49	% SZS status Ended for HL401362+5.p
14885.22/3027.54	% SZS status Started for HL401362+4.p
14885.22/3027.54	% SZS status GaveUp for HL401362+4.p
14885.22/3027.54	% SZS status Ended for HL401362+4.p
14900.53/3029.48	% SZS status Started for HL401364+4.p
14900.53/3029.48	% SZS status GaveUp for HL401364+4.p
14900.53/3029.48	% SZS status Ended for HL401364+4.p
14904.99/3030.12	% SZS status Started for HL401364+5.p
14904.99/3030.12	% SZS status GaveUp for HL401364+5.p
14904.99/3030.12	% SZS status Ended for HL401364+5.p
14911.39/3030.95	% SZS status Started for HL401365+4.p
14911.39/3030.95	% SZS status GaveUp for HL401365+4.p
14911.39/3030.95	% SZS status Ended for HL401365+4.p
14930.85/3033.37	% SZS status Started for HL401365+5.p
14930.85/3033.37	% SZS status GaveUp for HL401365+5.p
14930.85/3033.37	% SZS status Ended for HL401365+5.p
14939.52/3034.48	% SZS status Started for HL401367+4.p
14939.52/3034.48	% SZS status GaveUp for HL401367+4.p
14939.52/3034.48	% SZS status Ended for HL401367+4.p
14948.26/3035.56	% SZS status Started for HL401367+5.p
14948.26/3035.56	% SZS status GaveUp for HL401367+5.p
14948.26/3035.56	% SZS status Ended for HL401367+5.p
14950.24/3035.77	% SZS status Started for HL401368+5.p
14950.24/3035.77	% SZS status GaveUp for HL401368+5.p
14950.24/3035.77	% SZS status Ended for HL401368+5.p
14950.69/3035.86	% SZS status Started for HL401368+4.p
14950.69/3035.86	% SZS status GaveUp for HL401368+4.p
14950.69/3035.86	% SZS status Ended for HL401368+4.p
14965.54/3037.73	% SZS status Started for HL401369+4.p
14965.54/3037.73	% SZS status GaveUp for HL401369+4.p
14965.54/3037.73	% SZS status Ended for HL401369+4.p
14969.87/3038.38	% SZS status Started for HL401369+5.p
14969.87/3038.38	% SZS status GaveUp for HL401369+5.p
14969.87/3038.38	% SZS status Ended for HL401369+5.p
14977.34/3039.20	% SZS status Started for HL401370+4.p
14977.34/3039.20	% SZS status GaveUp for HL401370+4.p
14977.34/3039.20	% SZS status Ended for HL401370+4.p
14996.05/3041.57	% SZS status Started for HL401370+5.p
14996.05/3041.57	% SZS status GaveUp for HL401370+5.p
14996.05/3041.57	% SZS status Ended for HL401370+5.p
15005.37/3042.77	% SZS status Started for HL401371+4.p
15005.37/3042.77	% SZS status GaveUp for HL401371+4.p
15005.37/3042.77	% SZS status Ended for HL401371+4.p
15013.74/3043.77	% SZS status Started for HL401371+5.p
15013.74/3043.77	% SZS status GaveUp for HL401371+5.p
15013.74/3043.77	% SZS status Ended for HL401371+5.p
15013.74/3043.81	% SZS status Started for HL401377+4.p
15013.74/3043.81	% SZS status Theorem for HL401377+4.p
15013.74/3043.81	% SZS status Ended for HL401377+4.p
15014.61/3044.01	% SZS status Started for HL401372+5.p
15014.61/3044.01	% SZS status GaveUp for HL401372+5.p
15014.61/3044.01	% SZS status Ended for HL401372+5.p
15016.07/3044.04	% SZS status Started for HL401372+4.p
15016.07/3044.04	% SZS status GaveUp for HL401372+4.p
15016.07/3044.04	% SZS status Ended for HL401372+4.p
15016.07/3044.05	% SZS status Started for HL401378+4.p
15016.07/3044.05	% SZS status Theorem for HL401378+4.p
15016.07/3044.05	% SZS status Ended for HL401378+4.p
15017.28/3044.25	% SZS status Started for HL401377+5.p
15017.28/3044.25	% SZS status Theorem for HL401377+5.p
15017.28/3044.25	% SZS status Ended for HL401377+5.p
15017.28/3044.26	% SZS status Started for HL401380+4.p
15017.28/3044.26	% SZS status Theorem for HL401380+4.p
15017.28/3044.26	% SZS status Ended for HL401380+4.p
15018.06/3044.42	% SZS status Started for HL401378+5.p
15018.06/3044.42	% SZS status Theorem for HL401378+5.p
15018.06/3044.42	% SZS status Ended for HL401378+5.p
15018.78/3044.46	% SZS status Started for HL401380+5.p
15018.78/3044.46	% SZS status Theorem for HL401380+5.p
15018.78/3044.46	% SZS status Ended for HL401380+5.p
15022.41/3045.10	% SZS status Started for HL401381+4.p
15022.41/3045.10	% SZS status Theorem for HL401381+4.p
15022.41/3045.10	% SZS status Ended for HL401381+4.p
15025.04/3045.20	% SZS status Started for HL401381+5.p
15025.04/3045.20	% SZS status Theorem for HL401381+5.p
15025.04/3045.20	% SZS status Ended for HL401381+5.p
15026.90/3045.48	% SZS status Started for HL401383+5.p
15026.90/3045.48	% SZS status Theorem for HL401383+5.p
15026.90/3045.48	% SZS status Ended for HL401383+5.p
15031.22/3045.95	% SZS status Started for HL401373+4.p
15031.22/3045.95	% SZS status GaveUp for HL401373+4.p
15031.22/3045.95	% SZS status Ended for HL401373+4.p
15031.88/3046.10	% SZS status Started for HL401383+4.p
15031.88/3046.10	% SZS status Theorem for HL401383+4.p
15031.88/3046.10	% SZS status Ended for HL401383+4.p
15033.91/3046.30	% SZS status Started for HL401386+4.p
15033.91/3046.30	% SZS status Theorem for HL401386+4.p
15033.91/3046.30	% SZS status Ended for HL401386+4.p
15035.13/3046.61	% SZS status Started for HL401373+5.p
15035.13/3046.61	% SZS status GaveUp for HL401373+5.p
15035.13/3046.61	% SZS status Ended for HL401373+5.p
15038.41/3046.84	% SZS status Started for HL401386+5.p
15038.41/3046.84	% SZS status Theorem for HL401386+5.p
15038.41/3046.84	% SZS status Ended for HL401386+5.p
15042.67/3047.45	% SZS status Started for HL401388+4.p
15042.67/3047.45	% SZS status Theorem for HL401388+4.p
15042.67/3047.45	% SZS status Ended for HL401388+4.p
15043.31/3047.48	% SZS status Started for HL401375+4.p
15043.31/3047.48	% SZS status GaveUp for HL401375+4.p
15043.31/3047.48	% SZS status Ended for HL401375+4.p
15048.61/3048.17	% SZS status Started for HL401389+5.p
15048.61/3048.17	% SZS status Theorem for HL401389+5.p
15048.61/3048.17	% SZS status Ended for HL401389+5.p
15049.21/3048.27	% SZS status Started for HL401389+4.p
15049.21/3048.27	% SZS status Theorem for HL401389+4.p
15049.21/3048.27	% SZS status Ended for HL401389+4.p
15056.03/3049.09	% SZS status Started for HL401390+4.p
15056.03/3049.09	% SZS status Theorem for HL401390+4.p
15056.03/3049.09	% SZS status Ended for HL401390+4.p
15061.66/3049.77	% SZS status Started for HL401375+5.p
15061.66/3049.77	% SZS status GaveUp for HL401375+5.p
15061.66/3049.77	% SZS status Ended for HL401375+5.p
15062.47/3049.90	% SZS status Started for HL401391+4.p
15062.47/3049.90	% SZS status Theorem for HL401391+4.p
15062.47/3049.90	% SZS status Ended for HL401391+4.p
15067.06/3050.51	% SZS status Started for HL401391+5.p
15067.06/3050.51	% SZS status Theorem for HL401391+5.p
15067.06/3050.51	% SZS status Ended for HL401391+5.p
15068.89/3050.71	% SZS status Started for HL401392+4.p
15068.89/3050.71	% SZS status Theorem for HL401392+4.p
15068.89/3050.71	% SZS status Ended for HL401392+4.p
15070.14/3050.89	% SZS status Started for HL401392+5.p
15070.14/3050.89	% SZS status Theorem for HL401392+5.p
15070.14/3050.89	% SZS status Ended for HL401392+5.p
15075.26/3051.54	% SZS status Started for HL401393+4.p
15075.26/3051.54	% SZS status Theorem for HL401393+4.p
15075.26/3051.54	% SZS status Ended for HL401393+4.p
15075.26/3051.56	% SZS status Started for HL401393+5.p
15075.26/3051.56	% SZS status Theorem for HL401393+5.p
15075.26/3051.56	% SZS status Ended for HL401393+5.p
15077.47/3051.77	% SZS status Started for HL401385+4.p
15077.47/3051.77	% SZS status Theorem for HL401385+4.p
15077.47/3051.77	% SZS status Ended for HL401385+4.p
15090.34/3053.42	% SZS status Started for HL401385+5.p
15090.34/3053.42	% SZS status GaveUp for HL401385+5.p
15090.34/3053.42	% SZS status Ended for HL401385+5.p
15098.90/3054.48	% SZS status Started for HL401387+5.p
15098.90/3054.48	% SZS status GaveUp for HL401387+5.p
15098.90/3054.48	% SZS status Ended for HL401387+5.p
15099.89/3054.60	% SZS status Started for HL401387+4.p
15099.89/3054.60	% SZS status GaveUp for HL401387+4.p
15099.89/3054.60	% SZS status Ended for HL401387+4.p
15101.36/3055.02	% SZS status Started for HL401388+5.p
15101.36/3055.02	% SZS status GaveUp for HL401388+5.p
15101.36/3055.02	% SZS status Ended for HL401388+5.p
15109.89/3055.94	% SZS status Started for HL401399+4.p
15109.89/3055.94	% SZS status Theorem for HL401399+4.p
15109.89/3055.94	% SZS status Ended for HL401399+4.p
15113.39/3056.31	% SZS status Started for HL401397+4.p
15113.39/3056.31	% SZS status Theorem for HL401397+4.p
15113.39/3056.31	% SZS status Ended for HL401397+4.p
15114.66/3056.45	% SZS status Started for HL401390+5.p
15114.66/3056.45	% SZS status GaveUp for HL401390+5.p
15114.66/3056.45	% SZS status Ended for HL401390+5.p
15114.91/3056.51	% SZS status Started for HL401399+5.p
15114.91/3056.51	% SZS status Theorem for HL401399+5.p
15114.91/3056.51	% SZS status Ended for HL401399+5.p
15118.02/3057.00	% SZS status Started for HL401400+5.p
15118.02/3057.00	% SZS status Theorem for HL401400+5.p
15118.02/3057.00	% SZS status Ended for HL401400+5.p
15121.02/3057.23	% SZS status Started for HL401400+4.p
15121.02/3057.23	% SZS status Theorem for HL401400+4.p
15121.02/3057.23	% SZS status Ended for HL401400+4.p
15140.28/3059.72	% SZS status Started for HL401395+5.p
15140.28/3059.72	% SZS status GaveUp for HL401395+5.p
15140.28/3059.72	% SZS status Ended for HL401395+5.p
15140.99/3059.83	% SZS status Started for HL401395+4.p
15140.99/3059.83	% SZS status GaveUp for HL401395+4.p
15140.99/3059.83	% SZS status Ended for HL401395+4.p
15142.86/3060.02	% SZS status Started for HL401396+4.p
15142.86/3060.02	% SZS status GaveUp for HL401396+4.p
15142.86/3060.02	% SZS status Ended for HL401396+4.p
15148.95/3060.84	% SZS status Started for HL401403+4.p
15148.95/3060.84	% SZS status Theorem for HL401403+4.p
15148.95/3060.84	% SZS status Ended for HL401403+4.p
15154.75/3061.61	% SZS status Started for HL401396+5.p
15154.75/3061.61	% SZS status GaveUp for HL401396+5.p
15154.75/3061.61	% SZS status Ended for HL401396+5.p
15165.10/3062.80	% SZS status Started for HL401397+5.p
15165.10/3062.80	% SZS status GaveUp for HL401397+5.p
15165.10/3062.80	% SZS status Ended for HL401397+5.p
15166.18/3062.97	% SZS status Started for HL401401+4.p
15166.18/3062.97	% SZS status Theorem for HL401401+4.p
15166.18/3062.97	% SZS status Ended for HL401401+4.p
15183.99/3065.23	% SZS status Started for HL401401+5.p
15183.99/3065.23	% SZS status GaveUp for HL401401+5.p
15183.99/3065.23	% SZS status Ended for HL401401+5.p
15187.23/3065.61	% SZS status Started for HL401402+4.p
15187.23/3065.61	% SZS status GaveUp for HL401402+4.p
15187.23/3065.61	% SZS status Ended for HL401402+4.p
15205.81/3067.95	% SZS status Started for HL401402+5.p
15205.81/3067.95	% SZS status GaveUp for HL401402+5.p
15205.81/3067.95	% SZS status Ended for HL401402+5.p
15208.62/3068.25	% SZS status Started for HL401403+5.p
15208.62/3068.25	% SZS status GaveUp for HL401403+5.p
15208.62/3068.25	% SZS status Ended for HL401403+5.p
15215.21/3069.13	% SZS status Started for HL401404+4.p
15215.21/3069.13	% SZS status GaveUp for HL401404+4.p
15215.21/3069.13	% SZS status Ended for HL401404+4.p
15219.99/3069.81	% SZS status Started for HL401404+5.p
15219.99/3069.81	% SZS status GaveUp for HL401404+5.p
15219.99/3069.81	% SZS status Ended for HL401404+5.p
15230.71/3071.06	% SZS status Started for HL401405+4.p
15230.71/3071.06	% SZS status GaveUp for HL401405+4.p
15230.71/3071.06	% SZS status Ended for HL401405+4.p
15231.29/3071.11	% SZS status Started for HL401405+5.p
15231.29/3071.11	% SZS status GaveUp for HL401405+5.p
15231.29/3071.11	% SZS status Ended for HL401405+5.p
15244.48/3072.82	% SZS status Started for HL401409+4.p
15244.48/3072.82	% SZS status Theorem for HL401409+4.p
15244.48/3072.82	% SZS status Ended for HL401409+4.p
15249.53/3073.53	% SZS status Started for HL401406+4.p
15249.53/3073.53	% SZS status GaveUp for HL401406+4.p
15249.53/3073.53	% SZS status Ended for HL401406+4.p
15252.21/3073.76	% SZS status Started for HL401406+5.p
15252.21/3073.76	% SZS status GaveUp for HL401406+5.p
15252.21/3073.76	% SZS status Ended for HL401406+5.p
15252.21/3073.78	% SZS status Started for HL401410+4.p
15252.21/3073.78	% SZS status Theorem for HL401410+4.p
15252.21/3073.78	% SZS status Ended for HL401410+4.p
15258.07/3074.49	% SZS status Started for HL401411+5.p
15258.07/3074.49	% SZS status Theorem for HL401411+5.p
15258.07/3074.49	% SZS status Ended for HL401411+5.p
15267.83/3075.86	% SZS status Started for HL401411+4.p
15267.83/3075.86	% SZS status Theorem for HL401411+4.p
15267.83/3075.86	% SZS status Ended for HL401411+4.p
15271.74/3076.32	% SZS status Started for HL401407+4.p
15271.74/3076.32	% SZS status GaveUp for HL401407+4.p
15271.74/3076.32	% SZS status Ended for HL401407+4.p
15273.72/3076.51	% SZS status Started for HL401407+5.p
15273.72/3076.51	% SZS status GaveUp for HL401407+5.p
15273.72/3076.51	% SZS status Ended for HL401407+5.p
15276.38/3076.97	% SZS status Started for HL401412+4.p
15276.38/3076.97	% SZS status Theorem for HL401412+4.p
15276.38/3076.97	% SZS status Ended for HL401412+4.p
15280.94/3077.49	% SZS status Started for HL401408+4.p
15280.94/3077.49	% SZS status GaveUp for HL401408+4.p
15280.94/3077.49	% SZS status Ended for HL401408+4.p
15284.06/3077.99	% SZS status Started for HL401408+5.p
15284.06/3077.99	% SZS status GaveUp for HL401408+5.p
15284.06/3077.99	% SZS status Ended for HL401408+5.p
15296.69/3079.46	% SZS status Started for HL401409+5.p
15296.69/3079.46	% SZS status GaveUp for HL401409+5.p
15296.69/3079.46	% SZS status Ended for HL401409+5.p
15301.34/3080.04	% SZS status Started for HL401415+4.p
15301.34/3080.04	% SZS status Theorem for HL401415+4.p
15301.34/3080.04	% SZS status Ended for HL401415+4.p
15313.08/3081.76	% SZS status Started for HL401410+5.p
15313.08/3081.76	% SZS status GaveUp for HL401410+5.p
15313.08/3081.76	% SZS status Ended for HL401410+5.p
15322.64/3082.86	% SZS status Started for HL401412+5.p
15322.64/3082.86	% SZS status Theorem for HL401412+5.p
15322.64/3082.86	% SZS status Ended for HL401412+5.p
15338.49/3084.73	% SZS status Started for HL401413+4.p
15338.49/3084.73	% SZS status GaveUp for HL401413+4.p
15338.49/3084.73	% SZS status Ended for HL401413+4.p
15339.21/3084.83	% SZS status Started for HL401413+5.p
15339.21/3084.83	% SZS status GaveUp for HL401413+5.p
15339.21/3084.83	% SZS status Ended for HL401413+5.p
15345.56/3085.59	% SZS status Started for HL401414+4.p
15345.56/3085.59	% SZS status GaveUp for HL401414+4.p
15345.56/3085.59	% SZS status Ended for HL401414+4.p
15346.39/3085.76	% SZS status Started for HL401414+5.p
15346.39/3085.76	% SZS status GaveUp for HL401414+5.p
15346.39/3085.76	% SZS status Ended for HL401414+5.p
15360.78/3087.62	% SZS status Started for HL401415+5.p
15360.78/3087.62	% SZS status GaveUp for HL401415+5.p
15360.78/3087.62	% SZS status Ended for HL401415+5.p
15364.28/3088.29	% SZS status Started for HL401416+4.p
15364.28/3088.29	% SZS status GaveUp for HL401416+4.p
15364.28/3088.29	% SZS status Ended for HL401416+4.p
15379.86/3089.92	% SZS status Started for HL401416+5.p
15379.86/3089.92	% SZS status GaveUp for HL401416+5.p
15379.86/3089.92	% SZS status Ended for HL401416+5.p
15380.28/3090.00	% SZS status Started for HL401421+4.p
15380.28/3090.00	% SZS status Theorem for HL401421+4.p
15380.28/3090.00	% SZS status Ended for HL401421+4.p
15380.78/3090.27	% SZS status Started for HL401422+4.p
15380.78/3090.27	% SZS status Theorem for HL401422+4.p
15380.78/3090.27	% SZS status Ended for HL401422+4.p
15386.35/3090.76	% SZS status Started for HL401422+5.p
15386.35/3090.76	% SZS status Theorem for HL401422+5.p
15386.35/3090.76	% SZS status Ended for HL401422+5.p
15390.03/3091.19	% SZS status Started for HL401418+4.p
15390.03/3091.19	% SZS status GaveUp for HL401418+4.p
15390.03/3091.19	% SZS status Ended for HL401418+4.p
15392.97/3091.63	% SZS status Started for HL401423+4.p
15392.97/3091.63	% SZS status Theorem for HL401423+4.p
15392.97/3091.63	% SZS status Ended for HL401423+4.p
15395.80/3092.00	% SZS status Started for HL401423+5.p
15395.80/3092.00	% SZS status Theorem for HL401423+5.p
15395.80/3092.00	% SZS status Ended for HL401423+5.p
15401.26/3092.60	% SZS status Started for HL401425+5.p
15401.26/3092.60	% SZS status Theorem for HL401425+5.p
15401.26/3092.60	% SZS status Ended for HL401425+5.p
15401.26/3092.69	% SZS status Started for HL401425+4.p
15401.26/3092.69	% SZS status Theorem for HL401425+4.p
15401.26/3092.69	% SZS status Ended for HL401425+4.p
15403.01/3092.92	% SZS status Started for HL401418+5.p
15403.01/3092.92	% SZS status GaveUp for HL401418+5.p
15403.01/3092.92	% SZS status Ended for HL401418+5.p
15403.42/3093.07	% SZS status Started for HL401419+4.p
15403.42/3093.07	% SZS status GaveUp for HL401419+4.p
15403.42/3093.07	% SZS status Ended for HL401419+4.p
15410.25/3093.81	% SZS status Started for HL401419+5.p
15410.25/3093.81	% SZS status GaveUp for HL401419+5.p
15410.25/3093.81	% SZS status Ended for HL401419+5.p
15412.64/3094.08	% SZS status Started for HL401420+4.p
15412.64/3094.08	% SZS status GaveUp for HL401420+4.p
15412.64/3094.08	% SZS status Ended for HL401420+4.p
15419.96/3095.09	% SZS status Started for HL401429+5.p
15419.96/3095.09	% SZS status Theorem for HL401429+5.p
15419.96/3095.09	% SZS status Ended for HL401429+5.p
15426.18/3095.81	% SZS status Started for HL401420+5.p
15426.18/3095.81	% SZS status GaveUp for HL401420+5.p
15426.18/3095.81	% SZS status Ended for HL401420+5.p
15428.99/3096.16	% SZS status Started for HL401427+4.p
15428.99/3096.16	% SZS status Theorem for HL401427+4.p
15428.99/3096.16	% SZS status Ended for HL401427+4.p
15435.52/3096.94	% SZS status Started for HL401430+4.p
15435.52/3096.94	% SZS status Theorem for HL401430+4.p
15435.52/3096.94	% SZS status Ended for HL401430+4.p
15436.54/3097.16	% SZS status Started for HL401431+4.p
15436.54/3097.16	% SZS status Theorem for HL401431+4.p
15436.54/3097.16	% SZS status Ended for HL401431+4.p
15440.85/3097.61	% SZS status Started for HL401431+5.p
15440.85/3097.61	% SZS status Theorem for HL401431+5.p
15440.85/3097.61	% SZS status Ended for HL401431+5.p
15443.42/3098.09	% SZS status Started for HL401421+5.p
15443.42/3098.09	% SZS status GaveUp for HL401421+5.p
15443.42/3098.09	% SZS status Ended for HL401421+5.p
15443.42/3098.15	% SZS status Started for HL401432+4.p
15443.42/3098.15	% SZS status Theorem for HL401432+4.p
15443.42/3098.15	% SZS status Ended for HL401432+4.p
15446.12/3098.27	% SZS status Started for HL401432+5.p
15446.12/3098.27	% SZS status Theorem for HL401432+5.p
15446.12/3098.27	% SZS status Ended for HL401432+5.p
15460.17/3100.06	% SZS status Started for HL401436+4.p
15460.17/3100.06	% SZS status Theorem for HL401436+4.p
15460.17/3100.06	% SZS status Ended for HL401436+4.p
15466.63/3100.84	% SZS status Started for HL401427+5.p
15466.63/3100.84	% SZS status GaveUp for HL401427+5.p
15466.63/3100.84	% SZS status Ended for HL401427+5.p
15469.30/3101.23	% SZS status Started for HL401428+4.p
15469.30/3101.23	% SZS status GaveUp for HL401428+4.p
15469.30/3101.23	% SZS status Ended for HL401428+4.p
15469.30/3101.28	% SZS status Started for HL401428+5.p
15469.30/3101.28	% SZS status GaveUp for HL401428+5.p
15469.30/3101.28	% SZS status Ended for HL401428+5.p
15476.92/3102.18	% SZS status Started for HL401438+4.p
15476.92/3102.18	% SZS status Theorem for HL401438+4.p
15476.92/3102.18	% SZS status Ended for HL401438+4.p
15477.48/3102.26	% SZS status Started for HL401429+4.p
15477.48/3102.26	% SZS status GaveUp for HL401429+4.p
15477.48/3102.26	% SZS status Ended for HL401429+4.p
15492.25/3104.07	% SZS status Started for HL401430+5.p
15492.25/3104.07	% SZS status GaveUp for HL401430+5.p
15492.25/3104.07	% SZS status Ended for HL401430+5.p
15509.93/3106.29	% SZS status Started for HL401435+5.p
15509.93/3106.29	% SZS status GaveUp for HL401435+5.p
15509.93/3106.29	% SZS status Ended for HL401435+5.p
15510.13/3106.37	% SZS status Started for HL401435+4.p
15510.13/3106.37	% SZS status GaveUp for HL401435+4.p
15510.13/3106.37	% SZS status Ended for HL401435+4.p
15524.89/3108.14	% SZS status Started for HL401440+4.p
15524.89/3108.14	% SZS status Theorem for HL401440+4.p
15524.89/3108.14	% SZS status Ended for HL401440+4.p
15525.53/3108.25	% SZS status Started for HL401436+5.p
15525.53/3108.25	% SZS status GaveUp for HL401436+5.p
15525.53/3108.25	% SZS status Ended for HL401436+5.p
15531.95/3109.08	% SZS status Started for HL401437+4.p
15531.95/3109.08	% SZS status GaveUp for HL401437+4.p
15531.95/3109.08	% SZS status Ended for HL401437+4.p
15534.47/3109.40	% SZS status Started for HL401437+5.p
15534.47/3109.40	% SZS status GaveUp for HL401437+5.p
15534.47/3109.40	% SZS status Ended for HL401437+5.p
15538.90/3110.09	% SZS status Started for HL401441+4.p
15538.90/3110.09	% SZS status Theorem for HL401441+4.p
15538.90/3110.09	% SZS status Ended for HL401441+4.p
15541.94/3110.36	% SZS status Started for HL401438+5.p
15541.94/3110.36	% SZS status GaveUp for HL401438+5.p
15541.94/3110.36	% SZS status Ended for HL401438+5.p
15542.81/3110.58	% SZS status Started for HL401439+4.p
15542.81/3110.58	% SZS status GaveUp for HL401439+4.p
15542.81/3110.58	% SZS status Ended for HL401439+4.p
15557.51/3112.21	% SZS status Started for HL401439+5.p
15557.51/3112.21	% SZS status GaveUp for HL401439+5.p
15557.51/3112.21	% SZS status Ended for HL401439+5.p
15575.24/3114.58	% SZS status Started for HL401440+5.p
15575.24/3114.58	% SZS status GaveUp for HL401440+5.p
15575.24/3114.58	% SZS status Ended for HL401440+5.p
15590.11/3116.40	% SZS status Started for HL401441+5.p
15590.11/3116.40	% SZS status GaveUp for HL401441+5.p
15590.11/3116.40	% SZS status Ended for HL401441+5.p
15598.21/3117.36	% SZS status Started for HL401443+4.p
15598.21/3117.36	% SZS status GaveUp for HL401443+4.p
15598.21/3117.36	% SZS status Ended for HL401443+4.p
15599.45/3117.60	% SZS status Started for HL401443+5.p
15599.45/3117.60	% SZS status GaveUp for HL401443+5.p
15599.45/3117.60	% SZS status Ended for HL401443+5.p
15606.64/3118.39	% SZS status Started for HL401448+4.p
15606.64/3118.39	% SZS status Theorem for HL401448+4.p
15606.64/3118.39	% SZS status Ended for HL401448+4.p
15606.64/3118.39	% SZS status Started for HL401445+4.p
15606.64/3118.39	% SZS status GaveUp for HL401445+4.p
15606.64/3118.39	% SZS status Ended for HL401445+4.p
15607.42/3118.57	% SZS status Started for HL401445+5.p
15607.42/3118.57	% SZS status GaveUp for HL401445+5.p
15607.42/3118.57	% SZS status Ended for HL401445+5.p
15610.08/3118.86	% SZS status Started for HL401446+4.p
15610.08/3118.86	% SZS status GaveUp for HL401446+4.p
15610.08/3118.86	% SZS status Ended for HL401446+4.p
15623.57/3120.52	% SZS status Started for HL401446+5.p
15623.57/3120.52	% SZS status GaveUp for HL401446+5.p
15623.57/3120.52	% SZS status Ended for HL401446+5.p
15641.19/3122.95	% SZS status Started for HL401447+4.p
15641.19/3122.95	% SZS status GaveUp for HL401447+4.p
15641.19/3122.95	% SZS status Ended for HL401447+4.p
15655.48/3124.54	% SZS status Started for HL401447+5.p
15655.48/3124.54	% SZS status GaveUp for HL401447+5.p
15655.48/3124.54	% SZS status Ended for HL401447+5.p
15664.95/3125.75	% SZS status Started for HL401448+5.p
15664.95/3125.75	% SZS status GaveUp for HL401448+5.p
15664.95/3125.75	% SZS status Ended for HL401448+5.p
15671.13/3126.55	% SZS status Started for HL401449+5.p
15671.13/3126.55	% SZS status GaveUp for HL401449+5.p
15671.13/3126.55	% SZS status Ended for HL401449+5.p
15672.67/3126.77	% SZS status Started for HL401449+4.p
15672.67/3126.77	% SZS status GaveUp for HL401449+4.p
15672.67/3126.77	% SZS status Ended for HL401449+4.p
15673.28/3126.86	% SZS status Started for HL401450+4.p
15673.28/3126.86	% SZS status GaveUp for HL401450+4.p
15673.28/3126.86	% SZS status Ended for HL401450+4.p
15675.08/3127.02	% SZS status Started for HL401450+5.p
15675.08/3127.02	% SZS status GaveUp for HL401450+5.p
15675.08/3127.02	% SZS status Ended for HL401450+5.p
15688.22/3128.77	% SZS status Started for HL401451+4.p
15688.22/3128.77	% SZS status GaveUp for HL401451+4.p
15688.22/3128.77	% SZS status Ended for HL401451+4.p
15695.81/3129.70	% SZS status Started for HL401455+4.p
15695.81/3129.70	% SZS status Theorem for HL401455+4.p
15695.81/3129.70	% SZS status Ended for HL401455+4.p
15706.79/3131.22	% SZS status Started for HL401451+5.p
15706.79/3131.22	% SZS status GaveUp for HL401451+5.p
15706.79/3131.22	% SZS status Ended for HL401451+5.p
15710.73/3131.49	% SZS status Started for HL401456+4.p
15710.73/3131.49	% SZS status Theorem for HL401456+4.p
15710.73/3131.49	% SZS status Ended for HL401456+4.p
15722.85/3133.03	% SZS status Started for HL401452+4.p
15722.85/3133.03	% SZS status GaveUp for HL401452+4.p
15722.85/3133.03	% SZS status Ended for HL401452+4.p
15724.79/3133.38	% SZS status Started for HL401456+5.p
15724.79/3133.38	% SZS status Theorem for HL401456+5.p
15724.79/3133.38	% SZS status Ended for HL401456+5.p
15729.90/3133.90	% SZS status Started for HL401452+5.p
15729.90/3133.90	% SZS status GaveUp for HL401452+5.p
15729.90/3133.90	% SZS status Ended for HL401452+5.p
15737.43/3134.89	% SZS status Started for HL401453+4.p
15737.43/3134.89	% SZS status GaveUp for HL401453+4.p
15737.43/3134.89	% SZS status Ended for HL401453+4.p
15738.11/3134.97	% SZS status Started for HL401453+5.p
15738.11/3134.97	% SZS status GaveUp for HL401453+5.p
15738.11/3134.97	% SZS status Ended for HL401453+5.p
15739.87/3135.17	% SZS status Started for HL401454+5.p
15739.87/3135.17	% SZS status GaveUp for HL401454+5.p
15739.87/3135.17	% SZS status Ended for HL401454+5.p
15740.27/3135.23	% SZS status Started for HL401454+4.p
15740.27/3135.23	% SZS status GaveUp for HL401454+4.p
15740.27/3135.23	% SZS status Ended for HL401454+4.p
15749.47/3136.40	% SZS status Started for HL401461+4.p
15749.47/3136.40	% SZS status Theorem for HL401461+4.p
15749.47/3136.40	% SZS status Ended for HL401461+4.p
15760.05/3137.88	% SZS status Started for HL401455+5.p
15760.05/3137.88	% SZS status GaveUp for HL401455+5.p
15760.05/3137.88	% SZS status Ended for HL401455+5.p
15789.06/3141.42	% SZS status Started for HL401457+4.p
15789.06/3141.42	% SZS status GaveUp for HL401457+4.p
15789.06/3141.42	% SZS status Ended for HL401457+4.p
15789.53/3141.58	% SZS status Started for HL401457+5.p
15789.53/3141.58	% SZS status GaveUp for HL401457+5.p
15789.53/3141.58	% SZS status Ended for HL401457+5.p
15795.63/3142.19	% SZS status Started for HL401458+4.p
15795.63/3142.19	% SZS status GaveUp for HL401458+4.p
15795.63/3142.19	% SZS status Ended for HL401458+4.p
15800.45/3142.78	% SZS status Started for HL401463+5.p
15800.45/3142.78	% SZS status Theorem for HL401463+5.p
15800.45/3142.78	% SZS status Ended for HL401463+5.p
15801.49/3143.02	% SZS status Started for HL401465+4.p
15801.49/3143.02	% SZS status Theorem for HL401465+4.p
15801.49/3143.02	% SZS status Ended for HL401465+4.p
15802.18/3143.04	% SZS status Started for HL401458+5.p
15802.18/3143.04	% SZS status GaveUp for HL401458+5.p
15802.18/3143.04	% SZS status Ended for HL401458+5.p
15804.91/3143.36	% SZS status Started for HL401459+4.p
15804.91/3143.36	% SZS status GaveUp for HL401459+4.p
15804.91/3143.36	% SZS status Ended for HL401459+4.p
15805.35/3143.43	% SZS status Started for HL401465+5.p
15805.35/3143.43	% SZS status Theorem for HL401465+5.p
15805.35/3143.43	% SZS status Ended for HL401465+5.p
15805.79/3143.45	% SZS status Started for HL401459+5.p
15805.79/3143.45	% SZS status GaveUp for HL401459+5.p
15805.79/3143.45	% SZS status Ended for HL401459+5.p
15806.31/3143.59	% SZS status Started for HL401463+4.p
15806.31/3143.59	% SZS status Theorem for HL401463+4.p
15806.31/3143.59	% SZS status Ended for HL401463+4.p
15814.48/3144.56	% SZS status Started for HL401461+5.p
15814.48/3144.56	% SZS status GaveUp for HL401461+5.p
15814.48/3144.56	% SZS status Ended for HL401461+5.p
15828.02/3146.29	% SZS status Started for HL401462+4.p
15828.02/3146.29	% SZS status GaveUp for HL401462+4.p
15828.02/3146.29	% SZS status Ended for HL401462+4.p
15853.93/3149.57	% SZS status Started for HL401462+5.p
15853.93/3149.57	% SZS status GaveUp for HL401462+5.p
15853.93/3149.57	% SZS status Ended for HL401462+5.p
15868.62/3151.42	% SZS status Started for HL401466+4.p
15868.62/3151.42	% SZS status GaveUp for HL401466+4.p
15868.62/3151.42	% SZS status Ended for HL401466+4.p
15869.40/3151.51	% SZS status Started for HL401466+5.p
15869.40/3151.51	% SZS status GaveUp for HL401466+5.p
15869.40/3151.51	% SZS status Ended for HL401466+5.p
15870.06/3151.61	% SZS status Started for HL401468+5.p
15870.06/3151.61	% SZS status GaveUp for HL401468+5.p
15870.06/3151.61	% SZS status Ended for HL401468+5.p
15871.39/3151.94	% SZS status Started for HL401469+4.p
15871.39/3151.94	% SZS status GaveUp for HL401469+4.p
15871.39/3151.94	% SZS status Ended for HL401469+4.p
15871.39/3151.96	% SZS status Started for HL401468+4.p
15871.39/3151.96	% SZS status GaveUp for HL401468+4.p
15871.39/3151.96	% SZS status Ended for HL401468+4.p
15878.96/3152.73	% SZS status Started for HL401469+5.p
15878.96/3152.73	% SZS status GaveUp for HL401469+5.p
15878.96/3152.73	% SZS status Ended for HL401469+5.p
15894.24/3154.72	% SZS status Started for HL401470+4.p
15894.24/3154.72	% SZS status GaveUp for HL401470+4.p
15894.24/3154.72	% SZS status Ended for HL401470+4.p
15918.52/3157.73	% SZS status Started for HL401470+5.p
15918.52/3157.73	% SZS status GaveUp for HL401470+5.p
15918.52/3157.73	% SZS status Ended for HL401470+5.p
15934.39/3159.73	% SZS status Started for HL401472+5.p
15934.39/3159.73	% SZS status GaveUp for HL401472+5.p
15934.39/3159.73	% SZS status Ended for HL401472+5.p
15934.39/3159.74	% SZS status Started for HL401472+4.p
15934.39/3159.74	% SZS status GaveUp for HL401472+4.p
15934.39/3159.74	% SZS status Ended for HL401472+4.p
15936.63/3160.12	% SZS status Started for HL401473+4.p
15936.63/3160.12	% SZS status GaveUp for HL401473+4.p
15936.63/3160.12	% SZS status Ended for HL401473+4.p
15936.94/3160.17	% SZS status Started for HL401473+5.p
15936.94/3160.17	% SZS status GaveUp for HL401473+5.p
15936.94/3160.17	% SZS status Ended for HL401473+5.p
15939.85/3160.38	% SZS status Started for HL401474+4.p
15939.85/3160.38	% SZS status GaveUp for HL401474+4.p
15939.85/3160.38	% SZS status Ended for HL401474+4.p
15943.62/3160.91	% SZS status Started for HL401474+5.p
15943.62/3160.91	% SZS status GaveUp for HL401474+5.p
15943.62/3160.91	% SZS status Ended for HL401474+5.p
15961.09/3163.14	% SZS status Started for HL401475+4.p
15961.09/3163.14	% SZS status GaveUp for HL401475+4.p
15961.09/3163.14	% SZS status Ended for HL401475+4.p
15983.95/3165.96	% SZS status Started for HL401475+5.p
15983.95/3165.96	% SZS status GaveUp for HL401475+5.p
15983.95/3165.96	% SZS status Ended for HL401475+5.p
15998.84/3167.94	% SZS status Started for HL401476+5.p
15998.84/3167.94	% SZS status GaveUp for HL401476+5.p
15998.84/3167.94	% SZS status Ended for HL401476+5.p
16000.82/3168.13	% SZS status Started for HL401476+4.p
16000.82/3168.13	% SZS status GaveUp for HL401476+4.p
16000.82/3168.13	% SZS status Ended for HL401476+4.p
16001.96/3168.29	% SZS status Started for HL401480+4.p
16001.96/3168.29	% SZS status Theorem for HL401480+4.p
16001.96/3168.29	% SZS status Ended for HL401480+4.p
16002.32/3168.34	% SZS status Started for HL401477+5.p
16002.32/3168.34	% SZS status GaveUp for HL401477+5.p
16002.32/3168.34	% SZS status Ended for HL401477+5.p
16002.87/3168.49	% SZS status Started for HL401477+4.p
16002.87/3168.49	% SZS status GaveUp for HL401477+4.p
16002.87/3168.49	% SZS status Ended for HL401477+4.p
16005.72/3168.70	% SZS status Started for HL401478+4.p
16005.72/3168.70	% SZS status GaveUp for HL401478+4.p
16005.72/3168.70	% SZS status Ended for HL401478+4.p
16007.08/3168.86	% SZS status Started for HL401482+4.p
16007.08/3168.86	% SZS status Theorem for HL401482+4.p
16007.08/3168.86	% SZS status Ended for HL401482+4.p
16007.08/3168.90	% SZS status Started for HL401480+5.p
16007.08/3168.90	% SZS status Theorem for HL401480+5.p
16007.08/3168.90	% SZS status Ended for HL401480+5.p
16008.24/3169.08	% SZS status Started for HL401478+5.p
16008.24/3169.08	% SZS status GaveUp for HL401478+5.p
16008.24/3169.08	% SZS status Ended for HL401478+5.p
16010.05/3169.24	% SZS status Started for HL401483+4.p
16010.05/3169.24	% SZS status Theorem for HL401483+4.p
16010.05/3169.24	% SZS status Ended for HL401483+4.p
16011.41/3169.56	% SZS status Started for HL401483+5.p
16011.41/3169.56	% SZS status Theorem for HL401483+5.p
16011.41/3169.56	% SZS status Ended for HL401483+5.p
16027.66/3171.50	% SZS status Started for HL401479+4.p
16027.66/3171.50	% SZS status GaveUp for HL401479+4.p
16027.66/3171.50	% SZS status Ended for HL401479+4.p
16049.36/3174.18	% SZS status Started for HL401479+5.p
16049.36/3174.18	% SZS status GaveUp for HL401479+5.p
16049.36/3174.18	% SZS status Ended for HL401479+5.p
16050.50/3174.40	% SZS status Started for HL401482+5.p
16050.50/3174.40	% SZS status Theorem for HL401482+5.p
16050.50/3174.40	% SZS status Ended for HL401482+5.p
16067.67/3176.52	% SZS status Started for HL401481+5.p
16067.67/3176.52	% SZS status GaveUp for HL401481+5.p
16067.67/3176.52	% SZS status Ended for HL401481+5.p
16068.29/3176.75	% SZS status Started for HL401481+4.p
16068.29/3176.75	% SZS status GaveUp for HL401481+4.p
16068.29/3176.75	% SZS status Ended for HL401481+4.p
16074.52/3177.42	% SZS status Started for HL401485+5.p
16074.52/3177.42	% SZS status GaveUp for HL401485+5.p
16074.52/3177.42	% SZS status Ended for HL401485+5.p
16075.47/3177.50	% SZS status Started for HL401485+4.p
16075.47/3177.50	% SZS status GaveUp for HL401485+4.p
16075.47/3177.50	% SZS status Ended for HL401485+4.p
16075.95/3177.58	% SZS status Started for HL401489+4.p
16075.95/3177.58	% SZS status Theorem for HL401489+4.p
16075.95/3177.58	% SZS status Ended for HL401489+4.p
16076.85/3177.85	% SZS status Started for HL401487+4.p
16076.85/3177.85	% SZS status GaveUp for HL401487+4.p
16076.85/3177.85	% SZS status Ended for HL401487+4.p
16092.66/3179.64	% SZS status Started for HL401487+5.p
16092.66/3179.64	% SZS status GaveUp for HL401487+5.p
16092.66/3179.64	% SZS status Ended for HL401487+5.p
16115.84/3182.56	% SZS status Started for HL401489+5.p
16115.84/3182.56	% SZS status GaveUp for HL401489+5.p
16115.84/3182.56	% SZS status Ended for HL401489+5.p
16134.18/3185.02	% SZS status Started for HL401490+4.p
16134.18/3185.02	% SZS status GaveUp for HL401490+4.p
16134.18/3185.02	% SZS status Ended for HL401490+4.p
16135.86/3185.09	% SZS status Started for HL401490+5.p
16135.86/3185.09	% SZS status GaveUp for HL401490+5.p
16135.86/3185.09	% SZS status Ended for HL401490+5.p
16140.64/3185.68	% SZS status Started for HL401492+5.p
16140.64/3185.68	% SZS status GaveUp for HL401492+5.p
16140.64/3185.68	% SZS status Ended for HL401492+5.p
16141.11/3185.75	% SZS status Started for HL401492+4.p
16141.11/3185.75	% SZS status GaveUp for HL401492+4.p
16141.11/3185.75	% SZS status Ended for HL401492+4.p
16141.75/3185.92	% SZS status Started for HL401494+4.p
16141.75/3185.92	% SZS status GaveUp for HL401494+4.p
16141.75/3185.92	% SZS status Ended for HL401494+4.p
16142.29/3186.01	% SZS status Started for HL401494+5.p
16142.29/3186.01	% SZS status GaveUp for HL401494+5.p
16142.29/3186.01	% SZS status Ended for HL401494+5.p
16144.54/3186.20	% SZS status Started for HL401499+4.p
16144.54/3186.20	% SZS status Theorem for HL401499+4.p
16144.54/3186.20	% SZS status Ended for HL401499+4.p
16146.09/3186.50	% SZS status Started for HL401499+5.p
16146.09/3186.50	% SZS status Theorem for HL401499+5.p
16146.09/3186.50	% SZS status Ended for HL401499+5.p
16159.05/3188.01	% SZS status Started for HL401495+4.p
16159.05/3188.01	% SZS status GaveUp for HL401495+4.p
16159.05/3188.01	% SZS status Ended for HL401495+4.p
16180.64/3190.72	% SZS status Started for HL401495+5.p
16180.64/3190.72	% SZS status GaveUp for HL401495+5.p
16180.64/3190.72	% SZS status Ended for HL401495+5.p
16200.31/3193.26	% SZS status Started for HL401496+5.p
16200.31/3193.26	% SZS status GaveUp for HL401496+5.p
16200.31/3193.26	% SZS status Ended for HL401496+5.p
16201.66/3193.51	% SZS status Started for HL401496+4.p
16201.66/3193.51	% SZS status GaveUp for HL401496+4.p
16201.66/3193.51	% SZS status Ended for HL401496+4.p
16205.07/3193.93	% SZS status Started for HL401498+5.p
16205.07/3193.93	% SZS status GaveUp for HL401498+5.p
16205.07/3193.93	% SZS status Ended for HL401498+5.p
16206.97/3194.12	% SZS status Started for HL401498+4.p
16206.97/3194.12	% SZS status GaveUp for HL401498+4.p
16206.97/3194.12	% SZS status Ended for HL401498+4.p
16211.78/3194.68	% SZS status Started for HL401500+5.p
16211.78/3194.68	% SZS status GaveUp for HL401500+5.p
16211.78/3194.68	% SZS status Ended for HL401500+5.p
16212.75/3194.84	% SZS status Started for HL401500+4.p
16212.75/3194.84	% SZS status GaveUp for HL401500+4.p
16212.75/3194.84	% SZS status Ended for HL401500+4.p
16218.43/3195.59	% SZS status Started for HL401504+5.p
16218.43/3195.59	% SZS status Theorem for HL401504+5.p
16218.43/3195.59	% SZS status Ended for HL401504+5.p
16220.75/3195.77	% SZS status Started for HL401503+4.p
16220.75/3195.77	% SZS status Theorem for HL401503+4.p
16220.75/3195.77	% SZS status Ended for HL401503+4.p
16225.31/3196.36	% SZS status Started for HL401501+4.p
16225.31/3196.36	% SZS status GaveUp for HL401501+4.p
16225.31/3196.36	% SZS status Ended for HL401501+4.p
16226.82/3196.64	% SZS status Started for HL401504+4.p
16226.82/3196.64	% SZS status Theorem for HL401504+4.p
16226.82/3196.64	% SZS status Ended for HL401504+4.p
16244.39/3198.88	% SZS status Started for HL401501+5.p
16244.39/3198.88	% SZS status GaveUp for HL401501+5.p
16244.39/3198.88	% SZS status Ended for HL401501+5.p
16252.70/3199.87	% SZS status Started for HL401502+4.p
16252.70/3199.87	% SZS status Theorem for HL401502+4.p
16252.70/3199.87	% SZS status Ended for HL401502+4.p
16252.99/3199.95	% SZS status Started for HL401507+4.p
16252.99/3199.95	% SZS status Theorem for HL401507+4.p
16252.99/3199.95	% SZS status Ended for HL401507+4.p
16260.74/3200.85	% SZS status Started for HL401507+5.p
16260.74/3200.85	% SZS status Theorem for HL401507+5.p
16260.74/3200.85	% SZS status Ended for HL401507+5.p
16261.73/3201.08	% SZS status Started for HL401508+4.p
16261.73/3201.08	% SZS status Theorem for HL401508+4.p
16261.73/3201.08	% SZS status Ended for HL401508+4.p
16264.22/3201.33	% SZS status Started for HL401509+4.p
16264.22/3201.33	% SZS status Theorem for HL401509+4.p
16264.22/3201.33	% SZS status Ended for HL401509+4.p
16266.79/3201.71	% SZS status Started for HL401502+5.p
16266.79/3201.71	% SZS status GaveUp for HL401502+5.p
16266.79/3201.71	% SZS status Ended for HL401502+5.p
16268.20/3201.78	% SZS status Started for HL401509+5.p
16268.20/3201.78	% SZS status Theorem for HL401509+5.p
16268.20/3201.78	% SZS status Ended for HL401509+5.p
16268.88/3201.93	% SZS status Started for HL401508+5.p
16268.88/3201.93	% SZS status Theorem for HL401508+5.p
16268.88/3201.93	% SZS status Ended for HL401508+5.p
16269.90/3202.22	% SZS status Started for HL401512+4.p
16269.90/3202.22	% SZS status Theorem for HL401512+4.p
16269.90/3202.22	% SZS status Ended for HL401512+4.p
16272.62/3202.34	% SZS status Started for HL401511+5.p
16272.62/3202.34	% SZS status Theorem for HL401511+5.p
16272.62/3202.34	% SZS status Ended for HL401511+5.p
16272.62/3202.35	% SZS status Started for HL401503+5.p
16272.62/3202.35	% SZS status GaveUp for HL401503+5.p
16272.62/3202.35	% SZS status Ended for HL401503+5.p
16274.81/3202.77	% SZS status Started for HL401511+4.p
16274.81/3202.77	% SZS status Theorem for HL401511+4.p
16274.81/3202.77	% SZS status Ended for HL401511+4.p
16285.47/3204.00	% SZS status Started for HL401505+5.p
16285.47/3204.00	% SZS status GaveUp for HL401505+5.p
16285.47/3204.00	% SZS status Ended for HL401505+5.p
16286.06/3204.07	% SZS status Started for HL401505+4.p
16286.06/3204.07	% SZS status GaveUp for HL401505+4.p
16286.06/3204.07	% SZS status Ended for HL401505+4.p
16291.09/3204.70	% SZS status Started for HL401506+4.p
16291.09/3204.70	% SZS status GaveUp for HL401506+4.p
16291.09/3204.70	% SZS status Ended for HL401506+4.p
16291.67/3204.81	% SZS status Started for HL401506+5.p
16291.67/3204.81	% SZS status GaveUp for HL401506+5.p
16291.67/3204.81	% SZS status Ended for HL401506+5.p
16292.67/3204.97	% SZS status Started for HL401515+5.p
16292.67/3204.97	% SZS status Theorem for HL401515+5.p
16292.67/3204.97	% SZS status Ended for HL401515+5.p
16297.19/3205.61	% SZS status Started for HL401515+4.p
16297.19/3205.61	% SZS status Theorem for HL401515+4.p
16297.19/3205.61	% SZS status Ended for HL401515+4.p
16299.05/3205.72	% SZS status Started for HL401513+4.p
16299.05/3205.72	% SZS status Theorem for HL401513+4.p
16299.05/3205.72	% SZS status Ended for HL401513+4.p
16317.85/3208.17	% SZS status Started for HL401517+4.p
16317.85/3208.17	% SZS status Theorem for HL401517+4.p
16317.85/3208.17	% SZS status Ended for HL401517+4.p
16336.17/3210.40	% SZS status Started for HL401512+5.p
16336.17/3210.40	% SZS status GaveUp for HL401512+5.p
16336.17/3210.40	% SZS status Ended for HL401512+5.p
16336.81/3210.52	% SZS status Started for HL401513+5.p
16336.81/3210.52	% SZS status GaveUp for HL401513+5.p
16336.81/3210.52	% SZS status Ended for HL401513+5.p
16352.83/3212.52	% SZS status Started for HL401516+4.p
16352.83/3212.52	% SZS status GaveUp for HL401516+4.p
16352.83/3212.52	% SZS status Ended for HL401516+4.p
16355.81/3212.91	% SZS status Started for HL401516+5.p
16355.81/3212.91	% SZS status GaveUp for HL401516+5.p
16355.81/3212.91	% SZS status Ended for HL401516+5.p
16359.76/3213.33	% SZS status Started for HL401517+5.p
16359.76/3213.33	% SZS status GaveUp for HL401517+5.p
16359.76/3213.33	% SZS status Ended for HL401517+5.p
16363.88/3213.89	% SZS status Started for HL401518+5.p
16363.88/3213.89	% SZS status GaveUp for HL401518+5.p
16363.88/3213.89	% SZS status Ended for HL401518+5.p
16364.64/3213.96	% SZS status Started for HL401518+4.p
16364.64/3213.96	% SZS status GaveUp for HL401518+4.p
16364.64/3213.96	% SZS status Ended for HL401518+4.p
16384.72/3216.52	% SZS status Started for HL401519+4.p
16384.72/3216.52	% SZS status GaveUp for HL401519+4.p
16384.72/3216.52	% SZS status Ended for HL401519+4.p
16401.31/3218.61	% SZS status Started for HL401519+5.p
16401.31/3218.61	% SZS status GaveUp for HL401519+5.p
16401.31/3218.61	% SZS status Ended for HL401519+5.p
16402.88/3218.93	% SZS status Started for HL401520+4.p
16402.88/3218.93	% SZS status GaveUp for HL401520+4.p
16402.88/3218.93	% SZS status Ended for HL401520+4.p
16406.06/3219.23	% SZS status Started for HL401529+4.p
16406.06/3219.23	% SZS status Theorem for HL401529+4.p
16406.06/3219.23	% SZS status Ended for HL401529+4.p
16411.71/3220.00	% SZS status Started for HL401529+5.p
16411.71/3220.00	% SZS status Theorem for HL401529+5.p
16411.71/3220.00	% SZS status Ended for HL401529+5.p
16415.92/3220.72	% SZS status Started for HL401520+5.p
16415.92/3220.72	% SZS status GaveUp for HL401520+5.p
16415.92/3220.72	% SZS status Ended for HL401520+5.p
16421.04/3221.22	% SZS status Started for HL401521+4.p
16421.04/3221.22	% SZS status GaveUp for HL401521+4.p
16421.04/3221.22	% SZS status Ended for HL401521+4.p
16424.47/3221.59	% SZS status Started for HL401521+5.p
16424.47/3221.59	% SZS status GaveUp for HL401521+5.p
16424.47/3221.59	% SZS status Ended for HL401521+5.p
16428.85/3222.22	% SZS status Started for HL401524+5.p
16428.85/3222.22	% SZS status GaveUp for HL401524+5.p
16428.85/3222.22	% SZS status Ended for HL401524+5.p
16428.85/3222.23	% SZS status Started for HL401524+4.p
16428.85/3222.23	% SZS status GaveUp for HL401524+4.p
16428.85/3222.23	% SZS status Ended for HL401524+4.p
16450.90/3224.86	% SZS status Started for HL401525+4.p
16450.90/3224.86	% SZS status GaveUp for HL401525+4.p
16450.90/3224.86	% SZS status Ended for HL401525+4.p
16467.26/3226.92	% SZS status Started for HL401525+5.p
16467.26/3226.92	% SZS status GaveUp for HL401525+5.p
16467.26/3226.92	% SZS status Ended for HL401525+5.p
16480.67/3228.61	% SZS status Started for HL401530+4.p
16480.67/3228.61	% SZS status GaveUp for HL401530+4.p
16480.67/3228.61	% SZS status Ended for HL401530+4.p
16482.41/3228.93	% SZS status Started for HL401530+5.p
16482.41/3228.93	% SZS status GaveUp for HL401530+5.p
16482.41/3228.93	% SZS status Ended for HL401530+5.p
16486.62/3229.50	% SZS status Started for HL401531+4.p
16486.62/3229.50	% SZS status GaveUp for HL401531+4.p
16486.62/3229.50	% SZS status Ended for HL401531+4.p
16489.85/3229.78	% SZS status Started for HL401531+5.p
16489.85/3229.78	% SZS status GaveUp for HL401531+5.p
16489.85/3229.78	% SZS status Ended for HL401531+5.p
16495.00/3230.39	% SZS status Started for HL401533+5.p
16495.00/3230.39	% SZS status GaveUp for HL401533+5.p
16495.00/3230.39	% SZS status Ended for HL401533+5.p
16496.08/3230.54	% SZS status Started for HL401533+4.p
16496.08/3230.54	% SZS status GaveUp for HL401533+4.p
16496.08/3230.54	% SZS status Ended for HL401533+4.p
16497.05/3230.71	% SZS status Started for HL401537+4.p
16497.05/3230.71	% SZS status Theorem for HL401537+4.p
16497.05/3230.71	% SZS status Ended for HL401537+4.p
16516.82/3233.23	% SZS status Started for HL401534+4.p
16516.82/3233.23	% SZS status GaveUp for HL401534+4.p
16516.82/3233.23	% SZS status Ended for HL401534+4.p
16531.24/3235.08	% SZS status Started for HL401534+5.p
16531.24/3235.08	% SZS status GaveUp for HL401534+5.p
16531.24/3235.08	% SZS status Ended for HL401534+5.p
16547.58/3237.04	% SZS status Started for HL401535+4.p
16547.58/3237.04	% SZS status GaveUp for HL401535+4.p
16547.58/3237.04	% SZS status Ended for HL401535+4.p
16548.34/3237.16	% SZS status Started for HL401535+5.p
16548.34/3237.16	% SZS status GaveUp for HL401535+5.p
16548.34/3237.16	% SZS status Ended for HL401535+5.p
16554.02/3237.84	% SZS status Started for HL401536+4.p
16554.02/3237.84	% SZS status GaveUp for HL401536+4.p
16554.02/3237.84	% SZS status Ended for HL401536+4.p
16555.22/3238.02	% SZS status Started for HL401536+5.p
16555.22/3238.02	% SZS status GaveUp for HL401536+5.p
16555.22/3238.02	% SZS status Ended for HL401536+5.p
16561.55/3238.79	% SZS status Started for HL401537+5.p
16561.55/3238.79	% SZS status GaveUp for HL401537+5.p
16561.55/3238.79	% SZS status Ended for HL401537+5.p
16563.58/3239.09	% SZS status Started for HL401539+4.p
16563.58/3239.09	% SZS status GaveUp for HL401539+4.p
16563.58/3239.09	% SZS status Ended for HL401539+4.p
16582.93/3241.51	% SZS status Started for HL401539+5.p
16582.93/3241.51	% SZS status GaveUp for HL401539+5.p
16582.93/3241.51	% SZS status Ended for HL401539+5.p
16597.73/3243.38	% SZS status Started for HL401541+4.p
16597.73/3243.38	% SZS status GaveUp for HL401541+4.p
16597.73/3243.38	% SZS status Ended for HL401541+4.p
16612.28/3245.21	% SZS status Started for HL401541+5.p
16612.28/3245.21	% SZS status GaveUp for HL401541+5.p
16612.28/3245.21	% SZS status Ended for HL401541+5.p
16614.92/3245.55	% SZS status Started for HL401542+4.p
16614.92/3245.55	% SZS status GaveUp for HL401542+4.p
16614.92/3245.55	% SZS status Ended for HL401542+4.p
16619.88/3246.13	% SZS status Started for HL401542+5.p
16619.88/3246.13	% SZS status GaveUp for HL401542+5.p
16619.88/3246.13	% SZS status Ended for HL401542+5.p
16620.42/3246.28	% SZS status Started for HL401543+4.p
16620.42/3246.28	% SZS status GaveUp for HL401543+4.p
16620.42/3246.28	% SZS status Ended for HL401543+4.p
16625.29/3246.96	% SZS status Started for HL401543+5.p
16625.29/3246.96	% SZS status GaveUp for HL401543+5.p
16625.29/3246.96	% SZS status Ended for HL401543+5.p
16629.40/3247.41	% SZS status Started for HL401545+4.p
16629.40/3247.41	% SZS status GaveUp for HL401545+4.p
16629.40/3247.41	% SZS status Ended for HL401545+4.p
16646.98/3249.65	% SZS status Started for HL401545+5.p
16646.98/3249.65	% SZS status GaveUp for HL401545+5.p
16646.98/3249.65	% SZS status Ended for HL401545+5.p
16663.76/3251.67	% SZS status Started for HL401546+4.p
16663.76/3251.67	% SZS status GaveUp for HL401546+4.p
16663.76/3251.67	% SZS status Ended for HL401546+4.p
16678.01/3253.55	% SZS status Started for HL401546+5.p
16678.01/3253.55	% SZS status GaveUp for HL401546+5.p
16678.01/3253.55	% SZS status Ended for HL401546+5.p
16680.69/3253.81	% SZS status Started for HL401547+4.p
16680.69/3253.81	% SZS status GaveUp for HL401547+4.p
16680.69/3253.81	% SZS status Ended for HL401547+4.p
16681.80/3254.10	% SZS status Started for HL401554+4.p
16681.80/3254.10	% SZS status Theorem for HL401554+4.p
16681.80/3254.10	% SZS status Ended for HL401554+4.p
16684.52/3254.28	% SZS status Started for HL401547+5.p
16684.52/3254.28	% SZS status GaveUp for HL401547+5.p
16684.52/3254.28	% SZS status Ended for HL401547+5.p
16686.09/3254.57	% SZS status Started for HL401548+4.p
16686.09/3254.57	% SZS status GaveUp for HL401548+4.p
16686.09/3254.57	% SZS status Ended for HL401548+4.p
16689.81/3255.18	% SZS status Started for HL401548+5.p
16689.81/3255.18	% SZS status GaveUp for HL401548+5.p
16689.81/3255.18	% SZS status Ended for HL401548+5.p
16695.74/3255.75	% SZS status Started for HL401549+4.p
16695.74/3255.75	% SZS status GaveUp for HL401549+4.p
16695.74/3255.75	% SZS status Ended for HL401549+4.p
16712.49/3257.82	% SZS status Started for HL401549+5.p
16712.49/3257.82	% SZS status GaveUp for HL401549+5.p
16712.49/3257.82	% SZS status Ended for HL401549+5.p
16729.83/3259.98	% SZS status Started for HL401553+4.p
16729.83/3259.98	% SZS status GaveUp for HL401553+4.p
16729.83/3259.98	% SZS status Ended for HL401553+4.p
16743.82/3261.71	% SZS status Started for HL401553+5.p
16743.82/3261.71	% SZS status GaveUp for HL401553+5.p
16743.82/3261.71	% SZS status Ended for HL401553+5.p
16748.73/3262.31	% SZS status Started for HL401554+5.p
16748.73/3262.31	% SZS status GaveUp for HL401554+5.p
16748.73/3262.31	% SZS status Ended for HL401554+5.p
16750.77/3262.61	% SZS status Started for HL401555+4.p
16750.77/3262.61	% SZS status GaveUp for HL401555+4.p
16750.77/3262.61	% SZS status Ended for HL401555+4.p
16752.15/3262.75	% SZS status Started for HL401555+5.p
16752.15/3262.75	% SZS status GaveUp for HL401555+5.p
16752.15/3262.75	% SZS status Ended for HL401555+5.p
16758.11/3263.53	% SZS status Started for HL401556+4.p
16758.11/3263.53	% SZS status GaveUp for HL401556+4.p
16758.11/3263.53	% SZS status Ended for HL401556+4.p
16761.77/3263.97	% SZS status Started for HL401556+5.p
16761.77/3263.97	% SZS status GaveUp for HL401556+5.p
16761.77/3263.97	% SZS status Ended for HL401556+5.p
16761.77/3264.00	% SZS status Started for HL401557+4.p
16761.77/3264.00	% SZS status Theorem for HL401557+4.p
16761.77/3264.00	% SZS status Ended for HL401557+4.p
16785.86/3267.06	% SZS status Started for HL401561+4.p
16785.86/3267.06	% SZS status Theorem for HL401561+4.p
16785.86/3267.06	% SZS status Ended for HL401561+4.p
16794.22/3268.13	% SZS status Started for HL401557+5.p
16794.22/3268.13	% SZS status GaveUp for HL401557+5.p
16794.22/3268.13	% SZS status Ended for HL401557+5.p
16809.70/3270.05	% SZS status Started for HL401558+4.p
16809.70/3270.05	% SZS status GaveUp for HL401558+4.p
16809.70/3270.05	% SZS status Ended for HL401558+4.p
16812.69/3270.47	% SZS status Started for HL401558+5.p
16812.69/3270.47	% SZS status GaveUp for HL401558+5.p
16812.69/3270.47	% SZS status Ended for HL401558+5.p
16817.02/3270.92	% SZS status Started for HL401559+5.p
16817.02/3270.92	% SZS status GaveUp for HL401559+5.p
16817.02/3270.92	% SZS status Ended for HL401559+5.p
16817.57/3270.98	% SZS status Started for HL401559+4.p
16817.57/3270.98	% SZS status GaveUp for HL401559+4.p
16817.57/3270.98	% SZS status Ended for HL401559+4.p
16824.88/3271.90	% SZS status Started for HL401560+4.p
16824.88/3271.90	% SZS status GaveUp for HL401560+4.p
16824.88/3271.90	% SZS status Ended for HL401560+4.p
16826.94/3272.17	% SZS status Started for HL401560+5.p
16826.94/3272.17	% SZS status GaveUp for HL401560+5.p
16826.94/3272.17	% SZS status Ended for HL401560+5.p
16841.48/3274.03	% SZS status Started for HL401564+4.p
16841.48/3274.03	% SZS status Theorem for HL401564+4.p
16841.48/3274.03	% SZS status Ended for HL401564+4.p
16851.84/3275.29	% SZS status Started for HL401561+5.p
16851.84/3275.29	% SZS status GaveUp for HL401561+5.p
16851.84/3275.29	% SZS status Ended for HL401561+5.p
16861.44/3276.48	% SZS status Started for HL401562+4.p
16861.44/3276.48	% SZS status GaveUp for HL401562+4.p
16861.44/3276.48	% SZS status Ended for HL401562+4.p
16874.97/3278.23	% SZS status Started for HL401562+5.p
16874.97/3278.23	% SZS status GaveUp for HL401562+5.p
16874.97/3278.23	% SZS status Ended for HL401562+5.p
16879.02/3278.74	% SZS status Started for HL401563+4.p
16879.02/3278.74	% SZS status GaveUp for HL401563+4.p
16879.02/3278.74	% SZS status Ended for HL401563+4.p
16882.27/3279.17	% SZS status Started for HL401563+5.p
16882.27/3279.17	% SZS status GaveUp for HL401563+5.p
16882.27/3279.17	% SZS status Ended for HL401563+5.p
16888.60/3280.05	% SZS status Started for HL401567+4.p
16888.60/3280.05	% SZS status Theorem for HL401567+4.p
16888.60/3280.05	% SZS status Ended for HL401567+4.p
16890.70/3280.16	% SZS status Started for HL401564+5.p
16890.70/3280.16	% SZS status GaveUp for HL401564+5.p
16890.70/3280.16	% SZS status Ended for HL401564+5.p
16892.31/3280.45	% SZS status Started for HL401565+4.p
16892.31/3280.45	% SZS status GaveUp for HL401565+4.p
16892.31/3280.45	% SZS status Ended for HL401565+4.p
16897.78/3281.10	% SZS status Started for HL401568+4.p
16897.78/3281.10	% SZS status Theorem for HL401568+4.p
16897.78/3281.10	% SZS status Ended for HL401568+4.p
16906.96/3282.25	% SZS status Started for HL401565+5.p
16906.96/3282.25	% SZS status GaveUp for HL401565+5.p
16906.96/3282.25	% SZS status Ended for HL401565+5.p
16918.22/3283.62	% SZS status Started for HL401566+4.p
16918.22/3283.62	% SZS status GaveUp for HL401566+4.p
16918.22/3283.62	% SZS status Ended for HL401566+4.p
16926.39/3284.64	% SZS status Started for HL401566+5.p
16926.39/3284.64	% SZS status GaveUp for HL401566+5.p
16926.39/3284.64	% SZS status Ended for HL401566+5.p
16943.80/3286.89	% SZS status Started for HL401567+5.p
16943.80/3286.89	% SZS status GaveUp for HL401567+5.p
16943.80/3286.89	% SZS status Ended for HL401567+5.p
16954.52/3288.20	% SZS status Started for HL401568+5.p
16954.52/3288.20	% SZS status GaveUp for HL401568+5.p
16954.52/3288.20	% SZS status Ended for HL401568+5.p
16957.13/3288.56	% SZS status Started for HL401569+4.p
16957.13/3288.56	% SZS status GaveUp for HL401569+4.p
16957.13/3288.56	% SZS status Ended for HL401569+4.p
16958.53/3288.74	% SZS status Started for HL401569+5.p
16958.53/3288.74	% SZS status GaveUp for HL401569+5.p
16958.53/3288.74	% SZS status Ended for HL401569+5.p
16963.33/3289.37	% SZS status Started for HL401570+4.p
16963.33/3289.37	% SZS status GaveUp for HL401570+4.p
16963.33/3289.37	% SZS status Ended for HL401570+4.p
16972.11/3290.42	% SZS status Started for HL401571+4.p
16972.11/3290.42	% SZS status Theorem for HL401571+4.p
16972.11/3290.42	% SZS status Ended for HL401571+4.p
16973.09/3290.52	% SZS status Started for HL401570+5.p
16973.09/3290.52	% SZS status GaveUp for HL401570+5.p
16973.09/3290.52	% SZS status Ended for HL401570+5.p
16990.82/3292.84	% SZS status Started for HL401571+5.p
16990.82/3292.84	% SZS status GaveUp for HL401571+5.p
16990.82/3292.84	% SZS status Ended for HL401571+5.p
17009.24/3295.20	% SZS status Started for HL401572+4.p
17009.24/3295.20	% SZS status GaveUp for HL401572+4.p
17009.24/3295.20	% SZS status Ended for HL401572+4.p
17019.32/3296.40	% SZS status Started for HL401572+5.p
17019.32/3296.40	% SZS status GaveUp for HL401572+5.p
17019.32/3296.40	% SZS status Ended for HL401572+5.p
17021.20/3296.61	% SZS status Started for HL401575+4.p
17021.20/3296.61	% SZS status Theorem for HL401575+4.p
17021.20/3296.61	% SZS status Ended for HL401575+4.p
17022.48/3296.89	% SZS status Started for HL401573+4.p
17022.48/3296.89	% SZS status GaveUp for HL401573+4.p
17022.48/3296.89	% SZS status Ended for HL401573+4.p
17022.48/3296.90	% SZS status Started for HL401573+5.p
17022.48/3296.90	% SZS status GaveUp for HL401573+5.p
17022.48/3296.90	% SZS status Ended for HL401573+5.p
17027.11/3297.39	% SZS status Started for HL401577+4.p
17027.11/3297.39	% SZS status Theorem for HL401577+4.p
17027.11/3297.39	% SZS status Ended for HL401577+4.p
17037.37/3298.67	% SZS status Started for HL401575+5.p
17037.37/3298.67	% SZS status GaveUp for HL401575+5.p
17037.37/3298.67	% SZS status Ended for HL401575+5.p
17039.65/3298.94	% SZS status Started for HL401576+4.p
17039.65/3298.94	% SZS status GaveUp for HL401576+4.p
17039.65/3298.94	% SZS status Ended for HL401576+4.p
17056.58/3301.02	% SZS status Started for HL401576+5.p
17056.58/3301.02	% SZS status GaveUp for HL401576+5.p
17056.58/3301.02	% SZS status Ended for HL401576+5.p
17082.03/3304.55	% SZS status Started for HL401577+5.p
17082.03/3304.55	% SZS status GaveUp for HL401577+5.p
17082.03/3304.55	% SZS status Ended for HL401577+5.p
17087.41/3304.92	% SZS status Started for HL401580+4.p
17087.41/3304.92	% SZS status GaveUp for HL401580+4.p
17087.41/3304.92	% SZS status Ended for HL401580+4.p
17088.46/3305.14	% SZS status Started for HL401580+5.p
17088.46/3305.14	% SZS status GaveUp for HL401580+5.p
17088.46/3305.14	% SZS status Ended for HL401580+5.p
17090.26/3305.26	% SZS status Started for HL401581+4.p
17090.26/3305.26	% SZS status GaveUp for HL401581+4.p
17090.26/3305.26	% SZS status Ended for HL401581+4.p
17091.98/3305.57	% SZS status Started for HL401581+5.p
17091.98/3305.57	% SZS status GaveUp for HL401581+5.p
17091.98/3305.57	% SZS status Ended for HL401581+5.p
17104.43/3307.02	% SZS status Started for HL401582+4.p
17104.43/3307.02	% SZS status GaveUp for HL401582+4.p
17104.43/3307.02	% SZS status Ended for HL401582+4.p
17105.12/3307.12	% SZS status Started for HL401582+5.p
17105.12/3307.12	% SZS status GaveUp for HL401582+5.p
17105.12/3307.12	% SZS status Ended for HL401582+5.p
17123.33/3309.40	% SZS status Started for HL401583+4.p
17123.33/3309.40	% SZS status GaveUp for HL401583+4.p
17123.33/3309.40	% SZS status Ended for HL401583+4.p
17149.84/3312.77	% SZS status Started for HL401583+5.p
17149.84/3312.77	% SZS status GaveUp for HL401583+5.p
17149.84/3312.77	% SZS status Ended for HL401583+5.p
17153.08/3313.21	% SZS status Started for HL401584+4.p
17153.08/3313.21	% SZS status GaveUp for HL401584+4.p
17153.08/3313.21	% SZS status Ended for HL401584+4.p
17154.44/3313.30	% SZS status Started for HL401584+5.p
17154.44/3313.30	% SZS status GaveUp for HL401584+5.p
17154.44/3313.30	% SZS status Ended for HL401584+5.p
17155.35/3313.56	% SZS status Started for HL401585+4.p
17155.35/3313.56	% SZS status GaveUp for HL401585+4.p
17155.35/3313.56	% SZS status Ended for HL401585+4.p
17157.82/3313.72	% SZS status Started for HL401585+5.p
17157.82/3313.72	% SZS status GaveUp for HL401585+5.p
17157.82/3313.72	% SZS status Ended for HL401585+5.p
17170.22/3315.31	% SZS status Started for HL401586+5.p
17170.22/3315.31	% SZS status GaveUp for HL401586+5.p
17170.22/3315.31	% SZS status Ended for HL401586+5.p
17170.22/3315.32	% SZS status Started for HL401586+4.p
17170.22/3315.32	% SZS status GaveUp for HL401586+4.p
17170.22/3315.32	% SZS status Ended for HL401586+4.p
17188.69/3317.68	% SZS status Started for HL401587+4.p
17188.69/3317.68	% SZS status GaveUp for HL401587+4.p
17188.69/3317.68	% SZS status Ended for HL401587+4.p
17214.85/3320.95	% SZS status Started for HL401587+5.p
17214.85/3320.95	% SZS status GaveUp for HL401587+5.p
17214.85/3320.95	% SZS status Ended for HL401587+5.p
17219.02/3321.46	% SZS status Started for HL401589+5.p
17219.02/3321.46	% SZS status GaveUp for HL401589+5.p
17219.02/3321.46	% SZS status Ended for HL401589+5.p
17219.80/3321.50	% SZS status Started for HL401589+4.p
17219.80/3321.50	% SZS status GaveUp for HL401589+4.p
17219.80/3321.50	% SZS status Ended for HL401589+4.p
17222.31/3321.85	% SZS status Started for HL401590+4.p
17222.31/3321.85	% SZS status GaveUp for HL401590+4.p
17222.31/3321.85	% SZS status Ended for HL401590+4.p
17222.97/3321.94	% SZS status Started for HL401590+5.p
17222.97/3321.94	% SZS status GaveUp for HL401590+5.p
17222.97/3321.94	% SZS status Ended for HL401590+5.p
17235.86/3323.55	% SZS status Started for HL401591+5.p
17235.86/3323.55	% SZS status GaveUp for HL401591+5.p
17235.86/3323.55	% SZS status Ended for HL401591+5.p
17235.86/3323.58	% SZS status Started for HL401591+4.p
17235.86/3323.58	% SZS status GaveUp for HL401591+4.p
17235.86/3323.58	% SZS status Ended for HL401591+4.p
17254.95/3326.04	% SZS status Started for HL401593+4.p
17254.95/3326.04	% SZS status GaveUp for HL401593+4.p
17254.95/3326.04	% SZS status Ended for HL401593+4.p
17263.73/3327.02	% SZS status Started for HL401597+4.p
17263.73/3327.02	% SZS status Theorem for HL401597+4.p
17263.73/3327.02	% SZS status Ended for HL401597+4.p
17267.62/3327.58	% SZS status Started for HL401597+5.p
17267.62/3327.58	% SZS status Theorem for HL401597+5.p
17267.62/3327.58	% SZS status Ended for HL401597+5.p
17278.66/3329.13	% SZS status Started for HL401593+5.p
17278.66/3329.13	% SZS status GaveUp for HL401593+5.p
17278.66/3329.13	% SZS status Ended for HL401593+5.p
17284.51/3329.73	% SZS status Started for HL401594+4.p
17284.51/3329.73	% SZS status GaveUp for HL401594+4.p
17284.51/3329.73	% SZS status Ended for HL401594+4.p
17284.51/3329.74	% SZS status Started for HL401594+5.p
17284.51/3329.74	% SZS status GaveUp for HL401594+5.p
17284.51/3329.74	% SZS status Ended for HL401594+5.p
17287.47/3330.13	% SZS status Started for HL401595+4.p
17287.47/3330.13	% SZS status GaveUp for HL401595+4.p
17287.47/3330.13	% SZS status Ended for HL401595+4.p
17287.47/3330.15	% SZS status Started for HL401595+5.p
17287.47/3330.15	% SZS status GaveUp for HL401595+5.p
17287.47/3330.15	% SZS status Ended for HL401595+5.p
17301.72/3331.80	% SZS status Started for HL401596+4.p
17301.72/3331.80	% SZS status GaveUp for HL401596+4.p
17301.72/3331.80	% SZS status Ended for HL401596+4.p
17301.72/3331.82	% SZS status Started for HL401596+5.p
17301.72/3331.82	% SZS status GaveUp for HL401596+5.p
17301.72/3331.82	% SZS status Ended for HL401596+5.p
17334.52/3335.99	% SZS status Started for HL401598+4.p
17334.52/3335.99	% SZS status GaveUp for HL401598+4.p
17334.52/3335.99	% SZS status Ended for HL401598+4.p
17345.50/3337.37	% SZS status Started for HL401598+5.p
17345.50/3337.37	% SZS status GaveUp for HL401598+5.p
17345.50/3337.37	% SZS status Ended for HL401598+5.p
17350.35/3337.92	% SZS status Started for HL401599+5.p
17350.35/3337.92	% SZS status GaveUp for HL401599+5.p
17350.35/3337.92	% SZS status Ended for HL401599+5.p
17351.03/3338.03	% SZS status Started for HL401599+4.p
17351.03/3338.03	% SZS status GaveUp for HL401599+4.p
17351.03/3338.03	% SZS status Ended for HL401599+4.p
17353.59/3338.34	% SZS status Started for HL401600+5.p
17353.59/3338.34	% SZS status GaveUp for HL401600+5.p
17353.59/3338.34	% SZS status Ended for HL401600+5.p
17354.29/3338.45	% SZS status Started for HL401600+4.p
17354.29/3338.45	% SZS status GaveUp for HL401600+4.p
17354.29/3338.45	% SZS status Ended for HL401600+4.p
17366.45/3340.00	% SZS status Started for HL401601+5.p
17366.45/3340.00	% SZS status GaveUp for HL401601+5.p
17366.45/3340.00	% SZS status Ended for HL401601+5.p
17367.60/3340.13	% SZS status Started for HL401601+4.p
17367.60/3340.13	% SZS status GaveUp for HL401601+4.p
17367.60/3340.13	% SZS status Ended for HL401601+4.p
17387.14/3342.70	% SZS status Started for HL401605+4.p
17387.14/3342.70	% SZS status Theorem for HL401605+4.p
17387.14/3342.70	% SZS status Ended for HL401605+4.p
17391.03/3343.09	% SZS status Started for HL401605+5.p
17391.03/3343.09	% SZS status Theorem for HL401605+5.p
17391.03/3343.09	% SZS status Ended for HL401605+5.p
17401.90/3344.41	% SZS status Started for HL401602+4.p
17401.90/3344.41	% SZS status GaveUp for HL401602+4.p
17401.90/3344.41	% SZS status Ended for HL401602+4.p
17403.77/3344.68	% SZS status Started for HL401610+4.p
17403.77/3344.68	% SZS status Theorem for HL401610+4.p
17403.77/3344.68	% SZS status Ended for HL401610+4.p
17409.08/3345.49	% SZS status Started for HL401610+5.p
17409.08/3345.49	% SZS status Theorem for HL401610+5.p
17409.08/3345.49	% SZS status Ended for HL401610+5.p
17411.65/3345.62	% SZS status Started for HL401602+5.p
17411.65/3345.62	% SZS status GaveUp for HL401602+5.p
17411.65/3345.62	% SZS status Ended for HL401602+5.p
17413.91/3346.19	% SZS status Started for HL401603+5.p
17413.91/3346.19	% SZS status GaveUp for HL401603+5.p
17413.91/3346.19	% SZS status Ended for HL401603+5.p
17416.53/3346.24	% SZS status Started for HL401603+4.p
17416.53/3346.24	% SZS status GaveUp for HL401603+4.p
17416.53/3346.24	% SZS status Ended for HL401603+4.p
17418.68/3346.63	% SZS status Started for HL401604+4.p
17418.68/3346.63	% SZS status GaveUp for HL401604+4.p
17418.68/3346.63	% SZS status Ended for HL401604+4.p
17418.68/3346.64	% SZS status Started for HL401604+5.p
17418.68/3346.64	% SZS status GaveUp for HL401604+5.p
17418.68/3346.64	% SZS status Ended for HL401604+5.p
17425.22/3347.40	% SZS status Started for HL401608+4.p
17425.22/3347.40	% SZS status Theorem for HL401608+4.p
17425.22/3347.40	% SZS status Ended for HL401608+4.p
17427.02/3347.53	% SZS status Started for HL401611+5.p
17427.02/3347.53	% SZS status Theorem for HL401611+5.p
17427.02/3347.53	% SZS status Ended for HL401611+5.p
17429.16/3348.03	% SZS status Started for HL401611+4.p
17429.16/3348.03	% SZS status Theorem for HL401611+4.p
17429.16/3348.03	% SZS status Ended for HL401611+4.p
17457.11/3351.32	% SZS status Started for HL401608+5.p
17457.11/3351.32	% SZS status GaveUp for HL401608+5.p
17457.11/3351.32	% SZS status Ended for HL401608+5.p
17481.85/3354.44	% SZS status Started for HL401612+5.p
17481.85/3354.44	% SZS status GaveUp for HL401612+5.p
17481.85/3354.44	% SZS status Ended for HL401612+5.p
17481.85/3354.46	% SZS status Started for HL401612+4.p
17481.85/3354.46	% SZS status GaveUp for HL401612+4.p
17481.85/3354.46	% SZS status Ended for HL401612+4.p
17483.53/3354.80	% SZS status Started for HL401613+5.p
17483.53/3354.80	% SZS status GaveUp for HL401613+5.p
17483.53/3354.80	% SZS status Ended for HL401613+5.p
17484.01/3354.93	% SZS status Started for HL401613+4.p
17484.01/3354.93	% SZS status GaveUp for HL401613+4.p
17484.01/3354.93	% SZS status Ended for HL401613+4.p
17492.18/3355.73	% SZS status Started for HL401614+5.p
17492.18/3355.73	% SZS status GaveUp for HL401614+5.p
17492.18/3355.73	% SZS status Ended for HL401614+5.p
17492.32/3355.74	% SZS status Started for HL401614+4.p
17492.32/3355.74	% SZS status GaveUp for HL401614+4.p
17492.32/3355.74	% SZS status Ended for HL401614+4.p
17493.75/3355.98	% SZS status Started for HL401618+4.p
17493.75/3355.98	% SZS status Theorem for HL401618+4.p
17493.75/3355.98	% SZS status Ended for HL401618+4.p
17495.88/3356.23	% SZS status Started for HL401618+5.p
17495.88/3356.23	% SZS status Theorem for HL401618+5.p
17495.88/3356.23	% SZS status Ended for HL401618+5.p
17496.75/3356.32	% SZS status Started for HL401615+4.p
17496.75/3356.32	% SZS status GaveUp for HL401615+4.p
17496.75/3356.32	% SZS status Ended for HL401615+4.p
17521.72/3359.51	% SZS status Started for HL401615+5.p
17521.72/3359.51	% SZS status GaveUp for HL401615+5.p
17521.72/3359.51	% SZS status Ended for HL401615+5.p
17531.11/3360.68	% SZS status Started for HL401619+4.p
17531.11/3360.68	% SZS status Theorem for HL401619+4.p
17531.11/3360.68	% SZS status Ended for HL401619+4.p
17546.30/3362.63	% SZS status Started for HL401616+5.p
17546.30/3362.63	% SZS status GaveUp for HL401616+5.p
17546.30/3362.63	% SZS status Ended for HL401616+5.p
17548.25/3362.78	% SZS status Started for HL401616+4.p
17548.25/3362.78	% SZS status GaveUp for HL401616+4.p
17548.25/3362.78	% SZS status Ended for HL401616+4.p
17550.12/3363.09	% SZS status Started for HL401617+4.p
17550.12/3363.09	% SZS status GaveUp for HL401617+4.p
17550.12/3363.09	% SZS status Ended for HL401617+4.p
17550.12/3363.10	% SZS status Started for HL401617+5.p
17550.12/3363.10	% SZS status GaveUp for HL401617+5.p
17550.12/3363.10	% SZS status Ended for HL401617+5.p
17560.72/3364.39	% SZS status Started for HL401619+5.p
17560.72/3364.39	% SZS status GaveUp for HL401619+5.p
17560.72/3364.39	% SZS status Ended for HL401619+5.p
17563.89/3364.82	% SZS status Started for HL401620+4.p
17563.89/3364.82	% SZS status GaveUp for HL401620+4.p
17563.89/3364.82	% SZS status Ended for HL401620+4.p
17586.14/3367.68	% SZS status Started for HL401620+5.p
17586.14/3367.68	% SZS status GaveUp for HL401620+5.p
17586.14/3367.68	% SZS status Ended for HL401620+5.p
17598.40/3369.11	% SZS status Started for HL401621+4.p
17598.40/3369.11	% SZS status GaveUp for HL401621+4.p
17598.40/3369.11	% SZS status Ended for HL401621+4.p
17611.63/3370.80	% SZS status Started for HL401621+5.p
17611.63/3370.80	% SZS status GaveUp for HL401621+5.p
17611.63/3370.80	% SZS status Ended for HL401621+5.p
17615.37/3371.27	% SZS status Started for HL401622+5.p
17615.37/3371.27	% SZS status GaveUp for HL401622+5.p
17615.37/3371.27	% SZS status Ended for HL401622+5.p
17615.37/3371.27	% SZS status Started for HL401622+4.p
17615.37/3371.27	% SZS status GaveUp for HL401622+4.p
17615.37/3371.27	% SZS status Ended for HL401622+4.p
17615.95/3371.36	% SZS status Started for HL401623+4.p
17615.95/3371.36	% SZS status GaveUp for HL401623+4.p
17615.95/3371.36	% SZS status Ended for HL401623+4.p
17625.92/3372.60	% SZS status Started for HL401623+5.p
17625.92/3372.60	% SZS status GaveUp for HL401623+5.p
17625.92/3372.60	% SZS status Ended for HL401623+5.p
17630.68/3373.17	% SZS status Started for HL401624+4.p
17630.68/3373.17	% SZS status GaveUp for HL401624+4.p
17630.68/3373.17	% SZS status Ended for HL401624+4.p
17652.08/3375.85	% SZS status Started for HL401624+5.p
17652.08/3375.85	% SZS status GaveUp for HL401624+5.p
17652.08/3375.85	% SZS status Ended for HL401624+5.p
17665.52/3377.59	% SZS status Started for HL401625+4.p
17665.52/3377.59	% SZS status GaveUp for HL401625+4.p
17665.52/3377.59	% SZS status Ended for HL401625+4.p
17675.08/3378.96	% SZS status Started for HL401625+5.p
17675.08/3378.96	% SZS status GaveUp for HL401625+5.p
17675.08/3378.96	% SZS status Ended for HL401625+5.p
17680.05/3379.45	% SZS status Started for HL401626+5.p
17680.05/3379.45	% SZS status GaveUp for HL401626+5.p
17680.05/3379.45	% SZS status Ended for HL401626+5.p
17681.90/3379.56	% SZS status Started for HL401626+4.p
17681.90/3379.56	% SZS status GaveUp for HL401626+4.p
17681.90/3379.56	% SZS status Ended for HL401626+4.p
17682.94/3379.72	% SZS status Started for HL401627+4.p
17682.94/3379.72	% SZS status GaveUp for HL401627+4.p
17682.94/3379.72	% SZS status Ended for HL401627+4.p
17691.45/3380.80	% SZS status Started for HL401627+5.p
17691.45/3380.80	% SZS status GaveUp for HL401627+5.p
17691.45/3380.80	% SZS status Ended for HL401627+5.p
17697.39/3381.52	% SZS status Started for HL401628+4.p
17697.39/3381.52	% SZS status GaveUp for HL401628+4.p
17697.39/3381.52	% SZS status Ended for HL401628+4.p
17716.89/3384.03	% SZS status Started for HL401628+5.p
17716.89/3384.03	% SZS status GaveUp for HL401628+5.p
17716.89/3384.03	% SZS status Ended for HL401628+5.p
17732.05/3385.94	% SZS status Started for HL401629+4.p
17732.05/3385.94	% SZS status GaveUp for HL401629+4.p
17732.05/3385.94	% SZS status Ended for HL401629+4.p
17740.90/3387.18	% SZS status Started for HL401629+5.p
17740.90/3387.18	% SZS status GaveUp for HL401629+5.p
17740.90/3387.18	% SZS status Ended for HL401629+5.p
17745.93/3387.73	% SZS status Started for HL401631+5.p
17745.93/3387.73	% SZS status GaveUp for HL401631+5.p
17745.93/3387.73	% SZS status Ended for HL401631+5.p
17747.48/3387.86	% SZS status Started for HL401631+4.p
17747.48/3387.86	% SZS status GaveUp for HL401631+4.p
17747.48/3387.86	% SZS status Ended for HL401631+4.p
17748.38/3388.01	% SZS status Started for HL401632+4.p
17748.38/3388.01	% SZS status GaveUp for HL401632+4.p
17748.38/3388.01	% SZS status Ended for HL401632+4.p
17749.31/3388.32	% SZS status Started for HL401637+4.p
17749.31/3388.32	% SZS status Theorem for HL401637+4.p
17749.31/3388.32	% SZS status Ended for HL401637+4.p
17753.28/3388.56	% SZS status Started for HL401633+4.p
17753.28/3388.56	% SZS status Theorem for HL401633+4.p
17753.28/3388.56	% SZS status Ended for HL401633+4.p
17757.08/3389.04	% SZS status Started for HL401632+5.p
17757.08/3389.04	% SZS status GaveUp for HL401632+5.p
17757.08/3389.04	% SZS status Ended for HL401632+5.p
17782.80/3392.26	% SZS status Started for HL401633+5.p
17782.80/3392.26	% SZS status GaveUp for HL401633+5.p
17782.80/3392.26	% SZS status Ended for HL401633+5.p
17790.96/3393.28	% SZS status Started for HL401637+5.p
17790.96/3393.28	% SZS status Theorem for HL401637+5.p
17790.96/3393.28	% SZS status Ended for HL401637+5.p
17797.52/3394.25	% SZS status Started for HL401634+4.p
17797.52/3394.25	% SZS status GaveUp for HL401634+4.p
17797.52/3394.25	% SZS status Ended for HL401634+4.p
17806.72/3395.38	% SZS status Started for HL401634+5.p
17806.72/3395.38	% SZS status GaveUp for HL401634+5.p
17806.72/3395.38	% SZS status Ended for HL401634+5.p
17811.51/3396.04	% SZS status Started for HL401635+5.p
17811.51/3396.04	% SZS status GaveUp for HL401635+5.p
17811.51/3396.04	% SZS status Ended for HL401635+5.p
17811.51/3396.05	% SZS status Started for HL401635+4.p
17811.51/3396.05	% SZS status GaveUp for HL401635+4.p
17811.51/3396.05	% SZS status Ended for HL401635+4.p
17818.88/3396.85	% SZS status Started for HL401638+4.p
17818.88/3396.85	% SZS status GaveUp for HL401638+4.p
17818.88/3396.85	% SZS status Ended for HL401638+4.p
17822.80/3397.27	% SZS status Started for HL401638+5.p
17822.80/3397.27	% SZS status GaveUp for HL401638+5.p
17822.80/3397.27	% SZS status Ended for HL401638+5.p
17849.38/3400.66	% SZS status Started for HL401639+4.p
17849.38/3400.66	% SZS status GaveUp for HL401639+4.p
17849.38/3400.66	% SZS status Ended for HL401639+4.p
17856.12/3401.51	% SZS status Started for HL401639+5.p
17856.12/3401.51	% SZS status GaveUp for HL401639+5.p
17856.12/3401.51	% SZS status Ended for HL401639+5.p
17864.89/3402.64	% SZS status Started for HL401640+4.p
17864.89/3402.64	% SZS status GaveUp for HL401640+4.p
17864.89/3402.64	% SZS status Ended for HL401640+4.p
17872.16/3403.56	% SZS status Started for HL401640+5.p
17872.16/3403.56	% SZS status GaveUp for HL401640+5.p
17872.16/3403.56	% SZS status Ended for HL401640+5.p
17878.12/3404.29	% SZS status Started for HL401642+5.p
17878.12/3404.29	% SZS status GaveUp for HL401642+5.p
17878.12/3404.29	% SZS status Ended for HL401642+5.p
17878.12/3404.30	% SZS status Started for HL401642+4.p
17878.12/3404.30	% SZS status GaveUp for HL401642+4.p
17878.12/3404.30	% SZS status Ended for HL401642+4.p
17884.30/3405.20	% SZS status Started for HL401643+4.p
17884.30/3405.20	% SZS status GaveUp for HL401643+4.p
17884.30/3405.20	% SZS status Ended for HL401643+4.p
17887.72/3405.49	% SZS status Started for HL401643+5.p
17887.72/3405.49	% SZS status GaveUp for HL401643+5.p
17887.72/3405.49	% SZS status Ended for HL401643+5.p
17888.21/3405.59	% SZS status Started for HL401647+4.p
17888.21/3405.59	% SZS status Theorem for HL401647+4.p
17888.21/3405.59	% SZS status Ended for HL401647+4.p
17914.54/3408.98	% SZS status Started for HL401644+4.p
17914.54/3408.98	% SZS status GaveUp for HL401644+4.p
17914.54/3408.98	% SZS status Ended for HL401644+4.p
17921.40/3409.73	% SZS status Started for HL401644+5.p
17921.40/3409.73	% SZS status GaveUp for HL401644+5.p
17921.40/3409.73	% SZS status Ended for HL401644+5.p
17926.80/3410.36	% SZS status Started for HL401647+5.p
17926.80/3410.36	% SZS status Theorem for HL401647+5.p
17926.80/3410.36	% SZS status Ended for HL401647+5.p
17928.35/3410.59	% SZS status Started for HL401649+4.p
17928.35/3410.59	% SZS status Theorem for HL401649+4.p
17928.35/3410.59	% SZS status Ended for HL401649+4.p
17931.50/3411.02	% SZS status Started for HL401645+4.p
17931.50/3411.02	% SZS status GaveUp for HL401645+4.p
17931.50/3411.02	% SZS status Ended for HL401645+4.p
17937.47/3411.80	% SZS status Started for HL401645+5.p
17937.47/3411.80	% SZS status GaveUp for HL401645+5.p
17937.47/3411.80	% SZS status Ended for HL401645+5.p
17943.62/3412.48	% SZS status Started for HL401646+5.p
17943.62/3412.48	% SZS status GaveUp for HL401646+5.p
17943.62/3412.48	% SZS status Ended for HL401646+5.p
17944.88/3412.72	% SZS status Started for HL401646+4.p
17944.88/3412.72	% SZS status GaveUp for HL401646+4.p
17944.88/3412.72	% SZS status Ended for HL401646+4.p
17954.23/3413.91	% SZS status Started for HL401648+4.p
17954.23/3413.91	% SZS status GaveUp for HL401648+4.p
17954.23/3413.91	% SZS status Ended for HL401648+4.p
17980.29/3417.15	% SZS status Started for HL401648+5.p
17980.29/3417.15	% SZS status GaveUp for HL401648+5.p
17980.29/3417.15	% SZS status Ended for HL401648+5.p
17992.29/3418.59	% SZS status Started for HL401649+5.p
17992.29/3418.59	% SZS status GaveUp for HL401649+5.p
17992.29/3418.59	% SZS status Ended for HL401649+5.p
17994.63/3418.95	% SZS status Started for HL401650+4.p
17994.63/3418.95	% SZS status GaveUp for HL401650+4.p
17994.63/3418.95	% SZS status Ended for HL401650+4.p
17996.01/3419.08	% SZS status Started for HL401654+5.p
17996.01/3419.08	% SZS status Theorem for HL401654+5.p
17996.01/3419.08	% SZS status Ended for HL401654+5.p
17996.49/3419.17	% SZS status Started for HL401650+5.p
17996.49/3419.17	% SZS status GaveUp for HL401650+5.p
17996.49/3419.17	% SZS status Ended for HL401650+5.p
17996.99/3419.52	% SZS status Started for HL401654+4.p
17996.99/3419.52	% SZS status Theorem for HL401654+4.p
17996.99/3419.52	% SZS status Ended for HL401654+4.p
18001.50/3419.78	% SZS status Started for HL401656+5.p
18001.50/3419.78	% SZS status Theorem for HL401656+5.p
18001.50/3419.78	% SZS status Ended for HL401656+5.p
18002.42/3419.94	% SZS status Started for HL401656+4.p
18002.42/3419.94	% SZS status Theorem for HL401656+4.p
18002.42/3419.94	% SZS status Ended for HL401656+4.p
18002.83/3420.05	% SZS status Started for HL401658+4.p
18002.83/3420.05	% SZS status Theorem for HL401658+4.p
18002.83/3420.05	% SZS status Ended for HL401658+4.p
18004.15/3420.10	% SZS status Started for HL401651+4.p
18004.15/3420.10	% SZS status GaveUp for HL401651+4.p
18004.15/3420.10	% SZS status Ended for HL401651+4.p
18008.88/3420.70	% SZS status Started for HL401651+5.p
18008.88/3420.70	% SZS status GaveUp for HL401651+5.p
18008.88/3420.70	% SZS status Ended for HL401651+5.p
18009.87/3420.84	% SZS status Started for HL401658+5.p
18009.87/3420.84	% SZS status Theorem for HL401658+5.p
18009.87/3420.84	% SZS status Ended for HL401658+5.p
18010.67/3421.00	% SZS status Started for HL401660+4.p
18010.67/3421.00	% SZS status Theorem for HL401660+4.p
18010.67/3421.00	% SZS status Ended for HL401660+4.p
18011.52/3421.09	% SZS status Started for HL401652+4.p
18011.52/3421.09	% SZS status GaveUp for HL401652+4.p
18011.52/3421.09	% SZS status Ended for HL401652+4.p
18019.76/3422.11	% SZS status Started for HL401652+5.p
18019.76/3422.11	% SZS status GaveUp for HL401652+5.p
18019.76/3422.11	% SZS status Ended for HL401652+5.p
18050.44/3425.92	% SZS status Started for HL401660+5.p
18050.44/3425.92	% SZS status Theorem for HL401660+5.p
18050.44/3425.92	% SZS status Ended for HL401660+5.p
18053.33/3426.29	% SZS status Started for HL401657+4.p
18053.33/3426.29	% SZS status Theorem for HL401657+4.p
18053.33/3426.29	% SZS status Ended for HL401657+4.p
18062.73/3427.70	% SZS status Started for HL401657+5.p
18062.73/3427.70	% SZS status GaveUp for HL401657+5.p
18062.73/3427.70	% SZS status Ended for HL401657+5.p
18068.18/3428.26	% SZS status Started for HL401659+5.p
18068.18/3428.26	% SZS status GaveUp for HL401659+5.p
18068.18/3428.26	% SZS status Ended for HL401659+5.p
18070.61/3428.46	% SZS status Started for HL401665+4.p
18070.61/3428.46	% SZS status Theorem for HL401665+4.p
18070.61/3428.46	% SZS status Ended for HL401665+4.p
18070.96/3428.48	% SZS status Started for HL401659+4.p
18070.96/3428.48	% SZS status GaveUp for HL401659+4.p
18070.96/3428.48	% SZS status Ended for HL401659+4.p
18072.19/3428.81	% SZS status Started for HL401665+5.p
18072.19/3428.81	% SZS status Theorem for HL401665+5.p
18072.19/3428.81	% SZS status Ended for HL401665+5.p
18074.86/3429.01	% SZS status Started for HL401666+4.p
18074.86/3429.01	% SZS status Theorem for HL401666+4.p
18074.86/3429.01	% SZS status Ended for HL401666+4.p
18075.61/3429.11	% SZS status Started for HL401666+5.p
18075.61/3429.11	% SZS status Theorem for HL401666+5.p
18075.61/3429.11	% SZS status Ended for HL401666+5.p
18076.29/3429.26	% SZS status Started for HL401661+5.p
18076.29/3429.26	% SZS status GaveUp for HL401661+5.p
18076.29/3429.26	% SZS status Ended for HL401661+5.p
18076.70/3429.34	% SZS status Started for HL401661+4.p
18076.70/3429.34	% SZS status GaveUp for HL401661+4.p
18076.70/3429.34	% SZS status Ended for HL401661+4.p
18078.96/3429.51	% SZS status Started for HL401668+4.p
18078.96/3429.51	% SZS status Theorem for HL401668+4.p
18078.96/3429.51	% SZS status Ended for HL401668+4.p
18085.79/3430.40	% SZS status Started for HL401662+4.p
18085.79/3430.40	% SZS status GaveUp for HL401662+4.p
18085.79/3430.40	% SZS status Ended for HL401662+4.p
18115.16/3434.09	% SZS status Started for HL401662+5.p
18115.16/3434.09	% SZS status GaveUp for HL401662+5.p
18115.16/3434.09	% SZS status Ended for HL401662+5.p
18137.10/3436.80	% SZS status Started for HL401667+4.p
18137.10/3436.80	% SZS status GaveUp for HL401667+4.p
18137.10/3436.80	% SZS status Ended for HL401667+4.p
18137.94/3436.97	% SZS status Started for HL401667+5.p
18137.94/3436.97	% SZS status GaveUp for HL401667+5.p
18137.94/3436.97	% SZS status Ended for HL401667+5.p
18141.03/3437.30	% SZS status Started for HL401668+5.p
18141.03/3437.30	% SZS status GaveUp for HL401668+5.p
18141.03/3437.30	% SZS status Ended for HL401668+5.p
18142.00/3437.53	% SZS status Started for HL401669+4.p
18142.00/3437.53	% SZS status GaveUp for HL401669+4.p
18142.00/3437.53	% SZS status Ended for HL401669+4.p
18143.91/3437.65	% SZS status Started for HL401669+5.p
18143.91/3437.65	% SZS status GaveUp for HL401669+5.p
18143.91/3437.65	% SZS status Ended for HL401669+5.p
18145.46/3437.87	% SZS status Started for HL401670+4.p
18145.46/3437.87	% SZS status GaveUp for HL401670+4.p
18145.46/3437.87	% SZS status Ended for HL401670+4.p
18150.78/3438.57	% SZS status Started for HL401670+5.p
18150.78/3438.57	% SZS status GaveUp for HL401670+5.p
18150.78/3438.57	% SZS status Ended for HL401670+5.p
18162.57/3440.02	% SZS status Started for HL401674+4.p
18162.57/3440.02	% SZS status Theorem for HL401674+4.p
18162.57/3440.02	% SZS status Ended for HL401674+4.p
18181.85/3442.46	% SZS status Started for HL401671+4.p
18181.85/3442.46	% SZS status GaveUp for HL401671+4.p
18181.85/3442.46	% SZS status Ended for HL401671+4.p
18201.90/3444.95	% SZS status Started for HL401671+5.p
18201.90/3444.95	% SZS status GaveUp for HL401671+5.p
18201.90/3444.95	% SZS status Ended for HL401671+5.p
18204.95/3445.36	% SZS status Started for HL401672+4.p
18204.95/3445.36	% SZS status GaveUp for HL401672+4.p
18204.95/3445.36	% SZS status Ended for HL401672+4.p
18206.02/3445.49	% SZS status Started for HL401672+5.p
18206.02/3445.49	% SZS status GaveUp for HL401672+5.p
18206.02/3445.49	% SZS status Ended for HL401672+5.p
18207.75/3445.81	% SZS status Started for HL401673+4.p
18207.75/3445.81	% SZS status GaveUp for HL401673+4.p
18207.75/3445.81	% SZS status Ended for HL401673+4.p
18207.75/3445.82	% SZS status Started for HL401673+5.p
18207.75/3445.82	% SZS status GaveUp for HL401673+5.p
18207.75/3445.82	% SZS status Ended for HL401673+5.p
18216.12/3446.80	% SZS status Started for HL401674+5.p
18216.12/3446.80	% SZS status GaveUp for HL401674+5.p
18216.12/3446.80	% SZS status Ended for HL401674+5.p
18218.46/3447.04	% SZS status Started for HL401676+4.p
18218.46/3447.04	% SZS status Theorem for HL401676+4.p
18218.46/3447.04	% SZS status Ended for HL401676+4.p
18228.57/3448.34	% SZS status Started for HL401675+4.p
18228.57/3448.34	% SZS status GaveUp for HL401675+4.p
18228.57/3448.34	% SZS status Ended for HL401675+4.p
18246.97/3450.64	% SZS status Started for HL401675+5.p
18246.97/3450.64	% SZS status GaveUp for HL401675+5.p
18246.97/3450.64	% SZS status Ended for HL401675+5.p
18270.31/3453.61	% SZS status Started for HL401676+5.p
18270.31/3453.61	% SZS status GaveUp for HL401676+5.p
18270.31/3453.61	% SZS status Ended for HL401676+5.p
18271.79/3453.86	% SZS status Started for HL401677+4.p
18271.79/3453.86	% SZS status GaveUp for HL401677+4.p
18271.79/3453.86	% SZS status Ended for HL401677+4.p
18272.72/3454.01	% SZS status Started for HL401677+5.p
18272.72/3454.01	% SZS status GaveUp for HL401677+5.p
18272.72/3454.01	% SZS status Ended for HL401677+5.p
18275.42/3454.18	% SZS status Started for HL401678+4.p
18275.42/3454.18	% SZS status GaveUp for HL401678+4.p
18275.42/3454.18	% SZS status Ended for HL401678+4.p
18282.00/3455.02	% SZS status Started for HL401678+5.p
18282.00/3455.02	% SZS status GaveUp for HL401678+5.p
18282.00/3455.02	% SZS status Ended for HL401678+5.p
18284.66/3455.32	% SZS status Started for HL401679+4.p
18284.66/3455.32	% SZS status GaveUp for HL401679+4.p
18284.66/3455.32	% SZS status Ended for HL401679+4.p
18294.24/3456.54	% SZS status Started for HL401679+5.p
18294.24/3456.54	% SZS status GaveUp for HL401679+5.p
18294.24/3456.54	% SZS status Ended for HL401679+5.p
18312.66/3458.91	% SZS status Started for HL401680+4.p
18312.66/3458.91	% SZS status GaveUp for HL401680+4.p
18312.66/3458.91	% SZS status Ended for HL401680+4.p
18335.54/3461.82	% SZS status Started for HL401680+5.p
18335.54/3461.82	% SZS status GaveUp for HL401680+5.p
18335.54/3461.82	% SZS status Ended for HL401680+5.p
18338.86/3462.19	% SZS status Started for HL401681+4.p
18338.86/3462.19	% SZS status GaveUp for HL401681+4.p
18338.86/3462.19	% SZS status Ended for HL401681+4.p
18338.86/3462.19	% SZS status Started for HL401681+5.p
18338.86/3462.19	% SZS status GaveUp for HL401681+5.p
18338.86/3462.19	% SZS status Ended for HL401681+5.p
18341.91/3462.54	% SZS status Started for HL401682+4.p
18341.91/3462.54	% SZS status GaveUp for HL401682+4.p
18341.91/3462.54	% SZS status Ended for HL401682+4.p
18347.32/3463.24	% SZS status Started for HL401682+5.p
18347.32/3463.24	% SZS status GaveUp for HL401682+5.p
18347.32/3463.24	% SZS status Ended for HL401682+5.p
18350.25/3463.62	% SZS status Started for HL401683+4.p
18350.25/3463.62	% SZS status GaveUp for HL401683+4.p
18350.25/3463.62	% SZS status Ended for HL401683+4.p
18358.72/3464.71	% SZS status Started for HL401683+5.p
18358.72/3464.71	% SZS status GaveUp for HL401683+5.p
18358.72/3464.71	% SZS status Ended for HL401683+5.p
18364.05/3465.36	% SZS status Started for HL401687+4.p
18364.05/3465.36	% SZS status Theorem for HL401687+4.p
18364.05/3465.36	% SZS status Ended for HL401687+4.p
18378.18/3467.18	% SZS status Started for HL401685+4.p
18378.18/3467.18	% SZS status GaveUp for HL401685+4.p
18378.18/3467.18	% SZS status Ended for HL401685+4.p
18401.62/3470.13	% SZS status Started for HL401685+5.p
18401.62/3470.13	% SZS status GaveUp for HL401685+5.p
18401.62/3470.13	% SZS status Ended for HL401685+5.p
18404.17/3470.46	% SZS status Started for HL401686+5.p
18404.17/3470.46	% SZS status GaveUp for HL401686+5.p
18404.17/3470.46	% SZS status Ended for HL401686+5.p
18405.23/3470.63	% SZS status Started for HL401686+4.p
18405.23/3470.63	% SZS status GaveUp for HL401686+4.p
18405.23/3470.63	% SZS status Ended for HL401686+4.p
18412.16/3471.42	% SZS status Started for HL401687+5.p
18412.16/3471.42	% SZS status GaveUp for HL401687+5.p
18412.16/3471.42	% SZS status Ended for HL401687+5.p
18416.27/3471.92	% SZS status Started for HL401688+4.p
18416.27/3471.92	% SZS status GaveUp for HL401688+4.p
18416.27/3471.92	% SZS status Ended for HL401688+4.p
18423.44/3472.95	% SZS status Started for HL401688+5.p
18423.44/3472.95	% SZS status GaveUp for HL401688+5.p
18423.44/3472.95	% SZS status Ended for HL401688+5.p
18430.01/3473.67	% SZS status Started for HL401689+4.p
18430.01/3473.67	% SZS status GaveUp for HL401689+4.p
18430.01/3473.67	% SZS status Ended for HL401689+4.p
18443.98/3475.43	% SZS status Started for HL401689+5.p
18443.98/3475.43	% SZS status GaveUp for HL401689+5.p
18443.98/3475.43	% SZS status Ended for HL401689+5.p
18467.92/3478.58	% SZS status Started for HL401690+4.p
18467.92/3478.58	% SZS status GaveUp for HL401690+4.p
18467.92/3478.58	% SZS status Ended for HL401690+4.p
18467.92/3478.63	% SZS status Started for HL401690+5.p
18467.92/3478.63	% SZS status GaveUp for HL401690+5.p
18467.92/3478.63	% SZS status Ended for HL401690+5.p
18472.58/3479.14	% SZS status Started for HL401691+4.p
18472.58/3479.14	% SZS status GaveUp for HL401691+4.p
18472.58/3479.14	% SZS status Ended for HL401691+4.p
18477.26/3479.64	% SZS status Started for HL401691+5.p
18477.26/3479.64	% SZS status GaveUp for HL401691+5.p
18477.26/3479.64	% SZS status Ended for HL401691+5.p
18481.75/3480.24	% SZS status Started for HL401692+4.p
18481.75/3480.24	% SZS status GaveUp for HL401692+4.p
18481.75/3480.24	% SZS status Ended for HL401692+4.p
18489.65/3481.16	% SZS status Started for HL401692+5.p
18489.65/3481.16	% SZS status GaveUp for HL401692+5.p
18489.65/3481.16	% SZS status Ended for HL401692+5.p
18495.43/3481.96	% SZS status Started for HL401693+4.p
18495.43/3481.96	% SZS status GaveUp for HL401693+4.p
18495.43/3481.96	% SZS status Ended for HL401693+4.p
18500.29/3482.57	% SZS status Started for HL401697+4.p
18500.29/3482.57	% SZS status Theorem for HL401697+4.p
18500.29/3482.57	% SZS status Ended for HL401697+4.p
18507.92/3483.47	% SZS status Started for HL401695+4.p
18507.92/3483.47	% SZS status Theorem for HL401695+4.p
18507.92/3483.47	% SZS status Ended for HL401695+4.p
18508.77/3483.60	% SZS status Started for HL401693+5.p
18508.77/3483.60	% SZS status GaveUp for HL401693+5.p
18508.77/3483.60	% SZS status Ended for HL401693+5.p
18533.73/3486.79	% SZS status Started for HL401694+5.p
18533.73/3486.79	% SZS status GaveUp for HL401694+5.p
18533.73/3486.79	% SZS status Ended for HL401694+5.p
18534.18/3486.89	% SZS status Started for HL401694+4.p
18534.18/3486.89	% SZS status GaveUp for HL401694+4.p
18534.18/3486.89	% SZS status Ended for HL401694+4.p
18542.12/3487.82	% SZS status Started for HL401695+5.p
18542.12/3487.82	% SZS status GaveUp for HL401695+5.p
18542.12/3487.82	% SZS status Ended for HL401695+5.p
18547.35/3488.44	% SZS status Started for HL401697+5.p
18547.35/3488.44	% SZS status Theorem for HL401697+5.p
18547.35/3488.44	% SZS status Ended for HL401697+5.p
18560.45/3490.27	% SZS status Started for HL401698+4.p
18560.45/3490.27	% SZS status GaveUp for HL401698+4.p
18560.45/3490.27	% SZS status Ended for HL401698+4.p
18564.81/3490.72	% SZS status Started for HL401698+5.p
18564.81/3490.72	% SZS status GaveUp for HL401698+5.p
18564.81/3490.72	% SZS status Ended for HL401698+5.p
18573.53/3491.80	% SZS status Started for HL401699+5.p
18573.53/3491.80	% SZS status GaveUp for HL401699+5.p
18573.53/3491.80	% SZS status Ended for HL401699+5.p
18574.28/3491.92	% SZS status Started for HL401699+4.p
18574.28/3491.92	% SZS status GaveUp for HL401699+4.p
18574.28/3491.92	% SZS status Ended for HL401699+4.p
18600.07/3495.09	% SZS status Started for HL401700+5.p
18600.07/3495.09	% SZS status GaveUp for HL401700+5.p
18600.07/3495.09	% SZS status Ended for HL401700+5.p
18600.07/3495.13	% SZS status Started for HL401700+4.p
18600.07/3495.13	% SZS status GaveUp for HL401700+4.p
18600.07/3495.13	% SZS status Ended for HL401700+4.p
18608.35/3496.15	% SZS status Started for HL401701+4.p
18608.35/3496.15	% SZS status GaveUp for HL401701+4.p
18608.35/3496.15	% SZS status Ended for HL401701+4.p
18611.96/3496.61	% SZS status Started for HL401701+5.p
18611.96/3496.61	% SZS status GaveUp for HL401701+5.p
18611.96/3496.61	% SZS status Ended for HL401701+5.p
18626.42/3498.54	% SZS status Started for HL401702+4.p
18626.42/3498.54	% SZS status GaveUp for HL401702+4.p
18626.42/3498.54	% SZS status Ended for HL401702+4.p
18630.41/3498.98	% SZS status Started for HL401702+5.p
18630.41/3498.98	% SZS status GaveUp for HL401702+5.p
18630.41/3498.98	% SZS status Ended for HL401702+5.p
18640.77/3500.23	% SZS status Started for HL401703+5.p
18640.77/3500.23	% SZS status GaveUp for HL401703+5.p
18640.77/3500.23	% SZS status Ended for HL401703+5.p
18641.25/3500.31	% SZS status Started for HL401703+4.p
18641.25/3500.31	% SZS status GaveUp for HL401703+4.p
18641.25/3500.31	% SZS status Ended for HL401703+4.p
18642.71/3500.47	% SZS status Started for HL401706+4.p
18642.71/3500.47	% SZS status Theorem for HL401706+4.p
18642.71/3500.47	% SZS status Ended for HL401706+4.p
18665.55/3503.31	% SZS status Started for HL401704+5.p
18665.55/3503.31	% SZS status GaveUp for HL401704+5.p
18665.55/3503.31	% SZS status Ended for HL401704+5.p
18666.12/3503.38	% SZS status Started for HL401704+4.p
18666.12/3503.38	% SZS status GaveUp for HL401704+4.p
18666.12/3503.38	% SZS status Ended for HL401704+4.p
18675.32/3504.62	% SZS status Started for HL401705+4.p
18675.32/3504.62	% SZS status GaveUp for HL401705+4.p
18675.32/3504.62	% SZS status Ended for HL401705+4.p
18676.05/3504.84	% SZS status Started for HL401705+5.p
18676.05/3504.84	% SZS status GaveUp for HL401705+5.p
18676.05/3504.84	% SZS status Ended for HL401705+5.p
18696.38/3507.26	% SZS status Started for HL401706+5.p
18696.38/3507.26	% SZS status GaveUp for HL401706+5.p
18696.38/3507.26	% SZS status Ended for HL401706+5.p
18706.69/3508.52	% SZS status Started for HL401707+5.p
18706.69/3508.52	% SZS status GaveUp for HL401707+5.p
18706.69/3508.52	% SZS status Ended for HL401707+5.p
18706.69/3508.56	% SZS status Started for HL401707+4.p
18706.69/3508.56	% SZS status GaveUp for HL401707+4.p
18706.69/3508.56	% SZS status Ended for HL401707+4.p
18708.90/3508.82	% SZS status Started for HL401710+4.p
18708.90/3508.82	% SZS status GaveUp for HL401710+4.p
18708.90/3508.82	% SZS status Ended for HL401710+4.p
18730.79/3511.65	% SZS status Started for HL401711+4.p
18730.79/3511.65	% SZS status GaveUp for HL401711+4.p
18730.79/3511.65	% SZS status Ended for HL401711+4.p
18730.79/3511.68	% SZS status Started for HL401710+5.p
18730.79/3511.68	% SZS status GaveUp for HL401710+5.p
18730.79/3511.68	% SZS status Ended for HL401710+5.p
18740.33/3512.87	% SZS status Started for HL401711+5.p
18740.33/3512.87	% SZS status GaveUp for HL401711+5.p
18740.33/3512.87	% SZS status Ended for HL401711+5.p
18742.90/3513.16	% SZS status Started for HL401713+4.p
18742.90/3513.16	% SZS status GaveUp for HL401713+4.p
18742.90/3513.16	% SZS status Ended for HL401713+4.p
18760.32/3515.47	% SZS status Started for HL401713+5.p
18760.32/3515.47	% SZS status GaveUp for HL401713+5.p
18760.32/3515.47	% SZS status Ended for HL401713+5.p
18771.75/3516.76	% SZS status Started for HL401715+5.p
18771.75/3516.76	% SZS status GaveUp for HL401715+5.p
18771.75/3516.76	% SZS status Ended for HL401715+5.p
18771.75/3516.80	% SZS status Started for HL401715+4.p
18771.75/3516.80	% SZS status GaveUp for HL401715+4.p
18771.75/3516.80	% SZS status Ended for HL401715+4.p
18775.55/3517.28	% SZS status Started for HL401716+4.p
18775.55/3517.28	% SZS status GaveUp for HL401716+4.p
18775.55/3517.28	% SZS status Ended for HL401716+4.p
18795.82/3519.90	% SZS status Started for HL401716+5.p
18795.82/3519.90	% SZS status GaveUp for HL401716+5.p
18795.82/3519.90	% SZS status Ended for HL401716+5.p
18798.42/3520.14	% SZS status Started for HL401717+4.p
18798.42/3520.14	% SZS status GaveUp for HL401717+4.p
18798.42/3520.14	% SZS status Ended for HL401717+4.p
18805.94/3521.07	% SZS status Started for HL401717+5.p
18805.94/3521.07	% SZS status GaveUp for HL401717+5.p
18805.94/3521.07	% SZS status Ended for HL401717+5.p
18811.55/3521.72	% SZS status Started for HL401718+4.p
18811.55/3521.72	% SZS status GaveUp for HL401718+4.p
18811.55/3521.72	% SZS status Ended for HL401718+4.p
18826.66/3523.73	% SZS status Started for HL401718+5.p
18826.66/3523.73	% SZS status GaveUp for HL401718+5.p
18826.66/3523.73	% SZS status Ended for HL401718+5.p
18836.36/3525.02	% SZS status Started for HL401721+5.p
18836.36/3525.02	% SZS status GaveUp for HL401721+5.p
18836.36/3525.02	% SZS status Ended for HL401721+5.p
18836.72/3525.10	% SZS status Started for HL401721+4.p
18836.72/3525.10	% SZS status GaveUp for HL401721+4.p
18836.72/3525.10	% SZS status Ended for HL401721+4.p
18847.61/3525.59	% SZS status Started for HL401722+4.p
18847.61/3525.59	% SZS status GaveUp for HL401722+4.p
18847.61/3525.59	% SZS status Ended for HL401722+4.p
18857.02/3526.65	% SZS status Started for HL401726+4.p
18857.02/3526.65	% SZS status Theorem for HL401726+4.p
18857.02/3526.65	% SZS status Ended for HL401726+4.p
18862.64/3527.52	% SZS status Started for HL401724+4.p
18862.64/3527.52	% SZS status Theorem for HL401724+4.p
18862.64/3527.52	% SZS status Ended for HL401724+4.p
18866.34/3527.89	% SZS status Started for HL401729+4.p
18866.34/3527.89	% SZS status Theorem for HL401729+4.p
18866.34/3527.89	% SZS status Ended for HL401729+4.p
18867.70/3528.05	% SZS status Started for HL401722+5.p
18867.70/3528.05	% SZS status GaveUp for HL401722+5.p
18867.70/3528.05	% SZS status Ended for HL401722+5.p
18870.80/3528.50	% SZS status Started for HL401723+4.p
18870.80/3528.50	% SZS status GaveUp for HL401723+4.p
18870.80/3528.50	% SZS status Ended for HL401723+4.p
18878.32/3529.32	% SZS status Started for HL401723+5.p
18878.32/3529.32	% SZS status GaveUp for HL401723+5.p
18878.32/3529.32	% SZS status Ended for HL401723+5.p
18898.48/3531.93	% SZS status Started for HL401724+5.p
18898.48/3531.93	% SZS status GaveUp for HL401724+5.p
18898.48/3531.93	% SZS status Ended for HL401724+5.p
18909.18/3533.26	% SZS status Started for HL401725+5.p
18909.18/3533.26	% SZS status GaveUp for HL401725+5.p
18909.18/3533.26	% SZS status Ended for HL401725+5.p
18910.09/3533.32	% SZS status Started for HL401729+5.p
18910.09/3533.32	% SZS status Theorem for HL401729+5.p
18910.09/3533.32	% SZS status Ended for HL401729+5.p
18910.38/3533.35	% SZS status Started for HL401725+4.p
18910.38/3533.35	% SZS status GaveUp for HL401725+4.p
18910.38/3533.35	% SZS status Ended for HL401725+4.p
18922.91/3534.92	% SZS status Started for HL401726+5.p
18922.91/3534.92	% SZS status GaveUp for HL401726+5.p
18922.91/3534.92	% SZS status Ended for HL401726+5.p
18933.39/3536.33	% SZS status Started for HL401730+4.p
18933.39/3536.33	% SZS status GaveUp for HL401730+4.p
18933.39/3536.33	% SZS status Ended for HL401730+4.p
18937.18/3536.78	% SZS status Started for HL401730+5.p
18937.18/3536.78	% SZS status GaveUp for HL401730+5.p
18937.18/3536.78	% SZS status Ended for HL401730+5.p
18944.09/3537.64	% SZS status Started for HL401731+4.p
18944.09/3537.64	% SZS status GaveUp for HL401731+4.p
18944.09/3537.64	% SZS status Ended for HL401731+4.p
18964.07/3540.11	% SZS status Started for HL401731+5.p
18964.07/3540.11	% SZS status GaveUp for HL401731+5.p
18964.07/3540.11	% SZS status Ended for HL401731+5.p
18974.78/3541.49	% SZS status Started for HL401732+5.p
18974.78/3541.49	% SZS status GaveUp for HL401732+5.p
18974.78/3541.49	% SZS status Ended for HL401732+5.p
18975.37/3541.55	% SZS status Started for HL401732+4.p
18975.37/3541.55	% SZS status GaveUp for HL401732+4.p
18975.37/3541.55	% SZS status Ended for HL401732+4.p
18976.54/3541.72	% SZS status Started for HL401733+4.p
18976.54/3541.72	% SZS status GaveUp for HL401733+4.p
18976.54/3541.72	% SZS status Ended for HL401733+4.p
18986.40/3543.09	% SZS status Started for HL401733+5.p
18986.40/3543.09	% SZS status GaveUp for HL401733+5.p
18986.40/3543.09	% SZS status Ended for HL401733+5.p
18999.38/3544.60	% SZS status Started for HL401734+4.p
18999.38/3544.60	% SZS status GaveUp for HL401734+4.p
18999.38/3544.60	% SZS status Ended for HL401734+4.p
19002.03/3544.95	% SZS status Started for HL401734+5.p
19002.03/3544.95	% SZS status GaveUp for HL401734+5.p
19002.03/3544.95	% SZS status Ended for HL401734+5.p
19012.41/3546.25	% SZS status Started for HL401735+4.p
19012.41/3546.25	% SZS status GaveUp for HL401735+4.p
19012.41/3546.25	% SZS status Ended for HL401735+4.p
19029.24/3548.35	% SZS status Started for HL401735+5.p
19029.24/3548.35	% SZS status GaveUp for HL401735+5.p
19029.24/3548.35	% SZS status Ended for HL401735+5.p
19040.99/3549.78	% SZS status Started for HL401736+5.p
19040.99/3549.78	% SZS status GaveUp for HL401736+5.p
19040.99/3549.78	% SZS status Ended for HL401736+5.p
19041.97/3549.93	% SZS status Started for HL401736+4.p
19041.97/3549.93	% SZS status GaveUp for HL401736+4.p
19041.97/3549.93	% SZS status Ended for HL401736+4.p
19042.82/3550.15	% SZS status Started for HL401737+4.p
19042.82/3550.15	% SZS status GaveUp for HL401737+4.p
19042.82/3550.15	% SZS status Ended for HL401737+4.p
19051.79/3551.25	% SZS status Started for HL401737+5.p
19051.79/3551.25	% SZS status GaveUp for HL401737+5.p
19051.79/3551.25	% SZS status Ended for HL401737+5.p
19064.88/3552.94	% SZS status Started for HL401738+4.p
19064.88/3552.94	% SZS status GaveUp for HL401738+4.p
19064.88/3552.94	% SZS status Ended for HL401738+4.p
19067.80/3553.18	% SZS status Started for HL401738+5.p
19067.80/3553.18	% SZS status GaveUp for HL401738+5.p
19067.80/3553.18	% SZS status Ended for HL401738+5.p
19078.19/3554.64	% SZS status Started for HL401739+4.p
19078.19/3554.64	% SZS status GaveUp for HL401739+4.p
19078.19/3554.64	% SZS status Ended for HL401739+4.p
19094.39/3556.57	% SZS status Started for HL401739+5.p
19094.39/3556.57	% SZS status GaveUp for HL401739+5.p
19094.39/3556.57	% SZS status Ended for HL401739+5.p
19106.59/3558.09	% SZS status Started for HL401740+4.p
19106.59/3558.09	% SZS status GaveUp for HL401740+4.p
19106.59/3558.09	% SZS status Ended for HL401740+4.p
19107.24/3558.18	% SZS status Started for HL401740+5.p
19107.24/3558.18	% SZS status GaveUp for HL401740+5.p
19107.24/3558.18	% SZS status Ended for HL401740+5.p
19111.77/3558.73	% SZS status Started for HL401741+4.p
19111.77/3558.73	% SZS status GaveUp for HL401741+4.p
19111.77/3558.73	% SZS status Ended for HL401741+4.p
19116.56/3559.42	% SZS status Started for HL401741+5.p
19116.56/3559.42	% SZS status GaveUp for HL401741+5.p
19116.56/3559.42	% SZS status Ended for HL401741+5.p
19130.62/3561.24	% SZS status Started for HL401742+4.p
19130.62/3561.24	% SZS status GaveUp for HL401742+4.p
19130.62/3561.24	% SZS status Ended for HL401742+4.p
19132.71/3561.37	% SZS status Started for HL401742+5.p
19132.71/3561.37	% SZS status GaveUp for HL401742+5.p
19132.71/3561.37	% SZS status Ended for HL401742+5.p
19145.55/3563.00	% SZS status Started for HL401743+4.p
19145.55/3563.00	% SZS status GaveUp for HL401743+4.p
19145.55/3563.00	% SZS status Ended for HL401743+4.p
19147.43/3563.30	% SZS status Started for HL401748+4.p
19147.43/3563.30	% SZS status Theorem for HL401748+4.p
19147.43/3563.30	% SZS status Ended for HL401748+4.p
19149.75/3563.57	% SZS status Started for HL401748+5.p
19149.75/3563.57	% SZS status Theorem for HL401748+5.p
19149.75/3563.57	% SZS status Ended for HL401748+5.p
19160.06/3564.92	% SZS status Started for HL401743+5.p
19160.06/3564.92	% SZS status GaveUp for HL401743+5.p
19160.06/3564.92	% SZS status Ended for HL401743+5.p
19171.78/3566.35	% SZS status Started for HL401745+5.p
19171.78/3566.35	% SZS status GaveUp for HL401745+5.p
19171.78/3566.35	% SZS status Ended for HL401745+5.p
19172.60/3566.38	% SZS status Started for HL401745+4.p
19172.60/3566.38	% SZS status GaveUp for HL401745+4.p
19172.60/3566.38	% SZS status Ended for HL401745+4.p
19178.15/3567.15	% SZS status Started for HL401746+4.p
19178.15/3567.15	% SZS status GaveUp for HL401746+4.p
19178.15/3567.15	% SZS status Ended for HL401746+4.p
19182.39/3567.67	% SZS status Started for HL401746+5.p
19182.39/3567.67	% SZS status GaveUp for HL401746+5.p
19182.39/3567.67	% SZS status Ended for HL401746+5.p
19197.43/3569.54	% SZS status Started for HL401747+4.p
19197.43/3569.54	% SZS status GaveUp for HL401747+4.p
19197.43/3569.54	% SZS status Ended for HL401747+4.p
19198.72/3569.69	% SZS status Started for HL401747+5.p
19198.72/3569.69	% SZS status GaveUp for HL401747+5.p
19198.72/3569.69	% SZS status Ended for HL401747+5.p
19216.17/3571.93	% SZS status Started for HL401750+4.p
19216.17/3571.93	% SZS status GaveUp for HL401750+4.p
19216.17/3571.93	% SZS status Ended for HL401750+4.p
19225.62/3573.09	% SZS status Started for HL401750+5.p
19225.62/3573.09	% SZS status GaveUp for HL401750+5.p
19225.62/3573.09	% SZS status Ended for HL401750+5.p
19226.31/3573.24	% SZS status Started for HL401755+4.p
19226.31/3573.24	% SZS status Theorem for HL401755+4.p
19226.31/3573.24	% SZS status Ended for HL401755+4.p
19226.77/3573.33	% SZS status Started for HL401755+5.p
19226.77/3573.33	% SZS status Theorem for HL401755+5.p
19226.77/3573.33	% SZS status Ended for HL401755+5.p
19238.14/3574.66	% SZS status Started for HL401752+5.p
19238.14/3574.66	% SZS status GaveUp for HL401752+5.p
19238.14/3574.66	% SZS status Ended for HL401752+5.p
19238.76/3574.78	% SZS status Started for HL401752+4.p
19238.76/3574.78	% SZS status GaveUp for HL401752+4.p
19238.76/3574.78	% SZS status Ended for HL401752+4.p
19244.45/3575.47	% SZS status Started for HL401753+4.p
19244.45/3575.47	% SZS status GaveUp for HL401753+4.p
19244.45/3575.47	% SZS status Ended for HL401753+4.p
19247.44/3575.88	% SZS status Started for HL401753+5.p
19247.44/3575.88	% SZS status GaveUp for HL401753+5.p
19247.44/3575.88	% SZS status Ended for HL401753+5.p
19262.78/3577.86	% SZS status Started for HL401754+4.p
19262.78/3577.86	% SZS status GaveUp for HL401754+4.p
19262.78/3577.86	% SZS status Ended for HL401754+4.p
19264.27/3578.00	% SZS status Started for HL401758+4.p
19264.27/3578.00	% SZS status Theorem for HL401758+4.p
19264.27/3578.00	% SZS status Ended for HL401758+4.p
19264.27/3578.01	% SZS status Started for HL401754+5.p
19264.27/3578.01	% SZS status GaveUp for HL401754+5.p
19264.27/3578.01	% SZS status Ended for HL401754+5.p
19269.79/3578.69	% SZS status Started for HL401759+5.p
19269.79/3578.69	% SZS status Theorem for HL401759+5.p
19269.79/3578.69	% SZS status Ended for HL401759+5.p
19286.42/3580.76	% SZS status Started for HL401759+4.p
19286.42/3580.76	% SZS status Theorem for HL401759+4.p
19286.42/3580.76	% SZS status Ended for HL401759+4.p
19292.44/3581.51	% SZS status Started for HL401756+4.p
19292.44/3581.51	% SZS status GaveUp for HL401756+4.p
19292.44/3581.51	% SZS status Ended for HL401756+4.p
19293.03/3581.57	% SZS status Started for HL401756+5.p
19293.03/3581.57	% SZS status GaveUp for HL401756+5.p
19293.03/3581.57	% SZS status Ended for HL401756+5.p
19302.47/3582.77	% SZS status Started for HL401758+5.p
19302.47/3582.77	% SZS status Theorem for HL401758+5.p
19302.47/3582.77	% SZS status Ended for HL401758+5.p
19303.71/3582.96	% SZS status Started for HL401757+5.p
19303.71/3582.96	% SZS status GaveUp for HL401757+5.p
19303.71/3582.96	% SZS status Ended for HL401757+5.p
19304.33/3583.07	% SZS status Started for HL401757+4.p
19304.33/3583.07	% SZS status GaveUp for HL401757+4.p
19304.33/3583.07	% SZS status Ended for HL401757+4.p
19329.04/3586.29	% SZS status Started for HL401760+4.p
19329.04/3586.29	% SZS status GaveUp for HL401760+4.p
19329.04/3586.29	% SZS status Ended for HL401760+4.p
19335.94/3587.02	% SZS status Started for HL401760+5.p
19335.94/3587.02	% SZS status GaveUp for HL401760+5.p
19335.94/3587.02	% SZS status Ended for HL401760+5.p
19353.29/3589.20	% SZS status Started for HL401761+4.p
19353.29/3589.20	% SZS status GaveUp for HL401761+4.p
19353.29/3589.20	% SZS status Ended for HL401761+4.p
19355.97/3589.73	% SZS status Started for HL401761+5.p
19355.97/3589.73	% SZS status GaveUp for HL401761+5.p
19355.97/3589.73	% SZS status Ended for HL401761+5.p
19359.27/3589.98	% SZS status Started for HL401762+4.p
19359.27/3589.98	% SZS status GaveUp for HL401762+4.p
19359.27/3589.98	% SZS status Ended for HL401762+4.p
19367.31/3590.95	% SZS status Started for HL401762+5.p
19367.31/3590.95	% SZS status GaveUp for HL401762+5.p
19367.31/3590.95	% SZS status Ended for HL401762+5.p
19369.45/3591.30	% SZS status Started for HL401764+4.p
19369.45/3591.30	% SZS status GaveUp for HL401764+4.p
19369.45/3591.30	% SZS status Ended for HL401764+4.p
19370.23/3591.39	% SZS status Started for HL401764+5.p
19370.23/3591.39	% SZS status GaveUp for HL401764+5.p
19370.23/3591.39	% SZS status Ended for HL401764+5.p
19396.39/3594.69	% SZS status Started for HL401766+4.p
19396.39/3594.69	% SZS status GaveUp for HL401766+4.p
19396.39/3594.69	% SZS status Ended for HL401766+4.p
19400.57/3595.19	% SZS status Started for HL401766+5.p
19400.57/3595.19	% SZS status GaveUp for HL401766+5.p
19400.57/3595.19	% SZS status Ended for HL401766+5.p
19419.53/3597.57	% SZS status Started for HL401767+4.p
19419.53/3597.57	% SZS status GaveUp for HL401767+4.p
19419.53/3597.57	% SZS status Ended for HL401767+4.p
19422.63/3597.92	% SZS status Started for HL401767+5.p
19422.63/3597.92	% SZS status GaveUp for HL401767+5.p
19422.63/3597.92	% SZS status Ended for HL401767+5.p
19427.30/3598.55	% SZS status Started for HL401768+4.p
19427.30/3598.55	% SZS status GaveUp for HL401768+4.p
19427.30/3598.55	% SZS status Ended for HL401768+4.p
19431.99/3599.12	% SZS status Started for HL401768+5.p
19431.99/3599.12	% SZS status GaveUp for HL401768+5.p
19431.99/3599.12	% SZS status Ended for HL401768+5.p
19436.59/3599.63	% SZS status Started for HL401769+5.p
19436.59/3599.63	% SZS status GaveUp for HL401769+5.p
19436.59/3599.63	% SZS status Ended for HL401769+5.p
19436.59/3599.66	% SZS status Started for HL401771+4.p
19436.59/3599.66	% SZS status Theorem for HL401771+4.p
19436.59/3599.66	% SZS status Ended for HL401771+4.p
19437.11/3599.72	% SZS status Started for HL401769+4.p
19437.11/3599.72	% SZS status GaveUp for HL401769+4.p
19437.11/3599.72	% SZS status Ended for HL401769+4.p
19457.76/3602.30	% SZS status Started for HL401773+4.p
19457.76/3602.30	% SZS status Theorem for HL401773+4.p
19457.76/3602.30	% SZS status Ended for HL401773+4.p
19463.14/3603.04	% SZS status Started for HL401770+4.p
19463.14/3603.04	% SZS status GaveUp for HL401770+4.p
19463.14/3603.04	% SZS status Ended for HL401770+4.p
19464.18/3603.37	% SZS status Started for HL401770+5.p
19464.18/3603.37	% SZS status GaveUp for HL401770+5.p
19464.18/3603.37	% SZS status Ended for HL401770+5.p
19485.23/3605.75	% SZS status Started for HL401772+4.p
19485.23/3605.75	% SZS status Theorem for HL401772+4.p
19485.23/3605.75	% SZS status Ended for HL401772+4.p
19487.52/3606.17	% SZS status Started for HL401771+5.p
19487.52/3606.17	% SZS status GaveUp for HL401771+5.p
19487.52/3606.17	% SZS status Ended for HL401771+5.p
19497.89/3607.36	% SZS status Started for HL401772+5.p
19497.89/3607.36	% SZS status GaveUp for HL401772+5.p
19497.89/3607.36	% SZS status Ended for HL401772+5.p
19500.15/3607.83	% SZS status Started for HL401773+5.p
19500.15/3607.83	% SZS status GaveUp for HL401773+5.p
19500.15/3607.83	% SZS status Ended for HL401773+5.p
19503.37/3608.07	% SZS status Started for HL401774+4.p
19503.37/3608.07	% SZS status GaveUp for HL401774+4.p
19503.37/3608.07	% SZS status Ended for HL401774+4.p
19522.26/3610.49	% SZS status Started for HL401774+5.p
19522.26/3610.49	% SZS status GaveUp for HL401774+5.p
19522.26/3610.49	% SZS status Ended for HL401774+5.p
19530.29/3611.44	% SZS status Started for HL401775+4.p
19530.29/3611.44	% SZS status GaveUp for HL401775+4.p
19530.29/3611.44	% SZS status Ended for HL401775+4.p
19531.14/3611.59	% SZS status Started for HL401775+5.p
19531.14/3611.59	% SZS status GaveUp for HL401775+5.p
19531.14/3611.59	% SZS status Ended for HL401775+5.p
19551.84/3614.19	% SZS status Started for HL401776+4.p
19551.84/3614.19	% SZS status GaveUp for HL401776+4.p
19551.84/3614.19	% SZS status Ended for HL401776+4.p
19553.61/3614.37	% SZS status Started for HL401776+5.p
19553.61/3614.37	% SZS status GaveUp for HL401776+5.p
19553.61/3614.37	% SZS status Ended for HL401776+5.p
19564.24/3615.70	% SZS status Started for HL401777+4.p
19564.24/3615.70	% SZS status GaveUp for HL401777+4.p
19564.24/3615.70	% SZS status Ended for HL401777+4.p
19565.35/3616.01	% SZS status Started for HL401777+5.p
19565.35/3616.01	% SZS status GaveUp for HL401777+5.p
19565.35/3616.01	% SZS status Ended for HL401777+5.p
19569.74/3616.40	% SZS status Started for HL401778+4.p
19569.74/3616.40	% SZS status GaveUp for HL401778+4.p
19569.74/3616.40	% SZS status Ended for HL401778+4.p
19588.02/3618.72	% SZS status Started for HL401778+5.p
19588.02/3618.72	% SZS status GaveUp for HL401778+5.p
19588.02/3618.72	% SZS status Ended for HL401778+5.p
19596.26/3619.76	% SZS status Started for HL401779+4.p
19596.26/3619.76	% SZS status GaveUp for HL401779+4.p
19596.26/3619.76	% SZS status Ended for HL401779+4.p
19596.59/3619.86	% SZS status Started for HL401779+5.p
19596.59/3619.86	% SZS status GaveUp for HL401779+5.p
19596.59/3619.86	% SZS status Ended for HL401779+5.p
19618.54/3622.57	% SZS status Started for HL401781+4.p
19618.54/3622.57	% SZS status GaveUp for HL401781+4.p
19618.54/3622.57	% SZS status Ended for HL401781+4.p
19620.07/3622.68	% SZS status Started for HL401781+5.p
19620.07/3622.68	% SZS status GaveUp for HL401781+5.p
19620.07/3622.68	% SZS status Ended for HL401781+5.p
19629.98/3624.10	% SZS status Started for HL401782+4.p
19629.98/3624.10	% SZS status GaveUp for HL401782+4.p
19629.98/3624.10	% SZS status Ended for HL401782+4.p
19630.14/3624.18	% SZS status Started for HL401782+5.p
19630.14/3624.18	% SZS status GaveUp for HL401782+5.p
19630.14/3624.18	% SZS status Ended for HL401782+5.p
19635.32/3624.77	% SZS status Started for HL401785+4.p
19635.32/3624.77	% SZS status GaveUp for HL401785+4.p
19635.32/3624.77	% SZS status Ended for HL401785+4.p
19653.34/3626.88	% SZS status Started for HL401785+5.p
19653.34/3626.88	% SZS status GaveUp for HL401785+5.p
19653.34/3626.88	% SZS status Ended for HL401785+5.p
19662.17/3628.03	% SZS status Started for HL401786+4.p
19662.17/3628.03	% SZS status GaveUp for HL401786+4.p
19662.17/3628.03	% SZS status Ended for HL401786+4.p
19662.50/3628.11	% SZS status Started for HL401786+5.p
19662.50/3628.11	% SZS status GaveUp for HL401786+5.p
19662.50/3628.11	% SZS status Ended for HL401786+5.p
19684.66/3630.85	% SZS status Started for HL401787+5.p
19684.66/3630.85	% SZS status GaveUp for HL401787+5.p
19684.66/3630.85	% SZS status Ended for HL401787+5.p
19685.42/3630.93	% SZS status Started for HL401787+4.p
19685.42/3630.93	% SZS status GaveUp for HL401787+4.p
19685.42/3630.93	% SZS status Ended for HL401787+4.p
19697.08/3632.40	% SZS status Started for HL401788+5.p
19697.08/3632.40	% SZS status GaveUp for HL401788+5.p
19697.08/3632.40	% SZS status Ended for HL401788+5.p
19697.62/3632.49	% SZS status Started for HL401788+4.p
19697.62/3632.49	% SZS status GaveUp for HL401788+4.p
19697.62/3632.49	% SZS status Ended for HL401788+4.p
19703.14/3633.13	% SZS status Started for HL401789+4.p
19703.14/3633.13	% SZS status GaveUp for HL401789+4.p
19703.14/3633.13	% SZS status Ended for HL401789+4.p
19717.93/3635.11	% SZS status Started for HL401789+5.p
19717.93/3635.11	% SZS status GaveUp for HL401789+5.p
19717.93/3635.11	% SZS status Ended for HL401789+5.p
19727.98/3636.27	% SZS status Started for HL401790+5.p
19727.98/3636.27	% SZS status GaveUp for HL401790+5.p
19727.98/3636.27	% SZS status Ended for HL401790+5.p
19728.29/3636.36	% SZS status Started for HL401790+4.p
19728.29/3636.36	% SZS status GaveUp for HL401790+4.p
19728.29/3636.36	% SZS status Ended for HL401790+4.p
19750.05/3639.01	% SZS status Started for HL401794+4.p
19750.05/3639.01	% SZS status Theorem for HL401794+4.p
19750.05/3639.01	% SZS status Ended for HL401794+4.p
19750.87/3639.16	% SZS status Started for HL401791+5.p
19750.87/3639.16	% SZS status GaveUp for HL401791+5.p
19750.87/3639.16	% SZS status Ended for HL401791+5.p
19751.45/3639.28	% SZS status Started for HL401791+4.p
19751.45/3639.28	% SZS status GaveUp for HL401791+4.p
19751.45/3639.28	% SZS status Ended for HL401791+4.p
19762.38/3640.66	% SZS status Started for HL401792+5.p
19762.38/3640.66	% SZS status GaveUp for HL401792+5.p
19762.38/3640.66	% SZS status Ended for HL401792+5.p
19762.86/3640.68	% SZS status Started for HL401792+4.p
19762.86/3640.68	% SZS status GaveUp for HL401792+4.p
19762.86/3640.68	% SZS status Ended for HL401792+4.p
19769.99/3641.53	% SZS status Started for HL401793+4.p
19769.99/3641.53	% SZS status GaveUp for HL401793+4.p
19769.99/3641.53	% SZS status Ended for HL401793+4.p
19771.07/3641.73	% SZS status Started for HL401797+4.p
19771.07/3641.73	% SZS status Theorem for HL401797+4.p
19771.07/3641.73	% SZS status Ended for HL401797+4.p
19774.79/3642.17	% SZS status Started for HL401797+5.p
19774.79/3642.17	% SZS status Theorem for HL401797+5.p
19774.79/3642.17	% SZS status Ended for HL401797+5.p
19781.73/3643.09	% SZS status Started for HL401798+5.p
19781.73/3643.09	% SZS status Theorem for HL401798+5.p
19781.73/3643.09	% SZS status Ended for HL401798+5.p
19784.14/3643.29	% SZS status Started for HL401793+5.p
19784.14/3643.29	% SZS status GaveUp for HL401793+5.p
19784.14/3643.29	% SZS status Ended for HL401793+5.p
19792.88/3644.44	% SZS status Started for HL401798+4.p
19792.88/3644.44	% SZS status Theorem for HL401798+4.p
19792.88/3644.44	% SZS status Ended for HL401798+4.p
19793.82/3644.55	% SZS status Started for HL401794+5.p
19793.82/3644.55	% SZS status GaveUp for HL401794+5.p
19793.82/3644.55	% SZS status Ended for HL401794+5.p
19803.36/3645.73	% SZS status Started for HL401799+4.p
19803.36/3645.73	% SZS status Theorem for HL401799+4.p
19803.36/3645.73	% SZS status Ended for HL401799+4.p
19814.18/3647.11	% SZS status Started for HL401800+4.p
19814.18/3647.11	% SZS status Theorem for HL401800+4.p
19814.18/3647.11	% SZS status Ended for HL401800+4.p
19815.76/3647.34	% SZS status Started for HL401795+5.p
19815.76/3647.34	% SZS status GaveUp for HL401795+5.p
19815.76/3647.34	% SZS status Ended for HL401795+5.p
19815.76/3647.37	% SZS status Started for HL401795+4.p
19815.76/3647.37	% SZS status GaveUp for HL401795+4.p
19815.76/3647.37	% SZS status Ended for HL401795+4.p
19817.92/3647.61	% SZS status Started for HL401796+4.p
19817.92/3647.61	% SZS status GaveUp for HL401796+4.p
19817.92/3647.61	% SZS status Ended for HL401796+4.p
19821.36/3648.05	% SZS status Started for HL401799+5.p
19821.36/3648.05	% SZS status Theorem for HL401799+5.p
19821.36/3648.05	% SZS status Ended for HL401799+5.p
19827.74/3648.87	% SZS status Started for HL401796+5.p
19827.74/3648.87	% SZS status GaveUp for HL401796+5.p
19827.74/3648.87	% SZS status Ended for HL401796+5.p
19833.16/3649.68	% SZS status Started for HL401800+5.p
19833.16/3649.68	% SZS status Theorem for HL401800+5.p
19833.16/3649.68	% SZS status Ended for HL401800+5.p
19869.47/3654.10	% SZS status Started for HL401801+4.p
19869.47/3654.10	% SZS status GaveUp for HL401801+4.p
19869.47/3654.10	% SZS status Ended for HL401801+4.p
19879.53/3655.36	% SZS status Started for HL401801+5.p
19879.53/3655.36	% SZS status GaveUp for HL401801+5.p
19879.53/3655.36	% SZS status Ended for HL401801+5.p
19880.52/3655.53	% SZS status Started for HL401803+5.p
19880.52/3655.53	% SZS status GaveUp for HL401803+5.p
19880.52/3655.53	% SZS status Ended for HL401803+5.p
19882.09/3655.67	% SZS status Started for HL401803+4.p
19882.09/3655.67	% SZS status GaveUp for HL401803+4.p
19882.09/3655.67	% SZS status Ended for HL401803+4.p
19884.52/3656.00	% SZS status Started for HL401804+4.p
19884.52/3656.00	% SZS status GaveUp for HL401804+4.p
19884.52/3656.00	% SZS status Ended for HL401804+4.p
19885.26/3656.24	% SZS status Started for HL401804+5.p
19885.26/3656.24	% SZS status GaveUp for HL401804+5.p
19885.26/3656.24	% SZS status Ended for HL401804+5.p
19896.02/3657.39	% SZS status Started for HL401806+4.p
19896.02/3657.39	% SZS status GaveUp for HL401806+4.p
19896.02/3657.39	% SZS status Ended for HL401806+4.p
19898.88/3657.77	% SZS status Started for HL401810+4.p
19898.88/3657.77	% SZS status Theorem for HL401810+4.p
19898.88/3657.77	% SZS status Ended for HL401810+4.p
19899.21/3657.89	% SZS status Started for HL401806+5.p
19899.21/3657.89	% SZS status GaveUp for HL401806+5.p
19899.21/3657.89	% SZS status Ended for HL401806+5.p
19935.88/3662.43	% SZS status Started for HL401807+4.p
19935.88/3662.43	% SZS status GaveUp for HL401807+4.p
19935.88/3662.43	% SZS status Ended for HL401807+4.p
19941.59/3663.27	% SZS status Started for HL401809+4.p
19941.59/3663.27	% SZS status Theorem for HL401809+4.p
19941.59/3663.27	% SZS status Ended for HL401809+4.p
19944.87/3663.53	% SZS status Started for HL401807+5.p
19944.87/3663.53	% SZS status GaveUp for HL401807+5.p
19944.87/3663.53	% SZS status Ended for HL401807+5.p
19946.50/3663.87	% SZS status Started for HL401808+4.p
19946.50/3663.87	% SZS status GaveUp for HL401808+4.p
19946.50/3663.87	% SZS status Ended for HL401808+4.p
19949.29/3664.10	% SZS status Started for HL401808+5.p
19949.29/3664.10	% SZS status GaveUp for HL401808+5.p
19949.29/3664.10	% SZS status Ended for HL401808+5.p
19951.57/3664.44	% SZS status Started for HL401809+5.p
19951.57/3664.44	% SZS status GaveUp for HL401809+5.p
19951.57/3664.44	% SZS status Ended for HL401809+5.p
19955.26/3664.95	% SZS status Started for HL401810+5.p
19955.26/3664.95	% SZS status Theorem for HL401810+5.p
19955.26/3664.95	% SZS status Ended for HL401810+5.p
19965.90/3666.26	% SZS status Started for HL401811+4.p
19965.90/3666.26	% SZS status GaveUp for HL401811+4.p
19965.90/3666.26	% SZS status Ended for HL401811+4.p
19969.58/3666.75	% SZS status Started for HL401816+4.p
19969.58/3666.75	% SZS status Theorem for HL401816+4.p
19969.58/3666.75	% SZS status Ended for HL401816+4.p
19974.55/3667.34	% SZS status Started for HL401816+5.p
19974.55/3667.34	% SZS status Theorem for HL401816+5.p
19974.55/3667.34	% SZS status Ended for HL401816+5.p
19996.89/3670.16	% SZS status Started for HL401817+4.p
19996.89/3670.16	% SZS status Theorem for HL401817+4.p
19996.89/3670.16	% SZS status Ended for HL401817+4.p
19999.18/3670.61	% SZS status Started for HL401811+5.p
19999.18/3670.61	% SZS status GaveUp for HL401811+5.p
19999.18/3670.61	% SZS status Ended for HL401811+5.p
20002.62/3670.92	% SZS status Started for HL401818+4.p
20002.62/3670.92	% SZS status Theorem for HL401818+4.p
20002.62/3670.92	% SZS status Ended for HL401818+4.p
20007.88/3671.65	% SZS status Started for HL401812+4.p
20007.88/3671.65	% SZS status GaveUp for HL401812+4.p
20007.88/3671.65	% SZS status Ended for HL401812+4.p
20011.24/3671.94	% SZS status Started for HL401812+5.p
20011.24/3671.94	% SZS status GaveUp for HL401812+5.p
20011.24/3671.94	% SZS status Ended for HL401812+5.p
20013.25/3672.31	% SZS status Started for HL401813+4.p
20013.25/3672.31	% SZS status GaveUp for HL401813+4.p
20013.25/3672.31	% SZS status Ended for HL401813+4.p
20013.62/3672.36	% SZS status Started for HL401813+5.p
20013.62/3672.36	% SZS status GaveUp for HL401813+5.p
20013.62/3672.36	% SZS status Ended for HL401813+5.p
20016.87/3672.76	% SZS status Started for HL401815+4.p
20016.87/3672.76	% SZS status GaveUp for HL401815+4.p
20016.87/3672.76	% SZS status Ended for HL401815+4.p
20020.53/3673.13	% SZS status Started for HL401815+5.p
20020.53/3673.13	% SZS status GaveUp for HL401815+5.p
20020.53/3673.13	% SZS status Ended for HL401815+5.p
20037.64/3675.29	% SZS status Started for HL401817+5.p
20037.64/3675.29	% SZS status Theorem for HL401817+5.p
20037.64/3675.29	% SZS status Ended for HL401817+5.p
20041.04/3675.68	% SZS status Started for HL401820+4.p
20041.04/3675.68	% SZS status Theorem for HL401820+4.p
20041.04/3675.68	% SZS status Ended for HL401820+4.p
20041.04/3675.69	% SZS status Started for HL401818+5.p
20041.04/3675.69	% SZS status Theorem for HL401818+5.p
20041.04/3675.69	% SZS status Ended for HL401818+5.p
20046.80/3676.46	% SZS status Started for HL401822+4.p
20046.80/3676.46	% SZS status Theorem for HL401822+4.p
20046.80/3676.46	% SZS status Ended for HL401822+4.p
20074.28/3679.98	% SZS status Started for HL401819+4.p
20074.28/3679.98	% SZS status GaveUp for HL401819+4.p
20074.28/3679.98	% SZS status Ended for HL401819+4.p
20076.62/3680.21	% SZS status Started for HL401819+5.p
20076.62/3680.21	% SZS status GaveUp for HL401819+5.p
20076.62/3680.21	% SZS status Ended for HL401819+5.p
20078.48/3680.59	% SZS status Started for HL401820+5.p
20078.48/3680.59	% SZS status GaveUp for HL401820+5.p
20078.48/3680.59	% SZS status Ended for HL401820+5.p
20082.74/3681.05	% SZS status Started for HL401821+4.p
20082.74/3681.05	% SZS status GaveUp for HL401821+4.p
20082.74/3681.05	% SZS status Ended for HL401821+4.p
20085.22/3681.30	% SZS status Started for HL401821+5.p
20085.22/3681.30	% SZS status GaveUp for HL401821+5.p
20085.22/3681.30	% SZS status Ended for HL401821+5.p
20105.56/3683.88	% SZS status Started for HL401822+5.p
20105.56/3683.88	% SZS status GaveUp for HL401822+5.p
20105.56/3683.88	% SZS status Ended for HL401822+5.p
20108.25/3684.21	% SZS status Started for HL401823+4.p
20108.25/3684.21	% SZS status GaveUp for HL401823+4.p
20108.25/3684.21	% SZS status Ended for HL401823+4.p
20112.63/3684.72	% SZS status Started for HL401823+5.p
20112.63/3684.72	% SZS status GaveUp for HL401823+5.p
20112.63/3684.72	% SZS status Ended for HL401823+5.p
20125.75/3686.38	% SZS status Started for HL401826+4.p
20125.75/3686.38	% SZS status Theorem for HL401826+4.p
20125.75/3686.38	% SZS status Ended for HL401826+4.p
20127.44/3686.78	% SZS status Started for HL401827+4.p
20127.44/3686.78	% SZS status Theorem for HL401827+4.p
20127.44/3686.78	% SZS status Ended for HL401827+4.p
20140.81/3688.32	% SZS status Started for HL401824+4.p
20140.81/3688.32	% SZS status GaveUp for HL401824+4.p
20140.81/3688.32	% SZS status Ended for HL401824+4.p
20141.46/3688.45	% SZS status Started for HL401824+5.p
20141.46/3688.45	% SZS status GaveUp for HL401824+5.p
20141.46/3688.45	% SZS status Ended for HL401824+5.p
20145.43/3688.91	% SZS status Started for HL401825+4.p
20145.43/3688.91	% SZS status GaveUp for HL401825+4.p
20145.43/3688.91	% SZS status Ended for HL401825+4.p
20148.63/3689.27	% SZS status Started for HL401825+5.p
20148.63/3689.27	% SZS status GaveUp for HL401825+5.p
20148.63/3689.27	% SZS status Ended for HL401825+5.p
20171.32/3692.16	% SZS status Started for HL401826+5.p
20171.32/3692.16	% SZS status GaveUp for HL401826+5.p
20171.32/3692.16	% SZS status Ended for HL401826+5.p
20172.41/3692.45	% SZS status Started for HL401831+4.p
20172.41/3692.45	% SZS status Theorem for HL401831+4.p
20172.41/3692.45	% SZS status Ended for HL401831+4.p
20176.84/3692.98	% SZS status Started for HL401831+5.p
20176.84/3692.98	% SZS status Theorem for HL401831+5.p
20176.84/3692.98	% SZS status Ended for HL401831+5.p
20176.84/3692.98	% SZS status Started for HL401827+5.p
20176.84/3692.98	% SZS status GaveUp for HL401827+5.p
20176.84/3692.98	% SZS status Ended for HL401827+5.p
20193.26/3694.90	% SZS status Started for HL401828+4.p
20193.26/3694.90	% SZS status GaveUp for HL401828+4.p
20193.26/3694.90	% SZS status Ended for HL401828+4.p
20194.03/3694.98	% SZS status Started for HL401828+5.p
20194.03/3694.98	% SZS status GaveUp for HL401828+5.p
20194.03/3694.98	% SZS status Ended for HL401828+5.p
20207.12/3696.63	% SZS status Started for HL401829+5.p
20207.12/3696.63	% SZS status GaveUp for HL401829+5.p
20207.12/3696.63	% SZS status Ended for HL401829+5.p
20207.12/3696.63	% SZS status Started for HL401829+4.p
20207.12/3696.63	% SZS status GaveUp for HL401829+4.p
20207.12/3696.63	% SZS status Ended for HL401829+4.p
20211.59/3697.20	% SZS status Started for HL401830+4.p
20211.59/3697.20	% SZS status GaveUp for HL401830+4.p
20211.59/3697.20	% SZS status Ended for HL401830+4.p
20212.67/3697.54	% SZS status Started for HL401830+5.p
20212.67/3697.54	% SZS status GaveUp for HL401830+5.p
20212.67/3697.54	% SZS status Ended for HL401830+5.p
20243.48/3701.19	% SZS status Started for HL401832+5.p
20243.48/3701.19	% SZS status GaveUp for HL401832+5.p
20243.48/3701.19	% SZS status Ended for HL401832+5.p
20244.54/3701.38	% SZS status Started for HL401832+4.p
20244.54/3701.38	% SZS status GaveUp for HL401832+4.p
20244.54/3701.38	% SZS status Ended for HL401832+4.p
20258.45/3703.19	% SZS status Started for HL401834+5.p
20258.45/3703.19	% SZS status GaveUp for HL401834+5.p
20258.45/3703.19	% SZS status Ended for HL401834+5.p
20258.45/3703.24	% SZS status Started for HL401834+4.p
20258.45/3703.24	% SZS status GaveUp for HL401834+4.p
20258.45/3703.24	% SZS status Ended for HL401834+4.p
20271.43/3704.79	% SZS status Started for HL401835+5.p
20271.43/3704.79	% SZS status GaveUp for HL401835+5.p
20271.43/3704.79	% SZS status Ended for HL401835+5.p
20274.46/3705.11	% SZS status Started for HL401835+4.p
20274.46/3705.11	% SZS status GaveUp for HL401835+4.p
20274.46/3705.11	% SZS status Ended for HL401835+4.p
20278.48/3705.64	% SZS status Started for HL401836+4.p
20278.48/3705.64	% SZS status GaveUp for HL401836+4.p
20278.48/3705.64	% SZS status Ended for HL401836+4.p
20279.96/3705.86	% SZS status Started for HL401836+5.p
20279.96/3705.86	% SZS status GaveUp for HL401836+5.p
20279.96/3705.86	% SZS status Ended for HL401836+5.p
20284.61/3706.45	% SZS status Started for HL401838+4.p
20284.61/3706.45	% SZS status Theorem for HL401838+4.p
20284.61/3706.45	% SZS status Ended for HL401838+4.p
20309.79/3709.59	% SZS status Started for HL401837+4.p
20309.79/3709.59	% SZS status GaveUp for HL401837+4.p
20309.79/3709.59	% SZS status Ended for HL401837+4.p
20310.27/3709.63	% SZS status Started for HL401837+5.p
20310.27/3709.63	% SZS status GaveUp for HL401837+5.p
20310.27/3709.63	% SZS status Ended for HL401837+5.p
20324.14/3711.44	% SZS status Started for HL401838+5.p
20324.14/3711.44	% SZS status GaveUp for HL401838+5.p
20324.14/3711.44	% SZS status Ended for HL401838+5.p
20338.64/3713.28	% SZS status Started for HL401840+4.p
20338.64/3713.28	% SZS status GaveUp for HL401840+4.p
20338.64/3713.28	% SZS status Ended for HL401840+4.p
20338.64/3713.34	% SZS status Started for HL401840+5.p
20338.64/3713.34	% SZS status GaveUp for HL401840+5.p
20338.64/3713.34	% SZS status Ended for HL401840+5.p
20345.04/3714.10	% SZS status Started for HL401844+5.p
20345.04/3714.10	% SZS status Theorem for HL401844+5.p
20345.04/3714.10	% SZS status Ended for HL401844+5.p
20345.04/3714.12	% SZS status Started for HL401841+5.p
20345.04/3714.12	% SZS status GaveUp for HL401841+5.p
20345.04/3714.12	% SZS status Ended for HL401841+5.p
20345.04/3714.13	% SZS status Started for HL401841+4.p
20345.04/3714.13	% SZS status GaveUp for HL401841+4.p
20345.04/3714.13	% SZS status Ended for HL401841+4.p
20345.04/3714.13	% SZS status Started for HL401844+4.p
20345.04/3714.13	% SZS status Theorem for HL401844+4.p
20345.04/3714.13	% SZS status Ended for HL401844+4.p
20348.57/3714.44	% SZS status Started for HL401848+4.p
20348.57/3714.44	% SZS status Theorem for HL401848+4.p
20348.57/3714.44	% SZS status Ended for HL401848+4.p
20351.40/3714.88	% SZS status Started for HL401842+4.p
20351.40/3714.88	% SZS status GaveUp for HL401842+4.p
20351.40/3714.88	% SZS status Ended for HL401842+4.p
20355.48/3715.33	% SZS status Started for HL401850+4.p
20355.48/3715.33	% SZS status Theorem for HL401850+4.p
20355.48/3715.33	% SZS status Ended for HL401850+4.p
20373.59/3717.76	% SZS status Started for HL401842+5.p
20373.59/3717.76	% SZS status GaveUp for HL401842+5.p
20373.59/3717.76	% SZS status Ended for HL401842+5.p
20376.40/3717.93	% SZS status Started for HL401843+4.p
20376.40/3717.93	% SZS status GaveUp for HL401843+4.p
20376.40/3717.93	% SZS status Ended for HL401843+4.p
20376.80/3718.04	% SZS status Started for HL401850+5.p
20376.80/3718.04	% SZS status Theorem for HL401850+5.p
20376.80/3718.04	% SZS status Ended for HL401850+5.p
20383.60/3718.94	% SZS status Started for HL401848+5.p
20383.60/3718.94	% SZS status Theorem for HL401848+5.p
20383.60/3718.94	% SZS status Ended for HL401848+5.p
20389.79/3719.64	% SZS status Started for HL401843+5.p
20389.79/3719.64	% SZS status GaveUp for HL401843+5.p
20389.79/3719.64	% SZS status Ended for HL401843+5.p
20403.80/3721.37	% SZS status Started for HL401845+4.p
20403.80/3721.37	% SZS status Theorem for HL401845+4.p
20403.80/3721.37	% SZS status Ended for HL401845+4.p
20410.58/3722.28	% SZS status Started for HL401845+5.p
20410.58/3722.28	% SZS status GaveUp for HL401845+5.p
20410.58/3722.28	% SZS status Ended for HL401845+5.p
20422.19/3723.70	% SZS status Started for HL401852+4.p
20422.19/3723.70	% SZS status GaveUp for HL401852+4.p
20422.19/3723.70	% SZS status Ended for HL401852+4.p
20440.32/3725.96	% SZS status Started for HL401852+5.p
20440.32/3725.96	% SZS status GaveUp for HL401852+5.p
20440.32/3725.96	% SZS status Ended for HL401852+5.p
20441.56/3726.22	% SZS status Started for HL401854+5.p
20441.56/3726.22	% SZS status GaveUp for HL401854+5.p
20441.56/3726.22	% SZS status Ended for HL401854+5.p
20441.91/3726.29	% SZS status Started for HL401854+4.p
20441.91/3726.29	% SZS status GaveUp for HL401854+4.p
20441.91/3726.29	% SZS status Ended for HL401854+4.p
20449.92/3727.31	% SZS status Started for HL401856+4.p
20449.92/3727.31	% SZS status GaveUp for HL401856+4.p
20449.92/3727.31	% SZS status Ended for HL401856+4.p
20455.42/3727.88	% SZS status Started for HL401856+5.p
20455.42/3727.88	% SZS status GaveUp for HL401856+5.p
20455.42/3727.88	% SZS status Ended for HL401856+5.p
20460.27/3728.46	% SZS status Started for HL401860+5.p
20460.27/3728.46	% SZS status Theorem for HL401860+5.p
20460.27/3728.46	% SZS status Ended for HL401860+5.p
20461.11/3728.69	% SZS status Started for HL401860+4.p
20461.11/3728.69	% SZS status Theorem for HL401860+4.p
20461.11/3728.69	% SZS status Ended for HL401860+4.p
20469.53/3729.72	% SZS status Started for HL401857+4.p
20469.53/3729.72	% SZS status GaveUp for HL401857+4.p
20469.53/3729.72	% SZS status Ended for HL401857+4.p
20476.86/3730.55	% SZS status Started for HL401857+5.p
20476.86/3730.55	% SZS status GaveUp for HL401857+5.p
20476.86/3730.55	% SZS status Ended for HL401857+5.p
20482.53/3731.27	% SZS status Started for HL401862+5.p
20482.53/3731.27	% SZS status Theorem for HL401862+5.p
20482.53/3731.27	% SZS status Ended for HL401862+5.p
20488.16/3732.05	% SZS status Started for HL401858+4.p
20488.16/3732.05	% SZS status GaveUp for HL401858+4.p
20488.16/3732.05	% SZS status Ended for HL401858+4.p
20505.33/3734.19	% SZS status Started for HL401858+5.p
20505.33/3734.19	% SZS status GaveUp for HL401858+5.p
20505.33/3734.19	% SZS status Ended for HL401858+5.p
20506.39/3734.46	% SZS status Started for HL401859+5.p
20506.39/3734.46	% SZS status GaveUp for HL401859+5.p
20506.39/3734.46	% SZS status Ended for HL401859+5.p
20509.62/3734.66	% SZS status Started for HL401859+4.p
20509.62/3734.66	% SZS status GaveUp for HL401859+4.p
20509.62/3734.66	% SZS status Ended for HL401859+4.p
20516.45/3735.58	% SZS status Started for HL401864+4.p
20516.45/3735.58	% SZS status Theorem for HL401864+4.p
20516.45/3735.58	% SZS status Ended for HL401864+4.p
20524.51/3736.57	% SZS status Started for HL401862+4.p
20524.51/3736.57	% SZS status Theorem for HL401862+4.p
20524.51/3736.57	% SZS status Ended for HL401862+4.p
20525.92/3736.77	% SZS status Started for HL401861+4.p
20525.92/3736.77	% SZS status GaveUp for HL401861+4.p
20525.92/3736.77	% SZS status Ended for HL401861+4.p
20527.46/3736.91	% SZS status Started for HL401861+5.p
20527.46/3736.91	% SZS status GaveUp for HL401861+5.p
20527.46/3736.91	% SZS status Ended for HL401861+5.p
20549.53/3739.67	% SZS status Started for HL401863+4.p
20549.53/3739.67	% SZS status GaveUp for HL401863+4.p
20549.53/3739.67	% SZS status Ended for HL401863+4.p
20553.87/3740.25	% SZS status Started for HL401863+5.p
20553.87/3740.25	% SZS status GaveUp for HL401863+5.p
20553.87/3740.25	% SZS status Ended for HL401863+5.p
20572.20/3742.62	% SZS status Started for HL401864+5.p
20572.20/3742.62	% SZS status GaveUp for HL401864+5.p
20572.20/3742.62	% SZS status Ended for HL401864+5.p
20575.37/3742.97	% SZS status Started for HL401865+4.p
20575.37/3742.97	% SZS status GaveUp for HL401865+4.p
20575.37/3742.97	% SZS status Ended for HL401865+4.p
20583.10/3743.92	% SZS status Started for HL401865+5.p
20583.10/3743.92	% SZS status GaveUp for HL401865+5.p
20583.10/3743.92	% SZS status Ended for HL401865+5.p
20591.43/3744.92	% SZS status Started for HL401866+4.p
20591.43/3744.92	% SZS status GaveUp for HL401866+4.p
20591.43/3744.92	% SZS status Ended for HL401866+4.p
20591.66/3745.01	% SZS status Started for HL401866+5.p
20591.66/3745.01	% SZS status GaveUp for HL401866+5.p
20591.66/3745.01	% SZS status Ended for HL401866+5.p
20593.33/3745.27	% SZS status Started for HL401868+4.p
20593.33/3745.27	% SZS status GaveUp for HL401868+4.p
20593.33/3745.27	% SZS status Ended for HL401868+4.p
20614.13/3747.85	% SZS status Started for HL401868+5.p
20614.13/3747.85	% SZS status GaveUp for HL401868+5.p
20614.13/3747.85	% SZS status Ended for HL401868+5.p
20620.85/3748.72	% SZS status Started for HL401869+4.p
20620.85/3748.72	% SZS status GaveUp for HL401869+4.p
20620.85/3748.72	% SZS status Ended for HL401869+4.p
20637.83/3750.81	% SZS status Started for HL401869+5.p
20637.83/3750.81	% SZS status GaveUp for HL401869+5.p
20637.83/3750.81	% SZS status Ended for HL401869+5.p
20641.40/3751.35	% SZS status Started for HL401870+4.p
20641.40/3751.35	% SZS status GaveUp for HL401870+4.p
20641.40/3751.35	% SZS status Ended for HL401870+4.p
20649.15/3752.18	% SZS status Started for HL401870+5.p
20649.15/3752.18	% SZS status GaveUp for HL401870+5.p
20649.15/3752.18	% SZS status Ended for HL401870+5.p
20657.09/3753.18	% SZS status Started for HL401871+5.p
20657.09/3753.18	% SZS status GaveUp for HL401871+5.p
20657.09/3753.18	% SZS status Ended for HL401871+5.p
20657.82/3753.28	% SZS status Started for HL401871+4.p
20657.82/3753.28	% SZS status GaveUp for HL401871+4.p
20657.82/3753.28	% SZS status Ended for HL401871+4.p
20659.77/3753.68	% SZS status Started for HL401872+4.p
20659.77/3753.68	% SZS status GaveUp for HL401872+4.p
20659.77/3753.68	% SZS status Ended for HL401872+4.p
20678.95/3756.04	% SZS status Started for HL401872+5.p
20678.95/3756.04	% SZS status GaveUp for HL401872+5.p
20678.95/3756.04	% SZS status Ended for HL401872+5.p
20687.47/3757.04	% SZS status Started for HL401874+4.p
20687.47/3757.04	% SZS status GaveUp for HL401874+4.p
20687.47/3757.04	% SZS status Ended for HL401874+4.p
20702.85/3758.98	% SZS status Started for HL401874+5.p
20702.85/3758.98	% SZS status GaveUp for HL401874+5.p
20702.85/3758.98	% SZS status Ended for HL401874+5.p
20708.58/3759.67	% SZS status Started for HL401875+4.p
20708.58/3759.67	% SZS status GaveUp for HL401875+4.p
20708.58/3759.67	% SZS status Ended for HL401875+4.p
20713.61/3760.38	% SZS status Started for HL401875+5.p
20713.61/3760.38	% SZS status GaveUp for HL401875+5.p
20713.61/3760.38	% SZS status Ended for HL401875+5.p
20722.23/3761.46	% SZS status Started for HL401877+5.p
20722.23/3761.46	% SZS status GaveUp for HL401877+5.p
20722.23/3761.46	% SZS status Ended for HL401877+5.p
20722.95/3761.64	% SZS status Started for HL401877+4.p
20722.95/3761.64	% SZS status GaveUp for HL401877+4.p
20722.95/3761.64	% SZS status Ended for HL401877+4.p
20729.13/3762.32	% SZS status Started for HL401878+4.p
20729.13/3762.32	% SZS status GaveUp for HL401878+4.p
20729.13/3762.32	% SZS status Ended for HL401878+4.p
20744.32/3764.22	% SZS status Started for HL401878+5.p
20744.32/3764.22	% SZS status GaveUp for HL401878+5.p
20744.32/3764.22	% SZS status Ended for HL401878+5.p
20753.50/3765.41	% SZS status Started for HL401879+4.p
20753.50/3765.41	% SZS status GaveUp for HL401879+4.p
20753.50/3765.41	% SZS status Ended for HL401879+4.p
20768.18/3767.18	% SZS status Started for HL401879+5.p
20768.18/3767.18	% SZS status GaveUp for HL401879+5.p
20768.18/3767.18	% SZS status Ended for HL401879+5.p
20776.07/3768.14	% SZS status Started for HL401880+4.p
20776.07/3768.14	% SZS status GaveUp for HL401880+4.p
20776.07/3768.14	% SZS status Ended for HL401880+4.p
20779.65/3768.64	% SZS status Started for HL401880+5.p
20779.65/3768.64	% SZS status GaveUp for HL401880+5.p
20779.65/3768.64	% SZS status Ended for HL401880+5.p
20789.23/3769.81	% SZS status Started for HL401881+4.p
20789.23/3769.81	% SZS status GaveUp for HL401881+4.p
20789.23/3769.81	% SZS status Ended for HL401881+4.p
20789.23/3769.82	% SZS status Started for HL401881+5.p
20789.23/3769.82	% SZS status GaveUp for HL401881+5.p
20789.23/3769.82	% SZS status Ended for HL401881+5.p
20795.95/3770.82	% SZS status Started for HL401883+4.p
20795.95/3770.82	% SZS status GaveUp for HL401883+4.p
20795.95/3770.82	% SZS status Ended for HL401883+4.p
20810.29/3772.49	% SZS status Started for HL401883+5.p
20810.29/3772.49	% SZS status GaveUp for HL401883+5.p
20810.29/3772.49	% SZS status Ended for HL401883+5.p
20820.76/3773.81	% SZS status Started for HL401884+4.p
20820.76/3773.81	% SZS status GaveUp for HL401884+4.p
20820.76/3773.81	% SZS status Ended for HL401884+4.p
20833.34/3775.36	% SZS status Started for HL401884+5.p
20833.34/3775.36	% SZS status GaveUp for HL401884+5.p
20833.34/3775.36	% SZS status Ended for HL401884+5.p
20840.51/3776.43	% SZS status Started for HL401885+4.p
20840.51/3776.43	% SZS status GaveUp for HL401885+4.p
20840.51/3776.43	% SZS status Ended for HL401885+4.p
20844.38/3776.81	% SZS status Started for HL401885+5.p
20844.38/3776.81	% SZS status GaveUp for HL401885+5.p
20844.38/3776.81	% SZS status Ended for HL401885+5.p
20853.96/3778.01	% SZS status Started for HL401886+5.p
20853.96/3778.01	% SZS status GaveUp for HL401886+5.p
20853.96/3778.01	% SZS status Ended for HL401886+5.p
20854.17/3778.13	% SZS status Started for HL401886+4.p
20854.17/3778.13	% SZS status GaveUp for HL401886+4.p
20854.17/3778.13	% SZS status Ended for HL401886+4.p
20863.67/3779.21	% SZS status Started for HL401887+4.p
20863.67/3779.21	% SZS status GaveUp for HL401887+4.p
20863.67/3779.21	% SZS status Ended for HL401887+4.p
20875.77/3780.73	% SZS status Started for HL401887+5.p
20875.77/3780.73	% SZS status GaveUp for HL401887+5.p
20875.77/3780.73	% SZS status Ended for HL401887+5.p
20888.35/3782.27	% SZS status Started for HL401888+4.p
20888.35/3782.27	% SZS status GaveUp for HL401888+4.p
20888.35/3782.27	% SZS status Ended for HL401888+4.p
20898.65/3783.55	% SZS status Started for HL401888+5.p
20898.65/3783.55	% SZS status GaveUp for HL401888+5.p
20898.65/3783.55	% SZS status Ended for HL401888+5.p
20908.20/3784.79	% SZS status Started for HL401889+4.p
20908.20/3784.79	% SZS status GaveUp for HL401889+4.p
20908.20/3784.79	% SZS status Ended for HL401889+4.p
20909.17/3784.99	% SZS status Started for HL401889+5.p
20909.17/3784.99	% SZS status GaveUp for HL401889+5.p
20909.17/3784.99	% SZS status Ended for HL401889+5.p
20920.57/3786.33	% SZS status Started for HL401890+5.p
20920.57/3786.33	% SZS status GaveUp for HL401890+5.p
20920.57/3786.33	% SZS status Ended for HL401890+5.p
20921.42/3786.44	% SZS status Started for HL401890+4.p
20921.42/3786.44	% SZS status GaveUp for HL401890+4.p
20921.42/3786.44	% SZS status Ended for HL401890+4.p
20929.15/3787.42	% SZS status Started for HL401894+4.p
20929.15/3787.42	% SZS status Theorem for HL401894+4.p
20929.15/3787.42	% SZS status Ended for HL401894+4.p
20930.47/3787.56	% SZS status Started for HL401891+4.p
20930.47/3787.56	% SZS status GaveUp for HL401891+4.p
20930.47/3787.56	% SZS status Ended for HL401891+4.p
20940.08/3788.91	% SZS status Started for HL401891+5.p
20940.08/3788.91	% SZS status GaveUp for HL401891+5.p
20940.08/3788.91	% SZS status Ended for HL401891+5.p
20955.39/3790.67	% SZS status Started for HL401892+4.p
20955.39/3790.67	% SZS status GaveUp for HL401892+4.p
20955.39/3790.67	% SZS status Ended for HL401892+4.p
20964.08/3791.77	% SZS status Started for HL401892+5.p
20964.08/3791.77	% SZS status GaveUp for HL401892+5.p
20964.08/3791.77	% SZS status Ended for HL401892+5.p
20974.63/3793.19	% SZS status Started for HL401893+5.p
20974.63/3793.19	% SZS status GaveUp for HL401893+5.p
20974.63/3793.19	% SZS status Ended for HL401893+5.p
20974.98/3793.20	% SZS status Started for HL401893+4.p
20974.98/3793.20	% SZS status GaveUp for HL401893+4.p
20974.98/3793.20	% SZS status Ended for HL401893+4.p
20987.03/3794.64	% SZS status Started for HL401894+5.p
20987.03/3794.64	% SZS status GaveUp for HL401894+5.p
20987.03/3794.64	% SZS status Ended for HL401894+5.p
20995.86/3795.76	% SZS status Started for HL401895+5.p
20995.86/3795.76	% SZS status GaveUp for HL401895+5.p
20995.86/3795.76	% SZS status Ended for HL401895+5.p
20995.86/3795.79	% SZS status Started for HL401895+4.p
20995.86/3795.79	% SZS status GaveUp for HL401895+4.p
20995.86/3795.79	% SZS status Ended for HL401895+4.p
21007.57/3797.27	% SZS status Started for HL401896+4.p
21007.57/3797.27	% SZS status GaveUp for HL401896+4.p
21007.57/3797.27	% SZS status Ended for HL401896+4.p
21020.79/3798.93	% SZS status Started for HL401896+5.p
21020.79/3798.93	% SZS status GaveUp for HL401896+5.p
21020.79/3798.93	% SZS status Ended for HL401896+5.p
21030.10/3800.06	% SZS status Started for HL401897+4.p
21030.10/3800.06	% SZS status GaveUp for HL401897+4.p
21030.10/3800.06	% SZS status Ended for HL401897+4.p
21040.22/3801.45	% SZS status Started for HL401897+5.p
21040.22/3801.45	% SZS status GaveUp for HL401897+5.p
21040.22/3801.45	% SZS status Ended for HL401897+5.p
21040.77/3801.56	% SZS status Started for HL401898+4.p
21040.77/3801.56	% SZS status GaveUp for HL401898+4.p
21040.77/3801.56	% SZS status Ended for HL401898+4.p
21051.92/3802.81	% SZS status Started for HL401898+5.p
21051.92/3802.81	% SZS status GaveUp for HL401898+5.p
21051.92/3802.81	% SZS status Ended for HL401898+5.p
21061.61/3804.05	% SZS status Started for HL401899+5.p
21061.61/3804.05	% SZS status GaveUp for HL401899+5.p
21061.61/3804.05	% SZS status Ended for HL401899+5.p
21062.04/3804.14	% SZS status Started for HL401899+4.p
21062.04/3804.14	% SZS status GaveUp for HL401899+4.p
21062.04/3804.14	% SZS status Ended for HL401899+4.p
21074.47/3805.67	% SZS status Started for HL401900+4.p
21074.47/3805.67	% SZS status GaveUp for HL401900+4.p
21074.47/3805.67	% SZS status Ended for HL401900+4.p
21085.77/3807.11	% SZS status Started for HL401900+5.p
21085.77/3807.11	% SZS status GaveUp for HL401900+5.p
21085.77/3807.11	% SZS status Ended for HL401900+5.p
21096.99/3808.56	% SZS status Started for HL401901+4.p
21096.99/3808.56	% SZS status GaveUp for HL401901+4.p
21096.99/3808.56	% SZS status Ended for HL401901+4.p
21100.28/3808.91	% SZS status Started for HL401906+4.p
21100.28/3808.91	% SZS status Theorem for HL401906+4.p
21100.28/3808.91	% SZS status Ended for HL401906+4.p
21104.62/3809.50	% SZS status Started for HL401906+5.p
21104.62/3809.50	% SZS status Theorem for HL401906+5.p
21104.62/3809.50	% SZS status Ended for HL401906+5.p
21105.42/3809.66	% SZS status Started for HL401901+5.p
21105.42/3809.66	% SZS status GaveUp for HL401901+5.p
21105.42/3809.66	% SZS status Ended for HL401901+5.p
21109.16/3810.00	% SZS status Started for HL401902+4.p
21109.16/3810.00	% SZS status GaveUp for HL401902+4.p
21109.16/3810.00	% SZS status Ended for HL401902+4.p
21116.97/3811.01	% SZS status Started for HL401902+5.p
21116.97/3811.01	% SZS status GaveUp for HL401902+5.p
21116.97/3811.01	% SZS status Ended for HL401902+5.p
21127.35/3812.33	% SZS status Started for HL401904+5.p
21127.35/3812.33	% SZS status GaveUp for HL401904+5.p
21127.35/3812.33	% SZS status Ended for HL401904+5.p
21127.86/3812.49	% SZS status Started for HL401904+4.p
21127.86/3812.49	% SZS status GaveUp for HL401904+4.p
21127.86/3812.49	% SZS status Ended for HL401904+4.p
21140.79/3814.06	% SZS status Started for HL401905+4.p
21140.79/3814.06	% SZS status GaveUp for HL401905+4.p
21140.79/3814.06	% SZS status Ended for HL401905+4.p
21151.67/3815.35	% SZS status Started for HL401905+5.p
21151.67/3815.35	% SZS status GaveUp for HL401905+5.p
21151.67/3815.35	% SZS status Ended for HL401905+5.p
21172.08/3817.96	% SZS status Started for HL401907+5.p
21172.08/3817.96	% SZS status GaveUp for HL401907+5.p
21172.08/3817.96	% SZS status Ended for HL401907+5.p
21172.08/3817.97	% SZS status Started for HL401907+4.p
21172.08/3817.97	% SZS status GaveUp for HL401907+4.p
21172.08/3817.97	% SZS status Ended for HL401907+4.p
21175.16/3818.38	% SZS status Started for HL401908+4.p
21175.16/3818.38	% SZS status GaveUp for HL401908+4.p
21175.16/3818.38	% SZS status Ended for HL401908+4.p
21178.84/3818.80	% SZS status Started for HL401912+4.p
21178.84/3818.80	% SZS status Theorem for HL401912+4.p
21178.84/3818.80	% SZS status Ended for HL401912+4.p
21181.85/3819.21	% SZS status Started for HL401908+5.p
21181.85/3819.21	% SZS status GaveUp for HL401908+5.p
21181.85/3819.21	% SZS status Ended for HL401908+5.p
21193.58/3820.79	% SZS status Started for HL401909+4.p
21193.58/3820.79	% SZS status GaveUp for HL401909+4.p
21193.58/3820.79	% SZS status Ended for HL401909+4.p
21195.41/3820.89	% SZS status Started for HL401909+5.p
21195.41/3820.89	% SZS status GaveUp for HL401909+5.p
21195.41/3820.89	% SZS status Ended for HL401909+5.p
21206.03/3822.34	% SZS status Started for HL401914+4.p
21206.03/3822.34	% SZS status Theorem for HL401914+4.p
21206.03/3822.34	% SZS status Ended for HL401914+4.p
21208.69/3822.55	% SZS status Started for HL401910+4.p
21208.69/3822.55	% SZS status GaveUp for HL401910+4.p
21208.69/3822.55	% SZS status Ended for HL401910+4.p
21216.84/3823.57	% SZS status Started for HL401910+5.p
21216.84/3823.57	% SZS status GaveUp for HL401910+5.p
21216.84/3823.57	% SZS status Ended for HL401910+5.p
21219.96/3824.08	% SZS status Started for HL401916+5.p
21219.96/3824.08	% SZS status Theorem for HL401916+5.p
21219.96/3824.08	% SZS status Ended for HL401916+5.p
21220.59/3824.12	% SZS status Started for HL401912+5.p
21220.59/3824.12	% SZS status Theorem for HL401912+5.p
21220.59/3824.12	% SZS status Ended for HL401912+5.p
21237.63/3826.30	% SZS status Started for HL401911+5.p
21237.63/3826.30	% SZS status GaveUp for HL401911+5.p
21237.63/3826.30	% SZS status Ended for HL401911+5.p
21238.74/3826.33	% SZS status Started for HL401911+4.p
21238.74/3826.33	% SZS status GaveUp for HL401911+4.p
21238.74/3826.33	% SZS status Ended for HL401911+4.p
21248.62/3827.60	% SZS status Started for HL401913+4.p
21248.62/3827.60	% SZS status GaveUp for HL401913+4.p
21248.62/3827.60	% SZS status Ended for HL401913+4.p
21258.77/3829.03	% SZS status Started for HL401913+5.p
21258.77/3829.03	% SZS status GaveUp for HL401913+5.p
21258.77/3829.03	% SZS status Ended for HL401913+5.p
21263.40/3829.52	% SZS status Started for HL401914+5.p
21263.40/3829.52	% SZS status Theorem for HL401914+5.p
21263.40/3829.52	% SZS status Ended for HL401914+5.p
21275.63/3830.97	% SZS status Started for HL401916+4.p
21275.63/3830.97	% SZS status GaveUp for HL401916+4.p
21275.63/3830.97	% SZS status Ended for HL401916+4.p
21285.66/3832.31	% SZS status Started for HL401917+5.p
21285.66/3832.31	% SZS status GaveUp for HL401917+5.p
21285.66/3832.31	% SZS status Ended for HL401917+5.p
21288.25/3832.58	% SZS status Started for HL401917+4.p
21288.25/3832.58	% SZS status GaveUp for HL401917+4.p
21288.25/3832.58	% SZS status Ended for HL401917+4.p
21304.29/3834.59	% SZS status Started for HL401918+5.p
21304.29/3834.59	% SZS status GaveUp for HL401918+5.p
21304.29/3834.59	% SZS status Ended for HL401918+5.p
21305.08/3834.68	% SZS status Started for HL401918+4.p
21305.08/3834.68	% SZS status GaveUp for HL401918+4.p
21305.08/3834.68	% SZS status Ended for HL401918+4.p
21315.66/3836.01	% SZS status Started for HL401921+4.p
21315.66/3836.01	% SZS status Theorem for HL401921+4.p
21315.66/3836.01	% SZS status Ended for HL401921+4.p
21315.66/3836.03	% SZS status Started for HL401919+4.p
21315.66/3836.03	% SZS status GaveUp for HL401919+4.p
21315.66/3836.03	% SZS status Ended for HL401919+4.p
21325.00/3837.23	% SZS status Started for HL401919+5.p
21325.00/3837.23	% SZS status GaveUp for HL401919+5.p
21325.00/3837.23	% SZS status Ended for HL401919+5.p
21331.47/3838.03	% SZS status Started for HL401920+4.p
21331.47/3838.03	% SZS status GaveUp for HL401920+4.p
21331.47/3838.03	% SZS status Ended for HL401920+4.p
21334.28/3838.36	% SZS status Started for HL401921+5.p
21334.28/3838.36	% SZS status Theorem for HL401921+5.p
21334.28/3838.36	% SZS status Ended for HL401921+5.p
21335.46/3838.59	% SZS status Started for HL401922+4.p
21335.46/3838.59	% SZS status Theorem for HL401922+4.p
21335.46/3838.59	% SZS status Ended for HL401922+4.p
21340.79/3839.19	% SZS status Started for HL401920+5.p
21340.79/3839.19	% SZS status GaveUp for HL401920+5.p
21340.79/3839.19	% SZS status Ended for HL401920+5.p
21370.13/3842.92	% SZS status Started for HL401922+5.p
21370.13/3842.92	% SZS status GaveUp for HL401922+5.p
21370.13/3842.92	% SZS status Ended for HL401922+5.p
21380.60/3844.30	% SZS status Started for HL401923+5.p
21380.60/3844.30	% SZS status GaveUp for HL401923+5.p
21380.60/3844.30	% SZS status Ended for HL401923+5.p
21381.23/3844.42	% SZS status Started for HL401923+4.p
21381.23/3844.42	% SZS status GaveUp for HL401923+4.p
21381.23/3844.42	% SZS status Ended for HL401923+4.p
21392.63/3845.75	% SZS status Started for HL401925+4.p
21392.63/3845.75	% SZS status GaveUp for HL401925+4.p
21392.63/3845.75	% SZS status Ended for HL401925+4.p
21396.69/3846.29	% SZS status Started for HL401925+5.p
21396.69/3846.29	% SZS status GaveUp for HL401925+5.p
21396.69/3846.29	% SZS status Ended for HL401925+5.p
21400.99/3846.84	% SZS status Started for HL401927+5.p
21400.99/3846.84	% SZS status GaveUp for HL401927+5.p
21400.99/3846.84	% SZS status Ended for HL401927+5.p
21401.53/3846.90	% SZS status Started for HL401927+4.p
21401.53/3846.90	% SZS status GaveUp for HL401927+4.p
21401.53/3846.90	% SZS status Ended for HL401927+4.p
21407.64/3847.74	% SZS status Started for HL401928+4.p
21407.64/3847.74	% SZS status GaveUp for HL401928+4.p
21407.64/3847.74	% SZS status Ended for HL401928+4.p
21435.90/3851.37	% SZS status Started for HL401928+5.p
21435.90/3851.37	% SZS status GaveUp for HL401928+5.p
21435.90/3851.37	% SZS status Ended for HL401928+5.p
21447.89/3852.70	% SZS status Started for HL401929+5.p
21447.89/3852.70	% SZS status GaveUp for HL401929+5.p
21447.89/3852.70	% SZS status Ended for HL401929+5.p
21449.21/3852.88	% SZS status Started for HL401929+4.p
21449.21/3852.88	% SZS status GaveUp for HL401929+4.p
21449.21/3852.88	% SZS status Ended for HL401929+4.p
21459.84/3854.17	% SZS status Started for HL401930+4.p
21459.84/3854.17	% SZS status GaveUp for HL401930+4.p
21459.84/3854.17	% SZS status Ended for HL401930+4.p
21462.36/3854.59	% SZS status Started for HL401930+5.p
21462.36/3854.59	% SZS status GaveUp for HL401930+5.p
21462.36/3854.59	% SZS status Ended for HL401930+5.p
21465.20/3854.84	% SZS status Started for HL401935+4.p
21465.20/3854.84	% SZS status Theorem for HL401935+4.p
21465.20/3854.84	% SZS status Ended for HL401935+4.p
21466.69/3855.11	% SZS status Started for HL401931+5.p
21466.69/3855.11	% SZS status GaveUp for HL401931+5.p
21466.69/3855.11	% SZS status Ended for HL401931+5.p
21467.11/3855.23	% SZS status Started for HL401931+4.p
21467.11/3855.23	% SZS status GaveUp for HL401931+4.p
21467.11/3855.23	% SZS status Ended for HL401931+4.p
21471.00/3855.60	% SZS status Started for HL401938+4.p
21471.00/3855.60	% SZS status Theorem for HL401938+4.p
21471.00/3855.60	% SZS status Ended for HL401938+4.p
21474.72/3856.08	% SZS status Started for HL401932+4.p
21474.72/3856.08	% SZS status GaveUp for HL401932+4.p
21474.72/3856.08	% SZS status Ended for HL401932+4.p
21477.81/3856.47	% SZS status Started for HL401938+5.p
21477.81/3856.47	% SZS status Theorem for HL401938+5.p
21477.81/3856.47	% SZS status Ended for HL401938+5.p
21502.23/3859.60	% SZS status Started for HL401932+5.p
21502.23/3859.60	% SZS status GaveUp for HL401932+5.p
21502.23/3859.60	% SZS status Ended for HL401932+5.p
21514.08/3861.04	% SZS status Started for HL401933+4.p
21514.08/3861.04	% SZS status GaveUp for HL401933+4.p
21514.08/3861.04	% SZS status Ended for HL401933+4.p
21514.29/3861.05	% SZS status Started for HL401933+5.p
21514.29/3861.05	% SZS status GaveUp for HL401933+5.p
21514.29/3861.05	% SZS status Ended for HL401933+5.p
21528.12/3862.77	% SZS status Started for HL401935+5.p
21528.12/3862.77	% SZS status GaveUp for HL401935+5.p
21528.12/3862.77	% SZS status Ended for HL401935+5.p
21532.13/3863.31	% SZS status Started for HL401936+5.p
21532.13/3863.31	% SZS status GaveUp for HL401936+5.p
21532.13/3863.31	% SZS status Ended for HL401936+5.p
21532.74/3863.35	% SZS status Started for HL401936+4.p
21532.74/3863.35	% SZS status GaveUp for HL401936+4.p
21532.74/3863.35	% SZS status Ended for HL401936+4.p
21543.33/3864.68	% SZS status Started for HL401939+4.p
21543.33/3864.68	% SZS status GaveUp for HL401939+4.p
21543.33/3864.68	% SZS status Ended for HL401939+4.p
21543.96/3864.76	% SZS status Started for HL401939+5.p
21543.96/3864.76	% SZS status GaveUp for HL401939+5.p
21543.96/3864.76	% SZS status Ended for HL401939+5.p
21570.41/3868.13	% SZS status Started for HL401940+4.p
21570.41/3868.13	% SZS status GaveUp for HL401940+4.p
21570.41/3868.13	% SZS status Ended for HL401940+4.p
21579.30/3869.22	% SZS status Started for HL401940+5.p
21579.30/3869.22	% SZS status GaveUp for HL401940+5.p
21579.30/3869.22	% SZS status Ended for HL401940+5.p
21581.75/3869.53	% SZS status Started for HL401941+4.p
21581.75/3869.53	% SZS status GaveUp for HL401941+4.p
21581.75/3869.53	% SZS status Ended for HL401941+4.p
21593.15/3871.00	% SZS status Started for HL401941+5.p
21593.15/3871.00	% SZS status GaveUp for HL401941+5.p
21593.15/3871.00	% SZS status Ended for HL401941+5.p
21597.69/3871.63	% SZS status Started for HL401943+5.p
21597.69/3871.63	% SZS status GaveUp for HL401943+5.p
21597.69/3871.63	% SZS status Ended for HL401943+5.p
21600.29/3871.85	% SZS status Started for HL401943+4.p
21600.29/3871.85	% SZS status GaveUp for HL401943+4.p
21600.29/3871.85	% SZS status Ended for HL401943+4.p
21608.61/3873.04	% SZS status Started for HL401944+5.p
21608.61/3873.04	% SZS status GaveUp for HL401944+5.p
21608.61/3873.04	% SZS status Ended for HL401944+5.p
21609.19/3873.10	% SZS status Started for HL401944+4.p
21609.19/3873.10	% SZS status GaveUp for HL401944+4.p
21609.19/3873.10	% SZS status Ended for HL401944+4.p
21638.76/3876.94	% SZS status Started for HL401945+4.p
21638.76/3876.94	% SZS status GaveUp for HL401945+4.p
21638.76/3876.94	% SZS status Ended for HL401945+4.p
21643.00/3877.46	% SZS status Started for HL401945+5.p
21643.00/3877.46	% SZS status GaveUp for HL401945+5.p
21643.00/3877.46	% SZS status Ended for HL401945+5.p
21647.79/3878.07	% SZS status Started for HL401948+4.p
21647.79/3878.07	% SZS status GaveUp for HL401948+4.p
21647.79/3878.07	% SZS status Ended for HL401948+4.p
21657.55/3879.38	% SZS status Started for HL401948+5.p
21657.55/3879.38	% SZS status GaveUp for HL401948+5.p
21657.55/3879.38	% SZS status Ended for HL401948+5.p
21667.58/3880.63	% SZS status Started for HL401949+5.p
21667.58/3880.63	% SZS status GaveUp for HL401949+5.p
21667.58/3880.63	% SZS status Ended for HL401949+5.p
21669.73/3880.85	% SZS status Started for HL401949+4.p
21669.73/3880.85	% SZS status GaveUp for HL401949+4.p
21669.73/3880.85	% SZS status Ended for HL401949+4.p
21675.41/3881.61	% SZS status Started for HL401950+4.p
21675.41/3881.61	% SZS status GaveUp for HL401950+4.p
21675.41/3881.61	% SZS status Ended for HL401950+4.p
21675.91/3881.67	% SZS status Started for HL401950+5.p
21675.91/3881.67	% SZS status GaveUp for HL401950+5.p
21675.91/3881.67	% SZS status Ended for HL401950+5.p
21705.71/3885.46	% SZS status Started for HL401952+4.p
21705.71/3885.46	% SZS status GaveUp for HL401952+4.p
21705.71/3885.46	% SZS status Ended for HL401952+4.p
21707.79/3885.74	% SZS status Started for HL401952+5.p
21707.79/3885.74	% SZS status GaveUp for HL401952+5.p
21707.79/3885.74	% SZS status Ended for HL401952+5.p
21717.00/3886.90	% SZS status Started for HL401953+4.p
21717.00/3886.90	% SZS status GaveUp for HL401953+4.p
21717.00/3886.90	% SZS status Ended for HL401953+4.p
21723.02/3887.62	% SZS status Started for HL401953+5.p
21723.02/3887.62	% SZS status GaveUp for HL401953+5.p
21723.02/3887.62	% SZS status Ended for HL401953+5.p
21733.97/3889.18	% SZS status Started for HL401954+5.p
21733.97/3889.18	% SZS status GaveUp for HL401954+5.p
21733.97/3889.18	% SZS status Ended for HL401954+5.p
21733.97/3889.18	% SZS status Started for HL401954+4.p
21733.97/3889.18	% SZS status GaveUp for HL401954+4.p
21733.97/3889.18	% SZS status Ended for HL401954+4.p
21740.62/3889.86	% SZS status Started for HL401955+5.p
21740.62/3889.86	% SZS status GaveUp for HL401955+5.p
21740.62/3889.86	% SZS status Ended for HL401955+5.p
21742.02/3890.15	% SZS status Started for HL401955+4.p
21742.02/3890.15	% SZS status GaveUp for HL401955+4.p
21742.02/3890.15	% SZS status Ended for HL401955+4.p
21772.46/3893.85	% SZS status Started for HL401956+4.p
21772.46/3893.85	% SZS status GaveUp for HL401956+4.p
21772.46/3893.85	% SZS status Ended for HL401956+4.p
21772.97/3893.94	% SZS status Started for HL401956+5.p
21772.97/3893.94	% SZS status GaveUp for HL401956+5.p
21772.97/3893.94	% SZS status Ended for HL401956+5.p
21783.42/3895.39	% SZS status Started for HL401957+4.p
21783.42/3895.39	% SZS status GaveUp for HL401957+4.p
21783.42/3895.39	% SZS status Ended for HL401957+4.p
21788.45/3895.95	% SZS status Started for HL401957+5.p
21788.45/3895.95	% SZS status GaveUp for HL401957+5.p
21788.45/3895.95	% SZS status Ended for HL401957+5.p
21801.42/3897.52	% SZS status Started for HL401959+5.p
21801.42/3897.52	% SZS status GaveUp for HL401959+5.p
21801.42/3897.52	% SZS status Ended for HL401959+5.p
21802.50/3897.74	% SZS status Started for HL401959+4.p
21802.50/3897.74	% SZS status GaveUp for HL401959+4.p
21802.50/3897.74	% SZS status Ended for HL401959+4.p
21807.96/3898.44	% SZS status Started for HL401960+5.p
21807.96/3898.44	% SZS status GaveUp for HL401960+5.p
21807.96/3898.44	% SZS status Ended for HL401960+5.p
21807.96/3898.46	% SZS status Started for HL401960+4.p
21807.96/3898.46	% SZS status GaveUp for HL401960+4.p
21807.96/3898.46	% SZS status Ended for HL401960+4.p
21841.95/3903.34	% SZS status Started for HL401961+5.p
21841.95/3903.34	% SZS status GaveUp for HL401961+5.p
21841.95/3903.34	% SZS status Ended for HL401961+5.p
21845.82/3904.15	% SZS status Started for HL401961+4.p
21845.82/3904.15	% SZS status GaveUp for HL401961+4.p
21845.82/3904.15	% SZS status Ended for HL401961+4.p
21856.49/3906.38	% SZS status Started for HL401963+4.p
21856.49/3906.38	% SZS status GaveUp for HL401963+4.p
21856.49/3906.38	% SZS status Ended for HL401963+4.p
21858.91/3906.82	% SZS status Started for HL401963+5.p
21858.91/3906.82	% SZS status GaveUp for HL401963+5.p
21858.91/3906.82	% SZS status Ended for HL401963+5.p
21862.10/3907.32	% SZS status Started for HL401964+5.p
21862.10/3907.32	% SZS status GaveUp for HL401964+5.p
21862.10/3907.32	% SZS status Ended for HL401964+5.p
21862.10/3907.35	% SZS status Started for HL401965+4.p
21862.10/3907.35	% SZS status GaveUp for HL401965+4.p
21862.10/3907.35	% SZS status Ended for HL401965+4.p
21863.56/3907.85	% SZS status Started for HL401965+5.p
21863.56/3907.85	% SZS status GaveUp for HL401965+5.p
21863.56/3907.85	% SZS status Ended for HL401965+5.p
21876.82/3910.60	% SZS status Started for HL401964+4.p
21876.82/3910.60	% SZS status GaveUp for HL401964+4.p
21876.82/3910.60	% SZS status Ended for HL401964+4.p
21894.84/3915.07	% SZS status Started for HL401966+4.p
21894.84/3915.07	% SZS status GaveUp for HL401966+4.p
21894.84/3915.07	% SZS status Ended for HL401966+4.p
21906.07/3917.09	% SZS status Started for HL401966+5.p
21906.07/3917.09	% SZS status GaveUp for HL401966+5.p
21906.07/3917.09	% SZS status Ended for HL401966+5.p
21918.25/3919.43	% SZS status Started for HL401967+4.p
21918.25/3919.43	% SZS status GaveUp for HL401967+4.p
21918.25/3919.43	% SZS status Ended for HL401967+4.p
21934.99/3923.03	% SZS status Started for HL401968+5.p
21934.99/3923.03	% SZS status GaveUp for HL401968+5.p
21934.99/3923.03	% SZS status Ended for HL401968+5.p
21935.66/3923.26	% SZS status Started for HL401968+4.p
21935.66/3923.26	% SZS status GaveUp for HL401968+4.p
21935.66/3923.26	% SZS status Ended for HL401968+4.p
21936.39/3923.56	% SZS status Started for HL401967+5.p
21936.39/3923.56	% SZS status GaveUp for HL401967+5.p
21936.39/3923.56	% SZS status Ended for HL401967+5.p
21942.92/3924.62	% SZS status Started for HL401969+4.p
21942.92/3924.62	% SZS status GaveUp for HL401969+4.p
21942.92/3924.62	% SZS status Ended for HL401969+4.p
21951.56/3926.21	% SZS status Started for HL401970+4.p
21951.56/3926.21	% SZS status GaveUp for HL401970+4.p
21951.56/3926.21	% SZS status Ended for HL401970+4.p
21952.56/3926.47	% SZS status Started for HL401969+5.p
21952.56/3926.47	% SZS status GaveUp for HL401969+5.p
21952.56/3926.47	% SZS status Ended for HL401969+5.p
21965.23/3928.93	% SZS status Started for HL401970+5.p
21965.23/3928.93	% SZS status GaveUp for HL401970+5.p
21965.23/3928.93	% SZS status Ended for HL401970+5.p
21986.76/3933.48	% SZS status Started for HL401971+4.p
21986.76/3933.48	% SZS status GaveUp for HL401971+4.p
21986.76/3933.48	% SZS status Ended for HL401971+4.p
22002.79/3936.49	% SZS status Started for HL401975+4.p
22002.79/3936.49	% SZS status GaveUp for HL401975+4.p
22002.79/3936.49	% SZS status Ended for HL401975+4.p
22002.79/3936.50	% SZS status Started for HL401971+5.p
22002.79/3936.50	% SZS status GaveUp for HL401971+5.p
22002.79/3936.50	% SZS status Ended for HL401971+5.p
22004.46/3936.90	% SZS status Started for HL401972+5.p
22004.46/3936.90	% SZS status GaveUp for HL401972+5.p
22004.46/3936.90	% SZS status Ended for HL401972+5.p
22015.48/3939.37	% SZS status Started for HL401973+4.p
22015.48/3939.37	% SZS status GaveUp for HL401973+4.p
22015.48/3939.37	% SZS status Ended for HL401973+4.p
22015.48/3939.38	% SZS status Started for HL401972+4.p
22015.48/3939.38	% SZS status GaveUp for HL401972+4.p
22015.48/3939.38	% SZS status Ended for HL401972+4.p
22018.38/3940.06	% SZS status Started for HL401973+5.p
22018.38/3940.06	% SZS status GaveUp for HL401973+5.p
22018.38/3940.06	% SZS status Ended for HL401973+5.p
22040.68/3943.49	% SZS status Started for HL401975+5.p
22040.68/3943.49	% SZS status GaveUp for HL401975+5.p
22040.68/3943.49	% SZS status Ended for HL401975+5.p
22064.47/3946.56	% SZS status Started for HL401977+5.p
22064.47/3946.56	% SZS status GaveUp for HL401977+5.p
22064.47/3946.56	% SZS status Ended for HL401977+5.p
22065.85/3946.70	% SZS status Started for HL401976+4.p
22065.85/3946.70	% SZS status GaveUp for HL401976+4.p
22065.85/3946.70	% SZS status Ended for HL401976+4.p
22066.60/3946.82	% SZS status Started for HL401977+4.p
22066.60/3946.82	% SZS status GaveUp for HL401977+4.p
22066.60/3946.82	% SZS status Ended for HL401977+4.p
22069.67/3947.26	% SZS status Started for HL401976+5.p
22069.67/3947.26	% SZS status GaveUp for HL401976+5.p
22069.67/3947.26	% SZS status Ended for HL401976+5.p
22076.91/3948.25	% SZS status Started for HL401978+5.p
22076.91/3948.25	% SZS status GaveUp for HL401978+5.p
22076.91/3948.25	% SZS status Ended for HL401978+5.p
22083.88/3949.10	% SZS status Started for HL401978+4.p
22083.88/3949.10	% SZS status GaveUp for HL401978+4.p
22083.88/3949.10	% SZS status Ended for HL401978+4.p
22088.98/3949.74	% SZS status Started for HL401979+4.p
22088.98/3949.74	% SZS status GaveUp for HL401979+4.p
22088.98/3949.74	% SZS status Ended for HL401979+4.p
22107.79/3952.16	% SZS status Started for HL401979+5.p
22107.79/3952.16	% SZS status GaveUp for HL401979+5.p
22107.79/3952.16	% SZS status Ended for HL401979+5.p
22129.98/3955.17	% SZS status Started for HL401980+5.p
22129.98/3955.17	% SZS status GaveUp for HL401980+5.p
22129.98/3955.17	% SZS status Ended for HL401980+5.p
22132.49/3955.38	% SZS status Started for HL401980+4.p
22132.49/3955.38	% SZS status GaveUp for HL401980+4.p
22132.49/3955.38	% SZS status Ended for HL401980+4.p
22133.40/3955.54	% SZS status Started for HL401981+4.p
22133.40/3955.54	% SZS status GaveUp for HL401981+4.p
22133.40/3955.54	% SZS status Ended for HL401981+4.p
22135.61/3955.79	% SZS status Started for HL401981+5.p
22135.61/3955.79	% SZS status GaveUp for HL401981+5.p
22135.61/3955.79	% SZS status Ended for HL401981+5.p
22144.17/3956.93	% SZS status Started for HL401982+4.p
22144.17/3956.93	% SZS status GaveUp for HL401982+4.p
22144.17/3956.93	% SZS status Ended for HL401982+4.p
22150.25/3957.72	% SZS status Started for HL401982+5.p
22150.25/3957.72	% SZS status GaveUp for HL401982+5.p
22150.25/3957.72	% SZS status Ended for HL401982+5.p
22157.67/3958.69	% SZS status Started for HL401983+4.p
22157.67/3958.69	% SZS status GaveUp for HL401983+4.p
22157.67/3958.69	% SZS status Ended for HL401983+4.p
22171.60/3960.59	% SZS status Started for HL401983+5.p
22171.60/3960.59	% SZS status GaveUp for HL401983+5.p
22171.60/3960.59	% SZS status Ended for HL401983+5.p
22194.22/3963.57	% SZS status Started for HL401984+5.p
22194.22/3963.57	% SZS status GaveUp for HL401984+5.p
22194.22/3963.57	% SZS status Ended for HL401984+5.p
22201.29/3964.34	% SZS status Started for HL401985+4.p
22201.29/3964.34	% SZS status GaveUp for HL401985+4.p
22201.29/3964.34	% SZS status Ended for HL401985+4.p
22202.19/3964.44	% SZS status Started for HL401984+4.p
22202.19/3964.44	% SZS status GaveUp for HL401984+4.p
22202.19/3964.44	% SZS status Ended for HL401984+4.p
22202.97/3964.66	% SZS status Started for HL401985+5.p
22202.97/3964.66	% SZS status GaveUp for HL401985+5.p
22202.97/3964.66	% SZS status Ended for HL401985+5.p
22210.49/3965.51	% SZS status Started for HL401986+4.p
22210.49/3965.51	% SZS status GaveUp for HL401986+4.p
22210.49/3965.51	% SZS status Ended for HL401986+4.p
22215.21/3966.08	% SZS status Started for HL401986+5.p
22215.21/3966.08	% SZS status GaveUp for HL401986+5.p
22215.21/3966.08	% SZS status Ended for HL401986+5.p
22225.25/3967.34	% SZS status Started for HL401987+4.p
22225.25/3967.34	% SZS status GaveUp for HL401987+4.p
22225.25/3967.34	% SZS status Ended for HL401987+4.p
22238.30/3969.05	% SZS status Started for HL401987+5.p
22238.30/3969.05	% SZS status GaveUp for HL401987+5.p
22238.30/3969.05	% SZS status Ended for HL401987+5.p
22262.37/3971.95	% SZS status Started for HL401988+4.p
22262.37/3971.95	% SZS status GaveUp for HL401988+4.p
22262.37/3971.95	% SZS status Ended for HL401988+4.p
22267.55/3972.57	% SZS status Started for HL401988+5.p
22267.55/3972.57	% SZS status GaveUp for HL401988+5.p
22267.55/3972.57	% SZS status Ended for HL401988+5.p
22269.69/3972.94	% SZS status Started for HL401989+4.p
22269.69/3972.94	% SZS status GaveUp for HL401989+4.p
22269.69/3972.94	% SZS status Ended for HL401989+4.p
22271.54/3973.09	% SZS status Started for HL401989+5.p
22271.54/3973.09	% SZS status GaveUp for HL401989+5.p
22271.54/3973.09	% SZS status Ended for HL401989+5.p
22277.63/3973.87	% SZS status Started for HL401991+4.p
22277.63/3973.87	% SZS status GaveUp for HL401991+4.p
22277.63/3973.87	% SZS status Ended for HL401991+4.p
22280.94/3974.27	% SZS status Started for HL401991+5.p
22280.94/3974.27	% SZS status GaveUp for HL401991+5.p
22280.94/3974.27	% SZS status Ended for HL401991+5.p
22293.73/3975.88	% SZS status Started for HL401992+4.p
22293.73/3975.88	% SZS status GaveUp for HL401992+4.p
22293.73/3975.88	% SZS status Ended for HL401992+4.p
22304.86/3977.29	% SZS status Started for HL401992+5.p
22304.86/3977.29	% SZS status GaveUp for HL401992+5.p
22304.86/3977.29	% SZS status Ended for HL401992+5.p
22329.52/3980.44	% SZS status Started for HL401993+4.p
22329.52/3980.44	% SZS status GaveUp for HL401993+4.p
22329.52/3980.44	% SZS status Ended for HL401993+4.p
22333.23/3980.90	% SZS status Started for HL401993+5.p
22333.23/3980.90	% SZS status GaveUp for HL401993+5.p
22333.23/3980.90	% SZS status Ended for HL401993+5.p
22334.42/3981.02	% SZS status Started for HL401998+4.p
22334.42/3981.02	% SZS status Theorem for HL401998+4.p
22334.42/3981.02	% SZS status Ended for HL401998+4.p
22336.54/3981.33	% SZS status Started for HL401995+5.p
22336.54/3981.33	% SZS status GaveUp for HL401995+5.p
22336.54/3981.33	% SZS status Ended for HL401995+5.p
22337.36/3981.43	% SZS status Started for HL401995+4.p
22337.36/3981.43	% SZS status GaveUp for HL401995+4.p
22337.36/3981.43	% SZS status Ended for HL401995+4.p
22345.70/3982.43	% SZS status Started for HL401996+4.p
22345.70/3982.43	% SZS status GaveUp for HL401996+4.p
22345.70/3982.43	% SZS status Ended for HL401996+4.p
22345.70/3982.47	% SZS status Started for HL401996+5.p
22345.70/3982.47	% SZS status GaveUp for HL401996+5.p
22345.70/3982.47	% SZS status Ended for HL401996+5.p
22359.93/3984.26	% SZS status Started for HL402001+5.p
22359.93/3984.26	% SZS status Theorem for HL402001+5.p
22359.93/3984.26	% SZS status Ended for HL402001+5.p
22361.00/3984.38	% SZS status Started for HL401997+4.p
22361.00/3984.38	% SZS status GaveUp for HL401997+4.p
22361.00/3984.38	% SZS status Ended for HL401997+4.p
22369.73/3985.51	% SZS status Started for HL401997+5.p
22369.73/3985.51	% SZS status GaveUp for HL401997+5.p
22369.73/3985.51	% SZS status Ended for HL401997+5.p
22373.12/3986.09	% SZS status Started for HL402002+5.p
22373.12/3986.09	% SZS status Theorem for HL402002+5.p
22373.12/3986.09	% SZS status Ended for HL402002+5.p
22373.44/3986.18	% SZS status Started for HL402003+5.p
22373.44/3986.18	% SZS status Theorem for HL402003+5.p
22373.44/3986.18	% SZS status Ended for HL402003+5.p
22377.89/3986.62	% SZS status Started for HL402003+4.p
22377.89/3986.62	% SZS status Theorem for HL402003+4.p
22377.89/3986.62	% SZS status Ended for HL402003+4.p
22380.98/3986.96	% SZS status Started for HL402004+5.p
22380.98/3986.96	% SZS status Theorem for HL402004+5.p
22380.98/3986.96	% SZS status Ended for HL402004+5.p
22387.22/3987.77	% SZS status Started for HL402005+5.p
22387.22/3987.77	% SZS status Theorem for HL402005+5.p
22387.22/3987.77	% SZS status Ended for HL402005+5.p
22395.38/3988.78	% SZS status Started for HL402002+4.p
22395.38/3988.78	% SZS status Theorem for HL402002+4.p
22395.38/3988.78	% SZS status Ended for HL402002+4.p
22396.08/3988.93	% SZS status Started for HL402005+4.p
22396.08/3988.93	% SZS status Theorem for HL402005+4.p
22396.08/3988.93	% SZS status Ended for HL402005+4.p
22399.23/3989.23	% SZS status Started for HL401998+5.p
22399.23/3989.23	% SZS status GaveUp for HL401998+5.p
22399.23/3989.23	% SZS status Ended for HL401998+5.p
22400.53/3989.62	% SZS status Started for HL402000+5.p
22400.53/3989.62	% SZS status GaveUp for HL402000+5.p
22400.53/3989.62	% SZS status Ended for HL402000+5.p
22403.89/3989.83	% SZS status Started for HL402000+4.p
22403.89/3989.83	% SZS status GaveUp for HL402000+4.p
22403.89/3989.83	% SZS status Ended for HL402000+4.p
22405.83/3990.17	% SZS status Started for HL402001+4.p
22405.83/3990.17	% SZS status GaveUp for HL402001+4.p
22405.83/3990.17	% SZS status Ended for HL402001+4.p
22442.29/3994.63	% SZS status Started for HL402004+4.p
22442.29/3994.63	% SZS status GaveUp for HL402004+4.p
22442.29/3994.63	% SZS status Ended for HL402004+4.p
22455.44/3996.28	% SZS status Started for HL402006+4.p
22455.44/3996.28	% SZS status GaveUp for HL402006+4.p
22455.44/3996.28	% SZS status Ended for HL402006+4.p
22460.57/3996.98	% SZS status Started for HL402006+5.p
22460.57/3996.98	% SZS status GaveUp for HL402006+5.p
22460.57/3996.98	% SZS status Ended for HL402006+5.p
22463.42/3997.42	% SZS status Started for HL402007+5.p
22463.42/3997.42	% SZS status GaveUp for HL402007+5.p
22463.42/3997.42	% SZS status Ended for HL402007+5.p
22464.05/3997.52	% SZS status Started for HL402007+4.p
22464.05/3997.52	% SZS status GaveUp for HL402007+4.p
22464.05/3997.52	% SZS status Ended for HL402007+4.p
22467.82/3998.04	% SZS status Started for HL402008+4.p
22467.82/3998.04	% SZS status GaveUp for HL402008+4.p
22467.82/3998.04	% SZS status Ended for HL402008+4.p
22468.08/3998.17	% SZS status Started for HL402008+5.p
22468.08/3998.17	% SZS status GaveUp for HL402008+5.p
22468.08/3998.17	% SZS status Ended for HL402008+5.p
22473.69/3998.69	% SZS status Started for HL402009+4.p
22473.69/3998.69	% SZS status GaveUp for HL402009+4.p
22473.69/3998.69	% SZS status Ended for HL402009+4.p
22507.47/4002.80	% SZS status Started for HL402009+5.p
22507.47/4002.80	% SZS status GaveUp for HL402009+5.p
22507.47/4002.80	% SZS status Ended for HL402009+5.p
22523.45/4004.89	% SZS status Started for HL402010+4.p
22523.45/4004.89	% SZS status GaveUp for HL402010+4.p
22523.45/4004.89	% SZS status Ended for HL402010+4.p
22526.44/4005.22	% SZS status Started for HL402010+5.p
22526.44/4005.22	% SZS status GaveUp for HL402010+5.p
22526.44/4005.22	% SZS status Ended for HL402010+5.p
22530.62/4005.76	% SZS status Started for HL402011+5.p
22530.62/4005.76	% SZS status GaveUp for HL402011+5.p
22530.62/4005.76	% SZS status Ended for HL402011+5.p
22531.97/4005.92	% SZS status Started for HL402011+4.p
22531.97/4005.92	% SZS status GaveUp for HL402011+4.p
22531.97/4005.92	% SZS status Ended for HL402011+4.p
22535.61/4006.36	% SZS status Started for HL402012+5.p
22535.61/4006.36	% SZS status GaveUp for HL402012+5.p
22535.61/4006.36	% SZS status Ended for HL402012+5.p
22535.61/4006.45	% SZS status Started for HL402012+4.p
22535.61/4006.45	% SZS status GaveUp for HL402012+4.p
22535.61/4006.45	% SZS status Ended for HL402012+4.p
22542.15/4007.29	% SZS status Started for HL402017+4.p
22542.15/4007.29	% SZS status GaveUp for HL402017+4.p
22542.15/4007.29	% SZS status Ended for HL402017+4.p
22572.34/4011.06	% SZS status Started for HL402017+5.p
22572.34/4011.06	% SZS status GaveUp for HL402017+5.p
22572.34/4011.06	% SZS status Ended for HL402017+5.p
22590.49/4013.29	% SZS status Started for HL402018+4.p
22590.49/4013.29	% SZS status GaveUp for HL402018+4.p
22590.49/4013.29	% SZS status Ended for HL402018+4.p
22590.89/4013.39	% SZS status Started for HL402018+5.p
22590.89/4013.39	% SZS status GaveUp for HL402018+5.p
22590.89/4013.39	% SZS status Ended for HL402018+5.p
22597.33/4014.10	% SZS status Started for HL402019+5.p
22597.33/4014.10	% SZS status GaveUp for HL402019+5.p
22597.33/4014.10	% SZS status Ended for HL402019+5.p
22598.43/4014.23	% SZS status Started for HL402019+4.p
22598.43/4014.23	% SZS status GaveUp for HL402019+4.p
22598.43/4014.23	% SZS status Ended for HL402019+4.p
22601.55/4014.66	% SZS status Started for HL402020+5.p
22601.55/4014.66	% SZS status GaveUp for HL402020+5.p
22601.55/4014.66	% SZS status Ended for HL402020+5.p
22602.72/4014.80	% SZS status Started for HL402020+4.p
22602.72/4014.80	% SZS status GaveUp for HL402020+4.p
22602.72/4014.80	% SZS status Ended for HL402020+4.p
22609.98/4015.88	% SZS status Started for HL402021+4.p
22609.98/4015.88	% SZS status GaveUp for HL402021+4.p
22609.98/4015.88	% SZS status Ended for HL402021+4.p
22623.90/4017.57	% SZS status Started for HL402024+4.p
22623.90/4017.57	% SZS status Theorem for HL402024+4.p
22623.90/4017.57	% SZS status Ended for HL402024+4.p
22637.34/4019.28	% SZS status Started for HL402021+5.p
22637.34/4019.28	% SZS status GaveUp for HL402021+5.p
22637.34/4019.28	% SZS status Ended for HL402021+5.p
22656.69/4021.61	% SZS status Started for HL402023+5.p
22656.69/4021.61	% SZS status GaveUp for HL402023+5.p
22656.69/4021.61	% SZS status Ended for HL402023+5.p
22659.37/4021.91	% SZS status Started for HL402023+4.p
22659.37/4021.91	% SZS status GaveUp for HL402023+4.p
22659.37/4021.91	% SZS status Ended for HL402023+4.p
22664.26/4022.54	% SZS status Started for HL402024+5.p
22664.26/4022.54	% SZS status GaveUp for HL402024+5.p
22664.26/4022.54	% SZS status Ended for HL402024+5.p
22667.91/4023.10	% SZS status Started for HL402025+5.p
22667.91/4023.10	% SZS status GaveUp for HL402025+5.p
22667.91/4023.10	% SZS status Ended for HL402025+5.p
22669.20/4023.20	% SZS status Started for HL402025+4.p
22669.20/4023.20	% SZS status GaveUp for HL402025+4.p
22669.20/4023.20	% SZS status Ended for HL402025+4.p
22678.32/4024.35	% SZS status Started for HL402026+4.p
22678.32/4024.35	% SZS status GaveUp for HL402026+4.p
22678.32/4024.35	% SZS status Ended for HL402026+4.p
22690.26/4025.82	% SZS status Started for HL402026+5.p
22690.26/4025.82	% SZS status GaveUp for HL402026+5.p
22690.26/4025.82	% SZS status Ended for HL402026+5.p
22707.50/4028.05	% SZS status Started for HL402027+4.p
22707.50/4028.05	% SZS status GaveUp for HL402027+4.p
22707.50/4028.05	% SZS status Ended for HL402027+4.p
22724.43/4030.15	% SZS status Started for HL402027+5.p
22724.43/4030.15	% SZS status GaveUp for HL402027+5.p
22724.43/4030.15	% SZS status Ended for HL402027+5.p
22728.28/4030.62	% SZS status Started for HL402028+4.p
22728.28/4030.62	% SZS status GaveUp for HL402028+4.p
22728.28/4030.62	% SZS status Ended for HL402028+4.p
22729.34/4030.86	% SZS status Started for HL402028+5.p
22729.34/4030.86	% SZS status GaveUp for HL402028+5.p
22729.34/4030.86	% SZS status Ended for HL402028+5.p
22735.25/4031.49	% SZS status Started for HL402029+5.p
22735.25/4031.49	% SZS status GaveUp for HL402029+5.p
22735.25/4031.49	% SZS status Ended for HL402029+5.p
22736.69/4031.75	% SZS status Started for HL402029+4.p
22736.69/4031.75	% SZS status GaveUp for HL402029+4.p
22736.69/4031.75	% SZS status Ended for HL402029+4.p
22746.93/4033.08	% SZS status Started for HL402030+4.p
22746.93/4033.08	% SZS status GaveUp for HL402030+4.p
22746.93/4033.08	% SZS status Ended for HL402030+4.p
22755.58/4034.14	% SZS status Started for HL402030+5.p
22755.58/4034.14	% SZS status GaveUp for HL402030+5.p
22755.58/4034.14	% SZS status Ended for HL402030+5.p
22776.85/4036.76	% SZS status Started for HL402031+4.p
22776.85/4036.76	% SZS status GaveUp for HL402031+4.p
22776.85/4036.76	% SZS status Ended for HL402031+4.p
22789.82/4038.35	% SZS status Started for HL402031+5.p
22789.82/4038.35	% SZS status GaveUp for HL402031+5.p
22789.82/4038.35	% SZS status Ended for HL402031+5.p
22795.11/4039.05	% SZS status Started for HL402032+4.p
22795.11/4039.05	% SZS status GaveUp for HL402032+4.p
22795.11/4039.05	% SZS status Ended for HL402032+4.p
22796.16/4039.17	% SZS status Started for HL402032+5.p
22796.16/4039.17	% SZS status GaveUp for HL402032+5.p
22796.16/4039.17	% SZS status Ended for HL402032+5.p
22802.68/4039.97	% SZS status Started for HL402033+4.p
22802.68/4039.97	% SZS status GaveUp for HL402033+4.p
22802.68/4039.97	% SZS status Ended for HL402033+4.p
22802.97/4039.99	% SZS status Started for HL402033+5.p
22802.97/4039.99	% SZS status GaveUp for HL402033+5.p
22802.97/4039.99	% SZS status Ended for HL402033+5.p
22815.29/4041.56	% SZS status Started for HL402034+4.p
22815.29/4041.56	% SZS status GaveUp for HL402034+4.p
22815.29/4041.56	% SZS status Ended for HL402034+4.p
22821.63/4042.51	% SZS status Started for HL402034+5.p
22821.63/4042.51	% SZS status GaveUp for HL402034+5.p
22821.63/4042.51	% SZS status Ended for HL402034+5.p
22843.72/4045.17	% SZS status Started for HL402036+4.p
22843.72/4045.17	% SZS status GaveUp for HL402036+4.p
22843.72/4045.17	% SZS status Ended for HL402036+4.p
22855.17/4046.60	% SZS status Started for HL402036+5.p
22855.17/4046.60	% SZS status GaveUp for HL402036+5.p
22855.17/4046.60	% SZS status Ended for HL402036+5.p
22861.41/4047.37	% SZS status Started for HL402037+5.p
22861.41/4047.37	% SZS status GaveUp for HL402037+5.p
22861.41/4047.37	% SZS status Ended for HL402037+5.p
22861.89/4047.44	% SZS status Started for HL402037+4.p
22861.89/4047.44	% SZS status GaveUp for HL402037+4.p
22861.89/4047.44	% SZS status Ended for HL402037+4.p
22867.53/4048.20	% SZS status Started for HL402038+5.p
22867.53/4048.20	% SZS status GaveUp for HL402038+5.p
22867.53/4048.20	% SZS status Ended for HL402038+5.p
22869.63/4048.38	% SZS status Started for HL402038+4.p
22869.63/4048.38	% SZS status GaveUp for HL402038+4.p
22869.63/4048.38	% SZS status Ended for HL402038+4.p
22883.12/4050.15	% SZS status Started for HL402039+4.p
22883.12/4050.15	% SZS status GaveUp for HL402039+4.p
22883.12/4050.15	% SZS status Ended for HL402039+4.p
22887.27/4050.73	% SZS status Started for HL402039+5.p
22887.27/4050.73	% SZS status GaveUp for HL402039+5.p
22887.27/4050.73	% SZS status Ended for HL402039+5.p
22913.52/4054.80	% SZS status Started for HL402040+4.p
22913.52/4054.80	% SZS status GaveUp for HL402040+4.p
22913.52/4054.80	% SZS status Ended for HL402040+4.p
22918.05/4055.32	% SZS status Started for HL402040+5.p
22918.05/4055.32	% SZS status GaveUp for HL402040+5.p
22918.05/4055.32	% SZS status Ended for HL402040+5.p
22927.93/4056.61	% SZS status Started for HL402041+4.p
22927.93/4056.61	% SZS status GaveUp for HL402041+4.p
22927.93/4056.61	% SZS status Ended for HL402041+4.p
22929.68/4056.78	% SZS status Started for HL402041+5.p
22929.68/4056.78	% SZS status GaveUp for HL402041+5.p
22929.68/4056.78	% SZS status Ended for HL402041+5.p
22931.51/4057.06	% SZS status Started for HL402042+4.p
22931.51/4057.06	% SZS status GaveUp for HL402042+4.p
22931.51/4057.06	% SZS status Ended for HL402042+4.p
22936.41/4057.66	% SZS status Started for HL402042+5.p
22936.41/4057.66	% SZS status GaveUp for HL402042+5.p
22936.41/4057.66	% SZS status Ended for HL402042+5.p
22953.23/4059.73	% SZS status Started for HL402043+5.p
22953.23/4059.73	% SZS status GaveUp for HL402043+5.p
22953.23/4059.73	% SZS status Ended for HL402043+5.p
22954.67/4059.94	% SZS status Started for HL402043+4.p
22954.67/4059.94	% SZS status GaveUp for HL402043+4.p
22954.67/4059.94	% SZS status Ended for HL402043+4.p
22980.88/4063.23	% SZS status Started for HL402044+4.p
22980.88/4063.23	% SZS status GaveUp for HL402044+4.p
22980.88/4063.23	% SZS status Ended for HL402044+4.p
22982.96/4063.52	% SZS status Started for HL402044+5.p
22982.96/4063.52	% SZS status GaveUp for HL402044+5.p
22982.96/4063.52	% SZS status Ended for HL402044+5.p
22995.22/4065.01	% SZS status Started for HL402046+5.p
22995.22/4065.01	% SZS status GaveUp for HL402046+5.p
22995.22/4065.01	% SZS status Ended for HL402046+5.p
22995.22/4065.03	% SZS status Started for HL402046+4.p
22995.22/4065.03	% SZS status GaveUp for HL402046+4.p
22995.22/4065.03	% SZS status Ended for HL402046+4.p
22998.77/4065.48	% SZS status Started for HL402047+4.p
22998.77/4065.48	% SZS status GaveUp for HL402047+4.p
22998.77/4065.48	% SZS status Ended for HL402047+4.p
23001.87/4065.97	% SZS status Started for HL402047+5.p
23001.87/4065.97	% SZS status GaveUp for HL402047+5.p
23001.87/4065.97	% SZS status Ended for HL402047+5.p
23020.02/4068.18	% SZS status Started for HL402048+5.p
23020.02/4068.18	% SZS status GaveUp for HL402048+5.p
23020.02/4068.18	% SZS status Ended for HL402048+5.p
23020.02/4068.19	% SZS status Started for HL402048+4.p
23020.02/4068.19	% SZS status GaveUp for HL402048+4.p
23020.02/4068.19	% SZS status Ended for HL402048+4.p
23047.62/4071.66	% SZS status Started for HL402050+4.p
23047.62/4071.66	% SZS status GaveUp for HL402050+4.p
23047.62/4071.66	% SZS status Ended for HL402050+4.p
23047.62/4071.72	% SZS status Started for HL402050+5.p
23047.62/4071.72	% SZS status GaveUp for HL402050+5.p
23047.62/4071.72	% SZS status Ended for HL402050+5.p
23059.61/4073.22	% SZS status Started for HL402051+5.p
23059.61/4073.22	% SZS status GaveUp for HL402051+5.p
23059.61/4073.22	% SZS status Ended for HL402051+5.p
23060.44/4073.46	% SZS status Started for HL402051+4.p
23060.44/4073.46	% SZS status GaveUp for HL402051+4.p
23060.44/4073.46	% SZS status Ended for HL402051+4.p
23065.26/4073.98	% SZS status Started for HL402052+4.p
23065.26/4073.98	% SZS status GaveUp for HL402052+4.p
23065.26/4073.98	% SZS status Ended for HL402052+4.p
23067.65/4074.16	% SZS status Started for HL402052+5.p
23067.65/4074.16	% SZS status GaveUp for HL402052+5.p
23067.65/4074.16	% SZS status Ended for HL402052+5.p
23086.08/4076.51	% SZS status Started for HL402053+5.p
23086.08/4076.51	% SZS status GaveUp for HL402053+5.p
23086.08/4076.51	% SZS status Ended for HL402053+5.p
23087.39/4076.76	% SZS status Started for HL402053+4.p
23087.39/4076.76	% SZS status GaveUp for HL402053+4.p
23087.39/4076.76	% SZS status Ended for HL402053+4.p
23113.41/4079.90	% SZS status Started for HL402054+5.p
23113.41/4079.90	% SZS status GaveUp for HL402054+5.p
23113.41/4079.90	% SZS status Ended for HL402054+5.p
23114.47/4080.09	% SZS status Started for HL402054+4.p
23114.47/4080.09	% SZS status GaveUp for HL402054+4.p
23114.47/4080.09	% SZS status Ended for HL402054+4.p
23127.42/4081.66	% SZS status Started for HL402056+4.p
23127.42/4081.66	% SZS status GaveUp for HL402056+4.p
23127.42/4081.66	% SZS status Ended for HL402056+4.p
23127.42/4081.66	% SZS status Started for HL402056+5.p
23127.42/4081.66	% SZS status GaveUp for HL402056+5.p
23127.42/4081.66	% SZS status Ended for HL402056+5.p
23133.18/4082.38	% SZS status Started for HL402057+4.p
23133.18/4082.38	% SZS status GaveUp for HL402057+4.p
23133.18/4082.38	% SZS status Ended for HL402057+4.p
23133.67/4082.45	% SZS status Started for HL402057+5.p
23133.67/4082.45	% SZS status GaveUp for HL402057+5.p
23133.67/4082.45	% SZS status Ended for HL402057+5.p
23153.62/4084.93	% SZS status Started for HL402058+4.p
23153.62/4084.93	% SZS status GaveUp for HL402058+4.p
23153.62/4084.93	% SZS status Ended for HL402058+4.p
23153.93/4085.01	% SZS status Started for HL402058+5.p
23153.93/4085.01	% SZS status GaveUp for HL402058+5.p
23153.93/4085.01	% SZS status Ended for HL402058+5.p
23180.20/4088.30	% SZS status Started for HL402059+5.p
23180.20/4088.30	% SZS status GaveUp for HL402059+5.p
23180.20/4088.30	% SZS status Ended for HL402059+5.p
23180.74/4088.35	% SZS status Started for HL402059+4.p
23180.74/4088.35	% SZS status GaveUp for HL402059+4.p
23180.74/4088.35	% SZS status Ended for HL402059+4.p
23193.66/4089.95	% SZS status Started for HL402060+5.p
23193.66/4089.95	% SZS status GaveUp for HL402060+5.p
23193.66/4089.95	% SZS status Ended for HL402060+5.p
23194.78/4090.11	% SZS status Started for HL402060+4.p
23194.78/4090.11	% SZS status GaveUp for HL402060+4.p
23194.78/4090.11	% SZS status Ended for HL402060+4.p
23199.13/4090.68	% SZS status Started for HL402061+5.p
23199.13/4090.68	% SZS status GaveUp for HL402061+5.p
23199.13/4090.68	% SZS status Ended for HL402061+5.p
23200.01/4090.80	% SZS status Started for HL402061+4.p
23200.01/4090.80	% SZS status GaveUp for HL402061+4.p
23200.01/4090.80	% SZS status Ended for HL402061+4.p
23219.25/4093.24	% SZS status Started for HL402062+5.p
23219.25/4093.24	% SZS status GaveUp for HL402062+5.p
23219.25/4093.24	% SZS status Ended for HL402062+5.p
23220.62/4093.37	% SZS status Started for HL402062+4.p
23220.62/4093.37	% SZS status GaveUp for HL402062+4.p
23220.62/4093.37	% SZS status Ended for HL402062+4.p
23245.52/4096.54	% SZS status Started for HL402063+5.p
23245.52/4096.54	% SZS status GaveUp for HL402063+5.p
23245.52/4096.54	% SZS status Ended for HL402063+5.p
23247.79/4096.74	% SZS status Started for HL402063+4.p
23247.79/4096.74	% SZS status GaveUp for HL402063+4.p
23247.79/4096.74	% SZS status Ended for HL402063+4.p
23260.63/4098.36	% SZS status Started for HL402064+5.p
23260.63/4098.36	% SZS status GaveUp for HL402064+5.p
23260.63/4098.36	% SZS status Ended for HL402064+5.p
23260.94/4098.42	% SZS status Started for HL402064+4.p
23260.94/4098.42	% SZS status GaveUp for HL402064+4.p
23260.94/4098.42	% SZS status Ended for HL402064+4.p
23265.44/4099.01	% SZS status Started for HL402065+5.p
23265.44/4099.01	% SZS status GaveUp for HL402065+5.p
23265.44/4099.01	% SZS status Ended for HL402065+5.p
23265.89/4099.10	% SZS status Started for HL402065+4.p
23265.89/4099.10	% SZS status GaveUp for HL402065+4.p
23265.89/4099.10	% SZS status Ended for HL402065+4.p
23286.91/4101.68	% SZS status Started for HL402066+4.p
23286.91/4101.68	% SZS status GaveUp for HL402066+4.p
23286.91/4101.68	% SZS status Ended for HL402066+4.p
23286.91/4101.68	% SZS status Started for HL402066+5.p
23286.91/4101.68	% SZS status GaveUp for HL402066+5.p
23286.91/4101.68	% SZS status Ended for HL402066+5.p
23288.27/4102.02	% SZS status Started for HL402071+4.p
23288.27/4102.02	% SZS status Theorem for HL402071+4.p
23288.27/4102.02	% SZS status Ended for HL402071+4.p
23291.32/4102.24	% SZS status Started for HL402071+5.p
23291.32/4102.24	% SZS status Theorem for HL402071+5.p
23291.32/4102.24	% SZS status Ended for HL402071+5.p
23311.66/4104.95	% SZS status Started for HL402067+4.p
23311.66/4104.95	% SZS status GaveUp for HL402067+4.p
23311.66/4104.95	% SZS status Ended for HL402067+4.p
23313.12/4104.99	% SZS status Started for HL402067+5.p
23313.12/4104.99	% SZS status GaveUp for HL402067+5.p
23313.12/4104.99	% SZS status Ended for HL402067+5.p
23314.94/4105.27	% SZS status Started for HL402074+5.p
23314.94/4105.27	% SZS status Theorem for HL402074+5.p
23314.94/4105.27	% SZS status Ended for HL402074+5.p
23320.70/4106.02	% SZS status Started for HL402074+4.p
23320.70/4106.02	% SZS status Theorem for HL402074+4.p
23320.70/4106.02	% SZS status Ended for HL402074+4.p
23324.49/4106.50	% SZS status Started for HL402075+5.p
23324.49/4106.50	% SZS status Theorem for HL402075+5.p
23324.49/4106.50	% SZS status Ended for HL402075+5.p
23326.55/4106.68	% SZS status Started for HL402069+5.p
23326.55/4106.68	% SZS status GaveUp for HL402069+5.p
23326.55/4106.68	% SZS status Ended for HL402069+5.p
23327.72/4106.83	% SZS status Started for HL402069+4.p
23327.72/4106.83	% SZS status GaveUp for HL402069+4.p
23327.72/4106.83	% SZS status Ended for HL402069+4.p
23329.29/4107.13	% SZS status Started for HL402077+4.p
23329.29/4107.13	% SZS status Theorem for HL402077+4.p
23329.29/4107.13	% SZS status Ended for HL402077+4.p
23330.62/4107.21	% SZS status Started for HL402076+5.p
23330.62/4107.21	% SZS status Theorem for HL402076+5.p
23330.62/4107.21	% SZS status Ended for HL402076+5.p
23330.62/4107.23	% SZS status Started for HL402075+4.p
23330.62/4107.23	% SZS status Theorem for HL402075+4.p
23330.62/4107.23	% SZS status Ended for HL402075+4.p
23331.30/4107.28	% SZS status Started for HL402070+5.p
23331.30/4107.28	% SZS status GaveUp for HL402070+5.p
23331.30/4107.28	% SZS status Ended for HL402070+5.p
23331.81/4107.43	% SZS status Started for HL402070+4.p
23331.81/4107.43	% SZS status GaveUp for HL402070+4.p
23331.81/4107.43	% SZS status Ended for HL402070+4.p
23331.81/4107.44	% SZS status Started for HL402077+5.p
23331.81/4107.44	% SZS status Theorem for HL402077+5.p
23331.81/4107.44	% SZS status Ended for HL402077+5.p
23332.48/4107.56	% SZS status Started for HL402079+4.p
23332.48/4107.56	% SZS status Theorem for HL402079+4.p
23332.48/4107.56	% SZS status Ended for HL402079+4.p
23332.87/4107.68	% SZS status Started for HL402080+4.p
23332.87/4107.68	% SZS status Theorem for HL402080+4.p
23332.87/4107.68	% SZS status Ended for HL402080+4.p
23332.87/4107.71	% SZS status Started for HL402079+5.p
23332.87/4107.71	% SZS status Theorem for HL402079+5.p
23332.87/4107.71	% SZS status Ended for HL402079+5.p
23336.26/4107.85	% SZS status Started for HL402080+5.p
23336.26/4107.85	% SZS status Theorem for HL402080+5.p
23336.26/4107.85	% SZS status Ended for HL402080+5.p
23336.57/4107.94	% SZS status Started for HL402081+4.p
23336.57/4107.94	% SZS status Theorem for HL402081+4.p
23336.57/4107.94	% SZS status Ended for HL402081+4.p
23336.89/4108.02	% SZS status Started for HL402081+5.p
23336.89/4108.02	% SZS status Theorem for HL402081+5.p
23336.89/4108.02	% SZS status Ended for HL402081+5.p
23341.65/4108.59	% SZS status Started for HL402076+4.p
23341.65/4108.59	% SZS status Theorem for HL402076+4.p
23341.65/4108.59	% SZS status Ended for HL402076+4.p
23342.14/4108.74	% SZS status Started for HL402083+5.p
23342.14/4108.74	% SZS status Theorem for HL402083+5.p
23342.14/4108.74	% SZS status Ended for HL402083+5.p
23355.04/4110.30	% SZS status Started for HL402073+4.p
23355.04/4110.30	% SZS status GaveUp for HL402073+4.p
23355.04/4110.30	% SZS status Ended for HL402073+4.p
23356.29/4110.47	% SZS status Started for HL402073+5.p
23356.29/4110.47	% SZS status GaveUp for HL402073+5.p
23356.29/4110.47	% SZS status Ended for HL402073+5.p
23396.02/4115.49	% SZS status Started for HL402078+5.p
23396.02/4115.49	% SZS status GaveUp for HL402078+5.p
23396.02/4115.49	% SZS status Ended for HL402078+5.p
23396.79/4115.66	% SZS status Started for HL402078+4.p
23396.79/4115.66	% SZS status GaveUp for HL402078+4.p
23396.79/4115.66	% SZS status Ended for HL402078+4.p
23401.36/4116.22	% SZS status Started for HL402083+4.p
23401.36/4116.22	% SZS status GaveUp for HL402083+4.p
23401.36/4116.22	% SZS status Ended for HL402083+4.p
23403.92/4116.39	% SZS status Started for HL402084+4.p
23403.92/4116.39	% SZS status GaveUp for HL402084+4.p
23403.92/4116.39	% SZS status Ended for HL402084+4.p
23405.98/4116.80	% SZS status Started for HL402084+5.p
23405.98/4116.80	% SZS status GaveUp for HL402084+5.p
23405.98/4116.80	% SZS status Ended for HL402084+5.p
23409.62/4117.20	% SZS status Started for HL402085+4.p
23409.62/4117.20	% SZS status GaveUp for HL402085+4.p
23409.62/4117.20	% SZS status Ended for HL402085+4.p
23420.42/4118.55	% SZS status Started for HL402085+5.p
23420.42/4118.55	% SZS status GaveUp for HL402085+5.p
23420.42/4118.55	% SZS status Ended for HL402085+5.p
23423.32/4118.95	% SZS status Started for HL402086+4.p
23423.32/4118.95	% SZS status GaveUp for HL402086+4.p
23423.32/4118.95	% SZS status Ended for HL402086+4.p
23429.17/4119.67	% SZS status Started for HL402089+5.p
23429.17/4119.67	% SZS status Theorem for HL402089+5.p
23429.17/4119.67	% SZS status Ended for HL402089+5.p
23462.16/4123.72	% SZS status Started for HL402086+5.p
23462.16/4123.72	% SZS status GaveUp for HL402086+5.p
23462.16/4123.72	% SZS status Ended for HL402086+5.p
23464.03/4124.02	% SZS status Started for HL402087+4.p
23464.03/4124.02	% SZS status GaveUp for HL402087+4.p
23464.03/4124.02	% SZS status Ended for HL402087+4.p
23468.04/4124.51	% SZS status Started for HL402087+5.p
23468.04/4124.51	% SZS status GaveUp for HL402087+5.p
23468.04/4124.51	% SZS status Ended for HL402087+5.p
23471.09/4124.84	% SZS status Started for HL402088+4.p
23471.09/4124.84	% SZS status GaveUp for HL402088+4.p
23471.09/4124.84	% SZS status Ended for HL402088+4.p
23472.01/4125.04	% SZS status Started for HL402088+5.p
23472.01/4125.04	% SZS status GaveUp for HL402088+5.p
23472.01/4125.04	% SZS status Ended for HL402088+5.p
23476.26/4125.55	% SZS status Started for HL402089+4.p
23476.26/4125.55	% SZS status GaveUp for HL402089+4.p
23476.26/4125.55	% SZS status Ended for HL402089+4.p
23490.87/4127.37	% SZS status Started for HL402090+4.p
23490.87/4127.37	% SZS status GaveUp for HL402090+4.p
23490.87/4127.37	% SZS status Ended for HL402090+4.p
23495.15/4127.88	% SZS status Started for HL402090+5.p
23495.15/4127.88	% SZS status GaveUp for HL402090+5.p
23495.15/4127.88	% SZS status Ended for HL402090+5.p
23527.83/4132.09	% SZS status Started for HL402091+4.p
23527.83/4132.09	% SZS status GaveUp for HL402091+4.p
23527.83/4132.09	% SZS status Ended for HL402091+4.p
23530.33/4132.33	% SZS status Started for HL402091+5.p
23530.33/4132.33	% SZS status GaveUp for HL402091+5.p
23530.33/4132.33	% SZS status Ended for HL402091+5.p
23534.40/4132.82	% SZS status Started for HL402092+4.p
23534.40/4132.82	% SZS status GaveUp for HL402092+4.p
23534.40/4132.82	% SZS status Ended for HL402092+4.p
23535.81/4133.05	% SZS status Started for HL402092+5.p
23535.81/4133.05	% SZS status GaveUp for HL402092+5.p
23535.81/4133.05	% SZS status Ended for HL402092+5.p
23539.18/4133.40	% SZS status Started for HL402094+4.p
23539.18/4133.40	% SZS status GaveUp for HL402094+4.p
23539.18/4133.40	% SZS status Ended for HL402094+4.p
23543.23/4133.93	% SZS status Started for HL402094+5.p
23543.23/4133.93	% SZS status GaveUp for HL402094+5.p
23543.23/4133.93	% SZS status Ended for HL402094+5.p
23558.76/4135.90	% SZS status Started for HL402095+4.p
23558.76/4135.90	% SZS status GaveUp for HL402095+4.p
23558.76/4135.90	% SZS status Ended for HL402095+4.p
23560.96/4136.19	% SZS status Started for HL402095+5.p
23560.96/4136.19	% SZS status GaveUp for HL402095+5.p
23560.96/4136.19	% SZS status Ended for HL402095+5.p
23594.45/4140.51	% SZS status Started for HL402096+4.p
23594.45/4140.51	% SZS status GaveUp for HL402096+4.p
23594.45/4140.51	% SZS status Ended for HL402096+4.p
23594.57/4140.56	% SZS status Started for HL402096+5.p
23594.57/4140.56	% SZS status GaveUp for HL402096+5.p
23594.57/4140.56	% SZS status Ended for HL402096+5.p
23599.36/4141.14	% SZS status Started for HL402097+4.p
23599.36/4141.14	% SZS status GaveUp for HL402097+4.p
23599.36/4141.14	% SZS status Ended for HL402097+4.p
23601.68/4141.30	% SZS status Started for HL402097+5.p
23601.68/4141.30	% SZS status GaveUp for HL402097+5.p
23601.68/4141.30	% SZS status Ended for HL402097+5.p
23605.95/4141.83	% SZS status Started for HL402098+4.p
23605.95/4141.83	% SZS status GaveUp for HL402098+4.p
23605.95/4141.83	% SZS status Ended for HL402098+4.p
23608.61/4142.16	% SZS status Started for HL402098+5.p
23608.61/4142.16	% SZS status GaveUp for HL402098+5.p
23608.61/4142.16	% SZS status Ended for HL402098+5.p
23625.66/4144.31	% SZS status Started for HL402099+4.p
23625.66/4144.31	% SZS status GaveUp for HL402099+4.p
23625.66/4144.31	% SZS status Ended for HL402099+4.p
23626.69/4144.47	% SZS status Started for HL402099+5.p
23626.69/4144.47	% SZS status GaveUp for HL402099+5.p
23626.69/4144.47	% SZS status Ended for HL402099+5.p
23660.33/4148.77	% SZS status Started for HL402100+5.p
23660.33/4148.77	% SZS status GaveUp for HL402100+5.p
23660.33/4148.77	% SZS status Ended for HL402100+5.p
23660.52/4148.84	% SZS status Started for HL402100+4.p
23660.52/4148.84	% SZS status GaveUp for HL402100+4.p
23660.52/4148.84	% SZS status Ended for HL402100+4.p
23667.29/4149.54	% SZS status Started for HL402101+4.p
23667.29/4149.54	% SZS status GaveUp for HL402101+4.p
23667.29/4149.54	% SZS status Ended for HL402101+4.p
23667.86/4149.58	% SZS status Started for HL402101+5.p
23667.86/4149.58	% SZS status GaveUp for HL402101+5.p
23667.86/4149.58	% SZS status Ended for HL402101+5.p
23672.25/4150.18	% SZS status Started for HL402102+4.p
23672.25/4150.18	% SZS status GaveUp for HL402102+4.p
23672.25/4150.18	% SZS status Ended for HL402102+4.p
23673.32/4150.38	% SZS status Started for HL402102+5.p
23673.32/4150.38	% SZS status GaveUp for HL402102+5.p
23673.32/4150.38	% SZS status Ended for HL402102+5.p
23692.34/4152.71	% SZS status Started for HL402103+4.p
23692.34/4152.71	% SZS status GaveUp for HL402103+4.p
23692.34/4152.71	% SZS status Ended for HL402103+4.p
23692.34/4152.72	% SZS status Started for HL402103+5.p
23692.34/4152.72	% SZS status GaveUp for HL402103+5.p
23692.34/4152.72	% SZS status Ended for HL402103+5.p
23727.33/4157.12	% SZS status Started for HL402104+4.p
23727.33/4157.12	% SZS status GaveUp for HL402104+4.p
23727.33/4157.12	% SZS status Ended for HL402104+4.p
23727.33/4157.14	% SZS status Started for HL402104+5.p
23727.33/4157.14	% SZS status GaveUp for HL402104+5.p
23727.33/4157.14	% SZS status Ended for HL402104+5.p
23733.63/4157.87	% SZS status Started for HL402105+5.p
23733.63/4157.87	% SZS status GaveUp for HL402105+5.p
23733.63/4157.87	% SZS status Ended for HL402105+5.p
23733.63/4157.89	% SZS status Started for HL402105+4.p
23733.63/4157.89	% SZS status GaveUp for HL402105+4.p
23733.63/4157.89	% SZS status Ended for HL402105+4.p
23738.43/4158.57	% SZS status Started for HL402107+4.p
23738.43/4158.57	% SZS status GaveUp for HL402107+4.p
23738.43/4158.57	% SZS status Ended for HL402107+4.p
23738.81/4158.67	% SZS status Started for HL402107+5.p
23738.81/4158.67	% SZS status GaveUp for HL402107+5.p
23738.81/4158.67	% SZS status Ended for HL402107+5.p
23758.23/4161.01	% SZS status Started for HL402108+5.p
23758.23/4161.01	% SZS status GaveUp for HL402108+5.p
23758.23/4161.01	% SZS status Ended for HL402108+5.p
23759.79/4161.19	% SZS status Started for HL402108+4.p
23759.79/4161.19	% SZS status GaveUp for HL402108+4.p
23759.79/4161.19	% SZS status Ended for HL402108+4.p
23766.67/4162.08	% SZS status Started for HL402112+5.p
23766.67/4162.08	% SZS status Theorem for HL402112+5.p
23766.67/4162.08	% SZS status Ended for HL402112+5.p
23769.13/4162.39	% SZS status Started for HL402113+4.p
23769.13/4162.39	% SZS status Theorem for HL402113+4.p
23769.13/4162.39	% SZS status Ended for HL402113+4.p
23774.79/4163.10	% SZS status Started for HL402113+5.p
23774.79/4163.10	% SZS status Theorem for HL402113+5.p
23774.79/4163.10	% SZS status Ended for HL402113+5.p
23782.93/4164.12	% SZS status Started for HL402114+4.p
23782.93/4164.12	% SZS status Theorem for HL402114+4.p
23782.93/4164.12	% SZS status Ended for HL402114+4.p
23789.22/4164.86	% SZS status Started for HL402114+5.p
23789.22/4164.86	% SZS status Theorem for HL402114+5.p
23789.22/4164.86	% SZS status Ended for HL402114+5.p
23793.27/4165.36	% SZS status Started for HL402109+5.p
23793.27/4165.36	% SZS status GaveUp for HL402109+5.p
23793.27/4165.36	% SZS status Ended for HL402109+5.p
23794.37/4165.54	% SZS status Started for HL402109+4.p
23794.37/4165.54	% SZS status GaveUp for HL402109+4.p
23794.37/4165.54	% SZS status Ended for HL402109+4.p
23798.69/4166.09	% SZS status Started for HL402110+5.p
23798.69/4166.09	% SZS status GaveUp for HL402110+5.p
23798.69/4166.09	% SZS status Ended for HL402110+5.p
23802.11/4166.51	% SZS status Started for HL402110+4.p
23802.11/4166.51	% SZS status GaveUp for HL402110+4.p
23802.11/4166.51	% SZS status Ended for HL402110+4.p
23806.37/4167.06	% SZS status Started for HL402111+4.p
23806.37/4167.06	% SZS status GaveUp for HL402111+4.p
23806.37/4167.06	% SZS status Ended for HL402111+4.p
23806.93/4167.10	% SZS status Started for HL402111+5.p
23806.93/4167.10	% SZS status GaveUp for HL402111+5.p
23806.93/4167.10	% SZS status Ended for HL402111+5.p
23824.75/4169.38	% SZS status Started for HL402112+4.p
23824.75/4169.38	% SZS status GaveUp for HL402112+4.p
23824.75/4169.38	% SZS status Ended for HL402112+4.p
23855.86/4173.27	% SZS status Started for HL402115+4.p
23855.86/4173.27	% SZS status GaveUp for HL402115+4.p
23855.86/4173.27	% SZS status Ended for HL402115+4.p
23858.30/4173.57	% SZS status Started for HL402115+5.p
23858.30/4173.57	% SZS status GaveUp for HL402115+5.p
23858.30/4173.57	% SZS status Ended for HL402115+5.p
23860.66/4173.95	% SZS status Started for HL402116+4.p
23860.66/4173.95	% SZS status GaveUp for HL402116+4.p
23860.66/4173.95	% SZS status Ended for HL402116+4.p
23864.14/4174.30	% SZS status Started for HL402116+5.p
23864.14/4174.30	% SZS status GaveUp for HL402116+5.p
23864.14/4174.30	% SZS status Ended for HL402116+5.p
23869.31/4174.96	% SZS status Started for HL402120+5.p
23869.31/4174.96	% SZS status Theorem for HL402120+5.p
23869.31/4174.96	% SZS status Ended for HL402120+5.p
23870.06/4175.06	% SZS status Started for HL402117+4.p
23870.06/4175.06	% SZS status GaveUp for HL402117+4.p
23870.06/4175.06	% SZS status Ended for HL402117+4.p
23870.70/4175.26	% SZS status Started for HL402117+5.p
23870.70/4175.26	% SZS status GaveUp for HL402117+5.p
23870.70/4175.26	% SZS status Ended for HL402117+5.p
23873.91/4175.54	% SZS status Started for HL402118+4.p
23873.91/4175.54	% SZS status GaveUp for HL402118+4.p
23873.91/4175.54	% SZS status Ended for HL402118+4.p
23873.91/4175.55	% SZS status Started for HL402121+4.p
23873.91/4175.55	% SZS status GaveUp for HL402121+4.p
23873.91/4175.55	% SZS status Ended for HL402121+4.p
23880.27/4176.51	% SZS status Started for HL402120+4.p
23880.27/4176.51	% SZS status Theorem for HL402120+4.p
23880.27/4176.51	% SZS status Ended for HL402120+4.p
23890.95/4177.58	% SZS status Started for HL402118+5.p
23890.95/4177.58	% SZS status GaveUp for HL402118+5.p
23890.95/4177.58	% SZS status Ended for HL402118+5.p
23917.04/4181.03	% SZS status Started for HL402125+4.p
23917.04/4181.03	% SZS status Theorem for HL402125+4.p
23917.04/4181.03	% SZS status Ended for HL402125+4.p
23923.86/4181.70	% SZS status Started for HL402119+4.p
23923.86/4181.70	% SZS status GaveUp for HL402119+4.p
23923.86/4181.70	% SZS status Ended for HL402119+4.p
23924.61/4181.84	% SZS status Started for HL402119+5.p
23924.61/4181.84	% SZS status GaveUp for HL402119+5.p
23924.61/4181.84	% SZS status Ended for HL402119+5.p
23937.89/4183.46	% SZS status Started for HL402121+5.p
23937.89/4183.46	% SZS status GaveUp for HL402121+5.p
23937.89/4183.46	% SZS status Ended for HL402121+5.p
23938.30/4183.55	% SZS status Started for HL402123+4.p
23938.30/4183.55	% SZS status GaveUp for HL402123+4.p
23938.30/4183.55	% SZS status Ended for HL402123+4.p
23939.79/4183.76	% SZS status Started for HL402123+5.p
23939.79/4183.76	% SZS status GaveUp for HL402123+5.p
23939.79/4183.76	% SZS status Ended for HL402123+5.p
23940.24/4183.92	% SZS status Started for HL402124+4.p
23940.24/4183.92	% SZS status GaveUp for HL402124+4.p
23940.24/4183.92	% SZS status Ended for HL402124+4.p
23947.43/4184.70	% SZS status Started for HL402124+5.p
23947.43/4184.70	% SZS status GaveUp for HL402124+5.p
23947.43/4184.70	% SZS status Ended for HL402124+5.p
23983.79/4189.29	% SZS status Started for HL402125+5.p
23983.79/4189.29	% SZS status GaveUp for HL402125+5.p
23983.79/4189.29	% SZS status Ended for HL402125+5.p
23990.00/4190.10	% SZS status Started for HL402126+4.p
23990.00/4190.10	% SZS status GaveUp for HL402126+4.p
23990.00/4190.10	% SZS status Ended for HL402126+4.p
23991.64/4190.23	% SZS status Started for HL402126+5.p
23991.64/4190.23	% SZS status GaveUp for HL402126+5.p
23991.64/4190.23	% SZS status Ended for HL402126+5.p
24002.84/4191.76	% SZS status Started for HL402127+5.p
24002.84/4191.76	% SZS status GaveUp for HL402127+5.p
24002.84/4191.76	% SZS status Ended for HL402127+5.p
24004.27/4191.86	% SZS status Started for HL402127+4.p
24004.27/4191.86	% SZS status GaveUp for HL402127+4.p
24004.27/4191.86	% SZS status Ended for HL402127+4.p
24006.65/4192.19	% SZS status Started for HL402128+4.p
24006.65/4192.19	% SZS status GaveUp for HL402128+4.p
24006.65/4192.19	% SZS status Ended for HL402128+4.p
24006.65/4192.20	% SZS status Started for HL402128+5.p
24006.65/4192.20	% SZS status GaveUp for HL402128+5.p
24006.65/4192.20	% SZS status Ended for HL402128+5.p
24014.35/4193.12	% SZS status Started for HL402129+4.p
24014.35/4193.12	% SZS status GaveUp for HL402129+4.p
24014.35/4193.12	% SZS status Ended for HL402129+4.p
24050.03/4197.63	% SZS status Started for HL402129+5.p
24050.03/4197.63	% SZS status GaveUp for HL402129+5.p
24050.03/4197.63	% SZS status Ended for HL402129+5.p
24056.05/4198.42	% SZS status Started for HL402130+5.p
24056.05/4198.42	% SZS status GaveUp for HL402130+5.p
24056.05/4198.42	% SZS status Ended for HL402130+5.p
24058.63/4198.70	% SZS status Started for HL402130+4.p
24058.63/4198.70	% SZS status GaveUp for HL402130+4.p
24058.63/4198.70	% SZS status Ended for HL402130+4.p
24069.78/4200.10	% SZS status Started for HL402131+5.p
24069.78/4200.10	% SZS status GaveUp for HL402131+5.p
24069.78/4200.10	% SZS status Ended for HL402131+5.p
24070.66/4200.18	% SZS status Started for HL402131+4.p
24070.66/4200.18	% SZS status GaveUp for HL402131+4.p
24070.66/4200.18	% SZS status Ended for HL402131+4.p
24072.27/4200.45	% SZS status Started for HL402132+5.p
24072.27/4200.45	% SZS status GaveUp for HL402132+5.p
24072.27/4200.45	% SZS status Ended for HL402132+5.p
24074.39/4200.71	% SZS status Started for HL402132+4.p
24074.39/4200.71	% SZS status GaveUp for HL402132+4.p
24074.39/4200.71	% SZS status Ended for HL402132+4.p
24083.05/4201.76	% SZS status Started for HL402133+4.p
24083.05/4201.76	% SZS status GaveUp for HL402133+4.p
24083.05/4201.76	% SZS status Ended for HL402133+4.p
24115.77/4205.92	% SZS status Started for HL402133+5.p
24115.77/4205.92	% SZS status GaveUp for HL402133+5.p
24115.77/4205.92	% SZS status Ended for HL402133+5.p
24122.38/4206.78	% SZS status Started for HL402134+4.p
24122.38/4206.78	% SZS status GaveUp for HL402134+4.p
24122.38/4206.78	% SZS status Ended for HL402134+4.p
24124.18/4206.93	% SZS status Started for HL402134+5.p
24124.18/4206.93	% SZS status GaveUp for HL402134+5.p
24124.18/4206.93	% SZS status Ended for HL402134+5.p
24134.87/4208.39	% SZS status Started for HL402135+5.p
24134.87/4208.39	% SZS status GaveUp for HL402135+5.p
24134.87/4208.39	% SZS status Ended for HL402135+5.p
24135.17/4208.46	% SZS status Started for HL402135+4.p
24135.17/4208.46	% SZS status GaveUp for HL402135+4.p
24135.17/4208.46	% SZS status Ended for HL402135+4.p
24139.61/4208.95	% SZS status Started for HL402136+4.p
24139.61/4208.95	% SZS status GaveUp for HL402136+4.p
24139.61/4208.95	% SZS status Ended for HL402136+4.p
24139.61/4208.96	% SZS status Started for HL402136+5.p
24139.61/4208.96	% SZS status GaveUp for HL402136+5.p
24139.61/4208.96	% SZS status Ended for HL402136+5.p
24150.62/4210.33	% SZS status Started for HL402138+4.p
24150.62/4210.33	% SZS status GaveUp for HL402138+4.p
24150.62/4210.33	% SZS status Ended for HL402138+4.p
24182.19/4214.29	% SZS status Started for HL402138+5.p
24182.19/4214.29	% SZS status GaveUp for HL402138+5.p
24182.19/4214.29	% SZS status Ended for HL402138+5.p
24188.32/4215.15	% SZS status Started for HL402139+5.p
24188.32/4215.15	% SZS status GaveUp for HL402139+5.p
24188.32/4215.15	% SZS status Ended for HL402139+5.p
24190.33/4215.31	% SZS status Started for HL402139+4.p
24190.33/4215.31	% SZS status GaveUp for HL402139+4.p
24190.33/4215.31	% SZS status Ended for HL402139+4.p
24200.65/4216.72	% SZS status Started for HL402140+5.p
24200.65/4216.72	% SZS status GaveUp for HL402140+5.p
24200.65/4216.72	% SZS status Ended for HL402140+5.p
24203.95/4217.03	% SZS status Started for HL402140+4.p
24203.95/4217.03	% SZS status GaveUp for HL402140+4.p
24203.95/4217.03	% SZS status Ended for HL402140+4.p
24205.07/4217.16	% SZS status Started for HL402141+5.p
24205.07/4217.16	% SZS status GaveUp for HL402141+5.p
24205.07/4217.16	% SZS status Ended for HL402141+5.p
24206.97/4217.42	% SZS status Started for HL402141+4.p
24206.97/4217.42	% SZS status GaveUp for HL402141+4.p
24206.97/4217.42	% SZS status Ended for HL402141+4.p
24208.14/4217.55	% SZS status Started for HL402146+4.p
24208.14/4217.55	% SZS status Theorem for HL402146+4.p
24208.14/4217.55	% SZS status Ended for HL402146+4.p
24217.35/4218.85	% SZS status Started for HL402142+4.p
24217.35/4218.85	% SZS status GaveUp for HL402142+4.p
24217.35/4218.85	% SZS status Ended for HL402142+4.p
24247.44/4222.52	% SZS status Started for HL402142+5.p
24247.44/4222.52	% SZS status GaveUp for HL402142+5.p
24247.44/4222.52	% SZS status Ended for HL402142+5.p
24247.76/4222.56	% SZS status Started for HL402146+5.p
24247.76/4222.56	% SZS status Theorem for HL402146+5.p
24247.76/4222.56	% SZS status Ended for HL402146+5.p
24255.14/4223.51	% SZS status Started for HL402143+5.p
24255.14/4223.51	% SZS status GaveUp for HL402143+5.p
24255.14/4223.51	% SZS status Ended for HL402143+5.p
24256.21/4223.61	% SZS status Started for HL402143+4.p
24256.21/4223.61	% SZS status GaveUp for HL402143+4.p
24256.21/4223.61	% SZS status Ended for HL402143+4.p
24268.03/4225.15	% SZS status Started for HL402144+4.p
24268.03/4225.15	% SZS status GaveUp for HL402144+4.p
24268.03/4225.15	% SZS status Ended for HL402144+4.p
24269.89/4225.42	% SZS status Started for HL402144+5.p
24269.89/4225.42	% SZS status GaveUp for HL402144+5.p
24269.89/4225.42	% SZS status Ended for HL402144+5.p
24274.67/4226.00	% SZS status Started for HL402147+4.p
24274.67/4226.00	% SZS status GaveUp for HL402147+4.p
24274.67/4226.00	% SZS status Ended for HL402147+4.p
24282.80/4227.10	% SZS status Started for HL402147+5.p
24282.80/4227.10	% SZS status GaveUp for HL402147+5.p
24282.80/4227.10	% SZS status Ended for HL402147+5.p
24313.11/4230.82	% SZS status Started for HL402149+5.p
24313.11/4230.82	% SZS status GaveUp for HL402149+5.p
24313.11/4230.82	% SZS status Ended for HL402149+5.p
24314.48/4231.05	% SZS status Started for HL402149+4.p
24314.48/4231.05	% SZS status GaveUp for HL402149+4.p
24314.48/4231.05	% SZS status Ended for HL402149+4.p
24321.28/4231.81	% SZS status Started for HL402150+5.p
24321.28/4231.81	% SZS status GaveUp for HL402150+5.p
24321.28/4231.81	% SZS status Ended for HL402150+5.p
24322.52/4232.03	% SZS status Started for HL402150+4.p
24322.52/4232.03	% SZS status GaveUp for HL402150+4.p
24322.52/4232.03	% SZS status Ended for HL402150+4.p
24335.15/4233.58	% SZS status Started for HL402151+4.p
24335.15/4233.58	% SZS status GaveUp for HL402151+4.p
24335.15/4233.58	% SZS status Ended for HL402151+4.p
24335.51/4233.64	% SZS status Started for HL402151+5.p
24335.51/4233.64	% SZS status GaveUp for HL402151+5.p
24335.51/4233.64	% SZS status Ended for HL402151+5.p
24342.56/4234.52	% SZS status Started for HL402152+4.p
24342.56/4234.52	% SZS status GaveUp for HL402152+4.p
24342.56/4234.52	% SZS status Ended for HL402152+4.p
24349.13/4235.41	% SZS status Started for HL402152+5.p
24349.13/4235.41	% SZS status GaveUp for HL402152+5.p
24349.13/4235.41	% SZS status Ended for HL402152+5.p
24379.57/4239.30	% SZS status Started for HL402153+5.p
24379.57/4239.30	% SZS status GaveUp for HL402153+5.p
24379.57/4239.30	% SZS status Ended for HL402153+5.p
24381.14/4239.38	% SZS status Started for HL402153+4.p
24381.14/4239.38	% SZS status GaveUp for HL402153+4.p
24381.14/4239.38	% SZS status Ended for HL402153+4.p
24387.29/4240.24	% SZS status Started for HL402155+5.p
24387.29/4240.24	% SZS status GaveUp for HL402155+5.p
24387.29/4240.24	% SZS status Ended for HL402155+5.p
24387.54/4240.27	% SZS status Started for HL402155+4.p
24387.54/4240.27	% SZS status GaveUp for HL402155+4.p
24387.54/4240.27	% SZS status Ended for HL402155+4.p
24401.13/4241.97	% SZS status Started for HL402156+5.p
24401.13/4241.97	% SZS status GaveUp for HL402156+5.p
24401.13/4241.97	% SZS status Ended for HL402156+5.p
24401.35/4241.99	% SZS status Started for HL402156+4.p
24401.35/4241.99	% SZS status GaveUp for HL402156+4.p
24401.35/4241.99	% SZS status Ended for HL402156+4.p
24410.37/4243.07	% SZS status Started for HL402157+4.p
24410.37/4243.07	% SZS status GaveUp for HL402157+4.p
24410.37/4243.07	% SZS status Ended for HL402157+4.p
24414.11/4243.68	% SZS status Started for HL402157+5.p
24414.11/4243.68	% SZS status GaveUp for HL402157+5.p
24414.11/4243.68	% SZS status Ended for HL402157+5.p
24445.51/4247.66	% SZS status Started for HL402158+4.p
24445.51/4247.66	% SZS status GaveUp for HL402158+4.p
24445.51/4247.66	% SZS status Ended for HL402158+4.p
24445.99/4247.70	% SZS status Started for HL402158+5.p
24445.99/4247.70	% SZS status GaveUp for HL402158+5.p
24445.99/4247.70	% SZS status Ended for HL402158+5.p
24453.20/4248.50	% SZS status Started for HL402159+5.p
24453.20/4248.50	% SZS status GaveUp for HL402159+5.p
24453.20/4248.50	% SZS status Ended for HL402159+5.p
24453.95/4248.64	% SZS status Started for HL402159+4.p
24453.95/4248.64	% SZS status GaveUp for HL402159+4.p
24453.95/4248.64	% SZS status Ended for HL402159+4.p
24456.58/4248.89	% SZS status Started for HL402164+4.p
24456.58/4248.89	% SZS status Theorem for HL402164+4.p
24456.58/4248.89	% SZS status Ended for HL402164+4.p
24467.40/4250.29	% SZS status Started for HL402160+5.p
24467.40/4250.29	% SZS status GaveUp for HL402160+5.p
24467.40/4250.29	% SZS status Ended for HL402160+5.p
24467.71/4250.34	% SZS status Started for HL402160+4.p
24467.71/4250.34	% SZS status GaveUp for HL402160+4.p
24467.71/4250.34	% SZS status Ended for HL402160+4.p
24476.52/4251.41	% SZS status Started for HL402162+4.p
24476.52/4251.41	% SZS status GaveUp for HL402162+4.p
24476.52/4251.41	% SZS status Ended for HL402162+4.p
24481.33/4251.98	% SZS status Started for HL402162+5.p
24481.33/4251.98	% SZS status GaveUp for HL402162+5.p
24481.33/4251.98	% SZS status Ended for HL402162+5.p
24512.29/4255.98	% SZS status Started for HL402163+5.p
24512.29/4255.98	% SZS status GaveUp for HL402163+5.p
24512.29/4255.98	% SZS status Ended for HL402163+5.p
24513.03/4256.14	% SZS status Started for HL402163+4.p
24513.03/4256.14	% SZS status GaveUp for HL402163+4.p
24513.03/4256.14	% SZS status Ended for HL402163+4.p
24520.94/4256.95	% SZS status Started for HL402164+5.p
24520.94/4256.95	% SZS status GaveUp for HL402164+5.p
24520.94/4256.95	% SZS status Ended for HL402164+5.p
24522.58/4257.20	% SZS status Started for HL402165+4.p
24522.58/4257.20	% SZS status GaveUp for HL402165+4.p
24522.58/4257.20	% SZS status Ended for HL402165+4.p
24526.05/4257.62	% SZS status Started for HL402168+5.p
24526.05/4257.62	% SZS status Theorem for HL402168+5.p
24526.05/4257.62	% SZS status Ended for HL402168+5.p
24532.50/4258.52	% SZS status Started for HL402165+5.p
24532.50/4258.52	% SZS status GaveUp for HL402165+5.p
24532.50/4258.52	% SZS status Ended for HL402165+5.p
24532.94/4258.54	% SZS status Started for HL402168+4.p
24532.94/4258.54	% SZS status Theorem for HL402168+4.p
24532.94/4258.54	% SZS status Ended for HL402168+4.p
24535.18/4258.81	% SZS status Started for HL402166+4.p
24535.18/4258.81	% SZS status GaveUp for HL402166+4.p
24535.18/4258.81	% SZS status Ended for HL402166+4.p
24543.24/4259.76	% SZS status Started for HL402166+5.p
24543.24/4259.76	% SZS status GaveUp for HL402166+5.p
24543.24/4259.76	% SZS status Ended for HL402166+5.p
24548.66/4260.43	% SZS status Started for HL402167+4.p
24548.66/4260.43	% SZS status GaveUp for HL402167+4.p
24548.66/4260.43	% SZS status Ended for HL402167+4.p
24578.44/4264.19	% SZS status Started for HL402167+5.p
24578.44/4264.19	% SZS status GaveUp for HL402167+5.p
24578.44/4264.19	% SZS status Ended for HL402167+5.p
24589.20/4265.63	% SZS status Started for HL402169+4.p
24589.20/4265.63	% SZS status GaveUp for HL402169+4.p
24589.20/4265.63	% SZS status Ended for HL402169+4.p
24591.40/4265.83	% SZS status Started for HL402169+5.p
24591.40/4265.83	% SZS status GaveUp for HL402169+5.p
24591.40/4265.83	% SZS status Ended for HL402169+5.p
24598.74/4266.84	% SZS status Started for HL402170+5.p
24598.74/4266.84	% SZS status GaveUp for HL402170+5.p
24598.74/4266.84	% SZS status Ended for HL402170+5.p
24600.33/4266.94	% SZS status Started for HL402170+4.p
24600.33/4266.94	% SZS status GaveUp for HL402170+4.p
24600.33/4266.94	% SZS status Ended for HL402170+4.p
24601.27/4267.19	% SZS status Started for HL402171+4.p
24601.27/4267.19	% SZS status GaveUp for HL402171+4.p
24601.27/4267.19	% SZS status Ended for HL402171+4.p
24604.79/4267.52	% SZS status Started for HL402175+4.p
24604.79/4267.52	% SZS status Theorem for HL402175+4.p
24604.79/4267.52	% SZS status Ended for HL402175+4.p
24608.57/4268.02	% SZS status Started for HL402171+5.p
24608.57/4268.02	% SZS status GaveUp for HL402171+5.p
24608.57/4268.02	% SZS status Ended for HL402171+5.p
24609.49/4268.13	% SZS status Started for HL402175+5.p
24609.49/4268.13	% SZS status Theorem for HL402175+5.p
24609.49/4268.13	% SZS status Ended for HL402175+5.p
24609.87/4268.34	% SZS status Started for HL402176+4.p
24609.87/4268.34	% SZS status Theorem for HL402176+4.p
24609.87/4268.34	% SZS status Ended for HL402176+4.p
24614.13/4268.73	% SZS status Started for HL402176+5.p
24614.13/4268.73	% SZS status Theorem for HL402176+5.p
24614.13/4268.73	% SZS status Ended for HL402176+5.p
24616.51/4269.03	% SZS status Started for HL402172+4.p
24616.51/4269.03	% SZS status GaveUp for HL402172+4.p
24616.51/4269.03	% SZS status Ended for HL402172+4.p
24619.61/4269.39	% SZS status Started for HL402179+4.p
24619.61/4269.39	% SZS status Theorem for HL402179+4.p
24619.61/4269.39	% SZS status Ended for HL402179+4.p
24643.62/4272.43	% SZS status Started for HL402172+5.p
24643.62/4272.43	% SZS status GaveUp for HL402172+5.p
24643.62/4272.43	% SZS status Ended for HL402172+5.p
24655.72/4273.98	% SZS status Started for HL402173+4.p
24655.72/4273.98	% SZS status GaveUp for HL402173+4.p
24655.72/4273.98	% SZS status Ended for HL402173+4.p
24656.37/4274.08	% SZS status Started for HL402173+5.p
24656.37/4274.08	% SZS status GaveUp for HL402173+5.p
24656.37/4274.08	% SZS status Ended for HL402173+5.p
24660.04/4274.50	% SZS status Started for HL402179+5.p
24660.04/4274.50	% SZS status Theorem for HL402179+5.p
24660.04/4274.50	% SZS status Ended for HL402179+5.p
24665.69/4275.16	% SZS status Started for HL402174+5.p
24665.69/4275.16	% SZS status GaveUp for HL402174+5.p
24665.69/4275.16	% SZS status Ended for HL402174+5.p
24666.02/4275.24	% SZS status Started for HL402174+4.p
24666.02/4275.24	% SZS status GaveUp for HL402174+4.p
24666.02/4275.24	% SZS status Ended for HL402174+4.p
24677.81/4276.73	% SZS status Started for HL402178+4.p
24677.81/4276.73	% SZS status GaveUp for HL402178+4.p
24677.81/4276.73	% SZS status Ended for HL402178+4.p
24679.57/4277.02	% SZS status Started for HL402178+5.p
24679.57/4277.02	% SZS status GaveUp for HL402178+5.p
24679.57/4277.02	% SZS status Ended for HL402178+5.p
24710.89/4280.83	% SZS status Started for HL402180+4.p
24710.89/4280.83	% SZS status GaveUp for HL402180+4.p
24710.89/4280.83	% SZS status Ended for HL402180+4.p
24721.58/4282.24	% SZS status Started for HL402180+5.p
24721.58/4282.24	% SZS status GaveUp for HL402180+5.p
24721.58/4282.24	% SZS status Ended for HL402180+5.p
24723.54/4282.45	% SZS status Started for HL402181+4.p
24723.54/4282.45	% SZS status GaveUp for HL402181+4.p
24723.54/4282.45	% SZS status Ended for HL402181+4.p
24724.47/4282.72	% SZS status Started for HL402181+5.p
24724.47/4282.72	% SZS status GaveUp for HL402181+5.p
24724.47/4282.72	% SZS status Ended for HL402181+5.p
24724.85/4282.86	% SZS status Started for HL402186+4.p
24724.85/4282.86	% SZS status Theorem for HL402186+4.p
24724.85/4282.86	% SZS status Ended for HL402186+4.p
24730.58/4283.50	% SZS status Started for HL402183+5.p
24730.58/4283.50	% SZS status GaveUp for HL402183+5.p
24730.58/4283.50	% SZS status Ended for HL402183+5.p
24732.73/4283.60	% SZS status Started for HL402183+4.p
24732.73/4283.60	% SZS status GaveUp for HL402183+4.p
24732.73/4283.60	% SZS status Ended for HL402183+4.p
24744.39/4285.08	% SZS status Started for HL402184+4.p
24744.39/4285.08	% SZS status GaveUp for HL402184+4.p
24744.39/4285.08	% SZS status Ended for HL402184+4.p
24746.14/4285.24	% SZS status Started for HL402184+5.p
24746.14/4285.24	% SZS status GaveUp for HL402184+5.p
24746.14/4285.24	% SZS status Ended for HL402184+5.p
24777.48/4289.21	% SZS status Started for HL402185+4.p
24777.48/4289.21	% SZS status GaveUp for HL402185+4.p
24777.48/4289.21	% SZS status Ended for HL402185+4.p
24787.01/4290.44	% SZS status Started for HL402185+5.p
24787.01/4290.44	% SZS status GaveUp for HL402185+5.p
24787.01/4290.44	% SZS status Ended for HL402185+5.p
24791.27/4290.99	% SZS status Started for HL402186+5.p
24791.27/4290.99	% SZS status GaveUp for HL402186+5.p
24791.27/4290.99	% SZS status Ended for HL402186+5.p
24792.83/4291.27	% SZS status Started for HL402187+4.p
24792.83/4291.27	% SZS status GaveUp for HL402187+4.p
24792.83/4291.27	% SZS status Ended for HL402187+4.p
24796.60/4291.76	% SZS status Started for HL402187+5.p
24796.60/4291.76	% SZS status GaveUp for HL402187+5.p
24796.60/4291.76	% SZS status Ended for HL402187+5.p
24800.07/4292.07	% SZS status Started for HL402188+4.p
24800.07/4292.07	% SZS status GaveUp for HL402188+4.p
24800.07/4292.07	% SZS status Ended for HL402188+4.p
24803.24/4292.50	% SZS status Started for HL402192+4.p
24803.24/4292.50	% SZS status Theorem for HL402192+4.p
24803.24/4292.50	% SZS status Ended for HL402192+4.p
24809.90/4293.36	% SZS status Started for HL402188+5.p
24809.90/4293.36	% SZS status GaveUp for HL402188+5.p
24809.90/4293.36	% SZS status Ended for HL402188+5.p
24811.26/4293.47	% SZS status Started for HL402192+5.p
24811.26/4293.47	% SZS status Theorem for HL402192+5.p
24811.26/4293.47	% SZS status Ended for HL402192+5.p
24812.97/4293.79	% SZS status Started for HL402189+4.p
24812.97/4293.79	% SZS status GaveUp for HL402189+4.p
24812.97/4293.79	% SZS status Ended for HL402189+4.p
24843.24/4297.50	% SZS status Started for HL402189+5.p
24843.24/4297.50	% SZS status GaveUp for HL402189+5.p
24843.24/4297.50	% SZS status Ended for HL402189+5.p
24853.08/4298.83	% SZS status Started for HL402190+4.p
24853.08/4298.83	% SZS status GaveUp for HL402190+4.p
24853.08/4298.83	% SZS status Ended for HL402190+4.p
24859.42/4299.54	% SZS status Started for HL402190+5.p
24859.42/4299.54	% SZS status GaveUp for HL402190+5.p
24859.42/4299.54	% SZS status Ended for HL402190+5.p
24859.78/4299.62	% SZS status Started for HL402191+4.p
24859.78/4299.62	% SZS status GaveUp for HL402191+4.p
24859.78/4299.62	% SZS status Ended for HL402191+4.p
24861.53/4300.01	% SZS status Started for HL402191+5.p
24861.53/4300.01	% SZS status GaveUp for HL402191+5.p
24861.53/4300.01	% SZS status Ended for HL402191+5.p
24876.89/4301.81	% SZS status Started for HL402193+5.p
24876.89/4301.81	% SZS status GaveUp for HL402193+5.p
24876.89/4301.81	% SZS status Ended for HL402193+5.p
24877.33/4301.85	% SZS status Started for HL402193+4.p
24877.33/4301.85	% SZS status GaveUp for HL402193+4.p
24877.33/4301.85	% SZS status Ended for HL402193+4.p
24878.51/4302.20	% SZS status Started for HL402194+4.p
24878.51/4302.20	% SZS status GaveUp for HL402194+4.p
24878.51/4302.20	% SZS status Ended for HL402194+4.p
24909.29/4305.87	% SZS status Started for HL402194+5.p
24909.29/4305.87	% SZS status GaveUp for HL402194+5.p
24909.29/4305.87	% SZS status Ended for HL402194+5.p
24921.20/4307.38	% SZS status Started for HL402195+4.p
24921.20/4307.38	% SZS status GaveUp for HL402195+4.p
24921.20/4307.38	% SZS status Ended for HL402195+4.p
24923.69/4307.75	% SZS status Started for HL402200+4.p
24923.69/4307.75	% SZS status Theorem for HL402200+4.p
24923.69/4307.75	% SZS status Ended for HL402200+4.p
24923.69/4307.82	% SZS status Started for HL402195+5.p
24923.69/4307.82	% SZS status GaveUp for HL402195+5.p
24923.69/4307.82	% SZS status Ended for HL402195+5.p
24925.95/4308.02	% SZS status Started for HL402197+4.p
24925.95/4308.02	% SZS status GaveUp for HL402197+4.p
24925.95/4308.02	% SZS status Ended for HL402197+4.p
24927.41/4308.36	% SZS status Started for HL402197+5.p
24927.41/4308.36	% SZS status GaveUp for HL402197+5.p
24927.41/4308.36	% SZS status Ended for HL402197+5.p
24932.22/4308.82	% SZS status Started for HL402200+5.p
24932.22/4308.82	% SZS status Theorem for HL402200+5.p
24932.22/4308.82	% SZS status Ended for HL402200+5.p
24943.64/4310.29	% SZS status Started for HL402198+4.p
24943.64/4310.29	% SZS status GaveUp for HL402198+4.p
24943.64/4310.29	% SZS status Ended for HL402198+4.p
24943.64/4310.31	% SZS status Started for HL402198+5.p
24943.64/4310.31	% SZS status GaveUp for HL402198+5.p
24943.64/4310.31	% SZS status Ended for HL402198+5.p
24948.00/4310.80	% SZS status Started for HL402199+4.p
24948.00/4310.80	% SZS status GaveUp for HL402199+4.p
24948.00/4310.80	% SZS status Ended for HL402199+4.p
24974.57/4314.13	% SZS status Started for HL402199+5.p
24974.57/4314.13	% SZS status GaveUp for HL402199+5.p
24974.57/4314.13	% SZS status Ended for HL402199+5.p
24991.24/4316.23	% SZS status Started for HL402201+5.p
24991.24/4316.23	% SZS status GaveUp for HL402201+5.p
24991.24/4316.23	% SZS status Ended for HL402201+5.p
24991.45/4316.26	% SZS status Started for HL402201+4.p
24991.45/4316.26	% SZS status GaveUp for HL402201+4.p
24991.45/4316.26	% SZS status Ended for HL402201+4.p
24994.59/4316.75	% SZS status Started for HL402203+4.p
24994.59/4316.75	% SZS status GaveUp for HL402203+4.p
24994.59/4316.75	% SZS status Ended for HL402203+4.p
24998.12/4317.05	% SZS status Started for HL402203+5.p
24998.12/4317.05	% SZS status GaveUp for HL402203+5.p
24998.12/4317.05	% SZS status Ended for HL402203+5.p
24998.12/4317.10	% SZS status Started for HL402207+4.p
24998.12/4317.10	% SZS status Theorem for HL402207+4.p
24998.12/4317.10	% SZS status Ended for HL402207+4.p
25002.41/4317.61	% SZS status Started for HL402207+5.p
25002.41/4317.61	% SZS status Theorem for HL402207+5.p
25002.41/4317.61	% SZS status Ended for HL402207+5.p
25008.87/4318.53	% SZS status Started for HL402204+5.p
25008.87/4318.53	% SZS status GaveUp for HL402204+5.p
25008.87/4318.53	% SZS status Ended for HL402204+5.p
25011.84/4318.82	% SZS status Started for HL402204+4.p
25011.84/4318.82	% SZS status GaveUp for HL402204+4.p
25011.84/4318.82	% SZS status Ended for HL402204+4.p
25015.49/4319.23	% SZS status Started for HL402205+4.p
25015.49/4319.23	% SZS status GaveUp for HL402205+4.p
25015.49/4319.23	% SZS status Ended for HL402205+4.p
25019.65/4319.77	% SZS status Started for HL402209+4.p
25019.65/4319.77	% SZS status Theorem for HL402209+4.p
25019.65/4319.77	% SZS status Ended for HL402209+4.p
25024.71/4320.43	% SZS status Started for HL402209+5.p
25024.71/4320.43	% SZS status Theorem for HL402209+5.p
25024.71/4320.43	% SZS status Ended for HL402209+5.p
25039.79/4322.34	% SZS status Started for HL402205+5.p
25039.79/4322.34	% SZS status GaveUp for HL402205+5.p
25039.79/4322.34	% SZS status Ended for HL402205+5.p
25055.73/4324.33	% SZS status Started for HL402213+4.p
25055.73/4324.33	% SZS status Theorem for HL402213+4.p
25055.73/4324.33	% SZS status Ended for HL402213+4.p
25056.79/4324.48	% SZS status Started for HL402206+5.p
25056.79/4324.48	% SZS status GaveUp for HL402206+5.p
25056.79/4324.48	% SZS status Ended for HL402206+5.p
25057.43/4324.55	% SZS status Started for HL402206+4.p
25057.43/4324.55	% SZS status GaveUp for HL402206+4.p
25057.43/4324.55	% SZS status Ended for HL402206+4.p
25074.49/4326.72	% SZS status Started for HL402214+4.p
25074.49/4326.72	% SZS status Theorem for HL402214+4.p
25074.49/4326.72	% SZS status Ended for HL402214+4.p
25075.16/4326.87	% SZS status Started for HL402210+4.p
25075.16/4326.87	% SZS status GaveUp for HL402210+4.p
25075.16/4326.87	% SZS status Ended for HL402210+4.p
25079.02/4327.28	% SZS status Started for HL402210+5.p
25079.02/4327.28	% SZS status GaveUp for HL402210+5.p
25079.02/4327.28	% SZS status Ended for HL402210+5.p
25081.96/4327.62	% SZS status Started for HL402212+4.p
25081.96/4327.62	% SZS status GaveUp for HL402212+4.p
25081.96/4327.62	% SZS status Ended for HL402212+4.p
25084.11/4328.00	% SZS status Started for HL402212+5.p
25084.11/4328.00	% SZS status GaveUp for HL402212+5.p
25084.11/4328.00	% SZS status Ended for HL402212+5.p
25105.23/4330.57	% SZS status Started for HL402213+5.p
25105.23/4330.57	% SZS status GaveUp for HL402213+5.p
25105.23/4330.57	% SZS status Ended for HL402213+5.p
25108.52/4331.00	% SZS status Started for HL402217+4.p
25108.52/4331.00	% SZS status Theorem for HL402217+4.p
25108.52/4331.00	% SZS status Ended for HL402217+4.p
25123.75/4332.90	% SZS status Started for HL402215+4.p
25123.75/4332.90	% SZS status GaveUp for HL402215+4.p
25123.75/4332.90	% SZS status Ended for HL402215+4.p
25124.19/4332.96	% SZS status Started for HL402214+5.p
25124.19/4332.96	% SZS status GaveUp for HL402214+5.p
25124.19/4332.96	% SZS status Ended for HL402214+5.p
25127.23/4333.40	% SZS status Started for HL402219+4.p
25127.23/4333.40	% SZS status Theorem for HL402219+4.p
25127.23/4333.40	% SZS status Ended for HL402219+4.p
25135.93/4334.47	% SZS status Started for HL402220+4.p
25135.93/4334.47	% SZS status Theorem for HL402220+4.p
25135.93/4334.47	% SZS status Ended for HL402220+4.p
25139.73/4334.95	% SZS status Started for HL402215+5.p
25139.73/4334.95	% SZS status GaveUp for HL402215+5.p
25139.73/4334.95	% SZS status Ended for HL402215+5.p
25142.48/4335.29	% SZS status Started for HL402216+4.p
25142.48/4335.29	% SZS status GaveUp for HL402216+4.p
25142.48/4335.29	% SZS status Ended for HL402216+4.p
25142.48/4335.31	% SZS status Started for HL402222+4.p
25142.48/4335.31	% SZS status Theorem for HL402222+4.p
25142.48/4335.31	% SZS status Ended for HL402222+4.p
25144.40/4335.49	% SZS status Started for HL402216+5.p
25144.40/4335.49	% SZS status GaveUp for HL402216+5.p
25144.40/4335.49	% SZS status Ended for HL402216+5.p
25150.50/4336.26	% SZS status Started for HL402217+5.p
25150.50/4336.26	% SZS status GaveUp for HL402217+5.p
25150.50/4336.26	% SZS status Ended for HL402217+5.p
25161.98/4337.70	% SZS status Started for HL402223+4.p
25161.98/4337.70	% SZS status Theorem for HL402223+4.p
25161.98/4337.70	% SZS status Ended for HL402223+4.p
25174.04/4339.21	% SZS status Started for HL402219+5.p
25174.04/4339.21	% SZS status GaveUp for HL402219+5.p
25174.04/4339.21	% SZS status Ended for HL402219+5.p
25187.32/4340.87	% SZS status Started for HL402223+5.p
25187.32/4340.87	% SZS status Theorem for HL402223+5.p
25187.32/4340.87	% SZS status Ended for HL402223+5.p
25188.89/4341.23	% SZS status Started for HL402220+5.p
25188.89/4341.23	% SZS status GaveUp for HL402220+5.p
25188.89/4341.23	% SZS status Ended for HL402220+5.p
25193.58/4341.86	% SZS status Started for HL402221+4.p
25193.58/4341.86	% SZS status GaveUp for HL402221+4.p
25193.58/4341.86	% SZS status Ended for HL402221+4.p
25201.19/4342.71	% SZS status Started for HL402221+5.p
25201.19/4342.71	% SZS status GaveUp for HL402221+5.p
25201.19/4342.71	% SZS status Ended for HL402221+5.p
25207.52/4343.53	% SZS status Started for HL402222+5.p
25207.52/4343.53	% SZS status GaveUp for HL402222+5.p
25207.52/4343.53	% SZS status Ended for HL402222+5.p
25217.54/4344.65	% SZS status Started for HL402224+4.p
25217.54/4344.65	% SZS status GaveUp for HL402224+4.p
25217.54/4344.65	% SZS status Ended for HL402224+4.p
25227.16/4345.91	% SZS status Started for HL402224+5.p
25227.16/4345.91	% SZS status GaveUp for HL402224+5.p
25227.16/4345.91	% SZS status Ended for HL402224+5.p
25239.87/4347.55	% SZS status Started for HL402225+4.p
25239.87/4347.55	% SZS status GaveUp for HL402225+4.p
25239.87/4347.55	% SZS status Ended for HL402225+4.p
25252.80/4349.13	% SZS status Started for HL402225+5.p
25252.80/4349.13	% SZS status GaveUp for HL402225+5.p
25252.80/4349.13	% SZS status Ended for HL402225+5.p
25254.87/4349.58	% SZS status Started for HL402226+4.p
25254.87/4349.58	% SZS status GaveUp for HL402226+4.p
25254.87/4349.58	% SZS status Ended for HL402226+4.p
25259.87/4350.10	% SZS status Started for HL402226+5.p
25259.87/4350.10	% SZS status GaveUp for HL402226+5.p
25259.87/4350.10	% SZS status Ended for HL402226+5.p
25267.99/4351.13	% SZS status Started for HL402227+4.p
25267.99/4351.13	% SZS status GaveUp for HL402227+4.p
25267.99/4351.13	% SZS status Ended for HL402227+4.p
25273.93/4351.87	% SZS status Started for HL402227+5.p
25273.93/4351.87	% SZS status GaveUp for HL402227+5.p
25273.93/4351.87	% SZS status Ended for HL402227+5.p
25284.24/4353.05	% SZS status Started for HL402228+4.p
25284.24/4353.05	% SZS status GaveUp for HL402228+4.p
25284.24/4353.05	% SZS status Ended for HL402228+4.p
25292.18/4354.14	% SZS status Started for HL402228+5.p
25292.18/4354.14	% SZS status GaveUp for HL402228+5.p
25292.18/4354.14	% SZS status Ended for HL402228+5.p
25307.05/4355.95	% SZS status Started for HL402229+4.p
25307.05/4355.95	% SZS status GaveUp for HL402229+4.p
25307.05/4355.95	% SZS status Ended for HL402229+4.p
25315.93/4357.06	% SZS status Started for HL402232+4.p
25315.93/4357.06	% SZS status Theorem for HL402232+4.p
25315.93/4357.06	% SZS status Ended for HL402232+4.p
25316.96/4357.18	% SZS status Started for HL402232+5.p
25316.96/4357.18	% SZS status Theorem for HL402232+5.p
25316.96/4357.18	% SZS status Ended for HL402232+5.p
25318.23/4357.45	% SZS status Started for HL402229+5.p
25318.23/4357.45	% SZS status GaveUp for HL402229+5.p
25318.23/4357.45	% SZS status Ended for HL402229+5.p
25322.75/4357.93	% SZS status Started for HL402230+4.p
25322.75/4357.93	% SZS status GaveUp for HL402230+4.p
25322.75/4357.93	% SZS status Ended for HL402230+4.p
25326.07/4358.32	% SZS status Started for HL402230+5.p
25326.07/4358.32	% SZS status GaveUp for HL402230+5.p
25326.07/4358.32	% SZS status Ended for HL402230+5.p
25335.63/4359.53	% SZS status Started for HL402231+4.p
25335.63/4359.53	% SZS status GaveUp for HL402231+4.p
25335.63/4359.53	% SZS status Ended for HL402231+4.p
25341.57/4360.29	% SZS status Started for HL402231+5.p
25341.57/4360.29	% SZS status GaveUp for HL402231+5.p
25341.57/4360.29	% SZS status Ended for HL402231+5.p
25373.84/4364.33	% SZS status Started for HL402233+4.p
25373.84/4364.33	% SZS status GaveUp for HL402233+4.p
25373.84/4364.33	% SZS status Ended for HL402233+4.p
25381.02/4365.31	% SZS status Started for HL402233+5.p
25381.02/4365.31	% SZS status GaveUp for HL402233+5.p
25381.02/4365.31	% SZS status Ended for HL402233+5.p
25383.64/4365.61	% SZS status Started for HL402234+4.p
25383.64/4365.61	% SZS status GaveUp for HL402234+4.p
25383.64/4365.61	% SZS status Ended for HL402234+4.p
25384.14/4365.68	% SZS status Started for HL402234+5.p
25384.14/4365.68	% SZS status GaveUp for HL402234+5.p
25384.14/4365.68	% SZS status Ended for HL402234+5.p
25389.29/4366.30	% SZS status Started for HL402235+4.p
25389.29/4366.30	% SZS status GaveUp for HL402235+4.p
25389.29/4366.30	% SZS status Ended for HL402235+4.p
25392.34/4366.70	% SZS status Started for HL402235+5.p
25392.34/4366.70	% SZS status GaveUp for HL402235+5.p
25392.34/4366.70	% SZS status Ended for HL402235+5.p
25400.62/4367.75	% SZS status Started for HL402239+4.p
25400.62/4367.75	% SZS status Theorem for HL402239+4.p
25400.62/4367.75	% SZS status Ended for HL402239+4.p
25401.63/4367.91	% SZS status Started for HL402237+4.p
25401.63/4367.91	% SZS status GaveUp for HL402237+4.p
25401.63/4367.91	% SZS status Ended for HL402237+4.p
25402.93/4368.13	% SZS status Started for HL402241+4.p
25402.93/4368.13	% SZS status Theorem for HL402241+4.p
25402.93/4368.13	% SZS status Ended for HL402241+4.p
25407.09/4368.55	% SZS status Started for HL402237+5.p
25407.09/4368.55	% SZS status GaveUp for HL402237+5.p
25407.09/4368.55	% SZS status Ended for HL402237+5.p
25410.45/4369.00	% SZS status Started for HL402241+5.p
25410.45/4369.00	% SZS status Theorem for HL402241+5.p
25410.45/4369.00	% SZS status Ended for HL402241+5.p
25425.43/4371.08	% SZS status Started for HL402239+5.p
25425.43/4371.08	% SZS status Theorem for HL402239+5.p
25425.43/4371.08	% SZS status Ended for HL402239+5.p
25438.94/4372.70	% SZS status Started for HL402238+4.p
25438.94/4372.70	% SZS status GaveUp for HL402238+4.p
25438.94/4372.70	% SZS status Ended for HL402238+4.p
25446.67/4373.55	% SZS status Started for HL402238+5.p
25446.67/4373.55	% SZS status GaveUp for HL402238+5.p
25446.67/4373.55	% SZS status Ended for HL402238+5.p
25456.74/4374.85	% SZS status Started for HL402240+4.p
25456.74/4374.85	% SZS status GaveUp for HL402240+4.p
25456.74/4374.85	% SZS status Ended for HL402240+4.p
25457.50/4374.92	% SZS status Started for HL402240+5.p
25457.50/4374.92	% SZS status GaveUp for HL402240+5.p
25457.50/4374.92	% SZS status Ended for HL402240+5.p
25469.76/4376.47	% SZS status Started for HL402242+4.p
25469.76/4376.47	% SZS status GaveUp for HL402242+4.p
25469.76/4376.47	% SZS status Ended for HL402242+4.p
25474.05/4376.98	% SZS status Started for HL402242+5.p
25474.05/4376.98	% SZS status GaveUp for HL402242+5.p
25474.05/4376.98	% SZS status Ended for HL402242+5.p
25477.21/4377.40	% SZS status Started for HL402243+4.p
25477.21/4377.40	% SZS status GaveUp for HL402243+4.p
25477.21/4377.40	% SZS status Ended for HL402243+4.p
25492.29/4379.31	% SZS status Started for HL402243+5.p
25492.29/4379.31	% SZS status GaveUp for HL402243+5.p
25492.29/4379.31	% SZS status Ended for HL402243+5.p
25508.59/4381.35	% SZS status Started for HL402244+4.p
25508.59/4381.35	% SZS status GaveUp for HL402244+4.p
25508.59/4381.35	% SZS status Ended for HL402244+4.p
25511.39/4381.79	% SZS status Started for HL402244+5.p
25511.39/4381.79	% SZS status GaveUp for HL402244+5.p
25511.39/4381.79	% SZS status Ended for HL402244+5.p
25523.41/4383.21	% SZS status Started for HL402245+5.p
25523.41/4383.21	% SZS status GaveUp for HL402245+5.p
25523.41/4383.21	% SZS status Ended for HL402245+5.p
25523.41/4383.23	% SZS status Started for HL402245+4.p
25523.41/4383.23	% SZS status GaveUp for HL402245+4.p
25523.41/4383.23	% SZS status Ended for HL402245+4.p
25536.57/4384.84	% SZS status Started for HL402246+4.p
25536.57/4384.84	% SZS status GaveUp for HL402246+4.p
25536.57/4384.84	% SZS status Ended for HL402246+4.p
25538.31/4385.21	% SZS status Started for HL402246+5.p
25538.31/4385.21	% SZS status GaveUp for HL402246+5.p
25538.31/4385.21	% SZS status Ended for HL402246+5.p
25542.61/4385.72	% SZS status Started for HL402247+4.p
25542.61/4385.72	% SZS status GaveUp for HL402247+4.p
25542.61/4385.72	% SZS status Ended for HL402247+4.p
25558.33/4387.59	% SZS status Started for HL402247+5.p
25558.33/4387.59	% SZS status GaveUp for HL402247+5.p
25558.33/4387.59	% SZS status Ended for HL402247+5.p
25574.39/4389.68	% SZS status Started for HL402248+4.p
25574.39/4389.68	% SZS status GaveUp for HL402248+4.p
25574.39/4389.68	% SZS status Ended for HL402248+4.p
25578.29/4390.08	% SZS status Started for HL402248+5.p
25578.29/4390.08	% SZS status GaveUp for HL402248+5.p
25578.29/4390.08	% SZS status Ended for HL402248+5.p
25587.96/4391.50	% SZS status Started for HL402249+5.p
25587.96/4391.50	% SZS status GaveUp for HL402249+5.p
25587.96/4391.50	% SZS status Ended for HL402249+5.p
25590.55/4391.61	% SZS status Started for HL402249+4.p
25590.55/4391.61	% SZS status GaveUp for HL402249+4.p
25590.55/4391.61	% SZS status Ended for HL402249+4.p
25601.71/4393.17	% SZS status Started for HL402250+4.p
25601.71/4393.17	% SZS status GaveUp for HL402250+4.p
25601.71/4393.17	% SZS status Ended for HL402250+4.p
25604.59/4393.43	% SZS status Started for HL402250+5.p
25604.59/4393.43	% SZS status GaveUp for HL402250+5.p
25604.59/4393.43	% SZS status Ended for HL402250+5.p
25609.50/4394.10	% SZS status Started for HL402251+4.p
25609.50/4394.10	% SZS status GaveUp for HL402251+4.p
25609.50/4394.10	% SZS status Ended for HL402251+4.p
25623.57/4395.88	% SZS status Started for HL402251+5.p
25623.57/4395.88	% SZS status GaveUp for HL402251+5.p
25623.57/4395.88	% SZS status Ended for HL402251+5.p
25641.20/4398.00	% SZS status Started for HL402252+4.p
25641.20/4398.00	% SZS status GaveUp for HL402252+4.p
25641.20/4398.00	% SZS status Ended for HL402252+4.p
25643.98/4398.35	% SZS status Started for HL402252+5.p
25643.98/4398.35	% SZS status GaveUp for HL402252+5.p
25643.98/4398.35	% SZS status Ended for HL402252+5.p
25649.12/4399.06	% SZS status Started for HL402257+5.p
25649.12/4399.06	% SZS status Theorem for HL402257+5.p
25649.12/4399.06	% SZS status Ended for HL402257+5.p
25655.31/4399.84	% SZS status Started for HL402254+5.p
25655.31/4399.84	% SZS status GaveUp for HL402254+5.p
25655.31/4399.84	% SZS status Ended for HL402254+5.p
25655.31/4399.87	% SZS status Started for HL402254+4.p
25655.31/4399.87	% SZS status GaveUp for HL402254+4.p
25655.31/4399.87	% SZS status Ended for HL402254+4.p
25667.95/4401.44	% SZS status Started for HL402257+4.p
25667.95/4401.44	% SZS status Theorem for HL402257+4.p
25667.95/4401.44	% SZS status Ended for HL402257+4.p
25668.64/4401.54	% SZS status Started for HL402255+4.p
25668.64/4401.54	% SZS status GaveUp for HL402255+4.p
25668.64/4401.54	% SZS status Ended for HL402255+4.p
25668.97/4401.66	% SZS status Started for HL402255+5.p
25668.97/4401.66	% SZS status GaveUp for HL402255+5.p
25668.97/4401.66	% SZS status Ended for HL402255+5.p
25668.97/4401.67	% SZS status Started for HL402258+4.p
25668.97/4401.67	% SZS status Theorem for HL402258+4.p
25668.97/4401.67	% SZS status Ended for HL402258+4.p
25672.06/4401.88	% SZS status Started for HL402262+4.p
25672.06/4401.88	% SZS status Theorem for HL402262+4.p
25672.06/4401.88	% SZS status Ended for HL402262+4.p
25678.28/4402.64	% SZS status Started for HL402256+4.p
25678.28/4402.64	% SZS status GaveUp for HL402256+4.p
25678.28/4402.64	% SZS status Ended for HL402256+4.p
25690.21/4404.20	% SZS status Started for HL402256+5.p
25690.21/4404.20	% SZS status GaveUp for HL402256+5.p
25690.21/4404.20	% SZS status Ended for HL402256+5.p
25698.65/4405.18	% SZS status Started for HL402258+5.p
25698.65/4405.18	% SZS status Theorem for HL402258+5.p
25698.65/4405.18	% SZS status Ended for HL402258+5.p
25722.06/4408.25	% SZS status Started for HL402259+4.p
25722.06/4408.25	% SZS status GaveUp for HL402259+4.p
25722.06/4408.25	% SZS status Ended for HL402259+4.p
25734.81/4409.78	% SZS status Started for HL402259+5.p
25734.81/4409.78	% SZS status GaveUp for HL402259+5.p
25734.81/4409.78	% SZS status Ended for HL402259+5.p
25736.38/4409.93	% SZS status Started for HL402262+5.p
25736.38/4409.93	% SZS status GaveUp for HL402262+5.p
25736.38/4409.93	% SZS status Ended for HL402262+5.p
25736.94/4410.04	% SZS status Started for HL402264+4.p
25736.94/4410.04	% SZS status GaveUp for HL402264+4.p
25736.94/4410.04	% SZS status Ended for HL402264+4.p
25737.66/4410.17	% SZS status Started for HL402264+5.p
25737.66/4410.17	% SZS status GaveUp for HL402264+5.p
25737.66/4410.17	% SZS status Ended for HL402264+5.p
25744.78/4411.02	% SZS status Started for HL402265+4.p
25744.78/4411.02	% SZS status GaveUp for HL402265+4.p
25744.78/4411.02	% SZS status Ended for HL402265+4.p
25748.79/4411.72	% SZS status Started for HL402270+4.p
25748.79/4411.72	% SZS status Theorem for HL402270+4.p
25748.79/4411.72	% SZS status Ended for HL402270+4.p
25756.32/4412.46	% SZS status Started for HL402265+5.p
25756.32/4412.46	% SZS status GaveUp for HL402265+5.p
25756.32/4412.46	% SZS status Ended for HL402265+5.p
25763.85/4413.57	% SZS status Started for HL402266+4.p
25763.85/4413.57	% SZS status GaveUp for HL402266+4.p
25763.85/4413.57	% SZS status Ended for HL402266+4.p
25788.17/4416.48	% SZS status Started for HL402266+5.p
25788.17/4416.48	% SZS status GaveUp for HL402266+5.p
25788.17/4416.48	% SZS status Ended for HL402266+5.p
25801.32/4418.16	% SZS status Started for HL402267+4.p
25801.32/4418.16	% SZS status GaveUp for HL402267+4.p
25801.32/4418.16	% SZS status Ended for HL402267+4.p
25802.10/4418.18	% SZS status Started for HL402267+5.p
25802.10/4418.18	% SZS status GaveUp for HL402267+5.p
25802.10/4418.18	% SZS status Ended for HL402267+5.p
25803.48/4418.47	% SZS status Started for HL402269+4.p
25803.48/4418.47	% SZS status GaveUp for HL402269+4.p
25803.48/4418.47	% SZS status Ended for HL402269+4.p
25804.03/4418.47	% SZS status Started for HL402269+5.p
25804.03/4418.47	% SZS status GaveUp for HL402269+5.p
25804.03/4418.47	% SZS status Ended for HL402269+5.p
25814.23/4419.96	% SZS status Started for HL402270+5.p
25814.23/4419.96	% SZS status GaveUp for HL402270+5.p
25814.23/4419.96	% SZS status Ended for HL402270+5.p
25823.10/4420.83	% SZS status Started for HL402271+4.p
25823.10/4420.83	% SZS status GaveUp for HL402271+4.p
25823.10/4420.83	% SZS status Ended for HL402271+4.p
25830.22/4421.81	% SZS status Started for HL402271+5.p
25830.22/4421.81	% SZS status GaveUp for HL402271+5.p
25830.22/4421.81	% SZS status Ended for HL402271+5.p
25855.17/4424.86	% SZS status Started for HL402273+4.p
25855.17/4424.86	% SZS status GaveUp for HL402273+4.p
25855.17/4424.86	% SZS status Ended for HL402273+4.p
25866.13/4426.44	% SZS status Started for HL402273+5.p
25866.13/4426.44	% SZS status GaveUp for HL402273+5.p
25866.13/4426.44	% SZS status Ended for HL402273+5.p
25866.41/4426.59	% SZS status Started for HL402275+4.p
25866.41/4426.59	% SZS status GaveUp for HL402275+4.p
25866.41/4426.59	% SZS status Ended for HL402275+4.p
25869.74/4426.70	% SZS status Started for HL402275+5.p
25869.74/4426.70	% SZS status GaveUp for HL402275+5.p
25869.74/4426.70	% SZS status Ended for HL402275+5.p
25871.33/4427.03	% SZS status Started for HL402276+4.p
25871.33/4427.03	% SZS status GaveUp for HL402276+4.p
25871.33/4427.03	% SZS status Ended for HL402276+4.p
25881.54/4428.21	% SZS status Started for HL402276+5.p
25881.54/4428.21	% SZS status GaveUp for HL402276+5.p
25881.54/4428.21	% SZS status Ended for HL402276+5.p
25888.10/4429.18	% SZS status Started for HL402277+4.p
25888.10/4429.18	% SZS status GaveUp for HL402277+4.p
25888.10/4429.18	% SZS status Ended for HL402277+4.p
25896.00/4430.02	% SZS status Started for HL402277+5.p
25896.00/4430.02	% SZS status GaveUp for HL402277+5.p
25896.00/4430.02	% SZS status Ended for HL402277+5.p
25921.53/4433.23	% SZS status Started for HL402281+4.p
25921.53/4433.23	% SZS status Theorem for HL402281+4.p
25921.53/4433.23	% SZS status Ended for HL402281+4.p
25922.23/4433.28	% SZS status Started for HL402278+4.p
25922.23/4433.28	% SZS status GaveUp for HL402278+4.p
25922.23/4433.28	% SZS status Ended for HL402278+4.p
25932.01/4434.68	% SZS status Started for HL402278+5.p
25932.01/4434.68	% SZS status GaveUp for HL402278+5.p
25932.01/4434.68	% SZS status Ended for HL402278+5.p
25935.33/4434.92	% SZS status Started for HL402279+5.p
25935.33/4434.92	% SZS status GaveUp for HL402279+5.p
25935.33/4434.92	% SZS status Ended for HL402279+5.p
25935.33/4434.97	% SZS status Started for HL402279+4.p
25935.33/4434.97	% SZS status GaveUp for HL402279+4.p
25935.33/4434.97	% SZS status Ended for HL402279+4.p
25937.86/4435.47	% SZS status Started for HL402280+4.p
25937.86/4435.47	% SZS status GaveUp for HL402280+4.p
25937.86/4435.47	% SZS status Ended for HL402280+4.p
25946.96/4436.44	% SZS status Started for HL402280+5.p
25946.96/4436.44	% SZS status GaveUp for HL402280+5.p
25946.96/4436.44	% SZS status Ended for HL402280+5.p
25961.86/4438.39	% SZS status Started for HL402281+5.p
25961.86/4438.39	% SZS status GaveUp for HL402281+5.p
25961.86/4438.39	% SZS status Ended for HL402281+5.p
25987.60/4441.51	% SZS status Started for HL402282+5.p
25987.60/4441.51	% SZS status GaveUp for HL402282+5.p
25987.60/4441.51	% SZS status Ended for HL402282+5.p
25988.28/4441.60	% SZS status Started for HL402282+4.p
25988.28/4441.60	% SZS status GaveUp for HL402282+4.p
25988.28/4441.60	% SZS status Ended for HL402282+4.p
25999.72/4443.10	% SZS status Started for HL402283+4.p
25999.72/4443.10	% SZS status GaveUp for HL402283+4.p
25999.72/4443.10	% SZS status Ended for HL402283+4.p
26000.36/4443.13	% SZS status Started for HL402283+5.p
26000.36/4443.13	% SZS status GaveUp for HL402283+5.p
26000.36/4443.13	% SZS status Ended for HL402283+5.p
26001.49/4443.39	% SZS status Started for HL402284+4.p
26001.49/4443.39	% SZS status GaveUp for HL402284+4.p
26001.49/4443.39	% SZS status Ended for HL402284+4.p
26004.65/4443.71	% SZS status Started for HL402284+5.p
26004.65/4443.71	% SZS status GaveUp for HL402284+5.p
26004.65/4443.71	% SZS status Ended for HL402284+5.p
26010.25/4444.36	% SZS status Started for HL402289+5.p
26010.25/4444.36	% SZS status Theorem for HL402289+5.p
26010.25/4444.36	% SZS status Ended for HL402289+5.p
26013.88/4444.80	% SZS status Started for HL402286+4.p
26013.88/4444.80	% SZS status GaveUp for HL402286+4.p
26013.88/4444.80	% SZS status Ended for HL402286+4.p
26014.63/4444.97	% SZS status Started for HL402290+5.p
26014.63/4444.97	% SZS status Theorem for HL402290+5.p
26014.63/4444.97	% SZS status Ended for HL402290+5.p
26020.75/4445.86	% SZS status Started for HL402289+4.p
26020.75/4445.86	% SZS status Theorem for HL402289+4.p
26020.75/4445.86	% SZS status Ended for HL402289+4.p
26023.43/4446.17	% SZS status Started for HL402290+4.p
26023.43/4446.17	% SZS status Theorem for HL402290+4.p
26023.43/4446.17	% SZS status Ended for HL402290+4.p
26031.86/4447.27	% SZS status Started for HL402286+5.p
26031.86/4447.27	% SZS status GaveUp for HL402286+5.p
26031.86/4447.27	% SZS status Ended for HL402286+5.p
26053.47/4449.94	% SZS status Started for HL402288+5.p
26053.47/4449.94	% SZS status GaveUp for HL402288+5.p
26053.47/4449.94	% SZS status Ended for HL402288+5.p
26054.84/4450.10	% SZS status Started for HL402288+4.p
26054.84/4450.10	% SZS status GaveUp for HL402288+4.p
26054.84/4450.10	% SZS status Ended for HL402288+4.p
26078.26/4453.11	% SZS status Started for HL402291+4.p
26078.26/4453.11	% SZS status GaveUp for HL402291+4.p
26078.26/4453.11	% SZS status Ended for HL402291+4.p
26081.35/4453.58	% SZS status Started for HL402291+5.p
26081.35/4453.58	% SZS status GaveUp for HL402291+5.p
26081.35/4453.58	% SZS status Ended for HL402291+5.p
26081.79/4453.76	% SZS status Started for HL402292+4.p
26081.79/4453.76	% SZS status GaveUp for HL402292+4.p
26081.79/4453.76	% SZS status Ended for HL402292+4.p
26087.69/4454.23	% SZS status Started for HL402292+5.p
26087.69/4454.23	% SZS status GaveUp for HL402292+5.p
26087.69/4454.23	% SZS status Ended for HL402292+5.p
26091.10/4454.80	% SZS status Started for HL402293+4.p
26091.10/4454.80	% SZS status GaveUp for HL402293+4.p
26091.10/4454.80	% SZS status Ended for HL402293+4.p
26097.83/4455.48	% SZS status Started for HL402293+5.p
26097.83/4455.48	% SZS status GaveUp for HL402293+5.p
26097.83/4455.48	% SZS status Ended for HL402293+5.p
26119.37/4458.34	% SZS status Started for HL402294+5.p
26119.37/4458.34	% SZS status GaveUp for HL402294+5.p
26119.37/4458.34	% SZS status Ended for HL402294+5.p
26119.37/4458.36	% SZS status Started for HL402294+4.p
26119.37/4458.36	% SZS status GaveUp for HL402294+4.p
26119.37/4458.36	% SZS status Ended for HL402294+4.p
26145.93/4461.53	% SZS status Started for HL402296+4.p
26145.93/4461.53	% SZS status GaveUp for HL402296+4.p
26145.93/4461.53	% SZS status Ended for HL402296+4.p
26148.12/4461.82	% SZS status Started for HL402296+5.p
26148.12/4461.82	% SZS status GaveUp for HL402296+5.p
26148.12/4461.82	% SZS status Ended for HL402296+5.p
26150.29/4462.18	% SZS status Started for HL402297+4.p
26150.29/4462.18	% SZS status GaveUp for HL402297+4.p
26150.29/4462.18	% SZS status Ended for HL402297+4.p
26153.22/4462.51	% SZS status Started for HL402297+5.p
26153.22/4462.51	% SZS status GaveUp for HL402297+5.p
26153.22/4462.51	% SZS status Ended for HL402297+5.p
26159.10/4463.20	% SZS status Started for HL402298+4.p
26159.10/4463.20	% SZS status GaveUp for HL402298+4.p
26159.10/4463.20	% SZS status Ended for HL402298+4.p
26162.89/4463.77	% SZS status Started for HL402298+5.p
26162.89/4463.77	% SZS status GaveUp for HL402298+5.p
26162.89/4463.77	% SZS status Ended for HL402298+5.p
26186.81/4466.69	% SZS status Started for HL402300+5.p
26186.81/4466.69	% SZS status GaveUp for HL402300+5.p
26186.81/4466.69	% SZS status Ended for HL402300+5.p
26187.03/4466.75	% SZS status Started for HL402300+4.p
26187.03/4466.75	% SZS status GaveUp for HL402300+4.p
26187.03/4466.75	% SZS status Ended for HL402300+4.p
26213.11/4470.00	% SZS status Started for HL402302+4.p
26213.11/4470.00	% SZS status GaveUp for HL402302+4.p
26213.11/4470.00	% SZS status Ended for HL402302+4.p
26213.11/4470.04	% SZS status Started for HL402302+5.p
26213.11/4470.04	% SZS status GaveUp for HL402302+5.p
26213.11/4470.04	% SZS status Ended for HL402302+5.p
26217.79/4470.65	% SZS status Started for HL402303+4.p
26217.79/4470.65	% SZS status GaveUp for HL402303+4.p
26217.79/4470.65	% SZS status Ended for HL402303+4.p
26218.28/4470.74	% SZS status Started for HL402303+5.p
26218.28/4470.74	% SZS status GaveUp for HL402303+5.p
26218.28/4470.74	% SZS status Ended for HL402303+5.p
26226.88/4471.79	% SZS status Started for HL402304+4.p
26226.88/4471.79	% SZS status GaveUp for HL402304+4.p
26226.88/4471.79	% SZS status Ended for HL402304+4.p
26228.70/4472.00	% SZS status Started for HL402304+5.p
26228.70/4472.00	% SZS status GaveUp for HL402304+5.p
26228.70/4472.00	% SZS status Ended for HL402304+5.p
26252.98/4475.11	% SZS status Started for HL402305+4.p
26252.98/4475.11	% SZS status GaveUp for HL402305+4.p
26252.98/4475.11	% SZS status Ended for HL402305+4.p
26254.43/4475.35	% SZS status Started for HL402305+5.p
26254.43/4475.35	% SZS status GaveUp for HL402305+5.p
26254.43/4475.35	% SZS status Ended for HL402305+5.p
26277.87/4478.27	% SZS status Started for HL402306+5.p
26277.87/4478.27	% SZS status GaveUp for HL402306+5.p
26277.87/4478.27	% SZS status Ended for HL402306+5.p
26281.08/4478.73	% SZS status Started for HL402306+4.p
26281.08/4478.73	% SZS status GaveUp for HL402306+4.p
26281.08/4478.73	% SZS status Ended for HL402306+4.p
26285.07/4479.22	% SZS status Started for HL402307+5.p
26285.07/4479.22	% SZS status GaveUp for HL402307+5.p
26285.07/4479.22	% SZS status Ended for HL402307+5.p
26286.63/4479.47	% SZS status Started for HL402307+4.p
26286.63/4479.47	% SZS status GaveUp for HL402307+4.p
26286.63/4479.47	% SZS status Ended for HL402307+4.p
26293.34/4480.24	% SZS status Started for HL402308+5.p
26293.34/4480.24	% SZS status GaveUp for HL402308+5.p
26293.34/4480.24	% SZS status Ended for HL402308+5.p
26294.39/4480.43	% SZS status Started for HL402308+4.p
26294.39/4480.43	% SZS status GaveUp for HL402308+4.p
26294.39/4480.43	% SZS status Ended for HL402308+4.p
26319.51/4483.59	% SZS status Started for HL402309+4.p
26319.51/4483.59	% SZS status GaveUp for HL402309+4.p
26319.51/4483.59	% SZS status Ended for HL402309+4.p
26320.84/4483.87	% SZS status Started for HL402309+5.p
26320.84/4483.87	% SZS status GaveUp for HL402309+5.p
26320.84/4483.87	% SZS status Ended for HL402309+5.p
26344.38/4486.83	% SZS status Started for HL402310+4.p
26344.38/4486.83	% SZS status GaveUp for HL402310+4.p
26344.38/4486.83	% SZS status Ended for HL402310+4.p
26346.00/4486.99	% SZS status Started for HL402310+5.p
26346.00/4486.99	% SZS status GaveUp for HL402310+5.p
26346.00/4486.99	% SZS status Ended for HL402310+5.p
26352.87/4487.90	% SZS status Started for HL402311+5.p
26352.87/4487.90	% SZS status GaveUp for HL402311+5.p
26352.87/4487.90	% SZS status Ended for HL402311+5.p
26353.14/4487.95	% SZS status Started for HL402311+4.p
26353.14/4487.95	% SZS status GaveUp for HL402311+4.p
26353.14/4487.95	% SZS status Ended for HL402311+4.p
26359.54/4488.68	% SZS status Started for HL402312+4.p
26359.54/4488.68	% SZS status GaveUp for HL402312+4.p
26359.54/4488.68	% SZS status Ended for HL402312+4.p
26359.89/4488.73	% SZS status Started for HL402312+5.p
26359.89/4488.73	% SZS status GaveUp for HL402312+5.p
26359.89/4488.73	% SZS status Ended for HL402312+5.p
26384.86/4492.00	% SZS status Started for HL402313+4.p
26384.86/4492.00	% SZS status GaveUp for HL402313+4.p
26384.86/4492.00	% SZS status Ended for HL402313+4.p
26388.30/4492.36	% SZS status Started for HL402313+5.p
26388.30/4492.36	% SZS status GaveUp for HL402313+5.p
26388.30/4492.36	% SZS status Ended for HL402313+5.p
26411.60/4495.24	% SZS status Started for HL402316+4.p
26411.60/4495.24	% SZS status GaveUp for HL402316+4.p
26411.60/4495.24	% SZS status Ended for HL402316+4.p
26412.33/4495.40	% SZS status Started for HL402316+5.p
26412.33/4495.40	% SZS status GaveUp for HL402316+5.p
26412.33/4495.40	% SZS status Ended for HL402316+5.p
26419.81/4496.25	% SZS status Started for HL402317+5.p
26419.81/4496.25	% SZS status GaveUp for HL402317+5.p
26419.81/4496.25	% SZS status Ended for HL402317+5.p
26420.53/4496.42	% SZS status Started for HL402317+4.p
26420.53/4496.42	% SZS status GaveUp for HL402317+4.p
26420.53/4496.42	% SZS status Ended for HL402317+4.p
26424.98/4496.98	% SZS status Started for HL402318+5.p
26424.98/4496.98	% SZS status GaveUp for HL402318+5.p
26424.98/4496.98	% SZS status Ended for HL402318+5.p
26426.93/4497.11	% SZS status Started for HL402318+4.p
26426.93/4497.11	% SZS status GaveUp for HL402318+4.p
26426.93/4497.11	% SZS status Ended for HL402318+4.p
26453.03/4500.41	% SZS status Started for HL402319+4.p
26453.03/4500.41	% SZS status GaveUp for HL402319+4.p
26453.03/4500.41	% SZS status Ended for HL402319+4.p
26454.10/4500.64	% SZS status Started for HL402319+5.p
26454.10/4500.64	% SZS status GaveUp for HL402319+5.p
26454.10/4500.64	% SZS status Ended for HL402319+5.p
26478.51/4503.61	% SZS status Started for HL402321+4.p
26478.51/4503.61	% SZS status GaveUp for HL402321+4.p
26478.51/4503.61	% SZS status Ended for HL402321+4.p
26478.51/4503.64	% SZS status Started for HL402321+5.p
26478.51/4503.64	% SZS status GaveUp for HL402321+5.p
26478.51/4503.64	% SZS status Ended for HL402321+5.p
26487.50/4504.74	% SZS status Started for HL402322+5.p
26487.50/4504.74	% SZS status GaveUp for HL402322+5.p
26487.50/4504.74	% SZS status Ended for HL402322+5.p
26487.80/4504.76	% SZS status Started for HL402322+4.p
26487.80/4504.76	% SZS status GaveUp for HL402322+4.p
26487.80/4504.76	% SZS status Ended for HL402322+4.p
26490.28/4505.14	% SZS status Started for HL402327+4.p
26490.28/4505.14	% SZS status Theorem for HL402327+4.p
26490.28/4505.14	% SZS status Ended for HL402327+4.p
26492.43/4505.39	% SZS status Started for HL402323+5.p
26492.43/4505.39	% SZS status GaveUp for HL402323+5.p
26492.43/4505.39	% SZS status Ended for HL402323+5.p
26492.85/4505.40	% SZS status Started for HL402323+4.p
26492.85/4505.40	% SZS status GaveUp for HL402323+4.p
26492.85/4505.40	% SZS status Ended for HL402323+4.p
26494.08/4505.68	% SZS status Started for HL402328+4.p
26494.08/4505.68	% SZS status Theorem for HL402328+4.p
26494.08/4505.68	% SZS status Ended for HL402328+4.p
26495.08/4505.79	% SZS status Started for HL402329+4.p
26495.08/4505.79	% SZS status Theorem for HL402329+4.p
26495.08/4505.79	% SZS status Ended for HL402329+4.p
26497.48/4506.14	% SZS status Started for HL402330+4.p
26497.48/4506.14	% SZS status Theorem for HL402330+4.p
26497.48/4506.14	% SZS status Ended for HL402330+4.p
26498.32/4506.43	% SZS status Started for HL402330+5.p
26498.32/4506.43	% SZS status Theorem for HL402330+5.p
26498.32/4506.43	% SZS status Ended for HL402330+5.p
26503.96/4506.85	% SZS status Started for HL402329+5.p
26503.96/4506.85	% SZS status Theorem for HL402329+5.p
26503.96/4506.85	% SZS status Ended for HL402329+5.p
26519.47/4508.82	% SZS status Started for HL402324+4.p
26519.47/4508.82	% SZS status GaveUp for HL402324+4.p
26519.47/4508.82	% SZS status Ended for HL402324+4.p
26520.74/4508.96	% SZS status Started for HL402324+5.p
26520.74/4508.96	% SZS status GaveUp for HL402324+5.p
26520.74/4508.96	% SZS status Ended for HL402324+5.p
26544.39/4511.96	% SZS status Started for HL402325+5.p
26544.39/4511.96	% SZS status GaveUp for HL402325+5.p
26544.39/4511.96	% SZS status Ended for HL402325+5.p
26545.27/4512.13	% SZS status Started for HL402325+4.p
26545.27/4512.13	% SZS status GaveUp for HL402325+4.p
26545.27/4512.13	% SZS status Ended for HL402325+4.p
26553.32/4513.06	% SZS status Started for HL402327+5.p
26553.32/4513.06	% SZS status GaveUp for HL402327+5.p
26553.32/4513.06	% SZS status Ended for HL402327+5.p
26558.67/4513.69	% SZS status Started for HL402328+5.p
26558.67/4513.69	% SZS status GaveUp for HL402328+5.p
26558.67/4513.69	% SZS status Ended for HL402328+5.p
26568.01/4514.89	% SZS status Started for HL402331+4.p
26568.01/4514.89	% SZS status GaveUp for HL402331+4.p
26568.01/4514.89	% SZS status Ended for HL402331+4.p
26569.88/4515.17	% SZS status Started for HL402331+5.p
26569.88/4515.17	% SZS status GaveUp for HL402331+5.p
26569.88/4515.17	% SZS status Ended for HL402331+5.p
26575.14/4515.77	% SZS status Started for HL402336+5.p
26575.14/4515.77	% SZS status Theorem for HL402336+5.p
26575.14/4515.77	% SZS status Ended for HL402336+5.p
26575.81/4515.85	% SZS status Started for HL402336+4.p
26575.81/4515.85	% SZS status Theorem for HL402336+4.p
26575.81/4515.85	% SZS status Ended for HL402336+4.p
26586.57/4517.28	% SZS status Started for HL402332+5.p
26586.57/4517.28	% SZS status GaveUp for HL402332+5.p
26586.57/4517.28	% SZS status Ended for HL402332+5.p
26587.51/4517.48	% SZS status Started for HL402332+4.p
26587.51/4517.48	% SZS status GaveUp for HL402332+4.p
26587.51/4517.48	% SZS status Ended for HL402332+4.p
26589.82/4517.66	% SZS status Started for HL402338+4.p
26589.82/4517.66	% SZS status Theorem for HL402338+4.p
26589.82/4517.66	% SZS status Ended for HL402338+4.p
26610.39/4520.35	% SZS status Started for HL402334+4.p
26610.39/4520.35	% SZS status GaveUp for HL402334+4.p
26610.39/4520.35	% SZS status Ended for HL402334+4.p
26610.39/4520.37	% SZS status Started for HL402334+5.p
26610.39/4520.37	% SZS status GaveUp for HL402334+5.p
26610.39/4520.37	% SZS status Ended for HL402334+5.p
26619.56/4521.46	% SZS status Started for HL402335+4.p
26619.56/4521.46	% SZS status GaveUp for HL402335+4.p
26619.56/4521.46	% SZS status Ended for HL402335+4.p
26623.20/4522.00	% SZS status Started for HL402335+5.p
26623.20/4522.00	% SZS status GaveUp for HL402335+5.p
26623.20/4522.00	% SZS status Ended for HL402335+5.p
26628.24/4522.60	% SZS status Started for HL402337+4.p
26628.24/4522.60	% SZS status Theorem for HL402337+4.p
26628.24/4522.60	% SZS status Ended for HL402337+4.p
26638.65/4524.09	% SZS status Started for HL402337+5.p
26638.65/4524.09	% SZS status GaveUp for HL402337+5.p
26638.65/4524.09	% SZS status Ended for HL402337+5.p
26652.01/4525.49	% SZS status Started for HL402342+4.p
26652.01/4525.49	% SZS status Theorem for HL402342+4.p
26652.01/4525.49	% SZS status Ended for HL402342+4.p
26653.47/4525.79	% SZS status Started for HL402338+5.p
26653.47/4525.79	% SZS status GaveUp for HL402338+5.p
26653.47/4525.79	% SZS status Ended for HL402338+5.p
26656.89/4526.06	% SZS status Started for HL402342+5.p
26656.89/4526.06	% SZS status Theorem for HL402342+5.p
26656.89/4526.06	% SZS status Ended for HL402342+5.p
26658.55/4526.35	% SZS status Started for HL402340+5.p
26658.55/4526.35	% SZS status Theorem for HL402340+5.p
26658.55/4526.35	% SZS status Ended for HL402340+5.p
26659.36/4526.39	% SZS status Started for HL402339+4.p
26659.36/4526.39	% SZS status GaveUp for HL402339+4.p
26659.36/4526.39	% SZS status Ended for HL402339+4.p
26677.52/4528.74	% SZS status Started for HL402339+5.p
26677.52/4528.74	% SZS status GaveUp for HL402339+5.p
26677.52/4528.74	% SZS status Ended for HL402339+5.p
26678.17/4528.78	% SZS status Started for HL402340+4.p
26678.17/4528.78	% SZS status GaveUp for HL402340+4.p
26678.17/4528.78	% SZS status Ended for HL402340+4.p
26693.13/4530.71	% SZS status Started for HL402341+4.p
26693.13/4530.71	% SZS status GaveUp for HL402341+4.p
26693.13/4530.71	% SZS status Ended for HL402341+4.p
26694.60/4530.86	% SZS status Started for HL402341+5.p
26694.60/4530.86	% SZS status GaveUp for HL402341+5.p
26694.60/4530.86	% SZS status Ended for HL402341+5.p
26721.16/4534.20	% SZS status Started for HL402343+4.p
26721.16/4534.20	% SZS status GaveUp for HL402343+4.p
26721.16/4534.20	% SZS status Ended for HL402343+4.p
26721.63/4534.31	% SZS status Started for HL402343+5.p
26721.63/4534.31	% SZS status GaveUp for HL402343+5.p
26721.63/4534.31	% SZS status Ended for HL402343+5.p
26724.99/4534.63	% SZS status Started for HL402347+5.p
26724.99/4534.63	% SZS status GaveUp for HL402347+5.p
26724.99/4534.63	% SZS status Ended for HL402347+5.p
26726.67/4534.89	% SZS status Started for HL402347+4.p
26726.67/4534.89	% SZS status GaveUp for HL402347+4.p
26726.67/4534.89	% SZS status Ended for HL402347+4.p
26744.06/4537.07	% SZS status Started for HL402348+5.p
26744.06/4537.07	% SZS status GaveUp for HL402348+5.p
26744.06/4537.07	% SZS status Ended for HL402348+5.p
26744.54/4537.14	% SZS status Started for HL402348+4.p
26744.54/4537.14	% SZS status GaveUp for HL402348+4.p
26744.54/4537.14	% SZS status Ended for HL402348+4.p
26760.86/4539.14	% SZS status Started for HL402349+4.p
26760.86/4539.14	% SZS status GaveUp for HL402349+4.p
26760.86/4539.14	% SZS status Ended for HL402349+4.p
26761.03/4539.22	% SZS status Started for HL402349+5.p
26761.03/4539.22	% SZS status GaveUp for HL402349+5.p
26761.03/4539.22	% SZS status Ended for HL402349+5.p
26765.75/4539.82	% SZS status Started for HL402353+5.p
26765.75/4539.82	% SZS status Theorem for HL402353+5.p
26765.75/4539.82	% SZS status Ended for HL402353+5.p
26768.63/4540.13	% SZS status Started for HL402353+4.p
26768.63/4540.13	% SZS status Theorem for HL402353+4.p
26768.63/4540.13	% SZS status Ended for HL402353+4.p
26787.80/4542.58	% SZS status Started for HL402350+5.p
26787.80/4542.58	% SZS status GaveUp for HL402350+5.p
26787.80/4542.58	% SZS status Ended for HL402350+5.p
26787.80/4542.63	% SZS status Started for HL402350+4.p
26787.80/4542.63	% SZS status GaveUp for HL402350+4.p
26787.80/4542.63	% SZS status Ended for HL402350+4.p
26791.06/4542.96	% SZS status Started for HL402355+4.p
26791.06/4542.96	% SZS status Theorem for HL402355+4.p
26791.06/4542.96	% SZS status Ended for HL402355+4.p
26791.94/4543.09	% SZS status Started for HL402351+4.p
26791.94/4543.09	% SZS status GaveUp for HL402351+4.p
26791.94/4543.09	% SZS status Ended for HL402351+4.p
26792.34/4543.13	% SZS status Started for HL402351+5.p
26792.34/4543.13	% SZS status GaveUp for HL402351+5.p
26792.34/4543.13	% SZS status Ended for HL402351+5.p
26810.33/4545.46	% SZS status Started for HL402352+5.p
26810.33/4545.46	% SZS status GaveUp for HL402352+5.p
26810.33/4545.46	% SZS status Ended for HL402352+5.p
26810.50/4545.51	% SZS status Started for HL402352+4.p
26810.50/4545.51	% SZS status GaveUp for HL402352+4.p
26810.50/4545.51	% SZS status Ended for HL402352+4.p
26831.23/4548.27	% SZS status Started for HL402354+4.p
26831.23/4548.27	% SZS status GaveUp for HL402354+4.p
26831.23/4548.27	% SZS status Ended for HL402354+4.p
26833.43/4548.53	% SZS status Started for HL402354+5.p
26833.43/4548.53	% SZS status GaveUp for HL402354+5.p
26833.43/4548.53	% SZS status Ended for HL402354+5.p
26855.19/4551.51	% SZS status Started for HL402356+5.p
26855.19/4551.51	% SZS status GaveUp for HL402356+5.p
26855.19/4551.51	% SZS status Ended for HL402356+5.p
26856.09/4551.66	% SZS status Started for HL402356+4.p
26856.09/4551.66	% SZS status GaveUp for HL402356+4.p
26856.09/4551.66	% SZS status Ended for HL402356+4.p
26856.09/4551.71	% SZS status Started for HL402355+5.p
26856.09/4551.71	% SZS status GaveUp for HL402355+5.p
26856.09/4551.71	% SZS status Ended for HL402355+5.p
26856.09/4551.71	% SZS status Started for HL402357+4.p
26856.09/4551.71	% SZS status GaveUp for HL402357+4.p
26856.09/4551.71	% SZS status Ended for HL402357+4.p
26877.78/4554.54	% SZS status Started for HL402357+5.p
26877.78/4554.54	% SZS status Theorem for HL402357+5.p
26877.78/4554.54	% SZS status Ended for HL402357+5.p
26885.55/4555.50	% SZS status Started for HL402358+4.p
26885.55/4555.50	% SZS status GaveUp for HL402358+4.p
26885.55/4555.50	% SZS status Ended for HL402358+4.p
26899.87/4557.41	% SZS status Started for HL402358+5.p
26899.87/4557.41	% SZS status GaveUp for HL402358+5.p
26899.87/4557.41	% SZS status Ended for HL402358+5.p
26903.03/4557.85	% SZS status Started for HL402359+4.p
26903.03/4557.85	% SZS status GaveUp for HL402359+4.p
26903.03/4557.85	% SZS status Ended for HL402359+4.p
26920.21/4560.02	% SZS status Started for HL402359+5.p
26920.21/4560.02	% SZS status GaveUp for HL402359+5.p
26920.21/4560.02	% SZS status Ended for HL402359+5.p
26922.04/4560.24	% SZS status Started for HL402361+4.p
26922.04/4560.24	% SZS status GaveUp for HL402361+4.p
26922.04/4560.24	% SZS status Ended for HL402361+4.p
26922.82/4560.27	% SZS status Started for HL402362+4.p
26922.82/4560.27	% SZS status GaveUp for HL402362+4.p
26922.82/4560.27	% SZS status Ended for HL402362+4.p
26923.15/4560.36	% SZS status Started for HL402361+5.p
26923.15/4560.36	% SZS status GaveUp for HL402361+5.p
26923.15/4560.36	% SZS status Ended for HL402361+5.p
26944.22/4563.03	% SZS status Started for HL402362+5.p
26944.22/4563.03	% SZS status GaveUp for HL402362+5.p
26944.22/4563.03	% SZS status Ended for HL402362+5.p
26950.60/4563.90	% SZS status Started for HL402363+4.p
26950.60/4563.90	% SZS status GaveUp for HL402363+4.p
26950.60/4563.90	% SZS status Ended for HL402363+4.p
26965.56/4565.74	% SZS status Started for HL402363+5.p
26965.56/4565.74	% SZS status GaveUp for HL402363+5.p
26965.56/4565.74	% SZS status Ended for HL402363+5.p
26970.65/4566.38	% SZS status Started for HL402364+4.p
26970.65/4566.38	% SZS status GaveUp for HL402364+4.p
26970.65/4566.38	% SZS status Ended for HL402364+4.p
26985.60/4568.33	% SZS status Started for HL402364+5.p
26985.60/4568.33	% SZS status GaveUp for HL402364+5.p
26985.60/4568.33	% SZS status Ended for HL402364+5.p
26988.55/4568.60	% SZS status Started for HL402365+5.p
26988.55/4568.60	% SZS status GaveUp for HL402365+5.p
26988.55/4568.60	% SZS status Ended for HL402365+5.p
26989.72/4568.76	% SZS status Started for HL402366+4.p
26989.72/4568.76	% SZS status GaveUp for HL402366+4.p
26989.72/4568.76	% SZS status Ended for HL402366+4.p
26991.85/4569.03	% SZS status Started for HL402365+4.p
26991.85/4569.03	% SZS status GaveUp for HL402365+4.p
26991.85/4569.03	% SZS status Ended for HL402365+4.p
26994.30/4569.36	% SZS status Started for HL402369+5.p
26994.30/4569.36	% SZS status Theorem for HL402369+5.p
26994.30/4569.36	% SZS status Ended for HL402369+5.p
27009.80/4571.27	% SZS status Started for HL402366+5.p
27009.80/4571.27	% SZS status GaveUp for HL402366+5.p
27009.80/4571.27	% SZS status Ended for HL402366+5.p
27010.92/4571.43	% SZS status Started for HL402369+4.p
27010.92/4571.43	% SZS status Theorem for HL402369+4.p
27010.92/4571.43	% SZS status Ended for HL402369+4.p
27015.93/4572.10	% SZS status Started for HL402371+5.p
27015.93/4572.10	% SZS status Theorem for HL402371+5.p
27015.93/4572.10	% SZS status Ended for HL402371+5.p
27016.39/4572.16	% SZS status Started for HL402371+4.p
27016.39/4572.16	% SZS status Theorem for HL402371+4.p
27016.39/4572.16	% SZS status Ended for HL402371+4.p
27018.04/4572.31	% SZS status Started for HL402367+4.p
27018.04/4572.31	% SZS status GaveUp for HL402367+4.p
27018.04/4572.31	% SZS status Ended for HL402367+4.p
27019.54/4572.57	% SZS status Started for HL402372+4.p
27019.54/4572.57	% SZS status Theorem for HL402372+4.p
27019.54/4572.57	% SZS status Ended for HL402372+4.p
27020.12/4572.72	% SZS status Started for HL402372+5.p
27020.12/4572.72	% SZS status Theorem for HL402372+5.p
27020.12/4572.72	% SZS status Ended for HL402372+5.p
27031.71/4574.00	% SZS status Started for HL402367+5.p
27031.71/4574.00	% SZS status GaveUp for HL402367+5.p
27031.71/4574.00	% SZS status Ended for HL402367+5.p
27037.30/4574.78	% SZS status Started for HL402368+4.p
27037.30/4574.78	% SZS status GaveUp for HL402368+4.p
27037.30/4574.78	% SZS status Ended for HL402368+4.p
27052.93/4576.68	% SZS status Started for HL402368+5.p
27052.93/4576.68	% SZS status GaveUp for HL402368+5.p
27052.93/4576.68	% SZS status Ended for HL402368+5.p
27059.07/4577.59	% SZS status Started for HL402370+5.p
27059.07/4577.59	% SZS status GaveUp for HL402370+5.p
27059.07/4577.59	% SZS status Ended for HL402370+5.p
27061.21/4577.72	% SZS status Started for HL402370+4.p
27061.21/4577.72	% SZS status GaveUp for HL402370+4.p
27061.21/4577.72	% SZS status Ended for HL402370+4.p
27085.97/4580.87	% SZS status Started for HL402373+4.p
27085.97/4580.87	% SZS status GaveUp for HL402373+4.p
27085.97/4580.87	% SZS status Ended for HL402373+4.p
27085.97/4580.88	% SZS status Started for HL402373+5.p
27085.97/4580.88	% SZS status GaveUp for HL402373+5.p
27085.97/4580.88	% SZS status Ended for HL402373+5.p
27087.75/4581.12	% SZS status Started for HL402374+4.p
27087.75/4581.12	% SZS status GaveUp for HL402374+4.p
27087.75/4581.12	% SZS status Ended for HL402374+4.p
27097.70/4582.34	% SZS status Started for HL402374+5.p
27097.70/4582.34	% SZS status GaveUp for HL402374+5.p
27097.70/4582.34	% SZS status Ended for HL402374+5.p
27105.04/4583.24	% SZS status Started for HL402375+4.p
27105.04/4583.24	% SZS status GaveUp for HL402375+4.p
27105.04/4583.24	% SZS status Ended for HL402375+4.p
27118.08/4584.91	% SZS status Started for HL402375+5.p
27118.08/4584.91	% SZS status GaveUp for HL402375+5.p
27118.08/4584.91	% SZS status Ended for HL402375+5.p
27125.48/4585.97	% SZS status Started for HL402376+4.p
27125.48/4585.97	% SZS status GaveUp for HL402376+4.p
27125.48/4585.97	% SZS status Ended for HL402376+4.p
27126.97/4586.00	% SZS status Started for HL402376+5.p
27126.97/4586.00	% SZS status GaveUp for HL402376+5.p
27126.97/4586.00	% SZS status Ended for HL402376+5.p
27151.55/4589.11	% SZS status Started for HL402377+5.p
27151.55/4589.11	% SZS status GaveUp for HL402377+5.p
27151.55/4589.11	% SZS status Ended for HL402377+5.p
27152.73/4589.24	% SZS status Started for HL402377+4.p
27152.73/4589.24	% SZS status GaveUp for HL402377+4.p
27152.73/4589.24	% SZS status Ended for HL402377+4.p
27155.25/4589.61	% SZS status Started for HL402381+4.p
27155.25/4589.61	% SZS status GaveUp for HL402381+4.p
27155.25/4589.61	% SZS status Ended for HL402381+4.p
27163.50/4590.65	% SZS status Started for HL402381+5.p
27163.50/4590.65	% SZS status GaveUp for HL402381+5.p
27163.50/4590.65	% SZS status Ended for HL402381+5.p
27171.96/4591.68	% SZS status Started for HL402382+4.p
27171.96/4591.68	% SZS status GaveUp for HL402382+4.p
27171.96/4591.68	% SZS status Ended for HL402382+4.p
27184.30/4593.19	% SZS status Started for HL402382+5.p
27184.30/4593.19	% SZS status GaveUp for HL402382+5.p
27184.30/4593.19	% SZS status Ended for HL402382+5.p
27192.65/4594.31	% SZS status Started for HL402383+5.p
27192.65/4594.31	% SZS status GaveUp for HL402383+5.p
27192.65/4594.31	% SZS status Ended for HL402383+5.p
27193.86/4594.41	% SZS status Started for HL402383+4.p
27193.86/4594.41	% SZS status GaveUp for HL402383+4.p
27193.86/4594.41	% SZS status Ended for HL402383+4.p
27218.02/4597.53	% SZS status Started for HL402385+5.p
27218.02/4597.53	% SZS status GaveUp for HL402385+5.p
27218.02/4597.53	% SZS status Ended for HL402385+5.p
27222.32/4597.96	% SZS status Started for HL402385+4.p
27222.32/4597.96	% SZS status GaveUp for HL402385+4.p
27222.32/4597.96	% SZS status Ended for HL402385+4.p
27226.38/4598.53	% SZS status Started for HL402386+4.p
27226.38/4598.53	% SZS status GaveUp for HL402386+4.p
27226.38/4598.53	% SZS status Ended for HL402386+4.p
27229.61/4598.89	% SZS status Started for HL402386+5.p
27229.61/4598.89	% SZS status GaveUp for HL402386+5.p
27229.61/4598.89	% SZS status Ended for HL402386+5.p
27240.58/4600.42	% SZS status Started for HL402387+4.p
27240.58/4600.42	% SZS status GaveUp for HL402387+4.p
27240.58/4600.42	% SZS status Ended for HL402387+4.p
27248.90/4601.42	% SZS status Started for HL402387+5.p
27248.90/4601.42	% SZS status GaveUp for HL402387+5.p
27248.90/4601.42	% SZS status Ended for HL402387+5.p
27259.25/4602.65	% SZS status Started for HL402388+5.p
27259.25/4602.65	% SZS status GaveUp for HL402388+5.p
27259.25/4602.65	% SZS status Ended for HL402388+5.p
27263.11/4603.11	% SZS status Started for HL402388+4.p
27263.11/4603.11	% SZS status GaveUp for HL402388+4.p
27263.11/4603.11	% SZS status Ended for HL402388+4.p
27287.89/4606.22	% SZS status Started for HL402389+5.p
27287.89/4606.22	% SZS status GaveUp for HL402389+5.p
27287.89/4606.22	% SZS status Ended for HL402389+5.p
27288.09/4606.33	% SZS status Started for HL402389+4.p
27288.09/4606.33	% SZS status GaveUp for HL402389+4.p
27288.09/4606.33	% SZS status Ended for HL402389+4.p
27295.73/4607.19	% SZS status Started for HL402390+5.p
27295.73/4607.19	% SZS status GaveUp for HL402390+5.p
27295.73/4607.19	% SZS status Ended for HL402390+5.p
27296.86/4607.46	% SZS status Started for HL402390+4.p
27296.86/4607.46	% SZS status GaveUp for HL402390+4.p
27296.86/4607.46	% SZS status Ended for HL402390+4.p
27302.87/4608.09	% SZS status Started for HL402394+4.p
27302.87/4608.09	% SZS status Theorem for HL402394+4.p
27302.87/4608.09	% SZS status Ended for HL402394+4.p
27309.09/4609.02	% SZS status Started for HL402396+4.p
27309.09/4609.02	% SZS status Theorem for HL402396+4.p
27309.09/4609.02	% SZS status Ended for HL402396+4.p
27309.84/4609.15	% SZS status Started for HL402392+4.p
27309.84/4609.15	% SZS status GaveUp for HL402392+4.p
27309.84/4609.15	% SZS status Ended for HL402392+4.p
27313.81/4609.67	% SZS status Started for HL402392+5.p
27313.81/4609.67	% SZS status GaveUp for HL402392+5.p
27313.81/4609.67	% SZS status Ended for HL402392+5.p
27328.86/4611.42	% SZS status Started for HL402393+4.p
27328.86/4611.42	% SZS status GaveUp for HL402393+4.p
27328.86/4611.42	% SZS status Ended for HL402393+4.p
27328.86/4611.45	% SZS status Started for HL402393+5.p
27328.86/4611.45	% SZS status GaveUp for HL402393+5.p
27328.86/4611.45	% SZS status Ended for HL402393+5.p
27354.45/4614.62	% SZS status Started for HL402394+5.p
27354.45/4614.62	% SZS status GaveUp for HL402394+5.p
27354.45/4614.62	% SZS status Ended for HL402394+5.p
27363.83/4615.77	% SZS status Started for HL402395+5.p
27363.83/4615.77	% SZS status GaveUp for HL402395+5.p
27363.83/4615.77	% SZS status Ended for HL402395+5.p
27365.19/4616.02	% SZS status Started for HL402395+4.p
27365.19/4616.02	% SZS status GaveUp for HL402395+4.p
27365.19/4616.02	% SZS status Ended for HL402395+4.p
27375.90/4617.29	% SZS status Started for HL402396+5.p
27375.90/4617.29	% SZS status GaveUp for HL402396+5.p
27375.90/4617.29	% SZS status Ended for HL402396+5.p
27380.41/4617.94	% SZS status Started for HL402397+5.p
27380.41/4617.94	% SZS status GaveUp for HL402397+5.p
27380.41/4617.94	% SZS status Ended for HL402397+5.p
27380.97/4617.98	% SZS status Started for HL402397+4.p
27380.97/4617.98	% SZS status GaveUp for HL402397+4.p
27380.97/4617.98	% SZS status Ended for HL402397+4.p
27394.86/4619.69	% SZS status Started for HL402398+5.p
27394.86/4619.69	% SZS status GaveUp for HL402398+5.p
27394.86/4619.69	% SZS status Ended for HL402398+5.p
27398.57/4620.18	% SZS status Started for HL402398+4.p
27398.57/4620.18	% SZS status GaveUp for HL402398+4.p
27398.57/4620.18	% SZS status Ended for HL402398+4.p
27424.59/4623.39	% SZS status Started for HL402399+4.p
27424.59/4623.39	% SZS status GaveUp for HL402399+4.p
27424.59/4623.39	% SZS status Ended for HL402399+4.p
27429.40/4624.05	% SZS status Started for HL402399+5.p
27429.40/4624.05	% SZS status GaveUp for HL402399+5.p
27429.40/4624.05	% SZS status Ended for HL402399+5.p
27435.33/4624.84	% SZS status Started for HL402400+4.p
27435.33/4624.84	% SZS status GaveUp for HL402400+4.p
27435.33/4624.84	% SZS status Ended for HL402400+4.p
27441.11/4625.58	% SZS status Started for HL402400+5.p
27441.11/4625.58	% SZS status GaveUp for HL402400+5.p
27441.11/4625.58	% SZS status Ended for HL402400+5.p
27445.90/4626.26	% SZS status Started for HL402402+5.p
27445.90/4626.26	% SZS status GaveUp for HL402402+5.p
27445.90/4626.26	% SZS status Ended for HL402402+5.p
27447.57/4626.28	% SZS status Started for HL402404+4.p
27447.57/4626.28	% SZS status Theorem for HL402404+4.p
27447.57/4626.28	% SZS status Ended for HL402404+4.p
27449.72/4626.72	% SZS status Started for HL402402+4.p
27449.72/4626.72	% SZS status GaveUp for HL402402+4.p
27449.72/4626.72	% SZS status Ended for HL402402+4.p
27463.84/4628.42	% SZS status Started for HL402403+5.p
27463.84/4628.42	% SZS status GaveUp for HL402403+5.p
27463.84/4628.42	% SZS status Ended for HL402403+5.p
27466.09/4628.62	% SZS status Started for HL402403+4.p
27466.09/4628.62	% SZS status GaveUp for HL402403+4.p
27466.09/4628.62	% SZS status Ended for HL402403+4.p
27470.44/4629.17	% SZS status Started for HL402406+4.p
27470.44/4629.17	% SZS status Theorem for HL402406+4.p
27470.44/4629.17	% SZS status Ended for HL402406+4.p
27495.30/4632.28	% SZS status Started for HL402404+5.p
27495.30/4632.28	% SZS status GaveUp for HL402404+5.p
27495.30/4632.28	% SZS status Ended for HL402404+5.p
27501.82/4633.15	% SZS status Started for HL402410+4.p
27501.82/4633.15	% SZS status Theorem for HL402410+4.p
27501.82/4633.15	% SZS status Ended for HL402410+4.p
27505.52/4633.60	% SZS status Started for HL402405+4.p
27505.52/4633.60	% SZS status GaveUp for HL402405+4.p
27505.52/4633.60	% SZS status Ended for HL402405+4.p
27508.20/4633.89	% SZS status Started for HL402405+5.p
27508.20/4633.89	% SZS status GaveUp for HL402405+5.p
27508.20/4633.89	% SZS status Ended for HL402405+5.p
27512.92/4634.57	% SZS status Started for HL402406+5.p
27512.92/4634.57	% SZS status GaveUp for HL402406+5.p
27512.92/4634.57	% SZS status Ended for HL402406+5.p
27519.92/4635.55	% SZS status Started for HL402407+4.p
27519.92/4635.55	% SZS status GaveUp for HL402407+4.p
27519.92/4635.55	% SZS status Ended for HL402407+4.p
27528.78/4636.66	% SZS status Started for HL402407+5.p
27528.78/4636.66	% SZS status GaveUp for HL402407+5.p
27528.78/4636.66	% SZS status Ended for HL402407+5.p
27535.98/4637.47	% SZS status Started for HL402408+4.p
27535.98/4637.47	% SZS status GaveUp for HL402408+4.p
27535.98/4637.47	% SZS status Ended for HL402408+4.p
27535.98/4637.50	% SZS status Started for HL402408+5.p
27535.98/4637.50	% SZS status GaveUp for HL402408+5.p
27535.98/4637.50	% SZS status Ended for HL402408+5.p
27567.92/4641.39	% SZS status Started for HL402410+5.p
27567.92/4641.39	% SZS status GaveUp for HL402410+5.p
27567.92/4641.39	% SZS status Ended for HL402410+5.p
27574.32/4642.19	% SZS status Started for HL402413+5.p
27574.32/4642.19	% SZS status GaveUp for HL402413+5.p
27574.32/4642.19	% SZS status Ended for HL402413+5.p
27575.55/4642.45	% SZS status Started for HL402413+4.p
27575.55/4642.45	% SZS status GaveUp for HL402413+4.p
27575.55/4642.45	% SZS status Ended for HL402413+4.p
27583.80/4643.43	% SZS status Started for HL402414+4.p
27583.80/4643.43	% SZS status GaveUp for HL402414+4.p
27583.80/4643.43	% SZS status Ended for HL402414+4.p
27586.63/4643.80	% SZS status Started for HL402414+5.p
27586.63/4643.80	% SZS status GaveUp for HL402414+5.p
27586.63/4643.80	% SZS status Ended for HL402414+5.p
27600.36/4645.49	% SZS status Started for HL402416+4.p
27600.36/4645.49	% SZS status GaveUp for HL402416+4.p
27600.36/4645.49	% SZS status Ended for HL402416+4.p
27601.80/4645.78	% SZS status Started for HL402416+5.p
27601.80/4645.78	% SZS status GaveUp for HL402416+5.p
27601.80/4645.78	% SZS status Ended for HL402416+5.p
27606.00/4646.29	% SZS status Started for HL402418+4.p
27606.00/4646.29	% SZS status GaveUp for HL402418+4.p
27606.00/4646.29	% SZS status Ended for HL402418+4.p
27634.09/4649.71	% SZS status Started for HL402418+5.p
27634.09/4649.71	% SZS status GaveUp for HL402418+5.p
27634.09/4649.71	% SZS status Ended for HL402418+5.p
27641.88/4650.73	% SZS status Started for HL402419+5.p
27641.88/4650.73	% SZS status GaveUp for HL402419+5.p
27641.88/4650.73	% SZS status Ended for HL402419+5.p
27642.54/4650.77	% SZS status Started for HL402419+4.p
27642.54/4650.77	% SZS status GaveUp for HL402419+4.p
27642.54/4650.77	% SZS status Ended for HL402419+4.p
27651.51/4651.97	% SZS status Started for HL402420+4.p
27651.51/4651.97	% SZS status GaveUp for HL402420+4.p
27651.51/4651.97	% SZS status Ended for HL402420+4.p
27652.53/4652.08	% SZS status Started for HL402420+5.p
27652.53/4652.08	% SZS status GaveUp for HL402420+5.p
27652.53/4652.08	% SZS status Ended for HL402420+5.p
27667.73/4653.96	% SZS status Started for HL402421+4.p
27667.73/4653.96	% SZS status GaveUp for HL402421+4.p
27667.73/4653.96	% SZS status Ended for HL402421+4.p
27668.27/4654.03	% SZS status Started for HL402421+5.p
27668.27/4654.03	% SZS status GaveUp for HL402421+5.p
27668.27/4654.03	% SZS status Ended for HL402421+5.p
27675.28/4654.88	% SZS status Started for HL402422+4.p
27675.28/4654.88	% SZS status GaveUp for HL402422+4.p
27675.28/4654.88	% SZS status Ended for HL402422+4.p
27700.00/4657.99	% SZS status Started for HL402422+5.p
27700.00/4657.99	% SZS status GaveUp for HL402422+5.p
27700.00/4657.99	% SZS status Ended for HL402422+5.p
27708.24/4659.08	% SZS status Started for HL402423+5.p
27708.24/4659.08	% SZS status GaveUp for HL402423+5.p
27708.24/4659.08	% SZS status Ended for HL402423+5.p
27709.61/4659.19	% SZS status Started for HL402423+4.p
27709.61/4659.19	% SZS status GaveUp for HL402423+4.p
27709.61/4659.19	% SZS status Ended for HL402423+4.p
27718.29/4660.36	% SZS status Started for HL402424+5.p
27718.29/4660.36	% SZS status GaveUp for HL402424+5.p
27718.29/4660.36	% SZS status Ended for HL402424+5.p
27719.33/4660.41	% SZS status Started for HL402424+4.p
27719.33/4660.41	% SZS status GaveUp for HL402424+4.p
27719.33/4660.41	% SZS status Ended for HL402424+4.p
27734.24/4662.29	% SZS status Started for HL402425+5.p
27734.24/4662.29	% SZS status GaveUp for HL402425+5.p
27734.24/4662.29	% SZS status Ended for HL402425+5.p
27735.68/4662.53	% SZS status Started for HL402425+4.p
27735.68/4662.53	% SZS status GaveUp for HL402425+4.p
27735.68/4662.53	% SZS status Ended for HL402425+4.p
27743.91/4663.52	% SZS status Started for HL402426+4.p
27743.91/4663.52	% SZS status GaveUp for HL402426+4.p
27743.91/4663.52	% SZS status Ended for HL402426+4.p
27764.96/4666.26	% SZS status Started for HL402426+5.p
27764.96/4666.26	% SZS status GaveUp for HL402426+5.p
27764.96/4666.26	% SZS status Ended for HL402426+5.p
27774.89/4667.47	% SZS status Started for HL402428+5.p
27774.89/4667.47	% SZS status GaveUp for HL402428+5.p
27774.89/4667.47	% SZS status Ended for HL402428+5.p
27776.33/4667.63	% SZS status Started for HL402428+4.p
27776.33/4667.63	% SZS status GaveUp for HL402428+4.p
27776.33/4667.63	% SZS status Ended for HL402428+4.p
27784.91/4668.70	% SZS status Started for HL402429+5.p
27784.91/4668.70	% SZS status GaveUp for HL402429+5.p
27784.91/4668.70	% SZS status Ended for HL402429+5.p
27785.31/4668.80	% SZS status Started for HL402429+4.p
27785.31/4668.80	% SZS status GaveUp for HL402429+4.p
27785.31/4668.80	% SZS status Ended for HL402429+4.p
27800.99/4670.72	% SZS status Started for HL402430+4.p
27800.99/4670.72	% SZS status GaveUp for HL402430+4.p
27800.99/4670.72	% SZS status Ended for HL402430+4.p
27801.63/4670.79	% SZS status Started for HL402430+5.p
27801.63/4670.79	% SZS status GaveUp for HL402430+5.p
27801.63/4670.79	% SZS status Ended for HL402430+5.p
27811.28/4672.01	% SZS status Started for HL402431+4.p
27811.28/4672.01	% SZS status GaveUp for HL402431+4.p
27811.28/4672.01	% SZS status Ended for HL402431+4.p
27817.19/4672.76	% SZS status Started for HL402436+4.p
27817.19/4672.76	% SZS status GaveUp for HL402436+4.p
27817.19/4672.76	% SZS status Ended for HL402436+4.p
27831.63/4674.51	% SZS status Started for HL402431+5.p
27831.63/4674.51	% SZS status GaveUp for HL402431+5.p
27831.63/4674.51	% SZS status Ended for HL402431+5.p
27841.75/4675.87	% SZS status Started for HL402432+5.p
27841.75/4675.87	% SZS status GaveUp for HL402432+5.p
27841.75/4675.87	% SZS status Ended for HL402432+5.p
27842.82/4675.94	% SZS status Started for HL402432+4.p
27842.82/4675.94	% SZS status GaveUp for HL402432+4.p
27842.82/4675.94	% SZS status Ended for HL402432+4.p
27851.83/4677.11	% SZS status Started for HL402433+5.p
27851.83/4677.11	% SZS status GaveUp for HL402433+5.p
27851.83/4677.11	% SZS status Ended for HL402433+5.p
27852.23/4677.27	% SZS status Started for HL402433+4.p
27852.23/4677.27	% SZS status GaveUp for HL402433+4.p
27852.23/4677.27	% SZS status Ended for HL402433+4.p
27868.35/4679.12	% SZS status Started for HL402435+5.p
27868.35/4679.12	% SZS status GaveUp for HL402435+5.p
27868.35/4679.12	% SZS status Ended for HL402435+5.p
27868.35/4679.22	% SZS status Started for HL402435+4.p
27868.35/4679.22	% SZS status GaveUp for HL402435+4.p
27868.35/4679.22	% SZS status Ended for HL402435+4.p
27883.13/4681.01	% SZS status Started for HL402436+5.p
27883.13/4681.01	% SZS status GaveUp for HL402436+5.p
27883.13/4681.01	% SZS status Ended for HL402436+5.p
27898.01/4682.96	% SZS status Started for HL402437+4.p
27898.01/4682.96	% SZS status GaveUp for HL402437+4.p
27898.01/4682.96	% SZS status Ended for HL402437+4.p
27907.53/4684.14	% SZS status Started for HL402437+5.p
27907.53/4684.14	% SZS status GaveUp for HL402437+5.p
27907.53/4684.14	% SZS status Ended for HL402437+5.p
27910.00/4684.47	% SZS status Started for HL402439+4.p
27910.00/4684.47	% SZS status GaveUp for HL402439+4.p
27910.00/4684.47	% SZS status Ended for HL402439+4.p
27918.11/4685.45	% SZS status Started for HL402439+5.p
27918.11/4685.45	% SZS status GaveUp for HL402439+5.p
27918.11/4685.45	% SZS status Ended for HL402439+5.p
27921.11/4685.85	% SZS status Started for HL402440+4.p
27921.11/4685.85	% SZS status GaveUp for HL402440+4.p
27921.11/4685.85	% SZS status Ended for HL402440+4.p
27933.56/4687.39	% SZS status Started for HL402440+5.p
27933.56/4687.39	% SZS status GaveUp for HL402440+5.p
27933.56/4687.39	% SZS status Ended for HL402440+5.p
27934.99/4687.69	% SZS status Started for HL402441+4.p
27934.99/4687.69	% SZS status GaveUp for HL402441+4.p
27934.99/4687.69	% SZS status Ended for HL402441+4.p
27949.42/4689.43	% SZS status Started for HL402441+5.p
27949.42/4689.43	% SZS status GaveUp for HL402441+5.p
27949.42/4689.43	% SZS status Ended for HL402441+5.p
27965.35/4691.41	% SZS status Started for HL402442+4.p
27965.35/4691.41	% SZS status GaveUp for HL402442+4.p
27965.35/4691.41	% SZS status Ended for HL402442+4.p
27974.53/4692.53	% SZS status Started for HL402442+5.p
27974.53/4692.53	% SZS status GaveUp for HL402442+5.p
27974.53/4692.53	% SZS status Ended for HL402442+5.p
27978.04/4693.02	% SZS status Started for HL402443+4.p
27978.04/4693.02	% SZS status GaveUp for HL402443+4.p
27978.04/4693.02	% SZS status Ended for HL402443+4.p
27984.01/4693.70	% SZS status Started for HL402443+5.p
27984.01/4693.70	% SZS status GaveUp for HL402443+5.p
27984.01/4693.70	% SZS status Ended for HL402443+5.p
27989.76/4694.44	% SZS status Started for HL402444+4.p
27989.76/4694.44	% SZS status GaveUp for HL402444+4.p
27989.76/4694.44	% SZS status Ended for HL402444+4.p
27998.57/4695.65	% SZS status Started for HL402444+5.p
27998.57/4695.65	% SZS status GaveUp for HL402444+5.p
27998.57/4695.65	% SZS status Ended for HL402444+5.p
28002.62/4696.16	% SZS status Started for HL402446+4.p
28002.62/4696.16	% SZS status GaveUp for HL402446+4.p
28002.62/4696.16	% SZS status Ended for HL402446+4.p
28015.38/4697.70	% SZS status Started for HL402446+5.p
28015.38/4697.70	% SZS status GaveUp for HL402446+5.p
28015.38/4697.70	% SZS status Ended for HL402446+5.p
28032.63/4699.91	% SZS status Started for HL402447+4.p
28032.63/4699.91	% SZS status GaveUp for HL402447+4.p
28032.63/4699.91	% SZS status Ended for HL402447+4.p
28041.21/4700.88	% SZS status Started for HL402447+5.p
28041.21/4700.88	% SZS status GaveUp for HL402447+5.p
28041.21/4700.88	% SZS status Ended for HL402447+5.p
28046.18/4701.55	% SZS status Started for HL402448+4.p
28046.18/4701.55	% SZS status GaveUp for HL402448+4.p
28046.18/4701.55	% SZS status Ended for HL402448+4.p
28049.88/4702.02	% SZS status Started for HL402448+5.p
28049.88/4702.02	% SZS status GaveUp for HL402448+5.p
28049.88/4702.02	% SZS status Ended for HL402448+5.p
28050.71/4702.24	% SZS status Started for HL402454+4.p
28050.71/4702.24	% SZS status GaveUp for HL402454+4.p
28050.71/4702.24	% SZS status Ended for HL402454+4.p
28057.13/4702.93	% SZS status Started for HL402449+4.p
28057.13/4702.93	% SZS status GaveUp for HL402449+4.p
28057.13/4702.93	% SZS status Ended for HL402449+4.p
28057.13/4702.93	% SZS status Started for HL402455+4.p
28057.13/4702.93	% SZS status GaveUp for HL402455+4.p
28057.13/4702.93	% SZS status Ended for HL402455+4.p
28065.05/4703.91	% SZS status Started for HL402449+5.p
28065.05/4703.91	% SZS status GaveUp for HL402449+5.p
28065.05/4703.91	% SZS status Ended for HL402449+5.p
28069.97/4704.67	% SZS status Started for HL402451+4.p
28069.97/4704.67	% SZS status GaveUp for HL402451+4.p
28069.97/4704.67	% SZS status Ended for HL402451+4.p
28076.84/4705.38	% SZS status Started for HL402458+4.p
28076.84/4705.38	% SZS status GaveUp for HL402458+4.p
28076.84/4705.38	% SZS status Ended for HL402458+4.p
28081.87/4706.00	% SZS status Started for HL402451+5.p
28081.87/4706.00	% SZS status GaveUp for HL402451+5.p
28081.87/4706.00	% SZS status Ended for HL402451+5.p
28100.37/4708.37	% SZS status Started for HL402452+4.p
28100.37/4708.37	% SZS status GaveUp for HL402452+4.p
28100.37/4708.37	% SZS status Ended for HL402452+4.p
28107.48/4709.26	% SZS status Started for HL402452+5.p
28107.48/4709.26	% SZS status GaveUp for HL402452+5.p
28107.48/4709.26	% SZS status Ended for HL402452+5.p
28115.47/4710.29	% SZS status Started for HL402454+5.p
28115.47/4710.29	% SZS status GaveUp for HL402454+5.p
28115.47/4710.29	% SZS status Ended for HL402454+5.p
28122.76/4711.19	% SZS status Started for HL402455+5.p
28122.76/4711.19	% SZS status GaveUp for HL402455+5.p
28122.76/4711.19	% SZS status Ended for HL402455+5.p
28123.97/4711.36	% SZS status Started for HL402457+4.p
28123.97/4711.36	% SZS status GaveUp for HL402457+4.p
28123.97/4711.36	% SZS status Ended for HL402457+4.p
28126.52/4711.78	% SZS status Started for HL402462+5.p
28126.52/4711.78	% SZS status Theorem for HL402462+5.p
28126.52/4711.78	% SZS status Ended for HL402462+5.p
28130.78/4712.18	% SZS status Started for HL402457+5.p
28130.78/4712.18	% SZS status GaveUp for HL402457+5.p
28130.78/4712.18	% SZS status Ended for HL402457+5.p
28139.42/4713.27	% SZS status Started for HL402462+4.p
28139.42/4713.27	% SZS status Theorem for HL402462+4.p
28139.42/4713.27	% SZS status Ended for HL402462+4.p
28142.58/4713.67	% SZS status Started for HL402458+5.p
28142.58/4713.67	% SZS status GaveUp for HL402458+5.p
28142.58/4713.67	% SZS status Ended for HL402458+5.p
28144.28/4714.08	% SZS status Started for HL402464+5.p
28144.28/4714.08	% SZS status Theorem for HL402464+5.p
28144.28/4714.08	% SZS status Ended for HL402464+5.p
28149.25/4714.54	% SZS status Started for HL402459+4.p
28149.25/4714.54	% SZS status GaveUp for HL402459+4.p
28149.25/4714.54	% SZS status Ended for HL402459+4.p
28158.44/4715.71	% SZS status Started for HL402465+5.p
28158.44/4715.71	% SZS status Theorem for HL402465+5.p
28158.44/4715.71	% SZS status Ended for HL402465+5.p
28161.45/4715.99	% SZS status Started for HL402465+4.p
28161.45/4715.99	% SZS status Theorem for HL402465+4.p
28161.45/4715.99	% SZS status Ended for HL402465+4.p
28163.57/4716.35	% SZS status Started for HL402466+4.p
28163.57/4716.35	% SZS status Theorem for HL402466+4.p
28163.57/4716.35	% SZS status Ended for HL402466+4.p
28166.50/4716.63	% SZS status Started for HL402459+5.p
28166.50/4716.63	% SZS status GaveUp for HL402459+5.p
28166.50/4716.63	% SZS status Ended for HL402459+5.p
28171.78/4717.38	% SZS status Started for HL402467+4.p
28171.78/4717.38	% SZS status Theorem for HL402467+4.p
28171.78/4717.38	% SZS status Ended for HL402467+4.p
28175.46/4717.85	% SZS status Started for HL402460+4.p
28175.46/4717.85	% SZS status GaveUp for HL402460+4.p
28175.46/4717.85	% SZS status Ended for HL402460+4.p
28176.00/4717.92	% SZS status Started for HL402468+4.p
28176.00/4717.92	% SZS status Theorem for HL402468+4.p
28176.00/4717.92	% SZS status Ended for HL402468+4.p
28180.79/4718.55	% SZS status Started for HL402460+5.p
28180.79/4718.55	% SZS status GaveUp for HL402460+5.p
28180.79/4718.55	% SZS status Ended for HL402460+5.p
28194.75/4720.21	% SZS status Started for HL402464+4.p
28194.75/4720.21	% SZS status Theorem for HL402464+4.p
28194.75/4720.21	% SZS status Ended for HL402464+4.p
28194.75/4720.22	% SZS status Started for HL402463+4.p
28194.75/4720.22	% SZS status GaveUp for HL402463+4.p
28194.75/4720.22	% SZS status Ended for HL402463+4.p
28196.77/4720.45	% SZS status Started for HL402463+5.p
28196.77/4720.45	% SZS status GaveUp for HL402463+5.p
28196.77/4720.45	% SZS status Ended for HL402463+5.p
28226.77/4724.31	% SZS status Started for HL402466+5.p
28226.77/4724.31	% SZS status GaveUp for HL402466+5.p
28226.77/4724.31	% SZS status Ended for HL402466+5.p
28230.69/4724.99	% SZS status Started for HL402467+5.p
28230.69/4724.99	% SZS status GaveUp for HL402467+5.p
28230.69/4724.99	% SZS status Ended for HL402467+5.p
28241.04/4726.14	% SZS status Started for HL402468+5.p
28241.04/4726.14	% SZS status GaveUp for HL402468+5.p
28241.04/4726.14	% SZS status Ended for HL402468+5.p
28243.79/4726.36	% SZS status Started for HL402469+4.p
28243.79/4726.36	% SZS status GaveUp for HL402469+4.p
28243.79/4726.36	% SZS status Ended for HL402469+4.p
28247.68/4726.83	% SZS status Started for HL402469+5.p
28247.68/4726.83	% SZS status GaveUp for HL402469+5.p
28247.68/4726.83	% SZS status Ended for HL402469+5.p
28249.27/4727.17	% SZS status Started for HL402470+4.p
28249.27/4727.17	% SZS status Theorem for HL402470+4.p
28249.27/4727.17	% SZS status Ended for HL402470+4.p
28259.42/4728.47	% SZS status Started for HL402470+5.p
28259.42/4728.47	% SZS status GaveUp for HL402470+5.p
28259.42/4728.47	% SZS status Ended for HL402470+5.p
28263.22/4728.88	% SZS status Started for HL402471+4.p
28263.22/4728.88	% SZS status GaveUp for HL402471+4.p
28263.22/4728.88	% SZS status Ended for HL402471+4.p
28294.56/4732.79	% SZS status Started for HL402471+5.p
28294.56/4732.79	% SZS status GaveUp for HL402471+5.p
28294.56/4732.79	% SZS status Ended for HL402471+5.p
28300.09/4733.53	% SZS status Started for HL402472+4.p
28300.09/4733.53	% SZS status GaveUp for HL402472+4.p
28300.09/4733.53	% SZS status Ended for HL402472+4.p
28308.20/4734.42	% SZS status Started for HL402472+5.p
28308.20/4734.42	% SZS status GaveUp for HL402472+5.p
28308.20/4734.42	% SZS status Ended for HL402472+5.p
28311.39/4734.93	% SZS status Started for HL402473+4.p
28311.39/4734.93	% SZS status GaveUp for HL402473+4.p
28311.39/4734.93	% SZS status Ended for HL402473+4.p
28312.24/4735.09	% SZS status Started for HL402473+5.p
28312.24/4735.09	% SZS status GaveUp for HL402473+5.p
28312.24/4735.09	% SZS status Ended for HL402473+5.p
28317.66/4735.71	% SZS status Started for HL402474+4.p
28317.66/4735.71	% SZS status GaveUp for HL402474+4.p
28317.66/4735.71	% SZS status Ended for HL402474+4.p
28326.13/4736.73	% SZS status Started for HL402474+5.p
28326.13/4736.73	% SZS status GaveUp for HL402474+5.p
28326.13/4736.73	% SZS status Ended for HL402474+5.p
28331.00/4737.40	% SZS status Started for HL402475+4.p
28331.00/4737.40	% SZS status GaveUp for HL402475+4.p
28331.00/4737.40	% SZS status Ended for HL402475+4.p
28360.85/4741.16	% SZS status Started for HL402475+5.p
28360.85/4741.16	% SZS status GaveUp for HL402475+5.p
28360.85/4741.16	% SZS status Ended for HL402475+5.p
28367.40/4742.03	% SZS status Started for HL402476+4.p
28367.40/4742.03	% SZS status GaveUp for HL402476+4.p
28367.40/4742.03	% SZS status Ended for HL402476+4.p
28371.20/4742.58	% SZS status Started for HL402481+4.p
28371.20/4742.58	% SZS status Theorem for HL402481+4.p
28371.20/4742.58	% SZS status Ended for HL402481+4.p
28374.09/4742.83	% SZS status Started for HL402476+5.p
28374.09/4742.83	% SZS status GaveUp for HL402476+5.p
28374.09/4742.83	% SZS status Ended for HL402476+5.p
28377.55/4743.28	% SZS status Started for HL402482+4.p
28377.55/4743.28	% SZS status Theorem for HL402482+4.p
28377.55/4743.28	% SZS status Ended for HL402482+4.p
28378.75/4743.54	% SZS status Started for HL402477+4.p
28378.75/4743.54	% SZS status GaveUp for HL402477+4.p
28378.75/4743.54	% SZS status Ended for HL402477+4.p
28379.17/4743.61	% SZS status Started for HL402477+5.p
28379.17/4743.61	% SZS status GaveUp for HL402477+5.p
28379.17/4743.61	% SZS status Ended for HL402477+5.p
28382.67/4743.99	% SZS status Started for HL402483+4.p
28382.67/4743.99	% SZS status Theorem for HL402483+4.p
28382.67/4743.99	% SZS status Ended for HL402483+4.p
28383.99/4744.27	% SZS status Started for HL402478+4.p
28383.99/4744.27	% SZS status GaveUp for HL402478+4.p
28383.99/4744.27	% SZS status Ended for HL402478+4.p
28393.43/4745.25	% SZS status Started for HL402478+5.p
28393.43/4745.25	% SZS status GaveUp for HL402478+5.p
28393.43/4745.25	% SZS status Ended for HL402478+5.p
28397.16/4745.89	% SZS status Started for HL402479+4.p
28397.16/4745.89	% SZS status GaveUp for HL402479+4.p
28397.16/4745.89	% SZS status Ended for HL402479+4.p
28426.91/4749.45	% SZS status Started for HL402479+5.p
28426.91/4749.45	% SZS status GaveUp for HL402479+5.p
28426.91/4749.45	% SZS status Ended for HL402479+5.p
28437.43/4750.88	% SZS status Started for HL402481+5.p
28437.43/4750.88	% SZS status GaveUp for HL402481+5.p
28437.43/4750.88	% SZS status Ended for HL402481+5.p
28443.88/4751.58	% SZS status Started for HL402482+5.p
28443.88/4751.58	% SZS status GaveUp for HL402482+5.p
28443.88/4751.58	% SZS status Ended for HL402482+5.p
28445.34/4751.89	% SZS status Started for HL402483+5.p
28445.34/4751.89	% SZS status GaveUp for HL402483+5.p
28445.34/4751.89	% SZS status Ended for HL402483+5.p
28451.89/4752.60	% SZS status Started for HL402485+5.p
28451.89/4752.60	% SZS status GaveUp for HL402485+5.p
28451.89/4752.60	% SZS status Ended for HL402485+5.p
28463.52/4754.13	% SZS status Started for HL402486+5.p
28463.52/4754.13	% SZS status GaveUp for HL402486+5.p
28463.52/4754.13	% SZS status Ended for HL402486+5.p
28477.88/4755.88	% SZS status Started for HL402485+4.p
28477.88/4755.88	% SZS status GaveUp for HL402485+4.p
28477.88/4755.88	% SZS status Ended for HL402485+4.p
28487.01/4757.07	% SZS status Started for HL402486+4.p
28487.01/4757.07	% SZS status GaveUp for HL402486+4.p
28487.01/4757.07	% SZS status Ended for HL402486+4.p
28495.77/4758.00	% SZS status Started for HL402487+4.p
28495.77/4758.00	% SZS status GaveUp for HL402487+4.p
28495.77/4758.00	% SZS status Ended for HL402487+4.p
28504.82/4759.16	% SZS status Started for HL402487+5.p
28504.82/4759.16	% SZS status GaveUp for HL402487+5.p
28504.82/4759.16	% SZS status Ended for HL402487+5.p
28512.22/4760.07	% SZS status Started for HL402488+4.p
28512.22/4760.07	% SZS status GaveUp for HL402488+4.p
28512.22/4760.07	% SZS status Ended for HL402488+4.p
28512.90/4760.17	% SZS status Started for HL402488+5.p
28512.90/4760.17	% SZS status GaveUp for HL402488+5.p
28512.90/4760.17	% SZS status Ended for HL402488+5.p
28521.08/4761.20	% SZS status Started for HL402489+4.p
28521.08/4761.20	% SZS status GaveUp for HL402489+4.p
28521.08/4761.20	% SZS status Ended for HL402489+4.p
28530.46/4762.38	% SZS status Started for HL402489+5.p
28530.46/4762.38	% SZS status GaveUp for HL402489+5.p
28530.46/4762.38	% SZS status Ended for HL402489+5.p
28546.44/4764.50	% SZS status Started for HL402490+4.p
28546.44/4764.50	% SZS status GaveUp for HL402490+4.p
28546.44/4764.50	% SZS status Ended for HL402490+4.p
28561.04/4765.31	% SZS status Started for HL402490+5.p
28561.04/4765.31	% SZS status GaveUp for HL402490+5.p
28561.04/4765.31	% SZS status Ended for HL402490+5.p
28578.11/4767.42	% SZS status Started for HL402492+5.p
28578.11/4767.42	% SZS status GaveUp for HL402492+5.p
28578.11/4767.42	% SZS status Ended for HL402492+5.p
28584.19/4768.23	% SZS status Started for HL402492+4.p
28584.19/4768.23	% SZS status GaveUp for HL402492+4.p
28584.19/4768.23	% SZS status Ended for HL402492+4.p
28585.18/4768.43	% SZS status Started for HL402493+5.p
28585.18/4768.43	% SZS status GaveUp for HL402493+5.p
28585.18/4768.43	% SZS status Ended for HL402493+5.p
28595.46/4769.62	% SZS status Started for HL402493+4.p
28595.46/4769.62	% SZS status GaveUp for HL402493+4.p
28595.46/4769.62	% SZS status Ended for HL402493+4.p
28596.48/4769.79	% SZS status Started for HL402494+4.p
28596.48/4769.79	% SZS status GaveUp for HL402494+4.p
28596.48/4769.79	% SZS status Ended for HL402494+4.p
28602.61/4770.68	% SZS status Started for HL402494+5.p
28602.61/4770.68	% SZS status GaveUp for HL402494+5.p
28602.61/4770.68	% SZS status Ended for HL402494+5.p
28626.48/4773.57	% SZS status Started for HL402495+5.p
28626.48/4773.57	% SZS status GaveUp for HL402495+5.p
28626.48/4773.57	% SZS status Ended for HL402495+5.p
28641.46/4775.48	% SZS status Started for HL402495+4.p
28641.46/4775.48	% SZS status GaveUp for HL402495+4.p
28641.46/4775.48	% SZS status Ended for HL402495+4.p
28650.02/4776.49	% SZS status Started for HL402496+5.p
28650.02/4776.49	% SZS status GaveUp for HL402496+5.p
28650.02/4776.49	% SZS status Ended for HL402496+5.p
28654.90/4777.08	% SZS status Started for HL402497+4.p
28654.90/4777.08	% SZS status GaveUp for HL402497+4.p
28654.90/4777.08	% SZS status Ended for HL402497+4.p
28661.24/4777.86	% SZS status Started for HL402496+4.p
28661.24/4777.86	% SZS status GaveUp for HL402496+4.p
28661.24/4777.86	% SZS status Ended for HL402496+4.p
28661.24/4777.88	% SZS status Started for HL402497+5.p
28661.24/4777.88	% SZS status GaveUp for HL402497+5.p
28661.24/4777.88	% SZS status Ended for HL402497+5.p
28664.91/4778.42	% SZS status Started for HL402498+4.p
28664.91/4778.42	% SZS status GaveUp for HL402498+4.p
28664.91/4778.42	% SZS status Ended for HL402498+4.p
28671.13/4779.14	% SZS status Started for HL402503+4.p
28671.13/4779.14	% SZS status Theorem for HL402503+4.p
28671.13/4779.14	% SZS status Ended for HL402503+4.p
28671.13/4779.17	% SZS status Started for HL402498+5.p
28671.13/4779.17	% SZS status GaveUp for HL402498+5.p
28671.13/4779.17	% SZS status Ended for HL402498+5.p
28673.48/4779.58	% SZS status Started for HL402503+5.p
28673.48/4779.58	% SZS status Theorem for HL402503+5.p
28673.48/4779.58	% SZS status Ended for HL402503+5.p
28677.68/4779.96	% SZS status Started for HL402504+4.p
28677.68/4779.96	% SZS status Theorem for HL402504+4.p
28677.68/4779.96	% SZS status Ended for HL402504+4.p
28678.25/4780.06	% SZS status Started for HL402504+5.p
28678.25/4780.06	% SZS status Theorem for HL402504+5.p
28678.25/4780.06	% SZS status Ended for HL402504+5.p
28683.76/4780.86	% SZS status Started for HL402505+4.p
28683.76/4780.86	% SZS status Theorem for HL402505+4.p
28683.76/4780.86	% SZS status Ended for HL402505+4.p
28689.26/4781.41	% SZS status Started for HL402499+4.p
28689.26/4781.41	% SZS status Theorem for HL402499+4.p
28689.26/4781.41	% SZS status Ended for HL402499+4.p
28691.58/4781.69	% SZS status Started for HL402506+4.p
28691.58/4781.69	% SZS status Theorem for HL402506+4.p
28691.58/4781.69	% SZS status Ended for HL402506+4.p
28692.86/4781.95	% SZS status Started for HL402506+5.p
28692.86/4781.95	% SZS status Theorem for HL402506+5.p
28692.86/4781.95	% SZS status Ended for HL402506+5.p
28696.92/4782.39	% SZS status Started for HL402508+5.p
28696.92/4782.39	% SZS status Theorem for HL402508+5.p
28696.92/4782.39	% SZS status Ended for HL402508+5.p
28697.28/4782.44	% SZS status Started for HL402508+4.p
28697.28/4782.44	% SZS status Theorem for HL402508+4.p
28697.28/4782.44	% SZS status Ended for HL402508+4.p
28700.93/4782.91	% SZS status Started for HL402510+5.p
28700.93/4782.91	% SZS status Theorem for HL402510+5.p
28700.93/4782.91	% SZS status Ended for HL402510+5.p
28702.82/4783.14	% SZS status Started for HL402510+4.p
28702.82/4783.14	% SZS status Theorem for HL402510+4.p
28702.82/4783.14	% SZS status Ended for HL402510+4.p
28705.87/4783.58	% SZS status Started for HL402512+5.p
28705.87/4783.58	% SZS status Theorem for HL402512+5.p
28705.87/4783.58	% SZS status Ended for HL402512+5.p
28705.87/4783.61	% SZS status Started for HL402512+4.p
28705.87/4783.61	% SZS status Theorem for HL402512+4.p
28705.87/4783.61	% SZS status Ended for HL402512+4.p
28709.57/4783.93	% SZS status Started for HL402499+5.p
28709.57/4783.93	% SZS status GaveUp for HL402499+5.p
28709.57/4783.93	% SZS status Ended for HL402499+5.p
28720.83/4785.45	% SZS status Started for HL402500+4.p
28720.83/4785.45	% SZS status GaveUp for HL402500+4.p
28720.83/4785.45	% SZS status Ended for HL402500+4.p
28720.83/4785.47	% SZS status Started for HL402500+5.p
28720.83/4785.47	% SZS status GaveUp for HL402500+5.p
28720.83/4785.47	% SZS status Ended for HL402500+5.p
28724.16/4785.96	% SZS status Started for HL402515+4.p
28724.16/4785.96	% SZS status Theorem for HL402515+4.p
28724.16/4785.96	% SZS status Ended for HL402515+4.p
28727.86/4786.28	% SZS status Started for HL402502+5.p
28727.86/4786.28	% SZS status GaveUp for HL402502+5.p
28727.86/4786.28	% SZS status Ended for HL402502+5.p
28727.86/4786.28	% SZS status Started for HL402515+5.p
28727.86/4786.28	% SZS status Theorem for HL402515+5.p
28727.86/4786.28	% SZS status Ended for HL402515+5.p
28731.09/4786.69	% SZS status Started for HL402502+4.p
28731.09/4786.69	% SZS status GaveUp for HL402502+4.p
28731.09/4786.69	% SZS status Ended for HL402502+4.p
28745.71/4788.53	% SZS status Started for HL402505+5.p
28745.71/4788.53	% SZS status GaveUp for HL402505+5.p
28745.71/4788.53	% SZS status Ended for HL402505+5.p
28772.19/4791.88	% SZS status Started for HL402513+5.p
28772.19/4791.88	% SZS status GaveUp for HL402513+5.p
28772.19/4791.88	% SZS status Ended for HL402513+5.p
28774.52/4792.11	% SZS status Started for HL402513+4.p
28774.52/4792.11	% SZS status GaveUp for HL402513+4.p
28774.52/4792.11	% SZS status Ended for HL402513+4.p
28776.25/4792.43	% SZS status Started for HL402514+4.p
28776.25/4792.43	% SZS status GaveUp for HL402514+4.p
28776.25/4792.43	% SZS status Ended for HL402514+4.p
28780.81/4792.91	% SZS status Started for HL402520+4.p
28780.81/4792.91	% SZS status Theorem for HL402520+4.p
28780.81/4792.91	% SZS status Ended for HL402520+4.p
28783.53/4793.23	% SZS status Started for HL402520+5.p
28783.53/4793.23	% SZS status Theorem for HL402520+5.p
28783.53/4793.23	% SZS status Ended for HL402520+5.p
28785.51/4793.70	% SZS status Started for HL402514+5.p
28785.51/4793.70	% SZS status GaveUp for HL402514+5.p
28785.51/4793.70	% SZS status Ended for HL402514+5.p
28792.01/4794.29	% SZS status Started for HL402522+4.p
28792.01/4794.29	% SZS status Theorem for HL402522+4.p
28792.01/4794.29	% SZS status Ended for HL402522+4.p
28793.80/4794.63	% SZS status Started for HL402517+5.p
28793.80/4794.63	% SZS status GaveUp for HL402517+5.p
28793.80/4794.63	% SZS status Ended for HL402517+5.p
28797.31/4794.97	% SZS status Started for HL402517+4.p
28797.31/4794.97	% SZS status GaveUp for HL402517+4.p
28797.31/4794.97	% SZS status Ended for HL402517+4.p
28798.63/4795.17	% SZS status Started for HL402518+4.p
28798.63/4795.17	% SZS status GaveUp for HL402518+4.p
28798.63/4795.17	% SZS status Ended for HL402518+4.p
28799.51/4795.34	% SZS status Started for HL402523+5.p
28799.51/4795.34	% SZS status Theorem for HL402523+5.p
28799.51/4795.34	% SZS status Ended for HL402523+5.p
28800.83/4795.44	% SZS status Started for HL402526+4.p
28800.83/4795.44	% SZS status Theorem for HL402526+4.p
28800.83/4795.44	% SZS status Ended for HL402526+4.p
28801.42/4795.46	% SZS status Started for HL402523+4.p
28801.42/4795.46	% SZS status Theorem for HL402523+4.p
28801.42/4795.46	% SZS status Ended for HL402523+4.p
28807.14/4796.24	% SZS status Started for HL402526+5.p
28807.14/4796.24	% SZS status Theorem for HL402526+5.p
28807.14/4796.24	% SZS status Ended for HL402526+5.p
28809.17/4796.47	% SZS status Started for HL402522+5.p
28809.17/4796.47	% SZS status Theorem for HL402522+5.p
28809.17/4796.47	% SZS status Ended for HL402522+5.p
28809.17/4796.50	% SZS status Started for HL402527+4.p
28809.17/4796.50	% SZS status Theorem for HL402527+4.p
28809.17/4796.50	% SZS status Ended for HL402527+4.p
28810.22/4796.62	% SZS status Started for HL402528+4.p
28810.22/4796.62	% SZS status Theorem for HL402528+4.p
28810.22/4796.62	% SZS status Ended for HL402528+4.p
28810.70/4796.81	% SZS status Started for HL402518+5.p
28810.70/4796.81	% SZS status GaveUp for HL402518+5.p
28810.70/4796.81	% SZS status Ended for HL402518+5.p
28816.60/4797.56	% SZS status Started for HL402529+4.p
28816.60/4797.56	% SZS status Theorem for HL402529+4.p
28816.60/4797.56	% SZS status Ended for HL402529+4.p
28819.61/4797.79	% SZS status Started for HL402530+4.p
28819.61/4797.79	% SZS status Theorem for HL402530+4.p
28819.61/4797.79	% SZS status Ended for HL402530+4.p
28821.23/4798.03	% SZS status Started for HL402531+4.p
28821.23/4798.03	% SZS status Theorem for HL402531+4.p
28821.23/4798.03	% SZS status Ended for HL402531+4.p
28825.25/4798.52	% SZS status Started for HL402532+4.p
28825.25/4798.52	% SZS status Theorem for HL402532+4.p
28825.25/4798.52	% SZS status Ended for HL402532+4.p
28829.69/4799.04	% SZS status Started for HL402528+5.p
28829.69/4799.04	% SZS status Theorem for HL402528+5.p
28829.69/4799.04	% SZS status Ended for HL402528+5.p
28838.98/4800.24	% SZS status Started for HL402533+4.p
28838.98/4800.24	% SZS status Theorem for HL402533+4.p
28838.98/4800.24	% SZS status Ended for HL402533+4.p
28839.93/4800.41	% SZS status Started for HL402519+4.p
28839.93/4800.41	% SZS status GaveUp for HL402519+4.p
28839.93/4800.41	% SZS status Ended for HL402519+4.p
28839.93/4800.47	% SZS status Started for HL402519+5.p
28839.93/4800.47	% SZS status GaveUp for HL402519+5.p
28839.93/4800.47	% SZS status Ended for HL402519+5.p
28843.88/4800.91	% SZS status Started for HL402527+5.p
28843.88/4800.91	% SZS status Theorem for HL402527+5.p
28843.88/4800.91	% SZS status Ended for HL402527+5.p
28843.88/4800.92	% SZS status Started for HL402534+4.p
28843.88/4800.92	% SZS status Theorem for HL402534+4.p
28843.88/4800.92	% SZS status Ended for HL402534+4.p
28844.89/4801.18	% SZS status Started for HL402533+5.p
28844.89/4801.18	% SZS status Theorem for HL402533+5.p
28844.89/4801.18	% SZS status Ended for HL402533+5.p
28848.97/4801.50	% SZS status Started for HL402536+4.p
28848.97/4801.50	% SZS status Theorem for HL402536+4.p
28848.97/4801.50	% SZS status Ended for HL402536+4.p
28855.22/4802.35	% SZS status Started for HL402536+5.p
28855.22/4802.35	% SZS status Theorem for HL402536+5.p
28855.22/4802.35	% SZS status Ended for HL402536+5.p
28858.40/4802.67	% SZS status Started for HL402538+5.p
28858.40/4802.67	% SZS status Theorem for HL402538+5.p
28858.40/4802.67	% SZS status Ended for HL402538+5.p
28862.79/4803.26	% SZS status Started for HL402534+5.p
28862.79/4803.26	% SZS status Theorem for HL402534+5.p
28862.79/4803.26	% SZS status Ended for HL402534+5.p
28864.17/4803.50	% SZS status Started for HL402538+4.p
28864.17/4803.50	% SZS status Theorem for HL402538+4.p
28864.17/4803.50	% SZS status Ended for HL402538+4.p
28866.81/4803.75	% SZS status Started for HL402540+4.p
28866.81/4803.75	% SZS status Theorem for HL402540+4.p
28866.81/4803.75	% SZS status Ended for HL402540+4.p
28870.40/4804.17	% SZS status Started for HL402540+5.p
28870.40/4804.17	% SZS status Theorem for HL402540+5.p
28870.40/4804.17	% SZS status Ended for HL402540+5.p
28871.36/4804.34	% SZS status Started for HL402541+4.p
28871.36/4804.34	% SZS status Theorem for HL402541+4.p
28871.36/4804.34	% SZS status Ended for HL402541+4.p
28875.21/4804.77	% SZS status Started for HL402529+5.p
28875.21/4804.77	% SZS status GaveUp for HL402529+5.p
28875.21/4804.77	% SZS status Ended for HL402529+5.p
28875.93/4804.90	% SZS status Started for HL402542+4.p
28875.93/4804.90	% SZS status Theorem for HL402542+4.p
28875.93/4804.90	% SZS status Ended for HL402542+4.p
28876.68/4805.08	% SZS status Started for HL402530+5.p
28876.68/4805.08	% SZS status GaveUp for HL402530+5.p
28876.68/4805.08	% SZS status Ended for HL402530+5.p
28884.80/4806.05	% SZS status Started for HL402531+5.p
28884.80/4806.05	% SZS status GaveUp for HL402531+5.p
28884.80/4806.05	% SZS status Ended for HL402531+5.p
28885.59/4806.31	% SZS status Started for HL402541+5.p
28885.59/4806.31	% SZS status Theorem for HL402541+5.p
28885.59/4806.31	% SZS status Ended for HL402541+5.p
28891.79/4806.84	% SZS status Started for HL402532+5.p
28891.79/4806.84	% SZS status GaveUp for HL402532+5.p
28891.79/4806.84	% SZS status Ended for HL402532+5.p
28892.35/4806.93	% SZS status Started for HL402542+5.p
28892.35/4806.93	% SZS status Theorem for HL402542+5.p
28892.35/4806.93	% SZS status Ended for HL402542+5.p
28894.04/4807.36	% SZS status Started for HL402547+4.p
28894.04/4807.36	% SZS status Theorem for HL402547+4.p
28894.04/4807.36	% SZS status Ended for HL402547+4.p
28894.74/4807.44	% SZS status Started for HL402547+5.p
28894.74/4807.44	% SZS status Theorem for HL402547+5.p
28894.74/4807.44	% SZS status Ended for HL402547+5.p
28901.41/4808.30	% SZS status Started for HL402548+5.p
28901.41/4808.30	% SZS status Theorem for HL402548+5.p
28901.41/4808.30	% SZS status Ended for HL402548+5.p
28915.08/4809.90	% SZS status Started for HL402549+4.p
28915.08/4809.90	% SZS status Theorem for HL402549+4.p
28915.08/4809.90	% SZS status Ended for HL402549+4.p
28917.61/4810.15	% SZS status Started for HL402548+4.p
28917.61/4810.15	% SZS status Theorem for HL402548+4.p
28917.61/4810.15	% SZS status Ended for HL402548+4.p
28923.33/4810.89	% SZS status Started for HL402539+4.p
28923.33/4810.89	% SZS status GaveUp for HL402539+4.p
28923.33/4810.89	% SZS status Ended for HL402539+4.p
28924.12/4811.02	% SZS status Started for HL402539+5.p
28924.12/4811.02	% SZS status GaveUp for HL402539+5.p
28924.12/4811.02	% SZS status Ended for HL402539+5.p
28943.40/4813.38	% SZS status Started for HL402545+4.p
28943.40/4813.38	% SZS status GaveUp for HL402545+4.p
28943.40/4813.38	% SZS status Ended for HL402545+4.p
28943.40/4813.40	% SZS status Started for HL402545+5.p
28943.40/4813.40	% SZS status GaveUp for HL402545+5.p
28943.40/4813.40	% SZS status Ended for HL402545+5.p
28952.60/4814.58	% SZS status Started for HL402546+4.p
28952.60/4814.58	% SZS status GaveUp for HL402546+4.p
28952.60/4814.58	% SZS status Ended for HL402546+4.p
28953.13/4814.61	% SZS status Started for HL402546+5.p
28953.13/4814.61	% SZS status GaveUp for HL402546+5.p
28953.13/4814.61	% SZS status Ended for HL402546+5.p
28981.84/4818.16	% SZS status Started for HL402549+5.p
28981.84/4818.16	% SZS status GaveUp for HL402549+5.p
28981.84/4818.16	% SZS status Ended for HL402549+5.p
28986.15/4818.72	% SZS status Started for HL402550+4.p
28986.15/4818.72	% SZS status GaveUp for HL402550+4.p
28986.15/4818.72	% SZS status Ended for HL402550+4.p
28989.14/4819.21	% SZS status Started for HL402550+5.p
28989.14/4819.21	% SZS status GaveUp for HL402550+5.p
28989.14/4819.21	% SZS status Ended for HL402550+5.p
28993.44/4819.64	% SZS status Started for HL402551+4.p
28993.44/4819.64	% SZS status GaveUp for HL402551+4.p
28993.44/4819.64	% SZS status Ended for HL402551+4.p
29009.71/4821.67	% SZS status Started for HL402551+5.p
29009.71/4821.67	% SZS status GaveUp for HL402551+5.p
29009.71/4821.67	% SZS status Ended for HL402551+5.p
29012.80/4822.04	% SZS status Started for HL402552+4.p
29012.80/4822.04	% SZS status GaveUp for HL402552+4.p
29012.80/4822.04	% SZS status Ended for HL402552+4.p
29021.08/4823.10	% SZS status Started for HL402552+5.p
29021.08/4823.10	% SZS status GaveUp for HL402552+5.p
29021.08/4823.10	% SZS status Ended for HL402552+5.p
29022.00/4823.20	% SZS status Started for HL402553+4.p
29022.00/4823.20	% SZS status GaveUp for HL402553+4.p
29022.00/4823.20	% SZS status Ended for HL402553+4.p
29049.50/4826.69	% SZS status Started for HL402553+5.p
29049.50/4826.69	% SZS status GaveUp for HL402553+5.p
29049.50/4826.69	% SZS status Ended for HL402553+5.p
29054.07/4827.32	% SZS status Started for HL402555+4.p
29054.07/4827.32	% SZS status GaveUp for HL402555+4.p
29054.07/4827.32	% SZS status Ended for HL402555+4.p
29058.08/4827.79	% SZS status Started for HL402555+5.p
29058.08/4827.79	% SZS status GaveUp for HL402555+5.p
29058.08/4827.79	% SZS status Ended for HL402555+5.p
29063.24/4828.47	% SZS status Started for HL402556+4.p
29063.24/4828.47	% SZS status GaveUp for HL402556+4.p
29063.24/4828.47	% SZS status Ended for HL402556+4.p
29078.33/4830.30	% SZS status Started for HL402556+5.p
29078.33/4830.30	% SZS status GaveUp for HL402556+5.p
29078.33/4830.30	% SZS status Ended for HL402556+5.p
29081.35/4830.73	% SZS status Started for HL402557+4.p
29081.35/4830.73	% SZS status GaveUp for HL402557+4.p
29081.35/4830.73	% SZS status Ended for HL402557+4.p
29111.62/4834.51	% SZS status Started for HL402558+4.p
29111.62/4834.51	% SZS status GaveUp for HL402558+4.p
29111.62/4834.51	% SZS status Ended for HL402558+4.p
29133.96/4837.27	% SZS status Started for HL402557+5.p
29133.96/4837.27	% SZS status GaveUp for HL402557+5.p
29133.96/4837.27	% SZS status Ended for HL402557+5.p
29147.42/4838.97	% SZS status Started for HL402560+4.p
29147.42/4838.97	% SZS status GaveUp for HL402560+4.p
29147.42/4838.97	% SZS status Ended for HL402560+4.p
29151.35/4839.55	% SZS status Started for HL402562+4.p
29151.35/4839.55	% SZS status Theorem for HL402562+4.p
29151.35/4839.55	% SZS status Ended for HL402562+4.p
29174.75/4842.42	% SZS status Started for HL402564+4.p
29174.75/4842.42	% SZS status Theorem for HL402564+4.p
29174.75/4842.42	% SZS status Ended for HL402564+4.p
29191.08/4844.44	% SZS status Started for HL402561+4.p
29191.08/4844.44	% SZS status GaveUp for HL402561+4.p
29191.08/4844.44	% SZS status Ended for HL402561+4.p
29192.14/4844.64	% SZS status Started for HL402559+4.p
29192.14/4844.64	% SZS status GaveUp for HL402559+4.p
29192.14/4844.64	% SZS status Ended for HL402559+4.p
29195.69/4845.07	% SZS status Started for HL402562+5.p
29195.69/4845.07	% SZS status Theorem for HL402562+5.p
29195.69/4845.07	% SZS status Ended for HL402562+5.p
29196.11/4845.17	% SZS status Started for HL402565+4.p
29196.11/4845.17	% SZS status Theorem for HL402565+4.p
29196.11/4845.17	% SZS status Ended for HL402565+4.p
29217.73/4847.86	% SZS status Started for HL402566+4.p
29217.73/4847.86	% SZS status Theorem for HL402566+4.p
29217.73/4847.86	% SZS status Ended for HL402566+4.p
29220.65/4848.16	% SZS status Started for HL402564+5.p
29220.65/4848.16	% SZS status Theorem for HL402564+5.p
29220.65/4848.16	% SZS status Ended for HL402564+5.p
29237.88/4850.35	% SZS status Started for HL402565+5.p
29237.88/4850.35	% SZS status Theorem for HL402565+5.p
29237.88/4850.35	% SZS status Ended for HL402565+5.p
29241.43/4850.90	% SZS status Started for HL402566+5.p
29241.43/4850.90	% SZS status Theorem for HL402566+5.p
29241.43/4850.90	% SZS status Ended for HL402566+5.p
29243.45/4851.07	% SZS status Started for HL402560+5.p
29243.45/4851.07	% SZS status GaveUp for HL402560+5.p
29243.45/4851.07	% SZS status Ended for HL402560+5.p
29243.99/4851.16	% SZS status Started for HL402558+5.p
29243.99/4851.16	% SZS status GaveUp for HL402558+5.p
29243.99/4851.16	eprover: CPU time limit exceeded, terminating
29243.99/4851.16	% SZS status Ended for HL402558+5.p
29254.72/4852.48	% SZS status Started for HL402559+5.p
29254.72/4852.48	% SZS status GaveUp for HL402559+5.p
29254.72/4852.48	eprover: CPU time limit exceeded, terminating
29254.72/4852.48	% SZS status Ended for HL402559+5.p
29288.04/4856.70	% SZS status Started for HL402568+4.p
29288.04/4856.70	% SZS status GaveUp for HL402568+4.p
29288.04/4856.70	% SZS status Ended for HL402568+4.p
29288.43/4856.71	% SZS status Started for HL402561+5.p
29288.43/4856.71	% SZS status GaveUp for HL402561+5.p
29288.43/4856.71	eprover: CPU time limit exceeded, terminating
29288.43/4856.71	% SZS status Ended for HL402561+5.p
29306.66/4859.03	% SZS status Started for HL402569+4.p
29306.66/4859.03	% SZS status GaveUp for HL402569+4.p
29306.66/4859.03	% SZS status Ended for HL402569+4.p
29309.01/4859.42	% SZS status Started for HL402569+5.p
29309.01/4859.42	% SZS status GaveUp for HL402569+5.p
29309.01/4859.42	% SZS status Ended for HL402569+5.p
29311.65/4859.69	% SZS status Started for HL402570+5.p
29311.65/4859.69	% SZS status GaveUp for HL402570+5.p
29311.65/4859.69	% SZS status Ended for HL402570+5.p
29312.95/4859.86	% SZS status Started for HL402570+4.p
29312.95/4859.86	% SZS status GaveUp for HL402570+4.p
29312.95/4859.86	% SZS status Ended for HL402570+4.p
29324.33/4861.28	% SZS status Started for HL402571+4.p
29324.33/4861.28	% SZS status GaveUp for HL402571+4.p
29324.33/4861.28	% SZS status Ended for HL402571+4.p
29335.70/4862.79	% SZS status Started for HL402574+4.p
29335.70/4862.79	% SZS status Theorem for HL402574+4.p
29335.70/4862.79	% SZS status Ended for HL402574+4.p
29359.58/4865.69	% SZS status Started for HL402576+4.p
29359.58/4865.69	% SZS status Theorem for HL402576+4.p
29359.58/4865.69	% SZS status Ended for HL402576+4.p
29378.59/4868.09	% SZS status Started for HL402572+4.p
29378.59/4868.09	% SZS status GaveUp for HL402572+4.p
29378.59/4868.09	% SZS status Ended for HL402572+4.p
29388.71/4869.40	% SZS status Started for HL402568+5.p
29388.71/4869.40	% SZS status GaveUp for HL402568+5.p
29388.71/4869.40	% SZS status Ended for HL402568+5.p
29396.19/4870.30	% SZS status Started for HL402573+4.p
29396.19/4870.30	% SZS status GaveUp for HL402573+4.p
29396.19/4870.30	% SZS status Ended for HL402573+4.p
29401.07/4870.94	% SZS status Started for HL402577+4.p
29401.07/4870.94	% SZS status Theorem for HL402577+4.p
29401.07/4870.94	% SZS status Ended for HL402577+4.p
29402.10/4871.11	% SZS status Started for HL402578+4.p
29402.10/4871.11	% SZS status Theorem for HL402578+4.p
29402.10/4871.11	% SZS status Ended for HL402578+4.p
29407.98/4871.85	% SZS status Started for HL402579+4.p
29407.98/4871.85	% SZS status Theorem for HL402579+4.p
29407.98/4871.85	% SZS status Ended for HL402579+4.p
29450.73/4877.23	% SZS status Started for HL402578+5.p
29450.73/4877.23	% SZS status Theorem for HL402578+5.p
29450.73/4877.23	% SZS status Ended for HL402578+5.p
29456.03/4877.90	% SZS status Started for HL402579+5.p
29456.03/4877.90	% SZS status Theorem for HL402579+5.p
29456.03/4877.90	% SZS status Ended for HL402579+5.p
29459.53/4878.33	% SZS status Started for HL402571+5.p
29459.53/4878.33	% SZS status GaveUp for HL402571+5.p
29459.53/4878.33	eprover: CPU time limit exceeded, terminating
29459.53/4878.33	% SZS status Ended for HL402571+5.p
29473.45/4880.01	% SZS status Started for HL402581+4.p
29473.45/4880.01	% SZS status Theorem for HL402581+4.p
29473.45/4880.01	% SZS status Ended for HL402581+4.p
29480.08/4880.88	% SZS status Started for HL402573+5.p
29480.08/4880.88	% SZS status GaveUp for HL402573+5.p
29480.08/4880.88	% SZS status Ended for HL402573+5.p
29484.13/4881.37	% SZS status Started for HL402572+5.p
29484.13/4881.37	% SZS status GaveUp for HL402572+5.p
29484.13/4881.37	% SZS status Ended for HL402572+5.p
29501.88/4883.61	% SZS status Started for HL402574+5.p
29501.88/4883.61	% SZS status GaveUp for HL402574+5.p
29501.88/4883.61	% SZS status Ended for HL402574+5.p
29504.04/4884.08	% SZS status Started for HL402581+5.p
29504.04/4884.08	% SZS status Theorem for HL402581+5.p
29504.04/4884.08	% SZS status Ended for HL402581+5.p
29529.31/4887.12	% SZS status Started for HL402576+5.p
29529.31/4887.12	% SZS status GaveUp for HL402576+5.p
29529.31/4887.12	% SZS status Ended for HL402576+5.p
29529.31/4887.12	% SZS status Started for HL402582+4.p
29529.31/4887.12	% SZS status GaveUp for HL402582+4.p
29529.31/4887.12	% SZS status Ended for HL402582+4.p
29543.99/4889.06	% SZS status Started for HL402582+5.p
29543.99/4889.06	% SZS status GaveUp for HL402582+5.p
29543.99/4889.06	% SZS status Ended for HL402582+5.p
29549.65/4889.69	% SZS status Started for HL402584+4.p
29549.65/4889.69	% SZS status GaveUp for HL402584+4.p
29549.65/4889.69	% SZS status Ended for HL402584+4.p
29553.72/4890.13	% SZS status Started for HL402584+5.p
29553.72/4890.13	% SZS status GaveUp for HL402584+5.p
29553.72/4890.13	% SZS status Ended for HL402584+5.p
29567.24/4891.99	% SZS status Started for HL402577+5.p
29567.24/4891.99	% SZS status GaveUp for HL402577+5.p
29567.24/4891.99	% SZS status Ended for HL402577+5.p
29570.87/4892.31	% SZS status Started for HL402585+4.p
29570.87/4892.31	% SZS status GaveUp for HL402585+4.p
29570.87/4892.31	% SZS status Ended for HL402585+4.p
29574.69/4892.84	% SZS status Started for HL402585+5.p
29574.69/4892.84	% SZS status GaveUp for HL402585+5.p
29574.69/4892.84	% SZS status Ended for HL402585+5.p
29598.41/4895.82	% SZS status Started for HL402586+4.p
29598.41/4895.82	% SZS status GaveUp for HL402586+4.p
29598.41/4895.82	% SZS status Ended for HL402586+4.p
29598.95/4895.91	% SZS status Started for HL402586+5.p
29598.95/4895.91	% SZS status GaveUp for HL402586+5.p
29598.95/4895.91	% SZS status Ended for HL402586+5.p
29613.31/4897.76	% SZS status Started for HL402587+4.p
29613.31/4897.76	% SZS status GaveUp for HL402587+4.p
29613.31/4897.76	% SZS status Ended for HL402587+4.p
29620.54/4898.61	% SZS status Started for HL402587+5.p
29620.54/4898.61	% SZS status GaveUp for HL402587+5.p
29620.54/4898.61	% SZS status Ended for HL402587+5.p
29622.34/4898.81	% SZS status Started for HL402588+4.p
29622.34/4898.81	% SZS status GaveUp for HL402588+4.p
29622.34/4898.81	% SZS status Ended for HL402588+4.p
29639.96/4901.02	% SZS status Started for HL402589+4.p
29639.96/4901.02	% SZS status GaveUp for HL402589+4.p
29639.96/4901.02	% SZS status Ended for HL402589+4.p
29666.50/4904.51	% SZS status Started for HL402590+4.p
29666.50/4904.51	% SZS status GaveUp for HL402590+4.p
29666.50/4904.51	% SZS status Ended for HL402590+4.p
29683.08/4906.45	% SZS status Started for HL402591+4.p
29683.08/4906.45	% SZS status GaveUp for HL402591+4.p
29683.08/4906.45	% SZS status Ended for HL402591+4.p
29691.71/4907.52	% SZS status Started for HL402592+4.p
29691.71/4907.52	% SZS status GaveUp for HL402592+4.p
29691.71/4907.52	% SZS status Ended for HL402592+4.p
29737.07/4913.24	% SZS status Started for HL402593+4.p
29737.07/4913.24	% SZS status GaveUp for HL402593+4.p
29737.07/4913.24	% SZS status Ended for HL402593+4.p
29740.29/4913.64	% SZS status Started for HL402588+5.p
29740.29/4913.64	% SZS status GaveUp for HL402588+5.p
29740.29/4913.64	% SZS status Ended for HL402588+5.p
29742.61/4914.08	% SZS status Started for HL402589+5.p
29742.61/4914.08	% SZS status GaveUp for HL402589+5.p
29742.61/4914.08	% SZS status Ended for HL402589+5.p
29761.32/4916.29	% SZS status Started for HL402594+4.p
29761.32/4916.29	% SZS status GaveUp for HL402594+4.p
29761.32/4916.29	% SZS status Ended for HL402594+4.p
29767.32/4917.04	% SZS status Started for HL402597+4.p
29767.32/4917.04	% SZS status Theorem for HL402597+4.p
29767.32/4917.04	% SZS status Ended for HL402597+4.p
29767.76/4917.16	% SZS status Started for HL402590+5.p
29767.76/4917.16	% SZS status GaveUp for HL402590+5.p
29767.76/4917.16	% SZS status Ended for HL402590+5.p
29776.97/4918.29	% SZS status Started for HL402597+5.p
29776.97/4918.29	% SZS status Theorem for HL402597+5.p
29776.97/4918.29	% SZS status Ended for HL402597+5.p
29793.42/4920.32	% SZS status Started for HL402591+5.p
29793.42/4920.32	% SZS status GaveUp for HL402591+5.p
29793.42/4920.32	% SZS status Ended for HL402591+5.p
29806.72/4922.06	% SZS status Started for HL402592+5.p
29806.72/4922.06	% SZS status GaveUp for HL402592+5.p
29806.72/4922.06	% SZS status Ended for HL402592+5.p
29809.42/4922.31	% SZS status Started for HL402596+4.p
29809.42/4922.31	% SZS status GaveUp for HL402596+4.p
29809.42/4922.31	% SZS status Ended for HL402596+4.p
29810.99/4922.56	% SZS status Started for HL402596+5.p
29810.99/4922.56	% SZS status GaveUp for HL402596+5.p
29810.99/4922.56	% SZS status Ended for HL402596+5.p
29836.90/4925.83	% SZS status Started for HL402598+4.p
29836.90/4925.83	% SZS status GaveUp for HL402598+4.p
29836.90/4925.83	% SZS status Ended for HL402598+4.p
29846.77/4927.08	% SZS status Started for HL402593+5.p
29846.77/4927.08	% SZS status GaveUp for HL402593+5.p
29846.77/4927.08	% SZS status Ended for HL402593+5.p
29862.20/4929.00	% SZS status Started for HL402599+4.p
29862.20/4929.00	% SZS status GaveUp for HL402599+4.p
29862.20/4929.00	% SZS status Ended for HL402599+4.p
29877.53/4931.04	% SZS status Started for HL402600+4.p
29877.53/4931.04	% SZS status GaveUp for HL402600+4.p
29877.53/4931.04	% SZS status Ended for HL402600+4.p
29891.87/4932.85	% SZS status Started for HL402602+4.p
29891.87/4932.85	% SZS status Theorem for HL402602+4.p
29891.87/4932.85	% SZS status Ended for HL402602+4.p
29902.48/4934.02	% SZS status Started for HL402594+5.p
29902.48/4934.02	% SZS status GaveUp for HL402594+5.p
29902.48/4934.02	% SZS status Ended for HL402594+5.p
29906.17/4934.48	% SZS status Started for HL402601+4.p
29906.17/4934.48	% SZS status GaveUp for HL402601+4.p
29906.17/4934.48	% SZS status Ended for HL402601+4.p
29923.15/4936.78	% SZS status Started for HL402602+5.p
29923.15/4936.78	% SZS status Theorem for HL402602+5.p
29923.15/4936.78	% SZS status Ended for HL402602+5.p
29941.63/4938.96	% SZS status Started for HL402598+5.p
29941.63/4938.96	% SZS status GaveUp for HL402598+5.p
29941.63/4938.96	% SZS status Ended for HL402598+5.p
29962.51/4941.60	% SZS status Started for HL402603+4.p
29962.51/4941.60	% SZS status Theorem for HL402603+4.p
29962.51/4941.60	% SZS status Ended for HL402603+4.p
29969.64/4942.51	% SZS status Started for HL402603+5.p
29969.64/4942.51	% SZS status GaveUp for HL402603+5.p
29969.64/4942.51	% SZS status Ended for HL402603+5.p
29972.91/4942.86	% SZS status Started for HL402605+4.p
29972.91/4942.86	% SZS status Theorem for HL402605+4.p
29972.91/4942.86	% SZS status Ended for HL402605+4.p
29973.54/4943.00	% SZS status Started for HL402600+5.p
29973.54/4943.00	% SZS status GaveUp for HL402600+5.p
29973.54/4943.00	% SZS status Ended for HL402600+5.p
29976.00/4943.24	% SZS status Started for HL402604+4.p
29976.00/4943.24	% SZS status GaveUp for HL402604+4.p
29976.00/4943.24	% SZS status Ended for HL402604+4.p
29981.44/4943.97	% SZS status Started for HL402599+5.p
29981.44/4943.97	% SZS status GaveUp for HL402599+5.p
29981.44/4943.97	% SZS status Ended for HL402599+5.p
29993.36/4945.50	% SZS status Started for HL402604+5.p
29993.36/4945.50	% SZS status GaveUp for HL402604+5.p
29993.36/4945.50	% SZS status Ended for HL402604+5.p
30012.06/4947.78	% SZS status Started for HL402601+5.p
30012.06/4947.78	% SZS status GaveUp for HL402601+5.p
30012.06/4947.78	% SZS status Ended for HL402601+5.p
30031.49/4950.32	% SZS status Started for HL402605+5.p
30031.49/4950.32	% SZS status GaveUp for HL402605+5.p
30031.49/4950.32	% SZS status Ended for HL402605+5.p
30039.05/4951.19	% SZS status Started for HL402606+4.p
30039.05/4951.19	% SZS status GaveUp for HL402606+4.p
30039.05/4951.19	% SZS status Ended for HL402606+4.p
30042.65/4951.70	% SZS status Started for HL402606+5.p
30042.65/4951.70	% SZS status GaveUp for HL402606+5.p
30042.65/4951.70	% SZS status Ended for HL402606+5.p
30043.28/4951.75	% SZS status Started for HL402607+4.p
30043.28/4951.75	% SZS status GaveUp for HL402607+4.p
30043.28/4951.75	% SZS status Ended for HL402607+4.p
30044.57/4952.07	% SZS status Started for HL402607+5.p
30044.57/4952.07	% SZS status GaveUp for HL402607+5.p
30044.57/4952.07	% SZS status Ended for HL402607+5.p
30049.93/4952.64	% SZS status Started for HL402608+4.p
30049.93/4952.64	% SZS status GaveUp for HL402608+4.p
30049.93/4952.64	% SZS status Ended for HL402608+4.p
30063.00/4954.21	% SZS status Started for HL402608+5.p
30063.00/4954.21	% SZS status GaveUp for HL402608+5.p
30063.00/4954.21	% SZS status Ended for HL402608+5.p
30081.02/4956.49	% SZS status Started for HL402610+4.p
30081.02/4956.49	% SZS status GaveUp for HL402610+4.p
30081.02/4956.49	% SZS status Ended for HL402610+4.p
30108.59/4960.00	% SZS status Started for HL402611+4.p
30108.59/4960.00	% SZS status GaveUp for HL402611+4.p
30108.59/4960.00	% SZS status Ended for HL402611+4.p
30112.62/4960.47	% SZS status Started for HL402611+5.p
30112.62/4960.47	% SZS status GaveUp for HL402611+5.p
30112.62/4960.47	% SZS status Ended for HL402611+5.p
30113.37/4960.57	% SZS status Started for HL402612+4.p
30113.37/4960.57	% SZS status GaveUp for HL402612+4.p
30113.37/4960.57	% SZS status Ended for HL402612+4.p
30115.50/4960.80	% SZS status Started for HL402612+5.p
30115.50/4960.80	% SZS status GaveUp for HL402612+5.p
30115.50/4960.80	% SZS status Ended for HL402612+5.p
30120.81/4961.54	% SZS status Started for HL402613+4.p
30120.81/4961.54	% SZS status GaveUp for HL402613+4.p
30120.81/4961.54	% SZS status Ended for HL402613+4.p
30124.07/4962.07	% SZS status Started for HL402615+4.p
30124.07/4962.07	% SZS status Theorem for HL402615+4.p
30124.07/4962.07	% SZS status Ended for HL402615+4.p
30132.77/4962.99	% SZS status Started for HL402613+5.p
30132.77/4962.99	% SZS status GaveUp for HL402613+5.p
30132.77/4962.99	% SZS status Ended for HL402613+5.p
30149.89/4965.15	% SZS status Started for HL402614+4.p
30149.89/4965.15	% SZS status GaveUp for HL402614+4.p
30149.89/4965.15	% SZS status Ended for HL402614+4.p
30178.07/4968.77	% SZS status Started for HL402614+5.p
30178.07/4968.77	% SZS status GaveUp for HL402614+5.p
30178.07/4968.77	% SZS status Ended for HL402614+5.p
30180.77/4969.04	% SZS status Started for HL402615+5.p
30180.77/4969.04	% SZS status GaveUp for HL402615+5.p
30180.77/4969.04	% SZS status Ended for HL402615+5.p
30183.47/4969.47	% SZS status Started for HL402616+4.p
30183.47/4969.47	% SZS status GaveUp for HL402616+4.p
30183.47/4969.47	% SZS status Ended for HL402616+4.p
30190.97/4970.35	% SZS status Started for HL402616+5.p
30190.97/4970.35	% SZS status GaveUp for HL402616+5.p
30190.97/4970.35	% SZS status Ended for HL402616+5.p
30194.45/4970.77	% SZS status Started for HL402617+4.p
30194.45/4970.77	% SZS status GaveUp for HL402617+4.p
30194.45/4970.77	% SZS status Ended for HL402617+4.p
30199.45/4971.46	% SZS status Started for HL402617+5.p
30199.45/4971.46	% SZS status GaveUp for HL402617+5.p
30199.45/4971.46	% SZS status Ended for HL402617+5.p
30209.29/4972.66	% SZS status Started for HL402610+5.p
30209.29/4972.66	% SZS status GaveUp for HL402610+5.p
30209.29/4972.66	% SZS status Ended for HL402610+5.p
30219.10/4973.89	% SZS status Started for HL402618+4.p
30219.10/4973.89	% SZS status GaveUp for HL402618+4.p
30219.10/4973.89	% SZS status Ended for HL402618+4.p
30221.44/4974.27	% SZS status Started for HL402619+4.p
30221.44/4974.27	% SZS status Theorem for HL402619+4.p
30221.44/4974.27	% SZS status Ended for HL402619+4.p
30229.95/4975.22	% SZS status Started for HL402622+4.p
30229.95/4975.22	% SZS status Theorem for HL402622+4.p
30229.95/4975.22	% SZS status Ended for HL402622+4.p
30245.96/4977.25	% SZS status Started for HL402618+5.p
30245.96/4977.25	% SZS status GaveUp for HL402618+5.p
30245.96/4977.25	% SZS status Ended for HL402618+5.p
30253.29/4978.18	% SZS status Started for HL402619+5.p
30253.29/4978.18	% SZS status GaveUp for HL402619+5.p
30253.29/4978.18	% SZS status Ended for HL402619+5.p
30258.20/4978.83	% SZS status Started for HL402622+5.p
30258.20/4978.83	% SZS status Theorem for HL402622+5.p
30258.20/4978.83	% SZS status Ended for HL402622+5.p
30258.57/4979.11	% SZS status Started for HL402624+4.p
30258.57/4979.11	% SZS status Theorem for HL402624+4.p
30258.57/4979.11	% SZS status Ended for HL402624+4.p
30262.18/4979.30	% SZS status Started for HL402621+4.p
30262.18/4979.30	% SZS status GaveUp for HL402621+4.p
30262.18/4979.30	% SZS status Ended for HL402621+4.p
30264.06/4979.66	% SZS status Started for HL402621+5.p
30264.06/4979.66	% SZS status GaveUp for HL402621+5.p
30264.06/4979.66	% SZS status Ended for HL402621+5.p
30290.72/4982.91	% SZS status Started for HL402623+4.p
30290.72/4982.91	% SZS status GaveUp for HL402623+4.p
30290.72/4982.91	% SZS status Ended for HL402623+4.p
30290.99/4982.94	% SZS status Started for HL402623+5.p
30290.99/4982.94	% SZS status GaveUp for HL402623+5.p
30290.99/4982.94	% SZS status Ended for HL402623+5.p
30314.36/4985.98	% SZS status Started for HL402624+5.p
30314.36/4985.98	% SZS status GaveUp for HL402624+5.p
30314.36/4985.98	% SZS status Ended for HL402624+5.p
30323.48/4987.10	% SZS status Started for HL402625+4.p
30323.48/4987.10	% SZS status GaveUp for HL402625+4.p
30323.48/4987.10	% SZS status Ended for HL402625+4.p
30329.44/4987.78	% SZS status Started for HL402626+4.p
30329.44/4987.78	% SZS status GaveUp for HL402626+4.p
30329.44/4987.78	% SZS status Ended for HL402626+4.p
30329.84/4987.82	% SZS status Started for HL402625+5.p
30329.84/4987.82	% SZS status GaveUp for HL402625+5.p
30329.84/4987.82	% SZS status Ended for HL402625+5.p
30330.87/4988.02	% SZS status Started for HL402626+5.p
30330.87/4988.02	% SZS status GaveUp for HL402626+5.p
30330.87/4988.02	% SZS status Ended for HL402626+5.p
30334.74/4988.41	% SZS status Started for HL402627+4.p
30334.74/4988.41	% SZS status GaveUp for HL402627+4.p
30334.74/4988.41	% SZS status Ended for HL402627+4.p
30357.29/4991.39	% SZS status Started for HL402627+5.p
30357.29/4991.39	% SZS status GaveUp for HL402627+5.p
30357.29/4991.39	% SZS status Ended for HL402627+5.p
30360.42/4991.66	% SZS status Started for HL402629+4.p
30360.42/4991.66	% SZS status GaveUp for HL402629+4.p
30360.42/4991.66	% SZS status Ended for HL402629+4.p
30382.22/4994.46	% SZS status Started for HL402629+5.p
30382.22/4994.46	% SZS status GaveUp for HL402629+5.p
30382.22/4994.46	% SZS status Ended for HL402629+5.p
30400.73/4996.73	% SZS status Started for HL402631+5.p
30400.73/4996.73	% SZS status GaveUp for HL402631+5.p
30400.73/4996.73	% SZS status Ended for HL402631+5.p
30401.17/4996.80	% SZS status Started for HL402631+4.p
30401.17/4996.80	% SZS status GaveUp for HL402631+4.p
30401.17/4996.80	% SZS status Ended for HL402631+4.p
30403.77/4997.16	% SZS status Started for HL402632+4.p
30403.77/4997.16	% SZS status GaveUp for HL402632+4.p
30403.77/4997.16	% SZS status Ended for HL402632+4.p
30407.41/4997.62	% SZS status Started for HL402630+4.p
30407.41/4997.62	% SZS status GaveUp for HL402630+4.p
30407.41/4997.62	% SZS status Ended for HL402630+4.p
30427.80/5000.17	% SZS status Started for HL402632+5.p
30427.80/5000.17	% SZS status GaveUp for HL402632+5.p
30427.80/5000.17	% SZS status Ended for HL402632+5.p
30429.43/5000.33	% SZS status Started for HL402633+4.p
30429.43/5000.33	% SZS status GaveUp for HL402633+4.p
30429.43/5000.33	% SZS status Ended for HL402633+4.p
30454.17/5003.49	% SZS status Started for HL402633+5.p
30454.17/5003.49	% SZS status GaveUp for HL402633+5.p
30454.17/5003.49	% SZS status Ended for HL402633+5.p
30468.50/5005.26	% SZS status Started for HL402637+4.p
30468.50/5005.26	% SZS status Theorem for HL402637+4.p
30468.50/5005.26	% SZS status Ended for HL402637+4.p
30470.08/5005.51	% SZS status Started for HL402634+5.p
30470.08/5005.51	% SZS status GaveUp for HL402634+5.p
30470.08/5005.51	% SZS status Ended for HL402634+5.p
30470.59/5005.56	% SZS status Started for HL402634+4.p
30470.59/5005.56	% SZS status GaveUp for HL402634+4.p
30470.59/5005.56	% SZS status Ended for HL402634+4.p
30474.47/5006.02	% SZS status Started for HL402635+4.p
30474.47/5006.02	% SZS status GaveUp for HL402635+4.p
30474.47/5006.02	% SZS status Ended for HL402635+4.p
30496.84/5008.91	% SZS status Started for HL402630+5.p
30496.84/5008.91	% SZS status GaveUp for HL402630+5.p
30496.84/5008.91	% SZS status Ended for HL402630+5.p
30497.36/5008.98	% SZS status Started for HL402636+4.p
30497.36/5008.98	% SZS status GaveUp for HL402636+4.p
30497.36/5008.98	% SZS status Ended for HL402636+4.p
30539.34/5014.22	% SZS status Started for HL402638+4.p
30539.34/5014.22	% SZS status GaveUp for HL402638+4.p
30539.34/5014.22	% SZS status Ended for HL402638+4.p
30543.46/5014.76	% SZS status Started for HL402639+4.p
30543.46/5014.76	% SZS status GaveUp for HL402639+4.p
30543.46/5014.76	% SZS status Ended for HL402639+4.p
30566.40/5017.75	% SZS status Started for HL402639+5.p
30566.40/5017.75	% SZS status GaveUp for HL402639+5.p
30566.40/5017.75	% SZS status Ended for HL402639+5.p
30568.31/5017.91	% SZS status Started for HL402640+4.p
30568.31/5017.91	% SZS status GaveUp for HL402640+4.p
30568.31/5017.91	% SZS status Ended for HL402640+4.p
30576.07/5018.90	% SZS status Started for HL402635+5.p
30576.07/5018.90	% SZS status GaveUp for HL402635+5.p
30576.07/5018.90	% SZS status Ended for HL402635+5.p
30596.25/5021.44	% SZS status Started for HL402636+5.p
30596.25/5021.44	% SZS status GaveUp for HL402636+5.p
30596.25/5021.44	% SZS status Ended for HL402636+5.p
30608.98/5022.98	% SZS status Started for HL402640+5.p
30608.98/5022.98	% SZS status GaveUp for HL402640+5.p
30608.98/5022.98	% SZS status Ended for HL402640+5.p
30612.59/5023.49	% SZS status Started for HL402641+4.p
30612.59/5023.49	% SZS status GaveUp for HL402641+4.p
30612.59/5023.49	% SZS status Ended for HL402641+4.p
30636.48/5026.50	% SZS status Started for HL402641+5.p
30636.48/5026.50	% SZS status GaveUp for HL402641+5.p
30636.48/5026.50	% SZS status Ended for HL402641+5.p
30636.48/5026.53	% SZS status Started for HL402637+5.p
30636.48/5026.53	% SZS status GaveUp for HL402637+5.p
30636.48/5026.53	% SZS status Ended for HL402637+5.p
30638.20/5026.67	% SZS status Started for HL402642+4.p
30638.20/5026.67	% SZS status GaveUp for HL402642+4.p
30638.20/5026.67	% SZS status Ended for HL402642+4.p
30644.24/5027.41	% SZS status Started for HL402642+5.p
30644.24/5027.41	% SZS status GaveUp for HL402642+5.p
30644.24/5027.41	% SZS status Ended for HL402642+5.p
30652.39/5028.43	% SZS status Started for HL402638+5.p
30652.39/5028.43	% SZS status GaveUp for HL402638+5.p
30652.39/5028.43	% SZS status Ended for HL402638+5.p
30666.05/5030.19	% SZS status Started for HL402643+4.p
30666.05/5030.19	% SZS status GaveUp for HL402643+4.p
30666.05/5030.19	% SZS status Ended for HL402643+4.p
30675.58/5031.54	% SZS status Started for HL402643+5.p
30675.58/5031.54	% SZS status GaveUp for HL402643+5.p
30675.58/5031.54	% SZS status Ended for HL402643+5.p
30682.31/5032.25	% SZS status Started for HL402645+4.p
30682.31/5032.25	% SZS status GaveUp for HL402645+4.p
30682.31/5032.25	% SZS status Ended for HL402645+4.p
30706.00/5035.19	% SZS status Started for HL402645+5.p
30706.00/5035.19	% SZS status GaveUp for HL402645+5.p
30706.00/5035.19	% SZS status Ended for HL402645+5.p
30706.48/5035.32	% SZS status Started for HL402646+4.p
30706.48/5035.32	% SZS status GaveUp for HL402646+4.p
30706.48/5035.32	% SZS status Ended for HL402646+4.p
30706.81/5035.36	% SZS status Started for HL402646+5.p
30706.81/5035.36	% SZS status GaveUp for HL402646+5.p
30706.81/5035.36	% SZS status Ended for HL402646+5.p
30714.16/5036.19	% SZS status Started for HL402647+4.p
30714.16/5036.19	% SZS status GaveUp for HL402647+4.p
30714.16/5036.19	% SZS status Ended for HL402647+4.p
30721.59/5037.13	% SZS status Started for HL402647+5.p
30721.59/5037.13	% SZS status GaveUp for HL402647+5.p
30721.59/5037.13	% SZS status Ended for HL402647+5.p
30735.58/5038.90	% SZS status Started for HL402648+4.p
30735.58/5038.90	% SZS status GaveUp for HL402648+4.p
30735.58/5038.90	% SZS status Ended for HL402648+4.p
30745.77/5040.39	% SZS status Started for HL402648+5.p
30745.77/5040.39	% SZS status GaveUp for HL402648+5.p
30745.77/5040.39	% SZS status Ended for HL402648+5.p
30752.56/5041.01	% SZS status Started for HL402649+4.p
30752.56/5041.01	% SZS status GaveUp for HL402649+4.p
30752.56/5041.01	% SZS status Ended for HL402649+4.p
30775.99/5044.00	% SZS status Started for HL402649+5.p
30775.99/5044.00	% SZS status GaveUp for HL402649+5.p
30775.99/5044.00	% SZS status Ended for HL402649+5.p
30775.99/5044.03	% SZS status Started for HL402650+4.p
30775.99/5044.03	% SZS status GaveUp for HL402650+4.p
30775.99/5044.03	% SZS status Ended for HL402650+4.p
30776.20/5044.08	% SZS status Started for HL402650+5.p
30776.20/5044.08	% SZS status GaveUp for HL402650+5.p
30776.20/5044.08	% SZS status Ended for HL402650+5.p
30783.81/5044.99	% SZS status Started for HL402651+4.p
30783.81/5044.99	% SZS status GaveUp for HL402651+4.p
30783.81/5044.99	% SZS status Ended for HL402651+4.p
30789.58/5045.82	% SZS status Started for HL402651+5.p
30789.58/5045.82	% SZS status GaveUp for HL402651+5.p
30789.58/5045.82	% SZS status Ended for HL402651+5.p
30804.42/5047.60	% SZS status Started for HL402652+4.p
30804.42/5047.60	% SZS status GaveUp for HL402652+4.p
30804.42/5047.60	% SZS status Ended for HL402652+4.p
30815.61/5049.15	% SZS status Started for HL402652+5.p
30815.61/5049.15	% SZS status GaveUp for HL402652+5.p
30815.61/5049.15	% SZS status Ended for HL402652+5.p
30821.44/5049.79	% SZS status Started for HL402653+4.p
30821.44/5049.79	% SZS status GaveUp for HL402653+4.p
30821.44/5049.79	% SZS status Ended for HL402653+4.p
30827.58/5050.58	% SZS status Started for HL402657+4.p
30827.58/5050.58	% SZS status Theorem for HL402657+4.p
30827.58/5050.58	% SZS status Ended for HL402657+4.p
30845.56/5052.82	% SZS status Started for HL402653+5.p
30845.56/5052.82	% SZS status GaveUp for HL402653+5.p
30845.56/5052.82	% SZS status Ended for HL402653+5.p
30846.22/5053.01	% SZS status Started for HL402654+5.p
30846.22/5053.01	% SZS status GaveUp for HL402654+5.p
30846.22/5053.01	% SZS status Ended for HL402654+5.p
30846.41/5053.04	% SZS status Started for HL402654+4.p
30846.41/5053.04	% SZS status GaveUp for HL402654+4.p
30846.41/5053.04	% SZS status Ended for HL402654+4.p
30853.25/5053.77	% SZS status Started for HL402655+4.p
30853.25/5053.77	% SZS status GaveUp for HL402655+4.p
30853.25/5053.77	% SZS status Ended for HL402655+4.p
30858.77/5054.59	% SZS status Started for HL402655+5.p
30858.77/5054.59	% SZS status GaveUp for HL402655+5.p
30858.77/5054.59	% SZS status Ended for HL402655+5.p
30874.69/5057.27	% SZS status Started for HL402656+4.p
30874.69/5057.27	% SZS status GaveUp for HL402656+4.p
30874.69/5057.27	% SZS status Ended for HL402656+4.p
30887.25/5059.39	% SZS status Started for HL402656+5.p
30887.25/5059.39	% SZS status GaveUp for HL402656+5.p
30887.25/5059.39	% SZS status Ended for HL402656+5.p
30899.55/5060.93	% SZS status Started for HL402657+5.p
30899.55/5060.93	% SZS status GaveUp for HL402657+5.p
30899.55/5060.93	% SZS status Ended for HL402657+5.p
30913.52/5062.69	% SZS status Started for HL402658+5.p
30913.52/5062.69	% SZS status GaveUp for HL402658+5.p
30913.52/5062.69	% SZS status Ended for HL402658+5.p
30914.88/5062.91	% SZS status Started for HL402659+4.p
30914.88/5062.91	% SZS status GaveUp for HL402659+4.p
30914.88/5062.91	% SZS status Ended for HL402659+4.p
30916.43/5063.10	% SZS status Started for HL402658+4.p
30916.43/5063.10	% SZS status GaveUp for HL402658+4.p
30916.43/5063.10	% SZS status Ended for HL402658+4.p
30924.09/5064.11	% SZS status Started for HL402659+5.p
30924.09/5064.11	% SZS status GaveUp for HL402659+5.p
30924.09/5064.11	% SZS status Ended for HL402659+5.p
30927.64/5064.50	% SZS status Started for HL402661+4.p
30927.64/5064.50	% SZS status GaveUp for HL402661+4.p
30927.64/5064.50	% SZS status Ended for HL402661+4.p
30945.02/5066.85	% SZS status Started for HL402661+5.p
30945.02/5066.85	% SZS status GaveUp for HL402661+5.p
30945.02/5066.85	% SZS status Ended for HL402661+5.p
30957.59/5068.25	% SZS status Started for HL402663+4.p
30957.59/5068.25	% SZS status GaveUp for HL402663+4.p
30957.59/5068.25	% SZS status Ended for HL402663+4.p
30968.99/5069.69	% SZS status Started for HL402663+5.p
30968.99/5069.69	% SZS status GaveUp for HL402663+5.p
30968.99/5069.69	% SZS status Ended for HL402663+5.p
30970.67/5069.91	% SZS status Started for HL402666+4.p
30970.67/5069.91	% SZS status Theorem for HL402666+4.p
30970.67/5069.91	% SZS status Ended for HL402666+4.p
30982.86/5071.43	% SZS status Started for HL402664+4.p
30982.86/5071.43	% SZS status GaveUp for HL402664+4.p
30982.86/5071.43	% SZS status Ended for HL402664+4.p
30984.77/5071.69	% SZS status Started for HL402664+5.p
30984.77/5071.69	% SZS status GaveUp for HL402664+5.p
30984.77/5071.69	% SZS status Ended for HL402664+5.p
30985.08/5071.80	% SZS status Started for HL402665+4.p
30985.08/5071.80	% SZS status GaveUp for HL402665+4.p
30985.08/5071.80	% SZS status Ended for HL402665+4.p
30992.45/5072.61	% SZS status Started for HL402665+5.p
30992.45/5072.61	% SZS status GaveUp for HL402665+5.p
30992.45/5072.61	% SZS status Ended for HL402665+5.p
31013.62/5075.31	% SZS status Started for HL402666+5.p
31013.62/5075.31	% SZS status GaveUp for HL402666+5.p
31013.62/5075.31	% SZS status Ended for HL402666+5.p
31017.54/5075.85	% SZS status Started for HL402670+4.p
31017.54/5075.85	% SZS status Theorem for HL402670+4.p
31017.54/5075.85	% SZS status Ended for HL402670+4.p
31027.41/5076.99	% SZS status Started for HL402667+4.p
31027.41/5076.99	% SZS status GaveUp for HL402667+4.p
31027.41/5076.99	% SZS status Ended for HL402667+4.p
31038.57/5078.43	% SZS status Started for HL402667+5.p
31038.57/5078.43	% SZS status GaveUp for HL402667+5.p
31038.57/5078.43	% SZS status Ended for HL402667+5.p
31039.95/5078.58	% SZS status Started for HL402668+4.p
31039.95/5078.58	% SZS status GaveUp for HL402668+4.p
31039.95/5078.58	% SZS status Ended for HL402668+4.p
31042.37/5078.94	% SZS status Started for HL402671+4.p
31042.37/5078.94	% SZS status Theorem for HL402671+4.p
31042.37/5078.94	% SZS status Ended for HL402671+4.p
31053.71/5080.38	% SZS status Started for HL402669+4.p
31053.71/5080.38	% SZS status GaveUp for HL402669+4.p
31053.71/5080.38	% SZS status Ended for HL402669+4.p
31108.70/5087.27	% SZS status Started for HL402672+4.p
31108.70/5087.27	% SZS status GaveUp for HL402672+4.p
31108.70/5087.27	% SZS status Ended for HL402672+4.p
31111.40/5087.63	% SZS status Started for HL402673+4.p
31111.40/5087.63	% SZS status GaveUp for HL402673+4.p
31111.40/5087.63	% SZS status Ended for HL402673+4.p
31147.43/5092.13	% SZS status Started for HL402668+5.p
31147.43/5092.13	% SZS status GaveUp for HL402668+5.p
31147.43/5092.13	% SZS status Ended for HL402668+5.p
31149.20/5092.36	% SZS status Started for HL402669+5.p
31149.20/5092.36	% SZS status GaveUp for HL402669+5.p
31149.20/5092.36	% SZS status Ended for HL402669+5.p
31177.25/5095.90	% SZS status Started for HL402670+5.p
31177.25/5095.90	% SZS status GaveUp for HL402670+5.p
31177.25/5095.90	% SZS status Ended for HL402670+5.p
31178.18/5096.05	% SZS status Started for HL402675+4.p
31178.18/5096.05	% SZS status GaveUp for HL402675+4.p
31178.18/5096.05	% SZS status Ended for HL402675+4.p
31194.64/5098.03	% SZS status Started for HL402671+5.p
31194.64/5098.03	% SZS status GaveUp for HL402671+5.p
31194.64/5098.03	% SZS status Ended for HL402671+5.p
31205.55/5099.42	% SZS status Started for HL402672+5.p
31205.55/5099.42	% SZS status GaveUp for HL402672+5.p
31205.55/5099.42	% SZS status Ended for HL402672+5.p
31217.49/5100.87	% SZS status Started for HL402676+4.p
31217.49/5100.87	% SZS status GaveUp for HL402676+4.p
31217.49/5100.87	% SZS status Ended for HL402676+4.p
31222.92/5101.60	% SZS status Started for HL402673+5.p
31222.92/5101.60	% SZS status GaveUp for HL402673+5.p
31222.92/5101.60	eprover: CPU time limit exceeded, terminating
31222.92/5101.60	% SZS status Ended for HL402673+5.p
31247.10/5104.63	% SZS status Started for HL402677+4.p
31247.10/5104.63	% SZS status GaveUp for HL402677+4.p
31247.10/5104.63	% SZS status Ended for HL402677+4.p
31264.26/5106.77	% SZS status Started for HL402678+4.p
31264.26/5106.77	% SZS status GaveUp for HL402678+4.p
31264.26/5106.77	% SZS status Ended for HL402678+4.p
31288.87/5109.89	% SZS status Started for HL402675+5.p
31288.87/5109.89	% SZS status GaveUp for HL402675+5.p
31288.87/5109.89	% SZS status Ended for HL402675+5.p
31289.62/5110.01	% SZS status Started for HL402679+4.p
31289.62/5110.01	% SZS status GaveUp for HL402679+4.p
31289.62/5110.01	% SZS status Ended for HL402679+4.p
31316.00/5113.34	% SZS status Started for HL402680+4.p
31316.00/5113.34	% SZS status GaveUp for HL402680+4.p
31316.00/5113.34	% SZS status Ended for HL402680+4.p
31319.39/5113.72	% SZS status Started for HL402676+5.p
31319.39/5113.72	% SZS status GaveUp for HL402676+5.p
31319.39/5113.72	% SZS status Ended for HL402676+5.p
31355.20/5118.28	% SZS status Started for HL402677+5.p
31355.20/5118.28	% SZS status GaveUp for HL402677+5.p
31355.20/5118.28	eprover: CPU time limit exceeded, terminating
31355.20/5118.28	% SZS status Ended for HL402677+5.p
31358.12/5118.62	% SZS status Started for HL402681+4.p
31358.12/5118.62	% SZS status GaveUp for HL402681+4.p
31358.12/5118.62	% SZS status Ended for HL402681+4.p
31383.38/5121.77	% SZS status Started for HL402678+5.p
31383.38/5121.77	% SZS status GaveUp for HL402678+5.p
31383.38/5121.77	eprover: CPU time limit exceeded, terminating
31383.38/5121.77	% SZS status Ended for HL402678+5.p
31385.94/5122.08	% SZS status Started for HL402682+4.p
31385.94/5122.08	% SZS status GaveUp for HL402682+4.p
31385.94/5122.08	% SZS status Ended for HL402682+4.p
31403.52/5124.28	% SZS status Started for HL402679+5.p
31403.52/5124.28	% SZS status GaveUp for HL402679+5.p
31403.52/5124.28	eprover: CPU time limit exceeded, terminating
31403.52/5124.28	% SZS status Ended for HL402679+5.p
31427.92/5127.38	% SZS status Started for HL402683+4.p
31427.92/5127.38	% SZS status GaveUp for HL402683+4.p
31427.92/5127.38	% SZS status Ended for HL402683+4.p
31448.13/5129.96	% SZS status Started for HL402680+5.p
31448.13/5129.96	% SZS status GaveUp for HL402680+5.p
31448.13/5129.96	% SZS status Ended for HL402680+5.p
31455.37/5130.85	% SZS status Started for HL402684+4.p
31455.37/5130.85	% SZS status GaveUp for HL402684+4.p
31455.37/5130.85	% SZS status Ended for HL402684+4.p
31472.65/5133.00	% SZS status Started for HL402681+5.p
31472.65/5133.00	% SZS status GaveUp for HL402681+5.p
31472.65/5133.00	% SZS status Ended for HL402681+5.p
31475.59/5133.35	% SZS status Started for HL402685+4.p
31475.59/5133.35	% SZS status GaveUp for HL402685+4.p
31475.59/5133.35	% SZS status Ended for HL402685+4.p
31503.88/5137.06	% SZS status Started for HL402682+5.p
31503.88/5137.06	% SZS status GaveUp for HL402682+5.p
31503.88/5137.06	% SZS status Ended for HL402682+5.p
31517.07/5138.65	% SZS status Started for HL402687+4.p
31517.07/5138.65	% SZS status GaveUp for HL402687+4.p
31517.07/5138.65	% SZS status Ended for HL402687+4.p
31545.88/5141.17	% SZS status Started for HL402683+5.p
31545.88/5141.17	% SZS status GaveUp for HL402683+5.p
31545.88/5141.17	% SZS status Ended for HL402683+5.p
31549.86/5141.74	% SZS status Started for HL402688+4.p
31549.86/5141.74	% SZS status GaveUp for HL402688+4.p
31549.86/5141.74	% SZS status Ended for HL402688+4.p
31571.12/5144.38	% SZS status Started for HL402684+5.p
31571.12/5144.38	% SZS status GaveUp for HL402684+5.p
31571.12/5144.38	% SZS status Ended for HL402684+5.p
31582.58/5145.80	% SZS status Started for HL402689+4.p
31582.58/5145.80	% SZS status GaveUp for HL402689+4.p
31582.58/5145.80	% SZS status Ended for HL402689+4.p
31594.05/5147.28	% SZS status Started for HL402691+4.p
31594.05/5147.28	% SZS status Theorem for HL402691+4.p
31594.05/5147.28	% SZS status Ended for HL402691+4.p
31605.61/5148.68	% SZS status Started for HL402685+5.p
31605.61/5148.68	% SZS status GaveUp for HL402685+5.p
31605.61/5148.68	% SZS status Ended for HL402685+5.p
31615.15/5149.88	% SZS status Started for HL402690+4.p
31615.15/5149.88	% SZS status GaveUp for HL402690+4.p
31615.15/5149.88	% SZS status Ended for HL402690+4.p
31627.45/5151.45	% SZS status Started for HL402687+5.p
31627.45/5151.45	% SZS status GaveUp for HL402687+5.p
31627.45/5151.45	% SZS status Ended for HL402687+5.p
31651.45/5154.57	% SZS status Started for HL402688+5.p
31651.45/5154.57	% SZS status GaveUp for HL402688+5.p
31651.45/5154.57	% SZS status Ended for HL402688+5.p
31664.27/5156.08	% SZS status Started for HL402692+4.p
31664.27/5156.08	% SZS status GaveUp for HL402692+4.p
31664.27/5156.08	% SZS status Ended for HL402692+4.p
31685.16/5158.68	% SZS status Started for HL402693+4.p
31685.16/5158.68	% SZS status GaveUp for HL402693+4.p
31685.16/5158.68	% SZS status Ended for HL402693+4.p
31691.13/5159.50	% SZS status Started for HL402689+5.p
31691.13/5159.50	% SZS status GaveUp for HL402689+5.p
31691.13/5159.50	% SZS status Ended for HL402689+5.p
31716.50/5162.71	% SZS status Started for HL402690+5.p
31716.50/5162.71	% SZS status GaveUp for HL402690+5.p
31716.50/5162.71	% SZS status Ended for HL402690+5.p
31722.05/5163.38	% SZS status Started for HL402694+4.p
31722.05/5163.38	% SZS status GaveUp for HL402694+4.p
31722.05/5163.38	% SZS status Ended for HL402694+4.p
31723.56/5163.54	% SZS status Started for HL402696+4.p
31723.56/5163.54	% SZS status Theorem for HL402696+4.p
31723.56/5163.54	% SZS status Ended for HL402696+4.p
31753.92/5167.37	% SZS status Started for HL402691+5.p
31753.92/5167.37	% SZS status GaveUp for HL402691+5.p
31753.92/5167.37	% SZS status Ended for HL402691+5.p
31754.85/5167.49	% SZS status Started for HL402695+4.p
31754.85/5167.49	% SZS status GaveUp for HL402695+4.p
31754.85/5167.49	% SZS status Ended for HL402695+4.p
31773.08/5169.76	% SZS status Started for HL402692+5.p
31773.08/5169.76	% SZS status GaveUp for HL402692+5.p
31773.08/5169.76	% SZS status Ended for HL402692+5.p
31780.79/5170.78	% SZS status Started for HL402698+4.p
31780.79/5170.78	% SZS status Theorem for HL402698+4.p
31780.79/5170.78	% SZS status Ended for HL402698+4.p
31792.36/5172.19	% SZS status Started for HL402696+5.p
31792.36/5172.19	% SZS status GaveUp for HL402696+5.p
31792.36/5172.19	% SZS status Ended for HL402696+5.p
31794.53/5172.53	% SZS status Started for HL402693+5.p
31794.53/5172.53	% SZS status GaveUp for HL402693+5.p
31794.53/5172.53	% SZS status Ended for HL402693+5.p
31806.05/5173.95	% SZS status Started for HL402697+4.p
31806.05/5173.95	% SZS status GaveUp for HL402697+4.p
31806.05/5173.95	% SZS status Ended for HL402697+4.p
31840.49/5178.28	% SZS status Started for HL402694+5.p
31840.49/5178.28	% SZS status GaveUp for HL402694+5.p
31840.49/5178.28	% SZS status Ended for HL402694+5.p
31863.72/5181.28	% SZS status Started for HL402701+4.p
31863.72/5181.28	% SZS status GaveUp for HL402701+4.p
31863.72/5181.28	% SZS status Ended for HL402701+4.p
31866.60/5181.57	% SZS status Started for HL402700+4.p
31866.60/5181.57	% SZS status GaveUp for HL402700+4.p
31866.60/5181.57	% SZS status Ended for HL402700+4.p
31871.79/5182.22	% SZS status Started for HL402695+5.p
31871.79/5182.22	% SZS status GaveUp for HL402695+5.p
31871.79/5182.22	% SZS status Ended for HL402695+5.p
31872.90/5182.41	% SZS status Started for HL402703+4.p
31872.90/5182.41	% SZS status Theorem for HL402703+4.p
31872.90/5182.41	% SZS status Ended for HL402703+4.p
31909.47/5187.03	% SZS status Started for HL402702+4.p
31909.47/5187.03	% SZS status GaveUp for HL402702+4.p
31909.47/5187.03	% SZS status Ended for HL402702+4.p
31929.28/5189.46	% SZS status Started for HL402697+5.p
31929.28/5189.46	% SZS status GaveUp for HL402697+5.p
31929.28/5189.46	% SZS status Ended for HL402697+5.p
31934.28/5190.11	% SZS status Started for HL402702+5.p
31934.28/5190.11	% SZS status GaveUp for HL402702+5.p
31934.28/5190.11	% SZS status Ended for HL402702+5.p
31941.77/5191.03	% SZS status Started for HL402703+5.p
31941.77/5191.03	% SZS status GaveUp for HL402703+5.p
31941.77/5191.03	% SZS status Ended for HL402703+5.p
31942.58/5191.14	% SZS status Started for HL402704+4.p
31942.58/5191.14	% SZS status GaveUp for HL402704+4.p
31942.58/5191.14	% SZS status Ended for HL402704+4.p
31943.61/5191.35	% SZS status Started for HL402698+5.p
31943.61/5191.35	% SZS status GaveUp for HL402698+5.p
31943.61/5191.35	% SZS status Ended for HL402698+5.p
31962.87/5193.71	% SZS status Started for HL402700+5.p
31962.87/5193.71	% SZS status GaveUp for HL402700+5.p
31962.87/5193.71	% SZS status Ended for HL402700+5.p
31974.12/5195.13	% SZS status Started for HL402701+5.p
31974.12/5195.13	% SZS status GaveUp for HL402701+5.p
31974.12/5195.13	% SZS status Ended for HL402701+5.p
31980.02/5195.91	% SZS status Started for HL402704+5.p
31980.02/5195.91	% SZS status GaveUp for HL402704+5.p
31980.02/5195.91	% SZS status Ended for HL402704+5.p
32001.27/5198.66	% SZS status Started for HL402705+4.p
32001.27/5198.66	% SZS status GaveUp for HL402705+4.p
32001.27/5198.66	% SZS status Ended for HL402705+4.p
32004.26/5198.95	% SZS status Started for HL402705+5.p
32004.26/5198.95	% SZS status GaveUp for HL402705+5.p
32004.26/5198.95	% SZS status Ended for HL402705+5.p
32009.93/5199.71	% SZS status Started for HL402706+4.p
32009.93/5199.71	% SZS status GaveUp for HL402706+4.p
32009.93/5199.71	% SZS status Ended for HL402706+4.p
32019.18/5199.97	% SZS status Started for HL402706+5.p
32019.18/5199.97	% SZS status GaveUp for HL402706+5.p
32019.18/5199.97	% SZS status Ended for HL402706+5.p
32022.96/5200.25	% SZS status Started for HL402707+4.p
32022.96/5200.25	% SZS status GaveUp for HL402707+4.p
32022.96/5200.25	% SZS status Ended for HL402707+4.p
32040.46/5202.47	% SZS status Started for HL402707+5.p
32040.46/5202.47	% SZS status GaveUp for HL402707+5.p
32040.46/5202.47	% SZS status Ended for HL402707+5.p
32051.37/5203.81	% SZS status Started for HL402708+4.p
32051.37/5203.81	% SZS status GaveUp for HL402708+4.p
32051.37/5203.81	% SZS status Ended for HL402708+4.p
32057.71/5204.68	% SZS status Started for HL402708+5.p
32057.71/5204.68	% SZS status GaveUp for HL402708+5.p
32057.71/5204.68	% SZS status Ended for HL402708+5.p
32080.61/5207.44	% SZS status Started for HL402709+4.p
32080.61/5207.44	% SZS status GaveUp for HL402709+4.p
32080.61/5207.44	% SZS status Ended for HL402709+4.p
32082.02/5207.70	% SZS status Started for HL402709+5.p
32082.02/5207.70	% SZS status GaveUp for HL402709+5.p
32082.02/5207.70	% SZS status Ended for HL402709+5.p
32086.81/5208.43	% SZS status Started for HL402710+4.p
32086.81/5208.43	% SZS status GaveUp for HL402710+4.p
32086.81/5208.43	% SZS status Ended for HL402710+4.p
32092.90/5209.04	% SZS status Started for HL402711+4.p
32092.90/5209.04	% SZS status GaveUp for HL402711+4.p
32092.90/5209.04	% SZS status Ended for HL402711+4.p
32092.90/5209.05	% SZS status Started for HL402710+5.p
32092.90/5209.05	% SZS status GaveUp for HL402710+5.p
32092.90/5209.05	% SZS status Ended for HL402710+5.p
32111.77/5211.36	% SZS status Started for HL402711+5.p
32111.77/5211.36	% SZS status GaveUp for HL402711+5.p
32111.77/5211.36	% SZS status Ended for HL402711+5.p
32121.65/5212.67	% SZS status Started for HL402712+4.p
32121.65/5212.67	% SZS status GaveUp for HL402712+4.p
32121.65/5212.67	% SZS status Ended for HL402712+4.p
32127.48/5213.48	% SZS status Started for HL402712+5.p
32127.48/5213.48	% SZS status GaveUp for HL402712+5.p
32127.48/5213.48	% SZS status Ended for HL402712+5.p
32136.22/5214.53	% SZS status Started for HL402717+4.p
32136.22/5214.53	% SZS status Theorem for HL402717+4.p
32136.22/5214.53	% SZS status Ended for HL402717+4.p
32150.27/5216.31	% SZS status Started for HL402714+4.p
32150.27/5216.31	% SZS status GaveUp for HL402714+4.p
32150.27/5216.31	% SZS status Ended for HL402714+4.p
32151.41/5216.48	% SZS status Started for HL402714+5.p
32151.41/5216.48	% SZS status GaveUp for HL402714+5.p
32151.41/5216.48	% SZS status Ended for HL402714+5.p
32158.19/5217.24	% SZS status Started for HL402715+4.p
32158.19/5217.24	% SZS status GaveUp for HL402715+4.p
32158.19/5217.24	% SZS status Ended for HL402715+4.p
32162.55/5217.79	% SZS status Started for HL402715+5.p
32162.55/5217.79	% SZS status GaveUp for HL402715+5.p
32162.55/5217.79	% SZS status Ended for HL402715+5.p
32162.55/5217.79	% SZS status Started for HL402716+4.p
32162.55/5217.79	% SZS status GaveUp for HL402716+4.p
32162.55/5217.79	% SZS status Ended for HL402716+4.p
32177.07/5219.67	% SZS status Started for HL402717+5.p
32177.07/5219.67	% SZS status Theorem for HL402717+5.p
32177.07/5219.67	% SZS status Ended for HL402717+5.p
32181.48/5220.25	% SZS status Started for HL402716+5.p
32181.48/5220.25	% SZS status GaveUp for HL402716+5.p
32181.48/5220.25	% SZS status Ended for HL402716+5.p
32206.68/5223.39	% SZS status Started for HL402719+4.p
32206.68/5223.39	% SZS status GaveUp for HL402719+4.p
32206.68/5223.39	% SZS status Ended for HL402719+4.p
32220.55/5225.12	% SZS status Started for HL402719+5.p
32220.55/5225.12	% SZS status GaveUp for HL402719+5.p
32220.55/5225.12	% SZS status Ended for HL402719+5.p
32222.00/5225.32	% SZS status Started for HL402720+4.p
32222.00/5225.32	% SZS status GaveUp for HL402720+4.p
32222.00/5225.32	% SZS status Ended for HL402720+4.p
32226.39/5225.93	% SZS status Started for HL402720+5.p
32226.39/5225.93	% SZS status GaveUp for HL402720+5.p
32226.39/5225.93	% SZS status Ended for HL402720+5.p
32232.18/5226.60	% SZS status Started for HL402721+5.p
32232.18/5226.60	% SZS status GaveUp for HL402721+5.p
32232.18/5226.60	% SZS status Ended for HL402721+5.p
32232.95/5226.68	% SZS status Started for HL402721+4.p
32232.95/5226.68	% SZS status GaveUp for HL402721+4.p
32232.95/5226.68	% SZS status Ended for HL402721+4.p
32247.39/5228.46	% SZS status Started for HL402722+4.p
32247.39/5228.46	% SZS status GaveUp for HL402722+4.p
32247.39/5228.46	% SZS status Ended for HL402722+4.p
32252.33/5229.13	% SZS status Started for HL402722+5.p
32252.33/5229.13	% SZS status GaveUp for HL402722+5.p
32252.33/5229.13	% SZS status Ended for HL402722+5.p
32275.71/5232.12	% SZS status Started for HL402723+4.p
32275.71/5232.12	% SZS status GaveUp for HL402723+4.p
32275.71/5232.12	% SZS status Ended for HL402723+4.p
32290.40/5233.87	% SZS status Started for HL402723+5.p
32290.40/5233.87	% SZS status GaveUp for HL402723+5.p
32290.40/5233.87	% SZS status Ended for HL402723+5.p
32290.40/5233.93	% SZS status Started for HL402728+4.p
32290.40/5233.93	% SZS status Theorem for HL402728+4.p
32290.40/5233.93	% SZS status Ended for HL402728+4.p
32291.49/5234.04	% SZS status Started for HL402724+4.p
32291.49/5234.04	% SZS status GaveUp for HL402724+4.p
32291.49/5234.04	% SZS status Ended for HL402724+4.p
32296.23/5234.66	% SZS status Started for HL402724+5.p
32296.23/5234.66	% SZS status GaveUp for HL402724+5.p
32296.23/5234.66	% SZS status Ended for HL402724+5.p
32297.00/5234.86	% SZS status Started for HL402730+4.p
32297.00/5234.86	% SZS status Theorem for HL402730+4.p
32297.00/5234.86	% SZS status Ended for HL402730+4.p
32301.15/5235.33	% SZS status Started for HL402725+4.p
32301.15/5235.33	% SZS status GaveUp for HL402725+4.p
32301.15/5235.33	% SZS status Ended for HL402725+4.p
32303.03/5235.48	% SZS status Started for HL402725+5.p
32303.03/5235.48	% SZS status GaveUp for HL402725+5.p
32303.03/5235.48	% SZS status Ended for HL402725+5.p
32316.57/5237.17	% SZS status Started for HL402726+4.p
32316.57/5237.17	% SZS status GaveUp for HL402726+4.p
32316.57/5237.17	% SZS status Ended for HL402726+4.p
32323.26/5238.06	% SZS status Started for HL402726+5.p
32323.26/5238.06	% SZS status GaveUp for HL402726+5.p
32323.26/5238.06	% SZS status Ended for HL402726+5.p
32338.01/5239.92	% SZS status Started for HL402728+5.p
32338.01/5239.92	% SZS status Theorem for HL402728+5.p
32338.01/5239.92	% SZS status Ended for HL402728+5.p
32361.34/5242.84	% SZS status Started for HL402730+5.p
32361.34/5242.84	% SZS status GaveUp for HL402730+5.p
32361.34/5242.84	% SZS status Ended for HL402730+5.p
32366.00/5243.48	% SZS status Started for HL402731+4.p
32366.00/5243.48	% SZS status GaveUp for HL402731+4.p
32366.00/5243.48	% SZS status Ended for HL402731+4.p
32367.02/5243.71	% SZS status Started for HL402731+5.p
32367.02/5243.71	% SZS status GaveUp for HL402731+5.p
32367.02/5243.71	% SZS status Ended for HL402731+5.p
32371.04/5244.17	% SZS status Started for HL402732+4.p
32371.04/5244.17	% SZS status GaveUp for HL402732+4.p
32371.04/5244.17	% SZS status Ended for HL402732+4.p
32372.84/5244.26	% SZS status Started for HL402732+5.p
32372.84/5244.26	% SZS status GaveUp for HL402732+5.p
32372.84/5244.26	% SZS status Ended for HL402732+5.p
32386.11/5245.96	% SZS status Started for HL402733+4.p
32386.11/5245.96	% SZS status GaveUp for HL402733+4.p
32386.11/5245.96	% SZS status Ended for HL402733+4.p
32392.43/5246.75	% SZS status Started for HL402737+4.p
32392.43/5246.75	% SZS status Theorem for HL402737+4.p
32392.43/5246.75	% SZS status Ended for HL402737+4.p
32394.69/5247.03	% SZS status Started for HL402733+5.p
32394.69/5247.03	% SZS status GaveUp for HL402733+5.p
32394.69/5247.03	% SZS status Ended for HL402733+5.p
32406.23/5248.66	% SZS status Started for HL402734+4.p
32406.23/5248.66	% SZS status GaveUp for HL402734+4.p
32406.23/5248.66	% SZS status Ended for HL402734+4.p
32430.75/5251.62	% SZS status Started for HL402734+5.p
32430.75/5251.62	% SZS status GaveUp for HL402734+5.p
32430.75/5251.62	% SZS status Ended for HL402734+5.p
32432.02/5251.80	% SZS status Started for HL402737+5.p
32432.02/5251.80	% SZS status Theorem for HL402737+5.p
32432.02/5251.80	% SZS status Ended for HL402737+5.p
32435.75/5252.26	% SZS status Started for HL402735+4.p
32435.75/5252.26	% SZS status GaveUp for HL402735+4.p
32435.75/5252.26	% SZS status Ended for HL402735+4.p
32436.16/5252.51	% SZS status Started for HL402735+5.p
32436.16/5252.51	% SZS status GaveUp for HL402735+5.p
32436.16/5252.51	% SZS status Ended for HL402735+5.p
32440.86/5252.92	% SZS status Started for HL402736+4.p
32440.86/5252.92	% SZS status GaveUp for HL402736+4.p
32440.86/5252.92	% SZS status Ended for HL402736+4.p
32441.87/5253.04	% SZS status Started for HL402736+5.p
32441.87/5253.04	% SZS status GaveUp for HL402736+5.p
32441.87/5253.04	% SZS status Ended for HL402736+5.p
32466.33/5256.10	% SZS status Started for HL402738+4.p
32466.33/5256.10	% SZS status GaveUp for HL402738+4.p
32466.33/5256.10	% SZS status Ended for HL402738+4.p
32473.26/5256.93	% SZS status Started for HL402743+4.p
32473.26/5256.93	% SZS status Theorem for HL402743+4.p
32473.26/5256.93	% SZS status Ended for HL402743+4.p
32476.12/5257.39	% SZS status Started for HL402738+5.p
32476.12/5257.39	% SZS status GaveUp for HL402738+5.p
32476.12/5257.39	% SZS status Ended for HL402738+5.p
32501.15/5260.47	% SZS status Started for HL402739+4.p
32501.15/5260.47	% SZS status GaveUp for HL402739+4.p
32501.15/5260.47	% SZS status Ended for HL402739+4.p
32501.84/5260.63	% SZS status Started for HL402739+5.p
32501.84/5260.63	% SZS status GaveUp for HL402739+5.p
32501.84/5260.63	% SZS status Ended for HL402739+5.p
32506.41/5261.19	% SZS status Started for HL402740+4.p
32506.41/5261.19	% SZS status GaveUp for HL402740+4.p
32506.41/5261.19	% SZS status Ended for HL402740+4.p
32506.87/5261.31	% SZS status Started for HL402740+5.p
32506.87/5261.31	% SZS status GaveUp for HL402740+5.p
32506.87/5261.31	% SZS status Ended for HL402740+5.p
32509.18/5261.44	% SZS status Started for HL402745+4.p
32509.18/5261.44	% SZS status Theorem for HL402745+4.p
32509.18/5261.44	% SZS status Ended for HL402745+4.p
32510.51/5261.65	% SZS status Started for HL402741+4.p
32510.51/5261.65	% SZS status GaveUp for HL402741+4.p
32510.51/5261.65	% SZS status Ended for HL402741+4.p
32512.71/5261.90	% SZS status Started for HL402741+5.p
32512.71/5261.90	% SZS status GaveUp for HL402741+5.p
32512.71/5261.90	% SZS status Ended for HL402741+5.p
32518.28/5262.58	% SZS status Started for HL402747+4.p
32518.28/5262.58	% SZS status Theorem for HL402747+4.p
32518.28/5262.58	% SZS status Ended for HL402747+4.p
32541.67/5265.73	% SZS status Started for HL402743+5.p
32541.67/5265.73	% SZS status GaveUp for HL402743+5.p
32541.67/5265.73	% SZS status Ended for HL402743+5.p
32546.01/5266.23	% SZS status Started for HL402744+4.p
32546.01/5266.23	% SZS status GaveUp for HL402744+4.p
32546.01/5266.23	% SZS status Ended for HL402744+4.p
32571.43/5269.36	% SZS status Started for HL402744+5.p
32571.43/5269.36	% SZS status GaveUp for HL402744+5.p
32571.43/5269.36	% SZS status Ended for HL402744+5.p
32575.59/5269.91	% SZS status Started for HL402745+5.p
32575.59/5269.91	% SZS status GaveUp for HL402745+5.p
32575.59/5269.91	% SZS status Ended for HL402745+5.p
32576.93/5270.16	% SZS status Started for HL402746+4.p
32576.93/5270.16	% SZS status GaveUp for HL402746+4.p
32576.93/5270.16	% SZS status Ended for HL402746+4.p
32579.49/5270.35	% SZS status Started for HL402746+5.p
32579.49/5270.35	% SZS status GaveUp for HL402746+5.p
32579.49/5270.35	% SZS status Ended for HL402746+5.p
32581.52/5270.66	% SZS status Started for HL402747+5.p
32581.52/5270.66	% SZS status GaveUp for HL402747+5.p
32581.52/5270.66	% SZS status Ended for HL402747+5.p
32586.25/5271.29	% SZS status Started for HL402748+4.p
32586.25/5271.29	% SZS status GaveUp for HL402748+4.p
32586.25/5271.29	% SZS status Ended for HL402748+4.p
32612.90/5274.58	% SZS status Started for HL402748+5.p
32612.90/5274.58	% SZS status GaveUp for HL402748+5.p
32612.90/5274.58	% SZS status Ended for HL402748+5.p
32616.13/5274.93	% SZS status Started for HL402749+4.p
32616.13/5274.93	% SZS status GaveUp for HL402749+4.p
32616.13/5274.93	% SZS status Ended for HL402749+4.p
32621.20/5275.61	% SZS status Started for HL402752+4.p
32621.20/5275.61	% SZS status Theorem for HL402752+4.p
32621.20/5275.61	% SZS status Ended for HL402752+4.p
32626.12/5276.32	% SZS status Started for HL402750+4.p
32626.12/5276.32	% SZS status Theorem for HL402750+4.p
32626.12/5276.32	% SZS status Ended for HL402750+4.p
32640.53/5278.07	% SZS status Started for HL402749+5.p
32640.53/5278.07	% SZS status GaveUp for HL402749+5.p
32640.53/5278.07	% SZS status Ended for HL402749+5.p
32648.26/5278.99	% SZS status Started for HL402750+5.p
32648.26/5278.99	% SZS status GaveUp for HL402750+5.p
32648.26/5278.99	% SZS status Ended for HL402750+5.p
32649.58/5279.17	% SZS status Started for HL402751+4.p
32649.58/5279.17	% SZS status GaveUp for HL402751+4.p
32649.58/5279.17	% SZS status Ended for HL402751+4.p
32651.74/5279.40	% SZS status Started for HL402751+5.p
32651.74/5279.40	% SZS status GaveUp for HL402751+5.p
32651.74/5279.40	% SZS status Ended for HL402751+5.p
32682.48/5283.34	% SZS status Started for HL402752+5.p
32682.48/5283.34	% SZS status GaveUp for HL402752+5.p
32682.48/5283.34	% SZS status Ended for HL402752+5.p
32685.69/5283.82	% SZS status Started for HL402753+4.p
32685.69/5283.82	% SZS status GaveUp for HL402753+4.p
32685.69/5283.82	% SZS status Ended for HL402753+4.p
32690.56/5284.41	% SZS status Started for HL402753+5.p
32690.56/5284.41	% SZS status GaveUp for HL402753+5.p
32690.56/5284.41	% SZS status Ended for HL402753+5.p
32695.38/5285.00	% SZS status Started for HL402756+4.p
32695.38/5285.00	% SZS status GaveUp for HL402756+4.p
32695.38/5285.00	% SZS status Ended for HL402756+4.p
32702.40/5285.79	% SZS status Started for HL402760+4.p
32702.40/5285.79	% SZS status Theorem for HL402760+4.p
32702.40/5285.79	% SZS status Ended for HL402760+4.p
32711.14/5286.86	% SZS status Started for HL402756+5.p
32711.14/5286.86	% SZS status GaveUp for HL402756+5.p
32711.14/5286.86	% SZS status Ended for HL402756+5.p
32716.81/5287.64	% SZS status Started for HL402761+4.p
32716.81/5287.64	% SZS status Theorem for HL402761+4.p
32716.81/5287.64	% SZS status Ended for HL402761+4.p
32717.93/5287.82	% SZS status Started for HL402757+4.p
32717.93/5287.82	% SZS status GaveUp for HL402757+4.p
32717.93/5287.82	% SZS status Ended for HL402757+4.p
32719.47/5287.90	% SZS status Started for HL402757+5.p
32719.47/5287.90	% SZS status GaveUp for HL402757+5.p
32719.47/5287.90	% SZS status Ended for HL402757+5.p
32720.60/5288.20	% SZS status Started for HL402758+4.p
32720.60/5288.20	% SZS status GaveUp for HL402758+4.p
32720.60/5288.20	% SZS status Ended for HL402758+4.p
32752.54/5292.11	% SZS status Started for HL402758+5.p
32752.54/5292.11	% SZS status GaveUp for HL402758+5.p
32752.54/5292.11	% SZS status Ended for HL402758+5.p
32756.34/5292.59	% SZS status Started for HL402759+4.p
32756.34/5292.59	% SZS status GaveUp for HL402759+4.p
32756.34/5292.59	% SZS status Ended for HL402759+4.p
32760.95/5293.14	% SZS status Started for HL402759+5.p
32760.95/5293.14	% SZS status GaveUp for HL402759+5.p
32760.95/5293.14	% SZS status Ended for HL402759+5.p
32771.74/5294.58	% SZS status Started for HL402760+5.p
32771.74/5294.58	% SZS status GaveUp for HL402760+5.p
32771.74/5294.58	% SZS status Ended for HL402760+5.p
32787.04/5296.42	% SZS status Started for HL402761+5.p
32787.04/5296.42	% SZS status GaveUp for HL402761+5.p
32787.04/5296.42	% SZS status Ended for HL402761+5.p
32787.94/5296.52	% SZS status Started for HL402762+4.p
32787.94/5296.52	% SZS status GaveUp for HL402762+4.p
32787.94/5296.52	% SZS status Ended for HL402762+4.p
32789.10/5296.70	% SZS status Started for HL402762+5.p
32789.10/5296.70	% SZS status GaveUp for HL402762+5.p
32789.10/5296.70	% SZS status Ended for HL402762+5.p
32790.79/5296.93	% SZS status Started for HL402763+4.p
32790.79/5296.93	% SZS status GaveUp for HL402763+4.p
32790.79/5296.93	% SZS status Ended for HL402763+4.p
32797.55/5297.76	% SZS status Started for HL402767+4.p
32797.55/5297.76	% SZS status Theorem for HL402767+4.p
32797.55/5297.76	% SZS status Ended for HL402767+4.p
32820.34/5300.88	% SZS status Started for HL402763+5.p
32820.34/5300.88	% SZS status GaveUp for HL402763+5.p
32820.34/5300.88	% SZS status Ended for HL402763+5.p
32825.82/5301.32	% SZS status Started for HL402764+4.p
32825.82/5301.32	% SZS status GaveUp for HL402764+4.p
32825.82/5301.32	% SZS status Ended for HL402764+4.p
32829.05/5301.71	% SZS status Started for HL402768+4.p
32829.05/5301.71	% SZS status Theorem for HL402768+4.p
32829.05/5301.71	% SZS status Ended for HL402768+4.p
32830.31/5301.90	% SZS status Started for HL402764+5.p
32830.31/5301.90	% SZS status GaveUp for HL402764+5.p
32830.31/5301.90	% SZS status Ended for HL402764+5.p
32842.09/5303.31	% SZS status Started for HL402765+4.p
32842.09/5303.31	% SZS status GaveUp for HL402765+4.p
32842.09/5303.31	% SZS status Ended for HL402765+4.p
32855.97/5305.14	% SZS status Started for HL402765+5.p
32855.97/5305.14	% SZS status GaveUp for HL402765+5.p
32855.97/5305.14	% SZS status Ended for HL402765+5.p
32856.84/5305.30	% SZS status Started for HL402766+4.p
32856.84/5305.30	% SZS status GaveUp for HL402766+4.p
32856.84/5305.30	% SZS status Ended for HL402766+4.p
32859.28/5305.46	% SZS status Started for HL402766+5.p
32859.28/5305.46	% SZS status GaveUp for HL402766+5.p
32859.28/5305.46	% SZS status Ended for HL402766+5.p
32867.04/5306.47	% SZS status Started for HL402767+5.p
32867.04/5306.47	% SZS status GaveUp for HL402767+5.p
32867.04/5306.47	% SZS status Ended for HL402767+5.p
32895.32/5310.04	% SZS status Started for HL402768+5.p
32895.32/5310.04	% SZS status GaveUp for HL402768+5.p
32895.32/5310.04	% SZS status Ended for HL402768+5.p
32898.71/5310.47	% SZS status Started for HL402769+4.p
32898.71/5310.47	% SZS status GaveUp for HL402769+4.p
32898.71/5310.47	% SZS status Ended for HL402769+4.p
32899.93/5310.64	% SZS status Started for HL402769+5.p
32899.93/5310.64	% SZS status GaveUp for HL402769+5.p
32899.93/5310.64	% SZS status Ended for HL402769+5.p
32904.75/5311.25	% SZS status Started for HL402773+4.p
32904.75/5311.25	% SZS status Theorem for HL402773+4.p
32904.75/5311.25	% SZS status Ended for HL402773+4.p
32910.67/5312.00	% SZS status Started for HL402774+4.p
32910.67/5312.00	% SZS status Theorem for HL402774+4.p
32910.67/5312.00	% SZS status Ended for HL402774+4.p
32911.39/5312.07	% SZS status Started for HL402770+4.p
32911.39/5312.07	% SZS status GaveUp for HL402770+4.p
32911.39/5312.07	% SZS status Ended for HL402770+4.p
32926.49/5313.95	% SZS status Started for HL402770+5.p
32926.49/5313.95	% SZS status GaveUp for HL402770+5.p
32926.49/5313.95	% SZS status Ended for HL402770+5.p
32927.57/5314.10	% SZS status Started for HL402771+4.p
32927.57/5314.10	% SZS status GaveUp for HL402771+4.p
32927.57/5314.10	% SZS status Ended for HL402771+4.p
32928.90/5314.30	% SZS status Started for HL402771+5.p
32928.90/5314.30	% SZS status GaveUp for HL402771+5.p
32928.90/5314.30	% SZS status Ended for HL402771+5.p
32936.23/5315.20	% SZS status Started for HL402772+4.p
32936.23/5315.20	% SZS status GaveUp for HL402772+4.p
32936.23/5315.20	% SZS status Ended for HL402772+4.p
32965.36/5318.94	% SZS status Started for HL402772+5.p
32965.36/5318.94	% SZS status GaveUp for HL402772+5.p
32965.36/5318.94	% SZS status Ended for HL402772+5.p
32970.15/5319.44	% SZS status Started for HL402773+5.p
32970.15/5319.44	% SZS status GaveUp for HL402773+5.p
32970.15/5319.44	% SZS status Ended for HL402773+5.p
32980.54/5320.75	% SZS status Started for HL402774+5.p
32980.54/5320.75	% SZS status GaveUp for HL402774+5.p
32980.54/5320.75	% SZS status Ended for HL402774+5.p
32981.12/5320.82	% SZS status Started for HL402775+4.p
32981.12/5320.82	% SZS status GaveUp for HL402775+4.p
32981.12/5320.82	% SZS status Ended for HL402775+4.p
32987.48/5321.67	% SZS status Started for HL402780+4.p
32987.48/5321.67	% SZS status Theorem for HL402780+4.p
32987.48/5321.67	% SZS status Ended for HL402780+4.p
32995.90/5322.69	% SZS status Started for HL402775+5.p
32995.90/5322.69	% SZS status GaveUp for HL402775+5.p
32995.90/5322.69	% SZS status Ended for HL402775+5.p
32996.86/5322.84	% SZS status Started for HL402777+4.p
32996.86/5322.84	% SZS status GaveUp for HL402777+4.p
32996.86/5322.84	% SZS status Ended for HL402777+4.p
32999.77/5323.15	% SZS status Started for HL402777+5.p
32999.77/5323.15	% SZS status GaveUp for HL402777+5.p
32999.77/5323.15	% SZS status Ended for HL402777+5.p
33005.32/5323.89	% SZS status Started for HL402778+4.p
33005.32/5323.89	% SZS status GaveUp for HL402778+4.p
33005.32/5323.89	% SZS status Ended for HL402778+4.p
33034.80/5327.72	% SZS status Started for HL402778+5.p
33034.80/5327.72	% SZS status GaveUp for HL402778+5.p
33034.80/5327.72	% SZS status Ended for HL402778+5.p
33038.76/5328.19	% SZS status Started for HL402779+4.p
33038.76/5328.19	% SZS status GaveUp for HL402779+4.p
33038.76/5328.19	% SZS status Ended for HL402779+4.p
33050.29/5329.54	% SZS status Started for HL402779+5.p
33050.29/5329.54	% SZS status GaveUp for HL402779+5.p
33050.29/5329.54	% SZS status Ended for HL402779+5.p
33057.59/5330.45	% SZS status Started for HL402780+5.p
33057.59/5330.45	% SZS status GaveUp for HL402780+5.p
33057.59/5330.45	% SZS status Ended for HL402780+5.p
33065.48/5331.42	% SZS status Started for HL402781+4.p
33065.48/5331.42	% SZS status GaveUp for HL402781+4.p
33065.48/5331.42	% SZS status Ended for HL402781+4.p
33066.02/5331.57	% SZS status Started for HL402781+5.p
33066.02/5331.57	% SZS status GaveUp for HL402781+5.p
33066.02/5331.57	% SZS status Ended for HL402781+5.p
33067.56/5331.86	% SZS status Started for HL402782+4.p
33067.56/5331.86	% SZS status GaveUp for HL402782+4.p
33067.56/5331.86	% SZS status Ended for HL402782+4.p
33075.41/5332.66	% SZS status Started for HL402782+5.p
33075.41/5332.66	% SZS status GaveUp for HL402782+5.p
33075.41/5332.66	% SZS status Ended for HL402782+5.p
33106.08/5336.50	% SZS status Started for HL402783+4.p
33106.08/5336.50	% SZS status GaveUp for HL402783+4.p
33106.08/5336.50	% SZS status Ended for HL402783+4.p
33110.34/5337.06	% SZS status Started for HL402783+5.p
33110.34/5337.06	% SZS status GaveUp for HL402783+5.p
33110.34/5337.06	% SZS status Ended for HL402783+5.p
33119.57/5338.21	% SZS status Started for HL402784+4.p
33119.57/5338.21	% SZS status GaveUp for HL402784+4.p
33119.57/5338.21	% SZS status Ended for HL402784+4.p
33127.47/5339.22	% SZS status Started for HL402784+5.p
33127.47/5339.22	% SZS status GaveUp for HL402784+5.p
33127.47/5339.22	% SZS status Ended for HL402784+5.p
33134.65/5340.12	% SZS status Started for HL402785+4.p
33134.65/5340.12	% SZS status GaveUp for HL402785+4.p
33134.65/5340.12	% SZS status Ended for HL402785+4.p
33135.60/5340.33	% SZS status Started for HL402785+5.p
33135.60/5340.33	% SZS status GaveUp for HL402785+5.p
33135.60/5340.33	% SZS status Ended for HL402785+5.p
33138.45/5340.63	% SZS status Started for HL402786+4.p
33138.45/5340.63	% SZS status GaveUp for HL402786+4.p
33138.45/5340.63	% SZS status Ended for HL402786+4.p
33145.31/5341.43	% SZS status Started for HL402786+5.p
33145.31/5341.43	% SZS status GaveUp for HL402786+5.p
33145.31/5341.43	% SZS status Ended for HL402786+5.p
33175.08/5345.26	% SZS status Started for HL402787+4.p
33175.08/5345.26	% SZS status GaveUp for HL402787+4.p
33175.08/5345.26	% SZS status Ended for HL402787+4.p
33179.63/5345.77	% SZS status Started for HL402787+5.p
33179.63/5345.77	% SZS status GaveUp for HL402787+5.p
33179.63/5345.77	% SZS status Ended for HL402787+5.p
33190.20/5347.12	% SZS status Started for HL402788+4.p
33190.20/5347.12	% SZS status GaveUp for HL402788+4.p
33190.20/5347.12	% SZS status Ended for HL402788+4.p
33197.04/5347.96	% SZS status Started for HL402788+5.p
33197.04/5347.96	% SZS status GaveUp for HL402788+5.p
33197.04/5347.96	% SZS status Ended for HL402788+5.p
33204.34/5348.86	% SZS status Started for HL402789+4.p
33204.34/5348.86	% SZS status GaveUp for HL402789+4.p
33204.34/5348.86	% SZS status Ended for HL402789+4.p
33208.02/5349.36	% SZS status Started for HL402790+4.p
33208.02/5349.36	% SZS status GaveUp for HL402790+4.p
33208.02/5349.36	% SZS status Ended for HL402790+4.p
33213.96/5350.15	% SZS status Started for HL402790+5.p
33213.96/5350.15	% SZS status GaveUp for HL402790+5.p
33213.96/5350.15	% SZS status Ended for HL402790+5.p
33232.38/5352.41	% SZS status Started for HL402794+4.p
33232.38/5352.41	% SZS status Theorem for HL402794+4.p
33232.38/5352.41	% SZS status Ended for HL402794+4.p
33244.85/5354.00	% SZS status Started for HL402791+4.p
33244.85/5354.00	% SZS status GaveUp for HL402791+4.p
33244.85/5354.00	% SZS status Ended for HL402791+4.p
33249.22/5354.50	% SZS status Started for HL402791+5.p
33249.22/5354.50	% SZS status GaveUp for HL402791+5.p
33249.22/5354.50	% SZS status Ended for HL402791+5.p
33260.71/5355.96	% SZS status Started for HL402793+4.p
33260.71/5355.96	% SZS status GaveUp for HL402793+4.p
33260.71/5355.96	% SZS status Ended for HL402793+4.p
33266.55/5356.71	% SZS status Started for HL402793+5.p
33266.55/5356.71	% SZS status GaveUp for HL402793+5.p
33266.55/5356.71	% SZS status Ended for HL402793+5.p
33277.33/5358.14	% SZS status Started for HL402794+5.p
33277.33/5358.14	% SZS status GaveUp for HL402794+5.p
33277.33/5358.14	% SZS status Ended for HL402794+5.p
33284.29/5358.91	% SZS status Started for HL402795+4.p
33284.29/5358.91	% SZS status GaveUp for HL402795+4.p
33284.29/5358.91	% SZS status Ended for HL402795+4.p
33295.41/5360.34	% SZS status Started for HL402789+5.p
33295.41/5360.34	% SZS status GaveUp for HL402789+5.p
33295.41/5360.34	% SZS status Ended for HL402789+5.p
33302.27/5361.20	% SZS status Started for HL402795+5.p
33302.27/5361.20	% SZS status GaveUp for HL402795+5.p
33302.27/5361.20	% SZS status Ended for HL402795+5.p
33314.81/5362.76	% SZS status Started for HL402796+4.p
33314.81/5362.76	% SZS status GaveUp for HL402796+4.p
33314.81/5362.76	% SZS status Ended for HL402796+4.p
33316.55/5363.27	% SZS status Started for HL402796+5.p
33316.55/5363.27	% SZS status GaveUp for HL402796+5.p
33316.55/5363.27	% SZS status Ended for HL402796+5.p
33330.16/5364.74	% SZS status Started for HL402797+4.p
33330.16/5364.74	% SZS status GaveUp for HL402797+4.p
33330.16/5364.74	% SZS status Ended for HL402797+4.p
33337.14/5365.53	% SZS status Started for HL402797+5.p
33337.14/5365.53	% SZS status GaveUp for HL402797+5.p
33337.14/5365.53	% SZS status Ended for HL402797+5.p
33337.14/5365.56	% SZS status Started for HL402800+4.p
33337.14/5365.56	% SZS status Theorem for HL402800+4.p
33337.14/5365.56	% SZS status Ended for HL402800+4.p
33347.33/5366.84	% SZS status Started for HL402798+4.p
33347.33/5366.84	% SZS status GaveUp for HL402798+4.p
33347.33/5366.84	% SZS status Ended for HL402798+4.p
33353.14/5367.60	% SZS status Started for HL402801+4.p
33353.14/5367.60	% SZS status Theorem for HL402801+4.p
33353.14/5367.60	% SZS status Ended for HL402801+4.p
33353.90/5367.70	% SZS status Started for HL402798+5.p
33353.90/5367.70	% SZS status GaveUp for HL402798+5.p
33353.90/5367.70	% SZS status Ended for HL402798+5.p
33361.68/5368.66	% SZS status Started for HL402802+4.p
33361.68/5368.66	% SZS status Theorem for HL402802+4.p
33361.68/5368.66	% SZS status Ended for HL402802+4.p
33365.22/5369.09	% SZS status Started for HL402799+4.p
33365.22/5369.09	% SZS status GaveUp for HL402799+4.p
33365.22/5369.09	% SZS status Ended for HL402799+4.p
33371.59/5369.96	% SZS status Started for HL402799+5.p
33371.59/5369.96	% SZS status GaveUp for HL402799+5.p
33371.59/5369.96	% SZS status Ended for HL402799+5.p
33376.11/5370.55	% SZS status Started for HL402803+4.p
33376.11/5370.55	% SZS status Theorem for HL402803+4.p
33376.11/5370.55	% SZS status Ended for HL402803+4.p
33389.13/5372.14	% SZS status Started for HL402800+5.p
33389.13/5372.14	% SZS status GaveUp for HL402800+5.p
33389.13/5372.14	% SZS status Ended for HL402800+5.p
33407.32/5374.45	% SZS status Started for HL402801+5.p
33407.32/5374.45	% SZS status GaveUp for HL402801+5.p
33407.32/5374.45	% SZS status Ended for HL402801+5.p
33416.47/5375.63	% SZS status Started for HL402802+5.p
33416.47/5375.63	% SZS status GaveUp for HL402802+5.p
33416.47/5375.63	% SZS status Ended for HL402802+5.p
33424.00/5376.55	% SZS status Started for HL402803+5.p
33424.00/5376.55	% SZS status GaveUp for HL402803+5.p
33424.00/5376.55	% SZS status Ended for HL402803+5.p
33431.36/5377.45	% SZS status Started for HL402805+4.p
33431.36/5377.45	% SZS status GaveUp for HL402805+4.p
33431.36/5377.45	% SZS status Ended for HL402805+4.p
33432.98/5377.66	% SZS status Started for HL402805+5.p
33432.98/5377.66	% SZS status GaveUp for HL402805+5.p
33432.98/5377.66	% SZS status Ended for HL402805+5.p
33436.89/5378.22	% SZS status Started for HL402811+4.p
33436.89/5378.22	% SZS status Theorem for HL402811+4.p
33436.89/5378.22	% SZS status Ended for HL402811+4.p
33442.13/5378.83	% SZS status Started for HL402806+4.p
33442.13/5378.83	% SZS status GaveUp for HL402806+4.p
33442.13/5378.83	% SZS status Ended for HL402806+4.p
33442.79/5378.87	% SZS status Started for HL402811+5.p
33442.79/5378.87	% SZS status Theorem for HL402811+5.p
33442.79/5378.87	% SZS status Ended for HL402811+5.p
33446.00/5379.36	% SZS status Started for HL402806+5.p
33446.00/5379.36	% SZS status GaveUp for HL402806+5.p
33446.00/5379.36	% SZS status Ended for HL402806+5.p
33458.81/5380.91	% SZS status Started for HL402807+4.p
33458.81/5380.91	% SZS status GaveUp for HL402807+4.p
33458.81/5380.91	% SZS status Ended for HL402807+4.p
33468.52/5382.17	% SZS status Started for HL402812+4.p
33468.52/5382.17	% SZS status Theorem for HL402812+4.p
33468.52/5382.17	% SZS status Ended for HL402812+4.p
33476.88/5383.20	% SZS status Started for HL402807+5.p
33476.88/5383.20	% SZS status GaveUp for HL402807+5.p
33476.88/5383.20	% SZS status Ended for HL402807+5.p
33486.46/5384.42	% SZS status Started for HL402808+4.p
33486.46/5384.42	% SZS status GaveUp for HL402808+4.p
33486.46/5384.42	% SZS status Ended for HL402808+4.p
33494.17/5385.31	% SZS status Started for HL402808+5.p
33494.17/5385.31	% SZS status GaveUp for HL402808+5.p
33494.17/5385.31	% SZS status Ended for HL402808+5.p
33508.60/5387.32	% SZS status Started for HL402812+5.p
33508.60/5387.32	% SZS status GaveUp for HL402812+5.p
33508.60/5387.32	% SZS status Ended for HL402812+5.p
33513.34/5387.74	% SZS status Started for HL402813+4.p
33513.34/5387.74	% SZS status GaveUp for HL402813+4.p
33513.34/5387.74	% SZS status Ended for HL402813+4.p
33514.57/5387.87	% SZS status Started for HL402813+5.p
33514.57/5387.87	% SZS status GaveUp for HL402813+5.p
33514.57/5387.87	% SZS status Ended for HL402813+5.p
33529.59/5389.80	% SZS status Started for HL402814+4.p
33529.59/5389.80	% SZS status GaveUp for HL402814+4.p
33529.59/5389.80	% SZS status Ended for HL402814+4.p
33535.64/5390.65	% SZS status Started for HL402814+5.p
33535.64/5390.65	% SZS status GaveUp for HL402814+5.p
33535.64/5390.65	% SZS status Ended for HL402814+5.p
33547.20/5391.99	% SZS status Started for HL402815+4.p
33547.20/5391.99	% SZS status GaveUp for HL402815+4.p
33547.20/5391.99	% SZS status Ended for HL402815+4.p
33556.61/5393.26	% SZS status Started for HL402815+5.p
33556.61/5393.26	% SZS status GaveUp for HL402815+5.p
33556.61/5393.26	% SZS status Ended for HL402815+5.p
33565.30/5394.27	% SZS status Started for HL402816+4.p
33565.30/5394.27	% SZS status GaveUp for HL402816+4.p
33565.30/5394.27	% SZS status Ended for HL402816+4.p
33576.15/5395.78	% SZS status Started for HL402816+5.p
33576.15/5395.78	% SZS status GaveUp for HL402816+5.p
33576.15/5395.78	% SZS status Ended for HL402816+5.p
33581.91/5396.36	% SZS status Started for HL402817+5.p
33581.91/5396.36	% SZS status GaveUp for HL402817+5.p
33581.91/5396.36	% SZS status Ended for HL402817+5.p
33582.64/5396.49	% SZS status Started for HL402817+4.p
33582.64/5396.49	% SZS status GaveUp for HL402817+4.p
33582.64/5396.49	% SZS status Ended for HL402817+4.p
33588.00/5397.12	% SZS status Started for HL402819+4.p
33588.00/5397.12	% SZS status Theorem for HL402819+4.p
33588.00/5397.12	% SZS status Ended for HL402819+4.p
33598.29/5398.48	% SZS status Started for HL402818+4.p
33598.29/5398.48	% SZS status GaveUp for HL402818+4.p
33598.29/5398.48	% SZS status Ended for HL402818+4.p
33602.76/5399.16	% SZS status Started for HL402818+5.p
33602.76/5399.16	% SZS status GaveUp for HL402818+5.p
33602.76/5399.16	% SZS status Ended for HL402818+5.p
33621.07/5401.46	% SZS status Started for HL402822+4.p
33621.07/5401.46	% SZS status Theorem for HL402822+4.p
33621.07/5401.46	% SZS status Ended for HL402822+4.p
33625.24/5401.79	% SZS status Started for HL402819+5.p
33625.24/5401.79	% SZS status GaveUp for HL402819+5.p
33625.24/5401.79	% SZS status Ended for HL402819+5.p
33634.67/5403.06	% SZS status Started for HL402820+4.p
33634.67/5403.06	% SZS status GaveUp for HL402820+4.p
33634.67/5403.06	% SZS status Ended for HL402820+4.p
33643.52/5404.25	% SZS status Started for HL402822+5.p
33643.52/5404.25	% SZS status Theorem for HL402822+5.p
33643.52/5404.25	% SZS status Ended for HL402822+5.p
33643.99/5404.29	% SZS status Started for HL402820+5.p
33643.99/5404.29	% SZS status GaveUp for HL402820+5.p
33643.99/5404.29	% SZS status Ended for HL402820+5.p
33650.56/5404.99	% SZS status Started for HL402821+5.p
33650.56/5404.99	% SZS status GaveUp for HL402821+5.p
33650.56/5404.99	% SZS status Ended for HL402821+5.p
33651.75/5405.15	% SZS status Started for HL402821+4.p
33651.75/5405.15	% SZS status GaveUp for HL402821+4.p
33651.75/5405.15	% SZS status Ended for HL402821+4.p
33675.19/5407.97	% SZS status Started for HL402824+4.p
33675.19/5407.97	% SZS status GaveUp for HL402824+4.p
33675.19/5407.97	% SZS status Ended for HL402824+4.p
33692.66/5410.19	% SZS status Started for HL402824+5.p
33692.66/5410.19	% SZS status GaveUp for HL402824+5.p
33692.66/5410.19	% SZS status Ended for HL402824+5.p
33694.55/5410.53	% SZS status Started for HL402825+4.p
33694.55/5410.53	% SZS status GaveUp for HL402825+4.p
33694.55/5410.53	% SZS status Ended for HL402825+4.p
33706.27/5411.87	% SZS status Started for HL402825+5.p
33706.27/5411.87	% SZS status GaveUp for HL402825+5.p
33706.27/5411.87	% SZS status Ended for HL402825+5.p
33712.72/5412.81	% SZS status Started for HL402826+5.p
33712.72/5412.81	% SZS status GaveUp for HL402826+5.p
33712.72/5412.81	% SZS status Ended for HL402826+5.p
33715.19/5412.98	% SZS status Started for HL402826+4.p
33715.19/5412.98	% SZS status GaveUp for HL402826+4.p
33715.19/5412.98	% SZS status Ended for HL402826+4.p
33719.65/5413.65	% SZS status Started for HL402827+5.p
33719.65/5413.65	% SZS status GaveUp for HL402827+5.p
33719.65/5413.65	% SZS status Ended for HL402827+5.p
33720.50/5413.74	% SZS status Started for HL402827+4.p
33720.50/5413.74	% SZS status GaveUp for HL402827+4.p
33720.50/5413.74	% SZS status Ended for HL402827+4.p
33745.76/5416.93	% SZS status Started for HL402828+4.p
33745.76/5416.93	% SZS status GaveUp for HL402828+4.p
33745.76/5416.93	% SZS status Ended for HL402828+4.p
33759.52/5418.66	% SZS status Started for HL402828+5.p
33759.52/5418.66	% SZS status GaveUp for HL402828+5.p
33759.52/5418.66	% SZS status Ended for HL402828+5.p
33764.67/5419.22	% SZS status Started for HL402830+4.p
33764.67/5419.22	% SZS status GaveUp for HL402830+4.p
33764.67/5419.22	% SZS status Ended for HL402830+4.p
33773.12/5420.37	% SZS status Started for HL402830+5.p
33773.12/5420.37	% SZS status GaveUp for HL402830+5.p
33773.12/5420.37	% SZS status Ended for HL402830+5.p
33782.25/5421.50	% SZS status Started for HL402831+5.p
33782.25/5421.50	% SZS status GaveUp for HL402831+5.p
33782.25/5421.50	% SZS status Ended for HL402831+5.p
33784.23/5421.67	% SZS status Started for HL402831+4.p
33784.23/5421.67	% SZS status GaveUp for HL402831+4.p
33784.23/5421.67	% SZS status Ended for HL402831+4.p
33789.03/5422.27	% SZS status Started for HL402832+5.p
33789.03/5422.27	% SZS status GaveUp for HL402832+5.p
33789.03/5422.27	% SZS status Ended for HL402832+5.p
33791.17/5422.61	% SZS status Started for HL402832+4.p
33791.17/5422.61	% SZS status GaveUp for HL402832+4.p
33791.17/5422.61	% SZS status Ended for HL402832+4.p
33816.59/5425.81	% SZS status Started for HL402833+4.p
33816.59/5425.81	% SZS status GaveUp for HL402833+4.p
33816.59/5425.81	% SZS status Ended for HL402833+4.p
33826.98/5427.14	% SZS status Started for HL402833+5.p
33826.98/5427.14	% SZS status GaveUp for HL402833+5.p
33826.98/5427.14	% SZS status Ended for HL402833+5.p
33833.44/5427.99	% SZS status Started for HL402834+4.p
33833.44/5427.99	% SZS status GaveUp for HL402834+4.p
33833.44/5427.99	% SZS status Ended for HL402834+4.p
33841.08/5428.85	% SZS status Started for HL402834+5.p
33841.08/5428.85	% SZS status GaveUp for HL402834+5.p
33841.08/5428.85	% SZS status Ended for HL402834+5.p
33851.07/5430.16	% SZS status Started for HL402835+5.p
33851.07/5430.16	% SZS status GaveUp for HL402835+5.p
33851.07/5430.16	% SZS status Ended for HL402835+5.p
33852.04/5430.25	% SZS status Started for HL402835+4.p
33852.04/5430.25	% SZS status GaveUp for HL402835+4.p
33852.04/5430.25	% SZS status Ended for HL402835+4.p
33857.96/5430.99	% SZS status Started for HL402836+4.p
33857.96/5430.99	% SZS status GaveUp for HL402836+4.p
33857.96/5430.99	% SZS status Ended for HL402836+4.p
33861.18/5431.42	% SZS status Started for HL402836+5.p
33861.18/5431.42	% SZS status GaveUp for HL402836+5.p
33861.18/5431.42	% SZS status Ended for HL402836+5.p
33886.59/5434.56	% SZS status Started for HL402837+4.p
33886.59/5434.56	% SZS status GaveUp for HL402837+4.p
33886.59/5434.56	% SZS status Ended for HL402837+4.p
33897.02/5435.89	% SZS status Started for HL402837+5.p
33897.02/5435.89	% SZS status GaveUp for HL402837+5.p
33897.02/5435.89	% SZS status Ended for HL402837+5.p
33904.66/5436.88	% SZS status Started for HL402839+4.p
33904.66/5436.88	% SZS status GaveUp for HL402839+4.p
33904.66/5436.88	% SZS status Ended for HL402839+4.p
33911.28/5437.74	% SZS status Started for HL402839+5.p
33911.28/5437.74	% SZS status GaveUp for HL402839+5.p
33911.28/5437.74	% SZS status Ended for HL402839+5.p
33921.39/5438.99	% SZS status Started for HL402840+5.p
33921.39/5438.99	% SZS status GaveUp for HL402840+5.p
33921.39/5438.99	% SZS status Ended for HL402840+5.p
33921.39/5439.03	% SZS status Started for HL402840+4.p
33921.39/5439.03	% SZS status GaveUp for HL402840+4.p
33921.39/5439.03	% SZS status Ended for HL402840+4.p
33925.74/5439.71	% SZS status Started for HL402841+4.p
33925.74/5439.71	% SZS status GaveUp for HL402841+4.p
33925.74/5439.71	% SZS status Ended for HL402841+4.p
33932.77/5440.43	% SZS status Started for HL402841+5.p
33932.77/5440.43	% SZS status GaveUp for HL402841+5.p
33932.77/5440.43	% SZS status Ended for HL402841+5.p
33956.82/5443.50	% SZS status Started for HL402842+4.p
33956.82/5443.50	% SZS status GaveUp for HL402842+4.p
33956.82/5443.50	% SZS status Ended for HL402842+4.p
33966.60/5444.77	% SZS status Started for HL402842+5.p
33966.60/5444.77	% SZS status GaveUp for HL402842+5.p
33966.60/5444.77	% SZS status Ended for HL402842+5.p
33974.58/5445.69	% SZS status Started for HL402844+4.p
33974.58/5445.69	% SZS status GaveUp for HL402844+4.p
33974.58/5445.69	% SZS status Ended for HL402844+4.p
33980.45/5446.57	% SZS status Started for HL402844+5.p
33980.45/5446.57	% SZS status GaveUp for HL402844+5.p
33980.45/5446.57	% SZS status Ended for HL402844+5.p
33989.02/5447.70	% SZS status Started for HL402845+4.p
33989.02/5447.70	% SZS status GaveUp for HL402845+4.p
33989.02/5447.70	% SZS status Ended for HL402845+4.p
33991.85/5447.84	% SZS status Started for HL402845+5.p
33991.85/5447.84	% SZS status GaveUp for HL402845+5.p
33991.85/5447.84	% SZS status Ended for HL402845+5.p
33996.36/5448.42	% SZS status Started for HL402846+4.p
33996.36/5448.42	% SZS status GaveUp for HL402846+4.p
33996.36/5448.42	% SZS status Ended for HL402846+4.p
34004.16/5449.38	% SZS status Started for HL402846+5.p
34004.16/5449.38	% SZS status GaveUp for HL402846+5.p
34004.16/5449.38	% SZS status Ended for HL402846+5.p
34005.29/5449.56	% SZS status Started for HL402849+4.p
34005.29/5449.56	% SZS status Theorem for HL402849+4.p
34005.29/5449.56	% SZS status Ended for HL402849+4.p
34011.65/5450.43	% SZS status Started for HL402851+4.p
34011.65/5450.43	% SZS status Theorem for HL402851+4.p
34011.65/5450.43	% SZS status Ended for HL402851+4.p
34025.72/5452.20	% SZS status Started for HL402847+4.p
34025.72/5452.20	% SZS status GaveUp for HL402847+4.p
34025.72/5452.20	% SZS status Ended for HL402847+4.p
34027.19/5452.28	% SZS status Started for HL402850+4.p
34027.19/5452.28	% SZS status Theorem for HL402850+4.p
34027.19/5452.28	% SZS status Ended for HL402850+4.p
34035.96/5453.57	% SZS status Started for HL402849+5.p
34035.96/5453.57	% SZS status Theorem for HL402849+5.p
34035.96/5453.57	% SZS status Ended for HL402849+5.p
34038.84/5453.73	% SZS status Started for HL402847+5.p
34038.84/5453.73	% SZS status GaveUp for HL402847+5.p
34038.84/5453.73	% SZS status Ended for HL402847+5.p
34043.73/5454.45	% SZS status Started for HL402848+4.p
34043.73/5454.45	% SZS status GaveUp for HL402848+4.p
34043.73/5454.45	% SZS status Ended for HL402848+4.p
34052.70/5455.52	% SZS status Started for HL402848+5.p
34052.70/5455.52	% SZS status GaveUp for HL402848+5.p
34052.70/5455.52	% SZS status Ended for HL402848+5.p
34070.97/5457.92	% SZS status Started for HL402850+5.p
34070.97/5457.92	% SZS status GaveUp for HL402850+5.p
34070.97/5457.92	% SZS status Ended for HL402850+5.p
34081.98/5459.19	% SZS status Started for HL402851+5.p
34081.98/5459.19	% SZS status GaveUp for HL402851+5.p
34081.98/5459.19	% SZS status Ended for HL402851+5.p
34096.82/5461.04	% SZS status Started for HL402852+5.p
34096.82/5461.04	% SZS status GaveUp for HL402852+5.p
34096.82/5461.04	% SZS status Ended for HL402852+5.p
34099.86/5461.47	% SZS status Started for HL402852+4.p
34099.86/5461.47	% SZS status GaveUp for HL402852+4.p
34099.86/5461.47	% SZS status Ended for HL402852+4.p
34106.48/5462.33	% SZS status Started for HL402853+4.p
34106.48/5462.33	% SZS status GaveUp for HL402853+4.p
34106.48/5462.33	% SZS status Ended for HL402853+4.p
34108.96/5462.63	% SZS status Started for HL402853+5.p
34108.96/5462.63	% SZS status GaveUp for HL402853+5.p
34108.96/5462.63	% SZS status Ended for HL402853+5.p
34113.86/5463.24	% SZS status Started for HL402854+4.p
34113.86/5463.24	% SZS status GaveUp for HL402854+4.p
34113.86/5463.24	% SZS status Ended for HL402854+4.p
34122.45/5464.29	% SZS status Started for HL402854+5.p
34122.45/5464.29	% SZS status GaveUp for HL402854+5.p
34122.45/5464.29	% SZS status Ended for HL402854+5.p
34142.25/5466.77	% SZS status Started for HL402855+4.p
34142.25/5466.77	% SZS status GaveUp for HL402855+4.p
34142.25/5466.77	% SZS status Ended for HL402855+4.p
34151.72/5467.96	% SZS status Started for HL402855+5.p
34151.72/5467.96	% SZS status GaveUp for HL402855+5.p
34151.72/5467.96	% SZS status Ended for HL402855+5.p
34165.96/5469.76	% SZS status Started for HL402856+4.p
34165.96/5469.76	% SZS status GaveUp for HL402856+4.p
34165.96/5469.76	% SZS status Ended for HL402856+4.p
34171.50/5470.46	% SZS status Started for HL402856+5.p
34171.50/5470.46	% SZS status GaveUp for HL402856+5.p
34171.50/5470.46	% SZS status Ended for HL402856+5.p
34176.38/5471.18	% SZS status Started for HL402857+4.p
34176.38/5471.18	% SZS status GaveUp for HL402857+4.p
34176.38/5471.18	% SZS status Ended for HL402857+4.p
34179.00/5471.40	% SZS status Started for HL402857+5.p
34179.00/5471.40	% SZS status GaveUp for HL402857+5.p
34179.00/5471.40	% SZS status Ended for HL402857+5.p
34183.84/5472.06	% SZS status Started for HL402859+4.p
34183.84/5472.06	% SZS status GaveUp for HL402859+4.p
34183.84/5472.06	% SZS status Ended for HL402859+4.p
34189.61/5472.81	% SZS status Started for HL402859+5.p
34189.61/5472.81	% SZS status GaveUp for HL402859+5.p
34189.61/5472.81	% SZS status Ended for HL402859+5.p
34223.01/5476.97	% SZS status Started for HL402860+4.p
34223.01/5476.97	% SZS status GaveUp for HL402860+4.p
34223.01/5476.97	% SZS status Ended for HL402860+4.p
34235.09/5478.52	% SZS status Started for HL402861+4.p
34235.09/5478.52	% SZS status GaveUp for HL402861+4.p
34235.09/5478.52	% SZS status Ended for HL402861+4.p
34240.63/5479.22	% SZS status Started for HL402861+5.p
34240.63/5479.22	% SZS status GaveUp for HL402861+5.p
34240.63/5479.22	% SZS status Ended for HL402861+5.p
34245.83/5480.00	% SZS status Started for HL402862+4.p
34245.83/5480.00	% SZS status GaveUp for HL402862+4.p
34245.83/5480.00	% SZS status Ended for HL402862+4.p
34247.73/5480.06	% SZS status Started for HL402865+4.p
34247.73/5480.06	% SZS status Theorem for HL402865+4.p
34247.73/5480.06	% SZS status Ended for HL402865+4.p
34248.75/5480.25	% SZS status Started for HL402862+5.p
34248.75/5480.25	% SZS status GaveUp for HL402862+5.p
34248.75/5480.25	% SZS status Ended for HL402862+5.p
34253.62/5480.86	% SZS status Started for HL402863+4.p
34253.62/5480.86	% SZS status GaveUp for HL402863+4.p
34253.62/5480.86	% SZS status Ended for HL402863+4.p
34259.63/5481.61	% SZS status Started for HL402863+5.p
34259.63/5481.61	% SZS status GaveUp for HL402863+5.p
34259.63/5481.61	% SZS status Ended for HL402863+5.p
34273.92/5483.36	% SZS status Started for HL402867+4.p
34273.92/5483.36	% SZS status Theorem for HL402867+4.p
34273.92/5483.36	% SZS status Ended for HL402867+4.p
34292.83/5485.76	% SZS status Started for HL402864+4.p
34292.83/5485.76	% SZS status GaveUp for HL402864+4.p
34292.83/5485.76	% SZS status Ended for HL402864+4.p
34296.80/5486.26	% SZS status Started for HL402865+5.p
34296.80/5486.26	% SZS status Theorem for HL402865+5.p
34296.80/5486.26	% SZS status Ended for HL402865+5.p
34305.51/5487.28	% SZS status Started for HL402864+5.p
34305.51/5487.28	% SZS status GaveUp for HL402864+5.p
34305.51/5487.28	% SZS status Ended for HL402864+5.p
34317.56/5488.82	% SZS status Started for HL402866+4.p
34317.56/5488.82	% SZS status GaveUp for HL402866+4.p
34317.56/5488.82	% SZS status Ended for HL402866+4.p
34318.94/5488.99	% SZS status Started for HL402866+5.p
34318.94/5488.99	% SZS status GaveUp for HL402866+5.p
34318.94/5488.99	% SZS status Ended for HL402866+5.p
34324.29/5489.71	% SZS status Started for HL402871+4.p
34324.29/5489.71	% SZS status Theorem for HL402871+4.p
34324.29/5489.71	% SZS status Ended for HL402871+4.p
34329.10/5490.30	% SZS status Started for HL402867+5.p
34329.10/5490.30	% SZS status GaveUp for HL402867+5.p
34329.10/5490.30	% SZS status Ended for HL402867+5.p
34332.62/5490.70	% SZS status Started for HL402860+5.p
34332.62/5490.70	% SZS status GaveUp for HL402860+5.p
34332.62/5490.70	% SZS status Ended for HL402860+5.p
34343.27/5492.09	% SZS status Started for HL402872+4.p
34343.27/5492.09	% SZS status Theorem for HL402872+4.p
34343.27/5492.09	% SZS status Ended for HL402872+4.p
34343.27/5492.13	% SZS status Started for HL402869+4.p
34343.27/5492.13	% SZS status GaveUp for HL402869+4.p
34343.27/5492.13	% SZS status Ended for HL402869+4.p
34358.76/5494.05	% SZS status Started for HL402871+5.p
34358.76/5494.05	% SZS status Theorem for HL402871+5.p
34358.76/5494.05	% SZS status Ended for HL402871+5.p
34362.57/5494.55	% SZS status Started for HL402869+5.p
34362.57/5494.55	% SZS status GaveUp for HL402869+5.p
34362.57/5494.55	% SZS status Ended for HL402869+5.p
34366.94/5495.07	% SZS status Started for HL402870+4.p
34366.94/5495.07	% SZS status GaveUp for HL402870+4.p
34366.94/5495.07	% SZS status Ended for HL402870+4.p
34375.03/5496.07	% SZS status Started for HL402870+5.p
34375.03/5496.07	% SZS status GaveUp for HL402870+5.p
34375.03/5496.07	% SZS status Ended for HL402870+5.p
34398.33/5499.14	% SZS status Started for HL402872+5.p
34398.33/5499.14	% SZS status GaveUp for HL402872+5.p
34398.33/5499.14	% SZS status Ended for HL402872+5.p
34403.69/5499.72	% SZS status Started for HL402874+4.p
34403.69/5499.72	% SZS status GaveUp for HL402874+4.p
34403.69/5499.72	% SZS status Ended for HL402874+4.p
34412.91/5500.91	% SZS status Started for HL402875+4.p
34412.91/5500.91	% SZS status GaveUp for HL402875+4.p
34412.91/5500.91	% SZS status Ended for HL402875+4.p
34413.73/5500.98	% SZS status Started for HL402874+5.p
34413.73/5500.98	% SZS status GaveUp for HL402874+5.p
34413.73/5500.98	% SZS status Ended for HL402874+5.p
34414.66/5501.16	% SZS status Started for HL402878+4.p
34414.66/5501.16	% SZS status Theorem for HL402878+4.p
34414.66/5501.16	% SZS status Ended for HL402878+4.p
34428.85/5502.87	% SZS status Started for HL402875+5.p
34428.85/5502.87	% SZS status GaveUp for HL402875+5.p
34428.85/5502.87	% SZS status Ended for HL402875+5.p
34431.38/5503.25	% SZS status Started for HL402876+4.p
34431.38/5503.25	% SZS status GaveUp for HL402876+4.p
34431.38/5503.25	% SZS status Ended for HL402876+4.p
34437.28/5503.94	% SZS status Started for HL402876+5.p
34437.28/5503.94	% SZS status GaveUp for HL402876+5.p
34437.28/5503.94	% SZS status Ended for HL402876+5.p
34444.26/5504.94	% SZS status Started for HL402877+4.p
34444.26/5504.94	% SZS status GaveUp for HL402877+4.p
34444.26/5504.94	% SZS status Ended for HL402877+4.p
34468.00/5507.98	% SZS status Started for HL402877+5.p
34468.00/5507.98	% SZS status GaveUp for HL402877+5.p
34468.00/5507.98	% SZS status Ended for HL402877+5.p
34483.73/5509.89	% SZS status Started for HL402879+4.p
34483.73/5509.89	% SZS status GaveUp for HL402879+4.p
34483.73/5509.89	% SZS status Ended for HL402879+4.p
34483.73/5509.91	% SZS status Started for HL402878+5.p
34483.73/5509.91	% SZS status GaveUp for HL402878+5.p
34483.73/5509.91	% SZS status Ended for HL402878+5.p
34485.91/5510.08	% SZS status Started for HL402879+5.p
34485.91/5510.08	% SZS status GaveUp for HL402879+5.p
34485.91/5510.08	% SZS status Ended for HL402879+5.p
34498.42/5511.69	% SZS status Started for HL402880+4.p
34498.42/5511.69	% SZS status GaveUp for HL402880+4.p
34498.42/5511.69	% SZS status Ended for HL402880+4.p
34499.63/5512.02	% SZS status Started for HL402880+5.p
34499.63/5512.02	% SZS status GaveUp for HL402880+5.p
34499.63/5512.02	% SZS status Ended for HL402880+5.p
34506.02/5512.74	% SZS status Started for HL402882+4.p
34506.02/5512.74	% SZS status GaveUp for HL402882+4.p
34506.02/5512.74	% SZS status Ended for HL402882+4.p
34513.48/5513.59	% SZS status Started for HL402886+4.p
34513.48/5513.59	% SZS status Theorem for HL402886+4.p
34513.48/5513.59	% SZS status Ended for HL402886+4.p
34514.18/5513.73	% SZS status Started for HL402882+5.p
34514.18/5513.73	% SZS status GaveUp for HL402882+5.p
34514.18/5513.73	% SZS status Ended for HL402882+5.p
34539.06/5516.83	% SZS status Started for HL402883+4.p
34539.06/5516.83	% SZS status GaveUp for HL402883+4.p
34539.06/5516.83	% SZS status Ended for HL402883+4.p
34554.17/5518.76	% SZS status Started for HL402883+5.p
34554.17/5518.76	% SZS status GaveUp for HL402883+5.p
34554.17/5518.76	% SZS status Ended for HL402883+5.p
34554.17/5518.78	% SZS status Started for HL402884+4.p
34554.17/5518.78	% SZS status GaveUp for HL402884+4.p
34554.17/5518.78	% SZS status Ended for HL402884+4.p
34557.02/5519.01	% SZS status Started for HL402884+5.p
34557.02/5519.01	% SZS status GaveUp for HL402884+5.p
34557.02/5519.01	% SZS status Ended for HL402884+5.p
34569.91/5520.64	% SZS status Started for HL402885+4.p
34569.91/5520.64	% SZS status GaveUp for HL402885+4.p
34569.91/5520.64	% SZS status Ended for HL402885+4.p
34571.06/5520.83	% SZS status Started for HL402885+5.p
34571.06/5520.83	% SZS status GaveUp for HL402885+5.p
34571.06/5520.83	% SZS status Ended for HL402885+5.p
34583.07/5522.36	% SZS status Started for HL402886+5.p
34583.07/5522.36	% SZS status GaveUp for HL402886+5.p
34583.07/5522.36	% SZS status Ended for HL402886+5.p
34584.55/5522.51	% SZS status Started for HL402887+4.p
34584.55/5522.51	% SZS status GaveUp for HL402887+4.p
34584.55/5522.51	% SZS status Ended for HL402887+4.p
34585.28/5522.85	% SZS status Started for HL402888+4.p
34585.28/5522.85	% SZS status Theorem for HL402888+4.p
34585.28/5522.85	% SZS status Ended for HL402888+4.p
34603.11/5524.89	% SZS status Started for HL402888+5.p
34603.11/5524.89	% SZS status Theorem for HL402888+5.p
34603.11/5524.89	% SZS status Ended for HL402888+5.p
34608.29/5525.54	% SZS status Started for HL402887+5.p
34608.29/5525.54	% SZS status GaveUp for HL402887+5.p
34608.29/5525.54	% SZS status Ended for HL402887+5.p
34625.64/5527.70	% SZS status Started for HL402889+4.p
34625.64/5527.70	% SZS status GaveUp for HL402889+4.p
34625.64/5527.70	% SZS status Ended for HL402889+4.p
34626.03/5527.81	% SZS status Started for HL402892+4.p
34626.03/5527.81	% SZS status Theorem for HL402892+4.p
34626.03/5527.81	% SZS status Ended for HL402892+4.p
34640.20/5529.55	% SZS status Started for HL402889+5.p
34640.20/5529.55	% SZS status GaveUp for HL402889+5.p
34640.20/5529.55	% SZS status Ended for HL402889+5.p
34641.72/5529.72	% SZS status Started for HL402890+4.p
34641.72/5529.72	% SZS status GaveUp for HL402890+4.p
34641.72/5529.72	% SZS status Ended for HL402890+4.p
34653.04/5531.13	% SZS status Started for HL402890+5.p
34653.04/5531.13	% SZS status GaveUp for HL402890+5.p
34653.04/5531.13	% SZS status Ended for HL402890+5.p
34655.66/5531.42	% SZS status Started for HL402891+4.p
34655.66/5531.42	% SZS status GaveUp for HL402891+4.p
34655.66/5531.42	% SZS status Ended for HL402891+4.p
34656.60/5531.60	% SZS status Started for HL402892+5.p
34656.60/5531.60	% SZS status Theorem for HL402892+5.p
34656.60/5531.60	% SZS status Ended for HL402892+5.p
34656.60/5531.67	% SZS status Started for HL402891+5.p
34656.60/5531.67	% SZS status GaveUp for HL402891+5.p
34656.60/5531.67	% SZS status Ended for HL402891+5.p
34678.50/5534.35	% SZS status Started for HL402896+4.p
34678.50/5534.35	% SZS status Theorem for HL402896+4.p
34678.50/5534.35	% SZS status Ended for HL402896+4.p
34695.92/5536.49	% SZS status Started for HL402894+4.p
34695.92/5536.49	% SZS status GaveUp for HL402894+4.p
34695.92/5536.49	% SZS status Ended for HL402894+4.p
34696.73/5536.60	% SZS status Started for HL402894+5.p
34696.73/5536.60	% SZS status GaveUp for HL402894+5.p
34696.73/5536.60	% SZS status Ended for HL402894+5.p
34721.27/5539.77	% SZS status Started for HL402895+4.p
34721.27/5539.77	% SZS status GaveUp for HL402895+4.p
34721.27/5539.77	% SZS status Ended for HL402895+4.p
34724.82/5540.19	% SZS status Started for HL402896+5.p
34724.82/5540.19	% SZS status GaveUp for HL402896+5.p
34724.82/5540.19	% SZS status Ended for HL402896+5.p
34725.85/5540.45	% SZS status Started for HL402897+5.p
34725.85/5540.45	% SZS status GaveUp for HL402897+5.p
34725.85/5540.45	% SZS status Ended for HL402897+5.p
34726.00/5540.54	% SZS status Started for HL402897+4.p
34726.00/5540.54	% SZS status GaveUp for HL402897+4.p
34726.00/5540.54	% SZS status Ended for HL402897+4.p
34747.89/5543.11	% SZS status Started for HL402898+4.p
34747.89/5543.11	% SZS status GaveUp for HL402898+4.p
34747.89/5543.11	% SZS status Ended for HL402898+4.p
34765.41/5545.25	% SZS status Started for HL402898+5.p
34765.41/5545.25	% SZS status GaveUp for HL402898+5.p
34765.41/5545.25	% SZS status Ended for HL402898+5.p
34766.05/5545.38	% SZS status Started for HL402899+4.p
34766.05/5545.38	% SZS status GaveUp for HL402899+4.p
34766.05/5545.38	% SZS status Ended for HL402899+4.p
34771.18/5546.07	% SZS status Started for HL402903+4.p
34771.18/5546.07	% SZS status Theorem for HL402903+4.p
34771.18/5546.07	% SZS status Ended for HL402903+4.p
34791.13/5548.50	% SZS status Started for HL402899+5.p
34791.13/5548.50	% SZS status GaveUp for HL402899+5.p
34791.13/5548.50	% SZS status Ended for HL402899+5.p
34794.57/5548.89	% SZS status Started for HL402901+4.p
34794.57/5548.89	% SZS status GaveUp for HL402901+4.p
34794.57/5548.89	% SZS status Ended for HL402901+4.p
34795.35/5549.18	% SZS status Started for HL402901+5.p
34795.35/5549.18	% SZS status GaveUp for HL402901+5.p
34795.35/5549.18	% SZS status Ended for HL402901+5.p
34798.84/5549.42	% SZS status Started for HL402902+4.p
34798.84/5549.42	% SZS status GaveUp for HL402902+4.p
34798.84/5549.42	% SZS status Ended for HL402902+4.p
34804.89/5550.31	% SZS status Started for HL402895+5.p
34804.89/5550.31	% SZS status GaveUp for HL402895+5.p
34804.89/5550.31	% SZS status Ended for HL402895+5.p
34813.86/5551.47	% SZS status Started for HL402903+5.p
34813.86/5551.47	% SZS status Theorem for HL402903+5.p
34813.86/5551.47	% SZS status Ended for HL402903+5.p
34817.86/5551.88	% SZS status Started for HL402902+5.p
34817.86/5551.88	% SZS status GaveUp for HL402902+5.p
34817.86/5551.88	% SZS status Ended for HL402902+5.p
34841.30/5554.83	% SZS status Started for HL402904+4.p
34841.30/5554.83	% SZS status GaveUp for HL402904+4.p
34841.30/5554.83	% SZS status Ended for HL402904+4.p
34859.90/5557.28	% SZS status Started for HL402904+5.p
34859.90/5557.28	% SZS status GaveUp for HL402904+5.p
34859.90/5557.28	% SZS status Ended for HL402904+5.p
34863.85/5557.77	% SZS status Started for HL402906+4.p
34863.85/5557.77	% SZS status GaveUp for HL402906+4.p
34863.85/5557.77	% SZS status Ended for HL402906+4.p
34866.72/5557.96	% SZS status Started for HL402906+5.p
34866.72/5557.96	% SZS status GaveUp for HL402906+5.p
34866.72/5557.96	% SZS status Ended for HL402906+5.p
34869.08/5558.31	% SZS status Started for HL402907+4.p
34869.08/5558.31	% SZS status GaveUp for HL402907+4.p
34869.08/5558.31	% SZS status Ended for HL402907+4.p
34875.28/5559.06	% SZS status Started for HL402907+5.p
34875.28/5559.06	% SZS status GaveUp for HL402907+5.p
34875.28/5559.06	% SZS status Ended for HL402907+5.p
34876.13/5559.13	% SZS status Started for HL402911+4.p
34876.13/5559.13	% SZS status Theorem for HL402911+4.p
34876.13/5559.13	% SZS status Ended for HL402911+4.p
34880.04/5559.66	% SZS status Started for HL402911+5.p
34880.04/5559.66	% SZS status Theorem for HL402911+5.p
34880.04/5559.66	% SZS status Ended for HL402911+5.p
34882.68/5560.29	% SZS status Started for HL402908+4.p
34882.68/5560.29	% SZS status GaveUp for HL402908+4.p
34882.68/5560.29	% SZS status Ended for HL402908+4.p
34887.40/5560.65	% SZS status Started for HL402908+5.p
34887.40/5560.65	% SZS status GaveUp for HL402908+5.p
34887.40/5560.65	% SZS status Ended for HL402908+5.p
34911.75/5563.67	% SZS status Started for HL402909+4.p
34911.75/5563.67	% SZS status GaveUp for HL402909+4.p
34911.75/5563.67	% SZS status Ended for HL402909+4.p
34931.03/5566.09	% SZS status Started for HL402909+5.p
34931.03/5566.09	% SZS status GaveUp for HL402909+5.p
34931.03/5566.09	% SZS status Ended for HL402909+5.p
34934.59/5566.59	% SZS status Started for HL402910+4.p
34934.59/5566.59	% SZS status GaveUp for HL402910+4.p
34934.59/5566.59	% SZS status Ended for HL402910+4.p
34935.77/5566.78	% SZS status Started for HL402910+5.p
34935.77/5566.78	% SZS status GaveUp for HL402910+5.p
34935.77/5566.78	% SZS status Ended for HL402910+5.p
34947.55/5568.13	% SZS status Started for HL402913+4.p
34947.55/5568.13	% SZS status GaveUp for HL402913+4.p
34947.55/5568.13	% SZS status Ended for HL402913+4.p
34948.10/5568.22	% SZS status Started for HL402913+5.p
34948.10/5568.22	% SZS status GaveUp for HL402913+5.p
34948.10/5568.22	% SZS status Ended for HL402913+5.p
34955.37/5569.16	% SZS status Started for HL402914+4.p
34955.37/5569.16	% SZS status GaveUp for HL402914+4.p
34955.37/5569.16	% SZS status Ended for HL402914+4.p
34959.11/5569.58	% SZS status Started for HL402914+5.p
34959.11/5569.58	% SZS status GaveUp for HL402914+5.p
34959.11/5569.58	% SZS status Ended for HL402914+5.p
34984.05/5572.72	% SZS status Started for HL402915+4.p
34984.05/5572.72	% SZS status GaveUp for HL402915+4.p
34984.05/5572.72	% SZS status Ended for HL402915+4.p
35004.31/5575.55	% SZS status Started for HL402918+4.p
35004.31/5575.55	% SZS status GaveUp for HL402918+4.p
35004.31/5575.55	% SZS status Ended for HL402918+4.p
35007.10/5575.68	% SZS status Started for HL402918+5.p
35007.10/5575.68	% SZS status GaveUp for HL402918+5.p
35007.10/5575.68	% SZS status Ended for HL402918+5.p
35017.37/5576.96	% SZS status Started for HL402919+4.p
35017.37/5576.96	% SZS status GaveUp for HL402919+4.p
35017.37/5576.96	% SZS status Ended for HL402919+4.p
35018.37/5577.10	% SZS status Started for HL402919+5.p
35018.37/5577.10	% SZS status GaveUp for HL402919+5.p
35018.37/5577.10	% SZS status Ended for HL402919+5.p
35025.18/5577.97	% SZS status Started for HL402920+4.p
35025.18/5577.97	% SZS status GaveUp for HL402920+4.p
35025.18/5577.97	% SZS status Ended for HL402920+4.p
35029.31/5578.46	% SZS status Started for HL402920+5.p
35029.31/5578.46	% SZS status GaveUp for HL402920+5.p
35029.31/5578.46	% SZS status Ended for HL402920+5.p
35053.86/5581.62	% SZS status Started for HL402921+4.p
35053.86/5581.62	% SZS status GaveUp for HL402921+4.p
35053.86/5581.62	% SZS status Ended for HL402921+4.p
35075.35/5584.35	% SZS status Started for HL402921+5.p
35075.35/5584.35	% SZS status GaveUp for HL402921+5.p
35075.35/5584.35	% SZS status Ended for HL402921+5.p
35078.98/5584.72	% SZS status Started for HL402922+4.p
35078.98/5584.72	% SZS status GaveUp for HL402922+4.p
35078.98/5584.72	% SZS status Ended for HL402922+4.p
35087.53/5585.76	% SZS status Started for HL402922+5.p
35087.53/5585.76	% SZS status GaveUp for HL402922+5.p
35087.53/5585.76	% SZS status Ended for HL402922+5.p
35088.51/5585.93	% SZS status Started for HL402924+4.p
35088.51/5585.93	% SZS status GaveUp for HL402924+4.p
35088.51/5585.93	% SZS status Ended for HL402924+4.p
35098.46/5587.16	% SZS status Started for HL402924+5.p
35098.46/5587.16	% SZS status GaveUp for HL402924+5.p
35098.46/5587.16	% SZS status Ended for HL402924+5.p
35099.52/5587.36	% SZS status Started for HL402925+4.p
35099.52/5587.36	% SZS status GaveUp for HL402925+4.p
35099.52/5587.36	% SZS status Ended for HL402925+4.p
35106.19/5588.18	% SZS status Started for HL402915+5.p
35106.19/5588.18	% SZS status GaveUp for HL402915+5.p
35106.19/5588.18	eprover: CPU time limit exceeded, terminating
35106.19/5588.18	% SZS status Ended for HL402915+5.p
35126.64/5590.71	% SZS status Started for HL402925+5.p
35126.64/5590.71	% SZS status GaveUp for HL402925+5.p
35126.64/5590.71	% SZS status Ended for HL402925+5.p
35151.15/5593.76	% SZS status Started for HL402926+4.p
35151.15/5593.76	% SZS status GaveUp for HL402926+4.p
35151.15/5593.76	% SZS status Ended for HL402926+4.p
35151.15/5593.79	% SZS status Started for HL402926+5.p
35151.15/5593.79	% SZS status GaveUp for HL402926+5.p
35151.15/5593.79	% SZS status Ended for HL402926+5.p
35160.90/5594.99	% SZS status Started for HL402927+5.p
35160.90/5594.99	% SZS status GaveUp for HL402927+5.p
35160.90/5594.99	% SZS status Ended for HL402927+5.p
35160.90/5595.02	% SZS status Started for HL402927+4.p
35160.90/5595.02	% SZS status GaveUp for HL402927+4.p
35160.90/5595.02	% SZS status Ended for HL402927+4.p
35171.57/5596.38	% SZS status Started for HL402929+4.p
35171.57/5596.38	% SZS status GaveUp for HL402929+4.p
35171.57/5596.38	% SZS status Ended for HL402929+4.p
35171.91/5596.42	% SZS status Started for HL402929+5.p
35171.91/5596.42	% SZS status GaveUp for HL402929+5.p
35171.91/5596.42	% SZS status Ended for HL402929+5.p
35182.17/5597.72	% SZS status Started for HL402930+4.p
35182.17/5597.72	% SZS status GaveUp for HL402930+4.p
35182.17/5597.72	% SZS status Ended for HL402930+4.p
35198.40/5599.76	% SZS status Started for HL402930+5.p
35198.40/5599.76	% SZS status GaveUp for HL402930+5.p
35198.40/5599.76	% SZS status Ended for HL402930+5.p
35223.16/5602.81	% SZS status Started for HL402932+5.p
35223.16/5602.81	% SZS status GaveUp for HL402932+5.p
35223.16/5602.81	% SZS status Ended for HL402932+5.p
35224.44/5603.04	% SZS status Started for HL402932+4.p
35224.44/5603.04	% SZS status GaveUp for HL402932+4.p
35224.44/5603.04	% SZS status Ended for HL402932+4.p
35230.18/5603.81	% SZS status Started for HL402933+5.p
35230.18/5603.81	% SZS status GaveUp for HL402933+5.p
35230.18/5603.81	% SZS status Ended for HL402933+5.p
35233.93/5604.26	% SZS status Started for HL402933+4.p
35233.93/5604.26	% SZS status GaveUp for HL402933+4.p
35233.93/5604.26	% SZS status Ended for HL402933+4.p
35243.18/5605.56	% SZS status Started for HL402934+4.p
35243.18/5605.56	% SZS status GaveUp for HL402934+4.p
35243.18/5605.56	% SZS status Ended for HL402934+4.p
35247.48/5605.88	% SZS status Started for HL402934+5.p
35247.48/5605.88	% SZS status GaveUp for HL402934+5.p
35247.48/5605.88	% SZS status Ended for HL402934+5.p
35255.97/5606.97	% SZS status Started for HL402935+4.p
35255.97/5606.97	% SZS status GaveUp for HL402935+4.p
35255.97/5606.97	% SZS status Ended for HL402935+4.p
35267.17/5608.44	% SZS status Started for HL402939+4.p
35267.17/5608.44	% SZS status Theorem for HL402939+4.p
35267.17/5608.44	% SZS status Ended for HL402939+4.p
35268.50/5608.54	% SZS status Started for HL402935+5.p
35268.50/5608.54	% SZS status GaveUp for HL402935+5.p
35268.50/5608.54	% SZS status Ended for HL402935+5.p
35294.18/5611.81	% SZS status Started for HL402936+5.p
35294.18/5611.81	% SZS status GaveUp for HL402936+5.p
35294.18/5611.81	% SZS status Ended for HL402936+5.p
35296.50/5612.18	% SZS status Started for HL402936+4.p
35296.50/5612.18	% SZS status GaveUp for HL402936+4.p
35296.50/5612.18	% SZS status Ended for HL402936+4.p
35304.10/5613.05	% SZS status Started for HL402937+5.p
35304.10/5613.05	% SZS status GaveUp for HL402937+5.p
35304.10/5613.05	% SZS status Ended for HL402937+5.p
35304.73/5613.11	% SZS status Started for HL402937+4.p
35304.73/5613.11	% SZS status GaveUp for HL402937+4.p
35304.73/5613.11	% SZS status Ended for HL402937+4.p
35309.12/5613.65	% SZS status Started for HL402939+5.p
35309.12/5613.65	% SZS status Theorem for HL402939+5.p
35309.12/5613.65	% SZS status Ended for HL402939+5.p
35318.41/5614.92	% SZS status Started for HL402938+5.p
35318.41/5614.92	% SZS status GaveUp for HL402938+5.p
35318.41/5614.92	% SZS status Ended for HL402938+5.p
35321.89/5615.27	% SZS status Started for HL402938+4.p
35321.89/5615.27	% SZS status GaveUp for HL402938+4.p
35321.89/5615.27	% SZS status Ended for HL402938+4.p
35341.24/5617.81	% SZS status Started for HL402940+4.p
35341.24/5617.81	% SZS status GaveUp for HL402940+4.p
35341.24/5617.81	% SZS status Ended for HL402940+4.p
35366.37/5620.88	% SZS status Started for HL402940+5.p
35366.37/5620.88	% SZS status GaveUp for HL402940+5.p
35366.37/5620.88	% SZS status Ended for HL402940+5.p
35371.91/5621.59	% SZS status Started for HL402941+4.p
35371.91/5621.59	% SZS status GaveUp for HL402941+4.p
35371.91/5621.59	% SZS status Ended for HL402941+4.p
35375.51/5622.03	% SZS status Started for HL402941+5.p
35375.51/5622.03	% SZS status GaveUp for HL402941+5.p
35375.51/5622.03	% SZS status Ended for HL402941+5.p
35378.57/5622.44	% SZS status Started for HL402942+4.p
35378.57/5622.44	% SZS status GaveUp for HL402942+4.p
35378.57/5622.44	% SZS status Ended for HL402942+4.p
35379.69/5622.55	% SZS status Started for HL402942+5.p
35379.69/5622.55	% SZS status GaveUp for HL402942+5.p
35379.69/5622.55	% SZS status Ended for HL402942+5.p
35389.49/5623.76	% SZS status Started for HL402943+4.p
35389.49/5623.76	% SZS status GaveUp for HL402943+4.p
35389.49/5623.76	% SZS status Ended for HL402943+4.p
35389.49/5623.80	% SZS status Started for HL402943+5.p
35389.49/5623.80	% SZS status GaveUp for HL402943+5.p
35389.49/5623.80	% SZS status Ended for HL402943+5.p
35414.03/5626.88	% SZS status Started for HL402946+4.p
35414.03/5626.88	% SZS status GaveUp for HL402946+4.p
35414.03/5626.88	% SZS status Ended for HL402946+4.p
35434.23/5629.53	% SZS status Started for HL402946+5.p
35434.23/5629.53	% SZS status GaveUp for HL402946+5.p
35434.23/5629.53	% SZS status Ended for HL402946+5.p
35441.97/5630.61	% SZS status Started for HL402947+4.p
35441.97/5630.61	% SZS status GaveUp for HL402947+4.p
35441.97/5630.61	% SZS status Ended for HL402947+4.p
35442.69/5630.71	% SZS status Started for HL402947+5.p
35442.69/5630.71	% SZS status GaveUp for HL402947+5.p
35442.69/5630.71	% SZS status Ended for HL402947+5.p
35446.91/5631.30	% SZS status Started for HL402948+5.p
35446.91/5631.30	% SZS status GaveUp for HL402948+5.p
35446.91/5631.30	% SZS status Ended for HL402948+5.p
35449.91/5631.71	% SZS status Started for HL402953+4.p
35449.91/5631.71	% SZS status Theorem for HL402953+4.p
35449.91/5631.71	% SZS status Ended for HL402953+4.p
35452.89/5632.16	% SZS status Started for HL402948+4.p
35452.89/5632.16	% SZS status GaveUp for HL402948+4.p
35452.89/5632.16	% SZS status Ended for HL402948+4.p
35459.94/5632.98	% SZS status Started for HL402949+5.p
35459.94/5632.98	% SZS status GaveUp for HL402949+5.p
35459.94/5632.98	% SZS status Ended for HL402949+5.p
35462.74/5633.34	% SZS status Started for HL402949+4.p
35462.74/5633.34	% SZS status GaveUp for HL402949+4.p
35462.74/5633.34	% SZS status Ended for HL402949+4.p
35483.38/5636.27	% SZS status Started for HL402950+4.p
35483.38/5636.27	% SZS status GaveUp for HL402950+4.p
35483.38/5636.27	% SZS status Ended for HL402950+4.p
35501.91/5638.65	% SZS status Started for HL402950+5.p
35501.91/5638.65	% SZS status GaveUp for HL402950+5.p
35501.91/5638.65	% SZS status Ended for HL402950+5.p
35512.46/5640.09	% SZS status Started for HL402953+5.p
35512.46/5640.09	% SZS status GaveUp for HL402953+5.p
35512.46/5640.09	% SZS status Ended for HL402953+5.p
35520.95/5641.20	% SZS status Started for HL402954+4.p
35520.95/5641.20	% SZS status GaveUp for HL402954+4.p
35520.95/5641.20	% SZS status Ended for HL402954+4.p
35522.12/5641.40	% SZS status Started for HL402954+5.p
35522.12/5641.40	% SZS status GaveUp for HL402954+5.p
35522.12/5641.40	% SZS status Ended for HL402954+5.p
35528.23/5642.22	% SZS status Started for HL402957+4.p
35528.23/5642.22	% SZS status GaveUp for HL402957+4.p
35528.23/5642.22	% SZS status Ended for HL402957+4.p
35531.54/5642.68	% SZS status Started for HL402957+5.p
35531.54/5642.68	% SZS status GaveUp for HL402957+5.p
35531.54/5642.68	% SZS status Ended for HL402957+5.p
35532.08/5642.70	% SZS status Started for HL402958+4.p
35532.08/5642.70	% SZS status GaveUp for HL402958+4.p
35532.08/5642.70	% SZS status Ended for HL402958+4.p
35557.11/5646.10	% SZS status Started for HL402958+5.p
35557.11/5646.10	% SZS status GaveUp for HL402958+5.p
35557.11/5646.10	% SZS status Ended for HL402958+5.p
35571.47/5648.15	% SZS status Started for HL402959+4.p
35571.47/5648.15	% SZS status GaveUp for HL402959+4.p
35571.47/5648.15	% SZS status Ended for HL402959+4.p
35586.38/5650.10	% SZS status Started for HL402959+5.p
35586.38/5650.10	% SZS status GaveUp for HL402959+5.p
35586.38/5650.10	% SZS status Ended for HL402959+5.p
35591.13/5650.75	% SZS status Started for HL402960+5.p
35591.13/5650.75	% SZS status GaveUp for HL402960+5.p
35591.13/5650.75	% SZS status Ended for HL402960+5.p
35596.73/5651.51	% SZS status Started for HL402960+4.p
35596.73/5651.51	% SZS status GaveUp for HL402960+4.p
35596.73/5651.51	% SZS status Ended for HL402960+4.p
35600.20/5651.98	% SZS status Started for HL402962+4.p
35600.20/5651.98	% SZS status GaveUp for HL402962+4.p
35600.20/5651.98	% SZS status Ended for HL402962+4.p
35600.20/5651.99	% SZS status Started for HL402961+4.p
35600.20/5651.99	% SZS status GaveUp for HL402961+4.p
35600.20/5651.99	% SZS status Ended for HL402961+4.p
35604.86/5652.58	% SZS status Started for HL402961+5.p
35604.86/5652.58	% SZS status GaveUp for HL402961+5.p
35604.86/5652.58	% SZS status Ended for HL402961+5.p
35628.16/5655.61	% SZS status Started for HL402962+5.p
35628.16/5655.61	% SZS status GaveUp for HL402962+5.p
35628.16/5655.61	% SZS status Ended for HL402962+5.p
35644.98/5657.81	% SZS status Started for HL402963+4.p
35644.98/5657.81	% SZS status GaveUp for HL402963+4.p
35644.98/5657.81	% SZS status Ended for HL402963+4.p
35646.11/5657.97	% SZS status Started for HL402966+4.p
35646.11/5657.97	% SZS status Theorem for HL402966+4.p
35646.11/5657.97	% SZS status Ended for HL402966+4.p
35657.16/5659.38	% SZS status Started for HL402963+5.p
35657.16/5659.38	% SZS status GaveUp for HL402963+5.p
35657.16/5659.38	% SZS status Ended for HL402963+5.p
35659.50/5659.89	% SZS status Started for HL402964+4.p
35659.50/5659.89	% SZS status GaveUp for HL402964+4.p
35659.50/5659.89	% SZS status Ended for HL402964+4.p
35674.32/5660.94	% SZS status Started for HL402964+5.p
35674.32/5660.94	% SZS status GaveUp for HL402964+5.p
35674.32/5660.94	% SZS status Ended for HL402964+5.p
35680.17/5661.58	% SZS status Started for HL402965+5.p
35680.17/5661.58	% SZS status GaveUp for HL402965+5.p
35680.17/5661.58	% SZS status Ended for HL402965+5.p
35681.60/5661.67	% SZS status Started for HL402965+4.p
35681.60/5661.67	% SZS status GaveUp for HL402965+4.p
35681.60/5661.67	% SZS status Ended for HL402965+4.p
35708.32/5665.25	% SZS status Started for HL402966+5.p
35708.32/5665.25	% SZS status GaveUp for HL402966+5.p
35708.32/5665.25	% SZS status Ended for HL402966+5.p
35721.20/5667.01	% SZS status Started for HL402967+4.p
35721.20/5667.01	% SZS status GaveUp for HL402967+4.p
35721.20/5667.01	% SZS status Ended for HL402967+4.p
35721.70/5667.21	% SZS status Started for HL402967+5.p
35721.70/5667.21	% SZS status GaveUp for HL402967+5.p
35721.70/5667.21	% SZS status Ended for HL402967+5.p
35734.32/5668.69	% SZS status Started for HL402968+4.p
35734.32/5668.69	% SZS status GaveUp for HL402968+4.p
35734.32/5668.69	% SZS status Ended for HL402968+4.p
35742.18/5669.68	% SZS status Started for HL402968+5.p
35742.18/5669.68	% SZS status GaveUp for HL402968+5.p
35742.18/5669.68	% SZS status Ended for HL402968+5.p
35750.30/5670.92	% SZS status Started for HL402969+5.p
35750.30/5670.92	% SZS status GaveUp for HL402969+5.p
35750.30/5670.92	% SZS status Ended for HL402969+5.p
35752.58/5671.08	% SZS status Started for HL402970+4.p
35752.58/5671.08	% SZS status GaveUp for HL402970+4.p
35752.58/5671.08	% SZS status Ended for HL402970+4.p
35754.30/5671.35	% SZS status Started for HL402969+4.p
35754.30/5671.35	% SZS status GaveUp for HL402969+4.p
35754.30/5671.35	% SZS status Ended for HL402969+4.p
35778.66/5674.37	% SZS status Started for HL402970+5.p
35778.66/5674.37	% SZS status GaveUp for HL402970+5.p
35778.66/5674.37	% SZS status Ended for HL402970+5.p
35791.96/5676.03	% SZS status Started for HL402971+5.p
35791.96/5676.03	% SZS status GaveUp for HL402971+5.p
35791.96/5676.03	% SZS status Ended for HL402971+5.p
35792.60/5676.22	% SZS status Started for HL402971+4.p
35792.60/5676.22	% SZS status GaveUp for HL402971+4.p
35792.60/5676.22	% SZS status Ended for HL402971+4.p
35804.48/5677.59	% SZS status Started for HL402972+4.p
35804.48/5677.59	% SZS status GaveUp for HL402972+4.p
35804.48/5677.59	% SZS status Ended for HL402972+4.p
35812.49/5678.54	% SZS status Started for HL402972+5.p
35812.49/5678.54	% SZS status GaveUp for HL402972+5.p
35812.49/5678.54	% SZS status Ended for HL402972+5.p
35822.71/5679.84	% SZS status Started for HL402973+4.p
35822.71/5679.84	% SZS status GaveUp for HL402973+4.p
35822.71/5679.84	% SZS status Ended for HL402973+4.p
35823.06/5679.91	% SZS status Started for HL402973+5.p
35823.06/5679.91	% SZS status GaveUp for HL402973+5.p
35823.06/5679.91	% SZS status Ended for HL402973+5.p
35826.87/5680.38	% SZS status Started for HL402974+4.p
35826.87/5680.38	% SZS status GaveUp for HL402974+4.p
35826.87/5680.38	% SZS status Ended for HL402974+4.p
35849.27/5683.16	% SZS status Started for HL402974+5.p
35849.27/5683.16	% SZS status GaveUp for HL402974+5.p
35849.27/5683.16	% SZS status Ended for HL402974+5.p
35862.25/5684.92	% SZS status Started for HL402976+4.p
35862.25/5684.92	% SZS status GaveUp for HL402976+4.p
35862.25/5684.92	% SZS status Ended for HL402976+4.p
35862.97/5685.06	% SZS status Started for HL402976+5.p
35862.97/5685.06	% SZS status GaveUp for HL402976+5.p
35862.97/5685.06	% SZS status Ended for HL402976+5.p
35876.36/5686.63	% SZS status Started for HL402977+4.p
35876.36/5686.63	% SZS status GaveUp for HL402977+4.p
35876.36/5686.63	% SZS status Ended for HL402977+4.p
35882.82/5687.38	% SZS status Started for HL402977+5.p
35882.82/5687.38	% SZS status GaveUp for HL402977+5.p
35882.82/5687.38	% SZS status Ended for HL402977+5.p
35891.13/5688.45	% SZS status Started for HL402978+5.p
35891.13/5688.45	% SZS status GaveUp for HL402978+5.p
35891.13/5688.45	% SZS status Ended for HL402978+5.p
35892.62/5688.66	% SZS status Started for HL402978+4.p
35892.62/5688.66	% SZS status GaveUp for HL402978+4.p
35892.62/5688.66	% SZS status Ended for HL402978+4.p
35898.57/5689.37	% SZS status Started for HL402979+4.p
35898.57/5689.37	% SZS status GaveUp for HL402979+4.p
35898.57/5689.37	% SZS status Ended for HL402979+4.p
35918.17/5691.93	% SZS status Started for HL402979+5.p
35918.17/5691.93	% SZS status GaveUp for HL402979+5.p
35918.17/5691.93	% SZS status Ended for HL402979+5.p
35932.93/5693.67	% SZS status Started for HL402980+5.p
35932.93/5693.67	% SZS status GaveUp for HL402980+5.p
35932.93/5693.67	% SZS status Ended for HL402980+5.p
35933.50/5693.76	% SZS status Started for HL402980+4.p
35933.50/5693.76	% SZS status GaveUp for HL402980+4.p
35933.50/5693.76	% SZS status Ended for HL402980+4.p
35947.10/5695.57	% SZS status Started for HL402981+4.p
35947.10/5695.57	% SZS status GaveUp for HL402981+4.p
35947.10/5695.57	% SZS status Ended for HL402981+4.p
35952.98/5696.20	% SZS status Started for HL402981+5.p
35952.98/5696.20	% SZS status GaveUp for HL402981+5.p
35952.98/5696.20	% SZS status Ended for HL402981+5.p
35962.60/5697.42	% SZS status Started for HL402982+5.p
35962.60/5697.42	% SZS status GaveUp for HL402982+5.p
35962.60/5697.42	% SZS status Ended for HL402982+5.p
35962.97/5697.44	% SZS status Started for HL402982+4.p
35962.97/5697.44	% SZS status GaveUp for HL402982+4.p
35962.97/5697.44	% SZS status Ended for HL402982+4.p
35970.09/5698.33	% SZS status Started for HL402983+4.p
35970.09/5698.33	% SZS status GaveUp for HL402983+4.p
35970.09/5698.33	% SZS status Ended for HL402983+4.p
35988.27/5700.72	% SZS status Started for HL402983+5.p
35988.27/5700.72	% SZS status GaveUp for HL402983+5.p
35988.27/5700.72	% SZS status Ended for HL402983+5.p
36001.96/5702.53	% SZS status Started for HL402984+4.p
36001.96/5702.53	% SZS status GaveUp for HL402984+4.p
36001.96/5702.53	% SZS status Ended for HL402984+4.p
36001.96/5702.57	% SZS status Started for HL402984+5.p
36001.96/5702.57	% SZS status GaveUp for HL402984+5.p
36001.96/5702.57	% SZS status Ended for HL402984+5.p
36032.11/5706.16	% SZS status Started for HL402985+4.p
36032.11/5706.16	% SZS status GaveUp for HL402985+4.p
36032.11/5706.16	% SZS status Ended for HL402985+4.p
36032.78/5706.26	% SZS status Started for HL402987+5.p
36032.78/5706.26	% SZS status GaveUp for HL402987+5.p
36032.78/5706.26	% SZS status Ended for HL402987+5.p
36033.11/5706.30	% SZS status Started for HL402987+4.p
36033.11/5706.30	% SZS status GaveUp for HL402987+4.p
36033.11/5706.30	% SZS status Ended for HL402987+4.p
36039.14/5707.22	% SZS status Started for HL402988+4.p
36039.14/5707.22	% SZS status GaveUp for HL402988+4.p
36039.14/5707.22	% SZS status Ended for HL402988+4.p
36054.42/5708.97	% SZS status Started for HL402992+4.p
36054.42/5708.97	% SZS status Theorem for HL402992+4.p
36054.42/5708.97	% SZS status Ended for HL402992+4.p
36059.18/5709.57	% SZS status Started for HL402988+5.p
36059.18/5709.57	% SZS status GaveUp for HL402988+5.p
36059.18/5709.57	% SZS status Ended for HL402988+5.p
36073.60/5711.35	% SZS status Started for HL402989+5.p
36073.60/5711.35	% SZS status GaveUp for HL402989+5.p
36073.60/5711.35	% SZS status Ended for HL402989+5.p
36073.60/5711.42	% SZS status Started for HL402989+4.p
36073.60/5711.42	% SZS status GaveUp for HL402989+4.p
36073.60/5711.42	% SZS status Ended for HL402989+4.p
36102.64/5715.01	% SZS status Started for HL402990+4.p
36102.64/5715.01	% SZS status GaveUp for HL402990+4.p
36102.64/5715.01	% SZS status Ended for HL402990+4.p
36102.64/5715.02	% SZS status Started for HL402990+5.p
36102.64/5715.02	% SZS status GaveUp for HL402990+5.p
36102.64/5715.02	% SZS status Ended for HL402990+5.p
36111.12/5716.08	% SZS status Started for HL402992+5.p
36111.12/5716.08	% SZS status GaveUp for HL402992+5.p
36111.12/5716.08	% SZS status Ended for HL402992+5.p
36119.53/5717.12	% SZS status Started for HL402985+5.p
36119.53/5717.12	% SZS status GaveUp for HL402985+5.p
36119.53/5717.12	% SZS status Ended for HL402985+5.p
36125.42/5717.99	% SZS status Started for HL402993+4.p
36125.42/5717.99	% SZS status GaveUp for HL402993+4.p
36125.42/5717.99	% SZS status Ended for HL402993+4.p
36129.01/5718.35	% SZS status Started for HL402993+5.p
36129.01/5718.35	% SZS status GaveUp for HL402993+5.p
36129.01/5718.35	% SZS status Ended for HL402993+5.p
36144.29/5720.26	% SZS status Started for HL402994+5.p
36144.29/5720.26	% SZS status GaveUp for HL402994+5.p
36144.29/5720.26	% SZS status Ended for HL402994+5.p
36144.29/5720.27	% SZS status Started for HL402994+4.p
36144.29/5720.27	% SZS status GaveUp for HL402994+4.p
36144.29/5720.27	% SZS status Ended for HL402994+4.p
36172.93/5723.84	% SZS status Started for HL402995+5.p
36172.93/5723.84	% SZS status GaveUp for HL402995+5.p
36172.93/5723.84	% SZS status Ended for HL402995+5.p
36174.02/5724.08	% SZS status Started for HL402995+4.p
36174.02/5724.08	% SZS status GaveUp for HL402995+4.p
36174.02/5724.08	% SZS status Ended for HL402995+4.p
36182.82/5725.21	% SZS status Started for HL402996+4.p
36182.82/5725.21	% SZS status GaveUp for HL402996+4.p
36182.82/5725.21	% SZS status Ended for HL402996+4.p
36189.59/5725.96	% SZS status Started for HL402996+5.p
36189.59/5725.96	% SZS status GaveUp for HL402996+5.p
36189.59/5725.96	% SZS status Ended for HL402996+5.p
36197.31/5726.92	% SZS status Started for HL402997+4.p
36197.31/5726.92	% SZS status GaveUp for HL402997+4.p
36197.31/5726.92	% SZS status Ended for HL402997+4.p
36198.15/5727.10	% SZS status Started for HL402997+5.p
36198.15/5727.10	% SZS status GaveUp for HL402997+5.p
36198.15/5727.10	% SZS status Ended for HL402997+5.p
36214.37/5729.08	% SZS status Started for HL402999+5.p
36214.37/5729.08	% SZS status GaveUp for HL402999+5.p
36214.37/5729.08	% SZS status Ended for HL402999+5.p
36214.37/5729.09	% SZS status Started for HL402999+4.p
36214.37/5729.09	% SZS status GaveUp for HL402999+4.p
36214.37/5729.09	% SZS status Ended for HL402999+4.p
36243.24/5732.71	% SZS status Started for HL403000+4.p
36243.24/5732.71	% SZS status GaveUp for HL403000+4.p
36243.24/5732.71	% SZS status Ended for HL403000+4.p
36243.77/5732.87	% SZS status Started for HL403000+5.p
36243.77/5732.87	% SZS status GaveUp for HL403000+5.p
36243.77/5732.87	% SZS status Ended for HL403000+5.p
36254.86/5734.16	% SZS status Started for HL403001+4.p
36254.86/5734.16	% SZS status GaveUp for HL403001+4.p
36254.86/5734.16	% SZS status Ended for HL403001+4.p
36256.99/5734.51	% SZS status Started for HL403001+5.p
36256.99/5734.51	% SZS status GaveUp for HL403001+5.p
36256.99/5734.51	% SZS status Ended for HL403001+5.p
36267.82/5735.77	% SZS status Started for HL403002+5.p
36267.82/5735.77	% SZS status GaveUp for HL403002+5.p
36267.82/5735.77	% SZS status Ended for HL403002+5.p
36267.82/5735.82	% SZS status Started for HL403002+4.p
36267.82/5735.82	% SZS status GaveUp for HL403002+4.p
36267.82/5735.82	% SZS status Ended for HL403002+4.p
36282.19/5737.65	% SZS status Started for HL403003+5.p
36282.19/5737.65	% SZS status GaveUp for HL403003+5.p
36282.19/5737.65	% SZS status Ended for HL403003+5.p
36285.65/5738.03	% SZS status Started for HL403003+4.p
36285.65/5738.03	% SZS status GaveUp for HL403003+4.p
36285.65/5738.03	% SZS status Ended for HL403003+4.p
36316.06/5741.88	% SZS status Started for HL403005+5.p
36316.06/5741.88	% SZS status GaveUp for HL403005+5.p
36316.06/5741.88	% SZS status Ended for HL403005+5.p
36316.84/5741.98	% SZS status Started for HL403005+4.p
36316.84/5741.98	% SZS status GaveUp for HL403005+4.p
36316.84/5741.98	% SZS status Ended for HL403005+4.p
36326.24/5743.15	% SZS status Started for HL403006+4.p
36326.24/5743.15	% SZS status GaveUp for HL403006+4.p
36326.24/5743.15	% SZS status Ended for HL403006+4.p
36328.31/5743.49	% SZS status Started for HL403006+5.p
36328.31/5743.49	% SZS status GaveUp for HL403006+5.p
36328.31/5743.49	% SZS status Ended for HL403006+5.p
36337.66/5744.63	% SZS status Started for HL403007+5.p
36337.66/5744.63	% SZS status GaveUp for HL403007+5.p
36337.66/5744.63	% SZS status Ended for HL403007+5.p
36338.95/5744.75	% SZS status Started for HL403007+4.p
36338.95/5744.75	% SZS status GaveUp for HL403007+4.p
36338.95/5744.75	% SZS status Ended for HL403007+4.p
36353.74/5746.63	% SZS status Started for HL403008+5.p
36353.74/5746.63	% SZS status GaveUp for HL403008+5.p
36353.74/5746.63	% SZS status Ended for HL403008+5.p
36354.24/5746.71	% SZS status Started for HL403008+4.p
36354.24/5746.71	% SZS status GaveUp for HL403008+4.p
36354.24/5746.71	% SZS status Ended for HL403008+4.p
36385.49/5750.80	% SZS status Started for HL403009+4.p
36385.49/5750.80	% SZS status GaveUp for HL403009+4.p
36385.49/5750.80	% SZS status Ended for HL403009+4.p
36385.73/5750.90	% SZS status Started for HL403009+5.p
36385.73/5750.90	% SZS status GaveUp for HL403009+5.p
36385.73/5750.90	% SZS status Ended for HL403009+5.p
36395.14/5752.02	% SZS status Started for HL403010+4.p
36395.14/5752.02	% SZS status GaveUp for HL403010+4.p
36395.14/5752.02	% SZS status Ended for HL403010+4.p
36400.06/5752.49	% SZS status Started for HL403010+5.p
36400.06/5752.49	% SZS status GaveUp for HL403010+5.p
36400.06/5752.49	% SZS status Ended for HL403010+5.p
36409.01/5753.63	% SZS status Started for HL403011+4.p
36409.01/5753.63	% SZS status GaveUp for HL403011+4.p
36409.01/5753.63	% SZS status Ended for HL403011+4.p
36409.01/5753.63	% SZS status Started for HL403011+5.p
36409.01/5753.63	% SZS status GaveUp for HL403011+5.p
36409.01/5753.63	% SZS status Ended for HL403011+5.p
36423.85/5755.54	% SZS status Started for HL403012+5.p
36423.85/5755.54	% SZS status GaveUp for HL403012+5.p
36423.85/5755.54	% SZS status Ended for HL403012+5.p
36425.79/5755.74	% SZS status Started for HL403012+4.p
36425.79/5755.74	% SZS status GaveUp for HL403012+4.p
36425.79/5755.74	% SZS status Ended for HL403012+4.p
36455.16/5759.57	% SZS status Started for HL403013+4.p
36455.16/5759.57	% SZS status GaveUp for HL403013+4.p
36455.16/5759.57	% SZS status Ended for HL403013+4.p
36455.46/5759.63	% SZS status Started for HL403013+5.p
36455.46/5759.63	% SZS status GaveUp for HL403013+5.p
36455.46/5759.63	% SZS status Ended for HL403013+5.p
36466.09/5760.82	% SZS status Started for HL403014+4.p
36466.09/5760.82	% SZS status GaveUp for HL403014+4.p
36466.09/5760.82	% SZS status Ended for HL403014+4.p
36468.18/5761.12	% SZS status Started for HL403014+5.p
36468.18/5761.12	% SZS status GaveUp for HL403014+5.p
36468.18/5761.12	% SZS status Ended for HL403014+5.p
36478.93/5762.49	% SZS status Started for HL403015+4.p
36478.93/5762.49	% SZS status GaveUp for HL403015+4.p
36478.93/5762.49	% SZS status Ended for HL403015+4.p
36479.48/5762.73	% SZS status Started for HL403015+5.p
36479.48/5762.73	% SZS status GaveUp for HL403015+5.p
36479.48/5762.73	% SZS status Ended for HL403015+5.p
36494.61/5764.55	% SZS status Started for HL403016+5.p
36494.61/5764.55	% SZS status GaveUp for HL403016+5.p
36494.61/5764.55	% SZS status Ended for HL403016+5.p
36496.32/5764.62	% SZS status Started for HL403016+4.p
36496.32/5764.62	% SZS status GaveUp for HL403016+4.p
36496.32/5764.62	% SZS status Ended for HL403016+4.p
36522.91/5768.18	% SZS status Started for HL403017+5.p
36522.91/5768.18	% SZS status GaveUp for HL403017+5.p
36522.91/5768.18	% SZS status Ended for HL403017+5.p
36523.72/5768.35	% SZS status Started for HL403017+4.p
36523.72/5768.35	% SZS status GaveUp for HL403017+4.p
36523.72/5768.35	% SZS status Ended for HL403017+4.p
36536.88/5769.73	% SZS status Started for HL403019+4.p
36536.88/5769.73	% SZS status GaveUp for HL403019+4.p
36536.88/5769.73	% SZS status Ended for HL403019+4.p
36537.49/5769.89	% SZS status Started for HL403019+5.p
36537.49/5769.89	% SZS status GaveUp for HL403019+5.p
36537.49/5769.89	% SZS status Ended for HL403019+5.p
36548.82/5771.34	% SZS status Started for HL403020+4.p
36548.82/5771.34	% SZS status GaveUp for HL403020+4.p
36548.82/5771.34	% SZS status Ended for HL403020+4.p
36552.08/5771.76	% SZS status Started for HL403020+5.p
36552.08/5771.76	% SZS status GaveUp for HL403020+5.p
36552.08/5771.76	% SZS status Ended for HL403020+5.p
36565.37/5773.32	% SZS status Started for HL403021+5.p
36565.37/5773.32	% SZS status GaveUp for HL403021+5.p
36565.37/5773.32	% SZS status Ended for HL403021+5.p
36565.53/5773.39	% SZS status Started for HL403021+4.p
36565.53/5773.39	% SZS status GaveUp for HL403021+4.p
36565.53/5773.39	% SZS status Ended for HL403021+4.p
36595.54/5777.13	% SZS status Started for HL403022+5.p
36595.54/5777.13	% SZS status GaveUp for HL403022+5.p
36595.54/5777.13	% SZS status Ended for HL403022+5.p
36595.98/5777.23	% SZS status Started for HL403022+4.p
36595.98/5777.23	% SZS status GaveUp for HL403022+4.p
36595.98/5777.23	% SZS status Ended for HL403022+4.p
36607.40/5778.61	% SZS status Started for HL403023+4.p
36607.40/5778.61	% SZS status GaveUp for HL403023+4.p
36607.40/5778.61	% SZS status Ended for HL403023+4.p
36608.51/5778.80	% SZS status Started for HL403023+5.p
36608.51/5778.80	% SZS status GaveUp for HL403023+5.p
36608.51/5778.80	% SZS status Ended for HL403023+5.p
36619.29/5780.22	% SZS status Started for HL403024+4.p
36619.29/5780.22	% SZS status GaveUp for HL403024+4.p
36619.29/5780.22	% SZS status Ended for HL403024+4.p
36622.80/5780.61	% SZS status Started for HL403024+5.p
36622.80/5780.61	% SZS status GaveUp for HL403024+5.p
36622.80/5780.61	% SZS status Ended for HL403024+5.p
36635.91/5782.23	% SZS status Started for HL403025+4.p
36635.91/5782.23	% SZS status GaveUp for HL403025+4.p
36635.91/5782.23	% SZS status Ended for HL403025+4.p
36635.91/5782.23	% SZS status Started for HL403025+5.p
36635.91/5782.23	% SZS status GaveUp for HL403025+5.p
36635.91/5782.23	% SZS status Ended for HL403025+5.p
36665.46/5785.98	% SZS status Started for HL403026+4.p
36665.46/5785.98	% SZS status GaveUp for HL403026+4.p
36665.46/5785.98	% SZS status Ended for HL403026+4.p
36665.57/5786.01	% SZS status Started for HL403026+5.p
36665.57/5786.01	% SZS status GaveUp for HL403026+5.p
36665.57/5786.01	% SZS status Ended for HL403026+5.p
36676.52/5787.48	% SZS status Started for HL403027+4.p
36676.52/5787.48	% SZS status GaveUp for HL403027+4.p
36676.52/5787.48	% SZS status Ended for HL403027+4.p
36678.79/5787.64	% SZS status Started for HL403027+5.p
36678.79/5787.64	% SZS status GaveUp for HL403027+5.p
36678.79/5787.64	% SZS status Ended for HL403027+5.p
36690.38/5789.15	% SZS status Started for HL403028+5.p
36690.38/5789.15	% SZS status GaveUp for HL403028+5.p
36690.38/5789.15	% SZS status Ended for HL403028+5.p
36692.88/5789.40	% SZS status Started for HL403028+4.p
36692.88/5789.40	% SZS status GaveUp for HL403028+4.p
36692.88/5789.40	% SZS status Ended for HL403028+4.p
36704.65/5791.13	% SZS status Started for HL403029+5.p
36704.65/5791.13	% SZS status GaveUp for HL403029+5.p
36704.65/5791.13	% SZS status Ended for HL403029+5.p
36704.85/5791.19	% SZS status Started for HL403029+4.p
36704.85/5791.19	% SZS status GaveUp for HL403029+4.p
36704.85/5791.19	% SZS status Ended for HL403029+4.p
36734.67/5794.65	% SZS status Started for HL403031+5.p
36734.67/5794.65	% SZS status GaveUp for HL403031+5.p
36734.67/5794.65	% SZS status Ended for HL403031+5.p
36735.40/5794.78	% SZS status Started for HL403031+4.p
36735.40/5794.78	% SZS status GaveUp for HL403031+4.p
36735.40/5794.78	% SZS status Ended for HL403031+4.p
36747.37/5796.25	% SZS status Started for HL403032+5.p
36747.37/5796.25	% SZS status GaveUp for HL403032+5.p
36747.37/5796.25	% SZS status Ended for HL403032+5.p
36751.61/5796.85	% SZS status Started for HL403032+4.p
36751.61/5796.85	% SZS status GaveUp for HL403032+4.p
36751.61/5796.85	% SZS status Ended for HL403032+4.p
36760.84/5797.97	% SZS status Started for HL403033+4.p
36760.84/5797.97	% SZS status GaveUp for HL403033+4.p
36760.84/5797.97	% SZS status Ended for HL403033+4.p
36761.20/5798.02	% SZS status Started for HL403033+5.p
36761.20/5798.02	% SZS status GaveUp for HL403033+5.p
36761.20/5798.02	% SZS status Ended for HL403033+5.p
36775.89/5799.88	% SZS status Started for HL403034+5.p
36775.89/5799.88	% SZS status GaveUp for HL403034+5.p
36775.89/5799.88	% SZS status Ended for HL403034+5.p
36776.72/5800.04	% SZS status Started for HL403034+4.p
36776.72/5800.04	% SZS status GaveUp for HL403034+4.p
36776.72/5800.04	% SZS status Ended for HL403034+4.p
36803.33/5803.35	% SZS status Started for HL403035+5.p
36803.33/5803.35	% SZS status GaveUp for HL403035+5.p
36803.33/5803.35	% SZS status Ended for HL403035+5.p
36805.16/5803.56	% SZS status Started for HL403035+4.p
36805.16/5803.56	% SZS status GaveUp for HL403035+4.p
36805.16/5803.56	% SZS status Ended for HL403035+4.p
36816.61/5805.08	% SZS status Started for HL403036+4.p
36816.61/5805.08	% SZS status GaveUp for HL403036+4.p
36816.61/5805.08	% SZS status Ended for HL403036+4.p
36823.30/5805.93	% SZS status Started for HL403036+5.p
36823.30/5805.93	% SZS status GaveUp for HL403036+5.p
36823.30/5805.93	% SZS status Ended for HL403036+5.p
36828.98/5806.58	% SZS status Started for HL403037+5.p
36828.98/5806.58	% SZS status GaveUp for HL403037+5.p
36828.98/5806.58	% SZS status Ended for HL403037+5.p
36830.38/5806.81	% SZS status Started for HL403037+4.p
36830.38/5806.81	% SZS status GaveUp for HL403037+4.p
36830.38/5806.81	% SZS status Ended for HL403037+4.p
36845.68/5808.71	% SZS status Started for HL403038+4.p
36845.68/5808.71	% SZS status GaveUp for HL403038+4.p
36845.68/5808.71	% SZS status Ended for HL403038+4.p
36846.09/5808.75	% SZS status Started for HL403038+5.p
36846.09/5808.75	% SZS status GaveUp for HL403038+5.p
36846.09/5808.75	% SZS status Ended for HL403038+5.p
36873.41/5812.15	% SZS status Started for HL403039+4.p
36873.41/5812.15	% SZS status GaveUp for HL403039+4.p
36873.41/5812.15	% SZS status Ended for HL403039+4.p
36873.41/5812.17	% SZS status Started for HL403039+5.p
36873.41/5812.17	% SZS status GaveUp for HL403039+5.p
36873.41/5812.17	% SZS status Ended for HL403039+5.p
36889.34/5814.16	% SZS status Started for HL403040+4.p
36889.34/5814.16	% SZS status GaveUp for HL403040+4.p
36889.34/5814.16	% SZS status Ended for HL403040+4.p
36892.44/5814.58	% SZS status Started for HL403040+5.p
36892.44/5814.58	% SZS status GaveUp for HL403040+5.p
36892.44/5814.58	% SZS status Ended for HL403040+5.p
36898.75/5815.36	% SZS status Started for HL403041+4.p
36898.75/5815.36	% SZS status GaveUp for HL403041+4.p
36898.75/5815.36	% SZS status Ended for HL403041+4.p
36899.49/5815.44	% SZS status Started for HL403041+5.p
36899.49/5815.44	% SZS status GaveUp for HL403041+5.p
36899.49/5815.44	% SZS status Ended for HL403041+5.p
36915.73/5817.51	% SZS status Started for HL403042+4.p
36915.73/5817.51	% SZS status GaveUp for HL403042+4.p
36915.73/5817.51	% SZS status Ended for HL403042+4.p
36915.73/5817.53	% SZS status Started for HL403042+5.p
36915.73/5817.53	% SZS status GaveUp for HL403042+5.p
36915.73/5817.53	% SZS status Ended for HL403042+5.p
36940.49/5820.71	% SZS status Started for HL403043+5.p
36940.49/5820.71	% SZS status GaveUp for HL403043+5.p
36940.49/5820.71	% SZS status Ended for HL403043+5.p
36943.06/5820.94	% SZS status Started for HL403043+4.p
36943.06/5820.94	% SZS status GaveUp for HL403043+4.p
36943.06/5820.94	% SZS status Ended for HL403043+4.p
36958.77/5823.01	% SZS status Started for HL403045+4.p
36958.77/5823.01	% SZS status GaveUp for HL403045+4.p
36958.77/5823.01	% SZS status Ended for HL403045+4.p
36961.09/5823.22	% SZS status Started for HL403045+5.p
36961.09/5823.22	% SZS status GaveUp for HL403045+5.p
36961.09/5823.22	% SZS status Ended for HL403045+5.p
36968.27/5824.21	% SZS status Started for HL403046+5.p
36968.27/5824.21	% SZS status GaveUp for HL403046+5.p
36968.27/5824.21	% SZS status Ended for HL403046+5.p
36969.57/5824.28	% SZS status Started for HL403046+4.p
36969.57/5824.28	% SZS status GaveUp for HL403046+4.p
36969.57/5824.28	% SZS status Ended for HL403046+4.p
36985.44/5826.45	% SZS status Started for HL403047+5.p
36985.44/5826.45	% SZS status GaveUp for HL403047+5.p
36985.44/5826.45	% SZS status Ended for HL403047+5.p
36987.26/5826.51	% SZS status Started for HL403047+4.p
36987.26/5826.51	% SZS status GaveUp for HL403047+4.p
36987.26/5826.51	% SZS status Ended for HL403047+4.p
37011.52/5829.60	% SZS status Started for HL403048+4.p
37011.52/5829.60	% SZS status GaveUp for HL403048+4.p
37011.52/5829.60	% SZS status Ended for HL403048+4.p
37012.24/5829.77	% SZS status Started for HL403048+5.p
37012.24/5829.77	% SZS status GaveUp for HL403048+5.p
37012.24/5829.77	% SZS status Ended for HL403048+5.p
37029.71/5831.90	% SZS status Started for HL403049+5.p
37029.71/5831.90	% SZS status GaveUp for HL403049+5.p
37029.71/5831.90	% SZS status Ended for HL403049+5.p
37031.77/5832.17	% SZS status Started for HL403049+4.p
37031.77/5832.17	% SZS status GaveUp for HL403049+4.p
37031.77/5832.17	% SZS status Ended for HL403049+4.p
37036.89/5832.85	% SZS status Started for HL403050+5.p
37036.89/5832.85	% SZS status GaveUp for HL403050+5.p
37036.89/5832.85	% SZS status Ended for HL403050+5.p
37037.59/5832.88	% SZS status Started for HL403053+4.p
37037.59/5832.88	% SZS status Theorem for HL403053+4.p
37037.59/5832.88	% SZS status Ended for HL403053+4.p
37038.35/5833.03	% SZS status Started for HL403050+4.p
37038.35/5833.03	% SZS status GaveUp for HL403050+4.p
37038.35/5833.03	% SZS status Ended for HL403050+4.p
37042.29/5833.56	% SZS status Started for HL403054+5.p
37042.29/5833.56	% SZS status Theorem for HL403054+5.p
37042.29/5833.56	% SZS status Ended for HL403054+5.p
37045.20/5833.82	% SZS status Started for HL403054+4.p
37045.20/5833.82	% SZS status Theorem for HL403054+4.p
37045.20/5833.82	% SZS status Ended for HL403054+4.p
37056.16/5835.27	% SZS status Started for HL403051+4.p
37056.16/5835.27	% SZS status GaveUp for HL403051+4.p
37056.16/5835.27	% SZS status Ended for HL403051+4.p
37056.95/5835.47	% SZS status Started for HL403051+5.p
37056.95/5835.47	% SZS status GaveUp for HL403051+5.p
37056.95/5835.47	% SZS status Ended for HL403051+5.p
37080.91/5838.41	% SZS status Started for HL403052+5.p
37080.91/5838.41	% SZS status GaveUp for HL403052+5.p
37080.91/5838.41	% SZS status Ended for HL403052+5.p
37083.42/5838.73	% SZS status Started for HL403052+4.p
37083.42/5838.73	% SZS status GaveUp for HL403052+4.p
37083.42/5838.73	% SZS status Ended for HL403052+4.p
37099.57/5840.75	% SZS status Started for HL403053+5.p
37099.57/5840.75	% SZS status GaveUp for HL403053+5.p
37099.57/5840.75	% SZS status Ended for HL403053+5.p
37110.28/5842.05	% SZS status Started for HL403055+4.p
37110.28/5842.05	% SZS status GaveUp for HL403055+4.p
37110.28/5842.05	% SZS status Ended for HL403055+4.p
37111.47/5842.20	% SZS status Started for HL403055+5.p
37111.47/5842.20	% SZS status GaveUp for HL403055+5.p
37111.47/5842.20	% SZS status Ended for HL403055+5.p
37117.40/5842.96	% SZS status Started for HL403056+4.p
37117.40/5842.96	% SZS status GaveUp for HL403056+4.p
37117.40/5842.96	% SZS status Ended for HL403056+4.p
37126.22/5844.10	% SZS status Started for HL403056+5.p
37126.22/5844.10	% SZS status GaveUp for HL403056+5.p
37126.22/5844.10	% SZS status Ended for HL403056+5.p
37129.22/5844.42	% SZS status Started for HL403057+4.p
37129.22/5844.42	% SZS status GaveUp for HL403057+4.p
37129.22/5844.42	% SZS status Ended for HL403057+4.p
37140.29/5845.91	% SZS status Started for HL403062+4.p
37140.29/5845.91	% SZS status Theorem for HL403062+4.p
37140.29/5845.91	% SZS status Ended for HL403062+4.p
37149.04/5847.10	% SZS status Started for HL403057+5.p
37149.04/5847.10	% SZS status GaveUp for HL403057+5.p
37149.04/5847.10	% SZS status Ended for HL403057+5.p
37149.66/5847.26	% SZS status Started for HL403062+5.p
37149.66/5847.26	% SZS status Theorem for HL403062+5.p
37149.66/5847.26	% SZS status Ended for HL403062+5.p
37155.24/5847.81	% SZS status Started for HL403058+4.p
37155.24/5847.81	% SZS status GaveUp for HL403058+4.p
37155.24/5847.81	% SZS status Ended for HL403058+4.p
37158.93/5848.34	% SZS status Started for HL403063+4.p
37158.93/5848.34	% SZS status Theorem for HL403063+4.p
37158.93/5848.34	% SZS status Ended for HL403063+4.p
37161.70/5848.54	% SZS status Started for HL403063+5.p
37161.70/5848.54	% SZS status Theorem for HL403063+5.p
37161.70/5848.54	% SZS status Ended for HL403063+5.p
37167.57/5849.37	% SZS status Started for HL403058+5.p
37167.57/5849.37	% SZS status GaveUp for HL403058+5.p
37167.57/5849.37	% SZS status Ended for HL403058+5.p
37179.50/5850.85	% SZS status Started for HL403059+5.p
37179.50/5850.85	% SZS status GaveUp for HL403059+5.p
37179.50/5850.85	% SZS status Ended for HL403059+5.p
37180.72/5851.05	% SZS status Started for HL403059+4.p
37180.72/5851.05	% SZS status GaveUp for HL403059+4.p
37180.72/5851.05	% SZS status Ended for HL403059+4.p
37188.57/5851.96	% SZS status Started for HL403060+4.p
37188.57/5851.96	% SZS status GaveUp for HL403060+4.p
37188.57/5851.96	% SZS status Ended for HL403060+4.p
37194.09/5852.72	% SZS status Started for HL403060+5.p
37194.09/5852.72	% SZS status GaveUp for HL403060+5.p
37194.09/5852.72	% SZS status Ended for HL403060+5.p
37228.87/5857.13	% SZS status Started for HL403064+5.p
37228.87/5857.13	% SZS status GaveUp for HL403064+5.p
37228.87/5857.13	% SZS status Ended for HL403064+5.p
37232.42/5857.49	% SZS status Started for HL403065+4.p
37232.42/5857.49	% SZS status GaveUp for HL403065+4.p
37232.42/5857.49	% SZS status Ended for HL403065+4.p
37232.99/5857.52	% SZS status Started for HL403064+4.p
37232.99/5857.52	% SZS status GaveUp for HL403064+4.p
37232.99/5857.52	% SZS status Ended for HL403064+4.p
37236.68/5857.98	% SZS status Started for HL403065+5.p
37236.68/5857.98	% SZS status GaveUp for HL403065+5.p
37236.68/5857.98	% SZS status Ended for HL403065+5.p
37251.25/5859.81	% SZS status Started for HL403066+5.p
37251.25/5859.81	% SZS status GaveUp for HL403066+5.p
37251.25/5859.81	% SZS status Ended for HL403066+5.p
37251.40/5859.84	% SZS status Started for HL403066+4.p
37251.40/5859.84	% SZS status GaveUp for HL403066+4.p
37251.40/5859.84	% SZS status Ended for HL403066+4.p
37260.47/5860.99	% SZS status Started for HL403067+4.p
37260.47/5860.99	% SZS status GaveUp for HL403067+4.p
37260.47/5860.99	% SZS status Ended for HL403067+4.p
37262.10/5861.34	% SZS status Started for HL403067+5.p
37262.10/5861.34	% SZS status GaveUp for HL403067+5.p
37262.10/5861.34	% SZS status Ended for HL403067+5.p
37300.72/5866.05	% SZS status Started for HL403068+5.p
37300.72/5866.05	% SZS status GaveUp for HL403068+5.p
37300.72/5866.05	% SZS status Ended for HL403068+5.p
37301.38/5866.13	% SZS status Started for HL403068+4.p
37301.38/5866.13	% SZS status GaveUp for HL403068+4.p
37301.38/5866.13	% SZS status Ended for HL403068+4.p
37303.86/5866.45	% SZS status Started for HL403069+4.p
37303.86/5866.45	% SZS status GaveUp for HL403069+4.p
37303.86/5866.45	% SZS status Ended for HL403069+4.p
37305.12/5866.61	% SZS status Started for HL403069+5.p
37305.12/5866.61	% SZS status GaveUp for HL403069+5.p
37305.12/5866.61	% SZS status Ended for HL403069+5.p
37319.94/5868.48	% SZS status Started for HL403070+5.p
37319.94/5868.48	% SZS status GaveUp for HL403070+5.p
37319.94/5868.48	% SZS status Ended for HL403070+5.p
37321.31/5868.72	% SZS status Started for HL403070+4.p
37321.31/5868.72	% SZS status GaveUp for HL403070+4.p
37321.31/5868.72	% SZS status Ended for HL403070+4.p
37331.43/5869.95	% SZS status Started for HL403071+5.p
37331.43/5869.95	% SZS status GaveUp for HL403071+5.p
37331.43/5869.95	% SZS status Ended for HL403071+5.p
37331.43/5869.98	% SZS status Started for HL403071+4.p
37331.43/5869.98	% SZS status GaveUp for HL403071+4.p
37331.43/5869.98	% SZS status Ended for HL403071+4.p
37369.31/5874.71	% SZS status Started for HL403072+5.p
37369.31/5874.71	% SZS status GaveUp for HL403072+5.p
37369.31/5874.71	% SZS status Ended for HL403072+5.p
37371.93/5875.00	% SZS status Started for HL403072+4.p
37371.93/5875.00	% SZS status GaveUp for HL403072+4.p
37371.93/5875.00	% SZS status Ended for HL403072+4.p
37372.70/5875.17	% SZS status Started for HL403073+5.p
37372.70/5875.17	% SZS status GaveUp for HL403073+5.p
37372.70/5875.17	% SZS status Ended for HL403073+5.p
37373.86/5875.36	% SZS status Started for HL403073+4.p
37373.86/5875.36	% SZS status GaveUp for HL403073+4.p
37373.86/5875.36	% SZS status Ended for HL403073+4.p
37389.18/5877.27	% SZS status Started for HL403074+5.p
37389.18/5877.27	% SZS status GaveUp for HL403074+5.p
37389.18/5877.27	% SZS status Ended for HL403074+5.p
37392.89/5877.65	% SZS status Started for HL403074+4.p
37392.89/5877.65	% SZS status GaveUp for HL403074+4.p
37392.89/5877.65	% SZS status Ended for HL403074+4.p
37400.84/5878.55	% SZS status Started for HL403075+5.p
37400.84/5878.55	% SZS status GaveUp for HL403075+5.p
37400.84/5878.55	% SZS status Ended for HL403075+5.p
37404.79/5879.06	% SZS status Started for HL403075+4.p
37404.79/5879.06	% SZS status GaveUp for HL403075+4.p
37404.79/5879.06	% SZS status Ended for HL403075+4.p
37441.75/5883.71	% SZS status Started for HL403076+5.p
37441.75/5883.71	% SZS status GaveUp for HL403076+5.p
37441.75/5883.71	% SZS status Ended for HL403076+5.p
37442.92/5883.88	% SZS status Started for HL403076+4.p
37442.92/5883.88	% SZS status GaveUp for HL403076+4.p
37442.92/5883.88	% SZS status Ended for HL403076+4.p
37443.50/5883.90	% SZS status Started for HL403077+5.p
37443.50/5883.90	% SZS status GaveUp for HL403077+5.p
37443.50/5883.90	% SZS status Ended for HL403077+5.p
37445.30/5884.27	% SZS status Started for HL403077+4.p
37445.30/5884.27	% SZS status GaveUp for HL403077+4.p
37445.30/5884.27	% SZS status Ended for HL403077+4.p
37461.48/5886.21	% SZS status Started for HL403079+5.p
37461.48/5886.21	% SZS status GaveUp for HL403079+5.p
37461.48/5886.21	% SZS status Ended for HL403079+5.p
37461.87/5886.22	% SZS status Started for HL403079+4.p
37461.87/5886.22	% SZS status GaveUp for HL403079+4.p
37461.87/5886.22	% SZS status Ended for HL403079+4.p
37471.26/5887.48	% SZS status Started for HL403080+4.p
37471.26/5887.48	% SZS status GaveUp for HL403080+4.p
37471.26/5887.48	% SZS status Ended for HL403080+4.p
37475.00/5887.94	% SZS status Started for HL403080+5.p
37475.00/5887.94	% SZS status GaveUp for HL403080+5.p
37475.00/5887.94	% SZS status Ended for HL403080+5.p
37513.74/5892.65	% SZS status Started for HL403081+4.p
37513.74/5892.65	% SZS status GaveUp for HL403081+4.p
37513.74/5892.65	% SZS status Ended for HL403081+4.p
37513.74/5892.67	% SZS status Started for HL403081+5.p
37513.74/5892.67	% SZS status GaveUp for HL403081+5.p
37513.74/5892.67	% SZS status Ended for HL403081+5.p
37514.17/5892.80	% SZS status Started for HL403082+5.p
37514.17/5892.80	% SZS status GaveUp for HL403082+5.p
37514.17/5892.80	% SZS status Ended for HL403082+5.p
37521.20/5893.56	% SZS status Started for HL403082+4.p
37521.20/5893.56	% SZS status GaveUp for HL403082+4.p
37521.20/5893.56	% SZS status Ended for HL403082+4.p
37531.93/5895.04	% SZS status Started for HL403083+5.p
37531.93/5895.04	% SZS status GaveUp for HL403083+5.p
37531.93/5895.04	% SZS status Ended for HL403083+5.p
37532.64/5895.17	% SZS status Started for HL403083+4.p
37532.64/5895.17	% SZS status GaveUp for HL403083+4.p
37532.64/5895.17	% SZS status Ended for HL403083+4.p
37544.32/5896.48	% SZS status Started for HL403084+4.p
37544.32/5896.48	% SZS status GaveUp for HL403084+4.p
37544.32/5896.48	% SZS status Ended for HL403084+4.p
37545.46/5896.63	% SZS status Started for HL403084+5.p
37545.46/5896.63	% SZS status GaveUp for HL403084+5.p
37545.46/5896.63	% SZS status Ended for HL403084+5.p
37580.96/5901.21	% SZS status Started for HL403085+5.p
37580.96/5901.21	% SZS status GaveUp for HL403085+5.p
37580.96/5901.21	% SZS status Ended for HL403085+5.p
37585.09/5901.65	% SZS status Started for HL403085+4.p
37585.09/5901.65	% SZS status GaveUp for HL403085+4.p
37585.09/5901.65	% SZS status Ended for HL403085+4.p
37587.27/5901.92	% SZS status Started for HL403086+4.p
37587.27/5901.92	% SZS status GaveUp for HL403086+4.p
37587.27/5901.92	% SZS status Ended for HL403086+4.p
37589.31/5902.14	% SZS status Started for HL403086+5.p
37589.31/5902.14	% SZS status GaveUp for HL403086+5.p
37589.31/5902.14	% SZS status Ended for HL403086+5.p
37604.14/5904.03	% SZS status Started for HL403087+5.p
37604.14/5904.03	% SZS status GaveUp for HL403087+5.p
37604.14/5904.03	% SZS status Ended for HL403087+5.p
37604.65/5904.10	% SZS status Started for HL403087+4.p
37604.65/5904.10	% SZS status GaveUp for HL403087+4.p
37604.65/5904.10	% SZS status Ended for HL403087+4.p
37613.20/5905.22	% SZS status Started for HL403088+5.p
37613.20/5905.22	% SZS status GaveUp for HL403088+5.p
37613.20/5905.22	% SZS status Ended for HL403088+5.p
37622.79/5905.49	% SZS status Started for HL403088+4.p
37622.79/5905.49	% SZS status GaveUp for HL403088+4.p
37622.79/5905.49	% SZS status Ended for HL403088+4.p
37661.02/5910.22	% SZS status Started for HL403089+4.p
37661.02/5910.22	% SZS status GaveUp for HL403089+4.p
37661.02/5910.22	% SZS status Ended for HL403089+4.p
37662.56/5910.44	% SZS status Started for HL403089+5.p
37662.56/5910.44	% SZS status GaveUp for HL403089+5.p
37662.56/5910.44	% SZS status Ended for HL403089+5.p
37666.32/5910.85	% SZS status Started for HL403091+4.p
37666.32/5910.85	% SZS status GaveUp for HL403091+4.p
37666.32/5910.85	% SZS status Ended for HL403091+4.p
37666.79/5910.92	% SZS status Started for HL403091+5.p
37666.79/5910.92	% SZS status GaveUp for HL403091+5.p
37666.79/5910.92	% SZS status Ended for HL403091+5.p
37681.09/5912.75	% SZS status Started for HL403092+5.p
37681.09/5912.75	% SZS status GaveUp for HL403092+5.p
37681.09/5912.75	% SZS status Ended for HL403092+5.p
37684.13/5913.11	% SZS status Started for HL403092+4.p
37684.13/5913.11	% SZS status GaveUp for HL403092+4.p
37684.13/5913.11	% SZS status Ended for HL403092+4.p
37693.29/5914.23	% SZS status Started for HL403093+4.p
37693.29/5914.23	% SZS status GaveUp for HL403093+4.p
37693.29/5914.23	% SZS status Ended for HL403093+4.p
37693.82/5914.34	% SZS status Started for HL403093+5.p
37693.82/5914.34	% SZS status GaveUp for HL403093+5.p
37693.82/5914.34	% SZS status Ended for HL403093+5.p
37730.58/5919.01	% SZS status Started for HL403094+5.p
37730.58/5919.01	% SZS status GaveUp for HL403094+5.p
37730.58/5919.01	% SZS status Ended for HL403094+5.p
37734.79/5919.47	% SZS status Started for HL403094+4.p
37734.79/5919.47	% SZS status GaveUp for HL403094+4.p
37734.79/5919.47	% SZS status Ended for HL403094+4.p
37735.42/5919.53	% SZS status Started for HL403095+5.p
37735.42/5919.53	% SZS status GaveUp for HL403095+5.p
37735.42/5919.53	% SZS status Ended for HL403095+5.p
37736.76/5919.86	% SZS status Started for HL403095+4.p
37736.76/5919.86	% SZS status GaveUp for HL403095+4.p
37736.76/5919.86	% SZS status Ended for HL403095+4.p
37752.00/5921.66	% SZS status Started for HL403096+5.p
37752.00/5921.66	% SZS status GaveUp for HL403096+5.p
37752.00/5921.66	% SZS status Ended for HL403096+5.p
37753.29/5921.84	% SZS status Started for HL403096+4.p
37753.29/5921.84	% SZS status GaveUp for HL403096+4.p
37753.29/5921.84	% SZS status Ended for HL403096+4.p
37765.10/5923.32	% SZS status Started for HL403097+5.p
37765.10/5923.32	% SZS status GaveUp for HL403097+5.p
37765.10/5923.32	% SZS status Ended for HL403097+5.p
37766.50/5923.54	% SZS status Started for HL403097+4.p
37766.50/5923.54	% SZS status GaveUp for HL403097+4.p
37766.50/5923.54	% SZS status Ended for HL403097+4.p
37802.11/5927.98	% SZS status Started for HL403098+4.p
37802.11/5927.98	% SZS status GaveUp for HL403098+4.p
37802.11/5927.98	% SZS status Ended for HL403098+4.p
37804.45/5928.27	% SZS status Started for HL403098+5.p
37804.45/5928.27	% SZS status GaveUp for HL403098+5.p
37804.45/5928.27	% SZS status Ended for HL403098+5.p
37807.16/5928.67	% SZS status Started for HL403099+4.p
37807.16/5928.67	% SZS status GaveUp for HL403099+4.p
37807.16/5928.67	% SZS status Ended for HL403099+4.p
37809.74/5928.90	% SZS status Started for HL403099+5.p
37809.74/5928.90	% SZS status GaveUp for HL403099+5.p
37809.74/5928.90	% SZS status Ended for HL403099+5.p
37823.42/5930.63	% SZS status Started for HL403100+5.p
37823.42/5930.63	% SZS status GaveUp for HL403100+5.p
37823.42/5930.63	% SZS status Ended for HL403100+5.p
37823.77/5930.67	% SZS status Started for HL403100+4.p
37823.77/5930.67	% SZS status GaveUp for HL403100+4.p
37823.77/5930.67	% SZS status Ended for HL403100+4.p
37834.56/5932.10	% SZS status Started for HL403101+5.p
37834.56/5932.10	% SZS status GaveUp for HL403101+5.p
37834.56/5932.10	% SZS status Ended for HL403101+5.p
37838.28/5932.51	% SZS status Started for HL403101+4.p
37838.28/5932.51	% SZS status GaveUp for HL403101+4.p
37838.28/5932.51	% SZS status Ended for HL403101+4.p
37872.29/5936.90	% SZS status Started for HL403102+5.p
37872.29/5936.90	% SZS status GaveUp for HL403102+5.p
37872.29/5936.90	% SZS status Ended for HL403102+5.p
37875.39/5937.17	% SZS status Started for HL403102+4.p
37875.39/5937.17	% SZS status GaveUp for HL403102+4.p
37875.39/5937.17	% SZS status Ended for HL403102+4.p
37877.34/5937.47	% SZS status Started for HL403103+5.p
37877.34/5937.47	% SZS status GaveUp for HL403103+5.p
37877.34/5937.47	% SZS status Ended for HL403103+5.p
37880.14/5937.76	% SZS status Started for HL403103+4.p
37880.14/5937.76	% SZS status GaveUp for HL403103+4.p
37880.14/5937.76	% SZS status Ended for HL403103+4.p
37894.93/5939.61	% SZS status Started for HL403105+5.p
37894.93/5939.61	% SZS status GaveUp for HL403105+5.p
37894.93/5939.61	% SZS status Ended for HL403105+5.p
37895.52/5939.72	% SZS status Started for HL403105+4.p
37895.52/5939.72	% SZS status GaveUp for HL403105+4.p
37895.52/5939.72	% SZS status Ended for HL403105+4.p
37905.11/5941.04	% SZS status Started for HL403106+4.p
37905.11/5941.04	% SZS status GaveUp for HL403106+4.p
37905.11/5941.04	% SZS status Ended for HL403106+4.p
37907.94/5941.29	% SZS status Started for HL403106+5.p
37907.94/5941.29	% SZS status GaveUp for HL403106+5.p
37907.94/5941.29	% SZS status Ended for HL403106+5.p
37945.83/5946.09	% SZS status Started for HL403107+4.p
37945.83/5946.09	% SZS status GaveUp for HL403107+4.p
37945.83/5946.09	% SZS status Ended for HL403107+4.p
37945.92/5946.13	% SZS status Started for HL403107+5.p
37945.92/5946.13	% SZS status GaveUp for HL403107+5.p
37945.92/5946.13	% SZS status Ended for HL403107+5.p
37956.22/5946.44	% SZS status Started for HL403108+4.p
37956.22/5946.44	% SZS status GaveUp for HL403108+4.p
37956.22/5946.44	% SZS status Ended for HL403108+4.p
37957.71/5946.69	% SZS status Started for HL403108+5.p
37957.71/5946.69	% SZS status GaveUp for HL403108+5.p
37957.71/5946.69	% SZS status Ended for HL403108+5.p
37974.14/5948.62	% SZS status Started for HL403109+5.p
37974.14/5948.62	% SZS status GaveUp for HL403109+5.p
37974.14/5948.62	% SZS status Ended for HL403109+5.p
37976.02/5948.97	% SZS status Started for HL403109+4.p
37976.02/5948.97	% SZS status GaveUp for HL403109+4.p
37976.02/5948.97	% SZS status Ended for HL403109+4.p
37985.21/5950.10	% SZS status Started for HL403110+5.p
37985.21/5950.10	% SZS status GaveUp for HL403110+5.p
37985.21/5950.10	% SZS status Ended for HL403110+5.p
37986.47/5950.17	% SZS status Started for HL403110+4.p
37986.47/5950.17	% SZS status GaveUp for HL403110+4.p
37986.47/5950.17	% SZS status Ended for HL403110+4.p
38024.75/5955.12	% SZS status Started for HL403111+5.p
38024.75/5955.12	% SZS status GaveUp for HL403111+5.p
38024.75/5955.12	% SZS status Ended for HL403111+5.p
38027.69/5955.35	% SZS status Started for HL403111+4.p
38027.69/5955.35	% SZS status GaveUp for HL403111+4.p
38027.69/5955.35	% SZS status Ended for HL403111+4.p
38028.81/5955.50	% SZS status Started for HL403112+5.p
38028.81/5955.50	% SZS status GaveUp for HL403112+5.p
38028.81/5955.50	% SZS status Ended for HL403112+5.p
38030.32/5955.76	% SZS status Started for HL403112+4.p
38030.32/5955.76	% SZS status GaveUp for HL403112+4.p
38030.32/5955.76	% SZS status Ended for HL403112+4.p
38046.56/5957.71	% SZS status Started for HL403113+4.p
38046.56/5957.71	% SZS status GaveUp for HL403113+4.p
38046.56/5957.71	% SZS status Ended for HL403113+4.p
38046.56/5957.74	% SZS status Started for HL403113+5.p
38046.56/5957.74	% SZS status GaveUp for HL403113+5.p
38046.56/5957.74	% SZS status Ended for HL403113+5.p
38056.48/5959.03	% SZS status Started for HL403114+5.p
38056.48/5959.03	% SZS status GaveUp for HL403114+5.p
38056.48/5959.03	% SZS status Ended for HL403114+5.p
38057.98/5959.16	% SZS status Started for HL403114+4.p
38057.98/5959.16	% SZS status GaveUp for HL403114+4.p
38057.98/5959.16	% SZS status Ended for HL403114+4.p
38096.87/5964.08	% SZS status Started for HL403115+4.p
38096.87/5964.08	% SZS status GaveUp for HL403115+4.p
38096.87/5964.08	% SZS status Ended for HL403115+4.p
38100.45/5964.59	% SZS status Started for HL403117+5.p
38100.45/5964.59	% SZS status GaveUp for HL403117+5.p
38100.45/5964.59	% SZS status Ended for HL403117+5.p
38100.84/5964.60	% SZS status Started for HL403115+5.p
38100.84/5964.60	% SZS status GaveUp for HL403115+5.p
38100.84/5964.60	% SZS status Ended for HL403115+5.p
38101.04/5964.75	% SZS status Started for HL403117+4.p
38101.04/5964.75	% SZS status GaveUp for HL403117+4.p
38101.04/5964.75	% SZS status Ended for HL403117+4.p
38117.17/5966.62	% SZS status Started for HL403118+5.p
38117.17/5966.62	% SZS status GaveUp for HL403118+5.p
38117.17/5966.62	% SZS status Ended for HL403118+5.p
38119.07/5966.89	% SZS status Started for HL403118+4.p
38119.07/5966.89	% SZS status GaveUp for HL403118+4.p
38119.07/5966.89	% SZS status Ended for HL403118+4.p
38127.87/5967.97	% SZS status Started for HL403119+5.p
38127.87/5967.97	% SZS status GaveUp for HL403119+5.p
38127.87/5967.97	% SZS status Ended for HL403119+5.p
38127.87/5967.97	% SZS status Started for HL403119+4.p
38127.87/5967.97	% SZS status GaveUp for HL403119+4.p
38127.87/5967.97	% SZS status Ended for HL403119+4.p
38166.87/5973.03	% SZS status Started for HL403120+4.p
38166.87/5973.03	% SZS status GaveUp for HL403120+4.p
38166.87/5973.03	% SZS status Ended for HL403120+4.p
38171.74/5973.51	% SZS status Started for HL403122+4.p
38171.74/5973.51	% SZS status GaveUp for HL403122+4.p
38171.74/5973.51	% SZS status Ended for HL403122+4.p
38173.14/5973.69	% SZS status Started for HL403122+5.p
38173.14/5973.69	% SZS status GaveUp for HL403122+5.p
38173.14/5973.69	% SZS status Ended for HL403122+5.p
38173.14/5973.73	% SZS status Started for HL403120+5.p
38173.14/5973.73	% SZS status GaveUp for HL403120+5.p
38173.14/5973.73	% SZS status Ended for HL403120+5.p
38189.33/5975.72	% SZS status Started for HL403123+4.p
38189.33/5975.72	% SZS status GaveUp for HL403123+4.p
38189.33/5975.72	% SZS status Ended for HL403123+4.p
38189.33/5975.73	% SZS status Started for HL403123+5.p
38189.33/5975.73	% SZS status GaveUp for HL403123+5.p
38189.33/5975.73	% SZS status Ended for HL403123+5.p
38197.94/5976.90	% SZS status Started for HL403124+5.p
38197.94/5976.90	% SZS status GaveUp for HL403124+5.p
38197.94/5976.90	% SZS status Ended for HL403124+5.p
38198.59/5977.01	% SZS status Started for HL403124+4.p
38198.59/5977.01	% SZS status GaveUp for HL403124+4.p
38198.59/5977.01	% SZS status Ended for HL403124+4.p
38238.61/5982.09	% SZS status Started for HL403125+4.p
38238.61/5982.09	% SZS status GaveUp for HL403125+4.p
38238.61/5982.09	% SZS status Ended for HL403125+4.p
38241.48/5982.34	% SZS status Started for HL403125+5.p
38241.48/5982.34	% SZS status GaveUp for HL403125+5.p
38241.48/5982.34	% SZS status Ended for HL403125+5.p
38242.87/5982.58	% SZS status Started for HL403126+5.p
38242.87/5982.58	% SZS status GaveUp for HL403126+5.p
38242.87/5982.58	% SZS status Ended for HL403126+5.p
38243.31/5982.67	% SZS status Started for HL403126+4.p
38243.31/5982.67	% SZS status GaveUp for HL403126+4.p
38243.31/5982.67	% SZS status Ended for HL403126+4.p
38259.23/5984.52	% SZS status Started for HL403127+5.p
38259.23/5984.52	% SZS status GaveUp for HL403127+5.p
38259.23/5984.52	% SZS status Ended for HL403127+5.p
38261.63/5984.92	% SZS status Started for HL403127+4.p
38261.63/5984.92	% SZS status GaveUp for HL403127+4.p
38261.63/5984.92	% SZS status Ended for HL403127+4.p
38269.75/5985.84	% SZS status Started for HL403128+5.p
38269.75/5985.84	% SZS status GaveUp for HL403128+5.p
38269.75/5985.84	% SZS status Ended for HL403128+5.p
38272.25/5986.15	% SZS status Started for HL403128+4.p
38272.25/5986.15	% SZS status GaveUp for HL403128+4.p
38272.25/5986.15	% SZS status Ended for HL403128+4.p
38312.80/5991.31	% SZS status Started for HL403129+5.p
38312.80/5991.31	% SZS status GaveUp for HL403129+5.p
38312.80/5991.31	% SZS status Ended for HL403129+5.p
38314.51/5991.49	% SZS status Started for HL403131+5.p
38314.51/5991.49	% SZS status GaveUp for HL403131+5.p
38314.51/5991.49	% SZS status Ended for HL403131+5.p
38332.65/5993.75	% SZS status Started for HL403132+5.p
38332.65/5993.75	% SZS status GaveUp for HL403132+5.p
38332.65/5993.75	% SZS status Ended for HL403132+5.p
38342.27/5995.02	% SZS status Started for HL403133+5.p
38342.27/5995.02	% SZS status GaveUp for HL403133+5.p
38342.27/5995.02	% SZS status Ended for HL403133+5.p
38382.48/6000.08	% SZS status Started for HL403134+5.p
38382.48/6000.08	% SZS status GaveUp for HL403134+5.p
38382.48/6000.08	% SZS status Ended for HL403134+5.p
38412.43/6003.84	% SZS status Started for HL403136+5.p
38412.43/6003.84	% SZS status GaveUp for HL403136+5.p
38412.43/6003.84	% SZS status Ended for HL403136+5.p
38438.32/6007.07	% SZS status Started for HL403129+4.p
38438.32/6007.07	% SZS status GaveUp for HL403129+4.p
38438.32/6007.07	eprover: CPU time limit exceeded, terminating
38438.32/6007.07	% SZS status Ended for HL403129+4.p
38440.54/6007.46	% SZS status Started for HL403131+4.p
38440.54/6007.46	% SZS status GaveUp for HL403131+4.p
38440.54/6007.46	eprover: CPU time limit exceeded, terminating
38440.54/6007.46	% SZS status Ended for HL403131+4.p
38458.86/6009.64	% SZS status Started for HL403132+4.p
38458.86/6009.64	% SZS status GaveUp for HL403132+4.p
38458.86/6009.64	eprover: CPU time limit exceeded, terminating
38458.86/6009.64	% SZS status Ended for HL403132+4.p
38472.18/6011.36	% SZS status Started for HL403133+4.p
38472.18/6011.36	% SZS status GaveUp for HL403133+4.p
38472.18/6011.36	eprover: CPU time limit exceeded, terminating
38472.18/6011.36	% SZS status Ended for HL403133+4.p
38484.81/6012.96	% SZS status Started for HL403137+5.p
38484.81/6012.96	% SZS status GaveUp for HL403137+5.p
38484.81/6012.96	% SZS status Ended for HL403137+5.p
38510.37/6016.19	% SZS status Started for HL403134+4.p
38510.37/6016.19	% SZS status GaveUp for HL403134+4.p
38510.37/6016.19	eprover: CPU time limit exceeded, terminating
38510.37/6016.19	% SZS status Ended for HL403134+4.p
38513.58/6016.57	% SZS status Started for HL403138+5.p
38513.58/6016.57	% SZS status GaveUp for HL403138+5.p
38513.58/6016.57	% SZS status Ended for HL403138+5.p
38530.38/6018.71	% SZS status Started for HL403136+4.p
38530.38/6018.71	% SZS status GaveUp for HL403136+4.p
38530.38/6018.71	eprover: CPU time limit exceeded, terminating
38530.38/6018.71	% SZS status Ended for HL403136+4.p
38543.80/6020.43	% SZS status Started for HL403139+5.p
38543.80/6020.43	% SZS status GaveUp for HL403139+5.p
38543.80/6020.43	% SZS status Ended for HL403139+5.p
38582.27/6025.19	% SZS status Started for HL403137+4.p
38582.27/6025.19	% SZS status GaveUp for HL403137+4.p
38582.27/6025.19	eprover: CPU time limit exceeded, terminating
38582.27/6025.19	% SZS status Ended for HL403137+4.p
38582.67/6025.29	% SZS status Started for HL403140+5.p
38582.67/6025.29	% SZS status GaveUp for HL403140+5.p
38582.67/6025.29	% SZS status Ended for HL403140+5.p
38602.87/6027.82	% SZS status Started for HL403141+5.p
38602.87/6027.82	% SZS status GaveUp for HL403141+5.p
38602.87/6027.82	% SZS status Ended for HL403141+5.p
38650.67/6033.85	% SZS status Started for HL403138+4.p
38650.67/6033.85	% SZS status GaveUp for HL403138+4.p
38650.67/6033.85	eprover: CPU time limit exceeded, terminating
38650.67/6033.85	% SZS status Ended for HL403138+4.p
38652.79/6034.30	% SZS status Started for HL403142+5.p
38652.79/6034.30	% SZS status GaveUp for HL403142+5.p
38652.79/6034.30	% SZS status Ended for HL403142+5.p
38660.42/6035.02	% SZS status Started for HL403139+4.p
38660.42/6035.02	% SZS status GaveUp for HL403139+4.p
38660.42/6035.02	eprover: CPU time limit exceeded, terminating
38660.42/6035.02	% SZS status Ended for HL403139+4.p
38674.74/6036.90	% SZS status Started for HL403143+5.p
38674.74/6036.90	% SZS status GaveUp for HL403143+5.p
38674.74/6036.90	% SZS status Ended for HL403143+5.p
38685.77/6038.27	% SZS status Started for HL403140+4.p
38685.77/6038.27	% SZS status GaveUp for HL403140+4.p
38685.77/6038.27	eprover: CPU time limit exceeded, terminating
38685.77/6038.27	% SZS status Ended for HL403140+4.p
38717.00/6042.18	% SZS status Started for HL403141+4.p
38717.00/6042.18	% SZS status GaveUp for HL403141+4.p
38717.00/6042.18	eprover: CPU time limit exceeded, terminating
38717.00/6042.18	% SZS status Ended for HL403141+4.p
38724.98/6043.20	% SZS status Started for HL403144+5.p
38724.98/6043.20	% SZS status GaveUp for HL403144+5.p
38724.98/6043.20	% SZS status Ended for HL403144+5.p
38745.60/6045.77	% SZS status Started for HL403145+5.p
38745.60/6045.77	% SZS status GaveUp for HL403145+5.p
38745.60/6045.77	% SZS status Ended for HL403145+5.p
38746.18/6045.83	% SZS status Started for HL403142+4.p
38746.18/6045.83	% SZS status GaveUp for HL403142+4.p
38746.18/6045.83	eprover: CPU time limit exceeded, terminating
38746.18/6045.83	% SZS status Ended for HL403142+4.p
38784.07/6050.59	% SZS status Started for HL403143+4.p
38784.07/6050.59	% SZS status GaveUp for HL403143+4.p
38784.07/6050.59	eprover: CPU time limit exceeded, terminating
38784.07/6050.59	% SZS status Ended for HL403143+4.p
38788.29/6051.15	% SZS status Started for HL403146+5.p
38788.29/6051.15	% SZS status GaveUp for HL403146+5.p
38788.29/6051.15	% SZS status Ended for HL403146+5.p
38815.78/6054.68	% SZS status Started for HL403147+5.p
38815.78/6054.68	% SZS status GaveUp for HL403147+5.p
38815.78/6054.68	% SZS status Ended for HL403147+5.p
38853.13/6059.32	% SZS status Started for HL403144+4.p
38853.13/6059.32	% SZS status GaveUp for HL403144+4.p
38853.13/6059.32	eprover: CPU time limit exceeded, terminating
38853.13/6059.32	% SZS status Ended for HL403144+4.p
38854.44/6059.52	% SZS status Started for HL403148+5.p
38854.44/6059.52	% SZS status GaveUp for HL403148+5.p
38854.44/6059.52	% SZS status Ended for HL403148+5.p
38861.17/6060.31	% SZS status Started for HL403145+4.p
38861.17/6060.31	% SZS status GaveUp for HL403145+4.p
38861.17/6060.31	eprover: CPU time limit exceeded, terminating
38861.17/6060.31	% SZS status Ended for HL403145+4.p
38888.47/6063.76	% SZS status Started for HL403149+5.p
38888.47/6063.76	% SZS status GaveUp for HL403149+5.p
38888.47/6063.76	% SZS status Ended for HL403149+5.p
38895.84/6064.73	% SZS status Started for HL403146+4.p
38895.84/6064.73	% SZS status GaveUp for HL403146+4.p
38895.84/6064.73	eprover: CPU time limit exceeded, terminating
38895.84/6064.73	% SZS status Ended for HL403146+4.p
38926.02/6068.49	% SZS status Started for HL403147+4.p
38926.02/6068.49	% SZS status GaveUp for HL403147+4.p
38926.02/6068.49	eprover: CPU time limit exceeded, terminating
38926.02/6068.49	% SZS status Ended for HL403147+4.p
38927.23/6068.64	% SZS status Started for HL403150+5.p
38927.23/6068.64	% SZS status GaveUp for HL403150+5.p
38927.23/6068.64	% SZS status Ended for HL403150+5.p
38947.46/6071.16	% SZS status Started for HL403148+4.p
38947.46/6071.16	% SZS status GaveUp for HL403148+4.p
38947.46/6071.16	eprover: CPU time limit exceeded, terminating
38947.46/6071.16	% SZS status Ended for HL403148+4.p
38962.71/6073.09	% SZS status Started for HL403151+5.p
38962.71/6073.09	% SZS status GaveUp for HL403151+5.p
38962.71/6073.09	% SZS status Ended for HL403151+5.p
38989.56/6076.50	% SZS status Started for HL403149+4.p
38989.56/6076.50	% SZS status GaveUp for HL403149+4.p
38989.56/6076.50	eprover: CPU time limit exceeded, terminating
38989.56/6076.50	% SZS status Ended for HL403149+4.p
38997.80/6077.57	% SZS status Started for HL403152+5.p
38997.80/6077.57	% SZS status GaveUp for HL403152+5.p
38997.80/6077.57	% SZS status Ended for HL403152+5.p
39020.05/6080.34	% SZS status Started for HL403153+5.p
39020.05/6080.34	% SZS status GaveUp for HL403153+5.p
39020.05/6080.34	% SZS status Ended for HL403153+5.p
39054.32/6084.73	% SZS status Started for HL403150+4.p
39054.32/6084.73	% SZS status GaveUp for HL403150+4.p
39054.32/6084.73	eprover: CPU time limit exceeded, terminating
39054.32/6084.73	% SZS status Ended for HL403150+4.p
39061.13/6085.45	% SZS status Started for HL403154+5.p
39061.13/6085.45	% SZS status GaveUp for HL403154+5.p
39061.13/6085.45	% SZS status Ended for HL403154+5.p
39062.58/6085.68	% SZS status Started for HL403151+4.p
39062.58/6085.68	% SZS status GaveUp for HL403151+4.p
39062.58/6085.68	eprover: CPU time limit exceeded, terminating
39062.58/6085.68	% SZS status Ended for HL403151+4.p
39091.16/6089.25	% SZS status Started for HL403156+5.p
39091.16/6089.25	% SZS status GaveUp for HL403156+5.p
39091.16/6089.25	% SZS status Ended for HL403156+5.p
39101.60/6090.55	% SZS status Started for HL403152+4.p
39101.60/6090.55	% SZS status GaveUp for HL403152+4.p
39101.60/6090.55	eprover: CPU time limit exceeded, terminating
39101.60/6090.55	% SZS status Ended for HL403152+4.p
39129.98/6094.22	% SZS status Started for HL403153+4.p
39129.98/6094.22	% SZS status GaveUp for HL403153+4.p
39129.98/6094.22	eprover: CPU time limit exceeded, terminating
39129.98/6094.22	% SZS status Ended for HL403153+4.p
39131.05/6094.41	% SZS status Started for HL403157+5.p
39131.05/6094.41	% SZS status GaveUp for HL403157+5.p
39131.05/6094.41	% SZS status Ended for HL403157+5.p
39161.72/6098.29	% SZS status Started for HL403158+5.p
39161.72/6098.29	% SZS status GaveUp for HL403158+5.p
39161.72/6098.29	% SZS status Ended for HL403158+5.p
39165.07/6098.70	% SZS status Started for HL403154+4.p
39165.07/6098.70	% SZS status GaveUp for HL403154+4.p
39165.07/6098.70	eprover: CPU time limit exceeded, terminating
39165.07/6098.70	% SZS status Ended for HL403154+4.p
39198.73/6103.07	% SZS status Started for HL403159+5.p
39198.73/6103.07	% SZS status GaveUp for HL403159+5.p
39198.73/6103.07	% SZS status Ended for HL403159+5.p
39199.18/6103.15	% SZS status Started for HL403156+4.p
39199.18/6103.15	% SZS status GaveUp for HL403156+4.p
39199.18/6103.15	eprover: CPU time limit exceeded, terminating
39199.18/6103.15	% SZS status Ended for HL403156+4.p
39236.20/6107.86	% SZS status Started for HL403160+5.p
39236.20/6107.86	% SZS status GaveUp for HL403160+5.p
39236.20/6107.86	% SZS status Ended for HL403160+5.p
39253.38/6110.18	% SZS status Started for HL403157+4.p
39253.38/6110.18	% SZS status GaveUp for HL403157+4.p
39253.38/6110.18	eprover: CPU time limit exceeded, terminating
39253.38/6110.18	% SZS status Ended for HL403157+4.p
39260.82/6111.15	% SZS status Started for HL403158+4.p
39260.82/6111.15	% SZS status GaveUp for HL403158+4.p
39260.82/6111.15	eprover: CPU time limit exceeded, terminating
39260.82/6111.15	% SZS status Ended for HL403158+4.p
39270.38/6112.48	% SZS status Started for HL403161+5.p
39270.38/6112.48	% SZS status GaveUp for HL403161+5.p
39270.38/6112.48	% SZS status Ended for HL403161+5.p
39303.91/6116.66	% SZS status Started for HL403159+4.p
39303.91/6116.66	% SZS status GaveUp for HL403159+4.p
39303.91/6116.66	eprover: CPU time limit exceeded, terminating
39303.91/6116.66	% SZS status Ended for HL403159+4.p
39310.23/6117.60	% SZS status Started for HL403162+5.p
39310.23/6117.60	% SZS status GaveUp for HL403162+5.p
39310.23/6117.60	% SZS status Ended for HL403162+5.p
39333.17/6120.58	% SZS status Started for HL403160+4.p
39333.17/6120.58	% SZS status GaveUp for HL403160+4.p
39333.17/6120.58	eprover: CPU time limit exceeded, terminating
39333.17/6120.58	% SZS status Ended for HL403160+4.p
39333.17/6120.65	% SZS status Started for HL403163+5.p
39333.17/6120.65	% SZS status GaveUp for HL403163+5.p
39333.17/6120.65	% SZS status Ended for HL403163+5.p
39368.24/6125.29	% SZS status Started for HL403161+4.p
39368.24/6125.29	% SZS status GaveUp for HL403161+4.p
39368.24/6125.29	eprover: CPU time limit exceeded, terminating
39368.24/6125.29	% SZS status Ended for HL403161+4.p
39378.00/6126.53	% SZS status Started for HL403164+5.p
39378.00/6126.53	% SZS status GaveUp for HL403164+5.p
39378.00/6126.53	% SZS status Ended for HL403164+5.p
39394.00/6128.77	% SZS status Started for HL403162+4.p
39394.00/6128.77	% SZS status GaveUp for HL403162+4.p
39394.00/6128.77	eprover: CPU time limit exceeded, terminating
39394.00/6128.77	% SZS status Ended for HL403162+4.p
39404.54/6130.20	% SZS status Started for HL403165+5.p
39404.54/6130.20	% SZS status GaveUp for HL403165+5.p
39404.54/6130.20	% SZS status Ended for HL403165+5.p
39441.01/6134.96	% SZS status Started for HL403166+5.p
39441.01/6134.96	% SZS status GaveUp for HL403166+5.p
39441.01/6134.96	% SZS status Ended for HL403166+5.p
39451.05/6136.23	% SZS status Started for HL403163+4.p
39451.05/6136.23	% SZS status GaveUp for HL403163+4.p
39451.05/6136.23	eprover: CPU time limit exceeded, terminating
39451.05/6136.23	% SZS status Ended for HL403163+4.p
39469.83/6138.58	% SZS status Started for HL403168+5.p
39469.83/6138.58	% SZS status GaveUp for HL403168+5.p
39469.83/6138.58	% SZS status Ended for HL403168+5.p
39474.77/6139.19	% SZS status Started for HL403164+4.p
39474.77/6139.19	% SZS status GaveUp for HL403164+4.p
39474.77/6139.19	eprover: CPU time limit exceeded, terminating
39474.77/6139.19	% SZS status Ended for HL403164+4.p
39511.36/6143.89	% SZS status Started for HL403169+5.p
39511.36/6143.89	% SZS status GaveUp for HL403169+5.p
39511.36/6143.89	% SZS status Ended for HL403169+5.p
39512.99/6144.02	% SZS status Started for HL403165+4.p
39512.99/6144.02	% SZS status GaveUp for HL403165+4.p
39512.99/6144.02	eprover: CPU time limit exceeded, terminating
39512.99/6144.02	% SZS status Ended for HL403165+4.p
39540.33/6147.47	% SZS status Started for HL403166+4.p
39540.33/6147.47	% SZS status GaveUp for HL403166+4.p
39540.33/6147.47	eprover: CPU time limit exceeded, terminating
39540.33/6147.47	% SZS status Ended for HL403166+4.p
39540.88/6147.61	% SZS status Started for HL403170+5.p
39540.88/6147.61	% SZS status GaveUp for HL403170+5.p
39540.88/6147.61	% SZS status Ended for HL403170+5.p
39576.20/6152.01	% SZS status Started for HL403168+4.p
39576.20/6152.01	% SZS status GaveUp for HL403168+4.p
39576.20/6152.01	eprover: CPU time limit exceeded, terminating
39576.20/6152.01	% SZS status Ended for HL403168+4.p
39583.49/6152.98	% SZS status Started for HL403171+5.p
39583.49/6152.98	% SZS status GaveUp for HL403171+5.p
39583.49/6152.98	% SZS status Ended for HL403171+5.p
39606.00/6155.90	% SZS status Started for HL403169+4.p
39606.00/6155.90	% SZS status GaveUp for HL403169+4.p
39606.00/6155.90	eprover: CPU time limit exceeded, terminating
39606.00/6155.90	% SZS status Ended for HL403169+4.p
39611.52/6156.55	% SZS status Started for HL403172+5.p
39611.52/6156.55	% SZS status GaveUp for HL403172+5.p
39611.52/6156.55	% SZS status Ended for HL403172+5.p
39647.04/6161.06	% SZS status Started for HL403173+5.p
39647.04/6161.06	% SZS status GaveUp for HL403173+5.p
39647.04/6161.06	% SZS status Ended for HL403173+5.p
39648.58/6161.32	% SZS status Started for HL403170+4.p
39648.58/6161.32	% SZS status GaveUp for HL403170+4.p
39648.58/6161.32	eprover: CPU time limit exceeded, terminating
39648.58/6161.32	% SZS status Ended for HL403170+4.p
39677.75/6165.04	% SZS status Started for HL403171+4.p
39677.75/6165.04	% SZS status GaveUp for HL403171+4.p
39677.75/6165.04	eprover: CPU time limit exceeded, terminating
39677.75/6165.04	% SZS status Ended for HL403171+4.p
39677.95/6165.08	% SZS status Started for HL403174+5.p
39677.95/6165.08	% SZS status GaveUp for HL403174+5.p
39677.95/6165.08	% SZS status Ended for HL403174+5.p
39710.86/6169.29	% SZS status Started for HL403172+4.p
39710.86/6169.29	% SZS status GaveUp for HL403172+4.p
39710.86/6169.29	eprover: CPU time limit exceeded, terminating
39710.86/6169.29	% SZS status Ended for HL403172+4.p
39716.47/6170.11	% SZS status Started for HL403175+5.p
39716.47/6170.11	% SZS status GaveUp for HL403175+5.p
39716.47/6170.11	% SZS status Ended for HL403175+5.p
39741.52/6173.20	% SZS status Started for HL403173+4.p
39741.52/6173.20	% SZS status GaveUp for HL403173+4.p
39741.52/6173.20	eprover: CPU time limit exceeded, terminating
39741.52/6173.20	% SZS status Ended for HL403173+4.p
39749.25/6174.19	% SZS status Started for HL403176+5.p
39749.25/6174.19	% SZS status GaveUp for HL403176+5.p
39749.25/6174.19	% SZS status Ended for HL403176+5.p
39781.86/6178.41	% SZS status Started for HL403177+5.p
39781.86/6178.41	% SZS status GaveUp for HL403177+5.p
39781.86/6178.41	% SZS status Ended for HL403177+5.p
39785.28/6178.81	% SZS status Started for HL403174+4.p
39785.28/6178.81	% SZS status GaveUp for HL403174+4.p
39785.28/6178.81	eprover: CPU time limit exceeded, terminating
39785.28/6178.81	% SZS status Ended for HL403174+4.p
39810.52/6182.13	% SZS status Started for HL403175+4.p
39810.52/6182.13	% SZS status GaveUp for HL403175+4.p
39810.52/6182.13	eprover: CPU time limit exceeded, terminating
39810.52/6182.13	% SZS status Ended for HL403175+4.p
39811.58/6182.25	% SZS status Started for HL403178+5.p
39811.58/6182.25	% SZS status GaveUp for HL403178+5.p
39811.58/6182.25	% SZS status Ended for HL403178+5.p
39843.57/6186.52	% SZS status Started for HL403176+4.p
39843.57/6186.52	% SZS status GaveUp for HL403176+4.p
39843.57/6186.52	eprover: CPU time limit exceeded, terminating
39843.57/6186.52	% SZS status Ended for HL403176+4.p
39851.38/6187.47	% SZS status Started for HL403179+5.p
39851.38/6187.47	% SZS status GaveUp for HL403179+5.p
39851.38/6187.47	% SZS status Ended for HL403179+5.p
39879.67/6191.12	% SZS status Started for HL403177+4.p
39879.67/6191.12	% SZS status GaveUp for HL403177+4.p
39879.67/6191.12	eprover: CPU time limit exceeded, terminating
39879.67/6191.12	% SZS status Ended for HL403177+4.p
39880.89/6191.21	% SZS status Started for HL403180+5.p
39880.89/6191.21	% SZS status GaveUp for HL403180+5.p
39880.89/6191.21	% SZS status Ended for HL403180+5.p
39912.93/6195.49	% SZS status Started for HL403182+5.p
39912.93/6195.49	% SZS status GaveUp for HL403182+5.p
39912.93/6195.49	% SZS status Ended for HL403182+5.p
39923.18/6196.86	% SZS status Started for HL403178+4.p
39923.18/6196.86	% SZS status GaveUp for HL403178+4.p
39923.18/6196.86	eprover: CPU time limit exceeded, terminating
39923.18/6196.86	% SZS status Ended for HL403178+4.p
39947.24/6199.94	% SZS status Started for HL403179+4.p
39947.24/6199.94	% SZS status GaveUp for HL403179+4.p
39947.24/6199.94	eprover: CPU time limit exceeded, terminating
39947.24/6199.94	% SZS status Ended for HL403179+4.p
39956.18/6201.12	% SZS status Started for HL403183+5.p
39956.18/6201.12	% SZS status GaveUp for HL403183+5.p
39956.18/6201.12	% SZS status Ended for HL403183+5.p
39985.72/6204.81	% SZS status Started for HL403184+5.p
39985.72/6204.81	% SZS status GaveUp for HL403184+5.p
39985.72/6204.81	% SZS status Ended for HL403184+5.p
39987.48/6205.03	% SZS status Started for HL403180+4.p
39987.48/6205.03	% SZS status GaveUp for HL403180+4.p
39987.48/6205.03	eprover: CPU time limit exceeded, terminating
39987.48/6205.03	% SZS status Ended for HL403180+4.p
40009.03/6207.78	% SZS status Started for HL403182+4.p
40009.03/6207.78	% SZS status GaveUp for HL403182+4.p
40009.03/6207.78	eprover: CPU time limit exceeded, terminating
40009.03/6207.78	% SZS status Ended for HL403182+4.p
40021.93/6209.35	% SZS status Started for HL403185+5.p
40021.93/6209.35	% SZS status GaveUp for HL403185+5.p
40021.93/6209.35	% SZS status Ended for HL403185+5.p
40054.04/6213.50	% SZS status Started for HL403183+4.p
40054.04/6213.50	% SZS status GaveUp for HL403183+4.p
40054.04/6213.50	eprover: CPU time limit exceeded, terminating
40054.04/6213.50	% SZS status Ended for HL403183+4.p
40056.48/6213.76	% SZS status Started for HL403186+5.p
40056.48/6213.76	% SZS status GaveUp for HL403186+5.p
40056.48/6213.76	% SZS status Ended for HL403186+5.p
40076.83/6216.31	% SZS status Started for HL403184+4.p
40076.83/6216.31	% SZS status GaveUp for HL403184+4.p
40076.83/6216.31	eprover: CPU time limit exceeded, terminating
40076.83/6216.31	% SZS status Ended for HL403184+4.p
40079.19/6216.61	% SZS status Started for HL403188+5.p
40079.19/6216.61	% SZS status GaveUp for HL403188+5.p
40079.19/6216.61	% SZS status Ended for HL403188+5.p
40106.08/6219.98	% SZS status Started for HL403189+5.p
40106.08/6219.98	% SZS status Theorem for HL403189+5.p
40106.08/6219.98	% SZS status Ended for HL403189+5.p
40125.49/6222.43	% SZS status Started for HL403185+4.p
40125.49/6222.43	% SZS status GaveUp for HL403185+4.p
40125.49/6222.43	eprover: CPU time limit exceeded, terminating
40125.49/6222.43	% SZS status Ended for HL403185+4.p
40147.01/6225.14	% SZS status Started for HL403190+5.p
40147.01/6225.14	% SZS status GaveUp for HL403190+5.p
40147.01/6225.14	% SZS status Ended for HL403190+5.p
40155.69/6226.24	% SZS status Started for HL403186+4.p
40155.69/6226.24	% SZS status GaveUp for HL403186+4.p
40155.69/6226.24	eprover: CPU time limit exceeded, terminating
40155.69/6226.24	% SZS status Ended for HL403186+4.p
40176.04/6228.78	% SZS status Started for HL403191+5.p
40176.04/6228.78	% SZS status GaveUp for HL403191+5.p
40176.04/6228.78	% SZS status Ended for HL403191+5.p
40187.22/6230.18	% SZS status Started for HL403188+4.p
40187.22/6230.18	% SZS status GaveUp for HL403188+4.p
40187.22/6230.18	eprover: CPU time limit exceeded, terminating
40187.22/6230.18	% SZS status Ended for HL403188+4.p
40198.91/6231.70	% SZS status Started for HL403192+5.p
40198.91/6231.70	% SZS status Theorem for HL403192+5.p
40198.91/6231.70	% SZS status Ended for HL403192+5.p
40221.45/6234.53	% SZS status Started for HL403189+4.p
40221.45/6234.53	% SZS status GaveUp for HL403189+4.p
40221.45/6234.53	eprover: CPU time limit exceeded, terminating
40221.45/6234.53	% SZS status Ended for HL403189+4.p
40247.54/6237.81	% SZS status Started for HL403193+5.p
40247.54/6237.81	% SZS status GaveUp for HL403193+5.p
40247.54/6237.81	% SZS status Ended for HL403193+5.p
40254.42/6238.66	% SZS status Started for HL403190+4.p
40254.42/6238.66	% SZS status GaveUp for HL403190+4.p
40254.42/6238.66	eprover: CPU time limit exceeded, terminating
40254.42/6238.66	% SZS status Ended for HL403190+4.p
40269.21/6240.58	% SZS status Started for HL403194+5.p
40269.21/6240.58	% SZS status GaveUp for HL403194+5.p
40269.21/6240.58	% SZS status Ended for HL403194+5.p
40277.56/6241.59	% SZS status Started for HL403191+4.p
40277.56/6241.59	% SZS status GaveUp for HL403191+4.p
40277.56/6241.59	eprover: CPU time limit exceeded, terminating
40277.56/6241.59	% SZS status Ended for HL403191+4.p
40316.48/6246.52	% SZS status Started for HL403195+5.p
40316.48/6246.52	% SZS status GaveUp for HL403195+5.p
40316.48/6246.52	% SZS status Ended for HL403195+5.p
40325.23/6247.60	% SZS status Started for HL403192+4.p
40325.23/6247.60	% SZS status GaveUp for HL403192+4.p
40325.23/6247.60	eprover: CPU time limit exceeded, terminating
40325.23/6247.60	% SZS status Ended for HL403192+4.p
40338.00/6249.22	% SZS status Started for HL403197+5.p
40338.00/6249.22	% SZS status GaveUp for HL403197+5.p
40338.00/6249.22	% SZS status Ended for HL403197+5.p
40358.00/6251.70	% SZS status Started for HL403193+4.p
40358.00/6251.70	% SZS status GaveUp for HL403193+4.p
40358.00/6251.70	eprover: CPU time limit exceeded, terminating
40358.00/6251.70	% SZS status Ended for HL403193+4.p
40385.20/6255.25	% SZS status Started for HL403198+5.p
40385.20/6255.25	% SZS status GaveUp for HL403198+5.p
40385.20/6255.25	% SZS status Ended for HL403198+5.p
40385.20/6255.26	% SZS status Started for HL403194+4.p
40385.20/6255.26	% SZS status GaveUp for HL403194+4.p
40385.20/6255.26	eprover: CPU time limit exceeded, terminating
40385.20/6255.26	% SZS status Ended for HL403194+4.p
40408.00/6258.13	% SZS status Started for HL403200+5.p
40408.00/6258.13	% SZS status GaveUp for HL403200+5.p
40408.00/6258.13	% SZS status Ended for HL403200+5.p
40420.81/6259.66	% SZS status Started for HL403195+4.p
40420.81/6259.66	% SZS status GaveUp for HL403195+4.p
40420.81/6259.66	eprover: CPU time limit exceeded, terminating
40420.81/6259.66	% SZS status Ended for HL403195+4.p
40455.58/6264.05	% SZS status Started for HL403197+4.p
40455.58/6264.05	% SZS status GaveUp for HL403197+4.p
40455.58/6264.05	eprover: CPU time limit exceeded, terminating
40455.58/6264.05	% SZS status Ended for HL403197+4.p
40455.97/6264.13	% SZS status Started for HL403202+5.p
40455.97/6264.13	% SZS status GaveUp for HL403202+5.p
40455.97/6264.13	% SZS status Ended for HL403202+5.p
40479.72/6267.05	% SZS status Started for HL403203+5.p
40479.72/6267.05	% SZS status GaveUp for HL403203+5.p
40479.72/6267.05	% SZS status Ended for HL403203+5.p
40481.21/6267.29	% SZS status Started for HL403198+4.p
40481.21/6267.29	% SZS status GaveUp for HL403198+4.p
40481.21/6267.29	eprover: CPU time limit exceeded, terminating
40481.21/6267.29	% SZS status Ended for HL403198+4.p
40525.18/6272.84	% SZS status Started for HL403200+4.p
40525.18/6272.84	% SZS status GaveUp for HL403200+4.p
40525.18/6272.84	eprover: CPU time limit exceeded, terminating
40525.18/6272.84	% SZS status Ended for HL403200+4.p
40526.21/6272.97	% SZS status Started for HL403205+5.p
40526.21/6272.97	% SZS status GaveUp for HL403205+5.p
40526.21/6272.97	% SZS status Ended for HL403205+5.p
40548.71/6275.75	% SZS status Started for HL403207+5.p
40548.71/6275.75	% SZS status GaveUp for HL403207+5.p
40548.71/6275.75	% SZS status Ended for HL403207+5.p
40557.64/6276.92	% SZS status Started for HL403202+4.p
40557.64/6276.92	% SZS status GaveUp for HL403202+4.p
40557.64/6276.92	eprover: CPU time limit exceeded, terminating
40557.64/6276.92	% SZS status Ended for HL403202+4.p
40586.80/6280.51	% SZS status Started for HL403203+4.p
40586.80/6280.51	% SZS status GaveUp for HL403203+4.p
40586.80/6280.51	eprover: CPU time limit exceeded, terminating
40586.80/6280.51	% SZS status Ended for HL403203+4.p
40622.29/6284.96	% SZS status Started for HL403205+4.p
40622.29/6284.96	% SZS status GaveUp for HL403205+4.p
40622.29/6284.96	eprover: CPU time limit exceeded, terminating
40622.29/6284.96	% SZS status Ended for HL403205+4.p
40654.82/6289.06	% SZS status Started for HL403207+4.p
40654.82/6289.06	% SZS status GaveUp for HL403207+4.p
40654.82/6289.06	eprover: CPU time limit exceeded, terminating
40654.82/6289.06	% SZS status Ended for HL403207+4.p
40679.10/6292.18	% SZS status Started for HL403208+4.p
40679.10/6292.18	% SZS status GaveUp for HL403208+4.p
40679.10/6292.18	eprover: CPU time limit exceeded, terminating
40679.10/6292.18	% SZS status Ended for HL403208+4.p
40719.61/6297.19	% SZS status Started for HL403208+5.p
40719.61/6297.19	% SZS status GaveUp for HL403208+5.p
40719.61/6297.19	% SZS status Ended for HL403208+5.p
40726.88/6298.13	% SZS status Started for HL403209+4.p
40726.88/6298.13	% SZS status GaveUp for HL403209+4.p
40726.88/6298.13	eprover: CPU time limit exceeded, terminating
40726.88/6298.13	% SZS status Ended for HL403209+4.p
40737.73/6299.47	% SZS status Started for HL403209+5.p
40737.73/6299.47	% SZS status GaveUp for HL403209+5.p
40737.73/6299.47	% SZS status Ended for HL403209+5.p
40757.64/6301.98	% SZS status Started for HL403210+4.p
40757.64/6301.98	% SZS status GaveUp for HL403210+4.p
40757.64/6301.98	eprover: CPU time limit exceeded, terminating
40757.64/6301.98	% SZS status Ended for HL403210+4.p
40782.10/6305.07	% SZS status Started for HL403210+5.p
40782.10/6305.07	% SZS status GaveUp for HL403210+5.p
40782.10/6305.07	eprover: CPU time limit exceeded, terminating
40782.10/6305.07	% SZS status Ended for HL403210+5.p
40821.29/6309.98	% SZS status Started for HL403211+4.p
40821.29/6309.98	% SZS status GaveUp for HL403211+4.p
40821.29/6309.98	eprover: CPU time limit exceeded, terminating
40821.29/6309.98	% SZS status Ended for HL403211+4.p
40845.61/6313.02	% SZS status Started for HL403211+5.p
40845.61/6313.02	% SZS status GaveUp for HL403211+5.p
40845.61/6313.02	% SZS status Ended for HL403211+5.p
40879.18/6317.28	% SZS status Started for HL403212+4.p
40879.18/6317.28	% SZS status GaveUp for HL403212+4.p
40879.18/6317.28	eprover: CPU time limit exceeded, terminating
40879.18/6317.28	% SZS status Ended for HL403212+4.p
40910.47/6321.27	% SZS status Started for HL403212+5.p
40910.47/6321.27	% SZS status GaveUp for HL403212+5.p
40910.47/6321.27	eprover: CPU time limit exceeded, terminating
40910.47/6321.27	% SZS status Ended for HL403212+5.p
40927.67/6323.05	% SZS status Started for HL403213+4.p
40927.67/6323.05	% SZS status GaveUp for HL403213+4.p
40927.67/6323.05	eprover: CPU time limit exceeded, terminating
40927.67/6323.05	% SZS status Ended for HL403213+4.p
40937.82/6324.37	% SZS status Started for HL403213+5.p
40937.82/6324.37	% SZS status GaveUp for HL403213+5.p
40937.82/6324.37	eprover: CPU time limit exceeded, terminating
40937.82/6324.37	% SZS status Ended for HL403213+5.p
40958.79/6327.02	% SZS status Started for HL403214+4.p
40958.79/6327.02	% SZS status GaveUp for HL403214+4.p
40958.79/6327.02	eprover: CPU time limit exceeded, terminating
40958.79/6327.02	% SZS status Ended for HL403214+4.p
40978.98/6329.54	% SZS status Started for HL403214+5.p
40978.98/6329.54	% SZS status GaveUp for HL403214+5.p
40978.98/6329.54	% SZS status Ended for HL403214+5.p
41022.91/6335.05	% SZS status Started for HL403216+4.p
41022.91/6335.05	% SZS status GaveUp for HL403216+4.p
41022.91/6335.05	eprover: CPU time limit exceeded, terminating
41022.91/6335.05	% SZS status Ended for HL403216+4.p
41041.39/6337.40	% SZS status Started for HL403216+5.p
41041.39/6337.40	% SZS status GaveUp for HL403216+5.p
41041.39/6337.40	eprover: CPU time limit exceeded, terminating
41041.39/6337.40	% SZS status Ended for HL403216+5.p
41080.59/6342.32	% SZS status Started for HL403217+4.p
41080.59/6342.32	% SZS status GaveUp for HL403217+4.p
41080.59/6342.32	eprover: CPU time limit exceeded, terminating
41080.59/6342.32	% SZS status Ended for HL403217+4.p
41108.24/6345.86	% SZS status Started for HL403217+5.p
41108.24/6345.86	% SZS status GaveUp for HL403217+5.p
41108.24/6345.86	eprover: CPU time limit exceeded, terminating
41108.24/6345.86	% SZS status Ended for HL403217+5.p
41125.53/6348.02	% SZS status Started for HL403218+4.p
41125.53/6348.02	% SZS status GaveUp for HL403218+4.p
41125.53/6348.02	eprover: CPU time limit exceeded, terminating
41125.53/6348.02	% SZS status Ended for HL403218+4.p
41133.26/6348.96	% SZS status Started for HL403218+5.p
41133.26/6348.96	% SZS status GaveUp for HL403218+5.p
41133.26/6348.96	eprover: CPU time limit exceeded, terminating
41133.26/6348.96	% SZS status Ended for HL403218+5.p
41157.29/6352.01	% SZS status Started for HL403220+4.p
41157.29/6352.01	% SZS status GaveUp for HL403220+4.p
41157.29/6352.01	eprover: CPU time limit exceeded, terminating
41157.29/6352.01	% SZS status Ended for HL403220+4.p
41176.97/6354.48	% SZS status Started for HL403220+5.p
41176.97/6354.48	% SZS status GaveUp for HL403220+5.p
41176.97/6354.48	eprover: CPU time limit exceeded, terminating
41176.97/6354.48	% SZS status Ended for HL403220+5.p
41221.19/6360.04	% SZS status Started for HL403221+4.p
41221.19/6360.04	% SZS status GaveUp for HL403221+4.p
41221.19/6360.04	eprover: CPU time limit exceeded, terminating
41221.19/6360.04	% SZS status Ended for HL403221+4.p
41240.93/6362.52	% SZS status Started for HL403221+5.p
41240.93/6362.52	% SZS status GaveUp for HL403221+5.p
41240.93/6362.52	eprover: CPU time limit exceeded, terminating
41240.93/6362.52	% SZS status Ended for HL403221+5.p
41280.75/6367.55	% SZS status Started for HL403222+4.p
41280.75/6367.55	% SZS status GaveUp for HL403222+4.p
41280.75/6367.55	eprover: CPU time limit exceeded, terminating
41280.75/6367.55	% SZS status Ended for HL403222+4.p
41303.96/6370.52	% SZS status Started for HL403222+5.p
41303.96/6370.52	% SZS status GaveUp for HL403222+5.p
41303.96/6370.52	eprover: CPU time limit exceeded, terminating
41303.96/6370.52	% SZS status Ended for HL403222+5.p
41326.57/6373.36	% SZS status Started for HL403223+5.p
41326.57/6373.36	% SZS status GaveUp for HL403223+5.p
41326.57/6373.36	eprover: CPU time limit exceeded, terminating
41326.57/6373.36	% SZS status Ended for HL403223+5.p
41327.15/6373.39	% SZS status Started for HL403223+4.p
41327.15/6373.39	% SZS status GaveUp for HL403223+4.p
41327.15/6373.39	eprover: CPU time limit exceeded, terminating
41327.15/6373.39	% SZS status Ended for HL403223+4.p
41357.28/6377.27	% SZS status Started for HL403224+4.p
41357.28/6377.27	% SZS status GaveUp for HL403224+4.p
41357.28/6377.27	eprover: CPU time limit exceeded, terminating
41357.28/6377.27	% SZS status Ended for HL403224+4.p
41370.64/6378.95	% SZS status Started for HL403224+5.p
41370.64/6378.95	% SZS status GaveUp for HL403224+5.p
41370.64/6378.95	% SZS status Ended for HL403224+5.p
41420.48/6385.14	% SZS status Started for HL403225+4.p
41420.48/6385.14	% SZS status GaveUp for HL403225+4.p
41420.48/6385.14	eprover: CPU time limit exceeded, terminating
41420.48/6385.14	% SZS status Ended for HL403225+4.p
41430.68/6386.56	% SZS status Started for HL403225+5.p
41430.68/6386.56	% SZS status GaveUp for HL403225+5.p
41430.68/6386.56	eprover: CPU time limit exceeded, terminating
41430.68/6386.56	% SZS status Ended for HL403225+5.p
41480.74/6392.74	% SZS status Started for HL403226+4.p
41480.74/6392.74	% SZS status GaveUp for HL403226+4.p
41480.74/6392.74	eprover: CPU time limit exceeded, terminating
41480.74/6392.74	% SZS status Ended for HL403226+4.p
41499.79/6395.15	% SZS status Started for HL403226+5.p
41499.79/6395.15	% SZS status GaveUp for HL403226+5.p
41499.79/6395.15	eprover: CPU time limit exceeded, terminating
41499.79/6395.15	% SZS status Ended for HL403226+5.p
41523.41/6398.14	% SZS status Started for HL403228+5.p
41523.41/6398.14	% SZS status GaveUp for HL403228+5.p
41523.41/6398.14	eprover: CPU time limit exceeded, terminating
41523.41/6398.14	% SZS status Ended for HL403228+5.p
41528.78/6398.81	% SZS status Started for HL403228+4.p
41528.78/6398.81	% SZS status GaveUp for HL403228+4.p
41528.78/6398.81	eprover: CPU time limit exceeded, terminating
41528.78/6398.81	% SZS status Ended for HL403228+4.p
41559.93/6402.70	% SZS status Started for HL403229+4.p
41559.93/6402.70	% SZS status GaveUp for HL403229+4.p
41559.93/6402.70	eprover: CPU time limit exceeded, terminating
41559.93/6402.70	% SZS status Ended for HL403229+4.p
41560.54/6402.87	% SZS status Started for HL403229+5.p
41560.54/6402.87	% SZS status GaveUp for HL403229+5.p
41560.54/6402.87	eprover: CPU time limit exceeded, terminating
41560.54/6402.87	% SZS status Ended for HL403229+5.p
41622.04/6410.58	% SZS status Started for HL403230+4.p
41622.04/6410.58	% SZS status GaveUp for HL403230+4.p
41622.04/6410.58	eprover: CPU time limit exceeded, terminating
41622.04/6410.58	% SZS status Ended for HL403230+4.p
41629.03/6411.50	% SZS status Started for HL403230+5.p
41629.03/6411.50	% SZS status GaveUp for HL403230+5.p
41629.03/6411.50	eprover: CPU time limit exceeded, terminating
41629.03/6411.50	% SZS status Ended for HL403230+5.p
41679.16/6417.69	% SZS status Started for HL403231+4.p
41679.16/6417.69	% SZS status GaveUp for HL403231+4.p
41679.16/6417.69	eprover: CPU time limit exceeded, terminating
41679.16/6417.69	% SZS status Ended for HL403231+4.p
41697.05/6420.00	% SZS status Started for HL403231+5.p
41697.05/6420.00	% SZS status GaveUp for HL403231+5.p
41697.05/6420.00	eprover: CPU time limit exceeded, terminating
41697.05/6420.00	% SZS status Ended for HL403231+5.p
41722.70/6423.18	% SZS status Started for HL403232+4.p
41722.70/6423.18	% SZS status GaveUp for HL403232+4.p
41722.70/6423.18	eprover: CPU time limit exceeded, terminating
41722.70/6423.18	% SZS status Ended for HL403232+4.p
41726.16/6423.67	% SZS status Started for HL403232+5.p
41726.16/6423.67	% SZS status GaveUp for HL403232+5.p
41726.16/6423.67	eprover: CPU time limit exceeded, terminating
41726.16/6423.67	% SZS status Ended for HL403232+5.p
41757.70/6427.60	% SZS status Started for HL403233+5.p
41757.70/6427.60	% SZS status GaveUp for HL403233+5.p
41757.70/6427.60	eprover: CPU time limit exceeded, terminating
41757.70/6427.60	% SZS status Ended for HL403233+5.p
41760.21/6427.89	% SZS status Started for HL403233+4.p
41760.21/6427.89	% SZS status GaveUp for HL403233+4.p
41760.21/6427.89	eprover: CPU time limit exceeded, terminating
41760.21/6427.89	% SZS status Ended for HL403233+4.p
41821.35/6435.65	% SZS status Started for HL403234+4.p
41821.35/6435.65	% SZS status GaveUp for HL403234+4.p
41821.35/6435.65	eprover: CPU time limit exceeded, terminating
41821.35/6435.65	% SZS status Ended for HL403234+4.p
41823.83/6436.02	% SZS status Started for HL403234+5.p
41823.83/6436.02	% SZS status GaveUp for HL403234+5.p
41823.83/6436.02	eprover: CPU time limit exceeded, terminating
41823.83/6436.02	% SZS status Ended for HL403234+5.p
41880.60/6443.02	% SZS status Started for HL403235+4.p
41880.60/6443.02	% SZS status GaveUp for HL403235+4.p
41880.60/6443.02	eprover: CPU time limit exceeded, terminating
41880.60/6443.02	% SZS status Ended for HL403235+4.p
41892.82/6444.64	% SZS status Started for HL403235+5.p
41892.82/6444.64	% SZS status GaveUp for HL403235+5.p
41892.82/6444.64	eprover: CPU time limit exceeded, terminating
41892.82/6444.64	% SZS status Ended for HL403235+5.p
41921.57/6448.24	% SZS status Started for HL403236+4.p
41921.57/6448.24	% SZS status GaveUp for HL403236+4.p
41921.57/6448.24	eprover: CPU time limit exceeded, terminating
41921.57/6448.24	% SZS status Ended for HL403236+4.p
41922.31/6448.28	% SZS status Started for HL403236+5.p
41922.31/6448.28	% SZS status GaveUp for HL403236+5.p
41922.31/6448.28	eprover: CPU time limit exceeded, terminating
41922.31/6448.28	% SZS status Ended for HL403236+5.p
41956.88/6452.64	% SZS status Started for HL403237+5.p
41956.88/6452.64	% SZS status GaveUp for HL403237+5.p
41956.88/6452.64	eprover: CPU time limit exceeded, terminating
41956.88/6452.64	% SZS status Ended for HL403237+5.p
41956.88/6452.70	% SZS status Started for HL403237+4.p
41956.88/6452.70	% SZS status GaveUp for HL403237+4.p
41956.88/6452.70	eprover: CPU time limit exceeded, terminating
41956.88/6452.70	% SZS status Ended for HL403237+4.p
42021.35/6460.73	% SZS status Started for HL403238+4.p
42021.35/6460.73	% SZS status GaveUp for HL403238+4.p
42021.35/6460.73	eprover: CPU time limit exceeded, terminating
42021.35/6460.73	% SZS status Ended for HL403238+4.p
42022.05/6460.84	% SZS status Started for HL403238+5.p
42022.05/6460.84	% SZS status GaveUp for HL403238+5.p
42022.05/6460.84	eprover: CPU time limit exceeded, terminating
42022.05/6460.84	% SZS status Ended for HL403238+5.p
42080.41/6468.17	% SZS status Started for HL403239+4.p
42080.41/6468.17	% SZS status GaveUp for HL403239+4.p
42080.41/6468.17	eprover: CPU time limit exceeded, terminating
42080.41/6468.17	% SZS status Ended for HL403239+4.p
42085.34/6468.85	% SZS status Started for HL403239+5.p
42085.34/6468.85	% SZS status GaveUp for HL403239+5.p
42085.34/6468.85	% SZS status Ended for HL403239+5.p
42090.66/6469.50	% SZS status Started for HL403243+5.p
42090.66/6469.50	% SZS status GaveUp for HL403243+5.p
42090.66/6469.50	% SZS status Ended for HL403243+5.p
42110.94/6472.02	% SZS status Started for HL403240+5.p
42110.94/6472.02	% SZS status GaveUp for HL403240+5.p
42110.94/6472.02	eprover: CPU time limit exceeded, terminating
42110.94/6472.02	% SZS status Ended for HL403240+5.p
42121.52/6473.37	% SZS status Started for HL403240+4.p
42121.52/6473.37	% SZS status GaveUp for HL403240+4.p
42121.52/6473.37	eprover: CPU time limit exceeded, terminating
42121.52/6473.37	% SZS status Ended for HL403240+4.p
42148.66/6476.79	% SZS status Started for HL403242+5.p
42148.66/6476.79	% SZS status GaveUp for HL403242+5.p
42148.66/6476.79	eprover: CPU time limit exceeded, terminating
42148.66/6476.79	% SZS status Ended for HL403242+5.p
42156.04/6477.69	% SZS status Started for HL403242+4.p
42156.04/6477.69	% SZS status GaveUp for HL403242+4.p
42156.04/6477.69	eprover: CPU time limit exceeded, terminating
42156.04/6477.69	% SZS status Ended for HL403242+4.p
42220.19/6485.78	% SZS status Started for HL403243+4.p
42220.19/6485.78	% SZS status GaveUp for HL403243+4.p
42220.19/6485.78	eprover: CPU time limit exceeded, terminating
42220.19/6485.78	% SZS status Ended for HL403243+4.p
42279.08/6493.10	% SZS status Started for HL403244+4.p
42279.08/6493.10	% SZS status GaveUp for HL403244+4.p
42279.08/6493.10	eprover: CPU time limit exceeded, terminating
42279.08/6493.10	% SZS status Ended for HL403244+4.p
42283.09/6493.65	% SZS status Started for HL403244+5.p
42283.09/6493.65	% SZS status GaveUp for HL403244+5.p
42283.09/6493.65	eprover: CPU time limit exceeded, terminating
42283.09/6493.65	% SZS status Ended for HL403244+5.p
42289.78/6494.47	% SZS status Started for HL403245+4.p
42289.78/6494.47	% SZS status GaveUp for HL403245+4.p
42289.78/6494.47	eprover: CPU time limit exceeded, terminating
42289.78/6494.47	% SZS status Ended for HL403245+4.p
42307.20/6496.64	% SZS status Started for HL403245+5.p
42307.20/6496.64	% SZS status GaveUp for HL403245+5.p
42307.20/6496.64	eprover: CPU time limit exceeded, terminating
42307.20/6496.64	% SZS status Ended for HL403245+5.p
42321.06/6498.41	% SZS status Started for HL403246+4.p
42321.06/6498.41	% SZS status GaveUp for HL403246+4.p
42321.06/6498.41	eprover: CPU time limit exceeded, terminating
42321.06/6498.41	% SZS status Ended for HL403246+4.p
42342.73/6501.17	% SZS status Started for HL403246+5.p
42342.73/6501.17	% SZS status GaveUp for HL403246+5.p
42342.73/6501.17	eprover: CPU time limit exceeded, terminating
42342.73/6501.17	% SZS status Ended for HL403246+5.p
42355.70/6502.84	% SZS status Started for HL403247+4.p
42355.70/6502.84	% SZS status GaveUp for HL403247+4.p
42355.70/6502.84	eprover: CPU time limit exceeded, terminating
42355.70/6502.84	% SZS status Ended for HL403247+4.p
42415.09/6510.24	% SZS status Started for HL403247+5.p
42415.09/6510.24	% SZS status GaveUp for HL403247+5.p
42415.09/6510.24	eprover: CPU time limit exceeded, terminating
42415.09/6510.24	% SZS status Ended for HL403247+5.p
42478.16/6518.25	% SZS status Started for HL403249+4.p
42478.16/6518.25	% SZS status GaveUp for HL403249+4.p
42478.16/6518.25	eprover: CPU time limit exceeded, terminating
42478.16/6518.25	% SZS status Ended for HL403249+4.p
42480.80/6518.58	% SZS status Started for HL403249+5.p
42480.80/6518.58	% SZS status GaveUp for HL403249+5.p
42480.80/6518.58	eprover: CPU time limit exceeded, terminating
42480.80/6518.58	% SZS status Ended for HL403249+5.p
42488.38/6519.47	% SZS status Started for HL403250+4.p
42488.38/6519.47	% SZS status GaveUp for HL403250+4.p
42488.38/6519.47	eprover: CPU time limit exceeded, terminating
42488.38/6519.47	% SZS status Ended for HL403250+4.p
42503.24/6521.37	% SZS status Started for HL403250+5.p
42503.24/6521.37	% SZS status GaveUp for HL403250+5.p
42503.24/6521.37	eprover: CPU time limit exceeded, terminating
42503.24/6521.37	% SZS status Ended for HL403250+5.p
42522.71/6523.87	% SZS status Started for HL403251+4.p
42522.71/6523.87	% SZS status GaveUp for HL403251+4.p
42522.71/6523.87	eprover: CPU time limit exceeded, terminating
42522.71/6523.87	% SZS status Ended for HL403251+4.p
42537.23/6525.64	% SZS status Started for HL403251+5.p
42537.23/6525.64	% SZS status GaveUp for HL403251+5.p
42537.23/6525.64	eprover: CPU time limit exceeded, terminating
42537.23/6525.64	% SZS status Ended for HL403251+5.p
42554.27/6527.81	% SZS status Started for HL403252+4.p
42554.27/6527.81	% SZS status GaveUp for HL403252+4.p
42554.27/6527.81	eprover: CPU time limit exceeded, terminating
42554.27/6527.81	% SZS status Ended for HL403252+4.p
42610.06/6534.83	% SZS status Started for HL403252+5.p
42610.06/6534.83	% SZS status GaveUp for HL403252+5.p
42610.06/6534.83	eprover: CPU time limit exceeded, terminating
42610.06/6534.83	% SZS status Ended for HL403252+5.p
42676.61/6543.23	% SZS status Started for HL403253+4.p
42676.61/6543.23	% SZS status GaveUp for HL403253+4.p
42676.61/6543.23	eprover: CPU time limit exceeded, terminating
42676.61/6543.23	% SZS status Ended for HL403253+4.p
42677.36/6543.26	% SZS status Started for HL403253+5.p
42677.36/6543.26	% SZS status GaveUp for HL403253+5.p
42677.36/6543.26	eprover: CPU time limit exceeded, terminating
42677.36/6543.26	% SZS status Ended for HL403253+5.p
42688.12/6544.70	% SZS status Started for HL403254+4.p
42688.12/6544.70	% SZS status GaveUp for HL403254+4.p
42688.12/6544.70	eprover: CPU time limit exceeded, terminating
42688.12/6544.70	% SZS status Ended for HL403254+4.p
42700.29/6546.24	% SZS status Started for HL403254+5.p
42700.29/6546.24	% SZS status GaveUp for HL403254+5.p
42700.29/6546.24	eprover: CPU time limit exceeded, terminating
42700.29/6546.24	% SZS status Ended for HL403254+5.p
42724.86/6549.28	% SZS status Started for HL403255+4.p
42724.86/6549.28	% SZS status GaveUp for HL403255+4.p
42724.86/6549.28	eprover: CPU time limit exceeded, terminating
42724.86/6549.28	% SZS status Ended for HL403255+4.p
42733.87/6550.42	% SZS status Started for HL403255+5.p
42733.87/6550.42	% SZS status GaveUp for HL403255+5.p
42733.87/6550.42	eprover: CPU time limit exceeded, terminating
42733.87/6550.42	% SZS status Ended for HL403255+5.p
42754.07/6553.02	% SZS status Started for HL403256+4.p
42754.07/6553.02	% SZS status GaveUp for HL403256+4.p
42754.07/6553.02	eprover: CPU time limit exceeded, terminating
42754.07/6553.02	% SZS status Ended for HL403256+4.p
42807.41/6559.65	% SZS status Started for HL403256+5.p
42807.41/6559.65	% SZS status GaveUp for HL403256+5.p
42807.41/6559.65	eprover: CPU time limit exceeded, terminating
42807.41/6559.65	% SZS status Ended for HL403256+5.p
42873.41/6567.96	% SZS status Started for HL403257+5.p
42873.41/6567.96	% SZS status GaveUp for HL403257+5.p
42873.41/6567.96	eprover: CPU time limit exceeded, terminating
42873.41/6567.96	% SZS status Ended for HL403257+5.p
42874.65/6568.18	% SZS status Started for HL403257+4.p
42874.65/6568.18	% SZS status GaveUp for HL403257+4.p
42874.65/6568.18	eprover: CPU time limit exceeded, terminating
42874.65/6568.18	% SZS status Ended for HL403257+4.p
42889.16/6569.94	% SZS status Started for HL403258+4.p
42889.16/6569.94	% SZS status GaveUp for HL403258+4.p
42889.16/6569.94	eprover: CPU time limit exceeded, terminating
42889.16/6569.94	% SZS status Ended for HL403258+4.p
42897.04/6570.94	% SZS status Started for HL403258+5.p
42897.04/6570.94	% SZS status GaveUp for HL403258+5.p
42897.04/6570.94	eprover: CPU time limit exceeded, terminating
42897.04/6570.94	% SZS status Ended for HL403258+5.p
42923.33/6574.25	% SZS status Started for HL403261+4.p
42923.33/6574.25	% SZS status GaveUp for HL403261+4.p
42923.33/6574.25	eprover: CPU time limit exceeded, terminating
42923.33/6574.25	% SZS status Ended for HL403261+4.p
42931.54/6575.33	% SZS status Started for HL403261+5.p
42931.54/6575.33	% SZS status GaveUp for HL403261+5.p
42931.54/6575.33	eprover: CPU time limit exceeded, terminating
42931.54/6575.33	% SZS status Ended for HL403261+5.p
42956.85/6578.56	% SZS status Started for HL403262+4.p
42956.85/6578.56	% SZS status GaveUp for HL403262+4.p
42956.85/6578.56	eprover: CPU time limit exceeded, terminating
42956.85/6578.56	% SZS status Ended for HL403262+4.p
43002.98/6584.29	% SZS status Started for HL403262+5.p
43002.98/6584.29	% SZS status GaveUp for HL403262+5.p
43002.98/6584.29	eprover: CPU time limit exceeded, terminating
43002.98/6584.29	% SZS status Ended for HL403262+5.p
43070.61/6592.80	% SZS status Started for HL403263+5.p
43070.61/6592.80	% SZS status GaveUp for HL403263+5.p
43070.61/6592.80	eprover: CPU time limit exceeded, terminating
43070.61/6592.80	% SZS status Ended for HL403263+5.p
43073.04/6593.09	% SZS status Started for HL403263+4.p
43073.04/6593.09	% SZS status GaveUp for HL403263+4.p
43073.04/6593.09	eprover: CPU time limit exceeded, terminating
43073.04/6593.09	% SZS status Ended for HL403263+4.p
43090.32/6595.27	% SZS status Started for HL403264+4.p
43090.32/6595.27	% SZS status GaveUp for HL403264+4.p
43090.32/6595.27	eprover: CPU time limit exceeded, terminating
43090.32/6595.27	% SZS status Ended for HL403264+4.p
43095.29/6595.91	% SZS status Started for HL403264+5.p
43095.29/6595.91	% SZS status GaveUp for HL403264+5.p
43095.29/6595.91	eprover: CPU time limit exceeded, terminating
43095.29/6595.91	% SZS status Ended for HL403264+5.p
43122.26/6599.32	% SZS status Started for HL403265+4.p
43122.26/6599.32	% SZS status GaveUp for HL403265+4.p
43122.26/6599.32	eprover: CPU time limit exceeded, terminating
43122.26/6599.32	% SZS status Ended for HL403265+4.p
43128.54/6600.16	% SZS status Started for HL403265+5.p
43128.54/6600.16	% SZS status GaveUp for HL403265+5.p
43128.54/6600.16	eprover: CPU time limit exceeded, terminating
43128.54/6600.16	% SZS status Ended for HL403265+5.p
43158.28/6603.88	% SZS status Started for HL403267+4.p
43158.28/6603.88	% SZS status GaveUp for HL403267+4.p
43158.28/6603.88	eprover: CPU time limit exceeded, terminating
43158.28/6603.88	% SZS status Ended for HL403267+4.p
43199.10/6608.98	% SZS status Started for HL403267+5.p
43199.10/6608.98	% SZS status GaveUp for HL403267+5.p
43199.10/6608.98	eprover: CPU time limit exceeded, terminating
43199.10/6608.98	% SZS status Ended for HL403267+5.p
43268.71/6617.76	% SZS status Started for HL403268+5.p
43268.71/6617.76	% SZS status GaveUp for HL403268+5.p
43268.71/6617.76	eprover: CPU time limit exceeded, terminating
43268.71/6617.76	% SZS status Ended for HL403268+5.p
43269.72/6617.89	% SZS status Started for HL403268+4.p
43269.72/6617.89	% SZS status GaveUp for HL403268+4.p
43269.72/6617.89	eprover: CPU time limit exceeded, terminating
43269.72/6617.89	% SZS status Ended for HL403268+4.p
43289.62/6620.43	% SZS status Started for HL403269+4.p
43289.62/6620.43	% SZS status GaveUp for HL403269+4.p
43289.62/6620.43	eprover: CPU time limit exceeded, terminating
43289.62/6620.43	% SZS status Ended for HL403269+4.p
43292.76/6620.80	% SZS status Started for HL403269+5.p
43292.76/6620.80	% SZS status GaveUp for HL403269+5.p
43292.76/6620.80	eprover: CPU time limit exceeded, terminating
43292.76/6620.80	% SZS status Ended for HL403269+5.p
43321.93/6624.56	% SZS status Started for HL403270+4.p
43321.93/6624.56	% SZS status GaveUp for HL403270+4.p
43321.93/6624.56	eprover: CPU time limit exceeded, terminating
43321.93/6624.56	% SZS status Ended for HL403270+4.p
43323.05/6624.82	% SZS status Started for HL403270+5.p
43323.05/6624.82	% SZS status GaveUp for HL403270+5.p
43323.05/6624.82	eprover: CPU time limit exceeded, terminating
43323.05/6624.82	% SZS status Ended for HL403270+5.p
43359.70/6629.05	% SZS status Started for HL403271+4.p
43359.70/6629.05	% SZS status GaveUp for HL403271+4.p
43359.70/6629.05	eprover: CPU time limit exceeded, terminating
43359.70/6629.05	% SZS status Ended for HL403271+4.p
43398.86/6634.00	% SZS status Started for HL403271+5.p
43398.86/6634.00	% SZS status GaveUp for HL403271+5.p
43398.86/6634.00	eprover: CPU time limit exceeded, terminating
43398.86/6634.00	% SZS status Ended for HL403271+5.p
43467.55/6642.64	% SZS status Started for HL403272+5.p
43467.55/6642.64	% SZS status GaveUp for HL403272+5.p
43467.55/6642.64	eprover: CPU time limit exceeded, terminating
43467.55/6642.64	% SZS status Ended for HL403272+5.p
43473.14/6643.34	% SZS status Started for HL403272+4.p
43473.14/6643.34	% SZS status GaveUp for HL403272+4.p
43473.14/6643.34	eprover: CPU time limit exceeded, terminating
43473.14/6643.34	% SZS status Ended for HL403272+4.p
43489.25/6645.45	% SZS status Started for HL403273+5.p
43489.25/6645.45	% SZS status GaveUp for HL403273+5.p
43489.25/6645.45	eprover: CPU time limit exceeded, terminating
43489.25/6645.45	% SZS status Ended for HL403273+5.p
43492.02/6645.71	% SZS status Started for HL403273+4.p
43492.02/6645.71	% SZS status GaveUp for HL403273+4.p
43492.02/6645.71	eprover: CPU time limit exceeded, terminating
43492.02/6645.71	% SZS status Ended for HL403273+4.p
43521.64/6649.54	% SZS status Started for HL403274+5.p
43521.64/6649.54	% SZS status GaveUp for HL403274+5.p
43521.64/6649.54	eprover: CPU time limit exceeded, terminating
43521.64/6649.54	% SZS status Ended for HL403274+5.p
43524.20/6649.83	% SZS status Started for HL403274+4.p
43524.20/6649.83	% SZS status GaveUp for HL403274+4.p
43524.20/6649.83	eprover: CPU time limit exceeded, terminating
43524.20/6649.83	% SZS status Ended for HL403274+4.p
43559.30/6654.23	% SZS status Started for HL403275+4.p
43559.30/6654.23	% SZS status GaveUp for HL403275+4.p
43559.30/6654.23	eprover: CPU time limit exceeded, terminating
43559.30/6654.23	% SZS status Ended for HL403275+4.p
43595.05/6658.74	% SZS status Started for HL403275+5.p
43595.05/6658.74	% SZS status GaveUp for HL403275+5.p
43595.05/6658.74	eprover: CPU time limit exceeded, terminating
43595.05/6658.74	% SZS status Ended for HL403275+5.p
43666.98/6667.89	% SZS status Started for HL403276+4.p
43666.98/6667.89	% SZS status GaveUp for HL403276+4.p
43666.98/6667.89	eprover: CPU time limit exceeded, terminating
43666.98/6667.89	% SZS status Ended for HL403276+4.p
43669.55/6668.19	% SZS status Started for HL403276+5.p
43669.55/6668.19	% SZS status GaveUp for HL403276+5.p
43669.55/6668.19	eprover: CPU time limit exceeded, terminating
43669.55/6668.19	% SZS status Ended for HL403276+5.p
43688.77/6670.66	% SZS status Started for HL403277+5.p
43688.77/6670.66	% SZS status GaveUp for HL403277+5.p
43688.77/6670.66	eprover: CPU time limit exceeded, terminating
43688.77/6670.66	% SZS status Ended for HL403277+5.p
43688.77/6670.74	% SZS status Started for HL403277+4.p
43688.77/6670.74	% SZS status GaveUp for HL403277+4.p
43688.77/6670.74	eprover: CPU time limit exceeded, terminating
43688.77/6670.74	% SZS status Ended for HL403277+4.p
43721.75/6674.63	% SZS status Started for HL403278+5.p
43721.75/6674.63	% SZS status GaveUp for HL403278+5.p
43721.75/6674.63	eprover: CPU time limit exceeded, terminating
43721.75/6674.63	% SZS status Ended for HL403278+5.p
43722.14/6674.75	% SZS status Started for HL403278+4.p
43722.14/6674.75	% SZS status GaveUp for HL403278+4.p
43722.14/6674.75	eprover: CPU time limit exceeded, terminating
43722.14/6674.75	% SZS status Ended for HL403278+4.p
43743.76/6677.37	% SZS status Started for HL403280+5.p
43743.76/6677.37	% SZS status GaveUp for HL403280+5.p
43743.76/6677.37	% SZS status Ended for HL403280+5.p
43760.82/6679.54	% SZS status Started for HL403279+4.p
43760.82/6679.54	% SZS status GaveUp for HL403279+4.p
43760.82/6679.54	eprover: CPU time limit exceeded, terminating
43760.82/6679.54	% SZS status Ended for HL403279+4.p
43762.16/6679.75	% SZS status Started for HL403281+5.p
43762.16/6679.75	% SZS status GaveUp for HL403281+5.p
43762.16/6679.75	% SZS status Ended for HL403281+5.p
43793.83/6683.75	% SZS status Started for HL403282+5.p
43793.83/6683.75	% SZS status GaveUp for HL403282+5.p
43793.83/6683.75	% SZS status Ended for HL403282+5.p
43794.65/6683.91	% SZS status Started for HL403279+5.p
43794.65/6683.91	% SZS status GaveUp for HL403279+5.p
43794.65/6683.91	eprover: CPU time limit exceeded, terminating
43794.65/6683.91	% SZS status Ended for HL403279+5.p
43831.44/6688.50	% SZS status Started for HL403284+5.p
43831.44/6688.50	% SZS status GaveUp for HL403284+5.p
43831.44/6688.50	% SZS status Ended for HL403284+5.p
43864.07/6692.60	% SZS status Started for HL403285+5.p
43864.07/6692.60	% SZS status GaveUp for HL403285+5.p
43864.07/6692.60	% SZS status Ended for HL403285+5.p
43870.23/6693.34	% SZS status Started for HL403280+4.p
43870.23/6693.34	% SZS status GaveUp for HL403280+4.p
43870.23/6693.34	eprover: CPU time limit exceeded, terminating
43870.23/6693.34	% SZS status Ended for HL403280+4.p
43891.98/6696.09	% SZS status Started for HL403281+4.p
43891.98/6696.09	% SZS status GaveUp for HL403281+4.p
43891.98/6696.09	eprover: CPU time limit exceeded, terminating
43891.98/6696.09	% SZS status Ended for HL403281+4.p
43902.12/6697.41	% SZS status Started for HL403286+5.p
43902.12/6697.41	% SZS status GaveUp for HL403286+5.p
43902.12/6697.41	% SZS status Ended for HL403286+5.p
43920.57/6699.73	% SZS status Started for HL403282+4.p
43920.57/6699.73	% SZS status GaveUp for HL403282+4.p
43920.57/6699.73	eprover: CPU time limit exceeded, terminating
43920.57/6699.73	% SZS status Ended for HL403282+4.p
43941.67/6702.32	% SZS status Started for HL403287+5.p
43941.67/6702.32	% SZS status GaveUp for HL403287+5.p
43941.67/6702.32	% SZS status Ended for HL403287+5.p
43946.80/6702.99	% SZS status Started for HL403284+4.p
43946.80/6702.99	% SZS status GaveUp for HL403284+4.p
43946.80/6702.99	eprover: CPU time limit exceeded, terminating
43946.80/6702.99	% SZS status Ended for HL403284+4.p
43961.76/6704.86	% SZS status Started for HL403285+4.p
43961.76/6704.86	% SZS status GaveUp for HL403285+4.p
43961.76/6704.86	eprover: CPU time limit exceeded, terminating
43961.76/6704.86	% SZS status Ended for HL403285+4.p
43973.07/6706.32	% SZS status Started for HL403288+5.p
43973.07/6706.32	% SZS status GaveUp for HL403288+5.p
43973.07/6706.32	% SZS status Ended for HL403288+5.p
43992.94/6708.86	% SZS status Started for HL403286+4.p
43992.94/6708.86	% SZS status GaveUp for HL403286+4.p
43992.94/6708.86	eprover: CPU time limit exceeded, terminating
43992.94/6708.86	% SZS status Ended for HL403286+4.p
44010.57/6711.08	% SZS status Started for HL403290+5.p
44010.57/6711.08	% SZS status Theorem for HL403290+5.p
44010.57/6711.08	% SZS status Ended for HL403290+5.p
44012.09/6711.30	% SZS status Started for HL403289+5.p
44012.09/6711.30	% SZS status GaveUp for HL403289+5.p
44012.09/6711.30	% SZS status Ended for HL403289+5.p
44062.31/6717.63	% SZS status Started for HL403287+4.p
44062.31/6717.63	% SZS status GaveUp for HL403287+4.p
44062.31/6717.63	eprover: CPU time limit exceeded, terminating
44062.31/6717.63	% SZS status Ended for HL403287+4.p
44083.30/6720.33	% SZS status Started for HL403293+5.p
44083.30/6720.33	% SZS status GaveUp for HL403293+5.p
44083.30/6720.33	% SZS status Ended for HL403293+5.p
44092.64/6721.46	% SZS status Started for HL403288+4.p
44092.64/6721.46	% SZS status GaveUp for HL403288+4.p
44092.64/6721.46	eprover: CPU time limit exceeded, terminating
44092.64/6721.46	% SZS status Ended for HL403288+4.p
44120.44/6724.93	% SZS status Started for HL403289+4.p
44120.44/6724.93	% SZS status GaveUp for HL403289+4.p
44120.44/6724.93	eprover: CPU time limit exceeded, terminating
44120.44/6724.93	% SZS status Ended for HL403289+4.p
44147.58/6728.39	% SZS status Started for HL403290+4.p
44147.58/6728.39	% SZS status GaveUp for HL403290+4.p
44147.58/6728.39	eprover: CPU time limit exceeded, terminating
44147.58/6728.39	% SZS status Ended for HL403290+4.p
44155.19/6729.39	% SZS status Started for HL403294+5.p
44155.19/6729.39	% SZS status GaveUp for HL403294+5.p
44155.19/6729.39	% SZS status Ended for HL403294+5.p
44174.38/6731.80	% SZS status Started for HL403291+4.p
44174.38/6731.80	% SZS status GaveUp for HL403291+4.p
44174.38/6731.80	eprover: CPU time limit exceeded, terminating
44174.38/6731.80	% SZS status Ended for HL403291+4.p
44188.67/6733.56	% SZS status Started for HL403291+5.p
44188.67/6733.56	% SZS status GaveUp for HL403291+5.p
44188.67/6733.56	eprover: CPU time limit exceeded, terminating
44188.67/6733.56	% SZS status Ended for HL403291+5.p
44191.59/6734.06	% SZS status Started for HL403295+5.p
44191.59/6734.06	% SZS status GaveUp for HL403295+5.p
44191.59/6734.06	% SZS status Ended for HL403295+5.p
44208.44/6736.10	% SZS status Started for HL403293+4.p
44208.44/6736.10	% SZS status GaveUp for HL403293+4.p
44208.44/6736.10	eprover: CPU time limit exceeded, terminating
44208.44/6736.10	% SZS status Ended for HL403293+4.p
44225.95/6738.36	% SZS status Started for HL403296+5.p
44225.95/6738.36	% SZS status GaveUp for HL403296+5.p
44225.95/6738.36	% SZS status Ended for HL403296+5.p
44259.88/6742.52	% SZS status Started for HL403297+5.p
44259.88/6742.52	% SZS status GaveUp for HL403297+5.p
44259.88/6742.52	% SZS status Ended for HL403297+5.p
44260.87/6742.70	% SZS status Started for HL403294+4.p
44260.87/6742.70	% SZS status GaveUp for HL403294+4.p
44260.87/6742.70	eprover: CPU time limit exceeded, terminating
44260.87/6742.70	% SZS status Ended for HL403294+4.p
44292.31/6746.64	% SZS status Started for HL403295+4.p
44292.31/6746.64	% SZS status GaveUp for HL403295+4.p
44292.31/6746.64	eprover: CPU time limit exceeded, terminating
44292.31/6746.64	% SZS status Ended for HL403295+4.p
44330.68/6751.49	% SZS status Started for HL403299+5.p
44330.68/6751.49	% SZS status GaveUp for HL403299+5.p
44330.68/6751.49	% SZS status Ended for HL403299+5.p
44347.50/6753.57	% SZS status Started for HL403296+4.p
44347.50/6753.57	% SZS status GaveUp for HL403296+4.p
44347.50/6753.57	eprover: CPU time limit exceeded, terminating
44347.50/6753.57	% SZS status Ended for HL403296+4.p
44363.30/6755.55	% SZS status Started for HL403300+5.p
44363.30/6755.55	% SZS status GaveUp for HL403300+5.p
44363.30/6755.55	% SZS status Ended for HL403300+5.p
44373.96/6756.87	% SZS status Started for HL403297+4.p
44373.96/6756.87	% SZS status GaveUp for HL403297+4.p
44373.96/6756.87	eprover: CPU time limit exceeded, terminating
44373.96/6756.87	% SZS status Ended for HL403297+4.p
44391.95/6759.13	% SZS status Started for HL403298+4.p
44391.95/6759.13	% SZS status GaveUp for HL403298+4.p
44391.95/6759.13	eprover: CPU time limit exceeded, terminating
44391.95/6759.13	% SZS status Ended for HL403298+4.p
44402.86/6760.54	% SZS status Started for HL403298+5.p
44402.86/6760.54	% SZS status GaveUp for HL403298+5.p
44402.86/6760.54	% SZS status Ended for HL403298+5.p
44418.95/6762.58	% SZS status Started for HL403301+5.p
44418.95/6762.58	% SZS status GaveUp for HL403301+5.p
44418.95/6762.58	% SZS status Ended for HL403301+5.p
44425.24/6763.42	% SZS status Started for HL403299+4.p
44425.24/6763.42	% SZS status GaveUp for HL403299+4.p
44425.24/6763.42	eprover: CPU time limit exceeded, terminating
44425.24/6763.42	% SZS status Ended for HL403299+4.p
44444.53/6765.77	% SZS status Started for HL403302+5.p
44444.53/6765.77	% SZS status GaveUp for HL403302+5.p
44444.53/6765.77	% SZS status Ended for HL403302+5.p
44462.20/6767.94	% SZS status Started for HL403300+4.p
44462.20/6767.94	% SZS status GaveUp for HL403300+4.p
44462.20/6767.94	eprover: CPU time limit exceeded, terminating
44462.20/6767.94	% SZS status Ended for HL403300+4.p
44472.91/6769.39	% SZS status Started for HL403303+5.p
44472.91/6769.39	% SZS status GaveUp for HL403303+5.p
44472.91/6769.39	% SZS status Ended for HL403303+5.p
44496.59/6772.29	% SZS status Started for HL403304+5.p
44496.59/6772.29	% SZS status GaveUp for HL403304+5.p
44496.59/6772.29	% SZS status Ended for HL403304+5.p
44529.71/6776.45	% SZS status Started for HL403301+4.p
44529.71/6776.45	% SZS status GaveUp for HL403301+4.p
44529.71/6776.45	eprover: CPU time limit exceeded, terminating
44529.71/6776.45	% SZS status Ended for HL403301+4.p
44532.49/6776.83	% SZS status Started for HL403305+5.p
44532.49/6776.83	% SZS status GaveUp for HL403305+5.p
44532.49/6776.83	% SZS status Ended for HL403305+5.p
44563.30/6780.72	% SZS status Started for HL403302+4.p
44563.30/6780.72	% SZS status GaveUp for HL403302+4.p
44563.30/6780.72	eprover: CPU time limit exceeded, terminating
44563.30/6780.72	% SZS status Ended for HL403302+4.p
44566.20/6781.14	% SZS status Started for HL403306+5.p
44566.20/6781.14	% SZS status GaveUp for HL403306+5.p
44566.20/6781.14	% SZS status Ended for HL403306+5.p
44592.29/6784.33	% SZS status Started for HL403303+4.p
44592.29/6784.33	% SZS status GaveUp for HL403303+4.p
44592.29/6784.33	eprover: CPU time limit exceeded, terminating
44592.29/6784.33	% SZS status Ended for HL403303+4.p
44602.88/6785.70	% SZS status Started for HL403307+5.p
44602.88/6785.70	% SZS status GaveUp for HL403307+5.p
44602.88/6785.70	% SZS status Ended for HL403307+5.p
44618.10/6787.54	% SZS status Started for HL403304+4.p
44618.10/6787.54	% SZS status GaveUp for HL403304+4.p
44618.10/6787.54	eprover: CPU time limit exceeded, terminating
44618.10/6787.54	% SZS status Ended for HL403304+4.p
44637.76/6790.04	% SZS status Started for HL403308+5.p
44637.76/6790.04	% SZS status GaveUp for HL403308+5.p
44637.76/6790.04	% SZS status Ended for HL403308+5.p
44643.46/6790.79	% SZS status Started for HL403305+4.p
44643.46/6790.79	% SZS status GaveUp for HL403305+4.p
44643.46/6790.79	eprover: CPU time limit exceeded, terminating
44643.46/6790.79	% SZS status Ended for HL403305+4.p
44672.21/6794.36	% SZS status Started for HL403306+4.p
44672.21/6794.36	% SZS status GaveUp for HL403306+4.p
44672.21/6794.36	eprover: CPU time limit exceeded, terminating
44672.21/6794.36	% SZS status Ended for HL403306+4.p
44673.86/6794.60	% SZS status Started for HL403309+5.p
44673.86/6794.60	% SZS status GaveUp for HL403309+5.p
44673.86/6794.60	% SZS status Ended for HL403309+5.p
44706.46/6798.74	% SZS status Started for HL403313+5.p
44706.46/6798.74	% SZS status GaveUp for HL403313+5.p
44706.46/6798.74	% SZS status Ended for HL403313+5.p
44729.16/6801.50	% SZS status Started for HL403307+4.p
44729.16/6801.50	% SZS status GaveUp for HL403307+4.p
44729.16/6801.50	eprover: CPU time limit exceeded, terminating
44729.16/6801.50	% SZS status Ended for HL403307+4.p
44740.58/6802.98	% SZS status Started for HL403314+5.p
44740.58/6802.98	% SZS status GaveUp for HL403314+5.p
44740.58/6802.98	% SZS status Ended for HL403314+5.p
44766.09/6806.15	% SZS status Started for HL403308+4.p
44766.09/6806.15	% SZS status GaveUp for HL403308+4.p
44766.09/6806.15	eprover: CPU time limit exceeded, terminating
44766.09/6806.15	% SZS status Ended for HL403308+4.p
44775.49/6807.38	% SZS status Started for HL403316+5.p
44775.49/6807.38	% SZS status GaveUp for HL403316+5.p
44775.49/6807.38	% SZS status Ended for HL403316+5.p
44791.53/6809.35	% SZS status Started for HL403309+4.p
44791.53/6809.35	% SZS status GaveUp for HL403309+4.p
44791.53/6809.35	eprover: CPU time limit exceeded, terminating
44791.53/6809.35	% SZS status Ended for HL403309+4.p
44809.76/6811.65	% SZS status Started for HL403317+5.p
44809.76/6811.65	% SZS status GaveUp for HL403317+5.p
44809.76/6811.65	% SZS status Ended for HL403317+5.p
44816.62/6812.52	% SZS status Started for HL403313+4.p
44816.62/6812.52	% SZS status GaveUp for HL403313+4.p
44816.62/6812.52	eprover: CPU time limit exceeded, terminating
44816.62/6812.52	% SZS status Ended for HL403313+4.p
44843.33/6815.88	% SZS status Started for HL403314+4.p
44843.33/6815.88	% SZS status GaveUp for HL403314+4.p
44843.33/6815.88	eprover: CPU time limit exceeded, terminating
44843.33/6815.88	% SZS status Ended for HL403314+4.p
44845.39/6816.18	% SZS status Started for HL403318+5.p
44845.39/6816.18	% SZS status GaveUp for HL403318+5.p
44845.39/6816.18	% SZS status Ended for HL403318+5.p
44872.33/6819.63	% SZS status Started for HL403316+4.p
44872.33/6819.63	% SZS status GaveUp for HL403316+4.p
44872.33/6819.63	eprover: CPU time limit exceeded, terminating
44872.33/6819.63	% SZS status Ended for HL403316+4.p
44878.66/6820.35	% SZS status Started for HL403319+5.p
44878.66/6820.35	% SZS status GaveUp for HL403319+5.p
44878.66/6820.35	% SZS status Ended for HL403319+5.p
44912.27/6824.61	% SZS status Started for HL403320+5.p
44912.27/6824.61	% SZS status GaveUp for HL403320+5.p
44912.27/6824.61	% SZS status Ended for HL403320+5.p
44927.05/6826.49	% SZS status Started for HL403317+4.p
44927.05/6826.49	% SZS status GaveUp for HL403317+4.p
44927.05/6826.49	eprover: CPU time limit exceeded, terminating
44927.05/6826.49	% SZS status Ended for HL403317+4.p
44942.71/6828.42	% SZS status Started for HL403321+5.p
44942.71/6828.42	% SZS status GaveUp for HL403321+5.p
44942.71/6828.42	% SZS status Ended for HL403321+5.p
44964.67/6831.15	% SZS status Started for HL403318+4.p
44964.67/6831.15	% SZS status GaveUp for HL403318+4.p
44964.67/6831.15	eprover: CPU time limit exceeded, terminating
44964.67/6831.15	% SZS status Ended for HL403318+4.p
44982.73/6833.45	% SZS status Started for HL403322+5.p
44982.73/6833.45	% SZS status GaveUp for HL403322+5.p
44982.73/6833.45	% SZS status Ended for HL403322+5.p
44990.01/6834.36	% SZS status Started for HL403319+4.p
44990.01/6834.36	% SZS status GaveUp for HL403319+4.p
44990.01/6834.36	eprover: CPU time limit exceeded, terminating
44990.01/6834.36	% SZS status Ended for HL403319+4.p
45011.59/6837.05	% SZS status Started for HL403323+5.p
45011.59/6837.05	% SZS status GaveUp for HL403323+5.p
45011.59/6837.05	% SZS status Ended for HL403323+5.p
45014.23/6837.47	% SZS status Started for HL403320+4.p
45014.23/6837.47	% SZS status GaveUp for HL403320+4.p
45014.23/6837.47	eprover: CPU time limit exceeded, terminating
45014.23/6837.47	% SZS status Ended for HL403320+4.p
45045.38/6841.38	% SZS status Started for HL403321+4.p
45045.38/6841.38	% SZS status GaveUp for HL403321+4.p
45045.38/6841.38	eprover: CPU time limit exceeded, terminating
45045.38/6841.38	% SZS status Ended for HL403321+4.p
45079.89/6845.71	% SZS status Started for HL403322+4.p
45079.89/6845.71	% SZS status GaveUp for HL403322+4.p
45079.89/6845.71	eprover: CPU time limit exceeded, terminating
45079.89/6845.71	% SZS status Ended for HL403322+4.p
45081.63/6845.87	% SZS status Started for HL403325+5.p
45081.63/6845.87	% SZS status GaveUp for HL403325+5.p
45081.63/6845.87	% SZS status Ended for HL403325+5.p
45127.68/6851.67	% SZS status Started for HL403323+4.p
45127.68/6851.67	% SZS status GaveUp for HL403323+4.p
45127.68/6851.67	eprover: CPU time limit exceeded, terminating
45127.68/6851.67	% SZS status Ended for HL403323+4.p
45165.12/6856.42	% SZS status Started for HL403324+4.p
45165.12/6856.42	% SZS status GaveUp for HL403324+4.p
45165.12/6856.42	eprover: CPU time limit exceeded, terminating
45165.12/6856.42	% SZS status Ended for HL403324+4.p
45179.11/6858.16	% SZS status Started for HL403324+5.p
45179.11/6858.16	% SZS status GaveUp for HL403324+5.p
45179.11/6858.16	eprover: CPU time limit exceeded, terminating
45179.11/6858.16	% SZS status Ended for HL403324+5.p
45189.34/6859.44	% SZS status Started for HL403325+4.p
45189.34/6859.44	% SZS status GaveUp for HL403325+4.p
45189.34/6859.44	eprover: CPU time limit exceeded, terminating
45189.34/6859.44	% SZS status Ended for HL403325+4.p
45211.92/6862.41	% SZS status Started for HL403326+4.p
45211.92/6862.41	% SZS status GaveUp for HL403326+4.p
45211.92/6862.41	eprover: CPU time limit exceeded, terminating
45211.92/6862.41	% SZS status Ended for HL403326+4.p
45234.01/6865.06	% SZS status Started for HL403328+5.p
45234.01/6865.06	% SZS status GaveUp for HL403328+5.p
45234.01/6865.06	% SZS status Ended for HL403328+5.p
45238.23/6865.64	% SZS status Started for HL403326+5.p
45238.23/6865.64	% SZS status GaveUp for HL403326+5.p
45238.23/6865.64	% SZS status Ended for HL403326+5.p
45258.97/6868.23	% SZS status Started for HL403330+5.p
45258.97/6868.23	% SZS status GaveUp for HL403330+5.p
45258.97/6868.23	% SZS status Ended for HL403330+5.p
45271.72/6869.81	% SZS status Started for HL403327+5.p
45271.72/6869.81	% SZS status GaveUp for HL403327+5.p
45271.72/6869.81	eprover: CPU time limit exceeded, terminating
45271.72/6869.81	% SZS status Ended for HL403327+5.p
45278.57/6870.66	% SZS status Started for HL403327+4.p
45278.57/6870.66	% SZS status GaveUp for HL403327+4.p
45278.57/6870.66	eprover: CPU time limit exceeded, terminating
45278.57/6870.66	% SZS status Ended for HL403327+4.p
45329.36/6877.05	% SZS status Started for HL403328+4.p
45329.36/6877.05	% SZS status GaveUp for HL403328+4.p
45329.36/6877.05	eprover: CPU time limit exceeded, terminating
45329.36/6877.05	% SZS status Ended for HL403328+4.p
45378.12/6883.17	% SZS status Started for HL403330+4.p
45378.12/6883.17	% SZS status GaveUp for HL403330+4.p
45378.12/6883.17	eprover: CPU time limit exceeded, terminating
45378.12/6883.17	% SZS status Ended for HL403330+4.p
45412.16/6887.51	% SZS status Started for HL403331+4.p
45412.16/6887.51	% SZS status GaveUp for HL403331+4.p
45412.16/6887.51	eprover: CPU time limit exceeded, terminating
45412.16/6887.51	% SZS status Ended for HL403331+4.p
45428.96/6889.58	% SZS status Started for HL403331+5.p
45428.96/6889.58	% SZS status GaveUp for HL403331+5.p
45428.96/6889.58	% SZS status Ended for HL403331+5.p
45437.91/6890.66	% SZS status Started for HL403332+4.p
45437.91/6890.66	% SZS status GaveUp for HL403332+4.p
45437.91/6890.66	eprover: CPU time limit exceeded, terminating
45437.91/6890.66	% SZS status Ended for HL403332+4.p
45448.96/6892.11	% SZS status Started for HL403335+5.p
45448.96/6892.11	% SZS status GaveUp for HL403335+5.p
45448.96/6892.11	% SZS status Ended for HL403335+5.p
45454.57/6892.81	% SZS status Started for HL403332+5.p
45454.57/6892.81	% SZS status GaveUp for HL403332+5.p
45454.57/6892.81	% SZS status Ended for HL403332+5.p
45472.78/6895.05	% SZS status Started for HL403333+4.p
45472.78/6895.05	% SZS status GaveUp for HL403333+4.p
45472.78/6895.05	eprover: CPU time limit exceeded, terminating
45472.78/6895.05	% SZS status Ended for HL403333+4.p
45474.30/6895.26	% SZS status Started for HL403333+5.p
45474.30/6895.26	% SZS status GaveUp for HL403333+5.p
45474.30/6895.26	% SZS status Ended for HL403333+5.p
45500.82/6898.61	% SZS status Started for HL403336+5.p
45500.82/6898.61	% SZS status GaveUp for HL403336+5.p
45500.82/6898.61	% SZS status Ended for HL403336+5.p
45517.29/6900.72	% SZS status Started for HL403337+5.p
45517.29/6900.72	% SZS status GaveUp for HL403337+5.p
45517.29/6900.72	% SZS status Ended for HL403337+5.p
45528.45/6902.06	% SZS status Started for HL403335+4.p
45528.45/6902.06	% SZS status GaveUp for HL403335+4.p
45528.45/6902.06	eprover: CPU time limit exceeded, terminating
45528.45/6902.06	% SZS status Ended for HL403335+4.p
45541.16/6903.66	% SZS status Started for HL403338+5.p
45541.16/6903.66	% SZS status GaveUp for HL403338+5.p
45541.16/6903.66	% SZS status Ended for HL403338+5.p
45570.44/6907.36	% SZS status Started for HL403339+5.p
45570.44/6907.36	% SZS status GaveUp for HL403339+5.p
45570.44/6907.36	% SZS status Ended for HL403339+5.p
45597.67/6910.90	% SZS status Started for HL403340+5.p
45597.67/6910.90	% SZS status GaveUp for HL403340+5.p
45597.67/6910.90	% SZS status Ended for HL403340+5.p
45611.27/6912.54	% SZS status Started for HL403336+4.p
45611.27/6912.54	% SZS status GaveUp for HL403336+4.p
45611.27/6912.54	eprover: CPU time limit exceeded, terminating
45611.27/6912.54	% SZS status Ended for HL403336+4.p
45636.39/6915.75	% SZS status Started for HL403337+4.p
45636.39/6915.75	% SZS status GaveUp for HL403337+4.p
45636.39/6915.75	eprover: CPU time limit exceeded, terminating
45636.39/6915.75	% SZS status Ended for HL403337+4.p
45644.18/6916.66	% SZS status Started for HL403341+5.p
45644.18/6916.66	% SZS status GaveUp for HL403341+5.p
45644.18/6916.66	% SZS status Ended for HL403341+5.p
45657.93/6918.38	% SZS status Started for HL403338+4.p
45657.93/6918.38	% SZS status GaveUp for HL403338+4.p
45657.93/6918.38	eprover: CPU time limit exceeded, terminating
45657.93/6918.38	% SZS status Ended for HL403338+4.p
45671.76/6920.20	% SZS status Started for HL403339+4.p
45671.76/6920.20	% SZS status GaveUp for HL403339+4.p
45671.76/6920.20	eprover: CPU time limit exceeded, terminating
45671.76/6920.20	% SZS status Ended for HL403339+4.p
45684.88/6921.87	% SZS status Started for HL403342+5.p
45684.88/6921.87	% SZS status GaveUp for HL403342+5.p
45684.88/6921.87	% SZS status Ended for HL403342+5.p
45715.03/6925.60	% SZS status Started for HL403343+5.p
45715.03/6925.60	% SZS status GaveUp for HL403343+5.p
45715.03/6925.60	% SZS status Ended for HL403343+5.p
45715.98/6925.73	% SZS status Started for HL403340+4.p
45715.98/6925.73	% SZS status GaveUp for HL403340+4.p
45715.98/6925.73	eprover: CPU time limit exceeded, terminating
45715.98/6925.73	% SZS status Ended for HL403340+4.p
45742.22/6929.04	% SZS status Started for HL403341+4.p
45742.22/6929.04	% SZS status GaveUp for HL403341+4.p
45742.22/6929.04	eprover: CPU time limit exceeded, terminating
45742.22/6929.04	% SZS status Ended for HL403341+4.p
45743.06/6929.07	% SZS status Started for HL403344+5.p
45743.06/6929.07	% SZS status GaveUp for HL403344+5.p
45743.06/6929.07	% SZS status Ended for HL403344+5.p
45785.96/6934.50	% SZS status Started for HL403347+5.p
45785.96/6934.50	% SZS status GaveUp for HL403347+5.p
45785.96/6934.50	% SZS status Ended for HL403347+5.p
45803.59/6936.72	% SZS status Started for HL403342+4.p
45803.59/6936.72	% SZS status GaveUp for HL403342+4.p
45803.59/6936.72	eprover: CPU time limit exceeded, terminating
45803.59/6936.72	% SZS status Ended for HL403342+4.p
45814.64/6938.09	% SZS status Started for HL403348+5.p
45814.64/6938.09	% SZS status GaveUp for HL403348+5.p
45814.64/6938.09	% SZS status Ended for HL403348+5.p
45836.57/6940.86	% SZS status Started for HL403343+4.p
45836.57/6940.86	% SZS status GaveUp for HL403343+4.p
45836.57/6940.86	eprover: CPU time limit exceeded, terminating
45836.57/6940.86	% SZS status Ended for HL403343+4.p
45857.23/6943.49	% SZS status Started for HL403344+4.p
45857.23/6943.49	% SZS status GaveUp for HL403344+4.p
45857.23/6943.49	eprover: CPU time limit exceeded, terminating
45857.23/6943.49	% SZS status Ended for HL403344+4.p
45883.62/6946.76	% SZS status Started for HL403350+5.p
45883.62/6946.76	% SZS status GaveUp for HL403350+5.p
45883.62/6946.76	% SZS status Ended for HL403350+5.p
45884.32/6946.88	% SZS status Started for HL403347+4.p
45884.32/6946.88	% SZS status GaveUp for HL403347+4.p
45884.32/6946.88	eprover: CPU time limit exceeded, terminating
45884.32/6946.88	% SZS status Ended for HL403347+4.p
45913.76/6950.70	% SZS status Started for HL403348+4.p
45913.76/6950.70	% SZS status GaveUp for HL403348+4.p
45913.76/6950.70	eprover: CPU time limit exceeded, terminating
45913.76/6950.70	% SZS status Ended for HL403348+4.p
45943.20/6954.27	% SZS status Started for HL403349+4.p
45943.20/6954.27	% SZS status GaveUp for HL403349+4.p
45943.20/6954.27	eprover: CPU time limit exceeded, terminating
45943.20/6954.27	% SZS status Ended for HL403349+4.p
45953.44/6955.52	% SZS status Started for HL403352+5.p
45953.44/6955.52	% SZS status GaveUp for HL403352+5.p
45953.44/6955.52	% SZS status Ended for HL403352+5.p
45981.08/6959.06	% SZS status Started for HL403349+5.p
45981.08/6959.06	% SZS status GaveUp for HL403349+5.p
45981.08/6959.06	eprover: CPU time limit exceeded, terminating
45981.08/6959.06	% SZS status Ended for HL403349+5.p
46003.86/6961.85	% SZS status Started for HL403350+4.p
46003.86/6961.85	% SZS status GaveUp for HL403350+4.p
46003.86/6961.85	eprover: CPU time limit exceeded, terminating
46003.86/6961.85	% SZS status Ended for HL403350+4.p
46011.72/6962.92	% SZS status Started for HL403353+5.p
46011.72/6962.92	% SZS status GaveUp for HL403353+5.p
46011.72/6962.92	% SZS status Ended for HL403353+5.p
46035.34/6965.86	% SZS status Started for HL403351+4.p
46035.34/6965.86	% SZS status GaveUp for HL403351+4.p
46035.34/6965.86	eprover: CPU time limit exceeded, terminating
46035.34/6965.86	% SZS status Ended for HL403351+4.p
46051.52/6967.87	% SZS status Started for HL403351+5.p
46051.52/6967.87	% SZS status GaveUp for HL403351+5.p
46051.52/6967.87	% SZS status Ended for HL403351+5.p
46083.45/6971.88	% SZS status Started for HL403352+4.p
46083.45/6971.88	% SZS status GaveUp for HL403352+4.p
46083.45/6971.88	eprover: CPU time limit exceeded, terminating
46083.45/6971.88	% SZS status Ended for HL403352+4.p
46114.71/6975.86	% SZS status Started for HL403353+4.p
46114.71/6975.86	% SZS status GaveUp for HL403353+4.p
46114.71/6975.86	eprover: CPU time limit exceeded, terminating
46114.71/6975.86	% SZS status Ended for HL403353+4.p
46148.98/6980.87	% SZS status Started for HL403354+4.p
46148.98/6980.87	% SZS status GaveUp for HL403354+4.p
46148.98/6980.87	eprover: CPU time limit exceeded, terminating
46148.98/6980.87	% SZS status Ended for HL403354+4.p
46182.11/6985.11	% SZS status Started for HL403354+5.p
46182.11/6985.11	% SZS status GaveUp for HL403354+5.p
46182.11/6985.11	eprover: CPU time limit exceeded, terminating
46182.11/6985.11	% SZS status Ended for HL403354+5.p
46198.86/6987.14	% SZS status Started for HL403355+4.p
46198.86/6987.14	% SZS status GaveUp for HL403355+4.p
46198.86/6987.14	eprover: CPU time limit exceeded, terminating
46198.86/6987.14	% SZS status Ended for HL403355+4.p
46211.94/6988.83	% SZS status Started for HL403355+5.p
46211.94/6988.83	% SZS status GaveUp for HL403355+5.p
46211.94/6988.83	eprover: CPU time limit exceeded, terminating
46211.94/6988.83	% SZS status Ended for HL403355+5.p
46237.77/6992.04	% SZS status Started for HL403356+4.p
46237.77/6992.04	% SZS status GaveUp for HL403356+4.p
46237.77/6992.04	eprover: CPU time limit exceeded, terminating
46237.77/6992.04	% SZS status Ended for HL403356+4.p
46246.79/6993.17	% SZS status Started for HL403356+5.p
46246.79/6993.17	% SZS status GaveUp for HL403356+5.p
46246.79/6993.17	eprover: CPU time limit exceeded, terminating
46246.79/6993.17	% SZS status Ended for HL403356+5.p
46279.19/6997.28	% SZS status Started for HL403357+4.p
46279.19/6997.28	% SZS status GaveUp for HL403357+4.p
46279.19/6997.28	eprover: CPU time limit exceeded, terminating
46279.19/6997.28	% SZS status Ended for HL403357+4.p
46315.54/7001.91	% SZS status Started for HL403357+5.p
46315.54/7001.91	% SZS status GaveUp for HL403357+5.p
46315.54/7001.91	eprover: CPU time limit exceeded, terminating
46315.54/7001.91	% SZS status Ended for HL403357+5.p
46348.81/7006.07	% SZS status Started for HL403359+4.p
46348.81/7006.07	% SZS status GaveUp for HL403359+4.p
46348.81/7006.07	eprover: CPU time limit exceeded, terminating
46348.81/7006.07	% SZS status Ended for HL403359+4.p
46380.07/7010.01	% SZS status Started for HL403359+5.p
46380.07/7010.01	% SZS status GaveUp for HL403359+5.p
46380.07/7010.01	eprover: CPU time limit exceeded, terminating
46380.07/7010.01	% SZS status Ended for HL403359+5.p
46398.07/7012.29	% SZS status Started for HL403360+4.p
46398.07/7012.29	% SZS status GaveUp for HL403360+4.p
46398.07/7012.29	eprover: CPU time limit exceeded, terminating
46398.07/7012.29	% SZS status Ended for HL403360+4.p
46408.62/7013.55	% SZS status Started for HL403360+5.p
46408.62/7013.55	% SZS status GaveUp for HL403360+5.p
46408.62/7013.55	eprover: CPU time limit exceeded, terminating
46408.62/7013.55	% SZS status Ended for HL403360+5.p
46436.30/7017.04	% SZS status Started for HL403361+4.p
46436.30/7017.04	% SZS status GaveUp for HL403361+4.p
46436.30/7017.04	eprover: CPU time limit exceeded, terminating
46436.30/7017.04	% SZS status Ended for HL403361+4.p
46444.53/7018.15	% SZS status Started for HL403361+5.p
46444.53/7018.15	% SZS status GaveUp for HL403361+5.p
46444.53/7018.15	eprover: CPU time limit exceeded, terminating
46444.53/7018.15	% SZS status Ended for HL403361+5.p
46478.66/7022.46	% SZS status Started for HL403362+4.p
46478.66/7022.46	% SZS status GaveUp for HL403362+4.p
46478.66/7022.46	eprover: CPU time limit exceeded, terminating
46478.66/7022.46	% SZS status Ended for HL403362+4.p
46511.18/7026.51	% SZS status Started for HL403362+5.p
46511.18/7026.51	% SZS status GaveUp for HL403362+5.p
46511.18/7026.51	eprover: CPU time limit exceeded, terminating
46511.18/7026.51	% SZS status Ended for HL403362+5.p
46514.36/7026.88	% SZS status Started for HL403365+5.p
46514.36/7026.88	% SZS status GaveUp for HL403365+5.p
46514.36/7026.88	% SZS status Ended for HL403365+5.p
46547.86/7031.13	% SZS status Started for HL403363+4.p
46547.86/7031.13	% SZS status GaveUp for HL403363+4.p
46547.86/7031.13	eprover: CPU time limit exceeded, terminating
46547.86/7031.13	% SZS status Ended for HL403363+4.p
46580.27/7035.15	% SZS status Started for HL403366+5.p
46580.27/7035.15	% SZS status GaveUp for HL403366+5.p
46580.27/7035.15	% SZS status Ended for HL403366+5.p
46582.13/7035.44	% SZS status Started for HL403363+5.p
46582.13/7035.44	% SZS status GaveUp for HL403363+5.p
46582.13/7035.44	eprover: CPU time limit exceeded, terminating
46582.13/7035.44	% SZS status Ended for HL403363+5.p
46596.88/7037.24	% SZS status Started for HL403364+4.p
46596.88/7037.24	% SZS status GaveUp for HL403364+4.p
46596.88/7037.24	eprover: CPU time limit exceeded, terminating
46596.88/7037.24	% SZS status Ended for HL403364+4.p
46604.02/7038.16	% SZS status Started for HL403364+5.p
46604.02/7038.16	% SZS status GaveUp for HL403364+5.p
46604.02/7038.16	eprover: CPU time limit exceeded, terminating
46604.02/7038.16	% SZS status Ended for HL403364+5.p
46635.58/7042.15	% SZS status Started for HL403365+4.p
46635.58/7042.15	% SZS status GaveUp for HL403365+4.p
46635.58/7042.15	eprover: CPU time limit exceeded, terminating
46635.58/7042.15	% SZS status Ended for HL403365+4.p
46653.64/7044.42	% SZS status Started for HL403370+5.p
46653.64/7044.42	% SZS status GaveUp for HL403370+5.p
46653.64/7044.42	% SZS status Ended for HL403370+5.p
46678.88/7047.58	% SZS status Started for HL403366+4.p
46678.88/7047.58	% SZS status GaveUp for HL403366+4.p
46678.88/7047.58	eprover: CPU time limit exceeded, terminating
46678.88/7047.58	% SZS status Ended for HL403366+4.p
46715.65/7052.22	% SZS status Started for HL403369+4.p
46715.65/7052.22	% SZS status GaveUp for HL403369+4.p
46715.65/7052.22	eprover: CPU time limit exceeded, terminating
46715.65/7052.22	% SZS status Ended for HL403369+4.p
46721.88/7053.12	% SZS status Started for HL403372+5.p
46721.88/7053.12	% SZS status GaveUp for HL403372+5.p
46721.88/7053.12	% SZS status Ended for HL403372+5.p
46742.42/7055.60	% SZS status Started for HL403369+5.p
46742.42/7055.60	% SZS status GaveUp for HL403369+5.p
46742.42/7055.60	eprover: CPU time limit exceeded, terminating
46742.42/7055.60	% SZS status Ended for HL403369+5.p
46779.06/7060.25	% SZS status Started for HL403370+4.p
46779.06/7060.25	% SZS status GaveUp for HL403370+4.p
46779.06/7060.25	eprover: CPU time limit exceeded, terminating
46779.06/7060.25	% SZS status Ended for HL403370+4.p
46795.69/7062.30	% SZS status Started for HL403371+4.p
46795.69/7062.30	% SZS status GaveUp for HL403371+4.p
46795.69/7062.30	eprover: CPU time limit exceeded, terminating
46795.69/7062.30	% SZS status Ended for HL403371+4.p
46800.65/7062.98	% SZS status Started for HL403371+5.p
46800.65/7062.98	% SZS status GaveUp for HL403371+5.p
46800.65/7062.98	eprover: CPU time limit exceeded, terminating
46800.65/7062.98	% SZS status Ended for HL403371+5.p
46813.38/7064.63	% SZS status Started for HL403374+5.p
46813.38/7064.63	% SZS status GaveUp for HL403374+5.p
46813.38/7064.63	% SZS status Ended for HL403374+5.p
46835.07/7067.27	% SZS status Started for HL403372+4.p
46835.07/7067.27	% SZS status GaveUp for HL403372+4.p
46835.07/7067.27	eprover: CPU time limit exceeded, terminating
46835.07/7067.27	% SZS status Ended for HL403372+4.p
46877.91/7072.67	% SZS status Started for HL403373+4.p
46877.91/7072.67	% SZS status GaveUp for HL403373+4.p
46877.91/7072.67	eprover: CPU time limit exceeded, terminating
46877.91/7072.67	% SZS status Ended for HL403373+4.p
46911.27/7076.88	% SZS status Started for HL403373+5.p
46911.27/7076.88	% SZS status GaveUp for HL403373+5.p
46911.27/7076.88	eprover: CPU time limit exceeded, terminating
46911.27/7076.88	% SZS status Ended for HL403373+5.p
46922.08/7078.23	% SZS status Started for HL403374+4.p
46922.08/7078.23	% SZS status GaveUp for HL403374+4.p
46922.08/7078.23	eprover: CPU time limit exceeded, terminating
46922.08/7078.23	% SZS status Ended for HL403374+4.p
46979.31/7085.48	% SZS status Started for HL403375+4.p
46979.31/7085.48	% SZS status GaveUp for HL403375+4.p
46979.31/7085.48	eprover: CPU time limit exceeded, terminating
46979.31/7085.48	% SZS status Ended for HL403375+4.p
46992.40/7087.17	% SZS status Started for HL403375+5.p
46992.40/7087.17	% SZS status GaveUp for HL403375+5.p
46992.40/7087.17	eprover: CPU time limit exceeded, terminating
46992.40/7087.17	% SZS status Ended for HL403375+5.p
47000.86/7088.23	% SZS status Started for HL403376+4.p
47000.86/7088.23	% SZS status GaveUp for HL403376+4.p
47000.86/7088.23	eprover: CPU time limit exceeded, terminating
47000.86/7088.23	% SZS status Ended for HL403376+4.p
47012.99/7089.67	% SZS status Started for HL403376+5.p
47012.99/7089.67	% SZS status GaveUp for HL403376+5.p
47012.99/7089.67	eprover: CPU time limit exceeded, terminating
47012.99/7089.67	% SZS status Ended for HL403376+5.p
47034.15/7092.32	% SZS status Started for HL403377+4.p
47034.15/7092.32	% SZS status GaveUp for HL403377+4.p
47034.15/7092.32	eprover: CPU time limit exceeded, terminating
47034.15/7092.32	% SZS status Ended for HL403377+4.p
47062.39/7095.86	% SZS status Started for HL403379+5.p
47062.39/7095.86	% SZS status GaveUp for HL403379+5.p
47062.39/7095.86	% SZS status Ended for HL403379+5.p
47069.56/7096.77	% SZS status Started for HL403377+5.p
47069.56/7096.77	% SZS status GaveUp for HL403377+5.p
47069.56/7096.77	eprover: CPU time limit exceeded, terminating
47069.56/7096.77	% SZS status Ended for HL403377+5.p
47081.35/7098.30	% SZS status Started for HL403380+5.p
47081.35/7098.30	% SZS status GaveUp for HL403380+5.p
47081.35/7098.30	% SZS status Ended for HL403380+5.p
47109.78/7101.88	% SZS status Started for HL403378+4.p
47109.78/7101.88	% SZS status GaveUp for HL403378+4.p
47109.78/7101.88	eprover: CPU time limit exceeded, terminating
47109.78/7101.88	% SZS status Ended for HL403378+4.p
47115.71/7102.55	% SZS status Started for HL403378+5.p
47115.71/7102.55	% SZS status GaveUp for HL403378+5.p
47115.71/7102.55	eprover: CPU time limit exceeded, terminating
47115.71/7102.55	% SZS status Ended for HL403378+5.p
47129.66/7104.30	% SZS status Started for HL403384+5.p
47129.66/7104.30	% SZS status Theorem for HL403384+5.p
47129.66/7104.30	% SZS status Ended for HL403384+5.p
47179.71/7110.62	% SZS status Started for HL403379+4.p
47179.71/7110.62	% SZS status GaveUp for HL403379+4.p
47179.71/7110.62	eprover: CPU time limit exceeded, terminating
47179.71/7110.62	% SZS status Ended for HL403379+4.p
47185.86/7111.47	% SZS status Started for HL403386+5.p
47185.86/7111.47	% SZS status GaveUp for HL403386+5.p
47185.86/7111.47	% SZS status Ended for HL403386+5.p
47200.88/7113.27	% SZS status Started for HL403380+4.p
47200.88/7113.27	% SZS status GaveUp for HL403380+4.p
47200.88/7113.27	eprover: CPU time limit exceeded, terminating
47200.88/7113.27	% SZS status Ended for HL403380+4.p
47232.73/7117.32	% SZS status Started for HL403382+4.p
47232.73/7117.32	% SZS status GaveUp for HL403382+4.p
47232.73/7117.32	eprover: CPU time limit exceeded, terminating
47232.73/7117.32	% SZS status Ended for HL403382+4.p
47251.28/7119.60	% SZS status Started for HL403387+5.p
47251.28/7119.60	% SZS status GaveUp for HL403387+5.p
47251.28/7119.60	% SZS status Ended for HL403387+5.p
47258.19/7120.48	% SZS status Started for HL403382+5.p
47258.19/7120.48	% SZS status GaveUp for HL403382+5.p
47258.19/7120.48	eprover: CPU time limit exceeded, terminating
47258.19/7120.48	% SZS status Ended for HL403382+5.p
47270.04/7121.96	% SZS status Started for HL403388+5.p
47270.04/7121.96	% SZS status GaveUp for HL403388+5.p
47270.04/7121.96	% SZS status Ended for HL403388+5.p
47271.06/7122.07	% SZS status Started for HL403384+4.p
47271.06/7122.07	% SZS status GaveUp for HL403384+4.p
47271.06/7122.07	eprover: CPU time limit exceeded, terminating
47271.06/7122.07	% SZS status Ended for HL403384+4.p
47309.10/7126.91	% SZS status Started for HL403386+4.p
47309.10/7126.91	% SZS status GaveUp for HL403386+4.p
47309.10/7126.91	eprover: CPU time limit exceeded, terminating
47309.10/7126.91	% SZS status Ended for HL403386+4.p
47322.91/7128.61	% SZS status Started for HL403389+5.p
47322.91/7128.61	% SZS status GaveUp for HL403389+5.p
47322.91/7128.61	% SZS status Ended for HL403389+5.p
47329.06/7129.37	% SZS status Started for HL403387+4.p
47329.06/7129.37	% SZS status GaveUp for HL403387+4.p
47329.06/7129.37	eprover: CPU time limit exceeded, terminating
47329.06/7129.37	% SZS status Ended for HL403387+4.p
47341.87/7130.96	% SZS status Started for HL403390+5.p
47341.87/7130.96	% SZS status GaveUp for HL403390+5.p
47341.87/7130.96	% SZS status Ended for HL403390+5.p
47379.82/7135.75	% SZS status Started for HL403391+5.p
47379.82/7135.75	% SZS status GaveUp for HL403391+5.p
47379.82/7135.75	% SZS status Ended for HL403391+5.p
47385.25/7136.55	% SZS status Started for HL403388+4.p
47385.25/7136.55	% SZS status GaveUp for HL403388+4.p
47385.25/7136.55	eprover: CPU time limit exceeded, terminating
47385.25/7136.55	% SZS status Ended for HL403388+4.p
47400.22/7138.34	% SZS status Started for HL403392+5.p
47400.22/7138.34	% SZS status GaveUp for HL403392+5.p
47400.22/7138.34	% SZS status Ended for HL403392+5.p
47431.70/7142.32	% SZS status Started for HL403389+4.p
47431.70/7142.32	% SZS status GaveUp for HL403389+4.p
47431.70/7142.32	eprover: CPU time limit exceeded, terminating
47431.70/7142.32	% SZS status Ended for HL403389+4.p
47450.26/7144.62	% SZS status Started for HL403393+5.p
47450.26/7144.62	% SZS status GaveUp for HL403393+5.p
47450.26/7144.62	% SZS status Ended for HL403393+5.p
47457.02/7145.54	% SZS status Started for HL403390+4.p
47457.02/7145.54	% SZS status GaveUp for HL403390+4.p
47457.02/7145.54	eprover: CPU time limit exceeded, terminating
47457.02/7145.54	% SZS status Ended for HL403390+4.p
47470.40/7147.15	% SZS status Started for HL403391+4.p
47470.40/7147.15	% SZS status GaveUp for HL403391+4.p
47470.40/7147.15	eprover: CPU time limit exceeded, terminating
47470.40/7147.15	% SZS status Ended for HL403391+4.p
47470.65/7147.21	% SZS status Started for HL403394+5.p
47470.65/7147.21	% SZS status GaveUp for HL403394+5.p
47470.65/7147.21	% SZS status Ended for HL403394+5.p
47520.87/7153.50	% SZS status Started for HL403395+5.p
47520.87/7153.50	% SZS status GaveUp for HL403395+5.p
47520.87/7153.50	% SZS status Ended for HL403395+5.p
47522.50/7153.68	% SZS status Started for HL403392+4.p
47522.50/7153.68	% SZS status GaveUp for HL403392+4.p
47522.50/7153.68	eprover: CPU time limit exceeded, terminating
47522.50/7153.68	% SZS status Ended for HL403392+4.p
47542.26/7156.21	% SZS status Started for HL403393+4.p
47542.26/7156.21	% SZS status GaveUp for HL403393+4.p
47542.26/7156.21	eprover: CPU time limit exceeded, terminating
47542.26/7156.21	% SZS status Ended for HL403393+4.p
47543.05/7156.35	% SZS status Started for HL403396+5.p
47543.05/7156.35	% SZS status GaveUp for HL403396+5.p
47543.05/7156.35	% SZS status Ended for HL403396+5.p
47584.92/7161.56	% SZS status Started for HL403394+4.p
47584.92/7161.56	% SZS status GaveUp for HL403394+4.p
47584.92/7161.56	eprover: CPU time limit exceeded, terminating
47584.92/7161.56	% SZS status Ended for HL403394+4.p
47589.68/7162.16	% SZS status Started for HL403397+5.p
47589.68/7162.16	% SZS status GaveUp for HL403397+5.p
47589.68/7162.16	% SZS status Ended for HL403397+5.p
47613.50/7165.15	% SZS status Started for HL403398+5.p
47613.50/7165.15	% SZS status GaveUp for HL403398+5.p
47613.50/7165.15	% SZS status Ended for HL403398+5.p
47630.91/7167.36	% SZS status Started for HL403395+4.p
47630.91/7167.36	% SZS status GaveUp for HL403395+4.p
47630.91/7167.36	eprover: CPU time limit exceeded, terminating
47630.91/7167.36	% SZS status Ended for HL403395+4.p
47653.36/7170.23	% SZS status Started for HL403399+5.p
47653.36/7170.23	% SZS status GaveUp for HL403399+5.p
47653.36/7170.23	% SZS status Ended for HL403399+5.p
47655.59/7170.49	% SZS status Started for HL403396+4.p
47655.59/7170.49	% SZS status GaveUp for HL403396+4.p
47655.59/7170.49	eprover: CPU time limit exceeded, terminating
47655.59/7170.49	% SZS status Ended for HL403396+4.p
47669.52/7172.22	% SZS status Started for HL403397+4.p
47669.52/7172.22	% SZS status GaveUp for HL403397+4.p
47669.52/7172.22	eprover: CPU time limit exceeded, terminating
47669.52/7172.22	% SZS status Ended for HL403397+4.p
47682.26/7173.84	% SZS status Started for HL403400+5.p
47682.26/7173.84	% SZS status GaveUp for HL403400+5.p
47682.26/7173.84	% SZS status Ended for HL403400+5.p
47721.18/7178.75	% SZS status Started for HL403398+4.p
47721.18/7178.75	% SZS status GaveUp for HL403398+4.p
47721.18/7178.75	eprover: CPU time limit exceeded, terminating
47721.18/7178.75	% SZS status Ended for HL403398+4.p
47723.32/7178.95	% SZS status Started for HL403401+5.p
47723.32/7178.95	% SZS status GaveUp for HL403401+5.p
47723.32/7178.95	% SZS status Ended for HL403401+5.p
47737.52/7180.84	% SZS status Started for HL403402+5.p
47737.52/7180.84	% SZS status GaveUp for HL403402+5.p
47737.52/7180.84	% SZS status Ended for HL403402+5.p
47743.71/7181.56	% SZS status Started for HL403399+4.p
47743.71/7181.56	% SZS status GaveUp for HL403399+4.p
47743.71/7181.56	eprover: CPU time limit exceeded, terminating
47743.71/7181.56	% SZS status Ended for HL403399+4.p
47788.04/7187.14	% SZS status Started for HL403400+4.p
47788.04/7187.14	% SZS status GaveUp for HL403400+4.p
47788.04/7187.14	eprover: CPU time limit exceeded, terminating
47788.04/7187.14	% SZS status Ended for HL403400+4.p
47790.82/7187.45	% SZS status Started for HL403404+5.p
47790.82/7187.45	% SZS status GaveUp for HL403404+5.p
47790.82/7187.45	% SZS status Ended for HL403404+5.p
47807.39/7189.54	% SZS status Started for HL403405+5.p
47807.39/7189.54	% SZS status GaveUp for HL403405+5.p
47807.39/7189.54	% SZS status Ended for HL403405+5.p
47832.37/7192.71	% SZS status Started for HL403401+4.p
47832.37/7192.71	% SZS status GaveUp for HL403401+4.p
47832.37/7192.71	eprover: CPU time limit exceeded, terminating
47832.37/7192.71	% SZS status Ended for HL403401+4.p
47854.71/7195.50	% SZS status Started for HL403402+4.p
47854.71/7195.50	% SZS status GaveUp for HL403402+4.p
47854.71/7195.50	eprover: CPU time limit exceeded, terminating
47854.71/7195.50	% SZS status Ended for HL403402+4.p
47857.50/7195.88	% SZS status Started for HL403406+5.p
47857.50/7195.88	% SZS status GaveUp for HL403406+5.p
47857.50/7195.88	% SZS status Ended for HL403406+5.p
47876.89/7198.25	% SZS status Started for HL403407+5.p
47876.89/7198.25	% SZS status GaveUp for HL403407+5.p
47876.89/7198.25	% SZS status Ended for HL403407+5.p
47881.78/7198.92	% SZS status Started for HL403404+4.p
47881.78/7198.92	% SZS status GaveUp for HL403404+4.p
47881.78/7198.92	eprover: CPU time limit exceeded, terminating
47881.78/7198.92	% SZS status Ended for HL403404+4.p
47921.80/7203.95	% SZS status Started for HL403405+4.p
47921.80/7203.95	% SZS status GaveUp for HL403405+4.p
47921.80/7203.95	eprover: CPU time limit exceeded, terminating
47921.80/7203.95	% SZS status Ended for HL403405+4.p
47925.44/7204.43	% SZS status Started for HL403408+5.p
47925.44/7204.43	% SZS status GaveUp for HL403408+5.p
47925.44/7204.43	% SZS status Ended for HL403408+5.p
47943.91/7206.73	% SZS status Started for HL403406+4.p
47943.91/7206.73	% SZS status GaveUp for HL403406+4.p
47943.91/7206.73	eprover: CPU time limit exceeded, terminating
47943.91/7206.73	% SZS status Ended for HL403406+4.p
47947.61/7207.15	% SZS status Started for HL403409+5.p
47947.61/7207.15	% SZS status GaveUp for HL403409+5.p
47947.61/7207.15	% SZS status Ended for HL403409+5.p
47992.57/7212.84	% SZS status Started for HL403407+4.p
47992.57/7212.84	% SZS status GaveUp for HL403407+4.p
47992.57/7212.84	eprover: CPU time limit exceeded, terminating
47992.57/7212.84	% SZS status Ended for HL403407+4.p
47992.90/7212.89	% SZS status Started for HL403410+5.p
47992.90/7212.89	% SZS status GaveUp for HL403410+5.p
47992.90/7212.89	% SZS status Ended for HL403410+5.p
48014.56/7215.57	% SZS status Started for HL403411+5.p
48014.56/7215.57	% SZS status GaveUp for HL403411+5.p
48014.56/7215.57	% SZS status Ended for HL403411+5.p
48032.06/7217.80	% SZS status Started for HL403408+4.p
48032.06/7217.80	% SZS status GaveUp for HL403408+4.p
48032.06/7217.80	eprover: CPU time limit exceeded, terminating
48032.06/7217.80	% SZS status Ended for HL403408+4.p
48057.00/7220.91	% SZS status Started for HL403409+4.p
48057.00/7220.91	% SZS status GaveUp for HL403409+4.p
48057.00/7220.91	eprover: CPU time limit exceeded, terminating
48057.00/7220.91	% SZS status Ended for HL403409+4.p
48062.12/7221.57	% SZS status Started for HL403412+5.p
48062.12/7221.57	% SZS status GaveUp for HL403412+5.p
48062.12/7221.57	% SZS status Ended for HL403412+5.p
48083.07/7224.16	% SZS status Started for HL403410+4.p
48083.07/7224.16	% SZS status GaveUp for HL403410+4.p
48083.07/7224.16	eprover: CPU time limit exceeded, terminating
48083.07/7224.16	% SZS status Ended for HL403410+4.p
48085.66/7224.53	% SZS status Started for HL403413+5.p
48085.66/7224.53	% SZS status GaveUp for HL403413+5.p
48085.66/7224.53	% SZS status Ended for HL403413+5.p
48125.20/7229.54	% SZS status Started for HL403411+4.p
48125.20/7229.54	% SZS status GaveUp for HL403411+4.p
48125.20/7229.54	eprover: CPU time limit exceeded, terminating
48125.20/7229.54	% SZS status Ended for HL403411+4.p
48125.20/7229.54	% SZS status Started for HL403414+5.p
48125.20/7229.54	% SZS status GaveUp for HL403414+5.p
48125.20/7229.54	% SZS status Ended for HL403414+5.p
48146.04/7232.18	% SZS status Started for HL403412+4.p
48146.04/7232.18	% SZS status GaveUp for HL403412+4.p
48146.04/7232.18	eprover: CPU time limit exceeded, terminating
48146.04/7232.18	% SZS status Ended for HL403412+4.p
48153.23/7233.03	% SZS status Started for HL403415+5.p
48153.23/7233.03	% SZS status GaveUp for HL403415+5.p
48153.23/7233.03	% SZS status Ended for HL403415+5.p
48193.30/7238.15	% SZS status Started for HL403413+4.p
48193.30/7238.15	% SZS status GaveUp for HL403413+4.p
48193.30/7238.15	eprover: CPU time limit exceeded, terminating
48193.30/7238.15	% SZS status Ended for HL403413+4.p
48195.62/7238.54	% SZS status Started for HL403416+5.p
48195.62/7238.54	% SZS status GaveUp for HL403416+5.p
48195.62/7238.54	% SZS status Ended for HL403416+5.p
48216.61/7241.05	% SZS status Started for HL403417+5.p
48216.61/7241.05	% SZS status GaveUp for HL403417+5.p
48216.61/7241.05	% SZS status Ended for HL403417+5.p
48231.65/7243.02	% SZS status Started for HL403414+4.p
48231.65/7243.02	% SZS status GaveUp for HL403414+4.p
48231.65/7243.02	eprover: CPU time limit exceeded, terminating
48231.65/7243.02	% SZS status Ended for HL403414+4.p
48261.54/7246.69	% SZS status Started for HL403415+4.p
48261.54/7246.69	% SZS status GaveUp for HL403415+4.p
48261.54/7246.69	eprover: CPU time limit exceeded, terminating
48261.54/7246.69	% SZS status Ended for HL403415+4.p
48265.10/7247.17	% SZS status Started for HL403418+5.p
48265.10/7247.17	% SZS status GaveUp for HL403418+5.p
48265.10/7247.17	% SZS status Ended for HL403418+5.p
48285.46/7249.69	% SZS status Started for HL403416+4.p
48285.46/7249.69	% SZS status GaveUp for HL403416+4.p
48285.46/7249.69	eprover: CPU time limit exceeded, terminating
48285.46/7249.69	% SZS status Ended for HL403416+4.p
48287.94/7250.03	% SZS status Started for HL403420+5.p
48287.94/7250.03	% SZS status GaveUp for HL403420+5.p
48287.94/7250.03	% SZS status Ended for HL403420+5.p
48325.43/7254.76	% SZS status Started for HL403417+4.p
48325.43/7254.76	% SZS status GaveUp for HL403417+4.p
48325.43/7254.76	eprover: CPU time limit exceeded, terminating
48325.43/7254.76	% SZS status Ended for HL403417+4.p
48331.75/7255.48	% SZS status Started for HL403424+5.p
48331.75/7255.48	% SZS status Theorem for HL403424+5.p
48331.75/7255.48	% SZS status Ended for HL403424+5.p
48332.90/7255.59	% SZS status Started for HL403421+5.p
48332.90/7255.59	% SZS status GaveUp for HL403421+5.p
48332.90/7255.59	% SZS status Ended for HL403421+5.p
48352.10/7258.02	% SZS status Started for HL403418+4.p
48352.10/7258.02	% SZS status GaveUp for HL403418+4.p
48352.10/7258.02	eprover: CPU time limit exceeded, terminating
48352.10/7258.02	% SZS status Ended for HL403418+4.p
48357.13/7258.64	% SZS status Started for HL403422+5.p
48357.13/7258.64	% SZS status GaveUp for HL403422+5.p
48357.13/7258.64	% SZS status Ended for HL403422+5.p
48396.39/7263.65	% SZS status Started for HL403420+4.p
48396.39/7263.65	% SZS status GaveUp for HL403420+4.p
48396.39/7263.65	eprover: CPU time limit exceeded, terminating
48396.39/7263.65	% SZS status Ended for HL403420+4.p
48404.33/7264.63	% SZS status Started for HL403425+5.p
48404.33/7264.63	% SZS status GaveUp for HL403425+5.p
48404.33/7264.63	% SZS status Ended for HL403425+5.p
48426.24/7267.42	% SZS status Started for HL403426+5.p
48426.24/7267.42	% SZS status GaveUp for HL403426+5.p
48426.24/7267.42	% SZS status Ended for HL403426+5.p
48432.07/7268.10	% SZS status Started for HL403421+4.p
48432.07/7268.10	% SZS status GaveUp for HL403421+4.p
48432.07/7268.10	eprover: CPU time limit exceeded, terminating
48432.07/7268.10	% SZS status Ended for HL403421+4.p
48466.39/7272.42	% SZS status Started for HL403422+4.p
48466.39/7272.42	% SZS status GaveUp for HL403422+4.p
48466.39/7272.42	eprover: CPU time limit exceeded, terminating
48466.39/7272.42	% SZS status Ended for HL403422+4.p
48475.47/7273.57	% SZS status Started for HL403427+5.p
48475.47/7273.57	% SZS status GaveUp for HL403427+5.p
48475.47/7273.57	% SZS status Ended for HL403427+5.p
48488.12/7275.19	% SZS status Started for HL403424+4.p
48488.12/7275.19	% SZS status GaveUp for HL403424+4.p
48488.12/7275.19	eprover: CPU time limit exceeded, terminating
48488.12/7275.19	% SZS status Ended for HL403424+4.p
48500.38/7276.76	% SZS status Started for HL403428+5.p
48500.38/7276.76	% SZS status GaveUp for HL403428+5.p
48500.38/7276.76	% SZS status Ended for HL403428+5.p
48535.20/7281.09	% SZS status Started for HL403429+5.p
48535.20/7281.09	% SZS status Theorem for HL403429+5.p
48535.20/7281.09	% SZS status Ended for HL403429+5.p
48543.14/7281.18	% SZS status Started for HL403425+4.p
48543.14/7281.18	% SZS status GaveUp for HL403425+4.p
48543.14/7281.18	eprover: CPU time limit exceeded, terminating
48543.14/7281.18	% SZS status Ended for HL403425+4.p
48559.93/7283.30	% SZS status Started for HL403426+4.p
48559.93/7283.30	% SZS status GaveUp for HL403426+4.p
48559.93/7283.30	eprover: CPU time limit exceeded, terminating
48559.93/7283.30	% SZS status Ended for HL403426+4.p
48578.81/7285.67	% SZS status Started for HL403432+5.p
48578.81/7285.67	% SZS status GaveUp for HL403432+5.p
48578.81/7285.67	% SZS status Ended for HL403432+5.p
48603.57/7288.80	% SZS status Started for HL403427+4.p
48603.57/7288.80	% SZS status GaveUp for HL403427+4.p
48603.57/7288.80	eprover: CPU time limit exceeded, terminating
48603.57/7288.80	% SZS status Ended for HL403427+4.p
48638.45/7290.08	% SZS status Started for HL403433+5.p
48638.45/7290.08	% SZS status GaveUp for HL403433+5.p
48638.45/7290.08	% SZS status Ended for HL403433+5.p
48657.48/7292.62	% SZS status Started for HL403428+4.p
48657.48/7292.62	% SZS status GaveUp for HL403428+4.p
48657.48/7292.62	eprover: CPU time limit exceeded, terminating
48657.48/7292.62	% SZS status Ended for HL403428+4.p
48674.98/7294.85	% SZS status Started for HL403434+5.p
48674.98/7294.85	% SZS status GaveUp for HL403434+5.p
48674.98/7294.85	% SZS status Ended for HL403434+5.p
48687.20/7296.39	% SZS status Started for HL403436+4.p
48687.20/7296.39	% SZS status Theorem for HL403436+4.p
48687.20/7296.39	% SZS status Ended for HL403436+4.p
48700.00/7298.04	% SZS status Started for HL403429+4.p
48700.00/7298.04	% SZS status GaveUp for HL403429+4.p
48700.00/7298.04	eprover: CPU time limit exceeded, terminating
48700.00/7298.04	% SZS status Ended for HL403429+4.p
48713.07/7299.75	% SZS status Started for HL403437+4.p
48713.07/7299.75	% SZS status Theorem for HL403437+4.p
48713.07/7299.75	% SZS status Ended for HL403437+4.p
48713.07/7299.75	% SZS status Started for HL403435+5.p
48713.07/7299.75	% SZS status GaveUp for HL403435+5.p
48713.07/7299.75	% SZS status Ended for HL403435+5.p
48719.73/7300.59	% SZS status Started for HL403432+4.p
48719.73/7300.59	% SZS status GaveUp for HL403432+4.p
48719.73/7300.59	eprover: CPU time limit exceeded, terminating
48719.73/7300.59	% SZS status Ended for HL403432+4.p
48727.07/7301.59	% SZS status Started for HL403436+5.p
48727.07/7301.59	% SZS status Theorem for HL403436+5.p
48727.07/7301.59	% SZS status Ended for HL403436+5.p
48765.15/7306.49	% SZS status Started for HL403433+4.p
48765.15/7306.49	% SZS status GaveUp for HL403433+4.p
48765.15/7306.49	eprover: CPU time limit exceeded, terminating
48765.15/7306.49	% SZS status Ended for HL403433+4.p
48773.11/7307.60	% SZS status Started for HL403437+5.p
48773.11/7307.60	% SZS status GaveUp for HL403437+5.p
48773.11/7307.60	% SZS status Ended for HL403437+5.p
48781.18/7308.67	% SZS status Started for HL403434+4.p
48781.18/7308.67	% SZS status GaveUp for HL403434+4.p
48781.18/7308.67	eprover: CPU time limit exceeded, terminating
48781.18/7308.67	% SZS status Ended for HL403434+4.p
48783.65/7308.90	% SZS status Started for HL403440+4.p
48783.65/7308.90	% SZS status Theorem for HL403440+4.p
48783.65/7308.90	% SZS status Ended for HL403440+4.p
48784.33/7309.01	% SZS status Started for HL403439+4.p
48784.33/7309.01	% SZS status GaveUp for HL403439+4.p
48784.33/7309.01	% SZS status Ended for HL403439+4.p
48786.22/7309.32	% SZS status Started for HL403439+5.p
48786.22/7309.32	% SZS status GaveUp for HL403439+5.p
48786.22/7309.32	% SZS status Ended for HL403439+5.p
48797.79/7310.81	% SZS status Started for HL403440+5.p
48797.79/7310.81	% SZS status GaveUp for HL403440+5.p
48797.79/7310.81	% SZS status Ended for HL403440+5.p
48826.38/7314.38	% SZS status Started for HL403435+4.p
48826.38/7314.38	% SZS status GaveUp for HL403435+4.p
48826.38/7314.38	eprover: CPU time limit exceeded, terminating
48826.38/7314.38	% SZS status Ended for HL403435+4.p
48837.17/7315.87	% SZS status Started for HL403441+4.p
48837.17/7315.87	% SZS status GaveUp for HL403441+4.p
48837.17/7315.87	% SZS status Ended for HL403441+4.p
48843.92/7316.73	% SZS status Started for HL403441+5.p
48843.92/7316.73	% SZS status GaveUp for HL403441+5.p
48843.92/7316.73	% SZS status Ended for HL403441+5.p
48855.78/7318.25	% SZS status Started for HL403442+4.p
48855.78/7318.25	% SZS status GaveUp for HL403442+4.p
48855.78/7318.25	% SZS status Ended for HL403442+4.p
48855.78/7318.27	% SZS status Started for HL403443+4.p
48855.78/7318.27	% SZS status GaveUp for HL403443+4.p
48855.78/7318.27	% SZS status Ended for HL403443+4.p
48855.78/7318.30	% SZS status Started for HL403442+5.p
48855.78/7318.30	% SZS status GaveUp for HL403442+5.p
48855.78/7318.30	% SZS status Ended for HL403442+5.p
48857.79/7318.73	% SZS status Started for HL403443+5.p
48857.79/7318.73	% SZS status GaveUp for HL403443+5.p
48857.79/7318.73	% SZS status Ended for HL403443+5.p
48869.97/7320.05	% SZS status Started for HL403445+4.p
48869.97/7320.05	% SZS status GaveUp for HL403445+4.p
48869.97/7320.05	% SZS status Ended for HL403445+4.p
48899.46/7323.85	% SZS status Started for HL403445+5.p
48899.46/7323.85	% SZS status GaveUp for HL403445+5.p
48899.46/7323.85	% SZS status Ended for HL403445+5.p
48911.38/7325.35	% SZS status Started for HL403447+4.p
48911.38/7325.35	% SZS status GaveUp for HL403447+4.p
48911.38/7325.35	% SZS status Ended for HL403447+4.p
48914.40/7325.73	% SZS status Started for HL403447+5.p
48914.40/7325.73	% SZS status GaveUp for HL403447+5.p
48914.40/7325.73	% SZS status Ended for HL403447+5.p
48925.54/7327.12	% SZS status Started for HL403448+5.p
48925.54/7327.12	% SZS status GaveUp for HL403448+5.p
48925.54/7327.12	% SZS status Ended for HL403448+5.p
48926.60/7327.27	% SZS status Started for HL403448+4.p
48926.60/7327.27	% SZS status GaveUp for HL403448+4.p
48926.60/7327.27	% SZS status Ended for HL403448+4.p
48930.30/7327.73	% SZS status Started for HL403449+4.p
48930.30/7327.73	% SZS status GaveUp for HL403449+4.p
48930.30/7327.73	% SZS status Ended for HL403449+4.p
48931.11/7327.86	% SZS status Started for HL403449+5.p
48931.11/7327.86	% SZS status GaveUp for HL403449+5.p
48931.11/7327.86	% SZS status Ended for HL403449+5.p
48942.54/7329.25	% SZS status Started for HL403450+4.p
48942.54/7329.25	% SZS status GaveUp for HL403450+4.p
48942.54/7329.25	% SZS status Ended for HL403450+4.p
48970.66/7332.96	% SZS status Started for HL403450+5.p
48970.66/7332.96	% SZS status GaveUp for HL403450+5.p
48970.66/7332.96	% SZS status Ended for HL403450+5.p
48984.01/7334.62	% SZS status Started for HL403451+4.p
48984.01/7334.62	% SZS status GaveUp for HL403451+4.p
48984.01/7334.62	% SZS status Ended for HL403451+4.p
48988.45/7335.10	% SZS status Started for HL403451+5.p
48988.45/7335.10	% SZS status GaveUp for HL403451+5.p
48988.45/7335.10	% SZS status Ended for HL403451+5.p
48995.27/7336.13	% SZS status Started for HL403452+4.p
48995.27/7336.13	% SZS status GaveUp for HL403452+4.p
48995.27/7336.13	% SZS status Ended for HL403452+4.p
48995.70/7336.20	% SZS status Started for HL403452+5.p
48995.70/7336.20	% SZS status GaveUp for HL403452+5.p
48995.70/7336.20	% SZS status Ended for HL403452+5.p
49000.59/7336.72	% SZS status Started for HL403453+4.p
49000.59/7336.72	% SZS status GaveUp for HL403453+4.p
49000.59/7336.72	% SZS status Ended for HL403453+4.p
49000.98/7336.77	% SZS status Started for HL403453+5.p
49000.98/7336.77	% SZS status GaveUp for HL403453+5.p
49000.98/7336.77	% SZS status Ended for HL403453+5.p
49014.88/7338.43	% SZS status Started for HL403455+4.p
49014.88/7338.43	% SZS status GaveUp for HL403455+4.p
49014.88/7338.43	% SZS status Ended for HL403455+4.p
49042.70/7341.95	% SZS status Started for HL403455+5.p
49042.70/7341.95	% SZS status GaveUp for HL403455+5.p
49042.70/7341.95	% SZS status Ended for HL403455+5.p
49054.85/7343.61	% SZS status Started for HL403456+4.p
49054.85/7343.61	% SZS status GaveUp for HL403456+4.p
49054.85/7343.61	% SZS status Ended for HL403456+4.p
49061.59/7344.41	% SZS status Started for HL403456+5.p
49061.59/7344.41	% SZS status GaveUp for HL403456+5.p
49061.59/7344.41	% SZS status Ended for HL403456+5.p
49066.45/7344.97	% SZS status Started for HL403457+5.p
49066.45/7344.97	% SZS status GaveUp for HL403457+5.p
49066.45/7344.97	% SZS status Ended for HL403457+5.p
49067.88/7345.26	% SZS status Started for HL403457+4.p
49067.88/7345.26	% SZS status GaveUp for HL403457+4.p
49067.88/7345.26	% SZS status Ended for HL403457+4.p
49070.05/7345.45	% SZS status Started for HL403458+5.p
49070.05/7345.45	% SZS status GaveUp for HL403458+5.p
49070.05/7345.45	% SZS status Ended for HL403458+5.p
49071.30/7345.61	% SZS status Started for HL403460+4.p
49071.30/7345.61	% SZS status Theorem for HL403460+4.p
49071.30/7345.61	% SZS status Ended for HL403460+4.p
49072.30/7345.79	% SZS status Started for HL403458+4.p
49072.30/7345.79	% SZS status GaveUp for HL403458+4.p
49072.30/7345.79	% SZS status Ended for HL403458+4.p
49074.11/7345.96	% SZS status Started for HL403461+4.p
49074.11/7345.96	% SZS status Theorem for HL403461+4.p
49074.11/7345.96	% SZS status Ended for HL403461+4.p
49087.83/7347.76	% SZS status Started for HL403459+4.p
49087.83/7347.76	% SZS status GaveUp for HL403459+4.p
49087.83/7347.76	% SZS status Ended for HL403459+4.p
49115.31/7351.29	% SZS status Started for HL403459+5.p
49115.31/7351.29	% SZS status GaveUp for HL403459+5.p
49115.31/7351.29	% SZS status Ended for HL403459+5.p
49118.66/7351.70	% SZS status Started for HL403461+5.p
49118.66/7351.70	% SZS status Theorem for HL403461+5.p
49118.66/7351.70	% SZS status Ended for HL403461+5.p
49131.16/7353.36	% SZS status Started for HL403460+5.p
49131.16/7353.36	% SZS status GaveUp for HL403460+5.p
49131.16/7353.36	% SZS status Ended for HL403460+5.p
49140.84/7354.54	% SZS status Started for HL403462+4.p
49140.84/7354.54	% SZS status GaveUp for HL403462+4.p
49140.84/7354.54	% SZS status Ended for HL403462+4.p
49144.70/7355.03	% SZS status Started for HL403462+5.p
49144.70/7355.03	% SZS status GaveUp for HL403462+5.p
49144.70/7355.03	% SZS status Ended for HL403462+5.p
49145.25/7355.04	% SZS status Started for HL403464+5.p
49145.25/7355.04	% SZS status GaveUp for HL403464+5.p
49145.25/7355.04	% SZS status Ended for HL403464+5.p
49192.96/7361.14	% SZS status Started for HL403465+5.p
49192.96/7361.14	% SZS status GaveUp for HL403465+5.p
49192.96/7361.14	% SZS status Ended for HL403465+5.p
49202.71/7362.37	% SZS status Started for HL403466+5.p
49202.71/7362.37	% SZS status GaveUp for HL403466+5.p
49202.71/7362.37	% SZS status Ended for HL403466+5.p
49218.62/7364.43	% SZS status Started for HL403468+5.p
49218.62/7364.43	% SZS status GaveUp for HL403468+5.p
49218.62/7364.43	% SZS status Ended for HL403468+5.p
49264.15/7370.13	% SZS status Started for HL403469+5.p
49264.15/7370.13	% SZS status GaveUp for HL403469+5.p
49264.15/7370.13	% SZS status Ended for HL403469+5.p
49275.61/7371.58	% SZS status Started for HL403464+4.p
49275.61/7371.58	% SZS status GaveUp for HL403464+4.p
49275.61/7371.58	eprover: CPU time limit exceeded, terminating
49275.61/7371.58	% SZS status Ended for HL403464+4.p
49289.06/7373.28	% SZS status Started for HL403465+4.p
49289.06/7373.28	% SZS status GaveUp for HL403465+4.p
49289.06/7373.28	eprover: CPU time limit exceeded, terminating
49289.06/7373.28	% SZS status Ended for HL403465+4.p
49290.07/7373.46	% SZS status Started for HL403470+5.p
49290.07/7373.46	% SZS status GaveUp for HL403470+5.p
49290.07/7373.46	% SZS status Ended for HL403470+5.p
49317.45/7376.91	% SZS status Started for HL403466+4.p
49317.45/7376.91	% SZS status GaveUp for HL403466+4.p
49317.45/7376.91	eprover: CPU time limit exceeded, terminating
49317.45/7376.91	% SZS status Ended for HL403466+4.p
49325.38/7377.89	% SZS status Started for HL403471+5.p
49325.38/7377.89	% SZS status Theorem for HL403471+5.p
49325.38/7377.89	% SZS status Ended for HL403471+5.p
49341.45/7379.89	% SZS status Started for HL403472+5.p
49341.45/7379.89	% SZS status Theorem for HL403472+5.p
49341.45/7379.89	% SZS status Ended for HL403472+5.p
49344.50/7380.25	% SZS status Started for HL403468+4.p
49344.50/7380.25	% SZS status GaveUp for HL403468+4.p
49344.50/7380.25	eprover: CPU time limit exceeded, terminating
49344.50/7380.25	% SZS status Ended for HL403468+4.p
49344.50/7380.31	% SZS status Started for HL403469+4.p
49344.50/7380.31	% SZS status GaveUp for HL403469+4.p
49344.50/7380.31	eprover: CPU time limit exceeded, terminating
49344.50/7380.31	% SZS status Ended for HL403469+4.p
49375.49/7384.26	% SZS status Started for HL403473+5.p
49375.49/7384.26	% SZS status Theorem for HL403473+5.p
49375.49/7384.26	% SZS status Ended for HL403473+5.p
49393.33/7386.43	% SZS status Started for HL403475+5.p
49393.33/7386.43	% SZS status Theorem for HL403475+5.p
49393.33/7386.43	% SZS status Ended for HL403475+5.p
49403.60/7387.77	% SZS status Started for HL403470+4.p
49403.60/7387.77	% SZS status GaveUp for HL403470+4.p
49403.60/7387.77	eprover: CPU time limit exceeded, terminating
49403.60/7387.77	% SZS status Ended for HL403470+4.p
49414.18/7389.01	% SZS status Started for HL403474+5.p
49414.18/7389.01	% SZS status GaveUp for HL403474+5.p
49414.18/7389.01	% SZS status Ended for HL403474+5.p
49465.38/7395.46	% SZS status Started for HL403471+4.p
49465.38/7395.46	% SZS status GaveUp for HL403471+4.p
49465.38/7395.46	eprover: CPU time limit exceeded, terminating
49465.38/7395.46	% SZS status Ended for HL403471+4.p
49475.04/7396.71	% SZS status Started for HL403476+5.p
49475.04/7396.71	% SZS status GaveUp for HL403476+5.p
49475.04/7396.71	% SZS status Ended for HL403476+5.p
49483.62/7397.89	% SZS status Started for HL403477+5.p
49483.62/7397.89	% SZS status Theorem for HL403477+5.p
49483.62/7397.89	% SZS status Ended for HL403477+5.p
49489.50/7398.60	% SZS status Started for HL403472+4.p
49489.50/7398.60	% SZS status GaveUp for HL403472+4.p
49489.50/7398.60	eprover: CPU time limit exceeded, terminating
49489.50/7398.60	% SZS status Ended for HL403472+4.p
49520.19/7402.53	% SZS status Started for HL403473+4.p
49520.19/7402.53	% SZS status GaveUp for HL403473+4.p
49520.19/7402.53	eprover: CPU time limit exceeded, terminating
49520.19/7402.53	% SZS status Ended for HL403473+4.p
49530.29/7403.76	% SZS status Started for HL403480+5.p
49530.29/7403.76	% SZS status Theorem for HL403480+5.p
49530.29/7403.76	% SZS status Ended for HL403480+5.p
49541.71/7405.15	% SZS status Started for HL403474+4.p
49541.71/7405.15	% SZS status GaveUp for HL403474+4.p
49541.71/7405.15	eprover: CPU time limit exceeded, terminating
49541.71/7405.15	% SZS status Ended for HL403474+4.p
49546.69/7405.82	% SZS status Started for HL403475+4.p
49546.69/7405.82	% SZS status GaveUp for HL403475+4.p
49546.69/7405.82	eprover: CPU time limit exceeded, terminating
49546.69/7405.82	% SZS status Ended for HL403475+4.p
49553.58/7406.68	% SZS status Started for HL403478+5.p
49553.58/7406.68	% SZS status GaveUp for HL403478+5.p
49553.58/7406.68	% SZS status Ended for HL403478+5.p
49564.14/7407.99	% SZS status Started for HL403482+5.p
49564.14/7407.99	% SZS status Theorem for HL403482+5.p
49564.14/7407.99	% SZS status Ended for HL403482+5.p
49596.30/7412.10	% SZS status Started for HL403476+4.p
49596.30/7412.10	% SZS status GaveUp for HL403476+4.p
49596.30/7412.10	eprover: CPU time limit exceeded, terminating
49596.30/7412.10	% SZS status Ended for HL403476+4.p
49610.77/7413.84	% SZS status Started for HL403481+5.p
49610.77/7413.84	% SZS status GaveUp for HL403481+5.p
49610.77/7413.84	% SZS status Ended for HL403481+5.p
49615.06/7414.36	% SZS status Started for HL403477+4.p
49615.06/7414.36	% SZS status GaveUp for HL403477+4.p
49615.06/7414.36	eprover: CPU time limit exceeded, terminating
49615.06/7414.36	% SZS status Ended for HL403477+4.p
49668.01/7421.02	% SZS status Started for HL403483+5.p
49668.01/7421.02	% SZS status GaveUp for HL403483+5.p
49668.01/7421.02	% SZS status Ended for HL403483+5.p
49677.73/7422.22	% SZS status Started for HL403478+4.p
49677.73/7422.22	% SZS status GaveUp for HL403478+4.p
49677.73/7422.22	eprover: CPU time limit exceeded, terminating
49677.73/7422.22	% SZS status Ended for HL403478+4.p
49686.26/7423.32	% SZS status Started for HL403484+5.p
49686.26/7423.32	% SZS status GaveUp for HL403484+5.p
49686.26/7423.32	% SZS status Ended for HL403484+5.p
49690.51/7423.87	% SZS status Started for HL403480+4.p
49690.51/7423.87	% SZS status GaveUp for HL403480+4.p
49690.51/7423.87	eprover: CPU time limit exceeded, terminating
49690.51/7423.87	% SZS status Ended for HL403480+4.p
49731.33/7428.96	% SZS status Started for HL403481+4.p
49731.33/7428.96	% SZS status GaveUp for HL403481+4.p
49731.33/7428.96	eprover: CPU time limit exceeded, terminating
49731.33/7428.96	% SZS status Ended for HL403481+4.p
49747.97/7431.08	% SZS status Started for HL403482+4.p
49747.97/7431.08	% SZS status GaveUp for HL403482+4.p
49747.97/7431.08	eprover: CPU time limit exceeded, terminating
49747.97/7431.08	% SZS status Ended for HL403482+4.p
49749.53/7431.26	% SZS status Started for HL403485+5.p
49749.53/7431.26	% SZS status GaveUp for HL403485+5.p
49749.53/7431.26	% SZS status Ended for HL403485+5.p
49761.81/7432.81	% SZS status Started for HL403486+5.p
49761.81/7432.81	% SZS status GaveUp for HL403486+5.p
49761.81/7432.81	% SZS status Ended for HL403486+5.p
49765.70/7433.35	% SZS status Started for HL403483+4.p
49765.70/7433.35	% SZS status GaveUp for HL403483+4.p
49765.70/7433.35	eprover: CPU time limit exceeded, terminating
49765.70/7433.35	% SZS status Ended for HL403483+4.p
49804.44/7438.18	% SZS status Started for HL403488+5.p
49804.44/7438.18	% SZS status Theorem for HL403488+5.p
49804.44/7438.18	% SZS status Ended for HL403488+5.p
49813.13/7439.36	% SZS status Started for HL403484+4.p
49813.13/7439.36	% SZS status GaveUp for HL403484+4.p
49813.13/7439.36	eprover: CPU time limit exceeded, terminating
49813.13/7439.36	% SZS status Ended for HL403484+4.p
49841.87/7439.96	% SZS status Started for HL403487+5.p
49841.87/7439.96	% SZS status GaveUp for HL403487+5.p
49841.87/7439.96	% SZS status Ended for HL403487+5.p
49871.22/7443.52	% SZS status Started for HL403489+5.p
49871.22/7443.52	% SZS status Theorem for HL403489+5.p
49871.22/7443.52	% SZS status Ended for HL403489+5.p
49895.37/7446.54	% SZS status Started for HL403485+4.p
49895.37/7446.54	% SZS status GaveUp for HL403485+4.p
49895.37/7446.54	eprover: CPU time limit exceeded, terminating
49895.37/7446.54	% SZS status Ended for HL403485+4.p
49911.45/7448.57	% SZS status Started for HL403486+4.p
49911.45/7448.57	% SZS status GaveUp for HL403486+4.p
49911.45/7448.57	eprover: CPU time limit exceeded, terminating
49911.45/7448.57	% SZS status Ended for HL403486+4.p
49913.71/7448.89	% SZS status Started for HL403490+5.p
49913.71/7448.89	% SZS status GaveUp for HL403490+5.p
49913.71/7448.89	% SZS status Ended for HL403490+5.p
49957.74/7454.36	% SZS status Started for HL403487+4.p
49957.74/7454.36	% SZS status GaveUp for HL403487+4.p
49957.74/7454.36	eprover: CPU time limit exceeded, terminating
49957.74/7454.36	% SZS status Ended for HL403487+4.p
49966.40/7455.45	% SZS status Started for HL403491+5.p
49966.40/7455.45	% SZS status GaveUp for HL403491+5.p
49966.40/7455.45	% SZS status Ended for HL403491+5.p
49974.65/7456.52	% SZS status Started for HL403488+4.p
49974.65/7456.52	% SZS status GaveUp for HL403488+4.p
49974.65/7456.52	eprover: CPU time limit exceeded, terminating
49974.65/7456.52	% SZS status Ended for HL403488+4.p
49985.78/7457.93	% SZS status Started for HL403492+5.p
49985.78/7457.93	% SZS status GaveUp for HL403492+5.p
49985.78/7457.93	% SZS status Ended for HL403492+5.p
49992.34/7458.88	% SZS status Started for HL403489+4.p
49992.34/7458.88	% SZS status GaveUp for HL403489+4.p
49992.34/7458.88	eprover: CPU time limit exceeded, terminating
49992.34/7458.88	% SZS status Ended for HL403489+4.p
50037.15/7464.40	% SZS status Started for HL403493+5.p
50037.15/7464.40	% SZS status GaveUp for HL403493+5.p
50037.15/7464.40	% SZS status Ended for HL403493+5.p
50038.86/7464.64	% SZS status Started for HL403490+4.p
50038.86/7464.64	% SZS status GaveUp for HL403490+4.p
50038.86/7464.64	eprover: CPU time limit exceeded, terminating
50038.86/7464.64	% SZS status Ended for HL403490+4.p
50056.32/7466.86	% SZS status Started for HL403495+5.p
50056.32/7466.86	% SZS status GaveUp for HL403495+5.p
50056.32/7466.86	% SZS status Ended for HL403495+5.p
50072.86/7468.93	% SZS status Started for HL403491+4.p
50072.86/7468.93	% SZS status GaveUp for HL403491+4.p
50072.86/7468.93	eprover: CPU time limit exceeded, terminating
50072.86/7468.93	% SZS status Ended for HL403491+4.p
50108.16/7473.35	% SZS status Started for HL403498+5.p
50108.16/7473.35	% SZS status GaveUp for HL403498+5.p
50108.16/7473.35	% SZS status Ended for HL403498+5.p
50112.39/7473.86	% SZS status Started for HL403492+4.p
50112.39/7473.86	% SZS status GaveUp for HL403492+4.p
50112.39/7473.86	eprover: CPU time limit exceeded, terminating
50112.39/7473.86	% SZS status Ended for HL403492+4.p
50127.38/7475.78	% SZS status Started for HL403499+5.p
50127.38/7475.78	% SZS status GaveUp for HL403499+5.p
50127.38/7475.78	% SZS status Ended for HL403499+5.p
50158.75/7479.71	% SZS status Started for HL403493+4.p
50158.75/7479.71	% SZS status GaveUp for HL403493+4.p
50158.75/7479.71	eprover: CPU time limit exceeded, terminating
50158.75/7479.71	% SZS status Ended for HL403493+4.p
50175.26/7481.82	% SZS status Started for HL403495+4.p
50175.26/7481.82	% SZS status GaveUp for HL403495+4.p
50175.26/7481.82	eprover: CPU time limit exceeded, terminating
50175.26/7481.82	% SZS status Ended for HL403495+4.p
50180.34/7482.41	% SZS status Started for HL403500+5.p
50180.34/7482.41	% SZS status GaveUp for HL403500+5.p
50180.34/7482.41	% SZS status Ended for HL403500+5.p
50195.03/7484.30	% SZS status Started for HL403498+4.p
50195.03/7484.30	% SZS status GaveUp for HL403498+4.p
50195.03/7484.30	eprover: CPU time limit exceeded, terminating
50195.03/7484.30	% SZS status Ended for HL403498+4.p
50199.09/7484.77	% SZS status Started for HL403502+5.p
50199.09/7484.77	% SZS status GaveUp for HL403502+5.p
50199.09/7484.77	% SZS status Ended for HL403502+5.p
50241.77/7490.19	% SZS status Started for HL403499+4.p
50241.77/7490.19	% SZS status GaveUp for HL403499+4.p
50241.77/7490.19	eprover: CPU time limit exceeded, terminating
50241.77/7490.19	% SZS status Ended for HL403499+4.p
50248.61/7491.04	% SZS status Started for HL403503+5.p
50248.61/7491.04	% SZS status GaveUp for HL403503+5.p
50248.61/7491.04	% SZS status Ended for HL403503+5.p
50266.70/7493.27	% SZS status Started for HL403504+5.p
50266.70/7493.27	% SZS status GaveUp for HL403504+5.p
50266.70/7493.27	% SZS status Ended for HL403504+5.p
50274.84/7494.33	% SZS status Started for HL403500+4.p
50274.84/7494.33	% SZS status GaveUp for HL403500+4.p
50274.84/7494.33	eprover: CPU time limit exceeded, terminating
50274.84/7494.33	% SZS status Ended for HL403500+4.p
50318.05/7499.68	% SZS status Started for HL403505+5.p
50318.05/7499.68	% SZS status GaveUp for HL403505+5.p
50318.05/7499.68	% SZS status Ended for HL403505+5.p
50318.80/7499.78	% SZS status Started for HL403502+4.p
50318.80/7499.78	% SZS status GaveUp for HL403502+4.p
50318.80/7499.78	eprover: CPU time limit exceeded, terminating
50318.80/7499.78	% SZS status Ended for HL403502+4.p
50343.32/7502.90	% SZS status Started for HL403506+5.p
50343.32/7502.90	% SZS status GaveUp for HL403506+5.p
50343.32/7502.90	% SZS status Ended for HL403506+5.p
50360.91/7505.17	% SZS status Started for HL403503+4.p
50360.91/7505.17	% SZS status GaveUp for HL403503+4.p
50360.91/7505.17	eprover: CPU time limit exceeded, terminating
50360.91/7505.17	% SZS status Ended for HL403503+4.p
50382.37/7507.86	% SZS status Started for HL403504+4.p
50382.37/7507.86	% SZS status GaveUp for HL403504+4.p
50382.37/7507.86	eprover: CPU time limit exceeded, terminating
50382.37/7507.86	% SZS status Ended for HL403504+4.p
50389.18/7508.73	% SZS status Started for HL403507+5.p
50389.18/7508.73	% SZS status GaveUp for HL403507+5.p
50389.18/7508.73	% SZS status Ended for HL403507+5.p
50401.90/7510.32	% SZS status Started for HL403505+4.p
50401.90/7510.32	% SZS status GaveUp for HL403505+4.p
50401.90/7510.32	eprover: CPU time limit exceeded, terminating
50401.90/7510.32	% SZS status Ended for HL403505+4.p
50415.29/7512.12	% SZS status Started for HL403509+5.p
50415.29/7512.12	% SZS status GaveUp for HL403509+5.p
50415.29/7512.12	% SZS status Ended for HL403509+5.p
50455.41/7517.06	% SZS status Started for HL403511+5.p
50455.41/7517.06	% SZS status GaveUp for HL403511+5.p
50455.41/7517.06	% SZS status Ended for HL403511+5.p
50456.23/7517.14	% SZS status Started for HL403506+4.p
50456.23/7517.14	% SZS status GaveUp for HL403506+4.p
50456.23/7517.14	eprover: CPU time limit exceeded, terminating
50456.23/7517.14	% SZS status Ended for HL403506+4.p
50473.29/7519.32	% SZS status Started for HL403512+5.p
50473.29/7519.32	% SZS status GaveUp for HL403512+5.p
50473.29/7519.32	% SZS status Ended for HL403512+5.p
50486.23/7520.91	% SZS status Started for HL403507+4.p
50486.23/7520.91	% SZS status GaveUp for HL403507+4.p
50486.23/7520.91	eprover: CPU time limit exceeded, terminating
50486.23/7520.91	% SZS status Ended for HL403507+4.p
50522.84/7525.58	% SZS status Started for HL403509+4.p
50522.84/7525.58	% SZS status GaveUp for HL403509+4.p
50522.84/7525.58	eprover: CPU time limit exceeded, terminating
50522.84/7525.58	% SZS status Ended for HL403509+4.p
50526.68/7526.05	% SZS status Started for HL403513+5.p
50526.68/7526.05	% SZS status GaveUp for HL403513+5.p
50526.68/7526.05	% SZS status Ended for HL403513+5.p
50545.84/7528.51	% SZS status Started for HL403514+5.p
50545.84/7528.51	% SZS status GaveUp for HL403514+5.p
50545.84/7528.51	% SZS status Ended for HL403514+5.p
50561.61/7530.43	% SZS status Started for HL403511+4.p
50561.61/7530.43	% SZS status GaveUp for HL403511+4.p
50561.61/7530.43	eprover: CPU time limit exceeded, terminating
50561.61/7530.43	% SZS status Ended for HL403511+4.p
50590.14/7534.04	% SZS status Started for HL403512+4.p
50590.14/7534.04	% SZS status GaveUp for HL403512+4.p
50590.14/7534.04	eprover: CPU time limit exceeded, terminating
50590.14/7534.04	% SZS status Ended for HL403512+4.p
50594.61/7534.62	% SZS status Started for HL403515+5.p
50594.61/7534.62	% SZS status GaveUp for HL403515+5.p
50594.61/7534.62	% SZS status Ended for HL403515+5.p
50617.10/7537.46	% SZS status Started for HL403516+5.p
50617.10/7537.46	% SZS status GaveUp for HL403516+5.p
50617.10/7537.46	% SZS status Ended for HL403516+5.p
50618.67/7537.68	% SZS status Started for HL403513+4.p
50618.67/7537.68	% SZS status GaveUp for HL403513+4.p
50618.67/7537.68	eprover: CPU time limit exceeded, terminating
50618.67/7537.68	% SZS status Ended for HL403513+4.p
50656.33/7542.45	% SZS status Started for HL403514+4.p
50656.33/7542.45	% SZS status GaveUp for HL403514+4.p
50656.33/7542.45	eprover: CPU time limit exceeded, terminating
50656.33/7542.45	% SZS status Ended for HL403514+4.p
50660.26/7542.93	% SZS status Started for HL403517+5.p
50660.26/7542.93	% SZS status GaveUp for HL403517+5.p
50660.26/7542.93	% SZS status Ended for HL403517+5.p
50689.06/7546.48	% SZS status Started for HL403515+4.p
50689.06/7546.48	% SZS status GaveUp for HL403515+4.p
50689.06/7546.48	eprover: CPU time limit exceeded, terminating
50689.06/7546.48	% SZS status Ended for HL403515+4.p
50689.56/7546.57	% SZS status Started for HL403519+5.p
50689.56/7546.57	% SZS status GaveUp for HL403519+5.p
50689.56/7546.57	% SZS status Ended for HL403519+5.p
50727.00/7551.36	% SZS status Started for HL403516+4.p
50727.00/7551.36	% SZS status GaveUp for HL403516+4.p
50727.00/7551.36	eprover: CPU time limit exceeded, terminating
50727.00/7551.36	% SZS status Ended for HL403516+4.p
50728.18/7551.57	% SZS status Started for HL403520+5.p
50728.18/7551.57	% SZS status GaveUp for HL403520+5.p
50728.18/7551.57	% SZS status Ended for HL403520+5.p
50760.70/7555.46	% SZS status Started for HL403521+5.p
50760.70/7555.46	% SZS status GaveUp for HL403521+5.p
50760.70/7555.46	% SZS status Ended for HL403521+5.p
50763.16/7555.74	% SZS status Started for HL403517+4.p
50763.16/7555.74	% SZS status GaveUp for HL403517+4.p
50763.16/7555.74	eprover: CPU time limit exceeded, terminating
50763.16/7555.74	% SZS status Ended for HL403517+4.p
50796.87/7559.98	% SZS status Started for HL403519+4.p
50796.87/7559.98	% SZS status GaveUp for HL403519+4.p
50796.87/7559.98	eprover: CPU time limit exceeded, terminating
50796.87/7559.98	% SZS status Ended for HL403519+4.p
50798.13/7560.25	% SZS status Started for HL403522+5.p
50798.13/7560.25	% SZS status GaveUp for HL403522+5.p
50798.13/7560.25	% SZS status Ended for HL403522+5.p
50820.56/7563.06	% SZS status Started for HL403520+4.p
50820.56/7563.06	% SZS status GaveUp for HL403520+4.p
50820.56/7563.06	eprover: CPU time limit exceeded, terminating
50820.56/7563.06	% SZS status Ended for HL403520+4.p
50832.44/7564.46	% SZS status Started for HL403523+5.p
50832.44/7564.46	% SZS status GaveUp for HL403523+5.p
50832.44/7564.46	% SZS status Ended for HL403523+5.p
50863.30/7568.47	% SZS status Started for HL403521+4.p
50863.30/7568.47	% SZS status GaveUp for HL403521+4.p
50863.30/7568.47	eprover: CPU time limit exceeded, terminating
50863.30/7568.47	% SZS status Ended for HL403521+4.p
50869.04/7569.03	% SZS status Started for HL403524+5.p
50869.04/7569.03	% SZS status GaveUp for HL403524+5.p
50869.04/7569.03	% SZS status Ended for HL403524+5.p
50890.95/7571.82	% SZS status Started for HL403522+4.p
50890.95/7571.82	% SZS status GaveUp for HL403522+4.p
50890.95/7571.82	eprover: CPU time limit exceeded, terminating
50890.95/7571.82	% SZS status Ended for HL403522+4.p
50891.95/7571.99	% SZS status Started for HL403525+5.p
50891.95/7571.99	% SZS status GaveUp for HL403525+5.p
50891.95/7571.99	% SZS status Ended for HL403525+5.p
50931.10/7576.89	% SZS status Started for HL403523+4.p
50931.10/7576.89	% SZS status GaveUp for HL403523+4.p
50931.10/7576.89	eprover: CPU time limit exceeded, terminating
50931.10/7576.89	% SZS status Ended for HL403523+4.p
50936.00/7577.47	% SZS status Started for HL403526+5.p
50936.00/7577.47	% SZS status GaveUp for HL403526+5.p
50936.00/7577.47	% SZS status Ended for HL403526+5.p
50962.79/7580.81	% SZS status Started for HL403527+5.p
50962.79/7580.81	% SZS status GaveUp for HL403527+5.p
50962.79/7580.81	% SZS status Ended for HL403527+5.p
50964.03/7581.03	% SZS status Started for HL403524+4.p
50964.03/7581.03	% SZS status GaveUp for HL403524+4.p
50964.03/7581.03	eprover: CPU time limit exceeded, terminating
50964.03/7581.03	% SZS status Ended for HL403524+4.p
50998.90/7585.47	% SZS status Started for HL403525+4.p
50998.90/7585.47	% SZS status GaveUp for HL403525+4.p
50998.90/7585.47	eprover: CPU time limit exceeded, terminating
50998.90/7585.47	% SZS status Ended for HL403525+4.p
51001.89/7585.78	% SZS status Started for HL403528+5.p
51001.89/7585.78	% SZS status GaveUp for HL403528+5.p
51001.89/7585.78	% SZS status Ended for HL403528+5.p
51034.16/7589.77	% SZS status Started for HL403529+5.p
51034.16/7589.77	% SZS status GaveUp for HL403529+5.p
51034.16/7589.77	% SZS status Ended for HL403529+5.p
51034.68/7589.87	% SZS status Started for HL403526+4.p
51034.68/7589.87	% SZS status GaveUp for HL403526+4.p
51034.68/7589.87	eprover: CPU time limit exceeded, terminating
51034.68/7589.87	% SZS status Ended for HL403526+4.p
51069.89/7594.45	% SZS status Started for HL403527+4.p
51069.89/7594.45	% SZS status GaveUp for HL403527+4.p
51069.89/7594.45	eprover: CPU time limit exceeded, terminating
51069.89/7594.45	% SZS status Ended for HL403527+4.p
51071.80/7594.75	% SZS status Started for HL403530+5.p
51071.80/7594.75	% SZS status GaveUp for HL403530+5.p
51071.80/7594.75	% SZS status Ended for HL403530+5.p
51095.20/7597.83	% SZS status Started for HL403528+4.p
51095.20/7597.83	% SZS status GaveUp for HL403528+4.p
51095.20/7597.83	eprover: CPU time limit exceeded, terminating
51095.20/7597.83	% SZS status Ended for HL403528+4.p
51106.04/7599.30	% SZS status Started for HL403532+5.p
51106.04/7599.30	% SZS status GaveUp for HL403532+5.p
51106.04/7599.30	% SZS status Ended for HL403532+5.p
51136.93/7603.28	% SZS status Started for HL403529+4.p
51136.93/7603.28	% SZS status GaveUp for HL403529+4.p
51136.93/7603.28	eprover: CPU time limit exceeded, terminating
51136.93/7603.28	% SZS status Ended for HL403529+4.p
51145.77/7604.42	% SZS status Started for HL403533+5.p
51145.77/7604.42	% SZS status GaveUp for HL403533+5.p
51145.77/7604.42	% SZS status Ended for HL403533+5.p
51167.91/7607.19	% SZS status Started for HL403530+4.p
51167.91/7607.19	% SZS status GaveUp for HL403530+4.p
51167.91/7607.19	eprover: CPU time limit exceeded, terminating
51167.91/7607.19	% SZS status Ended for HL403530+4.p
51169.55/7607.61	% SZS status Started for HL403534+5.p
51169.55/7607.61	% SZS status GaveUp for HL403534+5.p
51169.55/7607.61	% SZS status Ended for HL403534+5.p
51200.25/7611.46	% SZS status Started for HL403532+4.p
51200.25/7611.46	% SZS status GaveUp for HL403532+4.p
51200.25/7611.46	eprover: CPU time limit exceeded, terminating
51200.25/7611.46	% SZS status Ended for HL403532+4.p
51206.52/7612.24	% SZS status Started for HL403535+5.p
51206.52/7612.24	% SZS status GaveUp for HL403535+5.p
51206.52/7612.24	% SZS status Ended for HL403535+5.p
51237.89/7616.17	% SZS status Started for HL403533+4.p
51237.89/7616.17	% SZS status GaveUp for HL403533+4.p
51237.89/7616.17	eprover: CPU time limit exceeded, terminating
51237.89/7616.17	% SZS status Ended for HL403533+4.p
51239.54/7616.37	% SZS status Started for HL403536+5.p
51239.54/7616.37	% SZS status GaveUp for HL403536+5.p
51239.54/7616.37	% SZS status Ended for HL403536+5.p
51272.58/7620.58	% SZS status Started for HL403537+5.p
51272.58/7620.58	% SZS status GaveUp for HL403537+5.p
51272.58/7620.58	% SZS status Ended for HL403537+5.p
51274.11/7620.77	% SZS status Started for HL403534+4.p
51274.11/7620.77	% SZS status GaveUp for HL403534+4.p
51274.11/7620.77	eprover: CPU time limit exceeded, terminating
51274.11/7620.77	% SZS status Ended for HL403534+4.p
51309.68/7625.17	% SZS status Started for HL403538+5.p
51309.68/7625.17	% SZS status GaveUp for HL403538+5.p
51309.68/7625.17	% SZS status Ended for HL403538+5.p
51314.27/7625.77	% SZS status Started for HL403535+4.p
51314.27/7625.77	% SZS status GaveUp for HL403535+4.p
51314.27/7625.77	eprover: CPU time limit exceeded, terminating
51314.27/7625.77	% SZS status Ended for HL403535+4.p
51344.40/7629.56	% SZS status Started for HL403539+5.p
51344.40/7629.56	% SZS status GaveUp for HL403539+5.p
51344.40/7629.56	% SZS status Ended for HL403539+5.p
51347.32/7629.95	% SZS status Started for HL403536+4.p
51347.32/7629.95	% SZS status GaveUp for HL403536+4.p
51347.32/7629.95	eprover: CPU time limit exceeded, terminating
51347.32/7629.95	% SZS status Ended for HL403536+4.p
51370.76/7632.91	% SZS status Started for HL403537+4.p
51370.76/7632.91	% SZS status GaveUp for HL403537+4.p
51370.76/7632.91	eprover: CPU time limit exceeded, terminating
51370.76/7632.91	% SZS status Ended for HL403537+4.p
51383.11/7634.46	% SZS status Started for HL403540+5.p
51383.11/7634.46	% SZS status GaveUp for HL403540+5.p
51383.11/7634.46	% SZS status Ended for HL403540+5.p
51407.48/7637.58	% SZS status Started for HL403538+4.p
51407.48/7637.58	% SZS status GaveUp for HL403538+4.p
51407.48/7637.58	eprover: CPU time limit exceeded, terminating
51407.48/7637.58	% SZS status Ended for HL403538+4.p
51414.85/7638.51	% SZS status Started for HL403541+5.p
51414.85/7638.51	% SZS status GaveUp for HL403541+5.p
51414.85/7638.51	% SZS status Ended for HL403541+5.p
51443.73/7642.10	% SZS status Started for HL403542+5.p
51443.73/7642.10	% SZS status GaveUp for HL403542+5.p
51443.73/7642.10	% SZS status Ended for HL403542+5.p
51443.73/7642.11	% SZS status Started for HL403539+4.p
51443.73/7642.11	% SZS status GaveUp for HL403539+4.p
51443.73/7642.11	eprover: CPU time limit exceeded, terminating
51443.73/7642.11	% SZS status Ended for HL403539+4.p
51476.65/7646.32	% SZS status Started for HL403540+4.p
51476.65/7646.32	% SZS status GaveUp for HL403540+4.p
51476.65/7646.32	eprover: CPU time limit exceeded, terminating
51476.65/7646.32	% SZS status Ended for HL403540+4.p
51478.73/7646.50	% SZS status Started for HL403543+5.p
51478.73/7646.50	% SZS status GaveUp for HL403543+5.p
51478.73/7646.50	% SZS status Ended for HL403543+5.p
51516.29/7651.29	% SZS status Started for HL403544+5.p
51516.29/7651.29	% SZS status GaveUp for HL403544+5.p
51516.29/7651.29	% SZS status Ended for HL403544+5.p
51518.89/7651.62	% SZS status Started for HL403541+4.p
51518.89/7651.62	% SZS status GaveUp for HL403541+4.p
51518.89/7651.62	eprover: CPU time limit exceeded, terminating
51518.89/7651.62	% SZS status Ended for HL403541+4.p
51549.41/7655.44	% SZS status Started for HL403545+5.p
51549.41/7655.44	% SZS status GaveUp for HL403545+5.p
51549.41/7655.44	% SZS status Ended for HL403545+5.p
51551.68/7655.79	% SZS status Started for HL403542+4.p
51551.68/7655.79	% SZS status GaveUp for HL403542+4.p
51551.68/7655.79	eprover: CPU time limit exceeded, terminating
51551.68/7655.79	% SZS status Ended for HL403542+4.p
51583.18/7659.74	% SZS status Started for HL403543+4.p
51583.18/7659.74	% SZS status GaveUp for HL403543+4.p
51583.18/7659.74	eprover: CPU time limit exceeded, terminating
51583.18/7659.74	% SZS status Ended for HL403543+4.p
51587.52/7660.25	% SZS status Started for HL403546+5.p
51587.52/7660.25	% SZS status GaveUp for HL403546+5.p
51587.52/7660.25	% SZS status Ended for HL403546+5.p
51618.63/7664.16	% SZS status Started for HL403544+4.p
51618.63/7664.16	% SZS status GaveUp for HL403544+4.p
51618.63/7664.16	eprover: CPU time limit exceeded, terminating
51618.63/7664.16	% SZS status Ended for HL403544+4.p
51620.85/7664.50	% SZS status Started for HL403547+5.p
51620.85/7664.50	% SZS status GaveUp for HL403547+5.p
51620.85/7664.50	% SZS status Ended for HL403547+5.p
51644.18/7667.37	% SZS status Started for HL403545+4.p
51644.18/7667.37	% SZS status GaveUp for HL403545+4.p
51644.18/7667.37	eprover: CPU time limit exceeded, terminating
51644.18/7667.37	% SZS status Ended for HL403545+4.p
51655.41/7668.80	% SZS status Started for HL403548+5.p
51655.41/7668.80	% SZS status GaveUp for HL403548+5.p
51655.41/7668.80	% SZS status Ended for HL403548+5.p
51680.12/7671.90	% SZS status Started for HL403546+4.p
51680.12/7671.90	% SZS status GaveUp for HL403546+4.p
51680.12/7671.90	eprover: CPU time limit exceeded, terminating
51680.12/7671.90	% SZS status Ended for HL403546+4.p
51689.08/7673.16	% SZS status Started for HL403550+5.p
51689.08/7673.16	% SZS status GaveUp for HL403550+5.p
51689.08/7673.16	% SZS status Ended for HL403550+5.p
51716.65/7676.49	% SZS status Started for HL403551+5.p
51716.65/7676.49	% SZS status GaveUp for HL403551+5.p
51716.65/7676.49	% SZS status Ended for HL403551+5.p
51719.11/7676.88	% SZS status Started for HL403547+4.p
51719.11/7676.88	% SZS status GaveUp for HL403547+4.p
51719.11/7676.88	eprover: CPU time limit exceeded, terminating
51719.11/7676.88	% SZS status Ended for HL403547+4.p
51751.06/7680.91	% SZS status Started for HL403552+5.p
51751.06/7680.91	% SZS status GaveUp for HL403552+5.p
51751.06/7680.91	% SZS status Ended for HL403552+5.p
51754.67/7681.34	% SZS status Started for HL403548+4.p
51754.67/7681.34	% SZS status GaveUp for HL403548+4.p
51754.67/7681.34	eprover: CPU time limit exceeded, terminating
51754.67/7681.34	% SZS status Ended for HL403548+4.p
51788.32/7685.52	% SZS status Started for HL403553+5.p
51788.32/7685.52	% SZS status GaveUp for HL403553+5.p
51788.32/7685.52	% SZS status Ended for HL403553+5.p
51789.68/7685.81	% SZS status Started for HL403550+4.p
51789.68/7685.81	% SZS status GaveUp for HL403550+4.p
51789.68/7685.81	eprover: CPU time limit exceeded, terminating
51789.68/7685.81	% SZS status Ended for HL403550+4.p
51822.04/7689.84	% SZS status Started for HL403551+4.p
51822.04/7689.84	% SZS status GaveUp for HL403551+4.p
51822.04/7689.84	eprover: CPU time limit exceeded, terminating
51822.04/7689.84	% SZS status Ended for HL403551+4.p
51822.75/7689.88	% SZS status Started for HL403554+5.p
51822.75/7689.88	% SZS status GaveUp for HL403554+5.p
51822.75/7689.88	% SZS status Ended for HL403554+5.p
51838.35/7691.91	% SZS status Started for HL403555+5.p
51838.35/7691.91	% SZS status Theorem for HL403555+5.p
51838.35/7691.91	% SZS status Ended for HL403555+5.p
51856.69/7694.17	% SZS status Started for HL403552+4.p
51856.69/7694.17	% SZS status GaveUp for HL403552+4.p
51856.69/7694.17	eprover: CPU time limit exceeded, terminating
51856.69/7694.17	% SZS status Ended for HL403552+4.p
51892.15/7698.62	% SZS status Started for HL403553+4.p
51892.15/7698.62	% SZS status GaveUp for HL403553+4.p
51892.15/7698.62	eprover: CPU time limit exceeded, terminating
51892.15/7698.62	% SZS status Ended for HL403553+4.p
51894.63/7698.93	% SZS status Started for HL403556+5.p
51894.63/7698.93	% SZS status GaveUp for HL403556+5.p
51894.63/7698.93	% SZS status Ended for HL403556+5.p
51908.53/7700.81	% SZS status Started for HL403557+5.p
51908.53/7700.81	% SZS status GaveUp for HL403557+5.p
51908.53/7700.81	% SZS status Ended for HL403557+5.p
51920.71/7702.21	% SZS status Started for HL403554+4.p
51920.71/7702.21	% SZS status GaveUp for HL403554+4.p
51920.71/7702.21	eprover: CPU time limit exceeded, terminating
51920.71/7702.21	% SZS status Ended for HL403554+4.p
51957.57/7706.83	% SZS status Started for HL403555+4.p
51957.57/7706.83	% SZS status GaveUp for HL403555+4.p
51957.57/7706.83	eprover: CPU time limit exceeded, terminating
51957.57/7706.83	% SZS status Ended for HL403555+4.p
51958.11/7706.90	% SZS status Started for HL403559+5.p
51958.11/7706.90	% SZS status Theorem for HL403559+5.p
51958.11/7706.90	% SZS status Ended for HL403559+5.p
51964.01/7707.65	% SZS status Started for HL403558+5.p
51964.01/7707.65	% SZS status GaveUp for HL403558+5.p
51964.01/7707.65	% SZS status Ended for HL403558+5.p
51991.02/7711.10	% SZS status Started for HL403556+4.p
51991.02/7711.10	% SZS status GaveUp for HL403556+4.p
51991.02/7711.10	eprover: CPU time limit exceeded, terminating
51991.02/7711.10	% SZS status Ended for HL403556+4.p
52025.62/7715.40	% SZS status Started for HL403557+4.p
52025.62/7715.40	% SZS status GaveUp for HL403557+4.p
52025.62/7715.40	eprover: CPU time limit exceeded, terminating
52025.62/7715.40	% SZS status Ended for HL403557+4.p
52028.12/7715.75	% SZS status Started for HL403560+5.p
52028.12/7715.75	% SZS status GaveUp for HL403560+5.p
52028.12/7715.75	% SZS status Ended for HL403560+5.p
52034.90/7716.58	% SZS status Started for HL403561+5.p
52034.90/7716.58	% SZS status GaveUp for HL403561+5.p
52034.90/7716.58	% SZS status Ended for HL403561+5.p
52061.10/7719.87	% SZS status Started for HL403558+4.p
52061.10/7719.87	% SZS status GaveUp for HL403558+4.p
52061.10/7719.87	eprover: CPU time limit exceeded, terminating
52061.10/7719.87	% SZS status Ended for HL403558+4.p
52097.39/7724.42	% SZS status Started for HL403562+5.p
52097.39/7724.42	% SZS status GaveUp for HL403562+5.p
52097.39/7724.42	% SZS status Ended for HL403562+5.p
52098.89/7724.63	% SZS status Started for HL403559+4.p
52098.89/7724.63	% SZS status GaveUp for HL403559+4.p
52098.89/7724.63	eprover: CPU time limit exceeded, terminating
52098.89/7724.63	% SZS status Ended for HL403559+4.p
52106.93/7725.60	% SZS status Started for HL403563+5.p
52106.93/7725.60	% SZS status GaveUp for HL403563+5.p
52106.93/7725.60	% SZS status Ended for HL403563+5.p
52122.06/7727.52	% SZS status Started for HL403560+4.p
52122.06/7727.52	% SZS status GaveUp for HL403560+4.p
52122.06/7727.52	eprover: CPU time limit exceeded, terminating
52122.06/7727.52	% SZS status Ended for HL403560+4.p
52160.00/7732.34	% SZS status Started for HL403561+4.p
52160.00/7732.34	% SZS status GaveUp for HL403561+4.p
52160.00/7732.34	eprover: CPU time limit exceeded, terminating
52160.00/7732.34	% SZS status Ended for HL403561+4.p
52168.89/7733.42	% SZS status Started for HL403565+5.p
52168.89/7733.42	% SZS status GaveUp for HL403565+5.p
52168.89/7733.42	% SZS status Ended for HL403565+5.p
52178.23/7734.60	% SZS status Started for HL403566+5.p
52178.23/7734.60	% SZS status GaveUp for HL403566+5.p
52178.23/7734.60	% SZS status Ended for HL403566+5.p
52192.69/7736.43	% SZS status Started for HL403562+4.p
52192.69/7736.43	% SZS status GaveUp for HL403562+4.p
52192.69/7736.43	eprover: CPU time limit exceeded, terminating
52192.69/7736.43	% SZS status Ended for HL403562+4.p
52231.60/7741.32	% SZS status Started for HL403563+4.p
52231.60/7741.32	% SZS status GaveUp for HL403563+4.p
52231.60/7741.32	eprover: CPU time limit exceeded, terminating
52231.60/7741.32	% SZS status Ended for HL403563+4.p
52233.51/7741.58	% SZS status Started for HL403567+5.p
52233.51/7741.58	% SZS status GaveUp for HL403567+5.p
52233.51/7741.58	% SZS status Ended for HL403567+5.p
52251.34/7743.83	% SZS status Started for HL403568+5.p
52251.34/7743.83	% SZS status GaveUp for HL403568+5.p
52251.34/7743.83	% SZS status Ended for HL403568+5.p
52267.89/7745.91	% SZS status Started for HL403565+4.p
52267.89/7745.91	% SZS status GaveUp for HL403565+4.p
52267.89/7745.91	eprover: CPU time limit exceeded, terminating
52267.89/7745.91	% SZS status Ended for HL403565+4.p
52299.63/7749.90	% SZS status Started for HL403566+4.p
52299.63/7749.90	% SZS status GaveUp for HL403566+4.p
52299.63/7749.90	eprover: CPU time limit exceeded, terminating
52299.63/7749.90	% SZS status Ended for HL403566+4.p
52304.23/7750.46	% SZS status Started for HL403570+5.p
52304.23/7750.46	% SZS status GaveUp for HL403570+5.p
52304.23/7750.46	% SZS status Ended for HL403570+5.p
52322.61/7752.82	% SZS status Started for HL403571+5.p
52322.61/7752.82	% SZS status GaveUp for HL403571+5.p
52322.61/7752.82	% SZS status Ended for HL403571+5.p
52322.61/7752.85	% SZS status Started for HL403567+4.p
52322.61/7752.85	% SZS status GaveUp for HL403567+4.p
52322.61/7752.85	eprover: CPU time limit exceeded, terminating
52322.61/7752.85	% SZS status Ended for HL403567+4.p
52369.61/7758.76	% SZS status Started for HL403572+5.p
52369.61/7758.76	% SZS status GaveUp for HL403572+5.p
52369.61/7758.76	% SZS status Ended for HL403572+5.p
52374.24/7759.46	% SZS status Started for HL403568+4.p
52374.24/7759.46	% SZS status GaveUp for HL403568+4.p
52374.24/7759.46	eprover: CPU time limit exceeded, terminating
52374.24/7759.46	% SZS status Ended for HL403568+4.p
52396.76/7762.51	% SZS status Started for HL403573+5.p
52396.76/7762.51	% SZS status GaveUp for HL403573+5.p
52396.76/7762.51	% SZS status Ended for HL403573+5.p
52399.30/7762.75	% SZS status Started for HL403570+4.p
52399.30/7762.75	% SZS status GaveUp for HL403570+4.p
52399.30/7762.75	eprover: CPU time limit exceeded, terminating
52399.30/7762.75	% SZS status Ended for HL403570+4.p
52442.31/7768.28	% SZS status Started for HL403571+4.p
52442.31/7768.28	% SZS status GaveUp for HL403571+4.p
52442.31/7768.28	eprover: CPU time limit exceeded, terminating
52442.31/7768.28	% SZS status Ended for HL403571+4.p
52444.31/7768.53	% SZS status Started for HL403574+5.p
52444.31/7768.53	% SZS status GaveUp for HL403574+5.p
52444.31/7768.53	% SZS status Ended for HL403574+5.p
52469.32/7771.76	% SZS status Started for HL403572+4.p
52469.32/7771.76	% SZS status GaveUp for HL403572+4.p
52469.32/7771.76	eprover: CPU time limit exceeded, terminating
52469.32/7771.76	% SZS status Ended for HL403572+4.p
52472.84/7772.19	% SZS status Started for HL403575+5.p
52472.84/7772.19	% SZS status GaveUp for HL403575+5.p
52472.84/7772.19	% SZS status Ended for HL403575+5.p
52505.05/7776.32	% SZS status Started for HL403573+4.p
52505.05/7776.32	% SZS status GaveUp for HL403573+4.p
52505.05/7776.32	eprover: CPU time limit exceeded, terminating
52505.05/7776.32	% SZS status Ended for HL403573+4.p
52512.56/7777.24	% SZS status Started for HL403578+5.p
52512.56/7777.24	% SZS status Theorem for HL403578+5.p
52512.56/7777.24	% SZS status Ended for HL403578+5.p
52514.38/7777.50	% SZS status Started for HL403576+5.p
52514.38/7777.50	% SZS status GaveUp for HL403576+5.p
52514.38/7777.50	% SZS status Ended for HL403576+5.p
52519.69/7778.22	% SZS status Started for HL403574+4.p
52519.69/7778.22	% SZS status GaveUp for HL403574+4.p
52519.69/7778.22	eprover: CPU time limit exceeded, terminating
52519.69/7778.22	% SZS status Ended for HL403574+4.p
52541.67/7780.91	% SZS status Started for HL403577+5.p
52541.67/7780.91	% SZS status GaveUp for HL403577+5.p
52541.67/7780.91	% SZS status Ended for HL403577+5.p
52577.53/7785.49	% SZS status Started for HL403575+4.p
52577.53/7785.49	% SZS status GaveUp for HL403575+4.p
52577.53/7785.49	eprover: CPU time limit exceeded, terminating
52577.53/7785.49	% SZS status Ended for HL403575+4.p
52584.82/7786.42	% SZS status Started for HL403579+5.p
52584.82/7786.42	% SZS status GaveUp for HL403579+5.p
52584.82/7786.42	% SZS status Ended for HL403579+5.p
52601.77/7788.73	% SZS status Started for HL403576+4.p
52601.77/7788.73	% SZS status GaveUp for HL403576+4.p
52601.77/7788.73	eprover: CPU time limit exceeded, terminating
52601.77/7788.73	% SZS status Ended for HL403576+4.p
52612.40/7789.88	% SZS status Started for HL403580+5.p
52612.40/7789.88	% SZS status GaveUp for HL403580+5.p
52612.40/7789.88	% SZS status Ended for HL403580+5.p
52647.54/7794.26	% SZS status Started for HL403577+4.p
52647.54/7794.26	% SZS status GaveUp for HL403577+4.p
52647.54/7794.26	eprover: CPU time limit exceeded, terminating
52647.54/7794.26	% SZS status Ended for HL403577+4.p
52656.30/7795.42	% SZS status Started for HL403581+5.p
52656.30/7795.42	% SZS status GaveUp for HL403581+5.p
52656.30/7795.42	% SZS status Ended for HL403581+5.p
52673.50/7797.56	% SZS status Started for HL403578+4.p
52673.50/7797.56	% SZS status GaveUp for HL403578+4.p
52673.50/7797.56	eprover: CPU time limit exceeded, terminating
52673.50/7797.56	% SZS status Ended for HL403578+4.p
52683.48/7798.88	% SZS status Started for HL403582+5.p
52683.48/7798.88	% SZS status GaveUp for HL403582+5.p
52683.48/7798.88	% SZS status Ended for HL403582+5.p
52713.71/7802.64	% SZS status Started for HL403579+4.p
52713.71/7802.64	% SZS status GaveUp for HL403579+4.p
52713.71/7802.64	eprover: CPU time limit exceeded, terminating
52713.71/7802.64	% SZS status Ended for HL403579+4.p
52723.00/7803.83	% SZS status Started for HL403580+4.p
52723.00/7803.83	% SZS status GaveUp for HL403580+4.p
52723.00/7803.83	eprover: CPU time limit exceeded, terminating
52723.00/7803.83	% SZS status Ended for HL403580+4.p
52724.79/7804.14	% SZS status Started for HL403583+5.p
52724.79/7804.14	% SZS status GaveUp for HL403583+5.p
52724.79/7804.14	% SZS status Ended for HL403583+5.p
52755.84/7808.00	% SZS status Started for HL403584+5.p
52755.84/7808.00	% SZS status GaveUp for HL403584+5.p
52755.84/7808.00	% SZS status Ended for HL403584+5.p
52778.47/7810.86	% SZS status Started for HL403581+4.p
52778.47/7810.86	% SZS status GaveUp for HL403581+4.p
52778.47/7810.86	eprover: CPU time limit exceeded, terminating
52778.47/7810.86	% SZS status Ended for HL403581+4.p
52795.47/7813.01	% SZS status Started for HL403585+5.p
52795.47/7813.01	% SZS status GaveUp for HL403585+5.p
52795.47/7813.01	% SZS status Ended for HL403585+5.p
52805.13/7814.14	% SZS status Started for HL403582+4.p
52805.13/7814.14	% SZS status GaveUp for HL403582+4.p
52805.13/7814.14	eprover: CPU time limit exceeded, terminating
52805.13/7814.14	% SZS status Ended for HL403582+4.p
52809.07/7814.63	% SZS status Started for HL403586+5.p
52809.07/7814.63	% SZS status Theorem for HL403586+5.p
52809.07/7814.63	% SZS status Ended for HL403586+5.p
52848.23/7819.56	% SZS status Started for HL403583+4.p
52848.23/7819.56	% SZS status GaveUp for HL403583+4.p
52848.23/7819.56	eprover: CPU time limit exceeded, terminating
52848.23/7819.56	% SZS status Ended for HL403583+4.p
52866.28/7821.86	% SZS status Started for HL403588+5.p
52866.28/7821.86	% SZS status GaveUp for HL403588+5.p
52866.28/7821.86	% SZS status Ended for HL403588+5.p
52875.81/7823.05	% SZS status Started for HL403584+4.p
52875.81/7823.05	% SZS status GaveUp for HL403584+4.p
52875.81/7823.05	eprover: CPU time limit exceeded, terminating
52875.81/7823.05	% SZS status Ended for HL403584+4.p
52882.56/7823.91	% SZS status Started for HL403589+5.p
52882.56/7823.91	% SZS status GaveUp for HL403589+5.p
52882.56/7823.91	% SZS status Ended for HL403589+5.p
52914.31/7827.95	% SZS status Started for HL403585+4.p
52914.31/7827.95	% SZS status GaveUp for HL403585+4.p
52914.31/7827.95	eprover: CPU time limit exceeded, terminating
52914.31/7827.95	% SZS status Ended for HL403585+4.p
52927.52/7829.56	% SZS status Started for HL403586+4.p
52927.52/7829.56	% SZS status GaveUp for HL403586+4.p
52927.52/7829.56	eprover: CPU time limit exceeded, terminating
52927.52/7829.56	% SZS status Ended for HL403586+4.p
52937.55/7830.80	% SZS status Started for HL403590+5.p
52937.55/7830.80	% SZS status GaveUp for HL403590+5.p
52937.55/7830.80	% SZS status Ended for HL403590+5.p
52956.84/7833.32	% SZS status Started for HL403591+5.p
52956.84/7833.32	% SZS status GaveUp for HL403591+5.p
52956.84/7833.32	% SZS status Ended for HL403591+5.p
52981.45/7836.34	% SZS status Started for HL403588+4.p
52981.45/7836.34	% SZS status GaveUp for HL403588+4.p
52981.45/7836.34	eprover: CPU time limit exceeded, terminating
52981.45/7836.34	% SZS status Ended for HL403588+4.p
52999.05/7838.57	% SZS status Started for HL403592+5.p
52999.05/7838.57	% SZS status GaveUp for HL403592+5.p
52999.05/7838.57	% SZS status Ended for HL403592+5.p
53004.52/7839.29	% SZS status Started for HL403589+4.p
53004.52/7839.29	% SZS status GaveUp for HL403589+4.p
53004.52/7839.29	eprover: CPU time limit exceeded, terminating
53004.52/7839.29	% SZS status Ended for HL403589+4.p
53028.48/7842.26	% SZS status Started for HL403593+5.p
53028.48/7842.26	% SZS status GaveUp for HL403593+5.p
53028.48/7842.26	% SZS status Ended for HL403593+5.p
53049.13/7844.85	% SZS status Started for HL403590+4.p
53049.13/7844.85	% SZS status GaveUp for HL403590+4.p
53049.13/7844.85	eprover: CPU time limit exceeded, terminating
53049.13/7844.85	% SZS status Ended for HL403590+4.p
53070.36/7847.56	% SZS status Started for HL403594+5.p
53070.36/7847.56	% SZS status GaveUp for HL403594+5.p
53070.36/7847.56	% SZS status Ended for HL403594+5.p
53075.90/7848.23	% SZS status Started for HL403591+4.p
53075.90/7848.23	% SZS status GaveUp for HL403591+4.p
53075.90/7848.23	eprover: CPU time limit exceeded, terminating
53075.90/7848.23	% SZS status Ended for HL403591+4.p
53099.91/7851.35	% SZS status Started for HL403595+5.p
53099.91/7851.35	% SZS status GaveUp for HL403595+5.p
53099.91/7851.35	% SZS status Ended for HL403595+5.p
53115.94/7853.36	% SZS status Started for HL403592+4.p
53115.94/7853.36	% SZS status GaveUp for HL403592+4.p
53115.94/7853.36	eprover: CPU time limit exceeded, terminating
53115.94/7853.36	% SZS status Ended for HL403592+4.p
53137.66/7856.07	% SZS status Started for HL403593+4.p
53137.66/7856.07	% SZS status GaveUp for HL403593+4.p
53137.66/7856.07	eprover: CPU time limit exceeded, terminating
53137.66/7856.07	% SZS status Ended for HL403593+4.p
53139.12/7856.30	% SZS status Started for HL403596+5.p
53139.12/7856.30	% SZS status GaveUp for HL403596+5.p
53139.12/7856.30	% SZS status Ended for HL403596+5.p
53169.26/7860.09	% SZS status Started for HL403597+5.p
53169.26/7860.09	% SZS status GaveUp for HL403597+5.p
53169.26/7860.09	% SZS status Ended for HL403597+5.p
53179.81/7861.48	% SZS status Started for HL403594+4.p
53179.81/7861.48	% SZS status GaveUp for HL403594+4.p
53179.81/7861.48	eprover: CPU time limit exceeded, terminating
53179.81/7861.48	% SZS status Ended for HL403594+4.p
53202.66/7864.34	% SZS status Started for HL403595+4.p
53202.66/7864.34	% SZS status GaveUp for HL403595+4.p
53202.66/7864.34	eprover: CPU time limit exceeded, terminating
53202.66/7864.34	% SZS status Ended for HL403595+4.p
53207.11/7864.85	% SZS status Started for HL403599+5.p
53207.11/7864.85	% SZS status GaveUp for HL403599+5.p
53207.11/7864.85	% SZS status Ended for HL403599+5.p
53240.73/7869.09	% SZS status Started for HL403601+5.p
53240.73/7869.09	% SZS status GaveUp for HL403601+5.p
53240.73/7869.09	% SZS status Ended for HL403601+5.p
53248.32/7870.06	% SZS status Started for HL403596+4.p
53248.32/7870.06	% SZS status GaveUp for HL403596+4.p
53248.32/7870.06	eprover: CPU time limit exceeded, terminating
53248.32/7870.06	% SZS status Ended for HL403596+4.p
53273.75/7873.29	% SZS status Started for HL403602+5.p
53273.75/7873.29	% SZS status GaveUp for HL403602+5.p
53273.75/7873.29	% SZS status Ended for HL403602+5.p
53287.38/7873.85	% SZS status Started for HL403597+4.p
53287.38/7873.85	% SZS status GaveUp for HL403597+4.p
53287.38/7873.85	eprover: CPU time limit exceeded, terminating
53287.38/7873.85	% SZS status Ended for HL403597+4.p
53320.20/7878.04	% SZS status Started for HL403603+5.p
53320.20/7878.04	% SZS status GaveUp for HL403603+5.p
53320.20/7878.04	% SZS status Ended for HL403603+5.p
53324.61/7878.53	% SZS status Started for HL403599+4.p
53324.61/7878.53	% SZS status GaveUp for HL403599+4.p
53324.61/7878.53	eprover: CPU time limit exceeded, terminating
53324.61/7878.53	% SZS status Ended for HL403599+4.p
53353.86/7882.25	% SZS status Started for HL403601+4.p
53353.86/7882.25	% SZS status GaveUp for HL403601+4.p
53353.86/7882.25	eprover: CPU time limit exceeded, terminating
53353.86/7882.25	% SZS status Ended for HL403601+4.p
53354.53/7882.31	% SZS status Started for HL403604+5.p
53354.53/7882.31	% SZS status GaveUp for HL403604+5.p
53354.53/7882.31	% SZS status Ended for HL403604+5.p
53388.24/7886.49	% SZS status Started for HL403602+4.p
53388.24/7886.49	% SZS status GaveUp for HL403602+4.p
53388.24/7886.49	eprover: CPU time limit exceeded, terminating
53388.24/7886.49	% SZS status Ended for HL403602+4.p
53393.37/7887.14	% SZS status Started for HL403605+5.p
53393.37/7887.14	% SZS status GaveUp for HL403605+5.p
53393.37/7887.14	% SZS status Ended for HL403605+5.p
53414.87/7889.84	% SZS status Started for HL403603+4.p
53414.87/7889.84	% SZS status GaveUp for HL403603+4.p
53414.87/7889.84	eprover: CPU time limit exceeded, terminating
53414.87/7889.84	% SZS status Ended for HL403603+4.p
53424.82/7891.17	% SZS status Started for HL403606+5.p
53424.82/7891.17	% SZS status GaveUp for HL403606+5.p
53424.82/7891.17	% SZS status Ended for HL403606+5.p
53452.79/7895.24	% SZS status Started for HL403604+4.p
53452.79/7895.24	% SZS status GaveUp for HL403604+4.p
53452.79/7895.24	eprover: CPU time limit exceeded, terminating
53452.79/7895.24	% SZS status Ended for HL403604+4.p
53458.30/7895.92	% SZS status Started for HL403607+5.p
53458.30/7895.92	% SZS status GaveUp for HL403607+5.p
53458.30/7895.92	% SZS status Ended for HL403607+5.p
53486.53/7899.55	% SZS status Started for HL403608+5.p
53486.53/7899.55	% SZS status GaveUp for HL403608+5.p
53486.53/7899.55	% SZS status Ended for HL403608+5.p
53496.63/7901.00	% SZS status Started for HL403605+4.p
53496.63/7901.00	% SZS status GaveUp for HL403605+4.p
53496.63/7901.00	eprover: CPU time limit exceeded, terminating
53496.63/7901.00	% SZS status Ended for HL403605+4.p
53521.79/7904.21	% SZS status Started for HL403606+4.p
53521.79/7904.21	% SZS status GaveUp for HL403606+4.p
53521.79/7904.21	eprover: CPU time limit exceeded, terminating
53521.79/7904.21	% SZS status Ended for HL403606+4.p
53528.48/7905.13	% SZS status Started for HL403610+5.p
53528.48/7905.13	% SZS status GaveUp for HL403610+5.p
53528.48/7905.13	% SZS status Ended for HL403610+5.p
53549.64/7907.86	% SZS status Started for HL403607+4.p
53549.64/7907.86	% SZS status GaveUp for HL403607+4.p
53549.64/7907.86	eprover: CPU time limit exceeded, terminating
53549.64/7907.86	% SZS status Ended for HL403607+4.p
53563.54/7909.58	% SZS status Started for HL403611+5.p
53563.54/7909.58	% SZS status GaveUp for HL403611+5.p
53563.54/7909.58	% SZS status Ended for HL403611+5.p
53597.25/7913.98	% SZS status Started for HL403612+5.p
53597.25/7913.98	% SZS status GaveUp for HL403612+5.p
53597.25/7913.98	% SZS status Ended for HL403612+5.p
53599.13/7914.41	% SZS status Started for HL403608+4.p
53599.13/7914.41	% SZS status GaveUp for HL403608+4.p
53599.13/7914.41	eprover: CPU time limit exceeded, terminating
53599.13/7914.41	% SZS status Ended for HL403608+4.p
53645.16/7917.21	% SZS status Started for HL403613+5.p
53645.16/7917.21	% SZS status GaveUp for HL403613+5.p
53645.16/7917.21	% SZS status Ended for HL403613+5.p
53647.64/7917.54	% SZS status Started for HL403610+4.p
53647.64/7917.54	% SZS status GaveUp for HL403610+4.p
53647.64/7917.54	eprover: CPU time limit exceeded, terminating
53647.64/7917.54	% SZS status Ended for HL403610+4.p
53673.71/7920.97	% SZS status Started for HL403614+5.p
53673.71/7920.97	% SZS status Theorem for HL403614+5.p
53673.71/7920.97	% SZS status Ended for HL403614+5.p
53688.98/7922.04	% SZS status Started for HL403611+4.p
53688.98/7922.04	% SZS status GaveUp for HL403611+4.p
53688.98/7922.04	eprover: CPU time limit exceeded, terminating
53688.98/7922.04	% SZS status Ended for HL403611+4.p
53703.75/7923.97	% SZS status Started for HL403615+5.p
53703.75/7923.97	% SZS status Theorem for HL403615+5.p
53703.75/7923.97	% SZS status Ended for HL403615+5.p
53730.79/7927.45	% SZS status Started for HL403612+4.p
53730.79/7927.45	% SZS status GaveUp for HL403612+4.p
53730.79/7927.45	eprover: CPU time limit exceeded, terminating
53730.79/7927.45	% SZS status Ended for HL403612+4.p
53750.60/7929.94	% SZS status Started for HL403616+5.p
53750.60/7929.94	% SZS status GaveUp for HL403616+5.p
53750.60/7929.94	% SZS status Ended for HL403616+5.p
53757.45/7930.88	% SZS status Started for HL403613+4.p
53757.45/7930.88	% SZS status GaveUp for HL403613+4.p
53757.45/7930.88	eprover: CPU time limit exceeded, terminating
53757.45/7930.88	% SZS status Ended for HL403613+4.p
53775.46/7933.18	% SZS status Started for HL403617+5.p
53775.46/7933.18	% SZS status GaveUp for HL403617+5.p
53775.46/7933.18	% SZS status Ended for HL403617+5.p
53797.02/7935.84	% SZS status Started for HL403614+4.p
53797.02/7935.84	% SZS status GaveUp for HL403614+4.p
53797.02/7935.84	eprover: CPU time limit exceeded, terminating
53797.02/7935.84	% SZS status Ended for HL403614+4.p
53803.38/7936.68	% SZS status Started for HL403619+5.p
53803.38/7936.68	% SZS status Theorem for HL403619+5.p
53803.38/7936.68	% SZS status Ended for HL403619+5.p
53830.93/7940.14	% SZS status Started for HL403615+4.p
53830.93/7940.14	% SZS status GaveUp for HL403615+4.p
53830.93/7940.14	eprover: CPU time limit exceeded, terminating
53830.93/7940.14	% SZS status Ended for HL403615+4.p
53847.45/7942.23	% SZS status Started for HL403620+5.p
53847.45/7942.23	% SZS status GaveUp for HL403620+5.p
53847.45/7942.23	% SZS status Ended for HL403620+5.p
53850.57/7942.71	% SZS status Started for HL403616+4.p
53850.57/7942.71	% SZS status GaveUp for HL403616+4.p
53850.57/7942.71	eprover: CPU time limit exceeded, terminating
53850.57/7942.71	% SZS status Ended for HL403616+4.p
53875.05/7945.79	% SZS status Started for HL403621+5.p
53875.05/7945.79	% SZS status GaveUp for HL403621+5.p
53875.05/7945.79	% SZS status Ended for HL403621+5.p
53892.63/7947.99	% SZS status Started for HL403617+4.p
53892.63/7947.99	% SZS status GaveUp for HL403617+4.p
53892.63/7947.99	eprover: CPU time limit exceeded, terminating
53892.63/7947.99	% SZS status Ended for HL403617+4.p
53920.97/7951.54	% SZS status Started for HL403622+5.p
53920.97/7951.54	% SZS status GaveUp for HL403622+5.p
53920.97/7951.54	% SZS status Ended for HL403622+5.p
53934.30/7953.29	% SZS status Started for HL403619+4.p
53934.30/7953.29	% SZS status GaveUp for HL403619+4.p
53934.30/7953.29	eprover: CPU time limit exceeded, terminating
53934.30/7953.29	% SZS status Ended for HL403619+4.p
53946.54/7954.82	% SZS status Started for HL403623+5.p
53946.54/7954.82	% SZS status GaveUp for HL403623+5.p
53946.54/7954.82	% SZS status Ended for HL403623+5.p
53957.68/7956.18	% SZS status Started for HL403620+4.p
53957.68/7956.18	% SZS status GaveUp for HL403620+4.p
53957.68/7956.18	eprover: CPU time limit exceeded, terminating
53957.68/7956.18	% SZS status Ended for HL403620+4.p
53991.79/7960.57	% SZS status Started for HL403624+5.p
53991.79/7960.57	% SZS status GaveUp for HL403624+5.p
53991.79/7960.57	% SZS status Ended for HL403624+5.p
53998.25/7961.28	% SZS status Started for HL403621+4.p
53998.25/7961.28	% SZS status GaveUp for HL403621+4.p
53998.25/7961.28	eprover: CPU time limit exceeded, terminating
53998.25/7961.28	% SZS status Ended for HL403621+4.p
54018.27/7963.82	% SZS status Started for HL403625+5.p
54018.27/7963.82	% SZS status GaveUp for HL403625+5.p
54018.27/7963.82	% SZS status Ended for HL403625+5.p
54029.15/7965.19	% SZS status Started for HL403622+4.p
54029.15/7965.19	% SZS status GaveUp for HL403622+4.p
54029.15/7965.19	eprover: CPU time limit exceeded, terminating
54029.15/7965.19	% SZS status Ended for HL403622+4.p
54054.34/7968.36	% SZS status Started for HL403623+4.p
54054.34/7968.36	% SZS status GaveUp for HL403623+4.p
54054.34/7968.36	eprover: CPU time limit exceeded, terminating
54054.34/7968.36	% SZS status Ended for HL403623+4.p
54064.63/7969.65	% SZS status Started for HL403626+5.p
54064.63/7969.65	% SZS status GaveUp for HL403626+5.p
54064.63/7969.65	% SZS status Ended for HL403626+5.p
54092.75/7973.20	% SZS status Started for HL403628+5.p
54092.75/7973.20	% SZS status GaveUp for HL403628+5.p
54092.75/7973.20	% SZS status Ended for HL403628+5.p
54095.16/7973.55	% SZS status Started for HL403624+4.p
54095.16/7973.55	% SZS status GaveUp for HL403624+4.p
54095.16/7973.55	eprover: CPU time limit exceeded, terminating
54095.16/7973.55	% SZS status Ended for HL403624+4.p
54125.86/7977.34	% SZS status Started for HL403629+5.p
54125.86/7977.34	% SZS status GaveUp for HL403629+5.p
54125.86/7977.34	% SZS status Ended for HL403629+5.p
54135.48/7978.57	% SZS status Started for HL403625+4.p
54135.48/7978.57	% SZS status GaveUp for HL403625+4.p
54135.48/7978.57	eprover: CPU time limit exceeded, terminating
54135.48/7978.57	% SZS status Ended for HL403625+4.p
54156.75/7981.29	% SZS status Started for HL403626+4.p
54156.75/7981.29	% SZS status GaveUp for HL403626+4.p
54156.75/7981.29	eprover: CPU time limit exceeded, terminating
54156.75/7981.29	% SZS status Ended for HL403626+4.p
54163.75/7982.16	% SZS status Started for HL403630+5.p
54163.75/7982.16	% SZS status GaveUp for HL403630+5.p
54163.75/7982.16	% SZS status Ended for HL403630+5.p
54197.32/7986.37	% SZS status Started for HL403631+5.p
54197.32/7986.37	% SZS status GaveUp for HL403631+5.p
54197.32/7986.37	% SZS status Ended for HL403631+5.p
54197.83/7986.46	% SZS status Started for HL403628+4.p
54197.83/7986.46	% SZS status GaveUp for HL403628+4.p
54197.83/7986.46	eprover: CPU time limit exceeded, terminating
54197.83/7986.46	% SZS status Ended for HL403628+4.p
54227.83/7990.24	% SZS status Started for HL403629+4.p
54227.83/7990.24	% SZS status GaveUp for HL403629+4.p
54227.83/7990.24	eprover: CPU time limit exceeded, terminating
54227.83/7990.24	% SZS status Ended for HL403629+4.p
54229.16/7990.37	% SZS status Started for HL403632+5.p
54229.16/7990.37	% SZS status GaveUp for HL403632+5.p
54229.16/7990.37	% SZS status Ended for HL403632+5.p
54266.25/7995.09	% SZS status Started for HL403630+4.p
54266.25/7995.09	% SZS status GaveUp for HL403630+4.p
54266.25/7995.09	eprover: CPU time limit exceeded, terminating
54266.25/7995.09	% SZS status Ended for HL403630+4.p
54269.35/7995.47	% SZS status Started for HL403634+5.p
54269.35/7995.47	% SZS status GaveUp for HL403634+5.p
54269.35/7995.47	% SZS status Ended for HL403634+5.p
54303.42/7998.69	% SZS status Started for HL403631+4.p
54303.42/7998.69	% SZS status GaveUp for HL403631+4.p
54303.42/7998.69	eprover: CPU time limit exceeded, terminating
54303.42/7998.69	% SZS status Ended for HL403631+4.p
54308.15/7999.23	% SZS status Started for HL403635+5.p
54308.15/7999.23	% SZS status GaveUp for HL403635+5.p
54308.15/7999.23	% SZS status Ended for HL403635+5.p
54343.31/8003.66	% SZS status Started for HL403632+4.p
54343.31/8003.66	% SZS status GaveUp for HL403632+4.p
54343.31/8003.66	eprover: CPU time limit exceeded, terminating
54343.31/8003.66	% SZS status Ended for HL403632+4.p
54345.82/8004.00	% SZS status Started for HL403636+5.p
54345.82/8004.00	% SZS status GaveUp for HL403636+5.p
54345.82/8004.00	% SZS status Ended for HL403636+5.p
54371.95/8007.25	% SZS status Started for HL403634+4.p
54371.95/8007.25	% SZS status GaveUp for HL403634+4.p
54371.95/8007.25	eprover: CPU time limit exceeded, terminating
54371.95/8007.25	% SZS status Ended for HL403634+4.p
54375.23/8007.73	% SZS status Started for HL403637+5.p
54375.23/8007.73	% SZS status GaveUp for HL403637+5.p
54375.23/8007.73	% SZS status Ended for HL403637+5.p
54407.01/8011.71	% SZS status Started for HL403635+4.p
54407.01/8011.71	% SZS status GaveUp for HL403635+4.p
54407.01/8011.71	eprover: CPU time limit exceeded, terminating
54407.01/8011.71	% SZS status Ended for HL403635+4.p
54413.90/8012.58	% SZS status Started for HL403638+5.p
54413.90/8012.58	% SZS status GaveUp for HL403638+5.p
54413.90/8012.58	% SZS status Ended for HL403638+5.p
54438.72/8015.76	% SZS status Started for HL403636+4.p
54438.72/8015.76	% SZS status GaveUp for HL403636+4.p
54438.72/8015.76	eprover: CPU time limit exceeded, terminating
54438.72/8015.76	% SZS status Ended for HL403636+4.p
54441.98/8016.15	% SZS status Started for HL403639+5.p
54441.98/8016.15	% SZS status GaveUp for HL403639+5.p
54441.98/8016.15	% SZS status Ended for HL403639+5.p
54478.32/8020.70	% SZS status Started for HL403640+5.p
54478.32/8020.70	% SZS status GaveUp for HL403640+5.p
54478.32/8020.70	% SZS status Ended for HL403640+5.p
54480.14/8020.90	% SZS status Started for HL403637+4.p
54480.14/8020.90	% SZS status GaveUp for HL403637+4.p
54480.14/8020.90	eprover: CPU time limit exceeded, terminating
54480.14/8020.90	% SZS status Ended for HL403637+4.p
54508.69/8024.55	% SZS status Started for HL403638+4.p
54508.69/8024.55	% SZS status GaveUp for HL403638+4.p
54508.69/8024.55	eprover: CPU time limit exceeded, terminating
54508.69/8024.55	% SZS status Ended for HL403638+4.p
54510.71/8024.73	% SZS status Started for HL403641+5.p
54510.71/8024.73	% SZS status GaveUp for HL403641+5.p
54510.71/8024.73	% SZS status Ended for HL403641+5.p
54548.25/8029.45	% SZS status Started for HL403639+4.p
54548.25/8029.45	% SZS status GaveUp for HL403639+4.p
54548.25/8029.45	eprover: CPU time limit exceeded, terminating
54548.25/8029.45	% SZS status Ended for HL403639+4.p
54549.45/8029.72	% SZS status Started for HL403642+5.p
54549.45/8029.72	% SZS status GaveUp for HL403642+5.p
54549.45/8029.72	% SZS status Ended for HL403642+5.p
54576.25/8033.00	% SZS status Started for HL403640+4.p
54576.25/8033.00	% SZS status GaveUp for HL403640+4.p
54576.25/8033.00	eprover: CPU time limit exceeded, terminating
54576.25/8033.00	% SZS status Ended for HL403640+4.p
54580.49/8033.54	% SZS status Started for HL403643+5.p
54580.49/8033.54	% SZS status GaveUp for HL403643+5.p
54580.49/8033.54	% SZS status Ended for HL403643+5.p
54615.19/8037.88	% SZS status Started for HL403641+4.p
54615.19/8037.88	% SZS status GaveUp for HL403641+4.p
54615.19/8037.88	eprover: CPU time limit exceeded, terminating
54615.19/8037.88	% SZS status Ended for HL403641+4.p
54619.46/8038.44	% SZS status Started for HL403646+5.p
54619.46/8038.44	% SZS status GaveUp for HL403646+5.p
54619.46/8038.44	% SZS status Ended for HL403646+5.p
54643.39/8041.52	% SZS status Started for HL403642+4.p
54643.39/8041.52	% SZS status GaveUp for HL403642+4.p
54643.39/8041.52	eprover: CPU time limit exceeded, terminating
54643.39/8041.52	% SZS status Ended for HL403642+4.p
54647.35/8042.08	% SZS status Started for HL403648+5.p
54647.35/8042.08	% SZS status GaveUp for HL403648+5.p
54647.35/8042.08	% SZS status Ended for HL403648+5.p
54679.18/8046.35	% SZS status Started for HL403643+4.p
54679.18/8046.35	% SZS status GaveUp for HL403643+4.p
54679.18/8046.35	eprover: CPU time limit exceeded, terminating
54679.18/8046.35	% SZS status Ended for HL403643+4.p
54687.22/8047.44	% SZS status Started for HL403649+5.p
54687.22/8047.44	% SZS status GaveUp for HL403649+5.p
54687.22/8047.44	% SZS status Ended for HL403649+5.p
54711.02/8050.52	% SZS status Started for HL403646+4.p
54711.02/8050.52	% SZS status GaveUp for HL403646+4.p
54711.02/8050.52	eprover: CPU time limit exceeded, terminating
54711.02/8050.52	% SZS status Ended for HL403646+4.p
54719.50/8051.58	% SZS status Started for HL403651+5.p
54719.50/8051.58	% SZS status GaveUp for HL403651+5.p
54719.50/8051.58	% SZS status Ended for HL403651+5.p
54757.43/8056.69	% SZS status Started for HL403648+4.p
54757.43/8056.69	% SZS status GaveUp for HL403648+4.p
54757.43/8056.69	eprover: CPU time limit exceeded, terminating
54757.43/8056.69	% SZS status Ended for HL403648+4.p
54759.66/8057.00	% SZS status Started for HL403652+5.p
54759.66/8057.00	% SZS status GaveUp for HL403652+5.p
54759.66/8057.00	% SZS status Ended for HL403652+5.p
54782.73/8059.97	% SZS status Started for HL403649+4.p
54782.73/8059.97	% SZS status GaveUp for HL403649+4.p
54782.73/8059.97	eprover: CPU time limit exceeded, terminating
54782.73/8059.97	% SZS status Ended for HL403649+4.p
54786.11/8060.53	% SZS status Started for HL403653+5.p
54786.11/8060.53	% SZS status GaveUp for HL403653+5.p
54786.11/8060.53	% SZS status Ended for HL403653+5.p
54817.66/8064.97	% SZS status Started for HL403651+4.p
54817.66/8064.97	% SZS status GaveUp for HL403651+4.p
54817.66/8064.97	eprover: CPU time limit exceeded, terminating
54817.66/8064.97	% SZS status Ended for HL403651+4.p
54827.61/8066.38	% SZS status Started for HL403655+5.p
54827.61/8066.38	% SZS status GaveUp for HL403655+5.p
54827.61/8066.38	% SZS status Ended for HL403655+5.p
54849.09/8069.40	% SZS status Started for HL403652+4.p
54849.09/8069.40	% SZS status GaveUp for HL403652+4.p
54849.09/8069.40	eprover: CPU time limit exceeded, terminating
54849.09/8069.40	% SZS status Ended for HL403652+4.p
54856.41/8070.25	% SZS status Started for HL403656+5.p
54856.41/8070.25	% SZS status GaveUp for HL403656+5.p
54856.41/8070.25	% SZS status Ended for HL403656+5.p
54883.31/8073.90	% SZS status Started for HL403653+4.p
54883.31/8073.90	% SZS status GaveUp for HL403653+4.p
54883.31/8073.90	eprover: CPU time limit exceeded, terminating
54883.31/8073.90	% SZS status Ended for HL403653+4.p
54899.41/8076.40	% SZS status Started for HL403657+5.p
54899.41/8076.40	% SZS status GaveUp for HL403657+5.p
54899.41/8076.40	% SZS status Ended for HL403657+5.p
54925.03/8080.00	% SZS status Started for HL403655+4.p
54925.03/8080.00	% SZS status GaveUp for HL403655+4.p
54925.03/8080.00	eprover: CPU time limit exceeded, terminating
54925.03/8080.00	% SZS status Ended for HL403655+4.p
54929.52/8080.64	% SZS status Started for HL403658+5.p
54929.52/8080.64	% SZS status GaveUp for HL403658+5.p
54929.52/8080.64	% SZS status Ended for HL403658+5.p
54954.13/8083.87	% SZS status Started for HL403660+5.p
54954.13/8083.87	% SZS status GaveUp for HL403660+5.p
54954.13/8083.87	% SZS status Ended for HL403660+5.p
54959.80/8084.61	% SZS status Started for HL403656+4.p
54959.80/8084.61	% SZS status GaveUp for HL403656+4.p
54959.80/8084.61	eprover: CPU time limit exceeded, terminating
54959.80/8084.61	% SZS status Ended for HL403656+4.p
54984.54/8087.85	% SZS status Started for HL403657+4.p
54984.54/8087.85	% SZS status GaveUp for HL403657+4.p
54984.54/8087.85	eprover: CPU time limit exceeded, terminating
54984.54/8087.85	% SZS status Ended for HL403657+4.p
55000.03/8089.72	% SZS status Started for HL403662+5.p
55000.03/8089.72	% SZS status GaveUp for HL403662+5.p
55000.03/8089.72	% SZS status Ended for HL403662+5.p
55028.31/8093.32	% SZS status Started for HL403663+5.p
55028.31/8093.32	% SZS status GaveUp for HL403663+5.p
55028.31/8093.32	% SZS status Ended for HL403663+5.p
55036.89/8094.45	% SZS status Started for HL403658+4.p
55036.89/8094.45	% SZS status GaveUp for HL403658+4.p
55036.89/8094.45	eprover: CPU time limit exceeded, terminating
55036.89/8094.45	% SZS status Ended for HL403658+4.p
55058.95/8097.19	% SZS status Started for HL403664+5.p
55058.95/8097.19	% SZS status GaveUp for HL403664+5.p
55058.95/8097.19	% SZS status Ended for HL403664+5.p
55058.95/8097.23	% SZS status Started for HL403660+4.p
55058.95/8097.23	% SZS status GaveUp for HL403660+4.p
55058.95/8097.23	eprover: CPU time limit exceeded, terminating
55058.95/8097.23	% SZS status Ended for HL403660+4.p
55101.22/8102.47	% SZS status Started for HL403665+5.p
55101.22/8102.47	% SZS status GaveUp for HL403665+5.p
55101.22/8102.47	% SZS status Ended for HL403665+5.p
55106.64/8103.15	% SZS status Started for HL403662+4.p
55106.64/8103.15	% SZS status GaveUp for HL403662+4.p
55106.64/8103.15	eprover: CPU time limit exceeded, terminating
55106.64/8103.15	% SZS status Ended for HL403662+4.p
55130.79/8106.18	% SZS status Started for HL403666+5.p
55130.79/8106.18	% SZS status GaveUp for HL403666+5.p
55130.79/8106.18	% SZS status Ended for HL403666+5.p
55143.27/8106.66	% SZS status Started for HL403663+4.p
55143.27/8106.66	% SZS status GaveUp for HL403663+4.p
55143.27/8106.66	eprover: CPU time limit exceeded, terminating
55143.27/8106.66	% SZS status Ended for HL403663+4.p
55169.47/8109.96	% SZS status Started for HL403664+4.p
55169.47/8109.96	% SZS status GaveUp for HL403664+4.p
55169.47/8109.96	eprover: CPU time limit exceeded, terminating
55169.47/8109.96	% SZS status Ended for HL403664+4.p
55181.77/8111.49	% SZS status Started for HL403667+5.p
55181.77/8111.49	% SZS status GaveUp for HL403667+5.p
55181.77/8111.49	% SZS status Ended for HL403667+5.p
55209.44/8114.99	% SZS status Started for HL403668+5.p
55209.44/8114.99	% SZS status GaveUp for HL403668+5.p
55209.44/8114.99	% SZS status Ended for HL403668+5.p
55209.44/8115.02	% SZS status Started for HL403665+4.p
55209.44/8115.02	% SZS status GaveUp for HL403665+4.p
55209.44/8115.02	eprover: CPU time limit exceeded, terminating
55209.44/8115.02	% SZS status Ended for HL403665+4.p
55241.13/8118.95	% SZS status Started for HL403669+5.p
55241.13/8118.95	% SZS status GaveUp for HL403669+5.p
55241.13/8118.95	% SZS status Ended for HL403669+5.p
55250.63/8120.14	% SZS status Started for HL403666+4.p
55250.63/8120.14	% SZS status GaveUp for HL403666+4.p
55250.63/8120.14	eprover: CPU time limit exceeded, terminating
55250.63/8120.14	% SZS status Ended for HL403666+4.p
55268.89/8122.42	% SZS status Started for HL403667+4.p
55268.89/8122.42	% SZS status GaveUp for HL403667+4.p
55268.89/8122.42	eprover: CPU time limit exceeded, terminating
55268.89/8122.42	% SZS status Ended for HL403667+4.p
55280.97/8123.98	% SZS status Started for HL403670+5.p
55280.97/8123.98	% SZS status GaveUp for HL403670+5.p
55280.97/8123.98	% SZS status Ended for HL403670+5.p
55311.99/8127.88	% SZS status Started for HL403671+5.p
55311.99/8127.88	% SZS status GaveUp for HL403671+5.p
55311.99/8127.88	% SZS status Ended for HL403671+5.p
55317.13/8128.53	% SZS status Started for HL403668+4.p
55317.13/8128.53	% SZS status GaveUp for HL403668+4.p
55317.13/8128.53	eprover: CPU time limit exceeded, terminating
55317.13/8128.53	% SZS status Ended for HL403668+4.p
55340.47/8131.54	% SZS status Started for HL403672+5.p
55340.47/8131.54	% SZS status GaveUp for HL403672+5.p
55340.47/8131.54	% SZS status Ended for HL403672+5.p
55343.10/8131.83	% SZS status Started for HL403669+4.p
55343.10/8131.83	% SZS status GaveUp for HL403669+4.p
55343.10/8131.83	eprover: CPU time limit exceeded, terminating
55343.10/8131.83	% SZS status Ended for HL403669+4.p
55382.66/8136.81	% SZS status Started for HL403670+4.p
55382.66/8136.81	% SZS status GaveUp for HL403670+4.p
55382.66/8136.81	eprover: CPU time limit exceeded, terminating
55382.66/8136.81	% SZS status Ended for HL403670+4.p
55383.25/8136.93	% SZS status Started for HL403673+5.p
55383.25/8136.93	% SZS status GaveUp for HL403673+5.p
55383.25/8136.93	% SZS status Ended for HL403673+5.p
55410.39/8140.24	% SZS status Started for HL403671+4.p
55410.39/8140.24	% SZS status GaveUp for HL403671+4.p
55410.39/8140.24	eprover: CPU time limit exceeded, terminating
55410.39/8140.24	% SZS status Ended for HL403671+4.p
55412.89/8140.58	% SZS status Started for HL403674+5.p
55412.89/8140.58	% SZS status GaveUp for HL403674+5.p
55412.89/8140.58	% SZS status Ended for HL403674+5.p
55450.26/8145.30	% SZS status Started for HL403672+4.p
55450.26/8145.30	% SZS status GaveUp for HL403672+4.p
55450.26/8145.30	eprover: CPU time limit exceeded, terminating
55450.26/8145.30	% SZS status Ended for HL403672+4.p
55454.71/8145.82	% SZS status Started for HL403677+5.p
55454.71/8145.82	% SZS status GaveUp for HL403677+5.p
55454.71/8145.82	% SZS status Ended for HL403677+5.p
55481.53/8149.24	% SZS status Started for HL403678+5.p
55481.53/8149.24	% SZS status GaveUp for HL403678+5.p
55481.53/8149.24	% SZS status Ended for HL403678+5.p
55482.09/8149.26	% SZS status Started for HL403673+4.p
55482.09/8149.26	% SZS status GaveUp for HL403673+4.p
55482.09/8149.26	eprover: CPU time limit exceeded, terminating
55482.09/8149.26	% SZS status Ended for HL403673+4.p
55518.48/8153.90	% SZS status Started for HL403674+4.p
55518.48/8153.90	% SZS status GaveUp for HL403674+4.p
55518.48/8153.90	eprover: CPU time limit exceeded, terminating
55518.48/8153.90	% SZS status Ended for HL403674+4.p
55522.11/8154.33	% SZS status Started for HL403679+5.p
55522.11/8154.33	% SZS status GaveUp for HL403679+5.p
55522.11/8154.33	% SZS status Ended for HL403679+5.p
55545.14/8157.34	% SZS status Started for HL403677+4.p
55545.14/8157.34	% SZS status GaveUp for HL403677+4.p
55545.14/8157.34	eprover: CPU time limit exceeded, terminating
55545.14/8157.34	% SZS status Ended for HL403677+4.p
55577.68/8158.28	% SZS status Started for HL403680+5.p
55577.68/8158.28	% SZS status GaveUp for HL403680+5.p
55577.68/8158.28	% SZS status Ended for HL403680+5.p
55609.09/8162.30	% SZS status Started for HL403678+4.p
55609.09/8162.30	% SZS status GaveUp for HL403678+4.p
55609.09/8162.30	eprover: CPU time limit exceeded, terminating
55609.09/8162.30	% SZS status Ended for HL403678+4.p
55614.64/8163.00	% SZS status Started for HL403681+5.p
55614.64/8163.00	% SZS status GaveUp for HL403681+5.p
55614.64/8163.00	% SZS status Ended for HL403681+5.p
55638.16/8165.98	% SZS status Started for HL403679+4.p
55638.16/8165.98	% SZS status GaveUp for HL403679+4.p
55638.16/8165.98	eprover: CPU time limit exceeded, terminating
55638.16/8165.98	% SZS status Ended for HL403679+4.p
55640.70/8166.30	% SZS status Started for HL403682+5.p
55640.70/8166.30	% SZS status GaveUp for HL403682+5.p
55640.70/8166.30	% SZS status Ended for HL403682+5.p
55679.65/8171.19	% SZS status Started for HL403680+4.p
55679.65/8171.19	% SZS status GaveUp for HL403680+4.p
55679.65/8171.19	eprover: CPU time limit exceeded, terminating
55679.65/8171.19	% SZS status Ended for HL403680+4.p
55681.75/8171.40	% SZS status Started for HL403684+5.p
55681.75/8171.40	% SZS status GaveUp for HL403684+5.p
55681.75/8171.40	% SZS status Ended for HL403684+5.p
55707.54/8174.71	% SZS status Started for HL403681+4.p
55707.54/8174.71	% SZS status GaveUp for HL403681+4.p
55707.54/8174.71	eprover: CPU time limit exceeded, terminating
55707.54/8174.71	% SZS status Ended for HL403681+4.p
55710.66/8175.12	% SZS status Started for HL403685+5.p
55710.66/8175.12	% SZS status GaveUp for HL403685+5.p
55710.66/8175.12	% SZS status Ended for HL403685+5.p
55747.32/8179.66	% SZS status Started for HL403682+4.p
55747.32/8179.66	% SZS status GaveUp for HL403682+4.p
55747.32/8179.66	eprover: CPU time limit exceeded, terminating
55747.32/8179.66	% SZS status Ended for HL403682+4.p
55750.41/8180.24	% SZS status Started for HL403686+5.p
55750.41/8180.24	% SZS status GaveUp for HL403686+5.p
55750.41/8180.24	% SZS status Ended for HL403686+5.p
55777.93/8183.52	% SZS status Started for HL403684+4.p
55777.93/8183.52	% SZS status GaveUp for HL403684+4.p
55777.93/8183.52	eprover: CPU time limit exceeded, terminating
55777.93/8183.52	% SZS status Ended for HL403684+4.p
55779.94/8183.80	% SZS status Started for HL403687+5.p
55779.94/8183.80	% SZS status GaveUp for HL403687+5.p
55779.94/8183.80	% SZS status Ended for HL403687+5.p
55814.36/8188.20	% SZS status Started for HL403685+4.p
55814.36/8188.20	% SZS status GaveUp for HL403685+4.p
55814.36/8188.20	eprover: CPU time limit exceeded, terminating
55814.36/8188.20	% SZS status Ended for HL403685+4.p
55818.66/8188.70	% SZS status Started for HL403688+5.p
55818.66/8188.70	% SZS status GaveUp for HL403688+5.p
55818.66/8188.70	% SZS status Ended for HL403688+5.p
55842.03/8191.61	% SZS status Started for HL403686+4.p
55842.03/8191.61	% SZS status GaveUp for HL403686+4.p
55842.03/8191.61	eprover: CPU time limit exceeded, terminating
55842.03/8191.61	% SZS status Ended for HL403686+4.p
55849.01/8192.51	% SZS status Started for HL403689+5.p
55849.01/8192.51	% SZS status GaveUp for HL403689+5.p
55849.01/8192.51	% SZS status Ended for HL403689+5.p
55882.78/8196.75	% SZS status Started for HL403687+4.p
55882.78/8196.75	% SZS status GaveUp for HL403687+4.p
55882.78/8196.75	eprover: CPU time limit exceeded, terminating
55882.78/8196.75	% SZS status Ended for HL403687+4.p
55886.20/8197.16	% SZS status Started for HL403690+5.p
55886.20/8197.16	% SZS status GaveUp for HL403690+5.p
55886.20/8197.16	% SZS status Ended for HL403690+5.p
55914.46/8200.76	% SZS status Started for HL403691+5.p
55914.46/8200.76	% SZS status GaveUp for HL403691+5.p
55914.46/8200.76	% SZS status Ended for HL403691+5.p
55914.46/8200.77	% SZS status Started for HL403688+4.p
55914.46/8200.77	% SZS status GaveUp for HL403688+4.p
55914.46/8200.77	eprover: CPU time limit exceeded, terminating
55914.46/8200.77	% SZS status Ended for HL403688+4.p
55953.07/8205.58	% SZS status Started for HL403689+4.p
55953.07/8205.58	% SZS status GaveUp for HL403689+4.p
55953.07/8205.58	eprover: CPU time limit exceeded, terminating
55953.07/8205.58	% SZS status Ended for HL403689+4.p
55954.43/8205.76	% SZS status Started for HL403692+5.p
55954.43/8205.76	% SZS status GaveUp for HL403692+5.p
55954.43/8205.76	% SZS status Ended for HL403692+5.p
55979.80/8209.01	% SZS status Started for HL403690+4.p
55979.80/8209.01	% SZS status GaveUp for HL403690+4.p
55979.80/8209.01	eprover: CPU time limit exceeded, terminating
55979.80/8209.01	% SZS status Ended for HL403690+4.p
55985.56/8209.71	% SZS status Started for HL403694+5.p
55985.56/8209.71	% SZS status GaveUp for HL403694+5.p
55985.56/8209.71	% SZS status Ended for HL403694+5.p
56020.73/8214.13	% SZS status Started for HL403691+4.p
56020.73/8214.13	% SZS status GaveUp for HL403691+4.p
56020.73/8214.13	eprover: CPU time limit exceeded, terminating
56020.73/8214.13	% SZS status Ended for HL403691+4.p
56024.48/8214.61	% SZS status Started for HL403695+5.p
56024.48/8214.61	% SZS status GaveUp for HL403695+5.p
56024.48/8214.61	% SZS status Ended for HL403695+5.p
56051.52/8218.02	% SZS status Started for HL403692+4.p
56051.52/8218.02	% SZS status GaveUp for HL403692+4.p
56051.52/8218.02	eprover: CPU time limit exceeded, terminating
56051.52/8218.02	% SZS status Ended for HL403692+4.p
56051.95/8218.05	% SZS status Started for HL403696+5.p
56051.95/8218.05	% SZS status GaveUp for HL403696+5.p
56051.95/8218.05	% SZS status Ended for HL403696+5.p
56086.71/8222.46	% SZS status Started for HL403694+4.p
56086.71/8222.46	% SZS status GaveUp for HL403694+4.p
56086.71/8222.46	eprover: CPU time limit exceeded, terminating
56086.71/8222.46	% SZS status Ended for HL403694+4.p
56092.68/8223.29	% SZS status Started for HL403697+5.p
56092.68/8223.29	% SZS status GaveUp for HL403697+5.p
56092.68/8223.29	% SZS status Ended for HL403697+5.p
56105.00/8224.73	% SZS status Started for HL403698+5.p
56105.00/8224.73	% SZS status Theorem for HL403698+5.p
56105.00/8224.73	% SZS status Ended for HL403698+5.p
56114.87/8226.00	% SZS status Started for HL403695+4.p
56114.87/8226.00	% SZS status GaveUp for HL403695+4.p
56114.87/8226.00	eprover: CPU time limit exceeded, terminating
56114.87/8226.00	% SZS status Ended for HL403695+4.p
56155.42/8231.08	% SZS status Started for HL403696+4.p
56155.42/8231.08	% SZS status GaveUp for HL403696+4.p
56155.42/8231.08	eprover: CPU time limit exceeded, terminating
56155.42/8231.08	% SZS status Ended for HL403696+4.p
56158.97/8231.52	% SZS status Started for HL403699+5.p
56158.97/8231.52	% SZS status GaveUp for HL403699+5.p
56158.97/8231.52	% SZS status Ended for HL403699+5.p
56177.02/8233.81	% SZS status Started for HL403702+5.p
56177.02/8233.81	% SZS status GaveUp for HL403702+5.p
56177.02/8233.81	% SZS status Ended for HL403702+5.p
56187.73/8235.19	% SZS status Started for HL403697+4.p
56187.73/8235.19	% SZS status GaveUp for HL403697+4.p
56187.73/8235.19	eprover: CPU time limit exceeded, terminating
56187.73/8235.19	% SZS status Ended for HL403697+4.p
56227.61/8240.21	% SZS status Started for HL403703+5.p
56227.61/8240.21	% SZS status GaveUp for HL403703+5.p
56227.61/8240.21	% SZS status Ended for HL403703+5.p
56228.46/8240.32	% SZS status Started for HL403698+4.p
56228.46/8240.32	% SZS status GaveUp for HL403698+4.p
56228.46/8240.32	eprover: CPU time limit exceeded, terminating
56228.46/8240.32	% SZS status Ended for HL403698+4.p
56247.63/8242.76	% SZS status Started for HL403704+5.p
56247.63/8242.76	% SZS status GaveUp for HL403704+5.p
56247.63/8242.76	% SZS status Ended for HL403704+5.p
56253.23/8243.39	% SZS status Started for HL403699+4.p
56253.23/8243.39	% SZS status GaveUp for HL403699+4.p
56253.23/8243.39	eprover: CPU time limit exceeded, terminating
56253.23/8243.39	% SZS status Ended for HL403699+4.p
56279.53/8246.69	% SZS status Started for HL403705+5.p
56279.53/8246.69	% SZS status Theorem for HL403705+5.p
56279.53/8246.69	% SZS status Ended for HL403705+5.p
56293.73/8248.55	% SZS status Started for HL403702+4.p
56293.73/8248.55	% SZS status GaveUp for HL403702+4.p
56293.73/8248.55	eprover: CPU time limit exceeded, terminating
56293.73/8248.55	% SZS status Ended for HL403702+4.p
56315.59/8251.29	% SZS status Started for HL403703+4.p
56315.59/8251.29	% SZS status GaveUp for HL403703+4.p
56315.59/8251.29	eprover: CPU time limit exceeded, terminating
56315.59/8251.29	% SZS status Ended for HL403703+4.p
56320.09/8251.83	% SZS status Started for HL403706+5.p
56320.09/8251.83	% SZS status GaveUp for HL403706+5.p
56320.09/8251.83	% SZS status Ended for HL403706+5.p
56350.93/8255.73	% SZS status Started for HL403707+5.p
56350.93/8255.73	% SZS status GaveUp for HL403707+5.p
56350.93/8255.73	% SZS status Ended for HL403707+5.p
56359.09/8256.76	% SZS status Started for HL403704+4.p
56359.09/8256.76	% SZS status GaveUp for HL403704+4.p
56359.09/8256.76	eprover: CPU time limit exceeded, terminating
56359.09/8256.76	% SZS status Ended for HL403704+4.p
56387.27/8260.28	% SZS status Started for HL403708+5.p
56387.27/8260.28	% SZS status GaveUp for HL403708+5.p
56387.27/8260.28	% SZS status Ended for HL403708+5.p
56388.48/8260.38	% SZS status Started for HL403705+4.p
56388.48/8260.38	% SZS status GaveUp for HL403705+4.p
56388.48/8260.38	eprover: CPU time limit exceeded, terminating
56388.48/8260.38	% SZS status Ended for HL403705+4.p
56422.28/8264.69	% SZS status Started for HL403709+5.p
56422.28/8264.69	% SZS status GaveUp for HL403709+5.p
56422.28/8264.69	% SZS status Ended for HL403709+5.p
56429.94/8265.66	% SZS status Started for HL403706+4.p
56429.94/8265.66	% SZS status GaveUp for HL403706+4.p
56429.94/8265.66	eprover: CPU time limit exceeded, terminating
56429.94/8265.66	% SZS status Ended for HL403706+4.p
56454.48/8268.74	% SZS status Started for HL403707+4.p
56454.48/8268.74	% SZS status GaveUp for HL403707+4.p
56454.48/8268.74	eprover: CPU time limit exceeded, terminating
56454.48/8268.74	% SZS status Ended for HL403707+4.p
56459.02/8269.28	% SZS status Started for HL403711+5.p
56459.02/8269.28	% SZS status GaveUp for HL403711+5.p
56459.02/8269.28	% SZS status Ended for HL403711+5.p
56495.22/8273.83	% SZS status Started for HL403713+5.p
56495.22/8273.83	% SZS status GaveUp for HL403713+5.p
56495.22/8273.83	% SZS status Ended for HL403713+5.p
56496.30/8274.00	% SZS status Started for HL403708+4.p
56496.30/8274.00	% SZS status GaveUp for HL403708+4.p
56496.30/8274.00	eprover: CPU time limit exceeded, terminating
56496.30/8274.00	% SZS status Ended for HL403708+4.p
56521.68/8277.16	% SZS status Started for HL403709+4.p
56521.68/8277.16	% SZS status GaveUp for HL403709+4.p
56521.68/8277.16	eprover: CPU time limit exceeded, terminating
56521.68/8277.16	% SZS status Ended for HL403709+4.p
56530.32/8278.26	% SZS status Started for HL403715+5.p
56530.32/8278.26	% SZS status GaveUp for HL403715+5.p
56530.32/8278.26	% SZS status Ended for HL403715+5.p
56563.21/8282.42	% SZS status Started for HL403711+4.p
56563.21/8282.42	% SZS status GaveUp for HL403711+4.p
56563.21/8282.42	eprover: CPU time limit exceeded, terminating
56563.21/8282.42	% SZS status Ended for HL403711+4.p
56566.54/8282.85	% SZS status Started for HL403716+5.p
56566.54/8282.85	% SZS status GaveUp for HL403716+5.p
56566.54/8282.85	% SZS status Ended for HL403716+5.p
56590.86/8285.92	% SZS status Started for HL403713+4.p
56590.86/8285.92	% SZS status GaveUp for HL403713+4.p
56590.86/8285.92	eprover: CPU time limit exceeded, terminating
56590.86/8285.92	% SZS status Ended for HL403713+4.p
56593.04/8286.24	% SZS status Started for HL403717+5.p
56593.04/8286.24	% SZS status GaveUp for HL403717+5.p
56593.04/8286.24	% SZS status Ended for HL403717+5.p
56635.27/8291.53	% SZS status Started for HL403715+4.p
56635.27/8291.53	% SZS status GaveUp for HL403715+4.p
56635.27/8291.53	eprover: CPU time limit exceeded, terminating
56635.27/8291.53	% SZS status Ended for HL403715+4.p
56636.96/8291.77	% SZS status Started for HL403718+5.p
56636.96/8291.77	% SZS status GaveUp for HL403718+5.p
56636.96/8291.77	% SZS status Ended for HL403718+5.p
56665.16/8295.24	% SZS status Started for HL403716+4.p
56665.16/8295.24	% SZS status GaveUp for HL403716+4.p
56665.16/8295.24	eprover: CPU time limit exceeded, terminating
56665.16/8295.24	% SZS status Ended for HL403716+4.p
56669.69/8295.83	% SZS status Started for HL403719+5.p
56669.69/8295.83	% SZS status GaveUp for HL403719+5.p
56669.69/8295.83	% SZS status Ended for HL403719+5.p
56696.33/8299.17	% SZS status Started for HL403717+4.p
56696.33/8299.17	% SZS status GaveUp for HL403717+4.p
56696.33/8299.17	eprover: CPU time limit exceeded, terminating
56696.33/8299.17	% SZS status Ended for HL403717+4.p
56709.57/8300.90	% SZS status Started for HL403720+5.p
56709.57/8300.90	% SZS status GaveUp for HL403720+5.p
56709.57/8300.90	% SZS status Ended for HL403720+5.p
56720.19/8302.17	% SZS status Started for HL403723+5.p
56720.19/8302.17	% SZS status Theorem for HL403723+5.p
56720.19/8302.17	% SZS status Ended for HL403723+5.p
56730.92/8303.56	% SZS status Started for HL403718+4.p
56730.92/8303.56	% SZS status GaveUp for HL403718+4.p
56730.92/8303.56	eprover: CPU time limit exceeded, terminating
56730.92/8303.56	% SZS status Ended for HL403718+4.p
56771.54/8308.62	% SZS status Started for HL403724+5.p
56771.54/8308.62	% SZS status GaveUp for HL403724+5.p
56771.54/8308.62	% SZS status Ended for HL403724+5.p
56771.54/8308.62	% SZS status Started for HL403719+4.p
56771.54/8308.62	% SZS status GaveUp for HL403719+4.p
56771.54/8308.62	eprover: CPU time limit exceeded, terminating
56771.54/8308.62	% SZS status Ended for HL403719+4.p
56794.49/8311.53	% SZS status Started for HL403725+5.p
56794.49/8311.53	% SZS status GaveUp for HL403725+5.p
56794.49/8311.53	% SZS status Ended for HL403725+5.p
56799.48/8312.25	% SZS status Started for HL403720+4.p
56799.48/8312.25	% SZS status GaveUp for HL403720+4.p
56799.48/8312.25	eprover: CPU time limit exceeded, terminating
56799.48/8312.25	% SZS status Ended for HL403720+4.p
56841.42/8317.53	% SZS status Started for HL403723+4.p
56841.42/8317.53	% SZS status GaveUp for HL403723+4.p
56841.42/8317.53	eprover: CPU time limit exceeded, terminating
56841.42/8317.53	% SZS status Ended for HL403723+4.p
56844.66/8317.97	% SZS status Started for HL403726+5.p
56844.66/8317.97	% SZS status GaveUp for HL403726+5.p
56844.66/8317.97	% SZS status Ended for HL403726+5.p
56871.55/8321.41	% SZS status Started for HL403728+5.p
56871.55/8321.41	% SZS status GaveUp for HL403728+5.p
56871.55/8321.41	% SZS status Ended for HL403728+5.p
56882.74/8321.73	% SZS status Started for HL403724+4.p
56882.74/8321.73	% SZS status GaveUp for HL403724+4.p
56882.74/8321.73	eprover: CPU time limit exceeded, terminating
56882.74/8321.73	% SZS status Ended for HL403724+4.p
56923.43/8326.82	% SZS status Started for HL403730+5.p
56923.43/8326.82	% SZS status GaveUp for HL403730+5.p
56923.43/8326.82	% SZS status Ended for HL403730+5.p
56926.30/8327.16	% SZS status Started for HL403725+4.p
56926.30/8327.16	% SZS status GaveUp for HL403725+4.p
56926.30/8327.16	eprover: CPU time limit exceeded, terminating
56926.30/8327.16	% SZS status Ended for HL403725+4.p
56941.97/8329.31	% SZS status Started for HL403726+4.p
56941.97/8329.31	% SZS status GaveUp for HL403726+4.p
56941.97/8329.31	eprover: CPU time limit exceeded, terminating
56941.97/8329.31	% SZS status Ended for HL403726+4.p
56957.47/8331.11	% SZS status Started for HL403731+5.p
56957.47/8331.11	% SZS status GaveUp for HL403731+5.p
56957.47/8331.11	% SZS status Ended for HL403731+5.p
56985.05/8334.62	% SZS status Started for HL403728+4.p
56985.05/8334.62	% SZS status GaveUp for HL403728+4.p
56985.05/8334.62	eprover: CPU time limit exceeded, terminating
56985.05/8334.62	% SZS status Ended for HL403728+4.p
56997.51/8336.16	% SZS status Started for HL403732+5.p
56997.51/8336.16	% SZS status GaveUp for HL403732+5.p
56997.51/8336.16	% SZS status Ended for HL403732+5.p
57012.33/8338.04	% SZS status Started for HL403730+4.p
57012.33/8338.04	% SZS status GaveUp for HL403730+4.p
57012.33/8338.04	eprover: CPU time limit exceeded, terminating
57012.33/8338.04	% SZS status Ended for HL403730+4.p
57018.71/8338.88	% SZS status Started for HL403734+5.p
57018.71/8338.88	% SZS status GaveUp for HL403734+5.p
57018.71/8338.88	% SZS status Ended for HL403734+5.p
57058.87/8343.90	% SZS status Started for HL403735+5.p
57058.87/8343.90	% SZS status GaveUp for HL403735+5.p
57058.87/8343.90	% SZS status Ended for HL403735+5.p
57062.37/8344.40	% SZS status Started for HL403731+4.p
57062.37/8344.40	% SZS status GaveUp for HL403731+4.p
57062.37/8344.40	eprover: CPU time limit exceeded, terminating
57062.37/8344.40	% SZS status Ended for HL403731+4.p
57086.32/8347.39	% SZS status Started for HL403737+5.p
57086.32/8347.39	% SZS status GaveUp for HL403737+5.p
57086.32/8347.39	% SZS status Ended for HL403737+5.p
57087.00/8347.43	% SZS status Started for HL403732+4.p
57087.00/8347.43	% SZS status GaveUp for HL403732+4.p
57087.00/8347.43	eprover: CPU time limit exceeded, terminating
57087.00/8347.43	% SZS status Ended for HL403732+4.p
57130.67/8352.93	% SZS status Started for HL403734+4.p
57130.67/8352.93	% SZS status GaveUp for HL403734+4.p
57130.67/8352.93	eprover: CPU time limit exceeded, terminating
57130.67/8352.93	% SZS status Ended for HL403734+4.p
57133.04/8353.27	% SZS status Started for HL403738+5.p
57133.04/8353.27	% SZS status GaveUp for HL403738+5.p
57133.04/8353.27	% SZS status Ended for HL403738+5.p
57157.11/8356.35	% SZS status Started for HL403741+5.p
57157.11/8356.35	% SZS status GaveUp for HL403741+5.p
57157.11/8356.35	% SZS status Ended for HL403741+5.p
57170.98/8357.00	% SZS status Started for HL403735+4.p
57170.98/8357.00	% SZS status GaveUp for HL403735+4.p
57170.98/8357.00	eprover: CPU time limit exceeded, terminating
57170.98/8357.00	% SZS status Ended for HL403735+4.p
57180.16/8358.17	% SZS status Started for HL403742+5.p
57180.16/8358.17	% SZS status Theorem for HL403742+5.p
57180.16/8358.17	% SZS status Ended for HL403742+5.p
57212.24/8362.17	% SZS status Started for HL403737+4.p
57212.24/8362.17	% SZS status GaveUp for HL403737+4.p
57212.24/8362.17	eprover: CPU time limit exceeded, terminating
57212.24/8362.17	% SZS status Ended for HL403737+4.p
57232.00/8364.72	% SZS status Started for HL403738+4.p
57232.00/8364.72	% SZS status GaveUp for HL403738+4.p
57232.00/8364.72	eprover: CPU time limit exceeded, terminating
57232.00/8364.72	% SZS status Ended for HL403738+4.p
57241.48/8365.94	% SZS status Started for HL403743+5.p
57241.48/8365.94	% SZS status GaveUp for HL403743+5.p
57241.48/8365.94	% SZS status Ended for HL403743+5.p
57252.06/8367.19	% SZS status Started for HL403744+5.p
57252.06/8367.19	% SZS status GaveUp for HL403744+5.p
57252.06/8367.19	% SZS status Ended for HL403744+5.p
57275.06/8370.26	% SZS status Started for HL403741+4.p
57275.06/8370.26	% SZS status GaveUp for HL403741+4.p
57275.06/8370.26	eprover: CPU time limit exceeded, terminating
57275.06/8370.26	% SZS status Ended for HL403741+4.p
57285.84/8371.24	% SZS status Started for HL403745+5.p
57285.84/8371.24	% SZS status Theorem for HL403745+5.p
57285.84/8371.24	% SZS status Ended for HL403745+5.p
57298.59/8372.86	% SZS status Started for HL403742+4.p
57298.59/8372.86	% SZS status GaveUp for HL403742+4.p
57298.59/8372.86	eprover: CPU time limit exceeded, terminating
57298.59/8372.86	% SZS status Ended for HL403742+4.p
57325.59/8376.27	% SZS status Started for HL403746+5.p
57325.59/8376.27	% SZS status GaveUp for HL403746+5.p
57325.59/8376.27	% SZS status Ended for HL403746+5.p
57342.98/8378.49	% SZS status Started for HL403743+4.p
57342.98/8378.49	% SZS status GaveUp for HL403743+4.p
57342.98/8378.49	eprover: CPU time limit exceeded, terminating
57342.98/8378.49	% SZS status Ended for HL403743+4.p
57356.68/8380.21	% SZS status Started for HL403748+5.p
57356.68/8380.21	% SZS status GaveUp for HL403748+5.p
57356.68/8380.21	% SZS status Ended for HL403748+5.p
57374.83/8382.47	% SZS status Started for HL403744+4.p
57374.83/8382.47	% SZS status GaveUp for HL403744+4.p
57374.83/8382.47	eprover: CPU time limit exceeded, terminating
57374.83/8382.47	% SZS status Ended for HL403744+4.p
57396.62/8385.22	% SZS status Started for HL403749+5.p
57396.62/8385.22	% SZS status GaveUp for HL403749+5.p
57396.62/8385.22	% SZS status Ended for HL403749+5.p
57416.04/8387.65	% SZS status Started for HL403745+4.p
57416.04/8387.65	% SZS status GaveUp for HL403745+4.p
57416.04/8387.65	eprover: CPU time limit exceeded, terminating
57416.04/8387.65	% SZS status Ended for HL403745+4.p
57426.64/8388.96	% SZS status Started for HL403750+5.p
57426.64/8388.96	% SZS status GaveUp for HL403750+5.p
57426.64/8388.96	% SZS status Ended for HL403750+5.p
57439.37/8390.57	% SZS status Started for HL403752+5.p
57439.37/8390.57	% SZS status Theorem for HL403752+5.p
57439.37/8390.57	% SZS status Ended for HL403752+5.p
57445.01/8391.28	% SZS status Started for HL403746+4.p
57445.01/8391.28	% SZS status GaveUp for HL403746+4.p
57445.01/8391.28	eprover: CPU time limit exceeded, terminating
57445.01/8391.28	% SZS status Ended for HL403746+4.p
57456.58/8392.78	% SZS status Started for HL403753+5.p
57456.58/8392.78	% SZS status Theorem for HL403753+5.p
57456.58/8392.78	% SZS status Ended for HL403753+5.p
57466.39/8394.02	% SZS status Started for HL403751+5.p
57466.39/8394.02	% SZS status GaveUp for HL403751+5.p
57466.39/8394.02	% SZS status Ended for HL403751+5.p
57479.04/8395.59	% SZS status Started for HL403748+4.p
57479.04/8395.59	% SZS status GaveUp for HL403748+4.p
57479.04/8395.59	eprover: CPU time limit exceeded, terminating
57479.04/8395.59	% SZS status Ended for HL403748+4.p
57480.92/8395.90	% SZS status Started for HL403754+5.p
57480.92/8395.90	% SZS status Theorem for HL403754+5.p
57480.92/8395.90	% SZS status Ended for HL403754+5.p
57494.91/8397.61	% SZS status Started for HL403755+5.p
57494.91/8397.61	% SZS status Theorem for HL403755+5.p
57494.91/8397.61	% SZS status Ended for HL403755+5.p
57499.21/8398.25	% SZS status Started for HL403749+4.p
57499.21/8398.25	% SZS status GaveUp for HL403749+4.p
57499.21/8398.25	eprover: CPU time limit exceeded, terminating
57499.21/8398.25	% SZS status Ended for HL403749+4.p
57513.05/8399.88	% SZS status Started for HL403756+5.p
57513.05/8399.88	% SZS status Theorem for HL403756+5.p
57513.05/8399.88	% SZS status Ended for HL403756+5.p
57544.61/8403.85	% SZS status Started for HL403750+4.p
57544.61/8403.85	% SZS status GaveUp for HL403750+4.p
57544.61/8403.85	eprover: CPU time limit exceeded, terminating
57544.61/8403.85	% SZS status Ended for HL403750+4.p
57556.98/8405.41	% SZS status Started for HL403757+5.p
57556.98/8405.41	% SZS status Theorem for HL403757+5.p
57556.98/8405.41	% SZS status Ended for HL403757+5.p
57575.13/8407.72	% SZS status Started for HL403751+4.p
57575.13/8407.72	% SZS status GaveUp for HL403751+4.p
57575.13/8407.72	eprover: CPU time limit exceeded, terminating
57575.13/8407.72	% SZS status Ended for HL403751+4.p
57588.75/8409.41	% SZS status Started for HL403758+5.p
57588.75/8409.41	% SZS status Theorem for HL403758+5.p
57588.75/8409.41	% SZS status Ended for HL403758+5.p
57617.94/8413.07	% SZS status Started for HL403752+4.p
57617.94/8413.07	% SZS status GaveUp for HL403752+4.p
57617.94/8413.07	eprover: CPU time limit exceeded, terminating
57617.94/8413.07	% SZS status Ended for HL403752+4.p
57640.93/8415.96	% SZS status Started for HL403753+4.p
57640.93/8415.96	% SZS status GaveUp for HL403753+4.p
57640.93/8415.96	eprover: CPU time limit exceeded, terminating
57640.93/8415.96	% SZS status Ended for HL403753+4.p
57659.65/8418.32	% SZS status Started for HL403754+4.p
57659.65/8418.32	% SZS status GaveUp for HL403754+4.p
57659.65/8418.32	eprover: CPU time limit exceeded, terminating
57659.65/8418.32	% SZS status Ended for HL403754+4.p
57680.73/8420.97	% SZS status Started for HL403755+4.p
57680.73/8420.97	% SZS status GaveUp for HL403755+4.p
57680.73/8420.97	eprover: CPU time limit exceeded, terminating
57680.73/8420.97	% SZS status Ended for HL403755+4.p
57689.87/8422.09	% SZS status Started for HL403759+5.p
57689.87/8422.09	% SZS status GaveUp for HL403759+5.p
57689.87/8422.09	% SZS status Ended for HL403759+5.p
57696.77/8423.00	% SZS status Started for HL403756+4.p
57696.77/8423.00	% SZS status GaveUp for HL403756+4.p
57696.77/8423.00	eprover: CPU time limit exceeded, terminating
57696.77/8423.00	% SZS status Ended for HL403756+4.p
57708.54/8424.51	% SZS status Started for HL403761+5.p
57708.54/8424.51	% SZS status Theorem for HL403761+5.p
57708.54/8424.51	% SZS status Ended for HL403761+5.p
57715.28/8425.27	% SZS status Started for HL403757+4.p
57715.28/8425.27	% SZS status GaveUp for HL403757+4.p
57715.28/8425.27	eprover: CPU time limit exceeded, terminating
57715.28/8425.27	% SZS status Ended for HL403757+4.p
57757.84/8430.72	% SZS status Started for HL403763+5.p
57757.84/8430.72	% SZS status Theorem for HL403763+5.p
57757.84/8430.72	% SZS status Ended for HL403763+5.p
57759.00/8430.76	% SZS status Started for HL403758+4.p
57759.00/8430.76	% SZS status GaveUp for HL403758+4.p
57759.00/8430.76	eprover: CPU time limit exceeded, terminating
57759.00/8430.76	% SZS status Ended for HL403758+4.p
57764.37/8431.46	% SZS status Started for HL403762+5.p
57764.37/8431.46	% SZS status GaveUp for HL403762+5.p
57764.37/8431.46	% SZS status Ended for HL403762+5.p
57790.93/8434.79	% SZS status Started for HL403759+4.p
57790.93/8434.79	% SZS status GaveUp for HL403759+4.p
57790.93/8434.79	eprover: CPU time limit exceeded, terminating
57790.93/8434.79	% SZS status Ended for HL403759+4.p
57807.56/8436.91	% SZS status Started for HL403764+5.p
57807.56/8436.91	% SZS status Theorem for HL403764+5.p
57807.56/8436.91	% SZS status Ended for HL403764+5.p
57813.57/8437.67	% SZS status Started for HL403765+5.p
57813.57/8437.67	% SZS status Theorem for HL403765+5.p
57813.57/8437.67	% SZS status Ended for HL403765+5.p
57842.56/8441.27	% SZS status Started for HL403761+4.p
57842.56/8441.27	% SZS status GaveUp for HL403761+4.p
57842.56/8441.27	eprover: CPU time limit exceeded, terminating
57842.56/8441.27	% SZS status Ended for HL403761+4.p
57857.28/8443.23	% SZS status Started for HL403766+5.p
57857.28/8443.23	% SZS status Theorem for HL403766+5.p
57857.28/8443.23	% SZS status Ended for HL403766+5.p
57882.22/8446.28	% SZS status Started for HL403762+4.p
57882.22/8446.28	% SZS status GaveUp for HL403762+4.p
57882.22/8446.28	eprover: CPU time limit exceeded, terminating
57882.22/8446.28	% SZS status Ended for HL403762+4.p
57892.15/8447.67	% SZS status Started for HL403767+5.p
57892.15/8447.67	% SZS status Theorem for HL403767+5.p
57892.15/8447.67	% SZS status Ended for HL403767+5.p
57899.10/8448.51	% SZS status Started for HL403763+4.p
57899.10/8448.51	% SZS status GaveUp for HL403763+4.p
57899.10/8448.51	eprover: CPU time limit exceeded, terminating
57899.10/8448.51	% SZS status Ended for HL403763+4.p
57914.99/8450.59	% SZS status Started for HL403764+4.p
57914.99/8450.59	% SZS status GaveUp for HL403764+4.p
57914.99/8450.59	eprover: CPU time limit exceeded, terminating
57914.99/8450.59	% SZS status Ended for HL403764+4.p
57932.83/8452.70	% SZS status Started for HL403768+5.p
57932.83/8452.70	% SZS status Theorem for HL403768+5.p
57932.83/8452.70	% SZS status Ended for HL403768+5.p
57959.86/8456.10	% SZS status Started for HL403765+4.p
57959.86/8456.10	% SZS status GaveUp for HL403765+4.p
57959.86/8456.10	eprover: CPU time limit exceeded, terminating
57959.86/8456.10	% SZS status Ended for HL403765+4.p
57969.64/8457.48	% SZS status Started for HL403769+5.p
57969.64/8457.48	% SZS status GaveUp for HL403769+5.p
57969.64/8457.48	% SZS status Ended for HL403769+5.p
57990.72/8460.05	% SZS status Started for HL403766+4.p
57990.72/8460.05	% SZS status GaveUp for HL403766+4.p
57990.72/8460.05	eprover: CPU time limit exceeded, terminating
57990.72/8460.05	% SZS status Ended for HL403766+4.p
58004.34/8461.73	% SZS status Started for HL403770+5.p
58004.34/8461.73	% SZS status GaveUp for HL403770+5.p
58004.34/8461.73	% SZS status Ended for HL403770+5.p
58014.77/8463.04	% SZS status Started for HL403767+4.p
58014.77/8463.04	% SZS status GaveUp for HL403767+4.p
58014.77/8463.04	eprover: CPU time limit exceeded, terminating
58014.77/8463.04	% SZS status Ended for HL403767+4.p
58021.01/8463.79	% SZS status Started for HL403771+5.p
58021.01/8463.79	% SZS status Theorem for HL403771+5.p
58021.01/8463.79	% SZS status Ended for HL403771+5.p
58057.63/8468.39	% SZS status Started for HL403772+5.p
58057.63/8468.39	% SZS status Theorem for HL403772+5.p
58057.63/8468.39	% SZS status Ended for HL403772+5.p
58059.22/8468.61	% SZS status Started for HL403768+4.p
58059.22/8468.61	% SZS status GaveUp for HL403768+4.p
58059.22/8468.61	eprover: CPU time limit exceeded, terminating
58059.22/8468.61	% SZS status Ended for HL403768+4.p
58070.14/8469.99	% SZS status Started for HL403773+5.p
58070.14/8469.99	% SZS status Theorem for HL403773+5.p
58070.14/8469.99	% SZS status Ended for HL403773+5.p
58096.95/8473.37	% SZS status Started for HL403769+4.p
58096.95/8473.37	% SZS status GaveUp for HL403769+4.p
58096.95/8473.37	eprover: CPU time limit exceeded, terminating
58096.95/8473.37	% SZS status Ended for HL403769+4.p
58116.49/8475.87	% SZS status Started for HL403770+4.p
58116.49/8475.87	% SZS status GaveUp for HL403770+4.p
58116.49/8475.87	eprover: CPU time limit exceeded, terminating
58116.49/8475.87	% SZS status Ended for HL403770+4.p
58129.84/8477.61	% SZS status Started for HL403777+5.p
58129.84/8477.61	% SZS status GaveUp for HL403777+5.p
58129.84/8477.61	% SZS status Ended for HL403777+5.p
58161.05/8481.42	% SZS status Started for HL403771+4.p
58161.05/8481.42	% SZS status GaveUp for HL403771+4.p
58161.05/8481.42	eprover: CPU time limit exceeded, terminating
58161.05/8481.42	% SZS status Ended for HL403771+4.p
58169.48/8482.46	% SZS status Started for HL403778+5.p
58169.48/8482.46	% SZS status GaveUp for HL403778+5.p
58169.48/8482.46	% SZS status Ended for HL403778+5.p
58180.73/8483.91	% SZS status Started for HL403779+5.p
58180.73/8483.91	% SZS status Theorem for HL403779+5.p
58180.73/8483.91	% SZS status Ended for HL403779+5.p
58197.16/8485.97	% SZS status Started for HL403772+4.p
58197.16/8485.97	% SZS status GaveUp for HL403772+4.p
58197.16/8485.97	eprover: CPU time limit exceeded, terminating
58197.16/8485.97	% SZS status Ended for HL403772+4.p
58217.72/8488.59	% SZS status Started for HL403773+4.p
58217.72/8488.59	% SZS status GaveUp for HL403773+4.p
58217.72/8488.59	eprover: CPU time limit exceeded, terminating
58217.72/8488.59	% SZS status Ended for HL403773+4.p
58219.11/8488.75	% SZS status Started for HL403781+5.p
58219.11/8488.75	% SZS status Theorem for HL403781+5.p
58219.11/8488.75	% SZS status Ended for HL403781+5.p
58258.32/8493.63	% SZS status Started for HL403777+4.p
58258.32/8493.63	% SZS status GaveUp for HL403777+4.p
58258.32/8493.63	eprover: CPU time limit exceeded, terminating
58258.32/8493.63	% SZS status Ended for HL403777+4.p
58269.17/8495.03	% SZS status Started for HL403783+5.p
58269.17/8495.03	% SZS status GaveUp for HL403783+5.p
58269.17/8495.03	% SZS status Ended for HL403783+5.p
58270.70/8495.30	% SZS status Started for HL403778+4.p
58270.70/8495.30	% SZS status GaveUp for HL403778+4.p
58270.70/8495.30	eprover: CPU time limit exceeded, terminating
58270.70/8495.30	% SZS status Ended for HL403778+4.p
58292.01/8497.92	% SZS status Started for HL403784+5.p
58292.01/8497.92	% SZS status GaveUp for HL403784+5.p
58292.01/8497.92	% SZS status Ended for HL403784+5.p
58318.75/8501.27	% SZS status Started for HL403779+4.p
58318.75/8501.27	% SZS status GaveUp for HL403779+4.p
58318.75/8501.27	eprover: CPU time limit exceeded, terminating
58318.75/8501.27	% SZS status Ended for HL403779+4.p
58341.14/8504.04	% SZS status Started for HL403785+5.p
58341.14/8504.04	% SZS status GaveUp for HL403785+5.p
58341.14/8504.04	% SZS status Ended for HL403785+5.p
58362.67/8506.80	% SZS status Started for HL403781+4.p
58362.67/8506.80	% SZS status GaveUp for HL403781+4.p
58362.67/8506.80	eprover: CPU time limit exceeded, terminating
58362.67/8506.80	% SZS status Ended for HL403781+4.p
58364.36/8507.00	% SZS status Started for HL403786+5.p
58364.36/8507.00	% SZS status GaveUp for HL403786+5.p
58364.36/8507.00	% SZS status Ended for HL403786+5.p
58383.07/8509.45	% SZS status Started for HL403783+4.p
58383.07/8509.45	% SZS status GaveUp for HL403783+4.p
58383.07/8509.45	eprover: CPU time limit exceeded, terminating
58383.07/8509.45	% SZS status Ended for HL403783+4.p
58411.99/8513.06	% SZS status Started for HL403787+5.p
58411.99/8513.06	% SZS status GaveUp for HL403787+5.p
58411.99/8513.06	% SZS status Ended for HL403787+5.p
58418.95/8513.98	% SZS status Started for HL403784+4.p
58418.95/8513.98	% SZS status GaveUp for HL403784+4.p
58418.95/8513.98	eprover: CPU time limit exceeded, terminating
58418.95/8513.98	% SZS status Ended for HL403784+4.p
58440.46/8516.67	% SZS status Started for HL403788+5.p
58440.46/8516.67	% SZS status GaveUp for HL403788+5.p
58440.46/8516.67	% SZS status Ended for HL403788+5.p
58460.11/8519.13	% SZS status Started for HL403785+4.p
58460.11/8519.13	% SZS status GaveUp for HL403785+4.p
58460.11/8519.13	eprover: CPU time limit exceeded, terminating
58460.11/8519.13	% SZS status Ended for HL403785+4.p
58473.68/8520.82	% SZS status Started for HL403786+4.p
58473.68/8520.82	% SZS status GaveUp for HL403786+4.p
58473.68/8520.82	eprover: CPU time limit exceeded, terminating
58473.68/8520.82	% SZS status Ended for HL403786+4.p
58484.26/8522.13	% SZS status Started for HL403789+5.p
58484.26/8522.13	% SZS status GaveUp for HL403789+5.p
58484.26/8522.13	% SZS status Ended for HL403789+5.p
58513.10/8525.74	% SZS status Started for HL403790+5.p
58513.10/8525.74	% SZS status GaveUp for HL403790+5.p
58513.10/8525.74	% SZS status Ended for HL403790+5.p
58517.80/8526.38	% SZS status Started for HL403787+4.p
58517.80/8526.38	% SZS status GaveUp for HL403787+4.p
58517.80/8526.38	eprover: CPU time limit exceeded, terminating
58517.80/8526.38	% SZS status Ended for HL403787+4.p
58545.46/8529.86	% SZS status Started for HL403791+5.p
58545.46/8529.86	% SZS status GaveUp for HL403791+5.p
58545.46/8529.86	% SZS status Ended for HL403791+5.p
58567.06/8532.51	% SZS status Started for HL403788+4.p
58567.06/8532.51	% SZS status GaveUp for HL403788+4.p
58567.06/8532.51	eprover: CPU time limit exceeded, terminating
58567.06/8532.51	% SZS status Ended for HL403788+4.p
58583.13/8534.53	% SZS status Started for HL403789+4.p
58583.13/8534.53	% SZS status GaveUp for HL403789+4.p
58583.13/8534.53	eprover: CPU time limit exceeded, terminating
58583.13/8534.53	% SZS status Ended for HL403789+4.p
58584.95/8534.79	% SZS status Started for HL403792+5.p
58584.95/8534.79	% SZS status GaveUp for HL403792+5.p
58584.95/8534.79	% SZS status Ended for HL403792+5.p
58617.74/8538.92	% SZS status Started for HL403793+5.p
58617.74/8538.92	% SZS status GaveUp for HL403793+5.p
58617.74/8538.92	% SZS status Ended for HL403793+5.p
58619.23/8539.20	% SZS status Started for HL403790+4.p
58619.23/8539.20	% SZS status GaveUp for HL403790+4.p
58619.23/8539.20	eprover: CPU time limit exceeded, terminating
58619.23/8539.20	% SZS status Ended for HL403790+4.p
58655.92/8543.68	% SZS status Started for HL403794+5.p
58655.92/8543.68	% SZS status GaveUp for HL403794+5.p
58655.92/8543.68	% SZS status Ended for HL403794+5.p
58660.28/8544.34	% SZS status Started for HL403791+4.p
58660.28/8544.34	% SZS status GaveUp for HL403791+4.p
58660.28/8544.34	eprover: CPU time limit exceeded, terminating
58660.28/8544.34	% SZS status Ended for HL403791+4.p
58683.09/8547.16	% SZS status Started for HL403792+4.p
58683.09/8547.16	% SZS status GaveUp for HL403792+4.p
58683.09/8547.16	eprover: CPU time limit exceeded, terminating
58683.09/8547.16	% SZS status Ended for HL403792+4.p
58689.63/8548.07	% SZS status Started for HL403795+5.p
58689.63/8548.07	% SZS status GaveUp for HL403795+5.p
58689.63/8548.07	% SZS status Ended for HL403795+5.p
58717.51/8551.57	% SZS status Started for HL403793+4.p
58717.51/8551.57	% SZS status GaveUp for HL403793+4.p
58717.51/8551.57	eprover: CPU time limit exceeded, terminating
58717.51/8551.57	% SZS status Ended for HL403793+4.p
58731.47/8553.43	% SZS status Started for HL403796+5.p
58731.47/8553.43	% SZS status GaveUp for HL403796+5.p
58731.47/8553.43	% SZS status Ended for HL403796+5.p
58754.57/8556.43	% SZS status Started for HL403798+5.p
58754.57/8556.43	% SZS status GaveUp for HL403798+5.p
58754.57/8556.43	% SZS status Ended for HL403798+5.p
58768.08/8558.12	% SZS status Started for HL403794+4.p
58768.08/8558.12	% SZS status GaveUp for HL403794+4.p
58768.08/8558.12	eprover: CPU time limit exceeded, terminating
58768.08/8558.12	% SZS status Ended for HL403794+4.p
58781.26/8559.93	% SZS status Started for HL403795+4.p
58781.26/8559.93	% SZS status GaveUp for HL403795+4.p
58781.26/8559.93	eprover: CPU time limit exceeded, terminating
58781.26/8559.93	% SZS status Ended for HL403795+4.p
58794.70/8561.65	% SZS status Started for HL403800+5.p
58794.70/8561.65	% SZS status GaveUp for HL403800+5.p
58794.70/8561.65	% SZS status Ended for HL403800+5.p
58811.77/8563.88	% SZS status Started for HL403801+5.p
58811.77/8563.88	% SZS status Theorem for HL403801+5.p
58811.77/8563.88	% SZS status Ended for HL403801+5.p
58819.41/8564.87	% SZS status Started for HL403796+4.p
58819.41/8564.87	% SZS status GaveUp for HL403796+4.p
58819.41/8564.87	eprover: CPU time limit exceeded, terminating
58819.41/8564.87	% SZS status Ended for HL403796+4.p
58856.61/8569.70	% SZS status Started for HL403802+5.p
58856.61/8569.70	% SZS status GaveUp for HL403802+5.p
58856.61/8569.70	% SZS status Ended for HL403802+5.p
58861.93/8570.40	% SZS status Started for HL403798+4.p
58861.93/8570.40	% SZS status GaveUp for HL403798+4.p
58861.93/8570.40	eprover: CPU time limit exceeded, terminating
58861.93/8570.40	% SZS status Ended for HL403798+4.p
58867.41/8571.09	% SZS status Started for HL403804+5.p
58867.41/8571.09	% SZS status Theorem for HL403804+5.p
58867.41/8571.09	% SZS status Ended for HL403804+5.p
58894.03/8573.78	% SZS status Started for HL403800+4.p
58894.03/8573.78	% SZS status GaveUp for HL403800+4.p
58894.03/8573.78	eprover: CPU time limit exceeded, terminating
58894.03/8573.78	% SZS status Ended for HL403800+4.p
58931.26/8578.83	% SZS status Started for HL403806+5.p
58931.26/8578.83	% SZS status Theorem for HL403806+5.p
58931.26/8578.83	% SZS status Ended for HL403806+5.p
58936.49/8579.38	% SZS status Started for HL403801+4.p
58936.49/8579.38	% SZS status GaveUp for HL403801+4.p
58936.49/8579.38	eprover: CPU time limit exceeded, terminating
58936.49/8579.38	% SZS status Ended for HL403801+4.p
58939.42/8579.72	% SZS status Started for HL403805+5.p
58939.42/8579.72	% SZS status GaveUp for HL403805+5.p
58939.42/8579.72	% SZS status Ended for HL403805+5.p
58977.57/8584.67	% SZS status Started for HL403802+4.p
58977.57/8584.67	% SZS status GaveUp for HL403802+4.p
58977.57/8584.67	eprover: CPU time limit exceeded, terminating
58977.57/8584.67	% SZS status Ended for HL403802+4.p
58996.56/8587.07	% SZS status Started for HL403808+5.p
58996.56/8587.07	% SZS status Theorem for HL403808+5.p
58996.56/8587.07	% SZS status Ended for HL403808+5.p
59003.32/8588.05	% SZS status Started for HL403804+4.p
59003.32/8588.05	% SZS status GaveUp for HL403804+4.p
59003.32/8588.05	eprover: CPU time limit exceeded, terminating
59003.32/8588.05	% SZS status Ended for HL403804+4.p
59006.14/8588.51	% SZS status Started for HL403807+5.p
59006.14/8588.51	% SZS status GaveUp for HL403807+5.p
59006.14/8588.51	% SZS status Ended for HL403807+5.p
59040.95/8591.91	% SZS status Started for HL403805+4.p
59040.95/8591.91	% SZS status GaveUp for HL403805+4.p
59040.95/8591.91	eprover: CPU time limit exceeded, terminating
59040.95/8591.91	% SZS status Ended for HL403805+4.p
59079.33/8596.91	% SZS status Started for HL403806+4.p
59079.33/8596.91	% SZS status GaveUp for HL403806+4.p
59079.33/8596.91	eprover: CPU time limit exceeded, terminating
59079.33/8596.91	% SZS status Ended for HL403806+4.p
59081.63/8597.19	% SZS status Started for HL403809+5.p
59081.63/8597.19	% SZS status GaveUp for HL403809+5.p
59081.63/8597.19	% SZS status Ended for HL403809+5.p
59088.59/8598.11	% SZS status Started for HL403811+5.p
59088.59/8598.11	% SZS status GaveUp for HL403811+5.p
59088.59/8598.11	% SZS status Ended for HL403811+5.p
59099.81/8599.66	% SZS status Started for HL403807+4.p
59099.81/8599.66	% SZS status GaveUp for HL403807+4.p
59099.81/8599.66	eprover: CPU time limit exceeded, terminating
59099.81/8599.66	% SZS status Ended for HL403807+4.p
59144.24/8605.58	% SZS status Started for HL403808+4.p
59144.24/8605.58	% SZS status GaveUp for HL403808+4.p
59144.24/8605.58	eprover: CPU time limit exceeded, terminating
59144.24/8605.58	% SZS status Ended for HL403808+4.p
59160.48/8607.77	% SZS status Started for HL403813+5.p
59160.48/8607.77	% SZS status GaveUp for HL403813+5.p
59160.48/8607.77	% SZS status Ended for HL403813+5.p
59160.48/8607.79	% SZS status Started for HL403812+5.p
59160.48/8607.79	% SZS status GaveUp for HL403812+5.p
59160.48/8607.79	% SZS status Ended for HL403812+5.p
59189.92/8611.42	% SZS status Started for HL403809+4.p
59189.92/8611.42	% SZS status GaveUp for HL403809+4.p
59189.92/8611.42	eprover: CPU time limit exceeded, terminating
59189.92/8611.42	% SZS status Ended for HL403809+4.p
59219.01/8615.16	% SZS status Started for HL403814+5.p
59219.01/8615.16	% SZS status GaveUp for HL403814+5.p
59219.01/8615.16	% SZS status Ended for HL403814+5.p
59219.68/8615.21	% SZS status Started for HL403811+4.p
59219.68/8615.21	% SZS status GaveUp for HL403811+4.p
59219.68/8615.21	eprover: CPU time limit exceeded, terminating
59219.68/8615.21	% SZS status Ended for HL403811+4.p
59233.07/8616.90	% SZS status Started for HL403815+5.p
59233.07/8616.90	% SZS status GaveUp for HL403815+5.p
59233.07/8616.90	% SZS status Ended for HL403815+5.p
59243.58/8618.31	% SZS status Started for HL403812+4.p
59243.58/8618.31	% SZS status GaveUp for HL403812+4.p
59243.58/8618.31	eprover: CPU time limit exceeded, terminating
59243.58/8618.31	% SZS status Ended for HL403812+4.p
59278.89/8622.79	% SZS status Started for HL403813+4.p
59278.89/8622.79	% SZS status GaveUp for HL403813+4.p
59278.89/8622.79	eprover: CPU time limit exceeded, terminating
59278.89/8622.79	% SZS status Ended for HL403813+4.p
59291.19/8624.20	% SZS status Started for HL403817+5.p
59291.19/8624.20	% SZS status GaveUp for HL403817+5.p
59291.19/8624.20	% SZS status Ended for HL403817+5.p
59303.36/8625.83	% SZS status Started for HL403814+4.p
59303.36/8625.83	% SZS status GaveUp for HL403814+4.p
59303.36/8625.83	eprover: CPU time limit exceeded, terminating
59303.36/8625.83	% SZS status Ended for HL403814+4.p
59303.71/8625.95	% SZS status Started for HL403818+5.p
59303.71/8625.95	% SZS status GaveUp for HL403818+5.p
59303.71/8625.95	% SZS status Ended for HL403818+5.p
59351.77/8631.82	% SZS status Started for HL403819+5.p
59351.77/8631.82	% SZS status GaveUp for HL403819+5.p
59351.77/8631.82	% SZS status Ended for HL403819+5.p
59362.27/8633.12	% SZS status Started for HL403815+4.p
59362.27/8633.12	% SZS status GaveUp for HL403815+4.p
59362.27/8633.12	eprover: CPU time limit exceeded, terminating
59362.27/8633.12	% SZS status Ended for HL403815+4.p
59375.69/8634.84	% SZS status Started for HL403820+5.p
59375.69/8634.84	% SZS status GaveUp for HL403820+5.p
59375.69/8634.84	% SZS status Ended for HL403820+5.p
59390.98/8636.77	% SZS status Started for HL403817+4.p
59390.98/8636.77	% SZS status GaveUp for HL403817+4.p
59390.98/8636.77	eprover: CPU time limit exceeded, terminating
59390.98/8636.77	% SZS status Ended for HL403817+4.p
59423.37/8640.84	% SZS status Started for HL403818+4.p
59423.37/8640.84	% SZS status GaveUp for HL403818+4.p
59423.37/8640.84	eprover: CPU time limit exceeded, terminating
59423.37/8640.84	% SZS status Ended for HL403818+4.p
59423.73/8640.89	% SZS status Started for HL403821+5.p
59423.73/8640.89	% SZS status GaveUp for HL403821+5.p
59423.73/8640.89	% SZS status Ended for HL403821+5.p
59445.85/8643.63	% SZS status Started for HL403819+4.p
59445.85/8643.63	% SZS status GaveUp for HL403819+4.p
59445.85/8643.63	eprover: CPU time limit exceeded, terminating
59445.85/8643.63	% SZS status Ended for HL403819+4.p
59447.02/8643.89	% SZS status Started for HL403822+5.p
59447.02/8643.89	% SZS status GaveUp for HL403822+5.p
59447.02/8643.89	% SZS status Ended for HL403822+5.p
59491.73/8649.43	% SZS status Started for HL403820+4.p
59491.73/8649.43	% SZS status GaveUp for HL403820+4.p
59491.73/8649.43	eprover: CPU time limit exceeded, terminating
59491.73/8649.43	% SZS status Ended for HL403820+4.p
59495.43/8649.88	% SZS status Started for HL403823+5.p
59495.43/8649.88	% SZS status GaveUp for HL403823+5.p
59495.43/8649.88	% SZS status Ended for HL403823+5.p
59505.61/8651.15	% SZS status Started for HL403821+4.p
59505.61/8651.15	% SZS status GaveUp for HL403821+4.p
59505.61/8651.15	eprover: CPU time limit exceeded, terminating
59505.61/8651.15	% SZS status Ended for HL403821+4.p
59516.39/8652.64	% SZS status Started for HL403824+5.p
59516.39/8652.64	% SZS status GaveUp for HL403824+5.p
59516.39/8652.64	% SZS status Ended for HL403824+5.p
59562.00/8658.25	% SZS status Started for HL403822+4.p
59562.00/8658.25	% SZS status GaveUp for HL403822+4.p
59562.00/8658.25	eprover: CPU time limit exceeded, terminating
59562.00/8658.25	% SZS status Ended for HL403822+4.p
59564.06/8658.48	% SZS status Started for HL403825+5.p
59564.06/8658.48	% SZS status GaveUp for HL403825+5.p
59564.06/8658.48	% SZS status Ended for HL403825+5.p
59577.82/8660.22	% SZS status Started for HL403827+5.p
59577.82/8660.22	% SZS status GaveUp for HL403827+5.p
59577.82/8660.22	% SZS status Ended for HL403827+5.p
59591.43/8661.95	% SZS status Started for HL403823+4.p
59591.43/8661.95	% SZS status GaveUp for HL403823+4.p
59591.43/8661.95	eprover: CPU time limit exceeded, terminating
59591.43/8661.95	% SZS status Ended for HL403823+4.p
59623.39/8665.98	% SZS status Started for HL403824+4.p
59623.39/8665.98	% SZS status GaveUp for HL403824+4.p
59623.39/8665.98	eprover: CPU time limit exceeded, terminating
59623.39/8665.98	% SZS status Ended for HL403824+4.p
59631.45/8667.04	% SZS status Started for HL403828+5.p
59631.45/8667.04	% SZS status GaveUp for HL403828+5.p
59631.45/8667.04	% SZS status Ended for HL403828+5.p
59647.88/8669.06	% SZS status Started for HL403825+4.p
59647.88/8669.06	% SZS status GaveUp for HL403825+4.p
59647.88/8669.06	eprover: CPU time limit exceeded, terminating
59647.88/8669.06	% SZS status Ended for HL403825+4.p
59648.80/8669.24	% SZS status Started for HL403829+5.p
59648.80/8669.24	% SZS status GaveUp for HL403829+5.p
59648.80/8669.24	% SZS status Ended for HL403829+5.p
59693.48/8674.82	% SZS status Started for HL403830+5.p
59693.48/8674.82	% SZS status GaveUp for HL403830+5.p
59693.48/8674.82	% SZS status Ended for HL403830+5.p
59694.82/8675.06	% SZS status Started for HL403827+4.p
59694.82/8675.06	% SZS status GaveUp for HL403827+4.p
59694.82/8675.06	eprover: CPU time limit exceeded, terminating
59694.82/8675.06	% SZS status Ended for HL403827+4.p
59717.22/8677.80	% SZS status Started for HL403828+4.p
59717.22/8677.80	% SZS status GaveUp for HL403828+4.p
59717.22/8677.80	eprover: CPU time limit exceeded, terminating
59717.22/8677.80	% SZS status Ended for HL403828+4.p
59719.77/8678.06	% SZS status Started for HL403831+5.p
59719.77/8678.06	% SZS status GaveUp for HL403831+5.p
59719.77/8678.06	% SZS status Ended for HL403831+5.p
59764.25/8683.70	% SZS status Started for HL403829+4.p
59764.25/8683.70	% SZS status GaveUp for HL403829+4.p
59764.25/8683.70	eprover: CPU time limit exceeded, terminating
59764.25/8683.70	% SZS status Ended for HL403829+4.p
59766.19/8683.92	% SZS status Started for HL403832+5.p
59766.19/8683.92	% SZS status GaveUp for HL403832+5.p
59766.19/8683.92	% SZS status Ended for HL403832+5.p
59789.30/8686.87	% SZS status Started for HL403833+5.p
59789.30/8686.87	% SZS status GaveUp for HL403833+5.p
59789.30/8686.87	% SZS status Ended for HL403833+5.p
59791.37/8687.10	% SZS status Started for HL403830+4.p
59791.37/8687.10	% SZS status GaveUp for HL403830+4.p
59791.37/8687.10	eprover: CPU time limit exceeded, terminating
59791.37/8687.10	% SZS status Ended for HL403830+4.p
59832.15/8692.19	% SZS status Started for HL403831+4.p
59832.15/8692.19	% SZS status GaveUp for HL403831+4.p
59832.15/8692.19	eprover: CPU time limit exceeded, terminating
59832.15/8692.19	% SZS status Ended for HL403831+4.p
59836.52/8692.76	% SZS status Started for HL403834+5.p
59836.52/8692.76	% SZS status GaveUp for HL403834+5.p
59836.52/8692.76	% SZS status Ended for HL403834+5.p
59849.86/8694.39	% SZS status Started for HL403832+4.p
59849.86/8694.39	% SZS status GaveUp for HL403832+4.p
59849.86/8694.39	eprover: CPU time limit exceeded, terminating
59849.86/8694.39	% SZS status Ended for HL403832+4.p
59862.20/8695.96	% SZS status Started for HL403835+5.p
59862.20/8695.96	% SZS status GaveUp for HL403835+5.p
59862.20/8695.96	% SZS status Ended for HL403835+5.p
59895.98/8700.24	% SZS status Started for HL403833+4.p
59895.98/8700.24	% SZS status GaveUp for HL403833+4.p
59895.98/8700.24	eprover: CPU time limit exceeded, terminating
59895.98/8700.24	% SZS status Ended for HL403833+4.p
59904.40/8701.25	% SZS status Started for HL403836+5.p
59904.40/8701.25	% SZS status GaveUp for HL403836+5.p
59904.40/8701.25	% SZS status Ended for HL403836+5.p
59919.38/8703.20	% SZS status Started for HL403834+4.p
59919.38/8703.20	% SZS status GaveUp for HL403834+4.p
59919.38/8703.20	eprover: CPU time limit exceeded, terminating
59919.38/8703.20	% SZS status Ended for HL403834+4.p
59921.87/8703.46	% SZS status Started for HL403838+5.p
59921.87/8703.46	% SZS status GaveUp for HL403838+5.p
59921.87/8703.46	% SZS status Ended for HL403838+5.p
59965.75/8709.02	% SZS status Started for HL403835+4.p
59965.75/8709.02	% SZS status GaveUp for HL403835+4.p
59965.75/8709.02	eprover: CPU time limit exceeded, terminating
59965.75/8709.02	% SZS status Ended for HL403835+4.p
59968.29/8709.28	% SZS status Started for HL403839+5.p
59968.29/8709.28	% SZS status GaveUp for HL403839+5.p
59968.29/8709.28	% SZS status Ended for HL403839+5.p
59991.57/8712.26	% SZS status Started for HL403840+5.p
59991.57/8712.26	% SZS status GaveUp for HL403840+5.p
59991.57/8712.26	% SZS status Ended for HL403840+5.p
59991.97/8712.32	% SZS status Started for HL403836+4.p
59991.97/8712.32	% SZS status GaveUp for HL403836+4.p
59991.97/8712.32	eprover: CPU time limit exceeded, terminating
59991.97/8712.32	% SZS status Ended for HL403836+4.p
60036.64/8717.90	% SZS status Started for HL403841+5.p
60036.64/8717.90	% SZS status GaveUp for HL403841+5.p
60036.64/8717.90	% SZS status Ended for HL403841+5.p
60037.17/8717.94	% SZS status Started for HL403838+4.p
60037.17/8717.94	% SZS status GaveUp for HL403838+4.p
60037.17/8717.94	eprover: CPU time limit exceeded, terminating
60037.17/8717.94	% SZS status Ended for HL403838+4.p
60061.95/8721.08	% SZS status Started for HL403839+4.p
60061.95/8721.08	% SZS status GaveUp for HL403839+4.p
60061.95/8721.08	eprover: CPU time limit exceeded, terminating
60061.95/8721.08	% SZS status Ended for HL403839+4.p
60062.26/8721.12	% SZS status Started for HL403843+5.p
60062.26/8721.12	% SZS status GaveUp for HL403843+5.p
60062.26/8721.12	% SZS status Ended for HL403843+5.p
60104.26/8726.35	% SZS status Started for HL403840+4.p
60104.26/8726.35	% SZS status GaveUp for HL403840+4.p
60104.26/8726.35	eprover: CPU time limit exceeded, terminating
60104.26/8726.35	% SZS status Ended for HL403840+4.p
60109.10/8727.00	% SZS status Started for HL403844+5.p
60109.10/8727.00	% SZS status GaveUp for HL403844+5.p
60109.10/8727.00	% SZS status Ended for HL403844+5.p
60120.72/8728.56	% SZS status Started for HL403841+4.p
60120.72/8728.56	% SZS status GaveUp for HL403841+4.p
60120.72/8728.56	eprover: CPU time limit exceeded, terminating
60120.72/8728.56	% SZS status Ended for HL403841+4.p
60132.93/8730.02	% SZS status Started for HL403845+5.p
60132.93/8730.02	% SZS status GaveUp for HL403845+5.p
60132.93/8730.02	% SZS status Ended for HL403845+5.p
60168.04/8734.38	% SZS status Started for HL403843+4.p
60168.04/8734.38	% SZS status GaveUp for HL403843+4.p
60168.04/8734.38	eprover: CPU time limit exceeded, terminating
60168.04/8734.38	% SZS status Ended for HL403843+4.p
60176.79/8735.45	% SZS status Started for HL403846+5.p
60176.79/8735.45	% SZS status GaveUp for HL403846+5.p
60176.79/8735.45	% SZS status Ended for HL403846+5.p
60191.86/8737.44	% SZS status Started for HL403844+4.p
60191.86/8737.44	% SZS status GaveUp for HL403844+4.p
60191.86/8737.44	eprover: CPU time limit exceeded, terminating
60191.86/8737.44	% SZS status Ended for HL403844+4.p
60192.38/8737.62	% SZS status Started for HL403847+5.p
60192.38/8737.62	% SZS status GaveUp for HL403847+5.p
60192.38/8737.62	% SZS status Ended for HL403847+5.p
60237.93/8743.21	% SZS status Started for HL403845+4.p
60237.93/8743.21	% SZS status GaveUp for HL403845+4.p
60237.93/8743.21	eprover: CPU time limit exceeded, terminating
60237.93/8743.21	% SZS status Ended for HL403845+4.p
60239.57/8743.37	% SZS status Started for HL403848+5.p
60239.57/8743.37	% SZS status GaveUp for HL403848+5.p
60239.57/8743.37	% SZS status Ended for HL403848+5.p
60262.85/8746.28	% SZS status Started for HL403851+5.p
60262.85/8746.28	% SZS status GaveUp for HL403851+5.p
60262.85/8746.28	% SZS status Ended for HL403851+5.p
60262.85/8746.32	% SZS status Started for HL403846+4.p
60262.85/8746.32	% SZS status GaveUp for HL403846+4.p
60262.85/8746.32	eprover: CPU time limit exceeded, terminating
60262.85/8746.32	% SZS status Ended for HL403846+4.p
60308.45/8752.06	% SZS status Started for HL403852+5.p
60308.45/8752.06	% SZS status GaveUp for HL403852+5.p
60308.45/8752.06	% SZS status Ended for HL403852+5.p
60309.73/8752.15	% SZS status Started for HL403847+4.p
60309.73/8752.15	% SZS status GaveUp for HL403847+4.p
60309.73/8752.15	eprover: CPU time limit exceeded, terminating
60309.73/8752.15	% SZS status Ended for HL403847+4.p
60332.46/8755.05	% SZS status Started for HL403853+5.p
60332.46/8755.05	% SZS status GaveUp for HL403853+5.p
60332.46/8755.05	% SZS status Ended for HL403853+5.p
60332.91/8755.07	% SZS status Started for HL403848+4.p
60332.91/8755.07	% SZS status GaveUp for HL403848+4.p
60332.91/8755.07	eprover: CPU time limit exceeded, terminating
60332.91/8755.07	% SZS status Ended for HL403848+4.p
60378.57/8760.82	% SZS status Started for HL403851+4.p
60378.57/8760.82	% SZS status GaveUp for HL403851+4.p
60378.57/8760.82	eprover: CPU time limit exceeded, terminating
60378.57/8760.82	% SZS status Ended for HL403851+4.p
60379.73/8761.05	% SZS status Started for HL403854+5.p
60379.73/8761.05	% SZS status GaveUp for HL403854+5.p
60379.73/8761.05	% SZS status Ended for HL403854+5.p
60394.32/8762.89	% SZS status Started for HL403852+4.p
60394.32/8762.89	% SZS status GaveUp for HL403852+4.p
60394.32/8762.89	eprover: CPU time limit exceeded, terminating
60394.32/8762.89	% SZS status Ended for HL403852+4.p
60401.94/8763.80	% SZS status Started for HL403855+5.p
60401.94/8763.80	% SZS status GaveUp for HL403855+5.p
60401.94/8763.80	% SZS status Ended for HL403855+5.p
60438.43/8768.51	% SZS status Started for HL403853+4.p
60438.43/8768.51	% SZS status GaveUp for HL403853+4.p
60438.43/8768.51	eprover: CPU time limit exceeded, terminating
60438.43/8768.51	% SZS status Ended for HL403853+4.p
60448.84/8769.71	% SZS status Started for HL403856+5.p
60448.84/8769.71	% SZS status GaveUp for HL403856+5.p
60448.84/8769.71	% SZS status Ended for HL403856+5.p
60462.39/8771.34	% SZS status Started for HL403854+4.p
60462.39/8771.34	% SZS status GaveUp for HL403854+4.p
60462.39/8771.34	eprover: CPU time limit exceeded, terminating
60462.39/8771.34	% SZS status Ended for HL403854+4.p
60464.79/8771.68	% SZS status Started for HL403858+5.p
60464.79/8771.68	% SZS status GaveUp for HL403858+5.p
60464.79/8771.68	% SZS status Ended for HL403858+5.p
60508.88/8777.19	% SZS status Started for HL403855+4.p
60508.88/8777.19	% SZS status GaveUp for HL403855+4.p
60508.88/8777.19	eprover: CPU time limit exceeded, terminating
60508.88/8777.19	% SZS status Ended for HL403855+4.p
60510.78/8777.52	% SZS status Started for HL403859+5.p
60510.78/8777.52	% SZS status GaveUp for HL403859+5.p
60510.78/8777.52	% SZS status Ended for HL403859+5.p
60533.57/8780.35	% SZS status Started for HL403860+5.p
60533.57/8780.35	% SZS status GaveUp for HL403860+5.p
60533.57/8780.35	% SZS status Ended for HL403860+5.p
60535.30/8780.54	% SZS status Started for HL403856+4.p
60535.30/8780.54	% SZS status GaveUp for HL403856+4.p
60535.30/8780.54	eprover: CPU time limit exceeded, terminating
60535.30/8780.54	% SZS status Ended for HL403856+4.p
60580.30/8786.18	% SZS status Started for HL403861+5.p
60580.30/8786.18	% SZS status GaveUp for HL403861+5.p
60580.30/8786.18	% SZS status Ended for HL403861+5.p
60580.89/8786.24	% SZS status Started for HL403858+4.p
60580.89/8786.24	% SZS status GaveUp for HL403858+4.p
60580.89/8786.24	eprover: CPU time limit exceeded, terminating
60580.89/8786.24	% SZS status Ended for HL403858+4.p
60603.08/8789.07	% SZS status Started for HL403859+4.p
60603.08/8789.07	% SZS status GaveUp for HL403859+4.p
60603.08/8789.07	eprover: CPU time limit exceeded, terminating
60603.08/8789.07	% SZS status Ended for HL403859+4.p
60605.90/8789.39	% SZS status Started for HL403862+5.p
60605.90/8789.39	% SZS status GaveUp for HL403862+5.p
60605.90/8789.39	% SZS status Ended for HL403862+5.p
60648.27/8794.76	% SZS status Started for HL403860+4.p
60648.27/8794.76	% SZS status GaveUp for HL403860+4.p
60648.27/8794.76	eprover: CPU time limit exceeded, terminating
60648.27/8794.76	% SZS status Ended for HL403860+4.p
60652.84/8795.30	% SZS status Started for HL403864+5.p
60652.84/8795.30	% SZS status GaveUp for HL403864+5.p
60652.84/8795.30	% SZS status Ended for HL403864+5.p
60665.77/8797.00	% SZS status Started for HL403861+4.p
60665.77/8797.00	% SZS status GaveUp for HL403861+4.p
60665.77/8797.00	eprover: CPU time limit exceeded, terminating
60665.77/8797.00	% SZS status Ended for HL403861+4.p
60674.74/8798.13	% SZS status Started for HL403865+5.p
60674.74/8798.13	% SZS status GaveUp for HL403865+5.p
60674.74/8798.13	% SZS status Ended for HL403865+5.p
60709.76/8802.56	% SZS status Started for HL403862+4.p
60709.76/8802.56	% SZS status GaveUp for HL403862+4.p
60709.76/8802.56	eprover: CPU time limit exceeded, terminating
60709.76/8802.56	% SZS status Ended for HL403862+4.p
60721.98/8804.00	% SZS status Started for HL403866+5.p
60721.98/8804.00	% SZS status GaveUp for HL403866+5.p
60721.98/8804.00	% SZS status Ended for HL403866+5.p
60733.73/8805.61	% SZS status Started for HL403864+4.p
60733.73/8805.61	% SZS status GaveUp for HL403864+4.p
60733.73/8805.61	eprover: CPU time limit exceeded, terminating
60733.73/8805.61	% SZS status Ended for HL403864+4.p
60739.36/8806.15	% SZS status Started for HL403867+5.p
60739.36/8806.15	% SZS status GaveUp for HL403867+5.p
60739.36/8806.15	% SZS status Ended for HL403867+5.p
60779.78/8811.29	% SZS status Started for HL403865+4.p
60779.78/8811.29	% SZS status GaveUp for HL403865+4.p
60779.78/8811.29	eprover: CPU time limit exceeded, terminating
60779.78/8811.29	% SZS status Ended for HL403865+4.p
60784.00/8811.75	% SZS status Started for HL403868+5.p
60784.00/8811.75	% SZS status GaveUp for HL403868+5.p
60784.00/8811.75	% SZS status Ended for HL403868+5.p
60805.33/8814.42	% SZS status Started for HL403866+4.p
60805.33/8814.42	% SZS status GaveUp for HL403866+4.p
60805.33/8814.42	eprover: CPU time limit exceeded, terminating
60805.33/8814.42	% SZS status Ended for HL403866+4.p
60807.39/8814.77	% SZS status Started for HL403869+5.p
60807.39/8814.77	% SZS status GaveUp for HL403869+5.p
60807.39/8814.77	% SZS status Ended for HL403869+5.p
60852.05/8820.34	% SZS status Started for HL403870+5.p
60852.05/8820.34	% SZS status GaveUp for HL403870+5.p
60852.05/8820.34	% SZS status Ended for HL403870+5.p
60852.65/8820.46	% SZS status Started for HL403867+4.p
60852.65/8820.46	% SZS status GaveUp for HL403867+4.p
60852.65/8820.46	eprover: CPU time limit exceeded, terminating
60852.65/8820.46	% SZS status Ended for HL403867+4.p
60874.68/8823.20	% SZS status Started for HL403868+4.p
60874.68/8823.20	% SZS status GaveUp for HL403868+4.p
60874.68/8823.20	eprover: CPU time limit exceeded, terminating
60874.68/8823.20	% SZS status Ended for HL403868+4.p
60877.25/8823.44	% SZS status Started for HL403871+5.p
60877.25/8823.44	% SZS status GaveUp for HL403871+5.p
60877.25/8823.44	% SZS status Ended for HL403871+5.p
60922.14/8829.16	% SZS status Started for HL403869+4.p
60922.14/8829.16	% SZS status GaveUp for HL403869+4.p
60922.14/8829.16	eprover: CPU time limit exceeded, terminating
60922.14/8829.16	% SZS status Ended for HL403869+4.p
60924.82/8829.49	% SZS status Started for HL403872+5.p
60924.82/8829.49	% SZS status GaveUp for HL403872+5.p
60924.82/8829.49	% SZS status Ended for HL403872+5.p
60940.10/8831.38	% SZS status Started for HL403870+4.p
60940.10/8831.38	% SZS status GaveUp for HL403870+4.p
60940.10/8831.38	eprover: CPU time limit exceeded, terminating
60940.10/8831.38	% SZS status Ended for HL403870+4.p
60947.36/8832.33	% SZS status Started for HL403873+5.p
60947.36/8832.33	% SZS status GaveUp for HL403873+5.p
60947.36/8832.33	% SZS status Ended for HL403873+5.p
60971.90/8835.35	% SZS status Started for HL403874+5.p
60971.90/8835.35	% SZS status Theorem for HL403874+5.p
60971.90/8835.35	% SZS status Ended for HL403874+5.p
60984.61/8837.01	% SZS status Started for HL403871+4.p
60984.61/8837.01	% SZS status GaveUp for HL403871+4.p
60984.61/8837.01	eprover: CPU time limit exceeded, terminating
60984.61/8837.01	% SZS status Ended for HL403871+4.p
61007.30/8839.82	% SZS status Started for HL403872+4.p
61007.30/8839.82	% SZS status GaveUp for HL403872+4.p
61007.30/8839.82	eprover: CPU time limit exceeded, terminating
61007.30/8839.82	% SZS status Ended for HL403872+4.p
61013.12/8840.62	% SZS status Started for HL403875+5.p
61013.12/8840.62	% SZS status GaveUp for HL403875+5.p
61013.12/8840.62	% SZS status Ended for HL403875+5.p
61045.00/8844.53	% SZS status Started for HL403877+5.p
61045.00/8844.53	% SZS status GaveUp for HL403877+5.p
61045.00/8844.53	% SZS status Ended for HL403877+5.p
61052.19/8845.50	% SZS status Started for HL403873+4.p
61052.19/8845.50	% SZS status GaveUp for HL403873+4.p
61052.19/8845.50	eprover: CPU time limit exceeded, terminating
61052.19/8845.50	% SZS status Ended for HL403873+4.p
61076.35/8848.48	% SZS status Started for HL403874+4.p
61076.35/8848.48	% SZS status GaveUp for HL403874+4.p
61076.35/8848.48	eprover: CPU time limit exceeded, terminating
61076.35/8848.48	% SZS status Ended for HL403874+4.p
61079.77/8848.90	% SZS status Started for HL403878+5.p
61079.77/8848.90	% SZS status GaveUp for HL403878+5.p
61079.77/8848.90	% SZS status Ended for HL403878+5.p
61117.84/8853.72	% SZS status Started for HL403879+5.p
61117.84/8853.72	% SZS status GaveUp for HL403879+5.p
61117.84/8853.72	% SZS status Ended for HL403879+5.p
61126.15/8854.85	% SZS status Started for HL403875+4.p
61126.15/8854.85	% SZS status GaveUp for HL403875+4.p
61126.15/8854.85	eprover: CPU time limit exceeded, terminating
61126.15/8854.85	% SZS status Ended for HL403875+4.p
61147.89/8857.52	% SZS status Started for HL403880+5.p
61147.89/8857.52	% SZS status GaveUp for HL403880+5.p
61147.89/8857.52	% SZS status Ended for HL403880+5.p
61148.73/8857.59	% SZS status Started for HL403877+4.p
61148.73/8857.59	% SZS status GaveUp for HL403877+4.p
61148.73/8857.59	eprover: CPU time limit exceeded, terminating
61148.73/8857.59	% SZS status Ended for HL403877+4.p
61183.07/8862.06	% SZS status Started for HL403878+4.p
61183.07/8862.06	% SZS status GaveUp for HL403878+4.p
61183.07/8862.06	eprover: CPU time limit exceeded, terminating
61183.07/8862.06	% SZS status Ended for HL403878+4.p
61190.68/8862.90	% SZS status Started for HL403881+5.p
61190.68/8862.90	% SZS status GaveUp for HL403881+5.p
61190.68/8862.90	% SZS status Ended for HL403881+5.p
61214.17/8865.81	% SZS status Started for HL403879+4.p
61214.17/8865.81	% SZS status GaveUp for HL403879+4.p
61214.17/8865.81	eprover: CPU time limit exceeded, terminating
61214.17/8865.81	% SZS status Ended for HL403879+4.p
61221.60/8866.74	% SZS status Started for HL403882+5.p
61221.60/8866.74	% SZS status GaveUp for HL403882+5.p
61221.60/8866.74	% SZS status Ended for HL403882+5.p
61252.62/8870.65	% SZS status Started for HL403880+4.p
61252.62/8870.65	% SZS status GaveUp for HL403880+4.p
61252.62/8870.65	eprover: CPU time limit exceeded, terminating
61252.62/8870.65	% SZS status Ended for HL403880+4.p
61256.67/8871.15	% SZS status Started for HL403883+5.p
61256.67/8871.15	% SZS status GaveUp for HL403883+5.p
61256.67/8871.15	% SZS status Ended for HL403883+5.p
61279.41/8874.10	% SZS status Started for HL403881+4.p
61279.41/8874.10	% SZS status GaveUp for HL403881+4.p
61279.41/8874.10	eprover: CPU time limit exceeded, terminating
61279.41/8874.10	% SZS status Ended for HL403881+4.p
61287.26/8874.98	% SZS status Started for HL403884+5.p
61287.26/8874.98	% SZS status GaveUp for HL403884+5.p
61287.26/8874.98	% SZS status Ended for HL403884+5.p
61325.55/8879.81	% SZS status Started for HL403885+5.p
61325.55/8879.81	% SZS status GaveUp for HL403885+5.p
61325.55/8879.81	% SZS status Ended for HL403885+5.p
61327.22/8880.15	% SZS status Started for HL403882+4.p
61327.22/8880.15	% SZS status GaveUp for HL403882+4.p
61327.22/8880.15	eprover: CPU time limit exceeded, terminating
61327.22/8880.15	% SZS status Ended for HL403882+4.p
61348.24/8882.68	% SZS status Started for HL403883+4.p
61348.24/8882.68	% SZS status GaveUp for HL403883+4.p
61348.24/8882.68	eprover: CPU time limit exceeded, terminating
61348.24/8882.68	% SZS status Ended for HL403883+4.p
61352.68/8883.22	% SZS status Started for HL403886+5.p
61352.68/8883.22	% SZS status GaveUp for HL403886+5.p
61352.68/8883.22	% SZS status Ended for HL403886+5.p
61393.53/8888.44	% SZS status Started for HL403884+4.p
61393.53/8888.44	% SZS status GaveUp for HL403884+4.p
61393.53/8888.44	eprover: CPU time limit exceeded, terminating
61393.53/8888.44	% SZS status Ended for HL403884+4.p
61397.86/8888.90	% SZS status Started for HL403887+5.p
61397.86/8888.90	% SZS status GaveUp for HL403887+5.p
61397.86/8888.90	% SZS status Ended for HL403887+5.p
61422.01/8891.91	% SZS status Started for HL403885+4.p
61422.01/8891.91	% SZS status GaveUp for HL403885+4.p
61422.01/8891.91	eprover: CPU time limit exceeded, terminating
61422.01/8891.91	% SZS status Ended for HL403885+4.p
61422.01/8891.92	% SZS status Started for HL403888+5.p
61422.01/8891.92	% SZS status GaveUp for HL403888+5.p
61422.01/8891.92	% SZS status Ended for HL403888+5.p
61456.80/8896.28	% SZS status Started for HL403886+4.p
61456.80/8896.28	% SZS status GaveUp for HL403886+4.p
61456.80/8896.28	eprover: CPU time limit exceeded, terminating
61456.80/8896.28	% SZS status Ended for HL403886+4.p
61465.63/8897.51	% SZS status Started for HL403889+5.p
61465.63/8897.51	% SZS status GaveUp for HL403889+5.p
61465.63/8897.51	% SZS status Ended for HL403889+5.p
61487.85/8900.25	% SZS status Started for HL403887+4.p
61487.85/8900.25	% SZS status GaveUp for HL403887+4.p
61487.85/8900.25	eprover: CPU time limit exceeded, terminating
61487.85/8900.25	% SZS status Ended for HL403887+4.p
61494.50/8901.03	% SZS status Started for HL403890+5.p
61494.50/8901.03	% SZS status GaveUp for HL403890+5.p
61494.50/8901.03	% SZS status Ended for HL403890+5.p
61528.00/8905.32	% SZS status Started for HL403893+5.p
61528.00/8905.32	% SZS status GaveUp for HL403893+5.p
61528.00/8905.32	% SZS status Ended for HL403893+5.p
61528.00/8905.33	% SZS status Started for HL403888+4.p
61528.00/8905.33	% SZS status GaveUp for HL403888+4.p
61528.00/8905.33	eprover: CPU time limit exceeded, terminating
61528.00/8905.33	% SZS status Ended for HL403888+4.p
61553.18/8908.40	% SZS status Started for HL403889+4.p
61553.18/8908.40	% SZS status GaveUp for HL403889+4.p
61553.18/8908.40	eprover: CPU time limit exceeded, terminating
61553.18/8908.40	% SZS status Ended for HL403889+4.p
61560.51/8909.36	% SZS status Started for HL403894+5.p
61560.51/8909.36	% SZS status GaveUp for HL403894+5.p
61560.51/8909.36	% SZS status Ended for HL403894+5.p
61597.34/8914.01	% SZS status Started for HL403890+4.p
61597.34/8914.01	% SZS status GaveUp for HL403890+4.p
61597.34/8914.01	eprover: CPU time limit exceeded, terminating
61597.34/8914.01	% SZS status Ended for HL403890+4.p
61600.02/8914.45	% SZS status Started for HL403895+5.p
61600.02/8914.45	% SZS status GaveUp for HL403895+5.p
61600.02/8914.45	% SZS status Ended for HL403895+5.p
61621.58/8917.00	% SZS status Started for HL403893+4.p
61621.58/8917.00	% SZS status GaveUp for HL403893+4.p
61621.58/8917.00	eprover: CPU time limit exceeded, terminating
61621.58/8917.00	% SZS status Ended for HL403893+4.p
61625.17/8917.44	% SZS status Started for HL403896+5.p
61625.17/8917.44	% SZS status GaveUp for HL403896+5.p
61625.17/8917.44	% SZS status Ended for HL403896+5.p
61667.35/8922.72	% SZS status Started for HL403894+4.p
61667.35/8922.72	% SZS status GaveUp for HL403894+4.p
61667.35/8922.72	eprover: CPU time limit exceeded, terminating
61667.35/8922.72	% SZS status Ended for HL403894+4.p
61670.29/8923.14	% SZS status Started for HL403897+5.p
61670.29/8923.14	% SZS status GaveUp for HL403897+5.p
61670.29/8923.14	% SZS status Ended for HL403897+5.p
61694.44/8926.12	% SZS status Started for HL403898+5.p
61694.44/8926.12	% SZS status GaveUp for HL403898+5.p
61694.44/8926.12	% SZS status Ended for HL403898+5.p
61694.87/8926.19	% SZS status Started for HL403895+4.p
61694.87/8926.19	% SZS status GaveUp for HL403895+4.p
61694.87/8926.19	eprover: CPU time limit exceeded, terminating
61694.87/8926.19	% SZS status Ended for HL403895+4.p
61721.46/8929.52	% SZS status Started for HL403899+5.p
61721.46/8929.52	% SZS status Theorem for HL403899+5.p
61721.46/8929.52	% SZS status Ended for HL403899+5.p
61729.97/8930.61	% SZS status Started for HL403896+4.p
61729.97/8930.61	% SZS status GaveUp for HL403896+4.p
61729.97/8930.61	eprover: CPU time limit exceeded, terminating
61729.97/8930.61	% SZS status Ended for HL403896+4.p
61760.18/8934.44	% SZS status Started for HL403897+4.p
61760.18/8934.44	% SZS status GaveUp for HL403897+4.p
61760.18/8934.44	eprover: CPU time limit exceeded, terminating
61760.18/8934.44	% SZS status Ended for HL403897+4.p
61764.55/8935.21	% SZS status Started for HL403900+5.p
61764.55/8935.21	% SZS status GaveUp for HL403900+5.p
61764.55/8935.21	% SZS status Ended for HL403900+5.p
61793.21/8938.61	% SZS status Started for HL403901+5.p
61793.21/8938.61	% SZS status GaveUp for HL403901+5.p
61793.21/8938.61	% SZS status Ended for HL403901+5.p
61801.71/8939.72	% SZS status Started for HL403898+4.p
61801.71/8939.72	% SZS status GaveUp for HL403898+4.p
61801.71/8939.72	eprover: CPU time limit exceeded, terminating
61801.71/8939.72	% SZS status Ended for HL403898+4.p
61824.48/8942.53	% SZS status Started for HL403899+4.p
61824.48/8942.53	% SZS status GaveUp for HL403899+4.p
61824.48/8942.53	eprover: CPU time limit exceeded, terminating
61824.48/8942.53	% SZS status Ended for HL403899+4.p
61833.33/8943.62	% SZS status Started for HL403902+5.p
61833.33/8943.62	% SZS status GaveUp for HL403902+5.p
61833.33/8943.62	% SZS status Ended for HL403902+5.p
61864.05/8947.51	% SZS status Started for HL403903+5.p
61864.05/8947.51	% SZS status GaveUp for HL403903+5.p
61864.05/8947.51	% SZS status Ended for HL403903+5.p
61870.64/8948.33	% SZS status Started for HL403900+4.p
61870.64/8948.33	% SZS status GaveUp for HL403900+4.p
61870.64/8948.33	eprover: CPU time limit exceeded, terminating
61870.64/8948.33	% SZS status Ended for HL403900+4.p
61894.80/8951.36	% SZS status Started for HL403905+5.p
61894.80/8951.36	% SZS status GaveUp for HL403905+5.p
61894.80/8951.36	% SZS status Ended for HL403905+5.p
61895.32/8951.39	% SZS status Started for HL403901+4.p
61895.32/8951.39	% SZS status GaveUp for HL403901+4.p
61895.32/8951.39	eprover: CPU time limit exceeded, terminating
61895.32/8951.39	% SZS status Ended for HL403901+4.p
61930.51/8955.80	% SZS status Started for HL403902+4.p
61930.51/8955.80	% SZS status GaveUp for HL403902+4.p
61930.51/8955.80	eprover: CPU time limit exceeded, terminating
61930.51/8955.80	% SZS status Ended for HL403902+4.p
61933.49/8956.34	% SZS status Started for HL403906+5.p
61933.49/8956.34	% SZS status GaveUp for HL403906+5.p
61933.49/8956.34	% SZS status Ended for HL403906+5.p
61965.45/8960.27	% SZS status Started for HL403903+4.p
61965.45/8960.27	% SZS status GaveUp for HL403903+4.p
61965.45/8960.27	eprover: CPU time limit exceeded, terminating
61965.45/8960.27	% SZS status Ended for HL403903+4.p
61969.12/8960.37	% SZS status Started for HL403908+5.p
61969.12/8960.37	% SZS status GaveUp for HL403908+5.p
61969.12/8960.37	% SZS status Ended for HL403908+5.p
62005.49/8964.92	% SZS status Started for HL403909+5.p
62005.49/8964.92	% SZS status GaveUp for HL403909+5.p
62005.49/8964.92	% SZS status Ended for HL403909+5.p
62005.73/8964.99	% SZS status Started for HL403905+4.p
62005.73/8964.99	% SZS status GaveUp for HL403905+4.p
62005.73/8964.99	eprover: CPU time limit exceeded, terminating
62005.73/8964.99	% SZS status Ended for HL403905+4.p
62037.29/8969.00	% SZS status Started for HL403906+4.p
62037.29/8969.00	% SZS status GaveUp for HL403906+4.p
62037.29/8969.00	eprover: CPU time limit exceeded, terminating
62037.29/8969.00	% SZS status Ended for HL403906+4.p
62041.14/8969.44	% SZS status Started for HL403910+5.p
62041.14/8969.44	% SZS status GaveUp for HL403910+5.p
62041.14/8969.44	% SZS status Ended for HL403910+5.p
62072.92/8973.43	% SZS status Started for HL403908+4.p
62072.92/8973.43	% SZS status GaveUp for HL403908+4.p
62072.92/8973.43	eprover: CPU time limit exceeded, terminating
62072.92/8973.43	% SZS status Ended for HL403908+4.p
62077.24/8973.96	% SZS status Started for HL403911+5.p
62077.24/8973.96	% SZS status GaveUp for HL403911+5.p
62077.24/8973.96	% SZS status Ended for HL403911+5.p
62097.92/8976.61	% SZS status Started for HL403909+4.p
62097.92/8976.61	% SZS status GaveUp for HL403909+4.p
62097.92/8976.61	eprover: CPU time limit exceeded, terminating
62097.92/8976.61	% SZS status Ended for HL403909+4.p
62109.62/8978.04	% SZS status Started for HL403912+5.p
62109.62/8978.04	% SZS status GaveUp for HL403912+5.p
62109.62/8978.04	% SZS status Ended for HL403912+5.p
62137.29/8981.53	% SZS status Started for HL403910+4.p
62137.29/8981.53	% SZS status GaveUp for HL403910+4.p
62137.29/8981.53	eprover: CPU time limit exceeded, terminating
62137.29/8981.53	% SZS status Ended for HL403910+4.p
62145.70/8982.55	% SZS status Started for HL403913+5.p
62145.70/8982.55	% SZS status GaveUp for HL403913+5.p
62145.70/8982.55	% SZS status Ended for HL403913+5.p
62169.98/8985.65	% SZS status Started for HL403911+4.p
62169.98/8985.65	% SZS status GaveUp for HL403911+4.p
62169.98/8985.65	eprover: CPU time limit exceeded, terminating
62169.98/8985.65	% SZS status Ended for HL403911+4.p
62169.98/8985.68	% SZS status Started for HL403914+5.p
62169.98/8985.68	% SZS status GaveUp for HL403914+5.p
62169.98/8985.68	% SZS status Ended for HL403914+5.p
62205.31/8990.07	% SZS status Started for HL403912+4.p
62205.31/8990.07	% SZS status GaveUp for HL403912+4.p
62205.31/8990.07	eprover: CPU time limit exceeded, terminating
62205.31/8990.07	% SZS status Ended for HL403912+4.p
62210.18/8990.65	% SZS status Started for HL403915+5.p
62210.18/8990.65	% SZS status GaveUp for HL403915+5.p
62210.18/8990.65	% SZS status Ended for HL403915+5.p
62242.25/8994.71	% SZS status Started for HL403913+4.p
62242.25/8994.71	% SZS status GaveUp for HL403913+4.p
62242.25/8994.71	eprover: CPU time limit exceeded, terminating
62242.25/8994.71	% SZS status Ended for HL403913+4.p
62242.25/8994.72	% SZS status Started for HL403916+5.p
62242.25/8994.72	% SZS status GaveUp for HL403916+5.p
62242.25/8994.72	% SZS status Ended for HL403916+5.p
62276.67/8999.12	% SZS status Started for HL403914+4.p
62276.67/8999.12	% SZS status GaveUp for HL403914+4.p
62276.67/8999.12	eprover: CPU time limit exceeded, terminating
62276.67/8999.12	% SZS status Ended for HL403914+4.p
62277.07/8999.14	% SZS status Started for HL403917+5.p
62277.07/8999.14	% SZS status GaveUp for HL403917+5.p
62277.07/8999.14	% SZS status Ended for HL403917+5.p
62308.86/9003.12	% SZS status Started for HL403915+4.p
62308.86/9003.12	% SZS status GaveUp for HL403915+4.p
62308.86/9003.12	eprover: CPU time limit exceeded, terminating
62308.86/9003.12	% SZS status Ended for HL403915+4.p
62314.46/9003.78	% SZS status Started for HL403918+5.p
62314.46/9003.78	% SZS status GaveUp for HL403918+5.p
62314.46/9003.78	% SZS status Ended for HL403918+5.p
62345.63/9007.70	% SZS status Started for HL403916+4.p
62345.63/9007.70	% SZS status GaveUp for HL403916+4.p
62345.63/9007.70	eprover: CPU time limit exceeded, terminating
62345.63/9007.70	% SZS status Ended for HL403916+4.p
62348.49/9008.15	% SZS status Started for HL403919+5.p
62348.49/9008.15	% SZS status GaveUp for HL403919+5.p
62348.49/9008.15	% SZS status Ended for HL403919+5.p
62370.33/9010.79	% SZS status Started for HL403917+4.p
62370.33/9010.79	% SZS status GaveUp for HL403917+4.p
62370.33/9010.79	eprover: CPU time limit exceeded, terminating
62370.33/9010.79	% SZS status Ended for HL403917+4.p
62383.08/9012.36	% SZS status Started for HL403920+5.p
62383.08/9012.36	% SZS status GaveUp for HL403920+5.p
62383.08/9012.36	% SZS status Ended for HL403920+5.p
62410.56/9015.85	% SZS status Started for HL403918+4.p
62410.56/9015.85	% SZS status GaveUp for HL403918+4.p
62410.56/9015.85	eprover: CPU time limit exceeded, terminating
62410.56/9015.85	% SZS status Ended for HL403918+4.p
62417.89/9016.79	% SZS status Started for HL403921+5.p
62417.89/9016.79	% SZS status GaveUp for HL403921+5.p
62417.89/9016.79	% SZS status Ended for HL403921+5.p
62442.37/9019.82	% SZS status Started for HL403922+5.p
62442.37/9019.82	% SZS status GaveUp for HL403922+5.p
62442.37/9019.82	% SZS status Ended for HL403922+5.p
62442.54/9019.84	% SZS status Started for HL403919+4.p
62442.54/9019.84	% SZS status GaveUp for HL403919+4.p
62442.54/9019.84	eprover: CPU time limit exceeded, terminating
62442.54/9019.84	% SZS status Ended for HL403919+4.p
62476.95/9024.29	% SZS status Started for HL403920+4.p
62476.95/9024.29	% SZS status GaveUp for HL403920+4.p
62476.95/9024.29	eprover: CPU time limit exceeded, terminating
62476.95/9024.29	% SZS status Ended for HL403920+4.p
62483.72/9025.04	% SZS status Started for HL403923+5.p
62483.72/9025.04	% SZS status GaveUp for HL403923+5.p
62483.72/9025.04	% SZS status Ended for HL403923+5.p
62493.12/9026.32	% SZS status Started for HL403924+5.p
62493.12/9026.32	% SZS status Theorem for HL403924+5.p
62493.12/9026.32	% SZS status Ended for HL403924+5.p
62515.78/9029.05	% SZS status Started for HL403921+4.p
62515.78/9029.05	% SZS status GaveUp for HL403921+4.p
62515.78/9029.05	eprover: CPU time limit exceeded, terminating
62515.78/9029.05	% SZS status Ended for HL403921+4.p
62549.58/9033.31	% SZS status Started for HL403922+4.p
62549.58/9033.31	% SZS status GaveUp for HL403922+4.p
62549.58/9033.31	eprover: CPU time limit exceeded, terminating
62549.58/9033.31	% SZS status Ended for HL403922+4.p
62549.97/9033.42	% SZS status Started for HL403926+5.p
62549.97/9033.42	% SZS status GaveUp for HL403926+5.p
62549.97/9033.42	% SZS status Ended for HL403926+5.p
62564.32/9035.16	% SZS status Started for HL403927+5.p
62564.32/9035.16	% SZS status GaveUp for HL403927+5.p
62564.32/9035.16	% SZS status Ended for HL403927+5.p
62582.81/9037.51	% SZS status Started for HL403923+4.p
62582.81/9037.51	% SZS status GaveUp for HL403923+4.p
62582.81/9037.51	eprover: CPU time limit exceeded, terminating
62582.81/9037.51	% SZS status Ended for HL403923+4.p
62618.81/9042.00	% SZS status Started for HL403924+4.p
62618.81/9042.00	% SZS status GaveUp for HL403924+4.p
62618.81/9042.00	eprover: CPU time limit exceeded, terminating
62618.81/9042.00	% SZS status Ended for HL403924+4.p
62622.36/9042.48	% SZS status Started for HL403928+5.p
62622.36/9042.48	% SZS status GaveUp for HL403928+5.p
62622.36/9042.48	% SZS status Ended for HL403928+5.p
62635.82/9044.20	% SZS status Started for HL403929+5.p
62635.82/9044.20	% SZS status GaveUp for HL403929+5.p
62635.82/9044.20	% SZS status Ended for HL403929+5.p
62643.53/9045.23	% SZS status Started for HL403926+4.p
62643.53/9045.23	% SZS status GaveUp for HL403926+4.p
62643.53/9045.23	eprover: CPU time limit exceeded, terminating
62643.53/9045.23	% SZS status Ended for HL403926+4.p
62683.80/9050.19	% SZS status Started for HL403927+4.p
62683.80/9050.19	% SZS status GaveUp for HL403927+4.p
62683.80/9050.19	eprover: CPU time limit exceeded, terminating
62683.80/9050.19	% SZS status Ended for HL403927+4.p
62690.93/9051.09	% SZS status Started for HL403930+5.p
62690.93/9051.09	% SZS status GaveUp for HL403930+5.p
62690.93/9051.09	% SZS status Ended for HL403930+5.p
62708.66/9053.28	% SZS status Started for HL403931+5.p
62708.66/9053.28	% SZS status GaveUp for HL403931+5.p
62708.66/9053.28	% SZS status Ended for HL403931+5.p
62716.70/9054.33	% SZS status Started for HL403928+4.p
62716.70/9054.33	% SZS status GaveUp for HL403928+4.p
62716.70/9054.33	eprover: CPU time limit exceeded, terminating
62716.70/9054.33	% SZS status Ended for HL403928+4.p
62749.76/9058.47	% SZS status Started for HL403929+4.p
62749.76/9058.47	% SZS status GaveUp for HL403929+4.p
62749.76/9058.47	eprover: CPU time limit exceeded, terminating
62749.76/9058.47	% SZS status Ended for HL403929+4.p
62757.19/9059.40	% SZS status Started for HL403932+5.p
62757.19/9059.40	% SZS status GaveUp for HL403932+5.p
62757.19/9059.40	% SZS status Ended for HL403932+5.p
62781.22/9062.39	% SZS status Started for HL403933+5.p
62781.22/9062.39	% SZS status GaveUp for HL403933+5.p
62781.22/9062.39	% SZS status Ended for HL403933+5.p
62782.27/9062.58	% SZS status Started for HL403930+4.p
62782.27/9062.58	% SZS status GaveUp for HL403930+4.p
62782.27/9062.58	eprover: CPU time limit exceeded, terminating
62782.27/9062.58	% SZS status Ended for HL403930+4.p
62821.98/9067.56	% SZS status Started for HL403931+4.p
62821.98/9067.56	% SZS status GaveUp for HL403931+4.p
62821.98/9067.56	eprover: CPU time limit exceeded, terminating
62821.98/9067.56	% SZS status Ended for HL403931+4.p
62821.98/9067.61	% SZS status Started for HL403934+5.p
62821.98/9067.61	% SZS status GaveUp for HL403934+5.p
62821.98/9067.61	% SZS status Ended for HL403934+5.p
62844.76/9070.43	% SZS status Started for HL403932+4.p
62844.76/9070.43	% SZS status GaveUp for HL403932+4.p
62844.76/9070.43	eprover: CPU time limit exceeded, terminating
62844.76/9070.43	% SZS status Ended for HL403932+4.p
62853.47/9071.52	% SZS status Started for HL403935+5.p
62853.47/9071.52	% SZS status GaveUp for HL403935+5.p
62853.47/9071.52	% SZS status Ended for HL403935+5.p
62891.42/9076.29	% SZS status Started for HL403933+4.p
62891.42/9076.29	% SZS status GaveUp for HL403933+4.p
62891.42/9076.29	eprover: CPU time limit exceeded, terminating
62891.42/9076.29	% SZS status Ended for HL403933+4.p
62895.24/9076.75	% SZS status Started for HL403936+5.p
62895.24/9076.75	% SZS status GaveUp for HL403936+5.p
62895.24/9076.75	% SZS status Ended for HL403936+5.p
62917.58/9079.52	% SZS status Started for HL403937+5.p
62917.58/9079.52	% SZS status GaveUp for HL403937+5.p
62917.58/9079.52	% SZS status Ended for HL403937+5.p
62918.20/9079.63	% SZS status Started for HL403934+4.p
62918.20/9079.63	% SZS status GaveUp for HL403934+4.p
62918.20/9079.63	eprover: CPU time limit exceeded, terminating
62918.20/9079.63	% SZS status Ended for HL403934+4.p
62957.97/9084.68	% SZS status Started for HL403935+4.p
62957.97/9084.68	% SZS status GaveUp for HL403935+4.p
62957.97/9084.68	eprover: CPU time limit exceeded, terminating
62957.97/9084.68	% SZS status Ended for HL403935+4.p
62963.83/9085.31	% SZS status Started for HL403938+5.p
62963.83/9085.31	% SZS status GaveUp for HL403938+5.p
62963.83/9085.31	% SZS status Ended for HL403938+5.p
62982.12/9087.65	% SZS status Started for HL403936+4.p
62982.12/9087.65	% SZS status GaveUp for HL403936+4.p
62982.12/9087.65	eprover: CPU time limit exceeded, terminating
62982.12/9087.65	% SZS status Ended for HL403936+4.p
62989.58/9088.58	% SZS status Started for HL403940+5.p
62989.58/9088.58	% SZS status GaveUp for HL403940+5.p
62989.58/9088.58	% SZS status Ended for HL403940+5.p
63022.10/9092.72	% SZS status Started for HL403937+4.p
63022.10/9092.72	% SZS status GaveUp for HL403937+4.p
63022.10/9092.72	eprover: CPU time limit exceeded, terminating
63022.10/9092.72	% SZS status Ended for HL403937+4.p
63029.27/9093.56	% SZS status Started for HL403941+5.p
63029.27/9093.56	% SZS status GaveUp for HL403941+5.p
63029.27/9093.56	% SZS status Ended for HL403941+5.p
63052.68/9096.47	% SZS status Started for HL403942+5.p
63052.68/9096.47	% SZS status GaveUp for HL403942+5.p
63052.68/9096.47	% SZS status Ended for HL403942+5.p
63054.27/9096.73	% SZS status Started for HL403938+4.p
63054.27/9096.73	% SZS status GaveUp for HL403938+4.p
63054.27/9096.73	eprover: CPU time limit exceeded, terminating
63054.27/9096.73	% SZS status Ended for HL403938+4.p
63095.21/9101.86	% SZS status Started for HL403943+5.p
63095.21/9101.86	% SZS status GaveUp for HL403943+5.p
63095.21/9101.86	% SZS status Ended for HL403943+5.p
63095.63/9101.93	% SZS status Started for HL403940+4.p
63095.63/9101.93	% SZS status GaveUp for HL403940+4.p
63095.63/9101.93	eprover: CPU time limit exceeded, terminating
63095.63/9101.93	% SZS status Ended for HL403940+4.p
63118.21/9104.79	% SZS status Started for HL403941+4.p
63118.21/9104.79	% SZS status GaveUp for HL403941+4.p
63118.21/9104.79	eprover: CPU time limit exceeded, terminating
63118.21/9104.79	% SZS status Ended for HL403941+4.p
63122.65/9105.29	% SZS status Started for HL403944+5.p
63122.65/9105.29	% SZS status GaveUp for HL403944+5.p
63122.65/9105.29	% SZS status Ended for HL403944+5.p
63164.64/9110.56	% SZS status Started for HL403942+4.p
63164.64/9110.56	% SZS status GaveUp for HL403942+4.p
63164.64/9110.56	eprover: CPU time limit exceeded, terminating
63164.64/9110.56	% SZS status Ended for HL403942+4.p
63165.54/9110.69	% SZS status Started for HL403945+5.p
63165.54/9110.69	% SZS status GaveUp for HL403945+5.p
63165.54/9110.69	% SZS status Ended for HL403945+5.p
63189.48/9113.68	% SZS status Started for HL403946+5.p
63189.48/9113.68	% SZS status GaveUp for HL403946+5.p
63189.48/9113.68	% SZS status Ended for HL403946+5.p
63189.48/9113.70	% SZS status Started for HL403943+4.p
63189.48/9113.70	% SZS status GaveUp for HL403943+4.p
63189.48/9113.70	eprover: CPU time limit exceeded, terminating
63189.48/9113.70	% SZS status Ended for HL403943+4.p
63232.40/9119.06	% SZS status Started for HL403944+4.p
63232.40/9119.06	% SZS status GaveUp for HL403944+4.p
63232.40/9119.06	eprover: CPU time limit exceeded, terminating
63232.40/9119.06	% SZS status Ended for HL403944+4.p
63234.55/9119.39	% SZS status Started for HL403948+5.p
63234.55/9119.39	% SZS status GaveUp for HL403948+5.p
63234.55/9119.39	% SZS status Ended for HL403948+5.p
63254.73/9121.86	% SZS status Started for HL403945+4.p
63254.73/9121.86	% SZS status GaveUp for HL403945+4.p
63254.73/9121.86	eprover: CPU time limit exceeded, terminating
63254.73/9121.86	% SZS status Ended for HL403945+4.p
63261.80/9122.78	% SZS status Started for HL403949+5.p
63261.80/9122.78	% SZS status GaveUp for HL403949+5.p
63261.80/9122.78	% SZS status Ended for HL403949+5.p
63295.57/9127.14	% SZS status Started for HL403946+4.p
63295.57/9127.14	% SZS status GaveUp for HL403946+4.p
63295.57/9127.14	eprover: CPU time limit exceeded, terminating
63295.57/9127.14	% SZS status Ended for HL403946+4.p
63304.19/9128.11	% SZS status Started for HL403950+5.p
63304.19/9128.11	% SZS status GaveUp for HL403950+5.p
63304.19/9128.11	% SZS status Ended for HL403950+5.p
63323.30/9130.47	% SZS status Started for HL403948+4.p
63323.30/9130.47	% SZS status GaveUp for HL403948+4.p
63323.30/9130.47	eprover: CPU time limit exceeded, terminating
63323.30/9130.47	% SZS status Ended for HL403948+4.p
63327.99/9131.06	% SZS status Started for HL403951+5.p
63327.99/9131.06	% SZS status GaveUp for HL403951+5.p
63327.99/9131.06	% SZS status Ended for HL403951+5.p
63366.11/9135.84	% SZS status Started for HL403949+4.p
63366.11/9135.84	% SZS status GaveUp for HL403949+4.p
63366.11/9135.84	eprover: CPU time limit exceeded, terminating
63366.11/9135.84	% SZS status Ended for HL403949+4.p
63369.52/9136.31	% SZS status Started for HL403952+5.p
63369.52/9136.31	% SZS status GaveUp for HL403952+5.p
63369.52/9136.31	% SZS status Ended for HL403952+5.p
63390.16/9138.89	% SZS status Started for HL403950+4.p
63390.16/9138.89	% SZS status GaveUp for HL403950+4.p
63390.16/9138.89	eprover: CPU time limit exceeded, terminating
63390.16/9138.89	% SZS status Ended for HL403950+4.p
63395.88/9139.61	% SZS status Started for HL403953+5.p
63395.88/9139.61	% SZS status GaveUp for HL403953+5.p
63395.88/9139.61	% SZS status Ended for HL403953+5.p
63434.34/9144.48	% SZS status Started for HL403951+4.p
63434.34/9144.48	% SZS status GaveUp for HL403951+4.p
63434.34/9144.48	eprover: CPU time limit exceeded, terminating
63434.34/9144.48	% SZS status Ended for HL403951+4.p
63438.00/9144.90	% SZS status Started for HL403955+5.p
63438.00/9144.90	% SZS status GaveUp for HL403955+5.p
63438.00/9144.90	% SZS status Ended for HL403955+5.p
63462.53/9147.96	% SZS status Started for HL403956+5.p
63462.53/9147.96	% SZS status GaveUp for HL403956+5.p
63462.53/9147.96	% SZS status Ended for HL403956+5.p
63463.11/9148.05	% SZS status Started for HL403952+4.p
63463.11/9148.05	% SZS status GaveUp for HL403952+4.p
63463.11/9148.05	eprover: CPU time limit exceeded, terminating
63463.11/9148.05	% SZS status Ended for HL403952+4.p
63505.47/9153.39	% SZS status Started for HL403953+4.p
63505.47/9153.39	% SZS status GaveUp for HL403953+4.p
63505.47/9153.39	eprover: CPU time limit exceeded, terminating
63505.47/9153.39	% SZS status Ended for HL403953+4.p
63507.33/9153.59	% SZS status Started for HL403957+5.p
63507.33/9153.59	% SZS status GaveUp for HL403957+5.p
63507.33/9153.59	% SZS status Ended for HL403957+5.p
63528.44/9156.27	% SZS status Started for HL403955+4.p
63528.44/9156.27	% SZS status GaveUp for HL403955+4.p
63528.44/9156.27	eprover: CPU time limit exceeded, terminating
63528.44/9156.27	% SZS status Ended for HL403955+4.p
63534.95/9157.07	% SZS status Started for HL403958+5.p
63534.95/9157.07	% SZS status GaveUp for HL403958+5.p
63534.95/9157.07	% SZS status Ended for HL403958+5.p
63570.56/9161.65	% SZS status Started for HL403956+4.p
63570.56/9161.65	% SZS status GaveUp for HL403956+4.p
63570.56/9161.65	eprover: CPU time limit exceeded, terminating
63570.56/9161.65	% SZS status Ended for HL403956+4.p
63578.40/9162.55	% SZS status Started for HL403959+5.p
63578.40/9162.55	% SZS status GaveUp for HL403959+5.p
63578.40/9162.55	% SZS status Ended for HL403959+5.p
63595.96/9164.77	% SZS status Started for HL403957+4.p
63595.96/9164.77	% SZS status GaveUp for HL403957+4.p
63595.96/9164.77	eprover: CPU time limit exceeded, terminating
63595.96/9164.77	% SZS status Ended for HL403957+4.p
63600.97/9165.37	% SZS status Started for HL403960+5.p
63600.97/9165.37	% SZS status GaveUp for HL403960+5.p
63600.97/9165.37	% SZS status Ended for HL403960+5.p
63638.73/9170.14	% SZS status Started for HL403958+4.p
63638.73/9170.14	% SZS status GaveUp for HL403958+4.p
63638.73/9170.14	eprover: CPU time limit exceeded, terminating
63638.73/9170.14	% SZS status Ended for HL403958+4.p
63644.34/9170.81	% SZS status Started for HL403961+5.p
63644.34/9170.81	% SZS status GaveUp for HL403961+5.p
63644.34/9170.81	% SZS status Ended for HL403961+5.p
63662.82/9173.19	% SZS status Started for HL403959+4.p
63662.82/9173.19	% SZS status GaveUp for HL403959+4.p
63662.82/9173.19	eprover: CPU time limit exceeded, terminating
63662.82/9173.19	% SZS status Ended for HL403959+4.p
63668.69/9173.94	% SZS status Started for HL403962+5.p
63668.69/9173.94	% SZS status GaveUp for HL403962+5.p
63668.69/9173.94	% SZS status Ended for HL403962+5.p
63707.04/9178.75	% SZS status Started for HL403960+4.p
63707.04/9178.75	% SZS status GaveUp for HL403960+4.p
63707.04/9178.75	eprover: CPU time limit exceeded, terminating
63707.04/9178.75	% SZS status Ended for HL403960+4.p
63711.53/9179.31	% SZS status Started for HL403963+5.p
63711.53/9179.31	% SZS status GaveUp for HL403963+5.p
63711.53/9179.31	% SZS status Ended for HL403963+5.p
63734.80/9182.22	% SZS status Started for HL403961+4.p
63734.80/9182.22	% SZS status GaveUp for HL403961+4.p
63734.80/9182.22	eprover: CPU time limit exceeded, terminating
63734.80/9182.22	% SZS status Ended for HL403961+4.p
63735.42/9182.23	% SZS status Started for HL403964+5.p
63735.42/9182.23	% SZS status GaveUp for HL403964+5.p
63735.42/9182.23	% SZS status Ended for HL403964+5.p
63779.41/9187.77	% SZS status Started for HL403962+4.p
63779.41/9187.77	% SZS status GaveUp for HL403962+4.p
63779.41/9187.77	eprover: CPU time limit exceeded, terminating
63779.41/9187.77	% SZS status Ended for HL403962+4.p
63779.41/9187.82	% SZS status Started for HL403965+5.p
63779.41/9187.82	% SZS status GaveUp for HL403965+5.p
63779.41/9187.82	% SZS status Ended for HL403965+5.p
63802.21/9190.66	% SZS status Started for HL403963+4.p
63802.21/9190.66	% SZS status GaveUp for HL403963+4.p
63802.21/9190.66	eprover: CPU time limit exceeded, terminating
63802.21/9190.66	% SZS status Ended for HL403963+4.p
63807.27/9191.32	% SZS status Started for HL403966+5.p
63807.27/9191.32	% SZS status GaveUp for HL403966+5.p
63807.27/9191.32	% SZS status Ended for HL403966+5.p
63843.33/9196.14	% SZS status Started for HL403964+4.p
63843.33/9196.14	% SZS status GaveUp for HL403964+4.p
63843.33/9196.14	eprover: CPU time limit exceeded, terminating
63843.33/9196.14	% SZS status Ended for HL403964+4.p
63848.56/9197.02	% SZS status Started for HL403968+5.p
63848.56/9197.02	% SZS status GaveUp for HL403968+5.p
63848.56/9197.02	% SZS status Ended for HL403968+5.p
63867.36/9199.64	% SZS status Started for HL403965+4.p
63867.36/9199.64	% SZS status GaveUp for HL403965+4.p
63867.36/9199.64	eprover: CPU time limit exceeded, terminating
63867.36/9199.64	% SZS status Ended for HL403965+4.p
63879.86/9201.24	% SZS status Started for HL403969+5.p
63879.86/9201.24	% SZS status GaveUp for HL403969+5.p
63879.86/9201.24	% SZS status Ended for HL403969+5.p
63909.89/9205.00	% SZS status Started for HL403966+4.p
63909.89/9205.00	% SZS status GaveUp for HL403966+4.p
63909.89/9205.00	eprover: CPU time limit exceeded, terminating
63909.89/9205.00	% SZS status Ended for HL403966+4.p
63920.16/9206.31	% SZS status Started for HL403970+5.p
63920.16/9206.31	% SZS status GaveUp for HL403970+5.p
63920.16/9206.31	% SZS status Ended for HL403970+5.p
63940.23/9208.75	% SZS status Started for HL403971+5.p
63940.23/9208.75	% SZS status GaveUp for HL403971+5.p
63940.23/9208.75	% SZS status Ended for HL403971+5.p
63940.73/9208.82	% SZS status Started for HL403968+4.p
63940.73/9208.82	% SZS status GaveUp for HL403968+4.p
63940.73/9208.82	eprover: CPU time limit exceeded, terminating
63940.73/9208.82	% SZS status Ended for HL403968+4.p
63975.34/9213.23	% SZS status Started for HL403969+4.p
63975.34/9213.23	% SZS status GaveUp for HL403969+4.p
63975.34/9213.23	eprover: CPU time limit exceeded, terminating
63975.34/9213.23	% SZS status Ended for HL403969+4.p
63982.70/9214.15	% SZS status Started for HL403972+5.p
63982.70/9214.15	% SZS status GaveUp for HL403972+5.p
63982.70/9214.15	% SZS status Ended for HL403972+5.p
64008.18/9217.34	% SZS status Started for HL403970+4.p
64008.18/9217.34	% SZS status GaveUp for HL403970+4.p
64008.18/9217.34	eprover: CPU time limit exceeded, terminating
64008.18/9217.34	% SZS status Ended for HL403970+4.p
64012.33/9217.84	% SZS status Started for HL403973+5.p
64012.33/9217.84	% SZS status GaveUp for HL403973+5.p
64012.33/9217.84	% SZS status Ended for HL403973+5.p
64048.38/9222.38	% SZS status Started for HL403974+5.p
64048.38/9222.38	% SZS status GaveUp for HL403974+5.p
64048.38/9222.38	% SZS status Ended for HL403974+5.p
64053.06/9222.97	% SZS status Started for HL403971+4.p
64053.06/9222.97	% SZS status GaveUp for HL403971+4.p
64053.06/9222.97	eprover: CPU time limit exceeded, terminating
64053.06/9222.97	% SZS status Ended for HL403971+4.p
64080.64/9226.47	% SZS status Started for HL403975+5.p
64080.64/9226.47	% SZS status GaveUp for HL403975+5.p
64080.64/9226.47	% SZS status Ended for HL403975+5.p
64080.64/9226.50	% SZS status Started for HL403972+4.p
64080.64/9226.50	% SZS status GaveUp for HL403972+4.p
64080.64/9226.50	eprover: CPU time limit exceeded, terminating
64080.64/9226.50	% SZS status Ended for HL403972+4.p
64090.19/9227.68	% SZS status Started for HL403977+5.p
64090.19/9227.68	% SZS status Theorem for HL403977+5.p
64090.19/9227.68	% SZS status Ended for HL403977+5.p
64099.80/9228.88	% SZS status Started for HL403978+5.p
64099.80/9228.88	% SZS status Theorem for HL403978+5.p
64099.80/9228.88	% SZS status Ended for HL403978+5.p
64119.09/9231.31	% SZS status Started for HL403976+5.p
64119.09/9231.31	% SZS status GaveUp for HL403976+5.p
64119.09/9231.31	% SZS status Ended for HL403976+5.p
64119.86/9231.46	% SZS status Started for HL403973+4.p
64119.86/9231.46	% SZS status GaveUp for HL403973+4.p
64119.86/9231.46	eprover: CPU time limit exceeded, terminating
64119.86/9231.46	% SZS status Ended for HL403973+4.p
64141.04/9234.04	% SZS status Started for HL403974+4.p
64141.04/9234.04	% SZS status GaveUp for HL403974+4.p
64141.04/9234.04	eprover: CPU time limit exceeded, terminating
64141.04/9234.04	% SZS status Ended for HL403974+4.p
64150.75/9235.26	% SZS status Started for HL403980+5.p
64150.75/9235.26	% SZS status Theorem for HL403980+5.p
64150.75/9235.26	% SZS status Ended for HL403980+5.p
64159.76/9236.51	% SZS status Started for HL403979+5.p
64159.76/9236.51	% SZS status Theorem for HL403979+5.p
64159.76/9236.51	% SZS status Ended for HL403979+5.p
64184.71/9239.58	% SZS status Started for HL403975+4.p
64184.71/9239.58	% SZS status GaveUp for HL403975+4.p
64184.71/9239.58	eprover: CPU time limit exceeded, terminating
64184.71/9239.58	% SZS status Ended for HL403975+4.p
64203.32/9241.86	% SZS status Started for HL403981+5.p
64203.32/9241.86	% SZS status Theorem for HL403981+5.p
64203.32/9241.86	% SZS status Ended for HL403981+5.p
64212.42/9243.01	% SZS status Started for HL403976+4.p
64212.42/9243.01	% SZS status GaveUp for HL403976+4.p
64212.42/9243.01	eprover: CPU time limit exceeded, terminating
64212.42/9243.01	% SZS status Ended for HL403976+4.p
64243.55/9247.02	% SZS status Started for HL403982+5.p
64243.55/9247.02	% SZS status Theorem for HL403982+5.p
64243.55/9247.02	% SZS status Ended for HL403982+5.p
64254.35/9248.30	% SZS status Started for HL403977+4.p
64254.35/9248.30	% SZS status GaveUp for HL403977+4.p
64254.35/9248.30	eprover: CPU time limit exceeded, terminating
64254.35/9248.30	% SZS status Ended for HL403977+4.p
64281.09/9251.65	% SZS status Started for HL403978+4.p
64281.09/9251.65	% SZS status GaveUp for HL403978+4.p
64281.09/9251.65	eprover: CPU time limit exceeded, terminating
64281.09/9251.65	% SZS status Ended for HL403978+4.p
64299.41/9253.98	% SZS status Started for HL403984+5.p
64299.41/9253.98	% SZS status Theorem for HL403984+5.p
64299.41/9253.98	% SZS status Ended for HL403984+5.p
64300.26/9254.12	% SZS status Started for HL403979+4.p
64300.26/9254.12	% SZS status GaveUp for HL403979+4.p
64300.26/9254.12	eprover: CPU time limit exceeded, terminating
64300.26/9254.12	% SZS status Ended for HL403979+4.p
64315.02/9255.91	% SZS status Started for HL403983+5.p
64315.02/9255.91	% SZS status GaveUp for HL403983+5.p
64315.02/9255.91	% SZS status Ended for HL403983+5.p
64321.77/9256.83	% SZS status Started for HL403980+4.p
64321.77/9256.83	% SZS status GaveUp for HL403980+4.p
64321.77/9256.83	eprover: CPU time limit exceeded, terminating
64321.77/9256.83	% SZS status Ended for HL403980+4.p
64350.23/9260.38	% SZS status Started for HL403981+4.p
64350.23/9260.38	% SZS status GaveUp for HL403981+4.p
64350.23/9260.38	eprover: CPU time limit exceeded, terminating
64350.23/9260.38	% SZS status Ended for HL403981+4.p
64372.95/9263.24	% SZS status Started for HL403985+5.p
64372.95/9263.24	% SZS status GaveUp for HL403985+5.p
64372.95/9263.24	% SZS status Ended for HL403985+5.p
64386.90/9264.94	% SZS status Started for HL403982+4.p
64386.90/9264.94	% SZS status GaveUp for HL403982+4.p
64386.90/9264.94	eprover: CPU time limit exceeded, terminating
64386.90/9264.94	% SZS status Ended for HL403982+4.p
64392.03/9265.66	% SZS status Started for HL403986+5.p
64392.03/9265.66	% SZS status GaveUp for HL403986+5.p
64392.03/9265.66	% SZS status Ended for HL403986+5.p
64413.18/9268.32	% SZS status Started for HL403983+4.p
64413.18/9268.32	% SZS status GaveUp for HL403983+4.p
64413.18/9268.32	eprover: CPU time limit exceeded, terminating
64413.18/9268.32	% SZS status Ended for HL403983+4.p
64445.50/9272.38	% SZS status Started for HL403987+5.p
64445.50/9272.38	% SZS status GaveUp for HL403987+5.p
64445.50/9272.38	% SZS status Ended for HL403987+5.p
64455.06/9273.54	% SZS status Started for HL403984+4.p
64455.06/9273.54	% SZS status GaveUp for HL403984+4.p
64455.06/9273.54	eprover: CPU time limit exceeded, terminating
64455.06/9273.54	% SZS status Ended for HL403984+4.p
64464.61/9274.78	% SZS status Started for HL403988+5.p
64464.61/9274.78	% SZS status GaveUp for HL403988+5.p
64464.61/9274.78	% SZS status Ended for HL403988+5.p
64502.82/9279.57	% SZS status Started for HL403985+4.p
64502.82/9279.57	% SZS status GaveUp for HL403985+4.p
64502.82/9279.57	eprover: CPU time limit exceeded, terminating
64502.82/9279.57	% SZS status Ended for HL403985+4.p
64514.73/9281.24	% SZS status Started for HL403989+5.p
64514.73/9281.24	% SZS status GaveUp for HL403989+5.p
64514.73/9281.24	% SZS status Ended for HL403989+5.p
64516.24/9281.24	% SZS status Started for HL403986+4.p
64516.24/9281.24	% SZS status GaveUp for HL403986+4.p
64516.24/9281.24	eprover: CPU time limit exceeded, terminating
64516.24/9281.24	% SZS status Ended for HL403986+4.p
64536.95/9283.92	% SZS status Started for HL403991+5.p
64536.95/9283.92	% SZS status GaveUp for HL403991+5.p
64536.95/9283.92	% SZS status Ended for HL403991+5.p
64550.58/9285.56	% SZS status Started for HL403987+4.p
64550.58/9285.56	% SZS status GaveUp for HL403987+4.p
64550.58/9285.56	eprover: CPU time limit exceeded, terminating
64550.58/9285.56	% SZS status Ended for HL403987+4.p
64586.70/9290.15	% SZS status Started for HL403992+5.p
64586.70/9290.15	% SZS status GaveUp for HL403992+5.p
64586.70/9290.15	% SZS status Ended for HL403992+5.p
64587.44/9290.24	% SZS status Started for HL403988+4.p
64587.44/9290.24	% SZS status GaveUp for HL403988+4.p
64587.44/9290.24	eprover: CPU time limit exceeded, terminating
64587.44/9290.24	% SZS status Ended for HL403988+4.p
64610.38/9293.15	% SZS status Started for HL403993+5.p
64610.38/9293.15	% SZS status GaveUp for HL403993+5.p
64610.38/9293.15	% SZS status Ended for HL403993+5.p
64614.52/9293.60	% SZS status Started for HL403989+4.p
64614.52/9293.60	% SZS status GaveUp for HL403989+4.p
64614.52/9293.60	eprover: CPU time limit exceeded, terminating
64614.52/9293.60	% SZS status Ended for HL403989+4.p
64658.23/9298.86	% SZS status Started for HL403991+4.p
64658.23/9298.86	% SZS status GaveUp for HL403991+4.p
64658.23/9298.86	eprover: CPU time limit exceeded, terminating
64658.23/9298.86	% SZS status Ended for HL403991+4.p
64658.84/9298.97	% SZS status Started for HL403995+5.p
64658.84/9298.97	% SZS status GaveUp for HL403995+5.p
64658.84/9298.97	% SZS status Ended for HL403995+5.p
64683.80/9302.22	% SZS status Started for HL403996+5.p
64683.80/9302.22	% SZS status GaveUp for HL403996+5.p
64683.80/9302.22	% SZS status Ended for HL403996+5.p
64705.52/9304.79	% SZS status Started for HL403992+4.p
64705.52/9304.79	% SZS status GaveUp for HL403992+4.p
64705.52/9304.79	eprover: CPU time limit exceeded, terminating
64705.52/9304.79	% SZS status Ended for HL403992+4.p
64720.90/9306.81	% SZS status Started for HL403993+4.p
64720.90/9306.81	% SZS status GaveUp for HL403993+4.p
64720.90/9306.81	eprover: CPU time limit exceeded, terminating
64720.90/9306.81	% SZS status Ended for HL403993+4.p
64731.61/9308.14	% SZS status Started for HL403997+5.p
64731.61/9308.14	% SZS status GaveUp for HL403997+5.p
64731.61/9308.14	% SZS status Ended for HL403997+5.p
64752.79/9310.86	% SZS status Started for HL403995+4.p
64752.79/9310.86	% SZS status GaveUp for HL403995+4.p
64752.79/9310.86	eprover: CPU time limit exceeded, terminating
64752.79/9310.86	% SZS status Ended for HL403995+4.p
64756.45/9311.33	% SZS status Started for HL403998+5.p
64756.45/9311.33	% SZS status GaveUp for HL403998+5.p
64756.45/9311.33	% SZS status Ended for HL403998+5.p
64789.96/9315.60	% SZS status Started for HL403996+4.p
64789.96/9315.60	% SZS status GaveUp for HL403996+4.p
64789.96/9315.60	eprover: CPU time limit exceeded, terminating
64789.96/9315.60	% SZS status Ended for HL403996+4.p
64796.40/9316.29	% SZS status Started for HL403999+5.p
64796.40/9316.29	% SZS status GaveUp for HL403999+5.p
64796.40/9316.29	% SZS status Ended for HL403999+5.p
64816.39/9318.94	% SZS status Started for HL403997+4.p
64816.39/9318.94	% SZS status GaveUp for HL403997+4.p
64816.39/9318.94	eprover: CPU time limit exceeded, terminating
64816.39/9318.94	% SZS status Ended for HL403997+4.p
64825.47/9319.96	% SZS status Started for HL404001+5.p
64825.47/9319.96	% SZS status GaveUp for HL404001+5.p
64825.47/9319.96	% SZS status Ended for HL404001+5.p
64861.54/9324.51	% SZS status Started for HL403998+4.p
64861.54/9324.51	% SZS status GaveUp for HL403998+4.p
64861.54/9324.51	eprover: CPU time limit exceeded, terminating
64861.54/9324.51	% SZS status Ended for HL403998+4.p
64862.34/9324.69	% SZS status Started for HL404002+5.p
64862.34/9324.69	% SZS status GaveUp for HL404002+5.p
64862.34/9324.69	% SZS status Ended for HL404002+5.p
64889.55/9328.03	% SZS status Started for HL404003+5.p
64889.55/9328.03	% SZS status GaveUp for HL404003+5.p
64889.55/9328.03	% SZS status Ended for HL404003+5.p
64904.95/9330.05	% SZS status Started for HL403999+4.p
64904.95/9330.05	% SZS status GaveUp for HL403999+4.p
64904.95/9330.05	eprover: CPU time limit exceeded, terminating
64904.95/9330.05	% SZS status Ended for HL403999+4.p
64930.89/9333.25	% SZS status Started for HL404001+4.p
64930.89/9333.25	% SZS status GaveUp for HL404001+4.p
64930.89/9333.25	eprover: CPU time limit exceeded, terminating
64930.89/9333.25	% SZS status Ended for HL404001+4.p
64933.73/9333.58	% SZS status Started for HL404004+5.p
64933.73/9333.58	% SZS status GaveUp for HL404004+5.p
64933.73/9333.58	% SZS status Ended for HL404004+5.p
64958.19/9336.68	% SZS status Started for HL404002+4.p
64958.19/9336.68	% SZS status GaveUp for HL404002+4.p
64958.19/9336.68	eprover: CPU time limit exceeded, terminating
64958.19/9336.68	% SZS status Ended for HL404002+4.p
64961.87/9337.12	% SZS status Started for HL404005+5.p
64961.87/9337.12	% SZS status GaveUp for HL404005+5.p
64961.87/9337.12	% SZS status Ended for HL404005+5.p
64999.71/9341.87	% SZS status Started for HL404003+4.p
64999.71/9341.87	% SZS status GaveUp for HL404003+4.p
64999.71/9341.87	eprover: CPU time limit exceeded, terminating
64999.71/9341.87	% SZS status Ended for HL404003+4.p
65003.88/9342.39	% SZS status Started for HL404006+5.p
65003.88/9342.39	% SZS status GaveUp for HL404006+5.p
65003.88/9342.39	% SZS status Ended for HL404006+5.p
65026.02/9345.21	% SZS status Started for HL404004+4.p
65026.02/9345.21	% SZS status GaveUp for HL404004+4.p
65026.02/9345.21	eprover: CPU time limit exceeded, terminating
65026.02/9345.21	% SZS status Ended for HL404004+4.p
65030.83/9345.77	% SZS status Started for HL404008+5.p
65030.83/9345.77	% SZS status GaveUp for HL404008+5.p
65030.83/9345.77	% SZS status Ended for HL404008+5.p
65064.89/9350.08	% SZS status Started for HL404005+4.p
65064.89/9350.08	% SZS status GaveUp for HL404005+4.p
65064.89/9350.08	eprover: CPU time limit exceeded, terminating
65064.89/9350.08	% SZS status Ended for HL404005+4.p
65071.70/9350.93	% SZS status Started for HL404009+5.p
65071.70/9350.93	% SZS status GaveUp for HL404009+5.p
65071.70/9350.93	% SZS status Ended for HL404009+5.p
65098.89/9354.39	% SZS status Started for HL404010+5.p
65098.89/9354.39	% SZS status GaveUp for HL404010+5.p
65098.89/9354.39	% SZS status Ended for HL404010+5.p
65105.76/9355.29	% SZS status Started for HL404006+4.p
65105.76/9355.29	% SZS status GaveUp for HL404006+4.p
65105.76/9355.29	eprover: CPU time limit exceeded, terminating
65105.76/9355.29	% SZS status Ended for HL404006+4.p
65134.73/9358.86	% SZS status Started for HL404008+4.p
65134.73/9358.86	% SZS status GaveUp for HL404008+4.p
65134.73/9358.86	eprover: CPU time limit exceeded, terminating
65134.73/9358.86	% SZS status Ended for HL404008+4.p
65136.59/9359.13	% SZS status Started for HL404011+5.p
65136.59/9359.13	% SZS status GaveUp for HL404011+5.p
65136.59/9359.13	% SZS status Ended for HL404011+5.p
65162.61/9362.34	% SZS status Started for HL404009+4.p
65162.61/9362.34	% SZS status GaveUp for HL404009+4.p
65162.61/9362.34	eprover: CPU time limit exceeded, terminating
65162.61/9362.34	% SZS status Ended for HL404009+4.p
65172.68/9363.77	% SZS status Started for HL404012+5.p
65172.68/9363.77	% SZS status GaveUp for HL404012+5.p
65172.68/9363.77	% SZS status Ended for HL404012+5.p
65203.46/9367.83	% SZS status Started for HL404010+4.p
65203.46/9367.83	% SZS status GaveUp for HL404010+4.p
65203.46/9367.83	eprover: CPU time limit exceeded, terminating
65203.46/9367.83	% SZS status Ended for HL404010+4.p
65208.00/9368.28	% SZS status Started for HL404013+5.p
65208.00/9368.28	% SZS status GaveUp for HL404013+5.p
65208.00/9368.28	% SZS status Ended for HL404013+5.p
65228.38/9370.94	% SZS status Started for HL404011+4.p
65228.38/9370.94	% SZS status GaveUp for HL404011+4.p
65228.38/9370.94	eprover: CPU time limit exceeded, terminating
65228.38/9370.94	% SZS status Ended for HL404011+4.p
65241.92/9372.57	% SZS status Started for HL404015+5.p
65241.92/9372.57	% SZS status GaveUp for HL404015+5.p
65241.92/9372.57	% SZS status Ended for HL404015+5.p
65271.04/9376.22	% SZS status Started for HL404012+4.p
65271.04/9376.22	% SZS status GaveUp for HL404012+4.p
65271.04/9376.22	eprover: CPU time limit exceeded, terminating
65271.04/9376.22	% SZS status Ended for HL404012+4.p
65276.03/9376.98	% SZS status Started for HL404016+5.p
65276.03/9376.98	% SZS status GaveUp for HL404016+5.p
65276.03/9376.98	% SZS status Ended for HL404016+5.p
65301.13/9380.18	% SZS status Started for HL404018+5.p
65301.13/9380.18	% SZS status GaveUp for HL404018+5.p
65301.13/9380.18	% SZS status Ended for HL404018+5.p
65304.71/9380.64	% SZS status Started for HL404013+4.p
65304.71/9380.64	% SZS status GaveUp for HL404013+4.p
65304.71/9380.64	eprover: CPU time limit exceeded, terminating
65304.71/9380.64	% SZS status Ended for HL404013+4.p
65338.11/9384.85	% SZS status Started for HL404015+4.p
65338.11/9384.85	% SZS status GaveUp for HL404015+4.p
65338.11/9384.85	eprover: CPU time limit exceeded, terminating
65338.11/9384.85	% SZS status Ended for HL404015+4.p
65346.15/9385.83	% SZS status Started for HL404019+5.p
65346.15/9385.83	% SZS status GaveUp for HL404019+5.p
65346.15/9385.83	% SZS status Ended for HL404019+5.p
65373.29/9389.36	% SZS status Started for HL404020+5.p
65373.29/9389.36	% SZS status GaveUp for HL404020+5.p
65373.29/9389.36	% SZS status Ended for HL404020+5.p
65376.40/9389.71	% SZS status Started for HL404016+4.p
65376.40/9389.71	% SZS status GaveUp for HL404016+4.p
65376.40/9389.71	eprover: CPU time limit exceeded, terminating
65376.40/9389.71	% SZS status Ended for HL404016+4.p
65411.36/9394.12	% SZS status Started for HL404018+4.p
65411.36/9394.12	% SZS status GaveUp for HL404018+4.p
65411.36/9394.12	eprover: CPU time limit exceeded, terminating
65411.36/9394.12	% SZS status Ended for HL404018+4.p
65411.36/9394.17	% SZS status Started for HL404021+5.p
65411.36/9394.17	% SZS status GaveUp for HL404021+5.p
65411.36/9394.17	% SZS status Ended for HL404021+5.p
65440.73/9397.83	% SZS status Started for HL404019+4.p
65440.73/9397.83	% SZS status GaveUp for HL404019+4.p
65440.73/9397.83	eprover: CPU time limit exceeded, terminating
65440.73/9397.83	% SZS status Ended for HL404019+4.p
65447.50/9398.75	% SZS status Started for HL404022+5.p
65447.50/9398.75	% SZS status GaveUp for HL404022+5.p
65447.50/9398.75	% SZS status Ended for HL404022+5.p
65475.35/9402.27	% SZS status Started for HL404020+4.p
65475.35/9402.27	% SZS status GaveUp for HL404020+4.p
65475.35/9402.27	eprover: CPU time limit exceeded, terminating
65475.35/9402.27	% SZS status Ended for HL404020+4.p
65483.36/9403.20	% SZS status Started for HL404023+5.p
65483.36/9403.20	% SZS status GaveUp for HL404023+5.p
65483.36/9403.20	% SZS status Ended for HL404023+5.p
65508.70/9406.43	% SZS status Started for HL404021+4.p
65508.70/9406.43	% SZS status GaveUp for HL404021+4.p
65508.70/9406.43	eprover: CPU time limit exceeded, terminating
65508.70/9406.43	% SZS status Ended for HL404021+4.p
65513.98/9407.06	% SZS status Started for HL404024+5.p
65513.98/9407.06	% SZS status GaveUp for HL404024+5.p
65513.98/9407.06	% SZS status Ended for HL404024+5.p
65547.14/9411.24	% SZS status Started for HL404022+4.p
65547.14/9411.24	% SZS status GaveUp for HL404022+4.p
65547.14/9411.24	eprover: CPU time limit exceeded, terminating
65547.14/9411.24	% SZS status Ended for HL404022+4.p
65550.52/9411.65	% SZS status Started for HL404025+5.p
65550.52/9411.65	% SZS status GaveUp for HL404025+5.p
65550.52/9411.65	% SZS status Ended for HL404025+5.p
65579.93/9415.37	% SZS status Started for HL404023+4.p
65579.93/9415.37	% SZS status GaveUp for HL404023+4.p
65579.93/9415.37	eprover: CPU time limit exceeded, terminating
65579.93/9415.37	% SZS status Ended for HL404023+4.p
65581.25/9415.52	% SZS status Started for HL404026+5.p
65581.25/9415.52	% SZS status GaveUp for HL404026+5.p
65581.25/9415.52	% SZS status Ended for HL404026+5.p
65613.42/9419.59	% SZS status Started for HL404024+4.p
65613.42/9419.59	% SZS status GaveUp for HL404024+4.p
65613.42/9419.59	eprover: CPU time limit exceeded, terminating
65613.42/9419.59	% SZS status Ended for HL404024+4.p
65620.26/9420.41	% SZS status Started for HL404028+5.p
65620.26/9420.41	% SZS status GaveUp for HL404028+5.p
65620.26/9420.41	% SZS status Ended for HL404028+5.p
65648.34/9423.99	% SZS status Started for HL404025+4.p
65648.34/9423.99	% SZS status GaveUp for HL404025+4.p
65648.34/9423.99	eprover: CPU time limit exceeded, terminating
65648.34/9423.99	% SZS status Ended for HL404025+4.p
65652.06/9424.44	% SZS status Started for HL404029+5.p
65652.06/9424.44	% SZS status GaveUp for HL404029+5.p
65652.06/9424.44	% SZS status Ended for HL404029+5.p
65685.27/9428.65	% SZS status Started for HL404026+4.p
65685.27/9428.65	% SZS status GaveUp for HL404026+4.p
65685.27/9428.65	eprover: CPU time limit exceeded, terminating
65685.27/9428.65	% SZS status Ended for HL404026+4.p
65686.38/9428.78	% SZS status Started for HL404031+5.p
65686.38/9428.78	% SZS status GaveUp for HL404031+5.p
65686.38/9428.78	% SZS status Ended for HL404031+5.p
65698.23/9430.35	% SZS status Started for HL404032+5.p
65698.23/9430.35	% SZS status Theorem for HL404032+5.p
65698.23/9430.35	% SZS status Ended for HL404032+5.p
65718.15/9432.73	% SZS status Started for HL404028+4.p
65718.15/9432.73	% SZS status GaveUp for HL404028+4.p
65718.15/9432.73	eprover: CPU time limit exceeded, terminating
65718.15/9432.73	% SZS status Ended for HL404028+4.p
65750.73/9436.88	% SZS status Started for HL404034+5.p
65750.73/9436.88	% SZS status Theorem for HL404034+5.p
65750.73/9436.88	% SZS status Ended for HL404034+5.p
65751.27/9436.96	% SZS status Started for HL404029+4.p
65751.27/9436.96	% SZS status GaveUp for HL404029+4.p
65751.27/9436.96	eprover: CPU time limit exceeded, terminating
65751.27/9436.96	% SZS status Ended for HL404029+4.p
65758.02/9437.87	% SZS status Started for HL404033+5.p
65758.02/9437.87	% SZS status GaveUp for HL404033+5.p
65758.02/9437.87	% SZS status Ended for HL404033+5.p
65781.63/9440.73	% SZS status Started for HL404031+4.p
65781.63/9440.73	% SZS status GaveUp for HL404031+4.p
65781.63/9440.73	eprover: CPU time limit exceeded, terminating
65781.63/9440.73	% SZS status Ended for HL404031+4.p
65820.66/9445.65	% SZS status Started for HL404032+4.p
65820.66/9445.65	% SZS status GaveUp for HL404032+4.p
65820.66/9445.65	eprover: CPU time limit exceeded, terminating
65820.66/9445.65	% SZS status Ended for HL404032+4.p
65823.53/9446.02	% SZS status Started for HL404035+5.p
65823.53/9446.02	% SZS status GaveUp for HL404035+5.p
65823.53/9446.02	% SZS status Ended for HL404035+5.p
65830.99/9446.96	% SZS status Started for HL404036+5.p
65830.99/9446.96	% SZS status GaveUp for HL404036+5.p
65830.99/9446.96	% SZS status Ended for HL404036+5.p
65852.41/9449.68	% SZS status Started for HL404033+4.p
65852.41/9449.68	% SZS status GaveUp for HL404033+4.p
65852.41/9449.68	eprover: CPU time limit exceeded, terminating
65852.41/9449.68	% SZS status Ended for HL404033+4.p
65888.53/9454.29	% SZS status Started for HL404034+4.p
65888.53/9454.29	% SZS status GaveUp for HL404034+4.p
65888.53/9454.29	eprover: CPU time limit exceeded, terminating
65888.53/9454.29	% SZS status Ended for HL404034+4.p
65894.35/9455.01	% SZS status Started for HL404037+5.p
65894.35/9455.01	% SZS status GaveUp for HL404037+5.p
65894.35/9455.01	% SZS status Ended for HL404037+5.p
65903.26/9456.17	% SZS status Started for HL404039+5.p
65903.26/9456.17	% SZS status GaveUp for HL404039+5.p
65903.26/9456.17	% SZS status Ended for HL404039+5.p
65910.42/9457.06	% SZS status Started for HL404041+5.p
65910.42/9457.06	% SZS status Theorem for HL404041+5.p
65910.42/9457.06	% SZS status Ended for HL404041+5.p
65919.07/9458.15	% SZS status Started for HL404035+4.p
65919.07/9458.15	% SZS status GaveUp for HL404035+4.p
65919.07/9458.15	eprover: CPU time limit exceeded, terminating
65919.07/9458.15	% SZS status Ended for HL404035+4.p
65925.66/9458.98	% SZS status Started for HL404042+5.p
65925.66/9458.98	% SZS status Theorem for HL404042+5.p
65925.66/9458.98	% SZS status Ended for HL404042+5.p
65951.84/9462.23	% SZS status Started for HL404036+4.p
65951.84/9462.23	% SZS status GaveUp for HL404036+4.p
65951.84/9462.23	eprover: CPU time limit exceeded, terminating
65951.84/9462.23	% SZS status Ended for HL404036+4.p
65958.72/9463.15	% SZS status Started for HL404043+5.p
65958.72/9463.15	% SZS status Theorem for HL404043+5.p
65958.72/9463.15	% SZS status Ended for HL404043+5.p
65959.68/9463.34	% SZS status Started for HL404040+5.p
65959.68/9463.34	% SZS status GaveUp for HL404040+5.p
65959.68/9463.34	% SZS status Ended for HL404040+5.p
65967.73/9464.27	% SZS status Started for HL404045+5.p
65967.73/9464.27	% SZS status Theorem for HL404045+5.p
65967.73/9464.27	% SZS status Ended for HL404045+5.p
65983.01/9466.16	% SZS status Started for HL404037+4.p
65983.01/9466.16	% SZS status GaveUp for HL404037+4.p
65983.01/9466.16	eprover: CPU time limit exceeded, terminating
65983.01/9466.16	% SZS status Ended for HL404037+4.p
65990.73/9467.15	% SZS status Started for HL404046+5.p
65990.73/9467.15	% SZS status Theorem for HL404046+5.p
65990.73/9467.15	% SZS status Ended for HL404046+5.p
66024.55/9471.43	% SZS status Started for HL404039+4.p
66024.55/9471.43	% SZS status GaveUp for HL404039+4.p
66024.55/9471.43	eprover: CPU time limit exceeded, terminating
66024.55/9471.43	% SZS status Ended for HL404039+4.p
66051.97/9474.88	% SZS status Started for HL404040+4.p
66051.97/9474.88	% SZS status GaveUp for HL404040+4.p
66051.97/9474.88	eprover: CPU time limit exceeded, terminating
66051.97/9474.88	% SZS status Ended for HL404040+4.p
66053.51/9475.04	% SZS status Started for HL404047+5.p
66053.51/9475.04	% SZS status Theorem for HL404047+5.p
66053.51/9475.04	% SZS status Ended for HL404047+5.p
66095.02/9480.28	% SZS status Started for HL404041+4.p
66095.02/9480.28	% SZS status GaveUp for HL404041+4.p
66095.02/9480.28	eprover: CPU time limit exceeded, terminating
66095.02/9480.28	% SZS status Ended for HL404041+4.p
66111.21/9482.28	% SZS status Started for HL404042+4.p
66111.21/9482.28	% SZS status GaveUp for HL404042+4.p
66111.21/9482.28	eprover: CPU time limit exceeded, terminating
66111.21/9482.28	% SZS status Ended for HL404042+4.p
66126.08/9484.18	% SZS status Started for HL404049+5.p
66126.08/9484.18	% SZS status GaveUp for HL404049+5.p
66126.08/9484.18	% SZS status Ended for HL404049+5.p
66128.89/9484.52	% SZS status Started for HL404043+4.p
66128.89/9484.52	% SZS status GaveUp for HL404043+4.p
66128.89/9484.52	eprover: CPU time limit exceeded, terminating
66128.89/9484.52	% SZS status Ended for HL404043+4.p
66159.28/9488.45	% SZS status Started for HL404045+4.p
66159.28/9488.45	% SZS status GaveUp for HL404045+4.p
66159.28/9488.45	eprover: CPU time limit exceeded, terminating
66159.28/9488.45	% SZS status Ended for HL404045+4.p
66191.82/9489.44	% SZS status Started for HL404046+4.p
66191.82/9489.44	% SZS status GaveUp for HL404046+4.p
66191.82/9489.44	eprover: CPU time limit exceeded, terminating
66191.82/9489.44	% SZS status Ended for HL404046+4.p
66209.05/9491.63	% SZS status Started for HL404051+5.p
66209.05/9491.63	% SZS status GaveUp for HL404051+5.p
66209.05/9491.63	% SZS status Ended for HL404051+5.p
66216.24/9492.53	% SZS status Started for HL404047+4.p
66216.24/9492.53	% SZS status GaveUp for HL404047+4.p
66216.24/9492.53	eprover: CPU time limit exceeded, terminating
66216.24/9492.53	% SZS status Ended for HL404047+4.p
66224.12/9493.45	% SZS status Started for HL404055+5.p
66224.12/9493.45	% SZS status Theorem for HL404055+5.p
66224.12/9493.45	% SZS status Ended for HL404055+5.p
66224.66/9493.65	% SZS status Started for HL404052+5.p
66224.66/9493.65	% SZS status GaveUp for HL404052+5.p
66224.66/9493.65	% SZS status Ended for HL404052+5.p
66232.28/9494.58	% SZS status Started for HL404056+5.p
66232.28/9494.58	% SZS status Theorem for HL404056+5.p
66232.28/9494.58	% SZS status Ended for HL404056+5.p
66264.58/9498.53	% SZS status Started for HL404053+5.p
66264.58/9498.53	% SZS status GaveUp for HL404053+5.p
66264.58/9498.53	% SZS status Ended for HL404053+5.p
66277.99/9500.26	% SZS status Started for HL404049+4.p
66277.99/9500.26	% SZS status GaveUp for HL404049+4.p
66277.99/9500.26	eprover: CPU time limit exceeded, terminating
66277.99/9500.26	% SZS status Ended for HL404049+4.p
66322.91/9505.92	% SZS status Started for HL404051+4.p
66322.91/9505.92	% SZS status GaveUp for HL404051+4.p
66322.91/9505.92	eprover: CPU time limit exceeded, terminating
66322.91/9505.92	% SZS status Ended for HL404051+4.p
66336.95/9507.69	% SZS status Started for HL404057+5.p
66336.95/9507.69	% SZS status GaveUp for HL404057+5.p
66336.95/9507.69	% SZS status Ended for HL404057+5.p
66351.67/9509.51	% SZS status Started for HL404052+4.p
66351.67/9509.51	% SZS status GaveUp for HL404052+4.p
66351.67/9509.51	eprover: CPU time limit exceeded, terminating
66351.67/9509.51	% SZS status Ended for HL404052+4.p
66384.12/9513.65	% SZS status Started for HL404053+4.p
66384.12/9513.65	% SZS status GaveUp for HL404053+4.p
66384.12/9513.65	eprover: CPU time limit exceeded, terminating
66384.12/9513.65	% SZS status Ended for HL404053+4.p
66395.42/9515.05	% SZS status Started for HL404059+5.p
66395.42/9515.05	% SZS status GaveUp for HL404059+5.p
66395.42/9515.05	% SZS status Ended for HL404059+5.p
66408.58/9516.76	% SZS status Started for HL404055+4.p
66408.58/9516.76	% SZS status GaveUp for HL404055+4.p
66408.58/9516.76	eprover: CPU time limit exceeded, terminating
66408.58/9516.76	% SZS status Ended for HL404055+4.p
66423.41/9518.58	% SZS status Started for HL404056+4.p
66423.41/9518.58	% SZS status GaveUp for HL404056+4.p
66423.41/9518.58	eprover: CPU time limit exceeded, terminating
66423.41/9518.58	% SZS status Ended for HL404056+4.p
66423.41/9518.59	% SZS status Started for HL404060+5.p
66423.41/9518.59	% SZS status GaveUp for HL404060+5.p
66423.41/9518.59	% SZS status Ended for HL404060+5.p
66433.10/9519.78	% SZS status Started for HL404057+4.p
66433.10/9519.78	% SZS status GaveUp for HL404057+4.p
66433.10/9519.78	eprover: CPU time limit exceeded, terminating
66433.10/9519.78	% SZS status Ended for HL404057+4.p
66467.66/9524.13	% SZS status Started for HL404061+5.p
66467.66/9524.13	% SZS status GaveUp for HL404061+5.p
66467.66/9524.13	% SZS status Ended for HL404061+5.p
66477.98/9525.43	% SZS status Started for HL404059+4.p
66477.98/9525.43	% SZS status GaveUp for HL404059+4.p
66477.98/9525.43	eprover: CPU time limit exceeded, terminating
66477.98/9525.43	% SZS status Ended for HL404059+4.p
66504.67/9529.82	% SZS status Started for HL404063+5.p
66504.67/9529.82	% SZS status GaveUp for HL404063+5.p
66504.67/9529.82	% SZS status Ended for HL404063+5.p
66509.36/9530.74	% SZS status Started for HL404062+5.p
66509.36/9530.74	% SZS status GaveUp for HL404062+5.p
66509.36/9530.74	% SZS status Ended for HL404062+5.p
66534.20/9534.12	% SZS status Started for HL404060+4.p
66534.20/9534.12	% SZS status GaveUp for HL404060+4.p
66534.20/9534.12	eprover: CPU time limit exceeded, terminating
66534.20/9534.12	% SZS status Ended for HL404060+4.p
66545.02/9535.45	% SZS status Started for HL404064+5.p
66545.02/9535.45	% SZS status GaveUp for HL404064+5.p
66545.02/9535.45	% SZS status Ended for HL404064+5.p
66582.14/9540.14	% SZS status Started for HL404061+4.p
66582.14/9540.14	% SZS status GaveUp for HL404061+4.p
66582.14/9540.14	eprover: CPU time limit exceeded, terminating
66582.14/9540.14	% SZS status Ended for HL404061+4.p
66608.07/9540.24	% SZS status Started for HL404065+5.p
66608.07/9540.24	% SZS status GaveUp for HL404065+5.p
66608.07/9540.24	% SZS status Ended for HL404065+5.p
66642.42/9544.60	% SZS status Started for HL404066+5.p
66642.42/9544.60	% SZS status GaveUp for HL404066+5.p
66642.42/9544.60	% SZS status Ended for HL404066+5.p
66648.09/9545.25	% SZS status Started for HL404062+4.p
66648.09/9545.25	% SZS status GaveUp for HL404062+4.p
66648.09/9545.25	eprover: CPU time limit exceeded, terminating
66648.09/9545.25	% SZS status Ended for HL404062+4.p
66660.72/9546.96	% SZS status Started for HL404063+4.p
66660.72/9546.96	% SZS status GaveUp for HL404063+4.p
66660.72/9546.96	eprover: CPU time limit exceeded, terminating
66660.72/9546.96	% SZS status Ended for HL404063+4.p
66680.47/9549.36	% SZS status Started for HL404067+5.p
66680.47/9549.36	% SZS status GaveUp for HL404067+5.p
66680.47/9549.36	% SZS status Ended for HL404067+5.p
66681.78/9549.62	% SZS status Started for HL404064+4.p
66681.78/9549.62	% SZS status GaveUp for HL404064+4.p
66681.78/9549.62	eprover: CPU time limit exceeded, terminating
66681.78/9549.62	% SZS status Ended for HL404064+4.p
66720.16/9554.38	% SZS status Started for HL404068+5.p
66720.16/9554.38	% SZS status GaveUp for HL404068+5.p
66720.16/9554.38	% SZS status Ended for HL404068+5.p
66730.38/9555.72	% SZS status Started for HL404065+4.p
66730.38/9555.72	% SZS status GaveUp for HL404065+4.p
66730.38/9555.72	eprover: CPU time limit exceeded, terminating
66730.38/9555.72	% SZS status Ended for HL404065+4.p
66752.25/9558.48	% SZS status Started for HL404069+5.p
66752.25/9558.48	% SZS status GaveUp for HL404069+5.p
66752.25/9558.48	% SZS status Ended for HL404069+5.p
66759.76/9559.47	% SZS status Started for HL404066+4.p
66759.76/9559.47	% SZS status GaveUp for HL404066+4.p
66759.76/9559.47	eprover: CPU time limit exceeded, terminating
66759.76/9559.47	% SZS status Ended for HL404066+4.p
66793.04/9563.67	% SZS status Started for HL404070+5.p
66793.04/9563.67	% SZS status GaveUp for HL404070+5.p
66793.04/9563.67	% SZS status Ended for HL404070+5.p
66811.76/9566.10	% SZS status Started for HL404067+4.p
66811.76/9566.10	% SZS status GaveUp for HL404067+4.p
66811.76/9566.10	eprover: CPU time limit exceeded, terminating
66811.76/9566.10	% SZS status Ended for HL404067+4.p
66827.35/9568.03	% SZS status Started for HL404071+5.p
66827.35/9568.03	% SZS status GaveUp for HL404071+5.p
66827.35/9568.03	% SZS status Ended for HL404071+5.p
66845.03/9570.41	% SZS status Started for HL404068+4.p
66845.03/9570.41	% SZS status GaveUp for HL404068+4.p
66845.03/9570.41	eprover: CPU time limit exceeded, terminating
66845.03/9570.41	% SZS status Ended for HL404068+4.p
66865.48/9572.86	% SZS status Started for HL404069+4.p
66865.48/9572.86	% SZS status GaveUp for HL404069+4.p
66865.48/9572.86	eprover: CPU time limit exceeded, terminating
66865.48/9572.86	% SZS status Ended for HL404069+4.p
66865.87/9572.93	% SZS status Started for HL404072+5.p
66865.87/9572.93	% SZS status GaveUp for HL404072+5.p
66865.87/9572.93	% SZS status Ended for HL404072+5.p
66884.27/9575.26	% SZS status Started for HL404070+4.p
66884.27/9575.26	% SZS status GaveUp for HL404070+4.p
66884.27/9575.26	eprover: CPU time limit exceeded, terminating
66884.27/9575.26	% SZS status Ended for HL404070+4.p
66899.52/9577.20	% SZS status Started for HL404073+5.p
66899.52/9577.20	% SZS status GaveUp for HL404073+5.p
66899.52/9577.20	% SZS status Ended for HL404073+5.p
66938.31/9582.02	% SZS status Started for HL404071+4.p
66938.31/9582.02	% SZS status GaveUp for HL404071+4.p
66938.31/9582.02	eprover: CPU time limit exceeded, terminating
66938.31/9582.02	% SZS status Ended for HL404071+4.p
66938.81/9582.12	% SZS status Started for HL404074+5.p
66938.81/9582.12	% SZS status GaveUp for HL404074+5.p
66938.81/9582.12	% SZS status Ended for HL404074+5.p
66956.96/9584.36	% SZS status Started for HL404076+5.p
66956.96/9584.36	% SZS status GaveUp for HL404076+5.p
66956.96/9584.36	% SZS status Ended for HL404076+5.p
66961.66/9585.02	% SZS status Started for HL404072+4.p
66961.66/9585.02	% SZS status GaveUp for HL404072+4.p
66961.66/9585.02	eprover: CPU time limit exceeded, terminating
66961.66/9585.02	% SZS status Ended for HL404072+4.p
67011.27/9591.19	% SZS status Started for HL404077+5.p
67011.27/9591.19	% SZS status GaveUp for HL404077+5.p
67011.27/9591.19	% SZS status Ended for HL404077+5.p
67014.91/9591.72	% SZS status Started for HL404073+4.p
67014.91/9591.72	% SZS status GaveUp for HL404073+4.p
67014.91/9591.72	eprover: CPU time limit exceeded, terminating
67014.91/9591.72	% SZS status Ended for HL404073+4.p
67029.12/9593.48	% SZS status Started for HL404078+5.p
67029.12/9593.48	% SZS status GaveUp for HL404078+5.p
67029.12/9593.48	% SZS status Ended for HL404078+5.p
67047.00/9595.85	% SZS status Started for HL404074+4.p
67047.00/9595.85	% SZS status GaveUp for HL404074+4.p
67047.00/9595.85	eprover: CPU time limit exceeded, terminating
67047.00/9595.85	% SZS status Ended for HL404074+4.p
67068.65/9598.58	% SZS status Started for HL404076+4.p
67068.65/9598.58	% SZS status GaveUp for HL404076+4.p
67068.65/9598.58	eprover: CPU time limit exceeded, terminating
67068.65/9598.58	% SZS status Ended for HL404076+4.p
67082.59/9600.36	% SZS status Started for HL404079+5.p
67082.59/9600.36	% SZS status GaveUp for HL404079+5.p
67082.59/9600.36	% SZS status Ended for HL404079+5.p
67104.40/9603.06	% SZS status Started for HL404080+5.p
67104.40/9603.06	% SZS status GaveUp for HL404080+5.p
67104.40/9603.06	% SZS status Ended for HL404080+5.p
67105.90/9603.21	% SZS status Started for HL404077+4.p
67105.90/9603.21	% SZS status GaveUp for HL404077+4.p
67105.90/9603.21	eprover: CPU time limit exceeded, terminating
67105.90/9603.21	% SZS status Ended for HL404077+4.p
67141.00/9607.67	% SZS status Started for HL404081+5.p
67141.00/9607.67	% SZS status GaveUp for HL404081+5.p
67141.00/9607.67	% SZS status Ended for HL404081+5.p
67142.08/9607.84	% SZS status Started for HL404078+4.p
67142.08/9607.84	% SZS status GaveUp for HL404078+4.p
67142.08/9607.84	eprover: CPU time limit exceeded, terminating
67142.08/9607.84	% SZS status Ended for HL404078+4.p
67166.16/9610.84	% SZS status Started for HL404079+4.p
67166.16/9610.84	% SZS status GaveUp for HL404079+4.p
67166.16/9610.84	eprover: CPU time limit exceeded, terminating
67166.16/9610.84	% SZS status Ended for HL404079+4.p
67179.42/9612.56	% SZS status Started for HL404082+5.p
67179.42/9612.56	% SZS status GaveUp for HL404082+5.p
67179.42/9612.56	% SZS status Ended for HL404082+5.p
67213.22/9616.80	% SZS status Started for HL404083+5.p
67213.22/9616.80	% SZS status GaveUp for HL404083+5.p
67213.22/9616.80	% SZS status Ended for HL404083+5.p
67222.86/9618.00	% SZS status Started for HL404080+4.p
67222.86/9618.00	% SZS status GaveUp for HL404080+4.p
67222.86/9618.00	eprover: CPU time limit exceeded, terminating
67222.86/9618.00	% SZS status Ended for HL404080+4.p
67240.80/9620.29	% SZS status Started for HL404084+5.p
67240.80/9620.29	% SZS status GaveUp for HL404084+5.p
67240.80/9620.29	% SZS status Ended for HL404084+5.p
67249.68/9621.39	% SZS status Started for HL404081+4.p
67249.68/9621.39	% SZS status GaveUp for HL404081+4.p
67249.68/9621.39	eprover: CPU time limit exceeded, terminating
67249.68/9621.39	% SZS status Ended for HL404081+4.p
67285.24/9625.95	% SZS status Started for HL404082+4.p
67285.24/9625.95	% SZS status GaveUp for HL404082+4.p
67285.24/9625.95	eprover: CPU time limit exceeded, terminating
67285.24/9625.95	% SZS status Ended for HL404082+4.p
67286.23/9626.10	% SZS status Started for HL404085+5.p
67286.23/9626.10	% SZS status GaveUp for HL404085+5.p
67286.23/9626.10	% SZS status Ended for HL404085+5.p
67306.77/9628.66	% SZS status Started for HL404083+4.p
67306.77/9628.66	% SZS status GaveUp for HL404083+4.p
67306.77/9628.66	eprover: CPU time limit exceeded, terminating
67306.77/9628.66	% SZS status Ended for HL404083+4.p
67313.05/9629.39	% SZS status Started for HL404086+5.p
67313.05/9629.39	% SZS status GaveUp for HL404086+5.p
67313.05/9629.39	% SZS status Ended for HL404086+5.p
67345.16/9633.50	% SZS status Started for HL404084+4.p
67345.16/9633.50	% SZS status GaveUp for HL404084+4.p
67345.16/9633.50	eprover: CPU time limit exceeded, terminating
67345.16/9633.50	% SZS status Ended for HL404084+4.p
67357.54/9635.08	% SZS status Started for HL404088+5.p
67357.54/9635.08	% SZS status GaveUp for HL404088+5.p
67357.54/9635.08	% SZS status Ended for HL404088+5.p
67382.38/9638.16	% SZS status Started for HL404089+5.p
67382.38/9638.16	% SZS status GaveUp for HL404089+5.p
67382.38/9638.16	% SZS status Ended for HL404089+5.p
67384.92/9638.57	% SZS status Started for HL404085+4.p
67384.92/9638.57	% SZS status GaveUp for HL404085+4.p
67384.92/9638.57	eprover: CPU time limit exceeded, terminating
67384.92/9638.57	% SZS status Ended for HL404085+4.p
67417.17/9642.62	% SZS status Started for HL404090+5.p
67417.17/9642.62	% SZS status GaveUp for HL404090+5.p
67417.17/9642.62	% SZS status Ended for HL404090+5.p
67426.88/9643.96	% SZS status Started for HL404086+4.p
67426.88/9643.96	% SZS status GaveUp for HL404086+4.p
67426.88/9643.96	eprover: CPU time limit exceeded, terminating
67426.88/9643.96	% SZS status Ended for HL404086+4.p
67428.95/9644.01	% SZS status Started for HL404091+5.p
67428.95/9644.01	% SZS status Theorem for HL404091+5.p
67428.95/9644.01	% SZS status Ended for HL404091+5.p
67455.73/9647.40	% SZS status Started for HL404088+4.p
67455.73/9647.40	% SZS status GaveUp for HL404088+4.p
67455.73/9647.40	eprover: CPU time limit exceeded, terminating
67455.73/9647.40	% SZS status Ended for HL404088+4.p
67488.78/9651.59	% SZS status Started for HL404089+4.p
67488.78/9651.59	% SZS status GaveUp for HL404089+4.p
67488.78/9651.59	eprover: CPU time limit exceeded, terminating
67488.78/9651.59	% SZS status Ended for HL404089+4.p
67491.23/9651.96	% SZS status Started for HL404092+5.p
67491.23/9651.96	% SZS status GaveUp for HL404092+5.p
67491.23/9651.96	% SZS status Ended for HL404092+5.p
67501.00/9653.16	% SZS status Started for HL404093+5.p
67501.00/9653.16	% SZS status GaveUp for HL404093+5.p
67501.00/9653.16	% SZS status Ended for HL404093+5.p
67517.09/9655.20	% SZS status Started for HL404090+4.p
67517.09/9655.20	% SZS status GaveUp for HL404090+4.p
67517.09/9655.20	eprover: CPU time limit exceeded, terminating
67517.09/9655.20	% SZS status Ended for HL404090+4.p
67536.77/9657.63	% SZS status Started for HL404094+4.p
67536.77/9657.63	% SZS status GaveUp for HL404094+4.p
67536.77/9657.63	eprover: CPU time limit exceeded, terminating
67536.77/9657.63	% SZS status Ended for HL404094+4.p
67560.62/9660.80	% SZS status Started for HL404091+4.p
67560.62/9660.80	% SZS status GaveUp for HL404091+4.p
67560.62/9660.80	eprover: CPU time limit exceeded, terminating
67560.62/9660.80	% SZS status Ended for HL404091+4.p
67561.39/9660.92	% SZS status Started for HL404094+5.p
67561.39/9660.92	% SZS status GaveUp for HL404094+5.p
67561.39/9660.92	% SZS status Ended for HL404094+5.p
67574.89/9662.53	% SZS status Started for HL404095+5.p
67574.89/9662.53	% SZS status GaveUp for HL404095+5.p
67574.89/9662.53	% SZS status Ended for HL404095+5.p
67593.77/9664.86	% SZS status Started for HL404092+4.p
67593.77/9664.86	% SZS status GaveUp for HL404092+4.p
67593.77/9664.86	eprover: CPU time limit exceeded, terminating
67593.77/9664.86	% SZS status Ended for HL404092+4.p
67609.73/9666.93	% SZS status Started for HL404096+5.p
67609.73/9666.93	% SZS status GaveUp for HL404096+5.p
67609.73/9666.93	% SZS status Ended for HL404096+5.p
67632.40/9669.74	% SZS status Started for HL404093+4.p
67632.40/9669.74	% SZS status GaveUp for HL404093+4.p
67632.40/9669.74	eprover: CPU time limit exceeded, terminating
67632.40/9669.74	% SZS status Ended for HL404093+4.p
67635.16/9670.15	% SZS status Started for HL404097+5.p
67635.16/9670.15	% SZS status GaveUp for HL404097+5.p
67635.16/9670.15	% SZS status Ended for HL404097+5.p
67667.48/9674.23	% SZS status Started for HL404098+5.p
67667.48/9674.23	% SZS status GaveUp for HL404098+5.p
67667.48/9674.23	% SZS status Ended for HL404098+5.p
67695.36/9677.78	% SZS status Started for HL404095+4.p
67695.36/9677.78	% SZS status GaveUp for HL404095+4.p
67695.36/9677.78	eprover: CPU time limit exceeded, terminating
67695.36/9677.78	% SZS status Ended for HL404095+4.p
67705.55/9679.00	% SZS status Started for HL404099+5.p
67705.55/9679.00	% SZS status GaveUp for HL404099+5.p
67705.55/9679.00	% SZS status Ended for HL404099+5.p
67720.31/9680.82	% SZS status Started for HL404096+4.p
67720.31/9680.82	% SZS status GaveUp for HL404096+4.p
67720.31/9680.82	eprover: CPU time limit exceeded, terminating
67720.31/9680.82	% SZS status Ended for HL404096+4.p
67740.95/9683.42	% SZS status Started for HL404100+5.p
67740.95/9683.42	% SZS status GaveUp for HL404100+5.p
67740.95/9683.42	% SZS status Ended for HL404100+5.p
67765.32/9686.50	% SZS status Started for HL404097+4.p
67765.32/9686.50	% SZS status GaveUp for HL404097+4.p
67765.32/9686.50	eprover: CPU time limit exceeded, terminating
67765.32/9686.50	% SZS status Ended for HL404097+4.p
67775.41/9687.91	% SZS status Started for HL404101+5.p
67775.41/9687.91	% SZS status GaveUp for HL404101+5.p
67775.41/9687.91	% SZS status Ended for HL404101+5.p
67778.85/9688.31	% SZS status Started for HL404098+4.p
67778.85/9688.31	% SZS status GaveUp for HL404098+4.p
67778.85/9688.31	eprover: CPU time limit exceeded, terminating
67778.85/9688.31	% SZS status Ended for HL404098+4.p
67811.80/9692.37	% SZS status Started for HL404102+5.p
67811.80/9692.37	% SZS status GaveUp for HL404102+5.p
67811.80/9692.37	% SZS status Ended for HL404102+5.p
67812.51/9692.48	% SZS status Started for HL404099+4.p
67812.51/9692.48	% SZS status GaveUp for HL404099+4.p
67812.51/9692.48	eprover: CPU time limit exceeded, terminating
67812.51/9692.48	% SZS status Ended for HL404099+4.p
67841.27/9696.10	% SZS status Started for HL404100+4.p
67841.27/9696.10	% SZS status GaveUp for HL404100+4.p
67841.27/9696.10	eprover: CPU time limit exceeded, terminating
67841.27/9696.10	% SZS status Ended for HL404100+4.p
67848.84/9697.01	% SZS status Started for HL404103+5.p
67848.84/9697.01	% SZS status GaveUp for HL404103+5.p
67848.84/9697.01	% SZS status Ended for HL404103+5.p
67882.44/9701.30	% SZS status Started for HL404104+5.p
67882.44/9701.30	% SZS status GaveUp for HL404104+5.p
67882.44/9701.30	% SZS status Ended for HL404104+5.p
67901.58/9703.69	% SZS status Started for HL404101+4.p
67901.58/9703.69	% SZS status GaveUp for HL404101+4.p
67901.58/9703.69	eprover: CPU time limit exceeded, terminating
67901.58/9703.69	% SZS status Ended for HL404101+4.p
67912.95/9705.15	% SZS status Started for HL404106+5.p
67912.95/9705.15	% SZS status GaveUp for HL404106+5.p
67912.95/9705.15	% SZS status Ended for HL404106+5.p
67926.33/9706.80	% SZS status Started for HL404102+4.p
67926.33/9706.80	% SZS status GaveUp for HL404102+4.p
67926.33/9706.80	eprover: CPU time limit exceeded, terminating
67926.33/9706.80	% SZS status Ended for HL404102+4.p
67954.21/9710.31	% SZS status Started for HL404107+5.p
67954.21/9710.31	% SZS status GaveUp for HL404107+5.p
67954.21/9710.31	% SZS status Ended for HL404107+5.p
67971.70/9712.62	% SZS status Started for HL404103+4.p
67971.70/9712.62	% SZS status GaveUp for HL404103+4.p
67971.70/9712.62	eprover: CPU time limit exceeded, terminating
67971.70/9712.62	% SZS status Ended for HL404103+4.p
67985.52/9714.25	% SZS status Started for HL404104+4.p
67985.52/9714.25	% SZS status GaveUp for HL404104+4.p
67985.52/9714.25	eprover: CPU time limit exceeded, terminating
67985.52/9714.25	% SZS status Ended for HL404104+4.p
67986.52/9714.34	% SZS status Started for HL404109+5.p
67986.52/9714.34	% SZS status GaveUp for HL404109+5.p
67986.52/9714.34	% SZS status Ended for HL404109+5.p
68019.02/9718.47	% SZS status Started for HL404106+4.p
68019.02/9718.47	% SZS status GaveUp for HL404106+4.p
68019.02/9718.47	eprover: CPU time limit exceeded, terminating
68019.02/9718.47	% SZS status Ended for HL404106+4.p
68027.27/9719.48	% SZS status Started for HL404110+5.p
68027.27/9719.48	% SZS status GaveUp for HL404110+5.p
68027.27/9719.48	% SZS status Ended for HL404110+5.p
68054.32/9722.88	% SZS status Started for HL404107+4.p
68054.32/9722.88	% SZS status GaveUp for HL404107+4.p
68054.32/9722.88	eprover: CPU time limit exceeded, terminating
68054.32/9722.88	% SZS status Ended for HL404107+4.p
68057.71/9723.35	% SZS status Started for HL404111+5.p
68057.71/9723.35	% SZS status GaveUp for HL404111+5.p
68057.71/9723.35	% SZS status Ended for HL404111+5.p
68091.39/9727.62	% SZS status Started for HL404112+5.p
68091.39/9727.62	% SZS status GaveUp for HL404112+5.p
68091.39/9727.62	% SZS status Ended for HL404112+5.p
68112.05/9729.20	% SZS status Started for HL404109+4.p
68112.05/9729.20	% SZS status GaveUp for HL404109+4.p
68112.05/9729.20	eprover: CPU time limit exceeded, terminating
68112.05/9729.20	% SZS status Ended for HL404109+4.p
68135.17/9732.09	% SZS status Started for HL404113+5.p
68135.17/9732.09	% SZS status GaveUp for HL404113+5.p
68135.17/9732.09	% SZS status Ended for HL404113+5.p
68139.21/9732.60	% SZS status Started for HL404110+4.p
68139.21/9732.60	% SZS status GaveUp for HL404110+4.p
68139.21/9732.60	eprover: CPU time limit exceeded, terminating
68139.21/9732.60	% SZS status Ended for HL404110+4.p
68150.29/9733.90	% SZS status Started for HL404114+4.p
68150.29/9733.90	% SZS status GaveUp for HL404114+4.p
68150.29/9733.90	eprover: CPU time limit exceeded, terminating
68150.29/9733.90	% SZS status Ended for HL404114+4.p
68172.34/9736.75	% SZS status Started for HL404114+5.p
68172.34/9736.75	% SZS status GaveUp for HL404114+5.p
68172.34/9736.75	% SZS status Ended for HL404114+5.p
68179.84/9737.76	% SZS status Started for HL404116+5.p
68179.84/9737.76	% SZS status Theorem for HL404116+5.p
68179.84/9737.76	% SZS status Ended for HL404116+5.p
68184.88/9738.31	% SZS status Started for HL404111+4.p
68184.88/9738.31	% SZS status GaveUp for HL404111+4.p
68184.88/9738.31	eprover: CPU time limit exceeded, terminating
68184.88/9738.31	% SZS status Ended for HL404111+4.p
68197.79/9739.94	% SZS status Started for HL404112+4.p
68197.79/9739.94	% SZS status GaveUp for HL404112+4.p
68197.79/9739.94	eprover: CPU time limit exceeded, terminating
68197.79/9739.94	% SZS status Ended for HL404112+4.p
68206.30/9740.99	% SZS status Started for HL404115+5.p
68206.30/9740.99	% SZS status GaveUp for HL404115+5.p
68206.30/9740.99	% SZS status Ended for HL404115+5.p
68241.82/9745.42	% SZS status Started for HL404113+4.p
68241.82/9745.42	% SZS status GaveUp for HL404113+4.p
68241.82/9745.42	eprover: CPU time limit exceeded, terminating
68241.82/9745.42	% SZS status Ended for HL404113+4.p
68247.83/9746.24	% SZS status Started for HL404118+5.p
68247.83/9746.24	% SZS status Theorem for HL404118+5.p
68247.83/9746.24	% SZS status Ended for HL404118+5.p
68251.78/9746.68	% SZS status Started for HL404117+5.p
68251.78/9746.68	% SZS status GaveUp for HL404117+5.p
68251.78/9746.68	% SZS status Ended for HL404117+5.p
68313.14/9754.47	% SZS status Started for HL404119+5.p
68313.14/9754.47	% SZS status GaveUp for HL404119+5.p
68313.14/9754.47	% SZS status Ended for HL404119+5.p
68318.70/9755.11	% SZS status Started for HL404115+4.p
68318.70/9755.11	% SZS status GaveUp for HL404115+4.p
68318.70/9755.11	eprover: CPU time limit exceeded, terminating
68318.70/9755.11	% SZS status Ended for HL404115+4.p
68326.12/9756.01	% SZS status Started for HL404120+5.p
68326.12/9756.01	% SZS status GaveUp for HL404120+5.p
68326.12/9756.01	% SZS status Ended for HL404120+5.p
68345.40/9758.51	% SZS status Started for HL404116+4.p
68345.40/9758.51	% SZS status GaveUp for HL404116+4.p
68345.40/9758.51	eprover: CPU time limit exceeded, terminating
68345.40/9758.51	% SZS status Ended for HL404116+4.p
68377.78/9762.53	% SZS status Started for HL404117+4.p
68377.78/9762.53	% SZS status GaveUp for HL404117+4.p
68377.78/9762.53	eprover: CPU time limit exceeded, terminating
68377.78/9762.53	% SZS status Ended for HL404117+4.p
68388.89/9764.05	% SZS status Started for HL404118+4.p
68388.89/9764.05	% SZS status GaveUp for HL404118+4.p
68388.89/9764.05	eprover: CPU time limit exceeded, terminating
68388.89/9764.05	% SZS status Ended for HL404118+4.p
68391.44/9764.25	% SZS status Started for HL404121+5.p
68391.44/9764.25	% SZS status GaveUp for HL404121+5.p
68391.44/9764.25	% SZS status Ended for HL404121+5.p
68410.62/9766.72	% SZS status Started for HL404119+4.p
68410.62/9766.72	% SZS status GaveUp for HL404119+4.p
68410.62/9766.72	eprover: CPU time limit exceeded, terminating
68410.62/9766.72	% SZS status Ended for HL404119+4.p
68419.91/9767.92	% SZS status Started for HL404122+5.p
68419.91/9767.92	% SZS status GaveUp for HL404122+5.p
68419.91/9767.92	% SZS status Ended for HL404122+5.p
68452.47/9772.05	% SZS status Started for HL404120+4.p
68452.47/9772.05	% SZS status GaveUp for HL404120+4.p
68452.47/9772.05	eprover: CPU time limit exceeded, terminating
68452.47/9772.05	% SZS status Ended for HL404120+4.p
68486.55/9773.13	% SZS status Started for HL404123+5.p
68486.55/9773.13	% SZS status GaveUp for HL404123+5.p
68486.55/9773.13	% SZS status Ended for HL404123+5.p
68509.15/9776.00	% SZS status Started for HL404124+5.p
68509.15/9776.00	% SZS status GaveUp for HL404124+5.p
68509.15/9776.00	% SZS status Ended for HL404124+5.p
68549.13/9781.01	% SZS status Started for HL404121+4.p
68549.13/9781.01	% SZS status GaveUp for HL404121+4.p
68549.13/9781.01	eprover: CPU time limit exceeded, terminating
68549.13/9781.01	% SZS status Ended for HL404121+4.p
68549.98/9781.21	% SZS status Started for HL404126+5.p
68549.98/9781.21	% SZS status GaveUp for HL404126+5.p
68549.98/9781.21	% SZS status Ended for HL404126+5.p
68556.70/9782.00	% SZS status Started for HL404122+4.p
68556.70/9782.00	% SZS status GaveUp for HL404122+4.p
68556.70/9782.00	eprover: CPU time limit exceeded, terminating
68556.70/9782.00	% SZS status Ended for HL404122+4.p
68581.85/9785.14	% SZS status Started for HL404127+5.p
68581.85/9785.14	% SZS status GaveUp for HL404127+5.p
68581.85/9785.14	% SZS status Ended for HL404127+5.p
68608.02/9788.46	% SZS status Started for HL404123+4.p
68608.02/9788.46	% SZS status GaveUp for HL404123+4.p
68608.02/9788.46	eprover: CPU time limit exceeded, terminating
68608.02/9788.46	% SZS status Ended for HL404123+4.p
68621.09/9790.12	% SZS status Started for HL404124+4.p
68621.09/9790.12	% SZS status GaveUp for HL404124+4.p
68621.09/9790.12	eprover: CPU time limit exceeded, terminating
68621.09/9790.12	% SZS status Ended for HL404124+4.p
68621.88/9790.34	% SZS status Started for HL404128+5.p
68621.88/9790.34	% SZS status GaveUp for HL404128+5.p
68621.88/9790.34	% SZS status Ended for HL404128+5.p
68650.97/9793.83	% SZS status Started for HL404126+4.p
68650.97/9793.83	% SZS status GaveUp for HL404126+4.p
68650.97/9793.83	eprover: CPU time limit exceeded, terminating
68650.97/9793.83	% SZS status Ended for HL404126+4.p
68652.49/9794.09	% SZS status Started for HL404129+5.p
68652.49/9794.09	% SZS status GaveUp for HL404129+5.p
68652.49/9794.09	% SZS status Ended for HL404129+5.p
68692.54/9799.14	% SZS status Started for HL404127+4.p
68692.54/9799.14	% SZS status GaveUp for HL404127+4.p
68692.54/9799.14	eprover: CPU time limit exceeded, terminating
68692.54/9799.14	% SZS status Ended for HL404127+4.p
68692.54/9799.15	% SZS status Started for HL404130+5.p
68692.54/9799.15	% SZS status GaveUp for HL404130+5.p
68692.54/9799.15	% SZS status Ended for HL404130+5.p
68723.84/9803.00	% SZS status Started for HL404131+5.p
68723.84/9803.00	% SZS status GaveUp for HL404131+5.p
68723.84/9803.00	% SZS status Ended for HL404131+5.p
68755.57/9807.02	% SZS status Started for HL404128+4.p
68755.57/9807.02	% SZS status GaveUp for HL404128+4.p
68755.57/9807.02	eprover: CPU time limit exceeded, terminating
68755.57/9807.02	% SZS status Ended for HL404128+4.p
68763.22/9808.01	% SZS status Started for HL404129+4.p
68763.22/9808.01	% SZS status GaveUp for HL404129+4.p
68763.22/9808.01	eprover: CPU time limit exceeded, terminating
68763.22/9808.01	% SZS status Ended for HL404129+4.p
68769.09/9808.77	% SZS status Started for HL404132+5.p
68769.09/9808.77	% SZS status GaveUp for HL404132+5.p
68769.09/9808.77	% SZS status Ended for HL404132+5.p
68781.38/9810.26	% SZS status Started for HL404133+4.p
68781.38/9810.26	% SZS status GaveUp for HL404133+4.p
68781.38/9810.26	eprover: CPU time limit exceeded, terminating
68781.38/9810.26	% SZS status Ended for HL404133+4.p
68799.57/9812.58	% SZS status Started for HL404133+5.p
68799.57/9812.58	% SZS status GaveUp for HL404133+5.p
68799.57/9812.58	% SZS status Ended for HL404133+5.p
68812.56/9814.23	% SZS status Started for HL404130+4.p
68812.56/9814.23	% SZS status GaveUp for HL404130+4.p
68812.56/9814.23	eprover: CPU time limit exceeded, terminating
68812.56/9814.23	% SZS status Ended for HL404130+4.p
68831.37/9816.55	% SZS status Started for HL404131+4.p
68831.37/9816.55	% SZS status GaveUp for HL404131+4.p
68831.37/9816.55	eprover: CPU time limit exceeded, terminating
68831.37/9816.55	% SZS status Ended for HL404131+4.p
68839.18/9817.58	% SZS status Started for HL404134+5.p
68839.18/9817.58	% SZS status GaveUp for HL404134+5.p
68839.18/9817.58	% SZS status Ended for HL404134+5.p
68839.18/9817.61	% SZS status Started for HL404134+4.p
68839.18/9817.61	% SZS status GaveUp for HL404134+4.p
68839.18/9817.61	eprover: CPU time limit exceeded, terminating
68839.18/9817.61	% SZS status Ended for HL404134+4.p
68852.54/9819.35	% SZS status Started for HL404135+4.p
68852.54/9819.35	% SZS status GaveUp for HL404135+4.p
68852.54/9819.35	eprover: CPU time limit exceeded, terminating
68852.54/9819.35	% SZS status Ended for HL404135+4.p
68857.43/9819.84	% SZS status Started for HL404135+5.p
68857.43/9819.84	% SZS status GaveUp for HL404135+5.p
68857.43/9819.84	% SZS status Ended for HL404135+5.p
68860.24/9820.18	% SZS status Started for HL404132+4.p
68860.24/9820.18	% SZS status GaveUp for HL404132+4.p
68860.24/9820.18	eprover: CPU time limit exceeded, terminating
68860.24/9820.18	% SZS status Ended for HL404132+4.p
68883.87/9823.15	% SZS status Started for HL404136+4.p
68883.87/9823.15	% SZS status GaveUp for HL404136+4.p
68883.87/9823.15	eprover: CPU time limit exceeded, terminating
68883.87/9823.15	% SZS status Ended for HL404136+4.p
68887.85/9823.75	% SZS status Started for HL404136+5.p
68887.85/9823.75	% SZS status GaveUp for HL404136+5.p
68887.85/9823.75	% SZS status Ended for HL404136+5.p
68913.29/9826.86	% SZS status Started for HL404137+4.p
68913.29/9826.86	% SZS status GaveUp for HL404137+4.p
68913.29/9826.86	eprover: CPU time limit exceeded, terminating
68913.29/9826.86	% SZS status Ended for HL404137+4.p
68913.93/9826.96	% SZS status Started for HL404137+5.p
68913.93/9826.96	% SZS status GaveUp for HL404137+5.p
68913.93/9826.96	% SZS status Ended for HL404137+5.p
68926.27/9828.49	% SZS status Started for HL404139+5.p
68926.27/9828.49	% SZS status GaveUp for HL404139+5.p
68926.27/9828.49	% SZS status Ended for HL404139+5.p
68933.38/9829.34	% SZS status Started for HL404140+5.p
68933.38/9829.34	% SZS status GaveUp for HL404140+5.p
68933.38/9829.34	% SZS status Ended for HL404140+5.p
68961.42/9832.96	% SZS status Started for HL404141+5.p
68961.42/9832.96	% SZS status GaveUp for HL404141+5.p
68961.42/9832.96	% SZS status Ended for HL404141+5.p
68986.82/9836.14	% SZS status Started for HL404142+5.p
68986.82/9836.14	% SZS status GaveUp for HL404142+5.p
68986.82/9836.14	% SZS status Ended for HL404142+5.p
69006.78/9838.65	% SZS status Started for HL404144+5.p
69006.78/9838.65	% SZS status GaveUp for HL404144+5.p
69006.78/9838.65	% SZS status Ended for HL404144+5.p
69047.04/9843.70	% SZS status Started for HL404139+4.p
69047.04/9843.70	% SZS status GaveUp for HL404139+4.p
69047.04/9843.70	eprover: CPU time limit exceeded, terminating
69047.04/9843.70	% SZS status Ended for HL404139+4.p
69059.95/9845.32	% SZS status Started for HL404145+5.p
69059.95/9845.32	% SZS status GaveUp for HL404145+5.p
69059.95/9845.32	% SZS status Ended for HL404145+5.p
69063.97/9845.87	% SZS status Started for HL404140+4.p
69063.97/9845.87	% SZS status GaveUp for HL404140+4.p
69063.97/9845.87	eprover: CPU time limit exceeded, terminating
69063.97/9845.87	% SZS status Ended for HL404140+4.p
69088.02/9848.90	% SZS status Started for HL404141+4.p
69088.02/9848.90	% SZS status GaveUp for HL404141+4.p
69088.02/9848.90	eprover: CPU time limit exceeded, terminating
69088.02/9848.90	% SZS status Ended for HL404141+4.p
69118.05/9852.68	% SZS status Started for HL404142+4.p
69118.05/9852.68	% SZS status GaveUp for HL404142+4.p
69118.05/9852.68	eprover: CPU time limit exceeded, terminating
69118.05/9852.68	% SZS status Ended for HL404142+4.p
69120.09/9852.89	% SZS status Started for HL404146+5.p
69120.09/9852.89	% SZS status GaveUp for HL404146+5.p
69120.09/9852.89	% SZS status Ended for HL404146+5.p
69131.60/9854.32	% SZS status Started for HL404144+4.p
69131.60/9854.32	% SZS status GaveUp for HL404144+4.p
69131.60/9854.32	eprover: CPU time limit exceeded, terminating
69131.60/9854.32	% SZS status Ended for HL404144+4.p
69138.08/9855.15	% SZS status Started for HL404147+5.p
69138.08/9855.15	% SZS status GaveUp for HL404147+5.p
69138.08/9855.15	% SZS status Ended for HL404147+5.p
69171.31/9859.41	% SZS status Started for HL404145+4.p
69171.31/9859.41	% SZS status GaveUp for HL404145+4.p
69171.31/9859.41	eprover: CPU time limit exceeded, terminating
69171.31/9859.41	% SZS status Ended for HL404145+4.p
69189.82/9861.83	% SZS status Started for HL404148+5.p
69189.82/9861.83	% SZS status GaveUp for HL404148+5.p
69189.82/9861.83	% SZS status Ended for HL404148+5.p
69204.41/9863.49	% SZS status Started for HL404149+5.p
69204.41/9863.49	% SZS status GaveUp for HL404149+5.p
69204.41/9863.49	% SZS status Ended for HL404149+5.p
69213.05/9864.61	% SZS status Started for HL404146+4.p
69213.05/9864.61	% SZS status GaveUp for HL404146+4.p
69213.05/9864.61	eprover: CPU time limit exceeded, terminating
69213.05/9864.61	% SZS status Ended for HL404146+4.p
69245.80/9868.69	% SZS status Started for HL404150+5.p
69245.80/9868.69	% SZS status GaveUp for HL404150+5.p
69245.80/9868.69	% SZS status Ended for HL404150+5.p
69266.39/9871.29	% SZS status Started for HL404147+4.p
69266.39/9871.29	% SZS status GaveUp for HL404147+4.p
69266.39/9871.29	eprover: CPU time limit exceeded, terminating
69266.39/9871.29	% SZS status Ended for HL404147+4.p
69279.38/9872.75	% SZS status Started for HL404151+5.p
69279.38/9872.75	% SZS status GaveUp for HL404151+5.p
69279.38/9872.75	% SZS status Ended for HL404151+5.p
69297.46/9874.95	% SZS status Started for HL404148+4.p
69297.46/9874.95	% SZS status GaveUp for HL404148+4.p
69297.46/9874.95	eprover: CPU time limit exceeded, terminating
69297.46/9874.95	% SZS status Ended for HL404148+4.p
69318.29/9877.62	% SZS status Started for HL404152+5.p
69318.29/9877.62	% SZS status GaveUp for HL404152+5.p
69318.29/9877.62	% SZS status Ended for HL404152+5.p
69328.95/9878.95	% SZS status Started for HL404149+4.p
69328.95/9878.95	% SZS status GaveUp for HL404149+4.p
69328.95/9878.95	eprover: CPU time limit exceeded, terminating
69328.95/9878.95	% SZS status Ended for HL404149+4.p
69344.42/9880.99	% SZS status Started for HL404150+4.p
69344.42/9880.99	% SZS status GaveUp for HL404150+4.p
69344.42/9880.99	eprover: CPU time limit exceeded, terminating
69344.42/9880.99	% SZS status Ended for HL404150+4.p
69352.87/9882.03	% SZS status Started for HL404153+5.p
69352.87/9882.03	% SZS status GaveUp for HL404153+5.p
69352.87/9882.03	% SZS status Ended for HL404153+5.p
69389.40/9886.56	% SZS status Started for HL404155+5.p
69389.40/9886.56	% SZS status GaveUp for HL404155+5.p
69389.40/9886.56	% SZS status Ended for HL404155+5.p
69398.11/9887.68	% SZS status Started for HL404151+4.p
69398.11/9887.68	% SZS status GaveUp for HL404151+4.p
69398.11/9887.68	eprover: CPU time limit exceeded, terminating
69398.11/9887.68	% SZS status Ended for HL404151+4.p
69419.30/9890.30	% SZS status Started for HL404156+5.p
69419.30/9890.30	% SZS status GaveUp for HL404156+5.p
69419.30/9890.30	% SZS status Ended for HL404156+5.p
69420.99/9890.55	% SZS status Started for HL404152+4.p
69420.99/9890.55	% SZS status GaveUp for HL404152+4.p
69420.99/9890.55	eprover: CPU time limit exceeded, terminating
69420.99/9890.55	% SZS status Ended for HL404152+4.p
69462.70/9895.81	% SZS status Started for HL404158+5.p
69462.70/9895.81	% SZS status GaveUp for HL404158+5.p
69462.70/9895.81	% SZS status Ended for HL404158+5.p
69473.60/9897.16	% SZS status Started for HL404153+4.p
69473.60/9897.16	% SZS status GaveUp for HL404153+4.p
69473.60/9897.16	eprover: CPU time limit exceeded, terminating
69473.60/9897.16	% SZS status Ended for HL404153+4.p
69491.79/9899.47	% SZS status Started for HL404159+5.p
69491.79/9899.47	% SZS status GaveUp for HL404159+5.p
69491.79/9899.47	% SZS status Ended for HL404159+5.p
69503.81/9900.97	% SZS status Started for HL404155+4.p
69503.81/9900.97	% SZS status GaveUp for HL404155+4.p
69503.81/9900.97	eprover: CPU time limit exceeded, terminating
69503.81/9900.97	% SZS status Ended for HL404155+4.p
69535.07/9904.96	% SZS status Started for HL404156+4.p
69535.07/9904.96	% SZS status GaveUp for HL404156+4.p
69535.07/9904.96	eprover: CPU time limit exceeded, terminating
69535.07/9904.96	% SZS status Ended for HL404156+4.p
69535.40/9905.12	% SZS status Started for HL404160+5.p
69535.40/9905.12	% SZS status GaveUp for HL404160+5.p
69535.40/9905.12	% SZS status Ended for HL404160+5.p
69558.11/9907.81	% SZS status Started for HL404158+4.p
69558.11/9907.81	% SZS status GaveUp for HL404158+4.p
69558.11/9907.81	eprover: CPU time limit exceeded, terminating
69558.11/9907.81	% SZS status Ended for HL404158+4.p
69566.49/9908.88	% SZS status Started for HL404161+5.p
69566.49/9908.88	% SZS status GaveUp for HL404161+5.p
69566.49/9908.88	% SZS status Ended for HL404161+5.p
69585.71/9911.31	% SZS status Started for HL404162+4.p
69585.71/9911.31	% SZS status GaveUp for HL404162+4.p
69585.71/9911.31	eprover: CPU time limit exceeded, terminating
69585.71/9911.31	% SZS status Ended for HL404162+4.p
69603.26/9913.48	% SZS status Started for HL404159+4.p
69603.26/9913.48	% SZS status GaveUp for HL404159+4.p
69603.26/9913.48	eprover: CPU time limit exceeded, terminating
69603.26/9913.48	% SZS status Ended for HL404159+4.p
69607.96/9914.14	% SZS status Started for HL404162+5.p
69607.96/9914.14	% SZS status GaveUp for HL404162+5.p
69607.96/9914.14	% SZS status Ended for HL404162+5.p
69630.77/9916.95	% SZS status Started for HL404160+4.p
69630.77/9916.95	% SZS status GaveUp for HL404160+4.p
69630.77/9916.95	eprover: CPU time limit exceeded, terminating
69630.77/9916.95	% SZS status Ended for HL404160+4.p
69631.46/9917.05	% SZS status Started for HL404163+5.p
69631.46/9917.05	% SZS status GaveUp for HL404163+5.p
69631.46/9917.05	% SZS status Ended for HL404163+5.p
69660.20/9920.67	% SZS status Started for HL404164+5.p
69660.20/9920.67	% SZS status GaveUp for HL404164+5.p
69660.20/9920.67	% SZS status Ended for HL404164+5.p
69679.59/9923.13	% SZS status Started for HL404161+4.p
69679.59/9923.13	% SZS status GaveUp for HL404161+4.p
69679.59/9923.13	eprover: CPU time limit exceeded, terminating
69679.59/9923.13	% SZS status Ended for HL404161+4.p
69681.13/9923.37	% SZS status Started for HL404165+5.p
69681.13/9923.37	% SZS status GaveUp for HL404165+5.p
69681.13/9923.37	% SZS status Ended for HL404165+5.p
69704.98/9926.32	% SZS status Started for HL404166+5.p
69704.98/9926.32	% SZS status GaveUp for HL404166+5.p
69704.98/9926.32	% SZS status Ended for HL404166+5.p
69743.77/9931.22	% SZS status Started for HL404163+4.p
69743.77/9931.22	% SZS status GaveUp for HL404163+4.p
69743.77/9931.22	eprover: CPU time limit exceeded, terminating
69743.77/9931.22	% SZS status Ended for HL404163+4.p
69754.40/9932.58	% SZS status Started for HL404167+5.p
69754.40/9932.58	% SZS status GaveUp for HL404167+5.p
69754.40/9932.58	% SZS status Ended for HL404167+5.p
69771.25/9934.72	% SZS status Started for HL404164+4.p
69771.25/9934.72	% SZS status GaveUp for HL404164+4.p
69771.25/9934.72	eprover: CPU time limit exceeded, terminating
69771.25/9934.72	% SZS status Ended for HL404164+4.p
69777.77/9935.50	% SZS status Started for HL404168+5.p
69777.77/9935.50	% SZS status GaveUp for HL404168+5.p
69777.77/9935.50	% SZS status Ended for HL404168+5.p
69807.95/9939.29	% SZS status Started for HL404165+4.p
69807.95/9939.29	% SZS status GaveUp for HL404165+4.p
69807.95/9939.29	eprover: CPU time limit exceeded, terminating
69807.95/9939.29	% SZS status Ended for HL404165+4.p
69827.82/9941.85	% SZS status Started for HL404169+5.p
69827.82/9941.85	% SZS status GaveUp for HL404169+5.p
69827.82/9941.85	% SZS status Ended for HL404169+5.p
69836.27/9942.86	% SZS status Started for HL404166+4.p
69836.27/9942.86	% SZS status GaveUp for HL404166+4.p
69836.27/9942.86	eprover: CPU time limit exceeded, terminating
69836.27/9942.86	% SZS status Ended for HL404166+4.p
69851.27/9944.72	% SZS status Started for HL404170+5.p
69851.27/9944.72	% SZS status GaveUp for HL404170+5.p
69851.27/9944.72	% SZS status Ended for HL404170+5.p
69871.28/9947.31	% SZS status Started for HL404167+4.p
69871.28/9947.31	% SZS status GaveUp for HL404167+4.p
69871.28/9947.31	eprover: CPU time limit exceeded, terminating
69871.28/9947.31	% SZS status Ended for HL404167+4.p
69887.47/9949.27	% SZS status Started for HL404168+4.p
69887.47/9949.27	% SZS status GaveUp for HL404168+4.p
69887.47/9949.27	eprover: CPU time limit exceeded, terminating
69887.47/9949.27	% SZS status Ended for HL404168+4.p
69900.79/9951.00	% SZS status Started for HL404171+5.p
69900.79/9951.00	% SZS status GaveUp for HL404171+5.p
69900.79/9951.00	% SZS status Ended for HL404171+5.p
69923.66/9953.86	% SZS status Started for HL404172+5.p
69923.66/9953.86	% SZS status GaveUp for HL404172+5.p
69923.66/9953.86	% SZS status Ended for HL404172+5.p
69948.46/9956.98	% SZS status Started for HL404169+4.p
69948.46/9956.98	% SZS status GaveUp for HL404169+4.p
69948.46/9956.98	eprover: CPU time limit exceeded, terminating
69948.46/9956.98	% SZS status Ended for HL404169+4.p
69961.38/9958.60	% SZS status Started for HL404173+5.p
69961.38/9958.60	% SZS status GaveUp for HL404173+5.p
69961.38/9958.60	% SZS status Ended for HL404173+5.p
69978.61/9960.76	% SZS status Started for HL404170+4.p
69978.61/9960.76	% SZS status GaveUp for HL404170+4.p
69978.61/9960.76	eprover: CPU time limit exceeded, terminating
69978.61/9960.76	% SZS status Ended for HL404170+4.p
69996.74/9963.10	% SZS status Started for HL404175+5.p
69996.74/9963.10	% SZS status GaveUp for HL404175+5.p
69996.74/9963.10	% SZS status Ended for HL404175+5.p
70013.37/9965.13	% SZS status Started for HL404171+4.p
70013.37/9965.13	% SZS status GaveUp for HL404171+4.p
70013.37/9965.13	eprover: CPU time limit exceeded, terminating
70013.37/9965.13	% SZS status Ended for HL404171+4.p
70034.84/9967.89	% SZS status Started for HL404176+5.p
70034.84/9967.89	% SZS status GaveUp for HL404176+5.p
70034.84/9967.89	% SZS status Ended for HL404176+5.p
70043.01/9968.86	% SZS status Started for HL404172+4.p
70043.01/9968.86	% SZS status GaveUp for HL404172+4.p
70043.01/9968.86	eprover: CPU time limit exceeded, terminating
70043.01/9968.86	% SZS status Ended for HL404172+4.p
70070.60/9972.37	% SZS status Started for HL404177+5.p
70070.60/9972.37	% SZS status GaveUp for HL404177+5.p
70070.60/9972.37	% SZS status Ended for HL404177+5.p
70079.13/9973.39	% SZS status Started for HL404173+4.p
70079.13/9973.39	% SZS status GaveUp for HL404173+4.p
70079.13/9973.39	eprover: CPU time limit exceeded, terminating
70079.13/9973.39	% SZS status Ended for HL404173+4.p
70105.31/9976.85	% SZS status Started for HL404175+4.p
70105.31/9976.85	% SZS status GaveUp for HL404175+4.p
70105.31/9976.85	eprover: CPU time limit exceeded, terminating
70105.31/9976.85	% SZS status Ended for HL404175+4.p
70110.98/9977.39	% SZS status Started for HL404178+5.p
70110.98/9977.39	% SZS status GaveUp for HL404178+5.p
70110.98/9977.39	% SZS status Ended for HL404178+5.p
70144.68/9981.62	% SZS status Started for HL404179+5.p
70144.68/9981.62	% SZS status GaveUp for HL404179+5.p
70144.68/9981.62	% SZS status Ended for HL404179+5.p
70154.73/9982.97	% SZS status Started for HL404176+4.p
70154.73/9982.97	% SZS status GaveUp for HL404176+4.p
70154.73/9982.97	eprover: CPU time limit exceeded, terminating
70154.73/9982.97	% SZS status Ended for HL404176+4.p
70179.00/9985.97	% SZS status Started for HL404180+5.p
70179.00/9985.97	% SZS status GaveUp for HL404180+5.p
70179.00/9985.97	% SZS status Ended for HL404180+5.p
70183.96/9986.61	% SZS status Started for HL404177+4.p
70183.96/9986.61	% SZS status GaveUp for HL404177+4.p
70183.96/9986.61	eprover: CPU time limit exceeded, terminating
70183.96/9986.61	% SZS status Ended for HL404177+4.p
70217.24/9990.77	% SZS status Started for HL404181+5.p
70217.24/9990.77	% SZS status GaveUp for HL404181+5.p
70217.24/9990.77	% SZS status Ended for HL404181+5.p
70221.55/9991.38	% SZS status Started for HL404178+4.p
70221.55/9991.38	% SZS status GaveUp for HL404178+4.p
70221.55/9991.38	eprover: CPU time limit exceeded, terminating
70221.55/9991.38	% SZS status Ended for HL404178+4.p
70251.14/9995.05	% SZS status Started for HL404179+4.p
70251.14/9995.05	% SZS status GaveUp for HL404179+4.p
70251.14/9995.05	eprover: CPU time limit exceeded, terminating
70251.14/9995.05	% SZS status Ended for HL404179+4.p
70251.50/9995.13	% SZS status Started for HL404182+5.p
70251.50/9995.13	% SZS status GaveUp for HL404182+5.p
70251.50/9995.13	% SZS status Ended for HL404182+5.p
70284.23/9999.21	% SZS status Started for HL404180+4.p
70284.23/9999.21	% SZS status GaveUp for HL404180+4.p
70284.23/9999.21	eprover: CPU time limit exceeded, terminating
70284.23/9999.21	% SZS status Ended for HL404180+4.p
70290.12/10000.01	% SZS status Started for HL404183+5.p
70290.12/10000.01	% SZS status GaveUp for HL404183+5.p
70290.12/10000.01	% SZS status Ended for HL404183+5.p
70316.30/10003.26	% SZS status Started for HL404181+4.p
70316.30/10003.26	% SZS status GaveUp for HL404181+4.p
70316.30/10003.26	eprover: CPU time limit exceeded, terminating
70316.30/10003.26	% SZS status Ended for HL404181+4.p
70323.89/10004.19	% SZS status Started for HL404184+5.p
70323.89/10004.19	% SZS status GaveUp for HL404184+5.p
70323.89/10004.19	% SZS status Ended for HL404184+5.p
70357.05/10008.38	% SZS status Started for HL404185+5.p
70357.05/10008.38	% SZS status GaveUp for HL404185+5.p
70357.05/10008.38	% SZS status Ended for HL404185+5.p
70360.05/10008.77	% SZS status Started for HL404182+4.p
70360.05/10008.77	% SZS status GaveUp for HL404182+4.p
70360.05/10008.77	eprover: CPU time limit exceeded, terminating
70360.05/10008.77	% SZS status Ended for HL404182+4.p
70373.09/10010.43	% SZS status Started for HL404186+4.p
70373.09/10010.43	% SZS status GaveUp for HL404186+4.p
70373.09/10010.43	eprover: CPU time limit exceeded, terminating
70373.09/10010.43	% SZS status Ended for HL404186+4.p
70390.91/10012.59	% SZS status Started for HL404186+5.p
70390.91/10012.59	% SZS status GaveUp for HL404186+5.p
70390.91/10012.59	% SZS status Ended for HL404186+5.p
70390.97/10012.61	% SZS status Started for HL404183+4.p
70390.97/10012.61	% SZS status GaveUp for HL404183+4.p
70390.97/10012.61	eprover: CPU time limit exceeded, terminating
70390.97/10012.61	% SZS status Ended for HL404183+4.p
70428.12/10017.31	% SZS status Started for HL404184+4.p
70428.12/10017.31	% SZS status GaveUp for HL404184+4.p
70428.12/10017.31	eprover: CPU time limit exceeded, terminating
70428.12/10017.31	% SZS status Ended for HL404184+4.p
70428.80/10017.45	% SZS status Started for HL404187+5.p
70428.80/10017.45	% SZS status GaveUp for HL404187+5.p
70428.80/10017.45	% SZS status Ended for HL404187+5.p
70445.62/10019.50	% SZS status Started for HL404188+5.p
70445.62/10019.50	% SZS status GaveUp for HL404188+5.p
70445.62/10019.50	% SZS status Ended for HL404188+5.p
70458.20/10021.11	% SZS status Started for HL404185+4.p
70458.20/10021.11	% SZS status GaveUp for HL404185+4.p
70458.20/10021.11	eprover: CPU time limit exceeded, terminating
70458.20/10021.11	% SZS status Ended for HL404185+4.p
70463.62/10021.85	% SZS status Started for HL404191+5.p
70463.62/10021.85	% SZS status GaveUp for HL404191+5.p
70463.62/10021.85	% SZS status Ended for HL404191+5.p
70500.91/10026.56	% SZS status Started for HL404192+5.p
70500.91/10026.56	% SZS status GaveUp for HL404192+5.p
70500.91/10026.56	% SZS status Ended for HL404192+5.p
70530.32/10030.19	% SZS status Started for HL404187+4.p
70530.32/10030.19	% SZS status GaveUp for HL404187+4.p
70530.32/10030.19	eprover: CPU time limit exceeded, terminating
70530.32/10030.19	% SZS status Ended for HL404187+4.p
70530.96/10030.25	% SZS status Started for HL404194+5.p
70530.96/10030.25	% SZS status GaveUp for HL404194+5.p
70530.96/10030.25	% SZS status Ended for HL404194+5.p
70566.00/10034.61	% SZS status Started for HL404188+4.p
70566.00/10034.61	% SZS status GaveUp for HL404188+4.p
70566.00/10034.61	eprover: CPU time limit exceeded, terminating
70566.00/10034.61	% SZS status Ended for HL404188+4.p
70574.63/10035.76	% SZS status Started for HL404195+5.p
70574.63/10035.76	% SZS status GaveUp for HL404195+5.p
70574.63/10035.76	% SZS status Ended for HL404195+5.p
70596.27/10038.44	% SZS status Started for HL404191+4.p
70596.27/10038.44	% SZS status GaveUp for HL404191+4.p
70596.27/10038.44	eprover: CPU time limit exceeded, terminating
70596.27/10038.44	% SZS status Ended for HL404191+4.p
70604.08/10039.40	% SZS status Started for HL404196+5.p
70604.08/10039.40	% SZS status GaveUp for HL404196+5.p
70604.08/10039.40	% SZS status Ended for HL404196+5.p
70633.45/10043.13	% SZS status Started for HL404192+4.p
70633.45/10043.13	% SZS status GaveUp for HL404192+4.p
70633.45/10043.13	eprover: CPU time limit exceeded, terminating
70633.45/10043.13	% SZS status Ended for HL404192+4.p
70647.69/10044.91	% SZS status Started for HL404197+5.p
70647.69/10044.91	% SZS status GaveUp for HL404197+5.p
70647.69/10044.91	% SZS status Ended for HL404197+5.p
70651.67/10045.45	% SZS status Started for HL404194+4.p
70651.67/10045.45	% SZS status GaveUp for HL404194+4.p
70651.67/10045.45	eprover: CPU time limit exceeded, terminating
70651.67/10045.45	% SZS status Ended for HL404194+4.p
70671.81/10047.93	% SZS status Started for HL404195+4.p
70671.81/10047.93	% SZS status GaveUp for HL404195+4.p
70671.81/10047.93	eprover: CPU time limit exceeded, terminating
70671.81/10047.93	% SZS status Ended for HL404195+4.p
70674.49/10048.31	% SZS status Started for HL404198+5.p
70674.49/10048.31	% SZS status GaveUp for HL404198+5.p
70674.49/10048.31	% SZS status Ended for HL404198+5.p
70737.70/10055.98	% SZS status Started for HL404196+4.p
70737.70/10055.98	% SZS status GaveUp for HL404196+4.p
70737.70/10055.98	eprover: CPU time limit exceeded, terminating
70737.70/10055.98	% SZS status Ended for HL404196+4.p
70737.70/10056.04	% SZS status Started for HL404199+5.p
70737.70/10056.04	% SZS status GaveUp for HL404199+5.p
70737.70/10056.04	% SZS status Ended for HL404199+5.p
70756.49/10058.67	% SZS status Started for HL404200+5.p
70756.49/10058.67	% SZS status GaveUp for HL404200+5.p
70756.49/10058.67	% SZS status Ended for HL404200+5.p
70777.27/10061.36	% SZS status Started for HL404197+4.p
70777.27/10061.36	% SZS status GaveUp for HL404197+4.p
70777.27/10061.36	eprover: CPU time limit exceeded, terminating
70777.27/10061.36	% SZS status Ended for HL404197+4.p
70813.00/10066.03	% SZS status Started for HL404198+4.p
70813.00/10066.03	% SZS status GaveUp for HL404198+4.p
70813.00/10066.03	eprover: CPU time limit exceeded, terminating
70813.00/10066.03	% SZS status Ended for HL404198+4.p
70817.91/10066.73	% SZS status Started for HL404202+5.p
70817.91/10066.73	% SZS status GaveUp for HL404202+5.p
70817.91/10066.73	% SZS status Ended for HL404202+5.p
70825.23/10067.73	% SZS status Started for HL404203+4.p
70825.23/10067.73	% SZS status GaveUp for HL404203+4.p
70825.23/10067.73	eprover: CPU time limit exceeded, terminating
70825.23/10067.73	% SZS status Ended for HL404203+4.p
70832.72/10068.62	% SZS status Started for HL404203+5.p
70832.72/10068.62	% SZS status GaveUp for HL404203+5.p
70832.72/10068.62	% SZS status Ended for HL404203+5.p
70840.16/10069.67	% SZS status Started for HL404199+4.p
70840.16/10069.67	% SZS status GaveUp for HL404199+4.p
70840.16/10069.67	eprover: CPU time limit exceeded, terminating
70840.16/10069.67	% SZS status Ended for HL404199+4.p
70864.34/10072.80	% SZS status Started for HL404200+4.p
70864.34/10072.80	% SZS status GaveUp for HL404200+4.p
70864.34/10072.80	eprover: CPU time limit exceeded, terminating
70864.34/10072.80	% SZS status Ended for HL404200+4.p
70865.05/10072.95	% SZS status Started for HL404204+4.p
70865.05/10072.95	% SZS status GaveUp for HL404204+4.p
70865.05/10072.95	eprover: CPU time limit exceeded, terminating
70865.05/10072.95	% SZS status Ended for HL404204+4.p
70883.94/10075.52	% SZS status Started for HL404202+4.p
70883.94/10075.52	% SZS status GaveUp for HL404202+4.p
70883.94/10075.52	eprover: CPU time limit exceeded, terminating
70883.94/10075.52	% SZS status Ended for HL404202+4.p
70890.53/10076.34	% SZS status Started for HL404204+5.p
70890.53/10076.34	% SZS status GaveUp for HL404204+5.p
70890.53/10076.34	% SZS status Ended for HL404204+5.p
70903.04/10078.02	% SZS status Started for HL404206+4.p
70903.04/10078.02	% SZS status GaveUp for HL404206+4.p
70903.04/10078.02	eprover: CPU time limit exceeded, terminating
70903.04/10078.02	% SZS status Ended for HL404206+4.p
70905.62/10078.29	% SZS status Started for HL404206+5.p
70905.62/10078.29	% SZS status GaveUp for HL404206+5.p
70905.62/10078.29	% SZS status Ended for HL404206+5.p
70913.95/10079.35	% SZS status Started for HL404207+4.p
70913.95/10079.35	% SZS status GaveUp for HL404207+4.p
70913.95/10079.35	eprover: CPU time limit exceeded, terminating
70913.95/10079.35	% SZS status Ended for HL404207+4.p
70915.72/10079.70	% SZS status Started for HL404207+5.p
70915.72/10079.70	% SZS status GaveUp for HL404207+5.p
70915.72/10079.70	% SZS status Ended for HL404207+5.p
70936.80/10082.31	% SZS status Started for HL404208+5.p
70936.80/10082.31	% SZS status GaveUp for HL404208+5.p
70936.80/10082.31	% SZS status Ended for HL404208+5.p
70945.51/10083.45	% SZS status Started for HL404208+4.p
70945.51/10083.45	% SZS status GaveUp for HL404208+4.p
70945.51/10083.45	eprover: CPU time limit exceeded, terminating
70945.51/10083.45	% SZS status Ended for HL404208+4.p
70962.94/10085.64	% SZS status Started for HL404209+5.p
70962.94/10085.64	% SZS status GaveUp for HL404209+5.p
70962.94/10085.64	% SZS status Ended for HL404209+5.p
70963.99/10085.86	% SZS status Started for HL404209+4.p
70963.99/10085.86	% SZS status GaveUp for HL404209+4.p
70963.99/10085.86	eprover: CPU time limit exceeded, terminating
70963.99/10085.86	% SZS status Ended for HL404209+4.p
70978.71/10087.66	% SZS status Started for HL404210+5.p
70978.71/10087.66	% SZS status GaveUp for HL404210+5.p
70978.71/10087.66	% SZS status Ended for HL404210+5.p
70987.88/10088.71	% SZS status Started for HL404210+4.p
70987.88/10088.71	% SZS status GaveUp for HL404210+4.p
70987.88/10088.71	eprover: CPU time limit exceeded, terminating
70987.88/10088.71	% SZS status Ended for HL404210+4.p
70989.54/10089.03	% SZS status Started for HL404211+5.p
70989.54/10089.03	% SZS status GaveUp for HL404211+5.p
70989.54/10089.03	% SZS status Ended for HL404211+5.p
71018.13/10092.65	% SZS status Started for HL404212+5.p
71018.13/10092.65	% SZS status GaveUp for HL404212+5.p
71018.13/10092.65	% SZS status Ended for HL404212+5.p
71039.37/10095.32	% SZS status Started for HL404214+5.p
71039.37/10095.32	% SZS status GaveUp for HL404214+5.p
71039.37/10095.32	% SZS status Ended for HL404214+5.p
71044.12/10095.96	% SZS status Started for HL404214+4.p
71044.12/10095.96	% SZS status GaveUp for HL404214+4.p
71044.12/10095.96	eprover: CPU time limit exceeded, terminating
71044.12/10095.96	% SZS status Ended for HL404214+4.p
71059.07/10097.88	% SZS status Started for HL404215+5.p
71059.07/10097.88	% SZS status GaveUp for HL404215+5.p
71059.07/10097.88	% SZS status Ended for HL404215+5.p
71090.70/10101.81	% SZS status Started for HL404216+5.p
71090.70/10101.81	% SZS status GaveUp for HL404216+5.p
71090.70/10101.81	% SZS status Ended for HL404216+5.p
71119.02/10105.38	% SZS status Started for HL404217+5.p
71119.02/10105.38	% SZS status GaveUp for HL404217+5.p
71119.02/10105.38	% SZS status Ended for HL404217+5.p
71121.09/10105.71	% SZS status Started for HL404211+4.p
71121.09/10105.71	% SZS status GaveUp for HL404211+4.p
71121.09/10105.71	eprover: CPU time limit exceeded, terminating
71121.09/10105.71	% SZS status Ended for HL404211+4.p
71143.91/10108.54	% SZS status Started for HL404212+4.p
71143.91/10108.54	% SZS status GaveUp for HL404212+4.p
71143.91/10108.54	eprover: CPU time limit exceeded, terminating
71143.91/10108.54	% SZS status Ended for HL404212+4.p
71164.59/10111.19	% SZS status Started for HL404218+5.p
71164.59/10111.19	% SZS status GaveUp for HL404218+5.p
71164.59/10111.19	% SZS status Ended for HL404218+5.p
71182.35/10113.44	% SZS status Started for HL404215+4.p
71182.35/10113.44	% SZS status GaveUp for HL404215+4.p
71182.35/10113.44	eprover: CPU time limit exceeded, terminating
71182.35/10113.44	% SZS status Ended for HL404215+4.p
71192.50/10114.64	% SZS status Started for HL404219+5.p
71192.50/10114.64	% SZS status GaveUp for HL404219+5.p
71192.50/10114.64	% SZS status Ended for HL404219+5.p
71197.32/10115.35	% SZS status Started for HL404216+4.p
71197.32/10115.35	% SZS status GaveUp for HL404216+4.p
71197.32/10115.35	eprover: CPU time limit exceeded, terminating
71197.32/10115.35	% SZS status Ended for HL404216+4.p
71237.58/10120.39	% SZS status Started for HL404221+5.p
71237.58/10120.39	% SZS status GaveUp for HL404221+5.p
71237.58/10120.39	% SZS status Ended for HL404221+5.p
71247.79/10121.61	% SZS status Started for HL404217+4.p
71247.79/10121.61	% SZS status GaveUp for HL404217+4.p
71247.79/10121.61	eprover: CPU time limit exceeded, terminating
71247.79/10121.61	% SZS status Ended for HL404217+4.p
71265.43/10123.84	% SZS status Started for HL404222+5.p
71265.43/10123.84	% SZS status GaveUp for HL404222+5.p
71265.43/10123.84	% SZS status Ended for HL404222+5.p
71266.43/10123.93	% SZS status Started for HL404218+4.p
71266.43/10123.93	% SZS status GaveUp for HL404218+4.p
71266.43/10123.93	eprover: CPU time limit exceeded, terminating
71266.43/10123.93	% SZS status Ended for HL404218+4.p
71310.80/10129.57	% SZS status Started for HL404223+5.p
71310.80/10129.57	% SZS status GaveUp for HL404223+5.p
71310.80/10129.57	% SZS status Ended for HL404223+5.p
71327.41/10131.62	% SZS status Started for HL404219+4.p
71327.41/10131.62	% SZS status GaveUp for HL404219+4.p
71327.41/10131.62	eprover: CPU time limit exceeded, terminating
71327.41/10131.62	% SZS status Ended for HL404219+4.p
71339.46/10133.20	% SZS status Started for HL404224+5.p
71339.46/10133.20	% SZS status GaveUp for HL404224+5.p
71339.46/10133.20	% SZS status Ended for HL404224+5.p
71350.45/10134.52	% SZS status Started for HL404221+4.p
71350.45/10134.52	% SZS status GaveUp for HL404221+4.p
71350.45/10134.52	eprover: CPU time limit exceeded, terminating
71350.45/10134.52	% SZS status Ended for HL404221+4.p
71382.31/10138.51	% SZS status Started for HL404225+5.p
71382.31/10138.51	% SZS status GaveUp for HL404225+5.p
71382.31/10138.51	% SZS status Ended for HL404225+5.p
71389.20/10139.35	% SZS status Started for HL404222+4.p
71389.20/10139.35	% SZS status GaveUp for HL404222+4.p
71389.20/10139.35	eprover: CPU time limit exceeded, terminating
71389.20/10139.35	% SZS status Ended for HL404222+4.p
71403.74/10141.18	% SZS status Started for HL404223+4.p
71403.74/10141.18	% SZS status GaveUp for HL404223+4.p
71403.74/10141.18	eprover: CPU time limit exceeded, terminating
71403.74/10141.18	% SZS status Ended for HL404223+4.p
71410.71/10142.18	% SZS status Started for HL404226+5.p
71410.71/10142.18	% SZS status GaveUp for HL404226+5.p
71410.71/10142.18	% SZS status Ended for HL404226+5.p
71432.93/10144.88	% SZS status Started for HL404227+4.p
71432.93/10144.88	% SZS status GaveUp for HL404227+4.p
71432.93/10144.88	eprover: CPU time limit exceeded, terminating
71432.93/10144.88	% SZS status Ended for HL404227+4.p
71454.64/10147.68	% SZS status Started for HL404227+5.p
71454.64/10147.68	% SZS status GaveUp for HL404227+5.p
71454.64/10147.68	% SZS status Ended for HL404227+5.p
71455.12/10147.78	% SZS status Started for HL404224+4.p
71455.12/10147.78	% SZS status GaveUp for HL404224+4.p
71455.12/10147.78	eprover: CPU time limit exceeded, terminating
71455.12/10147.78	% SZS status Ended for HL404224+4.p
71472.46/10149.83	% SZS status Started for HL404225+4.p
71472.46/10149.83	% SZS status GaveUp for HL404225+4.p
71472.46/10149.83	eprover: CPU time limit exceeded, terminating
71472.46/10149.83	% SZS status Ended for HL404225+4.p
71477.05/10150.48	% SZS status Started for HL404228+5.p
71477.05/10150.48	% SZS status GaveUp for HL404228+5.p
71477.05/10150.48	% SZS status Ended for HL404228+5.p
71506.08/10154.05	% SZS status Started for HL404229+5.p
71506.08/10154.05	% SZS status GaveUp for HL404229+5.p
71506.08/10154.05	% SZS status Ended for HL404229+5.p
71532.61/10157.15	% SZS status Started for HL404230+5.p
71532.61/10157.15	% SZS status GaveUp for HL404230+5.p
71532.61/10157.15	% SZS status Ended for HL404230+5.p
71535.95/10157.51	% SZS status Started for HL404226+4.p
71535.95/10157.51	% SZS status GaveUp for HL404226+4.p
71535.95/10157.51	eprover: CPU time limit exceeded, terminating
71535.95/10157.51	% SZS status Ended for HL404226+4.p
71541.88/10158.28	% SZS status Started for HL404230+4.p
71541.88/10158.28	% SZS status GaveUp for HL404230+4.p
71541.88/10158.28	eprover: CPU time limit exceeded, terminating
71541.88/10158.28	% SZS status Ended for HL404230+4.p
71554.23/10159.82	% SZS status Started for HL404231+5.p
71554.23/10159.82	% SZS status GaveUp for HL404231+5.p
71554.23/10159.82	% SZS status Ended for HL404231+5.p
71598.05/10165.34	% SZS status Started for HL404228+4.p
71598.05/10165.34	% SZS status GaveUp for HL404228+4.p
71598.05/10165.34	eprover: CPU time limit exceeded, terminating
71598.05/10165.34	% SZS status Ended for HL404228+4.p
71605.90/10166.38	% SZS status Started for HL404234+5.p
71605.90/10166.38	% SZS status GaveUp for HL404234+5.p
71605.90/10166.38	% SZS status Ended for HL404234+5.p
71615.19/10167.57	% SZS status Started for HL404235+5.p
71615.19/10167.57	% SZS status GaveUp for HL404235+5.p
71615.19/10167.57	% SZS status Ended for HL404235+5.p
71622.74/10168.49	% SZS status Started for HL404229+4.p
71622.74/10168.49	% SZS status GaveUp for HL404229+4.p
71622.74/10168.49	eprover: CPU time limit exceeded, terminating
71622.74/10168.49	% SZS status Ended for HL404229+4.p
71672.92/10174.77	% SZS status Started for HL404236+5.p
71672.92/10174.77	% SZS status GaveUp for HL404236+5.p
71672.92/10174.77	% SZS status Ended for HL404236+5.p
71681.82/10175.88	% SZS status Started for HL404231+4.p
71681.82/10175.88	% SZS status GaveUp for HL404231+4.p
71681.82/10175.88	eprover: CPU time limit exceeded, terminating
71681.82/10175.88	% SZS status Ended for HL404231+4.p
71689.36/10176.81	% SZS status Started for HL404237+5.p
71689.36/10176.81	% SZS status GaveUp for HL404237+5.p
71689.36/10176.81	% SZS status Ended for HL404237+5.p
71714.45/10180.00	% SZS status Started for HL404234+4.p
71714.45/10180.00	% SZS status GaveUp for HL404234+4.p
71714.45/10180.00	eprover: CPU time limit exceeded, terminating
71714.45/10180.00	% SZS status Ended for HL404234+4.p
71723.22/10181.21	% SZS status Started for HL404238+5.p
71723.22/10181.21	% SZS status Theorem for HL404238+5.p
71723.22/10181.21	% SZS status Ended for HL404238+5.p
71742.88/10183.55	% SZS status Started for HL404235+4.p
71742.88/10183.55	% SZS status GaveUp for HL404235+4.p
71742.88/10183.55	eprover: CPU time limit exceeded, terminating
71742.88/10183.55	% SZS status Ended for HL404235+4.p
71761.90/10185.94	% SZS status Started for HL404236+4.p
71761.90/10185.94	% SZS status GaveUp for HL404236+4.p
71761.90/10185.94	eprover: CPU time limit exceeded, terminating
71761.90/10185.94	% SZS status Ended for HL404236+4.p
71761.90/10186.00	% SZS status Started for HL404240+5.p
71761.90/10186.00	% SZS status GaveUp for HL404240+5.p
71761.90/10186.00	% SZS status Ended for HL404240+5.p
71776.30/10187.86	% SZS status Started for HL404241+5.p
71776.30/10187.86	% SZS status Theorem for HL404241+5.p
71776.30/10187.86	% SZS status Ended for HL404241+5.p
71812.24/10192.63	% SZS status Started for HL404237+4.p
71812.24/10192.63	% SZS status GaveUp for HL404237+4.p
71812.24/10192.63	eprover: CPU time limit exceeded, terminating
71812.24/10192.63	% SZS status Ended for HL404237+4.p
71817.52/10193.39	% SZS status Started for HL404242+5.p
71817.52/10193.39	% SZS status Theorem for HL404242+5.p
71817.52/10193.39	% SZS status Ended for HL404242+5.p
71826.81/10194.70	% SZS status Started for HL404238+4.p
71826.81/10194.70	% SZS status GaveUp for HL404238+4.p
71826.81/10194.70	eprover: CPU time limit exceeded, terminating
71826.81/10194.70	% SZS status Ended for HL404238+4.p
71847.48/10197.32	% SZS status Started for HL404243+4.p
71847.48/10197.32	% SZS status GaveUp for HL404243+4.p
71847.48/10197.32	eprover: CPU time limit exceeded, terminating
71847.48/10197.32	% SZS status Ended for HL404243+4.p
71854.70/10198.26	% SZS status Started for HL404243+5.p
71854.70/10198.26	% SZS status GaveUp for HL404243+5.p
71854.70/10198.26	% SZS status Ended for HL404243+5.p
71886.90/10202.51	% SZS status Started for HL404240+4.p
71886.90/10202.51	% SZS status GaveUp for HL404240+4.p
71886.90/10202.51	eprover: CPU time limit exceeded, terminating
71886.90/10202.51	% SZS status Ended for HL404240+4.p
71893.77/10203.41	% SZS status Started for HL404244+5.p
71893.77/10203.41	% SZS status GaveUp for HL404244+5.p
71893.77/10203.41	% SZS status Ended for HL404244+5.p
71894.25/10203.44	% SZS status Started for HL404244+4.p
71894.25/10203.44	% SZS status GaveUp for HL404244+4.p
71894.25/10203.44	eprover: CPU time limit exceeded, terminating
71894.25/10203.44	% SZS status Ended for HL404244+4.p
71903.34/10204.62	% SZS status Started for HL404245+5.p
71903.34/10204.62	% SZS status Theorem for HL404245+5.p
71903.34/10204.62	% SZS status Ended for HL404245+5.p
71912.28/10205.83	% SZS status Started for HL404245+4.p
71912.28/10205.83	% SZS status GaveUp for HL404245+4.p
71912.28/10205.83	eprover: CPU time limit exceeded, terminating
71912.28/10205.83	% SZS status Ended for HL404245+4.p
71919.45/10206.79	% SZS status Started for HL404241+4.p
71919.45/10206.79	% SZS status GaveUp for HL404241+4.p
71919.45/10206.79	eprover: CPU time limit exceeded, terminating
71919.45/10206.79	% SZS status Ended for HL404241+4.p
71950.33/10210.68	% SZS status Started for HL404242+4.p
71950.33/10210.68	% SZS status GaveUp for HL404242+4.p
71950.33/10210.68	eprover: CPU time limit exceeded, terminating
71950.33/10210.68	% SZS status Ended for HL404242+4.p
71967.32/10212.79	% SZS status Started for HL404246+5.p
71967.32/10212.79	% SZS status GaveUp for HL404246+5.p
71967.32/10212.79	% SZS status Ended for HL404246+5.p
71969.60/10213.14	% SZS status Started for HL404247+5.p
71969.60/10213.14	% SZS status GaveUp for HL404247+5.p
71969.60/10213.14	% SZS status Ended for HL404247+5.p
71976.13/10213.91	% SZS status Started for HL404247+4.p
71976.13/10213.91	% SZS status GaveUp for HL404247+4.p
71976.13/10213.91	eprover: CPU time limit exceeded, terminating
71976.13/10213.91	% SZS status Ended for HL404247+4.p
71987.63/10215.43	% SZS status Started for HL404248+4.p
71987.63/10215.43	% SZS status GaveUp for HL404248+4.p
71987.63/10215.43	eprover: CPU time limit exceeded, terminating
71987.63/10215.43	% SZS status Ended for HL404248+4.p
71990.14/10215.65	% SZS status Started for HL404248+5.p
71990.14/10215.65	% SZS status GaveUp for HL404248+5.p
71990.14/10215.65	% SZS status Ended for HL404248+5.p
72002.60/10217.25	% SZS status Started for HL404249+4.p
72002.60/10217.25	% SZS status GaveUp for HL404249+4.p
72002.60/10217.25	eprover: CPU time limit exceeded, terminating
72002.60/10217.25	% SZS status Ended for HL404249+4.p
72027.05/10220.34	% SZS status Started for HL404249+5.p
72027.05/10220.34	% SZS status GaveUp for HL404249+5.p
72027.05/10220.34	% SZS status Ended for HL404249+5.p
72046.00/10222.77	% SZS status Started for HL404250+5.p
72046.00/10222.77	% SZS status GaveUp for HL404250+5.p
72046.00/10222.77	% SZS status Ended for HL404250+5.p
72050.24/10223.20	% SZS status Started for HL404250+4.p
72050.24/10223.20	% SZS status GaveUp for HL404250+4.p
72050.24/10223.20	eprover: CPU time limit exceeded, terminating
72050.24/10223.20	% SZS status Ended for HL404250+4.p
72064.98/10225.12	% SZS status Started for HL404246+4.p
72064.98/10225.12	% SZS status GaveUp for HL404246+4.p
72064.98/10225.12	eprover: CPU time limit exceeded, terminating
72064.98/10225.12	% SZS status Ended for HL404246+4.p
72068.79/10225.59	% SZS status Started for HL404251+5.p
72068.79/10225.59	% SZS status GaveUp for HL404251+5.p
72068.79/10225.59	% SZS status Ended for HL404251+5.p
72079.30/10226.92	% SZS status Started for HL404252+5.p
72079.30/10226.92	% SZS status GaveUp for HL404252+5.p
72079.30/10226.92	% SZS status Ended for HL404252+5.p
72123.89/10232.46	% SZS status Started for HL404254+5.p
72123.89/10232.46	% SZS status GaveUp for HL404254+5.p
72123.89/10232.46	% SZS status Ended for HL404254+5.p
72146.23/10235.28	% SZS status Started for HL404256+5.p
72146.23/10235.28	% SZS status GaveUp for HL404256+5.p
72146.23/10235.28	% SZS status Ended for HL404256+5.p
72156.52/10236.59	% SZS status Started for HL404257+5.p
72156.52/10236.59	% SZS status GaveUp for HL404257+5.p
72156.52/10236.59	% SZS status Ended for HL404257+5.p
72182.83/10239.97	% SZS status Started for HL404251+4.p
72182.83/10239.97	% SZS status GaveUp for HL404251+4.p
72182.83/10239.97	eprover: CPU time limit exceeded, terminating
72182.83/10239.97	% SZS status Ended for HL404251+4.p
72196.25/10241.65	% SZS status Started for HL404252+4.p
72196.25/10241.65	% SZS status GaveUp for HL404252+4.p
72196.25/10241.65	eprover: CPU time limit exceeded, terminating
72196.25/10241.65	% SZS status Ended for HL404252+4.p
72227.21/10245.12	% SZS status Started for HL404258+5.p
72227.21/10245.12	% SZS status GaveUp for HL404258+5.p
72227.21/10245.12	% SZS status Ended for HL404258+5.p
72236.45/10246.32	% SZS status Started for HL404254+4.p
72236.45/10246.32	% SZS status GaveUp for HL404254+4.p
72236.45/10246.32	eprover: CPU time limit exceeded, terminating
72236.45/10246.32	% SZS status Ended for HL404254+4.p
72259.51/10249.20	% SZS status Started for HL404256+4.p
72259.51/10249.20	% SZS status GaveUp for HL404256+4.p
72259.51/10249.20	eprover: CPU time limit exceeded, terminating
72259.51/10249.20	% SZS status Ended for HL404256+4.p
72262.18/10249.65	% SZS status Started for HL404260+5.p
72262.18/10249.65	% SZS status GaveUp for HL404260+5.p
72262.18/10249.65	% SZS status Ended for HL404260+5.p
72278.66/10251.61	% SZS status Started for HL404257+4.p
72278.66/10251.61	% SZS status GaveUp for HL404257+4.p
72278.66/10251.61	eprover: CPU time limit exceeded, terminating
72278.66/10251.61	% SZS status Ended for HL404257+4.p
72304.43/10254.82	% SZS status Started for HL404261+5.p
72304.43/10254.82	% SZS status GaveUp for HL404261+5.p
72304.43/10254.82	% SZS status Ended for HL404261+5.p
72332.91/10258.45	% SZS status Started for HL404258+4.p
72332.91/10258.45	% SZS status GaveUp for HL404258+4.p
72332.91/10258.45	eprover: CPU time limit exceeded, terminating
72332.91/10258.45	% SZS status Ended for HL404258+4.p
72335.42/10258.75	% SZS status Started for HL404262+5.p
72335.42/10258.75	% SZS status GaveUp for HL404262+5.p
72335.42/10258.75	% SZS status Ended for HL404262+5.p
72350.99/10260.76	% SZS status Started for HL404263+5.p
72350.99/10260.76	% SZS status GaveUp for HL404263+5.p
72350.99/10260.76	% SZS status Ended for HL404263+5.p
72372.50/10263.54	% SZS status Started for HL404260+4.p
72372.50/10263.54	% SZS status GaveUp for HL404260+4.p
72372.50/10263.54	eprover: CPU time limit exceeded, terminating
72372.50/10263.54	% SZS status Ended for HL404260+4.p
72406.45/10267.79	% SZS status Started for HL404265+5.p
72406.45/10267.79	% SZS status GaveUp for HL404265+5.p
72406.45/10267.79	% SZS status Ended for HL404265+5.p
72409.25/10268.15	% SZS status Started for HL404261+4.p
72409.25/10268.15	% SZS status GaveUp for HL404261+4.p
72409.25/10268.15	eprover: CPU time limit exceeded, terminating
72409.25/10268.15	% SZS status Ended for HL404261+4.p
72431.53/10270.94	% SZS status Started for HL404267+5.p
72431.53/10270.94	% SZS status GaveUp for HL404267+5.p
72431.53/10270.94	% SZS status Ended for HL404267+5.p
72443.67/10272.47	% SZS status Started for HL404262+4.p
72443.67/10272.47	% SZS status GaveUp for HL404262+4.p
72443.67/10272.47	eprover: CPU time limit exceeded, terminating
72443.67/10272.47	% SZS status Ended for HL404262+4.p
72469.43/10275.86	% SZS status Started for HL404263+4.p
72469.43/10275.86	% SZS status GaveUp for HL404263+4.p
72469.43/10275.86	eprover: CPU time limit exceeded, terminating
72469.43/10275.86	% SZS status Ended for HL404263+4.p
72481.70/10277.50	% SZS status Started for HL404268+5.p
72481.70/10277.50	% SZS status GaveUp for HL404268+5.p
72481.70/10277.50	% SZS status Ended for HL404268+5.p
72504.88/10280.54	% SZS status Started for HL404265+4.p
72504.88/10280.54	% SZS status GaveUp for HL404265+4.p
72504.88/10280.54	eprover: CPU time limit exceeded, terminating
72504.88/10280.54	% SZS status Ended for HL404265+4.p
72509.11/10281.11	% SZS status Started for HL404269+5.p
72509.11/10281.11	% SZS status GaveUp for HL404269+5.p
72509.11/10281.11	% SZS status Ended for HL404269+5.p
72537.42/10284.88	% SZS status Started for HL404267+4.p
72537.42/10284.88	% SZS status GaveUp for HL404267+4.p
72537.42/10284.88	eprover: CPU time limit exceeded, terminating
72537.42/10284.88	% SZS status Ended for HL404267+4.p
72544.03/10285.74	% SZS status Started for HL404270+5.p
72544.03/10285.74	% SZS status GaveUp for HL404270+5.p
72544.03/10285.74	% SZS status Ended for HL404270+5.p
72578.89/10290.41	% SZS status Started for HL404268+4.p
72578.89/10290.41	% SZS status GaveUp for HL404268+4.p
72578.89/10290.41	eprover: CPU time limit exceeded, terminating
72578.89/10290.41	% SZS status Ended for HL404268+4.p
72582.56/10290.93	% SZS status Started for HL404271+5.p
72582.56/10290.93	% SZS status GaveUp for HL404271+5.p
72582.56/10290.93	% SZS status Ended for HL404271+5.p
72615.86/10295.21	% SZS status Started for HL404272+5.p
72615.86/10295.21	% SZS status GaveUp for HL404272+5.p
72615.86/10295.21	% SZS status Ended for HL404272+5.p
72619.27/10295.75	% SZS status Started for HL404269+4.p
72619.27/10295.75	% SZS status GaveUp for HL404269+4.p
72619.27/10295.75	eprover: CPU time limit exceeded, terminating
72619.27/10295.75	% SZS status Ended for HL404269+4.p
72646.04/10299.16	% SZS status Started for HL404270+4.p
72646.04/10299.16	% SZS status GaveUp for HL404270+4.p
72646.04/10299.16	eprover: CPU time limit exceeded, terminating
72646.04/10299.16	% SZS status Ended for HL404270+4.p
72654.27/10300.35	% SZS status Started for HL404273+5.p
72654.27/10300.35	% SZS status GaveUp for HL404273+5.p
72654.27/10300.35	% SZS status Ended for HL404273+5.p
72689.65/10304.98	% SZS status Started for HL404271+4.p
72689.65/10304.98	% SZS status GaveUp for HL404271+4.p
72689.65/10304.98	eprover: CPU time limit exceeded, terminating
72689.65/10304.98	% SZS status Ended for HL404271+4.p
72691.96/10305.25	% SZS status Started for HL404275+5.p
72691.96/10305.25	% SZS status GaveUp for HL404275+5.p
72691.96/10305.25	% SZS status Ended for HL404275+5.p
72711.69/10307.84	% SZS status Started for HL404272+4.p
72711.69/10307.84	% SZS status GaveUp for HL404272+4.p
72711.69/10307.84	eprover: CPU time limit exceeded, terminating
72711.69/10307.84	% SZS status Ended for HL404272+4.p
72722.23/10309.21	% SZS status Started for HL404276+5.p
72722.23/10309.21	% SZS status GaveUp for HL404276+5.p
72722.23/10309.21	% SZS status Ended for HL404276+5.p
72749.05/10312.86	% SZS status Started for HL404273+4.p
72749.05/10312.86	% SZS status GaveUp for HL404273+4.p
72749.05/10312.86	eprover: CPU time limit exceeded, terminating
72749.05/10312.86	% SZS status Ended for HL404273+4.p
72767.41/10315.32	% SZS status Started for HL404277+5.p
72767.41/10315.32	% SZS status GaveUp for HL404277+5.p
72767.41/10315.32	% SZS status Ended for HL404277+5.p
72782.23/10317.32	% SZS status Started for HL404275+4.p
72782.23/10317.32	% SZS status GaveUp for HL404275+4.p
72782.23/10317.32	eprover: CPU time limit exceeded, terminating
72782.23/10317.32	% SZS status Ended for HL404275+4.p
72793.02/10318.74	% SZS status Started for HL404278+5.p
72793.02/10318.74	% SZS status GaveUp for HL404278+5.p
72793.02/10318.74	% SZS status Ended for HL404278+5.p
72826.24/10323.02	% SZS status Started for HL404279+5.p
72826.24/10323.02	% SZS status GaveUp for HL404279+5.p
72826.24/10323.02	% SZS status Ended for HL404279+5.p
72828.16/10323.33	% SZS status Started for HL404276+4.p
72828.16/10323.33	% SZS status GaveUp for HL404276+4.p
72828.16/10323.33	eprover: CPU time limit exceeded, terminating
72828.16/10323.33	% SZS status Ended for HL404276+4.p
72859.45/10327.21	% SZS status Started for HL404277+4.p
72859.45/10327.21	% SZS status GaveUp for HL404277+4.p
72859.45/10327.21	eprover: CPU time limit exceeded, terminating
72859.45/10327.21	% SZS status Ended for HL404277+4.p
72860.42/10327.35	% SZS status Started for HL404280+5.p
72860.42/10327.35	% SZS status GaveUp for HL404280+5.p
72860.42/10327.35	% SZS status Ended for HL404280+5.p
72889.57/10331.09	% SZS status Started for HL404278+4.p
72889.57/10331.09	% SZS status GaveUp for HL404278+4.p
72889.57/10331.09	eprover: CPU time limit exceeded, terminating
72889.57/10331.09	% SZS status Ended for HL404278+4.p
72901.73/10332.83	% SZS status Started for HL404281+5.p
72901.73/10332.83	% SZS status GaveUp for HL404281+5.p
72901.73/10332.83	% SZS status Ended for HL404281+5.p
72924.01/10335.55	% SZS status Started for HL404279+4.p
72924.01/10335.55	% SZS status GaveUp for HL404279+4.p
72924.01/10335.55	eprover: CPU time limit exceeded, terminating
72924.01/10335.55	% SZS status Ended for HL404279+4.p
72934.52/10336.98	% SZS status Started for HL404282+5.p
72934.52/10336.98	% SZS status GaveUp for HL404282+5.p
72934.52/10336.98	% SZS status Ended for HL404282+5.p
72966.70/10341.14	% SZS status Started for HL404283+5.p
72966.70/10341.14	% SZS status GaveUp for HL404283+5.p
72966.70/10341.14	% SZS status Ended for HL404283+5.p
72971.03/10341.81	% SZS status Started for HL404280+4.p
72971.03/10341.81	% SZS status GaveUp for HL404280+4.p
72971.03/10341.81	eprover: CPU time limit exceeded, terminating
72971.03/10341.81	% SZS status Ended for HL404280+4.p
72998.29/10344.92	% SZS status Started for HL404281+4.p
72998.29/10344.92	% SZS status GaveUp for HL404281+4.p
72998.29/10344.92	eprover: CPU time limit exceeded, terminating
72998.29/10344.92	% SZS status Ended for HL404281+4.p
73005.18/10345.79	% SZS status Started for HL404284+5.p
73005.18/10345.79	% SZS status GaveUp for HL404284+5.p
73005.18/10345.79	% SZS status Ended for HL404284+5.p
73035.94/10349.90	% SZS status Started for HL404282+4.p
73035.94/10349.90	% SZS status GaveUp for HL404282+4.p
73035.94/10349.90	eprover: CPU time limit exceeded, terminating
73035.94/10349.90	% SZS status Ended for HL404282+4.p
73043.26/10350.90	% SZS status Started for HL404285+5.p
73043.26/10350.90	% SZS status GaveUp for HL404285+5.p
73043.26/10350.90	% SZS status Ended for HL404285+5.p
73067.21/10353.89	% SZS status Started for HL404283+4.p
73067.21/10353.89	% SZS status GaveUp for HL404283+4.p
73067.21/10353.89	eprover: CPU time limit exceeded, terminating
73067.21/10353.89	% SZS status Ended for HL404283+4.p
73076.40/10355.12	% SZS status Started for HL404286+5.p
73076.40/10355.12	% SZS status GaveUp for HL404286+5.p
73076.40/10355.12	% SZS status Ended for HL404286+5.p
73113.55/10359.95	% SZS status Started for HL404287+5.p
73113.55/10359.95	% SZS status GaveUp for HL404287+5.p
73113.55/10359.95	% SZS status Ended for HL404287+5.p
73113.97/10360.02	% SZS status Started for HL404284+4.p
73113.97/10360.02	% SZS status GaveUp for HL404284+4.p
73113.97/10360.02	eprover: CPU time limit exceeded, terminating
73113.97/10360.02	% SZS status Ended for HL404284+4.p
73140.89/10363.39	% SZS status Started for HL404285+4.p
73140.89/10363.39	% SZS status GaveUp for HL404285+4.p
73140.89/10363.39	eprover: CPU time limit exceeded, terminating
73140.89/10363.39	% SZS status Ended for HL404285+4.p
73144.59/10363.93	% SZS status Started for HL404288+5.p
73144.59/10363.93	% SZS status GaveUp for HL404288+5.p
73144.59/10363.93	% SZS status Ended for HL404288+5.p
73159.48/10365.85	% SZS status Started for HL404290+4.p
73159.48/10365.85	% SZS status GaveUp for HL404290+4.p
73159.48/10365.85	eprover: CPU time limit exceeded, terminating
73159.48/10365.85	% SZS status Ended for HL404290+4.p
73178.88/10368.33	% SZS status Started for HL404286+4.p
73178.88/10368.33	% SZS status GaveUp for HL404286+4.p
73178.88/10368.33	eprover: CPU time limit exceeded, terminating
73178.88/10368.33	% SZS status Ended for HL404286+4.p
73191.25/10369.89	% SZS status Started for HL404290+5.p
73191.25/10369.89	% SZS status GaveUp for HL404290+5.p
73191.25/10369.89	% SZS status Ended for HL404290+5.p
73199.38/10371.00	% SZS status Started for HL404291+4.p
73199.38/10371.00	% SZS status GaveUp for HL404291+4.p
73199.38/10371.00	eprover: CPU time limit exceeded, terminating
73199.38/10371.00	% SZS status Ended for HL404291+4.p
73207.66/10372.07	% SZS status Started for HL404287+4.p
73207.66/10372.07	% SZS status GaveUp for HL404287+4.p
73207.66/10372.07	eprover: CPU time limit exceeded, terminating
73207.66/10372.07	% SZS status Ended for HL404287+4.p
73217.23/10373.36	% SZS status Started for HL404291+5.p
73217.23/10373.36	% SZS status GaveUp for HL404291+5.p
73217.23/10373.36	% SZS status Ended for HL404291+5.p
73230.87/10375.21	% SZS status Started for HL404293+4.p
73230.87/10375.21	% SZS status GaveUp for HL404293+4.p
73230.87/10375.21	eprover: CPU time limit exceeded, terminating
73230.87/10375.21	% SZS status Ended for HL404293+4.p
73236.59/10376.04	% SZS status Started for HL404293+5.p
73236.59/10376.04	% SZS status GaveUp for HL404293+5.p
73236.59/10376.04	% SZS status Ended for HL404293+5.p
73247.38/10377.37	% SZS status Started for HL404288+4.p
73247.38/10377.37	% SZS status GaveUp for HL404288+4.p
73247.38/10377.37	eprover: CPU time limit exceeded, terminating
73247.38/10377.37	% SZS status Ended for HL404288+4.p
73265.66/10379.82	% SZS status Started for HL404294+5.p
73265.66/10379.82	% SZS status GaveUp for HL404294+5.p
73265.66/10379.82	% SZS status Ended for HL404294+5.p
73277.13/10381.49	% SZS status Started for HL404294+4.p
73277.13/10381.49	% SZS status GaveUp for HL404294+4.p
73277.13/10381.49	eprover: CPU time limit exceeded, terminating
73277.13/10381.49	% SZS status Ended for HL404294+4.p
73284.16/10382.20	% SZS status Started for HL404295+5.p
73284.16/10382.20	% SZS status GaveUp for HL404295+5.p
73284.16/10382.20	% SZS status Ended for HL404295+5.p
73307.05/10385.05	% SZS status Started for HL404296+5.p
73307.05/10385.05	% SZS status GaveUp for HL404296+5.p
73307.05/10385.05	% SZS status Ended for HL404296+5.p
73322.89/10387.10	% SZS status Started for HL404298+5.p
73322.89/10387.10	% SZS status GaveUp for HL404298+5.p
73322.89/10387.10	% SZS status Ended for HL404298+5.p
73352.06/10390.75	% SZS status Started for HL404299+5.p
73352.06/10390.75	% SZS status GaveUp for HL404299+5.p
73352.06/10390.75	% SZS status Ended for HL404299+5.p
73380.22/10394.30	% SZS status Started for HL404300+5.p
73380.22/10394.30	% SZS status GaveUp for HL404300+5.p
73380.22/10394.30	% SZS status Ended for HL404300+5.p
73407.99/10397.73	% SZS status Started for HL404295+4.p
73407.99/10397.73	% SZS status GaveUp for HL404295+4.p
73407.99/10397.73	eprover: CPU time limit exceeded, terminating
73407.99/10397.73	% SZS status Ended for HL404295+4.p
73425.91/10399.99	% SZS status Started for HL404301+5.p
73425.91/10399.99	% SZS status GaveUp for HL404301+5.p
73425.91/10399.99	% SZS status Ended for HL404301+5.p
73426.60/10400.08	% SZS status Started for HL404296+4.p
73426.60/10400.08	% SZS status GaveUp for HL404296+4.p
73426.60/10400.08	eprover: CPU time limit exceeded, terminating
73426.60/10400.08	% SZS status Ended for HL404296+4.p
73446.45/10402.59	% SZS status Started for HL404298+4.p
73446.45/10402.59	% SZS status GaveUp for HL404298+4.p
73446.45/10402.59	eprover: CPU time limit exceeded, terminating
73446.45/10402.59	% SZS status Ended for HL404298+4.p
73471.79/10405.74	% SZS status Started for HL404299+4.p
73471.79/10405.74	% SZS status GaveUp for HL404299+4.p
73471.79/10405.74	eprover: CPU time limit exceeded, terminating
73471.79/10405.74	% SZS status Ended for HL404299+4.p
73482.56/10407.10	% SZS status Started for HL404302+5.p
73482.56/10407.10	% SZS status GaveUp for HL404302+5.p
73482.56/10407.10	% SZS status Ended for HL404302+5.p
73488.92/10407.96	% SZS status Started for HL404300+4.p
73488.92/10407.96	% SZS status GaveUp for HL404300+4.p
73488.92/10407.96	eprover: CPU time limit exceeded, terminating
73488.92/10407.96	% SZS status Ended for HL404300+4.p
73498.94/10409.29	% SZS status Started for HL404303+5.p
73498.94/10409.29	% SZS status GaveUp for HL404303+5.p
73498.94/10409.29	% SZS status Ended for HL404303+5.p
73528.80/10412.93	% SZS status Started for HL404301+4.p
73528.80/10412.93	% SZS status GaveUp for HL404301+4.p
73528.80/10412.93	eprover: CPU time limit exceeded, terminating
73528.80/10412.93	% SZS status Ended for HL404301+4.p
73544.95/10414.97	% SZS status Started for HL404304+5.p
73544.95/10414.97	% SZS status GaveUp for HL404304+5.p
73544.95/10414.97	% SZS status Ended for HL404304+5.p
73563.64/10417.34	% SZS status Started for HL404305+5.p
73563.64/10417.34	% SZS status GaveUp for HL404305+5.p
73563.64/10417.34	% SZS status Ended for HL404305+5.p
73586.22/10420.20	% SZS status Started for HL404302+4.p
73586.22/10420.20	% SZS status GaveUp for HL404302+4.p
73586.22/10420.20	eprover: CPU time limit exceeded, terminating
73586.22/10420.20	% SZS status Ended for HL404302+4.p
73602.46/10422.27	% SZS status Started for HL404306+5.p
73602.46/10422.27	% SZS status GaveUp for HL404306+5.p
73602.46/10422.27	% SZS status Ended for HL404306+5.p
73633.50/10426.15	% SZS status Started for HL404303+4.p
73633.50/10426.15	% SZS status GaveUp for HL404303+4.p
73633.50/10426.15	eprover: CPU time limit exceeded, terminating
73633.50/10426.15	% SZS status Ended for HL404303+4.p
73637.91/10426.67	% SZS status Started for HL404307+5.p
73637.91/10426.67	% SZS status GaveUp for HL404307+5.p
73637.91/10426.67	% SZS status Ended for HL404307+5.p
73651.66/10428.43	% SZS status Started for HL404304+4.p
73651.66/10428.43	% SZS status GaveUp for HL404304+4.p
73651.66/10428.43	eprover: CPU time limit exceeded, terminating
73651.66/10428.43	% SZS status Ended for HL404304+4.p
73679.50/10431.91	% SZS status Started for HL404308+5.p
73679.50/10431.91	% SZS status GaveUp for HL404308+5.p
73679.50/10431.91	% SZS status Ended for HL404308+5.p
73688.27/10433.13	% SZS status Started for HL404305+4.p
73688.27/10433.13	% SZS status GaveUp for HL404305+4.p
73688.27/10433.13	eprover: CPU time limit exceeded, terminating
73688.27/10433.13	% SZS status Ended for HL404305+4.p
73705.43/10435.39	% SZS status Started for HL404306+4.p
73705.43/10435.39	% SZS status GaveUp for HL404306+4.p
73705.43/10435.39	eprover: CPU time limit exceeded, terminating
73705.43/10435.39	% SZS status Ended for HL404306+4.p
73713.23/10436.18	% SZS status Started for HL404311+5.p
73713.23/10436.18	% SZS status GaveUp for HL404311+5.p
73713.23/10436.18	% SZS status Ended for HL404311+5.p
73731.61/10438.50	% SZS status Started for HL404312+5.p
73731.61/10438.50	% SZS status Theorem for HL404312+5.p
73731.61/10438.50	% SZS status Ended for HL404312+5.p
73750.77/10440.98	% SZS status Started for HL404307+4.p
73750.77/10440.98	% SZS status GaveUp for HL404307+4.p
73750.77/10440.98	eprover: CPU time limit exceeded, terminating
73750.77/10440.98	% SZS status Ended for HL404307+4.p
73782.16/10444.88	% SZS status Started for HL404313+5.p
73782.16/10444.88	% SZS status GaveUp for HL404313+5.p
73782.16/10444.88	% SZS status Ended for HL404313+5.p
73794.32/10446.40	% SZS status Started for HL404308+4.p
73794.32/10446.40	% SZS status GaveUp for HL404308+4.p
73794.32/10446.40	eprover: CPU time limit exceeded, terminating
73794.32/10446.40	% SZS status Ended for HL404308+4.p
73806.79/10448.01	% SZS status Started for HL404314+5.p
73806.79/10448.01	% SZS status GaveUp for HL404314+5.p
73806.79/10448.01	% SZS status Ended for HL404314+5.p
73840.70/10452.27	% SZS status Started for HL404311+4.p
73840.70/10452.27	% SZS status GaveUp for HL404311+4.p
73840.70/10452.27	eprover: CPU time limit exceeded, terminating
73840.70/10452.27	% SZS status Ended for HL404311+4.p
73856.32/10454.26	% SZS status Started for HL404315+5.p
73856.32/10454.26	% SZS status GaveUp for HL404315+5.p
73856.32/10454.26	% SZS status Ended for HL404315+5.p
73857.09/10454.41	% SZS status Started for HL404312+4.p
73857.09/10454.41	% SZS status GaveUp for HL404312+4.p
73857.09/10454.41	eprover: CPU time limit exceeded, terminating
73857.09/10454.41	% SZS status Ended for HL404312+4.p
73880.53/10457.31	% SZS status Started for HL404316+5.p
73880.53/10457.31	% SZS status GaveUp for HL404316+5.p
73880.53/10457.31	% SZS status Ended for HL404316+5.p
73896.38/10459.27	% SZS status Started for HL404313+4.p
73896.38/10459.27	% SZS status GaveUp for HL404313+4.p
73896.38/10459.27	eprover: CPU time limit exceeded, terminating
73896.38/10459.27	% SZS status Ended for HL404313+4.p
73919.23/10462.19	% SZS status Started for HL404314+4.p
73919.23/10462.19	% SZS status GaveUp for HL404314+4.p
73919.23/10462.19	eprover: CPU time limit exceeded, terminating
73919.23/10462.19	% SZS status Ended for HL404314+4.p
73928.35/10463.29	% SZS status Started for HL404317+5.p
73928.35/10463.29	% SZS status GaveUp for HL404317+5.p
73928.35/10463.29	% SZS status Ended for HL404317+5.p
73952.59/10466.32	% SZS status Started for HL404318+5.p
73952.59/10466.32	% SZS status GaveUp for HL404318+5.p
73952.59/10466.32	% SZS status Ended for HL404318+5.p
73957.66/10467.03	% SZS status Started for HL404315+4.p
73957.66/10467.03	% SZS status GaveUp for HL404315+4.p
73957.66/10467.03	eprover: CPU time limit exceeded, terminating
73957.66/10467.03	% SZS status Ended for HL404315+4.p
73999.73/10472.32	% SZS status Started for HL404316+4.p
73999.73/10472.32	% SZS status GaveUp for HL404316+4.p
73999.73/10472.32	eprover: CPU time limit exceeded, terminating
73999.73/10472.32	% SZS status Ended for HL404316+4.p
73999.85/10472.35	% SZS status Started for HL404319+5.p
73999.85/10472.35	% SZS status GaveUp for HL404319+5.p
73999.85/10472.35	% SZS status Ended for HL404319+5.p
74025.15/10475.58	% SZS status Started for HL404321+5.p
74025.15/10475.58	% SZS status GaveUp for HL404321+5.p
74025.15/10475.58	% SZS status Ended for HL404321+5.p
74048.20/10478.41	% SZS status Started for HL404317+4.p
74048.20/10478.41	% SZS status GaveUp for HL404317+4.p
74048.20/10478.41	eprover: CPU time limit exceeded, terminating
74048.20/10478.41	% SZS status Ended for HL404317+4.p
74063.52/10480.40	% SZS status Started for HL404318+4.p
74063.52/10480.40	% SZS status GaveUp for HL404318+4.p
74063.52/10480.40	eprover: CPU time limit exceeded, terminating
74063.52/10480.40	% SZS status Ended for HL404318+4.p
74074.66/10481.80	% SZS status Started for HL404322+5.p
74074.66/10481.80	% SZS status GaveUp for HL404322+5.p
74074.66/10481.80	% SZS status Ended for HL404322+5.p
74098.87/10484.84	% SZS status Started for HL404323+5.p
74098.87/10484.84	% SZS status GaveUp for HL404323+5.p
74098.87/10484.84	% SZS status Ended for HL404323+5.p
74104.63/10485.52	% SZS status Started for HL404319+4.p
74104.63/10485.52	% SZS status GaveUp for HL404319+4.p
74104.63/10485.52	eprover: CPU time limit exceeded, terminating
74104.63/10485.52	% SZS status Ended for HL404319+4.p
74114.82/10486.87	% SZS status Started for HL404326+5.p
74114.82/10486.87	% SZS status Theorem for HL404326+5.p
74114.82/10486.87	% SZS status Ended for HL404326+5.p
74135.66/10489.46	% SZS status Started for HL404321+4.p
74135.66/10489.46	% SZS status GaveUp for HL404321+4.p
74135.66/10489.46	eprover: CPU time limit exceeded, terminating
74135.66/10489.46	% SZS status Ended for HL404321+4.p
74151.84/10491.49	% SZS status Started for HL404327+5.p
74151.84/10491.49	% SZS status Theorem for HL404327+5.p
74151.84/10491.49	% SZS status Ended for HL404327+5.p
74163.25/10492.92	% SZS status Started for HL404329+5.p
74163.25/10492.92	% SZS status Theorem for HL404329+5.p
74163.25/10492.92	% SZS status Ended for HL404329+5.p
74164.77/10493.08	% SZS status Started for HL404322+4.p
74164.77/10493.08	% SZS status GaveUp for HL404322+4.p
74164.77/10493.08	eprover: CPU time limit exceeded, terminating
74164.77/10493.08	% SZS status Ended for HL404322+4.p
74186.47/10495.90	% SZS status Started for HL404328+5.p
74186.47/10495.90	% SZS status GaveUp for HL404328+5.p
74186.47/10495.90	% SZS status Ended for HL404328+5.p
74205.98/10498.37	% SZS status Started for HL404323+4.p
74205.98/10498.37	% SZS status GaveUp for HL404323+4.p
74205.98/10498.37	eprover: CPU time limit exceeded, terminating
74205.98/10498.37	% SZS status Ended for HL404323+4.p
74235.96/10502.17	% SZS status Started for HL404330+5.p
74235.96/10502.17	% SZS status GaveUp for HL404330+5.p
74235.96/10502.17	% SZS status Ended for HL404330+5.p
74255.16/10504.54	% SZS status Started for HL404326+4.p
74255.16/10504.54	% SZS status GaveUp for HL404326+4.p
74255.16/10504.54	eprover: CPU time limit exceeded, terminating
74255.16/10504.54	% SZS status Ended for HL404326+4.p
74280.54/10507.72	% SZS status Started for HL404332+5.p
74280.54/10507.72	% SZS status GaveUp for HL404332+5.p
74280.54/10507.72	% SZS status Ended for HL404332+5.p
74282.98/10508.07	% SZS status Started for HL404327+4.p
74282.98/10508.07	% SZS status GaveUp for HL404327+4.p
74282.98/10508.07	eprover: CPU time limit exceeded, terminating
74282.98/10508.07	% SZS status Ended for HL404327+4.p
74314.61/10512.03	% SZS status Started for HL404328+4.p
74314.61/10512.03	% SZS status GaveUp for HL404328+4.p
74314.61/10512.03	eprover: CPU time limit exceeded, terminating
74314.61/10512.03	% SZS status Ended for HL404328+4.p
74328.68/10513.87	% SZS status Started for HL404334+5.p
74328.68/10513.87	% SZS status GaveUp for HL404334+5.p
74328.68/10513.87	% SZS status Ended for HL404334+5.p
74342.54/10515.54	% SZS status Started for HL404329+4.p
74342.54/10515.54	% SZS status GaveUp for HL404329+4.p
74342.54/10515.54	eprover: CPU time limit exceeded, terminating
74342.54/10515.54	% SZS status Ended for HL404329+4.p
74356.84/10517.33	% SZS status Started for HL404335+5.p
74356.84/10517.33	% SZS status GaveUp for HL404335+5.p
74356.84/10517.33	% SZS status Ended for HL404335+5.p
74372.80/10519.35	% SZS status Started for HL404330+4.p
74372.80/10519.35	% SZS status GaveUp for HL404330+4.p
74372.80/10519.35	eprover: CPU time limit exceeded, terminating
74372.80/10519.35	% SZS status Ended for HL404330+4.p
74393.68/10522.01	% SZS status Started for HL404332+4.p
74393.68/10522.01	% SZS status GaveUp for HL404332+4.p
74393.68/10522.01	eprover: CPU time limit exceeded, terminating
74393.68/10522.01	% SZS status Ended for HL404332+4.p
74427.20/10523.00	% SZS status Started for HL404337+5.p
74427.20/10523.00	% SZS status GaveUp for HL404337+5.p
74427.20/10523.00	% SZS status Ended for HL404337+5.p
74456.20/10526.66	% SZS status Started for HL404338+5.p
74456.20/10526.66	% SZS status GaveUp for HL404338+5.p
74456.20/10526.66	% SZS status Ended for HL404338+5.p
74468.12/10528.20	% SZS status Started for HL404334+4.p
74468.12/10528.20	% SZS status GaveUp for HL404334+4.p
74468.12/10528.20	eprover: CPU time limit exceeded, terminating
74468.12/10528.20	% SZS status Ended for HL404334+4.p
74518.08/10531.25	% SZS status Started for HL404339+5.p
74518.08/10531.25	% SZS status GaveUp for HL404339+5.p
74518.08/10531.25	% SZS status Ended for HL404339+5.p
74534.92/10533.38	% SZS status Started for HL404335+4.p
74534.92/10533.38	% SZS status GaveUp for HL404335+4.p
74534.92/10533.38	eprover: CPU time limit exceeded, terminating
74534.92/10533.38	% SZS status Ended for HL404335+4.p
74552.90/10535.62	% SZS status Started for HL404341+5.p
74552.90/10535.62	% SZS status GaveUp for HL404341+5.p
74552.90/10535.62	% SZS status Ended for HL404341+5.p
74568.04/10537.53	% SZS status Started for HL404337+4.p
74568.04/10537.53	% SZS status GaveUp for HL404337+4.p
74568.04/10537.53	eprover: CPU time limit exceeded, terminating
74568.04/10537.53	% SZS status Ended for HL404337+4.p
74589.48/10540.27	% SZS status Started for HL404342+5.p
74589.48/10540.27	% SZS status GaveUp for HL404342+5.p
74589.48/10540.27	% SZS status Ended for HL404342+5.p
74596.39/10541.21	% SZS status Started for HL404338+4.p
74596.39/10541.21	% SZS status GaveUp for HL404338+4.p
74596.39/10541.21	eprover: CPU time limit exceeded, terminating
74596.39/10541.21	% SZS status Ended for HL404338+4.p
74624.31/10544.65	% SZS status Started for HL404343+5.p
74624.31/10544.65	% SZS status GaveUp for HL404343+5.p
74624.31/10544.65	% SZS status Ended for HL404343+5.p
74627.85/10545.05	% SZS status Started for HL404339+4.p
74627.85/10545.05	% SZS status GaveUp for HL404339+4.p
74627.85/10545.05	eprover: CPU time limit exceeded, terminating
74627.85/10545.05	% SZS status Ended for HL404339+4.p
74655.60/10548.59	% SZS status Started for HL404341+4.p
74655.60/10548.59	% SZS status GaveUp for HL404341+4.p
74655.60/10548.59	eprover: CPU time limit exceeded, terminating
74655.60/10548.59	% SZS status Ended for HL404341+4.p
74662.27/10549.40	% SZS status Started for HL404346+5.p
74662.27/10549.40	% SZS status GaveUp for HL404346+5.p
74662.27/10549.40	% SZS status Ended for HL404346+5.p
74698.91/10554.01	% SZS status Started for HL404347+5.p
74698.91/10554.01	% SZS status GaveUp for HL404347+5.p
74698.91/10554.01	% SZS status Ended for HL404347+5.p
74699.31/10554.02	% SZS status Started for HL404342+4.p
74699.31/10554.02	% SZS status GaveUp for HL404342+4.p
74699.31/10554.02	eprover: CPU time limit exceeded, terminating
74699.31/10554.02	% SZS status Ended for HL404342+4.p
74708.91/10555.30	% SZS status Started for HL404349+4.p
74708.91/10555.30	% SZS status GaveUp for HL404349+4.p
74708.91/10555.30	eprover: CPU time limit exceeded, terminating
74708.91/10555.30	% SZS status Ended for HL404349+4.p
74730.51/10558.01	% SZS status Started for HL404349+5.p
74730.51/10558.01	% SZS status GaveUp for HL404349+5.p
74730.51/10558.01	% SZS status Ended for HL404349+5.p
74738.76/10558.99	% SZS status Started for HL404343+4.p
74738.76/10558.99	% SZS status GaveUp for HL404343+4.p
74738.76/10558.99	eprover: CPU time limit exceeded, terminating
74738.76/10558.99	% SZS status Ended for HL404343+4.p
74752.23/10560.70	% SZS status Started for HL404353+5.p
74752.23/10560.70	% SZS status Theorem for HL404353+5.p
74752.23/10560.70	% SZS status Ended for HL404353+5.p
74771.16/10563.11	% SZS status Started for HL404351+5.p
74771.16/10563.11	% SZS status GaveUp for HL404351+5.p
74771.16/10563.11	% SZS status Ended for HL404351+5.p
74771.94/10563.21	% SZS status Started for HL404346+4.p
74771.94/10563.21	% SZS status GaveUp for HL404346+4.p
74771.94/10563.21	eprover: CPU time limit exceeded, terminating
74771.94/10563.21	% SZS status Ended for HL404346+4.p
74799.88/10566.77	% SZS status Started for HL404347+4.p
74799.88/10566.77	% SZS status GaveUp for HL404347+4.p
74799.88/10566.77	eprover: CPU time limit exceeded, terminating
74799.88/10566.77	% SZS status Ended for HL404347+4.p
74809.65/10567.97	% SZS status Started for HL404355+5.p
74809.65/10567.97	% SZS status GaveUp for HL404355+5.p
74809.65/10567.97	% SZS status Ended for HL404355+5.p
74845.88/10572.54	% SZS status Started for HL404356+5.p
74845.88/10572.54	% SZS status GaveUp for HL404356+5.p
74845.88/10572.54	% SZS status Ended for HL404356+5.p
74868.29/10575.34	% SZS status Started for HL404351+4.p
74868.29/10575.34	% SZS status GaveUp for HL404351+4.p
74868.29/10575.34	eprover: CPU time limit exceeded, terminating
74868.29/10575.34	% SZS status Ended for HL404351+4.p
74873.55/10575.99	% SZS status Started for HL404357+5.p
74873.55/10575.99	% SZS status GaveUp for HL404357+5.p
74873.55/10575.99	% SZS status Ended for HL404357+5.p
74901.90/10579.58	% SZS status Started for HL404353+4.p
74901.90/10579.58	% SZS status GaveUp for HL404353+4.p
74901.90/10579.58	eprover: CPU time limit exceeded, terminating
74901.90/10579.58	% SZS status Ended for HL404353+4.p
74919.98/10581.80	% SZS status Started for HL404358+5.p
74919.98/10581.80	% SZS status GaveUp for HL404358+5.p
74919.98/10581.80	% SZS status Ended for HL404358+5.p
74934.07/10583.59	% SZS status Started for HL404355+4.p
74934.07/10583.59	% SZS status GaveUp for HL404355+4.p
74934.07/10583.59	eprover: CPU time limit exceeded, terminating
74934.07/10583.59	% SZS status Ended for HL404355+4.p
74945.20/10585.03	% SZS status Started for HL404359+5.p
74945.20/10585.03	% SZS status GaveUp for HL404359+5.p
74945.20/10585.03	% SZS status Ended for HL404359+5.p
74954.98/10586.26	% SZS status Started for HL404356+4.p
74954.98/10586.26	% SZS status GaveUp for HL404356+4.p
74954.98/10586.26	eprover: CPU time limit exceeded, terminating
74954.98/10586.26	% SZS status Ended for HL404356+4.p
74977.20/10589.05	% SZS status Started for HL404357+4.p
74977.20/10589.05	% SZS status GaveUp for HL404357+4.p
74977.20/10589.05	eprover: CPU time limit exceeded, terminating
74977.20/10589.05	% SZS status Ended for HL404357+4.p
74990.71/10590.79	% SZS status Started for HL404360+5.p
74990.71/10590.79	% SZS status GaveUp for HL404360+5.p
74990.71/10590.79	% SZS status Ended for HL404360+5.p
74992.07/10590.92	% SZS status Started for HL404362+5.p
74992.07/10590.92	% SZS status Theorem for HL404362+5.p
74992.07/10590.92	% SZS status Ended for HL404362+5.p
74992.07/10590.98	% SZS status Started for HL404361+5.p
74992.07/10590.98	% SZS status Theorem for HL404361+5.p
74992.07/10590.98	% SZS status Ended for HL404361+5.p
75013.20/10593.59	% SZS status Started for HL404358+4.p
75013.20/10593.59	% SZS status GaveUp for HL404358+4.p
75013.20/10593.59	eprover: CPU time limit exceeded, terminating
75013.20/10593.59	% SZS status Ended for HL404358+4.p
75066.17/10599.90	% SZS status Started for HL404363+5.p
75066.17/10599.90	% SZS status GaveUp for HL404363+5.p
75066.17/10599.90	% SZS status Ended for HL404363+5.p
75075.64/10601.09	% SZS status Started for HL404359+4.p
75075.64/10601.09	% SZS status GaveUp for HL404359+4.p
75075.64/10601.09	eprover: CPU time limit exceeded, terminating
75075.64/10601.09	% SZS status Ended for HL404359+4.p
75089.29/10602.83	% SZS status Started for HL404364+5.p
75089.29/10602.83	% SZS status GaveUp for HL404364+5.p
75089.29/10602.83	% SZS status Ended for HL404364+5.p
75107.52/10605.09	% SZS status Started for HL404360+4.p
75107.52/10605.09	% SZS status GaveUp for HL404360+4.p
75107.52/10605.09	eprover: CPU time limit exceeded, terminating
75107.52/10605.09	% SZS status Ended for HL404360+4.p
75139.34/10609.16	% SZS status Started for HL404361+4.p
75139.34/10609.16	% SZS status GaveUp for HL404361+4.p
75139.34/10609.16	eprover: CPU time limit exceeded, terminating
75139.34/10609.16	% SZS status Ended for HL404361+4.p
75151.90/10610.34	% SZS status Started for HL404365+5.p
75151.90/10610.34	% SZS status GaveUp for HL404365+5.p
75151.90/10610.34	% SZS status Ended for HL404365+5.p
75167.37/10612.34	% SZS status Started for HL404362+4.p
75167.37/10612.34	% SZS status GaveUp for HL404362+4.p
75167.37/10612.34	eprover: CPU time limit exceeded, terminating
75167.37/10612.34	% SZS status Ended for HL404362+4.p
75181.15/10614.08	% SZS status Started for HL404366+5.p
75181.15/10614.08	% SZS status GaveUp for HL404366+5.p
75181.15/10614.08	% SZS status Ended for HL404366+5.p
75199.78/10616.46	% SZS status Started for HL404363+4.p
75199.78/10616.46	% SZS status GaveUp for HL404363+4.p
75199.78/10616.46	eprover: CPU time limit exceeded, terminating
75199.78/10616.46	% SZS status Ended for HL404363+4.p
75200.34/10616.50	% SZS status Started for HL404364+4.p
75200.34/10616.50	% SZS status GaveUp for HL404364+4.p
75200.34/10616.50	eprover: CPU time limit exceeded, terminating
75200.34/10616.50	% SZS status Ended for HL404364+4.p
75223.59/10619.38	% SZS status Started for HL404367+5.p
75223.59/10619.38	% SZS status GaveUp for HL404367+5.p
75223.59/10619.38	% SZS status Ended for HL404367+5.p
75253.32/10623.13	% SZS status Started for HL404368+5.p
75253.32/10623.13	% SZS status GaveUp for HL404368+5.p
75253.32/10623.13	% SZS status Ended for HL404368+5.p
75272.14/10625.47	% SZS status Started for HL404369+5.p
75272.14/10625.47	% SZS status GaveUp for HL404369+5.p
75272.14/10625.47	% SZS status Ended for HL404369+5.p
75273.52/10625.67	% SZS status Started for HL404365+4.p
75273.52/10625.67	% SZS status GaveUp for HL404365+4.p
75273.52/10625.67	eprover: CPU time limit exceeded, terminating
75273.52/10625.67	% SZS status Ended for HL404365+4.p
75296.38/10628.52	% SZS status Started for HL404366+4.p
75296.38/10628.52	% SZS status GaveUp for HL404366+4.p
75296.38/10628.52	eprover: CPU time limit exceeded, terminating
75296.38/10628.52	% SZS status Ended for HL404366+4.p
75327.02/10632.37	% SZS status Started for HL404370+5.p
75327.02/10632.37	% SZS status GaveUp for HL404370+5.p
75327.02/10632.37	% SZS status Ended for HL404370+5.p
75347.20/10634.89	% SZS status Started for HL404371+5.p
75347.20/10634.89	% SZS status GaveUp for HL404371+5.p
75347.20/10634.89	% SZS status Ended for HL404371+5.p
75350.71/10635.36	% SZS status Started for HL404367+4.p
75350.71/10635.36	% SZS status GaveUp for HL404367+4.p
75350.71/10635.36	eprover: CPU time limit exceeded, terminating
75350.71/10635.36	% SZS status Ended for HL404367+4.p
75371.54/10637.94	% SZS status Started for HL404368+4.p
75371.54/10637.94	% SZS status GaveUp for HL404368+4.p
75371.54/10637.94	eprover: CPU time limit exceeded, terminating
75371.54/10637.94	% SZS status Ended for HL404368+4.p
75398.36/10641.34	% SZS status Started for HL404373+5.p
75398.36/10641.34	% SZS status GaveUp for HL404373+5.p
75398.36/10641.34	% SZS status Ended for HL404373+5.p
75404.22/10642.09	% SZS status Started for HL404369+4.p
75404.22/10642.09	% SZS status GaveUp for HL404369+4.p
75404.22/10642.09	eprover: CPU time limit exceeded, terminating
75404.22/10642.09	% SZS status Ended for HL404369+4.p
75422.27/10644.35	% SZS status Started for HL404374+5.p
75422.27/10644.35	% SZS status GaveUp for HL404374+5.p
75422.27/10644.35	% SZS status Ended for HL404374+5.p
75428.51/10645.13	% SZS status Started for HL404370+4.p
75428.51/10645.13	% SZS status GaveUp for HL404370+4.p
75428.51/10645.13	eprover: CPU time limit exceeded, terminating
75428.51/10645.13	% SZS status Ended for HL404370+4.p
75471.76/10650.57	% SZS status Started for HL404375+5.p
75471.76/10650.57	% SZS status GaveUp for HL404375+5.p
75471.76/10650.57	% SZS status Ended for HL404375+5.p
75475.00/10651.02	% SZS status Started for HL404371+4.p
75475.00/10651.02	% SZS status GaveUp for HL404371+4.p
75475.00/10651.02	eprover: CPU time limit exceeded, terminating
75475.00/10651.02	% SZS status Ended for HL404371+4.p
75496.13/10653.65	% SZS status Started for HL404376+5.p
75496.13/10653.65	% SZS status GaveUp for HL404376+5.p
75496.13/10653.65	% SZS status Ended for HL404376+5.p
75500.33/10654.18	% SZS status Started for HL404373+4.p
75500.33/10654.18	% SZS status GaveUp for HL404373+4.p
75500.33/10654.18	eprover: CPU time limit exceeded, terminating
75500.33/10654.18	% SZS status Ended for HL404373+4.p
75544.98/10659.81	% SZS status Started for HL404377+5.p
75544.98/10659.81	% SZS status GaveUp for HL404377+5.p
75544.98/10659.81	% SZS status Ended for HL404377+5.p
75552.56/10660.76	% SZS status Started for HL404374+4.p
75552.56/10660.76	% SZS status GaveUp for HL404374+4.p
75552.56/10660.76	eprover: CPU time limit exceeded, terminating
75552.56/10660.76	% SZS status Ended for HL404374+4.p
75571.13/10663.11	% SZS status Started for HL404378+5.p
75571.13/10663.11	% SZS status GaveUp for HL404378+5.p
75571.13/10663.11	% SZS status Ended for HL404378+5.p
75574.95/10663.56	% SZS status Started for HL404375+4.p
75574.95/10663.56	% SZS status GaveUp for HL404375+4.p
75574.95/10663.56	eprover: CPU time limit exceeded, terminating
75574.95/10663.56	% SZS status Ended for HL404375+4.p
75608.35/10667.79	% SZS status Started for HL404376+4.p
75608.35/10667.79	% SZS status GaveUp for HL404376+4.p
75608.35/10667.79	eprover: CPU time limit exceeded, terminating
75608.35/10667.79	% SZS status Ended for HL404376+4.p
75618.95/10669.09	% SZS status Started for HL404379+5.p
75618.95/10669.09	% SZS status GaveUp for HL404379+5.p
75618.95/10669.09	% SZS status Ended for HL404379+5.p
75634.69/10671.13	% SZS status Started for HL404377+4.p
75634.69/10671.13	% SZS status GaveUp for HL404377+4.p
75634.69/10671.13	eprover: CPU time limit exceeded, terminating
75634.69/10671.13	% SZS status Ended for HL404377+4.p
75644.67/10672.38	% SZS status Started for HL404380+5.p
75644.67/10672.38	% SZS status GaveUp for HL404380+5.p
75644.67/10672.38	% SZS status Ended for HL404380+5.p
75678.95/10676.68	% SZS status Started for HL404378+4.p
75678.95/10676.68	% SZS status GaveUp for HL404378+4.p
75678.95/10676.68	eprover: CPU time limit exceeded, terminating
75678.95/10676.68	% SZS status Ended for HL404378+4.p
75680.06/10676.81	% SZS status Started for HL404382+5.p
75680.06/10676.81	% SZS status GaveUp for HL404382+5.p
75680.06/10676.81	% SZS status Ended for HL404382+5.p
75706.49/10680.17	% SZS status Started for HL404379+4.p
75706.49/10680.17	% SZS status GaveUp for HL404379+4.p
75706.49/10680.17	eprover: CPU time limit exceeded, terminating
75706.49/10680.17	% SZS status Ended for HL404379+4.p
75708.36/10680.41	% SZS status Started for HL404383+5.p
75708.36/10680.41	% SZS status GaveUp for HL404383+5.p
75708.36/10680.41	% SZS status Ended for HL404383+5.p
75750.84/10685.72	% SZS status Started for HL404384+5.p
75750.84/10685.72	% SZS status GaveUp for HL404384+5.p
75750.84/10685.72	% SZS status Ended for HL404384+5.p
75759.33/10686.76	% SZS status Started for HL404380+4.p
75759.33/10686.76	% SZS status GaveUp for HL404380+4.p
75759.33/10686.76	eprover: CPU time limit exceeded, terminating
75759.33/10686.76	% SZS status Ended for HL404380+4.p
75777.43/10689.17	% SZS status Started for HL404382+4.p
75777.43/10689.17	% SZS status GaveUp for HL404382+4.p
75777.43/10689.17	eprover: CPU time limit exceeded, terminating
75777.43/10689.17	% SZS status Ended for HL404382+4.p
75779.05/10689.26	% SZS status Started for HL404385+5.p
75779.05/10689.26	% SZS status GaveUp for HL404385+5.p
75779.05/10689.26	% SZS status Ended for HL404385+5.p
75823.18/10694.78	% SZS status Started for HL404386+5.p
75823.18/10694.78	% SZS status GaveUp for HL404386+5.p
75823.18/10694.78	% SZS status Ended for HL404386+5.p
75823.18/10694.78	% SZS status Started for HL404383+4.p
75823.18/10694.78	% SZS status GaveUp for HL404383+4.p
75823.18/10694.78	eprover: CPU time limit exceeded, terminating
75823.18/10694.78	% SZS status Ended for HL404383+4.p
75845.34/10697.96	% SZS status Started for HL404384+4.p
75845.34/10697.96	% SZS status GaveUp for HL404384+4.p
75845.34/10697.96	eprover: CPU time limit exceeded, terminating
75845.34/10697.96	% SZS status Ended for HL404384+4.p
75850.45/10698.68	% SZS status Started for HL404387+5.p
75850.45/10698.68	% SZS status GaveUp for HL404387+5.p
75850.45/10698.68	% SZS status Ended for HL404387+5.p
75882.37/10703.07	% SZS status Started for HL404385+4.p
75882.37/10703.07	% SZS status GaveUp for HL404385+4.p
75882.37/10703.07	eprover: CPU time limit exceeded, terminating
75882.37/10703.07	% SZS status Ended for HL404385+4.p
75902.41/10705.69	% SZS status Started for HL404388+5.p
75902.41/10705.69	% SZS status GaveUp for HL404388+5.p
75902.41/10705.69	% SZS status Ended for HL404388+5.p
75911.64/10706.77	% SZS status Started for HL404386+4.p
75911.64/10706.77	% SZS status GaveUp for HL404386+4.p
75911.64/10706.77	eprover: CPU time limit exceeded, terminating
75911.64/10706.77	% SZS status Ended for HL404386+4.p
75926.94/10708.69	% SZS status Started for HL404389+5.p
75926.94/10708.69	% SZS status GaveUp for HL404389+5.p
75926.94/10708.69	% SZS status Ended for HL404389+5.p
75937.95/10710.13	% SZS status Started for HL404390+4.p
75937.95/10710.13	% SZS status GaveUp for HL404390+4.p
75937.95/10710.13	eprover: CPU time limit exceeded, terminating
75937.95/10710.13	% SZS status Ended for HL404390+4.p
75958.01/10712.59	% SZS status Started for HL404387+4.p
75958.01/10712.59	% SZS status GaveUp for HL404387+4.p
75958.01/10712.59	eprover: CPU time limit exceeded, terminating
75958.01/10712.59	% SZS status Ended for HL404387+4.p
75959.17/10712.87	% SZS status Started for HL404390+5.p
75959.17/10712.87	% SZS status GaveUp for HL404390+5.p
75959.17/10712.87	% SZS status Ended for HL404390+5.p
75984.30/10716.08	% SZS status Started for HL404391+4.p
75984.30/10716.08	% SZS status GaveUp for HL404391+4.p
75984.30/10716.08	eprover: CPU time limit exceeded, terminating
75984.30/10716.08	% SZS status Ended for HL404391+4.p
75984.77/10716.17	% SZS status Started for HL404388+4.p
75984.77/10716.17	% SZS status GaveUp for HL404388+4.p
75984.77/10716.17	eprover: CPU time limit exceeded, terminating
75984.77/10716.17	% SZS status Ended for HL404388+4.p
75992.39/10717.21	% SZS status Started for HL404391+5.p
75992.39/10717.21	% SZS status GaveUp for HL404391+5.p
75992.39/10717.21	% SZS status Ended for HL404391+5.p
76008.20/10719.45	% SZS status Started for HL404392+4.p
76008.20/10719.45	% SZS status GaveUp for HL404392+4.p
76008.20/10719.45	eprover: CPU time limit exceeded, terminating
76008.20/10719.45	% SZS status Ended for HL404392+4.p
76018.85/10720.83	% SZS status Started for HL404392+5.p
76018.85/10720.83	% SZS status GaveUp for HL404392+5.p
76018.85/10720.83	% SZS status Ended for HL404392+5.p
76033.23/10722.80	% SZS status Started for HL404389+4.p
76033.23/10722.80	% SZS status GaveUp for HL404389+4.p
76033.23/10722.80	eprover: CPU time limit exceeded, terminating
76033.23/10722.80	% SZS status Ended for HL404389+4.p
76037.97/10723.41	% SZS status Started for HL404393+4.p
76037.97/10723.41	% SZS status GaveUp for HL404393+4.p
76037.97/10723.41	eprover: CPU time limit exceeded, terminating
76037.97/10723.41	% SZS status Ended for HL404393+4.p
76042.81/10724.06	% SZS status Started for HL404393+5.p
76042.81/10724.06	% SZS status GaveUp for HL404393+5.p
76042.81/10724.06	% SZS status Ended for HL404393+5.p
76059.72/10726.15	% SZS status Started for HL404394+5.p
76059.72/10726.15	% SZS status GaveUp for HL404394+5.p
76059.72/10726.15	% SZS status Ended for HL404394+5.p
76063.48/10726.54	% SZS status Started for HL404394+4.p
76063.48/10726.54	% SZS status GaveUp for HL404394+4.p
76063.48/10726.54	eprover: CPU time limit exceeded, terminating
76063.48/10726.54	% SZS status Ended for HL404394+4.p
76072.73/10727.76	% SZS status Started for HL404396+4.p
76072.73/10727.76	% SZS status GaveUp for HL404396+4.p
76072.73/10727.76	eprover: CPU time limit exceeded, terminating
76072.73/10727.76	% SZS status Ended for HL404396+4.p
76080.56/10728.74	% SZS status Started for HL404396+5.p
76080.56/10728.74	% SZS status GaveUp for HL404396+5.p
76080.56/10728.74	% SZS status Ended for HL404396+5.p
76104.81/10731.97	% SZS status Started for HL404397+5.p
76104.81/10731.97	% SZS status GaveUp for HL404397+5.p
76104.81/10731.97	% SZS status Ended for HL404397+5.p
76117.62/10733.52	% SZS status Started for HL404398+5.p
76117.62/10733.52	% SZS status GaveUp for HL404398+5.p
76117.62/10733.52	% SZS status Ended for HL404398+5.p
76121.31/10734.00	% SZS status Started for HL404398+4.p
76121.31/10734.00	% SZS status GaveUp for HL404398+4.p
76121.31/10734.00	eprover: CPU time limit exceeded, terminating
76121.31/10734.00	% SZS status Ended for HL404398+4.p
76128.38/10734.85	% SZS status Started for HL404400+5.p
76128.38/10734.85	% SZS status Theorem for HL404400+5.p
76128.38/10734.85	% SZS status Ended for HL404400+5.p
76136.42/10735.93	% SZS status Started for HL404399+5.p
76136.42/10735.93	% SZS status GaveUp for HL404399+5.p
76136.42/10735.93	% SZS status Ended for HL404399+5.p
76191.42/10742.94	% SZS status Started for HL404401+5.p
76191.42/10742.94	% SZS status GaveUp for HL404401+5.p
76191.42/10742.94	% SZS status Ended for HL404401+5.p
76209.58/10744.14	% SZS status Started for HL404403+5.p
76209.58/10744.14	% SZS status GaveUp for HL404403+5.p
76209.58/10744.14	% SZS status Ended for HL404403+5.p
76234.19/10747.22	% SZS status Started for HL404397+4.p
76234.19/10747.22	% SZS status GaveUp for HL404397+4.p
76234.19/10747.22	eprover: CPU time limit exceeded, terminating
76234.19/10747.22	% SZS status Ended for HL404397+4.p
76272.04/10751.95	% SZS status Started for HL404404+5.p
76272.04/10751.95	% SZS status GaveUp for HL404404+5.p
76272.04/10751.95	% SZS status Ended for HL404404+5.p
76273.02/10752.15	% SZS status Started for HL404399+4.p
76273.02/10752.15	% SZS status GaveUp for HL404399+4.p
76273.02/10752.15	eprover: CPU time limit exceeded, terminating
76273.02/10752.15	% SZS status Ended for HL404399+4.p
76282.30/10753.27	% SZS status Started for HL404407+5.p
76282.30/10753.27	% SZS status Theorem for HL404407+5.p
76282.30/10753.27	% SZS status Ended for HL404407+5.p
76284.39/10753.52	% SZS status Started for HL404400+4.p
76284.39/10753.52	% SZS status GaveUp for HL404400+4.p
76284.39/10753.52	eprover: CPU time limit exceeded, terminating
76284.39/10753.52	% SZS status Ended for HL404400+4.p
76293.09/10754.70	% SZS status Started for HL404408+5.p
76293.09/10754.70	% SZS status Theorem for HL404408+5.p
76293.09/10754.70	% SZS status Ended for HL404408+5.p
76307.83/10756.50	% SZS status Started for HL404405+5.p
76307.83/10756.50	% SZS status GaveUp for HL404405+5.p
76307.83/10756.50	% SZS status Ended for HL404405+5.p
76317.81/10757.74	% SZS status Started for HL404401+4.p
76317.81/10757.74	% SZS status GaveUp for HL404401+4.p
76317.81/10757.74	eprover: CPU time limit exceeded, terminating
76317.81/10757.74	% SZS status Ended for HL404401+4.p
76333.22/10759.82	% SZS status Started for HL404403+4.p
76333.22/10759.82	% SZS status GaveUp for HL404403+4.p
76333.22/10759.82	eprover: CPU time limit exceeded, terminating
76333.22/10759.82	% SZS status Ended for HL404403+4.p
76342.81/10760.95	% SZS status Started for HL404411+5.p
76342.81/10760.95	% SZS status Theorem for HL404411+5.p
76342.81/10760.95	% SZS status Ended for HL404411+5.p
76349.64/10761.77	% SZS status Started for HL404404+4.p
76349.64/10761.77	% SZS status GaveUp for HL404404+4.p
76349.64/10761.77	eprover: CPU time limit exceeded, terminating
76349.64/10761.77	% SZS status Ended for HL404404+4.p
76381.03/10765.80	% SZS status Started for HL404410+5.p
76381.03/10765.80	% SZS status GaveUp for HL404410+5.p
76381.03/10765.80	% SZS status Ended for HL404410+5.p
76412.83/10769.69	% SZS status Started for HL404405+4.p
76412.83/10769.69	% SZS status GaveUp for HL404405+4.p
76412.83/10769.69	eprover: CPU time limit exceeded, terminating
76412.83/10769.69	% SZS status Ended for HL404405+4.p
76422.98/10771.01	% SZS status Started for HL404414+5.p
76422.98/10771.01	% SZS status GaveUp for HL404414+5.p
76422.98/10771.01	% SZS status Ended for HL404414+5.p
76475.48/10777.60	% SZS status Started for HL404407+4.p
76475.48/10777.60	% SZS status GaveUp for HL404407+4.p
76475.48/10777.60	eprover: CPU time limit exceeded, terminating
76475.48/10777.60	% SZS status Ended for HL404407+4.p
76477.90/10777.92	% SZS status Started for HL404415+5.p
76477.90/10777.92	% SZS status GaveUp for HL404415+5.p
76477.90/10777.92	% SZS status Ended for HL404415+5.p
76489.66/10779.38	% SZS status Started for HL404408+4.p
76489.66/10779.38	% SZS status GaveUp for HL404408+4.p
76489.66/10779.38	eprover: CPU time limit exceeded, terminating
76489.66/10779.38	% SZS status Ended for HL404408+4.p
76499.26/10780.62	% SZS status Started for HL404410+4.p
76499.26/10780.62	% SZS status GaveUp for HL404410+4.p
76499.26/10780.62	eprover: CPU time limit exceeded, terminating
76499.26/10780.62	% SZS status Ended for HL404410+4.p
76521.74/10783.42	% SZS status Started for HL404411+4.p
76521.74/10783.42	% SZS status GaveUp for HL404411+4.p
76521.74/10783.42	eprover: CPU time limit exceeded, terminating
76521.74/10783.42	% SZS status Ended for HL404411+4.p
76548.54/10786.86	% SZS status Started for HL404414+4.p
76548.54/10786.86	% SZS status GaveUp for HL404414+4.p
76548.54/10786.86	eprover: CPU time limit exceeded, terminating
76548.54/10786.86	% SZS status Ended for HL404414+4.p
76548.63/10786.91	% SZS status Started for HL404416+5.p
76548.63/10786.91	% SZS status GaveUp for HL404416+5.p
76548.63/10786.91	% SZS status Ended for HL404416+5.p
76563.72/10788.72	% SZS status Started for HL404418+5.p
76563.72/10788.72	% SZS status GaveUp for HL404418+5.p
76563.72/10788.72	% SZS status Ended for HL404418+5.p
76587.00/10791.66	% SZS status Started for HL404415+4.p
76587.00/10791.66	% SZS status GaveUp for HL404415+4.p
76587.00/10791.66	eprover: CPU time limit exceeded, terminating
76587.00/10791.66	% SZS status Ended for HL404415+4.p
76595.44/10792.76	% SZS status Started for HL404420+5.p
76595.44/10792.76	% SZS status GaveUp for HL404420+5.p
76595.44/10792.76	% SZS status Ended for HL404420+5.p
76623.77/10796.29	% SZS status Started for HL404421+5.p
76623.77/10796.29	% SZS status GaveUp for HL404421+5.p
76623.77/10796.29	% SZS status Ended for HL404421+5.p
76626.02/10796.64	% SZS status Started for HL404416+4.p
76626.02/10796.64	% SZS status GaveUp for HL404416+4.p
76626.02/10796.64	eprover: CPU time limit exceeded, terminating
76626.02/10796.64	% SZS status Ended for HL404416+4.p
76661.28/10801.03	% SZS status Started for HL404422+5.p
76661.28/10801.03	% SZS status GaveUp for HL404422+5.p
76661.28/10801.03	% SZS status Ended for HL404422+5.p
76682.69/10803.73	% SZS status Started for HL404418+4.p
76682.69/10803.73	% SZS status GaveUp for HL404418+4.p
76682.69/10803.73	eprover: CPU time limit exceeded, terminating
76682.69/10803.73	% SZS status Ended for HL404418+4.p
76698.05/10805.63	% SZS status Started for HL404423+5.p
76698.05/10805.63	% SZS status GaveUp for HL404423+5.p
76698.05/10805.63	% SZS status Ended for HL404423+5.p
76703.27/10806.29	% SZS status Started for HL404420+4.p
76703.27/10806.29	% SZS status GaveUp for HL404420+4.p
76703.27/10806.29	eprover: CPU time limit exceeded, terminating
76703.27/10806.29	% SZS status Ended for HL404420+4.p
76735.48/10810.33	% SZS status Started for HL404424+5.p
76735.48/10810.33	% SZS status GaveUp for HL404424+5.p
76735.48/10810.33	% SZS status Ended for HL404424+5.p
76752.25/10812.46	% SZS status Started for HL404421+4.p
76752.25/10812.46	% SZS status GaveUp for HL404421+4.p
76752.25/10812.46	eprover: CPU time limit exceeded, terminating
76752.25/10812.46	% SZS status Ended for HL404421+4.p
76766.30/10814.34	% SZS status Started for HL404422+4.p
76766.30/10814.34	% SZS status GaveUp for HL404422+4.p
76766.30/10814.34	eprover: CPU time limit exceeded, terminating
76766.30/10814.34	% SZS status Ended for HL404422+4.p
76771.80/10814.93	% SZS status Started for HL404425+5.p
76771.80/10814.93	% SZS status GaveUp for HL404425+5.p
76771.80/10814.93	% SZS status Ended for HL404425+5.p
76802.06/10818.79	% SZS status Started for HL404423+4.p
76802.06/10818.79	% SZS status GaveUp for HL404423+4.p
76802.06/10818.79	eprover: CPU time limit exceeded, terminating
76802.06/10818.79	% SZS status Ended for HL404423+4.p
76808.06/10819.45	% SZS status Started for HL404426+5.p
76808.06/10819.45	% SZS status GaveUp for HL404426+5.p
76808.06/10819.45	% SZS status Ended for HL404426+5.p
76831.36/10822.38	% SZS status Started for HL404424+4.p
76831.36/10822.38	% SZS status GaveUp for HL404424+4.p
76831.36/10822.38	eprover: CPU time limit exceeded, terminating
76831.36/10822.38	% SZS status Ended for HL404424+4.p
76839.85/10823.50	% SZS status Started for HL404427+5.p
76839.85/10823.50	% SZS status GaveUp for HL404427+5.p
76839.85/10823.50	% SZS status Ended for HL404427+5.p
76875.80/10828.01	% SZS status Started for HL404428+5.p
76875.80/10828.01	% SZS status GaveUp for HL404428+5.p
76875.80/10828.01	% SZS status Ended for HL404428+5.p
76887.12/10829.40	% SZS status Started for HL404425+4.p
76887.12/10829.40	% SZS status GaveUp for HL404425+4.p
76887.12/10829.40	eprover: CPU time limit exceeded, terminating
76887.12/10829.40	% SZS status Ended for HL404425+4.p
76905.23/10831.69	% SZS status Started for HL404429+5.p
76905.23/10831.69	% SZS status GaveUp for HL404429+5.p
76905.23/10831.69	% SZS status Ended for HL404429+5.p
76909.96/10832.26	% SZS status Started for HL404426+4.p
76909.96/10832.26	% SZS status GaveUp for HL404426+4.p
76909.96/10832.26	eprover: CPU time limit exceeded, terminating
76909.96/10832.26	% SZS status Ended for HL404426+4.p
76949.23/10837.27	% SZS status Started for HL404430+5.p
76949.23/10837.27	% SZS status GaveUp for HL404430+5.p
76949.23/10837.27	% SZS status Ended for HL404430+5.p
76954.98/10838.07	% SZS status Started for HL404427+4.p
76954.98/10838.07	% SZS status GaveUp for HL404427+4.p
76954.98/10838.07	eprover: CPU time limit exceeded, terminating
76954.98/10838.07	% SZS status Ended for HL404427+4.p
76975.55/10840.62	% SZS status Started for HL404428+4.p
76975.55/10840.62	% SZS status GaveUp for HL404428+4.p
76975.55/10840.62	eprover: CPU time limit exceeded, terminating
76975.55/10840.62	% SZS status Ended for HL404428+4.p
76983.18/10841.53	% SZS status Started for HL404431+5.p
76983.18/10841.53	% SZS status GaveUp for HL404431+5.p
76983.18/10841.53	% SZS status Ended for HL404431+5.p
76992.64/10842.69	% SZS status Started for HL404434+4.p
76992.64/10842.69	% SZS status GaveUp for HL404434+4.p
76992.64/10842.69	eprover: CPU time limit exceeded, terminating
76992.64/10842.69	% SZS status Ended for HL404434+4.p
77018.91/10846.02	% SZS status Started for HL404429+4.p
77018.91/10846.02	% SZS status GaveUp for HL404429+4.p
77018.91/10846.02	eprover: CPU time limit exceeded, terminating
77018.91/10846.02	% SZS status Ended for HL404429+4.p
77027.26/10847.08	% SZS status Started for HL404434+5.p
77027.26/10847.08	% SZS status GaveUp for HL404434+5.p
77027.26/10847.08	% SZS status Ended for HL404434+5.p
77038.53/10848.47	% SZS status Started for HL404435+4.p
77038.53/10848.47	% SZS status GaveUp for HL404435+4.p
77038.53/10848.47	eprover: CPU time limit exceeded, terminating
77038.53/10848.47	% SZS status Ended for HL404435+4.p
77041.62/10849.09	% SZS status Started for HL404430+4.p
77041.62/10849.09	% SZS status GaveUp for HL404430+4.p
77041.62/10849.09	eprover: CPU time limit exceeded, terminating
77041.62/10849.09	% SZS status Ended for HL404430+4.p
77053.91/10850.44	% SZS status Started for HL404435+5.p
77053.91/10850.44	% SZS status GaveUp for HL404435+5.p
77053.91/10850.44	% SZS status Ended for HL404435+5.p
77058.45/10851.01	% SZS status Started for HL404438+5.p
77058.45/10851.01	% SZS status Theorem for HL404438+5.p
77058.45/10851.01	% SZS status Ended for HL404438+5.p
77065.59/10851.90	% SZS status Started for HL404436+4.p
77065.59/10851.90	% SZS status GaveUp for HL404436+4.p
77065.59/10851.90	eprover: CPU time limit exceeded, terminating
77065.59/10851.90	% SZS status Ended for HL404436+4.p
77071.77/10852.69	% SZS status Started for HL404436+5.p
77071.77/10852.69	% SZS status GaveUp for HL404436+5.p
77071.77/10852.69	% SZS status Ended for HL404436+5.p
77092.42/10855.32	% SZS status Started for HL404431+4.p
77092.42/10855.32	% SZS status GaveUp for HL404431+4.p
77092.42/10855.32	eprover: CPU time limit exceeded, terminating
77092.42/10855.32	% SZS status Ended for HL404431+4.p
77100.22/10856.41	% SZS status Started for HL404437+4.p
77100.22/10856.41	% SZS status GaveUp for HL404437+4.p
77100.22/10856.41	eprover: CPU time limit exceeded, terminating
77100.22/10856.41	% SZS status Ended for HL404437+4.p
77105.26/10856.90	% SZS status Started for HL404437+5.p
77105.26/10856.90	% SZS status GaveUp for HL404437+5.p
77105.26/10856.90	% SZS status Ended for HL404437+5.p
77117.91/10858.54	% SZS status Started for HL404439+5.p
77117.91/10858.54	% SZS status Theorem for HL404439+5.p
77117.91/10858.54	% SZS status Ended for HL404439+5.p
77120.85/10858.85	% SZS status Started for HL404438+4.p
77120.85/10858.85	% SZS status GaveUp for HL404438+4.p
77120.85/10858.85	eprover: CPU time limit exceeded, terminating
77120.85/10858.85	% SZS status Ended for HL404438+4.p
77136.22/10860.84	% SZS status Started for HL404439+4.p
77136.22/10860.84	% SZS status GaveUp for HL404439+4.p
77136.22/10860.84	eprover: CPU time limit exceeded, terminating
77136.22/10860.84	% SZS status Ended for HL404439+4.p
77147.72/10862.28	% SZS status Started for HL404440+4.p
77147.72/10862.28	% SZS status GaveUp for HL404440+4.p
77147.72/10862.28	eprover: CPU time limit exceeded, terminating
77147.72/10862.28	% SZS status Ended for HL404440+4.p
77148.20/10862.49	% SZS status Started for HL404440+5.p
77148.20/10862.49	% SZS status GaveUp for HL404440+5.p
77148.20/10862.49	% SZS status Ended for HL404440+5.p
77176.75/10865.98	% SZS status Started for HL404441+4.p
77176.75/10865.98	% SZS status GaveUp for HL404441+4.p
77176.75/10865.98	eprover: CPU time limit exceeded, terminating
77176.75/10865.98	% SZS status Ended for HL404441+4.p
77179.16/10866.21	% SZS status Started for HL404441+5.p
77179.16/10866.21	% SZS status GaveUp for HL404441+5.p
77179.16/10866.21	% SZS status Ended for HL404441+5.p
77188.77/10867.42	% SZS status Started for HL404442+4.p
77188.77/10867.42	% SZS status GaveUp for HL404442+4.p
77188.77/10867.42	eprover: CPU time limit exceeded, terminating
77188.77/10867.42	% SZS status Ended for HL404442+4.p
77195.61/10868.33	% SZS status Started for HL404442+5.p
77195.61/10868.33	% SZS status GaveUp for HL404442+5.p
77195.61/10868.33	% SZS status Ended for HL404442+5.p
77203.19/10869.22	% SZS status Started for HL404443+4.p
77203.19/10869.22	% SZS status GaveUp for HL404443+4.p
77203.19/10869.22	eprover: CPU time limit exceeded, terminating
77203.19/10869.22	% SZS status Ended for HL404443+4.p
77213.78/10870.65	% SZS status Started for HL404443+5.p
77213.78/10870.65	% SZS status GaveUp for HL404443+5.p
77213.78/10870.65	% SZS status Ended for HL404443+5.p
77226.73/10872.28	% SZS status Started for HL404444+5.p
77226.73/10872.28	% SZS status GaveUp for HL404444+5.p
77226.73/10872.28	% SZS status Ended for HL404444+5.p
77230.66/10872.66	% SZS status Started for HL404444+4.p
77230.66/10872.66	% SZS status GaveUp for HL404444+4.p
77230.66/10872.66	eprover: CPU time limit exceeded, terminating
77230.66/10872.66	% SZS status Ended for HL404444+4.p
77255.83/10876.02	% SZS status Started for HL404445+5.p
77255.83/10876.02	% SZS status GaveUp for HL404445+5.p
77255.83/10876.02	% SZS status Ended for HL404445+5.p
77259.53/10876.46	% SZS status Started for HL404445+4.p
77259.53/10876.46	% SZS status GaveUp for HL404445+4.p
77259.53/10876.46	eprover: CPU time limit exceeded, terminating
77259.53/10876.46	% SZS status Ended for HL404445+4.p
77273.80/10878.14	% SZS status Started for HL404446+5.p
77273.80/10878.14	% SZS status GaveUp for HL404446+5.p
77273.80/10878.14	% SZS status Ended for HL404446+5.p
77276.22/10878.38	% SZS status Started for HL404446+4.p
77276.22/10878.38	% SZS status GaveUp for HL404446+4.p
77276.22/10878.38	eprover: CPU time limit exceeded, terminating
77276.22/10878.38	% SZS status Ended for HL404446+4.p
77285.99/10879.61	% SZS status Started for HL404447+4.p
77285.99/10879.61	% SZS status GaveUp for HL404447+4.p
77285.99/10879.61	eprover: CPU time limit exceeded, terminating
77285.99/10879.61	% SZS status Ended for HL404447+4.p
77292.32/10880.43	% SZS status Started for HL404447+5.p
77292.32/10880.43	% SZS status GaveUp for HL404447+5.p
77292.32/10880.43	% SZS status Ended for HL404447+5.p
77305.84/10882.25	% SZS status Started for HL404452+5.p
77305.84/10882.25	% SZS status Theorem for HL404452+5.p
77305.84/10882.25	% SZS status Ended for HL404452+5.p
77308.30/10882.47	% SZS status Started for HL404448+5.p
77308.30/10882.47	% SZS status GaveUp for HL404448+5.p
77308.30/10882.47	% SZS status Ended for HL404448+5.p
77309.66/10882.68	% SZS status Started for HL404448+4.p
77309.66/10882.68	% SZS status GaveUp for HL404448+4.p
77309.66/10882.68	eprover: CPU time limit exceeded, terminating
77309.66/10882.68	% SZS status Ended for HL404448+4.p
77338.02/10886.24	% SZS status Started for HL404449+5.p
77338.02/10886.24	% SZS status GaveUp for HL404449+5.p
77338.02/10886.24	% SZS status Ended for HL404449+5.p
77341.36/10886.61	% SZS status Started for HL404449+4.p
77341.36/10886.61	% SZS status GaveUp for HL404449+4.p
77341.36/10886.61	eprover: CPU time limit exceeded, terminating
77341.36/10886.61	% SZS status Ended for HL404449+4.p
77353.85/10888.24	% SZS status Started for HL404451+5.p
77353.85/10888.24	% SZS status GaveUp for HL404451+5.p
77353.85/10888.24	% SZS status Ended for HL404451+5.p
77355.66/10888.51	% SZS status Started for HL404451+4.p
77355.66/10888.51	% SZS status GaveUp for HL404451+4.p
77355.66/10888.51	eprover: CPU time limit exceeded, terminating
77355.66/10888.51	% SZS status Ended for HL404451+4.p
77369.87/10890.33	% SZS status Started for HL404452+4.p
77369.87/10890.33	% SZS status GaveUp for HL404452+4.p
77369.87/10890.33	eprover: CPU time limit exceeded, terminating
77369.87/10890.33	% SZS status Ended for HL404452+4.p
77385.24/10892.29	% SZS status Started for HL404453+5.p
77385.24/10892.29	% SZS status GaveUp for HL404453+5.p
77385.24/10892.29	% SZS status Ended for HL404453+5.p
77388.98/10892.62	% SZS status Started for HL404453+4.p
77388.98/10892.62	% SZS status GaveUp for HL404453+4.p
77388.98/10892.62	eprover: CPU time limit exceeded, terminating
77388.98/10892.62	% SZS status Ended for HL404453+4.p
77392.44/10893.10	% SZS status Started for HL404455+4.p
77392.44/10893.10	% SZS status GaveUp for HL404455+4.p
77392.44/10893.10	eprover: CPU time limit exceeded, terminating
77392.44/10893.10	% SZS status Ended for HL404455+4.p
77402.97/10894.37	% SZS status Started for HL404459+5.p
77402.97/10894.37	% SZS status Theorem for HL404459+5.p
77402.97/10894.37	% SZS status Ended for HL404459+5.p
77415.96/10896.11	% SZS status Started for HL404455+5.p
77415.96/10896.11	% SZS status GaveUp for HL404455+5.p
77415.96/10896.11	% SZS status Ended for HL404455+5.p
77425.34/10897.22	% SZS status Started for HL404456+4.p
77425.34/10897.22	% SZS status GaveUp for HL404456+4.p
77425.34/10897.22	eprover: CPU time limit exceeded, terminating
77425.34/10897.22	% SZS status Ended for HL404456+4.p
77431.58/10898.03	% SZS status Started for HL404456+5.p
77431.58/10898.03	% SZS status GaveUp for HL404456+5.p
77431.58/10898.03	% SZS status Ended for HL404456+5.p
77439.35/10899.00	% SZS status Started for HL404457+4.p
77439.35/10899.00	% SZS status GaveUp for HL404457+4.p
77439.35/10899.00	eprover: CPU time limit exceeded, terminating
77439.35/10899.00	% SZS status Ended for HL404457+4.p
77446.39/10899.87	% SZS status Started for HL404457+5.p
77446.39/10899.87	% SZS status GaveUp for HL404457+5.p
77446.39/10899.87	% SZS status Ended for HL404457+5.p
77462.34/10901.94	% SZS status Started for HL404460+5.p
77462.34/10901.94	% SZS status Theorem for HL404460+5.p
77462.34/10901.94	% SZS status Ended for HL404460+5.p
77470.15/10902.90	% SZS status Started for HL404459+4.p
77470.15/10902.90	% SZS status GaveUp for HL404459+4.p
77470.15/10902.90	eprover: CPU time limit exceeded, terminating
77470.15/10902.90	% SZS status Ended for HL404459+4.p
77475.07/10903.47	% SZS status Started for HL404460+4.p
77475.07/10903.47	% SZS status GaveUp for HL404460+4.p
77475.07/10903.47	eprover: CPU time limit exceeded, terminating
77475.07/10903.47	% SZS status Ended for HL404460+4.p
77479.74/10904.05	% SZS status Started for HL404463+5.p
77479.74/10904.05	% SZS status Theorem for HL404463+5.p
77479.74/10904.05	% SZS status Ended for HL404463+5.p
77480.38/10904.17	% SZS status Started for HL404461+5.p
77480.38/10904.17	% SZS status Theorem for HL404461+5.p
77480.38/10904.17	% SZS status Ended for HL404461+5.p
77499.48/10906.78	% SZS status Started for HL404461+4.p
77499.48/10906.78	% SZS status GaveUp for HL404461+4.p
77499.48/10906.78	eprover: CPU time limit exceeded, terminating
77499.48/10906.78	% SZS status Ended for HL404461+4.p
77514.07/10908.47	% SZS status Started for HL404462+4.p
77514.07/10908.47	% SZS status GaveUp for HL404462+4.p
77514.07/10908.47	eprover: CPU time limit exceeded, terminating
77514.07/10908.47	% SZS status Ended for HL404462+4.p
77522.56/10909.57	% SZS status Started for HL404467+5.p
77522.56/10909.57	% SZS status Theorem for HL404467+5.p
77522.56/10909.57	% SZS status Ended for HL404467+5.p
77528.31/10910.22	% SZS status Started for HL404463+4.p
77528.31/10910.22	% SZS status GaveUp for HL404463+4.p
77528.31/10910.22	eprover: CPU time limit exceeded, terminating
77528.31/10910.22	% SZS status Ended for HL404463+4.p
77546.80/10912.48	% SZS status Started for HL404464+5.p
77546.80/10912.48	% SZS status GaveUp for HL404464+5.p
77546.80/10912.48	% SZS status Ended for HL404464+5.p
77552.63/10913.21	% SZS status Started for HL404465+5.p
77552.63/10913.21	% SZS status GaveUp for HL404465+5.p
77552.63/10913.21	% SZS status Ended for HL404465+5.p
77561.86/10914.38	% SZS status Started for HL404469+5.p
77561.86/10914.38	% SZS status Theorem for HL404469+5.p
77561.86/10914.38	% SZS status Ended for HL404469+5.p
77579.76/10916.75	% SZS status Started for HL404468+5.p
77579.76/10916.75	% SZS status Theorem for HL404468+5.p
77579.76/10916.75	% SZS status Ended for HL404468+5.p
77589.97/10917.95	% SZS status Started for HL404471+5.p
77589.97/10917.95	% SZS status Theorem for HL404471+5.p
77589.97/10917.95	% SZS status Ended for HL404471+5.p
77635.42/10923.75	% SZS status Started for HL404462+5.p
77635.42/10923.75	% SZS status GaveUp for HL404462+5.p
77635.42/10923.75	eprover: CPU time limit exceeded, terminating
77635.42/10923.75	% SZS status Ended for HL404462+5.p
77673.78/10928.42	% SZS status Started for HL404464+4.p
77673.78/10928.42	% SZS status GaveUp for HL404464+4.p
77673.78/10928.42	eprover: CPU time limit exceeded, terminating
77673.78/10928.42	% SZS status Ended for HL404464+4.p
77685.78/10930.01	% SZS status Started for HL404465+4.p
77685.78/10930.01	% SZS status GaveUp for HL404465+4.p
77685.78/10930.01	eprover: CPU time limit exceeded, terminating
77685.78/10930.01	% SZS status Ended for HL404465+4.p
77704.68/10932.33	% SZS status Started for HL404467+4.p
77704.68/10932.33	% SZS status GaveUp for HL404467+4.p
77704.68/10932.33	eprover: CPU time limit exceeded, terminating
77704.68/10932.33	% SZS status Ended for HL404467+4.p
77711.45/10933.27	% SZS status Started for HL404472+5.p
77711.45/10933.27	% SZS status GaveUp for HL404472+5.p
77711.45/10933.27	% SZS status Ended for HL404472+5.p
77729.23/10935.48	% SZS status Started for HL404468+4.p
77729.23/10935.48	% SZS status GaveUp for HL404468+4.p
77729.23/10935.48	eprover: CPU time limit exceeded, terminating
77729.23/10935.48	% SZS status Ended for HL404468+4.p
77750.02/10938.05	% SZS status Started for HL404469+4.p
77750.02/10938.05	% SZS status GaveUp for HL404469+4.p
77750.02/10938.05	eprover: CPU time limit exceeded, terminating
77750.02/10938.05	% SZS status Ended for HL404469+4.p
77758.71/10939.18	% SZS status Started for HL404473+5.p
77758.71/10939.18	% SZS status GaveUp for HL404473+5.p
77758.71/10939.18	% SZS status Ended for HL404473+5.p
77765.46/10939.98	% SZS status Started for HL404471+4.p
77765.46/10939.98	% SZS status GaveUp for HL404471+4.p
77765.46/10939.98	eprover: CPU time limit exceeded, terminating
77765.46/10939.98	% SZS status Ended for HL404471+4.p
77783.78/10942.35	% SZS status Started for HL404474+5.p
77783.78/10942.35	% SZS status GaveUp for HL404474+5.p
77783.78/10942.35	% SZS status Ended for HL404474+5.p
77793.48/10943.61	% SZS status Started for HL404472+4.p
77793.48/10943.61	% SZS status GaveUp for HL404472+4.p
77793.48/10943.61	eprover: CPU time limit exceeded, terminating
77793.48/10943.61	% SZS status Ended for HL404472+4.p
77797.87/10944.19	% SZS status Started for HL404475+5.p
77797.87/10944.19	% SZS status Theorem for HL404475+5.p
77797.87/10944.19	% SZS status Ended for HL404475+5.p
77837.12/10949.06	% SZS status Started for HL404476+5.p
77837.12/10949.06	% SZS status GaveUp for HL404476+5.p
77837.12/10949.06	% SZS status Ended for HL404476+5.p
77841.31/10949.55	% SZS status Started for HL404477+5.p
77841.31/10949.55	% SZS status Theorem for HL404477+5.p
77841.31/10949.55	% SZS status Ended for HL404477+5.p
77878.06/10954.16	% SZS status Started for HL404473+4.p
77878.06/10954.16	% SZS status GaveUp for HL404473+4.p
77878.06/10954.16	eprover: CPU time limit exceeded, terminating
77878.06/10954.16	% SZS status Ended for HL404473+4.p
77908.59/10958.06	% SZS status Started for HL404474+4.p
77908.59/10958.06	% SZS status GaveUp for HL404474+4.p
77908.59/10958.06	eprover: CPU time limit exceeded, terminating
77908.59/10958.06	% SZS status Ended for HL404474+4.p
77908.59/10958.07	% SZS status Started for HL404478+5.p
77908.59/10958.07	% SZS status GaveUp for HL404478+5.p
77908.59/10958.07	% SZS status Ended for HL404478+5.p
77932.46/10961.04	% SZS status Started for HL404475+4.p
77932.46/10961.04	% SZS status GaveUp for HL404475+4.p
77932.46/10961.04	eprover: CPU time limit exceeded, terminating
77932.46/10961.04	% SZS status Ended for HL404475+4.p
77950.98/10963.47	% SZS status Started for HL404479+5.p
77950.98/10963.47	% SZS status GaveUp for HL404479+5.p
77950.98/10963.47	% SZS status Ended for HL404479+5.p
77965.58/10965.28	% SZS status Started for HL404476+4.p
77965.58/10965.28	% SZS status GaveUp for HL404476+4.p
77965.58/10965.28	eprover: CPU time limit exceeded, terminating
77965.58/10965.28	% SZS status Ended for HL404476+4.p
77980.41/10967.07	% SZS status Started for HL404480+5.p
77980.41/10967.07	% SZS status GaveUp for HL404480+5.p
77980.41/10967.07	% SZS status Ended for HL404480+5.p
77987.28/10967.94	% SZS status Started for HL404477+4.p
77987.28/10967.94	% SZS status GaveUp for HL404477+4.p
77987.28/10967.94	eprover: CPU time limit exceeded, terminating
77987.28/10967.94	% SZS status Ended for HL404477+4.p
78003.38/10969.94	% SZS status Started for HL404478+4.p
78003.38/10969.94	% SZS status GaveUp for HL404478+4.p
78003.38/10969.94	eprover: CPU time limit exceeded, terminating
78003.38/10969.94	% SZS status Ended for HL404478+4.p
78016.92/10971.61	% SZS status Started for HL404485+5.p
78016.92/10971.61	% SZS status Theorem for HL404485+5.p
78016.92/10971.61	% SZS status Ended for HL404485+5.p
78023.61/10972.51	% SZS status Started for HL404482+5.p
78023.61/10972.51	% SZS status GaveUp for HL404482+5.p
78023.61/10972.51	% SZS status Ended for HL404482+5.p
78045.16/10975.24	% SZS status Started for HL404479+4.p
78045.16/10975.24	% SZS status GaveUp for HL404479+4.p
78045.16/10975.24	eprover: CPU time limit exceeded, terminating
78045.16/10975.24	% SZS status Ended for HL404479+4.p
78052.46/10976.16	% SZS status Started for HL404484+5.p
78052.46/10976.16	% SZS status GaveUp for HL404484+5.p
78052.46/10976.16	% SZS status Ended for HL404484+5.p
78095.58/10981.54	% SZS status Started for HL404486+5.p
78095.58/10981.54	% SZS status GaveUp for HL404486+5.p
78095.58/10981.54	% SZS status Ended for HL404486+5.p
78112.40/10983.77	% SZS status Started for HL404480+4.p
78112.40/10983.77	% SZS status GaveUp for HL404480+4.p
78112.40/10983.77	eprover: CPU time limit exceeded, terminating
78112.40/10983.77	% SZS status Ended for HL404480+4.p
78125.38/10985.39	% SZS status Started for HL404487+5.p
78125.38/10985.39	% SZS status GaveUp for HL404487+5.p
78125.38/10985.39	% SZS status Ended for HL404487+5.p
78136.58/10986.74	% SZS status Started for HL404482+4.p
78136.58/10986.74	% SZS status GaveUp for HL404482+4.p
78136.58/10986.74	eprover: CPU time limit exceeded, terminating
78136.58/10986.74	% SZS status Ended for HL404482+4.p
78171.34/10991.15	% SZS status Started for HL404484+4.p
78171.34/10991.15	% SZS status GaveUp for HL404484+4.p
78171.34/10991.15	eprover: CPU time limit exceeded, terminating
78171.34/10991.15	% SZS status Ended for HL404484+4.p
78177.86/10992.00	% SZS status Started for HL404489+5.p
78177.86/10992.00	% SZS status Theorem for HL404489+5.p
78177.86/10992.00	% SZS status Ended for HL404489+5.p
78185.94/10993.00	% SZS status Started for HL404488+5.p
78185.94/10993.00	% SZS status GaveUp for HL404488+5.p
78185.94/10993.00	% SZS status Ended for HL404488+5.p
78191.31/10993.67	% SZS status Started for HL404485+4.p
78191.31/10993.67	% SZS status GaveUp for HL404485+4.p
78191.31/10993.67	eprover: CPU time limit exceeded, terminating
78191.31/10993.67	% SZS status Ended for HL404485+4.p
78220.26/10997.34	% SZS status Started for HL404486+4.p
78220.26/10997.34	% SZS status GaveUp for HL404486+4.p
78220.26/10997.34	eprover: CPU time limit exceeded, terminating
78220.26/10997.34	% SZS status Ended for HL404486+4.p
78231.85/10998.74	% SZS status Started for HL404491+5.p
78231.85/10998.74	% SZS status Theorem for HL404491+5.p
78231.85/10998.74	% SZS status Ended for HL404491+5.p
78249.88/11001.00	% SZS status Started for HL404490+5.p
78249.88/11001.00	% SZS status GaveUp for HL404490+5.p
78249.88/11001.00	% SZS status Ended for HL404490+5.p
78251.04/11001.18	% SZS status Started for HL404487+4.p
78251.04/11001.18	% SZS status GaveUp for HL404487+4.p
78251.04/11001.18	eprover: CPU time limit exceeded, terminating
78251.04/11001.18	% SZS status Ended for HL404487+4.p
78299.84/11007.32	% SZS status Started for HL404488+4.p
78299.84/11007.32	% SZS status GaveUp for HL404488+4.p
78299.84/11007.32	eprover: CPU time limit exceeded, terminating
78299.84/11007.32	% SZS status Ended for HL404488+4.p
78303.45/11007.80	% SZS status Started for HL404492+5.p
78303.45/11007.80	% SZS status GaveUp for HL404492+5.p
78303.45/11007.80	% SZS status Ended for HL404492+5.p
78314.06/11009.14	% SZS status Started for HL404495+5.p
78314.06/11009.14	% SZS status Theorem for HL404495+5.p
78314.06/11009.14	% SZS status Ended for HL404495+5.p
78330.38/11011.18	% SZS status Started for HL404489+4.p
78330.38/11011.18	% SZS status GaveUp for HL404489+4.p
78330.38/11011.18	eprover: CPU time limit exceeded, terminating
78330.38/11011.18	% SZS status Ended for HL404489+4.p
78374.94/11016.85	% SZS status Started for HL404496+5.p
78374.94/11016.85	% SZS status GaveUp for HL404496+5.p
78374.94/11016.85	% SZS status Ended for HL404496+5.p
78375.80/11016.91	% SZS status Started for HL404490+4.p
78375.80/11016.91	% SZS status GaveUp for HL404490+4.p
78375.80/11016.91	eprover: CPU time limit exceeded, terminating
78375.80/11016.91	% SZS status Ended for HL404490+4.p
78385.95/11018.15	% SZS status Started for HL404498+5.p
78385.95/11018.15	% SZS status Theorem for HL404498+5.p
78385.95/11018.15	% SZS status Ended for HL404498+5.p
78390.82/11018.81	% SZS status Started for HL404491+4.p
78390.82/11018.81	% SZS status GaveUp for HL404491+4.p
78390.82/11018.81	eprover: CPU time limit exceeded, terminating
78390.82/11018.81	% SZS status Ended for HL404491+4.p
78401.30/11020.14	% SZS status Started for HL404501+5.p
78401.30/11020.14	% SZS status Theorem for HL404501+5.p
78401.30/11020.14	% SZS status Ended for HL404501+5.p
78402.23/11020.25	% SZS status Started for HL404497+5.p
78402.23/11020.25	% SZS status GaveUp for HL404497+5.p
78402.23/11020.25	% SZS status Ended for HL404497+5.p
78411.41/11021.46	% SZS status Started for HL404502+5.p
78411.41/11021.46	% SZS status Theorem for HL404502+5.p
78411.41/11021.46	% SZS status Ended for HL404502+5.p
78426.43/11023.34	% SZS status Started for HL404492+4.p
78426.43/11023.34	% SZS status GaveUp for HL404492+4.p
78426.43/11023.34	eprover: CPU time limit exceeded, terminating
78426.43/11023.34	% SZS status Ended for HL404492+4.p
78453.27/11026.70	% SZS status Started for HL404495+4.p
78453.27/11026.70	% SZS status GaveUp for HL404495+4.p
78453.27/11026.70	eprover: CPU time limit exceeded, terminating
78453.27/11026.70	% SZS status Ended for HL404495+4.p
78498.59/11032.38	% SZS status Started for HL404503+5.p
78498.59/11032.38	% SZS status GaveUp for HL404503+5.p
78498.59/11032.38	% SZS status Ended for HL404503+5.p
78506.83/11033.42	% SZS status Started for HL404496+4.p
78506.83/11033.42	% SZS status GaveUp for HL404496+4.p
78506.83/11033.42	eprover: CPU time limit exceeded, terminating
78506.83/11033.42	% SZS status Ended for HL404496+4.p
78521.46/11035.32	% SZS status Started for HL404497+4.p
78521.46/11035.32	% SZS status GaveUp for HL404497+4.p
78521.46/11035.32	eprover: CPU time limit exceeded, terminating
78521.46/11035.32	% SZS status Ended for HL404497+4.p
78571.02/11041.45	% SZS status Started for HL404504+5.p
78571.02/11041.45	% SZS status GaveUp for HL404504+5.p
78571.02/11041.45	% SZS status Ended for HL404504+5.p
78578.91/11042.46	% SZS status Started for HL404498+4.p
78578.91/11042.46	% SZS status GaveUp for HL404498+4.p
78578.91/11042.46	eprover: CPU time limit exceeded, terminating
78578.91/11042.46	% SZS status Ended for HL404498+4.p
78589.19/11043.82	% SZS status Started for HL404501+4.p
78589.19/11043.82	% SZS status GaveUp for HL404501+4.p
78589.19/11043.82	eprover: CPU time limit exceeded, terminating
78589.19/11043.82	% SZS status Ended for HL404501+4.p
78593.75/11044.34	% SZS status Started for HL404505+5.p
78593.75/11044.34	% SZS status GaveUp for HL404505+5.p
78593.75/11044.34	% SZS status Ended for HL404505+5.p
78607.80/11046.12	% SZS status Started for HL404502+4.p
78607.80/11046.12	% SZS status GaveUp for HL404502+4.p
78607.80/11046.12	eprover: CPU time limit exceeded, terminating
78607.80/11046.12	% SZS status Ended for HL404502+4.p
78615.91/11047.08	% SZS status Started for HL404503+4.p
78615.91/11047.08	% SZS status GaveUp for HL404503+4.p
78615.91/11047.08	eprover: CPU time limit exceeded, terminating
78615.91/11047.08	% SZS status Ended for HL404503+4.p
78628.51/11048.70	% SZS status Started for HL404509+5.p
78628.51/11048.70	% SZS status Theorem for HL404509+5.p
78628.51/11048.70	% SZS status Ended for HL404509+5.p
78650.85/11051.52	% SZS status Started for HL404507+5.p
78650.85/11051.52	% SZS status GaveUp for HL404507+5.p
78650.85/11051.52	% SZS status Ended for HL404507+5.p
78659.24/11052.57	% SZS status Started for HL404504+4.p
78659.24/11052.57	% SZS status GaveUp for HL404504+4.p
78659.24/11052.57	eprover: CPU time limit exceeded, terminating
78659.24/11052.57	% SZS status Ended for HL404504+4.p
78664.15/11053.16	% SZS status Started for HL404510+5.p
78664.15/11053.16	% SZS status Theorem for HL404510+5.p
78664.15/11053.16	% SZS status Ended for HL404510+5.p
78666.61/11053.46	% SZS status Started for HL404508+5.p
78666.61/11053.46	% SZS status GaveUp for HL404508+5.p
78666.61/11053.46	% SZS status Ended for HL404508+5.p
78678.65/11055.02	% SZS status Started for HL404512+5.p
78678.65/11055.02	% SZS status Theorem for HL404512+5.p
78678.65/11055.02	% SZS status Ended for HL404512+5.p
78712.65/11059.31	% SZS status Started for HL404505+4.p
78712.65/11059.31	% SZS status GaveUp for HL404505+4.p
78712.65/11059.31	eprover: CPU time limit exceeded, terminating
78712.65/11059.31	% SZS status Ended for HL404505+4.p
78752.37/11064.30	% SZS status Started for HL404513+5.p
78752.37/11064.30	% SZS status GaveUp for HL404513+5.p
78752.37/11064.30	% SZS status Ended for HL404513+5.p
78775.44/11067.17	% SZS status Started for HL404507+4.p
78775.44/11067.17	% SZS status GaveUp for HL404507+4.p
78775.44/11067.17	eprover: CPU time limit exceeded, terminating
78775.44/11067.17	% SZS status Ended for HL404507+4.p
78795.95/11069.76	% SZS status Started for HL404508+4.p
78795.95/11069.76	% SZS status GaveUp for HL404508+4.p
78795.95/11069.76	eprover: CPU time limit exceeded, terminating
78795.95/11069.76	% SZS status Ended for HL404508+4.p
78812.52/11071.89	% SZS status Started for HL404509+4.p
78812.52/11071.89	% SZS status GaveUp for HL404509+4.p
78812.52/11071.89	eprover: CPU time limit exceeded, terminating
78812.52/11071.89	% SZS status Ended for HL404509+4.p
78824.77/11073.46	% SZS status Started for HL404515+5.p
78824.77/11073.46	% SZS status GaveUp for HL404515+5.p
78824.77/11073.46	% SZS status Ended for HL404515+5.p
78831.74/11074.32	% SZS status Started for HL404510+4.p
78831.74/11074.32	% SZS status GaveUp for HL404510+4.p
78831.74/11074.32	eprover: CPU time limit exceeded, terminating
78831.74/11074.32	% SZS status Ended for HL404510+4.p
78865.35/11078.27	% SZS status Started for HL404512+4.p
78865.35/11078.27	% SZS status GaveUp for HL404512+4.p
78865.35/11078.27	eprover: CPU time limit exceeded, terminating
78865.35/11078.27	% SZS status Ended for HL404512+4.p
78871.25/11079.03	% SZS status Started for HL404516+5.p
78871.25/11079.03	% SZS status GaveUp for HL404516+5.p
78871.25/11079.03	% SZS status Ended for HL404516+5.p
78872.88/11079.20	% SZS status Started for HL404513+4.p
78872.88/11079.20	% SZS status GaveUp for HL404513+4.p
78872.88/11079.20	eprover: CPU time limit exceeded, terminating
78872.88/11079.20	% SZS status Ended for HL404513+4.p
78896.62/11082.24	% SZS status Started for HL404518+5.p
78896.62/11082.24	% SZS status Theorem for HL404518+5.p
78896.62/11082.24	% SZS status Ended for HL404518+5.p
78900.63/11082.72	% SZS status Started for HL404517+5.p
78900.63/11082.72	% SZS status GaveUp for HL404517+5.p
78900.63/11082.72	% SZS status Ended for HL404517+5.p
78919.59/11085.13	% SZS status Started for HL404515+4.p
78919.59/11085.13	% SZS status GaveUp for HL404515+4.p
78919.59/11085.13	eprover: CPU time limit exceeded, terminating
78919.59/11085.13	% SZS status Ended for HL404515+4.p
78946.07/11088.41	% SZS status Started for HL404520+5.p
78946.07/11088.41	% SZS status GaveUp for HL404520+5.p
78946.07/11088.41	% SZS status Ended for HL404520+5.p
78977.05/11092.30	% SZS status Started for HL404521+5.p
78977.05/11092.30	% SZS status GaveUp for HL404521+5.p
78977.05/11092.30	% SZS status Ended for HL404521+5.p
78983.20/11093.10	% SZS status Started for HL404516+4.p
78983.20/11093.10	% SZS status GaveUp for HL404516+4.p
78983.20/11093.10	eprover: CPU time limit exceeded, terminating
78983.20/11093.10	% SZS status Ended for HL404516+4.p
79018.84/11097.53	% SZS status Started for HL404522+5.p
79018.84/11097.53	% SZS status GaveUp for HL404522+5.p
79018.84/11097.53	% SZS status Ended for HL404522+5.p
79019.30/11097.61	% SZS status Started for HL404517+4.p
79019.30/11097.61	% SZS status GaveUp for HL404517+4.p
79019.30/11097.61	eprover: CPU time limit exceeded, terminating
79019.30/11097.61	% SZS status Ended for HL404517+4.p
79038.03/11099.96	% SZS status Started for HL404518+4.p
79038.03/11099.96	% SZS status GaveUp for HL404518+4.p
79038.03/11099.96	eprover: CPU time limit exceeded, terminating
79038.03/11099.96	% SZS status Ended for HL404518+4.p
79056.44/11102.34	% SZS status Started for HL404523+5.p
79056.44/11102.34	% SZS status GaveUp for HL404523+5.p
79056.44/11102.34	% SZS status Ended for HL404523+5.p
79074.67/11104.64	% SZS status Started for HL404520+4.p
79074.67/11104.64	% SZS status GaveUp for HL404520+4.p
79074.67/11104.64	eprover: CPU time limit exceeded, terminating
79074.67/11104.64	% SZS status Ended for HL404520+4.p
79093.02/11106.87	% SZS status Started for HL404524+5.p
79093.02/11106.87	% SZS status GaveUp for HL404524+5.p
79093.02/11106.87	% SZS status Ended for HL404524+5.p
79104.05/11108.23	% SZS status Started for HL404521+4.p
79104.05/11108.23	% SZS status GaveUp for HL404521+4.p
79104.05/11108.23	eprover: CPU time limit exceeded, terminating
79104.05/11108.23	% SZS status Ended for HL404521+4.p
79124.20/11110.78	% SZS status Started for HL404522+4.p
79124.20/11110.78	% SZS status GaveUp for HL404522+4.p
79124.20/11110.78	eprover: CPU time limit exceeded, terminating
79124.20/11110.78	% SZS status Ended for HL404522+4.p
79128.67/11111.36	% SZS status Started for HL404525+5.p
79128.67/11111.36	% SZS status GaveUp for HL404525+5.p
79128.67/11111.36	% SZS status Ended for HL404525+5.p
79164.97/11115.96	% SZS status Started for HL404526+5.p
79164.97/11115.96	% SZS status GaveUp for HL404526+5.p
79164.97/11115.96	% SZS status Ended for HL404526+5.p
79183.33/11118.31	% SZS status Started for HL404523+4.p
79183.33/11118.31	% SZS status GaveUp for HL404523+4.p
79183.33/11118.31	eprover: CPU time limit exceeded, terminating
79183.33/11118.31	% SZS status Ended for HL404523+4.p
79195.85/11119.88	% SZS status Started for HL404527+5.p
79195.85/11119.88	% SZS status GaveUp for HL404527+5.p
79195.85/11119.88	% SZS status Ended for HL404527+5.p
79225.02/11123.59	% SZS status Started for HL404524+4.p
79225.02/11123.59	% SZS status GaveUp for HL404524+4.p
79225.02/11123.59	eprover: CPU time limit exceeded, terminating
79225.02/11123.59	% SZS status Ended for HL404524+4.p
79240.78/11125.59	% SZS status Started for HL404528+5.p
79240.78/11125.59	% SZS status GaveUp for HL404528+5.p
79240.78/11125.59	% SZS status Ended for HL404528+5.p
79242.27/11125.75	% SZS status Started for HL404525+4.p
79242.27/11125.75	% SZS status GaveUp for HL404525+4.p
79242.27/11125.75	eprover: CPU time limit exceeded, terminating
79242.27/11125.75	% SZS status Ended for HL404525+4.p
79270.09/11129.24	% SZS status Started for HL404529+5.p
79270.09/11129.24	% SZS status GaveUp for HL404529+5.p
79270.09/11129.24	% SZS status Ended for HL404529+5.p
79278.81/11130.42	% SZS status Started for HL404526+4.p
79278.81/11130.42	% SZS status GaveUp for HL404526+4.p
79278.81/11130.42	eprover: CPU time limit exceeded, terminating
79278.81/11130.42	% SZS status Ended for HL404526+4.p
79308.47/11134.12	% SZS status Started for HL404527+4.p
79308.47/11134.12	% SZS status GaveUp for HL404527+4.p
79308.47/11134.12	eprover: CPU time limit exceeded, terminating
79308.47/11134.12	% SZS status Ended for HL404527+4.p
79313.45/11134.70	% SZS status Started for HL404530+5.p
79313.45/11134.70	% SZS status GaveUp for HL404530+5.p
79313.45/11134.70	% SZS status Ended for HL404530+5.p
79332.50/11137.12	% SZS status Started for HL404528+4.p
79332.50/11137.12	% SZS status GaveUp for HL404528+4.p
79332.50/11137.12	eprover: CPU time limit exceeded, terminating
79332.50/11137.12	% SZS status Ended for HL404528+4.p
79341.70/11138.29	% SZS status Started for HL404531+5.p
79341.70/11138.29	% SZS status GaveUp for HL404531+5.p
79341.70/11138.29	% SZS status Ended for HL404531+5.p
79381.43/11143.27	% SZS status Started for HL404532+5.p
79381.43/11143.27	% SZS status GaveUp for HL404532+5.p
79381.43/11143.27	% SZS status Ended for HL404532+5.p
79390.63/11144.46	% SZS status Started for HL404529+4.p
79390.63/11144.46	% SZS status GaveUp for HL404529+4.p
79390.63/11144.46	eprover: CPU time limit exceeded, terminating
79390.63/11144.46	% SZS status Ended for HL404529+4.p
79405.23/11146.31	% SZS status Started for HL404534+5.p
79405.23/11146.31	% SZS status GaveUp for HL404534+5.p
79405.23/11146.31	% SZS status Ended for HL404534+5.p
79430.02/11149.39	% SZS status Started for HL404530+4.p
79430.02/11149.39	% SZS status GaveUp for HL404530+4.p
79430.02/11149.39	eprover: CPU time limit exceeded, terminating
79430.02/11149.39	% SZS status Ended for HL404530+4.p
79446.33/11151.48	% SZS status Started for HL404531+4.p
79446.33/11151.48	% SZS status GaveUp for HL404531+4.p
79446.33/11151.48	eprover: CPU time limit exceeded, terminating
79446.33/11151.48	% SZS status Ended for HL404531+4.p
79453.64/11152.38	% SZS status Started for HL404535+5.p
79453.64/11152.38	% SZS status GaveUp for HL404535+5.p
79453.64/11152.38	% SZS status Ended for HL404535+5.p
79478.40/11155.47	% SZS status Started for HL404536+5.p
79478.40/11155.47	% SZS status GaveUp for HL404536+5.p
79478.40/11155.47	% SZS status Ended for HL404536+5.p
79482.41/11156.01	% SZS status Started for HL404532+4.p
79482.41/11156.01	% SZS status GaveUp for HL404532+4.p
79482.41/11156.01	eprover: CPU time limit exceeded, terminating
79482.41/11156.01	% SZS status Ended for HL404532+4.p
79516.98/11160.33	% SZS status Started for HL404534+4.p
79516.98/11160.33	% SZS status GaveUp for HL404534+4.p
79516.98/11160.33	eprover: CPU time limit exceeded, terminating
79516.98/11160.33	% SZS status Ended for HL404534+4.p
79519.55/11160.66	% SZS status Started for HL404538+5.p
79519.55/11160.66	% SZS status GaveUp for HL404538+5.p
79519.55/11160.66	% SZS status Ended for HL404538+5.p
79544.91/11163.93	% SZS status Started for HL404535+4.p
79544.91/11163.93	% SZS status GaveUp for HL404535+4.p
79544.91/11163.93	eprover: CPU time limit exceeded, terminating
79544.91/11163.93	% SZS status Ended for HL404535+4.p
79551.86/11164.74	% SZS status Started for HL404539+5.p
79551.86/11164.74	% SZS status GaveUp for HL404539+5.p
79551.86/11164.74	% SZS status Ended for HL404539+5.p
79590.84/11169.60	% SZS status Started for HL404540+5.p
79590.84/11169.60	% SZS status GaveUp for HL404540+5.p
79590.84/11169.60	% SZS status Ended for HL404540+5.p
79594.16/11170.06	% SZS status Started for HL404536+4.p
79594.16/11170.06	% SZS status GaveUp for HL404536+4.p
79594.16/11170.06	eprover: CPU time limit exceeded, terminating
79594.16/11170.06	% SZS status Ended for HL404536+4.p
79619.52/11173.27	% SZS status Started for HL404541+5.p
79619.52/11173.27	% SZS status GaveUp for HL404541+5.p
79619.52/11173.27	% SZS status Ended for HL404541+5.p
79635.48/11175.26	% SZS status Started for HL404538+4.p
79635.48/11175.26	% SZS status GaveUp for HL404538+4.p
79635.48/11175.26	eprover: CPU time limit exceeded, terminating
79635.48/11175.26	% SZS status Ended for HL404538+4.p
79658.70/11178.24	% SZS status Started for HL404539+4.p
79658.70/11178.24	% SZS status GaveUp for HL404539+4.p
79658.70/11178.24	eprover: CPU time limit exceeded, terminating
79658.70/11178.24	% SZS status Ended for HL404539+4.p
79661.34/11178.62	% SZS status Started for HL404542+5.p
79661.34/11178.62	% SZS status GaveUp for HL404542+5.p
79661.34/11178.62	% SZS status Ended for HL404542+5.p
79687.16/11181.85	% SZS status Started for HL404540+4.p
79687.16/11181.85	% SZS status GaveUp for HL404540+4.p
79687.16/11181.85	eprover: CPU time limit exceeded, terminating
79687.16/11181.85	% SZS status Ended for HL404540+4.p
79692.84/11182.50	% SZS status Started for HL404543+5.p
79692.84/11182.50	% SZS status GaveUp for HL404543+5.p
79692.84/11182.50	% SZS status Ended for HL404543+5.p
79723.24/11186.29	% SZS status Started for HL404541+4.p
79723.24/11186.29	% SZS status GaveUp for HL404541+4.p
79723.24/11186.29	eprover: CPU time limit exceeded, terminating
79723.24/11186.29	% SZS status Ended for HL404541+4.p
79732.09/11187.42	% SZS status Started for HL404544+5.p
79732.09/11187.42	% SZS status GaveUp for HL404544+5.p
79732.09/11187.42	% SZS status Ended for HL404544+5.p
79756.08/11190.47	% SZS status Started for HL404542+4.p
79756.08/11190.47	% SZS status GaveUp for HL404542+4.p
79756.08/11190.47	eprover: CPU time limit exceeded, terminating
79756.08/11190.47	% SZS status Ended for HL404542+4.p
79762.01/11191.17	% SZS status Started for HL404545+5.p
79762.01/11191.17	% SZS status GaveUp for HL404545+5.p
79762.01/11191.17	% SZS status Ended for HL404545+5.p
79797.05/11195.63	% SZS status Started for HL404546+5.p
79797.05/11195.63	% SZS status GaveUp for HL404546+5.p
79797.05/11195.63	% SZS status Ended for HL404546+5.p
79798.34/11195.92	% SZS status Started for HL404543+4.p
79798.34/11195.92	% SZS status GaveUp for HL404543+4.p
79798.34/11195.92	eprover: CPU time limit exceeded, terminating
79798.34/11195.92	% SZS status Ended for HL404543+4.p
79828.18/11199.51	% SZS status Started for HL404547+5.p
79828.18/11199.51	% SZS status GaveUp for HL404547+5.p
79828.18/11199.51	% SZS status Ended for HL404547+5.p
79839.87/11201.04	% SZS status Started for HL404544+4.p
79839.87/11201.04	% SZS status GaveUp for HL404544+4.p
79839.87/11201.04	eprover: CPU time limit exceeded, terminating
79839.87/11201.04	% SZS status Ended for HL404544+4.p
79851.65/11202.50	% SZS status Started for HL404549+5.p
79851.65/11202.50	% SZS status Theorem for HL404549+5.p
79851.65/11202.50	% SZS status Ended for HL404549+5.p
79868.55/11204.61	% SZS status Started for HL404545+4.p
79868.55/11204.61	% SZS status GaveUp for HL404545+4.p
79868.55/11204.61	eprover: CPU time limit exceeded, terminating
79868.55/11204.61	% SZS status Ended for HL404545+4.p
79871.93/11205.01	% SZS status Started for HL404548+5.p
79871.93/11205.01	% SZS status GaveUp for HL404548+5.p
79871.93/11205.01	% SZS status Ended for HL404548+5.p
79898.28/11208.38	% SZS status Started for HL404546+4.p
79898.28/11208.38	% SZS status GaveUp for HL404546+4.p
79898.28/11208.38	eprover: CPU time limit exceeded, terminating
79898.28/11208.38	% SZS status Ended for HL404546+4.p
79926.77/11211.91	% SZS status Started for HL404550+5.p
79926.77/11211.91	% SZS status GaveUp for HL404550+5.p
79926.77/11211.91	% SZS status Ended for HL404550+5.p
79935.82/11213.08	% SZS status Started for HL404547+4.p
79935.82/11213.08	% SZS status GaveUp for HL404547+4.p
79935.82/11213.08	eprover: CPU time limit exceeded, terminating
79935.82/11213.08	% SZS status Ended for HL404547+4.p
79945.17/11214.21	% SZS status Started for HL404551+5.p
79945.17/11214.21	% SZS status GaveUp for HL404551+5.p
79945.17/11214.21	% SZS status Ended for HL404551+5.p
79965.81/11216.83	% SZS status Started for HL404548+4.p
79965.81/11216.83	% SZS status GaveUp for HL404548+4.p
79965.81/11216.83	eprover: CPU time limit exceeded, terminating
79965.81/11216.83	% SZS status Ended for HL404548+4.p
79972.55/11217.67	% SZS status Started for HL404552+5.p
79972.55/11217.67	% SZS status Theorem for HL404552+5.p
79972.55/11217.67	% SZS status Ended for HL404552+5.p
80003.91/11221.63	% SZS status Started for HL404549+4.p
80003.91/11221.63	% SZS status GaveUp for HL404549+4.p
80003.91/11221.63	eprover: CPU time limit exceeded, terminating
80003.91/11221.63	% SZS status Ended for HL404549+4.p
80017.41/11223.37	% SZS status Started for HL404553+5.p
80017.41/11223.37	% SZS status GaveUp for HL404553+5.p
80017.41/11223.37	% SZS status Ended for HL404553+5.p
80044.45/11226.81	% SZS status Started for HL404554+5.p
80044.45/11226.81	% SZS status GaveUp for HL404554+5.p
80044.45/11226.81	% SZS status Ended for HL404554+5.p
80044.45/11226.85	% SZS status Started for HL404550+4.p
80044.45/11226.85	% SZS status GaveUp for HL404550+4.p
80044.45/11226.85	eprover: CPU time limit exceeded, terminating
80044.45/11226.85	% SZS status Ended for HL404550+4.p
80073.03/11230.35	% SZS status Started for HL404551+4.p
80073.03/11230.35	% SZS status GaveUp for HL404551+4.p
80073.03/11230.35	eprover: CPU time limit exceeded, terminating
80073.03/11230.35	% SZS status Ended for HL404551+4.p
80092.74/11232.89	% SZS status Started for HL404555+5.p
80092.74/11232.89	% SZS status GaveUp for HL404555+5.p
80092.74/11232.89	% SZS status Ended for HL404555+5.p
80102.42/11234.04	% SZS status Started for HL404552+4.p
80102.42/11234.04	% SZS status GaveUp for HL404552+4.p
80102.42/11234.04	eprover: CPU time limit exceeded, terminating
80102.42/11234.04	% SZS status Ended for HL404552+4.p
80117.33/11235.97	% SZS status Started for HL404557+5.p
80117.33/11235.97	% SZS status GaveUp for HL404557+5.p
80117.33/11235.97	% SZS status Ended for HL404557+5.p
80140.39/11238.88	% SZS status Started for HL404553+4.p
80140.39/11238.88	% SZS status GaveUp for HL404553+4.p
80140.39/11238.88	eprover: CPU time limit exceeded, terminating
80140.39/11238.88	% SZS status Ended for HL404553+4.p
80167.34/11242.26	% SZS status Started for HL404558+5.p
80167.34/11242.26	% SZS status GaveUp for HL404558+5.p
80167.34/11242.26	% SZS status Ended for HL404558+5.p
80168.77/11242.50	% SZS status Started for HL404554+4.p
80168.77/11242.50	% SZS status GaveUp for HL404554+4.p
80168.77/11242.50	eprover: CPU time limit exceeded, terminating
80168.77/11242.50	% SZS status Ended for HL404554+4.p
80190.61/11245.21	% SZS status Started for HL404559+5.p
80190.61/11245.21	% SZS status GaveUp for HL404559+5.p
80190.61/11245.21	% SZS status Ended for HL404559+5.p
80207.63/11247.39	% SZS status Started for HL404555+4.p
80207.63/11247.39	% SZS status GaveUp for HL404555+4.p
80207.63/11247.39	eprover: CPU time limit exceeded, terminating
80207.63/11247.39	% SZS status Ended for HL404555+4.p
80242.06/11251.70	% SZS status Started for HL404560+5.p
80242.06/11251.70	% SZS status GaveUp for HL404560+5.p
80242.06/11251.70	% SZS status Ended for HL404560+5.p
80248.16/11252.46	% SZS status Started for HL404557+4.p
80248.16/11252.46	% SZS status GaveUp for HL404557+4.p
80248.16/11252.46	eprover: CPU time limit exceeded, terminating
80248.16/11252.46	% SZS status Ended for HL404557+4.p
80263.52/11254.34	% SZS status Started for HL404562+5.p
80263.52/11254.34	% SZS status GaveUp for HL404562+5.p
80263.52/11254.34	% SZS status Ended for HL404562+5.p
80274.98/11255.90	% SZS status Started for HL404565+5.p
80274.98/11255.90	% SZS status Theorem for HL404565+5.p
80274.98/11255.90	% SZS status Ended for HL404565+5.p
80278.84/11256.26	% SZS status Started for HL404558+4.p
80278.84/11256.26	% SZS status GaveUp for HL404558+4.p
80278.84/11256.26	eprover: CPU time limit exceeded, terminating
80278.84/11256.26	% SZS status Ended for HL404558+4.p
80293.30/11258.16	% SZS status Started for HL404566+5.p
80293.30/11258.16	% SZS status Theorem for HL404566+5.p
80293.30/11258.16	% SZS status Ended for HL404566+5.p
80307.87/11259.91	% SZS status Started for HL404559+4.p
80307.87/11259.91	% SZS status GaveUp for HL404559+4.p
80307.87/11259.91	eprover: CPU time limit exceeded, terminating
80307.87/11259.91	% SZS status Ended for HL404559+4.p
80315.86/11260.94	% SZS status Started for HL404563+5.p
80315.86/11260.94	% SZS status GaveUp for HL404563+5.p
80315.86/11260.94	% SZS status Ended for HL404563+5.p
80345.27/11264.65	% SZS status Started for HL404560+4.p
80345.27/11264.65	% SZS status GaveUp for HL404560+4.p
80345.27/11264.65	eprover: CPU time limit exceeded, terminating
80345.27/11264.65	% SZS status Ended for HL404560+4.p
80375.78/11268.50	% SZS status Started for HL404562+4.p
80375.78/11268.50	% SZS status GaveUp for HL404562+4.p
80375.78/11268.50	eprover: CPU time limit exceeded, terminating
80375.78/11268.50	% SZS status Ended for HL404562+4.p
80381.05/11269.30	% SZS status Started for HL404567+5.p
80381.05/11269.30	% SZS status GaveUp for HL404567+5.p
80381.05/11269.30	% SZS status Ended for HL404567+5.p
80397.38/11271.20	% SZS status Started for HL404569+5.p
80397.38/11271.20	% SZS status Theorem for HL404569+5.p
80397.38/11271.20	% SZS status Ended for HL404569+5.p
80412.66/11273.16	% SZS status Started for HL404563+4.p
80412.66/11273.16	% SZS status GaveUp for HL404563+4.p
80412.66/11273.16	eprover: CPU time limit exceeded, terminating
80412.66/11273.16	% SZS status Ended for HL404563+4.p
80419.87/11274.01	% SZS status Started for HL404568+5.p
80419.87/11274.01	% SZS status GaveUp for HL404568+5.p
80419.87/11274.01	% SZS status Ended for HL404568+5.p
80428.02/11275.06	% SZS status Started for HL404570+5.p
80428.02/11275.06	% SZS status Theorem for HL404570+5.p
80428.02/11275.06	% SZS status Ended for HL404570+5.p
80442.89/11276.93	% SZS status Started for HL404572+5.p
80442.89/11276.93	% SZS status Theorem for HL404572+5.p
80442.89/11276.93	% SZS status Ended for HL404572+5.p
80451.66/11278.01	% SZS status Started for HL404565+4.p
80451.66/11278.01	% SZS status GaveUp for HL404565+4.p
80451.66/11278.01	eprover: CPU time limit exceeded, terminating
80451.66/11278.01	% SZS status Ended for HL404565+4.p
80479.76/11281.64	% SZS status Started for HL404566+4.p
80479.76/11281.64	% SZS status GaveUp for HL404566+4.p
80479.76/11281.64	eprover: CPU time limit exceeded, terminating
80479.76/11281.64	% SZS status Ended for HL404566+4.p
80501.37/11284.35	% SZS status Started for HL404567+4.p
80501.37/11284.35	% SZS status GaveUp for HL404567+4.p
80501.37/11284.35	eprover: CPU time limit exceeded, terminating
80501.37/11284.35	% SZS status Ended for HL404567+4.p
80523.10/11287.21	% SZS status Started for HL404568+4.p
80523.10/11287.21	% SZS status GaveUp for HL404568+4.p
80523.10/11287.21	eprover: CPU time limit exceeded, terminating
80523.10/11287.21	% SZS status Ended for HL404568+4.p
80524.23/11287.30	% SZS status Started for HL404573+5.p
80524.23/11287.30	% SZS status GaveUp for HL404573+5.p
80524.23/11287.30	% SZS status Ended for HL404573+5.p
80579.95/11294.57	% SZS status Started for HL404569+4.p
80579.95/11294.57	% SZS status GaveUp for HL404569+4.p
80579.95/11294.57	eprover: CPU time limit exceeded, terminating
80579.95/11294.57	% SZS status Ended for HL404569+4.p
80585.81/11295.34	% SZS status Started for HL404574+5.p
80585.81/11295.34	% SZS status GaveUp for HL404574+5.p
80585.81/11295.34	% SZS status Ended for HL404574+5.p
80598.83/11297.14	% SZS status Started for HL404575+5.p
80598.83/11297.14	% SZS status GaveUp for HL404575+5.p
80598.83/11297.14	% SZS status Ended for HL404575+5.p
80604.72/11297.72	% SZS status Started for HL404570+4.p
80604.72/11297.72	% SZS status GaveUp for HL404570+4.p
80604.72/11297.72	eprover: CPU time limit exceeded, terminating
80604.72/11297.72	% SZS status Ended for HL404570+4.p
80604.72/11297.75	% SZS status Started for HL404575+4.p
80604.72/11297.75	% SZS status GaveUp for HL404575+4.p
80604.72/11297.75	eprover: CPU time limit exceeded, terminating
80604.72/11297.75	% SZS status Ended for HL404575+4.p
80620.62/11299.84	% SZS status Started for HL404572+4.p
80620.62/11299.84	% SZS status GaveUp for HL404572+4.p
80620.62/11299.84	eprover: CPU time limit exceeded, terminating
80620.62/11299.84	% SZS status Ended for HL404572+4.p
80646.53/11303.39	% SZS status Started for HL404573+4.p
80646.53/11303.39	% SZS status GaveUp for HL404573+4.p
80646.53/11303.39	eprover: CPU time limit exceeded, terminating
80646.53/11303.39	% SZS status Ended for HL404573+4.p
80652.20/11304.24	% SZS status Started for HL404577+5.p
80652.20/11304.24	% SZS status Theorem for HL404577+5.p
80652.20/11304.24	% SZS status Ended for HL404577+5.p
80658.77/11305.09	% SZS status Started for HL404578+5.p
80658.77/11305.09	% SZS status Theorem for HL404578+5.p
80658.77/11305.09	% SZS status Ended for HL404578+5.p
80661.85/11305.48	% SZS status Started for HL404576+5.p
80661.85/11305.48	% SZS status GaveUp for HL404576+5.p
80661.85/11305.48	% SZS status Ended for HL404576+5.p
80680.89/11308.04	% SZS status Started for HL404574+4.p
80680.89/11308.04	% SZS status GaveUp for HL404574+4.p
80680.89/11308.04	eprover: CPU time limit exceeded, terminating
80680.89/11308.04	% SZS status Ended for HL404574+4.p
80683.20/11308.40	% SZS status Started for HL404577+4.p
80683.20/11308.40	% SZS status GaveUp for HL404577+4.p
80683.20/11308.40	eprover: CPU time limit exceeded, terminating
80683.20/11308.40	% SZS status Ended for HL404577+4.p
80687.23/11308.90	% SZS status Started for HL404578+4.p
80687.23/11308.90	% SZS status GaveUp for HL404578+4.p
80687.23/11308.90	eprover: CPU time limit exceeded, terminating
80687.23/11308.90	% SZS status Ended for HL404578+4.p
80727.19/11314.18	% SZS status Started for HL404579+4.p
80727.19/11314.18	% SZS status GaveUp for HL404579+4.p
80727.19/11314.18	eprover: CPU time limit exceeded, terminating
80727.19/11314.18	% SZS status Ended for HL404579+4.p
80731.30/11314.72	% SZS status Started for HL404579+5.p
80731.30/11314.72	% SZS status GaveUp for HL404579+5.p
80731.30/11314.72	% SZS status Ended for HL404579+5.p
80738.44/11315.58	% SZS status Started for HL404581+5.p
80738.44/11315.58	% SZS status Theorem for HL404581+5.p
80738.44/11315.58	% SZS status Ended for HL404581+5.p
80738.44/11315.61	% SZS status Started for HL404580+4.p
80738.44/11315.61	% SZS status GaveUp for HL404580+4.p
80738.44/11315.61	eprover: CPU time limit exceeded, terminating
80738.44/11315.61	% SZS status Ended for HL404580+4.p
80739.34/11315.74	% SZS status Started for HL404580+5.p
80739.34/11315.74	% SZS status GaveUp for HL404580+5.p
80739.34/11315.74	% SZS status Ended for HL404580+5.p
80768.54/11319.53	% SZS status Started for HL404582+4.p
80768.54/11319.53	% SZS status GaveUp for HL404582+4.p
80768.54/11319.53	eprover: CPU time limit exceeded, terminating
80768.54/11319.53	% SZS status Ended for HL404582+4.p
80783.23/11321.39	% SZS status Started for HL404582+5.p
80783.23/11321.39	% SZS status Theorem for HL404582+5.p
80783.23/11321.39	% SZS status Ended for HL404582+5.p
80789.85/11322.26	% SZS status Started for HL404576+4.p
80789.85/11322.26	% SZS status GaveUp for HL404576+4.p
80789.85/11322.26	eprover: CPU time limit exceeded, terminating
80789.85/11322.26	% SZS status Ended for HL404576+4.p
80810.99/11325.12	% SZS status Started for HL404583+4.p
80810.99/11325.12	% SZS status GaveUp for HL404583+4.p
80810.99/11325.12	eprover: CPU time limit exceeded, terminating
80810.99/11325.12	% SZS status Ended for HL404583+4.p
80814.39/11325.60	% SZS status Started for HL404583+5.p
80814.39/11325.60	% SZS status GaveUp for HL404583+5.p
80814.39/11325.60	% SZS status Ended for HL404583+5.p
80819.40/11326.13	% SZS status Started for HL404584+5.p
80819.40/11326.13	% SZS status GaveUp for HL404584+5.p
80819.40/11326.13	% SZS status Ended for HL404584+5.p
80819.59/11326.20	% SZS status Started for HL404584+4.p
80819.59/11326.20	% SZS status GaveUp for HL404584+4.p
80819.59/11326.20	eprover: CPU time limit exceeded, terminating
80819.59/11326.20	% SZS status Ended for HL404584+4.p
80836.18/11328.51	% SZS status Started for HL404585+5.p
80836.18/11328.51	% SZS status Theorem for HL404585+5.p
80836.18/11328.51	% SZS status Ended for HL404585+5.p
80851.33/11330.37	% SZS status Started for HL404585+4.p
80851.33/11330.37	% SZS status GaveUp for HL404585+4.p
80851.33/11330.37	eprover: CPU time limit exceeded, terminating
80851.33/11330.37	% SZS status Ended for HL404585+4.p
80873.13/11333.46	% SZS status Started for HL404586+4.p
80873.13/11333.46	% SZS status GaveUp for HL404586+4.p
80873.13/11333.46	eprover: CPU time limit exceeded, terminating
80873.13/11333.46	% SZS status Ended for HL404586+4.p
80883.23/11335.04	% SZS status Started for HL404581+4.p
80883.23/11335.04	% SZS status GaveUp for HL404581+4.p
80883.23/11335.04	eprover: CPU time limit exceeded, terminating
80883.23/11335.04	% SZS status Ended for HL404581+4.p
80887.82/11335.67	% SZS status Started for HL404586+5.p
80887.82/11335.67	% SZS status GaveUp for HL404586+5.p
80887.82/11335.67	% SZS status Ended for HL404586+5.p
80898.33/11337.08	% SZS status Started for HL404587+5.p
80898.33/11337.08	% SZS status GaveUp for HL404587+5.p
80898.33/11337.08	% SZS status Ended for HL404587+5.p
80898.33/11337.11	% SZS status Started for HL404587+4.p
80898.33/11337.11	% SZS status GaveUp for HL404587+4.p
80898.33/11337.11	eprover: CPU time limit exceeded, terminating
80898.33/11337.11	% SZS status Ended for HL404587+4.p
80901.46/11337.43	% SZS status Started for HL404588+4.p
80901.46/11337.43	% SZS status GaveUp for HL404588+4.p
80901.46/11337.43	eprover: CPU time limit exceeded, terminating
80901.46/11337.43	% SZS status Ended for HL404588+4.p
80908.96/11338.51	% SZS status Started for HL404588+5.p
80908.96/11338.51	% SZS status GaveUp for HL404588+5.p
80908.96/11338.51	% SZS status Ended for HL404588+5.p
80946.66/11343.39	% SZS status Started for HL404589+5.p
80946.66/11343.39	% SZS status GaveUp for HL404589+5.p
80946.66/11343.39	% SZS status Ended for HL404589+5.p
80968.64/11346.28	% SZS status Started for HL404590+5.p
80968.64/11346.28	% SZS status GaveUp for HL404590+5.p
80968.64/11346.28	% SZS status Ended for HL404590+5.p
80978.91/11347.78	% SZS status Started for HL404592+5.p
80978.91/11347.78	% SZS status GaveUp for HL404592+5.p
80978.91/11347.78	% SZS status Ended for HL404592+5.p
80983.74/11348.40	% SZS status Started for HL404593+5.p
80983.74/11348.40	% SZS status GaveUp for HL404593+5.p
80983.74/11348.40	% SZS status Ended for HL404593+5.p
81018.27/11352.90	% SZS status Started for HL404594+5.p
81018.27/11352.90	% SZS status Theorem for HL404594+5.p
81018.27/11352.90	% SZS status Ended for HL404594+5.p
81062.54/11358.57	% SZS status Started for HL404589+4.p
81062.54/11358.57	% SZS status GaveUp for HL404589+4.p
81062.54/11358.57	eprover: CPU time limit exceeded, terminating
81062.54/11358.57	% SZS status Ended for HL404589+4.p
81066.33/11359.08	% SZS status Started for HL404595+5.p
81066.33/11359.08	% SZS status GaveUp for HL404595+5.p
81066.33/11359.08	% SZS status Ended for HL404595+5.p
81089.54/11362.05	% SZS status Started for HL404590+4.p
81089.54/11362.05	% SZS status GaveUp for HL404590+4.p
81089.54/11362.05	eprover: CPU time limit exceeded, terminating
81089.54/11362.05	% SZS status Ended for HL404590+4.p
81103.41/11363.77	% SZS status Started for HL404592+4.p
81103.41/11363.77	% SZS status GaveUp for HL404592+4.p
81103.41/11363.77	eprover: CPU time limit exceeded, terminating
81103.41/11363.77	% SZS status Ended for HL404592+4.p
81109.17/11364.65	% SZS status Started for HL404593+4.p
81109.17/11364.65	% SZS status GaveUp for HL404593+4.p
81109.17/11364.65	eprover: CPU time limit exceeded, terminating
81109.17/11364.65	% SZS status Ended for HL404593+4.p
81120.61/11365.98	% SZS status Started for HL404596+5.p
81120.61/11365.98	% SZS status Theorem for HL404596+5.p
81120.61/11365.98	% SZS status Ended for HL404596+5.p
81154.88/11370.41	% SZS status Started for HL404594+4.p
81154.88/11370.41	% SZS status GaveUp for HL404594+4.p
81154.88/11370.41	eprover: CPU time limit exceeded, terminating
81154.88/11370.41	% SZS status Ended for HL404594+4.p
81161.18/11371.30	% SZS status Started for HL404599+5.p
81161.18/11371.30	% SZS status Theorem for HL404599+5.p
81161.18/11371.30	% SZS status Ended for HL404599+5.p
81168.44/11372.13	% SZS status Started for HL404597+5.p
81168.44/11372.13	% SZS status GaveUp for HL404597+5.p
81168.44/11372.13	% SZS status Ended for HL404597+5.p
81184.76/11374.21	% SZS status Started for HL404595+4.p
81184.76/11374.21	% SZS status GaveUp for HL404595+4.p
81184.76/11374.21	eprover: CPU time limit exceeded, terminating
81184.76/11374.21	% SZS status Ended for HL404595+4.p
81226.76/11379.49	% SZS status Started for HL404596+4.p
81226.76/11379.49	% SZS status GaveUp for HL404596+4.p
81226.76/11379.49	eprover: CPU time limit exceeded, terminating
81226.76/11379.49	% SZS status Ended for HL404596+4.p
81228.34/11379.70	% SZS status Started for HL404600+5.p
81228.34/11379.70	% SZS status GaveUp for HL404600+5.p
81228.34/11379.70	% SZS status Ended for HL404600+5.p
81243.30/11381.55	% SZS status Started for HL404602+5.p
81243.30/11381.55	% SZS status GaveUp for HL404602+5.p
81243.30/11381.55	% SZS status Ended for HL404602+5.p
81272.34/11385.16	% SZS status Started for HL404597+4.p
81272.34/11385.16	% SZS status GaveUp for HL404597+4.p
81272.34/11385.16	eprover: CPU time limit exceeded, terminating
81272.34/11385.16	% SZS status Ended for HL404597+4.p
81302.52/11388.96	% SZS status Started for HL404603+5.p
81302.52/11388.96	% SZS status GaveUp for HL404603+5.p
81302.52/11388.96	% SZS status Ended for HL404603+5.p
81307.47/11389.64	% SZS status Started for HL404599+4.p
81307.47/11389.64	% SZS status GaveUp for HL404599+4.p
81307.47/11389.64	eprover: CPU time limit exceeded, terminating
81307.47/11389.64	% SZS status Ended for HL404599+4.p
81317.25/11390.91	% SZS status Started for HL404604+5.p
81317.25/11390.91	% SZS status GaveUp for HL404604+5.p
81317.25/11390.91	% SZS status Ended for HL404604+5.p
81325.95/11392.06	% SZS status Started for HL404600+4.p
81325.95/11392.06	% SZS status GaveUp for HL404600+4.p
81325.95/11392.06	eprover: CPU time limit exceeded, terminating
81325.95/11392.06	% SZS status Ended for HL404600+4.p
81364.73/11397.38	% SZS status Started for HL404602+4.p
81364.73/11397.38	% SZS status GaveUp for HL404602+4.p
81364.73/11397.38	eprover: CPU time limit exceeded, terminating
81364.73/11397.38	% SZS status Ended for HL404602+4.p
81367.84/11397.69	% SZS status Started for HL404606+5.p
81367.84/11397.69	% SZS status Theorem for HL404606+5.p
81367.84/11397.69	% SZS status Ended for HL404606+5.p
81382.29/11399.61	% SZS status Started for HL404605+5.p
81382.29/11399.61	% SZS status GaveUp for HL404605+5.p
81382.29/11399.61	% SZS status Ended for HL404605+5.p
81388.76/11400.54	% SZS status Started for HL404603+4.p
81388.76/11400.54	% SZS status GaveUp for HL404603+4.p
81388.76/11400.54	eprover: CPU time limit exceeded, terminating
81388.76/11400.54	% SZS status Ended for HL404603+4.p
81419.20/11404.92	% SZS status Started for HL404607+5.p
81419.20/11404.92	% SZS status Theorem for HL404607+5.p
81419.20/11404.92	% SZS status Ended for HL404607+5.p
81429.10/11406.26	% SZS status Started for HL404604+4.p
81429.10/11406.26	% SZS status GaveUp for HL404604+4.p
81429.10/11406.26	eprover: CPU time limit exceeded, terminating
81429.10/11406.26	% SZS status Ended for HL404604+4.p
81438.33/11407.60	% SZS status Started for HL404608+5.p
81438.33/11407.60	% SZS status Theorem for HL404608+5.p
81438.33/11407.60	% SZS status Ended for HL404608+5.p
81488.70/11413.34	% SZS status Started for HL404609+5.p
81488.70/11413.34	% SZS status Theorem for HL404609+5.p
81488.70/11413.34	% SZS status Ended for HL404609+5.p
81490.91/11413.61	% SZS status Started for HL404605+4.p
81490.91/11413.61	% SZS status GaveUp for HL404605+4.p
81490.91/11413.61	eprover: CPU time limit exceeded, terminating
81490.91/11413.61	% SZS status Ended for HL404605+4.p
81513.66/11416.72	% SZS status Started for HL404606+4.p
81513.66/11416.72	% SZS status GaveUp for HL404606+4.p
81513.66/11416.72	eprover: CPU time limit exceeded, terminating
81513.66/11416.72	% SZS status Ended for HL404606+4.p
81522.32/11417.97	% SZS status Started for HL404610+5.p
81522.32/11417.97	% SZS status GaveUp for HL404610+5.p
81522.32/11417.97	% SZS status Ended for HL404610+5.p
81538.04/11420.25	% SZS status Started for HL404607+4.p
81538.04/11420.25	% SZS status GaveUp for HL404607+4.p
81538.04/11420.25	eprover: CPU time limit exceeded, terminating
81538.04/11420.25	% SZS status Ended for HL404607+4.p
81567.89/11424.16	% SZS status Started for HL404611+5.p
81567.89/11424.16	% SZS status GaveUp for HL404611+5.p
81567.89/11424.16	% SZS status Ended for HL404611+5.p
81575.70/11425.16	% SZS status Started for HL404608+4.p
81575.70/11425.16	% SZS status GaveUp for HL404608+4.p
81575.70/11425.16	eprover: CPU time limit exceeded, terminating
81575.70/11425.16	% SZS status Ended for HL404608+4.p
81595.01/11427.67	% SZS status Started for HL404609+4.p
81595.01/11427.67	% SZS status GaveUp for HL404609+4.p
81595.01/11427.67	eprover: CPU time limit exceeded, terminating
81595.01/11427.67	% SZS status Ended for HL404609+4.p
81605.31/11429.04	% SZS status Started for HL404612+5.p
81605.31/11429.04	% SZS status GaveUp for HL404612+5.p
81605.31/11429.04	% SZS status Ended for HL404612+5.p
81647.43/11434.44	% SZS status Started for HL404613+5.p
81647.43/11434.44	% SZS status GaveUp for HL404613+5.p
81647.43/11434.44	% SZS status Ended for HL404613+5.p
81648.73/11434.63	% SZS status Started for HL404610+4.p
81648.73/11434.63	% SZS status GaveUp for HL404610+4.p
81648.73/11434.63	eprover: CPU time limit exceeded, terminating
81648.73/11434.63	% SZS status Ended for HL404610+4.p
81671.70/11437.68	% SZS status Started for HL404614+5.p
81671.70/11437.68	% SZS status GaveUp for HL404614+5.p
81671.70/11437.68	% SZS status Ended for HL404614+5.p
81689.52/11439.98	% SZS status Started for HL404611+4.p
81689.52/11439.98	% SZS status GaveUp for HL404611+4.p
81689.52/11439.98	eprover: CPU time limit exceeded, terminating
81689.52/11439.98	% SZS status Ended for HL404611+4.p
81718.91/11443.70	% SZS status Started for HL404612+4.p
81718.91/11443.70	% SZS status GaveUp for HL404612+4.p
81718.91/11443.70	eprover: CPU time limit exceeded, terminating
81718.91/11443.70	% SZS status Ended for HL404612+4.p
81724.35/11444.44	% SZS status Started for HL404615+5.p
81724.35/11444.44	% SZS status GaveUp for HL404615+5.p
81724.35/11444.44	% SZS status Ended for HL404615+5.p
81746.60/11447.24	% SZS status Started for HL404616+5.p
81746.60/11447.24	% SZS status GaveUp for HL404616+5.p
81746.60/11447.24	% SZS status Ended for HL404616+5.p
81746.82/11447.33	% SZS status Started for HL404613+4.p
81746.82/11447.33	% SZS status GaveUp for HL404613+4.p
81746.82/11447.33	eprover: CPU time limit exceeded, terminating
81746.82/11447.33	% SZS status Ended for HL404613+4.p
81772.50/11450.47	% SZS status Started for HL404618+4.p
81772.50/11450.47	% SZS status GaveUp for HL404618+4.p
81772.50/11450.47	eprover: CPU time limit exceeded, terminating
81772.50/11450.47	% SZS status Ended for HL404618+4.p
81779.95/11451.44	% SZS status Started for HL404614+4.p
81779.95/11451.44	% SZS status GaveUp for HL404614+4.p
81779.95/11451.44	eprover: CPU time limit exceeded, terminating
81779.95/11451.44	% SZS status Ended for HL404614+4.p
81792.91/11453.09	% SZS status Started for HL404618+5.p
81792.91/11453.09	% SZS status GaveUp for HL404618+5.p
81792.91/11453.09	% SZS status Ended for HL404618+5.p
81814.18/11455.76	% SZS status Started for HL404615+4.p
81814.18/11455.76	% SZS status GaveUp for HL404615+4.p
81814.18/11455.76	eprover: CPU time limit exceeded, terminating
81814.18/11455.76	% SZS status Ended for HL404615+4.p
81822.64/11456.86	% SZS status Started for HL404619+5.p
81822.64/11456.86	% SZS status GaveUp for HL404619+5.p
81822.64/11456.86	% SZS status Ended for HL404619+5.p
81848.30/11460.11	% SZS status Started for HL404620+5.p
81848.30/11460.11	% SZS status GaveUp for HL404620+5.p
81848.30/11460.11	% SZS status Ended for HL404620+5.p
81856.75/11461.17	% SZS status Started for HL404616+4.p
81856.75/11461.17	% SZS status GaveUp for HL404616+4.p
81856.75/11461.17	eprover: CPU time limit exceeded, terminating
81856.75/11461.17	% SZS status Ended for HL404616+4.p
81867.93/11462.60	% SZS status Started for HL404621+5.p
81867.93/11462.60	% SZS status GaveUp for HL404621+5.p
81867.93/11462.60	% SZS status Ended for HL404621+5.p
81896.63/11466.18	% SZS status Started for HL404622+5.p
81896.63/11466.18	% SZS status GaveUp for HL404622+5.p
81896.63/11466.18	% SZS status Ended for HL404622+5.p
81928.20/11470.17	% SZS status Started for HL404619+4.p
81928.20/11470.17	% SZS status GaveUp for HL404619+4.p
81928.20/11470.17	eprover: CPU time limit exceeded, terminating
81928.20/11470.17	% SZS status Ended for HL404619+4.p
81929.09/11470.27	% SZS status Started for HL404623+5.p
81929.09/11470.27	% SZS status GaveUp for HL404623+5.p
81929.09/11470.27	% SZS status Ended for HL404623+5.p
81952.02/11473.24	% SZS status Started for HL404620+4.p
81952.02/11473.24	% SZS status GaveUp for HL404620+4.p
81952.02/11473.24	eprover: CPU time limit exceeded, terminating
81952.02/11473.24	% SZS status Ended for HL404620+4.p
81972.13/11475.71	% SZS status Started for HL404624+5.p
81972.13/11475.71	% SZS status GaveUp for HL404624+5.p
81972.13/11475.71	% SZS status Ended for HL404624+5.p
81986.67/11477.55	% SZS status Started for HL404621+4.p
81986.67/11477.55	% SZS status GaveUp for HL404621+4.p
81986.67/11477.55	eprover: CPU time limit exceeded, terminating
81986.67/11477.55	% SZS status Ended for HL404621+4.p
82003.02/11479.63	% SZS status Started for HL404625+5.p
82003.02/11479.63	% SZS status GaveUp for HL404625+5.p
82003.02/11479.63	% SZS status Ended for HL404625+5.p
82021.33/11481.94	% SZS status Started for HL404622+4.p
82021.33/11481.94	% SZS status GaveUp for HL404622+4.p
82021.33/11481.94	eprover: CPU time limit exceeded, terminating
82021.33/11481.94	% SZS status Ended for HL404622+4.p
82047.19/11485.18	% SZS status Started for HL404626+5.p
82047.19/11485.18	% SZS status GaveUp for HL404626+5.p
82047.19/11485.18	% SZS status Ended for HL404626+5.p
82052.39/11485.81	% SZS status Started for HL404623+4.p
82052.39/11485.81	% SZS status GaveUp for HL404623+4.p
82052.39/11485.81	eprover: CPU time limit exceeded, terminating
82052.39/11485.81	% SZS status Ended for HL404623+4.p
82074.54/11488.69	% SZS status Started for HL404624+4.p
82074.54/11488.69	% SZS status GaveUp for HL404624+4.p
82074.54/11488.69	eprover: CPU time limit exceeded, terminating
82074.54/11488.69	% SZS status Ended for HL404624+4.p
82077.77/11489.01	% SZS status Started for HL404627+5.p
82077.77/11489.01	% SZS status GaveUp for HL404627+5.p
82077.77/11489.01	% SZS status Ended for HL404627+5.p
82131.83/11494.71	% SZS status Started for HL404628+5.p
82131.83/11494.71	% SZS status GaveUp for HL404628+5.p
82131.83/11494.71	% SZS status Ended for HL404628+5.p
82144.09/11496.24	% SZS status Started for HL404625+4.p
82144.09/11496.24	% SZS status GaveUp for HL404625+4.p
82144.09/11496.24	eprover: CPU time limit exceeded, terminating
82144.09/11496.24	% SZS status Ended for HL404625+4.p
82158.29/11498.06	% SZS status Started for HL404629+5.p
82158.29/11498.06	% SZS status GaveUp for HL404629+5.p
82158.29/11498.06	% SZS status Ended for HL404629+5.p
82166.95/11499.16	% SZS status Started for HL404626+4.p
82166.95/11499.16	% SZS status GaveUp for HL404626+4.p
82166.95/11499.16	eprover: CPU time limit exceeded, terminating
82166.95/11499.16	% SZS status Ended for HL404626+4.p
82202.13/11503.51	% SZS status Started for HL404627+4.p
82202.13/11503.51	% SZS status GaveUp for HL404627+4.p
82202.13/11503.51	eprover: CPU time limit exceeded, terminating
82202.13/11503.51	% SZS status Ended for HL404627+4.p
82206.28/11504.04	% SZS status Started for HL404630+5.p
82206.28/11504.04	% SZS status GaveUp for HL404630+5.p
82206.28/11504.04	% SZS status Ended for HL404630+5.p
82210.71/11504.59	% SZS status Started for HL404631+5.p
82210.71/11504.59	% SZS status Theorem for HL404631+5.p
82210.71/11504.59	% SZS status Ended for HL404631+5.p
82235.77/11507.79	% SZS status Started for HL404628+4.p
82235.77/11507.79	% SZS status GaveUp for HL404628+4.p
82235.77/11507.79	eprover: CPU time limit exceeded, terminating
82235.77/11507.79	% SZS status Ended for HL404628+4.p
82265.93/11511.56	% SZS status Started for HL404629+4.p
82265.93/11511.56	% SZS status GaveUp for HL404629+4.p
82265.93/11511.56	eprover: CPU time limit exceeded, terminating
82265.93/11511.56	% SZS status Ended for HL404629+4.p
82275.78/11512.83	% SZS status Started for HL404632+5.p
82275.78/11512.83	% SZS status GaveUp for HL404632+5.p
82275.78/11512.83	% SZS status Ended for HL404632+5.p
82286.27/11514.08	% SZS status Started for HL404635+5.p
82286.27/11514.08	% SZS status GaveUp for HL404635+5.p
82286.27/11514.08	% SZS status Ended for HL404635+5.p
82290.35/11514.61	% SZS status Started for HL404630+4.p
82290.35/11514.61	% SZS status GaveUp for HL404630+4.p
82290.35/11514.61	eprover: CPU time limit exceeded, terminating
82290.35/11514.61	% SZS status Ended for HL404630+4.p
82340.53/11520.93	% SZS status Started for HL404636+5.p
82340.53/11520.93	% SZS status GaveUp for HL404636+5.p
82340.53/11520.93	% SZS status Ended for HL404636+5.p
82347.88/11521.89	% SZS status Started for HL404631+4.p
82347.88/11521.89	% SZS status GaveUp for HL404631+4.p
82347.88/11521.89	eprover: CPU time limit exceeded, terminating
82347.88/11521.89	% SZS status Ended for HL404631+4.p
82359.55/11523.34	% SZS status Started for HL404637+5.p
82359.55/11523.34	% SZS status GaveUp for HL404637+5.p
82359.55/11523.34	% SZS status Ended for HL404637+5.p
82371.98/11524.97	% SZS status Started for HL404632+4.p
82371.98/11524.97	% SZS status GaveUp for HL404632+4.p
82371.98/11524.97	eprover: CPU time limit exceeded, terminating
82371.98/11524.97	% SZS status Ended for HL404632+4.p
82409.52/11529.64	% SZS status Started for HL404635+4.p
82409.52/11529.64	% SZS status GaveUp for HL404635+4.p
82409.52/11529.64	eprover: CPU time limit exceeded, terminating
82409.52/11529.64	% SZS status Ended for HL404635+4.p
82415.73/11530.38	% SZS status Started for HL404638+5.p
82415.73/11530.38	% SZS status GaveUp for HL404638+5.p
82415.73/11530.38	% SZS status Ended for HL404638+5.p
82433.59/11532.69	% SZS status Started for HL404639+5.p
82433.59/11532.69	% SZS status GaveUp for HL404639+5.p
82433.59/11532.69	% SZS status Ended for HL404639+5.p
82439.34/11533.45	% SZS status Started for HL404636+4.p
82439.34/11533.45	% SZS status GaveUp for HL404636+4.p
82439.34/11533.45	eprover: CPU time limit exceeded, terminating
82439.34/11533.45	% SZS status Ended for HL404636+4.p
82482.91/11538.85	% SZS status Started for HL404637+4.p
82482.91/11538.85	% SZS status GaveUp for HL404637+4.p
82482.91/11538.85	eprover: CPU time limit exceeded, terminating
82482.91/11538.85	% SZS status Ended for HL404637+4.p
82483.69/11539.00	% SZS status Started for HL404640+5.p
82483.69/11539.00	% SZS status GaveUp for HL404640+5.p
82483.69/11539.00	% SZS status Ended for HL404640+5.p
82493.90/11540.28	% SZS status Started for HL404638+4.p
82493.90/11540.28	% SZS status GaveUp for HL404638+4.p
82493.90/11540.28	eprover: CPU time limit exceeded, terminating
82493.90/11540.28	% SZS status Ended for HL404638+4.p
82508.14/11542.15	% SZS status Started for HL404641+5.p
82508.14/11542.15	% SZS status GaveUp for HL404641+5.p
82508.14/11542.15	% SZS status Ended for HL404641+5.p
82562.77/11547.88	% SZS status Started for HL404639+4.p
82562.77/11547.88	% SZS status GaveUp for HL404639+4.p
82562.77/11547.88	eprover: CPU time limit exceeded, terminating
82562.77/11547.88	% SZS status Ended for HL404639+4.p
82566.87/11548.37	% SZS status Started for HL404642+5.p
82566.87/11548.37	% SZS status GaveUp for HL404642+5.p
82566.87/11548.37	% SZS status Ended for HL404642+5.p
82576.28/11549.61	% SZS status Started for HL404643+5.p
82576.28/11549.61	% SZS status GaveUp for HL404643+5.p
82576.28/11549.61	% SZS status Ended for HL404643+5.p
82584.21/11550.60	% SZS status Started for HL404640+4.p
82584.21/11550.60	% SZS status GaveUp for HL404640+4.p
82584.21/11550.60	eprover: CPU time limit exceeded, terminating
82584.21/11550.60	% SZS status Ended for HL404640+4.p
82629.53/11556.40	% SZS status Started for HL404641+4.p
82629.53/11556.40	% SZS status GaveUp for HL404641+4.p
82629.53/11556.40	eprover: CPU time limit exceeded, terminating
82629.53/11556.40	% SZS status Ended for HL404641+4.p
82636.80/11557.19	% SZS status Started for HL404644+5.p
82636.80/11557.19	% SZS status GaveUp for HL404644+5.p
82636.80/11557.19	% SZS status Ended for HL404644+5.p
82650.40/11558.95	% SZS status Started for HL404645+5.p
82650.40/11558.95	% SZS status GaveUp for HL404645+5.p
82650.40/11558.95	% SZS status Ended for HL404645+5.p
82651.41/11559.07	% SZS status Started for HL404642+4.p
82651.41/11559.07	% SZS status GaveUp for HL404642+4.p
82651.41/11559.07	eprover: CPU time limit exceeded, terminating
82651.41/11559.07	% SZS status Ended for HL404642+4.p
82697.89/11564.94	% SZS status Started for HL404643+4.p
82697.89/11564.94	% SZS status GaveUp for HL404643+4.p
82697.89/11564.94	eprover: CPU time limit exceeded, terminating
82697.89/11564.94	% SZS status Ended for HL404643+4.p
82706.88/11566.05	% SZS status Started for HL404646+5.p
82706.88/11566.05	% SZS status GaveUp for HL404646+5.p
82706.88/11566.05	% SZS status Ended for HL404646+5.p
82720.35/11567.85	% SZS status Started for HL404644+4.p
82720.35/11567.85	% SZS status GaveUp for HL404644+4.p
82720.35/11567.85	eprover: CPU time limit exceeded, terminating
82720.35/11567.85	% SZS status Ended for HL404644+4.p
82725.68/11568.44	% SZS status Started for HL404647+5.p
82725.68/11568.44	% SZS status GaveUp for HL404647+5.p
82725.68/11568.44	% SZS status Ended for HL404647+5.p
82771.94/11574.22	% SZS status Started for HL404649+5.p
82771.94/11574.22	% SZS status GaveUp for HL404649+5.p
82771.94/11574.22	% SZS status Ended for HL404649+5.p
82772.48/11574.27	% SZS status Started for HL404645+4.p
82772.48/11574.27	% SZS status GaveUp for HL404645+4.p
82772.48/11574.27	eprover: CPU time limit exceeded, terminating
82772.48/11574.27	% SZS status Ended for HL404645+4.p
82793.59/11576.92	% SZS status Started for HL404650+5.p
82793.59/11576.92	% SZS status GaveUp for HL404650+5.p
82793.59/11576.92	% SZS status Ended for HL404650+5.p
82794.02/11576.98	% SZS status Started for HL404646+4.p
82794.02/11576.98	% SZS status GaveUp for HL404646+4.p
82794.02/11576.98	eprover: CPU time limit exceeded, terminating
82794.02/11576.98	% SZS status Ended for HL404646+4.p
82841.74/11583.01	% SZS status Started for HL404647+4.p
82841.74/11583.01	% SZS status GaveUp for HL404647+4.p
82841.74/11583.01	eprover: CPU time limit exceeded, terminating
82841.74/11583.01	% SZS status Ended for HL404647+4.p
82843.39/11583.24	% SZS status Started for HL404651+5.p
82843.39/11583.24	% SZS status GaveUp for HL404651+5.p
82843.39/11583.24	% SZS status Ended for HL404651+5.p
82855.16/11584.69	% SZS status Started for HL404649+4.p
82855.16/11584.69	% SZS status GaveUp for HL404649+4.p
82855.16/11584.69	eprover: CPU time limit exceeded, terminating
82855.16/11584.69	% SZS status Ended for HL404649+4.p
82865.62/11585.95	% SZS status Started for HL404652+5.p
82865.62/11585.95	% SZS status GaveUp for HL404652+5.p
82865.62/11585.95	% SZS status Ended for HL404652+5.p
82888.13/11588.82	% SZS status Started for HL404653+5.p
82888.13/11588.82	% SZS status Theorem for HL404653+5.p
82888.13/11588.82	% SZS status Ended for HL404653+5.p
82911.08/11591.73	% SZS status Started for HL404650+4.p
82911.08/11591.73	% SZS status GaveUp for HL404650+4.p
82911.08/11591.73	eprover: CPU time limit exceeded, terminating
82911.08/11591.73	% SZS status Ended for HL404650+4.p
82928.80/11594.02	% SZS status Started for HL404654+5.p
82928.80/11594.02	% SZS status GaveUp for HL404654+5.p
82928.80/11594.02	% SZS status Ended for HL404654+5.p
82929.81/11594.18	% SZS status Started for HL404651+4.p
82929.81/11594.18	% SZS status GaveUp for HL404651+4.p
82929.81/11594.18	eprover: CPU time limit exceeded, terminating
82929.81/11594.18	% SZS status Ended for HL404651+4.p
82960.59/11597.91	% SZS status Started for HL404655+5.p
82960.59/11597.91	% SZS status GaveUp for HL404655+5.p
82960.59/11597.91	% SZS status Ended for HL404655+5.p
82977.37/11600.05	% SZS status Started for HL404652+4.p
82977.37/11600.05	% SZS status GaveUp for HL404652+4.p
82977.37/11600.05	eprover: CPU time limit exceeded, terminating
82977.37/11600.05	% SZS status Ended for HL404652+4.p
82999.65/11602.84	% SZS status Started for HL404653+4.p
82999.65/11602.84	% SZS status GaveUp for HL404653+4.p
82999.65/11602.84	eprover: CPU time limit exceeded, terminating
82999.65/11602.84	% SZS status Ended for HL404653+4.p
83000.65/11603.07	% SZS status Started for HL404656+5.p
83000.65/11603.07	% SZS status GaveUp for HL404656+5.p
83000.65/11603.07	% SZS status Ended for HL404656+5.p
83033.27/11607.09	% SZS status Started for HL404657+5.p
83033.27/11607.09	% SZS status GaveUp for HL404657+5.p
83033.27/11607.09	% SZS status Ended for HL404657+5.p
83050.10/11609.30	% SZS status Started for HL404654+4.p
83050.10/11609.30	% SZS status GaveUp for HL404654+4.p
83050.10/11609.30	eprover: CPU time limit exceeded, terminating
83050.10/11609.30	% SZS status Ended for HL404654+4.p
83059.64/11610.45	% SZS status Started for HL404659+4.p
83059.64/11610.45	% SZS status GaveUp for HL404659+4.p
83059.64/11610.45	eprover: CPU time limit exceeded, terminating
83059.64/11610.45	% SZS status Ended for HL404659+4.p
83071.91/11612.09	% SZS status Started for HL404655+4.p
83071.91/11612.09	% SZS status GaveUp for HL404655+4.p
83071.91/11612.09	eprover: CPU time limit exceeded, terminating
83071.91/11612.09	% SZS status Ended for HL404655+4.p
83073.91/11612.21	% SZS status Started for HL404659+5.p
83073.91/11612.21	% SZS status GaveUp for HL404659+5.p
83073.91/11612.21	% SZS status Ended for HL404659+5.p
83078.80/11612.84	% SZS status Started for HL404661+5.p
83078.80/11612.84	% SZS status Theorem for HL404661+5.p
83078.80/11612.84	% SZS status Ended for HL404661+5.p
83116.86/11617.67	% SZS status Started for HL404656+4.p
83116.86/11617.67	% SZS status GaveUp for HL404656+4.p
83116.86/11617.67	eprover: CPU time limit exceeded, terminating
83116.86/11617.67	% SZS status Ended for HL404656+4.p
83131.95/11619.55	% SZS status Started for HL404662+5.p
83131.95/11619.55	% SZS status GaveUp for HL404662+5.p
83131.95/11619.55	% SZS status Ended for HL404662+5.p
83135.66/11620.01	% SZS status Started for HL404657+4.p
83135.66/11620.01	% SZS status GaveUp for HL404657+4.p
83135.66/11620.01	eprover: CPU time limit exceeded, terminating
83135.66/11620.01	% SZS status Ended for HL404657+4.p
83145.62/11621.32	% SZS status Started for HL404663+5.p
83145.62/11621.32	% SZS status GaveUp for HL404663+5.p
83145.62/11621.32	% SZS status Ended for HL404663+5.p
83189.68/11626.82	% SZS status Started for HL404664+5.p
83189.68/11626.82	% SZS status GaveUp for HL404664+5.p
83189.68/11626.82	% SZS status Ended for HL404664+5.p
83205.17/11628.75	% SZS status Started for HL404661+4.p
83205.17/11628.75	% SZS status GaveUp for HL404661+4.p
83205.17/11628.75	eprover: CPU time limit exceeded, terminating
83205.17/11628.75	% SZS status Ended for HL404661+4.p
83208.84/11629.24	% SZS status Started for HL404665+5.p
83208.84/11629.24	% SZS status GaveUp for HL404665+5.p
83208.84/11629.24	% SZS status Ended for HL404665+5.p
83256.26/11635.20	% SZS status Started for HL404662+4.p
83256.26/11635.20	% SZS status GaveUp for HL404662+4.p
83256.26/11635.20	eprover: CPU time limit exceeded, terminating
83256.26/11635.20	% SZS status Ended for HL404662+4.p
83262.30/11635.94	% SZS status Started for HL404667+5.p
83262.30/11635.94	% SZS status Theorem for HL404667+5.p
83262.30/11635.94	% SZS status Ended for HL404667+5.p
83263.12/11636.05	% SZS status Started for HL404666+5.p
83263.12/11636.05	% SZS status GaveUp for HL404666+5.p
83263.12/11636.05	% SZS status Ended for HL404666+5.p
83278.20/11637.96	% SZS status Started for HL404663+4.p
83278.20/11637.96	% SZS status GaveUp for HL404663+4.p
83278.20/11637.96	eprover: CPU time limit exceeded, terminating
83278.20/11637.96	% SZS status Ended for HL404663+4.p
83283.12/11638.63	% SZS status Started for HL404664+4.p
83283.12/11638.63	% SZS status GaveUp for HL404664+4.p
83283.12/11638.63	eprover: CPU time limit exceeded, terminating
83283.12/11638.63	% SZS status Ended for HL404664+4.p
83335.61/11645.18	% SZS status Started for HL404668+5.p
83335.61/11645.18	% SZS status GaveUp for HL404668+5.p
83335.61/11645.18	% SZS status Ended for HL404668+5.p
83335.61/11645.21	% SZS status Started for HL404665+4.p
83335.61/11645.21	% SZS status GaveUp for HL404665+4.p
83335.61/11645.21	eprover: CPU time limit exceeded, terminating
83335.61/11645.21	% SZS status Ended for HL404665+4.p
83350.71/11647.08	% SZS status Started for HL404669+5.p
83350.71/11647.08	% SZS status GaveUp for HL404669+5.p
83350.71/11647.08	% SZS status Ended for HL404669+5.p
83350.71/11647.09	% SZS status Started for HL404666+4.p
83350.71/11647.09	% SZS status GaveUp for HL404666+4.p
83350.71/11647.09	eprover: CPU time limit exceeded, terminating
83350.71/11647.09	% SZS status Ended for HL404666+4.p
83407.90/11654.27	% SZS status Started for HL404670+5.p
83407.90/11654.27	% SZS status GaveUp for HL404670+5.p
83407.90/11654.27	% SZS status Ended for HL404670+5.p
83411.90/11654.80	% SZS status Started for HL404667+4.p
83411.90/11654.80	% SZS status GaveUp for HL404667+4.p
83411.90/11654.80	eprover: CPU time limit exceeded, terminating
83411.90/11654.80	% SZS status Ended for HL404667+4.p
83422.14/11656.11	% SZS status Started for HL404671+5.p
83422.14/11656.11	% SZS status GaveUp for HL404671+5.p
83422.14/11656.11	% SZS status Ended for HL404671+5.p
83428.55/11656.85	% SZS status Started for HL404670+4.p
83428.55/11656.85	% SZS status GaveUp for HL404670+4.p
83428.55/11656.85	eprover: CPU time limit exceeded, terminating
83428.55/11656.85	% SZS status Ended for HL404670+4.p
83463.66/11661.33	% SZS status Started for HL404668+4.p
83463.66/11661.33	% SZS status GaveUp for HL404668+4.p
83463.66/11661.33	eprover: CPU time limit exceeded, terminating
83463.66/11661.33	% SZS status Ended for HL404668+4.p
83467.68/11661.75	% SZS status Started for HL404669+4.p
83467.68/11661.75	% SZS status GaveUp for HL404669+4.p
83467.68/11661.75	eprover: CPU time limit exceeded, terminating
83467.68/11661.75	% SZS status Ended for HL404669+4.p
83480.23/11663.39	% SZS status Started for HL404672+5.p
83480.23/11663.39	% SZS status GaveUp for HL404672+5.p
83480.23/11663.39	% SZS status Ended for HL404672+5.p
83495.09/11665.22	% SZS status Started for HL404673+5.p
83495.09/11665.22	% SZS status GaveUp for HL404673+5.p
83495.09/11665.22	% SZS status Ended for HL404673+5.p
83538.36/11670.68	% SZS status Started for HL404674+5.p
83538.36/11670.68	% SZS status GaveUp for HL404674+5.p
83538.36/11670.68	% SZS status Ended for HL404674+5.p
83541.80/11671.23	% SZS status Started for HL404671+4.p
83541.80/11671.23	% SZS status GaveUp for HL404671+4.p
83541.80/11671.23	eprover: CPU time limit exceeded, terminating
83541.80/11671.23	% SZS status Ended for HL404671+4.p
83550.12/11672.89	% SZS status Started for HL404672+4.p
83550.12/11672.89	% SZS status GaveUp for HL404672+4.p
83550.12/11672.89	eprover: CPU time limit exceeded, terminating
83550.12/11672.89	% SZS status Ended for HL404672+4.p
83559.93/11674.98	% SZS status Started for HL404675+5.p
83559.93/11674.98	% SZS status GaveUp for HL404675+5.p
83559.93/11674.98	% SZS status Ended for HL404675+5.p
83609.82/11684.91	% SZS status Started for HL404676+5.p
83609.82/11684.91	% SZS status GaveUp for HL404676+5.p
83609.82/11684.91	% SZS status Ended for HL404676+5.p
83623.48/11687.57	% SZS status Started for HL404673+4.p
83623.48/11687.57	% SZS status GaveUp for HL404673+4.p
83623.48/11687.57	eprover: CPU time limit exceeded, terminating
83623.48/11687.57	% SZS status Ended for HL404673+4.p
83625.02/11687.85	% SZS status Started for HL404678+4.p
83625.02/11687.85	% SZS status GaveUp for HL404678+4.p
83625.02/11687.85	eprover: CPU time limit exceeded, terminating
83625.02/11687.85	% SZS status Ended for HL404678+4.p
83636.23/11690.16	% SZS status Started for HL404674+4.p
83636.23/11690.16	% SZS status GaveUp for HL404674+4.p
83636.23/11690.16	eprover: CPU time limit exceeded, terminating
83636.23/11690.16	% SZS status Ended for HL404674+4.p
83637.97/11690.55	% SZS status Started for HL404680+4.p
83637.97/11690.55	% SZS status GaveUp for HL404680+4.p
83637.97/11690.55	eprover: CPU time limit exceeded, terminating
83637.97/11690.55	% SZS status Ended for HL404680+4.p
83638.66/11690.66	% SZS status Started for HL404678+5.p
83638.66/11690.66	% SZS status GaveUp for HL404678+5.p
83638.66/11690.66	% SZS status Ended for HL404678+5.p
83666.69/11695.45	% SZS status Started for HL404675+4.p
83666.69/11695.45	% SZS status GaveUp for HL404675+4.p
83666.69/11695.45	eprover: CPU time limit exceeded, terminating
83666.69/11695.45	% SZS status Ended for HL404675+4.p
83687.23/11698.43	% SZS status Started for HL404680+5.p
83687.23/11698.43	% SZS status GaveUp for HL404680+5.p
83687.23/11698.43	% SZS status Ended for HL404680+5.p
83694.73/11699.54	% SZS status Started for HL404676+4.p
83694.73/11699.54	% SZS status GaveUp for HL404676+4.p
83694.73/11699.54	eprover: CPU time limit exceeded, terminating
83694.73/11699.54	% SZS status Ended for HL404676+4.p
83704.94/11700.91	% SZS status Started for HL404681+5.p
83704.94/11700.91	% SZS status GaveUp for HL404681+5.p
83704.94/11700.91	% SZS status Ended for HL404681+5.p
83707.38/11701.31	% SZS status Started for HL404681+4.p
83707.38/11701.31	% SZS status GaveUp for HL404681+4.p
83707.38/11701.31	eprover: CPU time limit exceeded, terminating
83707.38/11701.31	% SZS status Ended for HL404681+4.p
83717.89/11702.98	% SZS status Started for HL404685+4.p
83717.89/11702.98	% SZS status GaveUp for HL404685+4.p
83717.89/11702.98	eprover: CPU time limit exceeded, terminating
83717.89/11702.98	% SZS status Ended for HL404685+4.p
83721.88/11703.58	% SZS status Started for HL404684+5.p
83721.88/11703.58	% SZS status GaveUp for HL404684+5.p
83721.88/11703.58	% SZS status Ended for HL404684+5.p
83729.69/11704.87	% SZS status Started for HL404684+4.p
83729.69/11704.87	% SZS status GaveUp for HL404684+4.p
83729.69/11704.87	eprover: CPU time limit exceeded, terminating
83729.69/11704.87	% SZS status Ended for HL404684+4.p
83745.80/11707.11	% SZS status Started for HL404685+5.p
83745.80/11707.11	% SZS status GaveUp for HL404685+5.p
83745.80/11707.11	% SZS status Ended for HL404685+5.p
83765.82/11709.67	% SZS status Started for HL404686+5.p
83765.82/11709.67	% SZS status GaveUp for HL404686+5.p
83765.82/11709.67	% SZS status Ended for HL404686+5.p
83771.19/11710.34	% SZS status Started for HL404686+4.p
83771.19/11710.34	% SZS status GaveUp for HL404686+4.p
83771.19/11710.34	eprover: CPU time limit exceeded, terminating
83771.19/11710.34	% SZS status Ended for HL404686+4.p
83783.93/11711.88	% SZS status Started for HL404687+5.p
83783.93/11711.88	% SZS status GaveUp for HL404687+5.p
83783.93/11711.88	% SZS status Ended for HL404687+5.p
83793.57/11713.10	% SZS status Started for HL404687+4.p
83793.57/11713.10	% SZS status GaveUp for HL404687+4.p
83793.57/11713.10	eprover: CPU time limit exceeded, terminating
83793.57/11713.10	% SZS status Ended for HL404687+4.p
83798.51/11713.76	% SZS status Started for HL404688+5.p
83798.51/11713.76	% SZS status GaveUp for HL404688+5.p
83798.51/11713.76	% SZS status Ended for HL404688+5.p
83802.55/11714.30	% SZS status Started for HL404688+4.p
83802.55/11714.30	% SZS status GaveUp for HL404688+4.p
83802.55/11714.30	eprover: CPU time limit exceeded, terminating
83802.55/11714.30	% SZS status Ended for HL404688+4.p
83814.48/11716.23	% SZS status Started for HL404689+4.p
83814.48/11716.23	% SZS status GaveUp for HL404689+4.p
83814.48/11716.23	eprover: CPU time limit exceeded, terminating
83814.48/11716.23	% SZS status Ended for HL404689+4.p
83822.18/11717.06	% SZS status Started for HL404689+5.p
83822.18/11717.06	% SZS status GaveUp for HL404689+5.p
83822.18/11717.06	% SZS status Ended for HL404689+5.p
83846.50/11720.46	% SZS status Started for HL404692+5.p
83846.50/11720.46	% SZS status Theorem for HL404692+5.p
83846.50/11720.46	% SZS status Ended for HL404692+5.p
83847.70/11720.60	% SZS status Started for HL404690+4.p
83847.70/11720.60	% SZS status GaveUp for HL404690+4.p
83847.70/11720.60	eprover: CPU time limit exceeded, terminating
83847.70/11720.60	% SZS status Ended for HL404690+4.p
83848.90/11720.65	% SZS status Started for HL404690+5.p
83848.90/11720.65	% SZS status GaveUp for HL404690+5.p
83848.90/11720.65	% SZS status Ended for HL404690+5.p
83868.38/11723.45	% SZS status Started for HL404692+4.p
83868.38/11723.45	% SZS status GaveUp for HL404692+4.p
83868.38/11723.45	eprover: CPU time limit exceeded, terminating
83868.38/11723.45	% SZS status Ended for HL404692+4.p
83880.41/11724.91	% SZS status Started for HL404693+5.p
83880.41/11724.91	% SZS status GaveUp for HL404693+5.p
83880.41/11724.91	% SZS status Ended for HL404693+5.p
83881.27/11725.06	% SZS status Started for HL404693+4.p
83881.27/11725.06	% SZS status GaveUp for HL404693+4.p
83881.27/11725.06	eprover: CPU time limit exceeded, terminating
83881.27/11725.06	% SZS status Ended for HL404693+4.p
83895.51/11726.98	% SZS status Started for HL404694+4.p
83895.51/11726.98	% SZS status GaveUp for HL404694+4.p
83895.51/11726.98	eprover: CPU time limit exceeded, terminating
83895.51/11726.98	% SZS status Ended for HL404694+4.p
83897.79/11727.44	% SZS status Started for HL404694+5.p
83897.79/11727.44	% SZS status GaveUp for HL404694+5.p
83897.79/11727.44	% SZS status Ended for HL404694+5.p
83925.97/11731.07	% SZS status Started for HL404695+5.p
83925.97/11731.07	% SZS status GaveUp for HL404695+5.p
83925.97/11731.07	% SZS status Ended for HL404695+5.p
83926.46/11731.08	% SZS status Started for HL404695+4.p
83926.46/11731.08	% SZS status GaveUp for HL404695+4.p
83926.46/11731.08	eprover: CPU time limit exceeded, terminating
83926.46/11731.08	% SZS status Ended for HL404695+4.p
83935.27/11732.34	% SZS status Started for HL404696+4.p
83935.27/11732.34	% SZS status GaveUp for HL404696+4.p
83935.27/11732.34	eprover: CPU time limit exceeded, terminating
83935.27/11732.34	% SZS status Ended for HL404696+4.p
83943.29/11733.29	% SZS status Started for HL404696+5.p
83943.29/11733.29	% SZS status GaveUp for HL404696+5.p
83943.29/11733.29	% SZS status Ended for HL404696+5.p
83959.05/11735.33	% SZS status Started for HL404697+5.p
83959.05/11735.33	% SZS status GaveUp for HL404697+5.p
83959.05/11735.33	% SZS status Ended for HL404697+5.p
83959.52/11735.50	% SZS status Started for HL404697+4.p
83959.52/11735.50	% SZS status GaveUp for HL404697+4.p
83959.52/11735.50	eprover: CPU time limit exceeded, terminating
83959.52/11735.50	% SZS status Ended for HL404697+4.p
83974.80/11737.45	% SZS status Started for HL404698+5.p
83974.80/11737.45	% SZS status GaveUp for HL404698+5.p
83974.80/11737.45	% SZS status Ended for HL404698+5.p
84001.45/11740.89	% SZS status Started for HL404699+5.p
84001.45/11740.89	% SZS status GaveUp for HL404699+5.p
84001.45/11740.89	% SZS status Ended for HL404699+5.p
84009.16/11741.85	% SZS status Started for HL404699+4.p
84009.16/11741.85	% SZS status GaveUp for HL404699+4.p
84009.16/11741.85	eprover: CPU time limit exceeded, terminating
84009.16/11741.85	% SZS status Ended for HL404699+4.p
84017.30/11742.89	% SZS status Started for HL404700+5.p
84017.30/11742.89	% SZS status GaveUp for HL404700+5.p
84017.30/11742.89	% SZS status Ended for HL404700+5.p
84017.98/11742.99	% SZS status Started for HL404700+4.p
84017.98/11742.99	% SZS status GaveUp for HL404700+4.p
84017.98/11742.99	eprover: CPU time limit exceeded, terminating
84017.98/11742.99	% SZS status Ended for HL404700+4.p
84035.20/11745.21	% SZS status Started for HL404701+5.p
84035.20/11745.21	% SZS status GaveUp for HL404701+5.p
84035.20/11745.21	% SZS status Ended for HL404701+5.p
84042.25/11746.05	% SZS status Started for HL404701+4.p
84042.25/11746.05	% SZS status GaveUp for HL404701+4.p
84042.25/11746.05	eprover: CPU time limit exceeded, terminating
84042.25/11746.05	% SZS status Ended for HL404701+4.p
84075.75/11750.37	% SZS status Started for HL404702+5.p
84075.75/11750.37	% SZS status GaveUp for HL404702+5.p
84075.75/11750.37	% SZS status Ended for HL404702+5.p
84089.27/11752.02	% SZS status Started for HL404703+5.p
84089.27/11752.02	% SZS status GaveUp for HL404703+5.p
84089.27/11752.02	% SZS status Ended for HL404703+5.p
84099.87/11753.33	% SZS status Started for HL404704+4.p
84099.87/11753.33	% SZS status GaveUp for HL404704+4.p
84099.87/11753.33	eprover: CPU time limit exceeded, terminating
84099.87/11753.33	% SZS status Ended for HL404704+4.p
84102.36/11753.69	% SZS status Started for HL404698+4.p
84102.36/11753.69	% SZS status GaveUp for HL404698+4.p
84102.36/11753.69	eprover: CPU time limit exceeded, terminating
84102.36/11753.69	% SZS status Ended for HL404698+4.p
84106.12/11754.28	% SZS status Started for HL404704+5.p
84106.12/11754.28	% SZS status GaveUp for HL404704+5.p
84106.12/11754.28	% SZS status Ended for HL404704+5.p
84150.09/11759.66	% SZS status Started for HL404705+5.p
84150.09/11759.66	% SZS status GaveUp for HL404705+5.p
84150.09/11759.66	% SZS status Ended for HL404705+5.p
84174.03/11762.68	% SZS status Started for HL404706+5.p
84174.03/11762.68	% SZS status GaveUp for HL404706+5.p
84174.03/11762.68	% SZS status Ended for HL404706+5.p
84181.24/11763.56	% SZS status Started for HL404707+5.p
84181.24/11763.56	% SZS status GaveUp for HL404707+5.p
84181.24/11763.56	% SZS status Ended for HL404707+5.p
84183.84/11763.97	% SZS status Started for HL404702+4.p
84183.84/11763.97	% SZS status GaveUp for HL404702+4.p
84183.84/11763.97	eprover: CPU time limit exceeded, terminating
84183.84/11763.97	% SZS status Ended for HL404702+4.p
84215.23/11767.80	% SZS status Started for HL404703+4.p
84215.23/11767.80	% SZS status GaveUp for HL404703+4.p
84215.23/11767.80	eprover: CPU time limit exceeded, terminating
84215.23/11767.80	% SZS status Ended for HL404703+4.p
84246.39/11771.80	% SZS status Started for HL404708+5.p
84246.39/11771.80	% SZS status GaveUp for HL404708+5.p
84246.39/11771.80	% SZS status Ended for HL404708+5.p
84247.42/11771.93	% SZS status Started for HL404705+4.p
84247.42/11771.93	% SZS status GaveUp for HL404705+4.p
84247.42/11771.93	eprover: CPU time limit exceeded, terminating
84247.42/11771.93	% SZS status Ended for HL404705+4.p
84255.92/11772.99	% SZS status Started for HL404709+5.p
84255.92/11772.99	% SZS status Theorem for HL404709+5.p
84255.92/11772.99	% SZS status Ended for HL404709+5.p
84293.97/11777.71	% SZS status Started for HL404706+4.p
84293.97/11777.71	% SZS status GaveUp for HL404706+4.p
84293.97/11777.71	eprover: CPU time limit exceeded, terminating
84293.97/11777.71	% SZS status Ended for HL404706+4.p
84307.31/11779.43	% SZS status Started for HL404707+4.p
84307.31/11779.43	% SZS status GaveUp for HL404707+4.p
84307.31/11779.43	eprover: CPU time limit exceeded, terminating
84307.31/11779.43	% SZS status Ended for HL404707+4.p
84323.38/11781.46	% SZS status Started for HL404710+5.p
84323.38/11781.46	% SZS status GaveUp for HL404710+5.p
84323.38/11781.46	% SZS status Ended for HL404710+5.p
84326.51/11782.04	% SZS status Started for HL404711+5.p
84326.51/11782.04	% SZS status GaveUp for HL404711+5.p
84326.51/11782.04	% SZS status Ended for HL404711+5.p
84354.06/11785.37	% SZS status Started for HL404708+4.p
84354.06/11785.37	% SZS status GaveUp for HL404708+4.p
84354.06/11785.37	eprover: CPU time limit exceeded, terminating
84354.06/11785.37	% SZS status Ended for HL404708+4.p
84383.15/11788.94	% SZS status Started for HL404712+5.p
84383.15/11788.94	% SZS status GaveUp for HL404712+5.p
84383.15/11788.94	% SZS status Ended for HL404712+5.p
84390.37/11789.91	% SZS status Started for HL404709+4.p
84390.37/11789.91	% SZS status GaveUp for HL404709+4.p
84390.37/11789.91	eprover: CPU time limit exceeded, terminating
84390.37/11789.91	% SZS status Ended for HL404709+4.p
84400.40/11791.15	% SZS status Started for HL404714+5.p
84400.40/11791.15	% SZS status GaveUp for HL404714+5.p
84400.40/11791.15	% SZS status Ended for HL404714+5.p
84419.14/11793.57	% SZS status Started for HL404710+4.p
84419.14/11793.57	% SZS status GaveUp for HL404710+4.p
84419.14/11793.57	eprover: CPU time limit exceeded, terminating
84419.14/11793.57	% SZS status Ended for HL404710+4.p
84452.01/11797.61	% SZS status Started for HL404711+4.p
84452.01/11797.61	% SZS status GaveUp for HL404711+4.p
84452.01/11797.61	eprover: CPU time limit exceeded, terminating
84452.01/11797.61	% SZS status Ended for HL404711+4.p
84455.10/11798.08	% SZS status Started for HL404715+5.p
84455.10/11798.08	% SZS status GaveUp for HL404715+5.p
84455.10/11798.08	% SZS status Ended for HL404715+5.p
84474.24/11800.42	% SZS status Started for HL404716+5.p
84474.24/11800.42	% SZS status GaveUp for HL404716+5.p
84474.24/11800.42	% SZS status Ended for HL404716+5.p
84498.77/11803.53	% SZS status Started for HL404712+4.p
84498.77/11803.53	% SZS status GaveUp for HL404712+4.p
84498.77/11803.53	eprover: CPU time limit exceeded, terminating
84498.77/11803.53	% SZS status Ended for HL404712+4.p
84525.55/11806.96	% SZS status Started for HL404717+5.p
84525.55/11806.96	% SZS status GaveUp for HL404717+5.p
84525.55/11806.96	% SZS status Ended for HL404717+5.p
84527.29/11807.14	% SZS status Started for HL404714+4.p
84527.29/11807.14	% SZS status GaveUp for HL404714+4.p
84527.29/11807.14	eprover: CPU time limit exceeded, terminating
84527.29/11807.14	% SZS status Ended for HL404714+4.p
84550.35/11810.03	% SZS status Started for HL404718+5.p
84550.35/11810.03	% SZS status GaveUp for HL404718+5.p
84550.35/11810.03	% SZS status Ended for HL404718+5.p
84559.50/11811.28	% SZS status Started for HL404715+4.p
84559.50/11811.28	% SZS status GaveUp for HL404715+4.p
84559.50/11811.28	eprover: CPU time limit exceeded, terminating
84559.50/11811.28	% SZS status Ended for HL404715+4.p
84597.25/11815.98	% SZS status Started for HL404716+4.p
84597.25/11815.98	% SZS status GaveUp for HL404716+4.p
84597.25/11815.98	eprover: CPU time limit exceeded, terminating
84597.25/11815.98	% SZS status Ended for HL404716+4.p
84599.80/11816.24	% SZS status Started for HL404720+5.p
84599.80/11816.24	% SZS status GaveUp for HL404720+5.p
84599.80/11816.24	% SZS status Ended for HL404720+5.p
84624.20/11819.39	% SZS status Started for HL404722+5.p
84624.20/11819.39	% SZS status GaveUp for HL404722+5.p
84624.20/11819.39	% SZS status Ended for HL404722+5.p
84624.20/11819.43	% SZS status Started for HL404717+4.p
84624.20/11819.43	% SZS status GaveUp for HL404717+4.p
84624.20/11819.43	eprover: CPU time limit exceeded, terminating
84624.20/11819.43	% SZS status Ended for HL404717+4.p
84660.82/11823.97	% SZS status Started for HL404718+4.p
84660.82/11823.97	% SZS status GaveUp for HL404718+4.p
84660.82/11823.97	eprover: CPU time limit exceeded, terminating
84660.82/11823.97	% SZS status Ended for HL404718+4.p
84672.17/11825.34	% SZS status Started for HL404725+5.p
84672.17/11825.34	% SZS status GaveUp for HL404725+5.p
84672.17/11825.34	% SZS status Ended for HL404725+5.p
84696.06/11828.44	% SZS status Started for HL404726+5.p
84696.06/11828.44	% SZS status GaveUp for HL404726+5.p
84696.06/11828.44	% SZS status Ended for HL404726+5.p
84703.84/11829.31	% SZS status Started for HL404720+4.p
84703.84/11829.31	% SZS status GaveUp for HL404720+4.p
84703.84/11829.31	eprover: CPU time limit exceeded, terminating
84703.84/11829.31	% SZS status Ended for HL404720+4.p
84731.60/11832.80	% SZS status Started for HL404722+4.p
84731.60/11832.80	% SZS status GaveUp for HL404722+4.p
84731.60/11832.80	eprover: CPU time limit exceeded, terminating
84731.60/11832.80	% SZS status Ended for HL404722+4.p
84735.51/11833.35	% SZS status Started for HL404727+5.p
84735.51/11833.35	% SZS status GaveUp for HL404727+5.p
84735.51/11833.35	% SZS status Ended for HL404727+5.p
84764.52/11836.93	% SZS status Started for HL404725+4.p
84764.52/11836.93	% SZS status GaveUp for HL404725+4.p
84764.52/11836.93	eprover: CPU time limit exceeded, terminating
84764.52/11836.93	% SZS status Ended for HL404725+4.p
84767.60/11837.58	% SZS status Started for HL404728+5.p
84767.60/11837.58	% SZS status GaveUp for HL404728+5.p
84767.60/11837.58	% SZS status Ended for HL404728+5.p
84804.28/11841.91	% SZS status Started for HL404726+4.p
84804.28/11841.91	% SZS status GaveUp for HL404726+4.p
84804.28/11841.91	eprover: CPU time limit exceeded, terminating
84804.28/11841.91	% SZS status Ended for HL404726+4.p
84806.09/11842.14	% SZS status Started for HL404729+5.p
84806.09/11842.14	% SZS status GaveUp for HL404729+5.p
84806.09/11842.14	% SZS status Ended for HL404729+5.p
84829.62/11845.13	% SZS status Started for HL404727+4.p
84829.62/11845.13	% SZS status GaveUp for HL404727+4.p
84829.62/11845.13	eprover: CPU time limit exceeded, terminating
84829.62/11845.13	% SZS status Ended for HL404727+4.p
84839.12/11846.30	% SZS status Started for HL404730+5.p
84839.12/11846.30	% SZS status GaveUp for HL404730+5.p
84839.12/11846.30	% SZS status Ended for HL404730+5.p
84877.62/11851.18	% SZS status Started for HL404728+4.p
84877.62/11851.18	% SZS status GaveUp for HL404728+4.p
84877.62/11851.18	eprover: CPU time limit exceeded, terminating
84877.62/11851.18	% SZS status Ended for HL404728+4.p
84881.35/11851.37	% SZS status Started for HL404731+5.p
84881.35/11851.37	% SZS status GaveUp for HL404731+5.p
84881.35/11851.37	% SZS status Ended for HL404731+5.p
84905.88/11854.47	% SZS status Started for HL404732+5.p
84905.88/11854.47	% SZS status GaveUp for HL404732+5.p
84905.88/11854.47	% SZS status Ended for HL404732+5.p
84911.77/11855.13	% SZS status Started for HL404729+4.p
84911.77/11855.13	% SZS status GaveUp for HL404729+4.p
84911.77/11855.13	eprover: CPU time limit exceeded, terminating
84911.77/11855.13	% SZS status Ended for HL404729+4.p
84944.55/11859.28	% SZS status Started for HL404730+4.p
84944.55/11859.28	% SZS status GaveUp for HL404730+4.p
84944.55/11859.28	eprover: CPU time limit exceeded, terminating
84944.55/11859.28	% SZS status Ended for HL404730+4.p
84953.71/11860.46	% SZS status Started for HL404733+5.p
84953.71/11860.46	% SZS status GaveUp for HL404733+5.p
84953.71/11860.46	% SZS status Ended for HL404733+5.p
84976.05/11863.32	% SZS status Started for HL404731+4.p
84976.05/11863.32	% SZS status GaveUp for HL404731+4.p
84976.05/11863.32	eprover: CPU time limit exceeded, terminating
84976.05/11863.32	% SZS status Ended for HL404731+4.p
84981.45/11863.95	% SZS status Started for HL404734+5.p
84981.45/11863.95	% SZS status GaveUp for HL404734+5.p
84981.45/11863.95	% SZS status Ended for HL404734+5.p
85013.12/11867.90	% SZS status Started for HL404732+4.p
85013.12/11867.90	% SZS status GaveUp for HL404732+4.p
85013.12/11867.90	eprover: CPU time limit exceeded, terminating
85013.12/11867.90	% SZS status Ended for HL404732+4.p
85018.95/11868.65	% SZS status Started for HL404735+5.p
85018.95/11868.65	% SZS status GaveUp for HL404735+5.p
85018.95/11868.65	% SZS status Ended for HL404735+5.p
85045.23/11872.01	% SZS status Started for HL404733+4.p
85045.23/11872.01	% SZS status GaveUp for HL404733+4.p
85045.23/11872.01	eprover: CPU time limit exceeded, terminating
85045.23/11872.01	% SZS status Ended for HL404733+4.p
85049.88/11872.58	% SZS status Started for HL404736+5.p
85049.88/11872.58	% SZS status GaveUp for HL404736+5.p
85049.88/11872.58	% SZS status Ended for HL404736+5.p
85086.81/11877.21	% SZS status Started for HL404734+4.p
85086.81/11877.21	% SZS status GaveUp for HL404734+4.p
85086.81/11877.21	eprover: CPU time limit exceeded, terminating
85086.81/11877.21	% SZS status Ended for HL404734+4.p
85090.12/11877.61	% SZS status Started for HL404737+5.p
85090.12/11877.61	% SZS status GaveUp for HL404737+5.p
85090.12/11877.61	% SZS status Ended for HL404737+5.p
85116.88/11881.01	% SZS status Started for HL404735+4.p
85116.88/11881.01	% SZS status GaveUp for HL404735+4.p
85116.88/11881.01	eprover: CPU time limit exceeded, terminating
85116.88/11881.01	% SZS status Ended for HL404735+4.p
85120.64/11881.47	% SZS status Started for HL404738+5.p
85120.64/11881.47	% SZS status GaveUp for HL404738+5.p
85120.64/11881.47	% SZS status Ended for HL404738+5.p
85157.95/11886.25	% SZS status Started for HL404736+4.p
85157.95/11886.25	% SZS status GaveUp for HL404736+4.p
85157.95/11886.25	eprover: CPU time limit exceeded, terminating
85157.95/11886.25	% SZS status Ended for HL404736+4.p
85162.21/11886.70	% SZS status Started for HL404739+5.p
85162.21/11886.70	% SZS status GaveUp for HL404739+5.p
85162.21/11886.70	% SZS status Ended for HL404739+5.p
85185.97/11889.85	% SZS status Started for HL404737+4.p
85185.97/11889.85	% SZS status GaveUp for HL404737+4.p
85185.97/11889.85	eprover: CPU time limit exceeded, terminating
85185.97/11889.85	% SZS status Ended for HL404737+4.p
85193.42/11890.62	% SZS status Started for HL404740+5.p
85193.42/11890.62	% SZS status GaveUp for HL404740+5.p
85193.42/11890.62	% SZS status Ended for HL404740+5.p
85223.72/11894.46	% SZS status Started for HL404738+4.p
85223.72/11894.46	% SZS status GaveUp for HL404738+4.p
85223.72/11894.46	eprover: CPU time limit exceeded, terminating
85223.72/11894.46	% SZS status Ended for HL404738+4.p
85231.76/11895.58	% SZS status Started for HL404741+5.p
85231.76/11895.58	% SZS status GaveUp for HL404741+5.p
85231.76/11895.58	% SZS status Ended for HL404741+5.p
85254.38/11898.38	% SZS status Started for HL404739+4.p
85254.38/11898.38	% SZS status GaveUp for HL404739+4.p
85254.38/11898.38	eprover: CPU time limit exceeded, terminating
85254.38/11898.38	% SZS status Ended for HL404739+4.p
85260.77/11899.18	% SZS status Started for HL404742+5.p
85260.77/11899.18	% SZS status GaveUp for HL404742+5.p
85260.77/11899.18	% SZS status Ended for HL404742+5.p
85294.88/11903.50	% SZS status Started for HL404740+4.p
85294.88/11903.50	% SZS status GaveUp for HL404740+4.p
85294.88/11903.50	eprover: CPU time limit exceeded, terminating
85294.88/11903.50	% SZS status Ended for HL404740+4.p
85299.62/11904.02	% SZS status Started for HL404744+5.p
85299.62/11904.02	% SZS status GaveUp for HL404744+5.p
85299.62/11904.02	% SZS status Ended for HL404744+5.p
85327.64/11907.56	% SZS status Started for HL404741+4.p
85327.64/11907.56	% SZS status GaveUp for HL404741+4.p
85327.64/11907.56	eprover: CPU time limit exceeded, terminating
85327.64/11907.56	% SZS status Ended for HL404741+4.p
85329.21/11907.68	% SZS status Started for HL404745+5.p
85329.21/11907.68	% SZS status GaveUp for HL404745+5.p
85329.21/11907.68	% SZS status Ended for HL404745+5.p
85367.61/11912.63	% SZS status Started for HL404742+4.p
85367.61/11912.63	% SZS status GaveUp for HL404742+4.p
85367.61/11912.63	eprover: CPU time limit exceeded, terminating
85367.61/11912.63	% SZS status Ended for HL404742+4.p
85369.57/11912.87	% SZS status Started for HL404746+5.p
85369.57/11912.87	% SZS status GaveUp for HL404746+5.p
85369.57/11912.87	% SZS status Ended for HL404746+5.p
85398.21/11916.42	% SZS status Started for HL404744+4.p
85398.21/11916.42	% SZS status GaveUp for HL404744+4.p
85398.21/11916.42	eprover: CPU time limit exceeded, terminating
85398.21/11916.42	% SZS status Ended for HL404744+4.p
85402.02/11916.96	% SZS status Started for HL404747+5.p
85402.02/11916.96	% SZS status GaveUp for HL404747+5.p
85402.02/11916.96	% SZS status Ended for HL404747+5.p
85435.81/11921.28	% SZS status Started for HL404745+4.p
85435.81/11921.28	% SZS status GaveUp for HL404745+4.p
85435.81/11921.28	eprover: CPU time limit exceeded, terminating
85435.81/11921.28	% SZS status Ended for HL404745+4.p
85442.98/11922.06	% SZS status Started for HL404748+5.p
85442.98/11922.06	% SZS status GaveUp for HL404748+5.p
85442.98/11922.06	% SZS status Ended for HL404748+5.p
85466.38/11925.02	% SZS status Started for HL404746+4.p
85466.38/11925.02	% SZS status GaveUp for HL404746+4.p
85466.38/11925.02	eprover: CPU time limit exceeded, terminating
85466.38/11925.02	% SZS status Ended for HL404746+4.p
85475.44/11926.16	% SZS status Started for HL404750+5.p
85475.44/11926.16	% SZS status GaveUp for HL404750+5.p
85475.44/11926.16	% SZS status Ended for HL404750+5.p
85503.62/11929.75	% SZS status Started for HL404747+4.p
85503.62/11929.75	% SZS status GaveUp for HL404747+4.p
85503.62/11929.75	eprover: CPU time limit exceeded, terminating
85503.62/11929.75	% SZS status Ended for HL404747+4.p
85513.36/11930.71	% SZS status Started for HL404751+5.p
85513.36/11930.71	% SZS status GaveUp for HL404751+5.p
85513.36/11930.71	% SZS status Ended for HL404751+5.p
85535.62/11933.49	% SZS status Started for HL404748+4.p
85535.62/11933.49	% SZS status GaveUp for HL404748+4.p
85535.62/11933.49	eprover: CPU time limit exceeded, terminating
85535.62/11933.49	% SZS status Ended for HL404748+4.p
85545.17/11934.67	% SZS status Started for HL404752+5.p
85545.17/11934.67	% SZS status GaveUp for HL404752+5.p
85545.17/11934.67	% SZS status Ended for HL404752+5.p
85577.60/11938.75	% SZS status Started for HL404750+4.p
85577.60/11938.75	% SZS status GaveUp for HL404750+4.p
85577.60/11938.75	eprover: CPU time limit exceeded, terminating
85577.60/11938.75	% SZS status Ended for HL404750+4.p
85579.09/11939.03	% SZS status Started for HL404753+5.p
85579.09/11939.03	% SZS status GaveUp for HL404753+5.p
85579.09/11939.03	% SZS status Ended for HL404753+5.p
85609.00/11942.74	% SZS status Started for HL404751+4.p
85609.00/11942.74	% SZS status GaveUp for HL404751+4.p
85609.00/11942.74	eprover: CPU time limit exceeded, terminating
85609.00/11942.74	% SZS status Ended for HL404751+4.p
85609.52/11942.82	% SZS status Started for HL404754+5.p
85609.52/11942.82	% SZS status GaveUp for HL404754+5.p
85609.52/11942.82	% SZS status Ended for HL404754+5.p
85650.60/11948.04	% SZS status Started for HL404752+4.p
85650.60/11948.04	% SZS status GaveUp for HL404752+4.p
85650.60/11948.04	eprover: CPU time limit exceeded, terminating
85650.60/11948.04	% SZS status Ended for HL404752+4.p
85651.84/11948.09	% SZS status Started for HL404755+5.p
85651.84/11948.09	% SZS status GaveUp for HL404755+5.p
85651.84/11948.09	% SZS status Ended for HL404755+5.p
85683.45/11952.05	% SZS status Started for HL404753+4.p
85683.45/11952.05	% SZS status GaveUp for HL404753+4.p
85683.45/11952.05	eprover: CPU time limit exceeded, terminating
85683.45/11952.05	% SZS status Ended for HL404753+4.p
85684.18/11952.15	% SZS status Started for HL404756+5.p
85684.18/11952.15	% SZS status GaveUp for HL404756+5.p
85684.18/11952.15	% SZS status Ended for HL404756+5.p
85718.77/11956.58	% SZS status Started for HL404754+4.p
85718.77/11956.58	% SZS status GaveUp for HL404754+4.p
85718.77/11956.58	eprover: CPU time limit exceeded, terminating
85718.77/11956.58	% SZS status Ended for HL404754+4.p
85725.55/11957.39	% SZS status Started for HL404757+5.p
85725.55/11957.39	% SZS status GaveUp for HL404757+5.p
85725.55/11957.39	% SZS status Ended for HL404757+5.p
85751.96/11960.78	% SZS status Started for HL404755+4.p
85751.96/11960.78	% SZS status GaveUp for HL404755+4.p
85751.96/11960.78	eprover: CPU time limit exceeded, terminating
85751.96/11960.78	% SZS status Ended for HL404755+4.p
85783.48/11961.44	% SZS status Started for HL404759+5.p
85783.48/11961.44	% SZS status GaveUp for HL404759+5.p
85783.48/11961.44	% SZS status Ended for HL404759+5.p
85811.19/11964.91	% SZS status Started for HL404756+4.p
85811.19/11964.91	% SZS status GaveUp for HL404756+4.p
85811.19/11964.91	eprover: CPU time limit exceeded, terminating
85811.19/11964.91	% SZS status Ended for HL404756+4.p
85819.17/11965.99	% SZS status Started for HL404760+5.p
85819.17/11965.99	% SZS status GaveUp for HL404760+5.p
85819.17/11965.99	% SZS status Ended for HL404760+5.p
85841.45/11968.69	% SZS status Started for HL404757+4.p
85841.45/11968.69	% SZS status GaveUp for HL404757+4.p
85841.45/11968.69	eprover: CPU time limit exceeded, terminating
85841.45/11968.69	% SZS status Ended for HL404757+4.p
85854.25/11970.32	% SZS status Started for HL404761+5.p
85854.25/11970.32	% SZS status GaveUp for HL404761+5.p
85854.25/11970.32	% SZS status Ended for HL404761+5.p
85883.73/11974.11	% SZS status Started for HL404759+4.p
85883.73/11974.11	% SZS status GaveUp for HL404759+4.p
85883.73/11974.11	eprover: CPU time limit exceeded, terminating
85883.73/11974.11	% SZS status Ended for HL404759+4.p
85884.58/11974.27	% SZS status Started for HL404762+5.p
85884.58/11974.27	% SZS status GaveUp for HL404762+5.p
85884.58/11974.27	% SZS status Ended for HL404762+5.p
85915.41/11978.08	% SZS status Started for HL404763+5.p
85915.41/11978.08	% SZS status GaveUp for HL404763+5.p
85915.41/11978.08	% SZS status Ended for HL404763+5.p
85925.16/11978.16	% SZS status Started for HL404760+4.p
85925.16/11978.16	% SZS status GaveUp for HL404760+4.p
85925.16/11978.16	eprover: CPU time limit exceeded, terminating
85925.16/11978.16	% SZS status Ended for HL404760+4.p
85964.95/11983.25	% SZS status Started for HL404761+4.p
85964.95/11983.25	% SZS status GaveUp for HL404761+4.p
85964.95/11983.25	eprover: CPU time limit exceeded, terminating
85964.95/11983.25	% SZS status Ended for HL404761+4.p
85967.83/11983.58	% SZS status Started for HL404764+5.p
85967.83/11983.58	% SZS status GaveUp for HL404764+5.p
85967.83/11983.58	% SZS status Ended for HL404764+5.p
85997.20/11987.27	% SZS status Started for HL404762+4.p
85997.20/11987.27	% SZS status GaveUp for HL404762+4.p
85997.20/11987.27	eprover: CPU time limit exceeded, terminating
85997.20/11987.27	% SZS status Ended for HL404762+4.p
86001.84/11987.83	% SZS status Started for HL404765+5.p
86001.84/11987.83	% SZS status GaveUp for HL404765+5.p
86001.84/11987.83	% SZS status Ended for HL404765+5.p
86032.36/11991.68	% SZS status Started for HL404763+4.p
86032.36/11991.68	% SZS status GaveUp for HL404763+4.p
86032.36/11991.68	eprover: CPU time limit exceeded, terminating
86032.36/11991.68	% SZS status Ended for HL404763+4.p
86037.82/11992.40	% SZS status Started for HL404766+5.p
86037.82/11992.40	% SZS status GaveUp for HL404766+5.p
86037.82/11992.40	% SZS status Ended for HL404766+5.p
86069.72/11996.39	% SZS status Started for HL404767+5.p
86069.72/11996.39	% SZS status GaveUp for HL404767+5.p
86069.72/11996.39	% SZS status Ended for HL404767+5.p
86070.43/11996.47	% SZS status Started for HL404764+4.p
86070.43/11996.47	% SZS status GaveUp for HL404764+4.p
86070.43/11996.47	eprover: CPU time limit exceeded, terminating
86070.43/11996.47	% SZS status Ended for HL404764+4.p
86101.42/12000.39	% SZS status Started for HL404765+4.p
86101.42/12000.39	% SZS status GaveUp for HL404765+4.p
86101.42/12000.39	eprover: CPU time limit exceeded, terminating
86101.42/12000.39	% SZS status Ended for HL404765+4.p
86103.47/12000.79	% SZS status Started for HL404768+5.p
86103.47/12000.79	% SZS status GaveUp for HL404768+5.p
86103.47/12000.79	% SZS status Ended for HL404768+5.p
86130.59/12004.04	% SZS status Started for HL404766+4.p
86130.59/12004.04	% SZS status GaveUp for HL404766+4.p
86130.59/12004.04	eprover: CPU time limit exceeded, terminating
86130.59/12004.04	% SZS status Ended for HL404766+4.p
86141.55/12005.48	% SZS status Started for HL404769+5.p
86141.55/12005.48	% SZS status GaveUp for HL404769+5.p
86141.55/12005.48	% SZS status Ended for HL404769+5.p
86142.70/12005.75	% SZS status Started for HL404772+5.p
86142.70/12005.75	% SZS status Theorem for HL404772+5.p
86142.70/12005.75	% SZS status Ended for HL404772+5.p
86174.38/12009.61	% SZS status Started for HL404767+4.p
86174.38/12009.61	% SZS status GaveUp for HL404767+4.p
86174.38/12009.61	eprover: CPU time limit exceeded, terminating
86174.38/12009.61	% SZS status Ended for HL404767+4.p
86175.23/12009.72	% SZS status Started for HL404771+5.p
86175.23/12009.72	% SZS status GaveUp for HL404771+5.p
86175.23/12009.72	% SZS status Ended for HL404771+5.p
86208.70/12013.95	% SZS status Started for HL404768+4.p
86208.70/12013.95	% SZS status GaveUp for HL404768+4.p
86208.70/12013.95	eprover: CPU time limit exceeded, terminating
86208.70/12013.95	% SZS status Ended for HL404768+4.p
86218.56/12015.26	% SZS status Started for HL404773+5.p
86218.56/12015.26	% SZS status GaveUp for HL404773+5.p
86218.56/12015.26	% SZS status Ended for HL404773+5.p
86241.94/12018.17	% SZS status Started for HL404769+4.p
86241.94/12018.17	% SZS status GaveUp for HL404769+4.p
86241.94/12018.17	eprover: CPU time limit exceeded, terminating
86241.94/12018.17	% SZS status Ended for HL404769+4.p
86246.34/12018.77	% SZS status Started for HL404774+5.p
86246.34/12018.77	% SZS status GaveUp for HL404774+5.p
86246.34/12018.77	% SZS status Ended for HL404774+5.p
86277.39/12022.59	% SZS status Started for HL404771+4.p
86277.39/12022.59	% SZS status GaveUp for HL404771+4.p
86277.39/12022.59	eprover: CPU time limit exceeded, terminating
86277.39/12022.59	% SZS status Ended for HL404771+4.p
86291.65/12024.39	% SZS status Started for HL404775+5.p
86291.65/12024.39	% SZS status GaveUp for HL404775+5.p
86291.65/12024.39	% SZS status Ended for HL404775+5.p
86308.02/12026.47	% SZS status Started for HL404772+4.p
86308.02/12026.47	% SZS status GaveUp for HL404772+4.p
86308.02/12026.47	eprover: CPU time limit exceeded, terminating
86308.02/12026.47	% SZS status Ended for HL404772+4.p
86318.76/12027.92	% SZS status Started for HL404777+5.p
86318.76/12027.92	% SZS status GaveUp for HL404777+5.p
86318.76/12027.92	% SZS status Ended for HL404777+5.p
86345.84/12031.31	% SZS status Started for HL404773+4.p
86345.84/12031.31	% SZS status GaveUp for HL404773+4.p
86345.84/12031.31	eprover: CPU time limit exceeded, terminating
86345.84/12031.31	% SZS status Ended for HL404773+4.p
86366.34/12033.79	% SZS status Started for HL404778+5.p
86366.34/12033.79	% SZS status GaveUp for HL404778+5.p
86366.34/12033.79	% SZS status Ended for HL404778+5.p
86378.10/12035.33	% SZS status Started for HL404774+4.p
86378.10/12035.33	% SZS status GaveUp for HL404774+4.p
86378.10/12035.33	eprover: CPU time limit exceeded, terminating
86378.10/12035.33	% SZS status Ended for HL404774+4.p
86391.15/12036.96	% SZS status Started for HL404779+5.p
86391.15/12036.96	% SZS status GaveUp for HL404779+5.p
86391.15/12036.96	% SZS status Ended for HL404779+5.p
86414.01/12039.80	% SZS status Started for HL404775+4.p
86414.01/12039.80	% SZS status GaveUp for HL404775+4.p
86414.01/12039.80	eprover: CPU time limit exceeded, terminating
86414.01/12039.80	% SZS status Ended for HL404775+4.p
86438.49/12042.92	% SZS status Started for HL404780+5.p
86438.49/12042.92	% SZS status GaveUp for HL404780+5.p
86438.49/12042.92	% SZS status Ended for HL404780+5.p
86446.72/12043.92	% SZS status Started for HL404777+4.p
86446.72/12043.92	% SZS status GaveUp for HL404777+4.p
86446.72/12043.92	eprover: CPU time limit exceeded, terminating
86446.72/12043.92	% SZS status Ended for HL404777+4.p
86468.02/12046.60	% SZS status Started for HL404781+5.p
86468.02/12046.60	% SZS status GaveUp for HL404781+5.p
86468.02/12046.60	% SZS status Ended for HL404781+5.p
86485.34/12048.76	% SZS status Started for HL404778+4.p
86485.34/12048.76	% SZS status GaveUp for HL404778+4.p
86485.34/12048.76	eprover: CPU time limit exceeded, terminating
86485.34/12048.76	% SZS status Ended for HL404778+4.p
86513.53/12052.31	% SZS status Started for HL404782+5.p
86513.53/12052.31	% SZS status GaveUp for HL404782+5.p
86513.53/12052.31	% SZS status Ended for HL404782+5.p
86514.66/12052.45	% SZS status Started for HL404779+4.p
86514.66/12052.45	% SZS status GaveUp for HL404779+4.p
86514.66/12052.45	eprover: CPU time limit exceeded, terminating
86514.66/12052.45	% SZS status Ended for HL404779+4.p
86542.86/12056.09	% SZS status Started for HL404784+5.p
86542.86/12056.09	% SZS status GaveUp for HL404784+5.p
86542.86/12056.09	% SZS status Ended for HL404784+5.p
86553.07/12057.37	% SZS status Started for HL404780+4.p
86553.07/12057.37	% SZS status GaveUp for HL404780+4.p
86553.07/12057.37	eprover: CPU time limit exceeded, terminating
86553.07/12057.37	% SZS status Ended for HL404780+4.p
86583.09/12061.08	% SZS status Started for HL404781+4.p
86583.09/12061.08	% SZS status GaveUp for HL404781+4.p
86583.09/12061.08	eprover: CPU time limit exceeded, terminating
86583.09/12061.08	% SZS status Ended for HL404781+4.p
86589.73/12061.97	% SZS status Started for HL404785+5.p
86589.73/12061.97	% SZS status GaveUp for HL404785+5.p
86589.73/12061.97	% SZS status Ended for HL404785+5.p
86615.78/12065.20	% SZS status Started for HL404786+5.p
86615.78/12065.20	% SZS status GaveUp for HL404786+5.p
86615.78/12065.20	% SZS status Ended for HL404786+5.p
86617.80/12065.50	% SZS status Started for HL404782+4.p
86617.80/12065.50	% SZS status GaveUp for HL404782+4.p
86617.80/12065.50	eprover: CPU time limit exceeded, terminating
86617.80/12065.50	% SZS status Ended for HL404782+4.p
86652.96/12069.87	% SZS status Started for HL404784+4.p
86652.96/12069.87	% SZS status GaveUp for HL404784+4.p
86652.96/12069.87	eprover: CPU time limit exceeded, terminating
86652.96/12069.87	% SZS status Ended for HL404784+4.p
86654.83/12070.17	% SZS status Started for HL404787+5.p
86654.83/12070.17	% SZS status GaveUp for HL404787+5.p
86654.83/12070.17	% SZS status Ended for HL404787+5.p
86689.34/12074.45	% SZS status Started for HL404788+5.p
86689.34/12074.45	% SZS status GaveUp for HL404788+5.p
86689.34/12074.45	% SZS status Ended for HL404788+5.p
86690.89/12074.64	% SZS status Started for HL404785+4.p
86690.89/12074.64	% SZS status GaveUp for HL404785+4.p
86690.89/12074.64	eprover: CPU time limit exceeded, terminating
86690.89/12074.64	% SZS status Ended for HL404785+4.p
86718.80/12078.27	% SZS status Started for HL404786+4.p
86718.80/12078.27	% SZS status GaveUp for HL404786+4.p
86718.80/12078.27	eprover: CPU time limit exceeded, terminating
86718.80/12078.27	% SZS status Ended for HL404786+4.p
86725.07/12078.97	% SZS status Started for HL404789+5.p
86725.07/12078.97	% SZS status GaveUp for HL404789+5.p
86725.07/12078.97	% SZS status Ended for HL404789+5.p
86758.95/12083.21	% SZS status Started for HL404787+4.p
86758.95/12083.21	% SZS status GaveUp for HL404787+4.p
86758.95/12083.21	eprover: CPU time limit exceeded, terminating
86758.95/12083.21	% SZS status Ended for HL404787+4.p
86766.30/12084.11	% SZS status Started for HL404791+5.p
86766.30/12084.11	% SZS status GaveUp for HL404791+5.p
86766.30/12084.11	% SZS status Ended for HL404791+5.p
86795.20/12087.75	% SZS status Started for HL404792+5.p
86795.20/12087.75	% SZS status GaveUp for HL404792+5.p
86795.20/12087.75	% SZS status Ended for HL404792+5.p
86797.84/12088.15	% SZS status Started for HL404788+4.p
86797.84/12088.15	% SZS status GaveUp for HL404788+4.p
86797.84/12088.15	eprover: CPU time limit exceeded, terminating
86797.84/12088.15	% SZS status Ended for HL404788+4.p
86824.14/12091.35	% SZS status Started for HL404789+4.p
86824.14/12091.35	% SZS status GaveUp for HL404789+4.p
86824.14/12091.35	eprover: CPU time limit exceeded, terminating
86824.14/12091.35	% SZS status Ended for HL404789+4.p
86836.34/12092.86	% SZS status Started for HL404793+5.p
86836.34/12092.86	% SZS status GaveUp for HL404793+5.p
86836.34/12092.86	% SZS status Ended for HL404793+5.p
86861.91/12096.11	% SZS status Started for HL404791+4.p
86861.91/12096.11	% SZS status GaveUp for HL404791+4.p
86861.91/12096.11	eprover: CPU time limit exceeded, terminating
86861.91/12096.11	% SZS status Ended for HL404791+4.p
86870.33/12097.15	% SZS status Started for HL404794+5.p
86870.33/12097.15	% SZS status GaveUp for HL404794+5.p
86870.33/12097.15	% SZS status Ended for HL404794+5.p
86895.36/12100.33	% SZS status Started for HL404792+4.p
86895.36/12100.33	% SZS status GaveUp for HL404792+4.p
86895.36/12100.33	eprover: CPU time limit exceeded, terminating
86895.36/12100.33	% SZS status Ended for HL404792+4.p
86897.27/12100.60	% SZS status Started for HL404796+5.p
86897.27/12100.60	% SZS status GaveUp for HL404796+5.p
86897.27/12100.60	% SZS status Ended for HL404796+5.p
86929.88/12104.69	% SZS status Started for HL404793+4.p
86929.88/12104.69	% SZS status GaveUp for HL404793+4.p
86929.88/12104.69	eprover: CPU time limit exceeded, terminating
86929.88/12104.69	% SZS status Ended for HL404793+4.p
86935.68/12105.40	% SZS status Started for HL404797+5.p
86935.68/12105.40	% SZS status GaveUp for HL404797+5.p
86935.68/12105.40	% SZS status Ended for HL404797+5.p
86970.42/12109.76	% SZS status Started for HL404798+5.p
86970.42/12109.76	% SZS status GaveUp for HL404798+5.p
86970.42/12109.76	% SZS status Ended for HL404798+5.p
86972.22/12110.12	% SZS status Started for HL404794+4.p
86972.22/12110.12	% SZS status GaveUp for HL404794+4.p
86972.22/12110.12	eprover: CPU time limit exceeded, terminating
86972.22/12110.12	% SZS status Ended for HL404794+4.p
87002.26/12113.77	% SZS status Started for HL404800+5.p
87002.26/12113.77	% SZS status GaveUp for HL404800+5.p
87002.26/12113.77	% SZS status Ended for HL404800+5.p
87002.26/12113.83	% SZS status Started for HL404796+4.p
87002.26/12113.83	% SZS status GaveUp for HL404796+4.p
87002.26/12113.83	eprover: CPU time limit exceeded, terminating
87002.26/12113.83	% SZS status Ended for HL404796+4.p
87041.22/12118.65	% SZS status Started for HL404797+4.p
87041.22/12118.65	% SZS status GaveUp for HL404797+4.p
87041.22/12118.65	eprover: CPU time limit exceeded, terminating
87041.22/12118.65	% SZS status Ended for HL404797+4.p
87042.53/12118.87	% SZS status Started for HL404801+5.p
87042.53/12118.87	% SZS status GaveUp for HL404801+5.p
87042.53/12118.87	% SZS status Ended for HL404801+5.p
87074.13/12122.84	% SZS status Started for HL404798+4.p
87074.13/12122.84	% SZS status GaveUp for HL404798+4.p
87074.13/12122.84	eprover: CPU time limit exceeded, terminating
87074.13/12122.84	% SZS status Ended for HL404798+4.p
87075.35/12122.97	% SZS status Started for HL404803+5.p
87075.35/12122.97	% SZS status GaveUp for HL404803+5.p
87075.35/12122.97	% SZS status Ended for HL404803+5.p
87102.22/12126.51	% SZS status Started for HL404800+4.p
87102.22/12126.51	% SZS status GaveUp for HL404800+4.p
87102.22/12126.51	eprover: CPU time limit exceeded, terminating
87102.22/12126.51	% SZS status Ended for HL404800+4.p
87140.02/12128.10	% SZS status Started for HL404804+5.p
87140.02/12128.10	% SZS status GaveUp for HL404804+5.p
87140.02/12128.10	% SZS status Ended for HL404804+5.p
87166.91/12131.32	% SZS status Started for HL404801+4.p
87166.91/12131.32	% SZS status GaveUp for HL404801+4.p
87166.91/12131.32	eprover: CPU time limit exceeded, terminating
87166.91/12131.32	% SZS status Ended for HL404801+4.p
87175.50/12132.43	% SZS status Started for HL404805+5.p
87175.50/12132.43	% SZS status GaveUp for HL404805+5.p
87175.50/12132.43	% SZS status Ended for HL404805+5.p
87204.44/12136.09	% SZS status Started for HL404806+5.p
87204.44/12136.09	% SZS status GaveUp for HL404806+5.p
87204.44/12136.09	% SZS status Ended for HL404806+5.p
87204.78/12136.10	% SZS status Started for HL404803+4.p
87204.78/12136.10	% SZS status GaveUp for HL404803+4.p
87204.78/12136.10	eprover: CPU time limit exceeded, terminating
87204.78/12136.10	% SZS status Ended for HL404803+4.p
87234.43/12139.86	% SZS status Started for HL404804+4.p
87234.43/12139.86	% SZS status GaveUp for HL404804+4.p
87234.43/12139.86	eprover: CPU time limit exceeded, terminating
87234.43/12139.86	% SZS status Ended for HL404804+4.p
87240.58/12140.64	% SZS status Started for HL404807+5.p
87240.58/12140.64	% SZS status GaveUp for HL404807+5.p
87240.58/12140.64	% SZS status Ended for HL404807+5.p
87273.30/12144.74	% SZS status Started for HL404805+4.p
87273.30/12144.74	% SZS status GaveUp for HL404805+4.p
87273.30/12144.74	eprover: CPU time limit exceeded, terminating
87273.30/12144.74	% SZS status Ended for HL404805+4.p
87278.18/12145.39	% SZS status Started for HL404808+5.p
87278.18/12145.39	% SZS status GaveUp for HL404808+5.p
87278.18/12145.39	% SZS status Ended for HL404808+5.p
87305.98/12148.84	% SZS status Started for HL404806+4.p
87305.98/12148.84	% SZS status GaveUp for HL404806+4.p
87305.98/12148.84	eprover: CPU time limit exceeded, terminating
87305.98/12148.84	% SZS status Ended for HL404806+4.p
87307.28/12149.03	% SZS status Started for HL404809+5.p
87307.28/12149.03	% SZS status GaveUp for HL404809+5.p
87307.28/12149.03	% SZS status Ended for HL404809+5.p
87345.80/12153.88	% SZS status Started for HL404807+4.p
87345.80/12153.88	% SZS status GaveUp for HL404807+4.p
87345.80/12153.88	eprover: CPU time limit exceeded, terminating
87345.80/12153.88	% SZS status Ended for HL404807+4.p
87347.38/12154.08	% SZS status Started for HL404810+5.p
87347.38/12154.08	% SZS status GaveUp for HL404810+5.p
87347.38/12154.08	% SZS status Ended for HL404810+5.p
87379.81/12158.16	% SZS status Started for HL404811+5.p
87379.81/12158.16	% SZS status GaveUp for HL404811+5.p
87379.81/12158.16	% SZS status Ended for HL404811+5.p
87381.79/12158.41	% SZS status Started for HL404808+4.p
87381.79/12158.41	% SZS status GaveUp for HL404808+4.p
87381.79/12158.41	eprover: CPU time limit exceeded, terminating
87381.79/12158.41	% SZS status Ended for HL404808+4.p
87409.84/12161.95	% SZS status Started for HL404809+4.p
87409.84/12161.95	% SZS status GaveUp for HL404809+4.p
87409.84/12161.95	eprover: CPU time limit exceeded, terminating
87409.84/12161.95	% SZS status Ended for HL404809+4.p
87421.06/12163.37	% SZS status Started for HL404812+5.p
87421.06/12163.37	% SZS status GaveUp for HL404812+5.p
87421.06/12163.37	% SZS status Ended for HL404812+5.p
87444.52/12166.39	% SZS status Started for HL404810+4.p
87444.52/12166.39	% SZS status GaveUp for HL404810+4.p
87444.52/12166.39	eprover: CPU time limit exceeded, terminating
87444.52/12166.39	% SZS status Ended for HL404810+4.p
87453.75/12167.43	% SZS status Started for HL404814+5.p
87453.75/12167.43	% SZS status GaveUp for HL404814+5.p
87453.75/12167.43	% SZS status Ended for HL404814+5.p
87482.92/12171.13	% SZS status Started for HL404811+4.p
87482.92/12171.13	% SZS status GaveUp for HL404811+4.p
87482.92/12171.13	eprover: CPU time limit exceeded, terminating
87482.92/12171.13	% SZS status Ended for HL404811+4.p
87483.69/12171.27	% SZS status Started for HL404815+5.p
87483.69/12171.27	% SZS status GaveUp for HL404815+5.p
87483.69/12171.27	% SZS status Ended for HL404815+5.p
87512.26/12174.93	% SZS status Started for HL404812+4.p
87512.26/12174.93	% SZS status GaveUp for HL404812+4.p
87512.26/12174.93	eprover: CPU time limit exceeded, terminating
87512.26/12174.93	% SZS status Ended for HL404812+4.p
87517.76/12175.53	% SZS status Started for HL404816+5.p
87517.76/12175.53	% SZS status GaveUp for HL404816+5.p
87517.76/12175.53	% SZS status Ended for HL404816+5.p
87552.32/12179.83	% SZS status Started for HL404814+4.p
87552.32/12179.83	% SZS status GaveUp for HL404814+4.p
87552.32/12179.83	eprover: CPU time limit exceeded, terminating
87552.32/12179.83	% SZS status Ended for HL404814+4.p
87557.71/12180.52	% SZS status Started for HL404817+5.p
87557.71/12180.52	% SZS status GaveUp for HL404817+5.p
87557.71/12180.52	% SZS status Ended for HL404817+5.p
87585.34/12184.02	% SZS status Started for HL404818+5.p
87585.34/12184.02	% SZS status GaveUp for HL404818+5.p
87585.34/12184.02	% SZS status Ended for HL404818+5.p
87588.04/12184.38	% SZS status Started for HL404815+4.p
87588.04/12184.38	% SZS status GaveUp for HL404815+4.p
87588.04/12184.38	eprover: CPU time limit exceeded, terminating
87588.04/12184.38	% SZS status Ended for HL404815+4.p
87623.94/12188.88	% SZS status Started for HL404819+5.p
87623.94/12188.88	% SZS status GaveUp for HL404819+5.p
87623.94/12188.88	% SZS status Ended for HL404819+5.p
87625.69/12189.16	% SZS status Started for HL404816+4.p
87625.69/12189.16	% SZS status GaveUp for HL404816+4.p
87625.69/12189.16	eprover: CPU time limit exceeded, terminating
87625.69/12189.16	% SZS status Ended for HL404816+4.p
87658.71/12193.20	% SZS status Started for HL404817+4.p
87658.71/12193.20	% SZS status GaveUp for HL404817+4.p
87658.71/12193.20	eprover: CPU time limit exceeded, terminating
87658.71/12193.20	% SZS status Ended for HL404817+4.p
87659.05/12193.28	% SZS status Started for HL404820+5.p
87659.05/12193.28	% SZS status GaveUp for HL404820+5.p
87659.05/12193.28	% SZS status Ended for HL404820+5.p
87689.08/12197.04	% SZS status Started for HL404818+4.p
87689.08/12197.04	% SZS status GaveUp for HL404818+4.p
87689.08/12197.04	eprover: CPU time limit exceeded, terminating
87689.08/12197.04	% SZS status Ended for HL404818+4.p
87698.97/12198.33	% SZS status Started for HL404821+5.p
87698.97/12198.33	% SZS status GaveUp for HL404821+5.p
87698.97/12198.33	% SZS status Ended for HL404821+5.p
87723.95/12201.46	% SZS status Started for HL404819+4.p
87723.95/12201.46	% SZS status GaveUp for HL404819+4.p
87723.95/12201.46	eprover: CPU time limit exceeded, terminating
87723.95/12201.46	% SZS status Ended for HL404819+4.p
87758.66/12202.60	% SZS status Started for HL404822+5.p
87758.66/12202.60	% SZS status GaveUp for HL404822+5.p
87758.66/12202.60	% SZS status Ended for HL404822+5.p
87785.84/12206.19	% SZS status Started for HL404820+4.p
87785.84/12206.19	% SZS status GaveUp for HL404820+4.p
87785.84/12206.19	eprover: CPU time limit exceeded, terminating
87785.84/12206.19	% SZS status Ended for HL404820+4.p
87790.69/12206.72	% SZS status Started for HL404823+5.p
87790.69/12206.72	% SZS status GaveUp for HL404823+5.p
87790.69/12206.72	% SZS status Ended for HL404823+5.p
87808.80/12208.95	% SZS status Started for HL404824+4.p
87808.80/12208.95	% SZS status GaveUp for HL404824+4.p
87808.80/12208.95	eprover: CPU time limit exceeded, terminating
87808.80/12208.95	% SZS status Ended for HL404824+4.p
87816.73/12210.04	% SZS status Started for HL404821+4.p
87816.73/12210.04	% SZS status GaveUp for HL404821+4.p
87816.73/12210.04	eprover: CPU time limit exceeded, terminating
87816.73/12210.04	% SZS status Ended for HL404821+4.p
87828.05/12211.36	% SZS status Started for HL404824+5.p
87828.05/12211.36	% SZS status GaveUp for HL404824+5.p
87828.05/12211.36	% SZS status Ended for HL404824+5.p
87843.11/12213.30	% SZS status Started for HL404826+4.p
87843.11/12213.30	% SZS status GaveUp for HL404826+4.p
87843.11/12213.30	eprover: CPU time limit exceeded, terminating
87843.11/12213.30	% SZS status Ended for HL404826+4.p
87855.74/12214.89	% SZS status Started for HL404822+4.p
87855.74/12214.89	% SZS status GaveUp for HL404822+4.p
87855.74/12214.89	eprover: CPU time limit exceeded, terminating
87855.74/12214.89	% SZS status Ended for HL404822+4.p
87867.21/12216.33	% SZS status Started for HL404826+5.p
87867.21/12216.33	% SZS status GaveUp for HL404826+5.p
87867.21/12216.33	% SZS status Ended for HL404826+5.p
87874.48/12217.25	% SZS status Started for HL404827+4.p
87874.48/12217.25	% SZS status GaveUp for HL404827+4.p
87874.48/12217.25	eprover: CPU time limit exceeded, terminating
87874.48/12217.25	% SZS status Ended for HL404827+4.p
87887.02/12218.88	% SZS status Started for HL404827+5.p
87887.02/12218.88	% SZS status GaveUp for HL404827+5.p
87887.02/12218.88	% SZS status Ended for HL404827+5.p
87893.02/12219.56	% SZS status Started for HL404823+4.p
87893.02/12219.56	% SZS status GaveUp for HL404823+4.p
87893.02/12219.56	eprover: CPU time limit exceeded, terminating
87893.02/12219.56	% SZS status Ended for HL404823+4.p
87900.62/12220.53	% SZS status Started for HL404829+4.p
87900.62/12220.53	% SZS status GaveUp for HL404829+4.p
87900.62/12220.53	eprover: CPU time limit exceeded, terminating
87900.62/12220.53	% SZS status Ended for HL404829+4.p
87910.18/12221.76	% SZS status Started for HL404829+5.p
87910.18/12221.76	% SZS status GaveUp for HL404829+5.p
87910.18/12221.76	% SZS status Ended for HL404829+5.p
87926.05/12223.77	% SZS status Started for HL404830+4.p
87926.05/12223.77	% SZS status GaveUp for HL404830+4.p
87926.05/12223.77	eprover: CPU time limit exceeded, terminating
87926.05/12223.77	% SZS status Ended for HL404830+4.p
87931.86/12224.48	% SZS status Started for HL404830+5.p
87931.86/12224.48	% SZS status GaveUp for HL404830+5.p
87931.86/12224.48	% SZS status Ended for HL404830+5.p
87950.52/12226.79	% SZS status Started for HL404831+4.p
87950.52/12226.79	% SZS status GaveUp for HL404831+4.p
87950.52/12226.79	eprover: CPU time limit exceeded, terminating
87950.52/12226.79	% SZS status Ended for HL404831+4.p
87951.52/12226.92	% SZS status Started for HL404831+5.p
87951.52/12226.92	% SZS status GaveUp for HL404831+5.p
87951.52/12226.92	% SZS status Ended for HL404831+5.p
87969.88/12229.35	% SZS status Started for HL404832+4.p
87969.88/12229.35	% SZS status GaveUp for HL404832+4.p
87969.88/12229.35	eprover: CPU time limit exceeded, terminating
87969.88/12229.35	% SZS status Ended for HL404832+4.p
87970.41/12229.51	% SZS status Started for HL404832+5.p
87970.41/12229.51	% SZS status GaveUp for HL404832+5.p
87970.41/12229.51	% SZS status Ended for HL404832+5.p
87986.12/12231.28	% SZS status Started for HL404833+4.p
87986.12/12231.28	% SZS status GaveUp for HL404833+4.p
87986.12/12231.28	eprover: CPU time limit exceeded, terminating
87986.12/12231.28	% SZS status Ended for HL404833+4.p
87988.56/12231.63	% SZS status Started for HL404833+5.p
87988.56/12231.63	% SZS status GaveUp for HL404833+5.p
87988.56/12231.63	% SZS status Ended for HL404833+5.p
88006.84/12234.06	% SZS status Started for HL404834+5.p
88006.84/12234.06	% SZS status GaveUp for HL404834+5.p
88006.84/12234.06	% SZS status Ended for HL404834+5.p
88018.26/12234.23	% SZS status Started for HL404834+4.p
88018.26/12234.23	% SZS status GaveUp for HL404834+4.p
88018.26/12234.23	eprover: CPU time limit exceeded, terminating
88018.26/12234.23	% SZS status Ended for HL404834+4.p
88036.29/12236.46	% SZS status Started for HL404835+5.p
88036.29/12236.46	% SZS status GaveUp for HL404835+5.p
88036.29/12236.46	% SZS status Ended for HL404835+5.p
88042.45/12237.22	% SZS status Started for HL404835+4.p
88042.45/12237.22	% SZS status GaveUp for HL404835+4.p
88042.45/12237.22	eprover: CPU time limit exceeded, terminating
88042.45/12237.22	% SZS status Ended for HL404835+4.p
88060.41/12239.56	% SZS status Started for HL404836+5.p
88060.41/12239.56	% SZS status GaveUp for HL404836+5.p
88060.41/12239.56	% SZS status Ended for HL404836+5.p
88062.82/12239.76	% SZS status Started for HL404836+4.p
88062.82/12239.76	% SZS status GaveUp for HL404836+4.p
88062.82/12239.76	eprover: CPU time limit exceeded, terminating
88062.82/12239.76	% SZS status Ended for HL404836+4.p
88074.54/12241.29	% SZS status Started for HL404837+5.p
88074.54/12241.29	% SZS status GaveUp for HL404837+5.p
88074.54/12241.29	% SZS status Ended for HL404837+5.p
88078.01/12241.67	% SZS status Started for HL404837+4.p
88078.01/12241.67	% SZS status GaveUp for HL404837+4.p
88078.01/12241.67	eprover: CPU time limit exceeded, terminating
88078.01/12241.67	% SZS status Ended for HL404837+4.p
88096.99/12244.20	% SZS status Started for HL404838+5.p
88096.99/12244.20	% SZS status GaveUp for HL404838+5.p
88096.99/12244.20	% SZS status Ended for HL404838+5.p
88099.68/12244.45	% SZS status Started for HL404838+4.p
88099.68/12244.45	% SZS status GaveUp for HL404838+4.p
88099.68/12244.45	eprover: CPU time limit exceeded, terminating
88099.68/12244.45	% SZS status Ended for HL404838+4.p
88119.10/12246.91	% SZS status Started for HL404840+4.p
88119.10/12246.91	% SZS status GaveUp for HL404840+4.p
88119.10/12246.91	eprover: CPU time limit exceeded, terminating
88119.10/12246.91	% SZS status Ended for HL404840+4.p
88121.85/12247.29	% SZS status Started for HL404840+5.p
88121.85/12247.29	% SZS status GaveUp for HL404840+5.p
88121.85/12247.29	% SZS status Ended for HL404840+5.p
88143.12/12249.93	% SZS status Started for HL404841+5.p
88143.12/12249.93	% SZS status GaveUp for HL404841+5.p
88143.12/12249.93	% SZS status Ended for HL404841+5.p
88144.67/12250.15	% SZS status Started for HL404841+4.p
88144.67/12250.15	% SZS status GaveUp for HL404841+4.p
88144.67/12250.15	eprover: CPU time limit exceeded, terminating
88144.67/12250.15	% SZS status Ended for HL404841+4.p
88153.28/12251.26	% SZS status Started for HL404842+5.p
88153.28/12251.26	% SZS status GaveUp for HL404842+5.p
88153.28/12251.26	% SZS status Ended for HL404842+5.p
88159.70/12252.09	% SZS status Started for HL404842+4.p
88159.70/12252.09	% SZS status GaveUp for HL404842+4.p
88159.70/12252.09	eprover: CPU time limit exceeded, terminating
88159.70/12252.09	% SZS status Ended for HL404842+4.p
88177.66/12254.25	% SZS status Started for HL404843+5.p
88177.66/12254.25	% SZS status GaveUp for HL404843+5.p
88177.66/12254.25	% SZS status Ended for HL404843+5.p
88181.86/12254.79	% SZS status Started for HL404843+4.p
88181.86/12254.79	% SZS status GaveUp for HL404843+4.p
88181.86/12254.79	eprover: CPU time limit exceeded, terminating
88181.86/12254.79	% SZS status Ended for HL404843+4.p
88199.20/12256.98	% SZS status Started for HL404845+5.p
88199.20/12256.98	% SZS status GaveUp for HL404845+5.p
88199.20/12256.98	% SZS status Ended for HL404845+5.p
88203.67/12257.52	% SZS status Started for HL404845+4.p
88203.67/12257.52	% SZS status GaveUp for HL404845+4.p
88203.67/12257.52	eprover: CPU time limit exceeded, terminating
88203.67/12257.52	% SZS status Ended for HL404845+4.p
88224.00/12260.11	% SZS status Started for HL404846+5.p
88224.00/12260.11	% SZS status GaveUp for HL404846+5.p
88224.00/12260.11	% SZS status Ended for HL404846+5.p
88227.18/12260.56	% SZS status Started for HL404846+4.p
88227.18/12260.56	% SZS status GaveUp for HL404846+4.p
88227.18/12260.56	eprover: CPU time limit exceeded, terminating
88227.18/12260.56	% SZS status Ended for HL404846+4.p
88238.32/12261.86	% SZS status Started for HL404847+4.p
88238.32/12261.86	% SZS status GaveUp for HL404847+4.p
88238.32/12261.86	eprover: CPU time limit exceeded, terminating
88238.32/12261.86	% SZS status Ended for HL404847+4.p
88239.80/12262.10	% SZS status Started for HL404847+5.p
88239.80/12262.10	% SZS status GaveUp for HL404847+5.p
88239.80/12262.10	% SZS status Ended for HL404847+5.p
88261.70/12264.91	% SZS status Started for HL404848+4.p
88261.70/12264.91	% SZS status GaveUp for HL404848+4.p
88261.70/12264.91	eprover: CPU time limit exceeded, terminating
88261.70/12264.91	% SZS status Ended for HL404848+4.p
88265.46/12265.29	% SZS status Started for HL404848+5.p
88265.46/12265.29	% SZS status GaveUp for HL404848+5.p
88265.46/12265.29	% SZS status Ended for HL404848+5.p
88283.11/12267.52	% SZS status Started for HL404851+5.p
88283.11/12267.52	% SZS status GaveUp for HL404851+5.p
88283.11/12267.52	% SZS status Ended for HL404851+5.p
88283.46/12267.59	% SZS status Started for HL404851+4.p
88283.46/12267.59	% SZS status GaveUp for HL404851+4.p
88283.46/12267.59	eprover: CPU time limit exceeded, terminating
88283.46/12267.59	% SZS status Ended for HL404851+4.p
88306.73/12270.53	% SZS status Started for HL404852+5.p
88306.73/12270.53	% SZS status GaveUp for HL404852+5.p
88306.73/12270.53	% SZS status Ended for HL404852+5.p
88308.07/12270.74	% SZS status Started for HL404852+4.p
88308.07/12270.74	% SZS status GaveUp for HL404852+4.p
88308.07/12270.74	eprover: CPU time limit exceeded, terminating
88308.07/12270.74	% SZS status Ended for HL404852+4.p
88318.73/12272.08	% SZS status Started for HL404854+5.p
88318.73/12272.08	% SZS status GaveUp for HL404854+5.p
88318.73/12272.08	% SZS status Ended for HL404854+5.p
88322.57/12272.49	% SZS status Started for HL404854+4.p
88322.57/12272.49	% SZS status GaveUp for HL404854+4.p
88322.57/12272.49	eprover: CPU time limit exceeded, terminating
88322.57/12272.49	% SZS status Ended for HL404854+4.p
88343.55/12275.17	% SZS status Started for HL404855+5.p
88343.55/12275.17	% SZS status GaveUp for HL404855+5.p
88343.55/12275.17	% SZS status Ended for HL404855+5.p
88350.93/12276.06	% SZS status Started for HL404855+4.p
88350.93/12276.06	% SZS status GaveUp for HL404855+4.p
88350.93/12276.06	eprover: CPU time limit exceeded, terminating
88350.93/12276.06	% SZS status Ended for HL404855+4.p
88363.07/12277.57	% SZS status Started for HL404856+5.p
88363.07/12277.57	% SZS status GaveUp for HL404856+5.p
88363.07/12277.57	% SZS status Ended for HL404856+5.p
88364.87/12277.97	% SZS status Started for HL404856+4.p
88364.87/12277.97	% SZS status GaveUp for HL404856+4.p
88364.87/12277.97	eprover: CPU time limit exceeded, terminating
88364.87/12277.97	% SZS status Ended for HL404856+4.p
88383.86/12280.35	% SZS status Started for HL404857+5.p
88383.86/12280.35	% SZS status GaveUp for HL404857+5.p
88383.86/12280.35	% SZS status Ended for HL404857+5.p
88389.52/12280.94	% SZS status Started for HL404857+4.p
88389.52/12280.94	% SZS status GaveUp for HL404857+4.p
88389.52/12280.94	eprover: CPU time limit exceeded, terminating
88389.52/12280.94	% SZS status Ended for HL404857+4.p
88400.86/12282.39	% SZS status Started for HL404858+5.p
88400.86/12282.39	% SZS status GaveUp for HL404858+5.p
88400.86/12282.39	% SZS status Ended for HL404858+5.p
88401.84/12282.53	% SZS status Started for HL404858+4.p
88401.84/12282.53	% SZS status GaveUp for HL404858+4.p
88401.84/12282.53	eprover: CPU time limit exceeded, terminating
88401.84/12282.53	% SZS status Ended for HL404858+4.p
88428.09/12285.76	% SZS status Started for HL404859+5.p
88428.09/12285.76	% SZS status GaveUp for HL404859+5.p
88428.09/12285.76	% SZS status Ended for HL404859+5.p
88429.38/12285.98	% SZS status Started for HL404859+4.p
88429.38/12285.98	% SZS status GaveUp for HL404859+4.p
88429.38/12285.98	eprover: CPU time limit exceeded, terminating
88429.38/12285.98	% SZS status Ended for HL404859+4.p
88447.60/12288.19	% SZS status Started for HL404860+4.p
88447.60/12288.19	% SZS status GaveUp for HL404860+4.p
88447.60/12288.19	eprover: CPU time limit exceeded, terminating
88447.60/12288.19	% SZS status Ended for HL404860+4.p
88448.48/12288.37	% SZS status Started for HL404860+5.p
88448.48/12288.37	% SZS status GaveUp for HL404860+5.p
88448.48/12288.37	% SZS status Ended for HL404860+5.p
88466.75/12290.67	% SZS status Started for HL404861+5.p
88466.75/12290.67	% SZS status GaveUp for HL404861+5.p
88466.75/12290.67	% SZS status Ended for HL404861+5.p
88471.53/12291.25	% SZS status Started for HL404861+4.p
88471.53/12291.25	% SZS status GaveUp for HL404861+4.p
88471.53/12291.25	eprover: CPU time limit exceeded, terminating
88471.53/12291.25	% SZS status Ended for HL404861+4.p
88480.55/12292.48	% SZS status Started for HL404862+5.p
88480.55/12292.48	% SZS status GaveUp for HL404862+5.p
88480.55/12292.48	% SZS status Ended for HL404862+5.p
88487.91/12293.30	% SZS status Started for HL404862+4.p
88487.91/12293.30	% SZS status GaveUp for HL404862+4.p
88487.91/12293.30	eprover: CPU time limit exceeded, terminating
88487.91/12293.30	% SZS status Ended for HL404862+4.p
88507.43/12295.76	% SZS status Started for HL404863+5.p
88507.43/12295.76	% SZS status GaveUp for HL404863+5.p
88507.43/12295.76	% SZS status Ended for HL404863+5.p
88508.23/12295.88	% SZS status Started for HL404865+5.p
88508.23/12295.88	% SZS status Theorem for HL404865+5.p
88508.23/12295.88	% SZS status Ended for HL404865+5.p
88512.23/12296.40	% SZS status Started for HL404863+4.p
88512.23/12296.40	% SZS status GaveUp for HL404863+4.p
88512.23/12296.40	eprover: CPU time limit exceeded, terminating
88512.23/12296.40	% SZS status Ended for HL404863+4.p
88533.16/12298.96	% SZS status Started for HL404866+5.p
88533.16/12298.96	% SZS status Theorem for HL404866+5.p
88533.16/12298.96	% SZS status Ended for HL404866+5.p
88536.70/12299.43	% SZS status Started for HL404865+4.p
88536.70/12299.43	% SZS status GaveUp for HL404865+4.p
88536.70/12299.43	eprover: CPU time limit exceeded, terminating
88536.70/12299.43	% SZS status Ended for HL404865+4.p
88546.14/12300.66	% SZS status Started for HL404867+5.p
88546.14/12300.66	% SZS status Theorem for HL404867+5.p
88546.14/12300.66	% SZS status Ended for HL404867+5.p
88553.88/12301.56	% SZS status Started for HL404866+4.p
88553.88/12301.56	% SZS status GaveUp for HL404866+4.p
88553.88/12301.56	eprover: CPU time limit exceeded, terminating
88553.88/12301.56	% SZS status Ended for HL404866+4.p
88565.55/12303.10	% SZS status Started for HL404869+5.p
88565.55/12303.10	% SZS status Theorem for HL404869+5.p
88565.55/12303.10	% SZS status Ended for HL404869+5.p
88567.59/12303.38	% SZS status Started for HL404867+4.p
88567.59/12303.38	% SZS status GaveUp for HL404867+4.p
88567.59/12303.38	eprover: CPU time limit exceeded, terminating
88567.59/12303.38	% SZS status Ended for HL404867+4.p
88580.88/12305.01	% SZS status Started for HL404872+5.p
88580.88/12305.01	% SZS status Theorem for HL404872+5.p
88580.88/12305.01	% SZS status Ended for HL404872+5.p
88593.39/12306.59	% SZS status Started for HL404870+5.p
88593.39/12306.59	% SZS status Theorem for HL404870+5.p
88593.39/12306.59	% SZS status Ended for HL404870+5.p
88594.12/12306.64	% SZS status Started for HL404869+4.p
88594.12/12306.64	% SZS status GaveUp for HL404869+4.p
88594.12/12306.64	eprover: CPU time limit exceeded, terminating
88594.12/12306.64	% SZS status Ended for HL404869+4.p
88596.05/12307.06	% SZS status Started for HL404870+4.p
88596.05/12307.06	% SZS status GaveUp for HL404870+4.p
88596.05/12307.06	eprover: CPU time limit exceeded, terminating
88596.05/12307.06	% SZS status Ended for HL404870+4.p
88621.85/12310.13	% SZS status Started for HL404871+4.p
88621.85/12310.13	% SZS status GaveUp for HL404871+4.p
88621.85/12310.13	eprover: CPU time limit exceeded, terminating
88621.85/12310.13	% SZS status Ended for HL404871+4.p
88625.65/12310.62	% SZS status Started for HL404871+5.p
88625.65/12310.62	% SZS status GaveUp for HL404871+5.p
88625.65/12310.62	% SZS status Ended for HL404871+5.p
88638.92/12312.34	% SZS status Started for HL404873+5.p
88638.92/12312.34	% SZS status Theorem for HL404873+5.p
88638.92/12312.34	% SZS status Ended for HL404873+5.p
88641.16/12312.67	% SZS status Started for HL404872+4.p
88641.16/12312.67	% SZS status GaveUp for HL404872+4.p
88641.16/12312.67	eprover: CPU time limit exceeded, terminating
88641.16/12312.67	% SZS status Ended for HL404872+4.p
88653.81/12314.21	% SZS status Started for HL404873+4.p
88653.81/12314.21	% SZS status GaveUp for HL404873+4.p
88653.81/12314.21	eprover: CPU time limit exceeded, terminating
88653.81/12314.21	% SZS status Ended for HL404873+4.p
88674.55/12316.88	% SZS status Started for HL404874+5.p
88674.55/12316.88	% SZS status GaveUp for HL404874+5.p
88674.55/12316.88	% SZS status Ended for HL404874+5.p
88679.48/12317.48	% SZS status Started for HL404874+4.p
88679.48/12317.48	% SZS status GaveUp for HL404874+4.p
88679.48/12317.48	eprover: CPU time limit exceeded, terminating
88679.48/12317.48	% SZS status Ended for HL404874+4.p
88683.56/12317.94	% SZS status Started for HL404875+4.p
88683.56/12317.94	% SZS status GaveUp for HL404875+4.p
88683.56/12317.94	eprover: CPU time limit exceeded, terminating
88683.56/12317.94	% SZS status Ended for HL404875+4.p
88698.35/12319.96	% SZS status Started for HL404875+5.p
88698.35/12319.96	% SZS status GaveUp for HL404875+5.p
88698.35/12319.96	% SZS status Ended for HL404875+5.p
88712.27/12321.54	% SZS status Started for HL404876+4.p
88712.27/12321.54	% SZS status GaveUp for HL404876+4.p
88712.27/12321.54	eprover: CPU time limit exceeded, terminating
88712.27/12321.54	% SZS status Ended for HL404876+4.p
88716.91/12322.12	% SZS status Started for HL404876+5.p
88716.91/12322.12	% SZS status GaveUp for HL404876+5.p
88716.91/12322.12	% SZS status Ended for HL404876+5.p
88725.38/12323.22	% SZS status Started for HL404877+4.p
88725.38/12323.22	% SZS status GaveUp for HL404877+4.p
88725.38/12323.22	eprover: CPU time limit exceeded, terminating
88725.38/12323.22	% SZS status Ended for HL404877+4.p
88733.03/12324.12	% SZS status Started for HL404877+5.p
88733.03/12324.12	% SZS status GaveUp for HL404877+5.p
88733.03/12324.12	% SZS status Ended for HL404877+5.p
88754.57/12326.82	% SZS status Started for HL404878+5.p
88754.57/12326.82	% SZS status GaveUp for HL404878+5.p
88754.57/12326.82	% SZS status Ended for HL404878+5.p
88772.36/12329.07	% SZS status Started for HL404879+5.p
88772.36/12329.07	% SZS status GaveUp for HL404879+5.p
88772.36/12329.07	% SZS status Ended for HL404879+5.p
88789.23/12331.21	% SZS status Started for HL404881+5.p
88789.23/12331.21	% SZS status GaveUp for HL404881+5.p
88789.23/12331.21	% SZS status Ended for HL404881+5.p
88805.45/12333.25	% SZS status Started for HL404882+5.p
88805.45/12333.25	% SZS status GaveUp for HL404882+5.p
88805.45/12333.25	% SZS status Ended for HL404882+5.p
88845.53/12338.27	% SZS status Started for HL404883+5.p
88845.53/12338.27	% SZS status GaveUp for HL404883+5.p
88845.53/12338.27	% SZS status Ended for HL404883+5.p
88879.34/12342.51	% SZS status Started for HL404884+5.p
88879.34/12342.51	% SZS status GaveUp for HL404884+5.p
88879.34/12342.51	% SZS status Ended for HL404884+5.p
88879.88/12342.61	% SZS status Started for HL404878+4.p
88879.88/12342.61	% SZS status GaveUp for HL404878+4.p
88879.88/12342.61	eprover: CPU time limit exceeded, terminating
88879.88/12342.61	% SZS status Ended for HL404878+4.p
88888.66/12343.69	% SZS status Started for HL404879+4.p
88888.66/12343.69	% SZS status GaveUp for HL404879+4.p
88888.66/12343.69	eprover: CPU time limit exceeded, terminating
88888.66/12343.69	% SZS status Ended for HL404879+4.p
88919.98/12347.60	% SZS status Started for HL404881+4.p
88919.98/12347.60	% SZS status GaveUp for HL404881+4.p
88919.98/12347.60	eprover: CPU time limit exceeded, terminating
88919.98/12347.60	% SZS status Ended for HL404881+4.p
88930.66/12348.95	% SZS status Started for HL404882+4.p
88930.66/12348.95	% SZS status GaveUp for HL404882+4.p
88930.66/12348.95	eprover: CPU time limit exceeded, terminating
88930.66/12348.95	% SZS status Ended for HL404882+4.p
88951.30/12351.63	% SZS status Started for HL404885+5.p
88951.30/12351.63	% SZS status GaveUp for HL404885+5.p
88951.30/12351.63	% SZS status Ended for HL404885+5.p
88958.69/12352.54	% SZS status Started for HL404883+4.p
88958.69/12352.54	% SZS status GaveUp for HL404883+4.p
88958.69/12352.54	eprover: CPU time limit exceeded, terminating
88958.69/12352.54	% SZS status Ended for HL404883+4.p
88961.19/12352.82	% SZS status Started for HL404886+5.p
88961.19/12352.82	% SZS status GaveUp for HL404886+5.p
88961.19/12352.82	% SZS status Ended for HL404886+5.p
88961.98/12352.88	% SZS status Started for HL404886+4.p
88961.98/12352.88	% SZS status GaveUp for HL404886+4.p
88961.98/12352.88	eprover: CPU time limit exceeded, terminating
88961.98/12352.88	% SZS status Ended for HL404886+4.p
88995.80/12357.18	% SZS status Started for HL404884+4.p
88995.80/12357.18	% SZS status GaveUp for HL404884+4.p
88995.80/12357.18	eprover: CPU time limit exceeded, terminating
88995.80/12357.18	% SZS status Ended for HL404884+4.p
89003.84/12358.23	% SZS status Started for HL404887+5.p
89003.84/12358.23	% SZS status GaveUp for HL404887+5.p
89003.84/12358.23	% SZS status Ended for HL404887+5.p
89031.92/12361.72	% SZS status Started for HL404888+5.p
89031.92/12361.72	% SZS status GaveUp for HL404888+5.p
89031.92/12361.72	% SZS status Ended for HL404888+5.p
89033.88/12362.04	% SZS status Started for HL404889+5.p
89033.88/12362.04	% SZS status GaveUp for HL404889+5.p
89033.88/12362.04	% SZS status Ended for HL404889+5.p
89044.33/12363.28	% SZS status Started for HL404889+4.p
89044.33/12363.28	% SZS status GaveUp for HL404889+4.p
89044.33/12363.28	eprover: CPU time limit exceeded, terminating
89044.33/12363.28	% SZS status Ended for HL404889+4.p
89049.70/12364.02	% SZS status Started for HL404885+4.p
89049.70/12364.02	% SZS status GaveUp for HL404885+4.p
89049.70/12364.02	eprover: CPU time limit exceeded, terminating
89049.70/12364.02	% SZS status Ended for HL404885+4.p
89076.51/12367.33	% SZS status Started for HL404890+5.p
89076.51/12367.33	% SZS status GaveUp for HL404890+5.p
89076.51/12367.33	% SZS status Ended for HL404890+5.p
89110.30/12371.43	% SZS status Started for HL404891+5.p
89110.30/12371.43	% SZS status GaveUp for HL404891+5.p
89110.30/12371.43	% SZS status Ended for HL404891+5.p
89124.27/12373.20	% SZS status Started for HL404892+5.p
89124.27/12373.20	% SZS status GaveUp for HL404892+5.p
89124.27/12373.20	% SZS status Ended for HL404892+5.p
89125.77/12373.41	% SZS status Started for HL404887+4.p
89125.77/12373.41	% SZS status GaveUp for HL404887+4.p
89125.77/12373.41	eprover: CPU time limit exceeded, terminating
89125.77/12373.41	% SZS status Ended for HL404887+4.p
89157.30/12377.40	% SZS status Started for HL404888+4.p
89157.30/12377.40	% SZS status GaveUp for HL404888+4.p
89157.30/12377.40	eprover: CPU time limit exceeded, terminating
89157.30/12377.40	% SZS status Ended for HL404888+4.p
89182.77/12380.59	% SZS status Started for HL404893+5.p
89182.77/12380.59	% SZS status GaveUp for HL404893+5.p
89182.77/12380.59	% SZS status Ended for HL404893+5.p
89199.25/12382.62	% SZS status Started for HL404894+5.p
89199.25/12382.62	% SZS status GaveUp for HL404894+5.p
89199.25/12382.62	% SZS status Ended for HL404894+5.p
89203.35/12383.12	% SZS status Started for HL404890+4.p
89203.35/12383.12	% SZS status GaveUp for HL404890+4.p
89203.35/12383.12	eprover: CPU time limit exceeded, terminating
89203.35/12383.12	% SZS status Ended for HL404890+4.p
89239.09/12387.74	% SZS status Started for HL404891+4.p
89239.09/12387.74	% SZS status GaveUp for HL404891+4.p
89239.09/12387.74	eprover: CPU time limit exceeded, terminating
89239.09/12387.74	% SZS status Ended for HL404891+4.p
89250.97/12389.19	% SZS status Started for HL404892+4.p
89250.97/12389.19	% SZS status GaveUp for HL404892+4.p
89250.97/12389.19	eprover: CPU time limit exceeded, terminating
89250.97/12389.19	% SZS status Ended for HL404892+4.p
89256.38/12389.86	% SZS status Started for HL404895+5.p
89256.38/12389.86	% SZS status GaveUp for HL404895+5.p
89256.38/12389.86	% SZS status Ended for HL404895+5.p
89276.48/12392.40	% SZS status Started for HL404896+5.p
89276.48/12392.40	% SZS status GaveUp for HL404896+5.p
89276.48/12392.40	% SZS status Ended for HL404896+5.p
89283.50/12393.22	% SZS status Started for HL404893+4.p
89283.50/12393.22	% SZS status GaveUp for HL404893+4.p
89283.50/12393.22	eprover: CPU time limit exceeded, terminating
89283.50/12393.22	% SZS status Ended for HL404893+4.p
89326.32/12398.61	% SZS status Started for HL404898+5.p
89326.32/12398.61	% SZS status GaveUp for HL404898+5.p
89326.32/12398.61	% SZS status Ended for HL404898+5.p
89328.27/12398.98	% SZS status Started for HL404894+4.p
89328.27/12398.98	% SZS status GaveUp for HL404894+4.p
89328.27/12398.98	eprover: CPU time limit exceeded, terminating
89328.27/12398.98	% SZS status Ended for HL404894+4.p
89353.51/12402.00	% SZS status Started for HL404899+5.p
89353.51/12402.00	% SZS status GaveUp for HL404899+5.p
89353.51/12402.00	% SZS status Ended for HL404899+5.p
89362.06/12403.19	% SZS status Started for HL404895+4.p
89362.06/12403.19	% SZS status GaveUp for HL404895+4.p
89362.06/12403.19	eprover: CPU time limit exceeded, terminating
89362.06/12403.19	% SZS status Ended for HL404895+4.p
89400.84/12407.98	% SZS status Started for HL404900+5.p
89400.84/12407.98	% SZS status GaveUp for HL404900+5.p
89400.84/12407.98	% SZS status Ended for HL404900+5.p
89405.89/12408.60	% SZS status Started for HL404896+4.p
89405.89/12408.60	% SZS status GaveUp for HL404896+4.p
89405.89/12408.60	eprover: CPU time limit exceeded, terminating
89405.89/12408.60	% SZS status Ended for HL404896+4.p
89428.27/12411.49	% SZS status Started for HL404901+5.p
89428.27/12411.49	% SZS status GaveUp for HL404901+5.p
89428.27/12411.49	% SZS status Ended for HL404901+5.p
89445.78/12413.68	% SZS status Started for HL404898+4.p
89445.78/12413.68	% SZS status GaveUp for HL404898+4.p
89445.78/12413.68	eprover: CPU time limit exceeded, terminating
89445.78/12413.68	% SZS status Ended for HL404898+4.p
89461.23/12415.64	% SZS status Started for HL404899+4.p
89461.23/12415.64	% SZS status GaveUp for HL404899+4.p
89461.23/12415.64	eprover: CPU time limit exceeded, terminating
89461.23/12415.64	% SZS status Ended for HL404899+4.p
89476.67/12417.49	% SZS status Started for HL404902+5.p
89476.67/12417.49	% SZS status GaveUp for HL404902+5.p
89476.67/12417.49	% SZS status Ended for HL404902+5.p
89488.22/12419.03	% SZS status Started for HL404900+4.p
89488.22/12419.03	% SZS status GaveUp for HL404900+4.p
89488.22/12419.03	eprover: CPU time limit exceeded, terminating
89488.22/12419.03	% SZS status Ended for HL404900+4.p
89503.62/12420.88	% SZS status Started for HL404903+5.p
89503.62/12420.88	% SZS status GaveUp for HL404903+5.p
89503.62/12420.88	% SZS status Ended for HL404903+5.p
89532.98/12424.69	% SZS status Started for HL404901+4.p
89532.98/12424.69	% SZS status GaveUp for HL404901+4.p
89532.98/12424.69	eprover: CPU time limit exceeded, terminating
89532.98/12424.69	% SZS status Ended for HL404901+4.p
89538.72/12425.40	% SZS status Started for HL404904+5.p
89538.72/12425.40	% SZS status GaveUp for HL404904+5.p
89538.72/12425.40	% SZS status Ended for HL404904+5.p
89565.30/12428.70	% SZS status Started for HL404905+5.p
89565.30/12428.70	% SZS status GaveUp for HL404905+5.p
89565.30/12428.70	% SZS status Ended for HL404905+5.p
89566.37/12428.95	% SZS status Started for HL404902+4.p
89566.37/12428.95	% SZS status GaveUp for HL404902+4.p
89566.37/12428.95	eprover: CPU time limit exceeded, terminating
89566.37/12428.95	% SZS status Ended for HL404902+4.p
89608.35/12434.11	% SZS status Started for HL404906+5.p
89608.35/12434.11	% SZS status GaveUp for HL404906+5.p
89608.35/12434.11	% SZS status Ended for HL404906+5.p
89610.02/12434.31	% SZS status Started for HL404903+4.p
89610.02/12434.31	% SZS status GaveUp for HL404903+4.p
89610.02/12434.31	eprover: CPU time limit exceeded, terminating
89610.02/12434.31	% SZS status Ended for HL404903+4.p
89640.38/12438.17	% SZS status Started for HL404907+5.p
89640.38/12438.17	% SZS status GaveUp for HL404907+5.p
89640.38/12438.17	% SZS status Ended for HL404907+5.p
89650.95/12439.55	% SZS status Started for HL404904+4.p
89650.95/12439.55	% SZS status GaveUp for HL404904+4.p
89650.95/12439.55	eprover: CPU time limit exceeded, terminating
89650.95/12439.55	% SZS status Ended for HL404904+4.p
89681.25/12443.31	% SZS status Started for HL404908+5.p
89681.25/12443.31	% SZS status GaveUp for HL404908+5.p
89681.25/12443.31	% SZS status Ended for HL404908+5.p
89682.27/12443.40	% SZS status Started for HL404905+4.p
89682.27/12443.40	% SZS status GaveUp for HL404905+4.p
89682.27/12443.40	eprover: CPU time limit exceeded, terminating
89682.27/12443.40	% SZS status Ended for HL404905+4.p
89710.42/12446.98	% SZS status Started for HL404906+4.p
89710.42/12446.98	% SZS status GaveUp for HL404906+4.p
89710.42/12446.98	eprover: CPU time limit exceeded, terminating
89710.42/12446.98	% SZS status Ended for HL404906+4.p
89715.02/12447.62	% SZS status Started for HL404909+5.p
89715.02/12447.62	% SZS status GaveUp for HL404909+5.p
89715.02/12447.62	% SZS status Ended for HL404909+5.p
89745.80/12451.49	% SZS status Started for HL404907+4.p
89745.80/12451.49	% SZS status GaveUp for HL404907+4.p
89745.80/12451.49	eprover: CPU time limit exceeded, terminating
89745.80/12451.49	% SZS status Ended for HL404907+4.p
89755.30/12452.67	% SZS status Started for HL404910+5.p
89755.30/12452.67	% SZS status GaveUp for HL404910+5.p
89755.30/12452.67	% SZS status Ended for HL404910+5.p
89773.14/12454.88	% SZS status Started for HL404908+4.p
89773.14/12454.88	% SZS status GaveUp for HL404908+4.p
89773.14/12454.88	eprover: CPU time limit exceeded, terminating
89773.14/12454.88	% SZS status Ended for HL404908+4.p
89785.00/12456.38	% SZS status Started for HL404911+5.p
89785.00/12456.38	% SZS status GaveUp for HL404911+5.p
89785.00/12456.38	% SZS status Ended for HL404911+5.p
89816.78/12460.34	% SZS status Started for HL404909+4.p
89816.78/12460.34	% SZS status GaveUp for HL404909+4.p
89816.78/12460.34	eprover: CPU time limit exceeded, terminating
89816.78/12460.34	% SZS status Ended for HL404909+4.p
89819.34/12460.69	% SZS status Started for HL404912+5.p
89819.34/12460.69	% SZS status GaveUp for HL404912+5.p
89819.34/12460.69	% SZS status Ended for HL404912+5.p
89846.98/12464.13	% SZS status Started for HL404913+5.p
89846.98/12464.13	% SZS status GaveUp for HL404913+5.p
89846.98/12464.13	% SZS status Ended for HL404913+5.p
89856.02/12465.28	% SZS status Started for HL404910+4.p
89856.02/12465.28	% SZS status GaveUp for HL404910+4.p
89856.02/12465.28	eprover: CPU time limit exceeded, terminating
89856.02/12465.28	% SZS status Ended for HL404910+4.p
89887.16/12469.21	% SZS status Started for HL404911+4.p
89887.16/12469.21	% SZS status GaveUp for HL404911+4.p
89887.16/12469.21	eprover: CPU time limit exceeded, terminating
89887.16/12469.21	% SZS status Ended for HL404911+4.p
89889.48/12469.48	% SZS status Started for HL404915+5.p
89889.48/12469.48	% SZS status GaveUp for HL404915+5.p
89889.48/12469.48	% SZS status Ended for HL404915+5.p
89901.48/12471.01	% SZS status Started for HL404917+5.p
89901.48/12471.01	% SZS status Theorem for HL404917+5.p
89901.48/12471.01	% SZS status Ended for HL404917+5.p
89922.88/12473.64	% SZS status Started for HL404916+5.p
89922.88/12473.64	% SZS status GaveUp for HL404916+5.p
89922.88/12473.64	% SZS status Ended for HL404916+5.p
89923.44/12473.75	% SZS status Started for HL404912+4.p
89923.44/12473.75	% SZS status GaveUp for HL404912+4.p
89923.44/12473.75	eprover: CPU time limit exceeded, terminating
89923.44/12473.75	% SZS status Ended for HL404912+4.p
89962.62/12478.68	% SZS status Started for HL404913+4.p
89962.62/12478.68	% SZS status GaveUp for HL404913+4.p
89962.62/12478.68	eprover: CPU time limit exceeded, terminating
89962.62/12478.68	% SZS status Ended for HL404913+4.p
89977.46/12480.58	% SZS status Started for HL404920+5.p
89977.46/12480.58	% SZS status GaveUp for HL404920+5.p
89977.46/12480.58	% SZS status Ended for HL404920+5.p
89991.75/12482.33	% SZS status Started for HL404915+4.p
89991.75/12482.33	% SZS status GaveUp for HL404915+4.p
89991.75/12482.33	eprover: CPU time limit exceeded, terminating
89991.75/12482.33	% SZS status Ended for HL404915+4.p
89996.48/12482.98	% SZS status Started for HL404921+5.p
89996.48/12482.98	% SZS status GaveUp for HL404921+5.p
89996.48/12482.98	% SZS status Ended for HL404921+5.p
90026.06/12486.63	% SZS status Started for HL404916+4.p
90026.06/12486.63	% SZS status GaveUp for HL404916+4.p
90026.06/12486.63	eprover: CPU time limit exceeded, terminating
90026.06/12486.63	% SZS status Ended for HL404916+4.p
90052.90/12490.01	% SZS status Started for HL404922+5.p
90052.90/12490.01	% SZS status GaveUp for HL404922+5.p
90052.90/12490.01	% SZS status Ended for HL404922+5.p
90063.16/12491.30	% SZS status Started for HL404917+4.p
90063.16/12491.30	% SZS status GaveUp for HL404917+4.p
90063.16/12491.30	eprover: CPU time limit exceeded, terminating
90063.16/12491.30	% SZS status Ended for HL404917+4.p
90072.01/12492.44	% SZS status Started for HL404923+5.p
90072.01/12492.44	% SZS status GaveUp for HL404923+5.p
90072.01/12492.44	% SZS status Ended for HL404923+5.p
90095.59/12495.40	% SZS status Started for HL404920+4.p
90095.59/12495.40	% SZS status GaveUp for HL404920+4.p
90095.59/12495.40	eprover: CPU time limit exceeded, terminating
90095.59/12495.40	% SZS status Ended for HL404920+4.p
90106.80/12496.86	% SZS status Started for HL404924+4.p
90106.80/12496.86	% SZS status GaveUp for HL404924+4.p
90106.80/12496.86	eprover: CPU time limit exceeded, terminating
90106.80/12496.86	% SZS status Ended for HL404924+4.p
90127.70/12499.50	% SZS status Started for HL404924+5.p
90127.70/12499.50	% SZS status GaveUp for HL404924+5.p
90127.70/12499.50	% SZS status Ended for HL404924+5.p
90130.47/12499.80	% SZS status Started for HL404921+4.p
90130.47/12499.80	% SZS status GaveUp for HL404921+4.p
90130.47/12499.80	eprover: CPU time limit exceeded, terminating
90130.47/12499.80	% SZS status Ended for HL404921+4.p
90148.18/12502.02	% SZS status Started for HL404925+5.p
90148.18/12502.02	% SZS status GaveUp for HL404925+5.p
90148.18/12502.02	% SZS status Ended for HL404925+5.p
90172.01/12504.99	% SZS status Started for HL404922+4.p
90172.01/12504.99	% SZS status GaveUp for HL404922+4.p
90172.01/12504.99	eprover: CPU time limit exceeded, terminating
90172.01/12504.99	% SZS status Ended for HL404922+4.p
90179.91/12506.01	% SZS status Started for HL404926+5.p
90179.91/12506.01	% SZS status GaveUp for HL404926+5.p
90179.91/12506.01	% SZS status Ended for HL404926+5.p
90197.38/12508.24	% SZS status Started for HL404923+4.p
90197.38/12508.24	% SZS status GaveUp for HL404923+4.p
90197.38/12508.24	eprover: CPU time limit exceeded, terminating
90197.38/12508.24	% SZS status Ended for HL404923+4.p
90205.48/12509.21	% SZS status Started for HL404927+5.p
90205.48/12509.21	% SZS status GaveUp for HL404927+5.p
90205.48/12509.21	% SZS status Ended for HL404927+5.p
90246.75/12514.42	% SZS status Started for HL404928+5.p
90246.75/12514.42	% SZS status GaveUp for HL404928+5.p
90246.75/12514.42	% SZS status Ended for HL404928+5.p
90270.64/12517.41	% SZS status Started for HL404925+4.p
90270.64/12517.41	% SZS status GaveUp for HL404925+4.p
90270.64/12517.41	eprover: CPU time limit exceeded, terminating
90270.64/12517.41	% SZS status Ended for HL404925+4.p
90271.91/12517.59	% SZS status Started for HL404929+5.p
90271.91/12517.59	% SZS status GaveUp for HL404929+5.p
90271.91/12517.59	% SZS status Ended for HL404929+5.p
90302.51/12521.45	% SZS status Started for HL404926+4.p
90302.51/12521.45	% SZS status GaveUp for HL404926+4.p
90302.51/12521.45	eprover: CPU time limit exceeded, terminating
90302.51/12521.45	% SZS status Ended for HL404926+4.p
90320.74/12523.72	% SZS status Started for HL404930+5.p
90320.74/12523.72	% SZS status GaveUp for HL404930+5.p
90320.74/12523.72	% SZS status Ended for HL404930+5.p
90323.62/12524.10	% SZS status Started for HL404931+5.p
90323.62/12524.10	% SZS status Theorem for HL404931+5.p
90323.62/12524.10	% SZS status Ended for HL404931+5.p
90335.20/12525.57	% SZS status Started for HL404927+4.p
90335.20/12525.57	% SZS status GaveUp for HL404927+4.p
90335.20/12525.57	eprover: CPU time limit exceeded, terminating
90335.20/12525.57	% SZS status Ended for HL404927+4.p
90355.55/12528.11	% SZS status Started for HL404928+4.p
90355.55/12528.11	% SZS status GaveUp for HL404928+4.p
90355.55/12528.11	eprover: CPU time limit exceeded, terminating
90355.55/12528.11	% SZS status Ended for HL404928+4.p
90386.66/12532.03	% SZS status Started for HL404929+4.p
90386.66/12532.03	% SZS status GaveUp for HL404929+4.p
90386.66/12532.03	eprover: CPU time limit exceeded, terminating
90386.66/12532.03	% SZS status Ended for HL404929+4.p
90394.29/12532.92	% SZS status Started for HL404932+5.p
90394.29/12532.92	% SZS status GaveUp for HL404932+5.p
90394.29/12532.92	% SZS status Ended for HL404932+5.p
90408.06/12534.74	% SZS status Started for HL404933+5.p
90408.06/12534.74	% SZS status GaveUp for HL404933+5.p
90408.06/12534.74	% SZS status Ended for HL404933+5.p
90411.74/12535.15	% SZS status Started for HL404930+4.p
90411.74/12535.15	% SZS status GaveUp for HL404930+4.p
90411.74/12535.15	eprover: CPU time limit exceeded, terminating
90411.74/12535.15	% SZS status Ended for HL404930+4.p
90461.12/12541.36	% SZS status Started for HL404934+5.p
90461.12/12541.36	% SZS status GaveUp for HL404934+5.p
90461.12/12541.36	% SZS status Ended for HL404934+5.p
90477.15/12543.36	% SZS status Started for HL404931+4.p
90477.15/12543.36	% SZS status GaveUp for HL404931+4.p
90477.15/12543.36	eprover: CPU time limit exceeded, terminating
90477.15/12543.36	% SZS status Ended for HL404931+4.p
90481.12/12543.83	% SZS status Started for HL404935+5.p
90481.12/12543.83	% SZS status GaveUp for HL404935+5.p
90481.12/12543.83	% SZS status Ended for HL404935+5.p
90509.36/12547.41	% SZS status Started for HL404932+4.p
90509.36/12547.41	% SZS status GaveUp for HL404932+4.p
90509.36/12547.41	eprover: CPU time limit exceeded, terminating
90509.36/12547.41	% SZS status Ended for HL404932+4.p
90531.73/12550.30	% SZS status Started for HL404933+4.p
90531.73/12550.30	% SZS status GaveUp for HL404933+4.p
90531.73/12550.30	eprover: CPU time limit exceeded, terminating
90531.73/12550.30	% SZS status Ended for HL404933+4.p
90534.41/12550.55	% SZS status Started for HL404936+5.p
90534.41/12550.55	% SZS status GaveUp for HL404936+5.p
90534.41/12550.55	% SZS status Ended for HL404936+5.p
90553.95/12552.99	% SZS status Started for HL404937+5.p
90553.95/12552.99	% SZS status GaveUp for HL404937+5.p
90553.95/12552.99	% SZS status Ended for HL404937+5.p
90561.97/12554.02	% SZS status Started for HL404934+4.p
90561.97/12554.02	% SZS status GaveUp for HL404934+4.p
90561.97/12554.02	eprover: CPU time limit exceeded, terminating
90561.97/12554.02	% SZS status Ended for HL404934+4.p
90601.11/12558.98	% SZS status Started for HL404935+4.p
90601.11/12558.98	% SZS status GaveUp for HL404935+4.p
90601.11/12558.98	eprover: CPU time limit exceeded, terminating
90601.11/12558.98	% SZS status Ended for HL404935+4.p
90601.58/12559.03	% SZS status Started for HL404939+5.p
90601.58/12559.03	% SZS status Theorem for HL404939+5.p
90601.58/12559.03	% SZS status Ended for HL404939+5.p
90605.27/12559.48	% SZS status Started for HL404938+5.p
90605.27/12559.48	% SZS status GaveUp for HL404938+5.p
90605.27/12559.48	% SZS status Ended for HL404938+5.p
90618.06/12561.12	% SZS status Started for HL404936+4.p
90618.06/12561.12	% SZS status GaveUp for HL404936+4.p
90618.06/12561.12	eprover: CPU time limit exceeded, terminating
90618.06/12561.12	% SZS status Ended for HL404936+4.p
90674.12/12568.16	% SZS status Started for HL404940+5.p
90674.12/12568.16	% SZS status GaveUp for HL404940+5.p
90674.12/12568.16	% SZS status Ended for HL404940+5.p
90676.72/12568.58	% SZS status Started for HL404941+5.p
90676.72/12568.58	% SZS status GaveUp for HL404941+5.p
90676.72/12568.58	% SZS status Ended for HL404941+5.p
90684.40/12569.42	% SZS status Started for HL404937+4.p
90684.40/12569.42	% SZS status GaveUp for HL404937+4.p
90684.40/12569.42	eprover: CPU time limit exceeded, terminating
90684.40/12569.42	% SZS status Ended for HL404937+4.p
90684.40/12569.43	% SZS status Started for HL404941+4.p
90684.40/12569.43	% SZS status GaveUp for HL404941+4.p
90684.40/12569.43	eprover: CPU time limit exceeded, terminating
90684.40/12569.43	% SZS status Ended for HL404941+4.p
90715.73/12573.41	% SZS status Started for HL404938+4.p
90715.73/12573.41	% SZS status GaveUp for HL404938+4.p
90715.73/12573.41	eprover: CPU time limit exceeded, terminating
90715.73/12573.41	% SZS status Ended for HL404938+4.p
90741.35/12576.59	% SZS status Started for HL404939+4.p
90741.35/12576.59	% SZS status GaveUp for HL404939+4.p
90741.35/12576.59	eprover: CPU time limit exceeded, terminating
90741.35/12576.59	% SZS status Ended for HL404939+4.p
90746.73/12577.27	% SZS status Started for HL404943+5.p
90746.73/12577.27	% SZS status GaveUp for HL404943+5.p
90746.73/12577.27	% SZS status Ended for HL404943+5.p
90756.74/12578.61	% SZS status Started for HL404944+5.p
90756.74/12578.61	% SZS status GaveUp for HL404944+5.p
90756.74/12578.61	% SZS status Ended for HL404944+5.p
90768.87/12580.04	% SZS status Started for HL404940+4.p
90768.87/12580.04	% SZS status GaveUp for HL404940+4.p
90768.87/12580.04	eprover: CPU time limit exceeded, terminating
90768.87/12580.04	% SZS status Ended for HL404940+4.p
90789.00/12582.67	% SZS status Started for HL404945+5.p
90789.00/12582.67	% SZS status GaveUp for HL404945+5.p
90789.00/12582.67	% SZS status Ended for HL404945+5.p
90820.02/12586.55	% SZS status Started for HL404946+5.p
90820.02/12586.55	% SZS status GaveUp for HL404946+5.p
90820.02/12586.55	% SZS status Ended for HL404946+5.p
90826.19/12587.35	% SZS status Started for HL404943+4.p
90826.19/12587.35	% SZS status GaveUp for HL404943+4.p
90826.19/12587.35	eprover: CPU time limit exceeded, terminating
90826.19/12587.35	% SZS status Ended for HL404943+4.p
90841.74/12589.23	% SZS status Started for HL404947+5.p
90841.74/12589.23	% SZS status GaveUp for HL404947+5.p
90841.74/12589.23	% SZS status Ended for HL404947+5.p
90884.19/12594.54	% SZS status Started for HL404944+4.p
90884.19/12594.54	% SZS status GaveUp for HL404944+4.p
90884.19/12594.54	eprover: CPU time limit exceeded, terminating
90884.19/12594.54	% SZS status Ended for HL404944+4.p
90892.89/12595.63	% SZS status Started for HL404945+4.p
90892.89/12595.63	% SZS status GaveUp for HL404945+4.p
90892.89/12595.63	eprover: CPU time limit exceeded, terminating
90892.89/12595.63	% SZS status Ended for HL404945+4.p
90894.41/12595.89	% SZS status Started for HL404949+5.p
90894.41/12595.89	% SZS status GaveUp for HL404949+5.p
90894.41/12595.89	% SZS status Ended for HL404949+5.p
90918.43/12598.86	% SZS status Started for HL404950+5.p
90918.43/12598.86	% SZS status GaveUp for HL404950+5.p
90918.43/12598.86	% SZS status Ended for HL404950+5.p
90950.37/12602.91	% SZS status Started for HL404946+4.p
90950.37/12602.91	% SZS status GaveUp for HL404946+4.p
90950.37/12602.91	eprover: CPU time limit exceeded, terminating
90950.37/12602.91	% SZS status Ended for HL404946+4.p
90962.54/12604.58	% SZS status Started for HL404947+4.p
90962.54/12604.58	% SZS status GaveUp for HL404947+4.p
90962.54/12604.58	eprover: CPU time limit exceeded, terminating
90962.54/12604.58	% SZS status Ended for HL404947+4.p
90965.30/12604.84	% SZS status Started for HL404951+4.p
90965.30/12604.84	% SZS status GaveUp for HL404951+4.p
90965.30/12604.84	eprover: CPU time limit exceeded, terminating
90965.30/12604.84	% SZS status Ended for HL404951+4.p
90966.05/12604.95	% SZS status Started for HL404951+5.p
90966.05/12604.95	% SZS status GaveUp for HL404951+5.p
90966.05/12604.95	% SZS status Ended for HL404951+5.p
90993.84/12608.43	% SZS status Started for HL404952+5.p
90993.84/12608.43	% SZS status GaveUp for HL404952+5.p
90993.84/12608.43	% SZS status Ended for HL404952+5.p
90995.16/12608.59	% SZS status Started for HL404949+4.p
90995.16/12608.59	% SZS status GaveUp for HL404949+4.p
90995.16/12608.59	eprover: CPU time limit exceeded, terminating
90995.16/12608.59	% SZS status Ended for HL404949+4.p
91032.14/12613.26	% SZS status Started for HL404950+4.p
91032.14/12613.26	% SZS status GaveUp for HL404950+4.p
91032.14/12613.26	eprover: CPU time limit exceeded, terminating
91032.14/12613.26	% SZS status Ended for HL404950+4.p
91037.79/12613.95	% SZS status Started for HL404953+5.p
91037.79/12613.95	% SZS status GaveUp for HL404953+5.p
91037.79/12613.95	% SZS status Ended for HL404953+5.p
91039.91/12614.34	% SZS status Started for HL404954+5.p
91039.91/12614.34	% SZS status GaveUp for HL404954+5.p
91039.91/12614.34	% SZS status Ended for HL404954+5.p
91070.57/12618.04	% SZS status Started for HL404955+5.p
91070.57/12618.04	% SZS status GaveUp for HL404955+5.p
91070.57/12618.04	% SZS status Ended for HL404955+5.p
91102.12/12622.05	% SZS status Started for HL404952+4.p
91102.12/12622.05	% SZS status GaveUp for HL404952+4.p
91102.12/12622.05	eprover: CPU time limit exceeded, terminating
91102.12/12622.05	% SZS status Ended for HL404952+4.p
91111.12/12623.20	% SZS status Started for HL404956+5.p
91111.12/12623.20	% SZS status GaveUp for HL404956+5.p
91111.12/12623.20	% SZS status Ended for HL404956+5.p
91121.40/12624.55	% SZS status Started for HL404957+4.p
91121.40/12624.55	% SZS status GaveUp for HL404957+4.p
91121.40/12624.55	eprover: CPU time limit exceeded, terminating
91121.40/12624.55	% SZS status Ended for HL404957+4.p
91144.65/12627.42	% SZS status Started for HL404957+5.p
91144.65/12627.42	% SZS status GaveUp for HL404957+5.p
91144.65/12627.42	% SZS status Ended for HL404957+5.p
91157.48/12629.06	% SZS status Started for HL404953+4.p
91157.48/12629.06	% SZS status GaveUp for HL404953+4.p
91157.48/12629.06	eprover: CPU time limit exceeded, terminating
91157.48/12629.06	% SZS status Ended for HL404953+4.p
91173.77/12631.12	% SZS status Started for HL404954+4.p
91173.77/12631.12	% SZS status GaveUp for HL404954+4.p
91173.77/12631.12	eprover: CPU time limit exceeded, terminating
91173.77/12631.12	% SZS status Ended for HL404954+4.p
91184.48/12632.43	% SZS status Started for HL404958+4.p
91184.48/12632.43	% SZS status GaveUp for HL404958+4.p
91184.48/12632.43	eprover: CPU time limit exceeded, terminating
91184.48/12632.43	% SZS status Ended for HL404958+4.p
91186.62/12632.69	% SZS status Started for HL404958+5.p
91186.62/12632.69	% SZS status GaveUp for HL404958+5.p
91186.62/12632.69	% SZS status Ended for HL404958+5.p
91200.46/12634.47	% SZS status Started for HL404955+4.p
91200.46/12634.47	% SZS status GaveUp for HL404955+4.p
91200.46/12634.47	eprover: CPU time limit exceeded, terminating
91200.46/12634.47	% SZS status Ended for HL404955+4.p
91221.03/12637.00	% SZS status Started for HL404959+5.p
91221.03/12637.00	% SZS status GaveUp for HL404959+5.p
91221.03/12637.00	% SZS status Ended for HL404959+5.p
91239.76/12639.49	% SZS status Started for HL404956+4.p
91239.76/12639.49	% SZS status GaveUp for HL404956+4.p
91239.76/12639.49	eprover: CPU time limit exceeded, terminating
91239.76/12639.49	% SZS status Ended for HL404956+4.p
91248.32/12640.49	% SZS status Started for HL404961+5.p
91248.32/12640.49	% SZS status GaveUp for HL404961+5.p
91248.32/12640.49	% SZS status Ended for HL404961+5.p
91261.52/12642.09	% SZS status Started for HL404962+5.p
91261.52/12642.09	% SZS status GaveUp for HL404962+5.p
91261.52/12642.09	% SZS status Ended for HL404962+5.p
91295.31/12646.39	% SZS status Started for HL404963+5.p
91295.31/12646.39	% SZS status GaveUp for HL404963+5.p
91295.31/12646.39	% SZS status Ended for HL404963+5.p
91322.35/12649.85	% SZS status Started for HL404964+5.p
91322.35/12649.85	% SZS status GaveUp for HL404964+5.p
91322.35/12649.85	% SZS status Ended for HL404964+5.p
91328.43/12650.54	% SZS status Started for HL404959+4.p
91328.43/12650.54	% SZS status GaveUp for HL404959+4.p
91328.43/12650.54	eprover: CPU time limit exceeded, terminating
91328.43/12650.54	% SZS status Ended for HL404959+4.p
91362.82/12654.95	% SZS status Started for HL404961+4.p
91362.82/12654.95	% SZS status GaveUp for HL404961+4.p
91362.82/12654.95	eprover: CPU time limit exceeded, terminating
91362.82/12654.95	% SZS status Ended for HL404961+4.p
91370.62/12655.84	% SZS status Started for HL404965+5.p
91370.62/12655.84	% SZS status GaveUp for HL404965+5.p
91370.62/12655.84	% SZS status Ended for HL404965+5.p
91390.12/12658.44	% SZS status Started for HL404962+4.p
91390.12/12658.44	% SZS status GaveUp for HL404962+4.p
91390.12/12658.44	eprover: CPU time limit exceeded, terminating
91390.12/12658.44	% SZS status Ended for HL404962+4.p
91403.99/12660.07	% SZS status Started for HL404967+5.p
91403.99/12660.07	% SZS status GaveUp for HL404967+5.p
91403.99/12660.07	% SZS status Ended for HL404967+5.p
91406.99/12660.64	% SZS status Started for HL404963+4.p
91406.99/12660.64	% SZS status GaveUp for HL404963+4.p
91406.99/12660.64	eprover: CPU time limit exceeded, terminating
91406.99/12660.64	% SZS status Ended for HL404963+4.p
91445.51/12665.28	% SZS status Started for HL404968+5.p
91445.51/12665.28	% SZS status GaveUp for HL404968+5.p
91445.51/12665.28	% SZS status Ended for HL404968+5.p
91447.40/12665.64	% SZS status Started for HL404964+4.p
91447.40/12665.64	% SZS status GaveUp for HL404964+4.p
91447.40/12665.64	eprover: CPU time limit exceeded, terminating
91447.40/12665.64	% SZS status Ended for HL404964+4.p
91469.62/12668.32	% SZS status Started for HL404965+4.p
91469.62/12668.32	% SZS status GaveUp for HL404965+4.p
91469.62/12668.32	eprover: CPU time limit exceeded, terminating
91469.62/12668.32	% SZS status Ended for HL404965+4.p
91479.52/12669.57	% SZS status Started for HL404969+5.p
91479.52/12669.57	% SZS status GaveUp for HL404969+5.p
91479.52/12669.57	% SZS status Ended for HL404969+5.p
91521.58/12674.84	% SZS status Started for HL404970+5.p
91521.58/12674.84	% SZS status GaveUp for HL404970+5.p
91521.58/12674.84	% SZS status Ended for HL404970+5.p
91529.78/12675.95	% SZS status Started for HL404967+4.p
91529.78/12675.95	% SZS status GaveUp for HL404967+4.p
91529.78/12675.95	eprover: CPU time limit exceeded, terminating
91529.78/12675.95	% SZS status Ended for HL404967+4.p
91543.73/12677.67	% SZS status Started for HL404971+5.p
91543.73/12677.67	% SZS status GaveUp for HL404971+5.p
91543.73/12677.67	% SZS status Ended for HL404971+5.p
91568.71/12680.91	% SZS status Started for HL404968+4.p
91568.71/12680.91	% SZS status GaveUp for HL404968+4.p
91568.71/12680.91	eprover: CPU time limit exceeded, terminating
91568.71/12680.91	% SZS status Ended for HL404968+4.p
91596.76/12684.29	% SZS status Started for HL404969+4.p
91596.76/12684.29	% SZS status GaveUp for HL404969+4.p
91596.76/12684.29	eprover: CPU time limit exceeded, terminating
91596.76/12684.29	% SZS status Ended for HL404969+4.p
91596.76/12684.35	% SZS status Started for HL404972+5.p
91596.76/12684.35	% SZS status GaveUp for HL404972+5.p
91596.76/12684.35	% SZS status Ended for HL404972+5.p
91616.32/12686.82	% SZS status Started for HL404970+4.p
91616.32/12686.82	% SZS status GaveUp for HL404970+4.p
91616.32/12686.82	eprover: CPU time limit exceeded, terminating
91616.32/12686.82	% SZS status Ended for HL404970+4.p
91619.24/12687.10	% SZS status Started for HL404973+5.p
91619.24/12687.10	% SZS status GaveUp for HL404973+5.p
91619.24/12687.10	% SZS status Ended for HL404973+5.p
91657.58/12691.93	% SZS status Started for HL404971+4.p
91657.58/12691.93	% SZS status GaveUp for HL404971+4.p
91657.58/12691.93	eprover: CPU time limit exceeded, terminating
91657.58/12691.93	% SZS status Ended for HL404971+4.p
91672.12/12693.79	% SZS status Started for HL404974+5.p
91672.12/12693.79	% SZS status GaveUp for HL404974+5.p
91672.12/12693.79	% SZS status Ended for HL404974+5.p
91686.59/12695.62	% SZS status Started for HL404972+4.p
91686.59/12695.62	% SZS status GaveUp for HL404972+4.p
91686.59/12695.62	eprover: CPU time limit exceeded, terminating
91686.59/12695.62	% SZS status Ended for HL404972+4.p
91693.06/12696.43	% SZS status Started for HL404975+5.p
91693.06/12696.43	% SZS status GaveUp for HL404975+5.p
91693.06/12696.43	% SZS status Ended for HL404975+5.p
91701.88/12697.62	% SZS status Started for HL404977+5.p
91701.88/12697.62	% SZS status Theorem for HL404977+5.p
91701.88/12697.62	% SZS status Ended for HL404977+5.p
91735.18/12701.76	% SZS status Started for HL404973+4.p
91735.18/12701.76	% SZS status GaveUp for HL404973+4.p
91735.18/12701.76	eprover: CPU time limit exceeded, terminating
91735.18/12701.76	% SZS status Ended for HL404973+4.p
91762.84/12705.26	% SZS status Started for HL404978+5.p
91762.84/12705.26	% SZS status GaveUp for HL404978+5.p
91762.84/12705.26	% SZS status Ended for HL404978+5.p
91775.52/12706.77	% SZS status Started for HL404974+4.p
91775.52/12706.77	% SZS status GaveUp for HL404974+4.p
91775.52/12706.77	eprover: CPU time limit exceeded, terminating
91775.52/12706.77	% SZS status Ended for HL404974+4.p
91778.76/12707.18	% SZS status Started for HL404979+5.p
91778.76/12707.18	% SZS status GaveUp for HL404979+5.p
91778.76/12707.18	% SZS status Ended for HL404979+5.p
91802.44/12710.23	% SZS status Started for HL404975+4.p
91802.44/12710.23	% SZS status GaveUp for HL404975+4.p
91802.44/12710.23	eprover: CPU time limit exceeded, terminating
91802.44/12710.23	% SZS status Ended for HL404975+4.p
91824.80/12712.98	% SZS status Started for HL404977+4.p
91824.80/12712.98	% SZS status GaveUp for HL404977+4.p
91824.80/12712.98	eprover: CPU time limit exceeded, terminating
91824.80/12712.98	% SZS status Ended for HL404977+4.p
91838.94/12714.84	% SZS status Started for HL404981+5.p
91838.94/12714.84	% SZS status GaveUp for HL404981+5.p
91838.94/12714.84	% SZS status Ended for HL404981+5.p
91854.98/12716.80	% SZS status Started for HL404982+5.p
91854.98/12716.80	% SZS status GaveUp for HL404982+5.p
91854.98/12716.80	% SZS status Ended for HL404982+5.p
91878.95/12719.83	% SZS status Started for HL404978+4.p
91878.95/12719.83	% SZS status GaveUp for HL404978+4.p
91878.95/12719.83	eprover: CPU time limit exceeded, terminating
91878.95/12719.83	% SZS status Ended for HL404978+4.p
91898.64/12722.33	% SZS status Started for HL404979+4.p
91898.64/12722.33	% SZS status GaveUp for HL404979+4.p
91898.64/12722.33	eprover: CPU time limit exceeded, terminating
91898.64/12722.33	% SZS status Ended for HL404979+4.p
91899.01/12722.38	% SZS status Started for HL404983+5.p
91899.01/12722.38	% SZS status GaveUp for HL404983+5.p
91899.01/12722.38	% SZS status Ended for HL404983+5.p
91930.27/12726.37	% SZS status Started for HL404984+5.p
91930.27/12726.37	% SZS status GaveUp for HL404984+5.p
91930.27/12726.37	% SZS status Ended for HL404984+5.p
91936.55/12727.10	% SZS status Started for HL404982+4.p
91936.55/12727.10	% SZS status GaveUp for HL404982+4.p
91936.55/12727.10	eprover: CPU time limit exceeded, terminating
91936.55/12727.10	% SZS status Ended for HL404982+4.p
91941.62/12727.91	% SZS status Started for HL404981+4.p
91941.62/12727.91	% SZS status GaveUp for HL404981+4.p
91941.62/12727.91	eprover: CPU time limit exceeded, terminating
91941.62/12727.91	% SZS status Ended for HL404981+4.p
91948.09/12728.57	% SZS status Started for HL404983+4.p
91948.09/12728.57	% SZS status GaveUp for HL404983+4.p
91948.09/12728.57	eprover: CPU time limit exceeded, terminating
91948.09/12728.57	% SZS status Ended for HL404983+4.p
91973.92/12731.91	% SZS status Started for HL404985+5.p
91973.92/12731.91	% SZS status GaveUp for HL404985+5.p
91973.92/12731.91	% SZS status Ended for HL404985+5.p
92005.18/12735.78	% SZS status Started for HL404986+5.p
92005.18/12735.78	% SZS status GaveUp for HL404986+5.p
92005.18/12735.78	% SZS status Ended for HL404986+5.p
92018.64/12737.49	% SZS status Started for HL404987+5.p
92018.64/12737.49	% SZS status GaveUp for HL404987+5.p
92018.64/12737.49	% SZS status Ended for HL404987+5.p
92029.77/12738.91	% SZS status Started for HL404988+4.p
92029.77/12738.91	% SZS status GaveUp for HL404988+4.p
92029.77/12738.91	eprover: CPU time limit exceeded, terminating
92029.77/12738.91	% SZS status Ended for HL404988+4.p
92043.50/12740.66	% SZS status Started for HL404984+4.p
92043.50/12740.66	% SZS status GaveUp for HL404984+4.p
92043.50/12740.66	eprover: CPU time limit exceeded, terminating
92043.50/12740.66	% SZS status Ended for HL404984+4.p
92048.31/12741.28	% SZS status Started for HL404988+5.p
92048.31/12741.28	% SZS status GaveUp for HL404988+5.p
92048.31/12741.28	% SZS status Ended for HL404988+5.p
92084.75/12745.82	% SZS status Started for HL404985+4.p
92084.75/12745.82	% SZS status GaveUp for HL404985+4.p
92084.75/12745.82	eprover: CPU time limit exceeded, terminating
92084.75/12745.82	% SZS status Ended for HL404985+4.p
92095.12/12747.15	% SZS status Started for HL404989+5.p
92095.12/12747.15	% SZS status GaveUp for HL404989+5.p
92095.12/12747.15	% SZS status Ended for HL404989+5.p
92105.18/12748.49	% SZS status Started for HL404986+4.p
92105.18/12748.49	% SZS status GaveUp for HL404986+4.p
92105.18/12748.49	eprover: CPU time limit exceeded, terminating
92105.18/12748.49	% SZS status Ended for HL404986+4.p
92117.93/12750.09	% SZS status Started for HL404990+5.p
92117.93/12750.09	% SZS status GaveUp for HL404990+5.p
92117.93/12750.09	% SZS status Ended for HL404990+5.p
92141.30/12753.01	% SZS status Started for HL404987+4.p
92141.30/12753.01	% SZS status GaveUp for HL404987+4.p
92141.30/12753.01	eprover: CPU time limit exceeded, terminating
92141.30/12753.01	% SZS status Ended for HL404987+4.p
92160.79/12755.36	% SZS status Started for HL404991+5.p
92160.79/12755.36	% SZS status GaveUp for HL404991+5.p
92160.79/12755.36	% SZS status Ended for HL404991+5.p
92181.41/12757.99	% SZS status Started for HL404992+5.p
92181.41/12757.99	% SZS status GaveUp for HL404992+5.p
92181.41/12757.99	% SZS status Ended for HL404992+5.p
92212.05/12761.82	% SZS status Started for HL404989+4.p
92212.05/12761.82	% SZS status GaveUp for HL404989+4.p
92212.05/12761.82	eprover: CPU time limit exceeded, terminating
92212.05/12761.82	% SZS status Ended for HL404989+4.p
92216.97/12762.48	% SZS status Started for HL404994+5.p
92216.97/12762.48	% SZS status GaveUp for HL404994+5.p
92216.97/12762.48	% SZS status Ended for HL404994+5.p
92235.99/12764.87	% SZS status Started for HL404990+4.p
92235.99/12764.87	% SZS status GaveUp for HL404990+4.p
92235.99/12764.87	eprover: CPU time limit exceeded, terminating
92235.99/12764.87	% SZS status Ended for HL404990+4.p
92256.16/12767.38	% SZS status Started for HL404995+5.p
92256.16/12767.38	% SZS status GaveUp for HL404995+5.p
92256.16/12767.38	% SZS status Ended for HL404995+5.p
92257.63/12767.61	% SZS status Started for HL404991+4.p
92257.63/12767.61	% SZS status GaveUp for HL404991+4.p
92257.63/12767.61	eprover: CPU time limit exceeded, terminating
92257.63/12767.61	% SZS status Ended for HL404991+4.p
92294.69/12772.21	% SZS status Started for HL404996+5.p
92294.69/12772.21	% SZS status GaveUp for HL404996+5.p
92294.69/12772.21	% SZS status Ended for HL404996+5.p
92300.02/12773.07	% SZS status Started for HL404992+4.p
92300.02/12773.07	% SZS status GaveUp for HL404992+4.p
92300.02/12773.07	eprover: CPU time limit exceeded, terminating
92300.02/12773.07	% SZS status Ended for HL404992+4.p
92323.70/12776.01	% SZS status Started for HL404994+4.p
92323.70/12776.01	% SZS status GaveUp for HL404994+4.p
92323.70/12776.01	eprover: CPU time limit exceeded, terminating
92323.70/12776.01	% SZS status Ended for HL404994+4.p
92331.09/12776.83	% SZS status Started for HL404997+5.p
92331.09/12776.83	% SZS status GaveUp for HL404997+5.p
92331.09/12776.83	% SZS status Ended for HL404997+5.p
92365.94/12781.26	% SZS status Started for HL404995+4.p
92365.94/12781.26	% SZS status GaveUp for HL404995+4.p
92365.94/12781.26	eprover: CPU time limit exceeded, terminating
92365.94/12781.26	% SZS status Ended for HL404995+4.p
92369.09/12781.64	% SZS status Started for HL404998+5.p
92369.09/12781.64	% SZS status GaveUp for HL404998+5.p
92369.09/12781.64	% SZS status Ended for HL404998+5.p
92370.12/12781.81	% SZS status Started for HL404998+4.p
92370.12/12781.81	% SZS status GaveUp for HL404998+4.p
92370.12/12781.81	eprover: CPU time limit exceeded, terminating
92370.12/12781.81	% SZS status Ended for HL404998+4.p
92399.50/12785.43	% SZS status Started for HL404999+5.p
92399.50/12785.43	% SZS status GaveUp for HL404999+5.p
92399.50/12785.43	% SZS status Ended for HL404999+5.p
92418.65/12787.86	% SZS status Started for HL404996+4.p
92418.65/12787.86	% SZS status GaveUp for HL404996+4.p
92418.65/12787.86	eprover: CPU time limit exceeded, terminating
92418.65/12787.86	% SZS status Ended for HL404996+4.p
92440.25/12790.62	% SZS status Started for HL405000+5.p
92440.25/12790.62	% SZS status GaveUp for HL405000+5.p
92440.25/12790.62	% SZS status Ended for HL405000+5.p
92442.29/12790.97	% SZS status Started for HL405001+5.p
92442.29/12790.97	% SZS status GaveUp for HL405001+5.p
92442.29/12790.97	% SZS status Ended for HL405001+5.p
92444.92/12791.22	% SZS status Started for HL404997+4.p
92444.92/12791.22	% SZS status GaveUp for HL404997+4.p
92444.92/12791.22	eprover: CPU time limit exceeded, terminating
92444.92/12791.22	% SZS status Ended for HL404997+4.p
92450.47/12791.87	% SZS status Started for HL405001+4.p
92450.47/12791.87	% SZS status GaveUp for HL405001+4.p
92450.47/12791.87	eprover: CPU time limit exceeded, terminating
92450.47/12791.87	% SZS status Ended for HL405001+4.p
92491.64/12797.08	% SZS status Started for HL405003+5.p
92491.64/12797.08	% SZS status GaveUp for HL405003+5.p
92491.64/12797.08	% SZS status Ended for HL405003+5.p
92494.31/12797.53	% SZS status Started for HL405005+5.p
92494.31/12797.53	% SZS status Theorem for HL405005+5.p
92494.31/12797.53	% SZS status Ended for HL405005+5.p
92511.29/12799.56	% SZS status Started for HL404999+4.p
92511.29/12799.56	% SZS status GaveUp for HL404999+4.p
92511.29/12799.56	eprover: CPU time limit exceeded, terminating
92511.29/12799.56	% SZS status Ended for HL404999+4.p
92517.30/12800.33	% SZS status Started for HL405004+5.p
92517.30/12800.33	% SZS status GaveUp for HL405004+5.p
92517.30/12800.33	% SZS status Ended for HL405004+5.p
92523.03/12801.06	% SZS status Started for HL405004+4.p
92523.03/12801.06	% SZS status GaveUp for HL405004+4.p
92523.03/12801.06	eprover: CPU time limit exceeded, terminating
92523.03/12801.06	% SZS status Ended for HL405004+4.p
92536.34/12802.78	% SZS status Started for HL405000+4.p
92536.34/12802.78	% SZS status GaveUp for HL405000+4.p
92536.34/12802.78	eprover: CPU time limit exceeded, terminating
92536.34/12802.78	% SZS status Ended for HL405000+4.p
92570.69/12807.02	% SZS status Started for HL405007+5.p
92570.69/12807.02	% SZS status GaveUp for HL405007+5.p
92570.69/12807.02	% SZS status Ended for HL405007+5.p
92592.04/12809.70	% SZS status Started for HL405008+4.p
92592.04/12809.70	% SZS status GaveUp for HL405008+4.p
92592.04/12809.70	eprover: CPU time limit exceeded, terminating
92592.04/12809.70	% SZS status Ended for HL405008+4.p
92592.84/12809.83	% SZS status Started for HL405008+5.p
92592.84/12809.83	% SZS status GaveUp for HL405008+5.p
92592.84/12809.83	% SZS status Ended for HL405008+5.p
92607.69/12811.77	% SZS status Started for HL405003+4.p
92607.69/12811.77	% SZS status GaveUp for HL405003+4.p
92607.69/12811.77	eprover: CPU time limit exceeded, terminating
92607.69/12811.77	% SZS status Ended for HL405003+4.p
92610.70/12812.28	% SZS status Started for HL405009+5.p
92610.70/12812.28	% SZS status GaveUp for HL405009+5.p
92610.70/12812.28	% SZS status Ended for HL405009+5.p
92650.53/12817.06	% SZS status Started for HL405005+4.p
92650.53/12817.06	% SZS status GaveUp for HL405005+4.p
92650.53/12817.06	eprover: CPU time limit exceeded, terminating
92650.53/12817.06	% SZS status Ended for HL405005+4.p
92666.54/12819.09	% SZS status Started for HL405010+5.p
92666.54/12819.09	% SZS status GaveUp for HL405010+5.p
92666.54/12819.09	% SZS status Ended for HL405010+5.p
92682.46/12821.16	% SZS status Started for HL405011+5.p
92682.46/12821.16	% SZS status GaveUp for HL405011+5.p
92682.46/12821.16	% SZS status Ended for HL405011+5.p
92696.64/12822.93	% SZS status Started for HL405007+4.p
92696.64/12822.93	% SZS status GaveUp for HL405007+4.p
92696.64/12822.93	eprover: CPU time limit exceeded, terminating
92696.64/12822.93	% SZS status Ended for HL405007+4.p
92727.50/12826.98	% SZS status Started for HL405009+4.p
92727.50/12826.98	% SZS status GaveUp for HL405009+4.p
92727.50/12826.98	eprover: CPU time limit exceeded, terminating
92727.50/12826.98	% SZS status Ended for HL405009+4.p
92730.83/12827.55	% SZS status Started for HL405012+5.p
92730.83/12827.55	% SZS status GaveUp for HL405012+5.p
92730.83/12827.55	% SZS status Ended for HL405012+5.p
92767.62/12834.23	% SZS status Started for HL405013+5.p
92767.62/12834.23	% SZS status GaveUp for HL405013+5.p
92767.62/12834.23	% SZS status Ended for HL405013+5.p
92767.62/12834.28	% SZS status Started for HL405010+4.p
92767.62/12834.28	% SZS status GaveUp for HL405010+4.p
92767.62/12834.28	eprover: CPU time limit exceeded, terminating
92767.62/12834.28	% SZS status Ended for HL405010+4.p
92783.68/12837.17	% SZS status Started for HL405011+4.p
92783.68/12837.17	% SZS status GaveUp for HL405011+4.p
92783.68/12837.17	eprover: CPU time limit exceeded, terminating
92783.68/12837.17	% SZS status Ended for HL405011+4.p
92811.09/12843.57	% SZS status Started for HL405014+5.p
92811.09/12843.57	% SZS status GaveUp for HL405014+5.p
92811.09/12843.57	% SZS status Ended for HL405014+5.p
92824.47/12846.35	% SZS status Started for HL405015+4.p
92824.47/12846.35	% SZS status GaveUp for HL405015+4.p
92824.47/12846.35	eprover: CPU time limit exceeded, terminating
92824.47/12846.35	% SZS status Ended for HL405015+4.p
92832.32/12847.93	% SZS status Started for HL405012+4.p
92832.32/12847.93	% SZS status GaveUp for HL405012+4.p
92832.32/12847.93	eprover: CPU time limit exceeded, terminating
92832.32/12847.93	% SZS status Ended for HL405012+4.p
92833.76/12848.22	% SZS status Started for HL405015+5.p
92833.76/12848.22	% SZS status GaveUp for HL405015+5.p
92833.76/12848.22	% SZS status Ended for HL405015+5.p
92852.22/12851.88	% SZS status Started for HL405016+4.p
92852.22/12851.88	% SZS status GaveUp for HL405016+4.p
92852.22/12851.88	eprover: CPU time limit exceeded, terminating
92852.22/12851.88	% SZS status Ended for HL405016+4.p
92858.57/12852.97	% SZS status Started for HL405016+5.p
92858.57/12852.97	% SZS status GaveUp for HL405016+5.p
92858.57/12852.97	% SZS status Ended for HL405016+5.p
92869.88/12854.84	% SZS status Started for HL405013+4.p
92869.88/12854.84	% SZS status GaveUp for HL405013+4.p
92869.88/12854.84	eprover: CPU time limit exceeded, terminating
92869.88/12854.84	% SZS status Ended for HL405013+4.p
92895.41/12859.29	% SZS status Started for HL405014+4.p
92895.41/12859.29	% SZS status GaveUp for HL405014+4.p
92895.41/12859.29	eprover: CPU time limit exceeded, terminating
92895.41/12859.29	% SZS status Ended for HL405014+4.p
92901.84/12860.40	% SZS status Started for HL405017+4.p
92901.84/12860.40	% SZS status GaveUp for HL405017+4.p
92901.84/12860.40	eprover: CPU time limit exceeded, terminating
92901.84/12860.40	% SZS status Ended for HL405017+4.p
92904.34/12860.74	% SZS status Started for HL405017+5.p
92904.34/12860.74	% SZS status GaveUp for HL405017+5.p
92904.34/12860.74	% SZS status Ended for HL405017+5.p
92914.63/12862.15	% SZS status Started for HL405018+5.p
92914.63/12862.15	% SZS status GaveUp for HL405018+5.p
92914.63/12862.15	% SZS status Ended for HL405018+5.p
92933.01/12864.58	% SZS status Started for HL405018+4.p
92933.01/12864.58	% SZS status GaveUp for HL405018+4.p
92933.01/12864.58	eprover: CPU time limit exceeded, terminating
92933.01/12864.58	% SZS status Ended for HL405018+4.p
92937.22/12865.17	% SZS status Started for HL405019+5.p
92937.22/12865.17	% SZS status GaveUp for HL405019+5.p
92937.22/12865.17	% SZS status Ended for HL405019+5.p
92942.06/12865.67	% SZS status Started for HL405019+4.p
92942.06/12865.67	% SZS status GaveUp for HL405019+4.p
92942.06/12865.67	eprover: CPU time limit exceeded, terminating
92942.06/12865.67	% SZS status Ended for HL405019+4.p
92951.72/12866.96	% SZS status Started for HL405020+4.p
92951.72/12866.96	% SZS status GaveUp for HL405020+4.p
92951.72/12866.96	eprover: CPU time limit exceeded, terminating
92951.72/12866.96	% SZS status Ended for HL405020+4.p
92975.24/12870.06	% SZS status Started for HL405020+5.p
92975.24/12870.06	% SZS status GaveUp for HL405020+5.p
92975.24/12870.06	% SZS status Ended for HL405020+5.p
92980.37/12870.80	% SZS status Started for HL405021+5.p
92980.37/12870.80	% SZS status GaveUp for HL405021+5.p
92980.37/12870.80	% SZS status Ended for HL405021+5.p
92993.84/12872.74	% SZS status Started for HL405021+4.p
92993.84/12872.74	% SZS status GaveUp for HL405021+4.p
92993.84/12872.74	eprover: CPU time limit exceeded, terminating
92993.84/12872.74	% SZS status Ended for HL405021+4.p
93006.40/12874.61	% SZS status Started for HL405023+4.p
93006.40/12874.61	% SZS status GaveUp for HL405023+4.p
93006.40/12874.61	eprover: CPU time limit exceeded, terminating
93006.40/12874.61	% SZS status Ended for HL405023+4.p
93013.47/12875.51	% SZS status Started for HL405023+5.p
93013.47/12875.51	% SZS status GaveUp for HL405023+5.p
93013.47/12875.51	% SZS status Ended for HL405023+5.p
93018.38/12876.21	% SZS status Started for HL405025+5.p
93018.38/12876.21	% SZS status GaveUp for HL405025+5.p
93018.38/12876.21	% SZS status Ended for HL405025+5.p
93020.02/12876.44	% SZS status Started for HL405025+4.p
93020.02/12876.44	% SZS status GaveUp for HL405025+4.p
93020.02/12876.44	eprover: CPU time limit exceeded, terminating
93020.02/12876.44	% SZS status Ended for HL405025+4.p
93033.80/12878.20	% SZS status Started for HL405026+4.p
93033.80/12878.20	% SZS status GaveUp for HL405026+4.p
93033.80/12878.20	eprover: CPU time limit exceeded, terminating
93033.80/12878.20	% SZS status Ended for HL405026+4.p
93052.61/12880.57	% SZS status Started for HL405026+5.p
93052.61/12880.57	% SZS status GaveUp for HL405026+5.p
93052.61/12880.57	% SZS status Ended for HL405026+5.p
93060.33/12881.66	% SZS status Started for HL405027+4.p
93060.33/12881.66	% SZS status GaveUp for HL405027+4.p
93060.33/12881.66	eprover: CPU time limit exceeded, terminating
93060.33/12881.66	% SZS status Ended for HL405027+4.p
93073.43/12883.38	% SZS status Started for HL405027+5.p
93073.43/12883.38	% SZS status GaveUp for HL405027+5.p
93073.43/12883.38	% SZS status Ended for HL405027+5.p
93094.23/12885.86	% SZS status Started for HL405028+4.p
93094.23/12885.86	% SZS status GaveUp for HL405028+4.p
93094.23/12885.86	eprover: CPU time limit exceeded, terminating
93094.23/12885.86	% SZS status Ended for HL405028+4.p
93094.23/12885.90	% SZS status Started for HL405028+5.p
93094.23/12885.90	% SZS status GaveUp for HL405028+5.p
93094.23/12885.90	% SZS status Ended for HL405028+5.p
93098.52/12886.44	% SZS status Started for HL405030+5.p
93098.52/12886.44	% SZS status GaveUp for HL405030+5.p
93098.52/12886.44	% SZS status Ended for HL405030+5.p
93103.62/12887.12	% SZS status Started for HL405030+4.p
93103.62/12887.12	% SZS status GaveUp for HL405030+4.p
93103.62/12887.12	eprover: CPU time limit exceeded, terminating
93103.62/12887.12	% SZS status Ended for HL405030+4.p
93119.30/12889.11	% SZS status Started for HL405031+4.p
93119.30/12889.11	% SZS status GaveUp for HL405031+4.p
93119.30/12889.11	eprover: CPU time limit exceeded, terminating
93119.30/12889.11	% SZS status Ended for HL405031+4.p
93131.11/12890.66	% SZS status Started for HL405031+5.p
93131.11/12890.66	% SZS status GaveUp for HL405031+5.p
93131.11/12890.66	% SZS status Ended for HL405031+5.p
93147.41/12892.80	% SZS status Started for HL405032+4.p
93147.41/12892.80	% SZS status GaveUp for HL405032+4.p
93147.41/12892.80	eprover: CPU time limit exceeded, terminating
93147.41/12892.80	% SZS status Ended for HL405032+4.p
93154.86/12893.77	% SZS status Started for HL405032+5.p
93154.86/12893.77	% SZS status GaveUp for HL405032+5.p
93154.86/12893.77	% SZS status Ended for HL405032+5.p
93170.89/12895.88	% SZS status Started for HL405034+5.p
93170.89/12895.88	% SZS status GaveUp for HL405034+5.p
93170.89/12895.88	% SZS status Ended for HL405034+5.p
93176.57/12896.77	% SZS status Started for HL405034+4.p
93176.57/12896.77	% SZS status GaveUp for HL405034+4.p
93176.57/12896.77	eprover: CPU time limit exceeded, terminating
93176.57/12896.77	% SZS status Ended for HL405034+4.p
93184.77/12897.68	% SZS status Started for HL405036+5.p
93184.77/12897.68	% SZS status GaveUp for HL405036+5.p
93184.77/12897.68	% SZS status Ended for HL405036+5.p
93188.65/12898.20	% SZS status Started for HL405036+4.p
93188.65/12898.20	% SZS status GaveUp for HL405036+4.p
93188.65/12898.20	eprover: CPU time limit exceeded, terminating
93188.65/12898.20	% SZS status Ended for HL405036+4.p
93206.44/12900.50	% SZS status Started for HL405037+4.p
93206.44/12900.50	% SZS status GaveUp for HL405037+4.p
93206.44/12900.50	eprover: CPU time limit exceeded, terminating
93206.44/12900.50	% SZS status Ended for HL405037+4.p
93206.98/12900.53	% SZS status Started for HL405037+5.p
93206.98/12900.53	% SZS status GaveUp for HL405037+5.p
93206.98/12900.53	% SZS status Ended for HL405037+5.p
93230.87/12903.74	% SZS status Started for HL405038+5.p
93230.87/12903.74	% SZS status GaveUp for HL405038+5.p
93230.87/12903.74	% SZS status Ended for HL405038+5.p
93251.63/12906.35	% SZS status Started for HL405039+5.p
93251.63/12906.35	% SZS status GaveUp for HL405039+5.p
93251.63/12906.35	% SZS status Ended for HL405039+5.p
93253.16/12906.68	% SZS status Started for HL405039+4.p
93253.16/12906.68	% SZS status GaveUp for HL405039+4.p
93253.16/12906.68	eprover: CPU time limit exceeded, terminating
93253.16/12906.68	% SZS status Ended for HL405039+4.p
93267.25/12908.33	% SZS status Started for HL405040+4.p
93267.25/12908.33	% SZS status GaveUp for HL405040+4.p
93267.25/12908.33	eprover: CPU time limit exceeded, terminating
93267.25/12908.33	% SZS status Ended for HL405040+4.p
93268.52/12908.50	% SZS status Started for HL405040+5.p
93268.52/12908.50	% SZS status GaveUp for HL405040+5.p
93268.52/12908.50	% SZS status Ended for HL405040+5.p
93291.27/12911.43	% SZS status Started for HL405041+5.p
93291.27/12911.43	% SZS status GaveUp for HL405041+5.p
93291.27/12911.43	% SZS status Ended for HL405041+5.p
93314.59/12914.33	% SZS status Started for HL405042+4.p
93314.59/12914.33	% SZS status GaveUp for HL405042+4.p
93314.59/12914.33	eprover: CPU time limit exceeded, terminating
93314.59/12914.33	% SZS status Ended for HL405042+4.p
93341.98/12917.94	% SZS status Started for HL405043+5.p
93341.98/12917.94	% SZS status GaveUp for HL405043+5.p
93341.98/12917.94	% SZS status Ended for HL405043+5.p
93351.67/12919.06	% SZS status Started for HL405038+4.p
93351.67/12919.06	% SZS status GaveUp for HL405038+4.p
93351.67/12919.06	eprover: CPU time limit exceeded, terminating
93351.67/12919.06	% SZS status Ended for HL405038+4.p
93353.12/12919.21	% SZS status Started for HL405044+4.p
93353.12/12919.21	% SZS status GaveUp for HL405044+4.p
93353.12/12919.21	eprover: CPU time limit exceeded, terminating
93353.12/12919.21	% SZS status Ended for HL405044+4.p
93363.34/12920.60	% SZS status Started for HL405042+5.p
93363.34/12920.60	% SZS status GaveUp for HL405042+5.p
93363.34/12920.60	eprover: CPU time limit exceeded, terminating
93363.34/12920.60	% SZS status Ended for HL405042+5.p
93365.84/12920.88	% SZS status Started for HL405044+5.p
93365.84/12920.88	% SZS status GaveUp for HL405044+5.p
93365.84/12920.88	% SZS status Ended for HL405044+5.p
93414.92/12927.07	% SZS status Started for HL405041+4.p
93414.92/12927.07	% SZS status GaveUp for HL405041+4.p
93414.92/12927.07	eprover: CPU time limit exceeded, terminating
93414.92/12927.07	% SZS status Ended for HL405041+4.p
93419.49/12927.62	% SZS status Started for HL405045+5.p
93419.49/12927.62	% SZS status GaveUp for HL405045+5.p
93419.49/12927.62	% SZS status Ended for HL405045+5.p
93426.48/12928.61	% SZS status Started for HL405046+5.p
93426.48/12928.61	% SZS status GaveUp for HL405046+5.p
93426.48/12928.61	% SZS status Ended for HL405046+5.p
93432.27/12929.29	% SZS status Started for HL405046+4.p
93432.27/12929.29	% SZS status GaveUp for HL405046+4.p
93432.27/12929.29	eprover: CPU time limit exceeded, terminating
93432.27/12929.29	% SZS status Ended for HL405046+4.p
93440.62/12930.30	% SZS status Started for HL405048+5.p
93440.62/12930.30	% SZS status GaveUp for HL405048+5.p
93440.62/12930.30	% SZS status Ended for HL405048+5.p
93462.44/12933.00	% SZS status Started for HL405043+4.p
93462.44/12933.00	% SZS status GaveUp for HL405043+4.p
93462.44/12933.00	eprover: CPU time limit exceeded, terminating
93462.44/12933.00	% SZS status Ended for HL405043+4.p
93493.34/12936.98	% SZS status Started for HL405049+5.p
93493.34/12936.98	% SZS status GaveUp for HL405049+5.p
93493.34/12936.98	% SZS status Ended for HL405049+5.p
93507.02/12938.64	% SZS status Started for HL405050+5.p
93507.02/12938.64	% SZS status GaveUp for HL405050+5.p
93507.02/12938.64	% SZS status Ended for HL405050+5.p
93521.30/12940.40	% SZS status Started for HL405045+4.p
93521.30/12940.40	% SZS status GaveUp for HL405045+4.p
93521.30/12940.40	eprover: CPU time limit exceeded, terminating
93521.30/12940.40	% SZS status Ended for HL405045+4.p
93537.15/12942.40	% SZS status Started for HL405051+5.p
93537.15/12942.40	% SZS status GaveUp for HL405051+5.p
93537.15/12942.40	% SZS status Ended for HL405051+5.p
93571.74/12947.45	% SZS status Started for HL405048+4.p
93571.74/12947.45	% SZS status GaveUp for HL405048+4.p
93571.74/12947.45	eprover: CPU time limit exceeded, terminating
93571.74/12947.45	% SZS status Ended for HL405048+4.p
93580.13/12948.87	% SZS status Started for HL405052+5.p
93580.13/12948.87	% SZS status GaveUp for HL405052+5.p
93580.13/12948.87	% SZS status Ended for HL405052+5.p
93618.13/12955.87	% SZS status Started for HL405050+4.p
93618.13/12955.87	% SZS status GaveUp for HL405050+4.p
93618.13/12955.87	eprover: CPU time limit exceeded, terminating
93618.13/12955.87	% SZS status Ended for HL405050+4.p
93628.59/12957.80	% SZS status Started for HL405049+4.p
93628.59/12957.80	% SZS status GaveUp for HL405049+4.p
93628.59/12957.80	eprover: CPU time limit exceeded, terminating
93628.59/12957.80	% SZS status Ended for HL405049+4.p
93654.01/12962.01	% SZS status Started for HL405051+4.p
93654.01/12962.01	% SZS status GaveUp for HL405051+4.p
93654.01/12962.01	eprover: CPU time limit exceeded, terminating
93654.01/12962.01	% SZS status Ended for HL405051+4.p
93654.01/12962.01	% SZS status Started for HL405054+4.p
93654.01/12962.01	% SZS status GaveUp for HL405054+4.p
93654.01/12962.01	eprover: CPU time limit exceeded, terminating
93654.01/12962.01	% SZS status Ended for HL405054+4.p
93656.68/12962.58	% SZS status Started for HL405053+5.p
93656.68/12962.58	% SZS status GaveUp for HL405053+5.p
93656.68/12962.58	eprover: CPU time limit exceeded, terminating
93656.68/12962.58	% SZS status Ended for HL405053+5.p
93689.27/12967.91	% SZS status Started for HL405052+4.p
93689.27/12967.91	% SZS status GaveUp for HL405052+4.p
93689.27/12967.91	eprover: CPU time limit exceeded, terminating
93689.27/12967.91	% SZS status Ended for HL405052+4.p
93689.96/12968.16	% SZS status Started for HL405054+5.p
93689.96/12968.16	% SZS status GaveUp for HL405054+5.p
93689.96/12968.16	% SZS status Ended for HL405054+5.p
93703.12/12970.04	% SZS status Started for HL405055+5.p
93703.12/12970.04	% SZS status GaveUp for HL405055+5.p
93703.12/12970.04	% SZS status Ended for HL405055+5.p
93715.04/12971.88	% SZS status Started for HL405055+4.p
93715.04/12971.88	% SZS status GaveUp for HL405055+4.p
93715.04/12971.88	eprover: CPU time limit exceeded, terminating
93715.04/12971.88	% SZS status Ended for HL405055+4.p
93729.49/12973.99	% SZS status Started for HL405056+4.p
93729.49/12973.99	% SZS status GaveUp for HL405056+4.p
93729.49/12973.99	eprover: CPU time limit exceeded, terminating
93729.49/12973.99	% SZS status Ended for HL405056+4.p
93730.52/12974.27	% SZS status Started for HL405056+5.p
93730.52/12974.27	% SZS status GaveUp for HL405056+5.p
93730.52/12974.27	% SZS status Ended for HL405056+5.p
93739.08/12975.49	% SZS status Started for HL405053+4.p
93739.08/12975.49	% SZS status GaveUp for HL405053+4.p
93739.08/12975.49	eprover: CPU time limit exceeded, terminating
93739.08/12975.49	% SZS status Ended for HL405053+4.p
93741.66/12975.92	% SZS status Started for HL405057+4.p
93741.66/12975.92	% SZS status GaveUp for HL405057+4.p
93741.66/12975.92	eprover: CPU time limit exceeded, terminating
93741.66/12975.92	% SZS status Ended for HL405057+4.p
93781.11/12980.93	% SZS status Started for HL405058+4.p
93781.11/12980.93	% SZS status GaveUp for HL405058+4.p
93781.11/12980.93	eprover: CPU time limit exceeded, terminating
93781.11/12980.93	% SZS status Ended for HL405058+4.p
93781.11/12980.93	% SZS status Started for HL405058+5.p
93781.11/12980.93	% SZS status GaveUp for HL405058+5.p
93781.11/12980.93	% SZS status Ended for HL405058+5.p
93783.48/12981.24	% SZS status Started for HL405057+5.p
93783.48/12981.24	% SZS status GaveUp for HL405057+5.p
93783.48/12981.24	% SZS status Ended for HL405057+5.p
93809.05/12984.70	% SZS status Started for HL405060+5.p
93809.05/12984.70	% SZS status GaveUp for HL405060+5.p
93809.05/12984.70	% SZS status Ended for HL405060+5.p
93811.77/12985.25	% SZS status Started for HL405061+4.p
93811.77/12985.25	% SZS status GaveUp for HL405061+4.p
93811.77/12985.25	eprover: CPU time limit exceeded, terminating
93811.77/12985.25	% SZS status Ended for HL405061+4.p
93814.15/12985.50	% SZS status Started for HL405060+4.p
93814.15/12985.50	% SZS status GaveUp for HL405060+4.p
93814.15/12985.50	eprover: CPU time limit exceeded, terminating
93814.15/12985.50	% SZS status Ended for HL405060+4.p
93819.84/12986.31	% SZS status Started for HL405061+5.p
93819.84/12986.31	% SZS status GaveUp for HL405061+5.p
93819.84/12986.31	% SZS status Ended for HL405061+5.p
93834.60/12988.28	% SZS status Started for HL405062+4.p
93834.60/12988.28	% SZS status GaveUp for HL405062+4.p
93834.60/12988.28	eprover: CPU time limit exceeded, terminating
93834.60/12988.28	% SZS status Ended for HL405062+4.p
93858.27/12991.38	% SZS status Started for HL405063+5.p
93858.27/12991.38	% SZS status GaveUp for HL405063+5.p
93858.27/12991.38	% SZS status Ended for HL405063+5.p
93863.09/12991.97	% SZS status Started for HL405062+5.p
93863.09/12991.97	% SZS status GaveUp for HL405062+5.p
93863.09/12991.97	% SZS status Ended for HL405062+5.p
93871.50/12993.06	% SZS status Started for HL405063+4.p
93871.50/12993.06	% SZS status GaveUp for HL405063+4.p
93871.50/12993.06	eprover: CPU time limit exceeded, terminating
93871.50/12993.06	% SZS status Ended for HL405063+4.p
93888.77/12995.30	% SZS status Started for HL405064+5.p
93888.77/12995.30	% SZS status GaveUp for HL405064+5.p
93888.77/12995.30	% SZS status Ended for HL405064+5.p
93894.27/12995.94	% SZS status Started for HL405064+4.p
93894.27/12995.94	% SZS status GaveUp for HL405064+4.p
93894.27/12995.94	eprover: CPU time limit exceeded, terminating
93894.27/12995.94	% SZS status Ended for HL405064+4.p
93895.44/12996.17	% SZS status Started for HL405065+5.p
93895.44/12996.17	% SZS status GaveUp for HL405065+5.p
93895.44/12996.17	% SZS status Ended for HL405065+5.p
93897.38/12996.38	% SZS status Started for HL405065+4.p
93897.38/12996.38	% SZS status GaveUp for HL405065+4.p
93897.38/12996.38	eprover: CPU time limit exceeded, terminating
93897.38/12996.38	% SZS status Ended for HL405065+4.p
93935.73/13001.29	% SZS status Started for HL405066+5.p
93935.73/13001.29	% SZS status GaveUp for HL405066+5.p
93935.73/13001.29	% SZS status Ended for HL405066+5.p
93943.92/13002.37	% SZS status Started for HL405067+4.p
93943.92/13002.37	% SZS status GaveUp for HL405067+4.p
93943.92/13002.37	eprover: CPU time limit exceeded, terminating
93943.92/13002.37	% SZS status Ended for HL405067+4.p
93946.26/13002.68	% SZS status Started for HL405067+5.p
93946.26/13002.68	% SZS status GaveUp for HL405067+5.p
93946.26/13002.68	% SZS status Ended for HL405067+5.p
93970.04/13005.76	% SZS status Started for HL405068+4.p
93970.04/13005.76	% SZS status GaveUp for HL405068+4.p
93970.04/13005.76	eprover: CPU time limit exceeded, terminating
93970.04/13005.76	% SZS status Ended for HL405068+4.p
93974.07/13006.24	% SZS status Started for HL405068+5.p
93974.07/13006.24	% SZS status GaveUp for HL405068+5.p
93974.07/13006.24	% SZS status Ended for HL405068+5.p
94003.51/13010.07	% SZS status Started for HL405069+5.p
94003.51/13010.07	% SZS status GaveUp for HL405069+5.p
94003.51/13010.07	eprover: CPU time limit exceeded, terminating
94003.51/13010.07	% SZS status Ended for HL405069+5.p
94020.41/13012.12	% SZS status Started for HL405070+4.p
94020.41/13012.12	% SZS status GaveUp for HL405070+4.p
94020.41/13012.12	eprover: CPU time limit exceeded, terminating
94020.41/13012.12	% SZS status Ended for HL405070+4.p
94030.32/13013.42	% SZS status Started for HL405072+4.p
94030.32/13013.42	% SZS status GaveUp for HL405072+4.p
94030.32/13013.42	eprover: CPU time limit exceeded, terminating
94030.32/13013.42	% SZS status Ended for HL405072+4.p
94042.77/13015.01	% SZS status Started for HL405072+5.p
94042.77/13015.01	% SZS status GaveUp for HL405072+5.p
94042.77/13015.01	% SZS status Ended for HL405072+5.p
94043.18/13015.01	% SZS status Started for HL405066+4.p
94043.18/13015.01	% SZS status GaveUp for HL405066+4.p
94043.18/13015.01	eprover: CPU time limit exceeded, terminating
94043.18/13015.01	% SZS status Ended for HL405066+4.p
94053.34/13016.36	% SZS status Started for HL405070+5.p
94053.34/13016.36	% SZS status GaveUp for HL405070+5.p
94053.34/13016.36	% SZS status Ended for HL405070+5.p
94078.78/13019.59	% SZS status Started for HL405073+5.p
94078.78/13019.59	% SZS status GaveUp for HL405073+5.p
94078.78/13019.59	% SZS status Ended for HL405073+5.p
94104.97/13022.88	% SZS status Started for HL405069+4.p
94104.97/13022.88	% SZS status GaveUp for HL405069+4.p
94104.97/13022.88	eprover: CPU time limit exceeded, terminating
94104.97/13022.88	% SZS status Ended for HL405069+4.p
94104.97/13022.89	% SZS status Started for HL405074+4.p
94104.97/13022.89	% SZS status GaveUp for HL405074+4.p
94104.97/13022.89	eprover: CPU time limit exceeded, terminating
94104.97/13022.89	% SZS status Ended for HL405074+4.p
94104.97/13022.93	% SZS status Started for HL405074+5.p
94104.97/13022.93	% SZS status GaveUp for HL405074+5.p
94104.97/13022.93	% SZS status Ended for HL405074+5.p
94117.73/13024.55	% SZS status Started for HL405075+5.p
94117.73/13024.55	% SZS status GaveUp for HL405075+5.p
94117.73/13024.55	% SZS status Ended for HL405075+5.p
94153.25/13028.95	% SZS status Started for HL405076+5.p
94153.25/13028.95	% SZS status GaveUp for HL405076+5.p
94153.25/13028.95	% SZS status Ended for HL405076+5.p
94178.59/13032.14	% SZS status Started for HL405078+5.p
94178.59/13032.14	% SZS status GaveUp for HL405078+5.p
94178.59/13032.14	% SZS status Ended for HL405078+5.p
94182.02/13032.57	% SZS status Started for HL405073+4.p
94182.02/13032.57	% SZS status GaveUp for HL405073+4.p
94182.02/13032.57	eprover: CPU time limit exceeded, terminating
94182.02/13032.57	% SZS status Ended for HL405073+4.p
94194.33/13034.11	% SZS status Started for HL405080+5.p
94194.33/13034.11	% SZS status GaveUp for HL405080+5.p
94194.33/13034.11	% SZS status Ended for HL405080+5.p
94249.16/13041.11	% SZS status Started for HL405075+4.p
94249.16/13041.11	% SZS status GaveUp for HL405075+4.p
94249.16/13041.11	eprover: CPU time limit exceeded, terminating
94249.16/13041.11	% SZS status Ended for HL405075+4.p
94253.62/13041.61	% SZS status Started for HL405081+5.p
94253.62/13041.61	% SZS status GaveUp for HL405081+5.p
94253.62/13041.61	% SZS status Ended for HL405081+5.p
94259.58/13042.34	% SZS status Started for HL405076+4.p
94259.58/13042.34	% SZS status GaveUp for HL405076+4.p
94259.58/13042.34	eprover: CPU time limit exceeded, terminating
94259.58/13042.34	% SZS status Ended for HL405076+4.p
94271.50/13043.84	% SZS status Started for HL405082+5.p
94271.50/13043.84	% SZS status GaveUp for HL405082+5.p
94271.50/13043.84	% SZS status Ended for HL405082+5.p
94310.76/13048.82	% SZS status Started for HL405078+4.p
94310.76/13048.82	% SZS status GaveUp for HL405078+4.p
94310.76/13048.82	eprover: CPU time limit exceeded, terminating
94310.76/13048.82	% SZS status Ended for HL405078+4.p
94315.44/13049.34	% SZS status Started for HL405080+4.p
94315.44/13049.34	% SZS status GaveUp for HL405080+4.p
94315.44/13049.34	eprover: CPU time limit exceeded, terminating
94315.44/13049.34	% SZS status Ended for HL405080+4.p
94333.63/13051.66	% SZS status Started for HL405083+5.p
94333.63/13051.66	% SZS status GaveUp for HL405083+5.p
94333.63/13051.66	% SZS status Ended for HL405083+5.p
94338.46/13052.30	% SZS status Started for HL405083+4.p
94338.46/13052.30	% SZS status GaveUp for HL405083+4.p
94338.46/13052.30	eprover: CPU time limit exceeded, terminating
94338.46/13052.30	% SZS status Ended for HL405083+4.p
94347.75/13053.46	% SZS status Started for HL405084+4.p
94347.75/13053.46	% SZS status GaveUp for HL405084+4.p
94347.75/13053.46	eprover: CPU time limit exceeded, terminating
94347.75/13053.46	% SZS status Ended for HL405084+4.p
94349.87/13053.67	% SZS status Started for HL405084+5.p
94349.87/13053.67	% SZS status GaveUp for HL405084+5.p
94349.87/13053.67	% SZS status Ended for HL405084+5.p
94352.65/13054.11	% SZS status Started for HL405086+5.p
94352.65/13054.11	% SZS status Theorem for HL405086+5.p
94352.65/13054.11	% SZS status Ended for HL405086+5.p
94360.09/13055.01	% SZS status Started for HL405081+4.p
94360.09/13055.01	% SZS status GaveUp for HL405081+4.p
94360.09/13055.01	eprover: CPU time limit exceeded, terminating
94360.09/13055.01	% SZS status Ended for HL405081+4.p
94372.09/13056.50	% SZS status Started for HL405087+4.p
94372.09/13056.50	% SZS status GaveUp for HL405087+4.p
94372.09/13056.50	eprover: CPU time limit exceeded, terminating
94372.09/13056.50	% SZS status Ended for HL405087+4.p
94388.83/13058.63	% SZS status Started for HL405082+4.p
94388.83/13058.63	% SZS status GaveUp for HL405082+4.p
94388.83/13058.63	eprover: CPU time limit exceeded, terminating
94388.83/13058.63	% SZS status Ended for HL405082+4.p
94395.95/13059.49	% SZS status Started for HL405085+5.p
94395.95/13059.49	% SZS status GaveUp for HL405085+5.p
94395.95/13059.49	% SZS status Ended for HL405085+5.p
94399.49/13059.95	% SZS status Started for HL405085+4.p
94399.49/13059.95	% SZS status GaveUp for HL405085+4.p
94399.49/13059.95	eprover: CPU time limit exceeded, terminating
94399.49/13059.95	% SZS status Ended for HL405085+4.p
94420.59/13062.65	% SZS status Started for HL405086+4.p
94420.59/13062.65	% SZS status GaveUp for HL405086+4.p
94420.59/13062.65	eprover: CPU time limit exceeded, terminating
94420.59/13062.65	% SZS status Ended for HL405086+4.p
94430.77/13064.02	% SZS status Started for HL405087+5.p
94430.77/13064.02	% SZS status GaveUp for HL405087+5.p
94430.77/13064.02	% SZS status Ended for HL405087+5.p
94437.75/13064.98	% SZS status Started for HL405088+5.p
94437.75/13064.98	% SZS status GaveUp for HL405088+5.p
94437.75/13064.98	% SZS status Ended for HL405088+5.p
94440.90/13065.15	% SZS status Started for HL405088+4.p
94440.90/13065.15	% SZS status GaveUp for HL405088+4.p
94440.90/13065.15	eprover: CPU time limit exceeded, terminating
94440.90/13065.15	% SZS status Ended for HL405088+4.p
94459.98/13067.59	% SZS status Started for HL405089+4.p
94459.98/13067.59	% SZS status GaveUp for HL405089+4.p
94459.98/13067.59	eprover: CPU time limit exceeded, terminating
94459.98/13067.59	% SZS status Ended for HL405089+4.p
94467.31/13068.53	% SZS status Started for HL405089+5.p
94467.31/13068.53	% SZS status GaveUp for HL405089+5.p
94467.31/13068.53	% SZS status Ended for HL405089+5.p
94478.60/13069.89	% SZS status Started for HL405090+5.p
94478.60/13069.89	% SZS status GaveUp for HL405090+5.p
94478.60/13069.89	% SZS status Ended for HL405090+5.p
94484.31/13070.60	% SZS status Started for HL405090+4.p
94484.31/13070.60	% SZS status GaveUp for HL405090+4.p
94484.31/13070.60	eprover: CPU time limit exceeded, terminating
94484.31/13070.60	% SZS status Ended for HL405090+4.p
94510.31/13073.99	% SZS status Started for HL405091+4.p
94510.31/13073.99	% SZS status GaveUp for HL405091+4.p
94510.31/13073.99	eprover: CPU time limit exceeded, terminating
94510.31/13073.99	% SZS status Ended for HL405091+4.p
94511.55/13074.01	% SZS status Started for HL405091+5.p
94511.55/13074.01	% SZS status GaveUp for HL405091+5.p
94511.55/13074.01	% SZS status Ended for HL405091+5.p
94522.16/13075.33	% SZS status Started for HL405092+5.p
94522.16/13075.33	% SZS status GaveUp for HL405092+5.p
94522.16/13075.33	% SZS status Ended for HL405092+5.p
94524.42/13076.08	% SZS status Started for HL405092+4.p
94524.42/13076.08	% SZS status GaveUp for HL405092+4.p
94524.42/13076.08	eprover: CPU time limit exceeded, terminating
94524.42/13076.08	% SZS status Ended for HL405092+4.p
94536.24/13077.15	% SZS status Started for HL405097+4.p
94536.24/13077.15	% SZS status GaveUp for HL405097+4.p
94536.24/13077.15	eprover: CPU time limit exceeded, terminating
94536.24/13077.15	% SZS status Ended for HL405097+4.p
94546.66/13078.45	% SZS status Started for HL405093+5.p
94546.66/13078.45	% SZS status GaveUp for HL405093+5.p
94546.66/13078.45	% SZS status Ended for HL405093+5.p
94547.45/13078.55	% SZS status Started for HL405093+4.p
94547.45/13078.55	% SZS status GaveUp for HL405093+4.p
94547.45/13078.55	eprover: CPU time limit exceeded, terminating
94547.45/13078.55	% SZS status Ended for HL405093+4.p
94560.52/13080.19	% SZS status Started for HL405100+4.p
94560.52/13080.19	% SZS status GaveUp for HL405100+4.p
94560.52/13080.19	eprover: CPU time limit exceeded, terminating
94560.52/13080.19	% SZS status Ended for HL405100+4.p
94562.26/13080.59	% SZS status Started for HL405095+5.p
94562.26/13080.59	% SZS status GaveUp for HL405095+5.p
94562.26/13080.59	% SZS status Ended for HL405095+5.p
94574.00/13080.85	% SZS status Started for HL405095+4.p
94574.00/13080.85	% SZS status GaveUp for HL405095+4.p
94574.00/13080.85	eprover: CPU time limit exceeded, terminating
94574.00/13080.85	% SZS status Ended for HL405095+4.p
94597.95/13083.95	% SZS status Started for HL405097+5.p
94597.95/13083.95	% SZS status GaveUp for HL405097+5.p
94597.95/13083.95	% SZS status Ended for HL405097+5.p
94618.45/13086.44	% SZS status Started for HL405099+4.p
94618.45/13086.44	% SZS status GaveUp for HL405099+4.p
94618.45/13086.44	eprover: CPU time limit exceeded, terminating
94618.45/13086.44	% SZS status Ended for HL405099+4.p
94619.09/13086.55	% SZS status Started for HL405099+5.p
94619.09/13086.55	% SZS status GaveUp for HL405099+5.p
94619.09/13086.55	% SZS status Ended for HL405099+5.p
94633.94/13088.41	% SZS status Started for HL405100+5.p
94633.94/13088.41	% SZS status GaveUp for HL405100+5.p
94633.94/13088.41	% SZS status Ended for HL405100+5.p
94643.66/13089.67	% SZS status Started for HL405104+4.p
94643.66/13089.67	% SZS status GaveUp for HL405104+4.p
94643.66/13089.67	eprover: CPU time limit exceeded, terminating
94643.66/13089.67	% SZS status Ended for HL405104+4.p
94643.66/13089.68	% SZS status Started for HL405101+4.p
94643.66/13089.68	% SZS status GaveUp for HL405101+4.p
94643.66/13089.68	eprover: CPU time limit exceeded, terminating
94643.66/13089.68	% SZS status Ended for HL405101+4.p
94648.06/13090.18	% SZS status Started for HL405101+5.p
94648.06/13090.18	% SZS status GaveUp for HL405101+5.p
94648.06/13090.18	% SZS status Ended for HL405101+5.p
94652.87/13090.80	% SZS status Started for HL405102+5.p
94652.87/13090.80	% SZS status GaveUp for HL405102+5.p
94652.87/13090.80	% SZS status Ended for HL405102+5.p
94659.81/13091.69	% SZS status Started for HL405102+4.p
94659.81/13091.69	% SZS status GaveUp for HL405102+4.p
94659.81/13091.69	eprover: CPU time limit exceeded, terminating
94659.81/13091.69	% SZS status Ended for HL405102+4.p
94667.90/13092.72	% SZS status Started for HL405105+4.p
94667.90/13092.72	% SZS status GaveUp for HL405105+4.p
94667.90/13092.72	eprover: CPU time limit exceeded, terminating
94667.90/13092.72	% SZS status Ended for HL405105+4.p
94685.54/13095.04	% SZS status Started for HL405103+4.p
94685.54/13095.04	% SZS status GaveUp for HL405103+4.p
94685.54/13095.04	eprover: CPU time limit exceeded, terminating
94685.54/13095.04	% SZS status Ended for HL405103+4.p
94697.71/13096.43	% SZS status Started for HL405103+5.p
94697.71/13096.43	% SZS status GaveUp for HL405103+5.p
94697.71/13096.43	% SZS status Ended for HL405103+5.p
94713.26/13098.45	% SZS status Started for HL405104+5.p
94713.26/13098.45	% SZS status GaveUp for HL405104+5.p
94713.26/13098.45	% SZS status Ended for HL405104+5.p
94724.70/13099.80	% SZS status Started for HL405108+4.p
94724.70/13099.80	% SZS status GaveUp for HL405108+4.p
94724.70/13099.80	eprover: CPU time limit exceeded, terminating
94724.70/13099.80	% SZS status Ended for HL405108+4.p
94725.34/13099.89	% SZS status Started for HL405105+5.p
94725.34/13099.89	% SZS status GaveUp for HL405105+5.p
94725.34/13099.89	% SZS status Ended for HL405105+5.p
94732.82/13100.82	% SZS status Started for HL405107+5.p
94732.82/13100.82	% SZS status GaveUp for HL405107+5.p
94732.82/13100.82	% SZS status Ended for HL405107+5.p
94736.34/13101.31	% SZS status Started for HL405107+4.p
94736.34/13101.31	% SZS status GaveUp for HL405107+4.p
94736.34/13101.31	eprover: CPU time limit exceeded, terminating
94736.34/13101.31	% SZS status Ended for HL405107+4.p
94746.44/13102.69	% SZS status Started for HL405108+5.p
94746.44/13102.69	% SZS status GaveUp for HL405108+5.p
94746.44/13102.69	% SZS status Ended for HL405108+5.p
94749.46/13102.93	% SZS status Started for HL405111+4.p
94749.46/13102.93	% SZS status GaveUp for HL405111+4.p
94749.46/13102.93	eprover: CPU time limit exceeded, terminating
94749.46/13102.93	% SZS status Ended for HL405111+4.p
94754.39/13103.56	% SZS status Started for HL405109+4.p
94754.39/13103.56	% SZS status GaveUp for HL405109+4.p
94754.39/13103.56	eprover: CPU time limit exceeded, terminating
94754.39/13103.56	% SZS status Ended for HL405109+4.p
94776.84/13106.38	% SZS status Started for HL405109+5.p
94776.84/13106.38	% SZS status GaveUp for HL405109+5.p
94776.84/13106.38	% SZS status Ended for HL405109+5.p
94801.38/13109.58	% SZS status Started for HL405110+4.p
94801.38/13109.58	% SZS status GaveUp for HL405110+4.p
94801.38/13109.58	eprover: CPU time limit exceeded, terminating
94801.38/13109.58	% SZS status Ended for HL405110+4.p
94813.49/13109.77	% SZS status Started for HL405110+5.p
94813.49/13109.77	% SZS status GaveUp for HL405110+5.p
94813.49/13109.77	% SZS status Ended for HL405110+5.p
94822.47/13110.84	% SZS status Started for HL405111+5.p
94822.47/13110.84	% SZS status GaveUp for HL405111+5.p
94822.47/13110.84	% SZS status Ended for HL405111+5.p
94833.95/13112.38	% SZS status Started for HL405112+4.p
94833.95/13112.38	% SZS status GaveUp for HL405112+4.p
94833.95/13112.38	eprover: CPU time limit exceeded, terminating
94833.95/13112.38	% SZS status Ended for HL405112+4.p
94836.76/13112.65	% SZS status Started for HL405112+5.p
94836.76/13112.65	% SZS status GaveUp for HL405112+5.p
94836.76/13112.65	% SZS status Ended for HL405112+5.p
94842.17/13113.41	% SZS status Started for HL405113+5.p
94842.17/13113.41	% SZS status GaveUp for HL405113+5.p
94842.17/13113.41	% SZS status Ended for HL405113+5.p
94850.86/13114.43	% SZS status Started for HL405113+4.p
94850.86/13114.43	% SZS status GaveUp for HL405113+4.p
94850.86/13114.43	eprover: CPU time limit exceeded, terminating
94850.86/13114.43	% SZS status Ended for HL405113+4.p
94875.04/13117.49	% SZS status Started for HL405114+4.p
94875.04/13117.49	% SZS status GaveUp for HL405114+4.p
94875.04/13117.49	eprover: CPU time limit exceeded, terminating
94875.04/13117.49	% SZS status Ended for HL405114+4.p
94889.77/13119.32	% SZS status Started for HL405114+5.p
94889.77/13119.32	% SZS status GaveUp for HL405114+5.p
94889.77/13119.32	% SZS status Ended for HL405114+5.p
94896.54/13120.25	% SZS status Started for HL405115+5.p
94896.54/13120.25	% SZS status GaveUp for HL405115+5.p
94896.54/13120.25	% SZS status Ended for HL405115+5.p
94898.94/13120.55	% SZS status Started for HL405115+4.p
94898.94/13120.55	% SZS status GaveUp for HL405115+4.p
94898.94/13120.55	eprover: CPU time limit exceeded, terminating
94898.94/13120.55	% SZS status Ended for HL405115+4.p
94909.83/13121.84	% SZS status Started for HL405116+5.p
94909.83/13121.84	% SZS status GaveUp for HL405116+5.p
94909.83/13121.84	% SZS status Ended for HL405116+5.p
94923.38/13123.60	% SZS status Started for HL405117+5.p
94923.38/13123.60	% SZS status GaveUp for HL405117+5.p
94923.38/13123.60	% SZS status Ended for HL405117+5.p
94963.38/13128.60	% SZS status Started for HL405119+5.p
94963.38/13128.60	% SZS status GaveUp for HL405119+5.p
94963.38/13128.60	% SZS status Ended for HL405119+5.p
94972.02/13129.66	% SZS status Started for HL405120+5.p
94972.02/13129.66	% SZS status GaveUp for HL405120+5.p
94972.02/13129.66	% SZS status Ended for HL405120+5.p
94990.55/13132.00	% SZS status Started for HL405121+4.p
94990.55/13132.00	% SZS status GaveUp for HL405121+4.p
94990.55/13132.00	eprover: CPU time limit exceeded, terminating
94990.55/13132.00	% SZS status Ended for HL405121+4.p
94996.50/13132.75	% SZS status Started for HL405121+5.p
94996.50/13132.75	% SZS status GaveUp for HL405121+5.p
94996.50/13132.75	% SZS status Ended for HL405121+5.p
95043.06/13138.61	% SZS status Started for HL405116+4.p
95043.06/13138.61	% SZS status GaveUp for HL405116+4.p
95043.06/13138.61	eprover: CPU time limit exceeded, terminating
95043.06/13138.61	% SZS status Ended for HL405116+4.p
95045.25/13138.89	% SZS status Started for HL405122+5.p
95045.25/13138.89	% SZS status GaveUp for HL405122+5.p
95045.25/13138.89	% SZS status Ended for HL405122+5.p
95051.75/13139.67	% SZS status Started for HL405117+4.p
95051.75/13139.67	% SZS status GaveUp for HL405117+4.p
95051.75/13139.67	eprover: CPU time limit exceeded, terminating
95051.75/13139.67	% SZS status Ended for HL405117+4.p
95069.70/13141.94	% SZS status Started for HL405123+5.p
95069.70/13141.94	% SZS status GaveUp for HL405123+5.p
95069.70/13141.94	% SZS status Ended for HL405123+5.p
95084.20/13143.82	% SZS status Started for HL405119+4.p
95084.20/13143.82	% SZS status GaveUp for HL405119+4.p
95084.20/13143.82	eprover: CPU time limit exceeded, terminating
95084.20/13143.82	% SZS status Ended for HL405119+4.p
95105.30/13146.49	% SZS status Started for HL405120+4.p
95105.30/13146.49	% SZS status GaveUp for HL405120+4.p
95105.30/13146.49	eprover: CPU time limit exceeded, terminating
95105.30/13146.49	% SZS status Ended for HL405120+4.p
95108.45/13146.85	% SZS status Started for HL405122+4.p
95108.45/13146.85	% SZS status GaveUp for HL405122+4.p
95108.45/13146.85	eprover: CPU time limit exceeded, terminating
95108.45/13146.85	% SZS status Ended for HL405122+4.p
95118.51/13148.20	% SZS status Started for HL405125+5.p
95118.51/13148.20	% SZS status GaveUp for HL405125+5.p
95118.51/13148.20	% SZS status Ended for HL405125+5.p
95124.91/13148.90	% SZS status Started for HL405125+4.p
95124.91/13148.90	% SZS status GaveUp for HL405125+4.p
95124.91/13148.90	eprover: CPU time limit exceeded, terminating
95124.91/13148.90	% SZS status Ended for HL405125+4.p
95132.42/13149.93	% SZS status Started for HL405126+4.p
95132.42/13149.93	% SZS status GaveUp for HL405126+4.p
95132.42/13149.93	eprover: CPU time limit exceeded, terminating
95132.42/13149.93	% SZS status Ended for HL405126+4.p
95144.99/13151.49	% SZS status Started for HL405126+5.p
95144.99/13151.49	% SZS status GaveUp for HL405126+5.p
95144.99/13151.49	% SZS status Ended for HL405126+5.p
95166.07/13154.11	% SZS status Started for HL405127+4.p
95166.07/13154.11	% SZS status GaveUp for HL405127+4.p
95166.07/13154.11	eprover: CPU time limit exceeded, terminating
95166.07/13154.11	% SZS status Ended for HL405127+4.p
95178.52/13155.70	% SZS status Started for HL405127+5.p
95178.52/13155.70	% SZS status GaveUp for HL405127+5.p
95178.52/13155.70	% SZS status Ended for HL405127+5.p
95192.28/13157.43	% SZS status Started for HL405128+5.p
95192.28/13157.43	% SZS status GaveUp for HL405128+5.p
95192.28/13157.43	% SZS status Ended for HL405128+5.p
95202.00/13158.66	% SZS status Started for HL405123+4.p
95202.00/13158.66	% SZS status GaveUp for HL405123+4.p
95202.00/13158.66	eprover: CPU time limit exceeded, terminating
95202.00/13158.66	% SZS status Ended for HL405123+4.p
95205.62/13159.10	% SZS status Started for HL405129+4.p
95205.62/13159.10	% SZS status GaveUp for HL405129+4.p
95205.62/13159.10	eprover: CPU time limit exceeded, terminating
95205.62/13159.10	% SZS status Ended for HL405129+4.p
95207.94/13159.35	% SZS status Started for HL405129+5.p
95207.94/13159.35	% SZS status GaveUp for HL405129+5.p
95207.94/13159.35	% SZS status Ended for HL405129+5.p
95226.74/13161.76	% SZS status Started for HL405130+4.p
95226.74/13161.76	% SZS status GaveUp for HL405130+4.p
95226.74/13161.76	eprover: CPU time limit exceeded, terminating
95226.74/13161.76	% SZS status Ended for HL405130+4.p
95238.95/13163.27	% SZS status Started for HL405130+5.p
95238.95/13163.27	% SZS status GaveUp for HL405130+5.p
95238.95/13163.27	% SZS status Ended for HL405130+5.p
95267.73/13166.96	% SZS status Started for HL405131+5.p
95267.73/13166.96	% SZS status GaveUp for HL405131+5.p
95267.73/13166.96	% SZS status Ended for HL405131+5.p
95283.03/13168.84	% SZS status Started for HL405132+5.p
95283.03/13168.84	% SZS status GaveUp for HL405132+5.p
95283.03/13168.84	% SZS status Ended for HL405132+5.p
95285.07/13169.16	% SZS status Started for HL405132+4.p
95285.07/13169.16	% SZS status GaveUp for HL405132+4.p
95285.07/13169.16	eprover: CPU time limit exceeded, terminating
95285.07/13169.16	% SZS status Ended for HL405132+4.p
95301.13/13171.13	% SZS status Started for HL405133+5.p
95301.13/13171.13	% SZS status GaveUp for HL405133+5.p
95301.13/13171.13	% SZS status Ended for HL405133+5.p
95302.69/13171.35	% SZS status Started for HL405128+4.p
95302.69/13171.35	% SZS status GaveUp for HL405128+4.p
95302.69/13171.35	eprover: CPU time limit exceeded, terminating
95302.69/13171.35	% SZS status Ended for HL405128+4.p
95343.38/13176.49	% SZS status Started for HL405134+5.p
95343.38/13176.49	% SZS status GaveUp for HL405134+5.p
95343.38/13176.49	% SZS status Ended for HL405134+5.p
95349.71/13177.26	% SZS status Started for HL405136+5.p
95349.71/13177.26	% SZS status Theorem for HL405136+5.p
95349.71/13177.26	% SZS status Ended for HL405136+5.p
95361.10/13178.71	% SZS status Started for HL405135+5.p
95361.10/13178.71	% SZS status GaveUp for HL405135+5.p
95361.10/13178.71	% SZS status Ended for HL405135+5.p
95363.54/13178.99	% SZS status Started for HL405135+4.p
95363.54/13178.99	% SZS status GaveUp for HL405135+4.p
95363.54/13178.99	eprover: CPU time limit exceeded, terminating
95363.54/13178.99	% SZS status Ended for HL405135+4.p
95370.09/13179.86	% SZS status Started for HL405131+4.p
95370.09/13179.86	% SZS status GaveUp for HL405131+4.p
95370.09/13179.86	eprover: CPU time limit exceeded, terminating
95370.09/13179.86	% SZS status Ended for HL405131+4.p
95384.35/13181.64	% SZS status Started for HL405134+4.p
95384.35/13181.64	% SZS status GaveUp for HL405134+4.p
95384.35/13181.64	eprover: CPU time limit exceeded, terminating
95384.35/13181.64	% SZS status Ended for HL405134+4.p
95415.40/13185.60	% SZS status Started for HL405133+4.p
95415.40/13185.60	% SZS status GaveUp for HL405133+4.p
95415.40/13185.60	eprover: CPU time limit exceeded, terminating
95415.40/13185.60	% SZS status Ended for HL405133+4.p
95417.54/13185.77	% SZS status Started for HL405138+5.p
95417.54/13185.77	% SZS status Theorem for HL405138+5.p
95417.54/13185.77	% SZS status Ended for HL405138+5.p
95425.06/13186.72	% SZS status Started for HL405137+5.p
95425.06/13186.72	% SZS status GaveUp for HL405137+5.p
95425.06/13186.72	% SZS status Ended for HL405137+5.p
95430.88/13187.45	% SZS status Started for HL405139+5.p
95430.88/13187.45	% SZS status Theorem for HL405139+5.p
95430.88/13187.45	% SZS status Ended for HL405139+5.p
95443.91/13189.15	% SZS status Started for HL405138+4.p
95443.91/13189.15	% SZS status GaveUp for HL405138+4.p
95443.91/13189.15	eprover: CPU time limit exceeded, terminating
95443.91/13189.15	% SZS status Ended for HL405138+4.p
95464.55/13191.79	% SZS status Started for HL405140+5.p
95464.55/13191.79	% SZS status Theorem for HL405140+5.p
95464.55/13191.79	% SZS status Ended for HL405140+5.p
95485.38/13194.32	% SZS status Started for HL405142+5.p
95485.38/13194.32	% SZS status Theorem for HL405142+5.p
95485.38/13194.32	% SZS status Ended for HL405142+5.p
95509.22/13197.43	% SZS status Started for HL405136+4.p
95509.22/13197.43	% SZS status GaveUp for HL405136+4.p
95509.22/13197.43	eprover: CPU time limit exceeded, terminating
95509.22/13197.43	% SZS status Ended for HL405136+4.p
95510.20/13197.61	% SZS status Started for HL405143+5.p
95510.20/13197.61	% SZS status Theorem for HL405143+5.p
95510.20/13197.61	% SZS status Ended for HL405143+5.p
95550.16/13202.48	% SZS status Started for HL405137+4.p
95550.16/13202.48	% SZS status GaveUp for HL405137+4.p
95550.16/13202.48	eprover: CPU time limit exceeded, terminating
95550.16/13202.48	% SZS status Ended for HL405137+4.p
95563.26/13204.33	% SZS status Started for HL405144+5.p
95563.26/13204.33	% SZS status Theorem for HL405144+5.p
95563.26/13204.33	% SZS status Ended for HL405144+5.p
95569.82/13204.97	% SZS status Started for HL405144+4.p
95569.82/13204.97	% SZS status GaveUp for HL405144+4.p
95569.82/13204.97	eprover: CPU time limit exceeded, terminating
95569.82/13204.97	% SZS status Ended for HL405144+4.p
95577.20/13205.96	% SZS status Started for HL405139+4.p
95577.20/13205.96	% SZS status GaveUp for HL405139+4.p
95577.20/13205.96	eprover: CPU time limit exceeded, terminating
95577.20/13205.96	% SZS status Ended for HL405139+4.p
95603.80/13209.34	% SZS status Started for HL405145+5.p
95603.80/13209.34	% SZS status Theorem for HL405145+5.p
95603.80/13209.34	% SZS status Ended for HL405145+5.p
95624.61/13211.83	% SZS status Started for HL405140+4.p
95624.61/13211.83	% SZS status GaveUp for HL405140+4.p
95624.61/13211.83	eprover: CPU time limit exceeded, terminating
95624.61/13211.83	% SZS status Ended for HL405140+4.p
95633.23/13212.91	% SZS status Started for HL405142+4.p
95633.23/13212.91	% SZS status GaveUp for HL405142+4.p
95633.23/13212.91	eprover: CPU time limit exceeded, terminating
95633.23/13212.91	% SZS status Ended for HL405142+4.p
95645.15/13214.49	% SZS status Started for HL405147+5.p
95645.15/13214.49	% SZS status GaveUp for HL405147+5.p
95645.15/13214.49	% SZS status Ended for HL405147+5.p
95650.96/13215.21	% SZS status Started for HL405143+4.p
95650.96/13215.21	% SZS status GaveUp for HL405143+4.p
95650.96/13215.21	eprover: CPU time limit exceeded, terminating
95650.96/13215.21	% SZS status Ended for HL405143+4.p
95657.17/13215.95	% SZS status Started for HL405145+4.p
95657.17/13215.95	% SZS status GaveUp for HL405145+4.p
95657.17/13215.95	eprover: CPU time limit exceeded, terminating
95657.17/13215.95	% SZS status Ended for HL405145+4.p
95658.89/13216.20	% SZS status Started for HL405149+4.p
95658.89/13216.20	% SZS status GaveUp for HL405149+4.p
95658.89/13216.20	eprover: CPU time limit exceeded, terminating
95658.89/13216.20	% SZS status Ended for HL405149+4.p
95679.94/13218.84	% SZS status Started for HL405149+5.p
95679.94/13218.84	% SZS status GaveUp for HL405149+5.p
95679.94/13218.84	% SZS status Ended for HL405149+5.p
95708.09/13222.36	% SZS status Started for HL405150+5.p
95708.09/13222.36	% SZS status GaveUp for HL405150+5.p
95708.09/13222.36	% SZS status Ended for HL405150+5.p
95713.55/13223.13	% SZS status Started for HL405152+5.p
95713.55/13223.13	% SZS status Theorem for HL405152+5.p
95713.55/13223.13	% SZS status Ended for HL405152+5.p
95728.14/13224.96	% SZS status Started for HL405151+5.p
95728.14/13224.96	% SZS status GaveUp for HL405151+5.p
95728.14/13224.96	% SZS status Ended for HL405151+5.p
95741.99/13226.61	% SZS status Started for HL405152+4.p
95741.99/13226.61	% SZS status GaveUp for HL405152+4.p
95741.99/13226.61	eprover: CPU time limit exceeded, terminating
95741.99/13226.61	% SZS status Ended for HL405152+4.p
95772.53/13230.47	% SZS status Started for HL405147+4.p
95772.53/13230.47	% SZS status GaveUp for HL405147+4.p
95772.53/13230.47	eprover: CPU time limit exceeded, terminating
95772.53/13230.47	% SZS status Ended for HL405147+4.p
95783.79/13231.92	% SZS status Started for HL405153+5.p
95783.79/13231.92	% SZS status GaveUp for HL405153+5.p
95783.79/13231.92	% SZS status Ended for HL405153+5.p
95804.00/13234.46	% SZS status Started for HL405154+5.p
95804.00/13234.46	% SZS status GaveUp for HL405154+5.p
95804.00/13234.46	% SZS status Ended for HL405154+5.p
95832.09/13237.96	% SZS status Started for HL405150+4.p
95832.09/13237.96	% SZS status GaveUp for HL405150+4.p
95832.09/13237.96	eprover: CPU time limit exceeded, terminating
95832.09/13237.96	% SZS status Ended for HL405150+4.p
95850.10/13240.21	% SZS status Started for HL405155+5.p
95850.10/13240.21	% SZS status GaveUp for HL405155+5.p
95850.10/13240.21	% SZS status Ended for HL405155+5.p
95854.40/13240.79	% SZS status Started for HL405151+4.p
95854.40/13240.79	% SZS status GaveUp for HL405151+4.p
95854.40/13240.79	eprover: CPU time limit exceeded, terminating
95854.40/13240.79	% SZS status Ended for HL405151+4.p
95880.09/13244.05	% SZS status Started for HL405156+5.p
95880.09/13244.05	% SZS status GaveUp for HL405156+5.p
95880.09/13244.05	% SZS status Ended for HL405156+5.p
95888.12/13245.00	% SZS status Started for HL405153+4.p
95888.12/13245.00	% SZS status GaveUp for HL405153+4.p
95888.12/13245.00	eprover: CPU time limit exceeded, terminating
95888.12/13245.00	% SZS status Ended for HL405153+4.p
95913.06/13248.17	% SZS status Started for HL405157+4.p
95913.06/13248.17	% SZS status GaveUp for HL405157+4.p
95913.06/13248.17	eprover: CPU time limit exceeded, terminating
95913.06/13248.17	% SZS status Ended for HL405157+4.p
95922.65/13249.36	% SZS status Started for HL405154+4.p
95922.65/13249.36	% SZS status GaveUp for HL405154+4.p
95922.65/13249.36	eprover: CPU time limit exceeded, terminating
95922.65/13249.36	% SZS status Ended for HL405154+4.p
95925.99/13249.76	% SZS status Started for HL405157+5.p
95925.99/13249.76	% SZS status GaveUp for HL405157+5.p
95925.99/13249.76	% SZS status Ended for HL405157+5.p
95951.48/13252.95	% SZS status Started for HL405155+4.p
95951.48/13252.95	% SZS status GaveUp for HL405155+4.p
95951.48/13252.95	eprover: CPU time limit exceeded, terminating
95951.48/13252.95	% SZS status Ended for HL405155+4.p
95991.84/13258.10	% SZS status Started for HL405156+4.p
95991.84/13258.10	% SZS status GaveUp for HL405156+4.p
95991.84/13258.10	eprover: CPU time limit exceeded, terminating
95991.84/13258.10	% SZS status Ended for HL405156+4.p
96001.33/13259.25	% SZS status Started for HL405160+5.p
96001.33/13259.25	% SZS status GaveUp for HL405160+5.p
96001.33/13259.25	% SZS status Ended for HL405160+5.p
96058.14/13267.05	% SZS status Started for HL405158+4.p
96058.14/13267.05	% SZS status GaveUp for HL405158+4.p
96058.14/13267.05	eprover: CPU time limit exceeded, terminating
96058.14/13267.05	% SZS status Ended for HL405158+4.p
96081.89/13270.08	% SZS status Started for HL405164+4.p
96081.89/13270.08	% SZS status GaveUp for HL405164+4.p
96081.89/13270.08	eprover: CPU time limit exceeded, terminating
96081.89/13270.08	% SZS status Ended for HL405164+4.p
96085.36/13270.50	% SZS status Started for HL405158+5.p
96085.36/13270.50	% SZS status GaveUp for HL405158+5.p
96085.36/13270.50	eprover: CPU time limit exceeded, terminating
96085.36/13270.50	% SZS status Ended for HL405158+5.p
96093.85/13271.58	% SZS status Started for HL405159+4.p
96093.85/13271.58	% SZS status GaveUp for HL405159+4.p
96093.85/13271.58	eprover: CPU time limit exceeded, terminating
96093.85/13271.58	% SZS status Ended for HL405159+4.p
96118.34/13274.77	% SZS status Started for HL405164+5.p
96118.34/13274.77	% SZS status Theorem for HL405164+5.p
96118.34/13274.77	% SZS status Ended for HL405164+5.p
96129.25/13275.26	% SZS status Started for HL405159+5.p
96129.25/13275.26	% SZS status GaveUp for HL405159+5.p
96129.25/13275.26	eprover: CPU time limit exceeded, terminating
96129.25/13275.26	% SZS status Ended for HL405159+5.p
96141.29/13276.80	% SZS status Started for HL405160+4.p
96141.29/13276.80	% SZS status GaveUp for HL405160+4.p
96141.29/13276.80	eprover: CPU time limit exceeded, terminating
96141.29/13276.80	% SZS status Ended for HL405160+4.p
96157.24/13278.95	% SZS status Started for HL405165+5.p
96157.24/13278.95	% SZS status Theorem for HL405165+5.p
96157.24/13278.95	% SZS status Ended for HL405165+5.p
96162.38/13279.79	% SZS status Started for HL405162+4.p
96162.38/13279.79	% SZS status GaveUp for HL405162+4.p
96162.38/13279.79	eprover: CPU time limit exceeded, terminating
96162.38/13279.79	% SZS status Ended for HL405162+4.p
96178.61/13281.82	% SZS status Started for HL405165+4.p
96178.61/13281.82	% SZS status GaveUp for HL405165+4.p
96178.61/13281.82	eprover: CPU time limit exceeded, terminating
96178.61/13281.82	% SZS status Ended for HL405165+4.p
96190.22/13283.30	% SZS status Started for HL405166+4.p
96190.22/13283.30	% SZS status GaveUp for HL405166+4.p
96190.22/13283.30	eprover: CPU time limit exceeded, terminating
96190.22/13283.30	% SZS status Ended for HL405166+4.p
96196.34/13284.14	% SZS status Started for HL405162+5.p
96196.34/13284.14	% SZS status GaveUp for HL405162+5.p
96196.34/13284.14	eprover: CPU time limit exceeded, terminating
96196.34/13284.14	% SZS status Ended for HL405162+5.p
96215.61/13286.63	% SZS status Started for HL405167+4.p
96215.61/13286.63	% SZS status GaveUp for HL405167+4.p
96215.61/13286.63	eprover: CPU time limit exceeded, terminating
96215.61/13286.63	% SZS status Ended for HL405167+4.p
96215.61/13286.64	% SZS status Started for HL405167+5.p
96215.61/13286.64	% SZS status GaveUp for HL405167+5.p
96215.61/13286.64	% SZS status Ended for HL405167+5.p
96238.45/13289.58	% SZS status Started for HL405168+5.p
96238.45/13289.58	% SZS status GaveUp for HL405168+5.p
96238.45/13289.58	% SZS status Ended for HL405168+5.p
96242.89/13290.12	% SZS status Started for HL405168+4.p
96242.89/13290.12	% SZS status GaveUp for HL405168+4.p
96242.89/13290.12	eprover: CPU time limit exceeded, terminating
96242.89/13290.12	% SZS status Ended for HL405168+4.p
96263.62/13292.77	% SZS status Started for HL405169+4.p
96263.62/13292.77	% SZS status GaveUp for HL405169+4.p
96263.62/13292.77	eprover: CPU time limit exceeded, terminating
96263.62/13292.77	% SZS status Ended for HL405169+4.p
96268.41/13293.44	% SZS status Started for HL405169+5.p
96268.41/13293.44	% SZS status GaveUp for HL405169+5.p
96268.41/13293.44	% SZS status Ended for HL405169+5.p
96283.87/13295.34	% SZS status Started for HL405170+4.p
96283.87/13295.34	% SZS status GaveUp for HL405170+4.p
96283.87/13295.34	eprover: CPU time limit exceeded, terminating
96283.87/13295.34	% SZS status Ended for HL405170+4.p
96291.05/13296.22	% SZS status Started for HL405170+5.p
96291.05/13296.22	% SZS status GaveUp for HL405170+5.p
96291.05/13296.22	% SZS status Ended for HL405170+5.p
96299.79/13297.34	% SZS status Started for HL405171+4.p
96299.79/13297.34	% SZS status GaveUp for HL405171+4.p
96299.79/13297.34	eprover: CPU time limit exceeded, terminating
96299.79/13297.34	% SZS status Ended for HL405171+4.p
96316.35/13299.43	% SZS status Started for HL405171+5.p
96316.35/13299.43	% SZS status GaveUp for HL405171+5.p
96316.35/13299.43	% SZS status Ended for HL405171+5.p
96318.02/13299.62	% SZS status Started for HL405166+5.p
96318.02/13299.62	% SZS status GaveUp for HL405166+5.p
96318.02/13299.62	% SZS status Ended for HL405166+5.p
96325.88/13300.65	% SZS status Started for HL405172+4.p
96325.88/13300.65	% SZS status GaveUp for HL405172+4.p
96325.88/13300.65	eprover: CPU time limit exceeded, terminating
96325.88/13300.65	% SZS status Ended for HL405172+4.p
96341.77/13302.70	% SZS status Started for HL405172+5.p
96341.77/13302.70	% SZS status GaveUp for HL405172+5.p
96341.77/13302.70	% SZS status Ended for HL405172+5.p
96360.63/13305.00	% SZS status Started for HL405173+5.p
96360.63/13305.00	% SZS status GaveUp for HL405173+5.p
96360.63/13305.00	% SZS status Ended for HL405173+5.p
96377.48/13307.19	% SZS status Started for HL405174+5.p
96377.48/13307.19	% SZS status GaveUp for HL405174+5.p
96377.48/13307.19	% SZS status Ended for HL405174+5.p
96391.92/13309.37	% SZS status Started for HL405175+5.p
96391.92/13309.37	% SZS status GaveUp for HL405175+5.p
96391.92/13309.37	% SZS status Ended for HL405175+5.p
96417.23/13312.15	% SZS status Started for HL405176+5.p
96417.23/13312.15	% SZS status GaveUp for HL405176+5.p
96417.23/13312.15	% SZS status Ended for HL405176+5.p
96441.62/13315.20	% SZS status Started for HL405177+4.p
96441.62/13315.20	% SZS status GaveUp for HL405177+4.p
96441.62/13315.20	eprover: CPU time limit exceeded, terminating
96441.62/13315.20	% SZS status Ended for HL405177+4.p
96453.75/13316.78	% SZS status Started for HL405177+5.p
96453.75/13316.78	% SZS status GaveUp for HL405177+5.p
96453.75/13316.78	% SZS status Ended for HL405177+5.p
96476.68/13319.62	% SZS status Started for HL405173+4.p
96476.68/13319.62	% SZS status GaveUp for HL405173+4.p
96476.68/13319.62	eprover: CPU time limit exceeded, terminating
96476.68/13319.62	% SZS status Ended for HL405173+4.p
96494.12/13321.81	% SZS status Started for HL405178+5.p
96494.12/13321.81	% SZS status GaveUp for HL405178+5.p
96494.12/13321.81	% SZS status Ended for HL405178+5.p
96499.67/13322.54	% SZS status Started for HL405174+4.p
96499.67/13322.54	% SZS status GaveUp for HL405174+4.p
96499.67/13322.54	eprover: CPU time limit exceeded, terminating
96499.67/13322.54	% SZS status Ended for HL405174+4.p
96527.34/13326.03	% SZS status Started for HL405175+4.p
96527.34/13326.03	% SZS status GaveUp for HL405175+4.p
96527.34/13326.03	eprover: CPU time limit exceeded, terminating
96527.34/13326.03	% SZS status Ended for HL405175+4.p
96528.77/13326.23	% SZS status Started for HL405179+5.p
96528.77/13326.23	% SZS status GaveUp for HL405179+5.p
96528.77/13326.23	% SZS status Ended for HL405179+5.p
96533.55/13326.78	% SZS status Started for HL405176+4.p
96533.55/13326.78	% SZS status GaveUp for HL405176+4.p
96533.55/13326.78	eprover: CPU time limit exceeded, terminating
96533.55/13326.78	% SZS status Ended for HL405176+4.p
96571.81/13331.63	% SZS status Started for HL405180+5.p
96571.81/13331.63	% SZS status GaveUp for HL405180+5.p
96571.81/13331.63	% SZS status Ended for HL405180+5.p
96581.43/13332.87	% SZS status Started for HL405181+4.p
96581.43/13332.87	% SZS status GaveUp for HL405181+4.p
96581.43/13332.87	eprover: CPU time limit exceeded, terminating
96581.43/13332.87	% SZS status Ended for HL405181+4.p
96601.57/13335.43	% SZS status Started for HL405178+4.p
96601.57/13335.43	% SZS status GaveUp for HL405178+4.p
96601.57/13335.43	eprover: CPU time limit exceeded, terminating
96601.57/13335.43	% SZS status Ended for HL405178+4.p
96602.45/13335.57	% SZS status Started for HL405181+5.p
96602.45/13335.57	% SZS status GaveUp for HL405181+5.p
96602.45/13335.57	% SZS status Ended for HL405181+5.p
96608.17/13336.25	% SZS status Started for HL405182+5.p
96608.17/13336.25	% SZS status GaveUp for HL405182+5.p
96608.17/13336.25	% SZS status Ended for HL405182+5.p
96614.00/13336.90	% SZS status Started for HL405182+4.p
96614.00/13336.90	% SZS status GaveUp for HL405182+4.p
96614.00/13336.90	eprover: CPU time limit exceeded, terminating
96614.00/13336.90	% SZS status Ended for HL405182+4.p
96648.23/13341.30	% SZS status Started for HL405179+4.p
96648.23/13341.30	% SZS status GaveUp for HL405179+4.p
96648.23/13341.30	eprover: CPU time limit exceeded, terminating
96648.23/13341.30	% SZS status Ended for HL405179+4.p
96656.48/13342.39	% SZS status Started for HL405183+5.p
96656.48/13342.39	% SZS status GaveUp for HL405183+5.p
96656.48/13342.39	% SZS status Ended for HL405183+5.p
96679.16/13345.09	% SZS status Started for HL405184+5.p
96679.16/13345.09	% SZS status GaveUp for HL405184+5.p
96679.16/13345.09	% SZS status Ended for HL405184+5.p
96683.12/13345.66	% SZS status Started for HL405180+4.p
96683.12/13345.66	% SZS status GaveUp for HL405180+4.p
96683.12/13345.66	eprover: CPU time limit exceeded, terminating
96683.12/13345.66	% SZS status Ended for HL405180+4.p
96688.85/13346.38	% SZS status Started for HL405185+5.p
96688.85/13346.38	% SZS status GaveUp for HL405185+5.p
96688.85/13346.38	% SZS status Ended for HL405185+5.p
96732.21/13351.82	% SZS status Started for HL405187+5.p
96732.21/13351.82	% SZS status GaveUp for HL405187+5.p
96732.21/13351.82	% SZS status Ended for HL405187+5.p
96758.60/13355.13	% SZS status Started for HL405188+5.p
96758.60/13355.13	% SZS status GaveUp for HL405188+5.p
96758.60/13355.13	% SZS status Ended for HL405188+5.p
96779.91/13357.77	% SZS status Started for HL405183+4.p
96779.91/13357.77	% SZS status GaveUp for HL405183+4.p
96779.91/13357.77	eprover: CPU time limit exceeded, terminating
96779.91/13357.77	% SZS status Ended for HL405183+4.p
96807.77/13361.28	% SZS status Started for HL405189+5.p
96807.77/13361.28	% SZS status GaveUp for HL405189+5.p
96807.77/13361.28	% SZS status Ended for HL405189+5.p
96809.78/13361.58	% SZS status Started for HL405184+4.p
96809.78/13361.58	% SZS status GaveUp for HL405184+4.p
96809.78/13361.58	eprover: CPU time limit exceeded, terminating
96809.78/13361.58	% SZS status Ended for HL405184+4.p
96817.57/13362.53	% SZS status Started for HL405185+4.p
96817.57/13362.53	% SZS status GaveUp for HL405185+4.p
96817.57/13362.53	eprover: CPU time limit exceeded, terminating
96817.57/13362.53	% SZS status Ended for HL405185+4.p
96854.26/13367.21	% SZS status Started for HL405190+5.p
96854.26/13367.21	% SZS status GaveUp for HL405190+5.p
96854.26/13367.21	% SZS status Ended for HL405190+5.p
96857.11/13367.60	% SZS status Started for HL405187+4.p
96857.11/13367.60	% SZS status GaveUp for HL405187+4.p
96857.11/13367.60	eprover: CPU time limit exceeded, terminating
96857.11/13367.60	% SZS status Ended for HL405187+4.p
96885.08/13371.12	% SZS status Started for HL405188+4.p
96885.08/13371.12	% SZS status GaveUp for HL405188+4.p
96885.08/13371.12	eprover: CPU time limit exceeded, terminating
96885.08/13371.12	% SZS status Ended for HL405188+4.p
96885.08/13371.16	% SZS status Started for HL405191+5.p
96885.08/13371.16	% SZS status GaveUp for HL405191+5.p
96885.08/13371.16	% SZS status Ended for HL405191+5.p
96896.11/13372.43	% SZS status Started for HL405189+4.p
96896.11/13372.43	% SZS status GaveUp for HL405189+4.p
96896.11/13372.43	eprover: CPU time limit exceeded, terminating
96896.11/13372.43	% SZS status Ended for HL405189+4.p
96932.86/13377.12	% SZS status Started for HL405192+5.p
96932.86/13377.12	% SZS status GaveUp for HL405192+5.p
96932.86/13377.12	% SZS status Ended for HL405192+5.p
96939.51/13377.99	% SZS status Started for HL405193+4.p
96939.51/13377.99	% SZS status GaveUp for HL405193+4.p
96939.51/13377.99	eprover: CPU time limit exceeded, terminating
96939.51/13377.99	% SZS status Ended for HL405193+4.p
96960.43/13380.58	% SZS status Started for HL405193+5.p
96960.43/13380.58	% SZS status GaveUp for HL405193+5.p
96960.43/13380.58	% SZS status Ended for HL405193+5.p
96965.42/13381.16	% SZS status Started for HL405190+4.p
96965.42/13381.16	% SZS status GaveUp for HL405190+4.p
96965.42/13381.16	eprover: CPU time limit exceeded, terminating
96965.42/13381.16	% SZS status Ended for HL405190+4.p
96967.97/13381.49	% SZS status Started for HL405194+4.p
96967.97/13381.49	% SZS status GaveUp for HL405194+4.p
96967.97/13381.49	eprover: CPU time limit exceeded, terminating
96967.97/13381.49	% SZS status Ended for HL405194+4.p
96975.62/13382.45	% SZS status Started for HL405194+5.p
96975.62/13382.45	% SZS status GaveUp for HL405194+5.p
96975.62/13382.45	% SZS status Ended for HL405194+5.p
97015.63/13387.45	% SZS status Started for HL405191+4.p
97015.63/13387.45	% SZS status GaveUp for HL405191+4.p
97015.63/13387.45	eprover: CPU time limit exceeded, terminating
97015.63/13387.45	% SZS status Ended for HL405191+4.p
97016.25/13387.57	% SZS status Started for HL405195+5.p
97016.25/13387.57	% SZS status GaveUp for HL405195+5.p
97016.25/13387.57	% SZS status Ended for HL405195+5.p
97025.05/13388.66	% SZS status Started for HL405192+4.p
97025.05/13388.66	% SZS status GaveUp for HL405192+4.p
97025.05/13388.66	eprover: CPU time limit exceeded, terminating
97025.05/13388.66	% SZS status Ended for HL405192+4.p
97040.78/13390.58	% SZS status Started for HL405196+5.p
97040.78/13390.58	% SZS status GaveUp for HL405196+5.p
97040.78/13390.58	% SZS status Ended for HL405196+5.p
97051.09/13391.89	% SZS status Started for HL405197+5.p
97051.09/13391.89	% SZS status GaveUp for HL405197+5.p
97051.09/13391.89	% SZS status Ended for HL405197+5.p
97092.57/13397.17	% SZS status Started for HL405198+5.p
97092.57/13397.17	% SZS status GaveUp for HL405198+5.p
97092.57/13397.17	% SZS status Ended for HL405198+5.p
97115.10/13400.17	% SZS status Started for HL405200+5.p
97115.10/13400.17	% SZS status GaveUp for HL405200+5.p
97115.10/13400.17	% SZS status Ended for HL405200+5.p
97149.18/13403.41	% SZS status Started for HL405195+4.p
97149.18/13403.41	% SZS status GaveUp for HL405195+4.p
97149.18/13403.41	eprover: CPU time limit exceeded, terminating
97149.18/13403.41	% SZS status Ended for HL405195+4.p
97162.02/13405.00	% SZS status Started for HL405201+5.p
97162.02/13405.00	% SZS status Theorem for HL405201+5.p
97162.02/13405.00	% SZS status Ended for HL405201+5.p
97176.71/13406.88	% SZS status Started for HL405196+4.p
97176.71/13406.88	% SZS status GaveUp for HL405196+4.p
97176.71/13406.88	eprover: CPU time limit exceeded, terminating
97176.71/13406.88	% SZS status Ended for HL405196+4.p
97181.36/13407.53	% SZS status Started for HL405197+4.p
97181.36/13407.53	% SZS status GaveUp for HL405197+4.p
97181.36/13407.53	eprover: CPU time limit exceeded, terminating
97181.36/13407.53	% SZS status Ended for HL405197+4.p
97213.85/13411.58	% SZS status Started for HL405202+4.p
97213.85/13411.58	% SZS status GaveUp for HL405202+4.p
97213.85/13411.58	eprover: CPU time limit exceeded, terminating
97213.85/13411.58	% SZS status Ended for HL405202+4.p
97229.27/13413.53	% SZS status Started for HL405198+4.p
97229.27/13413.53	% SZS status GaveUp for HL405198+4.p
97229.27/13413.53	eprover: CPU time limit exceeded, terminating
97229.27/13413.53	% SZS status Ended for HL405198+4.p
97229.27/13413.53	% SZS status Started for HL405202+5.p
97229.27/13413.53	% SZS status GaveUp for HL405202+5.p
97229.27/13413.53	% SZS status Ended for HL405202+5.p
97240.63/13415.11	% SZS status Started for HL405200+4.p
97240.63/13415.11	% SZS status GaveUp for HL405200+4.p
97240.63/13415.11	eprover: CPU time limit exceeded, terminating
97240.63/13415.11	% SZS status Ended for HL405200+4.p
97249.05/13416.20	% SZS status Started for HL405203+4.p
97249.05/13416.20	% SZS status GaveUp for HL405203+4.p
97249.05/13416.20	eprover: CPU time limit exceeded, terminating
97249.05/13416.20	% SZS status Ended for HL405203+4.p
97259.81/13417.55	% SZS status Started for HL405203+5.p
97259.81/13417.55	% SZS status GaveUp for HL405203+5.p
97259.81/13417.55	% SZS status Ended for HL405203+5.p
97267.91/13418.61	% SZS status Started for HL405205+4.p
97267.91/13418.61	% SZS status GaveUp for HL405205+4.p
97267.91/13418.61	eprover: CPU time limit exceeded, terminating
97267.91/13418.61	% SZS status Ended for HL405205+4.p
97272.43/13419.15	% SZS status Started for HL405201+4.p
97272.43/13419.15	% SZS status GaveUp for HL405201+4.p
97272.43/13419.15	eprover: CPU time limit exceeded, terminating
97272.43/13419.15	% SZS status Ended for HL405201+4.p
97292.09/13421.68	% SZS status Started for HL405205+5.p
97292.09/13421.68	% SZS status GaveUp for HL405205+5.p
97292.09/13421.68	% SZS status Ended for HL405205+5.p
97309.83/13423.99	% SZS status Started for HL405206+5.p
97309.83/13423.99	% SZS status GaveUp for HL405206+5.p
97309.83/13423.99	% SZS status Ended for HL405206+5.p
97317.79/13424.93	% SZS status Started for HL405206+4.p
97317.79/13424.93	% SZS status GaveUp for HL405206+4.p
97317.79/13424.93	eprover: CPU time limit exceeded, terminating
97317.79/13424.93	% SZS status Ended for HL405206+4.p
97326.73/13426.07	% SZS status Started for HL405207+4.p
97326.73/13426.07	% SZS status GaveUp for HL405207+4.p
97326.73/13426.07	eprover: CPU time limit exceeded, terminating
97326.73/13426.07	% SZS status Ended for HL405207+4.p
97328.64/13426.35	% SZS status Started for HL405207+5.p
97328.64/13426.35	% SZS status GaveUp for HL405207+5.p
97328.64/13426.35	% SZS status Ended for HL405207+5.p
97347.40/13428.76	% SZS status Started for HL405208+5.p
97347.40/13428.76	% SZS status GaveUp for HL405208+5.p
97347.40/13428.76	% SZS status Ended for HL405208+5.p
97347.92/13428.78	% SZS status Started for HL405208+4.p
97347.92/13428.78	% SZS status GaveUp for HL405208+4.p
97347.92/13428.78	eprover: CPU time limit exceeded, terminating
97347.92/13428.78	% SZS status Ended for HL405208+4.p
97358.61/13430.14	% SZS status Started for HL405210+4.p
97358.61/13430.14	% SZS status GaveUp for HL405210+4.p
97358.61/13430.14	eprover: CPU time limit exceeded, terminating
97358.61/13430.14	% SZS status Ended for HL405210+4.p
97371.24/13431.92	% SZS status Started for HL405210+5.p
97371.24/13431.92	% SZS status GaveUp for HL405210+5.p
97371.24/13431.92	% SZS status Ended for HL405210+5.p
97396.49/13435.01	% SZS status Started for HL405212+5.p
97396.49/13435.01	% SZS status GaveUp for HL405212+5.p
97396.49/13435.01	% SZS status Ended for HL405212+5.p
97398.41/13435.32	% SZS status Started for HL405212+4.p
97398.41/13435.32	% SZS status GaveUp for HL405212+4.p
97398.41/13435.32	eprover: CPU time limit exceeded, terminating
97398.41/13435.32	% SZS status Ended for HL405212+4.p
97411.48/13437.09	% SZS status Started for HL405213+5.p
97411.48/13437.09	% SZS status GaveUp for HL405213+5.p
97411.48/13437.09	% SZS status Ended for HL405213+5.p
97411.48/13437.11	% SZS status Started for HL405213+4.p
97411.48/13437.11	% SZS status GaveUp for HL405213+4.p
97411.48/13437.11	eprover: CPU time limit exceeded, terminating
97411.48/13437.11	% SZS status Ended for HL405213+4.p
97426.17/13438.91	% SZS status Started for HL405214+5.p
97426.17/13438.91	% SZS status GaveUp for HL405214+5.p
97426.17/13438.91	% SZS status Ended for HL405214+5.p
97435.16/13440.16	% SZS status Started for HL405214+4.p
97435.16/13440.16	% SZS status GaveUp for HL405214+4.p
97435.16/13440.16	eprover: CPU time limit exceeded, terminating
97435.16/13440.16	% SZS status Ended for HL405214+4.p
97443.73/13441.25	% SZS status Started for HL405215+4.p
97443.73/13441.25	% SZS status GaveUp for HL405215+4.p
97443.73/13441.25	eprover: CPU time limit exceeded, terminating
97443.73/13441.25	% SZS status Ended for HL405215+4.p
97460.72/13442.12	% SZS status Started for HL405215+5.p
97460.72/13442.12	% SZS status GaveUp for HL405215+5.p
97460.72/13442.12	% SZS status Ended for HL405215+5.p
97486.82/13445.62	% SZS status Started for HL405217+5.p
97486.82/13445.62	% SZS status GaveUp for HL405217+5.p
97486.82/13445.62	% SZS status Ended for HL405217+5.p
97493.98/13446.43	% SZS status Started for HL405217+4.p
97493.98/13446.43	% SZS status GaveUp for HL405217+4.p
97493.98/13446.43	eprover: CPU time limit exceeded, terminating
97493.98/13446.43	% SZS status Ended for HL405217+4.p
97500.51/13447.28	% SZS status Started for HL405218+5.p
97500.51/13447.28	% SZS status GaveUp for HL405218+5.p
97500.51/13447.28	% SZS status Ended for HL405218+5.p
97507.12/13448.07	% SZS status Started for HL405218+4.p
97507.12/13448.07	% SZS status GaveUp for HL405218+4.p
97507.12/13448.07	eprover: CPU time limit exceeded, terminating
97507.12/13448.07	% SZS status Ended for HL405218+4.p
97524.74/13450.32	% SZS status Started for HL405221+4.p
97524.74/13450.32	% SZS status GaveUp for HL405221+4.p
97524.74/13450.32	eprover: CPU time limit exceeded, terminating
97524.74/13450.32	% SZS status Ended for HL405221+4.p
97526.62/13450.59	% SZS status Started for HL405221+5.p
97526.62/13450.59	% SZS status GaveUp for HL405221+5.p
97526.62/13450.59	% SZS status Ended for HL405221+5.p
97539.02/13452.16	% SZS status Started for HL405222+4.p
97539.02/13452.16	% SZS status GaveUp for HL405222+4.p
97539.02/13452.16	eprover: CPU time limit exceeded, terminating
97539.02/13452.16	% SZS status Ended for HL405222+4.p
97539.02/13452.18	% SZS status Started for HL405222+5.p
97539.02/13452.18	% SZS status GaveUp for HL405222+5.p
97539.02/13452.18	% SZS status Ended for HL405222+5.p
97573.51/13456.59	% SZS status Started for HL405223+4.p
97573.51/13456.59	% SZS status GaveUp for HL405223+4.p
97573.51/13456.59	eprover: CPU time limit exceeded, terminating
97573.51/13456.59	% SZS status Ended for HL405223+4.p
97575.08/13456.75	% SZS status Started for HL405223+5.p
97575.08/13456.75	% SZS status GaveUp for HL405223+5.p
97575.08/13456.75	% SZS status Ended for HL405223+5.p
97587.45/13458.35	% SZS status Started for HL405224+4.p
97587.45/13458.35	% SZS status GaveUp for HL405224+4.p
97587.45/13458.35	eprover: CPU time limit exceeded, terminating
97587.45/13458.35	% SZS status Ended for HL405224+4.p
97587.45/13458.38	% SZS status Started for HL405224+5.p
97587.45/13458.38	% SZS status GaveUp for HL405224+5.p
97587.45/13458.38	% SZS status Ended for HL405224+5.p
97610.14/13461.20	% SZS status Started for HL405225+5.p
97610.14/13461.20	% SZS status GaveUp for HL405225+5.p
97610.14/13461.20	% SZS status Ended for HL405225+5.p
97610.14/13461.21	% SZS status Started for HL405225+4.p
97610.14/13461.21	% SZS status GaveUp for HL405225+4.p
97610.14/13461.21	eprover: CPU time limit exceeded, terminating
97610.14/13461.21	% SZS status Ended for HL405225+4.p
97617.98/13462.17	% SZS status Started for HL405226+5.p
97617.98/13462.17	% SZS status GaveUp for HL405226+5.p
97617.98/13462.17	% SZS status Ended for HL405226+5.p
97626.05/13463.16	% SZS status Started for HL405226+4.p
97626.05/13463.16	% SZS status GaveUp for HL405226+4.p
97626.05/13463.16	eprover: CPU time limit exceeded, terminating
97626.05/13463.16	% SZS status Ended for HL405226+4.p
97654.13/13466.77	% SZS status Started for HL405228+5.p
97654.13/13466.77	% SZS status GaveUp for HL405228+5.p
97654.13/13466.77	% SZS status Ended for HL405228+5.p
97660.99/13467.71	% SZS status Started for HL405228+4.p
97660.99/13467.71	% SZS status GaveUp for HL405228+4.p
97660.99/13467.71	eprover: CPU time limit exceeded, terminating
97660.99/13467.71	% SZS status Ended for HL405228+4.p
97666.59/13468.42	% SZS status Started for HL405229+5.p
97666.59/13468.42	% SZS status GaveUp for HL405229+5.p
97666.59/13468.42	% SZS status Ended for HL405229+5.p
97674.73/13469.56	% SZS status Started for HL405229+4.p
97674.73/13469.56	% SZS status GaveUp for HL405229+4.p
97674.73/13469.56	eprover: CPU time limit exceeded, terminating
97674.73/13469.56	% SZS status Ended for HL405229+4.p
97688.73/13471.35	% SZS status Started for HL405230+5.p
97688.73/13471.35	% SZS status GaveUp for HL405230+5.p
97688.73/13471.35	% SZS status Ended for HL405230+5.p
97689.23/13471.46	% SZS status Started for HL405233+4.p
97689.23/13471.46	% SZS status GaveUp for HL405233+4.p
97689.23/13471.46	eprover: CPU time limit exceeded, terminating
97689.23/13471.46	% SZS status Ended for HL405233+4.p
97699.35/13472.62	% SZS status Started for HL405230+4.p
97699.35/13472.62	% SZS status GaveUp for HL405230+4.p
97699.35/13472.62	eprover: CPU time limit exceeded, terminating
97699.35/13472.62	% SZS status Ended for HL405230+4.p
97703.97/13473.19	% SZS status Started for HL405231+5.p
97703.97/13473.19	% SZS status GaveUp for HL405231+5.p
97703.97/13473.19	% SZS status Ended for HL405231+5.p
97708.51/13473.81	% SZS status Started for HL405231+4.p
97708.51/13473.81	% SZS status GaveUp for HL405231+4.p
97708.51/13473.81	eprover: CPU time limit exceeded, terminating
97708.51/13473.81	% SZS status Ended for HL405231+4.p
97713.19/13474.38	% SZS status Started for HL405234+4.p
97713.19/13474.38	% SZS status GaveUp for HL405234+4.p
97713.19/13474.38	eprover: CPU time limit exceeded, terminating
97713.19/13474.38	% SZS status Ended for HL405234+4.p
97719.87/13475.22	% SZS status Started for HL405232+5.p
97719.87/13475.22	% SZS status Theorem for HL405232+5.p
97719.87/13475.22	% SZS status Ended for HL405232+5.p
97743.55/13478.20	% SZS status Started for HL405232+4.p
97743.55/13478.20	% SZS status GaveUp for HL405232+4.p
97743.55/13478.20	eprover: CPU time limit exceeded, terminating
97743.55/13478.20	% SZS status Ended for HL405232+4.p
97751.39/13479.19	% SZS status Started for HL405234+5.p
97751.39/13479.19	% SZS status Theorem for HL405234+5.p
97751.39/13479.19	% SZS status Ended for HL405234+5.p
97754.02/13479.57	% SZS status Started for HL405233+5.p
97754.02/13479.57	% SZS status GaveUp for HL405233+5.p
97754.02/13479.57	% SZS status Ended for HL405233+5.p
97765.29/13481.10	% SZS status Started for HL405235+5.p
97765.29/13481.10	% SZS status Theorem for HL405235+5.p
97765.29/13481.10	% SZS status Ended for HL405235+5.p
97786.72/13483.82	% SZS status Started for HL405235+4.p
97786.72/13483.82	% SZS status GaveUp for HL405235+4.p
97786.72/13483.82	eprover: CPU time limit exceeded, terminating
97786.72/13483.82	% SZS status Ended for HL405235+4.p
97793.01/13484.68	% SZS status Started for HL405237+5.p
97793.01/13484.68	% SZS status GaveUp for HL405237+5.p
97793.01/13484.68	% SZS status Ended for HL405237+5.p
97796.20/13484.87	% SZS status Started for HL405237+4.p
97796.20/13484.87	% SZS status GaveUp for HL405237+4.p
97796.20/13484.87	eprover: CPU time limit exceeded, terminating
97796.20/13484.87	% SZS status Ended for HL405237+4.p
97803.41/13485.89	% SZS status Started for HL405239+5.p
97803.41/13485.89	% SZS status Theorem for HL405239+5.p
97803.41/13485.89	% SZS status Ended for HL405239+5.p
97807.28/13486.33	% SZS status Started for HL405239+4.p
97807.28/13486.33	% SZS status GaveUp for HL405239+4.p
97807.28/13486.33	eprover: CPU time limit exceeded, terminating
97807.28/13486.33	% SZS status Ended for HL405239+4.p
97834.06/13489.67	% SZS status Started for HL405240+5.p
97834.06/13489.67	% SZS status GaveUp for HL405240+5.p
97834.06/13489.67	% SZS status Ended for HL405240+5.p
97836.23/13490.25	% SZS status Started for HL405240+4.p
97836.23/13490.25	% SZS status GaveUp for HL405240+4.p
97836.23/13490.25	eprover: CPU time limit exceeded, terminating
97836.23/13490.25	% SZS status Ended for HL405240+4.p
97854.16/13492.37	% SZS status Started for HL405241+4.p
97854.16/13492.37	% SZS status GaveUp for HL405241+4.p
97854.16/13492.37	eprover: CPU time limit exceeded, terminating
97854.16/13492.37	% SZS status Ended for HL405241+4.p
97866.85/13493.94	% SZS status Started for HL405241+5.p
97866.85/13493.94	% SZS status GaveUp for HL405241+5.p
97866.85/13493.94	% SZS status Ended for HL405241+5.p
97875.49/13495.04	% SZS status Started for HL405242+5.p
97875.49/13495.04	% SZS status GaveUp for HL405242+5.p
97875.49/13495.04	% SZS status Ended for HL405242+5.p
97880.60/13495.81	% SZS status Started for HL405242+4.p
97880.60/13495.81	% SZS status GaveUp for HL405242+4.p
97880.60/13495.81	eprover: CPU time limit exceeded, terminating
97880.60/13495.81	% SZS status Ended for HL405242+4.p
97887.97/13496.63	% SZS status Started for HL405243+5.p
97887.97/13496.63	% SZS status GaveUp for HL405243+5.p
97887.97/13496.63	% SZS status Ended for HL405243+5.p
97891.98/13497.10	% SZS status Started for HL405243+4.p
97891.98/13497.10	% SZS status GaveUp for HL405243+4.p
97891.98/13497.10	eprover: CPU time limit exceeded, terminating
97891.98/13497.10	% SZS status Ended for HL405243+4.p
97919.75/13500.55	% SZS status Started for HL405244+5.p
97919.75/13500.55	% SZS status GaveUp for HL405244+5.p
97919.75/13500.55	% SZS status Ended for HL405244+5.p
97920.41/13500.67	% SZS status Started for HL405244+4.p
97920.41/13500.67	% SZS status GaveUp for HL405244+4.p
97920.41/13500.67	eprover: CPU time limit exceeded, terminating
97920.41/13500.67	% SZS status Ended for HL405244+4.p
97926.08/13501.44	% SZS status Started for HL405245+5.p
97926.08/13501.44	% SZS status Theorem for HL405245+5.p
97926.08/13501.44	% SZS status Ended for HL405245+5.p
97943.20/13503.74	% SZS status Started for HL405245+4.p
97943.20/13503.74	% SZS status GaveUp for HL405245+4.p
97943.20/13503.74	eprover: CPU time limit exceeded, terminating
97943.20/13503.74	% SZS status Ended for HL405245+4.p
97964.14/13506.35	% SZS status Started for HL405246+4.p
97964.14/13506.35	% SZS status GaveUp for HL405246+4.p
97964.14/13506.35	eprover: CPU time limit exceeded, terminating
97964.14/13506.35	% SZS status Ended for HL405246+4.p
97964.70/13506.42	% SZS status Started for HL405246+5.p
97964.70/13506.42	% SZS status GaveUp for HL405246+5.p
97964.70/13506.42	% SZS status Ended for HL405246+5.p
97971.77/13507.26	% SZS status Started for HL405247+5.p
97971.77/13507.26	% SZS status GaveUp for HL405247+5.p
97971.77/13507.26	% SZS status Ended for HL405247+5.p
97974.42/13507.71	% SZS status Started for HL405247+4.p
97974.42/13507.71	% SZS status GaveUp for HL405247+4.p
97974.42/13507.71	eprover: CPU time limit exceeded, terminating
97974.42/13507.71	% SZS status Ended for HL405247+4.p
97999.33/13510.75	% SZS status Started for HL405248+5.p
97999.33/13510.75	% SZS status GaveUp for HL405248+5.p
97999.33/13510.75	% SZS status Ended for HL405248+5.p
98008.75/13512.04	% SZS status Started for HL405248+4.p
98008.75/13512.04	% SZS status GaveUp for HL405248+4.p
98008.75/13512.04	eprover: CPU time limit exceeded, terminating
98008.75/13512.04	% SZS status Ended for HL405248+4.p
98013.62/13512.72	% SZS status Started for HL405249+4.p
98013.62/13512.72	% SZS status GaveUp for HL405249+4.p
98013.62/13512.72	eprover: CPU time limit exceeded, terminating
98013.62/13512.72	% SZS status Ended for HL405249+4.p
98023.10/13513.82	% SZS status Started for HL405249+5.p
98023.10/13513.82	% SZS status GaveUp for HL405249+5.p
98023.10/13513.82	% SZS status Ended for HL405249+5.p
98044.33/13516.41	% SZS status Started for HL405250+5.p
98044.33/13516.41	% SZS status GaveUp for HL405250+5.p
98044.33/13516.41	% SZS status Ended for HL405250+5.p
98052.14/13517.40	% SZS status Started for HL405250+4.p
98052.14/13517.40	% SZS status GaveUp for HL405250+4.p
98052.14/13517.40	eprover: CPU time limit exceeded, terminating
98052.14/13517.40	% SZS status Ended for HL405250+4.p
98055.98/13517.92	% SZS status Started for HL405252+5.p
98055.98/13517.92	% SZS status GaveUp for HL405252+5.p
98055.98/13517.92	% SZS status Ended for HL405252+5.p
98058.25/13518.32	% SZS status Started for HL405252+4.p
98058.25/13518.32	% SZS status GaveUp for HL405252+4.p
98058.25/13518.32	eprover: CPU time limit exceeded, terminating
98058.25/13518.32	% SZS status Ended for HL405252+4.p
98086.86/13521.79	% SZS status Started for HL405253+4.p
98086.86/13521.79	% SZS status GaveUp for HL405253+4.p
98086.86/13521.79	eprover: CPU time limit exceeded, terminating
98086.86/13521.79	% SZS status Ended for HL405253+4.p
98088.42/13522.08	% SZS status Started for HL405253+5.p
98088.42/13522.08	% SZS status GaveUp for HL405253+5.p
98088.42/13522.08	% SZS status Ended for HL405253+5.p
98104.41/13523.93	% SZS status Started for HL405254+5.p
98104.41/13523.93	% SZS status GaveUp for HL405254+5.p
98104.41/13523.93	% SZS status Ended for HL405254+5.p
98104.41/13523.96	% SZS status Started for HL405254+4.p
98104.41/13523.96	% SZS status GaveUp for HL405254+4.p
98104.41/13523.96	eprover: CPU time limit exceeded, terminating
98104.41/13523.96	% SZS status Ended for HL405254+4.p
98127.06/13526.84	% SZS status Started for HL405255+5.p
98127.06/13526.84	% SZS status GaveUp for HL405255+5.p
98127.06/13526.84	% SZS status Ended for HL405255+5.p
98133.81/13527.75	% SZS status Started for HL405256+5.p
98133.81/13527.75	% SZS status GaveUp for HL405256+5.p
98133.81/13527.75	% SZS status Ended for HL405256+5.p
98164.89/13531.60	% SZS status Started for HL405257+5.p
98164.89/13531.60	% SZS status GaveUp for HL405257+5.p
98164.89/13531.60	% SZS status Ended for HL405257+5.p
98178.80/13533.38	% SZS status Started for HL405259+5.p
98178.80/13533.38	% SZS status GaveUp for HL405259+5.p
98178.80/13533.38	% SZS status Ended for HL405259+5.p
98212.30/13537.53	% SZS status Started for HL405260+5.p
98212.30/13537.53	% SZS status GaveUp for HL405260+5.p
98212.30/13537.53	% SZS status Ended for HL405260+5.p
98251.91/13542.55	% SZS status Started for HL405255+4.p
98251.91/13542.55	% SZS status GaveUp for HL405255+4.p
98251.91/13542.55	eprover: CPU time limit exceeded, terminating
98251.91/13542.55	% SZS status Ended for HL405255+4.p
98256.22/13543.10	% SZS status Started for HL405261+5.p
98256.22/13543.10	% SZS status GaveUp for HL405261+5.p
98256.22/13543.10	% SZS status Ended for HL405261+5.p
98263.20/13543.99	% SZS status Started for HL405256+4.p
98263.20/13543.99	% SZS status GaveUp for HL405256+4.p
98263.20/13543.99	eprover: CPU time limit exceeded, terminating
98263.20/13543.99	% SZS status Ended for HL405256+4.p
98294.88/13547.98	% SZS status Started for HL405257+4.p
98294.88/13547.98	% SZS status GaveUp for HL405257+4.p
98294.88/13547.98	eprover: CPU time limit exceeded, terminating
98294.88/13547.98	% SZS status Ended for HL405257+4.p
98312.05/13550.18	% SZS status Started for HL405259+4.p
98312.05/13550.18	% SZS status GaveUp for HL405259+4.p
98312.05/13550.18	eprover: CPU time limit exceeded, terminating
98312.05/13550.18	% SZS status Ended for HL405259+4.p
98329.48/13552.32	% SZS status Started for HL405262+5.p
98329.48/13552.32	% SZS status GaveUp for HL405262+5.p
98329.48/13552.32	% SZS status Ended for HL405262+5.p
98334.27/13552.93	% SZS status Started for HL405260+4.p
98334.27/13552.93	% SZS status GaveUp for HL405260+4.p
98334.27/13552.93	eprover: CPU time limit exceeded, terminating
98334.27/13552.93	% SZS status Ended for HL405260+4.p
98338.95/13553.55	% SZS status Started for HL405263+5.p
98338.95/13553.55	% SZS status GaveUp for HL405263+5.p
98338.95/13553.55	% SZS status Ended for HL405263+5.p
98373.10/13557.88	% SZS status Started for HL405261+4.p
98373.10/13557.88	% SZS status GaveUp for HL405261+4.p
98373.10/13557.88	eprover: CPU time limit exceeded, terminating
98373.10/13557.88	% SZS status Ended for HL405261+4.p
98388.34/13559.72	% SZS status Started for HL405265+5.p
98388.34/13559.72	% SZS status GaveUp for HL405265+5.p
98388.34/13559.72	% SZS status Ended for HL405265+5.p
98410.13/13562.47	% SZS status Started for HL405266+5.p
98410.13/13562.47	% SZS status GaveUp for HL405266+5.p
98410.13/13562.47	% SZS status Ended for HL405266+5.p
98420.37/13563.75	% SZS status Started for HL405262+4.p
98420.37/13563.75	% SZS status GaveUp for HL405262+4.p
98420.37/13563.75	eprover: CPU time limit exceeded, terminating
98420.37/13563.75	% SZS status Ended for HL405262+4.p
98448.75/13567.39	% SZS status Started for HL405267+5.p
98448.75/13567.39	% SZS status GaveUp for HL405267+5.p
98448.75/13567.39	% SZS status Ended for HL405267+5.p
98464.95/13569.44	% SZS status Started for HL405263+4.p
98464.95/13569.44	% SZS status GaveUp for HL405263+4.p
98464.95/13569.44	eprover: CPU time limit exceeded, terminating
98464.95/13569.44	% SZS status Ended for HL405263+4.p
98487.28/13572.18	% SZS status Started for HL405268+5.p
98487.28/13572.18	% SZS status GaveUp for HL405268+5.p
98487.28/13572.18	% SZS status Ended for HL405268+5.p
98504.51/13574.38	% SZS status Started for HL405265+4.p
98504.51/13574.38	% SZS status GaveUp for HL405265+4.p
98504.51/13574.38	eprover: CPU time limit exceeded, terminating
98504.51/13574.38	% SZS status Ended for HL405265+4.p
98505.67/13574.63	% SZS status Started for HL405269+4.p
98505.67/13574.63	% SZS status GaveUp for HL405269+4.p
98505.67/13574.63	eprover: CPU time limit exceeded, terminating
98505.67/13574.63	% SZS status Ended for HL405269+4.p
98524.01/13576.90	% SZS status Started for HL405269+5.p
98524.01/13576.90	% SZS status GaveUp for HL405269+5.p
98524.01/13576.90	% SZS status Ended for HL405269+5.p
98536.77/13578.42	% SZS status Started for HL405266+4.p
98536.77/13578.42	% SZS status GaveUp for HL405266+4.p
98536.77/13578.42	eprover: CPU time limit exceeded, terminating
98536.77/13578.42	% SZS status Ended for HL405266+4.p
98549.07/13580.02	% SZS status Started for HL405267+4.p
98549.07/13580.02	% SZS status GaveUp for HL405267+4.p
98549.07/13580.02	eprover: CPU time limit exceeded, terminating
98549.07/13580.02	% SZS status Ended for HL405267+4.p
98563.28/13581.85	% SZS status Started for HL405270+5.p
98563.28/13581.85	% SZS status GaveUp for HL405270+5.p
98563.28/13581.85	% SZS status Ended for HL405270+5.p
98581.45/13584.11	% SZS status Started for HL405271+5.p
98581.45/13584.11	% SZS status GaveUp for HL405271+5.p
98581.45/13584.11	% SZS status Ended for HL405271+5.p
98595.91/13585.87	% SZS status Started for HL405268+4.p
98595.91/13585.87	% SZS status GaveUp for HL405268+4.p
98595.91/13585.87	eprover: CPU time limit exceeded, terminating
98595.91/13585.87	% SZS status Ended for HL405268+4.p
98611.66/13587.97	% SZS status Started for HL405273+5.p
98611.66/13587.97	% SZS status GaveUp for HL405273+5.p
98611.66/13587.97	% SZS status Ended for HL405273+5.p
98619.94/13588.95	% SZS status Started for HL405275+5.p
98619.94/13588.95	% SZS status Theorem for HL405275+5.p
98619.94/13588.95	% SZS status Ended for HL405275+5.p
98632.41/13590.56	% SZS status Started for HL405275+4.p
98632.41/13590.56	% SZS status GaveUp for HL405275+4.p
98632.41/13590.56	eprover: CPU time limit exceeded, terminating
98632.41/13590.56	% SZS status Ended for HL405275+4.p
98665.72/13594.71	% SZS status Started for HL405276+4.p
98665.72/13594.71	% SZS status GaveUp for HL405276+4.p
98665.72/13594.71	eprover: CPU time limit exceeded, terminating
98665.72/13594.71	% SZS status Ended for HL405276+4.p
98671.88/13595.47	% SZS status Started for HL405270+4.p
98671.88/13595.47	% SZS status GaveUp for HL405270+4.p
98671.88/13595.47	eprover: CPU time limit exceeded, terminating
98671.88/13595.47	% SZS status Ended for HL405270+4.p
98671.88/13595.51	% SZS status Started for HL405276+5.p
98671.88/13595.51	% SZS status GaveUp for HL405276+5.p
98671.88/13595.51	% SZS status Ended for HL405276+5.p
98674.20/13595.73	% SZS status Started for HL405277+5.p
98674.20/13595.73	% SZS status Theorem for HL405277+5.p
98674.20/13595.73	% SZS status Ended for HL405277+5.p
98694.34/13598.44	% SZS status Started for HL405277+4.p
98694.34/13598.44	% SZS status GaveUp for HL405277+4.p
98694.34/13598.44	eprover: CPU time limit exceeded, terminating
98694.34/13598.44	% SZS status Ended for HL405277+4.p
98711.73/13600.68	% SZS status Started for HL405271+4.p
98711.73/13600.68	% SZS status GaveUp for HL405271+4.p
98711.73/13600.68	eprover: CPU time limit exceeded, terminating
98711.73/13600.68	% SZS status Ended for HL405271+4.p
98716.79/13601.19	% SZS status Started for HL405278+4.p
98716.79/13601.19	% SZS status GaveUp for HL405278+4.p
98716.79/13601.19	eprover: CPU time limit exceeded, terminating
98716.79/13601.19	% SZS status Ended for HL405278+4.p
98733.48/13603.23	% SZS status Started for HL405273+4.p
98733.48/13603.23	% SZS status GaveUp for HL405273+4.p
98733.48/13603.23	eprover: CPU time limit exceeded, terminating
98733.48/13603.23	% SZS status Ended for HL405273+4.p
98742.95/13604.48	% SZS status Started for HL405278+5.p
98742.95/13604.48	% SZS status GaveUp for HL405278+5.p
98742.95/13604.48	% SZS status Ended for HL405278+5.p
98750.36/13605.39	% SZS status Started for HL405279+5.p
98750.36/13605.39	% SZS status GaveUp for HL405279+5.p
98750.36/13605.39	% SZS status Ended for HL405279+5.p
98756.20/13606.15	% SZS status Started for HL405280+4.p
98756.20/13606.15	% SZS status GaveUp for HL405280+4.p
98756.20/13606.15	eprover: CPU time limit exceeded, terminating
98756.20/13606.15	% SZS status Ended for HL405280+4.p
98770.09/13607.94	% SZS status Started for HL405280+5.p
98770.09/13607.94	% SZS status GaveUp for HL405280+5.p
98770.09/13607.94	% SZS status Ended for HL405280+5.p
98792.16/13610.71	% SZS status Started for HL405281+5.p
98792.16/13610.71	% SZS status GaveUp for HL405281+5.p
98792.16/13610.71	% SZS status Ended for HL405281+5.p
98819.45/13614.05	% SZS status Started for HL405283+5.p
98819.45/13614.05	% SZS status GaveUp for HL405283+5.p
98819.45/13614.05	% SZS status Ended for HL405283+5.p
98832.12/13615.66	% SZS status Started for HL405284+5.p
98832.12/13615.66	% SZS status GaveUp for HL405284+5.p
98832.12/13615.66	% SZS status Ended for HL405284+5.p
98869.09/13620.29	% SZS status Started for HL405285+5.p
98869.09/13620.29	% SZS status GaveUp for HL405285+5.p
98869.09/13620.29	% SZS status Ended for HL405285+5.p
98879.16/13621.58	% SZS status Started for HL405279+4.p
98879.16/13621.58	% SZS status GaveUp for HL405279+4.p
98879.16/13621.58	eprover: CPU time limit exceeded, terminating
98879.16/13621.58	% SZS status Ended for HL405279+4.p
98908.38/13625.25	% SZS status Started for HL405286+5.p
98908.38/13625.25	% SZS status GaveUp for HL405286+5.p
98908.38/13625.25	% SZS status Ended for HL405286+5.p
98922.30/13627.05	% SZS status Started for HL405281+4.p
98922.30/13627.05	% SZS status GaveUp for HL405281+4.p
98922.30/13627.05	eprover: CPU time limit exceeded, terminating
98922.30/13627.05	% SZS status Ended for HL405281+4.p
98932.60/13628.56	% SZS status Started for HL405287+5.p
98932.60/13628.56	% SZS status Theorem for HL405287+5.p
98932.60/13628.56	% SZS status Ended for HL405287+5.p
98946.82/13629.52	% SZS status Started for HL405283+4.p
98946.82/13629.52	% SZS status GaveUp for HL405283+4.p
98946.82/13629.52	eprover: CPU time limit exceeded, terminating
98946.82/13629.52	% SZS status Ended for HL405283+4.p
98963.90/13631.70	% SZS status Started for HL405284+4.p
98963.90/13631.70	% SZS status GaveUp for HL405284+4.p
98963.90/13631.70	eprover: CPU time limit exceeded, terminating
98963.90/13631.70	% SZS status Ended for HL405284+4.p
98981.83/13634.02	% SZS status Started for HL405289+5.p
98981.83/13634.02	% SZS status Theorem for HL405289+5.p
98981.83/13634.02	% SZS status Ended for HL405289+5.p
98982.30/13634.13	% SZS status Started for HL405285+4.p
98982.30/13634.13	% SZS status GaveUp for HL405285+4.p
98982.30/13634.13	eprover: CPU time limit exceeded, terminating
98982.30/13634.13	% SZS status Ended for HL405285+4.p
99024.52/13639.30	% SZS status Started for HL405290+5.p
99024.52/13639.30	% SZS status GaveUp for HL405290+5.p
99024.52/13639.30	% SZS status Ended for HL405290+5.p
99032.49/13640.29	% SZS status Started for HL405286+4.p
99032.49/13640.29	% SZS status GaveUp for HL405286+4.p
99032.49/13640.29	eprover: CPU time limit exceeded, terminating
99032.49/13640.29	% SZS status Ended for HL405286+4.p
99036.12/13640.98	% SZS status Started for HL405292+5.p
99036.12/13640.98	% SZS status Theorem for HL405292+5.p
99036.12/13640.98	% SZS status Ended for HL405292+5.p
99066.48/13644.61	% SZS status Started for HL405293+4.p
99066.48/13644.61	% SZS status GaveUp for HL405293+4.p
99066.48/13644.61	eprover: CPU time limit exceeded, terminating
99066.48/13644.61	% SZS status Ended for HL405293+4.p
99080.78/13646.38	% SZS status Started for HL405287+4.p
99080.78/13646.38	% SZS status GaveUp for HL405287+4.p
99080.78/13646.38	eprover: CPU time limit exceeded, terminating
99080.78/13646.38	% SZS status Ended for HL405287+4.p
99094.64/13648.25	% SZS status Started for HL405295+5.p
99094.64/13648.25	% SZS status Theorem for HL405295+5.p
99094.64/13648.25	% SZS status Ended for HL405295+5.p
99097.84/13648.58	% SZS status Started for HL405293+5.p
99097.84/13648.58	% SZS status GaveUp for HL405293+5.p
99097.84/13648.58	% SZS status Ended for HL405293+5.p
99108.16/13649.96	% SZS status Started for HL405298+5.p
99108.16/13649.96	% SZS status Theorem for HL405298+5.p
99108.16/13649.96	% SZS status Ended for HL405298+5.p
99121.09/13651.64	% SZS status Started for HL405289+4.p
99121.09/13651.64	% SZS status GaveUp for HL405289+4.p
99121.09/13651.64	eprover: CPU time limit exceeded, terminating
99121.09/13651.64	% SZS status Ended for HL405289+4.p
99139.21/13653.78	% SZS status Started for HL405297+5.p
99139.21/13653.78	% SZS status Theorem for HL405297+5.p
99139.21/13653.78	% SZS status Ended for HL405297+5.p
99147.62/13654.85	% SZS status Started for HL405290+4.p
99147.62/13654.85	% SZS status GaveUp for HL405290+4.p
99147.62/13654.85	eprover: CPU time limit exceeded, terminating
99147.62/13654.85	% SZS status Ended for HL405290+4.p
99172.10/13657.95	% SZS status Started for HL405292+4.p
99172.10/13657.95	% SZS status GaveUp for HL405292+4.p
99172.10/13657.95	eprover: CPU time limit exceeded, terminating
99172.10/13657.95	% SZS status Ended for HL405292+4.p
99179.32/13658.80	% SZS status Started for HL405298+4.p
99179.32/13658.80	% SZS status GaveUp for HL405298+4.p
99179.32/13658.80	eprover: CPU time limit exceeded, terminating
99179.32/13658.80	% SZS status Ended for HL405298+4.p
99196.23/13660.99	% SZS status Started for HL405299+5.p
99196.23/13660.99	% SZS status GaveUp for HL405299+5.p
99196.23/13660.99	% SZS status Ended for HL405299+5.p
99219.91/13663.93	% SZS status Started for HL405300+4.p
99219.91/13663.93	% SZS status GaveUp for HL405300+4.p
99219.91/13663.93	eprover: CPU time limit exceeded, terminating
99219.91/13663.93	% SZS status Ended for HL405300+4.p
99222.65/13664.38	% SZS status Started for HL405300+5.p
99222.65/13664.38	% SZS status GaveUp for HL405300+5.p
99222.65/13664.38	% SZS status Ended for HL405300+5.p
99234.47/13665.76	% SZS status Started for HL405301+5.p
99234.47/13665.76	% SZS status Theorem for HL405301+5.p
99234.47/13665.76	% SZS status Ended for HL405301+5.p
99239.99/13666.48	% SZS status Started for HL405295+4.p
99239.99/13666.48	% SZS status GaveUp for HL405295+4.p
99239.99/13666.48	eprover: CPU time limit exceeded, terminating
99239.99/13666.48	% SZS status Ended for HL405295+4.p
99275.70/13670.94	% SZS status Started for HL405297+4.p
99275.70/13670.94	% SZS status GaveUp for HL405297+4.p
99275.70/13670.94	eprover: CPU time limit exceeded, terminating
99275.70/13670.94	% SZS status Ended for HL405297+4.p
99289.48/13672.65	% SZS status Started for HL405303+5.p
99289.48/13672.65	% SZS status Theorem for HL405303+5.p
99289.48/13672.65	% SZS status Ended for HL405303+5.p
99295.11/13673.39	% SZS status Started for HL405302+5.p
99295.11/13673.39	% SZS status GaveUp for HL405302+5.p
99295.11/13673.39	% SZS status Ended for HL405302+5.p
99315.73/13675.96	% SZS status Started for HL405307+5.p
99315.73/13675.96	% SZS status Theorem for HL405307+5.p
99315.73/13675.96	% SZS status Ended for HL405307+5.p
99316.53/13676.06	% SZS status Started for HL405299+4.p
99316.53/13676.06	% SZS status GaveUp for HL405299+4.p
99316.53/13676.06	eprover: CPU time limit exceeded, terminating
99316.53/13676.06	% SZS status Ended for HL405299+4.p
99327.59/13677.49	% SZS status Started for HL405308+5.p
99327.59/13677.49	% SZS status Theorem for HL405308+5.p
99327.59/13677.49	% SZS status Ended for HL405308+5.p
99331.42/13678.03	% SZS status Started for HL405305+5.p
99331.42/13678.03	% SZS status Theorem for HL405305+5.p
99331.42/13678.03	% SZS status Ended for HL405305+5.p
99343.16/13679.43	% SZS status Started for HL405309+5.p
99343.16/13679.43	% SZS status Theorem for HL405309+5.p
99343.16/13679.43	% SZS status Ended for HL405309+5.p
99379.41/13684.06	% SZS status Started for HL405301+4.p
99379.41/13684.06	% SZS status GaveUp for HL405301+4.p
99379.41/13684.06	eprover: CPU time limit exceeded, terminating
99379.41/13684.06	% SZS status Ended for HL405301+4.p
99392.27/13685.47	% SZS status Started for HL405310+5.p
99392.27/13685.47	% SZS status Theorem for HL405310+5.p
99392.27/13685.47	% SZS status Ended for HL405310+5.p
99405.09/13687.15	% SZS status Started for HL405302+4.p
99405.09/13687.15	% SZS status GaveUp for HL405302+4.p
99405.09/13687.15	eprover: CPU time limit exceeded, terminating
99405.09/13687.15	% SZS status Ended for HL405302+4.p
99410.19/13687.74	% SZS status Started for HL405309+4.p
99410.19/13687.74	% SZS status GaveUp for HL405309+4.p
99410.19/13687.74	eprover: CPU time limit exceeded, terminating
99410.19/13687.74	% SZS status Ended for HL405309+4.p
99417.66/13688.74	% SZS status Started for HL405311+5.p
99417.66/13688.74	% SZS status Theorem for HL405311+5.p
99417.66/13688.74	% SZS status Ended for HL405311+5.p
99426.23/13689.75	% SZS status Started for HL405310+4.p
99426.23/13689.75	% SZS status GaveUp for HL405310+4.p
99426.23/13689.75	eprover: CPU time limit exceeded, terminating
99426.23/13689.75	% SZS status Ended for HL405310+4.p
99429.34/13690.15	% SZS status Started for HL405313+5.p
99429.34/13690.15	% SZS status Theorem for HL405313+5.p
99429.34/13690.15	% SZS status Ended for HL405313+5.p
99434.27/13690.83	% SZS status Started for HL405303+4.p
99434.27/13690.83	% SZS status GaveUp for HL405303+4.p
99434.27/13690.83	eprover: CPU time limit exceeded, terminating
99434.27/13690.83	% SZS status Ended for HL405303+4.p
99440.20/13691.56	% SZS status Started for HL405314+5.p
99440.20/13691.56	% SZS status Theorem for HL405314+5.p
99440.20/13691.56	% SZS status Ended for HL405314+5.p
99450.07/13692.74	% SZS status Started for HL405305+4.p
99450.07/13692.74	% SZS status GaveUp for HL405305+4.p
99450.07/13692.74	eprover: CPU time limit exceeded, terminating
99450.07/13692.74	% SZS status Ended for HL405305+4.p
99451.90/13693.13	% SZS status Started for HL405316+5.p
99451.90/13693.13	% SZS status Theorem for HL405316+5.p
99451.90/13693.13	% SZS status Ended for HL405316+5.p
99464.47/13694.57	% SZS status Started for HL405317+5.p
99464.47/13694.57	% SZS status Theorem for HL405317+5.p
99464.47/13694.57	% SZS status Ended for HL405317+5.p
99499.73/13699.09	% SZS status Started for HL405307+4.p
99499.73/13699.09	% SZS status GaveUp for HL405307+4.p
99499.73/13699.09	eprover: CPU time limit exceeded, terminating
99499.73/13699.09	% SZS status Ended for HL405307+4.p
99508.55/13700.16	% SZS status Started for HL405314+4.p
99508.55/13700.16	% SZS status GaveUp for HL405314+4.p
99508.55/13700.16	eprover: CPU time limit exceeded, terminating
99508.55/13700.16	% SZS status Ended for HL405314+4.p
99511.88/13700.64	% SZS status Started for HL405318+5.p
99511.88/13700.64	% SZS status Theorem for HL405318+5.p
99511.88/13700.64	% SZS status Ended for HL405318+5.p
99522.82/13702.08	% SZS status Started for HL405320+5.p
99522.82/13702.08	% SZS status Theorem for HL405320+5.p
99522.82/13702.08	% SZS status Ended for HL405320+5.p
99524.38/13702.28	% SZS status Started for HL405308+4.p
99524.38/13702.28	% SZS status GaveUp for HL405308+4.p
99524.38/13702.28	eprover: CPU time limit exceeded, terminating
99524.38/13702.28	% SZS status Ended for HL405308+4.p
99536.67/13703.76	% SZS status Started for HL405321+5.p
99536.67/13703.76	% SZS status Theorem for HL405321+5.p
99536.67/13703.76	% SZS status Ended for HL405321+5.p
99593.25/13710.84	% SZS status Started for HL405320+4.p
99593.25/13710.84	% SZS status GaveUp for HL405320+4.p
99593.25/13710.84	eprover: CPU time limit exceeded, terminating
99593.25/13710.84	% SZS status Ended for HL405320+4.p
99600.07/13711.69	% SZS status Started for HL405311+4.p
99600.07/13711.69	% SZS status GaveUp for HL405311+4.p
99600.07/13711.69	eprover: CPU time limit exceeded, terminating
99600.07/13711.69	% SZS status Ended for HL405311+4.p
99603.80/13712.26	% SZS status Started for HL405321+4.p
99603.80/13712.26	% SZS status GaveUp for HL405321+4.p
99603.80/13712.26	eprover: CPU time limit exceeded, terminating
99603.80/13712.26	% SZS status Ended for HL405321+4.p
99605.09/13712.34	% SZS status Started for HL405322+5.p
99605.09/13712.34	% SZS status Theorem for HL405322+5.p
99605.09/13712.34	% SZS status Ended for HL405322+5.p
99615.45/13713.69	% SZS status Started for HL405323+5.p
99615.45/13713.69	% SZS status Theorem for HL405323+5.p
99615.45/13713.69	% SZS status Ended for HL405323+5.p
99618.82/13714.12	% SZS status Started for HL405313+4.p
99618.82/13714.12	% SZS status GaveUp for HL405313+4.p
99618.82/13714.12	eprover: CPU time limit exceeded, terminating
99618.82/13714.12	% SZS status Ended for HL405313+4.p
99626.03/13715.10	% SZS status Started for HL405324+5.p
99626.03/13715.10	% SZS status Theorem for HL405324+5.p
99626.03/13715.10	% SZS status Ended for HL405324+5.p
99641.98/13717.01	% SZS status Started for HL405316+4.p
99641.98/13717.01	% SZS status GaveUp for HL405316+4.p
99641.98/13717.01	eprover: CPU time limit exceeded, terminating
99641.98/13717.01	% SZS status Ended for HL405316+4.p
99658.20/13719.08	% SZS status Started for HL405317+4.p
99658.20/13719.08	% SZS status GaveUp for HL405317+4.p
99658.20/13719.08	eprover: CPU time limit exceeded, terminating
99658.20/13719.08	% SZS status Ended for HL405317+4.p
99672.44/13720.84	% SZS status Started for HL405318+4.p
99672.44/13720.84	% SZS status GaveUp for HL405318+4.p
99672.44/13720.84	eprover: CPU time limit exceeded, terminating
99672.44/13720.84	% SZS status Ended for HL405318+4.p
99703.96/13724.83	% SZS status Started for HL405325+5.p
99703.96/13724.83	% SZS status GaveUp for HL405325+5.p
99703.96/13724.83	% SZS status Ended for HL405325+5.p
99716.03/13726.35	% SZS status Started for HL405328+5.p
99716.03/13726.35	% SZS status Theorem for HL405328+5.p
99716.03/13726.35	% SZS status Ended for HL405328+5.p
99744.99/13729.97	% SZS status Started for HL405322+4.p
99744.99/13729.97	% SZS status GaveUp for HL405322+4.p
99744.99/13729.97	eprover: CPU time limit exceeded, terminating
99744.99/13729.97	% SZS status Ended for HL405322+4.p
99758.33/13731.71	% SZS status Started for HL405329+5.p
99758.33/13731.71	% SZS status Theorem for HL405329+5.p
99758.33/13731.71	% SZS status Ended for HL405329+5.p
99801.84/13737.14	% SZS status Started for HL405330+5.p
99801.84/13737.14	% SZS status Theorem for HL405330+5.p
99801.84/13737.14	% SZS status Ended for HL405330+5.p
99807.32/13737.86	% SZS status Started for HL405323+4.p
99807.32/13737.86	% SZS status GaveUp for HL405323+4.p
99807.32/13737.86	eprover: CPU time limit exceeded, terminating
99807.32/13737.86	% SZS status Ended for HL405323+4.p
99812.50/13738.51	% SZS status Started for HL405324+4.p
99812.50/13738.51	% SZS status GaveUp for HL405324+4.p
99812.50/13738.51	eprover: CPU time limit exceeded, terminating
99812.50/13738.51	% SZS status Ended for HL405324+4.p
99825.77/13740.24	% SZS status Started for HL405325+4.p
99825.77/13740.24	% SZS status GaveUp for HL405325+4.p
99825.77/13740.24	eprover: CPU time limit exceeded, terminating
99825.77/13740.24	% SZS status Ended for HL405325+4.p
99848.80/13743.24	% SZS status Started for HL405328+4.p
99848.80/13743.24	% SZS status GaveUp for HL405328+4.p
99848.80/13743.24	eprover: CPU time limit exceeded, terminating
99848.80/13743.24	% SZS status Ended for HL405328+4.p
99879.14/13746.85	% SZS status Started for HL405331+5.p
99879.14/13746.85	% SZS status GaveUp for HL405331+5.p
99879.14/13746.85	% SZS status Ended for HL405331+5.p
99880.70/13747.07	% SZS status Started for HL405329+4.p
99880.70/13747.07	% SZS status GaveUp for HL405329+4.p
99880.70/13747.07	eprover: CPU time limit exceeded, terminating
99880.70/13747.07	% SZS status Ended for HL405329+4.p
99888.14/13748.04	% SZS status Started for HL405332+4.p
99888.14/13748.04	% SZS status GaveUp for HL405332+4.p
99888.14/13748.04	eprover: CPU time limit exceeded, terminating
99888.14/13748.04	% SZS status Ended for HL405332+4.p
99889.50/13748.20	% SZS status Started for HL405332+5.p
99889.50/13748.20	% SZS status GaveUp for HL405332+5.p
99889.50/13748.20	% SZS status Ended for HL405332+5.p
99924.96/13752.71	% SZS status Started for HL405330+4.p
99924.96/13752.71	% SZS status GaveUp for HL405330+4.p
99924.96/13752.71	eprover: CPU time limit exceeded, terminating
99924.96/13752.71	% SZS status Ended for HL405330+4.p
99925.55/13752.77	% SZS status Started for HL405333+5.p
99925.55/13752.77	% SZS status GaveUp for HL405333+5.p
99925.55/13752.77	% SZS status Ended for HL405333+5.p
99935.55/13753.99	% SZS status Started for HL405336+5.p
99935.55/13753.99	% SZS status Theorem for HL405336+5.p
99935.55/13753.99	% SZS status Ended for HL405336+5.p
99965.00/13757.67	% SZS status Started for HL405337+5.p
99965.00/13757.67	% SZS status GaveUp for HL405337+5.p
99965.00/13757.67	% SZS status Ended for HL405337+5.p
99965.70/13757.81	% SZS status Started for HL405331+4.p
99965.70/13757.81	% SZS status GaveUp for HL405331+4.p
99965.70/13757.81	eprover: CPU time limit exceeded, terminating
99965.70/13757.81	% SZS status Ended for HL405331+4.p
99971.91/13758.64	% SZS status Started for HL405337+4.p
99971.91/13758.64	% SZS status GaveUp for HL405337+4.p
99971.91/13758.64	eprover: CPU time limit exceeded, terminating
99971.91/13758.64	% SZS status Ended for HL405337+4.p
100001.75/13762.36	% SZS status Started for HL405338+5.p
100001.75/13762.36	% SZS status GaveUp for HL405338+5.p
100001.75/13762.36	% SZS status Ended for HL405338+5.p
100009.16/13763.28	% SZS status Started for HL405338+4.p
100009.16/13763.28	% SZS status GaveUp for HL405338+4.p
100009.16/13763.28	eprover: CPU time limit exceeded, terminating
100009.16/13763.28	% SZS status Ended for HL405338+4.p
100037.52/13766.83	% SZS status Started for HL405333+4.p
100037.52/13766.83	% SZS status GaveUp for HL405333+4.p
100037.52/13766.83	eprover: CPU time limit exceeded, terminating
100037.52/13766.83	% SZS status Ended for HL405333+4.p
100041.16/13767.27	% SZS status Started for HL405339+5.p
100041.16/13767.27	% SZS status GaveUp for HL405339+5.p
100041.16/13767.27	% SZS status Ended for HL405339+5.p
100047.85/13768.13	% SZS status Started for HL405340+5.p
100047.85/13768.13	% SZS status GaveUp for HL405340+5.p
100047.85/13768.13	% SZS status Ended for HL405340+5.p
100084.98/13772.82	% SZS status Started for HL405341+5.p
100084.98/13772.82	% SZS status GaveUp for HL405341+5.p
100084.98/13772.82	% SZS status Ended for HL405341+5.p
100086.85/13773.02	% SZS status Started for HL405336+4.p
100086.85/13773.02	% SZS status GaveUp for HL405336+4.p
100086.85/13773.02	eprover: CPU time limit exceeded, terminating
100086.85/13773.02	% SZS status Ended for HL405336+4.p
100116.24/13776.79	% SZS status Started for HL405342+5.p
100116.24/13776.79	% SZS status GaveUp for HL405342+5.p
100116.24/13776.79	% SZS status Ended for HL405342+5.p
100147.34/13780.60	% SZS status Started for HL405339+4.p
100147.34/13780.60	% SZS status GaveUp for HL405339+4.p
100147.34/13780.60	eprover: CPU time limit exceeded, terminating
100147.34/13780.60	% SZS status Ended for HL405339+4.p
100163.56/13782.72	% SZS status Started for HL405343+5.p
100163.56/13782.72	% SZS status GaveUp for HL405343+5.p
100163.56/13782.72	% SZS status Ended for HL405343+5.p
100173.86/13783.98	% SZS status Started for HL405340+4.p
100173.86/13783.98	% SZS status GaveUp for HL405340+4.p
100173.86/13783.98	eprover: CPU time limit exceeded, terminating
100173.86/13783.98	% SZS status Ended for HL405340+4.p
100192.46/13786.34	% SZS status Started for HL405344+5.p
100192.46/13786.34	% SZS status GaveUp for HL405344+5.p
100192.46/13786.34	% SZS status Ended for HL405344+5.p
100211.94/13788.78	% SZS status Started for HL405341+4.p
100211.94/13788.78	% SZS status GaveUp for HL405341+4.p
100211.94/13788.78	eprover: CPU time limit exceeded, terminating
100211.94/13788.78	% SZS status Ended for HL405341+4.p
100218.60/13789.60	% SZS status Started for HL405345+5.p
100218.60/13789.60	% SZS status Theorem for HL405345+5.p
100218.60/13789.60	% SZS status Ended for HL405345+5.p
100244.82/13792.85	% SZS status Started for HL405342+4.p
100244.82/13792.85	% SZS status GaveUp for HL405342+4.p
100244.82/13792.85	eprover: CPU time limit exceeded, terminating
100244.82/13792.85	% SZS status Ended for HL405342+4.p
100249.09/13793.43	% SZS status Started for HL405346+5.p
100249.09/13793.43	% SZS status Theorem for HL405346+5.p
100249.09/13793.43	% SZS status Ended for HL405346+5.p
100254.99/13794.22	% SZS status Started for HL405343+4.p
100254.99/13794.22	% SZS status GaveUp for HL405343+4.p
100254.99/13794.22	eprover: CPU time limit exceeded, terminating
100254.99/13794.22	% SZS status Ended for HL405343+4.p
100274.36/13796.60	% SZS status Started for HL405347+5.p
100274.36/13796.60	% SZS status Theorem for HL405347+5.p
100274.36/13796.60	% SZS status Ended for HL405347+5.p
100294.60/13799.11	% SZS status Started for HL405344+4.p
100294.60/13799.11	% SZS status GaveUp for HL405344+4.p
100294.60/13799.11	eprover: CPU time limit exceeded, terminating
100294.60/13799.11	% SZS status Ended for HL405344+4.p
100325.30/13803.01	% SZS status Started for HL405348+5.p
100325.30/13803.01	% SZS status GaveUp for HL405348+5.p
100325.30/13803.01	% SZS status Ended for HL405348+5.p
100333.12/13804.04	% SZS status Started for HL405349+5.p
100333.12/13804.04	% SZS status Theorem for HL405349+5.p
100333.12/13804.04	% SZS status Ended for HL405349+5.p
100354.44/13806.67	% SZS status Started for HL405345+4.p
100354.44/13806.67	% SZS status GaveUp for HL405345+4.p
100354.44/13806.67	eprover: CPU time limit exceeded, terminating
100354.44/13806.67	% SZS status Ended for HL405345+4.p
100377.91/13809.63	% SZS status Started for HL405351+4.p
100377.91/13809.63	% SZS status GaveUp for HL405351+4.p
100377.91/13809.63	eprover: CPU time limit exceeded, terminating
100377.91/13809.63	% SZS status Ended for HL405351+4.p
100381.31/13810.05	% SZS status Started for HL405346+4.p
100381.31/13810.05	% SZS status GaveUp for HL405346+4.p
100381.31/13810.05	eprover: CPU time limit exceeded, terminating
100381.31/13810.05	% SZS status Ended for HL405346+4.p
100385.50/13810.63	% SZS status Started for HL405351+5.p
100385.50/13810.63	% SZS status Theorem for HL405351+5.p
100385.50/13810.63	% SZS status Ended for HL405351+5.p
100417.28/13814.68	% SZS status Started for HL405353+5.p
100417.28/13814.68	% SZS status Theorem for HL405353+5.p
100417.28/13814.68	% SZS status Ended for HL405353+5.p
100417.83/13814.84	% SZS status Started for HL405347+4.p
100417.83/13814.84	% SZS status GaveUp for HL405347+4.p
100417.83/13814.84	eprover: CPU time limit exceeded, terminating
100417.83/13814.84	% SZS status Ended for HL405347+4.p
100425.19/13815.55	% SZS status Started for HL405353+4.p
100425.19/13815.55	% SZS status GaveUp for HL405353+4.p
100425.19/13815.55	eprover: CPU time limit exceeded, terminating
100425.19/13815.55	% SZS status Ended for HL405353+4.p
100453.00/13819.12	% SZS status Started for HL405348+4.p
100453.00/13819.12	% SZS status GaveUp for HL405348+4.p
100453.00/13819.12	eprover: CPU time limit exceeded, terminating
100453.00/13819.12	% SZS status Ended for HL405348+4.p
100461.17/13820.16	% SZS status Started for HL405355+5.p
100461.17/13820.16	% SZS status GaveUp for HL405355+5.p
100461.17/13820.16	% SZS status Ended for HL405355+5.p
100463.51/13820.43	% SZS status Started for HL405349+4.p
100463.51/13820.43	% SZS status GaveUp for HL405349+4.p
100463.51/13820.43	eprover: CPU time limit exceeded, terminating
100463.51/13820.43	% SZS status Ended for HL405349+4.p
100464.48/13820.62	% SZS status Started for HL405355+4.p
100464.48/13820.62	% SZS status GaveUp for HL405355+4.p
100464.48/13820.62	eprover: CPU time limit exceeded, terminating
100464.48/13820.62	% SZS status Ended for HL405355+4.p
100473.30/13821.64	% SZS status Started for HL405356+4.p
100473.30/13821.64	% SZS status GaveUp for HL405356+4.p
100473.30/13821.64	eprover: CPU time limit exceeded, terminating
100473.30/13821.64	% SZS status Ended for HL405356+4.p
100478.49/13822.34	% SZS status Started for HL405356+5.p
100478.49/13822.34	% SZS status Theorem for HL405356+5.p
100478.49/13822.34	% SZS status Ended for HL405356+5.p
100504.10/13825.60	% SZS status Started for HL405357+5.p
100504.10/13825.60	% SZS status GaveUp for HL405357+5.p
100504.10/13825.60	% SZS status Ended for HL405357+5.p
100506.24/13825.82	% SZS status Started for HL405357+4.p
100506.24/13825.82	% SZS status GaveUp for HL405357+4.p
100506.24/13825.82	eprover: CPU time limit exceeded, terminating
100506.24/13825.82	% SZS status Ended for HL405357+4.p
100521.00/13827.73	% SZS status Started for HL405359+5.p
100521.00/13827.73	% SZS status Theorem for HL405359+5.p
100521.00/13827.73	% SZS status Ended for HL405359+5.p
100526.07/13828.28	% SZS status Started for HL405360+5.p
100526.07/13828.28	% SZS status Theorem for HL405360+5.p
100526.07/13828.28	% SZS status Ended for HL405360+5.p
100530.08/13828.95	% SZS status Started for HL405361+5.p
100530.08/13828.95	% SZS status Theorem for HL405361+5.p
100530.08/13828.95	% SZS status Ended for HL405361+5.p
100544.91/13830.67	% SZS status Started for HL405359+4.p
100544.91/13830.67	% SZS status GaveUp for HL405359+4.p
100544.91/13830.67	eprover: CPU time limit exceeded, terminating
100544.91/13830.67	% SZS status Ended for HL405359+4.p
100550.71/13831.38	% SZS status Started for HL405360+4.p
100550.71/13831.38	% SZS status GaveUp for HL405360+4.p
100550.71/13831.38	eprover: CPU time limit exceeded, terminating
100550.71/13831.38	% SZS status Ended for HL405360+4.p
100560.19/13832.61	% SZS status Started for HL405361+4.p
100560.19/13832.61	% SZS status GaveUp for HL405361+4.p
100560.19/13832.61	eprover: CPU time limit exceeded, terminating
100560.19/13832.61	% SZS status Ended for HL405361+4.p
100585.55/13835.82	% SZS status Started for HL405363+5.p
100585.55/13835.82	% SZS status Theorem for HL405363+5.p
100585.55/13835.82	% SZS status Ended for HL405363+5.p
100585.55/13835.84	% SZS status Started for HL405362+5.p
100585.55/13835.84	% SZS status GaveUp for HL405362+5.p
100585.55/13835.84	% SZS status Ended for HL405362+5.p
100591.96/13836.60	% SZS status Started for HL405362+4.p
100591.96/13836.60	% SZS status GaveUp for HL405362+4.p
100591.96/13836.60	eprover: CPU time limit exceeded, terminating
100591.96/13836.60	% SZS status Ended for HL405362+4.p
100608.48/13838.72	% SZS status Started for HL405363+4.p
100608.48/13838.72	% SZS status GaveUp for HL405363+4.p
100608.48/13838.72	eprover: CPU time limit exceeded, terminating
100608.48/13838.72	% SZS status Ended for HL405363+4.p
100617.20/13839.95	% SZS status Started for HL405364+4.p
100617.20/13839.95	% SZS status GaveUp for HL405364+4.p
100617.20/13839.95	eprover: CPU time limit exceeded, terminating
100617.20/13839.95	% SZS status Ended for HL405364+4.p
100624.43/13840.73	% SZS status Started for HL405364+5.p
100624.43/13840.73	% SZS status GaveUp for HL405364+5.p
100624.43/13840.73	% SZS status Ended for HL405364+5.p
100638.23/13842.41	% SZS status Started for HL405367+4.p
100638.23/13842.41	% SZS status GaveUp for HL405367+4.p
100638.23/13842.41	eprover: CPU time limit exceeded, terminating
100638.23/13842.41	% SZS status Ended for HL405367+4.p
100640.55/13842.87	% SZS status Started for HL405367+5.p
100640.55/13842.87	% SZS status GaveUp for HL405367+5.p
100640.55/13842.87	% SZS status Ended for HL405367+5.p
100664.73/13845.85	% SZS status Started for HL405368+5.p
100664.73/13845.85	% SZS status GaveUp for HL405368+5.p
100664.73/13845.85	% SZS status Ended for HL405368+5.p
100674.00/13846.98	% SZS status Started for HL405368+4.p
100674.00/13846.98	% SZS status GaveUp for HL405368+4.p
100674.00/13846.98	eprover: CPU time limit exceeded, terminating
100674.00/13846.98	% SZS status Ended for HL405368+4.p
100682.16/13847.90	% SZS status Started for HL405369+4.p
100682.16/13847.90	% SZS status GaveUp for HL405369+4.p
100682.16/13847.90	eprover: CPU time limit exceeded, terminating
100682.16/13847.90	% SZS status Ended for HL405369+4.p
100688.04/13848.71	% SZS status Started for HL405369+5.p
100688.04/13848.71	% SZS status GaveUp for HL405369+5.p
100688.04/13848.71	% SZS status Ended for HL405369+5.p
100704.23/13850.75	% SZS status Started for HL405371+5.p
100704.23/13850.75	% SZS status GaveUp for HL405371+5.p
100704.23/13850.75	% SZS status Ended for HL405371+5.p
100705.38/13850.93	% SZS status Started for HL405371+4.p
100705.38/13850.93	% SZS status GaveUp for HL405371+4.p
100705.38/13850.93	eprover: CPU time limit exceeded, terminating
100705.38/13850.93	% SZS status Ended for HL405371+4.p
100719.12/13852.64	% SZS status Started for HL405372+5.p
100719.12/13852.64	% SZS status GaveUp for HL405372+5.p
100719.12/13852.64	% SZS status Ended for HL405372+5.p
100724.30/13853.41	% SZS status Started for HL405372+4.p
100724.30/13853.41	% SZS status GaveUp for HL405372+4.p
100724.30/13853.41	eprover: CPU time limit exceeded, terminating
100724.30/13853.41	% SZS status Ended for HL405372+4.p
100753.82/13857.00	% SZS status Started for HL405373+5.p
100753.82/13857.00	% SZS status GaveUp for HL405373+5.p
100753.82/13857.00	% SZS status Ended for HL405373+5.p
100757.15/13857.36	% SZS status Started for HL405373+4.p
100757.15/13857.36	% SZS status GaveUp for HL405373+4.p
100757.15/13857.36	eprover: CPU time limit exceeded, terminating
100757.15/13857.36	% SZS status Ended for HL405373+4.p
100765.89/13858.48	% SZS status Started for HL405376+5.p
100765.89/13858.48	% SZS status Theorem for HL405376+5.p
100765.89/13858.48	% SZS status Ended for HL405376+5.p
100767.38/13858.72	% SZS status Started for HL405374+5.p
100767.38/13858.72	% SZS status GaveUp for HL405374+5.p
100767.38/13858.72	% SZS status Ended for HL405374+5.p
100768.06/13858.83	% SZS status Started for HL405374+4.p
100768.06/13858.83	% SZS status GaveUp for HL405374+4.p
100768.06/13858.83	eprover: CPU time limit exceeded, terminating
100768.06/13858.83	% SZS status Ended for HL405374+4.p
100790.70/13861.71	% SZS status Started for HL405376+4.p
100790.70/13861.71	% SZS status GaveUp for HL405376+4.p
100790.70/13861.71	eprover: CPU time limit exceeded, terminating
100790.70/13861.71	% SZS status Ended for HL405376+4.p
100804.59/13863.42	% SZS status Started for HL405377+5.p
100804.59/13863.42	% SZS status GaveUp for HL405377+5.p
100804.59/13863.42	% SZS status Ended for HL405377+5.p
100806.91/13863.61	% SZS status Started for HL405377+4.p
100806.91/13863.61	% SZS status GaveUp for HL405377+4.p
100806.91/13863.61	eprover: CPU time limit exceeded, terminating
100806.91/13863.61	% SZS status Ended for HL405377+4.p
100836.70/13867.35	% SZS status Started for HL405378+5.p
100836.70/13867.35	% SZS status GaveUp for HL405378+5.p
100836.70/13867.35	% SZS status Ended for HL405378+5.p
100845.27/13868.48	% SZS status Started for HL405378+4.p
100845.27/13868.48	% SZS status GaveUp for HL405378+4.p
100845.27/13868.48	eprover: CPU time limit exceeded, terminating
100845.27/13868.48	% SZS status Ended for HL405378+4.p
100847.48/13868.74	% SZS status Started for HL405379+5.p
100847.48/13868.74	% SZS status GaveUp for HL405379+5.p
100847.48/13868.74	% SZS status Ended for HL405379+5.p
100852.80/13869.40	% SZS status Started for HL405379+4.p
100852.80/13869.40	% SZS status GaveUp for HL405379+4.p
100852.80/13869.40	eprover: CPU time limit exceeded, terminating
100852.80/13869.40	% SZS status Ended for HL405379+4.p
100854.62/13869.76	% SZS status Started for HL405380+4.p
100854.62/13869.76	% SZS status GaveUp for HL405380+4.p
100854.62/13869.76	eprover: CPU time limit exceeded, terminating
100854.62/13869.76	% SZS status Ended for HL405380+4.p
100866.92/13871.18	% SZS status Started for HL405381+5.p
100866.92/13871.18	% SZS status Theorem for HL405381+5.p
100866.92/13871.18	% SZS status Ended for HL405381+5.p
100871.69/13871.74	% SZS status Started for HL405380+5.p
100871.69/13871.74	% SZS status GaveUp for HL405380+5.p
100871.69/13871.74	% SZS status Ended for HL405380+5.p
100892.48/13874.41	% SZS status Started for HL405381+4.p
100892.48/13874.41	% SZS status GaveUp for HL405381+4.p
100892.48/13874.41	eprover: CPU time limit exceeded, terminating
100892.48/13874.41	% SZS status Ended for HL405381+4.p
100923.46/13878.46	% SZS status Started for HL405382+4.p
100923.46/13878.46	% SZS status GaveUp for HL405382+4.p
100923.46/13878.46	eprover: CPU time limit exceeded, terminating
100923.46/13878.46	% SZS status Ended for HL405382+4.p
100925.63/13878.54	% SZS status Started for HL405382+5.p
100925.63/13878.54	% SZS status GaveUp for HL405382+5.p
100925.63/13878.54	% SZS status Ended for HL405382+5.p
100932.40/13879.49	% SZS status Started for HL405383+5.p
100932.40/13879.49	% SZS status GaveUp for HL405383+5.p
100932.40/13879.49	% SZS status Ended for HL405383+5.p
100932.99/13879.66	% SZS status Started for HL405383+4.p
100932.99/13879.66	% SZS status GaveUp for HL405383+4.p
100932.99/13879.66	eprover: CPU time limit exceeded, terminating
100932.99/13879.66	% SZS status Ended for HL405383+4.p
100954.61/13881.05	% SZS status Started for HL405385+4.p
100954.61/13881.05	% SZS status GaveUp for HL405385+4.p
100954.61/13881.05	eprover: CPU time limit exceeded, terminating
100954.61/13881.05	% SZS status Ended for HL405385+4.p
100955.83/13881.21	% SZS status Started for HL405385+5.p
100955.83/13881.21	% SZS status GaveUp for HL405385+5.p
100955.83/13881.21	% SZS status Ended for HL405385+5.p
100960.32/13881.86	% SZS status Started for HL405387+5.p
100960.32/13881.86	% SZS status Theorem for HL405387+5.p
100960.32/13881.86	% SZS status Ended for HL405387+5.p
100966.46/13882.69	% SZS status Started for HL405387+4.p
100966.46/13882.69	% SZS status GaveUp for HL405387+4.p
100966.46/13882.69	eprover: CPU time limit exceeded, terminating
100966.46/13882.69	% SZS status Ended for HL405387+4.p
101002.13/13886.09	% SZS status Started for HL405388+5.p
101002.13/13886.09	% SZS status Theorem for HL405388+5.p
101002.13/13886.09	% SZS status Ended for HL405388+5.p
101032.55/13889.67	% SZS status Started for HL405389+5.p
101032.55/13889.67	% SZS status GaveUp for HL405389+5.p
101032.55/13889.67	% SZS status Ended for HL405389+5.p
101033.68/13889.84	% SZS status Started for HL405388+4.p
101033.68/13889.84	% SZS status GaveUp for HL405388+4.p
101033.68/13889.84	eprover: CPU time limit exceeded, terminating
101033.68/13889.84	% SZS status Ended for HL405388+4.p
101038.05/13890.41	% SZS status Started for HL405389+4.p
101038.05/13890.41	% SZS status GaveUp for HL405389+4.p
101038.05/13890.41	eprover: CPU time limit exceeded, terminating
101038.05/13890.41	% SZS status Ended for HL405389+4.p
101045.23/13891.25	% SZS status Started for HL405390+5.p
101045.23/13891.25	% SZS status GaveUp for HL405390+5.p
101045.23/13891.25	% SZS status Ended for HL405390+5.p
101051.07/13892.02	% SZS status Started for HL405390+4.p
101051.07/13892.02	% SZS status GaveUp for HL405390+4.p
101051.07/13892.02	eprover: CPU time limit exceeded, terminating
101051.07/13892.02	% SZS status Ended for HL405390+4.p
101056.27/13892.70	% SZS status Started for HL405391+5.p
101056.27/13892.70	% SZS status GaveUp for HL405391+5.p
101056.27/13892.70	% SZS status Ended for HL405391+5.p
101057.11/13892.84	% SZS status Started for HL405391+4.p
101057.11/13892.84	% SZS status GaveUp for HL405391+4.p
101057.11/13892.84	eprover: CPU time limit exceeded, terminating
101057.11/13892.84	% SZS status Ended for HL405391+4.p
101092.65/13897.31	% SZS status Started for HL405392+4.p
101092.65/13897.31	% SZS status GaveUp for HL405392+4.p
101092.65/13897.31	eprover: CPU time limit exceeded, terminating
101092.65/13897.31	% SZS status Ended for HL405392+4.p
101112.05/13899.65	% SZS status Started for HL405396+5.p
101112.05/13899.65	% SZS status Theorem for HL405396+5.p
101112.05/13899.65	% SZS status Ended for HL405396+5.p
101112.05/13899.69	% SZS status Started for HL405392+5.p
101112.05/13899.69	% SZS status GaveUp for HL405392+5.p
101112.05/13899.69	% SZS status Ended for HL405392+5.p
101117.52/13900.41	% SZS status Started for HL405393+5.p
101117.52/13900.41	% SZS status GaveUp for HL405393+5.p
101117.52/13900.41	% SZS status Ended for HL405393+5.p
101120.85/13900.77	% SZS status Started for HL405393+4.p
101120.85/13900.77	% SZS status GaveUp for HL405393+4.p
101120.85/13900.77	eprover: CPU time limit exceeded, terminating
101120.85/13900.77	% SZS status Ended for HL405393+4.p
101131.65/13902.15	% SZS status Started for HL405396+4.p
101131.65/13902.15	% SZS status GaveUp for HL405396+4.p
101131.65/13902.15	eprover: CPU time limit exceeded, terminating
101131.65/13902.15	% SZS status Ended for HL405396+4.p
101141.48/13903.42	% SZS status Started for HL405397+5.p
101141.48/13903.42	% SZS status GaveUp for HL405397+5.p
101141.48/13903.42	% SZS status Ended for HL405397+5.p
101143.90/13903.69	% SZS status Started for HL405397+4.p
101143.90/13903.69	% SZS status GaveUp for HL405397+4.p
101143.90/13903.69	eprover: CPU time limit exceeded, terminating
101143.90/13903.69	% SZS status Ended for HL405397+4.p
101171.70/13907.16	% SZS status Started for HL405398+5.p
101171.70/13907.16	% SZS status Theorem for HL405398+5.p
101171.70/13907.16	% SZS status Ended for HL405398+5.p
101177.28/13907.94	% SZS status Started for HL405399+5.p
101177.28/13907.94	% SZS status Theorem for HL405399+5.p
101177.28/13907.94	% SZS status Ended for HL405399+5.p
101180.23/13908.24	% SZS status Started for HL405398+4.p
101180.23/13908.24	% SZS status GaveUp for HL405398+4.p
101180.23/13908.24	eprover: CPU time limit exceeded, terminating
101180.23/13908.24	% SZS status Ended for HL405398+4.p
101197.90/13910.59	% SZS status Started for HL405399+4.p
101197.90/13910.59	% SZS status GaveUp for HL405399+4.p
101197.90/13910.59	eprover: CPU time limit exceeded, terminating
101197.90/13910.59	% SZS status Ended for HL405399+4.p
101203.06/13911.11	% SZS status Started for HL405401+5.p
101203.06/13911.11	% SZS status Theorem for HL405401+5.p
101203.06/13911.11	% SZS status Ended for HL405401+5.p
101207.52/13911.69	% SZS status Started for HL405400+4.p
101207.52/13911.69	% SZS status GaveUp for HL405400+4.p
101207.52/13911.69	eprover: CPU time limit exceeded, terminating
101207.52/13911.69	% SZS status Ended for HL405400+4.p
101211.15/13912.15	% SZS status Started for HL405400+5.p
101211.15/13912.15	% SZS status GaveUp for HL405400+5.p
101211.15/13912.15	% SZS status Ended for HL405400+5.p
101231.86/13914.93	% SZS status Started for HL405401+4.p
101231.86/13914.93	% SZS status GaveUp for HL405401+4.p
101231.86/13914.93	eprover: CPU time limit exceeded, terminating
101231.86/13914.93	% SZS status Ended for HL405401+4.p
101237.05/13915.49	% SZS status Started for HL405402+5.p
101237.05/13915.49	% SZS status Theorem for HL405402+5.p
101237.05/13915.49	% SZS status Ended for HL405402+5.p
101258.85/13918.18	% SZS status Started for HL405402+4.p
101258.85/13918.18	% SZS status GaveUp for HL405402+4.p
101258.85/13918.18	eprover: CPU time limit exceeded, terminating
101258.85/13918.18	% SZS status Ended for HL405402+4.p
101266.81/13919.19	% SZS status Started for HL405403+4.p
101266.81/13919.19	% SZS status GaveUp for HL405403+4.p
101266.81/13919.19	eprover: CPU time limit exceeded, terminating
101266.81/13919.19	% SZS status Ended for HL405403+4.p
101267.39/13919.23	% SZS status Started for HL405404+5.p
101267.39/13919.23	% SZS status Theorem for HL405404+5.p
101267.39/13919.23	% SZS status Ended for HL405404+5.p
101277.75/13920.58	% SZS status Started for HL405403+5.p
101277.75/13920.58	% SZS status GaveUp for HL405403+5.p
101277.75/13920.58	% SZS status Ended for HL405403+5.p
101289.64/13922.04	% SZS status Started for HL405404+4.p
101289.64/13922.04	% SZS status GaveUp for HL405404+4.p
101289.64/13922.04	eprover: CPU time limit exceeded, terminating
101289.64/13922.04	% SZS status Ended for HL405404+4.p
101293.54/13922.52	% SZS status Started for HL405406+5.p
101293.54/13922.52	% SZS status Theorem for HL405406+5.p
101293.54/13922.52	% SZS status Ended for HL405406+5.p
101299.63/13923.32	% SZS status Started for HL405406+4.p
101299.63/13923.32	% SZS status GaveUp for HL405406+4.p
101299.63/13923.32	eprover: CPU time limit exceeded, terminating
101299.63/13923.32	% SZS status Ended for HL405406+4.p
101317.73/13925.69	% SZS status Started for HL405407+5.p
101317.73/13925.69	% SZS status Theorem for HL405407+5.p
101317.73/13925.69	% SZS status Ended for HL405407+5.p
101324.98/13926.48	% SZS status Started for HL405407+4.p
101324.98/13926.48	% SZS status GaveUp for HL405407+4.p
101324.98/13926.48	eprover: CPU time limit exceeded, terminating
101324.98/13926.48	% SZS status Ended for HL405407+4.p
101343.87/13928.90	% SZS status Started for HL405408+5.p
101343.87/13928.90	% SZS status GaveUp for HL405408+5.p
101343.87/13928.90	% SZS status Ended for HL405408+5.p
101348.14/13929.43	% SZS status Started for HL405408+4.p
101348.14/13929.43	% SZS status GaveUp for HL405408+4.p
101348.14/13929.43	eprover: CPU time limit exceeded, terminating
101348.14/13929.43	% SZS status Ended for HL405408+4.p
101365.52/13931.53	% SZS status Started for HL405409+5.p
101365.52/13931.53	% SZS status GaveUp for HL405409+5.p
101365.52/13931.53	% SZS status Ended for HL405409+5.p
101375.17/13932.81	% SZS status Started for HL405410+5.p
101375.17/13932.81	% SZS status GaveUp for HL405410+5.p
101375.17/13932.81	% SZS status Ended for HL405410+5.p
101379.24/13933.27	% SZS status Started for HL405411+5.p
101379.24/13933.27	% SZS status Theorem for HL405411+5.p
101379.24/13933.27	% SZS status Ended for HL405411+5.p
101424.16/13938.95	% SZS status Started for HL405412+5.p
101424.16/13938.95	% SZS status GaveUp for HL405412+5.p
101424.16/13938.95	% SZS status Ended for HL405412+5.p
101451.08/13942.37	% SZS status Started for HL405413+5.p
101451.08/13942.37	% SZS status GaveUp for HL405413+5.p
101451.08/13942.37	% SZS status Ended for HL405413+5.p
101478.34/13945.81	% SZS status Started for HL405414+5.p
101478.34/13945.81	% SZS status Theorem for HL405414+5.p
101478.34/13945.81	% SZS status Ended for HL405414+5.p
101486.34/13946.84	% SZS status Started for HL405409+4.p
101486.34/13946.84	% SZS status GaveUp for HL405409+4.p
101486.34/13946.84	eprover: CPU time limit exceeded, terminating
101486.34/13946.84	% SZS status Ended for HL405409+4.p
101501.39/13948.69	% SZS status Started for HL405410+4.p
101501.39/13948.69	% SZS status GaveUp for HL405410+4.p
101501.39/13948.69	eprover: CPU time limit exceeded, terminating
101501.39/13948.69	% SZS status Ended for HL405410+4.p
101528.99/13952.14	% SZS status Started for HL405411+4.p
101528.99/13952.14	% SZS status GaveUp for HL405411+4.p
101528.99/13952.14	eprover: CPU time limit exceeded, terminating
101528.99/13952.14	% SZS status Ended for HL405411+4.p
101553.46/13955.25	% SZS status Started for HL405412+4.p
101553.46/13955.25	% SZS status GaveUp for HL405412+4.p
101553.46/13955.25	eprover: CPU time limit exceeded, terminating
101553.46/13955.25	% SZS status Ended for HL405412+4.p
101554.93/13955.47	% SZS status Started for HL405415+5.p
101554.93/13955.47	% SZS status GaveUp for HL405415+5.p
101554.93/13955.47	% SZS status Ended for HL405415+5.p
101570.84/13957.46	% SZS status Started for HL405416+4.p
101570.84/13957.46	% SZS status GaveUp for HL405416+4.p
101570.84/13957.46	eprover: CPU time limit exceeded, terminating
101570.84/13957.46	% SZS status Ended for HL405416+4.p
101574.38/13957.87	% SZS status Started for HL405413+4.p
101574.38/13957.87	% SZS status GaveUp for HL405413+4.p
101574.38/13957.87	eprover: CPU time limit exceeded, terminating
101574.38/13957.87	% SZS status Ended for HL405413+4.p
101577.29/13958.28	% SZS status Started for HL405416+5.p
101577.29/13958.28	% SZS status GaveUp for HL405416+5.p
101577.29/13958.28	% SZS status Ended for HL405416+5.p
101586.87/13959.47	% SZS status Started for HL405414+4.p
101586.87/13959.47	% SZS status GaveUp for HL405414+4.p
101586.87/13959.47	eprover: CPU time limit exceeded, terminating
101586.87/13959.47	% SZS status Ended for HL405414+4.p
101609.42/13962.27	% SZS status Started for HL405417+5.p
101609.42/13962.27	% SZS status Theorem for HL405417+5.p
101609.42/13962.27	% SZS status Ended for HL405417+5.p
101645.96/13967.00	% SZS status Started for HL405418+5.p
101645.96/13967.00	% SZS status GaveUp for HL405418+5.p
101645.96/13967.00	% SZS status Ended for HL405418+5.p
101653.09/13967.85	% SZS status Started for HL405419+5.p
101653.09/13967.85	% SZS status GaveUp for HL405419+5.p
101653.09/13967.85	% SZS status Ended for HL405419+5.p
101661.08/13968.79	% SZS status Started for HL405415+4.p
101661.08/13968.79	% SZS status GaveUp for HL405415+4.p
101661.08/13968.79	eprover: CPU time limit exceeded, terminating
101661.08/13968.79	% SZS status Ended for HL405415+4.p
101685.01/13971.80	% SZS status Started for HL405420+5.p
101685.01/13971.80	% SZS status GaveUp for HL405420+5.p
101685.01/13971.80	% SZS status Ended for HL405420+5.p
101709.57/13974.99	% SZS status Started for HL405421+5.p
101709.57/13974.99	% SZS status Theorem for HL405421+5.p
101709.57/13974.99	% SZS status Ended for HL405421+5.p
101735.40/13978.29	% SZS status Started for HL405417+4.p
101735.40/13978.29	% SZS status GaveUp for HL405417+4.p
101735.40/13978.29	eprover: CPU time limit exceeded, terminating
101735.40/13978.29	% SZS status Ended for HL405417+4.p
101761.26/13981.47	% SZS status Started for HL405422+5.p
101761.26/13981.47	% SZS status GaveUp for HL405422+5.p
101761.26/13981.47	% SZS status Ended for HL405422+5.p
101762.62/13981.68	% SZS status Started for HL405418+4.p
101762.62/13981.68	% SZS status GaveUp for HL405418+4.p
101762.62/13981.68	eprover: CPU time limit exceeded, terminating
101762.62/13981.68	% SZS status Ended for HL405418+4.p
101781.45/13983.98	% SZS status Started for HL405419+4.p
101781.45/13983.98	% SZS status GaveUp for HL405419+4.p
101781.45/13983.98	eprover: CPU time limit exceeded, terminating
101781.45/13983.98	% SZS status Ended for HL405419+4.p
101794.34/13985.63	% SZS status Started for HL405420+4.p
101794.34/13985.63	% SZS status GaveUp for HL405420+4.p
101794.34/13985.63	eprover: CPU time limit exceeded, terminating
101794.34/13985.63	% SZS status Ended for HL405420+4.p
101797.67/13986.10	% SZS status Started for HL405423+4.p
101797.67/13986.10	% SZS status GaveUp for HL405423+4.p
101797.67/13986.10	eprover: CPU time limit exceeded, terminating
101797.67/13986.10	% SZS status Ended for HL405423+4.p
101812.05/13987.82	% SZS status Started for HL405423+5.p
101812.05/13987.82	% SZS status GaveUp for HL405423+5.p
101812.05/13987.82	% SZS status Ended for HL405423+5.p
101840.12/13991.41	% SZS status Started for HL405424+5.p
101840.12/13991.41	% SZS status GaveUp for HL405424+5.p
101840.12/13991.41	% SZS status Ended for HL405424+5.p
101855.02/13993.23	% SZS status Started for HL405421+4.p
101855.02/13993.23	% SZS status GaveUp for HL405421+4.p
101855.02/13993.23	eprover: CPU time limit exceeded, terminating
101855.02/13993.23	% SZS status Ended for HL405421+4.p
101862.74/13994.22	% SZS status Started for HL405426+4.p
101862.74/13994.22	% SZS status GaveUp for HL405426+4.p
101862.74/13994.22	eprover: CPU time limit exceeded, terminating
101862.74/13994.22	% SZS status Ended for HL405426+4.p
101868.77/13995.01	% SZS status Started for HL405422+4.p
101868.77/13995.01	% SZS status GaveUp for HL405422+4.p
101868.77/13995.01	eprover: CPU time limit exceeded, terminating
101868.77/13995.01	% SZS status Ended for HL405422+4.p
101870.55/13995.17	% SZS status Started for HL405426+5.p
101870.55/13995.17	% SZS status GaveUp for HL405426+5.p
101870.55/13995.17	% SZS status Ended for HL405426+5.p
101879.62/13996.38	% SZS status Started for HL405428+4.p
101879.62/13996.38	% SZS status GaveUp for HL405428+4.p
101879.62/13996.38	eprover: CPU time limit exceeded, terminating
101879.62/13996.38	% SZS status Ended for HL405428+4.p
101891.00/13997.76	% SZS status Started for HL405428+5.p
101891.00/13997.76	% SZS status GaveUp for HL405428+5.p
101891.00/13997.76	% SZS status Ended for HL405428+5.p
101923.06/14001.78	% SZS status Started for HL405429+4.p
101923.06/14001.78	% SZS status GaveUp for HL405429+4.p
101923.06/14001.78	eprover: CPU time limit exceeded, terminating
101923.06/14001.78	% SZS status Ended for HL405429+4.p
101931.48/14002.85	% SZS status Started for HL405429+5.p
101931.48/14002.85	% SZS status GaveUp for HL405429+5.p
101931.48/14002.85	% SZS status Ended for HL405429+5.p
101944.55/14004.51	% SZS status Started for HL405430+5.p
101944.55/14004.51	% SZS status GaveUp for HL405430+5.p
101944.55/14004.51	% SZS status Ended for HL405430+5.p
101955.67/14005.89	% SZS status Started for HL405431+5.p
101955.67/14005.89	% SZS status GaveUp for HL405431+5.p
101955.67/14005.89	% SZS status Ended for HL405431+5.p
101970.59/14007.74	% SZS status Started for HL405424+4.p
101970.59/14007.74	% SZS status GaveUp for HL405424+4.p
101970.59/14007.74	eprover: CPU time limit exceeded, terminating
101970.59/14007.74	% SZS status Ended for HL405424+4.p
101998.85/14011.35	% SZS status Started for HL405432+5.p
101998.85/14011.35	% SZS status GaveUp for HL405432+5.p
101998.85/14011.35	% SZS status Ended for HL405432+5.p
102020.17/14014.01	% SZS status Started for HL405433+5.p
102020.17/14014.01	% SZS status GaveUp for HL405433+5.p
102020.17/14014.01	% SZS status Ended for HL405433+5.p
102046.49/14017.29	% SZS status Started for HL405434+5.p
102046.49/14017.29	% SZS status GaveUp for HL405434+5.p
102046.49/14017.29	% SZS status Ended for HL405434+5.p
102074.12/14020.58	% SZS status Started for HL405430+4.p
102074.12/14020.58	% SZS status GaveUp for HL405430+4.p
102074.12/14020.58	eprover: CPU time limit exceeded, terminating
102074.12/14020.58	% SZS status Ended for HL405430+4.p
102079.66/14021.22	% SZS status Started for HL405431+4.p
102079.66/14021.22	% SZS status GaveUp for HL405431+4.p
102079.66/14021.22	eprover: CPU time limit exceeded, terminating
102079.66/14021.22	% SZS status Ended for HL405431+4.p
102097.66/14023.50	% SZS status Started for HL405435+5.p
102097.66/14023.50	% SZS status GaveUp for HL405435+5.p
102097.66/14023.50	% SZS status Ended for HL405435+5.p
102100.09/14023.85	% SZS status Started for HL405432+4.p
102100.09/14023.85	% SZS status GaveUp for HL405432+4.p
102100.09/14023.85	eprover: CPU time limit exceeded, terminating
102100.09/14023.85	% SZS status Ended for HL405432+4.p
102141.72/14029.12	% SZS status Started for HL405433+4.p
102141.72/14029.12	% SZS status GaveUp for HL405433+4.p
102141.72/14029.12	eprover: CPU time limit exceeded, terminating
102141.72/14029.12	% SZS status Ended for HL405433+4.p
102150.27/14030.19	% SZS status Started for HL405436+5.p
102150.27/14030.19	% SZS status GaveUp for HL405436+5.p
102150.27/14030.19	% SZS status Ended for HL405436+5.p
102159.93/14031.48	% SZS status Started for HL405437+4.p
102159.93/14031.48	% SZS status GaveUp for HL405437+4.p
102159.93/14031.48	eprover: CPU time limit exceeded, terminating
102159.93/14031.48	% SZS status Ended for HL405437+4.p
102169.30/14032.57	% SZS status Started for HL405434+4.p
102169.30/14032.57	% SZS status GaveUp for HL405434+4.p
102169.30/14032.57	eprover: CPU time limit exceeded, terminating
102169.30/14032.57	% SZS status Ended for HL405434+4.p
102173.65/14033.07	% SZS status Started for HL405437+5.p
102173.65/14033.07	% SZS status GaveUp for HL405437+5.p
102173.65/14033.07	% SZS status Ended for HL405437+5.p
102207.91/14037.42	% SZS status Started for HL405435+4.p
102207.91/14037.42	% SZS status GaveUp for HL405435+4.p
102207.91/14037.42	eprover: CPU time limit exceeded, terminating
102207.91/14037.42	% SZS status Ended for HL405435+4.p
102217.66/14038.65	% SZS status Started for HL405438+5.p
102217.66/14038.65	% SZS status GaveUp for HL405438+5.p
102217.66/14038.65	% SZS status Ended for HL405438+5.p
102234.11/14040.79	% SZS status Started for HL405439+4.p
102234.11/14040.79	% SZS status GaveUp for HL405439+4.p
102234.11/14040.79	eprover: CPU time limit exceeded, terminating
102234.11/14040.79	% SZS status Ended for HL405439+4.p
102236.47/14040.97	% SZS status Started for HL405439+5.p
102236.47/14040.97	% SZS status GaveUp for HL405439+5.p
102236.47/14040.97	% SZS status Ended for HL405439+5.p
102251.04/14042.82	% SZS status Started for HL405443+5.p
102251.04/14042.82	% SZS status GaveUp for HL405443+5.p
102251.04/14042.82	% SZS status Ended for HL405443+5.p
102256.40/14043.50	% SZS status Started for HL405436+4.p
102256.40/14043.50	% SZS status GaveUp for HL405436+4.p
102256.40/14043.50	eprover: CPU time limit exceeded, terminating
102256.40/14043.50	% SZS status Ended for HL405436+4.p
102288.16/14047.60	% SZS status Started for HL405444+4.p
102288.16/14047.60	% SZS status GaveUp for HL405444+4.p
102288.16/14047.60	eprover: CPU time limit exceeded, terminating
102288.16/14047.60	% SZS status Ended for HL405444+4.p
102293.58/14048.23	% SZS status Started for HL405444+5.p
102293.58/14048.23	% SZS status GaveUp for HL405444+5.p
102293.58/14048.23	% SZS status Ended for HL405444+5.p
102307.39/14049.99	% SZS status Started for HL405438+4.p
102307.39/14049.99	% SZS status GaveUp for HL405438+4.p
102307.39/14049.99	eprover: CPU time limit exceeded, terminating
102307.39/14049.99	% SZS status Ended for HL405438+4.p
102310.94/14050.37	% SZS status Started for HL405445+5.p
102310.94/14050.37	% SZS status GaveUp for HL405445+5.p
102310.94/14050.37	% SZS status Ended for HL405445+5.p
102332.43/14053.04	% SZS status Started for HL405446+5.p
102332.43/14053.04	% SZS status GaveUp for HL405446+5.p
102332.43/14053.04	% SZS status Ended for HL405446+5.p
102366.83/14057.45	% SZS status Started for HL405447+5.p
102366.83/14057.45	% SZS status GaveUp for HL405447+5.p
102366.83/14057.45	% SZS status Ended for HL405447+5.p
102377.73/14058.77	% SZS status Started for HL405443+4.p
102377.73/14058.77	% SZS status GaveUp for HL405443+4.p
102377.73/14058.77	eprover: CPU time limit exceeded, terminating
102377.73/14058.77	% SZS status Ended for HL405443+4.p
102387.01/14059.94	% SZS status Started for HL405448+5.p
102387.01/14059.94	% SZS status GaveUp for HL405448+5.p
102387.01/14059.94	% SZS status Ended for HL405448+5.p
102443.06/14067.01	% SZS status Started for HL405449+5.p
102443.06/14067.01	% SZS status GaveUp for HL405449+5.p
102443.06/14067.01	% SZS status Ended for HL405449+5.p
102444.22/14067.19	% SZS status Started for HL405445+4.p
102444.22/14067.19	% SZS status GaveUp for HL405445+4.p
102444.22/14067.19	eprover: CPU time limit exceeded, terminating
102444.22/14067.19	% SZS status Ended for HL405445+4.p
102457.38/14068.87	% SZS status Started for HL405446+4.p
102457.38/14068.87	% SZS status GaveUp for HL405446+4.p
102457.38/14068.87	eprover: CPU time limit exceeded, terminating
102457.38/14068.87	% SZS status Ended for HL405446+4.p
102462.99/14069.46	% SZS status Started for HL405451+5.p
102462.99/14069.46	% SZS status GaveUp for HL405451+5.p
102462.99/14069.46	% SZS status Ended for HL405451+5.p
102498.93/14074.02	% SZS status Started for HL405447+4.p
102498.93/14074.02	% SZS status GaveUp for HL405447+4.p
102498.93/14074.02	eprover: CPU time limit exceeded, terminating
102498.93/14074.02	% SZS status Ended for HL405447+4.p
102515.64/14076.10	% SZS status Started for HL405448+4.p
102515.64/14076.10	% SZS status GaveUp for HL405448+4.p
102515.64/14076.10	eprover: CPU time limit exceeded, terminating
102515.64/14076.10	% SZS status Ended for HL405448+4.p
102519.99/14076.66	% SZS status Started for HL405453+5.p
102519.99/14076.66	% SZS status Theorem for HL405453+5.p
102519.99/14076.66	% SZS status Ended for HL405453+5.p
102520.94/14076.80	% SZS status Started for HL405452+5.p
102520.94/14076.80	% SZS status GaveUp for HL405452+5.p
102520.94/14076.80	% SZS status Ended for HL405452+5.p
102539.18/14079.15	% SZS status Started for HL405453+4.p
102539.18/14079.15	% SZS status GaveUp for HL405453+4.p
102539.18/14079.15	eprover: CPU time limit exceeded, terminating
102539.18/14079.15	% SZS status Ended for HL405453+4.p
102540.62/14079.25	% SZS status Started for HL405449+4.p
102540.62/14079.25	% SZS status GaveUp for HL405449+4.p
102540.62/14079.25	eprover: CPU time limit exceeded, terminating
102540.62/14079.25	% SZS status Ended for HL405449+4.p
102585.97/14085.03	% SZS status Started for HL405451+4.p
102585.97/14085.03	% SZS status GaveUp for HL405451+4.p
102585.97/14085.03	eprover: CPU time limit exceeded, terminating
102585.97/14085.03	% SZS status Ended for HL405451+4.p
102591.14/14085.65	% SZS status Started for HL405454+5.p
102591.14/14085.65	% SZS status GaveUp for HL405454+5.p
102591.14/14085.65	% SZS status Ended for HL405454+5.p
102598.34/14086.55	% SZS status Started for HL405455+5.p
102598.34/14086.55	% SZS status GaveUp for HL405455+5.p
102598.34/14086.55	% SZS status Ended for HL405455+5.p
102616.56/14088.83	% SZS status Started for HL405456+5.p
102616.56/14088.83	% SZS status GaveUp for HL405456+5.p
102616.56/14088.83	% SZS status Ended for HL405456+5.p
102650.71/14093.22	% SZS status Started for HL405452+4.p
102650.71/14093.22	% SZS status GaveUp for HL405452+4.p
102650.71/14093.22	eprover: CPU time limit exceeded, terminating
102650.71/14093.22	% SZS status Ended for HL405452+4.p
102666.95/14095.23	% SZS status Started for HL405459+5.p
102666.95/14095.23	% SZS status GaveUp for HL405459+5.p
102666.95/14095.23	% SZS status Ended for HL405459+5.p
102666.95/14095.25	% SZS status Started for HL405459+4.p
102666.95/14095.25	% SZS status GaveUp for HL405459+4.p
102666.95/14095.25	eprover: CPU time limit exceeded, terminating
102666.95/14095.25	% SZS status Ended for HL405459+4.p
102681.78/14097.08	% SZS status Started for HL405460+4.p
102681.78/14097.08	% SZS status GaveUp for HL405460+4.p
102681.78/14097.08	eprover: CPU time limit exceeded, terminating
102681.78/14097.08	% SZS status Ended for HL405460+4.p
102693.20/14098.53	% SZS status Started for HL405460+5.p
102693.20/14098.53	% SZS status GaveUp for HL405460+5.p
102693.20/14098.53	% SZS status Ended for HL405460+5.p
102706.29/14100.15	% SZS status Started for HL405454+4.p
102706.29/14100.15	% SZS status GaveUp for HL405454+4.p
102706.29/14100.15	eprover: CPU time limit exceeded, terminating
102706.29/14100.15	% SZS status Ended for HL405454+4.p
102723.41/14102.35	% SZS status Started for HL405461+5.p
102723.41/14102.35	% SZS status Theorem for HL405461+5.p
102723.41/14102.35	% SZS status Ended for HL405461+5.p
102729.48/14103.11	% SZS status Started for HL405455+4.p
102729.48/14103.11	% SZS status GaveUp for HL405455+4.p
102729.48/14103.11	eprover: CPU time limit exceeded, terminating
102729.48/14103.11	% SZS status Ended for HL405455+4.p
102749.57/14105.63	% SZS status Started for HL405456+4.p
102749.57/14105.63	% SZS status GaveUp for HL405456+4.p
102749.57/14105.63	eprover: CPU time limit exceeded, terminating
102749.57/14105.63	% SZS status Ended for HL405456+4.p
102756.84/14106.55	% SZS status Started for HL405462+5.p
102756.84/14106.55	% SZS status GaveUp for HL405462+5.p
102756.84/14106.55	% SZS status Ended for HL405462+5.p
102781.73/14109.65	% SZS status Started for HL405463+5.p
102781.73/14109.65	% SZS status GaveUp for HL405463+5.p
102781.73/14109.65	% SZS status Ended for HL405463+5.p
102786.49/14110.21	% SZS status Started for HL405465+5.p
102786.49/14110.21	% SZS status Theorem for HL405465+5.p
102786.49/14110.21	% SZS status Ended for HL405465+5.p
102812.09/14113.44	% SZS status Started for HL405466+5.p
102812.09/14113.44	% SZS status Theorem for HL405466+5.p
102812.09/14113.44	% SZS status Ended for HL405466+5.p
102832.38/14116.04	% SZS status Started for HL405466+4.p
102832.38/14116.04	% SZS status GaveUp for HL405466+4.p
102832.38/14116.04	eprover: CPU time limit exceeded, terminating
102832.38/14116.04	% SZS status Ended for HL405466+4.p
102860.43/14119.55	% SZS status Started for HL405461+4.p
102860.43/14119.55	% SZS status GaveUp for HL405461+4.p
102860.43/14119.55	eprover: CPU time limit exceeded, terminating
102860.43/14119.55	% SZS status Ended for HL405461+4.p
102862.70/14119.82	% SZS status Started for HL405467+5.p
102862.70/14119.82	% SZS status GaveUp for HL405467+5.p
102862.70/14119.82	% SZS status Ended for HL405467+5.p
102863.17/14119.97	% SZS status Started for HL405467+4.p
102863.17/14119.97	% SZS status GaveUp for HL405467+4.p
102863.17/14119.97	eprover: CPU time limit exceeded, terminating
102863.17/14119.97	% SZS status Ended for HL405467+4.p
102875.64/14121.43	% SZS status Started for HL405462+4.p
102875.64/14121.43	% SZS status GaveUp for HL405462+4.p
102875.64/14121.43	eprover: CPU time limit exceeded, terminating
102875.64/14121.43	% SZS status Ended for HL405462+4.p
102885.65/14122.84	% SZS status Started for HL405470+5.p
102885.65/14122.84	% SZS status Theorem for HL405470+5.p
102885.65/14122.84	% SZS status Ended for HL405470+5.p
102901.19/14124.69	% SZS status Started for HL405463+4.p
102901.19/14124.69	% SZS status GaveUp for HL405463+4.p
102901.19/14124.69	eprover: CPU time limit exceeded, terminating
102901.19/14124.69	% SZS status Ended for HL405463+4.p
102958.67/14128.69	% SZS status Started for HL405465+4.p
102958.67/14128.69	% SZS status GaveUp for HL405465+4.p
102958.67/14128.69	eprover: CPU time limit exceeded, terminating
102958.67/14128.69	% SZS status Ended for HL405465+4.p
102967.59/14129.80	% SZS status Started for HL405471+5.p
102967.59/14129.80	% SZS status GaveUp for HL405471+5.p
102967.59/14129.80	% SZS status Ended for HL405471+5.p
102976.09/14130.92	% SZS status Started for HL405472+5.p
102976.09/14130.92	% SZS status GaveUp for HL405472+5.p
102976.09/14130.92	% SZS status Ended for HL405472+5.p
103001.30/14134.29	% SZS status Started for HL405473+5.p
103001.30/14134.29	% SZS status GaveUp for HL405473+5.p
103001.30/14134.29	% SZS status Ended for HL405473+5.p
103041.02/14139.12	% SZS status Started for HL405474+4.p
103041.02/14139.12	% SZS status GaveUp for HL405474+4.p
103041.02/14139.12	eprover: CPU time limit exceeded, terminating
103041.02/14139.12	% SZS status Ended for HL405474+4.p
103043.50/14139.38	% SZS status Started for HL405474+5.p
103043.50/14139.38	% SZS status GaveUp for HL405474+5.p
103043.50/14139.38	% SZS status Ended for HL405474+5.p
103046.34/14139.82	% SZS status Started for HL405470+4.p
103046.34/14139.82	% SZS status GaveUp for HL405470+4.p
103046.34/14139.82	eprover: CPU time limit exceeded, terminating
103046.34/14139.82	% SZS status Ended for HL405470+4.p
103079.66/14143.95	% SZS status Started for HL405475+5.p
103079.66/14143.95	% SZS status GaveUp for HL405475+5.p
103079.66/14143.95	% SZS status Ended for HL405475+5.p
103095.15/14145.89	% SZS status Started for HL405471+4.p
103095.15/14145.89	% SZS status GaveUp for HL405471+4.p
103095.15/14145.89	eprover: CPU time limit exceeded, terminating
103095.15/14145.89	% SZS status Ended for HL405471+4.p
103097.63/14146.24	% SZS status Started for HL405472+4.p
103097.63/14146.24	% SZS status GaveUp for HL405472+4.p
103097.63/14146.24	eprover: CPU time limit exceeded, terminating
103097.63/14146.24	% SZS status Ended for HL405472+4.p
103118.82/14148.92	% SZS status Started for HL405476+5.p
103118.82/14148.92	% SZS status GaveUp for HL405476+5.p
103118.82/14148.92	% SZS status Ended for HL405476+5.p
103120.54/14149.09	% SZS status Started for HL405473+4.p
103120.54/14149.09	% SZS status GaveUp for HL405473+4.p
103120.54/14149.09	eprover: CPU time limit exceeded, terminating
103120.54/14149.09	% SZS status Ended for HL405473+4.p
103155.59/14153.50	% SZS status Started for HL405477+5.p
103155.59/14153.50	% SZS status GaveUp for HL405477+5.p
103155.59/14153.50	% SZS status Ended for HL405477+5.p
103173.98/14155.83	% SZS status Started for HL405479+5.p
103173.98/14155.83	% SZS status GaveUp for HL405479+5.p
103173.98/14155.83	% SZS status Ended for HL405479+5.p
103176.77/14156.18	% SZS status Started for HL405479+4.p
103176.77/14156.18	% SZS status GaveUp for HL405479+4.p
103176.77/14156.18	eprover: CPU time limit exceeded, terminating
103176.77/14156.18	% SZS status Ended for HL405479+4.p
103186.73/14157.41	% SZS status Started for HL405475+4.p
103186.73/14157.41	% SZS status GaveUp for HL405475+4.p
103186.73/14157.41	eprover: CPU time limit exceeded, terminating
103186.73/14157.41	% SZS status Ended for HL405475+4.p
103196.32/14158.62	% SZS status Started for HL405480+5.p
103196.32/14158.62	% SZS status GaveUp for HL405480+5.p
103196.32/14158.62	% SZS status Ended for HL405480+5.p
103237.30/14163.81	% SZS status Started for HL405481+4.p
103237.30/14163.81	% SZS status GaveUp for HL405481+4.p
103237.30/14163.81	eprover: CPU time limit exceeded, terminating
103237.30/14163.81	% SZS status Ended for HL405481+4.p
103249.97/14165.39	% SZS status Started for HL405481+5.p
103249.97/14165.39	% SZS status GaveUp for HL405481+5.p
103249.97/14165.39	% SZS status Ended for HL405481+5.p
103250.30/14165.40	% SZS status Started for HL405476+4.p
103250.30/14165.40	% SZS status GaveUp for HL405476+4.p
103250.30/14165.40	eprover: CPU time limit exceeded, terminating
103250.30/14165.40	% SZS status Ended for HL405476+4.p
103252.52/14165.95	% SZS status Started for HL405477+4.p
103252.52/14165.95	% SZS status GaveUp for HL405477+4.p
103252.52/14165.95	eprover: CPU time limit exceeded, terminating
103252.52/14165.95	% SZS status Ended for HL405477+4.p
103262.51/14167.04	% SZS status Started for HL405482+5.p
103262.51/14167.04	% SZS status GaveUp for HL405482+5.p
103262.51/14167.04	% SZS status Ended for HL405482+5.p
103295.15/14171.12	% SZS status Started for HL405483+5.p
103295.15/14171.12	% SZS status Theorem for HL405483+5.p
103295.15/14171.12	% SZS status Ended for HL405483+5.p
103326.21/14175.01	% SZS status Started for HL405480+4.p
103326.21/14175.01	% SZS status GaveUp for HL405480+4.p
103326.21/14175.01	eprover: CPU time limit exceeded, terminating
103326.21/14175.01	% SZS status Ended for HL405480+4.p
103328.74/14175.33	% SZS status Started for HL405484+5.p
103328.74/14175.33	% SZS status GaveUp for HL405484+5.p
103328.74/14175.33	% SZS status Ended for HL405484+5.p
103338.91/14176.64	% SZS status Started for HL405485+5.p
103338.91/14176.64	% SZS status GaveUp for HL405485+5.p
103338.91/14176.64	% SZS status Ended for HL405485+5.p
103384.80/14182.41	% SZS status Started for HL405482+4.p
103384.80/14182.41	% SZS status GaveUp for HL405482+4.p
103384.80/14182.41	eprover: CPU time limit exceeded, terminating
103384.80/14182.41	% SZS status Ended for HL405482+4.p
103404.01/14184.78	% SZS status Started for HL405483+4.p
103404.01/14184.78	% SZS status GaveUp for HL405483+4.p
103404.01/14184.78	eprover: CPU time limit exceeded, terminating
103404.01/14184.78	% SZS status Ended for HL405483+4.p
103404.81/14184.88	% SZS status Started for HL405486+5.p
103404.81/14184.88	% SZS status GaveUp for HL405486+5.p
103404.81/14184.88	% SZS status Ended for HL405486+5.p
103415.36/14186.26	% SZS status Started for HL405487+5.p
103415.36/14186.26	% SZS status GaveUp for HL405487+5.p
103415.36/14186.26	% SZS status Ended for HL405487+5.p
103456.99/14191.54	% SZS status Started for HL405484+4.p
103456.99/14191.54	% SZS status GaveUp for HL405484+4.p
103456.99/14191.54	eprover: CPU time limit exceeded, terminating
103456.99/14191.54	% SZS status Ended for HL405484+4.p
103459.67/14191.79	% SZS status Started for HL405489+5.p
103459.67/14191.79	% SZS status Theorem for HL405489+5.p
103459.67/14191.79	% SZS status Ended for HL405489+5.p
103461.74/14192.15	% SZS status Started for HL405485+4.p
103461.74/14192.15	% SZS status GaveUp for HL405485+4.p
103461.74/14192.15	eprover: CPU time limit exceeded, terminating
103461.74/14192.15	% SZS status Ended for HL405485+4.p
103467.89/14192.85	% SZS status Started for HL405489+4.p
103467.89/14192.85	% SZS status GaveUp for HL405489+4.p
103467.89/14192.85	eprover: CPU time limit exceeded, terminating
103467.89/14192.85	% SZS status Ended for HL405489+4.p
103491.76/14195.85	% SZS status Started for HL405490+5.p
103491.76/14195.85	% SZS status GaveUp for HL405490+5.p
103491.76/14195.85	% SZS status Ended for HL405490+5.p
103505.45/14197.54	% SZS status Started for HL405486+4.p
103505.45/14197.54	% SZS status GaveUp for HL405486+4.p
103505.45/14197.54	eprover: CPU time limit exceeded, terminating
103505.45/14197.54	% SZS status Ended for HL405486+4.p
103522.41/14199.64	% SZS status Started for HL405493+5.p
103522.41/14199.64	% SZS status Theorem for HL405493+5.p
103522.41/14199.64	% SZS status Ended for HL405493+5.p
103535.45/14201.33	% SZS status Started for HL405492+5.p
103535.45/14201.33	% SZS status GaveUp for HL405492+5.p
103535.45/14201.33	% SZS status Ended for HL405492+5.p
103536.08/14201.41	% SZS status Started for HL405487+4.p
103536.08/14201.41	% SZS status GaveUp for HL405487+4.p
103536.08/14201.41	eprover: CPU time limit exceeded, terminating
103536.08/14201.41	% SZS status Ended for HL405487+4.p
103538.41/14201.66	% SZS status Started for HL405492+4.p
103538.41/14201.66	% SZS status GaveUp for HL405492+4.p
103538.41/14201.66	eprover: CPU time limit exceeded, terminating
103538.41/14201.66	% SZS status Ended for HL405492+4.p
103582.80/14207.25	% SZS status Started for HL405494+5.p
103582.80/14207.25	% SZS status GaveUp for HL405494+5.p
103582.80/14207.25	% SZS status Ended for HL405494+5.p
103590.52/14208.25	% SZS status Started for HL405495+5.p
103590.52/14208.25	% SZS status Theorem for HL405495+5.p
103590.52/14208.25	% SZS status Ended for HL405495+5.p
103612.98/14211.10	% SZS status Started for HL405490+4.p
103612.98/14211.10	% SZS status GaveUp for HL405490+4.p
103612.98/14211.10	eprover: CPU time limit exceeded, terminating
103612.98/14211.10	% SZS status Ended for HL405490+4.p
103614.32/14211.23	% SZS status Started for HL405497+5.p
103614.32/14211.23	% SZS status GaveUp for HL405497+5.p
103614.32/14211.23	% SZS status Ended for HL405497+5.p
103666.20/14217.76	% SZS status Started for HL405498+5.p
103666.20/14217.76	% SZS status GaveUp for HL405498+5.p
103666.20/14217.76	% SZS status Ended for HL405498+5.p
103670.29/14218.29	% SZS status Started for HL405493+4.p
103670.29/14218.29	% SZS status GaveUp for HL405493+4.p
103670.29/14218.29	eprover: CPU time limit exceeded, terminating
103670.29/14218.29	% SZS status Ended for HL405493+4.p
103690.73/14220.92	% SZS status Started for HL405499+5.p
103690.73/14220.92	% SZS status GaveUp for HL405499+5.p
103690.73/14220.92	% SZS status Ended for HL405499+5.p
103700.09/14222.07	% SZS status Started for HL405494+4.p
103700.09/14222.07	% SZS status GaveUp for HL405494+4.p
103700.09/14222.07	eprover: CPU time limit exceeded, terminating
103700.09/14222.07	% SZS status Ended for HL405494+4.p
103730.50/14225.86	% SZS status Started for HL405495+4.p
103730.50/14225.86	% SZS status GaveUp for HL405495+4.p
103730.50/14225.86	eprover: CPU time limit exceeded, terminating
103730.50/14225.86	% SZS status Ended for HL405495+4.p
103745.51/14227.84	% SZS status Started for HL405500+5.p
103745.51/14227.84	% SZS status GaveUp for HL405500+5.p
103745.51/14227.84	% SZS status Ended for HL405500+5.p
103745.51/14227.85	% SZS status Started for HL405497+4.p
103745.51/14227.85	% SZS status GaveUp for HL405497+4.p
103745.51/14227.85	eprover: CPU time limit exceeded, terminating
103745.51/14227.85	% SZS status Ended for HL405497+4.p
103775.92/14231.60	% SZS status Started for HL405501+4.p
103775.92/14231.60	% SZS status GaveUp for HL405501+4.p
103775.92/14231.60	eprover: CPU time limit exceeded, terminating
103775.92/14231.60	% SZS status Ended for HL405501+4.p
103776.74/14231.72	% SZS status Started for HL405501+5.p
103776.74/14231.72	% SZS status GaveUp for HL405501+5.p
103776.74/14231.72	% SZS status Ended for HL405501+5.p
103790.75/14233.56	% SZS status Started for HL405498+4.p
103790.75/14233.56	% SZS status GaveUp for HL405498+4.p
103790.75/14233.56	eprover: CPU time limit exceeded, terminating
103790.75/14233.56	% SZS status Ended for HL405498+4.p
103820.96/14237.29	% SZS status Started for HL405502+5.p
103820.96/14237.29	% SZS status GaveUp for HL405502+5.p
103820.96/14237.29	% SZS status Ended for HL405502+5.p
103821.68/14237.37	% SZS status Started for HL405499+4.p
103821.68/14237.37	% SZS status GaveUp for HL405499+4.p
103821.68/14237.37	eprover: CPU time limit exceeded, terminating
103821.68/14237.37	% SZS status Ended for HL405499+4.p
103851.00/14241.07	% SZS status Started for HL405504+5.p
103851.00/14241.07	% SZS status GaveUp for HL405504+5.p
103851.00/14241.07	% SZS status Ended for HL405504+5.p
103866.77/14243.04	% SZS status Started for HL405505+5.p
103866.77/14243.04	% SZS status GaveUp for HL405505+5.p
103866.77/14243.04	% SZS status Ended for HL405505+5.p
103874.61/14244.04	% SZS status Started for HL405500+4.p
103874.61/14244.04	% SZS status GaveUp for HL405500+4.p
103874.61/14244.04	eprover: CPU time limit exceeded, terminating
103874.61/14244.04	% SZS status Ended for HL405500+4.p
103897.73/14246.93	% SZS status Started for HL405506+5.p
103897.73/14246.93	% SZS status GaveUp for HL405506+5.p
103897.73/14246.93	% SZS status Ended for HL405506+5.p
103937.78/14252.00	% SZS status Started for HL405502+4.p
103937.78/14252.00	% SZS status GaveUp for HL405502+4.p
103937.78/14252.00	eprover: CPU time limit exceeded, terminating
103937.78/14252.00	% SZS status Ended for HL405502+4.p
103942.34/14252.61	% SZS status Started for HL405507+5.p
103942.34/14252.61	% SZS status GaveUp for HL405507+5.p
103942.34/14252.61	% SZS status Ended for HL405507+5.p
103953.34/14253.94	% SZS status Started for HL405504+4.p
103953.34/14253.94	% SZS status GaveUp for HL405504+4.p
103953.34/14253.94	eprover: CPU time limit exceeded, terminating
103953.34/14253.94	% SZS status Ended for HL405504+4.p
103974.23/14256.54	% SZS status Started for HL405508+5.p
103974.23/14256.54	% SZS status GaveUp for HL405508+5.p
103974.23/14256.54	% SZS status Ended for HL405508+5.p
103986.74/14258.11	% SZS status Started for HL405505+4.p
103986.74/14258.11	% SZS status GaveUp for HL405505+4.p
103986.74/14258.11	eprover: CPU time limit exceeded, terminating
103986.74/14258.11	% SZS status Ended for HL405505+4.p
104018.57/14262.19	% SZS status Started for HL405509+5.p
104018.57/14262.19	% SZS status GaveUp for HL405509+5.p
104018.57/14262.19	% SZS status Ended for HL405509+5.p
104031.27/14263.82	% SZS status Started for HL405506+4.p
104031.27/14263.82	% SZS status GaveUp for HL405506+4.p
104031.27/14263.82	eprover: CPU time limit exceeded, terminating
104031.27/14263.82	% SZS status Ended for HL405506+4.p
104035.34/14264.32	% SZS status Started for HL405511+4.p
104035.34/14264.32	% SZS status GaveUp for HL405511+4.p
104035.34/14264.32	eprover: CPU time limit exceeded, terminating
104035.34/14264.32	% SZS status Ended for HL405511+4.p
104049.75/14266.07	% SZS status Started for HL405511+5.p
104049.75/14266.07	% SZS status GaveUp for HL405511+5.p
104049.75/14266.07	% SZS status Ended for HL405511+5.p
104060.41/14267.43	% SZS status Started for HL405507+4.p
104060.41/14267.43	% SZS status GaveUp for HL405507+4.p
104060.41/14267.43	eprover: CPU time limit exceeded, terminating
104060.41/14267.43	% SZS status Ended for HL405507+4.p
104082.69/14270.20	% SZS status Started for HL405508+4.p
104082.69/14270.20	% SZS status GaveUp for HL405508+4.p
104082.69/14270.20	eprover: CPU time limit exceeded, terminating
104082.69/14270.20	% SZS status Ended for HL405508+4.p
104094.72/14271.77	% SZS status Started for HL405512+5.p
104094.72/14271.77	% SZS status GaveUp for HL405512+5.p
104094.72/14271.77	% SZS status Ended for HL405512+5.p
104115.02/14274.28	% SZS status Started for HL405514+5.p
104115.02/14274.28	% SZS status GaveUp for HL405514+5.p
104115.02/14274.28	% SZS status Ended for HL405514+5.p
104115.39/14274.32	% SZS status Started for HL405514+4.p
104115.39/14274.32	% SZS status GaveUp for HL405514+4.p
104115.39/14274.32	eprover: CPU time limit exceeded, terminating
104115.39/14274.32	% SZS status Ended for HL405514+4.p
104131.48/14276.44	% SZS status Started for HL405515+4.p
104131.48/14276.44	% SZS status GaveUp for HL405515+4.p
104131.48/14276.44	eprover: CPU time limit exceeded, terminating
104131.48/14276.44	% SZS status Ended for HL405515+4.p
104136.12/14276.95	% SZS status Started for HL405515+5.p
104136.12/14276.95	% SZS status GaveUp for HL405515+5.p
104136.12/14276.95	% SZS status Ended for HL405515+5.p
104145.59/14278.14	% SZS status Started for HL405509+4.p
104145.59/14278.14	% SZS status GaveUp for HL405509+4.p
104145.59/14278.14	eprover: CPU time limit exceeded, terminating
104145.59/14278.14	% SZS status Ended for HL405509+4.p
104170.52/14281.28	% SZS status Started for HL405516+5.p
104170.52/14281.28	% SZS status GaveUp for HL405516+5.p
104170.52/14281.28	% SZS status Ended for HL405516+5.p
104189.96/14283.89	% SZS status Started for HL405517+5.p
104189.96/14283.89	% SZS status GaveUp for HL405517+5.p
104189.96/14283.89	% SZS status Ended for HL405517+5.p
104194.70/14284.38	% SZS status Started for HL405512+4.p
104194.70/14284.38	% SZS status GaveUp for HL405512+4.p
104194.70/14284.38	eprover: CPU time limit exceeded, terminating
104194.70/14284.38	% SZS status Ended for HL405512+4.p
104212.30/14286.56	% SZS status Started for HL405518+5.p
104212.30/14286.56	% SZS status GaveUp for HL405518+5.p
104212.30/14286.56	% SZS status Ended for HL405518+5.p
104224.46/14288.10	% SZS status Started for HL405519+5.p
104224.46/14288.10	% SZS status Theorem for HL405519+5.p
104224.46/14288.10	% SZS status Ended for HL405519+5.p
104228.16/14288.52	% SZS status Started for HL405519+4.p
104228.16/14288.52	% SZS status GaveUp for HL405519+4.p
104228.16/14288.52	eprover: CPU time limit exceeded, terminating
104228.16/14288.52	% SZS status Ended for HL405519+4.p
104270.81/14293.95	% SZS status Started for HL405520+5.p
104270.81/14293.95	% SZS status GaveUp for HL405520+5.p
104270.81/14293.95	% SZS status Ended for HL405520+5.p
104292.39/14296.29	% SZS status Started for HL405516+4.p
104292.39/14296.29	% SZS status GaveUp for HL405516+4.p
104292.39/14296.29	eprover: CPU time limit exceeded, terminating
104292.39/14296.29	% SZS status Ended for HL405516+4.p
104303.30/14297.62	% SZS status Started for HL405521+5.p
104303.30/14297.62	% SZS status GaveUp for HL405521+5.p
104303.30/14297.62	% SZS status Ended for HL405521+5.p
104327.35/14300.75	% SZS status Started for HL405517+4.p
104327.35/14300.75	% SZS status GaveUp for HL405517+4.p
104327.35/14300.75	eprover: CPU time limit exceeded, terminating
104327.35/14300.75	% SZS status Ended for HL405517+4.p
104342.95/14302.66	% SZS status Started for HL405518+4.p
104342.95/14302.66	% SZS status GaveUp for HL405518+4.p
104342.95/14302.66	eprover: CPU time limit exceeded, terminating
104342.95/14302.66	% SZS status Ended for HL405518+4.p
104351.34/14303.73	% SZS status Started for HL405522+5.p
104351.34/14303.73	% SZS status GaveUp for HL405522+5.p
104351.34/14303.73	% SZS status Ended for HL405522+5.p
104378.95/14307.20	% SZS status Started for HL405523+5.p
104378.95/14307.20	% SZS status GaveUp for HL405523+5.p
104378.95/14307.20	% SZS status Ended for HL405523+5.p
104402.20/14310.11	% SZS status Started for HL405520+4.p
104402.20/14310.11	% SZS status GaveUp for HL405520+4.p
104402.20/14310.11	eprover: CPU time limit exceeded, terminating
104402.20/14310.11	% SZS status Ended for HL405520+4.p
104420.39/14312.42	% SZS status Started for HL405524+5.p
104420.39/14312.42	% SZS status GaveUp for HL405524+5.p
104420.39/14312.42	% SZS status Ended for HL405524+5.p
104422.95/14312.68	% SZS status Started for HL405521+4.p
104422.95/14312.68	% SZS status GaveUp for HL405521+4.p
104422.95/14312.68	eprover: CPU time limit exceeded, terminating
104422.95/14312.68	% SZS status Ended for HL405521+4.p
104437.70/14314.62	% SZS status Started for HL405522+4.p
104437.70/14314.62	% SZS status GaveUp for HL405522+4.p
104437.70/14314.62	eprover: CPU time limit exceeded, terminating
104437.70/14314.62	% SZS status Ended for HL405522+4.p
104456.43/14316.95	% SZS status Started for HL405525+5.p
104456.43/14316.95	% SZS status GaveUp for HL405525+5.p
104456.43/14316.95	% SZS status Ended for HL405525+5.p
104496.34/14322.00	% SZS status Started for HL405526+5.p
104496.34/14322.00	% SZS status GaveUp for HL405526+5.p
104496.34/14322.00	% SZS status Ended for HL405526+5.p
104501.66/14322.67	% SZS status Started for HL405523+4.p
104501.66/14322.67	% SZS status GaveUp for HL405523+4.p
104501.66/14322.67	eprover: CPU time limit exceeded, terminating
104501.66/14322.67	% SZS status Ended for HL405523+4.p
104516.15/14324.48	% SZS status Started for HL405527+5.p
104516.15/14324.48	% SZS status GaveUp for HL405527+5.p
104516.15/14324.48	% SZS status Ended for HL405527+5.p
104535.28/14326.94	% SZS status Started for HL405524+4.p
104535.28/14326.94	% SZS status GaveUp for HL405524+4.p
104535.28/14326.94	eprover: CPU time limit exceeded, terminating
104535.28/14326.94	% SZS status Ended for HL405524+4.p
104559.00/14329.90	% SZS status Started for HL405525+4.p
104559.00/14329.90	% SZS status GaveUp for HL405525+4.p
104559.00/14329.90	eprover: CPU time limit exceeded, terminating
104559.00/14329.90	% SZS status Ended for HL405525+4.p
104575.46/14331.92	% SZS status Started for HL405528+5.p
104575.46/14331.92	% SZS status GaveUp for HL405528+5.p
104575.46/14331.92	% SZS status Ended for HL405528+5.p
104592.24/14334.07	% SZS status Started for HL405529+5.p
104592.24/14334.07	% SZS status GaveUp for HL405529+5.p
104592.24/14334.07	% SZS status Ended for HL405529+5.p
104610.15/14336.32	% SZS status Started for HL405526+4.p
104610.15/14336.32	% SZS status GaveUp for HL405526+4.p
104610.15/14336.32	eprover: CPU time limit exceeded, terminating
104610.15/14336.32	% SZS status Ended for HL405526+4.p
104631.58/14338.98	% SZS status Started for HL405527+4.p
104631.58/14338.98	% SZS status GaveUp for HL405527+4.p
104631.58/14338.98	eprover: CPU time limit exceeded, terminating
104631.58/14338.98	% SZS status Ended for HL405527+4.p
104635.61/14339.48	% SZS status Started for HL405530+5.p
104635.61/14339.48	% SZS status GaveUp for HL405530+5.p
104635.61/14339.48	% SZS status Ended for HL405530+5.p
104664.55/14343.20	% SZS status Started for HL405528+4.p
104664.55/14343.20	% SZS status GaveUp for HL405528+4.p
104664.55/14343.20	eprover: CPU time limit exceeded, terminating
104664.55/14343.20	% SZS status Ended for HL405528+4.p
104668.45/14343.67	% SZS status Started for HL405531+5.p
104668.45/14343.67	% SZS status GaveUp for HL405531+5.p
104668.45/14343.67	% SZS status Ended for HL405531+5.p
104708.17/14348.66	% SZS status Started for HL405532+5.p
104708.17/14348.66	% SZS status GaveUp for HL405532+5.p
104708.17/14348.66	% SZS status Ended for HL405532+5.p
104709.61/14348.82	% SZS status Started for HL405529+4.p
104709.61/14348.82	% SZS status GaveUp for HL405529+4.p
104709.61/14348.82	eprover: CPU time limit exceeded, terminating
104709.61/14348.82	% SZS status Ended for HL405529+4.p
104717.87/14349.88	% SZS status Started for HL405534+4.p
104717.87/14349.88	% SZS status GaveUp for HL405534+4.p
104717.87/14349.88	eprover: CPU time limit exceeded, terminating
104717.87/14349.88	% SZS status Ended for HL405534+4.p
104722.06/14350.42	% SZS status Started for HL405534+5.p
104722.06/14350.42	% SZS status Theorem for HL405534+5.p
104722.06/14350.42	% SZS status Ended for HL405534+5.p
104743.44/14353.16	% SZS status Started for HL405530+4.p
104743.44/14353.16	% SZS status GaveUp for HL405530+4.p
104743.44/14353.16	eprover: CPU time limit exceeded, terminating
104743.44/14353.16	% SZS status Ended for HL405530+4.p
104775.16/14353.87	% SZS status Started for HL405536+4.p
104775.16/14353.87	% SZS status GaveUp for HL405536+4.p
104775.16/14353.87	eprover: CPU time limit exceeded, terminating
104775.16/14353.87	% SZS status Ended for HL405536+4.p
104788.60/14355.61	% SZS status Started for HL405536+5.p
104788.60/14355.61	% SZS status Theorem for HL405536+5.p
104788.60/14355.61	% SZS status Ended for HL405536+5.p
104810.69/14358.35	% SZS status Started for HL405531+4.p
104810.69/14358.35	% SZS status GaveUp for HL405531+4.p
104810.69/14358.35	eprover: CPU time limit exceeded, terminating
104810.69/14358.35	% SZS status Ended for HL405531+4.p
104818.48/14359.44	% SZS status Started for HL405537+5.p
104818.48/14359.44	% SZS status GaveUp for HL405537+5.p
104818.48/14359.44	% SZS status Ended for HL405537+5.p
104828.34/14360.67	% SZS status Started for HL405540+4.p
104828.34/14360.67	% SZS status GaveUp for HL405540+4.p
104828.34/14360.67	eprover: CPU time limit exceeded, terminating
104828.34/14360.67	% SZS status Ended for HL405540+4.p
104842.16/14362.42	% SZS status Started for HL405532+4.p
104842.16/14362.42	% SZS status GaveUp for HL405532+4.p
104842.16/14362.42	eprover: CPU time limit exceeded, terminating
104842.16/14362.42	% SZS status Ended for HL405532+4.p
104844.92/14362.73	% SZS status Started for HL405540+5.p
104844.92/14362.73	% SZS status GaveUp for HL405540+5.p
104844.92/14362.73	% SZS status Ended for HL405540+5.p
104857.62/14364.27	% SZS status Started for HL405541+4.p
104857.62/14364.27	% SZS status GaveUp for HL405541+4.p
104857.62/14364.27	eprover: CPU time limit exceeded, terminating
104857.62/14364.27	% SZS status Ended for HL405541+4.p
104863.81/14365.08	% SZS status Started for HL405541+5.p
104863.81/14365.08	% SZS status GaveUp for HL405541+5.p
104863.81/14365.08	% SZS status Ended for HL405541+5.p
104894.07/14368.97	% SZS status Started for HL405542+5.p
104894.07/14368.97	% SZS status GaveUp for HL405542+5.p
104894.07/14368.97	% SZS status Ended for HL405542+5.p
104917.80/14371.90	% SZS status Started for HL405543+5.p
104917.80/14371.90	% SZS status GaveUp for HL405543+5.p
104917.80/14371.90	% SZS status Ended for HL405543+5.p
104929.09/14373.29	% SZS status Started for HL405544+4.p
104929.09/14373.29	% SZS status GaveUp for HL405544+4.p
104929.09/14373.29	eprover: CPU time limit exceeded, terminating
104929.09/14373.29	% SZS status Ended for HL405544+4.p
104933.11/14373.78	% SZS status Started for HL405544+5.p
104933.11/14373.78	% SZS status GaveUp for HL405544+5.p
104933.11/14373.78	% SZS status Ended for HL405544+5.p
104942.61/14375.03	% SZS status Started for HL405537+4.p
104942.61/14375.03	% SZS status GaveUp for HL405537+4.p
104942.61/14375.03	eprover: CPU time limit exceeded, terminating
104942.61/14375.03	% SZS status Ended for HL405537+4.p
104945.13/14375.35	% SZS status Started for HL405546+4.p
104945.13/14375.35	% SZS status GaveUp for HL405546+4.p
104945.13/14375.35	eprover: CPU time limit exceeded, terminating
104945.13/14375.35	% SZS status Ended for HL405546+4.p
104971.47/14378.67	% SZS status Started for HL405546+5.p
104971.47/14378.67	% SZS status GaveUp for HL405546+5.p
104971.47/14378.67	% SZS status Ended for HL405546+5.p
105005.39/14382.89	% SZS status Started for HL405547+5.p
105005.39/14382.89	% SZS status GaveUp for HL405547+5.p
105005.39/14382.89	% SZS status Ended for HL405547+5.p
105018.24/14384.55	% SZS status Started for HL405548+5.p
105018.24/14384.55	% SZS status GaveUp for HL405548+5.p
105018.24/14384.55	% SZS status Ended for HL405548+5.p
105019.38/14384.73	% SZS status Started for HL405542+4.p
105019.38/14384.73	% SZS status GaveUp for HL405542+4.p
105019.38/14384.73	eprover: CPU time limit exceeded, terminating
105019.38/14384.73	% SZS status Ended for HL405542+4.p
105036.84/14386.93	% SZS status Started for HL405543+4.p
105036.84/14386.93	% SZS status GaveUp for HL405543+4.p
105036.84/14386.93	eprover: CPU time limit exceeded, terminating
105036.84/14386.93	% SZS status Ended for HL405543+4.p
105048.63/14388.34	% SZS status Started for HL405550+5.p
105048.63/14388.34	% SZS status GaveUp for HL405550+5.p
105048.63/14388.34	% SZS status Ended for HL405550+5.p
105094.35/14394.20	% SZS status Started for HL405551+5.p
105094.35/14394.20	% SZS status GaveUp for HL405551+5.p
105094.35/14394.20	% SZS status Ended for HL405551+5.p
105114.43/14396.72	% SZS status Started for HL405552+5.p
105114.43/14396.72	% SZS status GaveUp for HL405552+5.p
105114.43/14396.72	% SZS status Ended for HL405552+5.p
105126.34/14398.12	% SZS status Started for HL405547+4.p
105126.34/14398.12	% SZS status GaveUp for HL405547+4.p
105126.34/14398.12	eprover: CPU time limit exceeded, terminating
105126.34/14398.12	% SZS status Ended for HL405547+4.p
105142.59/14400.24	% SZS status Started for HL405548+4.p
105142.59/14400.24	% SZS status GaveUp for HL405548+4.p
105142.59/14400.24	eprover: CPU time limit exceeded, terminating
105142.59/14400.24	% SZS status Ended for HL405548+4.p
105153.32/14401.55	% SZS status Started for HL405550+4.p
105153.32/14401.55	% SZS status GaveUp for HL405550+4.p
105153.32/14401.55	eprover: CPU time limit exceeded, terminating
105153.32/14401.55	% SZS status Ended for HL405550+4.p
105170.91/14403.79	% SZS status Started for HL405553+5.p
105170.91/14403.79	% SZS status GaveUp for HL405553+5.p
105170.91/14403.79	% SZS status Ended for HL405553+5.p
105201.83/14407.68	% SZS status Started for HL405554+5.p
105201.83/14407.68	% SZS status GaveUp for HL405554+5.p
105201.83/14407.68	% SZS status Ended for HL405554+5.p
105213.29/14409.16	% SZS status Started for HL405551+4.p
105213.29/14409.16	% SZS status GaveUp for HL405551+4.p
105213.29/14409.16	eprover: CPU time limit exceeded, terminating
105213.29/14409.16	% SZS status Ended for HL405551+4.p
105228.86/14411.16	% SZS status Started for HL405555+5.p
105228.86/14411.16	% SZS status GaveUp for HL405555+5.p
105228.86/14411.16	% SZS status Ended for HL405555+5.p
105229.14/14411.20	% SZS status Started for HL405552+4.p
105229.14/14411.20	% SZS status GaveUp for HL405552+4.p
105229.14/14411.20	eprover: CPU time limit exceeded, terminating
105229.14/14411.20	% SZS status Ended for HL405552+4.p
105255.56/14414.53	% SZS status Started for HL405553+4.p
105255.56/14414.53	% SZS status GaveUp for HL405553+4.p
105255.56/14414.53	eprover: CPU time limit exceeded, terminating
105255.56/14414.53	% SZS status Ended for HL405553+4.p
105279.33/14417.44	% SZS status Started for HL405556+5.p
105279.33/14417.44	% SZS status GaveUp for HL405556+5.p
105279.33/14417.44	% SZS status Ended for HL405556+5.p
105294.67/14419.41	% SZS status Started for HL405557+4.p
105294.67/14419.41	% SZS status GaveUp for HL405557+4.p
105294.67/14419.41	eprover: CPU time limit exceeded, terminating
105294.67/14419.41	% SZS status Ended for HL405557+4.p
105303.95/14420.62	% SZS status Started for HL405557+5.p
105303.95/14420.62	% SZS status GaveUp for HL405557+5.p
105303.95/14420.62	% SZS status Ended for HL405557+5.p
105314.82/14421.98	% SZS status Started for HL405558+4.p
105314.82/14421.98	% SZS status GaveUp for HL405558+4.p
105314.82/14421.98	eprover: CPU time limit exceeded, terminating
105314.82/14421.98	% SZS status Ended for HL405558+4.p
105323.24/14422.99	% SZS status Started for HL405554+4.p
105323.24/14422.99	% SZS status GaveUp for HL405554+4.p
105323.24/14422.99	eprover: CPU time limit exceeded, terminating
105323.24/14422.99	% SZS status Ended for HL405554+4.p
105331.98/14424.13	% SZS status Started for HL405558+5.p
105331.98/14424.13	% SZS status GaveUp for HL405558+5.p
105331.98/14424.13	% SZS status Ended for HL405558+5.p
105351.33/14426.60	% SZS status Started for HL405555+4.p
105351.33/14426.60	% SZS status GaveUp for HL405555+4.p
105351.33/14426.60	eprover: CPU time limit exceeded, terminating
105351.33/14426.60	% SZS status Ended for HL405555+4.p
105367.88/14428.65	% SZS status Started for HL405559+5.p
105367.88/14428.65	% SZS status GaveUp for HL405559+5.p
105367.88/14428.65	% SZS status Ended for HL405559+5.p
105377.98/14429.93	% SZS status Started for HL405556+4.p
105377.98/14429.93	% SZS status GaveUp for HL405556+4.p
105377.98/14429.93	eprover: CPU time limit exceeded, terminating
105377.98/14429.93	% SZS status Ended for HL405556+4.p
105390.62/14431.47	% SZS status Started for HL405560+5.p
105390.62/14431.47	% SZS status GaveUp for HL405560+5.p
105390.62/14431.47	% SZS status Ended for HL405560+5.p
105406.08/14433.41	% SZS status Started for HL405561+5.p
105406.08/14433.41	% SZS status GaveUp for HL405561+5.p
105406.08/14433.41	% SZS status Ended for HL405561+5.p
105434.19/14437.03	% SZS status Started for HL405562+4.p
105434.19/14437.03	% SZS status GaveUp for HL405562+4.p
105434.19/14437.03	eprover: CPU time limit exceeded, terminating
105434.19/14437.03	% SZS status Ended for HL405562+4.p
105447.82/14438.72	% SZS status Started for HL405562+5.p
105447.82/14438.72	% SZS status GaveUp for HL405562+5.p
105447.82/14438.72	% SZS status Ended for HL405562+5.p
105460.00/14440.24	% SZS status Started for HL405563+4.p
105460.00/14440.24	% SZS status GaveUp for HL405563+4.p
105460.00/14440.24	eprover: CPU time limit exceeded, terminating
105460.00/14440.24	% SZS status Ended for HL405563+4.p
105467.93/14441.38	% SZS status Started for HL405563+5.p
105467.93/14441.38	% SZS status GaveUp for HL405563+5.p
105467.93/14441.38	% SZS status Ended for HL405563+5.p
105486.73/14443.65	% SZS status Started for HL405559+4.p
105486.73/14443.65	% SZS status GaveUp for HL405559+4.p
105486.73/14443.65	eprover: CPU time limit exceeded, terminating
105486.73/14443.65	% SZS status Ended for HL405559+4.p
105490.75/14444.15	% SZS status Started for HL405564+4.p
105490.75/14444.15	% SZS status GaveUp for HL405564+4.p
105490.75/14444.15	eprover: CPU time limit exceeded, terminating
105490.75/14444.15	% SZS status Ended for HL405564+4.p
105511.20/14446.66	% SZS status Started for HL405564+5.p
105511.20/14446.66	% SZS status GaveUp for HL405564+5.p
105511.20/14446.66	% SZS status Ended for HL405564+5.p
105512.95/14446.95	% SZS status Started for HL405560+4.p
105512.95/14446.95	% SZS status GaveUp for HL405560+4.p
105512.95/14446.95	eprover: CPU time limit exceeded, terminating
105512.95/14446.95	% SZS status Ended for HL405560+4.p
105530.60/14449.16	% SZS status Started for HL405561+4.p
105530.60/14449.16	% SZS status GaveUp for HL405561+4.p
105530.60/14449.16	eprover: CPU time limit exceeded, terminating
105530.60/14449.16	% SZS status Ended for HL405561+4.p
105535.77/14449.84	% SZS status Started for HL405565+5.p
105535.77/14449.84	% SZS status GaveUp for HL405565+5.p
105535.77/14449.84	% SZS status Ended for HL405565+5.p
105548.66/14451.48	% SZS status Started for HL405566+4.p
105548.66/14451.48	% SZS status GaveUp for HL405566+4.p
105548.66/14451.48	eprover: CPU time limit exceeded, terminating
105548.66/14451.48	% SZS status Ended for HL405566+4.p
105564.23/14453.36	% SZS status Started for HL405566+5.p
105564.23/14453.36	% SZS status GaveUp for HL405566+5.p
105564.23/14453.36	% SZS status Ended for HL405566+5.p
105587.70/14456.35	% SZS status Started for HL405567+5.p
105587.70/14456.35	% SZS status GaveUp for HL405567+5.p
105587.70/14456.35	% SZS status Ended for HL405567+5.p
105609.16/14459.05	% SZS status Started for HL405570+5.p
105609.16/14459.05	% SZS status GaveUp for HL405570+5.p
105609.16/14459.05	% SZS status Ended for HL405570+5.p
105618.85/14460.30	% SZS status Started for HL405571+4.p
105618.85/14460.30	% SZS status GaveUp for HL405571+4.p
105618.85/14460.30	eprover: CPU time limit exceeded, terminating
105618.85/14460.30	% SZS status Ended for HL405571+4.p
105627.02/14461.31	% SZS status Started for HL405571+5.p
105627.02/14461.31	% SZS status GaveUp for HL405571+5.p
105627.02/14461.31	% SZS status Ended for HL405571+5.p
105645.40/14463.62	% SZS status Started for HL405572+4.p
105645.40/14463.62	% SZS status GaveUp for HL405572+4.p
105645.40/14463.62	eprover: CPU time limit exceeded, terminating
105645.40/14463.62	% SZS status Ended for HL405572+4.p
105655.35/14464.87	% SZS status Started for HL405565+4.p
105655.35/14464.87	% SZS status GaveUp for HL405565+4.p
105655.35/14464.87	eprover: CPU time limit exceeded, terminating
105655.35/14464.87	% SZS status Ended for HL405565+4.p
105664.34/14466.04	% SZS status Started for HL405572+5.p
105664.34/14466.04	% SZS status GaveUp for HL405572+5.p
105664.34/14466.04	% SZS status Ended for HL405572+5.p
105691.98/14469.58	% SZS status Started for HL405573+4.p
105691.98/14469.58	% SZS status GaveUp for HL405573+4.p
105691.98/14469.58	eprover: CPU time limit exceeded, terminating
105691.98/14469.58	% SZS status Ended for HL405573+4.p
105694.70/14469.79	% SZS status Started for HL405573+5.p
105694.70/14469.79	% SZS status GaveUp for HL405573+5.p
105694.70/14469.79	% SZS status Ended for HL405573+5.p
105697.14/14470.23	% SZS status Started for HL405567+4.p
105697.14/14470.23	% SZS status GaveUp for HL405567+4.p
105697.14/14470.23	eprover: CPU time limit exceeded, terminating
105697.14/14470.23	% SZS status Ended for HL405567+4.p
105700.18/14470.53	% SZS status Started for HL405574+5.p
105700.18/14470.53	% SZS status Theorem for HL405574+5.p
105700.18/14470.53	% SZS status Ended for HL405574+5.p
105722.20/14473.24	% SZS status Started for HL405570+4.p
105722.20/14473.24	% SZS status GaveUp for HL405570+4.p
105722.20/14473.24	eprover: CPU time limit exceeded, terminating
105722.20/14473.24	% SZS status Ended for HL405570+4.p
105738.95/14475.35	% SZS status Started for HL405576+5.p
105738.95/14475.35	% SZS status GaveUp for HL405576+5.p
105738.95/14475.35	% SZS status Ended for HL405576+5.p
105754.03/14477.29	% SZS status Started for HL405579+5.p
105754.03/14477.29	% SZS status Theorem for HL405579+5.p
105754.03/14477.29	% SZS status Ended for HL405579+5.p
105770.17/14479.29	% SZS status Started for HL405577+5.p
105770.17/14479.29	% SZS status GaveUp for HL405577+5.p
105770.17/14479.29	% SZS status Ended for HL405577+5.p
105814.23/14484.86	% SZS status Started for HL405580+5.p
105814.23/14484.86	% SZS status GaveUp for HL405580+5.p
105814.23/14484.86	% SZS status Ended for HL405580+5.p
105827.20/14486.47	% SZS status Started for HL405582+5.p
105827.20/14486.47	% SZS status Theorem for HL405582+5.p
105827.20/14486.47	% SZS status Ended for HL405582+5.p
105835.01/14487.51	% SZS status Started for HL405582+4.p
105835.01/14487.51	% SZS status GaveUp for HL405582+4.p
105835.01/14487.51	eprover: CPU time limit exceeded, terminating
105835.01/14487.51	% SZS status Ended for HL405582+4.p
105835.58/14487.61	% SZS status Started for HL405574+4.p
105835.58/14487.61	% SZS status GaveUp for HL405574+4.p
105835.58/14487.61	eprover: CPU time limit exceeded, terminating
105835.58/14487.61	% SZS status Ended for HL405574+4.p
105864.62/14491.23	% SZS status Started for HL405576+4.p
105864.62/14491.23	% SZS status GaveUp for HL405576+4.p
105864.62/14491.23	eprover: CPU time limit exceeded, terminating
105864.62/14491.23	% SZS status Ended for HL405576+4.p
105902.05/14495.89	% SZS status Started for HL405577+4.p
105902.05/14495.89	% SZS status GaveUp for HL405577+4.p
105902.05/14495.89	eprover: CPU time limit exceeded, terminating
105902.05/14495.89	% SZS status Ended for HL405577+4.p
105903.34/14496.04	% SZS status Started for HL405583+5.p
105903.34/14496.04	% SZS status GaveUp for HL405583+5.p
105903.34/14496.04	% SZS status Ended for HL405583+5.p
105906.17/14496.39	% SZS status Started for HL405579+4.p
105906.17/14496.39	% SZS status GaveUp for HL405579+4.p
105906.17/14496.39	eprover: CPU time limit exceeded, terminating
105906.17/14496.39	% SZS status Ended for HL405579+4.p
105912.73/14497.27	% SZS status Started for HL405584+5.p
105912.73/14497.27	% SZS status GaveUp for HL405584+5.p
105912.73/14497.27	% SZS status Ended for HL405584+5.p
105922.95/14498.57	% SZS status Started for HL405584+4.p
105922.95/14498.57	% SZS status GaveUp for HL405584+4.p
105922.95/14498.57	eprover: CPU time limit exceeded, terminating
105922.95/14498.57	% SZS status Ended for HL405584+4.p
105929.77/14499.43	% SZS status Started for HL405580+4.p
105929.77/14499.43	% SZS status GaveUp for HL405580+4.p
105929.77/14499.43	eprover: CPU time limit exceeded, terminating
105929.77/14499.43	% SZS status Ended for HL405580+4.p
105952.82/14502.30	% SZS status Started for HL405588+5.p
105952.82/14502.30	% SZS status Theorem for HL405588+5.p
105952.82/14502.30	% SZS status Ended for HL405588+5.p
105977.51/14505.36	% SZS status Started for HL405585+5.p
105977.51/14505.36	% SZS status GaveUp for HL405585+5.p
105977.51/14505.36	% SZS status Ended for HL405585+5.p
105980.43/14505.74	% SZS status Started for HL405586+5.p
105980.43/14505.74	% SZS status GaveUp for HL405586+5.p
105980.43/14505.74	% SZS status Ended for HL405586+5.p
105990.52/14507.03	% SZS status Started for HL405583+4.p
105990.52/14507.03	% SZS status GaveUp for HL405583+4.p
105990.52/14507.03	eprover: CPU time limit exceeded, terminating
105990.52/14507.03	% SZS status Ended for HL405583+4.p
106030.20/14511.98	% SZS status Started for HL405590+5.p
106030.20/14511.98	% SZS status GaveUp for HL405590+5.p
106030.20/14511.98	% SZS status Ended for HL405590+5.p
106055.71/14515.22	% SZS status Started for HL405592+5.p
106055.71/14515.22	% SZS status GaveUp for HL405592+5.p
106055.71/14515.22	% SZS status Ended for HL405592+5.p
106057.83/14515.59	% SZS status Started for HL405592+4.p
106057.83/14515.59	% SZS status GaveUp for HL405592+4.p
106057.83/14515.59	eprover: CPU time limit exceeded, terminating
106057.83/14515.59	% SZS status Ended for HL405592+4.p
106072.34/14517.28	% SZS status Started for HL405593+4.p
106072.34/14517.28	% SZS status GaveUp for HL405593+4.p
106072.34/14517.28	eprover: CPU time limit exceeded, terminating
106072.34/14517.28	% SZS status Ended for HL405593+4.p
106073.09/14517.42	% SZS status Started for HL405585+4.p
106073.09/14517.42	% SZS status GaveUp for HL405585+4.p
106073.09/14517.42	eprover: CPU time limit exceeded, terminating
106073.09/14517.42	% SZS status Ended for HL405585+4.p
106106.15/14521.57	% SZS status Started for HL405593+5.p
106106.15/14521.57	% SZS status GaveUp for HL405593+5.p
106106.15/14521.57	% SZS status Ended for HL405593+5.p
106110.85/14522.15	% SZS status Started for HL405586+4.p
106110.85/14522.15	% SZS status GaveUp for HL405586+4.p
106110.85/14522.15	eprover: CPU time limit exceeded, terminating
106110.85/14522.15	% SZS status Ended for HL405586+4.p
106122.78/14523.62	% SZS status Started for HL405588+4.p
106122.78/14523.62	% SZS status GaveUp for HL405588+4.p
106122.78/14523.62	eprover: CPU time limit exceeded, terminating
106122.78/14523.62	% SZS status Ended for HL405588+4.p
106133.18/14525.08	% SZS status Started for HL405594+5.p
106133.18/14525.08	% SZS status GaveUp for HL405594+5.p
106133.18/14525.08	% SZS status Ended for HL405594+5.p
106138.79/14525.67	% SZS status Started for HL405590+4.p
106138.79/14525.67	% SZS status GaveUp for HL405590+4.p
106138.79/14525.67	eprover: CPU time limit exceeded, terminating
106138.79/14525.67	% SZS status Ended for HL405590+4.p
106146.74/14526.69	% SZS status Started for HL405595+5.p
106146.74/14526.69	% SZS status GaveUp for HL405595+5.p
106146.74/14526.69	% SZS status Ended for HL405595+5.p
106156.05/14527.87	% SZS status Started for HL405595+4.p
106156.05/14527.87	% SZS status GaveUp for HL405595+4.p
106156.05/14527.87	eprover: CPU time limit exceeded, terminating
106156.05/14527.87	% SZS status Ended for HL405595+4.p
106187.57/14531.86	% SZS status Started for HL405596+5.p
106187.57/14531.86	% SZS status GaveUp for HL405596+5.p
106187.57/14531.86	% SZS status Ended for HL405596+5.p
106208.05/14534.46	% SZS status Started for HL405598+5.p
106208.05/14534.46	% SZS status GaveUp for HL405598+5.p
106208.05/14534.46	% SZS status Ended for HL405598+5.p
106218.04/14535.68	% SZS status Started for HL405600+5.p
106218.04/14535.68	% SZS status Theorem for HL405600+5.p
106218.04/14535.68	% SZS status Ended for HL405600+5.p
106224.60/14536.48	% SZS status Started for HL405599+5.p
106224.60/14536.48	% SZS status GaveUp for HL405599+5.p
106224.60/14536.48	% SZS status Ended for HL405599+5.p
106263.56/14541.38	% SZS status Started for HL405594+4.p
106263.56/14541.38	% SZS status GaveUp for HL405594+4.p
106263.56/14541.38	eprover: CPU time limit exceeded, terminating
106263.56/14541.38	% SZS status Ended for HL405594+4.p
106294.20/14545.26	% SZS status Started for HL405601+5.p
106294.20/14545.26	% SZS status GaveUp for HL405601+5.p
106294.20/14545.26	% SZS status Ended for HL405601+5.p
106306.45/14546.79	% SZS status Started for HL405602+4.p
106306.45/14546.79	% SZS status GaveUp for HL405602+4.p
106306.45/14546.79	eprover: CPU time limit exceeded, terminating
106306.45/14546.79	% SZS status Ended for HL405602+4.p
106314.20/14547.82	% SZS status Started for HL405596+4.p
106314.20/14547.82	% SZS status GaveUp for HL405596+4.p
106314.20/14547.82	eprover: CPU time limit exceeded, terminating
106314.20/14547.82	% SZS status Ended for HL405596+4.p
106315.94/14547.98	% SZS status Started for HL405602+5.p
106315.94/14547.98	% SZS status Theorem for HL405602+5.p
106315.94/14547.98	% SZS status Ended for HL405602+5.p
106321.99/14548.81	% SZS status Started for HL405603+5.p
106321.99/14548.81	% SZS status Theorem for HL405603+5.p
106321.99/14548.81	% SZS status Ended for HL405603+5.p
106330.41/14549.83	% SZS status Started for HL405598+4.p
106330.41/14549.83	% SZS status GaveUp for HL405598+4.p
106330.41/14549.83	eprover: CPU time limit exceeded, terminating
106330.41/14549.83	% SZS status Ended for HL405598+4.p
106347.78/14552.01	% SZS status Started for HL405599+4.p
106347.78/14552.01	% SZS status GaveUp for HL405599+4.p
106347.78/14552.01	eprover: CPU time limit exceeded, terminating
106347.78/14552.01	% SZS status Ended for HL405599+4.p
106364.38/14554.09	% SZS status Started for HL405600+4.p
106364.38/14554.09	% SZS status GaveUp for HL405600+4.p
106364.38/14554.09	eprover: CPU time limit exceeded, terminating
106364.38/14554.09	% SZS status Ended for HL405600+4.p
106374.74/14555.50	% SZS status Started for HL405603+4.p
106374.74/14555.50	% SZS status GaveUp for HL405603+4.p
106374.74/14555.50	eprover: CPU time limit exceeded, terminating
106374.74/14555.50	% SZS status Ended for HL405603+4.p
106389.41/14557.28	% SZS status Started for HL405604+5.p
106389.41/14557.28	% SZS status GaveUp for HL405604+5.p
106389.41/14557.28	% SZS status Ended for HL405604+5.p
106404.08/14559.12	% SZS status Started for HL405605+5.p
106404.08/14559.12	% SZS status GaveUp for HL405605+5.p
106404.08/14559.12	% SZS status Ended for HL405605+5.p
106405.17/14559.27	% SZS status Started for HL405605+4.p
106405.17/14559.27	% SZS status GaveUp for HL405605+4.p
106405.17/14559.27	eprover: CPU time limit exceeded, terminating
106405.17/14559.27	% SZS status Ended for HL405605+4.p
106417.38/14560.76	% SZS status Started for HL405601+4.p
106417.38/14560.76	% SZS status GaveUp for HL405601+4.p
106417.38/14560.76	eprover: CPU time limit exceeded, terminating
106417.38/14560.76	% SZS status Ended for HL405601+4.p
106439.78/14563.59	% SZS status Started for HL405606+5.p
106439.78/14563.59	% SZS status GaveUp for HL405606+5.p
106439.78/14563.59	% SZS status Ended for HL405606+5.p
106459.23/14566.05	% SZS status Started for HL405604+4.p
106459.23/14566.05	% SZS status GaveUp for HL405604+4.p
106459.23/14566.05	eprover: CPU time limit exceeded, terminating
106459.23/14566.05	% SZS status Ended for HL405604+4.p
106466.60/14567.00	% SZS status Started for HL405607+5.p
106466.60/14567.00	% SZS status GaveUp for HL405607+5.p
106466.60/14567.00	% SZS status Ended for HL405607+5.p
106479.36/14568.57	% SZS status Started for HL405608+5.p
106479.36/14568.57	% SZS status GaveUp for HL405608+5.p
106479.36/14568.57	% SZS status Ended for HL405608+5.p
106492.20/14570.21	% SZS status Started for HL405608+4.p
106492.20/14570.21	% SZS status GaveUp for HL405608+4.p
106492.20/14570.21	eprover: CPU time limit exceeded, terminating
106492.20/14570.21	% SZS status Ended for HL405608+4.p
106518.26/14573.51	% SZS status Started for HL405609+5.p
106518.26/14573.51	% SZS status GaveUp for HL405609+5.p
106518.26/14573.51	% SZS status Ended for HL405609+5.p
106542.62/14576.54	% SZS status Started for HL405610+5.p
106542.62/14576.54	% SZS status GaveUp for HL405610+5.p
106542.62/14576.54	% SZS status Ended for HL405610+5.p
106555.36/14578.18	% SZS status Started for HL405606+4.p
106555.36/14578.18	% SZS status GaveUp for HL405606+4.p
106555.36/14578.18	eprover: CPU time limit exceeded, terminating
106555.36/14578.18	% SZS status Ended for HL405606+4.p
106566.59/14579.56	% SZS status Started for HL405613+5.p
106566.59/14579.56	% SZS status GaveUp for HL405613+5.p
106566.59/14579.56	% SZS status Ended for HL405613+5.p
106583.07/14581.66	% SZS status Started for HL405607+4.p
106583.07/14581.66	% SZS status GaveUp for HL405607+4.p
106583.07/14581.66	eprover: CPU time limit exceeded, terminating
106583.07/14581.66	% SZS status Ended for HL405607+4.p
106617.29/14585.94	% SZS status Started for HL405614+5.p
106617.29/14585.94	% SZS status GaveUp for HL405614+5.p
106617.29/14585.94	% SZS status Ended for HL405614+5.p
106624.39/14586.86	% SZS status Started for HL405613+4.p
106624.39/14586.86	% SZS status GaveUp for HL405613+4.p
106624.39/14586.86	eprover: CPU time limit exceeded, terminating
106624.39/14586.86	% SZS status Ended for HL405613+4.p
106628.57/14587.41	% SZS status Started for HL405609+4.p
106628.57/14587.41	% SZS status GaveUp for HL405609+4.p
106628.57/14587.41	eprover: CPU time limit exceeded, terminating
106628.57/14587.41	% SZS status Ended for HL405609+4.p
106640.88/14588.94	% SZS status Started for HL405615+5.p
106640.88/14588.94	% SZS status GaveUp for HL405615+5.p
106640.88/14588.94	% SZS status Ended for HL405615+5.p
106644.78/14589.44	% SZS status Started for HL405618+5.p
106644.78/14589.44	% SZS status Theorem for HL405618+5.p
106644.78/14589.44	% SZS status Ended for HL405618+5.p
106658.98/14591.23	% SZS status Started for HL405619+5.p
106658.98/14591.23	% SZS status Theorem for HL405619+5.p
106658.98/14591.23	% SZS status Ended for HL405619+5.p
106667.02/14592.23	% SZS status Started for HL405610+4.p
106667.02/14592.23	% SZS status GaveUp for HL405610+4.p
106667.02/14592.23	eprover: CPU time limit exceeded, terminating
106667.02/14592.23	% SZS status Ended for HL405610+4.p
106690.46/14595.21	% SZS status Started for HL405617+5.p
106690.46/14595.21	% SZS status GaveUp for HL405617+5.p
106690.46/14595.21	% SZS status Ended for HL405617+5.p
106715.52/14598.33	% SZS status Started for HL405615+4.p
106715.52/14598.33	% SZS status GaveUp for HL405615+4.p
106715.52/14598.33	eprover: CPU time limit exceeded, terminating
106715.52/14598.33	% SZS status Ended for HL405615+4.p
106721.40/14599.10	% SZS status Started for HL405619+4.p
106721.40/14599.10	% SZS status GaveUp for HL405619+4.p
106721.40/14599.10	eprover: CPU time limit exceeded, terminating
106721.40/14599.10	% SZS status Ended for HL405619+4.p
106728.91/14600.01	% SZS status Started for HL405614+4.p
106728.91/14600.01	% SZS status GaveUp for HL405614+4.p
106728.91/14600.01	eprover: CPU time limit exceeded, terminating
106728.91/14600.01	% SZS status Ended for HL405614+4.p
106740.03/14601.47	% SZS status Started for HL405620+5.p
106740.03/14601.47	% SZS status GaveUp for HL405620+5.p
106740.03/14601.47	% SZS status Ended for HL405620+5.p
106789.45/14607.65	% SZS status Started for HL405621+5.p
106789.45/14607.65	% SZS status GaveUp for HL405621+5.p
106789.45/14607.65	% SZS status Ended for HL405621+5.p
106792.33/14608.03	% SZS status Started for HL405617+4.p
106792.33/14608.03	% SZS status GaveUp for HL405617+4.p
106792.33/14608.03	eprover: CPU time limit exceeded, terminating
106792.33/14608.03	% SZS status Ended for HL405617+4.p
106804.59/14609.53	% SZS status Started for HL405622+5.p
106804.59/14609.53	% SZS status GaveUp for HL405622+5.p
106804.59/14609.53	% SZS status Ended for HL405622+5.p
106820.57/14611.52	% SZS status Started for HL405624+5.p
106820.57/14611.52	% SZS status Theorem for HL405624+5.p
106820.57/14611.52	% SZS status Ended for HL405624+5.p
106832.70/14613.02	% SZS status Started for HL405618+4.p
106832.70/14613.02	% SZS status GaveUp for HL405618+4.p
106832.70/14613.02	eprover: CPU time limit exceeded, terminating
106832.70/14613.02	% SZS status Ended for HL405618+4.p
106864.29/14617.04	% SZS status Started for HL405623+5.p
106864.29/14617.04	% SZS status GaveUp for HL405623+5.p
106864.29/14617.04	% SZS status Ended for HL405623+5.p
106867.65/14617.44	% SZS status Started for HL405620+4.p
106867.65/14617.44	% SZS status GaveUp for HL405620+4.p
106867.65/14617.44	eprover: CPU time limit exceeded, terminating
106867.65/14617.44	% SZS status Ended for HL405620+4.p
106900.55/14621.60	% SZS status Started for HL405621+4.p
106900.55/14621.60	% SZS status GaveUp for HL405621+4.p
106900.55/14621.60	eprover: CPU time limit exceeded, terminating
106900.55/14621.60	% SZS status Ended for HL405621+4.p
106901.86/14621.83	% SZS status Started for HL405625+4.p
106901.86/14621.83	% SZS status GaveUp for HL405625+4.p
106901.86/14621.83	eprover: CPU time limit exceeded, terminating
106901.86/14621.83	% SZS status Ended for HL405625+4.p
106908.32/14622.58	% SZS status Started for HL405625+5.p
106908.32/14622.58	% SZS status GaveUp for HL405625+5.p
106908.32/14622.58	% SZS status Ended for HL405625+5.p
106929.66/14625.34	% SZS status Started for HL405622+4.p
106929.66/14625.34	% SZS status GaveUp for HL405622+4.p
106929.66/14625.34	eprover: CPU time limit exceeded, terminating
106929.66/14625.34	% SZS status Ended for HL405622+4.p
106942.34/14626.86	% SZS status Started for HL405626+5.p
106942.34/14626.86	% SZS status GaveUp for HL405626+5.p
106942.34/14626.86	% SZS status Ended for HL405626+5.p
106949.21/14627.71	% SZS status Started for HL405623+4.p
106949.21/14627.71	% SZS status GaveUp for HL405623+4.p
106949.21/14627.71	eprover: CPU time limit exceeded, terminating
106949.21/14627.71	% SZS status Ended for HL405623+4.p
106955.82/14628.54	% SZS status Started for HL405627+5.p
106955.82/14628.54	% SZS status Theorem for HL405627+5.p
106955.82/14628.54	% SZS status Ended for HL405627+5.p
106982.77/14631.95	% SZS status Started for HL405627+4.p
106982.77/14631.95	% SZS status GaveUp for HL405627+4.p
106982.77/14631.95	eprover: CPU time limit exceeded, terminating
106982.77/14631.95	% SZS status Ended for HL405627+4.p
106984.44/14632.20	% SZS status Started for HL405630+5.p
106984.44/14632.20	% SZS status Theorem for HL405630+5.p
106984.44/14632.20	% SZS status Ended for HL405630+5.p
106990.00/14632.89	% SZS status Started for HL405630+4.p
106990.00/14632.89	% SZS status GaveUp for HL405630+4.p
106990.00/14632.89	eprover: CPU time limit exceeded, terminating
106990.00/14632.89	% SZS status Ended for HL405630+4.p
107000.53/14634.21	% SZS status Started for HL405624+4.p
107000.53/14634.21	% SZS status GaveUp for HL405624+4.p
107000.53/14634.21	eprover: CPU time limit exceeded, terminating
107000.53/14634.21	% SZS status Ended for HL405624+4.p
107025.92/14637.44	% SZS status Started for HL405631+5.p
107025.92/14637.44	% SZS status GaveUp for HL405631+5.p
107025.92/14637.44	% SZS status Ended for HL405631+5.p
107036.35/14638.85	% SZS status Started for HL405632+5.p
107036.35/14638.85	% SZS status Theorem for HL405632+5.p
107036.35/14638.85	% SZS status Ended for HL405632+5.p
107040.77/14639.27	% SZS status Started for HL405632+4.p
107040.77/14639.27	% SZS status GaveUp for HL405632+4.p
107040.77/14639.27	eprover: CPU time limit exceeded, terminating
107040.77/14639.27	% SZS status Ended for HL405632+4.p
107066.01/14642.49	% SZS status Started for HL405633+5.p
107066.01/14642.49	% SZS status GaveUp for HL405633+5.p
107066.01/14642.49	% SZS status Ended for HL405633+5.p
107066.48/14642.51	% SZS status Started for HL405633+4.p
107066.48/14642.51	% SZS status GaveUp for HL405633+4.p
107066.48/14642.51	eprover: CPU time limit exceeded, terminating
107066.48/14642.51	% SZS status Ended for HL405633+4.p
107073.40/14643.39	% SZS status Started for HL405626+4.p
107073.40/14643.39	% SZS status GaveUp for HL405626+4.p
107073.40/14643.39	eprover: CPU time limit exceeded, terminating
107073.40/14643.39	% SZS status Ended for HL405626+4.p
107103.62/14647.32	% SZS status Started for HL405634+5.p
107103.62/14647.32	% SZS status GaveUp for HL405634+5.p
107103.62/14647.32	% SZS status Ended for HL405634+5.p
107116.52/14648.96	% SZS status Started for HL405635+5.p
107116.52/14648.96	% SZS status GaveUp for HL405635+5.p
107116.52/14648.96	% SZS status Ended for HL405635+5.p
107147.05/14652.69	% SZS status Started for HL405637+4.p
107147.05/14652.69	% SZS status GaveUp for HL405637+4.p
107147.05/14652.69	eprover: CPU time limit exceeded, terminating
107147.05/14652.69	% SZS status Ended for HL405637+4.p
107147.75/14652.80	% SZS status Started for HL405637+5.p
107147.75/14652.80	% SZS status GaveUp for HL405637+5.p
107147.75/14652.80	% SZS status Ended for HL405637+5.p
107152.81/14653.19	% SZS status Started for HL405631+4.p
107152.81/14653.19	% SZS status GaveUp for HL405631+4.p
107152.81/14653.19	eprover: CPU time limit exceeded, terminating
107152.81/14653.19	% SZS status Ended for HL405631+4.p
107182.72/14656.89	% SZS status Started for HL405638+5.p
107182.72/14656.89	% SZS status GaveUp for HL405638+5.p
107182.72/14656.89	% SZS status Ended for HL405638+5.p
107201.33/14659.29	% SZS status Started for HL405639+4.p
107201.33/14659.29	% SZS status GaveUp for HL405639+4.p
107201.33/14659.29	eprover: CPU time limit exceeded, terminating
107201.33/14659.29	% SZS status Ended for HL405639+4.p
107207.02/14659.94	% SZS status Started for HL405640+5.p
107207.02/14659.94	% SZS status Theorem for HL405640+5.p
107207.02/14659.94	% SZS status Ended for HL405640+5.p
107210.10/14660.34	% SZS status Started for HL405634+4.p
107210.10/14660.34	% SZS status GaveUp for HL405634+4.p
107210.10/14660.34	eprover: CPU time limit exceeded, terminating
107210.10/14660.34	% SZS status Ended for HL405634+4.p
107227.02/14662.51	% SZS status Started for HL405639+5.p
107227.02/14662.51	% SZS status GaveUp for HL405639+5.p
107227.02/14662.51	% SZS status Ended for HL405639+5.p
107233.93/14663.38	% SZS status Started for HL405640+4.p
107233.93/14663.38	% SZS status GaveUp for HL405640+4.p
107233.93/14663.38	eprover: CPU time limit exceeded, terminating
107233.93/14663.38	% SZS status Ended for HL405640+4.p
107245.96/14664.98	% SZS status Started for HL405635+4.p
107245.96/14664.98	% SZS status GaveUp for HL405635+4.p
107245.96/14664.98	eprover: CPU time limit exceeded, terminating
107245.96/14664.98	% SZS status Ended for HL405635+4.p
107251.23/14665.58	% SZS status Started for HL405643+4.p
107251.23/14665.58	% SZS status GaveUp for HL405643+4.p
107251.23/14665.58	eprover: CPU time limit exceeded, terminating
107251.23/14665.58	% SZS status Ended for HL405643+4.p
107263.55/14667.17	% SZS status Started for HL405641+4.p
107263.55/14667.17	% SZS status GaveUp for HL405641+4.p
107263.55/14667.17	eprover: CPU time limit exceeded, terminating
107263.55/14667.17	% SZS status Ended for HL405641+4.p
107275.92/14668.64	% SZS status Started for HL405641+5.p
107275.92/14668.64	% SZS status GaveUp for HL405641+5.p
107275.92/14668.64	% SZS status Ended for HL405641+5.p
107283.59/14669.60	% SZS status Started for HL405638+4.p
107283.59/14669.60	% SZS status GaveUp for HL405638+4.p
107283.59/14669.60	eprover: CPU time limit exceeded, terminating
107283.59/14669.60	% SZS status Ended for HL405638+4.p
107284.09/14669.65	% SZS status Started for HL405642+5.p
107284.09/14669.65	% SZS status GaveUp for HL405642+5.p
107284.09/14669.65	% SZS status Ended for HL405642+5.p
107293.80/14671.04	% SZS status Started for HL405642+4.p
107293.80/14671.04	% SZS status GaveUp for HL405642+4.p
107293.80/14671.04	eprover: CPU time limit exceeded, terminating
107293.80/14671.04	% SZS status Ended for HL405642+4.p
107308.07/14672.70	% SZS status Started for HL405643+5.p
107308.07/14672.70	% SZS status GaveUp for HL405643+5.p
107308.07/14672.70	% SZS status Ended for HL405643+5.p
107324.45/14674.77	% SZS status Started for HL405649+5.p
107324.45/14674.77	% SZS status Theorem for HL405649+5.p
107324.45/14674.77	% SZS status Ended for HL405649+5.p
107325.43/14674.95	% SZS status Started for HL405644+5.p
107325.43/14674.95	% SZS status GaveUp for HL405644+5.p
107325.43/14674.95	% SZS status Ended for HL405644+5.p
107341.80/14675.87	% SZS status Started for HL405644+4.p
107341.80/14675.87	% SZS status GaveUp for HL405644+4.p
107341.80/14675.87	eprover: CPU time limit exceeded, terminating
107341.80/14675.87	% SZS status Ended for HL405644+4.p
107360.12/14678.20	% SZS status Started for HL405646+5.p
107360.12/14678.20	% SZS status GaveUp for HL405646+5.p
107360.12/14678.20	% SZS status Ended for HL405646+5.p
107368.28/14679.27	% SZS status Started for HL405647+5.p
107368.28/14679.27	% SZS status GaveUp for HL405647+5.p
107368.28/14679.27	% SZS status Ended for HL405647+5.p
107413.20/14684.86	% SZS status Started for HL405650+5.p
107413.20/14684.86	% SZS status GaveUp for HL405650+5.p
107413.20/14684.86	% SZS status Ended for HL405650+5.p
107417.98/14685.51	% SZS status Started for HL405650+4.p
107417.98/14685.51	% SZS status GaveUp for HL405650+4.p
107417.98/14685.51	eprover: CPU time limit exceeded, terminating
107417.98/14685.51	% SZS status Ended for HL405650+4.p
107422.78/14686.07	% SZS status Started for HL405651+4.p
107422.78/14686.07	% SZS status GaveUp for HL405651+4.p
107422.78/14686.07	eprover: CPU time limit exceeded, terminating
107422.78/14686.07	% SZS status Ended for HL405651+4.p
107436.52/14687.80	% SZS status Started for HL405651+5.p
107436.52/14687.80	% SZS status GaveUp for HL405651+5.p
107436.52/14687.80	% SZS status Ended for HL405651+5.p
107480.61/14693.40	% SZS status Started for HL405646+4.p
107480.61/14693.40	% SZS status GaveUp for HL405646+4.p
107480.61/14693.40	eprover: CPU time limit exceeded, terminating
107480.61/14693.40	% SZS status Ended for HL405646+4.p
107490.47/14694.61	% SZS status Started for HL405652+5.p
107490.47/14694.61	% SZS status GaveUp for HL405652+5.p
107490.47/14694.61	% SZS status Ended for HL405652+5.p
107497.89/14695.59	% SZS status Started for HL405653+5.p
107497.89/14695.59	% SZS status GaveUp for HL405653+5.p
107497.89/14695.59	% SZS status Ended for HL405653+5.p
107499.48/14695.75	% SZS status Started for HL405653+4.p
107499.48/14695.75	% SZS status GaveUp for HL405653+4.p
107499.48/14695.75	eprover: CPU time limit exceeded, terminating
107499.48/14695.75	% SZS status Ended for HL405653+4.p
107500.20/14695.87	% SZS status Started for HL405647+4.p
107500.20/14695.87	% SZS status GaveUp for HL405647+4.p
107500.20/14695.87	eprover: CPU time limit exceeded, terminating
107500.20/14695.87	% SZS status Ended for HL405647+4.p
107512.54/14697.39	% SZS status Started for HL405649+4.p
107512.54/14697.39	% SZS status GaveUp for HL405649+4.p
107512.54/14697.39	eprover: CPU time limit exceeded, terminating
107512.54/14697.39	% SZS status Ended for HL405649+4.p
107519.05/14698.26	% SZS status Started for HL405654+4.p
107519.05/14698.26	% SZS status GaveUp for HL405654+4.p
107519.05/14698.26	eprover: CPU time limit exceeded, terminating
107519.05/14698.26	% SZS status Ended for HL405654+4.p
107557.38/14703.06	% SZS status Started for HL405654+5.p
107557.38/14703.06	% SZS status GaveUp for HL405654+5.p
107557.38/14703.06	% SZS status Ended for HL405654+5.p
107572.70/14705.02	% SZS status Started for HL405655+5.p
107572.70/14705.02	% SZS status GaveUp for HL405655+5.p
107572.70/14705.02	% SZS status Ended for HL405655+5.p
107574.11/14705.17	% SZS status Started for HL405655+4.p
107574.11/14705.17	% SZS status GaveUp for HL405655+4.p
107574.11/14705.17	eprover: CPU time limit exceeded, terminating
107574.11/14705.17	% SZS status Ended for HL405655+4.p
107575.91/14705.45	% SZS status Started for HL405657+5.p
107575.91/14705.45	% SZS status GaveUp for HL405657+5.p
107575.91/14705.45	% SZS status Ended for HL405657+5.p
107576.24/14705.54	% SZS status Started for HL405652+4.p
107576.24/14705.54	% SZS status GaveUp for HL405652+4.p
107576.24/14705.54	eprover: CPU time limit exceeded, terminating
107576.24/14705.54	% SZS status Ended for HL405652+4.p
107598.36/14707.85	% SZS status Started for HL405658+5.p
107598.36/14707.85	% SZS status GaveUp for HL405658+5.p
107598.36/14707.85	% SZS status Ended for HL405658+5.p
107636.81/14712.73	% SZS status Started for HL405660+5.p
107636.81/14712.73	% SZS status Theorem for HL405660+5.p
107636.81/14712.73	% SZS status Ended for HL405660+5.p
107652.94/14714.73	% SZS status Started for HL405659+5.p
107652.94/14714.73	% SZS status GaveUp for HL405659+5.p
107652.94/14714.73	% SZS status Ended for HL405659+5.p
107657.62/14715.34	% SZS status Started for HL405660+4.p
107657.62/14715.34	% SZS status GaveUp for HL405660+4.p
107657.62/14715.34	eprover: CPU time limit exceeded, terminating
107657.62/14715.34	% SZS status Ended for HL405660+4.p
107663.00/14716.00	% SZS status Started for HL405662+4.p
107663.00/14716.00	% SZS status GaveUp for HL405662+4.p
107663.00/14716.00	eprover: CPU time limit exceeded, terminating
107663.00/14716.00	% SZS status Ended for HL405662+4.p
107673.87/14717.35	% SZS status Started for HL405662+5.p
107673.87/14717.35	% SZS status GaveUp for HL405662+5.p
107673.87/14717.35	% SZS status Ended for HL405662+5.p
107709.62/14721.93	% SZS status Started for HL405657+4.p
107709.62/14721.93	% SZS status GaveUp for HL405657+4.p
107709.62/14721.93	eprover: CPU time limit exceeded, terminating
107709.62/14721.93	% SZS status Ended for HL405657+4.p
107719.31/14723.11	% SZS status Started for HL405663+4.p
107719.31/14723.11	% SZS status GaveUp for HL405663+4.p
107719.31/14723.11	eprover: CPU time limit exceeded, terminating
107719.31/14723.11	% SZS status Ended for HL405663+4.p
107723.18/14723.66	% SZS status Started for HL405658+4.p
107723.18/14723.66	% SZS status GaveUp for HL405658+4.p
107723.18/14723.66	eprover: CPU time limit exceeded, terminating
107723.18/14723.66	% SZS status Ended for HL405658+4.p
107729.40/14724.37	% SZS status Started for HL405663+5.p
107729.40/14724.37	% SZS status GaveUp for HL405663+5.p
107729.40/14724.37	% SZS status Ended for HL405663+5.p
107738.93/14725.59	% SZS status Started for HL405665+5.p
107738.93/14725.59	% SZS status GaveUp for HL405665+5.p
107738.93/14725.59	% SZS status Ended for HL405665+5.p
107739.73/14725.75	% SZS status Started for HL405665+4.p
107739.73/14725.75	% SZS status GaveUp for HL405665+4.p
107739.73/14725.75	eprover: CPU time limit exceeded, terminating
107739.73/14725.75	% SZS status Ended for HL405665+4.p
107768.79/14729.41	% SZS status Started for HL405659+4.p
107768.79/14729.41	% SZS status GaveUp for HL405659+4.p
107768.79/14729.41	eprover: CPU time limit exceeded, terminating
107768.79/14729.41	% SZS status Ended for HL405659+4.p
107786.16/14731.51	% SZS status Started for HL405666+5.p
107786.16/14731.51	% SZS status GaveUp for HL405666+5.p
107786.16/14731.51	% SZS status Ended for HL405666+5.p
107799.03/14733.28	% SZS status Started for HL405667+5.p
107799.03/14733.28	% SZS status GaveUp for HL405667+5.p
107799.03/14733.28	% SZS status Ended for HL405667+5.p
107801.01/14733.41	% SZS status Started for HL405667+4.p
107801.01/14733.41	% SZS status GaveUp for HL405667+4.p
107801.01/14733.41	eprover: CPU time limit exceeded, terminating
107801.01/14733.41	% SZS status Ended for HL405667+4.p
107814.48/14735.08	% SZS status Started for HL405668+5.p
107814.48/14735.08	% SZS status GaveUp for HL405668+5.p
107814.48/14735.08	% SZS status Ended for HL405668+5.p
107845.59/14738.95	% SZS status Started for HL405669+5.p
107845.59/14738.95	% SZS status GaveUp for HL405669+5.p
107845.59/14738.95	% SZS status Ended for HL405669+5.p
107875.77/14742.79	% SZS status Started for HL405670+5.p
107875.77/14742.79	% SZS status GaveUp for HL405670+5.p
107875.77/14742.79	% SZS status Ended for HL405670+5.p
107881.78/14743.55	% SZS status Started for HL405666+4.p
107881.78/14743.55	% SZS status GaveUp for HL405666+4.p
107881.78/14743.55	eprover: CPU time limit exceeded, terminating
107881.78/14743.55	% SZS status Ended for HL405666+4.p
107890.27/14744.58	% SZS status Started for HL405671+5.p
107890.27/14744.58	% SZS status GaveUp for HL405671+5.p
107890.27/14744.58	% SZS status Ended for HL405671+5.p
107942.17/14751.09	% SZS status Started for HL405668+4.p
107942.17/14751.09	% SZS status GaveUp for HL405668+4.p
107942.17/14751.09	eprover: CPU time limit exceeded, terminating
107942.17/14751.09	% SZS status Ended for HL405668+4.p
107949.02/14751.95	% SZS status Started for HL405669+4.p
107949.02/14751.95	% SZS status GaveUp for HL405669+4.p
107949.02/14751.95	eprover: CPU time limit exceeded, terminating
107949.02/14751.95	% SZS status Ended for HL405669+4.p
107950.95/14752.29	% SZS status Started for HL405672+5.p
107950.95/14752.29	% SZS status GaveUp for HL405672+5.p
107950.95/14752.29	% SZS status Ended for HL405672+5.p
107966.52/14754.15	% SZS status Started for HL405673+5.p
107966.52/14754.15	% SZS status GaveUp for HL405673+5.p
107966.52/14754.15	% SZS status Ended for HL405673+5.p
107993.59/14757.72	% SZS status Started for HL405670+4.p
107993.59/14757.72	% SZS status GaveUp for HL405670+4.p
107993.59/14757.72	eprover: CPU time limit exceeded, terminating
107993.59/14757.72	% SZS status Ended for HL405670+4.p
108011.10/14759.94	% SZS status Started for HL405671+4.p
108011.10/14759.94	% SZS status GaveUp for HL405671+4.p
108011.10/14759.94	eprover: CPU time limit exceeded, terminating
108011.10/14759.94	% SZS status Ended for HL405671+4.p
108024.95/14761.57	% SZS status Started for HL405675+5.p
108024.95/14761.57	% SZS status GaveUp for HL405675+5.p
108024.95/14761.57	% SZS status Ended for HL405675+5.p
108024.95/14761.62	% SZS status Started for HL405675+4.p
108024.95/14761.62	% SZS status GaveUp for HL405675+4.p
108024.95/14761.62	eprover: CPU time limit exceeded, terminating
108024.95/14761.62	% SZS status Ended for HL405675+4.p
108042.00/14763.73	% SZS status Started for HL405676+5.p
108042.00/14763.73	% SZS status GaveUp for HL405676+5.p
108042.00/14763.73	% SZS status Ended for HL405676+5.p
108053.21/14765.12	% SZS status Started for HL405672+4.p
108053.21/14765.12	% SZS status GaveUp for HL405672+4.p
108053.21/14765.12	eprover: CPU time limit exceeded, terminating
108053.21/14765.12	% SZS status Ended for HL405672+4.p
108089.95/14769.71	% SZS status Started for HL405677+5.p
108089.95/14769.71	% SZS status GaveUp for HL405677+5.p
108089.95/14769.71	% SZS status Ended for HL405677+5.p
108089.95/14769.74	% SZS status Started for HL405673+4.p
108089.95/14769.74	% SZS status GaveUp for HL405673+4.p
108089.95/14769.74	eprover: CPU time limit exceeded, terminating
108089.95/14769.74	% SZS status Ended for HL405673+4.p
108103.13/14771.38	% SZS status Started for HL405678+5.p
108103.13/14771.38	% SZS status GaveUp for HL405678+5.p
108103.13/14771.38	% SZS status Ended for HL405678+5.p
108129.52/14774.71	% SZS status Started for HL405679+5.p
108129.52/14774.71	% SZS status GaveUp for HL405679+5.p
108129.52/14774.71	% SZS status Ended for HL405679+5.p
108146.01/14776.77	% SZS status Started for HL405680+5.p
108146.01/14776.77	% SZS status Theorem for HL405680+5.p
108146.01/14776.77	% SZS status Ended for HL405680+5.p
108159.48/14778.45	% SZS status Started for HL405676+4.p
108159.48/14778.45	% SZS status GaveUp for HL405676+4.p
108159.48/14778.45	eprover: CPU time limit exceeded, terminating
108159.48/14778.45	% SZS status Ended for HL405676+4.p
108185.10/14781.68	% SZS status Started for HL405681+4.p
108185.10/14781.68	% SZS status GaveUp for HL405681+4.p
108185.10/14781.68	eprover: CPU time limit exceeded, terminating
108185.10/14781.68	% SZS status Ended for HL405681+4.p
108203.38/14784.00	% SZS status Started for HL405677+4.p
108203.38/14784.00	% SZS status GaveUp for HL405677+4.p
108203.38/14784.00	eprover: CPU time limit exceeded, terminating
108203.38/14784.00	% SZS status Ended for HL405677+4.p
108204.72/14784.22	% SZS status Started for HL405681+5.p
108204.72/14784.22	% SZS status GaveUp for HL405681+5.p
108204.72/14784.22	% SZS status Ended for HL405681+5.p
108226.91/14786.99	% SZS status Started for HL405682+4.p
108226.91/14786.99	% SZS status GaveUp for HL405682+4.p
108226.91/14786.99	eprover: CPU time limit exceeded, terminating
108226.91/14786.99	% SZS status Ended for HL405682+4.p
108234.09/14787.86	% SZS status Started for HL405678+4.p
108234.09/14787.86	% SZS status GaveUp for HL405678+4.p
108234.09/14787.86	eprover: CPU time limit exceeded, terminating
108234.09/14787.86	% SZS status Ended for HL405678+4.p
108236.63/14788.21	% SZS status Started for HL405682+5.p
108236.63/14788.21	% SZS status GaveUp for HL405682+5.p
108236.63/14788.21	% SZS status Ended for HL405682+5.p
108249.91/14789.97	% SZS status Started for HL405679+4.p
108249.91/14789.97	% SZS status GaveUp for HL405679+4.p
108249.91/14789.97	eprover: CPU time limit exceeded, terminating
108249.91/14789.97	% SZS status Ended for HL405679+4.p
108265.45/14791.89	% SZS status Started for HL405685+4.p
108265.45/14791.89	% SZS status GaveUp for HL405685+4.p
108265.45/14791.89	eprover: CPU time limit exceeded, terminating
108265.45/14791.89	% SZS status Ended for HL405685+4.p
108280.26/14793.70	% SZS status Started for HL405685+5.p
108280.26/14793.70	% SZS status GaveUp for HL405685+5.p
108280.26/14793.70	% SZS status Ended for HL405685+5.p
108298.91/14796.03	% SZS status Started for HL405680+4.p
108298.91/14796.03	% SZS status GaveUp for HL405680+4.p
108298.91/14796.03	eprover: CPU time limit exceeded, terminating
108298.91/14796.03	% SZS status Ended for HL405680+4.p
108306.05/14796.91	% SZS status Started for HL405686+5.p
108306.05/14796.91	% SZS status GaveUp for HL405686+5.p
108306.05/14796.91	% SZS status Ended for HL405686+5.p
108312.84/14797.75	% SZS status Started for HL405687+5.p
108312.84/14797.75	% SZS status GaveUp for HL405687+5.p
108312.84/14797.75	% SZS status Ended for HL405687+5.p
108320.15/14798.67	% SZS status Started for HL405688+5.p
108320.15/14798.67	% SZS status Theorem for HL405688+5.p
108320.15/14798.67	% SZS status Ended for HL405688+5.p
108331.91/14800.20	% SZS status Started for HL405688+4.p
108331.91/14800.20	% SZS status GaveUp for HL405688+4.p
108331.91/14800.20	eprover: CPU time limit exceeded, terminating
108331.91/14800.20	% SZS status Ended for HL405688+4.p
108356.55/14803.29	% SZS status Started for HL405689+5.p
108356.55/14803.29	% SZS status Theorem for HL405689+5.p
108356.55/14803.29	% SZS status Ended for HL405689+5.p
108392.23/14807.79	% SZS status Started for HL405690+5.p
108392.23/14807.79	% SZS status GaveUp for HL405690+5.p
108392.23/14807.79	% SZS status Ended for HL405690+5.p
108408.99/14809.87	% SZS status Started for HL405692+5.p
108408.99/14809.87	% SZS status GaveUp for HL405692+5.p
108408.99/14809.87	% SZS status Ended for HL405692+5.p
108414.17/14810.52	% SZS status Started for HL405686+4.p
108414.17/14810.52	% SZS status GaveUp for HL405686+4.p
108414.17/14810.52	eprover: CPU time limit exceeded, terminating
108414.17/14810.52	% SZS status Ended for HL405686+4.p
108442.20/14814.11	% SZS status Started for HL405687+4.p
108442.20/14814.11	% SZS status GaveUp for HL405687+4.p
108442.20/14814.11	eprover: CPU time limit exceeded, terminating
108442.20/14814.11	% SZS status Ended for HL405687+4.p
108468.12/14817.35	% SZS status Started for HL405693+5.p
108468.12/14817.35	% SZS status GaveUp for HL405693+5.p
108468.12/14817.35	% SZS status Ended for HL405693+5.p
108489.48/14820.03	% SZS status Started for HL405689+4.p
108489.48/14820.03	% SZS status GaveUp for HL405689+4.p
108489.48/14820.03	eprover: CPU time limit exceeded, terminating
108489.48/14820.03	% SZS status Ended for HL405689+4.p
108489.69/14820.04	% SZS status Started for HL405694+5.p
108489.69/14820.04	% SZS status GaveUp for HL405694+5.p
108489.69/14820.04	% SZS status Ended for HL405694+5.p
108505.44/14822.10	% SZS status Started for HL405694+4.p
108505.44/14822.10	% SZS status GaveUp for HL405694+4.p
108505.44/14822.10	eprover: CPU time limit exceeded, terminating
108505.44/14822.10	% SZS status Ended for HL405694+4.p
108513.18/14823.08	% SZS status Started for HL405690+4.p
108513.18/14823.08	% SZS status GaveUp for HL405690+4.p
108513.18/14823.08	eprover: CPU time limit exceeded, terminating
108513.18/14823.08	% SZS status Ended for HL405690+4.p
108527.96/14824.92	% SZS status Started for HL405692+4.p
108527.96/14824.92	% SZS status GaveUp for HL405692+4.p
108527.96/14824.92	eprover: CPU time limit exceeded, terminating
108527.96/14824.92	% SZS status Ended for HL405692+4.p
108545.25/14827.09	% SZS status Started for HL405695+5.p
108545.25/14827.09	% SZS status GaveUp for HL405695+5.p
108545.25/14827.09	% SZS status Ended for HL405695+5.p
108554.79/14828.31	% SZS status Started for HL405695+4.p
108554.79/14828.31	% SZS status GaveUp for HL405695+4.p
108554.79/14828.31	eprover: CPU time limit exceeded, terminating
108554.79/14828.31	% SZS status Ended for HL405695+4.p
108564.61/14829.58	% SZS status Started for HL405696+5.p
108564.61/14829.58	% SZS status GaveUp for HL405696+5.p
108564.61/14829.58	% SZS status Ended for HL405696+5.p
108566.48/14829.76	% SZS status Started for HL405693+4.p
108566.48/14829.76	% SZS status GaveUp for HL405693+4.p
108566.48/14829.76	eprover: CPU time limit exceeded, terminating
108566.48/14829.76	% SZS status Ended for HL405693+4.p
108590.17/14832.71	% SZS status Started for HL405697+5.p
108590.17/14832.71	% SZS status GaveUp for HL405697+5.p
108590.17/14832.71	% SZS status Ended for HL405697+5.p
108608.73/14835.07	% SZS status Started for HL405698+4.p
108608.73/14835.07	% SZS status GaveUp for HL405698+4.p
108608.73/14835.07	eprover: CPU time limit exceeded, terminating
108608.73/14835.07	% SZS status Ended for HL405698+4.p
108620.62/14836.62	% SZS status Started for HL405698+5.p
108620.62/14836.62	% SZS status GaveUp for HL405698+5.p
108620.62/14836.62	% SZS status Ended for HL405698+5.p
108641.78/14839.22	% SZS status Started for HL405699+5.p
108641.78/14839.22	% SZS status GaveUp for HL405699+5.p
108641.78/14839.22	% SZS status Ended for HL405699+5.p
108663.44/14842.00	% SZS status Started for HL405700+5.p
108663.44/14842.00	% SZS status GaveUp for HL405700+5.p
108663.44/14842.00	% SZS status Ended for HL405700+5.p
108696.50/14846.11	% SZS status Started for HL405702+5.p
108696.50/14846.11	% SZS status GaveUp for HL405702+5.p
108696.50/14846.11	% SZS status Ended for HL405702+5.p
108696.50/14846.16	% SZS status Started for HL405696+4.p
108696.50/14846.16	% SZS status GaveUp for HL405696+4.p
108696.50/14846.16	eprover: CPU time limit exceeded, terminating
108696.50/14846.16	% SZS status Ended for HL405696+4.p
108715.45/14848.55	% SZS status Started for HL405697+4.p
108715.45/14848.55	% SZS status GaveUp for HL405697+4.p
108715.45/14848.55	eprover: CPU time limit exceeded, terminating
108715.45/14848.55	% SZS status Ended for HL405697+4.p
108740.25/14851.69	% SZS status Started for HL405704+5.p
108740.25/14851.69	% SZS status GaveUp for HL405704+5.p
108740.25/14851.69	% SZS status Ended for HL405704+5.p
108764.48/14854.68	% SZS status Started for HL405699+4.p
108764.48/14854.68	% SZS status GaveUp for HL405699+4.p
108764.48/14854.68	eprover: CPU time limit exceeded, terminating
108764.48/14854.68	% SZS status Ended for HL405699+4.p
108772.20/14855.67	% SZS status Started for HL405705+5.p
108772.20/14855.67	% SZS status GaveUp for HL405705+5.p
108772.20/14855.67	% SZS status Ended for HL405705+5.p
108774.75/14856.00	% SZS status Started for HL405700+4.p
108774.75/14856.00	% SZS status GaveUp for HL405700+4.p
108774.75/14856.00	eprover: CPU time limit exceeded, terminating
108774.75/14856.00	% SZS status Ended for HL405700+4.p
108778.40/14856.46	% SZS status Started for HL405705+4.p
108778.40/14856.46	% SZS status GaveUp for HL405705+4.p
108778.40/14856.46	eprover: CPU time limit exceeded, terminating
108778.40/14856.46	% SZS status Ended for HL405705+4.p
108799.01/14859.05	% SZS status Started for HL405706+4.p
108799.01/14859.05	% SZS status GaveUp for HL405706+4.p
108799.01/14859.05	eprover: CPU time limit exceeded, terminating
108799.01/14859.05	% SZS status Ended for HL405706+4.p
108816.34/14861.30	% SZS status Started for HL405706+5.p
108816.34/14861.30	% SZS status GaveUp for HL405706+5.p
108816.34/14861.30	% SZS status Ended for HL405706+5.p
108817.12/14861.40	% SZS status Started for HL405702+4.p
108817.12/14861.40	% SZS status GaveUp for HL405702+4.p
108817.12/14861.40	eprover: CPU time limit exceeded, terminating
108817.12/14861.40	% SZS status Ended for HL405702+4.p
108848.27/14865.26	% SZS status Started for HL405707+5.p
108848.27/14865.26	% SZS status GaveUp for HL405707+5.p
108848.27/14865.26	% SZS status Ended for HL405707+5.p
108848.92/14865.34	% SZS status Started for HL405704+4.p
108848.92/14865.34	% SZS status GaveUp for HL405704+4.p
108848.92/14865.34	eprover: CPU time limit exceeded, terminating
108848.92/14865.34	% SZS status Ended for HL405704+4.p
108853.59/14865.99	% SZS status Started for HL405708+5.p
108853.59/14865.99	% SZS status GaveUp for HL405708+5.p
108853.59/14865.99	% SZS status Ended for HL405708+5.p
108893.01/14870.84	% SZS status Started for HL405710+5.p
108893.01/14870.84	% SZS status GaveUp for HL405710+5.p
108893.01/14870.84	% SZS status Ended for HL405710+5.p
108899.02/14871.59	% SZS status Started for HL405711+4.p
108899.02/14871.59	% SZS status GaveUp for HL405711+4.p
108899.02/14871.59	eprover: CPU time limit exceeded, terminating
108899.02/14871.59	% SZS status Ended for HL405711+4.p
108925.50/14874.93	% SZS status Started for HL405711+5.p
108925.50/14874.93	% SZS status GaveUp for HL405711+5.p
108925.50/14874.93	% SZS status Ended for HL405711+5.p
108929.73/14875.48	% SZS status Started for HL405713+5.p
108929.73/14875.48	% SZS status GaveUp for HL405713+5.p
108929.73/14875.48	% SZS status Ended for HL405713+5.p
108973.11/14880.90	% SZS status Started for HL405707+4.p
108973.11/14880.90	% SZS status GaveUp for HL405707+4.p
108973.11/14880.90	eprover: CPU time limit exceeded, terminating
108973.11/14880.90	% SZS status Ended for HL405707+4.p
108974.47/14881.15	% SZS status Started for HL405714+5.p
108974.47/14881.15	% SZS status GaveUp for HL405714+5.p
108974.47/14881.15	% SZS status Ended for HL405714+5.p
108984.49/14882.46	% SZS status Started for HL405708+4.p
108984.49/14882.46	% SZS status GaveUp for HL405708+4.p
108984.49/14882.46	eprover: CPU time limit exceeded, terminating
108984.49/14882.46	% SZS status Ended for HL405708+4.p
109006.54/14885.11	% SZS status Started for HL405715+5.p
109006.54/14885.11	% SZS status GaveUp for HL405715+5.p
109006.54/14885.11	% SZS status Ended for HL405715+5.p
109006.91/14885.24	% SZS status Started for HL405710+4.p
109006.91/14885.24	% SZS status GaveUp for HL405710+4.p
109006.91/14885.24	eprover: CPU time limit exceeded, terminating
109006.91/14885.24	% SZS status Ended for HL405710+4.p
109051.46/14890.87	% SZS status Started for HL405716+5.p
109051.46/14890.87	% SZS status GaveUp for HL405716+5.p
109051.46/14890.87	% SZS status Ended for HL405716+5.p
109054.25/14891.20	% SZS status Started for HL405716+4.p
109054.25/14891.20	% SZS status GaveUp for HL405716+4.p
109054.25/14891.20	eprover: CPU time limit exceeded, terminating
109054.25/14891.20	% SZS status Ended for HL405716+4.p
109056.86/14891.52	% SZS status Started for HL405713+4.p
109056.86/14891.52	% SZS status GaveUp for HL405713+4.p
109056.86/14891.52	eprover: CPU time limit exceeded, terminating
109056.86/14891.52	% SZS status Ended for HL405713+4.p
109065.12/14892.60	% SZS status Started for HL405717+4.p
109065.12/14892.60	% SZS status GaveUp for HL405717+4.p
109065.12/14892.60	eprover: CPU time limit exceeded, terminating
109065.12/14892.60	% SZS status Ended for HL405717+4.p
109082.77/14894.68	% SZS status Started for HL405717+5.p
109082.77/14894.68	% SZS status GaveUp for HL405717+5.p
109082.77/14894.68	% SZS status Ended for HL405717+5.p
109091.23/14895.78	% SZS status Started for HL405719+4.p
109091.23/14895.78	% SZS status GaveUp for HL405719+4.p
109091.23/14895.78	eprover: CPU time limit exceeded, terminating
109091.23/14895.78	% SZS status Ended for HL405719+4.p
109100.66/14897.01	% SZS status Started for HL405714+4.p
109100.66/14897.01	% SZS status GaveUp for HL405714+4.p
109100.66/14897.01	eprover: CPU time limit exceeded, terminating
109100.66/14897.01	% SZS status Ended for HL405714+4.p
109128.05/14900.43	% SZS status Started for HL405719+5.p
109128.05/14900.43	% SZS status GaveUp for HL405719+5.p
109128.05/14900.43	% SZS status Ended for HL405719+5.p
109132.86/14901.06	% SZS status Started for HL405720+5.p
109132.86/14901.06	% SZS status GaveUp for HL405720+5.p
109132.86/14901.06	% SZS status Ended for HL405720+5.p
109135.27/14901.37	% SZS status Started for HL405715+4.p
109135.27/14901.37	% SZS status GaveUp for HL405715+4.p
109135.27/14901.37	eprover: CPU time limit exceeded, terminating
109135.27/14901.37	% SZS status Ended for HL405715+4.p
109147.96/14902.91	% SZS status Started for HL405722+4.p
109147.96/14902.91	% SZS status GaveUp for HL405722+4.p
109147.96/14902.91	eprover: CPU time limit exceeded, terminating
109147.96/14902.91	% SZS status Ended for HL405722+4.p
109159.77/14904.42	% SZS status Started for HL405722+5.p
109159.77/14904.42	% SZS status GaveUp for HL405722+5.p
109159.77/14904.42	% SZS status Ended for HL405722+5.p
109172.10/14905.96	% SZS status Started for HL405724+4.p
109172.10/14905.96	% SZS status GaveUp for HL405724+4.p
109172.10/14905.96	eprover: CPU time limit exceeded, terminating
109172.10/14905.96	% SZS status Ended for HL405724+4.p
109176.69/14906.58	% SZS status Started for HL405724+5.p
109176.69/14906.58	% SZS status GaveUp for HL405724+5.p
109176.69/14906.58	% SZS status Ended for HL405724+5.p
109208.74/14910.62	% SZS status Started for HL405725+5.p
109208.74/14910.62	% SZS status GaveUp for HL405725+5.p
109208.74/14910.62	% SZS status Ended for HL405725+5.p
109213.18/14911.13	% SZS status Started for HL405725+4.p
109213.18/14911.13	% SZS status GaveUp for HL405725+4.p
109213.18/14911.13	eprover: CPU time limit exceeded, terminating
109213.18/14911.13	% SZS status Ended for HL405725+4.p
109217.23/14911.59	% SZS status Started for HL405726+4.p
109217.23/14911.59	% SZS status GaveUp for HL405726+4.p
109217.23/14911.59	eprover: CPU time limit exceeded, terminating
109217.23/14911.59	% SZS status Ended for HL405726+4.p
109225.23/14912.64	% SZS status Started for HL405726+5.p
109225.23/14912.64	% SZS status GaveUp for HL405726+5.p
109225.23/14912.64	% SZS status Ended for HL405726+5.p
109240.87/14914.63	% SZS status Started for HL405727+4.p
109240.87/14914.63	% SZS status GaveUp for HL405727+4.p
109240.87/14914.63	eprover: CPU time limit exceeded, terminating
109240.87/14914.63	% SZS status Ended for HL405727+4.p
109248.12/14915.55	% SZS status Started for HL405727+5.p
109248.12/14915.55	% SZS status GaveUp for HL405727+5.p
109248.12/14915.55	% SZS status Ended for HL405727+5.p
109258.79/14916.90	% SZS status Started for HL405728+4.p
109258.79/14916.90	% SZS status GaveUp for HL405728+4.p
109258.79/14916.90	eprover: CPU time limit exceeded, terminating
109258.79/14916.90	% SZS status Ended for HL405728+4.p
109265.69/14917.69	% SZS status Started for HL405720+4.p
109265.69/14917.69	% SZS status GaveUp for HL405720+4.p
109265.69/14917.69	eprover: CPU time limit exceeded, terminating
109265.69/14917.69	% SZS status Ended for HL405720+4.p
109290.77/14920.93	% SZS status Started for HL405728+5.p
109290.77/14920.93	% SZS status GaveUp for HL405728+5.p
109290.77/14920.93	% SZS status Ended for HL405728+5.p
109293.59/14921.20	% SZS status Started for HL405729+5.p
109293.59/14921.20	% SZS status GaveUp for HL405729+5.p
109293.59/14921.20	% SZS status Ended for HL405729+5.p
109294.35/14921.33	% SZS status Started for HL405729+4.p
109294.35/14921.33	% SZS status GaveUp for HL405729+4.p
109294.35/14921.33	eprover: CPU time limit exceeded, terminating
109294.35/14921.33	% SZS status Ended for HL405729+4.p
109305.88/14922.87	% SZS status Started for HL405730+4.p
109305.88/14922.87	% SZS status GaveUp for HL405730+4.p
109305.88/14922.87	eprover: CPU time limit exceeded, terminating
109305.88/14922.87	% SZS status Ended for HL405730+4.p
109317.34/14924.25	% SZS status Started for HL405730+5.p
109317.34/14924.25	% SZS status GaveUp for HL405730+5.p
109317.34/14924.25	% SZS status Ended for HL405730+5.p
109329.47/14925.77	% SZS status Started for HL405731+4.p
109329.47/14925.77	% SZS status GaveUp for HL405731+4.p
109329.47/14925.77	eprover: CPU time limit exceeded, terminating
109329.47/14925.77	% SZS status Ended for HL405731+4.p
109336.70/14926.75	% SZS status Started for HL405731+5.p
109336.70/14926.75	% SZS status GaveUp for HL405731+5.p
109336.70/14926.75	% SZS status Ended for HL405731+5.p
109346.78/14927.96	% SZS status Started for HL405732+4.p
109346.78/14927.96	% SZS status GaveUp for HL405732+4.p
109346.78/14927.96	eprover: CPU time limit exceeded, terminating
109346.78/14927.96	% SZS status Ended for HL405732+4.p
109348.66/14928.31	% SZS status Started for HL405733+5.p
109348.66/14928.31	% SZS status Theorem for HL405733+5.p
109348.66/14928.31	% SZS status Ended for HL405733+5.p
109369.17/14930.84	% SZS status Started for HL405732+5.p
109369.17/14930.84	% SZS status GaveUp for HL405732+5.p
109369.17/14930.84	% SZS status Ended for HL405732+5.p
109374.54/14931.43	% SZS status Started for HL405733+4.p
109374.54/14931.43	% SZS status GaveUp for HL405733+4.p
109374.54/14931.43	eprover: CPU time limit exceeded, terminating
109374.54/14931.43	% SZS status Ended for HL405733+4.p
109388.77/14933.25	% SZS status Started for HL405734+4.p
109388.77/14933.25	% SZS status GaveUp for HL405734+4.p
109388.77/14933.25	eprover: CPU time limit exceeded, terminating
109388.77/14933.25	% SZS status Ended for HL405734+4.p
109392.72/14933.74	% SZS status Started for HL405734+5.p
109392.72/14933.74	% SZS status GaveUp for HL405734+5.p
109392.72/14933.74	% SZS status Ended for HL405734+5.p
109393.82/14933.98	% SZS status Started for HL405735+5.p
109393.82/14933.98	% SZS status Theorem for HL405735+5.p
109393.82/14933.98	% SZS status Ended for HL405735+5.p
109410.48/14935.97	% SZS status Started for HL405735+4.p
109410.48/14935.97	% SZS status GaveUp for HL405735+4.p
109410.48/14935.97	eprover: CPU time limit exceeded, terminating
109410.48/14935.97	% SZS status Ended for HL405735+4.p
109424.38/14937.73	% SZS status Started for HL405736+5.p
109424.38/14937.73	% SZS status GaveUp for HL405736+5.p
109424.38/14937.73	% SZS status Ended for HL405736+5.p
109427.80/14938.14	% SZS status Started for HL405736+4.p
109427.80/14938.14	% SZS status GaveUp for HL405736+4.p
109427.80/14938.14	eprover: CPU time limit exceeded, terminating
109427.80/14938.14	% SZS status Ended for HL405736+4.p
109449.25/14941.07	% SZS status Started for HL405737+5.p
109449.25/14941.07	% SZS status GaveUp for HL405737+5.p
109449.25/14941.07	% SZS status Ended for HL405737+5.p
109454.82/14941.66	% SZS status Started for HL405737+4.p
109454.82/14941.66	% SZS status GaveUp for HL405737+4.p
109454.82/14941.66	eprover: CPU time limit exceeded, terminating
109454.82/14941.66	% SZS status Ended for HL405737+4.p
109469.88/14943.43	% SZS status Started for HL405738+5.p
109469.88/14943.43	% SZS status GaveUp for HL405738+5.p
109469.88/14943.43	% SZS status Ended for HL405738+5.p
109471.02/14943.71	% SZS status Started for HL405738+4.p
109471.02/14943.71	% SZS status GaveUp for HL405738+4.p
109471.02/14943.71	eprover: CPU time limit exceeded, terminating
109471.02/14943.71	% SZS status Ended for HL405738+4.p
109479.56/14944.62	% SZS status Started for HL405739+4.p
109479.56/14944.62	% SZS status GaveUp for HL405739+4.p
109479.56/14944.62	eprover: CPU time limit exceeded, terminating
109479.56/14944.62	% SZS status Ended for HL405739+4.p
109486.52/14945.53	% SZS status Started for HL405739+5.p
109486.52/14945.53	% SZS status GaveUp for HL405739+5.p
109486.52/14945.53	% SZS status Ended for HL405739+5.p
109503.94/14947.72	% SZS status Started for HL405740+5.p
109503.94/14947.72	% SZS status GaveUp for HL405740+5.p
109503.94/14947.72	% SZS status Ended for HL405740+5.p
109508.63/14948.36	% SZS status Started for HL405740+4.p
109508.63/14948.36	% SZS status GaveUp for HL405740+4.p
109508.63/14948.36	eprover: CPU time limit exceeded, terminating
109508.63/14948.36	% SZS status Ended for HL405740+4.p
109532.35/14951.25	% SZS status Started for HL405741+5.p
109532.35/14951.25	% SZS status GaveUp for HL405741+5.p
109532.35/14951.25	% SZS status Ended for HL405741+5.p
109533.52/14951.46	% SZS status Started for HL405741+4.p
109533.52/14951.46	% SZS status GaveUp for HL405741+4.p
109533.52/14951.46	eprover: CPU time limit exceeded, terminating
109533.52/14951.46	% SZS status Ended for HL405741+4.p
109549.22/14953.45	% SZS status Started for HL405743+5.p
109549.22/14953.45	% SZS status GaveUp for HL405743+5.p
109549.22/14953.45	% SZS status Ended for HL405743+5.p
109556.48/14954.24	% SZS status Started for HL405743+4.p
109556.48/14954.24	% SZS status GaveUp for HL405743+4.p
109556.48/14954.24	eprover: CPU time limit exceeded, terminating
109556.48/14954.24	% SZS status Ended for HL405743+4.p
109561.87/14954.98	% SZS status Started for HL405744+4.p
109561.87/14954.98	% SZS status GaveUp for HL405744+4.p
109561.87/14954.98	eprover: CPU time limit exceeded, terminating
109561.87/14954.98	% SZS status Ended for HL405744+4.p
109562.86/14955.19	% SZS status Started for HL405744+5.p
109562.86/14955.19	% SZS status GaveUp for HL405744+5.p
109562.86/14955.19	% SZS status Ended for HL405744+5.p
109585.11/14957.91	% SZS status Started for HL405745+5.p
109585.11/14957.91	% SZS status GaveUp for HL405745+5.p
109585.11/14957.91	% SZS status Ended for HL405745+5.p
109586.85/14958.09	% SZS status Started for HL405745+4.p
109586.85/14958.09	% SZS status GaveUp for HL405745+4.p
109586.85/14958.09	eprover: CPU time limit exceeded, terminating
109586.85/14958.09	% SZS status Ended for HL405745+4.p
109609.56/14961.05	% SZS status Started for HL405746+5.p
109609.56/14961.05	% SZS status GaveUp for HL405746+5.p
109609.56/14961.05	% SZS status Ended for HL405746+5.p
109614.32/14961.58	% SZS status Started for HL405746+4.p
109614.32/14961.58	% SZS status GaveUp for HL405746+4.p
109614.32/14961.58	eprover: CPU time limit exceeded, terminating
109614.32/14961.58	% SZS status Ended for HL405746+4.p
109631.13/14963.66	% SZS status Started for HL405747+4.p
109631.13/14963.66	% SZS status GaveUp for HL405747+4.p
109631.13/14963.66	eprover: CPU time limit exceeded, terminating
109631.13/14963.66	% SZS status Ended for HL405747+4.p
109636.12/14964.11	% SZS status Started for HL405747+5.p
109636.12/14964.11	% SZS status GaveUp for HL405747+5.p
109636.12/14964.11	% SZS status Ended for HL405747+5.p
109640.72/14964.70	% SZS status Started for HL405749+5.p
109640.72/14964.70	% SZS status GaveUp for HL405749+5.p
109640.72/14964.70	% SZS status Ended for HL405749+5.p
109644.83/14965.22	% SZS status Started for HL405749+4.p
109644.83/14965.22	% SZS status GaveUp for HL405749+4.p
109644.83/14965.22	eprover: CPU time limit exceeded, terminating
109644.83/14965.22	% SZS status Ended for HL405749+4.p
109664.20/14967.74	% SZS status Started for HL405750+5.p
109664.20/14967.74	% SZS status GaveUp for HL405750+5.p
109664.20/14967.74	% SZS status Ended for HL405750+5.p
109673.46/14968.99	% SZS status Started for HL405750+4.p
109673.46/14968.99	% SZS status GaveUp for HL405750+4.p
109673.46/14968.99	eprover: CPU time limit exceeded, terminating
109673.46/14968.99	% SZS status Ended for HL405750+4.p
109686.39/14970.51	% SZS status Started for HL405755+5.p
109686.39/14970.51	% SZS status Theorem for HL405755+5.p
109686.39/14970.51	% SZS status Ended for HL405755+5.p
109692.25/14971.23	% SZS status Started for HL405751+5.p
109692.25/14971.23	% SZS status GaveUp for HL405751+5.p
109692.25/14971.23	% SZS status Ended for HL405751+5.p
109692.25/14971.27	% SZS status Started for HL405751+4.p
109692.25/14971.27	% SZS status GaveUp for HL405751+4.p
109692.25/14971.27	eprover: CPU time limit exceeded, terminating
109692.25/14971.27	% SZS status Ended for HL405751+4.p
109711.83/14973.73	% SZS status Started for HL405753+5.p
109711.83/14973.73	% SZS status GaveUp for HL405753+5.p
109711.83/14973.73	% SZS status Ended for HL405753+5.p
109713.37/14973.83	% SZS status Started for HL405753+4.p
109713.37/14973.83	% SZS status GaveUp for HL405753+4.p
109713.37/14973.83	eprover: CPU time limit exceeded, terminating
109713.37/14973.83	% SZS status Ended for HL405753+4.p
109719.36/14974.61	% SZS status Started for HL405754+5.p
109719.36/14974.61	% SZS status GaveUp for HL405754+5.p
109719.36/14974.61	% SZS status Ended for HL405754+5.p
109724.11/14975.20	% SZS status Started for HL405754+4.p
109724.11/14975.20	% SZS status GaveUp for HL405754+4.p
109724.11/14975.20	eprover: CPU time limit exceeded, terminating
109724.11/14975.20	% SZS status Ended for HL405754+4.p
109745.84/14977.92	% SZS status Started for HL405755+4.p
109745.84/14977.92	% SZS status GaveUp for HL405755+4.p
109745.84/14977.92	eprover: CPU time limit exceeded, terminating
109745.84/14977.92	% SZS status Ended for HL405755+4.p
109750.52/14978.59	% SZS status Started for HL405756+5.p
109750.52/14978.59	% SZS status Theorem for HL405756+5.p
109750.52/14978.59	% SZS status Ended for HL405756+5.p
109769.12/14980.92	% SZS status Started for HL405756+4.p
109769.12/14980.92	% SZS status GaveUp for HL405756+4.p
109769.12/14980.92	eprover: CPU time limit exceeded, terminating
109769.12/14980.92	% SZS status Ended for HL405756+4.p
109773.51/14981.49	% SZS status Started for HL405759+4.p
109773.51/14981.49	% SZS status GaveUp for HL405759+4.p
109773.51/14981.49	eprover: CPU time limit exceeded, terminating
109773.51/14981.49	% SZS status Ended for HL405759+4.p
109781.79/14982.56	% SZS status Started for HL405762+5.p
109781.79/14982.56	% SZS status Theorem for HL405762+5.p
109781.79/14982.56	% SZS status Ended for HL405762+5.p
109789.59/14983.47	% SZS status Started for HL405759+5.p
109789.59/14983.47	% SZS status GaveUp for HL405759+5.p
109789.59/14983.47	% SZS status Ended for HL405759+5.p
109795.11/14984.21	% SZS status Started for HL405760+4.p
109795.11/14984.21	% SZS status GaveUp for HL405760+4.p
109795.11/14984.21	eprover: CPU time limit exceeded, terminating
109795.11/14984.21	% SZS status Ended for HL405760+4.p
109796.38/14984.40	% SZS status Started for HL405760+5.p
109796.38/14984.40	% SZS status GaveUp for HL405760+5.p
109796.38/14984.40	% SZS status Ended for HL405760+5.p
109809.72/14986.04	% SZS status Started for HL405761+4.p
109809.72/14986.04	% SZS status GaveUp for HL405761+4.p
109809.72/14986.04	eprover: CPU time limit exceeded, terminating
109809.72/14986.04	% SZS status Ended for HL405761+4.p
109823.06/14987.76	% SZS status Started for HL405761+5.p
109823.06/14987.76	% SZS status GaveUp for HL405761+5.p
109823.06/14987.76	% SZS status Ended for HL405761+5.p
109833.10/14988.84	% SZS status Started for HL405762+4.p
109833.10/14988.84	% SZS status GaveUp for HL405762+4.p
109833.10/14988.84	eprover: CPU time limit exceeded, terminating
109833.10/14988.84	% SZS status Ended for HL405762+4.p
109856.04/14991.76	% SZS status Started for HL405763+4.p
109856.04/14991.76	% SZS status GaveUp for HL405763+4.p
109856.04/14991.76	eprover: CPU time limit exceeded, terminating
109856.04/14991.76	% SZS status Ended for HL405763+4.p
109857.09/14992.07	% SZS status Started for HL405763+5.p
109857.09/14992.07	% SZS status GaveUp for HL405763+5.p
109857.09/14992.07	% SZS status Ended for HL405763+5.p
109871.84/14993.75	% SZS status Started for HL405764+5.p
109871.84/14993.75	% SZS status GaveUp for HL405764+5.p
109871.84/14993.75	% SZS status Ended for HL405764+5.p
109877.30/14994.43	% SZS status Started for HL405764+4.p
109877.30/14994.43	% SZS status GaveUp for HL405764+4.p
109877.30/14994.43	eprover: CPU time limit exceeded, terminating
109877.30/14994.43	% SZS status Ended for HL405764+4.p
109879.84/14994.70	% SZS status Started for HL405765+4.p
109879.84/14994.70	% SZS status GaveUp for HL405765+4.p
109879.84/14994.70	eprover: CPU time limit exceeded, terminating
109879.84/14994.70	% SZS status Ended for HL405765+4.p
109886.37/14995.61	% SZS status Started for HL405765+5.p
109886.37/14995.61	% SZS status GaveUp for HL405765+5.p
109886.37/14995.61	% SZS status Ended for HL405765+5.p
109887.47/14995.70	% SZS status Started for HL405766+5.p
109887.47/14995.70	% SZS status Theorem for HL405766+5.p
109887.47/14995.70	% SZS status Ended for HL405766+5.p
109905.79/14998.12	% SZS status Started for HL405766+4.p
109905.79/14998.12	% SZS status GaveUp for HL405766+4.p
109905.79/14998.12	eprover: CPU time limit exceeded, terminating
109905.79/14998.12	% SZS status Ended for HL405766+4.p
109934.38/15001.68	% SZS status Started for HL405767+5.p
109934.38/15001.68	% SZS status GaveUp for HL405767+5.p
109934.38/15001.68	% SZS status Ended for HL405767+5.p
109937.16/15001.96	% SZS status Started for HL405767+4.p
109937.16/15001.96	% SZS status GaveUp for HL405767+4.p
109937.16/15001.96	eprover: CPU time limit exceeded, terminating
109937.16/15001.96	% SZS status Ended for HL405767+4.p
109952.57/15003.93	% SZS status Started for HL405768+4.p
109952.57/15003.93	% SZS status GaveUp for HL405768+4.p
109952.57/15003.93	eprover: CPU time limit exceeded, terminating
109952.57/15003.93	% SZS status Ended for HL405768+4.p
109953.03/15004.01	% SZS status Started for HL405768+5.p
109953.03/15004.01	% SZS status GaveUp for HL405768+5.p
109953.03/15004.01	% SZS status Ended for HL405768+5.p
109963.34/15005.19	% SZS status Started for HL405769+5.p
109963.34/15005.19	% SZS status GaveUp for HL405769+5.p
109963.34/15005.19	% SZS status Ended for HL405769+5.p
109964.41/15005.37	% SZS status Started for HL405769+4.p
109964.41/15005.37	% SZS status GaveUp for HL405769+4.p
109964.41/15005.37	eprover: CPU time limit exceeded, terminating
109964.41/15005.37	% SZS status Ended for HL405769+4.p
109968.43/15005.92	% SZS status Started for HL405770+4.p
109968.43/15005.92	% SZS status GaveUp for HL405770+4.p
109968.43/15005.92	eprover: CPU time limit exceeded, terminating
109968.43/15005.92	% SZS status Ended for HL405770+4.p
109982.75/15007.67	% SZS status Started for HL405770+5.p
109982.75/15007.67	% SZS status GaveUp for HL405770+5.p
109982.75/15007.67	% SZS status Ended for HL405770+5.p
109993.05/15009.05	% SZS status Started for HL405771+5.p
109993.05/15009.05	% SZS status Theorem for HL405771+5.p
109993.05/15009.05	% SZS status Ended for HL405771+5.p
110015.98/15011.88	% SZS status Started for HL405771+4.p
110015.98/15011.88	% SZS status GaveUp for HL405771+4.p
110015.98/15011.88	eprover: CPU time limit exceeded, terminating
110015.98/15011.88	% SZS status Ended for HL405771+4.p
110028.39/15013.58	% SZS status Started for HL405772+5.p
110028.39/15013.58	% SZS status GaveUp for HL405772+5.p
110028.39/15013.58	% SZS status Ended for HL405772+5.p
110033.68/15014.11	% SZS status Started for HL405772+4.p
110033.68/15014.11	% SZS status GaveUp for HL405772+4.p
110033.68/15014.11	eprover: CPU time limit exceeded, terminating
110033.68/15014.11	% SZS status Ended for HL405772+4.p
110037.45/15014.65	% SZS status Started for HL405774+5.p
110037.45/15014.65	% SZS status GaveUp for HL405774+5.p
110037.45/15014.65	% SZS status Ended for HL405774+5.p
110043.54/15015.35	% SZS status Started for HL405774+4.p
110043.54/15015.35	% SZS status GaveUp for HL405774+4.p
110043.54/15015.35	eprover: CPU time limit exceeded, terminating
110043.54/15015.35	% SZS status Ended for HL405774+4.p
110051.56/15016.28	% SZS status Started for HL405775+4.p
110051.56/15016.28	% SZS status GaveUp for HL405775+4.p
110051.56/15016.28	eprover: CPU time limit exceeded, terminating
110051.56/15016.28	% SZS status Ended for HL405775+4.p
110058.94/15017.24	% SZS status Started for HL405775+5.p
110058.94/15017.24	% SZS status GaveUp for HL405775+5.p
110058.94/15017.24	% SZS status Ended for HL405775+5.p
110074.96/15019.28	% SZS status Started for HL405776+4.p
110074.96/15019.28	% SZS status GaveUp for HL405776+4.p
110074.96/15019.28	eprover: CPU time limit exceeded, terminating
110074.96/15019.28	% SZS status Ended for HL405776+4.p
110092.82/15021.52	% SZS status Started for HL405776+5.p
110092.82/15021.52	% SZS status GaveUp for HL405776+5.p
110092.82/15021.52	% SZS status Ended for HL405776+5.p
110110.85/15023.80	% SZS status Started for HL405777+5.p
110110.85/15023.80	% SZS status GaveUp for HL405777+5.p
110110.85/15023.80	% SZS status Ended for HL405777+5.p
110110.85/15023.80	% SZS status Started for HL405777+4.p
110110.85/15023.80	% SZS status GaveUp for HL405777+4.p
110110.85/15023.80	eprover: CPU time limit exceeded, terminating
110110.85/15023.80	% SZS status Ended for HL405777+4.p
110118.66/15024.85	% SZS status Started for HL405778+4.p
110118.66/15024.85	% SZS status GaveUp for HL405778+4.p
110118.66/15024.85	eprover: CPU time limit exceeded, terminating
110118.66/15024.85	% SZS status Ended for HL405778+4.p
110120.80/15025.05	% SZS status Started for HL405778+5.p
110120.80/15025.05	% SZS status GaveUp for HL405778+5.p
110120.80/15025.05	% SZS status Ended for HL405778+5.p
110132.82/15026.53	% SZS status Started for HL405779+4.p
110132.82/15026.53	% SZS status GaveUp for HL405779+4.p
110132.82/15026.53	eprover: CPU time limit exceeded, terminating
110132.82/15026.53	% SZS status Ended for HL405779+4.p
110135.52/15026.92	% SZS status Started for HL405779+5.p
110135.52/15026.92	% SZS status GaveUp for HL405779+5.p
110135.52/15026.92	% SZS status Ended for HL405779+5.p
110155.41/15029.45	% SZS status Started for HL405780+4.p
110155.41/15029.45	% SZS status GaveUp for HL405780+4.p
110155.41/15029.45	eprover: CPU time limit exceeded, terminating
110155.41/15029.45	% SZS status Ended for HL405780+4.p
110169.59/15031.18	% SZS status Started for HL405780+5.p
110169.59/15031.18	% SZS status GaveUp for HL405780+5.p
110169.59/15031.18	% SZS status Ended for HL405780+5.p
110187.88/15033.55	% SZS status Started for HL405782+5.p
110187.88/15033.55	% SZS status GaveUp for HL405782+5.p
110187.88/15033.55	% SZS status Ended for HL405782+5.p
110194.82/15034.39	% SZS status Started for HL405782+4.p
110194.82/15034.39	% SZS status GaveUp for HL405782+4.p
110194.82/15034.39	eprover: CPU time limit exceeded, terminating
110194.82/15034.39	% SZS status Ended for HL405782+4.p
110196.52/15034.63	% SZS status Started for HL405783+5.p
110196.52/15034.63	% SZS status GaveUp for HL405783+5.p
110196.52/15034.63	% SZS status Ended for HL405783+5.p
110202.45/15035.35	% SZS status Started for HL405783+4.p
110202.45/15035.35	% SZS status GaveUp for HL405783+4.p
110202.45/15035.35	eprover: CPU time limit exceeded, terminating
110202.45/15035.35	% SZS status Ended for HL405783+4.p
110211.70/15036.45	% SZS status Started for HL405784+5.p
110211.70/15036.45	% SZS status GaveUp for HL405784+5.p
110211.70/15036.45	% SZS status Ended for HL405784+5.p
110215.16/15037.08	% SZS status Started for HL405784+4.p
110215.16/15037.08	% SZS status GaveUp for HL405784+4.p
110215.16/15037.08	eprover: CPU time limit exceeded, terminating
110215.16/15037.08	% SZS status Ended for HL405784+4.p
110237.24/15039.72	% SZS status Started for HL405785+4.p
110237.24/15039.72	% SZS status GaveUp for HL405785+4.p
110237.24/15039.72	eprover: CPU time limit exceeded, terminating
110237.24/15039.72	% SZS status Ended for HL405785+4.p
110245.80/15040.82	% SZS status Started for HL405785+5.p
110245.80/15040.82	% SZS status GaveUp for HL405785+5.p
110245.80/15040.82	% SZS status Ended for HL405785+5.p
110270.07/15043.94	% SZS status Started for HL405786+4.p
110270.07/15043.94	% SZS status GaveUp for HL405786+4.p
110270.07/15043.94	eprover: CPU time limit exceeded, terminating
110270.07/15043.94	% SZS status Ended for HL405786+4.p
110272.07/15044.08	% SZS status Started for HL405786+5.p
110272.07/15044.08	% SZS status GaveUp for HL405786+5.p
110272.07/15044.08	% SZS status Ended for HL405786+5.p
110278.91/15044.98	% SZS status Started for HL405787+4.p
110278.91/15044.98	% SZS status GaveUp for HL405787+4.p
110278.91/15044.98	eprover: CPU time limit exceeded, terminating
110278.91/15044.98	% SZS status Ended for HL405787+4.p
110278.91/15045.00	% SZS status Started for HL405787+5.p
110278.91/15045.00	% SZS status GaveUp for HL405787+5.p
110278.91/15045.00	% SZS status Ended for HL405787+5.p
110291.60/15046.62	% SZS status Started for HL405788+4.p
110291.60/15046.62	% SZS status GaveUp for HL405788+4.p
110291.60/15046.62	eprover: CPU time limit exceeded, terminating
110291.60/15046.62	% SZS status Ended for HL405788+4.p
110294.33/15046.90	% SZS status Started for HL405788+5.p
110294.33/15046.90	% SZS status GaveUp for HL405788+5.p
110294.33/15046.90	% SZS status Ended for HL405788+5.p
110317.75/15049.90	% SZS status Started for HL405789+4.p
110317.75/15049.90	% SZS status GaveUp for HL405789+4.p
110317.75/15049.90	eprover: CPU time limit exceeded, terminating
110317.75/15049.90	% SZS status Ended for HL405789+4.p
110322.27/15050.44	% SZS status Started for HL405789+5.p
110322.27/15050.44	% SZS status GaveUp for HL405789+5.p
110322.27/15050.44	% SZS status Ended for HL405789+5.p
110348.41/15053.77	% SZS status Started for HL405790+5.p
110348.41/15053.77	% SZS status GaveUp for HL405790+5.p
110348.41/15053.77	% SZS status Ended for HL405790+5.p
110355.38/15054.58	% SZS status Started for HL405791+5.p
110355.38/15054.58	% SZS status GaveUp for HL405791+5.p
110355.38/15054.58	% SZS status Ended for HL405791+5.p
110356.48/15054.76	% SZS status Started for HL405790+4.p
110356.48/15054.76	% SZS status GaveUp for HL405790+4.p
110356.48/15054.76	eprover: CPU time limit exceeded, terminating
110356.48/15054.76	% SZS status Ended for HL405790+4.p
110359.97/15055.18	% SZS status Started for HL405791+4.p
110359.97/15055.18	% SZS status GaveUp for HL405791+4.p
110359.97/15055.18	eprover: CPU time limit exceeded, terminating
110359.97/15055.18	% SZS status Ended for HL405791+4.p
110373.56/15056.84	% SZS status Started for HL405792+5.p
110373.56/15056.84	% SZS status GaveUp for HL405792+5.p
110373.56/15056.84	% SZS status Ended for HL405792+5.p
110378.70/15057.54	% SZS status Started for HL405792+4.p
110378.70/15057.54	% SZS status GaveUp for HL405792+4.p
110378.70/15057.54	eprover: CPU time limit exceeded, terminating
110378.70/15057.54	% SZS status Ended for HL405792+4.p
110398.97/15060.12	% SZS status Started for HL405793+5.p
110398.97/15060.12	% SZS status GaveUp for HL405793+5.p
110398.97/15060.12	% SZS status Ended for HL405793+5.p
110400.61/15060.34	% SZS status Started for HL405793+4.p
110400.61/15060.34	% SZS status GaveUp for HL405793+4.p
110400.61/15060.34	eprover: CPU time limit exceeded, terminating
110400.61/15060.34	% SZS status Ended for HL405793+4.p
110430.09/15063.99	% SZS status Started for HL405794+4.p
110430.09/15063.99	% SZS status GaveUp for HL405794+4.p
110430.09/15063.99	eprover: CPU time limit exceeded, terminating
110430.09/15063.99	% SZS status Ended for HL405794+4.p
110432.06/15064.39	% SZS status Started for HL405794+5.p
110432.06/15064.39	% SZS status GaveUp for HL405794+5.p
110432.06/15064.39	% SZS status Ended for HL405794+5.p
110435.63/15064.73	% SZS status Started for HL405795+5.p
110435.63/15064.73	% SZS status GaveUp for HL405795+5.p
110435.63/15064.73	% SZS status Ended for HL405795+5.p
110438.93/15065.10	% SZS status Started for HL405795+4.p
110438.93/15065.10	% SZS status GaveUp for HL405795+4.p
110438.93/15065.10	eprover: CPU time limit exceeded, terminating
110438.93/15065.10	% SZS status Ended for HL405795+4.p
110454.52/15067.11	% SZS status Started for HL405796+5.p
110454.52/15067.11	% SZS status GaveUp for HL405796+5.p
110454.52/15067.11	% SZS status Ended for HL405796+5.p
110455.86/15067.23	% SZS status Started for HL405796+4.p
110455.86/15067.23	% SZS status GaveUp for HL405796+4.p
110455.86/15067.23	eprover: CPU time limit exceeded, terminating
110455.86/15067.23	% SZS status Ended for HL405796+4.p
110476.32/15069.92	% SZS status Started for HL405799+5.p
110476.32/15069.92	% SZS status GaveUp for HL405799+5.p
110476.32/15069.92	% SZS status Ended for HL405799+5.p
110479.29/15070.31	% SZS status Started for HL405799+4.p
110479.29/15070.31	% SZS status GaveUp for HL405799+4.p
110479.29/15070.31	eprover: CPU time limit exceeded, terminating
110479.29/15070.31	% SZS status Ended for HL405799+4.p
110511.02/15074.29	% SZS status Started for HL405800+4.p
110511.02/15074.29	% SZS status GaveUp for HL405800+4.p
110511.02/15074.29	eprover: CPU time limit exceeded, terminating
110511.02/15074.29	% SZS status Ended for HL405800+4.p
110512.53/15074.39	% SZS status Started for HL405800+5.p
110512.53/15074.39	% SZS status GaveUp for HL405800+5.p
110512.53/15074.39	% SZS status Ended for HL405800+5.p
110514.58/15074.70	% SZS status Started for HL405801+5.p
110514.58/15074.70	% SZS status GaveUp for HL405801+5.p
110514.58/15074.70	% SZS status Ended for HL405801+5.p
110517.95/15075.05	% SZS status Started for HL405801+4.p
110517.95/15075.05	% SZS status GaveUp for HL405801+4.p
110517.95/15075.05	eprover: CPU time limit exceeded, terminating
110517.95/15075.05	% SZS status Ended for HL405801+4.p
110531.77/15076.87	% SZS status Started for HL405804+5.p
110531.77/15076.87	% SZS status GaveUp for HL405804+5.p
110531.77/15076.87	% SZS status Ended for HL405804+5.p
110537.36/15077.62	% SZS status Started for HL405804+4.p
110537.36/15077.62	% SZS status GaveUp for HL405804+4.p
110537.36/15077.62	eprover: CPU time limit exceeded, terminating
110537.36/15077.62	% SZS status Ended for HL405804+4.p
110556.04/15079.87	% SZS status Started for HL405805+5.p
110556.04/15079.87	% SZS status GaveUp for HL405805+5.p
110556.04/15079.87	% SZS status Ended for HL405805+5.p
110560.20/15080.40	% SZS status Started for HL405805+4.p
110560.20/15080.40	% SZS status GaveUp for HL405805+4.p
110560.20/15080.40	eprover: CPU time limit exceeded, terminating
110560.20/15080.40	% SZS status Ended for HL405805+4.p
110586.80/15083.75	% SZS status Started for HL405807+5.p
110586.80/15083.75	% SZS status GaveUp for HL405807+5.p
110586.80/15083.75	% SZS status Ended for HL405807+5.p
110592.52/15084.48	% SZS status Started for HL405807+4.p
110592.52/15084.48	% SZS status GaveUp for HL405807+4.p
110592.52/15084.48	eprover: CPU time limit exceeded, terminating
110592.52/15084.48	% SZS status Ended for HL405807+4.p
110593.27/15084.57	% SZS status Started for HL405809+5.p
110593.27/15084.57	% SZS status GaveUp for HL405809+5.p
110593.27/15084.57	% SZS status Ended for HL405809+5.p
110597.45/15085.06	% SZS status Started for HL405809+4.p
110597.45/15085.06	% SZS status GaveUp for HL405809+4.p
110597.45/15085.06	eprover: CPU time limit exceeded, terminating
110597.45/15085.06	% SZS status Ended for HL405809+4.p
110613.24/15087.12	% SZS status Started for HL405810+4.p
110613.24/15087.12	% SZS status GaveUp for HL405810+4.p
110613.24/15087.12	eprover: CPU time limit exceeded, terminating
110613.24/15087.12	% SZS status Ended for HL405810+4.p
110613.91/15087.13	% SZS status Started for HL405810+5.p
110613.91/15087.13	% SZS status GaveUp for HL405810+5.p
110613.91/15087.13	% SZS status Ended for HL405810+5.p
110633.44/15089.70	% SZS status Started for HL405811+5.p
110633.44/15089.70	% SZS status GaveUp for HL405811+5.p
110633.44/15089.70	% SZS status Ended for HL405811+5.p
110639.45/15090.46	% SZS status Started for HL405811+4.p
110639.45/15090.46	% SZS status GaveUp for HL405811+4.p
110639.45/15090.46	eprover: CPU time limit exceeded, terminating
110639.45/15090.46	% SZS status Ended for HL405811+4.p
110666.37/15093.81	% SZS status Started for HL405812+5.p
110666.37/15093.81	% SZS status GaveUp for HL405812+5.p
110666.37/15093.81	% SZS status Ended for HL405812+5.p
110671.05/15094.45	% SZS status Started for HL405812+4.p
110671.05/15094.45	% SZS status GaveUp for HL405812+4.p
110671.05/15094.45	eprover: CPU time limit exceeded, terminating
110671.05/15094.45	% SZS status Ended for HL405812+4.p
110672.35/15094.64	% SZS status Started for HL405813+5.p
110672.35/15094.64	% SZS status GaveUp for HL405813+5.p
110672.35/15094.64	% SZS status Ended for HL405813+5.p
110674.54/15094.81	% SZS status Started for HL405813+4.p
110674.54/15094.81	% SZS status GaveUp for HL405813+4.p
110674.54/15094.81	eprover: CPU time limit exceeded, terminating
110674.54/15094.81	% SZS status Ended for HL405813+4.p
110686.73/15096.41	% SZS status Started for HL405814+5.p
110686.73/15096.41	% SZS status GaveUp for HL405814+5.p
110686.73/15096.41	% SZS status Ended for HL405814+5.p
110693.81/15097.31	% SZS status Started for HL405814+4.p
110693.81/15097.31	% SZS status GaveUp for HL405814+4.p
110693.81/15097.31	eprover: CPU time limit exceeded, terminating
110693.81/15097.31	% SZS status Ended for HL405814+4.p
110716.04/15100.08	% SZS status Started for HL405815+4.p
110716.04/15100.08	% SZS status GaveUp for HL405815+4.p
110716.04/15100.08	eprover: CPU time limit exceeded, terminating
110716.04/15100.08	% SZS status Ended for HL405815+4.p
110717.12/15100.22	% SZS status Started for HL405815+5.p
110717.12/15100.22	% SZS status GaveUp for HL405815+5.p
110717.12/15100.22	% SZS status Ended for HL405815+5.p
110739.93/15103.09	% SZS status Started for HL405821+5.p
110739.93/15103.09	% SZS status Theorem for HL405821+5.p
110739.93/15103.09	% SZS status Ended for HL405821+5.p
110748.69/15104.14	% SZS status Started for HL405816+4.p
110748.69/15104.14	% SZS status GaveUp for HL405816+4.p
110748.69/15104.14	eprover: CPU time limit exceeded, terminating
110748.69/15104.14	% SZS status Ended for HL405816+4.p
110748.69/15104.16	% SZS status Started for HL405817+5.p
110748.69/15104.16	% SZS status GaveUp for HL405817+5.p
110748.69/15104.16	% SZS status Ended for HL405817+5.p
110749.97/15104.36	% SZS status Started for HL405816+5.p
110749.97/15104.36	% SZS status GaveUp for HL405816+5.p
110749.97/15104.36	% SZS status Ended for HL405816+5.p
110755.18/15104.98	% SZS status Started for HL405817+4.p
110755.18/15104.98	% SZS status GaveUp for HL405817+4.p
110755.18/15104.98	eprover: CPU time limit exceeded, terminating
110755.18/15104.98	% SZS status Ended for HL405817+4.p
110759.34/15105.49	% SZS status Started for HL405822+5.p
110759.34/15105.49	% SZS status Theorem for HL405822+5.p
110759.34/15105.49	% SZS status Ended for HL405822+5.p
110767.84/15106.59	% SZS status Started for HL405820+4.p
110767.84/15106.59	% SZS status GaveUp for HL405820+4.p
110767.84/15106.59	eprover: CPU time limit exceeded, terminating
110767.84/15106.59	% SZS status Ended for HL405820+4.p
110770.28/15106.90	% SZS status Started for HL405820+5.p
110770.28/15106.90	% SZS status GaveUp for HL405820+5.p
110770.28/15106.90	% SZS status Ended for HL405820+5.p
110797.23/15110.24	% SZS status Started for HL405821+4.p
110797.23/15110.24	% SZS status GaveUp for HL405821+4.p
110797.23/15110.24	eprover: CPU time limit exceeded, terminating
110797.23/15110.24	% SZS status Ended for HL405821+4.p
110824.14/15113.64	% SZS status Started for HL405824+5.p
110824.14/15113.64	% SZS status GaveUp for HL405824+5.p
110824.14/15113.64	% SZS status Ended for HL405824+5.p
110825.28/15113.82	% SZS status Started for HL405822+4.p
110825.28/15113.82	% SZS status GaveUp for HL405822+4.p
110825.28/15113.82	eprover: CPU time limit exceeded, terminating
110825.28/15113.82	% SZS status Ended for HL405822+4.p
110829.70/15114.33	% SZS status Started for HL405824+4.p
110829.70/15114.33	% SZS status GaveUp for HL405824+4.p
110829.70/15114.33	eprover: CPU time limit exceeded, terminating
110829.70/15114.33	% SZS status Ended for HL405824+4.p
110834.62/15115.01	% SZS status Started for HL405825+5.p
110834.62/15115.01	% SZS status GaveUp for HL405825+5.p
110834.62/15115.01	% SZS status Ended for HL405825+5.p
110837.95/15115.40	% SZS status Started for HL405825+4.p
110837.95/15115.40	% SZS status GaveUp for HL405825+4.p
110837.95/15115.40	eprover: CPU time limit exceeded, terminating
110837.95/15115.40	% SZS status Ended for HL405825+4.p
110843.68/15116.20	% SZS status Started for HL405826+5.p
110843.68/15116.20	% SZS status GaveUp for HL405826+5.p
110843.68/15116.20	% SZS status Ended for HL405826+5.p
110844.62/15116.34	% SZS status Started for HL405828+5.p
110844.62/15116.34	% SZS status Theorem for HL405828+5.p
110844.62/15116.34	% SZS status Ended for HL405828+5.p
110850.31/15116.96	% SZS status Started for HL405826+4.p
110850.31/15116.96	% SZS status GaveUp for HL405826+4.p
110850.31/15116.96	eprover: CPU time limit exceeded, terminating
110850.31/15116.96	% SZS status Ended for HL405826+4.p
110878.70/15120.53	% SZS status Started for HL405827+4.p
110878.70/15120.53	% SZS status GaveUp for HL405827+4.p
110878.70/15120.53	eprover: CPU time limit exceeded, terminating
110878.70/15120.53	% SZS status Ended for HL405827+4.p
110898.25/15123.13	% SZS status Started for HL405827+5.p
110898.25/15123.13	% SZS status GaveUp for HL405827+5.p
110898.25/15123.13	% SZS status Ended for HL405827+5.p
110908.09/15124.37	% SZS status Started for HL405828+4.p
110908.09/15124.37	% SZS status GaveUp for HL405828+4.p
110908.09/15124.37	eprover: CPU time limit exceeded, terminating
110908.09/15124.37	% SZS status Ended for HL405828+4.p
110912.28/15124.73	% SZS status Started for HL405829+5.p
110912.28/15124.73	% SZS status GaveUp for HL405829+5.p
110912.28/15124.73	% SZS status Ended for HL405829+5.p
110915.66/15125.19	% SZS status Started for HL405829+4.p
110915.66/15125.19	% SZS status GaveUp for HL405829+4.p
110915.66/15125.19	eprover: CPU time limit exceeded, terminating
110915.66/15125.19	% SZS status Ended for HL405829+4.p
110919.90/15125.74	% SZS status Started for HL405830+5.p
110919.90/15125.74	% SZS status GaveUp for HL405830+5.p
110919.90/15125.74	% SZS status Ended for HL405830+5.p
110924.76/15126.38	% SZS status Started for HL405830+4.p
110924.76/15126.38	% SZS status GaveUp for HL405830+4.p
110924.76/15126.38	eprover: CPU time limit exceeded, terminating
110924.76/15126.38	% SZS status Ended for HL405830+4.p
110930.24/15127.19	% SZS status Started for HL405831+4.p
110930.24/15127.19	% SZS status GaveUp for HL405831+4.p
110930.24/15127.19	eprover: CPU time limit exceeded, terminating
110930.24/15127.19	% SZS status Ended for HL405831+4.p
110955.80/15130.24	% SZS status Started for HL405831+5.p
110955.80/15130.24	% SZS status GaveUp for HL405831+5.p
110955.80/15130.24	% SZS status Ended for HL405831+5.p
110955.80/15130.26	% SZS status Started for HL405836+4.p
110955.80/15130.26	% SZS status GaveUp for HL405836+4.p
110955.80/15130.26	eprover: CPU time limit exceeded, terminating
110955.80/15130.26	% SZS status Ended for HL405836+4.p
110983.29/15133.84	% SZS status Started for HL405832+5.p
110983.29/15133.84	% SZS status GaveUp for HL405832+5.p
110983.29/15133.84	% SZS status Ended for HL405832+5.p
110985.69/15134.05	% SZS status Started for HL405832+4.p
110985.69/15134.05	% SZS status GaveUp for HL405832+4.p
110985.69/15134.05	eprover: CPU time limit exceeded, terminating
110985.69/15134.05	% SZS status Ended for HL405832+4.p
110988.01/15134.48	% SZS status Started for HL405833+5.p
110988.01/15134.48	% SZS status GaveUp for HL405833+5.p
110988.01/15134.48	% SZS status Ended for HL405833+5.p
110992.59/15134.97	% SZS status Started for HL405833+4.p
110992.59/15134.97	% SZS status GaveUp for HL405833+4.p
110992.59/15134.97	eprover: CPU time limit exceeded, terminating
110992.59/15134.97	% SZS status Ended for HL405833+4.p
110998.80/15135.71	% SZS status Started for HL405834+5.p
110998.80/15135.71	% SZS status GaveUp for HL405834+5.p
110998.80/15135.71	% SZS status Ended for HL405834+5.p
111000.55/15136.01	% SZS status Started for HL405834+4.p
111000.55/15136.01	% SZS status GaveUp for HL405834+4.p
111000.55/15136.01	eprover: CPU time limit exceeded, terminating
111000.55/15136.01	% SZS status Ended for HL405834+4.p
111032.61/15139.99	% SZS status Started for HL405836+5.p
111032.61/15139.99	% SZS status GaveUp for HL405836+5.p
111032.61/15139.99	% SZS status Ended for HL405836+5.p
111040.83/15141.00	% SZS status Started for HL405837+4.p
111040.83/15141.00	% SZS status GaveUp for HL405837+4.p
111040.83/15141.00	eprover: CPU time limit exceeded, terminating
111040.83/15141.00	% SZS status Ended for HL405837+4.p
111059.88/15143.38	% SZS status Started for HL405837+5.p
111059.88/15143.38	% SZS status GaveUp for HL405837+5.p
111059.88/15143.38	% SZS status Ended for HL405837+5.p
111064.84/15143.99	% SZS status Started for HL405838+5.p
111064.84/15143.99	% SZS status GaveUp for HL405838+5.p
111064.84/15143.99	% SZS status Ended for HL405838+5.p
111066.66/15144.34	% SZS status Started for HL405838+4.p
111066.66/15144.34	% SZS status GaveUp for HL405838+4.p
111066.66/15144.34	eprover: CPU time limit exceeded, terminating
111066.66/15144.34	% SZS status Ended for HL405838+4.p
111074.71/15145.25	% SZS status Started for HL405839+4.p
111074.71/15145.25	% SZS status GaveUp for HL405839+4.p
111074.71/15145.25	eprover: CPU time limit exceeded, terminating
111074.71/15145.25	% SZS status Ended for HL405839+4.p
111074.93/15145.28	% SZS status Started for HL405839+5.p
111074.93/15145.28	% SZS status GaveUp for HL405839+5.p
111074.93/15145.28	% SZS status Ended for HL405839+5.p
111082.34/15146.20	% SZS status Started for HL405840+4.p
111082.34/15146.20	% SZS status GaveUp for HL405840+4.p
111082.34/15146.20	eprover: CPU time limit exceeded, terminating
111082.34/15146.20	% SZS status Ended for HL405840+4.p
111109.22/15149.61	% SZS status Started for HL405840+5.p
111109.22/15149.61	% SZS status GaveUp for HL405840+5.p
111109.22/15149.61	% SZS status Ended for HL405840+5.p
111122.41/15151.22	% SZS status Started for HL405841+4.p
111122.41/15151.22	% SZS status GaveUp for HL405841+4.p
111122.41/15151.22	eprover: CPU time limit exceeded, terminating
111122.41/15151.22	% SZS status Ended for HL405841+4.p
111136.14/15152.99	% SZS status Started for HL405841+5.p
111136.14/15152.99	% SZS status GaveUp for HL405841+5.p
111136.14/15152.99	% SZS status Ended for HL405841+5.p
111143.12/15153.91	% SZS status Started for HL405842+5.p
111143.12/15153.91	% SZS status GaveUp for HL405842+5.p
111143.12/15153.91	% SZS status Ended for HL405842+5.p
111145.80/15154.21	% SZS status Started for HL405842+4.p
111145.80/15154.21	% SZS status GaveUp for HL405842+4.p
111145.80/15154.21	eprover: CPU time limit exceeded, terminating
111145.80/15154.21	% SZS status Ended for HL405842+4.p
111148.27/15154.57	% SZS status Started for HL405845+5.p
111148.27/15154.57	% SZS status Theorem for HL405845+5.p
111148.27/15154.57	% SZS status Ended for HL405845+5.p
111151.75/15154.90	% SZS status Started for HL405843+5.p
111151.75/15154.90	% SZS status GaveUp for HL405843+5.p
111151.75/15154.90	% SZS status Ended for HL405843+5.p
111156.34/15155.52	% SZS status Started for HL405843+4.p
111156.34/15155.52	% SZS status GaveUp for HL405843+4.p
111156.34/15155.52	eprover: CPU time limit exceeded, terminating
111156.34/15155.52	% SZS status Ended for HL405843+4.p
111164.88/15156.63	% SZS status Started for HL405844+4.p
111164.88/15156.63	% SZS status GaveUp for HL405844+4.p
111164.88/15156.63	eprover: CPU time limit exceeded, terminating
111164.88/15156.63	% SZS status Ended for HL405844+4.p
111186.28/15159.28	% SZS status Started for HL405844+5.p
111186.28/15159.28	% SZS status GaveUp for HL405844+5.p
111186.28/15159.28	% SZS status Ended for HL405844+5.p
111205.21/15161.72	% SZS status Started for HL405845+4.p
111205.21/15161.72	% SZS status GaveUp for HL405845+4.p
111205.21/15161.72	eprover: CPU time limit exceeded, terminating
111205.21/15161.72	% SZS status Ended for HL405845+4.p
111219.38/15163.56	% SZS status Started for HL405846+5.p
111219.38/15163.56	% SZS status GaveUp for HL405846+5.p
111219.38/15163.56	% SZS status Ended for HL405846+5.p
111225.29/15164.16	% SZS status Started for HL405846+4.p
111225.29/15164.16	% SZS status GaveUp for HL405846+4.p
111225.29/15164.16	eprover: CPU time limit exceeded, terminating
111225.29/15164.16	% SZS status Ended for HL405846+4.p
111227.66/15164.55	% SZS status Started for HL405847+5.p
111227.66/15164.55	% SZS status GaveUp for HL405847+5.p
111227.66/15164.55	% SZS status Ended for HL405847+5.p
111232.75/15165.16	% SZS status Started for HL405847+4.p
111232.75/15165.16	% SZS status GaveUp for HL405847+4.p
111232.75/15165.16	eprover: CPU time limit exceeded, terminating
111232.75/15165.16	% SZS status Ended for HL405847+4.p
111238.60/15165.85	% SZS status Started for HL405848+4.p
111238.60/15165.85	% SZS status GaveUp for HL405848+4.p
111238.60/15165.85	eprover: CPU time limit exceeded, terminating
111238.60/15165.85	% SZS status Ended for HL405848+4.p
111241.59/15166.33	% SZS status Started for HL405848+5.p
111241.59/15166.33	% SZS status GaveUp for HL405848+5.p
111241.59/15166.33	% SZS status Ended for HL405848+5.p
111268.99/15169.68	% SZS status Started for HL405849+4.p
111268.99/15169.68	% SZS status GaveUp for HL405849+4.p
111268.99/15169.68	eprover: CPU time limit exceeded, terminating
111268.99/15169.68	% SZS status Ended for HL405849+4.p
111282.12/15171.32	% SZS status Started for HL405849+5.p
111282.12/15171.32	% SZS status GaveUp for HL405849+5.p
111282.12/15171.32	% SZS status Ended for HL405849+5.p
111301.23/15173.75	% SZS status Started for HL405850+4.p
111301.23/15173.75	% SZS status GaveUp for HL405850+4.p
111301.23/15173.75	eprover: CPU time limit exceeded, terminating
111301.23/15173.75	% SZS status Ended for HL405850+4.p
111301.81/15173.89	% SZS status Started for HL405850+5.p
111301.81/15173.89	% SZS status GaveUp for HL405850+5.p
111301.81/15173.89	% SZS status Ended for HL405850+5.p
111309.61/15174.79	% SZS status Started for HL405852+4.p
111309.61/15174.79	% SZS status GaveUp for HL405852+4.p
111309.61/15174.79	eprover: CPU time limit exceeded, terminating
111309.61/15174.79	% SZS status Ended for HL405852+4.p
111309.61/15174.80	% SZS status Started for HL405852+5.p
111309.61/15174.80	% SZS status GaveUp for HL405852+5.p
111309.61/15174.80	% SZS status Ended for HL405852+5.p
111318.84/15175.94	% SZS status Started for HL405853+5.p
111318.84/15175.94	% SZS status GaveUp for HL405853+5.p
111318.84/15175.94	% SZS status Ended for HL405853+5.p
111323.42/15176.54	% SZS status Started for HL405853+4.p
111323.42/15176.54	% SZS status GaveUp for HL405853+4.p
111323.42/15176.54	eprover: CPU time limit exceeded, terminating
111323.42/15176.54	% SZS status Ended for HL405853+4.p
111354.00/15180.47	% SZS status Started for HL405854+4.p
111354.00/15180.47	% SZS status GaveUp for HL405854+4.p
111354.00/15180.47	eprover: CPU time limit exceeded, terminating
111354.00/15180.47	% SZS status Ended for HL405854+4.p
111358.27/15180.92	% SZS status Started for HL405854+5.p
111358.27/15180.92	% SZS status GaveUp for HL405854+5.p
111358.27/15180.92	% SZS status Ended for HL405854+5.p
111378.24/15183.44	% SZS status Started for HL405855+5.p
111378.24/15183.44	% SZS status GaveUp for HL405855+5.p
111378.24/15183.44	% SZS status Ended for HL405855+5.p
111383.02/15184.05	% SZS status Started for HL405855+4.p
111383.02/15184.05	% SZS status GaveUp for HL405855+4.p
111383.02/15184.05	eprover: CPU time limit exceeded, terminating
111383.02/15184.05	% SZS status Ended for HL405855+4.p
111384.79/15184.36	% SZS status Started for HL405856+5.p
111384.79/15184.36	% SZS status GaveUp for HL405856+5.p
111384.79/15184.36	% SZS status Ended for HL405856+5.p
111392.05/15185.21	% SZS status Started for HL405856+4.p
111392.05/15185.21	% SZS status GaveUp for HL405856+4.p
111392.05/15185.21	eprover: CPU time limit exceeded, terminating
111392.05/15185.21	% SZS status Ended for HL405856+4.p
111399.80/15186.14	% SZS status Started for HL405857+5.p
111399.80/15186.14	% SZS status GaveUp for HL405857+5.p
111399.80/15186.14	% SZS status Ended for HL405857+5.p
111401.35/15186.35	% SZS status Started for HL405857+4.p
111401.35/15186.35	% SZS status GaveUp for HL405857+4.p
111401.35/15186.35	eprover: CPU time limit exceeded, terminating
111401.35/15186.35	% SZS status Ended for HL405857+4.p
111434.33/15190.50	% SZS status Started for HL405858+5.p
111434.33/15190.50	% SZS status GaveUp for HL405858+5.p
111434.33/15190.50	% SZS status Ended for HL405858+5.p
111435.64/15190.68	% SZS status Started for HL405858+4.p
111435.64/15190.68	% SZS status GaveUp for HL405858+4.p
111435.64/15190.68	eprover: CPU time limit exceeded, terminating
111435.64/15190.68	% SZS status Ended for HL405858+4.p
111459.60/15193.66	% SZS status Started for HL405859+5.p
111459.60/15193.66	% SZS status GaveUp for HL405859+5.p
111459.60/15193.66	% SZS status Ended for HL405859+5.p
111460.05/15193.80	% SZS status Started for HL405859+4.p
111460.05/15193.80	% SZS status GaveUp for HL405859+4.p
111460.05/15193.80	eprover: CPU time limit exceeded, terminating
111460.05/15193.80	% SZS status Ended for HL405859+4.p
111466.16/15194.62	% SZS status Started for HL405860+4.p
111466.16/15194.62	% SZS status GaveUp for HL405860+4.p
111466.16/15194.62	eprover: CPU time limit exceeded, terminating
111466.16/15194.62	% SZS status Ended for HL405860+4.p
111467.94/15194.75	% SZS status Started for HL405860+5.p
111467.94/15194.75	% SZS status GaveUp for HL405860+5.p
111467.94/15194.75	% SZS status Ended for HL405860+5.p
111476.26/15195.83	% SZS status Started for HL405861+5.p
111476.26/15195.83	% SZS status GaveUp for HL405861+5.p
111476.26/15195.83	% SZS status Ended for HL405861+5.p
111481.41/15196.45	% SZS status Started for HL405861+4.p
111481.41/15196.45	% SZS status GaveUp for HL405861+4.p
111481.41/15196.45	eprover: CPU time limit exceeded, terminating
111481.41/15196.45	% SZS status Ended for HL405861+4.p
111512.41/15200.32	% SZS status Started for HL405862+5.p
111512.41/15200.32	% SZS status GaveUp for HL405862+5.p
111512.41/15200.32	% SZS status Ended for HL405862+5.p
111518.18/15201.05	% SZS status Started for HL405862+4.p
111518.18/15201.05	% SZS status GaveUp for HL405862+4.p
111518.18/15201.05	eprover: CPU time limit exceeded, terminating
111518.18/15201.05	% SZS status Ended for HL405862+4.p
111532.98/15203.02	% SZS status Started for HL405866+5.p
111532.98/15203.02	% SZS status Theorem for HL405866+5.p
111532.98/15203.02	% SZS status Ended for HL405866+5.p
111535.52/15203.35	% SZS status Started for HL405864+5.p
111535.52/15203.35	% SZS status GaveUp for HL405864+5.p
111535.52/15203.35	% SZS status Ended for HL405864+5.p
111541.50/15204.05	% SZS status Started for HL405864+4.p
111541.50/15204.05	% SZS status GaveUp for HL405864+4.p
111541.50/15204.05	eprover: CPU time limit exceeded, terminating
111541.50/15204.05	% SZS status Ended for HL405864+4.p
111546.85/15204.75	% SZS status Started for HL405865+5.p
111546.85/15204.75	% SZS status GaveUp for HL405865+5.p
111546.85/15204.75	% SZS status Ended for HL405865+5.p
111548.38/15204.85	% SZS status Started for HL405865+4.p
111548.38/15204.85	% SZS status GaveUp for HL405865+4.p
111548.38/15204.85	eprover: CPU time limit exceeded, terminating
111548.38/15204.85	% SZS status Ended for HL405865+4.p
111558.40/15206.22	% SZS status Started for HL405866+4.p
111558.40/15206.22	% SZS status GaveUp for HL405866+4.p
111558.40/15206.22	eprover: CPU time limit exceeded, terminating
111558.40/15206.22	% SZS status Ended for HL405866+4.p
111593.03/15210.54	% SZS status Started for HL405867+4.p
111593.03/15210.54	% SZS status GaveUp for HL405867+4.p
111593.03/15210.54	eprover: CPU time limit exceeded, terminating
111593.03/15210.54	% SZS status Ended for HL405867+4.p
111594.73/15210.75	% SZS status Started for HL405867+5.p
111594.73/15210.75	% SZS status GaveUp for HL405867+5.p
111594.73/15210.75	% SZS status Ended for HL405867+5.p
111613.05/15213.10	% SZS status Started for HL405868+5.p
111613.05/15213.10	% SZS status GaveUp for HL405868+5.p
111613.05/15213.10	% SZS status Ended for HL405868+5.p
111615.62/15213.38	% SZS status Started for HL405868+4.p
111615.62/15213.38	% SZS status GaveUp for HL405868+4.p
111615.62/15213.38	eprover: CPU time limit exceeded, terminating
111615.62/15213.38	% SZS status Ended for HL405868+4.p
111623.30/15214.35	% SZS status Started for HL405869+5.p
111623.30/15214.35	% SZS status GaveUp for HL405869+5.p
111623.30/15214.35	% SZS status Ended for HL405869+5.p
111624.42/15214.45	% SZS status Started for HL405869+4.p
111624.42/15214.45	% SZS status GaveUp for HL405869+4.p
111624.42/15214.45	eprover: CPU time limit exceeded, terminating
111624.42/15214.45	% SZS status Ended for HL405869+4.p
111629.20/15215.10	% SZS status Started for HL405870+4.p
111629.20/15215.10	% SZS status GaveUp for HL405870+4.p
111629.20/15215.10	eprover: CPU time limit exceeded, terminating
111629.20/15215.10	% SZS status Ended for HL405870+4.p
111635.48/15215.90	% SZS status Started for HL405870+5.p
111635.48/15215.90	% SZS status GaveUp for HL405870+5.p
111635.48/15215.90	% SZS status Ended for HL405870+5.p
111673.55/15220.68	% SZS status Started for HL405872+5.p
111673.55/15220.68	% SZS status GaveUp for HL405872+5.p
111673.55/15220.68	% SZS status Ended for HL405872+5.p
111675.01/15220.89	% SZS status Started for HL405872+4.p
111675.01/15220.89	% SZS status GaveUp for HL405872+4.p
111675.01/15220.89	eprover: CPU time limit exceeded, terminating
111675.01/15220.89	% SZS status Ended for HL405872+4.p
111689.52/15222.89	% SZS status Started for HL405873+5.p
111689.52/15222.89	% SZS status GaveUp for HL405873+5.p
111689.52/15222.89	% SZS status Ended for HL405873+5.p
111697.52/15223.69	% SZS status Started for HL405873+4.p
111697.52/15223.69	% SZS status GaveUp for HL405873+4.p
111697.52/15223.69	eprover: CPU time limit exceeded, terminating
111697.52/15223.69	% SZS status Ended for HL405873+4.p
111699.45/15224.05	% SZS status Started for HL405874+5.p
111699.45/15224.05	% SZS status GaveUp for HL405874+5.p
111699.45/15224.05	% SZS status Ended for HL405874+5.p
111703.45/15224.59	% SZS status Started for HL405874+4.p
111703.45/15224.59	% SZS status GaveUp for HL405874+4.p
111703.45/15224.59	eprover: CPU time limit exceeded, terminating
111703.45/15224.59	% SZS status Ended for HL405874+4.p
111710.65/15225.30	% SZS status Started for HL405875+4.p
111710.65/15225.30	% SZS status GaveUp for HL405875+4.p
111710.65/15225.30	eprover: CPU time limit exceeded, terminating
111710.65/15225.30	% SZS status Ended for HL405875+4.p
111710.65/15225.34	% SZS status Started for HL405875+5.p
111710.65/15225.34	% SZS status GaveUp for HL405875+5.p
111710.65/15225.34	% SZS status Ended for HL405875+5.p
111752.83/15230.65	% SZS status Started for HL405876+5.p
111752.83/15230.65	% SZS status GaveUp for HL405876+5.p
111752.83/15230.65	% SZS status Ended for HL405876+5.p
111754.48/15230.89	% SZS status Started for HL405876+4.p
111754.48/15230.89	% SZS status GaveUp for HL405876+4.p
111754.48/15230.89	eprover: CPU time limit exceeded, terminating
111754.48/15230.89	% SZS status Ended for HL405876+4.p
111772.84/15233.32	% SZS status Started for HL405877+5.p
111772.84/15233.32	% SZS status GaveUp for HL405877+5.p
111772.84/15233.32	% SZS status Ended for HL405877+5.p
111778.20/15233.88	% SZS status Started for HL405877+4.p
111778.20/15233.88	% SZS status GaveUp for HL405877+4.p
111778.20/15233.88	eprover: CPU time limit exceeded, terminating
111778.20/15233.88	% SZS status Ended for HL405877+4.p
111781.10/15234.20	% SZS status Started for HL405878+5.p
111781.10/15234.20	% SZS status GaveUp for HL405878+5.p
111781.10/15234.20	% SZS status Ended for HL405878+5.p
111781.30/15234.24	% SZS status Started for HL405878+4.p
111781.30/15234.24	% SZS status GaveUp for HL405878+4.p
111781.30/15234.24	eprover: CPU time limit exceeded, terminating
111781.30/15234.24	% SZS status Ended for HL405878+4.p
111787.63/15235.02	% SZS status Started for HL405879+5.p
111787.63/15235.02	% SZS status GaveUp for HL405879+5.p
111787.63/15235.02	% SZS status Ended for HL405879+5.p
111791.13/15235.49	% SZS status Started for HL405879+4.p
111791.13/15235.49	% SZS status GaveUp for HL405879+4.p
111791.13/15235.49	eprover: CPU time limit exceeded, terminating
111791.13/15235.49	% SZS status Ended for HL405879+4.p
111830.48/15240.46	% SZS status Started for HL405880+5.p
111830.48/15240.46	% SZS status GaveUp for HL405880+5.p
111830.48/15240.46	% SZS status Ended for HL405880+5.p
111836.69/15241.23	% SZS status Started for HL405880+4.p
111836.69/15241.23	% SZS status GaveUp for HL405880+4.p
111836.69/15241.23	eprover: CPU time limit exceeded, terminating
111836.69/15241.23	% SZS status Ended for HL405880+4.p
111855.51/15243.53	% SZS status Started for HL405881+5.p
111855.51/15243.53	% SZS status GaveUp for HL405881+5.p
111855.51/15243.53	% SZS status Ended for HL405881+5.p
111858.57/15243.97	% SZS status Started for HL405881+4.p
111858.57/15243.97	% SZS status GaveUp for HL405881+4.p
111858.57/15243.97	eprover: CPU time limit exceeded, terminating
111858.57/15243.97	% SZS status Ended for HL405881+4.p
111859.52/15244.06	% SZS status Started for HL405882+5.p
111859.52/15244.06	% SZS status GaveUp for HL405882+5.p
111859.52/15244.06	% SZS status Ended for HL405882+5.p
111863.80/15244.60	% SZS status Started for HL405882+4.p
111863.80/15244.60	% SZS status GaveUp for HL405882+4.p
111863.80/15244.60	eprover: CPU time limit exceeded, terminating
111863.80/15244.60	% SZS status Ended for HL405882+4.p
111867.45/15245.03	% SZS status Started for HL405883+5.p
111867.45/15245.03	% SZS status GaveUp for HL405883+5.p
111867.45/15245.03	% SZS status Ended for HL405883+5.p
111868.97/15245.31	% SZS status Started for HL405883+4.p
111868.97/15245.31	% SZS status GaveUp for HL405883+4.p
111868.97/15245.31	eprover: CPU time limit exceeded, terminating
111868.97/15245.31	% SZS status Ended for HL405883+4.p
111912.02/15250.70	% SZS status Started for HL405884+4.p
111912.02/15250.70	% SZS status GaveUp for HL405884+4.p
111912.02/15250.70	eprover: CPU time limit exceeded, terminating
111912.02/15250.70	% SZS status Ended for HL405884+4.p
111913.46/15251.00	% SZS status Started for HL405884+5.p
111913.46/15251.00	% SZS status GaveUp for HL405884+5.p
111913.46/15251.00	% SZS status Ended for HL405884+5.p
111934.61/15253.60	% SZS status Started for HL405885+5.p
111934.61/15253.60	% SZS status GaveUp for HL405885+5.p
111934.61/15253.60	% SZS status Ended for HL405885+5.p
111935.52/15253.73	% SZS status Started for HL405885+4.p
111935.52/15253.73	% SZS status GaveUp for HL405885+4.p
111935.52/15253.73	eprover: CPU time limit exceeded, terminating
111935.52/15253.73	% SZS status Ended for HL405885+4.p
111939.20/15254.22	% SZS status Started for HL405886+5.p
111939.20/15254.22	% SZS status GaveUp for HL405886+5.p
111939.20/15254.22	% SZS status Ended for HL405886+5.p
111939.61/15254.26	% SZS status Started for HL405886+4.p
111939.61/15254.26	% SZS status GaveUp for HL405886+4.p
111939.61/15254.26	eprover: CPU time limit exceeded, terminating
111939.61/15254.26	% SZS status Ended for HL405886+4.p
111946.10/15254.95	% SZS status Started for HL405887+5.p
111946.10/15254.95	% SZS status GaveUp for HL405887+5.p
111946.10/15254.95	% SZS status Ended for HL405887+5.p
111947.48/15255.22	% SZS status Started for HL405887+4.p
111947.48/15255.22	% SZS status GaveUp for HL405887+4.p
111947.48/15255.22	eprover: CPU time limit exceeded, terminating
111947.48/15255.22	% SZS status Ended for HL405887+4.p
111987.41/15260.34	% SZS status Started for HL405888+5.p
111987.41/15260.34	% SZS status GaveUp for HL405888+5.p
111987.41/15260.34	% SZS status Ended for HL405888+5.p
111994.70/15261.10	% SZS status Started for HL405888+4.p
111994.70/15261.10	% SZS status GaveUp for HL405888+4.p
111994.70/15261.10	eprover: CPU time limit exceeded, terminating
111994.70/15261.10	% SZS status Ended for HL405888+4.p
112012.80/15263.43	% SZS status Started for HL405890+5.p
112012.80/15263.43	% SZS status GaveUp for HL405890+5.p
112012.80/15263.43	% SZS status Ended for HL405890+5.p
112017.08/15263.97	% SZS status Started for HL405891+5.p
112017.08/15263.97	% SZS status GaveUp for HL405891+5.p
112017.08/15263.97	% SZS status Ended for HL405891+5.p
112017.57/15264.07	% SZS status Started for HL405890+4.p
112017.57/15264.07	% SZS status GaveUp for HL405890+4.p
112017.57/15264.07	eprover: CPU time limit exceeded, terminating
112017.57/15264.07	% SZS status Ended for HL405890+4.p
112023.99/15264.82	% SZS status Started for HL405893+5.p
112023.99/15264.82	% SZS status GaveUp for HL405893+5.p
112023.99/15264.82	% SZS status Ended for HL405893+5.p
112026.79/15265.27	% SZS status Started for HL405891+4.p
112026.79/15265.27	% SZS status GaveUp for HL405891+4.p
112026.79/15265.27	eprover: CPU time limit exceeded, terminating
112026.79/15265.27	% SZS status Ended for HL405891+4.p
112027.01/15265.34	% SZS status Started for HL405893+4.p
112027.01/15265.34	% SZS status GaveUp for HL405893+4.p
112027.01/15265.34	eprover: CPU time limit exceeded, terminating
112027.01/15265.34	% SZS status Ended for HL405893+4.p
112071.92/15270.83	% SZS status Started for HL405894+5.p
112071.92/15270.83	% SZS status GaveUp for HL405894+5.p
112071.92/15270.83	% SZS status Ended for HL405894+5.p
112072.15/15270.93	% SZS status Started for HL405894+4.p
112072.15/15270.93	% SZS status GaveUp for HL405894+4.p
112072.15/15270.93	eprover: CPU time limit exceeded, terminating
112072.15/15270.93	% SZS status Ended for HL405894+4.p
112092.86/15273.52	% SZS status Started for HL405895+5.p
112092.86/15273.52	% SZS status GaveUp for HL405895+5.p
112092.86/15273.52	% SZS status Ended for HL405895+5.p
112095.65/15273.87	% SZS status Started for HL405895+4.p
112095.65/15273.87	% SZS status GaveUp for HL405895+4.p
112095.65/15273.87	eprover: CPU time limit exceeded, terminating
112095.65/15273.87	% SZS status Ended for HL405895+4.p
112099.11/15274.25	% SZS status Started for HL405897+4.p
112099.11/15274.25	% SZS status GaveUp for HL405897+4.p
112099.11/15274.25	eprover: CPU time limit exceeded, terminating
112099.11/15274.25	% SZS status Ended for HL405897+4.p
112100.99/15274.54	% SZS status Started for HL405897+5.p
112100.99/15274.54	% SZS status GaveUp for HL405897+5.p
112100.99/15274.54	% SZS status Ended for HL405897+5.p
112105.25/15275.05	% SZS status Started for HL405898+5.p
112105.25/15275.05	% SZS status GaveUp for HL405898+5.p
112105.25/15275.05	% SZS status Ended for HL405898+5.p
112111.93/15275.85	% SZS status Started for HL405898+4.p
112111.93/15275.85	% SZS status GaveUp for HL405898+4.p
112111.93/15275.85	eprover: CPU time limit exceeded, terminating
112111.93/15275.85	% SZS status Ended for HL405898+4.p
112147.99/15280.47	% SZS status Started for HL405899+5.p
112147.99/15280.47	% SZS status GaveUp for HL405899+5.p
112147.99/15280.47	% SZS status Ended for HL405899+5.p
112153.02/15281.11	% SZS status Started for HL405899+4.p
112153.02/15281.11	% SZS status GaveUp for HL405899+4.p
112153.02/15281.11	eprover: CPU time limit exceeded, terminating
112153.02/15281.11	% SZS status Ended for HL405899+4.p
112173.01/15283.53	% SZS status Started for HL405900+5.p
112173.01/15283.53	% SZS status GaveUp for HL405900+5.p
112173.01/15283.53	% SZS status Ended for HL405900+5.p
112174.36/15283.81	% SZS status Started for HL405900+4.p
112174.36/15283.81	% SZS status GaveUp for HL405900+4.p
112174.36/15283.81	eprover: CPU time limit exceeded, terminating
112174.36/15283.81	% SZS status Ended for HL405900+4.p
112177.91/15284.15	% SZS status Started for HL405901+5.p
112177.91/15284.15	% SZS status GaveUp for HL405901+5.p
112177.91/15284.15	% SZS status Ended for HL405901+5.p
112179.83/15284.54	% SZS status Started for HL405901+4.p
112179.83/15284.54	% SZS status GaveUp for HL405901+4.p
112179.83/15284.54	eprover: CPU time limit exceeded, terminating
112179.83/15284.54	% SZS status Ended for HL405901+4.p
112186.86/15285.30	% SZS status Started for HL405902+4.p
112186.86/15285.30	% SZS status GaveUp for HL405902+4.p
112186.86/15285.30	eprover: CPU time limit exceeded, terminating
112186.86/15285.30	% SZS status Ended for HL405902+4.p
112187.50/15285.42	% SZS status Started for HL405902+5.p
112187.50/15285.42	% SZS status GaveUp for HL405902+5.p
112187.50/15285.42	% SZS status Ended for HL405902+5.p
112229.49/15290.68	% SZS status Started for HL405903+5.p
112229.49/15290.68	% SZS status GaveUp for HL405903+5.p
112229.49/15290.68	% SZS status Ended for HL405903+5.p
112234.21/15291.28	% SZS status Started for HL405903+4.p
112234.21/15291.28	% SZS status GaveUp for HL405903+4.p
112234.21/15291.28	eprover: CPU time limit exceeded, terminating
112234.21/15291.28	% SZS status Ended for HL405903+4.p
112251.23/15293.40	% SZS status Started for HL405904+5.p
112251.23/15293.40	% SZS status GaveUp for HL405904+5.p
112251.23/15293.40	% SZS status Ended for HL405904+5.p
112253.06/15293.78	% SZS status Started for HL405904+4.p
112253.06/15293.78	% SZS status GaveUp for HL405904+4.p
112253.06/15293.78	eprover: CPU time limit exceeded, terminating
112253.06/15293.78	% SZS status Ended for HL405904+4.p
112257.22/15294.18	% SZS status Started for HL405905+5.p
112257.22/15294.18	% SZS status GaveUp for HL405905+5.p
112257.22/15294.18	% SZS status Ended for HL405905+5.p
112260.57/15294.65	% SZS status Started for HL405905+4.p
112260.57/15294.65	% SZS status GaveUp for HL405905+4.p
112260.57/15294.65	eprover: CPU time limit exceeded, terminating
112260.57/15294.65	% SZS status Ended for HL405905+4.p
112266.05/15295.29	% SZS status Started for HL405908+5.p
112266.05/15295.29	% SZS status GaveUp for HL405908+5.p
112266.05/15295.29	% SZS status Ended for HL405908+5.p
112267.19/15295.56	% SZS status Started for HL405908+4.p
112267.19/15295.56	% SZS status GaveUp for HL405908+4.p
112267.19/15295.56	eprover: CPU time limit exceeded, terminating
112267.19/15295.56	% SZS status Ended for HL405908+4.p
112310.29/15300.93	% SZS status Started for HL405909+5.p
112310.29/15300.93	% SZS status GaveUp for HL405909+5.p
112310.29/15300.93	% SZS status Ended for HL405909+5.p
112315.82/15301.63	% SZS status Started for HL405909+4.p
112315.82/15301.63	% SZS status GaveUp for HL405909+4.p
112315.82/15301.63	eprover: CPU time limit exceeded, terminating
112315.82/15301.63	% SZS status Ended for HL405909+4.p
112329.78/15303.40	% SZS status Started for HL405910+5.p
112329.78/15303.40	% SZS status GaveUp for HL405910+5.p
112329.78/15303.40	% SZS status Ended for HL405910+5.p
112334.02/15303.87	% SZS status Started for HL405910+4.p
112334.02/15303.87	% SZS status GaveUp for HL405910+4.p
112334.02/15303.87	eprover: CPU time limit exceeded, terminating
112334.02/15303.87	% SZS status Ended for HL405910+4.p
112337.62/15304.35	% SZS status Started for HL405911+5.p
112337.62/15304.35	% SZS status GaveUp for HL405911+5.p
112337.62/15304.35	% SZS status Ended for HL405911+5.p
112340.51/15304.67	% SZS status Started for HL405911+4.p
112340.51/15304.67	% SZS status GaveUp for HL405911+4.p
112340.51/15304.67	eprover: CPU time limit exceeded, terminating
112340.51/15304.67	% SZS status Ended for HL405911+4.p
112343.54/15305.18	% SZS status Started for HL405912+5.p
112343.54/15305.18	% SZS status GaveUp for HL405912+5.p
112343.54/15305.18	% SZS status Ended for HL405912+5.p
112349.59/15305.81	% SZS status Started for HL405912+4.p
112349.59/15305.81	% SZS status GaveUp for HL405912+4.p
112349.59/15305.81	eprover: CPU time limit exceeded, terminating
112349.59/15305.81	% SZS status Ended for HL405912+4.p
112392.21/15311.19	% SZS status Started for HL405913+5.p
112392.21/15311.19	% SZS status GaveUp for HL405913+5.p
112392.21/15311.19	% SZS status Ended for HL405913+5.p
112392.70/15311.26	% SZS status Started for HL405913+4.p
112392.70/15311.26	% SZS status GaveUp for HL405913+4.p
112392.70/15311.26	eprover: CPU time limit exceeded, terminating
112392.70/15311.26	% SZS status Ended for HL405913+4.p
112410.40/15313.50	% SZS status Started for HL405914+5.p
112410.40/15313.50	% SZS status GaveUp for HL405914+5.p
112410.40/15313.50	% SZS status Ended for HL405914+5.p
112410.77/15313.62	% SZS status Started for HL405914+4.p
112410.77/15313.62	% SZS status GaveUp for HL405914+4.p
112410.77/15313.62	eprover: CPU time limit exceeded, terminating
112410.77/15313.62	% SZS status Ended for HL405914+4.p
112418.29/15314.50	% SZS status Started for HL405915+5.p
112418.29/15314.50	% SZS status GaveUp for HL405915+5.p
112418.29/15314.50	% SZS status Ended for HL405915+5.p
112419.14/15314.56	% SZS status Started for HL405915+4.p
112419.14/15314.56	% SZS status GaveUp for HL405915+4.p
112419.14/15314.56	eprover: CPU time limit exceeded, terminating
112419.14/15314.56	% SZS status Ended for HL405915+4.p
112426.30/15315.48	% SZS status Started for HL405916+4.p
112426.30/15315.48	% SZS status GaveUp for HL405916+4.p
112426.30/15315.48	eprover: CPU time limit exceeded, terminating
112426.30/15315.48	% SZS status Ended for HL405916+4.p
112426.30/15315.50	% SZS status Started for HL405916+5.p
112426.30/15315.50	% SZS status GaveUp for HL405916+5.p
112426.30/15315.50	% SZS status Ended for HL405916+5.p
112469.45/15320.89	% SZS status Started for HL405917+5.p
112469.45/15320.89	% SZS status GaveUp for HL405917+5.p
112469.45/15320.89	% SZS status Ended for HL405917+5.p
112473.63/15321.47	% SZS status Started for HL405917+4.p
112473.63/15321.47	% SZS status GaveUp for HL405917+4.p
112473.63/15321.47	eprover: CPU time limit exceeded, terminating
112473.63/15321.47	% SZS status Ended for HL405917+4.p
112488.03/15323.24	% SZS status Started for HL405918+5.p
112488.03/15323.24	% SZS status GaveUp for HL405918+5.p
112488.03/15323.24	% SZS status Ended for HL405918+5.p
112492.38/15323.81	% SZS status Started for HL405918+4.p
112492.38/15323.81	% SZS status GaveUp for HL405918+4.p
112492.38/15323.81	eprover: CPU time limit exceeded, terminating
112492.38/15323.81	% SZS status Ended for HL405918+4.p
112495.33/15324.17	% SZS status Started for HL405920+5.p
112495.33/15324.17	% SZS status GaveUp for HL405920+5.p
112495.33/15324.17	% SZS status Ended for HL405920+5.p
112502.68/15325.10	% SZS status Started for HL405921+5.p
112502.68/15325.10	% SZS status GaveUp for HL405921+5.p
112502.68/15325.10	% SZS status Ended for HL405921+5.p
112505.98/15325.48	% SZS status Started for HL405920+4.p
112505.98/15325.48	% SZS status GaveUp for HL405920+4.p
112505.98/15325.48	eprover: CPU time limit exceeded, terminating
112505.98/15325.48	% SZS status Ended for HL405920+4.p
112510.12/15326.04	% SZS status Started for HL405921+4.p
112510.12/15326.04	% SZS status GaveUp for HL405921+4.p
112510.12/15326.04	eprover: CPU time limit exceeded, terminating
112510.12/15326.04	% SZS status Ended for HL405921+4.p
112550.84/15331.17	% SZS status Started for HL405922+5.p
112550.84/15331.17	% SZS status GaveUp for HL405922+5.p
112550.84/15331.17	% SZS status Ended for HL405922+5.p
112551.84/15331.32	% SZS status Started for HL405922+4.p
112551.84/15331.32	% SZS status GaveUp for HL405922+4.p
112551.84/15331.32	eprover: CPU time limit exceeded, terminating
112551.84/15331.32	% SZS status Ended for HL405922+4.p
112569.34/15333.47	% SZS status Started for HL405923+5.p
112569.34/15333.47	% SZS status GaveUp for HL405923+5.p
112569.34/15333.47	% SZS status Ended for HL405923+5.p
112574.11/15334.12	% SZS status Started for HL405923+4.p
112574.11/15334.12	% SZS status GaveUp for HL405923+4.p
112574.11/15334.12	eprover: CPU time limit exceeded, terminating
112574.11/15334.12	% SZS status Ended for HL405923+4.p
112576.61/15334.44	% SZS status Started for HL405924+4.p
112576.61/15334.44	% SZS status GaveUp for HL405924+4.p
112576.61/15334.44	eprover: CPU time limit exceeded, terminating
112576.61/15334.44	% SZS status Ended for HL405924+4.p
112577.30/15334.65	% SZS status Started for HL405924+5.p
112577.30/15334.65	% SZS status GaveUp for HL405924+5.p
112577.30/15334.65	% SZS status Ended for HL405924+5.p
112586.70/15335.73	% SZS status Started for HL405925+5.p
112586.70/15335.73	% SZS status GaveUp for HL405925+5.p
112586.70/15335.73	% SZS status Ended for HL405925+5.p
112590.55/15336.14	% SZS status Started for HL405925+4.p
112590.55/15336.14	% SZS status GaveUp for HL405925+4.p
112590.55/15336.14	eprover: CPU time limit exceeded, terminating
112590.55/15336.14	% SZS status Ended for HL405925+4.p
112628.73/15340.92	% SZS status Started for HL405926+5.p
112628.73/15340.92	% SZS status GaveUp for HL405926+5.p
112628.73/15340.92	% SZS status Ended for HL405926+5.p
112631.45/15341.45	% SZS status Started for HL405926+4.p
112631.45/15341.45	% SZS status GaveUp for HL405926+4.p
112631.45/15341.45	eprover: CPU time limit exceeded, terminating
112631.45/15341.45	% SZS status Ended for HL405926+4.p
112649.73/15343.72	% SZS status Started for HL405927+4.p
112649.73/15343.72	% SZS status GaveUp for HL405927+4.p
112649.73/15343.72	eprover: CPU time limit exceeded, terminating
112649.73/15343.72	% SZS status Ended for HL405927+4.p
112649.73/15343.72	% SZS status Started for HL405927+5.p
112649.73/15343.72	% SZS status GaveUp for HL405927+5.p
112649.73/15343.72	% SZS status Ended for HL405927+5.p
112656.32/15344.46	% SZS status Started for HL405928+5.p
112656.32/15344.46	% SZS status GaveUp for HL405928+5.p
112656.32/15344.46	% SZS status Ended for HL405928+5.p
112663.69/15345.37	% SZS status Started for HL405928+4.p
112663.69/15345.37	% SZS status GaveUp for HL405928+4.p
112663.69/15345.37	eprover: CPU time limit exceeded, terminating
112663.69/15345.37	% SZS status Ended for HL405928+4.p
112666.06/15345.74	% SZS status Started for HL405929+5.p
112666.06/15345.74	% SZS status GaveUp for HL405929+5.p
112666.06/15345.74	% SZS status Ended for HL405929+5.p
112668.22/15345.98	% SZS status Started for HL405929+4.p
112668.22/15345.98	% SZS status GaveUp for HL405929+4.p
112668.22/15345.98	eprover: CPU time limit exceeded, terminating
112668.22/15345.98	% SZS status Ended for HL405929+4.p
112708.34/15351.04	% SZS status Started for HL405930+5.p
112708.34/15351.04	% SZS status GaveUp for HL405930+5.p
112708.34/15351.04	% SZS status Ended for HL405930+5.p
112711.70/15351.41	% SZS status Started for HL405930+4.p
112711.70/15351.41	% SZS status GaveUp for HL405930+4.p
112711.70/15351.41	eprover: CPU time limit exceeded, terminating
112711.70/15351.41	% SZS status Ended for HL405930+4.p
112728.77/15353.69	% SZS status Started for HL405931+5.p
112728.77/15353.69	% SZS status GaveUp for HL405931+5.p
112728.77/15353.69	% SZS status Ended for HL405931+5.p
112730.51/15354.06	% SZS status Started for HL405931+4.p
112730.51/15354.06	% SZS status GaveUp for HL405931+4.p
112730.51/15354.06	eprover: CPU time limit exceeded, terminating
112730.51/15354.06	% SZS status Ended for HL405931+4.p
112738.24/15354.73	% SZS status Started for HL405932+4.p
112738.24/15354.73	% SZS status GaveUp for HL405932+4.p
112738.24/15354.73	eprover: CPU time limit exceeded, terminating
112738.24/15354.73	% SZS status Ended for HL405932+4.p
112739.20/15354.94	% SZS status Started for HL405932+5.p
112739.20/15354.94	% SZS status GaveUp for HL405932+5.p
112739.20/15354.94	% SZS status Ended for HL405932+5.p
112745.66/15355.79	% SZS status Started for HL405933+5.p
112745.66/15355.79	% SZS status GaveUp for HL405933+5.p
112745.66/15355.79	% SZS status Ended for HL405933+5.p
112748.39/15356.11	% SZS status Started for HL405933+4.p
112748.39/15356.11	% SZS status GaveUp for HL405933+4.p
112748.39/15356.11	eprover: CPU time limit exceeded, terminating
112748.39/15356.11	% SZS status Ended for HL405933+4.p
112787.96/15361.09	% SZS status Started for HL405935+5.p
112787.96/15361.09	% SZS status GaveUp for HL405935+5.p
112787.96/15361.09	% SZS status Ended for HL405935+5.p
112788.90/15361.31	% SZS status Started for HL405935+4.p
112788.90/15361.31	% SZS status GaveUp for HL405935+4.p
112788.90/15361.31	eprover: CPU time limit exceeded, terminating
112788.90/15361.31	% SZS status Ended for HL405935+4.p
112809.03/15363.74	% SZS status Started for HL405936+5.p
112809.03/15363.74	% SZS status GaveUp for HL405936+5.p
112809.03/15363.74	% SZS status Ended for HL405936+5.p
112811.20/15363.97	% SZS status Started for HL405936+4.p
112811.20/15363.97	% SZS status GaveUp for HL405936+4.p
112811.20/15363.97	eprover: CPU time limit exceeded, terminating
112811.20/15363.97	% SZS status Ended for HL405936+4.p
112813.83/15364.47	% SZS status Started for HL405937+5.p
112813.83/15364.47	% SZS status GaveUp for HL405937+5.p
112813.83/15364.47	% SZS status Ended for HL405937+5.p
112819.20/15365.01	% SZS status Started for HL405937+4.p
112819.20/15365.01	% SZS status GaveUp for HL405937+4.p
112819.20/15365.01	eprover: CPU time limit exceeded, terminating
112819.20/15365.01	% SZS status Ended for HL405937+4.p
112825.78/15365.75	% SZS status Started for HL405938+5.p
112825.78/15365.75	% SZS status GaveUp for HL405938+5.p
112825.78/15365.75	% SZS status Ended for HL405938+5.p
112827.46/15366.02	% SZS status Started for HL405938+4.p
112827.46/15366.02	% SZS status GaveUp for HL405938+4.p
112827.46/15366.02	eprover: CPU time limit exceeded, terminating
112827.46/15366.02	% SZS status Ended for HL405938+4.p
112864.15/15370.68	% SZS status Started for HL405939+5.p
112864.15/15370.68	% SZS status GaveUp for HL405939+5.p
112864.15/15370.68	% SZS status Ended for HL405939+5.p
112871.30/15371.52	% SZS status Started for HL405939+4.p
112871.30/15371.52	% SZS status GaveUp for HL405939+4.p
112871.30/15371.52	eprover: CPU time limit exceeded, terminating
112871.30/15371.52	% SZS status Ended for HL405939+4.p
112887.80/15373.64	% SZS status Started for HL405940+5.p
112887.80/15373.64	% SZS status GaveUp for HL405940+5.p
112887.80/15373.64	% SZS status Ended for HL405940+5.p
112891.16/15374.08	% SZS status Started for HL405940+4.p
112891.16/15374.08	% SZS status GaveUp for HL405940+4.p
112891.16/15374.08	eprover: CPU time limit exceeded, terminating
112891.16/15374.08	% SZS status Ended for HL405940+4.p
112895.97/15374.64	% SZS status Started for HL405941+5.p
112895.97/15374.64	% SZS status GaveUp for HL405941+5.p
112895.97/15374.64	% SZS status Ended for HL405941+5.p
112896.78/15374.71	% SZS status Started for HL405941+4.p
112896.78/15374.71	% SZS status GaveUp for HL405941+4.p
112896.78/15374.71	eprover: CPU time limit exceeded, terminating
112896.78/15374.71	% SZS status Ended for HL405941+4.p
112903.13/15375.65	% SZS status Started for HL405942+5.p
112903.13/15375.65	% SZS status GaveUp for HL405942+5.p
112903.13/15375.65	% SZS status Ended for HL405942+5.p
112908.46/15376.28	% SZS status Started for HL405942+4.p
112908.46/15376.28	% SZS status GaveUp for HL405942+4.p
112908.46/15376.28	eprover: CPU time limit exceeded, terminating
112908.46/15376.28	% SZS status Ended for HL405942+4.p
112947.02/15381.08	% SZS status Started for HL405943+5.p
112947.02/15381.08	% SZS status GaveUp for HL405943+5.p
112947.02/15381.08	% SZS status Ended for HL405943+5.p
112947.51/15381.13	% SZS status Started for HL405944+5.p
112947.51/15381.13	% SZS status Theorem for HL405944+5.p
112947.51/15381.13	% SZS status Ended for HL405944+5.p
112948.41/15381.25	% SZS status Started for HL405943+4.p
112948.41/15381.25	% SZS status GaveUp for HL405943+4.p
112948.41/15381.25	eprover: CPU time limit exceeded, terminating
112948.41/15381.25	% SZS status Ended for HL405943+4.p
112962.91/15383.18	% SZS status Started for HL405946+5.p
112962.91/15383.18	% SZS status Theorem for HL405946+5.p
112962.91/15383.18	% SZS status Ended for HL405946+5.p
112971.11/15384.07	% SZS status Started for HL405944+4.p
112971.11/15384.07	% SZS status GaveUp for HL405944+4.p
112971.11/15384.07	eprover: CPU time limit exceeded, terminating
112971.11/15384.07	% SZS status Ended for HL405944+4.p
112975.02/15384.56	% SZS status Started for HL405945+5.p
112975.02/15384.56	% SZS status GaveUp for HL405945+5.p
112975.02/15384.56	% SZS status Ended for HL405945+5.p
112976.56/15384.87	% SZS status Started for HL405945+4.p
112976.56/15384.87	% SZS status GaveUp for HL405945+4.p
112976.56/15384.87	eprover: CPU time limit exceeded, terminating
112976.56/15384.87	% SZS status Ended for HL405945+4.p
112985.18/15385.89	% SZS status Started for HL405946+4.p
112985.18/15385.89	% SZS status GaveUp for HL405946+4.p
112985.18/15385.89	eprover: CPU time limit exceeded, terminating
112985.18/15385.89	% SZS status Ended for HL405946+4.p
113017.99/15390.00	% SZS status Started for HL405949+5.p
113017.99/15390.00	% SZS status Theorem for HL405949+5.p
113017.99/15390.00	% SZS status Ended for HL405949+5.p
113024.11/15390.81	% SZS status Started for HL405948+5.p
113024.11/15390.81	% SZS status GaveUp for HL405948+5.p
113024.11/15390.81	% SZS status Ended for HL405948+5.p
113028.27/15391.33	% SZS status Started for HL405948+4.p
113028.27/15391.33	% SZS status GaveUp for HL405948+4.p
113028.27/15391.33	eprover: CPU time limit exceeded, terminating
113028.27/15391.33	% SZS status Ended for HL405948+4.p
113031.07/15391.65	% SZS status Started for HL405949+4.p
113031.07/15391.65	% SZS status GaveUp for HL405949+4.p
113031.07/15391.65	eprover: CPU time limit exceeded, terminating
113031.07/15391.65	% SZS status Ended for HL405949+4.p
113039.80/15392.74	% SZS status Started for HL405951+5.p
113039.80/15392.74	% SZS status Theorem for HL405951+5.p
113039.80/15392.74	% SZS status Ended for HL405951+5.p
113051.07/15394.18	% SZS status Started for HL405950+5.p
113051.07/15394.18	% SZS status GaveUp for HL405950+5.p
113051.07/15394.18	% SZS status Ended for HL405950+5.p
113053.52/15394.46	% SZS status Started for HL405950+4.p
113053.52/15394.46	% SZS status GaveUp for HL405950+4.p
113053.52/15394.46	eprover: CPU time limit exceeded, terminating
113053.52/15394.46	% SZS status Ended for HL405950+4.p
113059.25/15395.26	% SZS status Started for HL405951+4.p
113059.25/15395.26	% SZS status GaveUp for HL405951+4.p
113059.25/15395.26	eprover: CPU time limit exceeded, terminating
113059.25/15395.26	% SZS status Ended for HL405951+4.p
113098.71/15400.24	% SZS status Started for HL405952+4.p
113098.71/15400.24	% SZS status GaveUp for HL405952+4.p
113098.71/15400.24	eprover: CPU time limit exceeded, terminating
113098.71/15400.24	% SZS status Ended for HL405952+4.p
113100.43/15400.37	% SZS status Started for HL405952+5.p
113100.43/15400.37	% SZS status GaveUp for HL405952+5.p
113100.43/15400.37	% SZS status Ended for HL405952+5.p
113106.83/15401.24	% SZS status Started for HL405954+5.p
113106.83/15401.24	% SZS status Theorem for HL405954+5.p
113106.83/15401.24	% SZS status Ended for HL405954+5.p
113111.27/15401.74	% SZS status Started for HL405953+4.p
113111.27/15401.74	% SZS status GaveUp for HL405953+4.p
113111.27/15401.74	eprover: CPU time limit exceeded, terminating
113111.27/15401.74	% SZS status Ended for HL405953+4.p
113111.27/15401.75	% SZS status Started for HL405953+5.p
113111.27/15401.75	% SZS status GaveUp for HL405953+5.p
113111.27/15401.75	% SZS status Ended for HL405953+5.p
113120.87/15403.00	% SZS status Started for HL405954+4.p
113120.87/15403.00	% SZS status GaveUp for HL405954+4.p
113120.87/15403.00	eprover: CPU time limit exceeded, terminating
113120.87/15403.00	% SZS status Ended for HL405954+4.p
113134.57/15404.73	% SZS status Started for HL405955+4.p
113134.57/15404.73	% SZS status GaveUp for HL405955+4.p
113134.57/15404.73	eprover: CPU time limit exceeded, terminating
113134.57/15404.73	% SZS status Ended for HL405955+4.p
113138.88/15405.32	% SZS status Started for HL405955+5.p
113138.88/15405.32	% SZS status GaveUp for HL405955+5.p
113138.88/15405.32	% SZS status Ended for HL405955+5.p
113177.64/15410.15	% SZS status Started for HL405957+5.p
113177.64/15410.15	% SZS status GaveUp for HL405957+5.p
113177.64/15410.15	% SZS status Ended for HL405957+5.p
113180.73/15410.50	% SZS status Started for HL405957+4.p
113180.73/15410.50	% SZS status GaveUp for HL405957+4.p
113180.73/15410.50	eprover: CPU time limit exceeded, terminating
113180.73/15410.50	% SZS status Ended for HL405957+4.p
113188.92/15411.52	% SZS status Started for HL405958+5.p
113188.92/15411.52	% SZS status GaveUp for HL405958+5.p
113188.92/15411.52	% SZS status Ended for HL405958+5.p
113190.15/15411.67	% SZS status Started for HL405958+4.p
113190.15/15411.67	% SZS status GaveUp for HL405958+4.p
113190.15/15411.67	eprover: CPU time limit exceeded, terminating
113190.15/15411.67	% SZS status Ended for HL405958+4.p
113192.30/15412.05	% SZS status Started for HL405959+4.p
113192.30/15412.05	% SZS status GaveUp for HL405959+4.p
113192.30/15412.05	eprover: CPU time limit exceeded, terminating
113192.30/15412.05	% SZS status Ended for HL405959+4.p
113193.27/15412.18	% SZS status Started for HL405960+5.p
113193.27/15412.18	% SZS status Theorem for HL405960+5.p
113193.27/15412.18	% SZS status Ended for HL405960+5.p
113195.95/15412.40	% SZS status Started for HL405959+5.p
113195.95/15412.40	% SZS status GaveUp for HL405959+5.p
113195.95/15412.40	% SZS status Ended for HL405959+5.p
113204.94/15413.53	% SZS status Started for HL405963+5.p
113204.94/15413.53	% SZS status Theorem for HL405963+5.p
113204.94/15413.53	% SZS status Ended for HL405963+5.p
113216.90/15415.03	% SZS status Started for HL405960+4.p
113216.90/15415.03	% SZS status GaveUp for HL405960+4.p
113216.90/15415.03	eprover: CPU time limit exceeded, terminating
113216.90/15415.03	% SZS status Ended for HL405960+4.p
113222.09/15415.73	% SZS status Started for HL405964+5.p
113222.09/15415.73	% SZS status Theorem for HL405964+5.p
113222.09/15415.73	% SZS status Ended for HL405964+5.p
113235.91/15417.45	% SZS status Started for HL405961+5.p
113235.91/15417.45	% SZS status Theorem for HL405961+5.p
113235.91/15417.45	% SZS status Ended for HL405961+5.p
113239.79/15417.90	% SZS status Started for HL405965+5.p
113239.79/15417.90	% SZS status Theorem for HL405965+5.p
113239.79/15417.90	% SZS status Ended for HL405965+5.p
113250.34/15419.29	% SZS status Started for HL405966+5.p
113250.34/15419.29	% SZS status Theorem for HL405966+5.p
113250.34/15419.29	% SZS status Ended for HL405966+5.p
113259.55/15420.39	% SZS status Started for HL405961+4.p
113259.55/15420.39	% SZS status GaveUp for HL405961+4.p
113259.55/15420.39	eprover: CPU time limit exceeded, terminating
113259.55/15420.39	% SZS status Ended for HL405961+4.p
113263.98/15421.06	% SZS status Started for HL405962+5.p
113263.98/15421.06	% SZS status GaveUp for HL405962+5.p
113263.98/15421.06	% SZS status Ended for HL405962+5.p
113270.20/15421.86	% SZS status Started for HL405962+4.p
113270.20/15421.86	% SZS status GaveUp for HL405962+4.p
113270.20/15421.86	eprover: CPU time limit exceeded, terminating
113270.20/15421.86	% SZS status Ended for HL405962+4.p
113274.60/15422.37	% SZS status Started for HL405963+4.p
113274.60/15422.37	% SZS status GaveUp for HL405963+4.p
113274.60/15422.37	eprover: CPU time limit exceeded, terminating
113274.60/15422.37	% SZS status Ended for HL405963+4.p
113275.27/15422.48	% SZS status Started for HL405967+5.p
113275.27/15422.48	% SZS status Theorem for HL405967+5.p
113275.27/15422.48	% SZS status Ended for HL405967+5.p
113276.23/15422.65	% SZS status Started for HL405964+4.p
113276.23/15422.65	% SZS status GaveUp for HL405964+4.p
113276.23/15422.65	eprover: CPU time limit exceeded, terminating
113276.23/15422.65	% SZS status Ended for HL405964+4.p
113288.90/15424.06	% SZS status Started for HL405968+5.p
113288.90/15424.06	% SZS status Theorem for HL405968+5.p
113288.90/15424.06	% SZS status Ended for HL405968+5.p
113288.90/15424.10	% SZS status Started for HL405968+4.p
113288.90/15424.10	% SZS status GaveUp for HL405968+4.p
113288.90/15424.10	eprover: CPU time limit exceeded, terminating
113288.90/15424.10	% SZS status Ended for HL405968+4.p
113298.59/15425.37	% SZS status Started for HL405965+4.p
113298.59/15425.37	% SZS status GaveUp for HL405965+4.p
113298.59/15425.37	eprover: CPU time limit exceeded, terminating
113298.59/15425.37	% SZS status Ended for HL405965+4.p
113299.25/15425.41	% SZS status Started for HL405969+4.p
113299.25/15425.41	% SZS status GaveUp for HL405969+4.p
113299.25/15425.41	eprover: CPU time limit exceeded, terminating
113299.25/15425.41	% SZS status Ended for HL405969+4.p
113300.21/15425.70	% SZS status Started for HL405970+4.p
113300.21/15425.70	% SZS status GaveUp for HL405970+4.p
113300.21/15425.70	eprover: CPU time limit exceeded, terminating
113300.21/15425.70	% SZS status Ended for HL405970+4.p
113312.91/15427.20	% SZS status Started for HL405971+4.p
113312.91/15427.20	% SZS status GaveUp for HL405971+4.p
113312.91/15427.20	eprover: CPU time limit exceeded, terminating
113312.91/15427.20	% SZS status Ended for HL405971+4.p
113313.95/15427.37	% SZS status Started for HL405971+5.p
113313.95/15427.37	% SZS status Theorem for HL405971+5.p
113313.95/15427.37	% SZS status Ended for HL405971+5.p
113318.34/15427.84	% SZS status Started for HL405966+4.p
113318.34/15427.84	% SZS status GaveUp for HL405966+4.p
113318.34/15427.84	eprover: CPU time limit exceeded, terminating
113318.34/15427.84	% SZS status Ended for HL405966+4.p
113323.12/15428.45	% SZS status Started for HL405973+4.p
113323.12/15428.45	% SZS status GaveUp for HL405973+4.p
113323.12/15428.45	eprover: CPU time limit exceeded, terminating
113323.12/15428.45	% SZS status Ended for HL405973+4.p
113337.07/15430.16	% SZS status Started for HL405967+4.p
113337.07/15430.16	% SZS status GaveUp for HL405967+4.p
113337.07/15430.16	eprover: CPU time limit exceeded, terminating
113337.07/15430.16	% SZS status Ended for HL405967+4.p
113337.87/15430.24	% SZS status Started for HL405974+4.p
113337.87/15430.24	% SZS status GaveUp for HL405974+4.p
113337.87/15430.24	eprover: CPU time limit exceeded, terminating
113337.87/15430.24	% SZS status Ended for HL405974+4.p
113342.82/15430.91	% SZS status Started for HL405975+4.p
113342.82/15430.91	% SZS status GaveUp for HL405975+4.p
113342.82/15430.91	eprover: CPU time limit exceeded, terminating
113342.82/15430.91	% SZS status Ended for HL405975+4.p
113349.77/15431.73	% SZS status Started for HL405970+5.p
113349.77/15431.73	% SZS status Theorem for HL405970+5.p
113349.77/15431.73	% SZS status Ended for HL405970+5.p
113357.74/15432.78	% SZS status Started for HL405969+5.p
113357.74/15432.78	% SZS status GaveUp for HL405969+5.p
113357.74/15432.78	% SZS status Ended for HL405969+5.p
113360.45/15433.22	% SZS status Started for HL405973+5.p
113360.45/15433.22	% SZS status Theorem for HL405973+5.p
113360.45/15433.22	% SZS status Ended for HL405973+5.p
113362.45/15433.38	% SZS status Started for HL405976+4.p
113362.45/15433.38	% SZS status GaveUp for HL405976+4.p
113362.45/15433.38	eprover: CPU time limit exceeded, terminating
113362.45/15433.38	% SZS status Ended for HL405976+4.p
113367.55/15433.94	% SZS status Started for HL405977+4.p
113367.55/15433.94	% SZS status GaveUp for HL405977+4.p
113367.55/15433.94	eprover: CPU time limit exceeded, terminating
113367.55/15433.94	% SZS status Ended for HL405977+4.p
113381.75/15435.81	% SZS status Started for HL405978+4.p
113381.75/15435.81	% SZS status GaveUp for HL405978+4.p
113381.75/15435.81	eprover: CPU time limit exceeded, terminating
113381.75/15435.81	% SZS status Ended for HL405978+4.p
113383.44/15436.05	% SZS status Started for HL405975+5.p
113383.44/15436.05	% SZS status Theorem for HL405975+5.p
113383.44/15436.05	% SZS status Ended for HL405975+5.p
113387.59/15436.53	% SZS status Started for HL405979+4.p
113387.59/15436.53	% SZS status GaveUp for HL405979+4.p
113387.59/15436.53	eprover: CPU time limit exceeded, terminating
113387.59/15436.53	% SZS status Ended for HL405979+4.p
113396.20/15437.63	% SZS status Started for HL405974+5.p
113396.20/15437.63	% SZS status GaveUp for HL405974+5.p
113396.20/15437.63	% SZS status Ended for HL405974+5.p
113398.37/15437.94	% SZS status Started for HL405976+5.p
113398.37/15437.94	% SZS status Theorem for HL405976+5.p
113398.37/15437.94	% SZS status Ended for HL405976+5.p
113406.30/15438.84	% SZS status Started for HL405980+4.p
113406.30/15438.84	% SZS status GaveUp for HL405980+4.p
113406.30/15438.84	eprover: CPU time limit exceeded, terminating
113406.30/15438.84	% SZS status Ended for HL405980+4.p
113409.58/15439.29	% SZS status Started for HL405977+5.p
113409.58/15439.29	% SZS status Theorem for HL405977+5.p
113409.58/15439.29	% SZS status Ended for HL405977+5.p
113411.91/15439.73	% SZS status Started for HL405981+4.p
113411.91/15439.73	% SZS status GaveUp for HL405981+4.p
113411.91/15439.73	eprover: CPU time limit exceeded, terminating
113411.91/15439.73	% SZS status Ended for HL405981+4.p
113420.53/15440.64	% SZS status Started for HL405978+5.p
113420.53/15440.64	% SZS status Theorem for HL405978+5.p
113420.53/15440.64	% SZS status Ended for HL405978+5.p
113422.41/15440.98	% SZS status Started for HL405982+4.p
113422.41/15440.98	% SZS status GaveUp for HL405982+4.p
113422.41/15440.98	eprover: CPU time limit exceeded, terminating
113422.41/15440.98	% SZS status Ended for HL405982+4.p
113427.06/15441.48	% SZS status Started for HL405979+5.p
113427.06/15441.48	% SZS status Theorem for HL405979+5.p
113427.06/15441.48	% SZS status Ended for HL405979+5.p
113434.98/15442.45	% SZS status Started for HL405983+4.p
113434.98/15442.45	% SZS status GaveUp for HL405983+4.p
113434.98/15442.45	eprover: CPU time limit exceeded, terminating
113434.98/15442.45	% SZS status Ended for HL405983+4.p
113443.30/15443.52	% SZS status Started for HL405980+5.p
113443.30/15443.52	% SZS status Theorem for HL405980+5.p
113443.30/15443.52	% SZS status Ended for HL405980+5.p
113444.30/15443.68	% SZS status Started for HL405984+4.p
113444.30/15443.68	% SZS status GaveUp for HL405984+4.p
113444.30/15443.68	eprover: CPU time limit exceeded, terminating
113444.30/15443.68	% SZS status Ended for HL405984+4.p
113452.22/15444.63	% SZS status Started for HL405985+4.p
113452.22/15444.63	% SZS status GaveUp for HL405985+4.p
113452.22/15444.63	eprover: CPU time limit exceeded, terminating
113452.22/15444.63	% SZS status Ended for HL405985+4.p
113458.21/15445.36	% SZS status Started for HL405981+5.p
113458.21/15445.36	% SZS status Theorem for HL405981+5.p
113458.21/15445.36	% SZS status Ended for HL405981+5.p
113465.99/15446.34	% SZS status Started for HL405982+5.p
113465.99/15446.34	% SZS status Theorem for HL405982+5.p
113465.99/15446.34	% SZS status Ended for HL405982+5.p
113467.41/15446.56	% SZS status Started for HL405987+4.p
113467.41/15446.56	% SZS status GaveUp for HL405987+4.p
113467.41/15446.56	eprover: CPU time limit exceeded, terminating
113467.41/15446.56	% SZS status Ended for HL405987+4.p
113476.32/15447.69	% SZS status Started for HL405988+4.p
113476.32/15447.69	% SZS status GaveUp for HL405988+4.p
113476.32/15447.69	eprover: CPU time limit exceeded, terminating
113476.32/15447.69	% SZS status Ended for HL405988+4.p
113489.66/15449.37	% SZS status Started for HL405989+4.p
113489.66/15449.37	% SZS status GaveUp for HL405989+4.p
113489.66/15449.37	eprover: CPU time limit exceeded, terminating
113489.66/15449.37	% SZS status Ended for HL405989+4.p
113494.48/15449.97	% SZS status Started for HL405983+5.p
113494.48/15449.97	% SZS status GaveUp for HL405983+5.p
113494.48/15449.97	% SZS status Ended for HL405983+5.p
113495.73/15450.25	% SZS status Started for HL405985+5.p
113495.73/15450.25	% SZS status Theorem for HL405985+5.p
113495.73/15450.25	% SZS status Ended for HL405985+5.p
113507.58/15450.81	% SZS status Started for HL405991+4.p
113507.58/15450.81	% SZS status GaveUp for HL405991+4.p
113507.58/15450.81	eprover: CPU time limit exceeded, terminating
113507.58/15450.81	% SZS status Ended for HL405991+4.p
113511.55/15451.23	% SZS status Started for HL405984+5.p
113511.55/15451.23	% SZS status GaveUp for HL405984+5.p
113511.55/15451.23	% SZS status Ended for HL405984+5.p
113525.45/15453.01	% SZS status Started for HL405992+4.p
113525.45/15453.01	% SZS status GaveUp for HL405992+4.p
113525.45/15453.01	eprover: CPU time limit exceeded, terminating
113525.45/15453.01	% SZS status Ended for HL405992+4.p
113532.48/15453.92	% SZS status Started for HL405993+4.p
113532.48/15453.92	% SZS status GaveUp for HL405993+4.p
113532.48/15453.92	eprover: CPU time limit exceeded, terminating
113532.48/15453.92	% SZS status Ended for HL405993+4.p
113533.14/15453.92	% SZS status Started for HL405987+5.p
113533.14/15453.92	% SZS status GaveUp for HL405987+5.p
113533.14/15453.92	% SZS status Ended for HL405987+5.p
113547.06/15455.71	% SZS status Started for HL405988+5.p
113547.06/15455.71	% SZS status GaveUp for HL405988+5.p
113547.06/15455.71	% SZS status Ended for HL405988+5.p
113549.72/15456.04	% SZS status Started for HL405994+4.p
113549.72/15456.04	% SZS status GaveUp for HL405994+4.p
113549.72/15456.04	eprover: CPU time limit exceeded, terminating
113549.72/15456.04	% SZS status Ended for HL405994+4.p
113555.99/15456.80	% SZS status Started for HL405989+5.p
113555.99/15456.80	% SZS status GaveUp for HL405989+5.p
113555.99/15456.80	% SZS status Ended for HL405989+5.p
113556.90/15456.96	% SZS status Started for HL405995+4.p
113556.90/15456.96	% SZS status GaveUp for HL405995+4.p
113556.90/15456.96	eprover: CPU time limit exceeded, terminating
113556.90/15456.96	% SZS status Ended for HL405995+4.p
113574.23/15459.08	% SZS status Started for HL405996+4.p
113574.23/15459.08	% SZS status GaveUp for HL405996+4.p
113574.23/15459.08	eprover: CPU time limit exceeded, terminating
113574.23/15459.08	% SZS status Ended for HL405996+4.p
113577.03/15459.64	% SZS status Started for HL405991+5.p
113577.03/15459.64	% SZS status GaveUp for HL405991+5.p
113577.03/15459.64	% SZS status Ended for HL405991+5.p
113580.51/15460.00	% SZS status Started for HL405997+4.p
113580.51/15460.00	% SZS status GaveUp for HL405997+4.p
113580.51/15460.00	eprover: CPU time limit exceeded, terminating
113580.51/15460.00	% SZS status Ended for HL405997+4.p
113584.68/15460.42	% SZS status Started for HL405992+5.p
113584.68/15460.42	% SZS status GaveUp for HL405992+5.p
113584.68/15460.42	% SZS status Ended for HL405992+5.p
113592.20/15461.38	% SZS status Started for HL405993+5.p
113592.20/15461.38	% SZS status GaveUp for HL405993+5.p
113592.20/15461.38	% SZS status Ended for HL405993+5.p
113603.48/15462.81	% SZS status Started for HL405998+4.p
113603.48/15462.81	% SZS status GaveUp for HL405998+4.p
113603.48/15462.81	eprover: CPU time limit exceeded, terminating
113603.48/15462.81	% SZS status Ended for HL405998+4.p
113608.71/15463.46	% SZS status Started for HL405999+4.p
113608.71/15463.46	% SZS status GaveUp for HL405999+4.p
113608.71/15463.46	eprover: CPU time limit exceeded, terminating
113608.71/15463.46	% SZS status Ended for HL405999+4.p
113617.09/15464.52	% SZS status Started for HL405994+5.p
113617.09/15464.52	% SZS status GaveUp for HL405994+5.p
113617.09/15464.52	% SZS status Ended for HL405994+5.p
113627.09/15465.85	% SZS status Started for HL406000+4.p
113627.09/15465.85	% SZS status GaveUp for HL406000+4.p
113627.09/15465.85	eprover: CPU time limit exceeded, terminating
113627.09/15465.85	% SZS status Ended for HL406000+4.p
113628.59/15465.94	% SZS status Started for HL405995+5.p
113628.59/15465.94	% SZS status GaveUp for HL405995+5.p
113628.59/15465.94	% SZS status Ended for HL405995+5.p
113637.09/15467.02	% SZS status Started for HL405996+5.p
113637.09/15467.02	% SZS status GaveUp for HL405996+5.p
113637.09/15467.02	% SZS status Ended for HL405996+5.p
113641.48/15467.56	% SZS status Started for HL406002+4.p
113641.48/15467.56	% SZS status GaveUp for HL406002+4.p
113641.48/15467.56	eprover: CPU time limit exceeded, terminating
113641.48/15467.56	% SZS status Ended for HL406002+4.p
113652.38/15468.98	% SZS status Started for HL406004+4.p
113652.38/15468.98	% SZS status GaveUp for HL406004+4.p
113652.38/15468.98	eprover: CPU time limit exceeded, terminating
113652.38/15468.98	% SZS status Ended for HL406004+4.p
113653.49/15469.24	% SZS status Started for HL405997+5.p
113653.49/15469.24	% SZS status GaveUp for HL405997+5.p
113653.49/15469.24	% SZS status Ended for HL405997+5.p
113662.11/15470.18	% SZS status Started for HL405998+5.p
113662.11/15470.18	% SZS status GaveUp for HL405998+5.p
113662.11/15470.18	% SZS status Ended for HL405998+5.p
113665.46/15470.60	% SZS status Started for HL406006+4.p
113665.46/15470.60	% SZS status GaveUp for HL406006+4.p
113665.46/15470.60	eprover: CPU time limit exceeded, terminating
113665.46/15470.60	% SZS status Ended for HL406006+4.p
113675.41/15471.91	% SZS status Started for HL405999+5.p
113675.41/15471.91	% SZS status GaveUp for HL405999+5.p
113675.41/15471.91	% SZS status Ended for HL405999+5.p
113680.08/15472.42	% SZS status Started for HL406007+4.p
113680.08/15472.42	% SZS status GaveUp for HL406007+4.p
113680.08/15472.42	eprover: CPU time limit exceeded, terminating
113680.08/15472.42	% SZS status Ended for HL406007+4.p
113688.62/15473.49	% SZS status Started for HL406002+5.p
113688.62/15473.49	% SZS status Theorem for HL406002+5.p
113688.62/15473.49	% SZS status Ended for HL406002+5.p
113689.88/15473.64	% SZS status Started for HL406008+4.p
113689.88/15473.64	% SZS status GaveUp for HL406008+4.p
113689.88/15473.64	eprover: CPU time limit exceeded, terminating
113689.88/15473.64	% SZS status Ended for HL406008+4.p
113689.88/15473.66	% SZS status Started for HL406000+5.p
113689.88/15473.66	% SZS status GaveUp for HL406000+5.p
113689.88/15473.66	% SZS status Ended for HL406000+5.p
113702.66/15475.46	% SZS status Started for HL406009+4.p
113702.66/15475.46	% SZS status GaveUp for HL406009+4.p
113702.66/15475.46	eprover: CPU time limit exceeded, terminating
113702.66/15475.46	% SZS status Ended for HL406009+4.p
113714.05/15476.67	% SZS status Started for HL406010+4.p
113714.05/15476.67	% SZS status GaveUp for HL406010+4.p
113714.05/15476.67	eprover: CPU time limit exceeded, terminating
113714.05/15476.67	% SZS status Ended for HL406010+4.p
113718.19/15477.20	% SZS status Started for HL406004+5.p
113718.19/15477.20	% SZS status GaveUp for HL406004+5.p
113718.19/15477.20	% SZS status Ended for HL406004+5.p
113728.09/15478.50	% SZS status Started for HL406011+4.p
113728.09/15478.50	% SZS status GaveUp for HL406011+4.p
113728.09/15478.50	eprover: CPU time limit exceeded, terminating
113728.09/15478.50	% SZS status Ended for HL406011+4.p
113734.17/15479.23	% SZS status Started for HL406006+5.p
113734.17/15479.23	% SZS status GaveUp for HL406006+5.p
113734.17/15479.23	% SZS status Ended for HL406006+5.p
113742.09/15480.24	% SZS status Started for HL406012+4.p
113742.09/15480.24	% SZS status GaveUp for HL406012+4.p
113742.09/15480.24	eprover: CPU time limit exceeded, terminating
113742.09/15480.24	% SZS status Ended for HL406012+4.p
113743.55/15480.39	% SZS status Started for HL406007+5.p
113743.55/15480.39	% SZS status GaveUp for HL406007+5.p
113743.55/15480.39	% SZS status Ended for HL406007+5.p
113757.88/15482.28	% SZS status Started for HL406013+4.p
113757.88/15482.28	% SZS status GaveUp for HL406013+4.p
113757.88/15482.28	eprover: CPU time limit exceeded, terminating
113757.88/15482.28	% SZS status Ended for HL406013+4.p
113758.73/15482.38	% SZS status Started for HL406008+5.p
113758.73/15482.38	% SZS status GaveUp for HL406008+5.p
113758.73/15482.38	% SZS status Ended for HL406008+5.p
113767.76/15483.43	% SZS status Started for HL406014+4.p
113767.76/15483.43	% SZS status GaveUp for HL406014+4.p
113767.76/15483.43	eprover: CPU time limit exceeded, terminating
113767.76/15483.43	% SZS status Ended for HL406014+4.p
113769.29/15483.71	% SZS status Started for HL406009+5.p
113769.29/15483.71	% SZS status GaveUp for HL406009+5.p
113769.29/15483.71	% SZS status Ended for HL406009+5.p
113771.24/15483.91	% SZS status Started for HL406010+5.p
113771.24/15483.91	% SZS status GaveUp for HL406010+5.p
113771.24/15483.91	% SZS status Ended for HL406010+5.p
113782.97/15485.42	% SZS status Started for HL406015+4.p
113782.97/15485.42	% SZS status GaveUp for HL406015+4.p
113782.97/15485.42	eprover: CPU time limit exceeded, terminating
113782.97/15485.42	% SZS status Ended for HL406015+4.p
113795.02/15486.90	% SZS status Started for HL406016+4.p
113795.02/15486.90	% SZS status GaveUp for HL406016+4.p
113795.02/15486.90	eprover: CPU time limit exceeded, terminating
113795.02/15486.90	% SZS status Ended for HL406016+4.p
113796.58/15487.09	% SZS status Started for HL406011+5.p
113796.58/15487.09	% SZS status GaveUp for HL406011+5.p
113796.58/15487.09	% SZS status Ended for HL406011+5.p
113808.36/15488.54	% SZS status Started for HL406017+4.p
113808.36/15488.54	% SZS status GaveUp for HL406017+4.p
113808.36/15488.54	eprover: CPU time limit exceeded, terminating
113808.36/15488.54	% SZS status Ended for HL406017+4.p
113808.67/15488.66	% SZS status Started for HL406012+5.p
113808.67/15488.66	% SZS status GaveUp for HL406012+5.p
113808.67/15488.66	% SZS status Ended for HL406012+5.p
113821.21/15490.17	% SZS status Started for HL406018+4.p
113821.21/15490.17	% SZS status GaveUp for HL406018+4.p
113821.21/15490.17	eprover: CPU time limit exceeded, terminating
113821.21/15490.17	% SZS status Ended for HL406018+4.p
113822.70/15490.43	% SZS status Started for HL406013+5.p
113822.70/15490.43	% SZS status GaveUp for HL406013+5.p
113822.70/15490.43	% SZS status Ended for HL406013+5.p
113833.28/15491.69	% SZS status Started for HL406019+4.p
113833.28/15491.69	% SZS status GaveUp for HL406019+4.p
113833.28/15491.69	eprover: CPU time limit exceeded, terminating
113833.28/15491.69	% SZS status Ended for HL406019+4.p
113839.42/15492.50	% SZS status Started for HL406014+5.p
113839.42/15492.50	% SZS status GaveUp for HL406014+5.p
113839.42/15492.50	% SZS status Ended for HL406014+5.p
113847.52/15493.46	% SZS status Started for HL406021+4.p
113847.52/15493.46	% SZS status GaveUp for HL406021+4.p
113847.52/15493.46	eprover: CPU time limit exceeded, terminating
113847.52/15493.46	% SZS status Ended for HL406021+4.p
113849.30/15493.82	% SZS status Started for HL406015+5.p
113849.30/15493.82	% SZS status GaveUp for HL406015+5.p
113849.30/15493.82	% SZS status Ended for HL406015+5.p
113852.53/15494.12	% SZS status Started for HL406016+5.p
113852.53/15494.12	% SZS status GaveUp for HL406016+5.p
113852.53/15494.12	% SZS status Ended for HL406016+5.p
113863.96/15495.54	% SZS status Started for HL406022+4.p
113863.96/15495.54	% SZS status GaveUp for HL406022+4.p
113863.96/15495.54	eprover: CPU time limit exceeded, terminating
113863.96/15495.54	% SZS status Ended for HL406022+4.p
113874.08/15496.85	% SZS status Started for HL406023+4.p
113874.08/15496.85	% SZS status GaveUp for HL406023+4.p
113874.08/15496.85	eprover: CPU time limit exceeded, terminating
113874.08/15496.85	% SZS status Ended for HL406023+4.p
113875.44/15497.13	% SZS status Started for HL406017+5.p
113875.44/15497.13	% SZS status GaveUp for HL406017+5.p
113875.44/15497.13	% SZS status Ended for HL406017+5.p
113887.77/15498.57	% SZS status Started for HL406024+4.p
113887.77/15498.57	% SZS status GaveUp for HL406024+4.p
113887.77/15498.57	eprover: CPU time limit exceeded, terminating
113887.77/15498.57	% SZS status Ended for HL406024+4.p
113892.20/15499.12	% SZS status Started for HL406018+5.p
113892.20/15499.12	% SZS status GaveUp for HL406018+5.p
113892.20/15499.12	% SZS status Ended for HL406018+5.p
113900.42/15500.16	% SZS status Started for HL406025+4.p
113900.42/15500.16	% SZS status GaveUp for HL406025+4.p
113900.42/15500.16	eprover: CPU time limit exceeded, terminating
113900.42/15500.16	% SZS status Ended for HL406025+4.p
113901.12/15500.33	% SZS status Started for HL406019+5.p
113901.12/15500.33	% SZS status GaveUp for HL406019+5.p
113901.12/15500.33	% SZS status Ended for HL406019+5.p
113914.02/15501.87	% SZS status Started for HL406021+5.p
113914.02/15501.87	% SZS status GaveUp for HL406021+5.p
113914.02/15501.87	% SZS status Ended for HL406021+5.p
113917.59/15502.33	% SZS status Started for HL406026+4.p
113917.59/15502.33	% SZS status GaveUp for HL406026+4.p
113917.59/15502.33	eprover: CPU time limit exceeded, terminating
113917.59/15502.33	% SZS status Ended for HL406026+4.p
113925.92/15503.37	% SZS status Started for HL406027+4.p
113925.92/15503.37	% SZS status GaveUp for HL406027+4.p
113925.92/15503.37	eprover: CPU time limit exceeded, terminating
113925.92/15503.37	% SZS status Ended for HL406027+4.p
113927.96/15503.65	% SZS status Started for HL406022+5.p
113927.96/15503.65	% SZS status GaveUp for HL406022+5.p
113927.96/15503.65	% SZS status Ended for HL406022+5.p
113932.45/15504.24	% SZS status Started for HL406023+5.p
113932.45/15504.24	% SZS status GaveUp for HL406023+5.p
113932.45/15504.24	% SZS status Ended for HL406023+5.p
113941.06/15505.43	% SZS status Started for HL406028+4.p
113941.06/15505.43	% SZS status GaveUp for HL406028+4.p
113941.06/15505.43	eprover: CPU time limit exceeded, terminating
113941.06/15505.43	% SZS status Ended for HL406028+4.p
113952.30/15506.68	% SZS status Started for HL406029+4.p
113952.30/15506.68	% SZS status GaveUp for HL406029+4.p
113952.30/15506.68	eprover: CPU time limit exceeded, terminating
113952.30/15506.68	% SZS status Ended for HL406029+4.p
113954.23/15507.07	% SZS status Started for HL406024+5.p
113954.23/15507.07	% SZS status GaveUp for HL406024+5.p
113954.23/15507.07	% SZS status Ended for HL406024+5.p
113965.52/15508.46	% SZS status Started for HL406030+4.p
113965.52/15508.46	% SZS status GaveUp for HL406030+4.p
113965.52/15508.46	eprover: CPU time limit exceeded, terminating
113965.52/15508.46	% SZS status Ended for HL406030+4.p
113968.81/15508.81	% SZS status Started for HL406025+5.p
113968.81/15508.81	% SZS status GaveUp for HL406025+5.p
113968.81/15508.81	% SZS status Ended for HL406025+5.p
113979.33/15510.11	% SZS status Started for HL406031+4.p
113979.33/15510.11	% SZS status GaveUp for HL406031+4.p
113979.33/15510.11	eprover: CPU time limit exceeded, terminating
113979.33/15510.11	% SZS status Ended for HL406031+4.p
113981.17/15510.36	% SZS status Started for HL406026+5.p
113981.17/15510.36	% SZS status GaveUp for HL406026+5.p
113981.17/15510.36	% SZS status Ended for HL406026+5.p
113992.30/15511.85	% SZS status Started for HL406033+4.p
113992.30/15511.85	% SZS status GaveUp for HL406033+4.p
113992.30/15511.85	eprover: CPU time limit exceeded, terminating
113992.30/15511.85	% SZS status Ended for HL406033+4.p
113995.23/15512.07	% SZS status Started for HL406027+5.p
113995.23/15512.07	% SZS status GaveUp for HL406027+5.p
113995.23/15512.07	% SZS status Ended for HL406027+5.p
114005.58/15513.40	% SZS status Started for HL406036+4.p
114005.58/15513.40	% SZS status GaveUp for HL406036+4.p
114005.58/15513.40	eprover: CPU time limit exceeded, terminating
114005.58/15513.40	% SZS status Ended for HL406036+4.p
114008.55/15513.80	% SZS status Started for HL406028+5.p
114008.55/15513.80	% SZS status GaveUp for HL406028+5.p
114008.55/15513.80	% SZS status Ended for HL406028+5.p
114013.39/15514.39	% SZS status Started for HL406029+5.p
114013.39/15514.39	% SZS status GaveUp for HL406029+5.p
114013.39/15514.39	% SZS status Ended for HL406029+5.p
114019.47/15515.12	% SZS status Started for HL406037+4.p
114019.47/15515.12	% SZS status GaveUp for HL406037+4.p
114019.47/15515.12	eprover: CPU time limit exceeded, terminating
114019.47/15515.12	% SZS status Ended for HL406037+4.p
114032.67/15516.84	% SZS status Started for HL406038+4.p
114032.67/15516.84	% SZS status GaveUp for HL406038+4.p
114032.67/15516.84	eprover: CPU time limit exceeded, terminating
114032.67/15516.84	% SZS status Ended for HL406038+4.p
114034.12/15517.09	% SZS status Started for HL406030+5.p
114034.12/15517.09	% SZS status GaveUp for HL406030+5.p
114034.12/15517.09	% SZS status Ended for HL406030+5.p
114043.38/15518.16	% SZS status Started for HL406039+4.p
114043.38/15518.16	% SZS status GaveUp for HL406039+4.p
114043.38/15518.16	eprover: CPU time limit exceeded, terminating
114043.38/15518.16	% SZS status Ended for HL406039+4.p
114047.76/15518.70	% SZS status Started for HL406031+5.p
114047.76/15518.70	% SZS status GaveUp for HL406031+5.p
114047.76/15518.70	% SZS status Ended for HL406031+5.p
114058.04/15520.12	% SZS status Started for HL406040+4.p
114058.04/15520.12	% SZS status GaveUp for HL406040+4.p
114058.04/15520.12	eprover: CPU time limit exceeded, terminating
114058.04/15520.12	% SZS status Ended for HL406040+4.p
114061.73/15520.56	% SZS status Started for HL406033+5.p
114061.73/15520.56	% SZS status GaveUp for HL406033+5.p
114061.73/15520.56	% SZS status Ended for HL406033+5.p
114071.48/15521.76	% SZS status Started for HL406041+4.p
114071.48/15521.76	% SZS status GaveUp for HL406041+4.p
114071.48/15521.76	eprover: CPU time limit exceeded, terminating
114071.48/15521.76	% SZS status Ended for HL406041+4.p
114071.48/15521.84	% SZS status Started for HL406036+5.p
114071.48/15521.84	% SZS status GaveUp for HL406036+5.p
114071.48/15521.84	% SZS status Ended for HL406036+5.p
114093.67/15523.54	% SZS status Started for HL406037+5.p
114093.67/15523.54	% SZS status GaveUp for HL406037+5.p
114093.67/15523.54	% SZS status Ended for HL406037+5.p
114095.96/15523.75	% SZS status Started for HL406042+4.p
114095.96/15523.75	% SZS status GaveUp for HL406042+4.p
114095.96/15523.75	eprover: CPU time limit exceeded, terminating
114095.96/15523.75	% SZS status Ended for HL406042+4.p
114102.14/15524.62	% SZS status Started for HL406038+5.p
114102.14/15524.62	% SZS status GaveUp for HL406038+5.p
114102.14/15524.62	% SZS status Ended for HL406038+5.p
114121.18/15526.93	% SZS status Started for HL406044+4.p
114121.18/15526.93	% SZS status GaveUp for HL406044+4.p
114121.18/15526.93	eprover: CPU time limit exceeded, terminating
114121.18/15526.93	% SZS status Ended for HL406044+4.p
114121.96/15527.04	% SZS status Started for HL406039+5.p
114121.96/15527.04	% SZS status GaveUp for HL406039+5.p
114121.96/15527.04	% SZS status Ended for HL406039+5.p
114134.71/15528.61	% SZS status Started for HL406040+5.p
114134.71/15528.61	% SZS status GaveUp for HL406040+5.p
114134.71/15528.61	% SZS status Ended for HL406040+5.p
114145.92/15529.97	% SZS status Started for HL406045+4.p
114145.92/15529.97	% SZS status GaveUp for HL406045+4.p
114145.92/15529.97	eprover: CPU time limit exceeded, terminating
114145.92/15529.97	% SZS status Ended for HL406045+4.p
114147.61/15530.35	% SZS status Started for HL406041+5.p
114147.61/15530.35	% SZS status GaveUp for HL406041+5.p
114147.61/15530.35	% SZS status Ended for HL406041+5.p
114158.80/15531.65	% SZS status Started for HL406046+4.p
114158.80/15531.65	% SZS status GaveUp for HL406046+4.p
114158.80/15531.65	eprover: CPU time limit exceeded, terminating
114158.80/15531.65	% SZS status Ended for HL406046+4.p
114161.05/15532.04	% SZS status Started for HL406042+5.p
114161.05/15532.04	% SZS status GaveUp for HL406042+5.p
114161.05/15532.04	% SZS status Ended for HL406042+5.p
114178.18/15533.00	% SZS status Started for HL406043+4.p
114178.18/15533.00	% SZS status GaveUp for HL406043+4.p
114178.18/15533.00	eprover: CPU time limit exceeded, terminating
114178.18/15533.00	% SZS status Ended for HL406043+4.p
114181.77/15533.38	% SZS status Started for HL406047+4.p
114181.77/15533.38	% SZS status GaveUp for HL406047+4.p
114181.77/15533.38	eprover: CPU time limit exceeded, terminating
114181.77/15533.38	% SZS status Ended for HL406047+4.p
114185.73/15533.87	% SZS status Started for HL406043+5.p
114185.73/15533.87	% SZS status GaveUp for HL406043+5.p
114185.73/15533.87	% SZS status Ended for HL406043+5.p
114192.80/15534.82	% SZS status Started for HL406044+5.p
114192.80/15534.82	% SZS status GaveUp for HL406044+5.p
114192.80/15534.82	% SZS status Ended for HL406044+5.p
114195.19/15535.07	% SZS status Started for HL406048+4.p
114195.19/15535.07	% SZS status GaveUp for HL406048+4.p
114195.19/15535.07	eprover: CPU time limit exceeded, terminating
114195.19/15535.07	% SZS status Ended for HL406048+4.p
114205.85/15536.43	% SZS status Started for HL406049+4.p
114205.85/15536.43	% SZS status GaveUp for HL406049+4.p
114205.85/15536.43	eprover: CPU time limit exceeded, terminating
114205.85/15536.43	% SZS status Ended for HL406049+4.p
114214.04/15537.45	% SZS status Started for HL406045+5.p
114214.04/15537.45	% SZS status GaveUp for HL406045+5.p
114214.04/15537.45	% SZS status Ended for HL406045+5.p
114218.20/15538.02	% SZS status Started for HL406050+4.p
114218.20/15538.02	% SZS status GaveUp for HL406050+4.p
114218.20/15538.02	eprover: CPU time limit exceeded, terminating
114218.20/15538.02	% SZS status Ended for HL406050+4.p
114228.19/15539.48	% SZS status Started for HL406052+4.p
114228.19/15539.48	% SZS status GaveUp for HL406052+4.p
114228.19/15539.48	eprover: CPU time limit exceeded, terminating
114228.19/15539.48	% SZS status Ended for HL406052+4.p
114235.61/15540.17	% SZS status Started for HL406046+5.p
114235.61/15540.17	% SZS status GaveUp for HL406046+5.p
114235.61/15540.17	% SZS status Ended for HL406046+5.p
114249.30/15541.87	% SZS status Started for HL406047+5.p
114249.30/15541.87	% SZS status GaveUp for HL406047+5.p
114249.30/15541.87	% SZS status Ended for HL406047+5.p
114258.66/15543.10	% SZS status Started for HL406048+5.p
114258.66/15543.10	% SZS status GaveUp for HL406048+5.p
114258.66/15543.10	% SZS status Ended for HL406048+5.p
114266.83/15544.10	% SZS status Started for HL406049+5.p
114266.83/15544.10	% SZS status GaveUp for HL406049+5.p
114266.83/15544.10	% SZS status Ended for HL406049+5.p
114275.75/15545.22	% SZS status Started for HL406050+5.p
114275.75/15545.22	% SZS status GaveUp for HL406050+5.p
114275.75/15545.22	% SZS status Ended for HL406050+5.p
114293.77/15547.66	% SZS status Started for HL406052+5.p
114293.77/15547.66	% SZS status GaveUp for HL406052+5.p
114293.77/15547.66	% SZS status Ended for HL406052+5.p
114306.15/15549.08	% SZS status Started for HL406053+4.p
114306.15/15549.08	% SZS status GaveUp for HL406053+4.p
114306.15/15549.08	eprover: CPU time limit exceeded, terminating
114306.15/15549.08	% SZS status Ended for HL406053+4.p
114308.76/15549.37	% SZS status Started for HL406053+5.p
114308.76/15549.37	% SZS status GaveUp for HL406053+5.p
114308.76/15549.37	% SZS status Ended for HL406053+5.p
114317.25/15550.45	% SZS status Started for HL406054+4.p
114317.25/15550.45	% SZS status GaveUp for HL406054+4.p
114317.25/15550.45	eprover: CPU time limit exceeded, terminating
114317.25/15550.45	% SZS status Ended for HL406054+4.p
114325.84/15551.59	% SZS status Started for HL406054+5.p
114325.84/15551.59	% SZS status GaveUp for HL406054+5.p
114325.84/15551.59	% SZS status Ended for HL406054+5.p
114341.45/15553.44	% SZS status Started for HL406055+4.p
114341.45/15553.44	% SZS status GaveUp for HL406055+4.p
114341.45/15553.44	eprover: CPU time limit exceeded, terminating
114341.45/15553.44	% SZS status Ended for HL406055+4.p
114342.91/15553.72	% SZS status Started for HL406055+5.p
114342.91/15553.72	% SZS status GaveUp for HL406055+5.p
114342.91/15553.72	% SZS status Ended for HL406055+5.p
114357.09/15555.47	% SZS status Started for HL406056+4.p
114357.09/15555.47	% SZS status GaveUp for HL406056+4.p
114357.09/15555.47	eprover: CPU time limit exceeded, terminating
114357.09/15555.47	% SZS status Ended for HL406056+4.p
114366.78/15556.80	% SZS status Started for HL406057+5.p
114366.78/15556.80	% SZS status Theorem for HL406057+5.p
114366.78/15556.80	% SZS status Ended for HL406057+5.p
114372.92/15557.45	% SZS status Started for HL406056+5.p
114372.92/15557.45	% SZS status GaveUp for HL406056+5.p
114372.92/15557.45	% SZS status Ended for HL406056+5.p
114381.56/15558.50	% SZS status Started for HL406060+4.p
114381.56/15558.50	% SZS status GaveUp for HL406060+4.p
114381.56/15558.50	eprover: CPU time limit exceeded, terminating
114381.56/15558.50	% SZS status Ended for HL406060+4.p
114387.98/15559.38	% SZS status Started for HL406057+4.p
114387.98/15559.38	% SZS status GaveUp for HL406057+4.p
114387.98/15559.38	eprover: CPU time limit exceeded, terminating
114387.98/15559.38	% SZS status Ended for HL406057+4.p
114396.88/15560.54	% SZS status Started for HL406061+4.p
114396.88/15560.54	% SZS status GaveUp for HL406061+4.p
114396.88/15560.54	eprover: CPU time limit exceeded, terminating
114396.88/15560.54	% SZS status Ended for HL406061+4.p
114397.58/15560.73	% SZS status Started for HL406058+4.p
114397.58/15560.73	% SZS status GaveUp for HL406058+4.p
114397.58/15560.73	eprover: CPU time limit exceeded, terminating
114397.58/15560.73	% SZS status Ended for HL406058+4.p
114402.23/15561.25	% SZS status Started for HL406058+5.p
114402.23/15561.25	% SZS status GaveUp for HL406058+5.p
114402.23/15561.25	% SZS status Ended for HL406058+5.p
114414.03/15562.60	% SZS status Started for HL406062+4.p
114414.03/15562.60	% SZS status GaveUp for HL406062+4.p
114414.03/15562.60	eprover: CPU time limit exceeded, terminating
114414.03/15562.60	% SZS status Ended for HL406062+4.p
114419.23/15563.31	% SZS status Started for HL406059+5.p
114419.23/15563.31	% SZS status GaveUp for HL406059+5.p
114419.23/15563.31	% SZS status Ended for HL406059+5.p
114423.09/15563.73	% SZS status Started for HL406059+4.p
114423.09/15563.73	% SZS status GaveUp for HL406059+4.p
114423.09/15563.73	eprover: CPU time limit exceeded, terminating
114423.09/15563.73	% SZS status Ended for HL406059+4.p
114423.43/15563.77	% SZS status Started for HL406063+4.p
114423.43/15563.77	% SZS status GaveUp for HL406063+4.p
114423.43/15563.77	eprover: CPU time limit exceeded, terminating
114423.43/15563.77	% SZS status Ended for HL406063+4.p
114437.96/15565.66	% SZS status Started for HL406064+4.p
114437.96/15565.66	% SZS status GaveUp for HL406064+4.p
114437.96/15565.66	eprover: CPU time limit exceeded, terminating
114437.96/15565.66	% SZS status Ended for HL406064+4.p
114446.36/15566.77	% SZS status Started for HL406065+4.p
114446.36/15566.77	% SZS status GaveUp for HL406065+4.p
114446.36/15566.77	eprover: CPU time limit exceeded, terminating
114446.36/15566.77	% SZS status Ended for HL406065+4.p
114449.68/15567.08	% SZS status Started for HL406060+5.p
114449.68/15567.08	% SZS status GaveUp for HL406060+5.p
114449.68/15567.08	% SZS status Ended for HL406060+5.p
114460.43/15568.52	% SZS status Started for HL406061+5.p
114460.43/15568.52	% SZS status GaveUp for HL406061+5.p
114460.43/15568.52	% SZS status Ended for HL406061+5.p
114461.42/15568.69	% SZS status Started for HL406066+4.p
114461.42/15568.69	% SZS status GaveUp for HL406066+4.p
114461.42/15568.69	eprover: CPU time limit exceeded, terminating
114461.42/15568.69	% SZS status Ended for HL406066+4.p
114473.39/15570.12	% SZS status Started for HL406068+4.p
114473.39/15570.12	% SZS status GaveUp for HL406068+4.p
114473.39/15570.12	eprover: CPU time limit exceeded, terminating
114473.39/15570.12	% SZS status Ended for HL406068+4.p
114478.37/15570.80	% SZS status Started for HL406062+5.p
114478.37/15570.80	% SZS status GaveUp for HL406062+5.p
114478.37/15570.80	% SZS status Ended for HL406062+5.p
114478.68/15570.84	% SZS status Started for HL406064+5.p
114478.68/15570.84	% SZS status Theorem for HL406064+5.p
114478.68/15570.84	% SZS status Ended for HL406064+5.p
114482.88/15571.24	% SZS status Started for HL406063+5.p
114482.88/15571.24	% SZS status GaveUp for HL406063+5.p
114482.88/15571.24	% SZS status Ended for HL406063+5.p
114486.28/15571.73	% SZS status Started for HL406070+4.p
114486.28/15571.73	% SZS status GaveUp for HL406070+4.p
114486.28/15571.73	eprover: CPU time limit exceeded, terminating
114486.28/15571.73	% SZS status Ended for HL406070+4.p
114503.32/15573.83	% SZS status Started for HL406071+4.p
114503.32/15573.83	% SZS status GaveUp for HL406071+4.p
114503.32/15573.83	eprover: CPU time limit exceeded, terminating
114503.32/15573.83	% SZS status Ended for HL406071+4.p
114504.04/15573.94	% SZS status Started for HL406065+5.p
114504.04/15573.94	% SZS status GaveUp for HL406065+5.p
114504.04/15573.94	% SZS status Ended for HL406065+5.p
114505.66/15574.28	% SZS status Started for HL406072+4.p
114505.66/15574.28	% SZS status GaveUp for HL406072+4.p
114505.66/15574.28	eprover: CPU time limit exceeded, terminating
114505.66/15574.28	% SZS status Ended for HL406072+4.p
114526.88/15576.79	% SZS status Started for HL406066+5.p
114526.88/15576.79	% SZS status GaveUp for HL406066+5.p
114526.88/15576.79	% SZS status Ended for HL406066+5.p
114526.88/15576.87	% SZS status Started for HL406073+4.p
114526.88/15576.87	% SZS status GaveUp for HL406073+4.p
114526.88/15576.87	eprover: CPU time limit exceeded, terminating
114526.88/15576.87	% SZS status Ended for HL406073+4.p
114531.00/15577.31	% SZS status Started for HL406074+4.p
114531.00/15577.31	% SZS status GaveUp for HL406074+4.p
114531.00/15577.31	eprover: CPU time limit exceeded, terminating
114531.00/15577.31	% SZS status Ended for HL406074+4.p
114544.89/15579.09	% SZS status Started for HL406068+5.p
114544.89/15579.09	% SZS status GaveUp for HL406068+5.p
114544.89/15579.09	% SZS status Ended for HL406068+5.p
114551.43/15579.91	% SZS status Started for HL406075+4.p
114551.43/15579.91	% SZS status GaveUp for HL406075+4.p
114551.43/15579.91	eprover: CPU time limit exceeded, terminating
114551.43/15579.91	% SZS status Ended for HL406075+4.p
114554.66/15580.34	% SZS status Started for HL406070+5.p
114554.66/15580.34	% SZS status GaveUp for HL406070+5.p
114554.66/15580.34	% SZS status Ended for HL406070+5.p
114568.20/15582.13	% SZS status Started for HL406076+4.p
114568.20/15582.13	% SZS status GaveUp for HL406076+4.p
114568.20/15582.13	eprover: CPU time limit exceeded, terminating
114568.20/15582.13	% SZS status Ended for HL406076+4.p
114571.60/15582.43	% SZS status Started for HL406072+5.p
114571.60/15582.43	% SZS status GaveUp for HL406072+5.p
114571.60/15582.43	% SZS status Ended for HL406072+5.p
114572.87/15582.59	% SZS status Started for HL406076+5.p
114572.87/15582.59	% SZS status Theorem for HL406076+5.p
114572.87/15582.59	% SZS status Ended for HL406076+5.p
114578.45/15583.38	% SZS status Started for HL406077+4.p
114578.45/15583.38	% SZS status GaveUp for HL406077+4.p
114578.45/15583.38	eprover: CPU time limit exceeded, terminating
114578.45/15583.38	% SZS status Ended for HL406077+4.p
114585.41/15584.19	% SZS status Started for HL406073+5.p
114585.41/15584.19	% SZS status GaveUp for HL406073+5.p
114585.41/15584.19	% SZS status Ended for HL406073+5.p
114595.68/15585.47	% SZS status Started for HL406078+4.p
114595.68/15585.47	% SZS status GaveUp for HL406078+4.p
114595.68/15585.47	eprover: CPU time limit exceeded, terminating
114595.68/15585.47	% SZS status Ended for HL406078+4.p
114603.46/15586.47	% SZS status Started for HL406079+4.p
114603.46/15586.47	% SZS status GaveUp for HL406079+4.p
114603.46/15586.47	eprover: CPU time limit exceeded, terminating
114603.46/15586.47	% SZS status Ended for HL406079+4.p
114608.31/15587.05	% SZS status Started for HL406074+5.p
114608.31/15587.05	% SZS status GaveUp for HL406074+5.p
114608.31/15587.05	% SZS status Ended for HL406074+5.p
114619.18/15588.50	% SZS status Started for HL406081+4.p
114619.18/15588.50	% SZS status GaveUp for HL406081+4.p
114619.18/15588.50	eprover: CPU time limit exceeded, terminating
114619.18/15588.50	% SZS status Ended for HL406081+4.p
114631.89/15590.10	% SZS status Started for HL406082+4.p
114631.89/15590.10	% SZS status GaveUp for HL406082+4.p
114631.89/15590.10	eprover: CPU time limit exceeded, terminating
114631.89/15590.10	% SZS status Ended for HL406082+4.p
114648.25/15592.13	% SZS status Started for HL406077+5.p
114648.25/15592.13	% SZS status GaveUp for HL406077+5.p
114648.25/15592.13	% SZS status Ended for HL406077+5.p
114656.45/15593.10	% SZS status Started for HL406081+5.p
114656.45/15593.10	% SZS status Theorem for HL406081+5.p
114656.45/15593.10	% SZS status Ended for HL406081+5.p
114656.45/15593.13	% SZS status Started for HL406083+4.p
114656.45/15593.13	% SZS status GaveUp for HL406083+4.p
114656.45/15593.13	eprover: CPU time limit exceeded, terminating
114656.45/15593.13	% SZS status Ended for HL406083+4.p
114664.80/15594.25	% SZS status Started for HL406079+5.p
114664.80/15594.25	% SZS status GaveUp for HL406079+5.p
114664.80/15594.25	% SZS status Ended for HL406079+5.p
114669.70/15594.80	% SZS status Started for HL406083+5.p
114669.70/15594.80	% SZS status Theorem for HL406083+5.p
114669.70/15594.80	% SZS status Ended for HL406083+5.p
114671.81/15595.12	% SZS status Started for HL406082+5.p
114671.81/15595.12	% SZS status Theorem for HL406082+5.p
114671.81/15595.12	% SZS status Ended for HL406082+5.p
114676.12/15595.58	% SZS status Started for HL406084+5.p
114676.12/15595.58	% SZS status Theorem for HL406084+5.p
114676.12/15595.58	% SZS status Ended for HL406084+5.p
114680.66/15596.13	% SZS status Started for HL406084+4.p
114680.66/15596.13	% SZS status GaveUp for HL406084+4.p
114680.66/15596.13	eprover: CPU time limit exceeded, terminating
114680.66/15596.13	% SZS status Ended for HL406084+4.p
114686.12/15596.85	% SZS status Started for HL406071+5.p
114686.12/15596.85	% SZS status GaveUp for HL406071+5.p
114686.12/15596.85	eprover: CPU time limit exceeded, terminating
114686.12/15596.85	% SZS status Ended for HL406071+5.p
114689.34/15597.29	% SZS status Started for HL406086+4.p
114689.34/15597.29	% SZS status GaveUp for HL406086+4.p
114689.34/15597.29	eprover: CPU time limit exceeded, terminating
114689.34/15597.29	% SZS status Ended for HL406086+4.p
114693.92/15597.94	% SZS status Started for HL406087+5.p
114693.92/15597.94	% SZS status Theorem for HL406087+5.p
114693.92/15597.94	% SZS status Ended for HL406087+5.p
114696.69/15598.16	% SZS status Started for HL406087+4.p
114696.69/15598.16	% SZS status GaveUp for HL406087+4.p
114696.69/15598.16	eprover: CPU time limit exceeded, terminating
114696.69/15598.16	% SZS status Ended for HL406087+4.p
114703.38/15599.15	% SZS status Started for HL406088+5.p
114703.38/15599.15	% SZS status Theorem for HL406088+5.p
114703.38/15599.15	% SZS status Ended for HL406088+5.p
114705.78/15599.17	% SZS status Started for HL406088+4.p
114705.78/15599.17	% SZS status GaveUp for HL406088+4.p
114705.78/15599.17	eprover: CPU time limit exceeded, terminating
114705.78/15599.17	% SZS status Ended for HL406088+4.p
114714.61/15600.33	% SZS status Started for HL406089+4.p
114714.61/15600.33	% SZS status GaveUp for HL406089+4.p
114714.61/15600.33	eprover: CPU time limit exceeded, terminating
114714.61/15600.33	% SZS status Ended for HL406089+4.p
114720.92/15601.20	% SZS status Started for HL406090+4.p
114720.92/15601.20	% SZS status GaveUp for HL406090+4.p
114720.92/15601.20	eprover: CPU time limit exceeded, terminating
114720.92/15601.20	% SZS status Ended for HL406090+4.p
114724.00/15601.50	% SZS status Started for HL406090+5.p
114724.00/15601.50	% SZS status Theorem for HL406090+5.p
114724.00/15601.50	% SZS status Ended for HL406090+5.p
114724.52/15601.58	% SZS status Started for HL406089+5.p
114724.52/15601.58	% SZS status Theorem for HL406089+5.p
114724.52/15601.58	% SZS status Ended for HL406089+5.p
114730.58/15602.34	% SZS status Started for HL406091+4.p
114730.58/15602.34	% SZS status GaveUp for HL406091+4.p
114730.58/15602.34	eprover: CPU time limit exceeded, terminating
114730.58/15602.34	% SZS status Ended for HL406091+4.p
114733.29/15602.66	% SZS status Started for HL406091+5.p
114733.29/15602.66	% SZS status Theorem for HL406091+5.p
114733.29/15602.66	% SZS status Ended for HL406091+5.p
114738.20/15603.30	% SZS status Started for HL406075+5.p
114738.20/15603.30	% SZS status GaveUp for HL406075+5.p
114738.20/15603.30	eprover: CPU time limit exceeded, terminating
114738.20/15603.30	% SZS status Ended for HL406075+5.p
114745.98/15604.23	% SZS status Started for HL406092+4.p
114745.98/15604.23	% SZS status GaveUp for HL406092+4.p
114745.98/15604.23	eprover: CPU time limit exceeded, terminating
114745.98/15604.23	% SZS status Ended for HL406092+4.p
114746.42/15604.31	% SZS status Started for HL406092+5.p
114746.42/15604.31	% SZS status Theorem for HL406092+5.p
114746.42/15604.31	% SZS status Ended for HL406092+5.p
114747.95/15604.63	% SZS status Started for HL406093+4.p
114747.95/15604.63	% SZS status GaveUp for HL406093+4.p
114747.95/15604.63	eprover: CPU time limit exceeded, terminating
114747.95/15604.63	% SZS status Ended for HL406093+4.p
114748.67/15604.81	% SZS status Started for HL406086+5.p
114748.67/15604.81	% SZS status GaveUp for HL406086+5.p
114748.67/15604.81	% SZS status Ended for HL406086+5.p
114758.97/15604.85	% SZS status Started for HL406093+5.p
114758.97/15604.85	% SZS status Theorem for HL406093+5.p
114758.97/15604.85	% SZS status Ended for HL406093+5.p
114765.22/15605.65	% SZS status Started for HL406094+5.p
114765.22/15605.65	% SZS status Theorem for HL406094+5.p
114765.22/15605.65	% SZS status Ended for HL406094+5.p
114765.78/15605.73	% SZS status Started for HL406094+4.p
114765.78/15605.73	% SZS status GaveUp for HL406094+4.p
114765.78/15605.73	eprover: CPU time limit exceeded, terminating
114765.78/15605.73	% SZS status Ended for HL406094+4.p
114777.76/15607.27	% SZS status Started for HL406096+4.p
114777.76/15607.27	% SZS status GaveUp for HL406096+4.p
114777.76/15607.27	eprover: CPU time limit exceeded, terminating
114777.76/15607.27	% SZS status Ended for HL406096+4.p
114780.97/15607.69	% SZS status Started for HL406097+4.p
114780.97/15607.69	% SZS status GaveUp for HL406097+4.p
114780.97/15607.69	eprover: CPU time limit exceeded, terminating
114780.97/15607.69	% SZS status Ended for HL406097+4.p
114782.66/15607.88	% SZS status Started for HL406098+4.p
114782.66/15607.88	% SZS status GaveUp for HL406098+4.p
114782.66/15607.88	eprover: CPU time limit exceeded, terminating
114782.66/15607.88	% SZS status Ended for HL406098+4.p
114789.99/15608.77	% SZS status Started for HL406099+4.p
114789.99/15608.77	% SZS status GaveUp for HL406099+4.p
114789.99/15608.77	eprover: CPU time limit exceeded, terminating
114789.99/15608.77	% SZS status Ended for HL406099+4.p
114795.23/15609.46	% SZS status Started for HL406078+5.p
114795.23/15609.46	% SZS status GaveUp for HL406078+5.p
114795.23/15609.46	eprover: CPU time limit exceeded, terminating
114795.23/15609.46	% SZS status Ended for HL406078+5.p
114797.27/15609.75	% SZS status Started for HL406099+5.p
114797.27/15609.75	% SZS status Theorem for HL406099+5.p
114797.27/15609.75	% SZS status Ended for HL406099+5.p
114805.30/15610.72	% SZS status Started for HL406100+4.p
114805.30/15610.72	% SZS status GaveUp for HL406100+4.p
114805.30/15610.72	eprover: CPU time limit exceeded, terminating
114805.30/15610.72	% SZS status Ended for HL406100+4.p
114813.46/15611.81	% SZS status Started for HL406101+4.p
114813.46/15611.81	% SZS status GaveUp for HL406101+4.p
114813.46/15611.81	eprover: CPU time limit exceeded, terminating
114813.46/15611.81	% SZS status Ended for HL406101+4.p
114821.62/15612.78	% SZS status Started for HL406102+4.p
114821.62/15612.78	% SZS status GaveUp for HL406102+4.p
114821.62/15612.78	eprover: CPU time limit exceeded, terminating
114821.62/15612.78	% SZS status Ended for HL406102+4.p
114833.76/15614.34	% SZS status Started for HL406096+5.p
114833.76/15614.34	% SZS status GaveUp for HL406096+5.p
114833.76/15614.34	% SZS status Ended for HL406096+5.p
114836.66/15614.85	% SZS status Started for HL406105+4.p
114836.66/15614.85	% SZS status GaveUp for HL406105+4.p
114836.66/15614.85	eprover: CPU time limit exceeded, terminating
114836.66/15614.85	% SZS status Ended for HL406105+4.p
114844.19/15615.65	% SZS status Started for HL406098+5.p
114844.19/15615.65	% SZS status GaveUp for HL406098+5.p
114844.19/15615.65	% SZS status Ended for HL406098+5.p
114858.25/15617.38	% SZS status Started for HL406106+4.p
114858.25/15617.38	% SZS status GaveUp for HL406106+4.p
114858.25/15617.38	eprover: CPU time limit exceeded, terminating
114858.25/15617.38	% SZS status Ended for HL406106+4.p
114858.25/15617.39	% SZS status Started for HL406106+5.p
114858.25/15617.39	% SZS status Theorem for HL406106+5.p
114858.25/15617.39	% SZS status Ended for HL406106+5.p
114866.03/15618.34	% SZS status Started for HL406100+5.p
114866.03/15618.34	% SZS status GaveUp for HL406100+5.p
114866.03/15618.34	% SZS status Ended for HL406100+5.p
114868.31/15618.69	% SZS status Started for HL406108+4.p
114868.31/15618.69	% SZS status GaveUp for HL406108+4.p
114868.31/15618.69	eprover: CPU time limit exceeded, terminating
114868.31/15618.69	% SZS status Ended for HL406108+4.p
114874.78/15619.45	% SZS status Started for HL406105+5.p
114874.78/15619.45	% SZS status Theorem for HL406105+5.p
114874.78/15619.45	% SZS status Ended for HL406105+5.p
114877.13/15619.81	% SZS status Started for HL406108+5.p
114877.13/15619.81	% SZS status Theorem for HL406108+5.p
114877.13/15619.81	% SZS status Ended for HL406108+5.p
114882.20/15620.43	% SZS status Started for HL406109+4.p
114882.20/15620.43	% SZS status GaveUp for HL406109+4.p
114882.20/15620.43	eprover: CPU time limit exceeded, terminating
114882.20/15620.43	% SZS status Ended for HL406109+4.p
114884.86/15620.72	% SZS status Started for HL406102+5.p
114884.86/15620.72	% SZS status GaveUp for HL406102+5.p
114884.86/15620.72	% SZS status Ended for HL406102+5.p
114885.96/15620.87	% SZS status Started for HL406109+5.p
114885.96/15620.87	% SZS status Theorem for HL406109+5.p
114885.96/15620.87	% SZS status Ended for HL406109+5.p
114892.66/15621.77	% SZS status Started for HL406110+4.p
114892.66/15621.77	% SZS status GaveUp for HL406110+4.p
114892.66/15621.77	eprover: CPU time limit exceeded, terminating
114892.66/15621.77	% SZS status Ended for HL406110+4.p
114893.41/15621.80	% SZS status Started for HL406110+5.p
114893.41/15621.80	% SZS status Theorem for HL406110+5.p
114893.41/15621.80	% SZS status Ended for HL406110+5.p
114900.88/15622.81	% SZS status Started for HL406111+5.p
114900.88/15622.81	% SZS status Theorem for HL406111+5.p
114900.88/15622.81	% SZS status Ended for HL406111+5.p
114901.95/15622.88	% SZS status Started for HL406111+4.p
114901.95/15622.88	% SZS status GaveUp for HL406111+4.p
114901.95/15622.88	eprover: CPU time limit exceeded, terminating
114901.95/15622.88	% SZS status Ended for HL406111+4.p
114905.11/15623.33	% SZS status Started for HL406112+5.p
114905.11/15623.33	% SZS status Theorem for HL406112+5.p
114905.11/15623.33	% SZS status Ended for HL406112+5.p
114908.84/15623.75	% SZS status Started for HL406112+4.p
114908.84/15623.75	% SZS status GaveUp for HL406112+4.p
114908.84/15623.75	eprover: CPU time limit exceeded, terminating
114908.84/15623.75	% SZS status Ended for HL406112+4.p
114912.56/15624.26	% SZS status Started for HL406113+5.p
114912.56/15624.26	% SZS status Theorem for HL406113+5.p
114912.56/15624.26	% SZS status Ended for HL406113+5.p
114917.26/15624.81	% SZS status Started for HL406113+4.p
114917.26/15624.81	% SZS status GaveUp for HL406113+4.p
114917.26/15624.81	eprover: CPU time limit exceeded, terminating
114917.26/15624.81	% SZS status Ended for HL406113+4.p
114919.74/15625.16	% SZS status Started for HL406114+5.p
114919.74/15625.16	% SZS status Theorem for HL406114+5.p
114919.74/15625.16	% SZS status Ended for HL406114+5.p
114925.09/15625.84	% SZS status Started for HL406114+4.p
114925.09/15625.84	% SZS status GaveUp for HL406114+4.p
114925.09/15625.84	eprover: CPU time limit exceeded, terminating
114925.09/15625.84	% SZS status Ended for HL406114+4.p
114927.29/15626.13	% SZS status Started for HL406118+5.p
114927.29/15626.13	% SZS status Theorem for HL406118+5.p
114927.29/15626.13	% SZS status Ended for HL406118+5.p
114929.69/15626.38	% SZS status Started for HL406118+4.p
114929.69/15626.38	% SZS status GaveUp for HL406118+4.p
114929.69/15626.38	eprover: CPU time limit exceeded, terminating
114929.69/15626.38	% SZS status Ended for HL406118+4.p
114937.47/15627.39	% SZS status Started for HL406119+4.p
114937.47/15627.39	% SZS status GaveUp for HL406119+4.p
114937.47/15627.39	eprover: CPU time limit exceeded, terminating
114937.47/15627.39	% SZS status Ended for HL406119+4.p
114944.16/15628.20	% SZS status Started for HL406120+4.p
114944.16/15628.20	% SZS status GaveUp for HL406120+4.p
114944.16/15628.20	eprover: CPU time limit exceeded, terminating
114944.16/15628.20	% SZS status Ended for HL406120+4.p
114951.84/15629.17	% SZS status Started for HL406121+4.p
114951.84/15629.17	% SZS status GaveUp for HL406121+4.p
114951.84/15629.17	eprover: CPU time limit exceeded, terminating
114951.84/15629.17	% SZS status Ended for HL406121+4.p
114961.79/15630.42	% SZS status Started for HL406122+4.p
114961.79/15630.42	% SZS status GaveUp for HL406122+4.p
114961.79/15630.42	eprover: CPU time limit exceeded, terminating
114961.79/15630.42	% SZS status Ended for HL406122+4.p
114966.97/15631.07	% SZS status Started for HL406097+5.p
114966.97/15631.07	% SZS status GaveUp for HL406097+5.p
114966.97/15631.07	eprover: CPU time limit exceeded, terminating
114966.97/15631.07	% SZS status Ended for HL406097+5.p
114975.79/15632.21	% SZS status Started for HL406123+4.p
114975.79/15632.21	% SZS status GaveUp for HL406123+4.p
114975.79/15632.21	eprover: CPU time limit exceeded, terminating
114975.79/15632.21	% SZS status Ended for HL406123+4.p
114984.35/15633.27	% SZS status Started for HL406123+5.p
114984.35/15633.27	% SZS status Theorem for HL406123+5.p
114984.35/15633.27	% SZS status Ended for HL406123+5.p
114990.91/15634.11	% SZS status Started for HL406125+4.p
114990.91/15634.11	% SZS status GaveUp for HL406125+4.p
114990.91/15634.11	eprover: CPU time limit exceeded, terminating
114990.91/15634.11	% SZS status Ended for HL406125+4.p
114998.60/15635.06	% SZS status Started for HL406119+5.p
114998.60/15635.06	% SZS status GaveUp for HL406119+5.p
114998.60/15635.06	% SZS status Ended for HL406119+5.p
115012.16/15635.46	% SZS status Started for HL406101+5.p
115012.16/15635.46	% SZS status GaveUp for HL406101+5.p
115012.16/15635.46	eprover: CPU time limit exceeded, terminating
115012.16/15635.46	% SZS status Ended for HL406101+5.p
115013.04/15635.64	% SZS status Started for HL406122+5.p
115013.04/15635.64	% SZS status Theorem for HL406122+5.p
115013.04/15635.64	% SZS status Ended for HL406122+5.p
115014.55/15635.84	% SZS status Started for HL406120+5.p
115014.55/15635.84	% SZS status GaveUp for HL406120+5.p
115014.55/15635.84	% SZS status Ended for HL406120+5.p
115018.90/15636.39	% SZS status Started for HL406127+4.p
115018.90/15636.39	% SZS status GaveUp for HL406127+4.p
115018.90/15636.39	eprover: CPU time limit exceeded, terminating
115018.90/15636.39	% SZS status Ended for HL406127+4.p
115021.67/15636.67	% SZS status Started for HL406121+5.p
115021.67/15636.67	% SZS status GaveUp for HL406121+5.p
115021.67/15636.67	% SZS status Ended for HL406121+5.p
115032.25/15638.09	% SZS status Started for HL406128+4.p
115032.25/15638.09	% SZS status GaveUp for HL406128+4.p
115032.25/15638.09	eprover: CPU time limit exceeded, terminating
115032.25/15638.09	% SZS status Ended for HL406128+4.p
115037.35/15638.68	% SZS status Started for HL406129+4.p
115037.35/15638.68	% SZS status GaveUp for HL406129+4.p
115037.35/15638.68	eprover: CPU time limit exceeded, terminating
115037.35/15638.68	% SZS status Ended for HL406129+4.p
115043.12/15639.43	% SZS status Started for HL406130+4.p
115043.12/15639.43	% SZS status GaveUp for HL406130+4.p
115043.12/15639.43	eprover: CPU time limit exceeded, terminating
115043.12/15639.43	% SZS status Ended for HL406130+4.p
115056.26/15641.13	% SZS status Started for HL406131+4.p
115056.26/15641.13	% SZS status GaveUp for HL406131+4.p
115056.26/15641.13	eprover: CPU time limit exceeded, terminating
115056.26/15641.13	% SZS status Ended for HL406131+4.p
115065.89/15642.35	% SZS status Started for HL406125+5.p
115065.89/15642.35	% SZS status GaveUp for HL406125+5.p
115065.89/15642.35	% SZS status Ended for HL406125+5.p
115066.26/15642.47	% SZS status Started for HL406132+4.p
115066.26/15642.47	% SZS status GaveUp for HL406132+4.p
115066.26/15642.47	eprover: CPU time limit exceeded, terminating
115066.26/15642.47	% SZS status Ended for HL406132+4.p
115082.55/15644.36	% SZS status Started for HL406127+5.p
115082.55/15644.36	% SZS status GaveUp for HL406127+5.p
115082.55/15644.36	% SZS status Ended for HL406127+5.p
115089.32/15645.39	% SZS status Started for HL406134+4.p
115089.32/15645.39	% SZS status GaveUp for HL406134+4.p
115089.32/15645.39	eprover: CPU time limit exceeded, terminating
115089.32/15645.39	% SZS status Ended for HL406134+4.p
115096.53/15646.10	% SZS status Started for HL406128+5.p
115096.53/15646.10	% SZS status GaveUp for HL406128+5.p
115096.53/15646.10	% SZS status Ended for HL406128+5.p
115096.70/15646.11	% SZS status Started for HL406129+5.p
115096.70/15646.11	% SZS status GaveUp for HL406129+5.p
115096.70/15646.11	% SZS status Ended for HL406129+5.p
115103.37/15646.95	% SZS status Started for HL406130+5.p
115103.37/15646.95	% SZS status GaveUp for HL406130+5.p
115103.37/15646.95	% SZS status Ended for HL406130+5.p
115107.05/15647.40	% SZS status Started for HL406135+4.p
115107.05/15647.40	% SZS status GaveUp for HL406135+4.p
115107.05/15647.40	eprover: CPU time limit exceeded, terminating
115107.05/15647.40	% SZS status Ended for HL406135+4.p
115116.70/15648.68	% SZS status Started for HL406136+5.p
115116.70/15648.68	% SZS status Theorem for HL406136+5.p
115116.70/15648.68	% SZS status Ended for HL406136+5.p
115117.54/15648.75	% SZS status Started for HL406131+5.p
115117.54/15648.75	% SZS status GaveUp for HL406131+5.p
115117.54/15648.75	% SZS status Ended for HL406131+5.p
115119.80/15649.13	% SZS status Started for HL406136+4.p
115119.80/15649.13	% SZS status GaveUp for HL406136+4.p
115119.80/15649.13	eprover: CPU time limit exceeded, terminating
115119.80/15649.13	% SZS status Ended for HL406136+4.p
115127.33/15649.98	% SZS status Started for HL406137+4.p
115127.33/15649.98	% SZS status GaveUp for HL406137+4.p
115127.33/15649.98	eprover: CPU time limit exceeded, terminating
115127.33/15649.98	% SZS status Ended for HL406137+4.p
115128.01/15650.08	% SZS status Started for HL406137+5.p
115128.01/15650.08	% SZS status Theorem for HL406137+5.p
115128.01/15650.08	% SZS status Ended for HL406137+5.p
115136.73/15651.16	% SZS status Started for HL406132+5.p
115136.73/15651.16	% SZS status GaveUp for HL406132+5.p
115136.73/15651.16	% SZS status Ended for HL406132+5.p
115141.36/15651.72	% SZS status Started for HL406138+4.p
115141.36/15651.72	% SZS status GaveUp for HL406138+4.p
115141.36/15651.72	eprover: CPU time limit exceeded, terminating
115141.36/15651.72	% SZS status Ended for HL406138+4.p
115143.51/15652.17	% SZS status Started for HL406139+4.p
115143.51/15652.17	% SZS status GaveUp for HL406139+4.p
115143.51/15652.17	eprover: CPU time limit exceeded, terminating
115143.51/15652.17	% SZS status Ended for HL406139+4.p
115152.07/15653.12	% SZS status Started for HL406140+4.p
115152.07/15653.12	% SZS status GaveUp for HL406140+4.p
115152.07/15653.12	eprover: CPU time limit exceeded, terminating
115152.07/15653.12	% SZS status Ended for HL406140+4.p
115152.87/15653.29	% SZS status Started for HL406134+5.p
115152.87/15653.29	% SZS status GaveUp for HL406134+5.p
115152.87/15653.29	% SZS status Ended for HL406134+5.p
115165.27/15654.75	% SZS status Started for HL406141+4.p
115165.27/15654.75	% SZS status GaveUp for HL406141+4.p
115165.27/15654.75	eprover: CPU time limit exceeded, terminating
115165.27/15654.75	% SZS status Ended for HL406141+4.p
115172.05/15655.68	% SZS status Started for HL406135+5.p
115172.05/15655.68	% SZS status GaveUp for HL406135+5.p
115172.05/15655.68	% SZS status Ended for HL406135+5.p
115175.97/15656.16	% SZS status Started for HL406144+4.p
115175.97/15656.16	% SZS status GaveUp for HL406144+4.p
115175.97/15656.16	eprover: CPU time limit exceeded, terminating
115175.97/15656.16	% SZS status Ended for HL406144+4.p
115189.19/15657.79	% SZS status Started for HL406145+4.p
115189.19/15657.79	% SZS status GaveUp for HL406145+4.p
115189.19/15657.79	eprover: CPU time limit exceeded, terminating
115189.19/15657.79	% SZS status Ended for HL406145+4.p
115199.25/15659.06	% SZS status Started for HL406138+5.p
115199.25/15659.06	% SZS status GaveUp for HL406138+5.p
115199.25/15659.06	% SZS status Ended for HL406138+5.p
115200.65/15659.20	% SZS status Started for HL406146+4.p
115200.65/15659.20	% SZS status GaveUp for HL406146+4.p
115200.65/15659.20	eprover: CPU time limit exceeded, terminating
115200.65/15659.20	% SZS status Ended for HL406146+4.p
115209.31/15660.28	% SZS status Started for HL406139+5.p
115209.31/15660.28	% SZS status GaveUp for HL406139+5.p
115209.31/15660.28	% SZS status Ended for HL406139+5.p
115218.28/15661.44	% SZS status Started for HL406140+5.p
115218.28/15661.44	% SZS status GaveUp for HL406140+5.p
115218.28/15661.44	% SZS status Ended for HL406140+5.p
115223.41/15662.10	% SZS status Started for HL406147+4.p
115223.41/15662.10	% SZS status GaveUp for HL406147+4.p
115223.41/15662.10	eprover: CPU time limit exceeded, terminating
115223.41/15662.10	% SZS status Ended for HL406147+4.p
115226.87/15662.48	% SZS status Started for HL406141+5.p
115226.87/15662.48	% SZS status GaveUp for HL406141+5.p
115226.87/15662.48	% SZS status Ended for HL406141+5.p
115233.30/15663.32	% SZS status Started for HL406148+4.p
115233.30/15663.32	% SZS status GaveUp for HL406148+4.p
115233.30/15663.32	eprover: CPU time limit exceeded, terminating
115233.30/15663.32	% SZS status Ended for HL406148+4.p
115237.90/15663.90	% SZS status Started for HL406144+5.p
115237.90/15663.90	% SZS status GaveUp for HL406144+5.p
115237.90/15663.90	% SZS status Ended for HL406144+5.p
115247.41/15665.14	% SZS status Started for HL406149+4.p
115247.41/15665.14	% SZS status GaveUp for HL406149+4.p
115247.41/15665.14	eprover: CPU time limit exceeded, terminating
115247.41/15665.14	% SZS status Ended for HL406149+4.p
115254.68/15665.99	% SZS status Started for HL406145+5.p
115254.68/15665.99	% SZS status GaveUp for HL406145+5.p
115254.68/15665.99	% SZS status Ended for HL406145+5.p
115257.30/15666.36	% SZS status Started for HL406150+4.p
115257.30/15666.36	% SZS status GaveUp for HL406150+4.p
115257.30/15666.36	eprover: CPU time limit exceeded, terminating
115257.30/15666.36	% SZS status Ended for HL406150+4.p
115267.80/15667.80	% SZS status Started for HL406146+5.p
115267.80/15667.80	% SZS status GaveUp for HL406146+5.p
115267.80/15667.80	% SZS status Ended for HL406146+5.p
115271.41/15668.18	% SZS status Started for HL406151+4.p
115271.41/15668.18	% SZS status GaveUp for HL406151+4.p
115271.41/15668.18	eprover: CPU time limit exceeded, terminating
115271.41/15668.18	% SZS status Ended for HL406151+4.p
115281.33/15669.39	% SZS status Started for HL406153+4.p
115281.33/15669.39	% SZS status GaveUp for HL406153+4.p
115281.33/15669.39	eprover: CPU time limit exceeded, terminating
115281.33/15669.39	% SZS status Ended for HL406153+4.p
115283.18/15669.65	% SZS status Started for HL406147+5.p
115283.18/15669.65	% SZS status GaveUp for HL406147+5.p
115283.18/15669.65	% SZS status Ended for HL406147+5.p
115296.04/15671.22	% SZS status Started for HL406154+4.p
115296.04/15671.22	% SZS status GaveUp for HL406154+4.p
115296.04/15671.22	eprover: CPU time limit exceeded, terminating
115296.04/15671.22	% SZS status Ended for HL406154+4.p
115299.75/15671.68	% SZS status Started for HL406148+5.p
115299.75/15671.68	% SZS status GaveUp for HL406148+5.p
115299.75/15671.68	% SZS status Ended for HL406148+5.p
115307.78/15672.68	% SZS status Started for HL406155+4.p
115307.78/15672.68	% SZS status GaveUp for HL406155+4.p
115307.78/15672.68	eprover: CPU time limit exceeded, terminating
115307.78/15672.68	% SZS status Ended for HL406155+4.p
115308.01/15672.74	% SZS status Started for HL406149+5.p
115308.01/15672.74	% SZS status GaveUp for HL406149+5.p
115308.01/15672.74	% SZS status Ended for HL406149+5.p
115323.60/15674.72	% SZS status Started for HL406156+4.p
115323.60/15674.72	% SZS status GaveUp for HL406156+4.p
115323.60/15674.72	eprover: CPU time limit exceeded, terminating
115323.60/15674.72	% SZS status Ended for HL406156+4.p
115324.26/15674.81	% SZS status Started for HL406150+5.p
115324.26/15674.81	% SZS status GaveUp for HL406150+5.p
115324.26/15674.81	% SZS status Ended for HL406150+5.p
115332.09/15675.78	% SZS status Started for HL406157+4.p
115332.09/15675.78	% SZS status GaveUp for HL406157+4.p
115332.09/15675.78	eprover: CPU time limit exceeded, terminating
115332.09/15675.78	% SZS status Ended for HL406157+4.p
115334.91/15676.26	% SZS status Started for HL406151+5.p
115334.91/15676.26	% SZS status GaveUp for HL406151+5.p
115334.91/15676.26	% SZS status Ended for HL406151+5.p
115362.03/15679.67	% SZS status Started for HL406154+5.p
115362.03/15679.67	% SZS status GaveUp for HL406154+5.p
115362.03/15679.67	% SZS status Ended for HL406154+5.p
115377.19/15681.45	% SZS status Started for HL406155+5.p
115377.19/15681.45	% SZS status GaveUp for HL406155+5.p
115377.19/15681.45	% SZS status Ended for HL406155+5.p
115387.95/15682.99	% SZS status Started for HL406156+5.p
115387.95/15682.99	% SZS status GaveUp for HL406156+5.p
115387.95/15682.99	% SZS status Ended for HL406156+5.p
115410.11/15685.59	% SZS status Started for HL406158+5.p
115410.11/15685.59	% SZS status GaveUp for HL406158+5.p
115410.11/15685.59	% SZS status Ended for HL406158+5.p
115410.34/15685.68	% SZS status Started for HL406158+4.p
115410.34/15685.68	% SZS status GaveUp for HL406158+4.p
115410.34/15685.68	eprover: CPU time limit exceeded, terminating
115410.34/15685.68	% SZS status Ended for HL406158+4.p
115418.09/15686.55	% SZS status Started for HL406159+4.p
115418.09/15686.55	% SZS status GaveUp for HL406159+4.p
115418.09/15686.55	eprover: CPU time limit exceeded, terminating
115418.09/15686.55	% SZS status Ended for HL406159+4.p
115440.35/15689.34	% SZS status Started for HL406159+5.p
115440.35/15689.34	% SZS status GaveUp for HL406159+5.p
115440.35/15689.34	% SZS status Ended for HL406159+5.p
115459.46/15691.84	% SZS status Started for HL406160+4.p
115459.46/15691.84	% SZS status GaveUp for HL406160+4.p
115459.46/15691.84	eprover: CPU time limit exceeded, terminating
115459.46/15691.84	% SZS status Ended for HL406160+4.p
115466.45/15692.68	% SZS status Started for HL406160+5.p
115466.45/15692.68	% SZS status GaveUp for HL406160+5.p
115466.45/15692.68	% SZS status Ended for HL406160+5.p
115472.98/15693.51	% SZS status Started for HL406153+5.p
115472.98/15693.51	% SZS status GaveUp for HL406153+5.p
115472.98/15693.51	eprover: CPU time limit exceeded, terminating
115472.98/15693.51	% SZS status Ended for HL406153+5.p
115487.81/15695.37	% SZS status Started for HL406162+5.p
115487.81/15695.37	% SZS status GaveUp for HL406162+5.p
115487.81/15695.37	% SZS status Ended for HL406162+5.p
115492.80/15695.93	% SZS status Started for HL406162+4.p
115492.80/15695.93	% SZS status GaveUp for HL406162+4.p
115492.80/15695.93	eprover: CPU time limit exceeded, terminating
115492.80/15695.93	% SZS status Ended for HL406162+4.p
115499.73/15696.90	% SZS status Started for HL406165+4.p
115499.73/15696.90	% SZS status GaveUp for HL406165+4.p
115499.73/15696.90	eprover: CPU time limit exceeded, terminating
115499.73/15696.90	% SZS status Ended for HL406165+4.p
115517.64/15699.10	% SZS status Started for HL406165+5.p
115517.64/15699.10	% SZS status GaveUp for HL406165+5.p
115517.64/15699.10	% SZS status Ended for HL406165+5.p
115529.84/15700.66	% SZS status Started for HL406157+5.p
115529.84/15700.66	% SZS status GaveUp for HL406157+5.p
115529.84/15700.66	eprover: CPU time limit exceeded, terminating
115529.84/15700.66	% SZS status Ended for HL406157+5.p
115540.59/15702.09	% SZS status Started for HL406166+5.p
115540.59/15702.09	% SZS status GaveUp for HL406166+5.p
115540.59/15702.09	% SZS status Ended for HL406166+5.p
115550.71/15702.24	% SZS status Started for HL406166+4.p
115550.71/15702.24	% SZS status GaveUp for HL406166+4.p
115550.71/15702.24	eprover: CPU time limit exceeded, terminating
115550.71/15702.24	% SZS status Ended for HL406166+4.p
115565.55/15704.18	% SZS status Started for HL406167+4.p
115565.55/15704.18	% SZS status GaveUp for HL406167+4.p
115565.55/15704.18	eprover: CPU time limit exceeded, terminating
115565.55/15704.18	% SZS status Ended for HL406167+4.p
115572.27/15704.97	% SZS status Started for HL406167+5.p
115572.27/15704.97	% SZS status GaveUp for HL406167+5.p
115572.27/15704.97	% SZS status Ended for HL406167+5.p
115582.51/15706.24	% SZS status Started for HL406168+4.p
115582.51/15706.24	% SZS status GaveUp for HL406168+4.p
115582.51/15706.24	eprover: CPU time limit exceeded, terminating
115582.51/15706.24	% SZS status Ended for HL406168+4.p
115582.94/15706.33	% SZS status Started for HL406168+5.p
115582.94/15706.33	% SZS status GaveUp for HL406168+5.p
115582.94/15706.33	% SZS status Ended for HL406168+5.p
115607.84/15709.42	% SZS status Started for HL406169+4.p
115607.84/15709.42	% SZS status GaveUp for HL406169+4.p
115607.84/15709.42	eprover: CPU time limit exceeded, terminating
115607.84/15709.42	% SZS status Ended for HL406169+4.p
115614.88/15710.32	% SZS status Started for HL406169+5.p
115614.88/15710.32	% SZS status GaveUp for HL406169+5.p
115614.88/15710.32	% SZS status Ended for HL406169+5.p
115629.62/15712.15	% SZS status Started for HL406170+5.p
115629.62/15712.15	% SZS status GaveUp for HL406170+5.p
115629.62/15712.15	% SZS status Ended for HL406170+5.p
115631.41/15712.38	% SZS status Started for HL406170+4.p
115631.41/15712.38	% SZS status GaveUp for HL406170+4.p
115631.41/15712.38	eprover: CPU time limit exceeded, terminating
115631.41/15712.38	% SZS status Ended for HL406170+4.p
115648.92/15714.65	% SZS status Started for HL406172+5.p
115648.92/15714.65	% SZS status GaveUp for HL406172+5.p
115648.92/15714.65	% SZS status Ended for HL406172+5.p
115649.55/15714.72	% SZS status Started for HL406172+4.p
115649.55/15714.72	% SZS status GaveUp for HL406172+4.p
115649.55/15714.72	eprover: CPU time limit exceeded, terminating
115649.55/15714.72	% SZS status Ended for HL406172+4.p
115662.19/15716.25	% SZS status Started for HL406173+5.p
115662.19/15716.25	% SZS status GaveUp for HL406173+5.p
115662.19/15716.25	% SZS status Ended for HL406173+5.p
115664.16/15716.57	% SZS status Started for HL406173+4.p
115664.16/15716.57	% SZS status GaveUp for HL406173+4.p
115664.16/15716.57	eprover: CPU time limit exceeded, terminating
115664.16/15716.57	% SZS status Ended for HL406173+4.p
115689.75/15719.78	% SZS status Started for HL406175+5.p
115689.75/15719.78	% SZS status GaveUp for HL406175+5.p
115689.75/15719.78	% SZS status Ended for HL406175+5.p
115690.38/15719.83	% SZS status Started for HL406175+4.p
115690.38/15719.83	% SZS status GaveUp for HL406175+4.p
115690.38/15719.83	eprover: CPU time limit exceeded, terminating
115690.38/15719.83	% SZS status Ended for HL406175+4.p
115708.17/15722.06	% SZS status Started for HL406176+5.p
115708.17/15722.06	% SZS status GaveUp for HL406176+5.p
115708.17/15722.06	% SZS status Ended for HL406176+5.p
115711.31/15722.41	% SZS status Started for HL406176+4.p
115711.31/15722.41	% SZS status GaveUp for HL406176+4.p
115711.31/15722.41	eprover: CPU time limit exceeded, terminating
115711.31/15722.41	% SZS status Ended for HL406176+4.p
115726.15/15724.45	% SZS status Started for HL406177+5.p
115726.15/15724.45	% SZS status GaveUp for HL406177+5.p
115726.15/15724.45	% SZS status Ended for HL406177+5.p
115732.09/15725.10	% SZS status Started for HL406177+4.p
115732.09/15725.10	% SZS status GaveUp for HL406177+4.p
115732.09/15725.10	eprover: CPU time limit exceeded, terminating
115732.09/15725.10	% SZS status Ended for HL406177+4.p
115741.70/15726.29	% SZS status Started for HL406178+5.p
115741.70/15726.29	% SZS status GaveUp for HL406178+5.p
115741.70/15726.29	% SZS status Ended for HL406178+5.p
115743.33/15726.52	% SZS status Started for HL406178+4.p
115743.33/15726.52	% SZS status GaveUp for HL406178+4.p
115743.33/15726.52	eprover: CPU time limit exceeded, terminating
115743.33/15726.52	% SZS status Ended for HL406178+4.p
115766.73/15729.56	% SZS status Started for HL406179+5.p
115766.73/15729.56	% SZS status GaveUp for HL406179+5.p
115766.73/15729.56	% SZS status Ended for HL406179+5.p
115771.05/15730.10	% SZS status Started for HL406179+4.p
115771.05/15730.10	% SZS status GaveUp for HL406179+4.p
115771.05/15730.10	eprover: CPU time limit exceeded, terminating
115771.05/15730.10	% SZS status Ended for HL406179+4.p
115787.12/15732.05	% SZS status Started for HL406180+5.p
115787.12/15732.05	% SZS status GaveUp for HL406180+5.p
115787.12/15732.05	% SZS status Ended for HL406180+5.p
115790.04/15732.39	% SZS status Started for HL406180+4.p
115790.04/15732.39	% SZS status GaveUp for HL406180+4.p
115790.04/15732.39	eprover: CPU time limit exceeded, terminating
115790.04/15732.39	% SZS status Ended for HL406180+4.p
115808.75/15734.70	% SZS status Started for HL406181+5.p
115808.75/15734.70	% SZS status GaveUp for HL406181+5.p
115808.75/15734.70	% SZS status Ended for HL406181+5.p
115812.09/15735.14	% SZS status Started for HL406181+4.p
115812.09/15735.14	% SZS status GaveUp for HL406181+4.p
115812.09/15735.14	eprover: CPU time limit exceeded, terminating
115812.09/15735.14	% SZS status Ended for HL406181+4.p
115821.51/15736.30	% SZS status Started for HL406182+5.p
115821.51/15736.30	% SZS status GaveUp for HL406182+5.p
115821.51/15736.30	% SZS status Ended for HL406182+5.p
115823.47/15736.73	% SZS status Started for HL406182+4.p
115823.47/15736.73	% SZS status GaveUp for HL406182+4.p
115823.47/15736.73	eprover: CPU time limit exceeded, terminating
115823.47/15736.73	% SZS status Ended for HL406182+4.p
115849.74/15739.94	% SZS status Started for HL406183+4.p
115849.74/15739.94	% SZS status GaveUp for HL406183+4.p
115849.74/15739.94	eprover: CPU time limit exceeded, terminating
115849.74/15739.94	% SZS status Ended for HL406183+4.p
115851.63/15740.24	% SZS status Started for HL406183+5.p
115851.63/15740.24	% SZS status GaveUp for HL406183+5.p
115851.63/15740.24	% SZS status Ended for HL406183+5.p
115868.80/15742.32	% SZS status Started for HL406184+5.p
115868.80/15742.32	% SZS status GaveUp for HL406184+5.p
115868.80/15742.32	% SZS status Ended for HL406184+5.p
115868.80/15742.37	% SZS status Started for HL406184+4.p
115868.80/15742.37	% SZS status GaveUp for HL406184+4.p
115868.80/15742.37	eprover: CPU time limit exceeded, terminating
115868.80/15742.37	% SZS status Ended for HL406184+4.p
115888.91/15744.94	% SZS status Started for HL406185+5.p
115888.91/15744.94	% SZS status GaveUp for HL406185+5.p
115888.91/15744.94	% SZS status Ended for HL406185+5.p
115895.98/15745.74	% SZS status Started for HL406185+4.p
115895.98/15745.74	% SZS status GaveUp for HL406185+4.p
115895.98/15745.74	eprover: CPU time limit exceeded, terminating
115895.98/15745.74	% SZS status Ended for HL406185+4.p
115901.21/15746.40	% SZS status Started for HL406186+5.p
115901.21/15746.40	% SZS status GaveUp for HL406186+5.p
115901.21/15746.40	% SZS status Ended for HL406186+5.p
115902.77/15746.68	% SZS status Started for HL406186+4.p
115902.77/15746.68	% SZS status GaveUp for HL406186+4.p
115902.77/15746.68	eprover: CPU time limit exceeded, terminating
115902.77/15746.68	% SZS status Ended for HL406186+4.p
115928.70/15749.88	% SZS status Started for HL406187+5.p
115928.70/15749.88	% SZS status GaveUp for HL406187+5.p
115928.70/15749.88	% SZS status Ended for HL406187+5.p
115933.39/15750.48	% SZS status Started for HL406187+4.p
115933.39/15750.48	% SZS status GaveUp for HL406187+4.p
115933.39/15750.48	eprover: CPU time limit exceeded, terminating
115933.39/15750.48	% SZS status Ended for HL406187+4.p
115949.41/15752.45	% SZS status Started for HL406190+5.p
115949.41/15752.45	% SZS status GaveUp for HL406190+5.p
115949.41/15752.45	% SZS status Ended for HL406190+5.p
115950.72/15752.66	% SZS status Started for HL406190+4.p
115950.72/15752.66	% SZS status GaveUp for HL406190+4.p
115950.72/15752.66	eprover: CPU time limit exceeded, terminating
115950.72/15752.66	% SZS status Ended for HL406190+4.p
115972.24/15755.34	% SZS status Started for HL406191+5.p
115972.24/15755.34	% SZS status GaveUp for HL406191+5.p
115972.24/15755.34	% SZS status Ended for HL406191+5.p
115973.07/15755.48	% SZS status Started for HL406191+4.p
115973.07/15755.48	% SZS status GaveUp for HL406191+4.p
115973.07/15755.48	eprover: CPU time limit exceeded, terminating
115973.07/15755.48	% SZS status Ended for HL406191+4.p
115979.06/15756.35	% SZS status Started for HL406192+5.p
115979.06/15756.35	% SZS status GaveUp for HL406192+5.p
115979.06/15756.35	% SZS status Ended for HL406192+5.p
115984.04/15756.83	% SZS status Started for HL406192+4.p
115984.04/15756.83	% SZS status GaveUp for HL406192+4.p
115984.04/15756.83	eprover: CPU time limit exceeded, terminating
115984.04/15756.83	% SZS status Ended for HL406192+4.p
116009.43/15760.00	% SZS status Started for HL406193+5.p
116009.43/15760.00	% SZS status GaveUp for HL406193+5.p
116009.43/15760.00	% SZS status Ended for HL406193+5.p
116011.08/15760.32	% SZS status Started for HL406193+4.p
116011.08/15760.32	% SZS status GaveUp for HL406193+4.p
116011.08/15760.32	eprover: CPU time limit exceeded, terminating
116011.08/15760.32	% SZS status Ended for HL406193+4.p
116028.16/15762.41	% SZS status Started for HL406194+5.p
116028.16/15762.41	% SZS status GaveUp for HL406194+5.p
116028.16/15762.41	% SZS status Ended for HL406194+5.p
116029.62/15762.72	% SZS status Started for HL406194+4.p
116029.62/15762.72	% SZS status GaveUp for HL406194+4.p
116029.62/15762.72	eprover: CPU time limit exceeded, terminating
116029.62/15762.72	% SZS status Ended for HL406194+4.p
116050.09/15765.17	% SZS status Started for HL406195+5.p
116050.09/15765.17	% SZS status GaveUp for HL406195+5.p
116050.09/15765.17	% SZS status Ended for HL406195+5.p
116054.05/15765.63	% SZS status Started for HL406195+4.p
116054.05/15765.63	% SZS status GaveUp for HL406195+4.p
116054.05/15765.63	eprover: CPU time limit exceeded, terminating
116054.05/15765.63	% SZS status Ended for HL406195+4.p
116058.53/15766.24	% SZS status Started for HL406197+5.p
116058.53/15766.24	% SZS status GaveUp for HL406197+5.p
116058.53/15766.24	% SZS status Ended for HL406197+5.p
116062.81/15766.73	% SZS status Started for HL406197+4.p
116062.81/15766.73	% SZS status GaveUp for HL406197+4.p
116062.81/15766.73	eprover: CPU time limit exceeded, terminating
116062.81/15766.73	% SZS status Ended for HL406197+4.p
116089.46/15770.18	% SZS status Started for HL406198+5.p
116089.46/15770.18	% SZS status GaveUp for HL406198+5.p
116089.46/15770.18	% SZS status Ended for HL406198+5.p
116090.73/15770.30	% SZS status Started for HL406198+4.p
116090.73/15770.30	% SZS status GaveUp for HL406198+4.p
116090.73/15770.30	eprover: CPU time limit exceeded, terminating
116090.73/15770.30	% SZS status Ended for HL406198+4.p
116108.38/15772.57	% SZS status Started for HL406199+5.p
116108.38/15772.57	% SZS status GaveUp for HL406199+5.p
116108.38/15772.57	% SZS status Ended for HL406199+5.p
116111.04/15772.89	% SZS status Started for HL406199+4.p
116111.04/15772.89	% SZS status GaveUp for HL406199+4.p
116111.04/15772.89	eprover: CPU time limit exceeded, terminating
116111.04/15772.89	% SZS status Ended for HL406199+4.p
116131.60/15775.43	% SZS status Started for HL406200+5.p
116131.60/15775.43	% SZS status GaveUp for HL406200+5.p
116131.60/15775.43	% SZS status Ended for HL406200+5.p
116131.84/15775.49	% SZS status Started for HL406200+4.p
116131.84/15775.49	% SZS status GaveUp for HL406200+4.p
116131.84/15775.49	eprover: CPU time limit exceeded, terminating
116131.84/15775.49	% SZS status Ended for HL406200+4.p
116139.71/15776.38	% SZS status Started for HL406201+5.p
116139.71/15776.38	% SZS status GaveUp for HL406201+5.p
116139.71/15776.38	% SZS status Ended for HL406201+5.p
116144.67/15777.07	% SZS status Started for HL406201+4.p
116144.67/15777.07	% SZS status GaveUp for HL406201+4.p
116144.67/15777.07	eprover: CPU time limit exceeded, terminating
116144.67/15777.07	% SZS status Ended for HL406201+4.p
116168.93/15780.14	% SZS status Started for HL406202+5.p
116168.93/15780.14	% SZS status GaveUp for HL406202+5.p
116168.93/15780.14	% SZS status Ended for HL406202+5.p
116172.67/15780.54	% SZS status Started for HL406202+4.p
116172.67/15780.54	% SZS status GaveUp for HL406202+4.p
116172.67/15780.54	eprover: CPU time limit exceeded, terminating
116172.67/15780.54	% SZS status Ended for HL406202+4.p
116186.12/15782.24	% SZS status Started for HL406203+5.p
116186.12/15782.24	% SZS status GaveUp for HL406203+5.p
116186.12/15782.24	% SZS status Ended for HL406203+5.p
116190.80/15782.86	% SZS status Started for HL406203+4.p
116190.80/15782.86	% SZS status GaveUp for HL406203+4.p
116190.80/15782.86	eprover: CPU time limit exceeded, terminating
116190.80/15782.86	% SZS status Ended for HL406203+4.p
116206.38/15784.93	% SZS status Started for HL406204+5.p
116206.38/15784.93	% SZS status GaveUp for HL406204+5.p
116206.38/15784.93	% SZS status Ended for HL406204+5.p
116213.15/15785.68	% SZS status Started for HL406204+4.p
116213.15/15785.68	% SZS status GaveUp for HL406204+4.p
116213.15/15785.68	eprover: CPU time limit exceeded, terminating
116213.15/15785.68	% SZS status Ended for HL406204+4.p
116223.00/15786.87	% SZS status Started for HL406205+5.p
116223.00/15786.87	% SZS status GaveUp for HL406205+5.p
116223.00/15786.87	% SZS status Ended for HL406205+5.p
116224.20/15787.10	% SZS status Started for HL406205+4.p
116224.20/15787.10	% SZS status GaveUp for HL406205+4.p
116224.20/15787.10	eprover: CPU time limit exceeded, terminating
116224.20/15787.10	% SZS status Ended for HL406205+4.p
116227.32/15787.41	% SZS status Started for HL406209+5.p
116227.32/15787.41	% SZS status Theorem for HL406209+5.p
116227.32/15787.41	% SZS status Ended for HL406209+5.p
116239.19/15788.99	% SZS status Started for HL406210+5.p
116239.19/15788.99	% SZS status Theorem for HL406210+5.p
116239.19/15788.99	% SZS status Ended for HL406210+5.p
116246.83/15789.90	% SZS status Started for HL406206+5.p
116246.83/15789.90	% SZS status GaveUp for HL406206+5.p
116246.83/15789.90	% SZS status Ended for HL406206+5.p
116251.20/15790.45	% SZS status Started for HL406206+4.p
116251.20/15790.45	% SZS status GaveUp for HL406206+4.p
116251.20/15790.45	eprover: CPU time limit exceeded, terminating
116251.20/15790.45	% SZS status Ended for HL406206+4.p
116265.27/15792.26	% SZS status Started for HL406207+5.p
116265.27/15792.26	% SZS status GaveUp for HL406207+5.p
116265.27/15792.26	% SZS status Ended for HL406207+5.p
116269.87/15792.76	% SZS status Started for HL406207+4.p
116269.87/15792.76	% SZS status GaveUp for HL406207+4.p
116269.87/15792.76	eprover: CPU time limit exceeded, terminating
116269.87/15792.76	% SZS status Ended for HL406207+4.p
116289.52/15795.33	% SZS status Started for HL406209+4.p
116289.52/15795.33	% SZS status GaveUp for HL406209+4.p
116289.52/15795.33	eprover: CPU time limit exceeded, terminating
116289.52/15795.33	% SZS status Ended for HL406209+4.p
116304.70/15797.18	% SZS status Started for HL406210+4.p
116304.70/15797.18	% SZS status GaveUp for HL406210+4.p
116304.70/15797.18	eprover: CPU time limit exceeded, terminating
116304.70/15797.18	% SZS status Ended for HL406210+4.p
116312.05/15798.12	% SZS status Started for HL406211+4.p
116312.05/15798.12	% SZS status GaveUp for HL406211+4.p
116312.05/15798.12	eprover: CPU time limit exceeded, terminating
116312.05/15798.12	% SZS status Ended for HL406211+4.p
116316.43/15798.69	% SZS status Started for HL406211+5.p
116316.43/15798.69	% SZS status GaveUp for HL406211+5.p
116316.43/15798.69	% SZS status Ended for HL406211+5.p
116328.61/15800.26	% SZS status Started for HL406213+5.p
116328.61/15800.26	% SZS status GaveUp for HL406213+5.p
116328.61/15800.26	% SZS status Ended for HL406213+5.p
116329.62/15800.31	% SZS status Started for HL406213+4.p
116329.62/15800.31	% SZS status GaveUp for HL406213+4.p
116329.62/15800.31	eprover: CPU time limit exceeded, terminating
116329.62/15800.31	% SZS status Ended for HL406213+4.p
116347.07/15802.53	% SZS status Started for HL406216+5.p
116347.07/15802.53	% SZS status GaveUp for HL406216+5.p
116347.07/15802.53	% SZS status Ended for HL406216+5.p
116348.15/15802.70	% SZS status Started for HL406216+4.p
116348.15/15802.70	% SZS status GaveUp for HL406216+4.p
116348.15/15802.70	eprover: CPU time limit exceeded, terminating
116348.15/15802.70	% SZS status Ended for HL406216+4.p
116364.28/15804.70	% SZS status Started for HL406218+5.p
116364.28/15804.70	% SZS status Theorem for HL406218+5.p
116364.28/15804.70	% SZS status Ended for HL406218+5.p
116373.53/15805.92	% SZS status Started for HL406217+4.p
116373.53/15805.92	% SZS status GaveUp for HL406217+4.p
116373.53/15805.92	eprover: CPU time limit exceeded, terminating
116373.53/15805.92	% SZS status Ended for HL406217+4.p
116381.19/15806.83	% SZS status Started for HL406217+5.p
116381.19/15806.83	% SZS status GaveUp for HL406217+5.p
116381.19/15806.83	% SZS status Ended for HL406217+5.p
116401.30/15809.37	% SZS status Started for HL406218+4.p
116401.30/15809.37	% SZS status GaveUp for HL406218+4.p
116401.30/15809.37	eprover: CPU time limit exceeded, terminating
116401.30/15809.37	% SZS status Ended for HL406218+4.p
116411.49/15810.63	% SZS status Started for HL406219+5.p
116411.49/15810.63	% SZS status GaveUp for HL406219+5.p
116411.49/15810.63	% SZS status Ended for HL406219+5.p
116411.49/15810.64	% SZS status Started for HL406219+4.p
116411.49/15810.64	% SZS status GaveUp for HL406219+4.p
116411.49/15810.64	eprover: CPU time limit exceeded, terminating
116411.49/15810.64	% SZS status Ended for HL406219+4.p
116427.74/15812.74	% SZS status Started for HL406220+5.p
116427.74/15812.74	% SZS status GaveUp for HL406220+5.p
116427.74/15812.74	% SZS status Ended for HL406220+5.p
116430.34/15813.02	% SZS status Started for HL406220+4.p
116430.34/15813.02	% SZS status GaveUp for HL406220+4.p
116430.34/15813.02	eprover: CPU time limit exceeded, terminating
116430.34/15813.02	% SZS status Ended for HL406220+4.p
116445.72/15815.01	% SZS status Started for HL406221+4.p
116445.72/15815.01	% SZS status GaveUp for HL406221+4.p
116445.72/15815.01	eprover: CPU time limit exceeded, terminating
116445.72/15815.01	% SZS status Ended for HL406221+4.p
116451.72/15815.69	% SZS status Started for HL406221+5.p
116451.72/15815.69	% SZS status GaveUp for HL406221+5.p
116451.72/15815.69	% SZS status Ended for HL406221+5.p
116462.77/15817.17	% SZS status Started for HL406223+4.p
116462.77/15817.17	% SZS status GaveUp for HL406223+4.p
116462.77/15817.17	eprover: CPU time limit exceeded, terminating
116462.77/15817.17	% SZS status Ended for HL406223+4.p
116478.64/15819.12	% SZS status Started for HL406223+5.p
116478.64/15819.12	% SZS status GaveUp for HL406223+5.p
116478.64/15819.12	% SZS status Ended for HL406223+5.p
116488.55/15820.32	% SZS status Started for HL406224+5.p
116488.55/15820.32	% SZS status GaveUp for HL406224+5.p
116488.55/15820.32	% SZS status Ended for HL406224+5.p
116493.58/15820.92	% SZS status Started for HL406224+4.p
116493.58/15820.92	% SZS status GaveUp for HL406224+4.p
116493.58/15820.92	eprover: CPU time limit exceeded, terminating
116493.58/15820.92	% SZS status Ended for HL406224+4.p
116506.46/15822.62	% SZS status Started for HL406225+5.p
116506.46/15822.62	% SZS status GaveUp for HL406225+5.p
116506.46/15822.62	% SZS status Ended for HL406225+5.p
116506.78/15822.66	% SZS status Started for HL406226+5.p
116506.78/15822.66	% SZS status Theorem for HL406226+5.p
116506.78/15822.66	% SZS status Ended for HL406226+5.p
116509.76/15823.01	% SZS status Started for HL406225+4.p
116509.76/15823.01	% SZS status GaveUp for HL406225+4.p
116509.76/15823.01	eprover: CPU time limit exceeded, terminating
116509.76/15823.01	% SZS status Ended for HL406225+4.p
116530.57/15825.60	% SZS status Started for HL406226+4.p
116530.57/15825.60	% SZS status GaveUp for HL406226+4.p
116530.57/15825.60	eprover: CPU time limit exceeded, terminating
116530.57/15825.60	% SZS status Ended for HL406226+4.p
116545.04/15827.44	% SZS status Started for HL406227+4.p
116545.04/15827.44	% SZS status GaveUp for HL406227+4.p
116545.04/15827.44	eprover: CPU time limit exceeded, terminating
116545.04/15827.44	% SZS status Ended for HL406227+4.p
116555.08/15828.83	% SZS status Started for HL406227+5.p
116555.08/15828.83	% SZS status GaveUp for HL406227+5.p
116555.08/15828.83	% SZS status Ended for HL406227+5.p
116570.38/15830.61	% SZS status Started for HL406228+5.p
116570.38/15830.61	% SZS status GaveUp for HL406228+5.p
116570.38/15830.61	% SZS status Ended for HL406228+5.p
116570.38/15830.64	% SZS status Started for HL406228+4.p
116570.38/15830.64	% SZS status GaveUp for HL406228+4.p
116570.38/15830.64	eprover: CPU time limit exceeded, terminating
116570.38/15830.64	% SZS status Ended for HL406228+4.p
116584.27/15832.39	% SZS status Started for HL406229+5.p
116584.27/15832.39	% SZS status GaveUp for HL406229+5.p
116584.27/15832.39	% SZS status Ended for HL406229+5.p
116587.41/15832.75	% SZS status Started for HL406230+5.p
116587.41/15832.75	% SZS status Theorem for HL406230+5.p
116587.41/15832.75	% SZS status Ended for HL406230+5.p
116588.19/15832.89	% SZS status Started for HL406229+4.p
116588.19/15832.89	% SZS status GaveUp for HL406229+4.p
116588.19/15832.89	eprover: CPU time limit exceeded, terminating
116588.19/15832.89	% SZS status Ended for HL406229+4.p
116591.72/15833.34	% SZS status Started for HL406230+4.p
116591.72/15833.34	% SZS status GaveUp for HL406230+4.p
116591.72/15833.34	eprover: CPU time limit exceeded, terminating
116591.72/15833.34	% SZS status Ended for HL406230+4.p
116627.25/15837.81	% SZS status Started for HL406231+4.p
116627.25/15837.81	% SZS status GaveUp for HL406231+4.p
116627.25/15837.81	eprover: CPU time limit exceeded, terminating
116627.25/15837.81	% SZS status Ended for HL406231+4.p
116633.47/15838.71	% SZS status Started for HL406231+5.p
116633.47/15838.71	% SZS status GaveUp for HL406231+5.p
116633.47/15838.71	% SZS status Ended for HL406231+5.p
116650.33/15840.68	% SZS status Started for HL406234+5.p
116650.33/15840.68	% SZS status Theorem for HL406234+5.p
116650.33/15840.68	% SZS status Ended for HL406234+5.p
116650.59/15840.70	% SZS status Started for HL406232+5.p
116650.59/15840.70	% SZS status GaveUp for HL406232+5.p
116650.59/15840.70	% SZS status Ended for HL406232+5.p
116651.69/15840.92	% SZS status Started for HL406232+4.p
116651.69/15840.92	% SZS status GaveUp for HL406232+4.p
116651.69/15840.92	eprover: CPU time limit exceeded, terminating
116651.69/15840.92	% SZS status Ended for HL406232+4.p
116663.51/15842.39	% SZS status Started for HL406233+5.p
116663.51/15842.39	% SZS status GaveUp for HL406233+5.p
116663.51/15842.39	% SZS status Ended for HL406233+5.p
116667.75/15842.94	% SZS status Started for HL406233+4.p
116667.75/15842.94	% SZS status GaveUp for HL406233+4.p
116667.75/15842.94	eprover: CPU time limit exceeded, terminating
116667.75/15842.94	% SZS status Ended for HL406233+4.p
116671.27/15843.34	% SZS status Started for HL406234+4.p
116671.27/15843.34	% SZS status GaveUp for HL406234+4.p
116671.27/15843.34	eprover: CPU time limit exceeded, terminating
116671.27/15843.34	% SZS status Ended for HL406234+4.p
116708.98/15848.09	% SZS status Started for HL406235+4.p
116708.98/15848.09	% SZS status GaveUp for HL406235+4.p
116708.98/15848.09	eprover: CPU time limit exceeded, terminating
116708.98/15848.09	% SZS status Ended for HL406235+4.p
116712.09/15848.49	% SZS status Started for HL406235+5.p
116712.09/15848.49	% SZS status GaveUp for HL406235+5.p
116712.09/15848.49	% SZS status Ended for HL406235+5.p
116726.77/15850.33	% SZS status Started for HL406238+5.p
116726.77/15850.33	% SZS status Theorem for HL406238+5.p
116726.77/15850.33	% SZS status Ended for HL406238+5.p
116727.33/15850.45	% SZS status Started for HL406236+5.p
116727.33/15850.45	% SZS status GaveUp for HL406236+5.p
116727.33/15850.45	% SZS status Ended for HL406236+5.p
116731.93/15851.02	% SZS status Started for HL406236+4.p
116731.93/15851.02	% SZS status GaveUp for HL406236+4.p
116731.93/15851.02	eprover: CPU time limit exceeded, terminating
116731.93/15851.02	% SZS status Ended for HL406236+4.p
116734.25/15851.26	% SZS status Started for HL406237+4.p
116734.25/15851.26	% SZS status GaveUp for HL406237+4.p
116734.25/15851.26	eprover: CPU time limit exceeded, terminating
116734.25/15851.26	% SZS status Ended for HL406237+4.p
116743.78/15852.55	% SZS status Started for HL406237+5.p
116743.78/15852.55	% SZS status GaveUp for HL406237+5.p
116743.78/15852.55	% SZS status Ended for HL406237+5.p
116750.09/15853.28	% SZS status Started for HL406238+4.p
116750.09/15853.28	% SZS status GaveUp for HL406238+4.p
116750.09/15853.28	eprover: CPU time limit exceeded, terminating
116750.09/15853.28	% SZS status Ended for HL406238+4.p
116787.80/15858.15	% SZS status Started for HL406239+5.p
116787.80/15858.15	% SZS status GaveUp for HL406239+5.p
116787.80/15858.15	% SZS status Ended for HL406239+5.p
116790.99/15858.41	% SZS status Started for HL406239+4.p
116790.99/15858.41	% SZS status GaveUp for HL406239+4.p
116790.99/15858.41	eprover: CPU time limit exceeded, terminating
116790.99/15858.41	% SZS status Ended for HL406239+4.p
116806.28/15860.35	% SZS status Started for HL406242+5.p
116806.28/15860.35	% SZS status Theorem for HL406242+5.p
116806.28/15860.35	% SZS status Ended for HL406242+5.p
116815.38/15860.64	% SZS status Started for HL406240+5.p
116815.38/15860.64	% SZS status GaveUp for HL406240+5.p
116815.38/15860.64	% SZS status Ended for HL406240+5.p
116816.48/15860.79	% SZS status Started for HL406240+4.p
116816.48/15860.79	% SZS status GaveUp for HL406240+4.p
116816.48/15860.79	eprover: CPU time limit exceeded, terminating
116816.48/15860.79	% SZS status Ended for HL406240+4.p
116817.05/15860.92	% SZS status Started for HL406241+5.p
116817.05/15860.92	% SZS status GaveUp for HL406241+5.p
116817.05/15860.92	% SZS status Ended for HL406241+5.p
116821.10/15861.34	% SZS status Started for HL406241+4.p
116821.10/15861.34	% SZS status GaveUp for HL406241+4.p
116821.10/15861.34	eprover: CPU time limit exceeded, terminating
116821.10/15861.34	% SZS status Ended for HL406241+4.p
116833.91/15862.96	% SZS status Started for HL406242+4.p
116833.91/15862.96	% SZS status GaveUp for HL406242+4.p
116833.91/15862.96	eprover: CPU time limit exceeded, terminating
116833.91/15862.96	% SZS status Ended for HL406242+4.p
116872.63/15867.93	% SZS status Started for HL406246+5.p
116872.63/15867.93	% SZS status Theorem for HL406246+5.p
116872.63/15867.93	% SZS status Ended for HL406246+5.p
116873.62/15868.12	% SZS status Started for HL406243+5.p
116873.62/15868.12	% SZS status GaveUp for HL406243+5.p
116873.62/15868.12	% SZS status Ended for HL406243+5.p
116880.41/15868.84	% SZS status Started for HL406243+4.p
116880.41/15868.84	% SZS status GaveUp for HL406243+4.p
116880.41/15868.84	eprover: CPU time limit exceeded, terminating
116880.41/15868.84	% SZS status Ended for HL406243+4.p
116891.63/15870.32	% SZS status Started for HL406244+5.p
116891.63/15870.32	% SZS status GaveUp for HL406244+5.p
116891.63/15870.32	% SZS status Ended for HL406244+5.p
116898.90/15871.21	% SZS status Started for HL406244+4.p
116898.90/15871.21	% SZS status GaveUp for HL406244+4.p
116898.90/15871.21	eprover: CPU time limit exceeded, terminating
116898.90/15871.21	% SZS status Ended for HL406244+4.p
116900.44/15871.50	% SZS status Started for HL406246+4.p
116900.44/15871.50	% SZS status GaveUp for HL406246+4.p
116900.44/15871.50	eprover: CPU time limit exceeded, terminating
116900.44/15871.50	% SZS status Ended for HL406246+4.p
116903.44/15871.79	% SZS status Started for HL406247+4.p
116903.44/15871.79	% SZS status GaveUp for HL406247+4.p
116903.44/15871.79	eprover: CPU time limit exceeded, terminating
116903.44/15871.79	% SZS status Ended for HL406247+4.p
116909.78/15872.58	% SZS status Started for HL406247+5.p
116909.78/15872.58	% SZS status GaveUp for HL406247+5.p
116909.78/15872.58	% SZS status Ended for HL406247+5.p
116929.37/15875.07	% SZS status Started for HL406250+5.p
116929.37/15875.07	% SZS status Theorem for HL406250+5.p
116929.37/15875.07	% SZS status Ended for HL406250+5.p
116955.12/15878.30	% SZS status Started for HL406250+4.p
116955.12/15878.30	% SZS status GaveUp for HL406250+4.p
116955.12/15878.30	eprover: CPU time limit exceeded, terminating
116955.12/15878.30	% SZS status Ended for HL406250+4.p
116962.56/15879.26	% SZS status Started for HL406251+4.p
116962.56/15879.26	% SZS status GaveUp for HL406251+4.p
116962.56/15879.26	eprover: CPU time limit exceeded, terminating
116962.56/15879.26	% SZS status Ended for HL406251+4.p
116970.56/15880.22	% SZS status Started for HL406251+5.p
116970.56/15880.22	% SZS status GaveUp for HL406251+5.p
116970.56/15880.22	% SZS status Ended for HL406251+5.p
116977.74/15881.10	% SZS status Started for HL406252+5.p
116977.74/15881.10	% SZS status GaveUp for HL406252+5.p
116977.74/15881.10	% SZS status Ended for HL406252+5.p
116979.89/15881.53	% SZS status Started for HL406252+4.p
116979.89/15881.53	% SZS status GaveUp for HL406252+4.p
116979.89/15881.53	eprover: CPU time limit exceeded, terminating
116979.89/15881.53	% SZS status Ended for HL406252+4.p
116986.01/15882.19	% SZS status Started for HL406253+5.p
116986.01/15882.19	% SZS status GaveUp for HL406253+5.p
116986.01/15882.19	% SZS status Ended for HL406253+5.p
116986.65/15882.24	% SZS status Started for HL406253+4.p
116986.65/15882.24	% SZS status GaveUp for HL406253+4.p
116986.65/15882.24	eprover: CPU time limit exceeded, terminating
116986.65/15882.24	% SZS status Ended for HL406253+4.p
117011.91/15885.43	% SZS status Started for HL406254+4.p
117011.91/15885.43	% SZS status GaveUp for HL406254+4.p
117011.91/15885.43	eprover: CPU time limit exceeded, terminating
117011.91/15885.43	% SZS status Ended for HL406254+4.p
117014.95/15885.81	% SZS status Started for HL406254+5.p
117014.95/15885.81	% SZS status Theorem for HL406254+5.p
117014.95/15885.81	% SZS status Ended for HL406254+5.p
117043.61/15889.55	% SZS status Started for HL406255+4.p
117043.61/15889.55	% SZS status GaveUp for HL406255+4.p
117043.61/15889.55	eprover: CPU time limit exceeded, terminating
117043.61/15889.55	% SZS status Ended for HL406255+4.p
117047.73/15889.95	% SZS status Started for HL406255+5.p
117047.73/15889.95	% SZS status GaveUp for HL406255+5.p
117047.73/15889.95	% SZS status Ended for HL406255+5.p
117057.26/15891.18	% SZS status Started for HL406256+5.p
117057.26/15891.18	% SZS status GaveUp for HL406256+5.p
117057.26/15891.18	% SZS status Ended for HL406256+5.p
117059.43/15891.39	% SZS status Started for HL406256+4.p
117059.43/15891.39	% SZS status GaveUp for HL406256+4.p
117059.43/15891.39	eprover: CPU time limit exceeded, terminating
117059.43/15891.39	% SZS status Ended for HL406256+4.p
117067.34/15892.43	% SZS status Started for HL406257+5.p
117067.34/15892.43	% SZS status GaveUp for HL406257+5.p
117067.34/15892.43	% SZS status Ended for HL406257+5.p
117068.72/15892.56	% SZS status Started for HL406257+4.p
117068.72/15892.56	% SZS status GaveUp for HL406257+4.p
117068.72/15892.56	eprover: CPU time limit exceeded, terminating
117068.72/15892.56	% SZS status Ended for HL406257+4.p
117091.38/15895.48	% SZS status Started for HL406259+5.p
117091.38/15895.48	% SZS status GaveUp for HL406259+5.p
117091.38/15895.48	% SZS status Ended for HL406259+5.p
117093.93/15895.92	% SZS status Started for HL406259+4.p
117093.93/15895.92	% SZS status GaveUp for HL406259+4.p
117093.93/15895.92	eprover: CPU time limit exceeded, terminating
117093.93/15895.92	% SZS status Ended for HL406259+4.p
117114.80/15898.58	% SZS status Started for HL406262+5.p
117114.80/15898.58	% SZS status Theorem for HL406262+5.p
117114.80/15898.58	% SZS status Ended for HL406262+5.p
117125.47/15899.78	% SZS status Started for HL406260+5.p
117125.47/15899.78	% SZS status GaveUp for HL406260+5.p
117125.47/15899.78	% SZS status Ended for HL406260+5.p
117130.71/15900.40	% SZS status Started for HL406260+4.p
117130.71/15900.40	% SZS status GaveUp for HL406260+4.p
117130.71/15900.40	eprover: CPU time limit exceeded, terminating
117130.71/15900.40	% SZS status Ended for HL406260+4.p
117139.66/15901.56	% SZS status Started for HL406262+4.p
117139.66/15901.56	% SZS status GaveUp for HL406262+4.p
117139.66/15901.56	eprover: CPU time limit exceeded, terminating
117139.66/15901.56	% SZS status Ended for HL406262+4.p
117144.87/15902.24	% SZS status Started for HL406263+5.p
117144.87/15902.24	% SZS status GaveUp for HL406263+5.p
117144.87/15902.24	% SZS status Ended for HL406263+5.p
117149.30/15902.86	% SZS status Started for HL406263+4.p
117149.30/15902.86	% SZS status GaveUp for HL406263+4.p
117149.30/15902.86	eprover: CPU time limit exceeded, terminating
117149.30/15902.86	% SZS status Ended for HL406263+4.p
117171.04/15905.59	% SZS status Started for HL406264+5.p
117171.04/15905.59	% SZS status GaveUp for HL406264+5.p
117171.04/15905.59	% SZS status Ended for HL406264+5.p
117174.59/15905.95	% SZS status Started for HL406264+4.p
117174.59/15905.95	% SZS status GaveUp for HL406264+4.p
117174.59/15905.95	eprover: CPU time limit exceeded, terminating
117174.59/15905.95	% SZS status Ended for HL406264+4.p
117195.74/15908.64	% SZS status Started for HL406266+5.p
117195.74/15908.64	% SZS status Theorem for HL406266+5.p
117195.74/15908.64	% SZS status Ended for HL406266+5.p
117201.12/15909.30	% SZS status Started for HL406265+4.p
117201.12/15909.30	% SZS status GaveUp for HL406265+4.p
117201.12/15909.30	eprover: CPU time limit exceeded, terminating
117201.12/15909.30	% SZS status Ended for HL406265+4.p
117202.90/15909.57	% SZS status Started for HL406265+5.p
117202.90/15909.57	% SZS status GaveUp for HL406265+5.p
117202.90/15909.57	% SZS status Ended for HL406265+5.p
117212.73/15910.74	% SZS status Started for HL406266+4.p
117212.73/15910.74	% SZS status GaveUp for HL406266+4.p
117212.73/15910.74	eprover: CPU time limit exceeded, terminating
117212.73/15910.74	% SZS status Ended for HL406266+4.p
117229.20/15912.82	% SZS status Started for HL406267+4.p
117229.20/15912.82	% SZS status GaveUp for HL406267+4.p
117229.20/15912.82	eprover: CPU time limit exceeded, terminating
117229.20/15912.82	% SZS status Ended for HL406267+4.p
117229.43/15912.84	% SZS status Started for HL406267+5.p
117229.43/15912.84	% SZS status GaveUp for HL406267+5.p
117229.43/15912.84	% SZS status Ended for HL406267+5.p
117253.88/15916.01	% SZS status Started for HL406268+5.p
117253.88/15916.01	% SZS status GaveUp for HL406268+5.p
117253.88/15916.01	% SZS status Ended for HL406268+5.p
117255.65/15916.21	% SZS status Started for HL406268+4.p
117255.65/15916.21	% SZS status GaveUp for HL406268+4.p
117255.65/15916.21	eprover: CPU time limit exceeded, terminating
117255.65/15916.21	% SZS status Ended for HL406268+4.p
117269.47/15917.91	% SZS status Started for HL406270+5.p
117269.47/15917.91	% SZS status Theorem for HL406270+5.p
117269.47/15917.91	% SZS status Ended for HL406270+5.p
117277.54/15918.91	% SZS status Started for HL406269+5.p
117277.54/15918.91	% SZS status GaveUp for HL406269+5.p
117277.54/15918.91	% SZS status Ended for HL406269+5.p
117278.89/15919.17	% SZS status Started for HL406269+4.p
117278.89/15919.17	% SZS status GaveUp for HL406269+4.p
117278.89/15919.17	eprover: CPU time limit exceeded, terminating
117278.89/15919.17	% SZS status Ended for HL406269+4.p
117285.05/15919.91	% SZS status Started for HL406270+4.p
117285.05/15919.91	% SZS status GaveUp for HL406270+4.p
117285.05/15919.91	eprover: CPU time limit exceeded, terminating
117285.05/15919.91	% SZS status Ended for HL406270+4.p
117309.52/15923.01	% SZS status Started for HL406271+5.p
117309.52/15923.01	% SZS status GaveUp for HL406271+5.p
117309.52/15923.01	% SZS status Ended for HL406271+5.p
117310.10/15923.11	% SZS status Started for HL406271+4.p
117310.10/15923.11	% SZS status GaveUp for HL406271+4.p
117310.10/15923.11	eprover: CPU time limit exceeded, terminating
117310.10/15923.11	% SZS status Ended for HL406271+4.p
117331.27/15925.86	% SZS status Started for HL406273+5.p
117331.27/15925.86	% SZS status GaveUp for HL406273+5.p
117331.27/15925.86	% SZS status Ended for HL406273+5.p
117334.30/15926.09	% SZS status Started for HL406274+5.p
117334.30/15926.09	% SZS status Theorem for HL406274+5.p
117334.30/15926.09	% SZS status Ended for HL406274+5.p
117342.04/15927.10	% SZS status Started for HL406273+4.p
117342.04/15927.10	% SZS status GaveUp for HL406273+4.p
117342.04/15927.10	eprover: CPU time limit exceeded, terminating
117342.04/15927.10	% SZS status Ended for HL406273+4.p
117353.39/15928.55	% SZS status Started for HL406274+4.p
117353.39/15928.55	% SZS status GaveUp for HL406274+4.p
117353.39/15928.55	eprover: CPU time limit exceeded, terminating
117353.39/15928.55	% SZS status Ended for HL406274+4.p
117360.84/15929.47	% SZS status Started for HL406275+4.p
117360.84/15929.47	% SZS status GaveUp for HL406275+4.p
117360.84/15929.47	eprover: CPU time limit exceeded, terminating
117360.84/15929.47	% SZS status Ended for HL406275+4.p
117370.48/15930.83	% SZS status Started for HL406275+5.p
117370.48/15930.83	% SZS status GaveUp for HL406275+5.p
117370.48/15930.83	% SZS status Ended for HL406275+5.p
117392.27/15933.40	% SZS status Started for HL406276+4.p
117392.27/15933.40	% SZS status GaveUp for HL406276+4.p
117392.27/15933.40	eprover: CPU time limit exceeded, terminating
117392.27/15933.40	% SZS status Ended for HL406276+4.p
117395.27/15933.74	% SZS status Started for HL406276+5.p
117395.27/15933.74	% SZS status GaveUp for HL406276+5.p
117395.27/15933.74	% SZS status Ended for HL406276+5.p
117410.41/15935.87	% SZS status Started for HL406277+5.p
117410.41/15935.87	% SZS status GaveUp for HL406277+5.p
117410.41/15935.87	% SZS status Ended for HL406277+5.p
117415.99/15936.41	% SZS status Started for HL406277+4.p
117415.99/15936.41	% SZS status GaveUp for HL406277+4.p
117415.99/15936.41	eprover: CPU time limit exceeded, terminating
117415.99/15936.41	% SZS status Ended for HL406277+4.p
117424.08/15937.45	% SZS status Started for HL406279+4.p
117424.08/15937.45	% SZS status GaveUp for HL406279+4.p
117424.08/15937.45	eprover: CPU time limit exceeded, terminating
117424.08/15937.45	% SZS status Ended for HL406279+4.p
117438.07/15939.18	% SZS status Started for HL406279+5.p
117438.07/15939.18	% SZS status GaveUp for HL406279+5.p
117438.07/15939.18	% SZS status Ended for HL406279+5.p
117446.48/15940.20	% SZS status Started for HL406280+4.p
117446.48/15940.20	% SZS status GaveUp for HL406280+4.p
117446.48/15940.20	eprover: CPU time limit exceeded, terminating
117446.48/15940.20	% SZS status Ended for HL406280+4.p
117462.06/15942.19	% SZS status Started for HL406280+5.p
117462.06/15942.19	% SZS status GaveUp for HL406280+5.p
117462.06/15942.19	% SZS status Ended for HL406280+5.p
117471.46/15943.44	% SZS status Started for HL406281+5.p
117471.46/15943.44	% SZS status GaveUp for HL406281+5.p
117471.46/15943.44	% SZS status Ended for HL406281+5.p
117471.46/15943.47	% SZS status Started for HL406282+5.p
117471.46/15943.47	% SZS status Theorem for HL406282+5.p
117471.46/15943.47	% SZS status Ended for HL406282+5.p
117475.55/15943.94	% SZS status Started for HL406281+4.p
117475.55/15943.94	% SZS status GaveUp for HL406281+4.p
117475.55/15943.94	eprover: CPU time limit exceeded, terminating
117475.55/15943.94	% SZS status Ended for HL406281+4.p
117493.57/15946.16	% SZS status Started for HL406282+4.p
117493.57/15946.16	% SZS status GaveUp for HL406282+4.p
117493.57/15946.16	eprover: CPU time limit exceeded, terminating
117493.57/15946.16	% SZS status Ended for HL406282+4.p
117507.02/15947.81	% SZS status Started for HL406283+4.p
117507.02/15947.81	% SZS status GaveUp for HL406283+4.p
117507.02/15947.81	eprover: CPU time limit exceeded, terminating
117507.02/15947.81	% SZS status Ended for HL406283+4.p
117528.41/15950.52	% SZS status Started for HL406284+4.p
117528.41/15950.52	% SZS status GaveUp for HL406284+4.p
117528.41/15950.52	eprover: CPU time limit exceeded, terminating
117528.41/15950.52	% SZS status Ended for HL406284+4.p
117546.38/15952.84	% SZS status Started for HL406283+5.p
117546.38/15952.84	% SZS status GaveUp for HL406283+5.p
117546.38/15952.84	eprover: CPU time limit exceeded, terminating
117546.38/15952.84	% SZS status Ended for HL406283+5.p
117549.07/15953.15	% SZS status Started for HL406286+5.p
117549.07/15953.15	% SZS status Theorem for HL406286+5.p
117549.07/15953.15	% SZS status Ended for HL406286+5.p
117549.68/15953.17	% SZS status Started for HL406285+5.p
117549.68/15953.17	% SZS status GaveUp for HL406285+5.p
117549.68/15953.17	% SZS status Ended for HL406285+5.p
117554.45/15953.77	% SZS status Started for HL406285+4.p
117554.45/15953.77	% SZS status GaveUp for HL406285+4.p
117554.45/15953.77	eprover: CPU time limit exceeded, terminating
117554.45/15953.77	% SZS status Ended for HL406285+4.p
117560.57/15954.64	% SZS status Started for HL406286+4.p
117560.57/15954.64	% SZS status GaveUp for HL406286+4.p
117560.57/15954.64	eprover: CPU time limit exceeded, terminating
117560.57/15954.64	% SZS status Ended for HL406286+4.p
117570.48/15955.87	% SZS status Started for HL406284+5.p
117570.48/15955.87	% SZS status GaveUp for HL406284+5.p
117570.48/15955.87	eprover: CPU time limit exceeded, terminating
117570.48/15955.87	% SZS status Ended for HL406284+5.p
117588.73/15958.12	% SZS status Started for HL406287+4.p
117588.73/15958.12	% SZS status GaveUp for HL406287+4.p
117588.73/15958.12	eprover: CPU time limit exceeded, terminating
117588.73/15958.12	% SZS status Ended for HL406287+4.p
117628.04/15963.13	% SZS status Started for HL406288+4.p
117628.04/15963.13	% SZS status GaveUp for HL406288+4.p
117628.04/15963.13	eprover: CPU time limit exceeded, terminating
117628.04/15963.13	% SZS status Ended for HL406288+4.p
117631.03/15963.44	% SZS status Started for HL406289+5.p
117631.03/15963.44	% SZS status GaveUp for HL406289+5.p
117631.03/15963.44	% SZS status Ended for HL406289+5.p
117631.03/15963.45	% SZS status Started for HL406289+4.p
117631.03/15963.45	% SZS status GaveUp for HL406289+4.p
117631.03/15963.45	eprover: CPU time limit exceeded, terminating
117631.03/15963.45	% SZS status Ended for HL406289+4.p
117637.38/15964.22	% SZS status Started for HL406287+5.p
117637.38/15964.22	% SZS status GaveUp for HL406287+5.p
117637.38/15964.22	eprover: CPU time limit exceeded, terminating
117637.38/15964.22	% SZS status Ended for HL406287+5.p
117642.95/15964.93	% SZS status Started for HL406292+4.p
117642.95/15964.93	% SZS status GaveUp for HL406292+4.p
117642.95/15964.93	eprover: CPU time limit exceeded, terminating
117642.95/15964.93	% SZS status Ended for HL406292+4.p
117657.43/15966.77	% SZS status Started for HL406288+5.p
117657.43/15966.77	% SZS status GaveUp for HL406288+5.p
117657.43/15966.77	eprover: CPU time limit exceeded, terminating
117657.43/15966.77	% SZS status Ended for HL406288+5.p
117670.73/15968.44	% SZS status Started for HL406294+4.p
117670.73/15968.44	% SZS status GaveUp for HL406294+4.p
117670.73/15968.44	eprover: CPU time limit exceeded, terminating
117670.73/15968.44	% SZS status Ended for HL406294+4.p
117679.16/15969.57	% SZS status Started for HL406292+5.p
117679.16/15969.57	% SZS status GaveUp for HL406292+5.p
117679.16/15969.57	eprover: CPU time limit exceeded, terminating
117679.16/15969.57	% SZS status Ended for HL406292+5.p
117683.21/15970.21	% SZS status Started for HL406294+5.p
117683.21/15970.21	% SZS status Theorem for HL406294+5.p
117683.21/15970.21	% SZS status Ended for HL406294+5.p
117684.44/15970.31	% SZS status Started for HL406297+5.p
117684.44/15970.31	% SZS status Theorem for HL406297+5.p
117684.44/15970.31	% SZS status Ended for HL406297+5.p
117712.45/15973.78	% SZS status Started for HL406295+4.p
117712.45/15973.78	% SZS status GaveUp for HL406295+4.p
117712.45/15973.78	eprover: CPU time limit exceeded, terminating
117712.45/15973.78	% SZS status Ended for HL406295+4.p
117719.02/15974.65	% SZS status Started for HL406296+4.p
117719.02/15974.65	% SZS status GaveUp for HL406296+4.p
117719.02/15974.65	eprover: CPU time limit exceeded, terminating
117719.02/15974.65	% SZS status Ended for HL406296+4.p
117726.37/15975.46	% SZS status Started for HL406299+5.p
117726.37/15975.46	% SZS status Theorem for HL406299+5.p
117726.37/15975.46	% SZS status Ended for HL406299+5.p
117738.88/15977.10	% SZS status Started for HL406297+4.p
117738.88/15977.10	% SZS status GaveUp for HL406297+4.p
117738.88/15977.10	eprover: CPU time limit exceeded, terminating
117738.88/15977.10	% SZS status Ended for HL406297+4.p
117741.33/15977.33	% SZS status Started for HL406295+5.p
117741.33/15977.33	% SZS status GaveUp for HL406295+5.p
117741.33/15977.33	eprover: CPU time limit exceeded, terminating
117741.33/15977.33	% SZS status Ended for HL406295+5.p
117752.10/15978.69	% SZS status Started for HL406296+5.p
117752.10/15978.69	% SZS status GaveUp for HL406296+5.p
117752.10/15978.69	eprover: CPU time limit exceeded, terminating
117752.10/15978.69	% SZS status Ended for HL406296+5.p
117759.69/15979.68	% SZS status Started for HL406298+5.p
117759.69/15979.68	% SZS status GaveUp for HL406298+5.p
117759.69/15979.68	% SZS status Ended for HL406298+5.p
117763.62/15980.19	% SZS status Started for HL406298+4.p
117763.62/15980.19	% SZS status GaveUp for HL406298+4.p
117763.62/15980.19	eprover: CPU time limit exceeded, terminating
117763.62/15980.19	% SZS status Ended for HL406298+4.p
117772.73/15981.33	% SZS status Started for HL406303+5.p
117772.73/15981.33	% SZS status Theorem for HL406303+5.p
117772.73/15981.33	% SZS status Ended for HL406303+5.p
117785.30/15983.07	% SZS status Started for HL406304+5.p
117785.30/15983.07	% SZS status Theorem for HL406304+5.p
117785.30/15983.07	% SZS status Ended for HL406304+5.p
117806.71/15985.58	% SZS status Started for HL406300+5.p
117806.71/15985.58	% SZS status GaveUp for HL406300+5.p
117806.71/15985.58	% SZS status Ended for HL406300+5.p
117816.49/15986.89	% SZS status Started for HL406302+5.p
117816.49/15986.89	% SZS status GaveUp for HL406302+5.p
117816.49/15986.89	% SZS status Ended for HL406302+5.p
117824.16/15987.84	% SZS status Started for HL406302+4.p
117824.16/15987.84	% SZS status GaveUp for HL406302+4.p
117824.16/15987.84	eprover: CPU time limit exceeded, terminating
117824.16/15987.84	% SZS status Ended for HL406302+4.p
117838.43/15989.64	% SZS status Started for HL406306+5.p
117838.43/15989.64	% SZS status Theorem for HL406306+5.p
117838.43/15989.64	% SZS status Ended for HL406306+5.p
117854.62/15991.87	% SZS status Started for HL406307+5.p
117854.62/15991.87	% SZS status Theorem for HL406307+5.p
117854.62/15991.87	% SZS status Ended for HL406307+5.p
117869.13/15993.51	% SZS status Started for HL406306+4.p
117869.13/15993.51	% SZS status GaveUp for HL406306+4.p
117869.13/15993.51	eprover: CPU time limit exceeded, terminating
117869.13/15993.51	% SZS status Ended for HL406306+4.p
117871.05/15993.72	% SZS status Started for HL406309+5.p
117871.05/15993.72	% SZS status Theorem for HL406309+5.p
117871.05/15993.72	% SZS status Ended for HL406309+5.p
117893.82/15996.62	% SZS status Started for HL406299+4.p
117893.82/15996.62	% SZS status GaveUp for HL406299+4.p
117893.82/15996.62	eprover: CPU time limit exceeded, terminating
117893.82/15996.62	% SZS status Ended for HL406299+4.p
117897.82/15997.05	% SZS status Started for HL406307+4.p
117897.82/15997.05	% SZS status GaveUp for HL406307+4.p
117897.82/15997.05	eprover: CPU time limit exceeded, terminating
117897.82/15997.05	% SZS status Ended for HL406307+4.p
117922.60/16000.20	% SZS status Started for HL406309+4.p
117922.60/16000.20	% SZS status GaveUp for HL406309+4.p
117922.60/16000.20	eprover: CPU time limit exceeded, terminating
117922.60/16000.20	% SZS status Ended for HL406309+4.p
117927.87/16000.95	% SZS status Started for HL406300+4.p
117927.87/16000.95	% SZS status GaveUp for HL406300+4.p
117927.87/16000.95	eprover: CPU time limit exceeded, terminating
117927.87/16000.95	% SZS status Ended for HL406300+4.p
117947.22/16003.34	% SZS status Started for HL406312+5.p
117947.22/16003.34	% SZS status Theorem for HL406312+5.p
117947.22/16003.34	% SZS status Ended for HL406312+5.p
117947.22/16003.35	% SZS status Started for HL406310+5.p
117947.22/16003.35	% SZS status GaveUp for HL406310+5.p
117947.22/16003.35	% SZS status Ended for HL406310+5.p
117950.12/16003.74	% SZS status Started for HL406310+4.p
117950.12/16003.74	% SZS status GaveUp for HL406310+4.p
117950.12/16003.74	eprover: CPU time limit exceeded, terminating
117950.12/16003.74	% SZS status Ended for HL406310+4.p
117954.80/16004.25	% SZS status Started for HL406311+5.p
117954.80/16004.25	% SZS status Theorem for HL406311+5.p
117954.80/16004.25	% SZS status Ended for HL406311+5.p
117956.76/16004.54	% SZS status Started for HL406304+4.p
117956.76/16004.54	% SZS status GaveUp for HL406304+4.p
117956.76/16004.54	eprover: CPU time limit exceeded, terminating
117956.76/16004.54	% SZS status Ended for HL406304+4.p
117959.77/16004.91	% SZS status Started for HL406303+4.p
117959.77/16004.91	% SZS status GaveUp for HL406303+4.p
117959.77/16004.91	eprover: CPU time limit exceeded, terminating
117959.77/16004.91	% SZS status Ended for HL406303+4.p
117965.75/16005.71	% SZS status Started for HL406313+5.p
117965.75/16005.71	% SZS status Theorem for HL406313+5.p
117965.75/16005.71	% SZS status Ended for HL406313+5.p
117974.45/16006.77	% SZS status Started for HL406311+4.p
117974.45/16006.77	% SZS status GaveUp for HL406311+4.p
117974.45/16006.77	eprover: CPU time limit exceeded, terminating
117974.45/16006.77	% SZS status Ended for HL406311+4.p
117974.45/16006.79	% SZS status Started for HL406317+5.p
117974.45/16006.79	% SZS status Theorem for HL406317+5.p
117974.45/16006.79	% SZS status Ended for HL406317+5.p
117988.43/16008.58	% SZS status Started for HL406318+5.p
117988.43/16008.58	% SZS status Theorem for HL406318+5.p
117988.43/16008.58	% SZS status Ended for HL406318+5.p
118002.19/16010.29	% SZS status Started for HL406319+5.p
118002.19/16010.29	% SZS status Theorem for HL406319+5.p
118002.19/16010.29	% SZS status Ended for HL406319+5.p
118003.30/16010.39	% SZS status Started for HL406312+4.p
118003.30/16010.39	% SZS status GaveUp for HL406312+4.p
118003.30/16010.39	eprover: CPU time limit exceeded, terminating
118003.30/16010.39	% SZS status Ended for HL406312+4.p
118012.68/16011.62	% SZS status Started for HL406314+5.p
118012.68/16011.62	% SZS status Theorem for HL406314+5.p
118012.68/16011.62	% SZS status Ended for HL406314+5.p
118036.56/16014.67	% SZS status Started for HL406317+4.p
118036.56/16014.67	% SZS status GaveUp for HL406317+4.p
118036.56/16014.67	eprover: CPU time limit exceeded, terminating
118036.56/16014.67	% SZS status Ended for HL406317+4.p
118047.28/16016.00	% SZS status Started for HL406318+4.p
118047.28/16016.00	% SZS status GaveUp for HL406318+4.p
118047.28/16016.00	eprover: CPU time limit exceeded, terminating
118047.28/16016.00	% SZS status Ended for HL406318+4.p
118055.27/16016.96	% SZS status Started for HL406319+4.p
118055.27/16016.96	% SZS status GaveUp for HL406319+4.p
118055.27/16016.96	eprover: CPU time limit exceeded, terminating
118055.27/16016.96	% SZS status Ended for HL406319+4.p
118079.98/16020.03	% SZS status Started for HL406320+5.p
118079.98/16020.03	% SZS status GaveUp for HL406320+5.p
118079.98/16020.03	% SZS status Ended for HL406320+5.p
118082.74/16020.47	% SZS status Started for HL406320+4.p
118082.74/16020.47	% SZS status GaveUp for HL406320+4.p
118082.74/16020.47	eprover: CPU time limit exceeded, terminating
118082.74/16020.47	% SZS status Ended for HL406320+4.p
118092.71/16021.65	% SZS status Started for HL406321+5.p
118092.71/16021.65	% SZS status Theorem for HL406321+5.p
118092.71/16021.65	% SZS status Ended for HL406321+5.p
118093.70/16021.78	% SZS status Started for HL406321+4.p
118093.70/16021.78	% SZS status GaveUp for HL406321+4.p
118093.70/16021.78	eprover: CPU time limit exceeded, terminating
118093.70/16021.78	% SZS status Ended for HL406321+4.p
118106.66/16023.38	% SZS status Started for HL406323+5.p
118106.66/16023.38	% SZS status Theorem for HL406323+5.p
118106.66/16023.38	% SZS status Ended for HL406323+5.p
118108.88/16023.80	% SZS status Started for HL406322+5.p
118108.88/16023.80	% SZS status Theorem for HL406322+5.p
118108.88/16023.80	% SZS status Ended for HL406322+5.p
118120.09/16025.12	% SZS status Started for HL406324+5.p
118120.09/16025.12	% SZS status Theorem for HL406324+5.p
118120.09/16025.12	% SZS status Ended for HL406324+5.p
118133.09/16026.76	% SZS status Started for HL406322+4.p
118133.09/16026.76	% SZS status GaveUp for HL406322+4.p
118133.09/16026.76	eprover: CPU time limit exceeded, terminating
118133.09/16026.76	% SZS status Ended for HL406322+4.p
118133.81/16026.94	% SZS status Started for HL406325+5.p
118133.81/16026.94	% SZS status Theorem for HL406325+5.p
118133.81/16026.94	% SZS status Ended for HL406325+5.p
118155.70/16029.60	% SZS status Started for HL406313+4.p
118155.70/16029.60	% SZS status GaveUp for HL406313+4.p
118155.70/16029.60	eprover: CPU time limit exceeded, terminating
118155.70/16029.60	% SZS status Ended for HL406313+4.p
118156.52/16029.71	% SZS status Started for HL406326+5.p
118156.52/16029.71	% SZS status Theorem for HL406326+5.p
118156.52/16029.71	% SZS status Ended for HL406326+5.p
118160.89/16030.23	% SZS status Started for HL406314+4.p
118160.89/16030.23	% SZS status GaveUp for HL406314+4.p
118160.89/16030.23	eprover: CPU time limit exceeded, terminating
118160.89/16030.23	% SZS status Ended for HL406314+4.p
118173.03/16031.78	% SZS status Started for HL406324+4.p
118173.03/16031.78	% SZS status GaveUp for HL406324+4.p
118173.03/16031.78	eprover: CPU time limit exceeded, terminating
118173.03/16031.78	% SZS status Ended for HL406324+4.p
118173.55/16031.84	% SZS status Started for HL406327+5.p
118173.55/16031.84	% SZS status Theorem for HL406327+5.p
118173.55/16031.84	% SZS status Ended for HL406327+5.p
118178.00/16032.45	% SZS status Started for HL406328+5.p
118178.00/16032.45	% SZS status Theorem for HL406328+5.p
118178.00/16032.45	% SZS status Ended for HL406328+5.p
118187.09/16033.66	% SZS status Started for HL406325+4.p
118187.09/16033.66	% SZS status GaveUp for HL406325+4.p
118187.09/16033.66	eprover: CPU time limit exceeded, terminating
118187.09/16033.66	% SZS status Ended for HL406325+4.p
118192.06/16034.20	% SZS status Started for HL406323+4.p
118192.06/16034.20	% SZS status GaveUp for HL406323+4.p
118192.06/16034.20	eprover: CPU time limit exceeded, terminating
118192.06/16034.20	% SZS status Ended for HL406323+4.p
118201.73/16035.36	% SZS status Started for HL406326+4.p
118201.73/16035.36	% SZS status GaveUp for HL406326+4.p
118201.73/16035.36	eprover: CPU time limit exceeded, terminating
118201.73/16035.36	% SZS status Ended for HL406326+4.p
118217.39/16037.35	% SZS status Started for HL406327+4.p
118217.39/16037.35	% SZS status GaveUp for HL406327+4.p
118217.39/16037.35	eprover: CPU time limit exceeded, terminating
118217.39/16037.35	% SZS status Ended for HL406327+4.p
118239.19/16040.10	% SZS status Started for HL406328+4.p
118239.19/16040.10	% SZS status GaveUp for HL406328+4.p
118239.19/16040.10	eprover: CPU time limit exceeded, terminating
118239.19/16040.10	% SZS status Ended for HL406328+4.p
118249.71/16041.45	% SZS status Started for HL406329+5.p
118249.71/16041.45	% SZS status GaveUp for HL406329+5.p
118249.71/16041.45	% SZS status Ended for HL406329+5.p
118254.20/16042.03	% SZS status Started for HL406329+4.p
118254.20/16042.03	% SZS status GaveUp for HL406329+4.p
118254.20/16042.03	eprover: CPU time limit exceeded, terminating
118254.20/16042.03	% SZS status Ended for HL406329+4.p
118254.97/16042.18	% SZS status Started for HL406332+5.p
118254.97/16042.18	% SZS status Theorem for HL406332+5.p
118254.97/16042.18	% SZS status Ended for HL406332+5.p
118261.02/16042.83	% SZS status Started for HL406330+4.p
118261.02/16042.83	% SZS status GaveUp for HL406330+4.p
118261.02/16042.83	eprover: CPU time limit exceeded, terminating
118261.02/16042.83	% SZS status Ended for HL406330+4.p
118263.12/16043.14	% SZS status Started for HL406330+5.p
118263.12/16043.14	% SZS status GaveUp for HL406330+5.p
118263.12/16043.14	% SZS status Ended for HL406330+5.p
118274.10/16044.55	% SZS status Started for HL406332+4.p
118274.10/16044.55	% SZS status GaveUp for HL406332+4.p
118274.10/16044.55	eprover: CPU time limit exceeded, terminating
118274.10/16044.55	% SZS status Ended for HL406332+4.p
118303.01/16048.23	% SZS status Started for HL406333+4.p
118303.01/16048.23	% SZS status GaveUp for HL406333+4.p
118303.01/16048.23	eprover: CPU time limit exceeded, terminating
118303.01/16048.23	% SZS status Ended for HL406333+4.p
118314.27/16049.64	% SZS status Started for HL406333+5.p
118314.27/16049.64	% SZS status GaveUp for HL406333+5.p
118314.27/16049.64	% SZS status Ended for HL406333+5.p
118329.72/16051.54	% SZS status Started for HL406334+5.p
118329.72/16051.54	% SZS status GaveUp for HL406334+5.p
118329.72/16051.54	% SZS status Ended for HL406334+5.p
118336.02/16052.33	% SZS status Started for HL406335+5.p
118336.02/16052.33	% SZS status GaveUp for HL406335+5.p
118336.02/16052.33	% SZS status Ended for HL406335+5.p
118348.87/16053.95	% SZS status Started for HL406336+5.p
118348.87/16053.95	% SZS status GaveUp for HL406336+5.p
118348.87/16053.95	% SZS status Ended for HL406336+5.p
118384.06/16058.42	% SZS status Started for HL406337+4.p
118384.06/16058.42	% SZS status GaveUp for HL406337+4.p
118384.06/16058.42	eprover: CPU time limit exceeded, terminating
118384.06/16058.42	% SZS status Ended for HL406337+4.p
118388.59/16058.94	% SZS status Started for HL406338+5.p
118388.59/16058.94	% SZS status Theorem for HL406338+5.p
118388.59/16058.94	% SZS status Ended for HL406338+5.p
118391.11/16059.23	% SZS status Started for HL406337+5.p
118391.11/16059.23	% SZS status GaveUp for HL406337+5.p
118391.11/16059.23	% SZS status Ended for HL406337+5.p
118391.70/16059.29	% SZS status Started for HL406336+4.p
118391.70/16059.29	% SZS status GaveUp for HL406336+4.p
118391.70/16059.29	eprover: CPU time limit exceeded, terminating
118391.70/16059.29	% SZS status Ended for HL406336+4.p
118414.60/16062.17	% SZS status Started for HL406338+4.p
118414.60/16062.17	% SZS status GaveUp for HL406338+4.p
118414.60/16062.17	eprover: CPU time limit exceeded, terminating
118414.60/16062.17	% SZS status Ended for HL406338+4.p
118432.19/16064.38	% SZS status Started for HL406339+4.p
118432.19/16064.38	% SZS status GaveUp for HL406339+4.p
118432.19/16064.38	eprover: CPU time limit exceeded, terminating
118432.19/16064.38	% SZS status Ended for HL406339+4.p
118458.97/16067.80	% SZS status Started for HL406334+4.p
118458.97/16067.80	% SZS status GaveUp for HL406334+4.p
118458.97/16067.80	eprover: CPU time limit exceeded, terminating
118458.97/16067.80	% SZS status Ended for HL406334+4.p
118459.61/16067.87	% SZS status Started for HL406339+5.p
118459.61/16067.87	% SZS status GaveUp for HL406339+5.p
118459.61/16067.87	% SZS status Ended for HL406339+5.p
118463.84/16068.37	% SZS status Started for HL406335+4.p
118463.84/16068.37	% SZS status GaveUp for HL406335+4.p
118463.84/16068.37	eprover: CPU time limit exceeded, terminating
118463.84/16068.37	% SZS status Ended for HL406335+4.p
118465.27/16068.59	% SZS status Started for HL406340+5.p
118465.27/16068.59	% SZS status GaveUp for HL406340+5.p
118465.27/16068.59	% SZS status Ended for HL406340+5.p
118470.10/16069.20	% SZS status Started for HL406340+4.p
118470.10/16069.20	% SZS status GaveUp for HL406340+4.p
118470.10/16069.20	eprover: CPU time limit exceeded, terminating
118470.10/16069.20	% SZS status Ended for HL406340+4.p
118479.14/16070.33	% SZS status Started for HL406341+4.p
118479.14/16070.33	% SZS status GaveUp for HL406341+4.p
118479.14/16070.33	eprover: CPU time limit exceeded, terminating
118479.14/16070.33	% SZS status Ended for HL406341+4.p
118488.86/16071.65	% SZS status Started for HL406341+5.p
118488.86/16071.65	% SZS status GaveUp for HL406341+5.p
118488.86/16071.65	% SZS status Ended for HL406341+5.p
118488.86/16071.66	% SZS status Started for HL406343+5.p
118488.86/16071.66	% SZS status Theorem for HL406343+5.p
118488.86/16071.66	% SZS status Ended for HL406343+5.p
118542.70/16077.29	% SZS status Started for HL406342+5.p
118542.70/16077.29	% SZS status GaveUp for HL406342+5.p
118542.70/16077.29	% SZS status Ended for HL406342+5.p
118553.68/16078.66	% SZS status Started for HL406344+5.p
118553.68/16078.66	% SZS status GaveUp for HL406344+5.p
118553.68/16078.66	% SZS status Ended for HL406344+5.p
118570.36/16080.76	% SZS status Started for HL406345+4.p
118570.36/16080.76	% SZS status GaveUp for HL406345+4.p
118570.36/16080.76	eprover: CPU time limit exceeded, terminating
118570.36/16080.76	% SZS status Ended for HL406345+4.p
118570.36/16080.82	% SZS status Started for HL406344+4.p
118570.36/16080.82	% SZS status GaveUp for HL406344+4.p
118570.36/16080.82	eprover: CPU time limit exceeded, terminating
118570.36/16080.82	% SZS status Ended for HL406344+4.p
118571.92/16081.03	% SZS status Started for HL406345+5.p
118571.92/16081.03	% SZS status GaveUp for HL406345+5.p
118571.92/16081.03	% SZS status Ended for HL406345+5.p
118611.88/16086.05	% SZS status Started for HL406343+4.p
118611.88/16086.05	% SZS status GaveUp for HL406343+4.p
118611.88/16086.05	eprover: CPU time limit exceeded, terminating
118611.88/16086.05	% SZS status Ended for HL406343+4.p
118617.52/16086.74	% SZS status Started for HL406346+5.p
118617.52/16086.74	% SZS status GaveUp for HL406346+5.p
118617.52/16086.74	% SZS status Ended for HL406346+5.p
118624.84/16087.64	% SZS status Started for HL406347+5.p
118624.84/16087.64	% SZS status Theorem for HL406347+5.p
118624.84/16087.64	% SZS status Ended for HL406347+5.p
118626.07/16087.82	% SZS status Started for HL406346+4.p
118626.07/16087.82	% SZS status GaveUp for HL406346+4.p
118626.07/16087.82	eprover: CPU time limit exceeded, terminating
118626.07/16087.82	% SZS status Ended for HL406346+4.p
118633.20/16088.65	% SZS status Started for HL406342+4.p
118633.20/16088.65	% SZS status GaveUp for HL406342+4.p
118633.20/16088.65	eprover: CPU time limit exceeded, terminating
118633.20/16088.65	% SZS status Ended for HL406342+4.p
118635.05/16088.97	% SZS status Started for HL406347+4.p
118635.05/16088.97	% SZS status GaveUp for HL406347+4.p
118635.05/16088.97	eprover: CPU time limit exceeded, terminating
118635.05/16088.97	% SZS status Ended for HL406347+4.p
118649.23/16090.70	% SZS status Started for HL406350+5.p
118649.23/16090.70	% SZS status GaveUp for HL406350+5.p
118649.23/16090.70	% SZS status Ended for HL406350+5.p
118651.13/16090.98	% SZS status Started for HL406350+4.p
118651.13/16090.98	% SZS status GaveUp for HL406350+4.p
118651.13/16090.98	eprover: CPU time limit exceeded, terminating
118651.13/16090.98	% SZS status Ended for HL406350+4.p
118693.41/16096.24	% SZS status Started for HL406351+4.p
118693.41/16096.24	% SZS status GaveUp for HL406351+4.p
118693.41/16096.24	eprover: CPU time limit exceeded, terminating
118693.41/16096.24	% SZS status Ended for HL406351+4.p
118694.64/16096.43	% SZS status Started for HL406351+5.p
118694.64/16096.43	% SZS status GaveUp for HL406351+5.p
118694.64/16096.43	% SZS status Ended for HL406351+5.p
118700.90/16097.21	% SZS status Started for HL406352+5.p
118700.90/16097.21	% SZS status GaveUp for HL406352+5.p
118700.90/16097.21	% SZS status Ended for HL406352+5.p
118712.52/16098.71	% SZS status Started for HL406353+5.p
118712.52/16098.71	% SZS status GaveUp for HL406353+5.p
118712.52/16098.71	% SZS status Ended for HL406353+5.p
118718.78/16099.41	% SZS status Started for HL406356+4.p
118718.78/16099.41	% SZS status GaveUp for HL406356+4.p
118718.78/16099.41	eprover: CPU time limit exceeded, terminating
118718.78/16099.41	% SZS status Ended for HL406356+4.p
118725.46/16100.24	% SZS status Started for HL406357+4.p
118725.46/16100.24	% SZS status GaveUp for HL406357+4.p
118725.46/16100.24	eprover: CPU time limit exceeded, terminating
118725.46/16100.24	% SZS status Ended for HL406357+4.p
118727.08/16100.46	% SZS status Started for HL406355+5.p
118727.08/16100.46	% SZS status GaveUp for HL406355+5.p
118727.08/16100.46	% SZS status Ended for HL406355+5.p
118742.77/16102.45	% SZS status Started for HL406358+4.p
118742.77/16102.45	% SZS status GaveUp for HL406358+4.p
118742.77/16102.45	eprover: CPU time limit exceeded, terminating
118742.77/16102.45	% SZS status Ended for HL406358+4.p
118745.76/16102.83	% SZS status Started for HL406358+5.p
118745.76/16102.83	% SZS status Theorem for HL406358+5.p
118745.76/16102.83	% SZS status Ended for HL406358+5.p
118751.29/16103.52	% SZS status Started for HL406359+4.p
118751.29/16103.52	% SZS status GaveUp for HL406359+4.p
118751.29/16103.52	eprover: CPU time limit exceeded, terminating
118751.29/16103.52	% SZS status Ended for HL406359+4.p
118753.73/16103.82	% SZS status Started for HL406352+4.p
118753.73/16103.82	% SZS status GaveUp for HL406352+4.p
118753.73/16103.82	eprover: CPU time limit exceeded, terminating
118753.73/16103.82	% SZS status Ended for HL406352+4.p
118768.93/16105.91	% SZS status Started for HL406360+4.p
118768.93/16105.91	% SZS status GaveUp for HL406360+4.p
118768.93/16105.91	eprover: CPU time limit exceeded, terminating
118768.93/16105.91	% SZS status Ended for HL406360+4.p
118774.77/16106.22	% SZS status Started for HL406360+5.p
118774.77/16106.22	% SZS status Theorem for HL406360+5.p
118774.77/16106.22	% SZS status Ended for HL406360+5.p
118777.10/16106.50	% SZS status Started for HL406356+5.p
118777.10/16106.50	% SZS status GaveUp for HL406356+5.p
118777.10/16106.50	% SZS status Ended for HL406356+5.p
118779.70/16106.86	% SZS status Started for HL406361+4.p
118779.70/16106.86	% SZS status GaveUp for HL406361+4.p
118779.70/16106.86	eprover: CPU time limit exceeded, terminating
118779.70/16106.86	% SZS status Ended for HL406361+4.p
118796.83/16108.99	% SZS status Started for HL406357+5.p
118796.83/16108.99	% SZS status GaveUp for HL406357+5.p
118796.83/16108.99	% SZS status Ended for HL406357+5.p
118799.62/16109.27	% SZS status Started for HL406362+4.p
118799.62/16109.27	% SZS status GaveUp for HL406362+4.p
118799.62/16109.27	eprover: CPU time limit exceeded, terminating
118799.62/16109.27	% SZS status Ended for HL406362+4.p
118804.05/16109.89	% SZS status Started for HL406363+4.p
118804.05/16109.89	% SZS status GaveUp for HL406363+4.p
118804.05/16109.89	eprover: CPU time limit exceeded, terminating
118804.05/16109.89	% SZS status Ended for HL406363+4.p
118805.80/16110.21	% SZS status Started for HL406359+5.p
118805.80/16110.21	% SZS status Theorem for HL406359+5.p
118805.80/16110.21	% SZS status Ended for HL406359+5.p
118823.34/16112.30	% SZS status Started for HL406364+4.p
118823.34/16112.30	% SZS status GaveUp for HL406364+4.p
118823.34/16112.30	eprover: CPU time limit exceeded, terminating
118823.34/16112.30	% SZS status Ended for HL406364+4.p
118831.74/16113.35	% SZS status Started for HL406365+4.p
118831.74/16113.35	% SZS status GaveUp for HL406365+4.p
118831.74/16113.35	eprover: CPU time limit exceeded, terminating
118831.74/16113.35	% SZS status Ended for HL406365+4.p
118833.11/16113.62	% SZS status Started for HL406362+5.p
118833.11/16113.62	% SZS status Theorem for HL406362+5.p
118833.11/16113.62	% SZS status Ended for HL406362+5.p
118844.05/16114.87	% SZS status Started for HL406353+4.p
118844.05/16114.87	% SZS status GaveUp for HL406353+4.p
118844.05/16114.87	eprover: CPU time limit exceeded, terminating
118844.05/16114.87	% SZS status Ended for HL406353+4.p
118854.55/16116.24	% SZS status Started for HL406361+5.p
118854.55/16116.24	% SZS status GaveUp for HL406361+5.p
118854.55/16116.24	% SZS status Ended for HL406361+5.p
118855.51/16116.40	% SZS status Started for HL406367+4.p
118855.51/16116.40	% SZS status GaveUp for HL406367+4.p
118855.51/16116.40	eprover: CPU time limit exceeded, terminating
118855.51/16116.40	% SZS status Ended for HL406367+4.p
118859.74/16116.87	% SZS status Started for HL406355+4.p
118859.74/16116.87	% SZS status GaveUp for HL406355+4.p
118859.74/16116.87	eprover: CPU time limit exceeded, terminating
118859.74/16116.87	% SZS status Ended for HL406355+4.p
118868.24/16117.91	% SZS status Started for HL406370+4.p
118868.24/16117.91	% SZS status GaveUp for HL406370+4.p
118868.24/16117.91	eprover: CPU time limit exceeded, terminating
118868.24/16117.91	% SZS status Ended for HL406370+4.p
118878.87/16119.30	% SZS status Started for HL406363+5.p
118878.87/16119.30	% SZS status GaveUp for HL406363+5.p
118878.87/16119.30	% SZS status Ended for HL406363+5.p
118879.91/16119.43	% SZS status Started for HL406371+4.p
118879.91/16119.43	% SZS status GaveUp for HL406371+4.p
118879.91/16119.43	eprover: CPU time limit exceeded, terminating
118879.91/16119.43	% SZS status Ended for HL406371+4.p
118886.08/16120.21	% SZS status Started for HL406364+5.p
118886.08/16120.21	% SZS status GaveUp for HL406364+5.p
118886.08/16120.21	% SZS status Ended for HL406364+5.p
118891.91/16120.93	% SZS status Started for HL406372+4.p
118891.91/16120.93	% SZS status GaveUp for HL406372+4.p
118891.91/16120.93	eprover: CPU time limit exceeded, terminating
118891.91/16120.93	% SZS status Ended for HL406372+4.p
118904.86/16122.69	% SZS status Started for HL406365+5.p
118904.86/16122.69	% SZS status GaveUp for HL406365+5.p
118904.86/16122.69	% SZS status Ended for HL406365+5.p
118919.35/16124.46	% SZS status Started for HL406367+5.p
118919.35/16124.46	% SZS status GaveUp for HL406367+5.p
118919.35/16124.46	% SZS status Ended for HL406367+5.p
118926.53/16125.28	% SZS status Started for HL406376+5.p
118926.53/16125.28	% SZS status Theorem for HL406376+5.p
118926.53/16125.28	% SZS status Ended for HL406376+5.p
118935.80/16126.47	% SZS status Started for HL406370+5.p
118935.80/16126.47	% SZS status GaveUp for HL406370+5.p
118935.80/16126.47	% SZS status Ended for HL406370+5.p
118942.26/16127.25	% SZS status Started for HL406371+5.p
118942.26/16127.25	% SZS status GaveUp for HL406371+5.p
118942.26/16127.25	% SZS status Ended for HL406371+5.p
118960.81/16129.63	% SZS status Started for HL406372+5.p
118960.81/16129.63	% SZS status GaveUp for HL406372+5.p
118960.81/16129.63	% SZS status Ended for HL406372+5.p
118966.54/16130.29	% SZS status Started for HL406373+5.p
118966.54/16130.29	% SZS status GaveUp for HL406373+5.p
118966.54/16130.29	% SZS status Ended for HL406373+5.p
118967.61/16130.48	% SZS status Started for HL406373+4.p
118967.61/16130.48	% SZS status GaveUp for HL406373+4.p
118967.61/16130.48	eprover: CPU time limit exceeded, terminating
118967.61/16130.48	% SZS status Ended for HL406373+4.p
118980.15/16131.99	% SZS status Started for HL406376+4.p
118980.15/16131.99	% SZS status GaveUp for HL406376+4.p
118980.15/16131.99	eprover: CPU time limit exceeded, terminating
118980.15/16131.99	% SZS status Ended for HL406376+4.p
119008.39/16135.65	% SZS status Started for HL406377+5.p
119008.39/16135.65	% SZS status GaveUp for HL406377+5.p
119008.39/16135.65	% SZS status Ended for HL406377+5.p
119008.45/16135.70	% SZS status Started for HL406377+4.p
119008.45/16135.70	% SZS status GaveUp for HL406377+4.p
119008.45/16135.70	eprover: CPU time limit exceeded, terminating
119008.45/16135.70	% SZS status Ended for HL406377+4.p
119022.86/16137.40	% SZS status Started for HL406378+5.p
119022.86/16137.40	% SZS status GaveUp for HL406378+5.p
119022.86/16137.40	% SZS status Ended for HL406378+5.p
119023.95/16137.54	% SZS status Started for HL406378+4.p
119023.95/16137.54	% SZS status GaveUp for HL406378+4.p
119023.95/16137.54	eprover: CPU time limit exceeded, terminating
119023.95/16137.54	% SZS status Ended for HL406378+4.p
119046.76/16140.36	% SZS status Started for HL406379+5.p
119046.76/16140.36	% SZS status GaveUp for HL406379+5.p
119046.76/16140.36	% SZS status Ended for HL406379+5.p
119050.55/16140.85	% SZS status Started for HL406379+4.p
119050.55/16140.85	% SZS status GaveUp for HL406379+4.p
119050.55/16140.85	eprover: CPU time limit exceeded, terminating
119050.55/16140.85	% SZS status Ended for HL406379+4.p
119056.16/16141.55	% SZS status Started for HL406380+4.p
119056.16/16141.55	% SZS status GaveUp for HL406380+4.p
119056.16/16141.55	eprover: CPU time limit exceeded, terminating
119056.16/16141.55	% SZS status Ended for HL406380+4.p
119064.97/16142.73	% SZS status Started for HL406380+5.p
119064.97/16142.73	% SZS status GaveUp for HL406380+5.p
119064.97/16142.73	% SZS status Ended for HL406380+5.p
119086.81/16145.40	% SZS status Started for HL406386+5.p
119086.81/16145.40	% SZS status Theorem for HL406386+5.p
119086.81/16145.40	% SZS status Ended for HL406386+5.p
119091.79/16146.06	% SZS status Started for HL406381+5.p
119091.79/16146.06	% SZS status GaveUp for HL406381+5.p
119091.79/16146.06	% SZS status Ended for HL406381+5.p
119096.55/16146.71	% SZS status Started for HL406381+4.p
119096.55/16146.71	% SZS status GaveUp for HL406381+4.p
119096.55/16146.71	eprover: CPU time limit exceeded, terminating
119096.55/16146.71	% SZS status Ended for HL406381+4.p
119103.52/16147.65	% SZS status Started for HL406382+5.p
119103.52/16147.65	% SZS status GaveUp for HL406382+5.p
119103.52/16147.65	% SZS status Ended for HL406382+5.p
119111.03/16148.46	% SZS status Started for HL406382+4.p
119111.03/16148.46	% SZS status GaveUp for HL406382+4.p
119111.03/16148.46	eprover: CPU time limit exceeded, terminating
119111.03/16148.46	% SZS status Ended for HL406382+4.p
119132.33/16151.21	% SZS status Started for HL406385+5.p
119132.33/16151.21	% SZS status GaveUp for HL406385+5.p
119132.33/16151.21	% SZS status Ended for HL406385+5.p
119135.81/16151.71	% SZS status Started for HL406385+4.p
119135.81/16151.71	% SZS status GaveUp for HL406385+4.p
119135.81/16151.71	eprover: CPU time limit exceeded, terminating
119135.81/16151.71	% SZS status Ended for HL406385+4.p
119143.46/16152.61	% SZS status Started for HL406386+4.p
119143.46/16152.61	% SZS status GaveUp for HL406386+4.p
119143.46/16152.61	eprover: CPU time limit exceeded, terminating
119143.46/16152.61	% SZS status Ended for HL406386+4.p
119171.95/16156.18	% SZS status Started for HL406387+5.p
119171.95/16156.18	% SZS status GaveUp for HL406387+5.p
119171.95/16156.18	% SZS status Ended for HL406387+5.p
119174.55/16156.47	% SZS status Started for HL406387+4.p
119174.55/16156.47	% SZS status GaveUp for HL406387+4.p
119174.55/16156.47	eprover: CPU time limit exceeded, terminating
119174.55/16156.47	% SZS status Ended for HL406387+4.p
119187.23/16158.06	% SZS status Started for HL406388+5.p
119187.23/16158.06	% SZS status GaveUp for HL406388+5.p
119187.23/16158.06	% SZS status Ended for HL406388+5.p
119187.23/16158.08	% SZS status Started for HL406388+4.p
119187.23/16158.08	% SZS status GaveUp for HL406388+4.p
119187.23/16158.08	eprover: CPU time limit exceeded, terminating
119187.23/16158.08	% SZS status Ended for HL406388+4.p
119199.65/16159.68	% SZS status Started for HL406389+4.p
119199.65/16159.68	% SZS status GaveUp for HL406389+4.p
119199.65/16159.68	eprover: CPU time limit exceeded, terminating
119199.65/16159.68	% SZS status Ended for HL406389+4.p
119212.79/16161.34	% SZS status Started for HL406389+5.p
119212.79/16161.34	% SZS status GaveUp for HL406389+5.p
119212.79/16161.34	% SZS status Ended for HL406389+5.p
119223.38/16162.70	% SZS status Started for HL406390+5.p
119223.38/16162.70	% SZS status GaveUp for HL406390+5.p
119223.38/16162.70	% SZS status Ended for HL406390+5.p
119223.51/16162.77	% SZS status Started for HL406390+4.p
119223.51/16162.77	% SZS status GaveUp for HL406390+4.p
119223.51/16162.77	eprover: CPU time limit exceeded, terminating
119223.51/16162.77	% SZS status Ended for HL406390+4.p
119247.87/16165.73	% SZS status Started for HL406394+4.p
119247.87/16165.73	% SZS status GaveUp for HL406394+4.p
119247.87/16165.73	eprover: CPU time limit exceeded, terminating
119247.87/16165.73	% SZS status Ended for HL406394+4.p
119254.88/16166.82	% SZS status Started for HL406391+5.p
119254.88/16166.82	% SZS status GaveUp for HL406391+5.p
119254.88/16166.82	% SZS status Ended for HL406391+5.p
119260.05/16167.29	% SZS status Started for HL406391+4.p
119260.05/16167.29	% SZS status GaveUp for HL406391+4.p
119260.05/16167.29	eprover: CPU time limit exceeded, terminating
119260.05/16167.29	% SZS status Ended for HL406391+4.p
119270.20/16168.53	% SZS status Started for HL406392+5.p
119270.20/16168.53	% SZS status GaveUp for HL406392+5.p
119270.20/16168.53	% SZS status Ended for HL406392+5.p
119278.90/16169.65	% SZS status Started for HL406392+4.p
119278.90/16169.65	% SZS status GaveUp for HL406392+4.p
119278.90/16169.65	eprover: CPU time limit exceeded, terminating
119278.90/16169.65	% SZS status Ended for HL406392+4.p
119287.43/16170.75	% SZS status Started for HL406393+4.p
119287.43/16170.75	% SZS status GaveUp for HL406393+4.p
119287.43/16170.75	eprover: CPU time limit exceeded, terminating
119287.43/16170.75	% SZS status Ended for HL406393+4.p
119293.96/16171.63	% SZS status Started for HL406393+5.p
119293.96/16171.63	% SZS status GaveUp for HL406393+5.p
119293.96/16171.63	% SZS status Ended for HL406393+5.p
119306.70/16173.13	% SZS status Started for HL406394+5.p
119306.70/16173.13	% SZS status GaveUp for HL406394+5.p
119306.70/16173.13	% SZS status Ended for HL406394+5.p
119319.85/16174.79	% SZS status Started for HL406395+5.p
119319.85/16174.79	% SZS status Theorem for HL406395+5.p
119319.85/16174.79	% SZS status Ended for HL406395+5.p
119335.08/16176.79	% SZS status Started for HL406395+4.p
119335.08/16176.79	% SZS status GaveUp for HL406395+4.p
119335.08/16176.79	eprover: CPU time limit exceeded, terminating
119335.08/16176.79	% SZS status Ended for HL406395+4.p
119348.21/16178.37	% SZS status Started for HL406396+4.p
119348.21/16178.37	% SZS status GaveUp for HL406396+4.p
119348.21/16178.37	eprover: CPU time limit exceeded, terminating
119348.21/16178.37	% SZS status Ended for HL406396+4.p
119349.45/16178.62	% SZS status Started for HL406396+5.p
119349.45/16178.62	% SZS status GaveUp for HL406396+5.p
119349.45/16178.62	% SZS status Ended for HL406396+5.p
119365.38/16180.52	% SZS status Started for HL406399+5.p
119365.38/16180.52	% SZS status Theorem for HL406399+5.p
119365.38/16180.52	% SZS status Ended for HL406399+5.p
119367.21/16180.76	% SZS status Started for HL406397+4.p
119367.21/16180.76	% SZS status GaveUp for HL406397+4.p
119367.21/16180.76	eprover: CPU time limit exceeded, terminating
119367.21/16180.76	% SZS status Ended for HL406397+4.p
119370.15/16181.34	% SZS status Started for HL406397+5.p
119370.15/16181.34	% SZS status GaveUp for HL406397+5.p
119370.15/16181.34	% SZS status Ended for HL406397+5.p
119382.37/16182.69	% SZS status Started for HL406398+4.p
119382.37/16182.69	% SZS status GaveUp for HL406398+4.p
119382.37/16182.69	eprover: CPU time limit exceeded, terminating
119382.37/16182.69	% SZS status Ended for HL406398+4.p
119388.83/16183.52	% SZS status Started for HL406398+5.p
119388.83/16183.52	% SZS status GaveUp for HL406398+5.p
119388.83/16183.52	% SZS status Ended for HL406398+5.p
119395.85/16184.31	% SZS status Started for HL406401+5.p
119395.85/16184.31	% SZS status Theorem for HL406401+5.p
119395.85/16184.31	% SZS status Ended for HL406401+5.p
119407.96/16185.88	% SZS status Started for HL406399+4.p
119407.96/16185.88	% SZS status GaveUp for HL406399+4.p
119407.96/16185.88	eprover: CPU time limit exceeded, terminating
119407.96/16185.88	% SZS status Ended for HL406399+4.p
119430.73/16188.78	% SZS status Started for HL406400+5.p
119430.73/16188.78	% SZS status GaveUp for HL406400+5.p
119430.73/16188.78	% SZS status Ended for HL406400+5.p
119436.52/16189.44	% SZS status Started for HL406400+4.p
119436.52/16189.44	% SZS status GaveUp for HL406400+4.p
119436.52/16189.44	eprover: CPU time limit exceeded, terminating
119436.52/16189.44	% SZS status Ended for HL406400+4.p
119453.38/16191.58	% SZS status Started for HL406401+4.p
119453.38/16191.58	% SZS status GaveUp for HL406401+4.p
119453.38/16191.58	eprover: CPU time limit exceeded, terminating
119453.38/16191.58	% SZS status Ended for HL406401+4.p
119460.41/16192.45	% SZS status Started for HL406402+4.p
119460.41/16192.45	% SZS status GaveUp for HL406402+4.p
119460.41/16192.45	eprover: CPU time limit exceeded, terminating
119460.41/16192.45	% SZS status Ended for HL406402+4.p
119463.66/16192.86	% SZS status Started for HL406402+5.p
119463.66/16192.86	% SZS status GaveUp for HL406402+5.p
119463.66/16192.86	% SZS status Ended for HL406402+5.p
119476.79/16194.54	% SZS status Started for HL406403+5.p
119476.79/16194.54	% SZS status GaveUp for HL406403+5.p
119476.79/16194.54	% SZS status Ended for HL406403+5.p
119477.41/16194.62	% SZS status Started for HL406403+4.p
119477.41/16194.62	% SZS status GaveUp for HL406403+4.p
119477.41/16194.62	eprover: CPU time limit exceeded, terminating
119477.41/16194.62	% SZS status Ended for HL406403+4.p
119497.05/16197.10	% SZS status Started for HL406405+4.p
119497.05/16197.10	% SZS status GaveUp for HL406405+4.p
119497.05/16197.10	eprover: CPU time limit exceeded, terminating
119497.05/16197.10	% SZS status Ended for HL406405+4.p
119515.71/16199.41	% SZS status Started for HL406405+5.p
119515.71/16199.41	% SZS status GaveUp for HL406405+5.p
119515.71/16199.41	% SZS status Ended for HL406405+5.p
119521.73/16200.16	% SZS status Started for HL406410+4.p
119521.73/16200.16	% SZS status GaveUp for HL406410+4.p
119521.73/16200.16	eprover: CPU time limit exceeded, terminating
119521.73/16200.16	% SZS status Ended for HL406410+4.p
119524.23/16200.51	% SZS status Started for HL406407+4.p
119524.23/16200.51	% SZS status GaveUp for HL406407+4.p
119524.23/16200.51	eprover: CPU time limit exceeded, terminating
119524.23/16200.51	% SZS status Ended for HL406407+4.p
119533.12/16201.68	% SZS status Started for HL406407+5.p
119533.12/16201.68	% SZS status GaveUp for HL406407+5.p
119533.12/16201.68	% SZS status Ended for HL406407+5.p
119543.94/16202.95	% SZS status Started for HL406408+5.p
119543.94/16202.95	% SZS status GaveUp for HL406408+5.p
119543.94/16202.95	% SZS status Ended for HL406408+5.p
119545.75/16203.20	% SZS status Started for HL406411+4.p
119545.75/16203.20	% SZS status GaveUp for HL406411+4.p
119545.75/16203.20	eprover: CPU time limit exceeded, terminating
119545.75/16203.20	% SZS status Ended for HL406411+4.p
119548.72/16203.57	% SZS status Started for HL406408+4.p
119548.72/16203.57	% SZS status GaveUp for HL406408+4.p
119548.72/16203.57	eprover: CPU time limit exceeded, terminating
119548.72/16203.57	% SZS status Ended for HL406408+4.p
119557.94/16204.81	% SZS status Started for HL406413+4.p
119557.94/16204.81	% SZS status GaveUp for HL406413+4.p
119557.94/16204.81	eprover: CPU time limit exceeded, terminating
119557.94/16204.81	% SZS status Ended for HL406413+4.p
119558.88/16204.94	% SZS status Started for HL406409+5.p
119558.88/16204.94	% SZS status GaveUp for HL406409+5.p
119558.88/16204.94	% SZS status Ended for HL406409+5.p
119565.05/16205.60	% SZS status Started for HL406409+4.p
119565.05/16205.60	% SZS status GaveUp for HL406409+4.p
119565.05/16205.60	eprover: CPU time limit exceeded, terminating
119565.05/16205.60	% SZS status Ended for HL406409+4.p
119569.37/16206.23	% SZS status Started for HL406414+4.p
119569.37/16206.23	% SZS status GaveUp for HL406414+4.p
119569.37/16206.23	eprover: CPU time limit exceeded, terminating
119569.37/16206.23	% SZS status Ended for HL406414+4.p
119577.77/16207.23	% SZS status Started for HL406410+5.p
119577.77/16207.23	% SZS status Theorem for HL406410+5.p
119577.77/16207.23	% SZS status Ended for HL406410+5.p
119582.23/16207.84	% SZS status Started for HL406415+4.p
119582.23/16207.84	% SZS status GaveUp for HL406415+4.p
119582.23/16207.84	eprover: CPU time limit exceeded, terminating
119582.23/16207.84	% SZS status Ended for HL406415+4.p
119588.45/16208.63	% SZS status Started for HL406418+4.p
119588.45/16208.63	% SZS status GaveUp for HL406418+4.p
119588.45/16208.63	eprover: CPU time limit exceeded, terminating
119588.45/16208.63	% SZS status Ended for HL406418+4.p
119601.77/16210.24	% SZS status Started for HL406419+5.p
119601.77/16210.24	% SZS status Theorem for HL406419+5.p
119601.77/16210.24	% SZS status Ended for HL406419+5.p
119601.87/16210.25	% SZS status Started for HL406419+4.p
119601.87/16210.25	% SZS status GaveUp for HL406419+4.p
119601.87/16210.25	eprover: CPU time limit exceeded, terminating
119601.87/16210.25	% SZS status Ended for HL406419+4.p
119606.51/16210.90	% SZS status Started for HL406411+5.p
119606.51/16210.90	% SZS status GaveUp for HL406411+5.p
119606.51/16210.90	% SZS status Ended for HL406411+5.p
119612.63/16211.66	% SZS status Started for HL406420+4.p
119612.63/16211.66	% SZS status GaveUp for HL406420+4.p
119612.63/16211.66	eprover: CPU time limit exceeded, terminating
119612.63/16211.66	% SZS status Ended for HL406420+4.p
119624.66/16213.29	% SZS status Started for HL406421+4.p
119624.66/16213.29	% SZS status GaveUp for HL406421+4.p
119624.66/16213.29	eprover: CPU time limit exceeded, terminating
119624.66/16213.29	% SZS status Ended for HL406421+4.p
119628.85/16213.75	% SZS status Started for HL406413+5.p
119628.85/16213.75	% SZS status GaveUp for HL406413+5.p
119628.85/16213.75	% SZS status Ended for HL406413+5.p
119631.13/16213.95	% SZS status Started for HL406414+5.p
119631.13/16213.95	% SZS status GaveUp for HL406414+5.p
119631.13/16213.95	% SZS status Ended for HL406414+5.p
119636.94/16214.69	% SZS status Started for HL406423+4.p
119636.94/16214.69	% SZS status GaveUp for HL406423+4.p
119636.94/16214.69	eprover: CPU time limit exceeded, terminating
119636.94/16214.69	% SZS status Ended for HL406423+4.p
119641.74/16215.28	% SZS status Started for HL406415+5.p
119641.74/16215.28	% SZS status GaveUp for HL406415+5.p
119641.74/16215.28	% SZS status Ended for HL406415+5.p
119651.70/16216.57	% SZS status Started for HL406418+5.p
119651.70/16216.57	% SZS status GaveUp for HL406418+5.p
119651.70/16216.57	% SZS status Ended for HL406418+5.p
119660.20/16217.71	% SZS status Started for HL406420+5.p
119660.20/16217.71	% SZS status Theorem for HL406420+5.p
119660.20/16217.71	% SZS status Ended for HL406420+5.p
119667.28/16218.52	% SZS status Started for HL406421+5.p
119667.28/16218.52	% SZS status Theorem for HL406421+5.p
119667.28/16218.52	% SZS status Ended for HL406421+5.p
119705.19/16223.23	% SZS status Started for HL406423+5.p
119705.19/16223.23	% SZS status GaveUp for HL406423+5.p
119705.19/16223.23	% SZS status Ended for HL406423+5.p
119710.16/16223.92	% SZS status Started for HL406424+5.p
119710.16/16223.92	% SZS status GaveUp for HL406424+5.p
119710.16/16223.92	% SZS status Ended for HL406424+5.p
119717.32/16224.80	% SZS status Started for HL406425+5.p
119717.32/16224.80	% SZS status GaveUp for HL406425+5.p
119717.32/16224.80	% SZS status Ended for HL406425+5.p
119717.32/16224.81	% SZS status Started for HL406424+4.p
119717.32/16224.81	% SZS status GaveUp for HL406424+4.p
119717.32/16224.81	eprover: CPU time limit exceeded, terminating
119717.32/16224.81	% SZS status Ended for HL406424+4.p
119720.74/16225.25	% SZS status Started for HL406425+4.p
119720.74/16225.25	% SZS status GaveUp for HL406425+4.p
119720.74/16225.25	eprover: CPU time limit exceeded, terminating
119720.74/16225.25	% SZS status Ended for HL406425+4.p
119734.60/16227.05	% SZS status Started for HL406426+4.p
119734.60/16227.05	% SZS status GaveUp for HL406426+4.p
119734.60/16227.05	eprover: CPU time limit exceeded, terminating
119734.60/16227.05	% SZS status Ended for HL406426+4.p
119736.45/16227.18	% SZS status Started for HL406426+5.p
119736.45/16227.18	% SZS status GaveUp for HL406426+5.p
119736.45/16227.18	% SZS status Ended for HL406426+5.p
119751.69/16229.11	% SZS status Started for HL406427+4.p
119751.69/16229.11	% SZS status GaveUp for HL406427+4.p
119751.69/16229.11	eprover: CPU time limit exceeded, terminating
119751.69/16229.11	% SZS status Ended for HL406427+4.p
119766.76/16230.97	% SZS status Started for HL406428+5.p
119766.76/16230.97	% SZS status Theorem for HL406428+5.p
119766.76/16230.97	% SZS status Ended for HL406428+5.p
119779.82/16232.69	% SZS status Started for HL406427+5.p
119779.82/16232.69	% SZS status GaveUp for HL406427+5.p
119779.82/16232.69	% SZS status Ended for HL406427+5.p
119795.05/16234.56	% SZS status Started for HL406428+4.p
119795.05/16234.56	% SZS status GaveUp for HL406428+4.p
119795.05/16234.56	eprover: CPU time limit exceeded, terminating
119795.05/16234.56	% SZS status Ended for HL406428+4.p
119795.82/16234.72	% SZS status Started for HL406429+5.p
119795.82/16234.72	% SZS status GaveUp for HL406429+5.p
119795.82/16234.72	% SZS status Ended for HL406429+5.p
119800.63/16235.34	% SZS status Started for HL406429+4.p
119800.63/16235.34	% SZS status GaveUp for HL406429+4.p
119800.63/16235.34	eprover: CPU time limit exceeded, terminating
119800.63/16235.34	% SZS status Ended for HL406429+4.p
119813.55/16236.96	% SZS status Started for HL406431+5.p
119813.55/16236.96	% SZS status GaveUp for HL406431+5.p
119813.55/16236.96	% SZS status Ended for HL406431+5.p
119818.94/16237.59	% SZS status Started for HL406431+4.p
119818.94/16237.59	% SZS status GaveUp for HL406431+4.p
119818.94/16237.59	eprover: CPU time limit exceeded, terminating
119818.94/16237.59	% SZS status Ended for HL406431+4.p
119835.97/16239.72	% SZS status Started for HL406432+4.p
119835.97/16239.72	% SZS status GaveUp for HL406432+4.p
119835.97/16239.72	eprover: CPU time limit exceeded, terminating
119835.97/16239.72	% SZS status Ended for HL406432+4.p
119848.04/16241.32	% SZS status Started for HL406432+5.p
119848.04/16241.32	% SZS status GaveUp for HL406432+5.p
119848.04/16241.32	% SZS status Ended for HL406432+5.p
119863.48/16243.23	% SZS status Started for HL406434+4.p
119863.48/16243.23	% SZS status GaveUp for HL406434+4.p
119863.48/16243.23	eprover: CPU time limit exceeded, terminating
119863.48/16243.23	% SZS status Ended for HL406434+4.p
119872.68/16244.31	% SZS status Started for HL406434+5.p
119872.68/16244.31	% SZS status GaveUp for HL406434+5.p
119872.68/16244.31	% SZS status Ended for HL406434+5.p
119878.68/16245.08	% SZS status Started for HL406435+5.p
119878.68/16245.08	% SZS status GaveUp for HL406435+5.p
119878.68/16245.08	% SZS status Ended for HL406435+5.p
119879.75/16245.24	% SZS status Started for HL406435+4.p
119879.75/16245.24	% SZS status GaveUp for HL406435+4.p
119879.75/16245.24	eprover: CPU time limit exceeded, terminating
119879.75/16245.24	% SZS status Ended for HL406435+4.p
119895.31/16247.29	% SZS status Started for HL406436+5.p
119895.31/16247.29	% SZS status GaveUp for HL406436+5.p
119895.31/16247.29	% SZS status Ended for HL406436+5.p
119899.41/16247.77	% SZS status Started for HL406436+4.p
119899.41/16247.77	% SZS status GaveUp for HL406436+4.p
119899.41/16247.77	eprover: CPU time limit exceeded, terminating
119899.41/16247.77	% SZS status Ended for HL406436+4.p
119918.76/16250.19	% SZS status Started for HL406437+4.p
119918.76/16250.19	% SZS status GaveUp for HL406437+4.p
119918.76/16250.19	eprover: CPU time limit exceeded, terminating
119918.76/16250.19	% SZS status Ended for HL406437+4.p
119924.94/16251.00	% SZS status Started for HL406437+5.p
119924.94/16251.00	% SZS status GaveUp for HL406437+5.p
119924.94/16251.00	% SZS status Ended for HL406437+5.p
119946.60/16253.72	% SZS status Started for HL406438+4.p
119946.60/16253.72	% SZS status GaveUp for HL406438+4.p
119946.60/16253.72	eprover: CPU time limit exceeded, terminating
119946.60/16253.72	% SZS status Ended for HL406438+4.p
119948.24/16253.96	% SZS status Started for HL406438+5.p
119948.24/16253.96	% SZS status GaveUp for HL406438+5.p
119948.24/16253.96	% SZS status Ended for HL406438+5.p
119957.03/16254.96	% SZS status Started for HL406439+5.p
119957.03/16254.96	% SZS status GaveUp for HL406439+5.p
119957.03/16254.96	% SZS status Ended for HL406439+5.p
119963.48/16255.84	% SZS status Started for HL406439+4.p
119963.48/16255.84	% SZS status GaveUp for HL406439+4.p
119963.48/16255.84	eprover: CPU time limit exceeded, terminating
119963.48/16255.84	% SZS status Ended for HL406439+4.p
119976.14/16257.49	% SZS status Started for HL406440+5.p
119976.14/16257.49	% SZS status GaveUp for HL406440+5.p
119976.14/16257.49	% SZS status Ended for HL406440+5.p
119979.80/16257.83	% SZS status Started for HL406440+4.p
119979.80/16257.83	% SZS status GaveUp for HL406440+4.p
119979.80/16257.83	eprover: CPU time limit exceeded, terminating
119979.80/16257.83	% SZS status Ended for HL406440+4.p
120002.02/16260.61	% SZS status Started for HL406441+4.p
120002.02/16260.61	% SZS status GaveUp for HL406441+4.p
120002.02/16260.61	eprover: CPU time limit exceeded, terminating
120002.02/16260.61	% SZS status Ended for HL406441+4.p
120002.02/16260.65	% SZS status Started for HL406441+5.p
120002.02/16260.65	% SZS status GaveUp for HL406441+5.p
120002.02/16260.65	% SZS status Ended for HL406441+5.p
120025.79/16263.67	% SZS status Started for HL406443+5.p
120025.79/16263.67	% SZS status GaveUp for HL406443+5.p
120025.79/16263.67	% SZS status Ended for HL406443+5.p
120029.95/16264.18	% SZS status Started for HL406443+4.p
120029.95/16264.18	% SZS status GaveUp for HL406443+4.p
120029.95/16264.18	eprover: CPU time limit exceeded, terminating
120029.95/16264.18	% SZS status Ended for HL406443+4.p
120040.58/16265.45	% SZS status Started for HL406445+4.p
120040.58/16265.45	% SZS status GaveUp for HL406445+4.p
120040.58/16265.45	eprover: CPU time limit exceeded, terminating
120040.58/16265.45	% SZS status Ended for HL406445+4.p
120041.16/16265.58	% SZS status Started for HL406445+5.p
120041.16/16265.58	% SZS status GaveUp for HL406445+5.p
120041.16/16265.58	% SZS status Ended for HL406445+5.p
120056.91/16267.58	% SZS status Started for HL406446+5.p
120056.91/16267.58	% SZS status GaveUp for HL406446+5.p
120056.91/16267.58	% SZS status Ended for HL406446+5.p
120060.45/16268.07	% SZS status Started for HL406446+4.p
120060.45/16268.07	% SZS status GaveUp for HL406446+4.p
120060.45/16268.07	eprover: CPU time limit exceeded, terminating
120060.45/16268.07	% SZS status Ended for HL406446+4.p
120081.27/16270.63	% SZS status Started for HL406447+5.p
120081.27/16270.63	% SZS status GaveUp for HL406447+5.p
120081.27/16270.63	% SZS status Ended for HL406447+5.p
120084.68/16271.07	% SZS status Started for HL406447+4.p
120084.68/16271.07	% SZS status GaveUp for HL406447+4.p
120084.68/16271.07	eprover: CPU time limit exceeded, terminating
120084.68/16271.07	% SZS status Ended for HL406447+4.p
120107.66/16273.90	% SZS status Started for HL406448+5.p
120107.66/16273.90	% SZS status GaveUp for HL406448+5.p
120107.66/16273.90	% SZS status Ended for HL406448+5.p
120108.43/16274.06	% SZS status Started for HL406448+4.p
120108.43/16274.06	% SZS status GaveUp for HL406448+4.p
120108.43/16274.06	eprover: CPU time limit exceeded, terminating
120108.43/16274.06	% SZS status Ended for HL406448+4.p
120118.12/16275.23	% SZS status Started for HL406449+5.p
120118.12/16275.23	% SZS status GaveUp for HL406449+5.p
120118.12/16275.23	% SZS status Ended for HL406449+5.p
120123.72/16275.99	% SZS status Started for HL406449+4.p
120123.72/16275.99	% SZS status GaveUp for HL406449+4.p
120123.72/16275.99	eprover: CPU time limit exceeded, terminating
120123.72/16275.99	% SZS status Ended for HL406449+4.p
120137.55/16277.76	% SZS status Started for HL406451+5.p
120137.55/16277.76	% SZS status GaveUp for HL406451+5.p
120137.55/16277.76	% SZS status Ended for HL406451+5.p
120144.86/16278.64	% SZS status Started for HL406451+4.p
120144.86/16278.64	% SZS status GaveUp for HL406451+4.p
120144.86/16278.64	eprover: CPU time limit exceeded, terminating
120144.86/16278.64	% SZS status Ended for HL406451+4.p
120161.99/16280.72	% SZS status Started for HL406453+5.p
120161.99/16280.72	% SZS status GaveUp for HL406453+5.p
120161.99/16280.72	% SZS status Ended for HL406453+5.p
120168.40/16281.52	% SZS status Started for HL406453+4.p
120168.40/16281.52	% SZS status GaveUp for HL406453+4.p
120168.40/16281.52	eprover: CPU time limit exceeded, terminating
120168.40/16281.52	% SZS status Ended for HL406453+4.p
120185.45/16283.73	% SZS status Started for HL406454+5.p
120185.45/16283.73	% SZS status GaveUp for HL406454+5.p
120185.45/16283.73	% SZS status Ended for HL406454+5.p
120193.04/16284.67	% SZS status Started for HL406454+4.p
120193.04/16284.67	% SZS status GaveUp for HL406454+4.p
120193.04/16284.67	eprover: CPU time limit exceeded, terminating
120193.04/16284.67	% SZS status Ended for HL406454+4.p
120200.30/16285.65	% SZS status Started for HL406455+5.p
120200.30/16285.65	% SZS status GaveUp for HL406455+5.p
120200.30/16285.65	% SZS status Ended for HL406455+5.p
120200.72/16285.70	% SZS status Started for HL406455+4.p
120200.72/16285.70	% SZS status GaveUp for HL406455+4.p
120200.72/16285.70	eprover: CPU time limit exceeded, terminating
120200.72/16285.70	% SZS status Ended for HL406455+4.p
120222.34/16288.39	% SZS status Started for HL406456+5.p
120222.34/16288.39	% SZS status GaveUp for HL406456+5.p
120222.34/16288.39	% SZS status Ended for HL406456+5.p
120224.88/16288.72	% SZS status Started for HL406456+4.p
120224.88/16288.72	% SZS status GaveUp for HL406456+4.p
120224.88/16288.72	eprover: CPU time limit exceeded, terminating
120224.88/16288.72	% SZS status Ended for HL406456+4.p
120245.12/16291.27	% SZS status Started for HL406457+5.p
120245.12/16291.27	% SZS status GaveUp for HL406457+5.p
120245.12/16291.27	% SZS status Ended for HL406457+5.p
120245.91/16291.36	% SZS status Started for HL406457+4.p
120245.91/16291.36	% SZS status GaveUp for HL406457+4.p
120245.91/16291.36	eprover: CPU time limit exceeded, terminating
120245.91/16291.36	% SZS status Ended for HL406457+4.p
120268.84/16294.25	% SZS status Started for HL406458+4.p
120268.84/16294.25	% SZS status GaveUp for HL406458+4.p
120268.84/16294.25	eprover: CPU time limit exceeded, terminating
120268.84/16294.25	% SZS status Ended for HL406458+4.p
120271.15/16294.66	% SZS status Started for HL406458+5.p
120271.15/16294.66	% SZS status GaveUp for HL406458+5.p
120271.15/16294.66	% SZS status Ended for HL406458+5.p
120278.34/16295.46	% SZS status Started for HL406459+5.p
120278.34/16295.46	% SZS status GaveUp for HL406459+5.p
120278.34/16295.46	% SZS status Ended for HL406459+5.p
120283.81/16296.14	% SZS status Started for HL406459+4.p
120283.81/16296.14	% SZS status GaveUp for HL406459+4.p
120283.81/16296.14	eprover: CPU time limit exceeded, terminating
120283.81/16296.14	% SZS status Ended for HL406459+4.p
120301.73/16298.43	% SZS status Started for HL406460+5.p
120301.73/16298.43	% SZS status GaveUp for HL406460+5.p
120301.73/16298.43	% SZS status Ended for HL406460+5.p
120309.57/16299.33	% SZS status Started for HL406460+4.p
120309.57/16299.33	% SZS status GaveUp for HL406460+4.p
120309.57/16299.33	eprover: CPU time limit exceeded, terminating
120309.57/16299.33	% SZS status Ended for HL406460+4.p
120322.95/16301.05	% SZS status Started for HL406462+5.p
120322.95/16301.05	% SZS status GaveUp for HL406462+5.p
120322.95/16301.05	% SZS status Ended for HL406462+5.p
120327.73/16301.66	% SZS status Started for HL406462+4.p
120327.73/16301.66	% SZS status GaveUp for HL406462+4.p
120327.73/16301.66	eprover: CPU time limit exceeded, terminating
120327.73/16301.66	% SZS status Ended for HL406462+4.p
120349.85/16304.41	% SZS status Started for HL406463+5.p
120349.85/16304.41	% SZS status GaveUp for HL406463+5.p
120349.85/16304.41	% SZS status Ended for HL406463+5.p
120352.20/16304.79	% SZS status Started for HL406463+4.p
120352.20/16304.79	% SZS status GaveUp for HL406463+4.p
120352.20/16304.79	eprover: CPU time limit exceeded, terminating
120352.20/16304.79	% SZS status Ended for HL406463+4.p
120361.99/16305.95	% SZS status Started for HL406464+5.p
120361.99/16305.95	% SZS status GaveUp for HL406464+5.p
120361.99/16305.95	% SZS status Ended for HL406464+5.p
120365.02/16306.36	% SZS status Started for HL406464+4.p
120365.02/16306.36	% SZS status GaveUp for HL406464+4.p
120365.02/16306.36	eprover: CPU time limit exceeded, terminating
120365.02/16306.36	% SZS status Ended for HL406464+4.p
120386.52/16309.05	% SZS status Started for HL406465+5.p
120386.52/16309.05	% SZS status GaveUp for HL406465+5.p
120386.52/16309.05	% SZS status Ended for HL406465+5.p
120386.52/16309.08	% SZS status Started for HL406465+4.p
120386.52/16309.08	% SZS status GaveUp for HL406465+4.p
120386.52/16309.08	eprover: CPU time limit exceeded, terminating
120386.52/16309.08	% SZS status Ended for HL406465+4.p
120405.32/16311.49	% SZS status Started for HL406468+5.p
120405.32/16311.49	% SZS status GaveUp for HL406468+5.p
120405.32/16311.49	% SZS status Ended for HL406468+5.p
120405.71/16311.57	% SZS status Started for HL406468+4.p
120405.71/16311.57	% SZS status GaveUp for HL406468+4.p
120405.71/16311.57	eprover: CPU time limit exceeded, terminating
120405.71/16311.57	% SZS status Ended for HL406468+4.p
120429.20/16314.51	% SZS status Started for HL406469+5.p
120429.20/16314.51	% SZS status GaveUp for HL406469+5.p
120429.20/16314.51	% SZS status Ended for HL406469+5.p
120436.68/16315.43	% SZS status Started for HL406469+4.p
120436.68/16315.43	% SZS status GaveUp for HL406469+4.p
120436.68/16315.43	eprover: CPU time limit exceeded, terminating
120436.68/16315.43	% SZS status Ended for HL406469+4.p
120443.25/16316.22	% SZS status Started for HL406470+5.p
120443.25/16316.22	% SZS status GaveUp for HL406470+5.p
120443.25/16316.22	% SZS status Ended for HL406470+5.p
120445.13/16316.43	% SZS status Started for HL406470+4.p
120445.13/16316.43	% SZS status GaveUp for HL406470+4.p
120445.13/16316.43	eprover: CPU time limit exceeded, terminating
120445.13/16316.43	% SZS status Ended for HL406470+4.p
120464.40/16318.86	% SZS status Started for HL406471+5.p
120464.40/16318.86	% SZS status GaveUp for HL406471+5.p
120464.40/16318.86	% SZS status Ended for HL406471+5.p
120465.38/16319.27	% SZS status Started for HL406475+4.p
120465.38/16319.27	% SZS status GaveUp for HL406475+4.p
120465.38/16319.27	eprover: CPU time limit exceeded, terminating
120465.38/16319.27	% SZS status Ended for HL406475+4.p
120469.22/16319.48	% SZS status Started for HL406471+4.p
120469.22/16319.48	% SZS status GaveUp for HL406471+4.p
120469.22/16319.48	eprover: CPU time limit exceeded, terminating
120469.22/16319.48	% SZS status Ended for HL406471+4.p
120488.20/16321.91	% SZS status Started for HL406473+5.p
120488.20/16321.91	% SZS status GaveUp for HL406473+5.p
120488.20/16321.91	% SZS status Ended for HL406473+5.p
120489.06/16322.04	% SZS status Started for HL406473+4.p
120489.06/16322.04	% SZS status GaveUp for HL406473+4.p
120489.06/16322.04	eprover: CPU time limit exceeded, terminating
120489.06/16322.04	% SZS status Ended for HL406473+4.p
120512.64/16324.97	% SZS status Started for HL406474+4.p
120512.64/16324.97	% SZS status GaveUp for HL406474+4.p
120512.64/16324.97	eprover: CPU time limit exceeded, terminating
120512.64/16324.97	% SZS status Ended for HL406474+4.p
120514.20/16325.18	% SZS status Started for HL406474+5.p
120514.20/16325.18	% SZS status GaveUp for HL406474+5.p
120514.20/16325.18	% SZS status Ended for HL406474+5.p
120519.51/16325.87	% SZS status Started for HL406475+5.p
120519.51/16325.87	% SZS status GaveUp for HL406475+5.p
120519.51/16325.87	% SZS status Ended for HL406475+5.p
120522.58/16326.21	% SZS status Started for HL406476+5.p
120522.58/16326.21	% SZS status Theorem for HL406476+5.p
120522.58/16326.21	% SZS status Ended for HL406476+5.p
120527.72/16326.87	% SZS status Started for HL406478+5.p
120527.72/16326.87	% SZS status Theorem for HL406478+5.p
120527.72/16326.87	% SZS status Ended for HL406478+5.p
120543.88/16328.94	% SZS status Started for HL406477+5.p
120543.88/16328.94	% SZS status Theorem for HL406477+5.p
120543.88/16328.94	% SZS status Ended for HL406477+5.p
120547.60/16329.37	% SZS status Started for HL406476+4.p
120547.60/16329.37	% SZS status GaveUp for HL406476+4.p
120547.60/16329.37	eprover: CPU time limit exceeded, terminating
120547.60/16329.37	% SZS status Ended for HL406476+4.p
120553.87/16330.14	% SZS status Started for HL406477+4.p
120553.87/16330.14	% SZS status GaveUp for HL406477+4.p
120553.87/16330.14	eprover: CPU time limit exceeded, terminating
120553.87/16330.14	% SZS status Ended for HL406477+4.p
120573.79/16332.66	% SZS status Started for HL406478+4.p
120573.79/16332.66	% SZS status GaveUp for HL406478+4.p
120573.79/16332.66	eprover: CPU time limit exceeded, terminating
120573.79/16332.66	% SZS status Ended for HL406478+4.p
120596.73/16335.66	% SZS status Started for HL406479+5.p
120596.73/16335.66	% SZS status GaveUp for HL406479+5.p
120596.73/16335.66	% SZS status Ended for HL406479+5.p
120598.22/16335.91	% SZS status Started for HL406479+4.p
120598.22/16335.91	% SZS status GaveUp for HL406479+4.p
120598.22/16335.91	eprover: CPU time limit exceeded, terminating
120598.22/16335.91	% SZS status Ended for HL406479+4.p
120605.55/16336.67	% SZS status Started for HL406480+5.p
120605.55/16336.67	% SZS status GaveUp for HL406480+5.p
120605.55/16336.67	% SZS status Ended for HL406480+5.p
120605.55/16336.68	% SZS status Started for HL406480+4.p
120605.55/16336.68	% SZS status GaveUp for HL406480+4.p
120605.55/16336.68	eprover: CPU time limit exceeded, terminating
120605.55/16336.68	% SZS status Ended for HL406480+4.p
120625.27/16339.34	% SZS status Started for HL406481+5.p
120625.27/16339.34	% SZS status GaveUp for HL406481+5.p
120625.27/16339.34	% SZS status Ended for HL406481+5.p
120625.52/16339.38	% SZS status Started for HL406481+4.p
120625.52/16339.38	% SZS status GaveUp for HL406481+4.p
120625.52/16339.38	eprover: CPU time limit exceeded, terminating
120625.52/16339.38	% SZS status Ended for HL406481+4.p
120638.62/16340.89	% SZS status Started for HL406482+4.p
120638.62/16340.89	% SZS status GaveUp for HL406482+4.p
120638.62/16340.89	eprover: CPU time limit exceeded, terminating
120638.62/16340.89	% SZS status Ended for HL406482+4.p
120650.60/16342.34	% SZS status Started for HL406482+5.p
120650.60/16342.34	% SZS status GaveUp for HL406482+5.p
120650.60/16342.34	% SZS status Ended for HL406482+5.p
120656.73/16343.15	% SZS status Started for HL406484+5.p
120656.73/16343.15	% SZS status Theorem for HL406484+5.p
120656.73/16343.15	% SZS status Ended for HL406484+5.p
120679.27/16346.08	% SZS status Started for HL406484+4.p
120679.27/16346.08	% SZS status GaveUp for HL406484+4.p
120679.27/16346.08	eprover: CPU time limit exceeded, terminating
120679.27/16346.08	% SZS status Ended for HL406484+4.p
120682.05/16346.36	% SZS status Started for HL406485+5.p
120682.05/16346.36	% SZS status GaveUp for HL406485+5.p
120682.05/16346.36	% SZS status Ended for HL406485+5.p
120688.05/16347.13	% SZS status Started for HL406485+4.p
120688.05/16347.13	% SZS status GaveUp for HL406485+4.p
120688.05/16347.13	eprover: CPU time limit exceeded, terminating
120688.05/16347.13	% SZS status Ended for HL406485+4.p
120704.24/16349.13	% SZS status Started for HL406486+5.p
120704.24/16349.13	% SZS status GaveUp for HL406486+5.p
120704.24/16349.13	% SZS status Ended for HL406486+5.p
120709.35/16349.76	% SZS status Started for HL406486+4.p
120709.35/16349.76	% SZS status GaveUp for HL406486+4.p
120709.35/16349.76	eprover: CPU time limit exceeded, terminating
120709.35/16349.76	% SZS status Ended for HL406486+4.p
120721.69/16351.36	% SZS status Started for HL406487+4.p
120721.69/16351.36	% SZS status GaveUp for HL406487+4.p
120721.69/16351.36	eprover: CPU time limit exceeded, terminating
120721.69/16351.36	% SZS status Ended for HL406487+4.p
120726.95/16352.08	% SZS status Started for HL406487+5.p
120726.95/16352.08	% SZS status GaveUp for HL406487+5.p
120726.95/16352.08	% SZS status Ended for HL406487+5.p
120742.09/16353.87	% SZS status Started for HL406488+4.p
120742.09/16353.87	% SZS status GaveUp for HL406488+4.p
120742.09/16353.87	eprover: CPU time limit exceeded, terminating
120742.09/16353.87	% SZS status Ended for HL406488+4.p
120758.11/16355.88	% SZS status Started for HL406488+5.p
120758.11/16355.88	% SZS status GaveUp for HL406488+5.p
120758.11/16355.88	% SZS status Ended for HL406488+5.p
120765.81/16356.90	% SZS status Started for HL406489+5.p
120765.81/16356.90	% SZS status GaveUp for HL406489+5.p
120765.81/16356.90	% SZS status Ended for HL406489+5.p
120766.45/16356.94	% SZS status Started for HL406489+4.p
120766.45/16356.94	% SZS status GaveUp for HL406489+4.p
120766.45/16356.94	eprover: CPU time limit exceeded, terminating
120766.45/16356.94	% SZS status Ended for HL406489+4.p
120771.65/16357.67	% SZS status Started for HL406492+5.p
120771.65/16357.67	% SZS status Theorem for HL406492+5.p
120771.65/16357.67	% SZS status Ended for HL406492+5.p
120786.83/16359.47	% SZS status Started for HL406490+5.p
120786.83/16359.47	% SZS status GaveUp for HL406490+5.p
120786.83/16359.47	% SZS status Ended for HL406490+5.p
120787.39/16359.53	% SZS status Started for HL406490+4.p
120787.39/16359.53	% SZS status GaveUp for HL406490+4.p
120787.39/16359.53	eprover: CPU time limit exceeded, terminating
120787.39/16359.53	% SZS status Ended for HL406490+4.p
120803.13/16361.67	% SZS status Started for HL406491+5.p
120803.13/16361.67	% SZS status GaveUp for HL406491+5.p
120803.13/16361.67	% SZS status Ended for HL406491+5.p
120805.27/16361.77	% SZS status Started for HL406491+4.p
120805.27/16361.77	% SZS status GaveUp for HL406491+4.p
120805.27/16361.77	eprover: CPU time limit exceeded, terminating
120805.27/16361.77	% SZS status Ended for HL406491+4.p
120824.59/16364.34	% SZS status Started for HL406492+4.p
120824.59/16364.34	% SZS status GaveUp for HL406492+4.p
120824.59/16364.34	eprover: CPU time limit exceeded, terminating
120824.59/16364.34	% SZS status Ended for HL406492+4.p
120846.37/16367.04	% SZS status Started for HL406493+5.p
120846.37/16367.04	% SZS status GaveUp for HL406493+5.p
120846.37/16367.04	% SZS status Ended for HL406493+5.p
120851.48/16367.69	% SZS status Started for HL406493+4.p
120851.48/16367.69	% SZS status GaveUp for HL406493+4.p
120851.48/16367.69	eprover: CPU time limit exceeded, terminating
120851.48/16367.69	% SZS status Ended for HL406493+4.p
120855.23/16368.19	% SZS status Started for HL406494+4.p
120855.23/16368.19	% SZS status GaveUp for HL406494+4.p
120855.23/16368.19	eprover: CPU time limit exceeded, terminating
120855.23/16368.19	% SZS status Ended for HL406494+4.p
120863.29/16369.21	% SZS status Started for HL406494+5.p
120863.29/16369.21	% SZS status GaveUp for HL406494+5.p
120863.29/16369.21	% SZS status Ended for HL406494+5.p
120871.31/16370.21	% SZS status Started for HL406495+4.p
120871.31/16370.21	% SZS status GaveUp for HL406495+4.p
120871.31/16370.21	eprover: CPU time limit exceeded, terminating
120871.31/16370.21	% SZS status Ended for HL406495+4.p
120879.07/16371.21	% SZS status Started for HL406495+5.p
120879.07/16371.21	% SZS status GaveUp for HL406495+5.p
120879.07/16371.21	% SZS status Ended for HL406495+5.p
120887.55/16372.32	% SZS status Started for HL406496+4.p
120887.55/16372.32	% SZS status GaveUp for HL406496+4.p
120887.55/16372.32	eprover: CPU time limit exceeded, terminating
120887.55/16372.32	% SZS status Ended for HL406496+4.p
120901.70/16374.18	% SZS status Started for HL406496+5.p
120901.70/16374.18	% SZS status GaveUp for HL406496+5.p
120901.70/16374.18	% SZS status Ended for HL406496+5.p
120927.52/16377.34	% SZS status Started for HL406497+5.p
120927.52/16377.34	% SZS status GaveUp for HL406497+5.p
120927.52/16377.34	% SZS status Ended for HL406497+5.p
120928.62/16377.56	% SZS status Started for HL406497+4.p
120928.62/16377.56	% SZS status GaveUp for HL406497+4.p
120928.62/16377.56	eprover: CPU time limit exceeded, terminating
120928.62/16377.56	% SZS status Ended for HL406497+4.p
120939.98/16378.96	% SZS status Started for HL406498+4.p
120939.98/16378.96	% SZS status GaveUp for HL406498+4.p
120939.98/16378.96	eprover: CPU time limit exceeded, terminating
120939.98/16378.96	% SZS status Ended for HL406498+4.p
120939.98/16379.01	% SZS status Started for HL406498+5.p
120939.98/16379.01	% SZS status GaveUp for HL406498+5.p
120939.98/16379.01	% SZS status Ended for HL406498+5.p
120949.20/16380.39	% SZS status Started for HL406502+4.p
120949.20/16380.39	% SZS status GaveUp for HL406502+4.p
120949.20/16380.39	eprover: CPU time limit exceeded, terminating
120949.20/16380.39	% SZS status Ended for HL406502+4.p
120956.20/16381.12	% SZS status Started for HL406499+5.p
120956.20/16381.12	% SZS status GaveUp for HL406499+5.p
120956.20/16381.12	% SZS status Ended for HL406499+5.p
120957.17/16381.35	% SZS status Started for HL406499+4.p
120957.17/16381.35	% SZS status GaveUp for HL406499+4.p
120957.17/16381.35	eprover: CPU time limit exceeded, terminating
120957.17/16381.35	% SZS status Ended for HL406499+4.p
120971.30/16383.29	% SZS status Started for HL406500+4.p
120971.30/16383.29	% SZS status GaveUp for HL406500+4.p
120971.30/16383.29	eprover: CPU time limit exceeded, terminating
120971.30/16383.29	% SZS status Ended for HL406500+4.p
120974.51/16383.52	% SZS status Started for HL406504+4.p
120974.51/16383.52	% SZS status GaveUp for HL406504+4.p
120974.51/16383.52	eprover: CPU time limit exceeded, terminating
120974.51/16383.52	% SZS status Ended for HL406504+4.p
120979.73/16384.24	% SZS status Started for HL406500+5.p
120979.73/16384.24	% SZS status GaveUp for HL406500+5.p
120979.73/16384.24	% SZS status Ended for HL406500+5.p
120981.71/16384.48	% SZS status Started for HL406505+4.p
120981.71/16384.48	% SZS status GaveUp for HL406505+4.p
120981.71/16384.48	eprover: CPU time limit exceeded, terminating
120981.71/16384.48	% SZS status Ended for HL406505+4.p
120998.27/16386.63	% SZS status Started for HL406506+4.p
120998.27/16386.63	% SZS status GaveUp for HL406506+4.p
120998.27/16386.63	eprover: CPU time limit exceeded, terminating
120998.27/16386.63	% SZS status Ended for HL406506+4.p
121006.26/16387.75	% SZS status Started for HL406507+4.p
121006.26/16387.75	% SZS status GaveUp for HL406507+4.p
121006.26/16387.75	eprover: CPU time limit exceeded, terminating
121006.26/16387.75	% SZS status Ended for HL406507+4.p
121011.18/16388.36	% SZS status Started for HL406502+5.p
121011.18/16388.36	% SZS status GaveUp for HL406502+5.p
121011.18/16388.36	% SZS status Ended for HL406502+5.p
121018.92/16389.33	% SZS status Started for HL406503+5.p
121018.92/16389.33	% SZS status GaveUp for HL406503+5.p
121018.92/16389.33	% SZS status Ended for HL406503+5.p
121028.82/16390.63	% SZS status Started for HL406503+4.p
121028.82/16390.63	% SZS status GaveUp for HL406503+4.p
121028.82/16390.63	eprover: CPU time limit exceeded, terminating
121028.82/16390.63	% SZS status Ended for HL406503+4.p
121029.51/16390.79	% SZS status Started for HL406508+4.p
121029.51/16390.79	% SZS status GaveUp for HL406508+4.p
121029.51/16390.79	eprover: CPU time limit exceeded, terminating
121029.51/16390.79	% SZS status Ended for HL406508+4.p
121036.84/16391.70	% SZS status Started for HL406504+5.p
121036.84/16391.70	% SZS status GaveUp for HL406504+5.p
121036.84/16391.70	% SZS status Ended for HL406504+5.p
121043.88/16392.66	% SZS status Started for HL406509+4.p
121043.88/16392.66	% SZS status GaveUp for HL406509+4.p
121043.88/16392.66	eprover: CPU time limit exceeded, terminating
121043.88/16392.66	% SZS status Ended for HL406509+4.p
121053.96/16394.04	% SZS status Started for HL406505+5.p
121053.96/16394.04	% SZS status GaveUp for HL406505+5.p
121053.96/16394.04	% SZS status Ended for HL406505+5.p
121061.05/16395.06	% SZS status Started for HL406506+5.p
121061.05/16395.06	% SZS status GaveUp for HL406506+5.p
121061.05/16395.06	% SZS status Ended for HL406506+5.p
121079.77/16397.36	% SZS status Started for HL406507+5.p
121079.77/16397.36	% SZS status GaveUp for HL406507+5.p
121079.77/16397.36	% SZS status Ended for HL406507+5.p
121085.24/16398.16	% SZS status Started for HL406513+4.p
121085.24/16398.16	% SZS status GaveUp for HL406513+4.p
121085.24/16398.16	eprover: CPU time limit exceeded, terminating
121085.24/16398.16	% SZS status Ended for HL406513+4.p
121092.32/16399.03	% SZS status Started for HL406508+5.p
121092.32/16399.03	% SZS status GaveUp for HL406508+5.p
121092.32/16399.03	% SZS status Ended for HL406508+5.p
121109.62/16401.37	% SZS status Started for HL406509+5.p
121109.62/16401.37	% SZS status GaveUp for HL406509+5.p
121109.62/16401.37	% SZS status Ended for HL406509+5.p
121116.31/16402.23	% SZS status Started for HL406510+4.p
121116.31/16402.23	% SZS status GaveUp for HL406510+4.p
121116.31/16402.23	eprover: CPU time limit exceeded, terminating
121116.31/16402.23	% SZS status Ended for HL406510+4.p
121116.91/16402.29	% SZS status Started for HL406510+5.p
121116.91/16402.29	% SZS status GaveUp for HL406510+5.p
121116.91/16402.29	% SZS status Ended for HL406510+5.p
121130.80/16404.20	% SZS status Started for HL406511+4.p
121130.80/16404.20	% SZS status GaveUp for HL406511+4.p
121130.80/16404.20	eprover: CPU time limit exceeded, terminating
121130.80/16404.20	% SZS status Ended for HL406511+4.p
121136.40/16404.91	% SZS status Started for HL406511+5.p
121136.40/16404.91	% SZS status GaveUp for HL406511+5.p
121136.40/16404.91	% SZS status Ended for HL406511+5.p
121139.89/16405.39	% SZS status Started for HL406516+4.p
121139.89/16405.39	% SZS status GaveUp for HL406516+4.p
121139.89/16405.39	eprover: CPU time limit exceeded, terminating
121139.89/16405.39	% SZS status Ended for HL406516+4.p
121149.52/16406.67	% SZS status Started for HL406516+5.p
121149.52/16406.67	% SZS status Theorem for HL406516+5.p
121149.52/16406.67	% SZS status Ended for HL406516+5.p
121155.09/16407.46	% SZS status Started for HL406517+5.p
121155.09/16407.46	% SZS status Theorem for HL406517+5.p
121155.09/16407.46	% SZS status Ended for HL406517+5.p
121161.62/16408.32	% SZS status Started for HL406513+5.p
121161.62/16408.32	% SZS status GaveUp for HL406513+5.p
121161.62/16408.32	% SZS status Ended for HL406513+5.p
121173.22/16409.84	% SZS status Started for HL406518+4.p
121173.22/16409.84	% SZS status GaveUp for HL406518+4.p
121173.22/16409.84	eprover: CPU time limit exceeded, terminating
121173.22/16409.84	% SZS status Ended for HL406518+4.p
121173.76/16409.96	% SZS status Started for HL406514+4.p
121173.76/16409.96	% SZS status GaveUp for HL406514+4.p
121173.76/16409.96	eprover: CPU time limit exceeded, terminating
121173.76/16409.96	% SZS status Ended for HL406514+4.p
121173.76/16409.98	% SZS status Started for HL406514+5.p
121173.76/16409.98	% SZS status GaveUp for HL406514+5.p
121173.76/16409.98	% SZS status Ended for HL406514+5.p
121198.09/16413.23	% SZS status Started for HL406515+4.p
121198.09/16413.23	% SZS status GaveUp for HL406515+4.p
121198.09/16413.23	eprover: CPU time limit exceeded, terminating
121198.09/16413.23	% SZS status Ended for HL406515+4.p
121199.52/16413.48	% SZS status Started for HL406515+5.p
121199.52/16413.48	% SZS status GaveUp for HL406515+5.p
121199.52/16413.48	% SZS status Ended for HL406515+5.p
121223.88/16416.86	% SZS status Started for HL406517+4.p
121223.88/16416.86	% SZS status GaveUp for HL406517+4.p
121223.88/16416.86	eprover: CPU time limit exceeded, terminating
121223.88/16416.86	% SZS status Ended for HL406517+4.p
121237.52/16418.71	% SZS status Started for HL406518+5.p
121237.52/16418.71	% SZS status GaveUp for HL406518+5.p
121237.52/16418.71	% SZS status Ended for HL406518+5.p
121246.68/16420.09	% SZS status Started for HL406519+4.p
121246.68/16420.09	% SZS status GaveUp for HL406519+4.p
121246.68/16420.09	eprover: CPU time limit exceeded, terminating
121246.68/16420.09	% SZS status Ended for HL406519+4.p
121253.23/16421.06	% SZS status Started for HL406519+5.p
121253.23/16421.06	% SZS status GaveUp for HL406519+5.p
121253.23/16421.06	% SZS status Ended for HL406519+5.p
121256.59/16421.44	% SZS status Started for HL406520+4.p
121256.59/16421.44	% SZS status GaveUp for HL406520+4.p
121256.59/16421.44	eprover: CPU time limit exceeded, terminating
121256.59/16421.44	% SZS status Ended for HL406520+4.p
121257.73/16421.64	% SZS status Started for HL406520+5.p
121257.73/16421.64	% SZS status GaveUp for HL406520+5.p
121257.73/16421.64	% SZS status Ended for HL406520+5.p
121276.87/16424.05	% SZS status Started for HL406523+5.p
121276.87/16424.05	% SZS status GaveUp for HL406523+5.p
121276.87/16424.05	% SZS status Ended for HL406523+5.p
121292.28/16426.10	% SZS status Started for HL406523+4.p
121292.28/16426.10	% SZS status GaveUp for HL406523+4.p
121292.28/16426.10	eprover: CPU time limit exceeded, terminating
121292.28/16426.10	% SZS status Ended for HL406523+4.p
121311.14/16428.47	% SZS status Started for HL406524+4.p
121311.14/16428.47	% SZS status GaveUp for HL406524+4.p
121311.14/16428.47	eprover: CPU time limit exceeded, terminating
121311.14/16428.47	% SZS status Ended for HL406524+4.p
121316.07/16429.13	% SZS status Started for HL406524+5.p
121316.07/16429.13	% SZS status GaveUp for HL406524+5.p
121316.07/16429.13	% SZS status Ended for HL406524+5.p
121332.02/16431.18	% SZS status Started for HL406525+5.p
121332.02/16431.18	% SZS status GaveUp for HL406525+5.p
121332.02/16431.18	% SZS status Ended for HL406525+5.p
121332.77/16431.34	% SZS status Started for HL406525+4.p
121332.77/16431.34	% SZS status GaveUp for HL406525+4.p
121332.77/16431.34	eprover: CPU time limit exceeded, terminating
121332.77/16431.34	% SZS status Ended for HL406525+4.p
121338.02/16431.89	% SZS status Started for HL406526+5.p
121338.02/16431.89	% SZS status GaveUp for HL406526+5.p
121338.02/16431.89	% SZS status Ended for HL406526+5.p
121343.38/16432.56	% SZS status Started for HL406526+4.p
121343.38/16432.56	% SZS status GaveUp for HL406526+4.p
121343.38/16432.56	eprover: CPU time limit exceeded, terminating
121343.38/16432.56	% SZS status Ended for HL406526+4.p
121363.15/16435.10	% SZS status Started for HL406527+4.p
121363.15/16435.10	% SZS status GaveUp for HL406527+4.p
121363.15/16435.10	eprover: CPU time limit exceeded, terminating
121363.15/16435.10	% SZS status Ended for HL406527+4.p
121372.23/16436.34	% SZS status Started for HL406527+5.p
121372.23/16436.34	% SZS status GaveUp for HL406527+5.p
121372.23/16436.34	% SZS status Ended for HL406527+5.p
121392.81/16438.90	% SZS status Started for HL406528+5.p
121392.81/16438.90	% SZS status GaveUp for HL406528+5.p
121392.81/16438.90	% SZS status Ended for HL406528+5.p
121395.70/16439.24	% SZS status Started for HL406528+4.p
121395.70/16439.24	% SZS status GaveUp for HL406528+4.p
121395.70/16439.24	eprover: CPU time limit exceeded, terminating
121395.70/16439.24	% SZS status Ended for HL406528+4.p
121413.95/16441.65	% SZS status Started for HL406529+5.p
121413.95/16441.65	% SZS status GaveUp for HL406529+5.p
121413.95/16441.65	% SZS status Ended for HL406529+5.p
121416.05/16441.97	% SZS status Started for HL406532+4.p
121416.05/16441.97	% SZS status GaveUp for HL406532+4.p
121416.05/16441.97	eprover: CPU time limit exceeded, terminating
121416.05/16441.97	% SZS status Ended for HL406532+4.p
121418.51/16442.24	% SZS status Started for HL406529+4.p
121418.51/16442.24	% SZS status GaveUp for HL406529+4.p
121418.51/16442.24	eprover: CPU time limit exceeded, terminating
121418.51/16442.24	% SZS status Ended for HL406529+4.p
121420.27/16442.53	% SZS status Started for HL406530+4.p
121420.27/16442.53	% SZS status GaveUp for HL406530+4.p
121420.27/16442.53	eprover: CPU time limit exceeded, terminating
121420.27/16442.53	% SZS status Ended for HL406530+4.p
121420.93/16442.63	% SZS status Started for HL406530+5.p
121420.93/16442.63	% SZS status GaveUp for HL406530+5.p
121420.93/16442.63	% SZS status Ended for HL406530+5.p
121437.14/16444.70	% SZS status Started for HL406533+4.p
121437.14/16444.70	% SZS status GaveUp for HL406533+4.p
121437.14/16444.70	eprover: CPU time limit exceeded, terminating
121437.14/16444.70	% SZS status Ended for HL406533+4.p
121442.18/16445.32	% SZS status Started for HL406535+4.p
121442.18/16445.32	% SZS status GaveUp for HL406535+4.p
121442.18/16445.32	eprover: CPU time limit exceeded, terminating
121442.18/16445.32	% SZS status Ended for HL406535+4.p
121448.32/16446.19	% SZS status Started for HL406531+4.p
121448.32/16446.19	% SZS status GaveUp for HL406531+4.p
121448.32/16446.19	eprover: CPU time limit exceeded, terminating
121448.32/16446.19	% SZS status Ended for HL406531+4.p
121451.52/16446.71	% SZS status Started for HL406531+5.p
121451.52/16446.71	% SZS status GaveUp for HL406531+5.p
121451.52/16446.71	% SZS status Ended for HL406531+5.p
121464.98/16448.43	% SZS status Started for HL406537+4.p
121464.98/16448.43	% SZS status GaveUp for HL406537+4.p
121464.98/16448.43	eprover: CPU time limit exceeded, terminating
121464.98/16448.43	% SZS status Ended for HL406537+4.p
121476.75/16449.81	% SZS status Started for HL406538+4.p
121476.75/16449.81	% SZS status GaveUp for HL406538+4.p
121476.75/16449.81	eprover: CPU time limit exceeded, terminating
121476.75/16449.81	% SZS status Ended for HL406538+4.p
121476.75/16449.83	% SZS status Started for HL406532+5.p
121476.75/16449.83	% SZS status GaveUp for HL406532+5.p
121476.75/16449.83	% SZS status Ended for HL406532+5.p
121494.04/16452.11	% SZS status Started for HL406539+5.p
121494.04/16452.11	% SZS status Theorem for HL406539+5.p
121494.04/16452.11	% SZS status Ended for HL406539+5.p
121501.30/16453.10	% SZS status Started for HL406533+5.p
121501.30/16453.10	% SZS status GaveUp for HL406533+5.p
121501.30/16453.10	% SZS status Ended for HL406533+5.p
121501.83/16453.12	% SZS status Started for HL406535+5.p
121501.83/16453.12	% SZS status GaveUp for HL406535+5.p
121501.83/16453.12	% SZS status Ended for HL406535+5.p
121502.09/16453.21	% SZS status Started for HL406539+4.p
121502.09/16453.21	% SZS status GaveUp for HL406539+4.p
121502.09/16453.21	eprover: CPU time limit exceeded, terminating
121502.09/16453.21	% SZS status Ended for HL406539+4.p
121509.40/16454.12	% SZS status Started for HL406536+4.p
121509.40/16454.12	% SZS status GaveUp for HL406536+4.p
121509.40/16454.12	eprover: CPU time limit exceeded, terminating
121509.40/16454.12	% SZS status Ended for HL406536+4.p
121516.68/16455.08	% SZS status Started for HL406536+5.p
121516.68/16455.08	% SZS status GaveUp for HL406536+5.p
121516.68/16455.08	% SZS status Ended for HL406536+5.p
121522.20/16455.83	% SZS status Started for HL406538+5.p
121522.20/16455.83	% SZS status Theorem for HL406538+5.p
121522.20/16455.83	% SZS status Ended for HL406538+5.p
121525.95/16456.26	% SZS status Started for HL406541+4.p
121525.95/16456.26	% SZS status GaveUp for HL406541+4.p
121525.95/16456.26	eprover: CPU time limit exceeded, terminating
121525.95/16456.26	% SZS status Ended for HL406541+4.p
121527.94/16456.57	% SZS status Started for HL406537+5.p
121527.94/16456.57	% SZS status GaveUp for HL406537+5.p
121527.94/16456.57	% SZS status Ended for HL406537+5.p
121578.48/16463.04	% SZS status Started for HL406540+4.p
121578.48/16463.04	% SZS status GaveUp for HL406540+4.p
121578.48/16463.04	eprover: CPU time limit exceeded, terminating
121578.48/16463.04	% SZS status Ended for HL406540+4.p
121581.11/16463.35	% SZS status Started for HL406541+5.p
121581.11/16463.35	% SZS status GaveUp for HL406541+5.p
121581.11/16463.35	% SZS status Ended for HL406541+5.p
121582.32/16463.55	% SZS status Started for HL406540+5.p
121582.32/16463.55	% SZS status GaveUp for HL406540+5.p
121582.32/16463.55	% SZS status Ended for HL406540+5.p
121593.41/16465.03	% SZS status Started for HL406542+4.p
121593.41/16465.03	% SZS status GaveUp for HL406542+4.p
121593.41/16465.03	eprover: CPU time limit exceeded, terminating
121593.41/16465.03	% SZS status Ended for HL406542+4.p
121594.52/16465.11	% SZS status Started for HL406542+5.p
121594.52/16465.11	% SZS status GaveUp for HL406542+5.p
121594.52/16465.11	% SZS status Ended for HL406542+5.p
121603.38/16466.25	% SZS status Started for HL406543+4.p
121603.38/16466.25	% SZS status GaveUp for HL406543+4.p
121603.38/16466.25	eprover: CPU time limit exceeded, terminating
121603.38/16466.25	% SZS status Ended for HL406543+4.p
121607.95/16466.84	% SZS status Started for HL406543+5.p
121607.95/16466.84	% SZS status GaveUp for HL406543+5.p
121607.95/16466.84	% SZS status Ended for HL406543+5.p
121610.77/16467.21	% SZS status Started for HL406544+4.p
121610.77/16467.21	% SZS status GaveUp for HL406544+4.p
121610.77/16467.21	eprover: CPU time limit exceeded, terminating
121610.77/16467.21	% SZS status Ended for HL406544+4.p
121657.15/16473.06	% SZS status Started for HL406545+5.p
121657.15/16473.06	% SZS status GaveUp for HL406545+5.p
121657.15/16473.06	% SZS status Ended for HL406545+5.p
121657.73/16473.14	% SZS status Started for HL406544+5.p
121657.73/16473.14	% SZS status GaveUp for HL406544+5.p
121657.73/16473.14	% SZS status Ended for HL406544+5.p
121667.37/16474.51	% SZS status Started for HL406545+4.p
121667.37/16474.51	% SZS status GaveUp for HL406545+4.p
121667.37/16474.51	eprover: CPU time limit exceeded, terminating
121667.37/16474.51	% SZS status Ended for HL406545+4.p
121674.14/16475.37	% SZS status Started for HL406546+5.p
121674.14/16475.37	% SZS status GaveUp for HL406546+5.p
121674.14/16475.37	% SZS status Ended for HL406546+5.p
121679.20/16476.12	% SZS status Started for HL406546+4.p
121679.20/16476.12	% SZS status GaveUp for HL406546+4.p
121679.20/16476.12	eprover: CPU time limit exceeded, terminating
121679.20/16476.12	% SZS status Ended for HL406546+4.p
121679.37/16476.22	% SZS status Started for HL406549+4.p
121679.37/16476.22	% SZS status GaveUp for HL406549+4.p
121679.37/16476.22	eprover: CPU time limit exceeded, terminating
121679.37/16476.22	% SZS status Ended for HL406549+4.p
121684.02/16476.74	% SZS status Started for HL406547+5.p
121684.02/16476.74	% SZS status GaveUp for HL406547+5.p
121684.02/16476.74	% SZS status Ended for HL406547+5.p
121686.52/16477.07	% SZS status Started for HL406547+4.p
121686.52/16477.07	% SZS status GaveUp for HL406547+4.p
121686.52/16477.07	eprover: CPU time limit exceeded, terminating
121686.52/16477.07	% SZS status Ended for HL406547+4.p
121695.40/16478.23	% SZS status Started for HL406548+4.p
121695.40/16478.23	% SZS status GaveUp for HL406548+4.p
121695.40/16478.23	eprover: CPU time limit exceeded, terminating
121695.40/16478.23	% SZS status Ended for HL406548+4.p
121703.57/16479.28	% SZS status Started for HL406552+4.p
121703.57/16479.28	% SZS status GaveUp for HL406552+4.p
121703.57/16479.28	eprover: CPU time limit exceeded, terminating
121703.57/16479.28	% SZS status Ended for HL406552+4.p
121726.47/16482.34	% SZS status Started for HL406554+4.p
121726.47/16482.34	% SZS status GaveUp for HL406554+4.p
121726.47/16482.34	eprover: CPU time limit exceeded, terminating
121726.47/16482.34	% SZS status Ended for HL406554+4.p
121737.32/16483.89	% SZS status Started for HL406548+5.p
121737.32/16483.89	% SZS status GaveUp for HL406548+5.p
121737.32/16483.89	% SZS status Ended for HL406548+5.p
121751.11/16485.61	% SZS status Started for HL406549+5.p
121751.11/16485.61	% SZS status GaveUp for HL406549+5.p
121751.11/16485.61	% SZS status Ended for HL406549+5.p
121761.19/16486.88	% SZS status Started for HL406551+5.p
121761.19/16486.88	% SZS status GaveUp for HL406551+5.p
121761.19/16486.88	% SZS status Ended for HL406551+5.p
121761.54/16486.91	% SZS status Started for HL406552+5.p
121761.54/16486.91	% SZS status GaveUp for HL406552+5.p
121761.54/16486.91	% SZS status Ended for HL406552+5.p
121762.11/16487.07	% SZS status Started for HL406551+4.p
121762.11/16487.07	% SZS status GaveUp for HL406551+4.p
121762.11/16487.07	eprover: CPU time limit exceeded, terminating
121762.11/16487.07	% SZS status Ended for HL406551+4.p
121776.48/16488.74	% SZS status Started for HL406553+4.p
121776.48/16488.74	% SZS status GaveUp for HL406553+4.p
121776.48/16488.74	eprover: CPU time limit exceeded, terminating
121776.48/16488.74	% SZS status Ended for HL406553+4.p
121778.09/16489.01	% SZS status Started for HL406553+5.p
121778.09/16489.01	% SZS status GaveUp for HL406553+5.p
121778.09/16489.01	% SZS status Ended for HL406553+5.p
121805.69/16492.56	% SZS status Started for HL406554+5.p
121805.69/16492.56	% SZS status GaveUp for HL406554+5.p
121805.69/16492.56	% SZS status Ended for HL406554+5.p
121821.86/16494.58	% SZS status Started for HL406555+4.p
121821.86/16494.58	% SZS status GaveUp for HL406555+4.p
121821.86/16494.58	eprover: CPU time limit exceeded, terminating
121821.86/16494.58	% SZS status Ended for HL406555+4.p
121829.09/16495.36	% SZS status Started for HL406555+5.p
121829.09/16495.36	% SZS status GaveUp for HL406555+5.p
121829.09/16495.36	% SZS status Ended for HL406555+5.p
121843.88/16497.28	% SZS status Started for HL406556+4.p
121843.88/16497.28	% SZS status GaveUp for HL406556+4.p
121843.88/16497.28	eprover: CPU time limit exceeded, terminating
121843.88/16497.28	% SZS status Ended for HL406556+4.p
121846.23/16497.53	% SZS status Started for HL406557+4.p
121846.23/16497.53	% SZS status GaveUp for HL406557+4.p
121846.23/16497.53	eprover: CPU time limit exceeded, terminating
121846.23/16497.53	% SZS status Ended for HL406557+4.p
121856.84/16498.92	% SZS status Started for HL406556+5.p
121856.84/16498.92	% SZS status GaveUp for HL406556+5.p
121856.84/16498.92	% SZS status Ended for HL406556+5.p
121862.73/16499.71	% SZS status Started for HL406558+4.p
121862.73/16499.71	% SZS status GaveUp for HL406558+4.p
121862.73/16499.71	eprover: CPU time limit exceeded, terminating
121862.73/16499.71	% SZS status Ended for HL406558+4.p
121884.50/16502.40	% SZS status Started for HL406558+5.p
121884.50/16502.40	% SZS status GaveUp for HL406558+5.p
121884.50/16502.40	% SZS status Ended for HL406558+5.p
121885.12/16502.49	% SZS status Started for HL406557+5.p
121885.12/16502.49	% SZS status GaveUp for HL406557+5.p
121885.12/16502.49	eprover: CPU time limit exceeded, terminating
121885.12/16502.49	% SZS status Ended for HL406557+5.p
121904.34/16504.85	% SZS status Started for HL406559+5.p
121904.34/16504.85	% SZS status GaveUp for HL406559+5.p
121904.34/16504.85	% SZS status Ended for HL406559+5.p
121906.45/16505.28	% SZS status Started for HL406559+4.p
121906.45/16505.28	% SZS status GaveUp for HL406559+4.p
121906.45/16505.28	eprover: CPU time limit exceeded, terminating
121906.45/16505.28	% SZS status Ended for HL406559+4.p
121921.22/16507.00	% SZS status Started for HL406560+5.p
121921.22/16507.00	% SZS status GaveUp for HL406560+5.p
121921.22/16507.00	% SZS status Ended for HL406560+5.p
121928.31/16507.95	% SZS status Started for HL406560+4.p
121928.31/16507.95	% SZS status GaveUp for HL406560+4.p
121928.31/16507.95	eprover: CPU time limit exceeded, terminating
121928.31/16507.95	% SZS status Ended for HL406560+4.p
121941.30/16509.49	% SZS status Started for HL406561+5.p
121941.30/16509.49	% SZS status GaveUp for HL406561+5.p
121941.30/16509.49	% SZS status Ended for HL406561+5.p
121941.84/16509.56	% SZS status Started for HL406561+4.p
121941.84/16509.56	% SZS status GaveUp for HL406561+4.p
121941.84/16509.56	eprover: CPU time limit exceeded, terminating
121941.84/16509.56	% SZS status Ended for HL406561+4.p
121964.27/16512.38	% SZS status Started for HL406562+5.p
121964.27/16512.38	% SZS status GaveUp for HL406562+5.p
121964.27/16512.38	% SZS status Ended for HL406562+5.p
121970.77/16513.29	% SZS status Started for HL406562+4.p
121970.77/16513.29	% SZS status GaveUp for HL406562+4.p
121970.77/16513.29	eprover: CPU time limit exceeded, terminating
121970.77/16513.29	% SZS status Ended for HL406562+4.p
121983.98/16514.95	% SZS status Started for HL406563+5.p
121983.98/16514.95	% SZS status GaveUp for HL406563+5.p
121983.98/16514.95	% SZS status Ended for HL406563+5.p
121988.56/16515.49	% SZS status Started for HL406563+4.p
121988.56/16515.49	% SZS status GaveUp for HL406563+4.p
121988.56/16515.49	eprover: CPU time limit exceeded, terminating
121988.56/16515.49	% SZS status Ended for HL406563+4.p
122006.15/16517.64	% SZS status Started for HL406564+4.p
122006.15/16517.64	% SZS status GaveUp for HL406564+4.p
122006.15/16517.64	eprover: CPU time limit exceeded, terminating
122006.15/16517.64	% SZS status Ended for HL406564+4.p
122007.22/16517.78	% SZS status Started for HL406564+5.p
122007.22/16517.78	% SZS status GaveUp for HL406564+5.p
122007.22/16517.78	% SZS status Ended for HL406564+5.p
122008.81/16518.04	% SZS status Started for HL406568+4.p
122008.81/16518.04	% SZS status GaveUp for HL406568+4.p
122008.81/16518.04	eprover: CPU time limit exceeded, terminating
122008.81/16518.04	% SZS status Ended for HL406568+4.p
122017.90/16519.23	% SZS status Started for HL406565+5.p
122017.90/16519.23	% SZS status GaveUp for HL406565+5.p
122017.90/16519.23	% SZS status Ended for HL406565+5.p
122026.38/16520.29	% SZS status Started for HL406565+4.p
122026.38/16520.29	% SZS status GaveUp for HL406565+4.p
122026.38/16520.29	eprover: CPU time limit exceeded, terminating
122026.38/16520.29	% SZS status Ended for HL406565+4.p
122033.06/16521.08	% SZS status Started for HL406570+4.p
122033.06/16521.08	% SZS status GaveUp for HL406570+4.p
122033.06/16521.08	eprover: CPU time limit exceeded, terminating
122033.06/16521.08	% SZS status Ended for HL406570+4.p
122049.20/16523.07	% SZS status Started for HL406566+4.p
122049.20/16523.07	% SZS status GaveUp for HL406566+4.p
122049.20/16523.07	eprover: CPU time limit exceeded, terminating
122049.20/16523.07	% SZS status Ended for HL406566+4.p
122050.50/16523.28	% SZS status Started for HL406566+5.p
122050.50/16523.28	% SZS status GaveUp for HL406566+5.p
122050.50/16523.28	% SZS status Ended for HL406566+5.p
122066.66/16525.25	% SZS status Started for HL406568+5.p
122066.66/16525.25	% SZS status GaveUp for HL406568+5.p
122066.66/16525.25	% SZS status Ended for HL406568+5.p
122082.89/16527.33	% SZS status Started for HL406569+5.p
122082.89/16527.33	% SZS status GaveUp for HL406569+5.p
122082.89/16527.33	% SZS status Ended for HL406569+5.p
122092.83/16528.59	% SZS status Started for HL406569+4.p
122092.83/16528.59	% SZS status GaveUp for HL406569+4.p
122092.83/16528.59	eprover: CPU time limit exceeded, terminating
122092.83/16528.59	% SZS status Ended for HL406569+4.p
122096.09/16528.99	% SZS status Started for HL406570+5.p
122096.09/16528.99	% SZS status GaveUp for HL406570+5.p
122096.09/16528.99	% SZS status Ended for HL406570+5.p
122110.57/16530.80	% SZS status Started for HL406571+5.p
122110.57/16530.80	% SZS status GaveUp for HL406571+5.p
122110.57/16530.80	% SZS status Ended for HL406571+5.p
122114.66/16531.35	% SZS status Started for HL406571+4.p
122114.66/16531.35	% SZS status GaveUp for HL406571+4.p
122114.66/16531.35	eprover: CPU time limit exceeded, terminating
122114.66/16531.35	% SZS status Ended for HL406571+4.p
122117.70/16531.69	% SZS status Started for HL406576+4.p
122117.70/16531.69	% SZS status GaveUp for HL406576+4.p
122117.70/16531.69	eprover: CPU time limit exceeded, terminating
122117.70/16531.69	% SZS status Ended for HL406576+4.p
122128.06/16533.03	% SZS status Started for HL406572+5.p
122128.06/16533.03	% SZS status GaveUp for HL406572+5.p
122128.06/16533.03	% SZS status Ended for HL406572+5.p
122136.14/16534.02	% SZS status Started for HL406572+4.p
122136.14/16534.02	% SZS status GaveUp for HL406572+4.p
122136.14/16534.02	eprover: CPU time limit exceeded, terminating
122136.14/16534.02	% SZS status Ended for HL406572+4.p
122150.62/16535.92	% SZS status Started for HL406574+4.p
122150.62/16535.92	% SZS status GaveUp for HL406574+4.p
122150.62/16535.92	eprover: CPU time limit exceeded, terminating
122150.62/16535.92	% SZS status Ended for HL406574+4.p
122158.32/16536.85	% SZS status Started for HL406574+5.p
122158.32/16536.85	% SZS status GaveUp for HL406574+5.p
122158.32/16536.85	% SZS status Ended for HL406574+5.p
122159.88/16537.06	% SZS status Started for HL406580+4.p
122159.88/16537.06	% SZS status GaveUp for HL406580+4.p
122159.88/16537.06	eprover: CPU time limit exceeded, terminating
122159.88/16537.06	% SZS status Ended for HL406580+4.p
122170.55/16538.46	% SZS status Started for HL406577+5.p
122170.55/16538.46	% SZS status Theorem for HL406577+5.p
122170.55/16538.46	% SZS status Ended for HL406577+5.p
122173.82/16538.88	% SZS status Started for HL406576+5.p
122173.82/16538.88	% SZS status GaveUp for HL406576+5.p
122173.82/16538.88	% SZS status Ended for HL406576+5.p
122182.12/16539.90	% SZS status Started for HL406581+4.p
122182.12/16539.90	% SZS status GaveUp for HL406581+4.p
122182.12/16539.90	eprover: CPU time limit exceeded, terminating
122182.12/16539.90	% SZS status Ended for HL406581+4.p
122196.27/16541.71	% SZS status Started for HL406577+4.p
122196.27/16541.71	% SZS status GaveUp for HL406577+4.p
122196.27/16541.71	eprover: CPU time limit exceeded, terminating
122196.27/16541.71	% SZS status Ended for HL406577+4.p
122205.53/16542.85	% SZS status Started for HL406578+4.p
122205.53/16542.85	% SZS status GaveUp for HL406578+4.p
122205.53/16542.85	eprover: CPU time limit exceeded, terminating
122205.53/16542.85	% SZS status Ended for HL406578+4.p
122205.63/16542.85	% SZS status Started for HL406578+5.p
122205.63/16542.85	% SZS status GaveUp for HL406578+5.p
122205.63/16542.85	% SZS status Ended for HL406578+5.p
122226.27/16545.39	% SZS status Started for HL406580+5.p
122226.27/16545.39	% SZS status GaveUp for HL406580+5.p
122226.27/16545.39	% SZS status Ended for HL406580+5.p
122236.45/16546.85	% SZS status Started for HL406581+5.p
122236.45/16546.85	% SZS status GaveUp for HL406581+5.p
122236.45/16546.85	% SZS status Ended for HL406581+5.p
122253.25/16548.75	% SZS status Started for HL406582+5.p
122253.25/16548.75	% SZS status GaveUp for HL406582+5.p
122253.25/16548.75	% SZS status Ended for HL406582+5.p
122256.05/16549.19	% SZS status Started for HL406582+4.p
122256.05/16549.19	% SZS status GaveUp for HL406582+4.p
122256.05/16549.19	eprover: CPU time limit exceeded, terminating
122256.05/16549.19	% SZS status Ended for HL406582+4.p
122267.60/16550.65	% SZS status Started for HL406583+4.p
122267.60/16550.65	% SZS status GaveUp for HL406583+4.p
122267.60/16550.65	eprover: CPU time limit exceeded, terminating
122267.60/16550.65	% SZS status Ended for HL406583+4.p
122276.91/16551.79	% SZS status Started for HL406583+5.p
122276.91/16551.79	% SZS status GaveUp for HL406583+5.p
122276.91/16551.79	% SZS status Ended for HL406583+5.p
122283.65/16552.63	% SZS status Started for HL406584+5.p
122283.65/16552.63	% SZS status GaveUp for HL406584+5.p
122283.65/16552.63	% SZS status Ended for HL406584+5.p
122290.84/16553.52	% SZS status Started for HL406584+4.p
122290.84/16553.52	% SZS status GaveUp for HL406584+4.p
122290.84/16553.52	eprover: CPU time limit exceeded, terminating
122290.84/16553.52	% SZS status Ended for HL406584+4.p
122294.91/16554.06	% SZS status Started for HL406585+5.p
122294.91/16554.06	% SZS status Theorem for HL406585+5.p
122294.91/16554.06	% SZS status Ended for HL406585+5.p
122310.95/16556.06	% SZS status Started for HL406585+4.p
122310.95/16556.06	% SZS status GaveUp for HL406585+4.p
122310.95/16556.06	eprover: CPU time limit exceeded, terminating
122310.95/16556.06	% SZS status Ended for HL406585+4.p
122334.84/16559.08	% SZS status Started for HL406586+5.p
122334.84/16559.08	% SZS status GaveUp for HL406586+5.p
122334.84/16559.08	% SZS status Ended for HL406586+5.p
122338.59/16559.55	% SZS status Started for HL406586+4.p
122338.59/16559.55	% SZS status GaveUp for HL406586+4.p
122338.59/16559.55	eprover: CPU time limit exceeded, terminating
122338.59/16559.55	% SZS status Ended for HL406586+4.p
122354.00/16561.52	% SZS status Started for HL406587+4.p
122354.00/16561.52	% SZS status GaveUp for HL406587+4.p
122354.00/16561.52	eprover: CPU time limit exceeded, terminating
122354.00/16561.52	% SZS status Ended for HL406587+4.p
122356.56/16561.79	% SZS status Started for HL406587+5.p
122356.56/16561.79	% SZS status GaveUp for HL406587+5.p
122356.56/16561.79	% SZS status Ended for HL406587+5.p
122358.02/16562.15	% SZS status Started for HL406592+4.p
122358.02/16562.15	% SZS status GaveUp for HL406592+4.p
122358.02/16562.15	eprover: CPU time limit exceeded, terminating
122358.02/16562.15	% SZS status Ended for HL406592+4.p
122367.11/16563.19	% SZS status Started for HL406589+5.p
122367.11/16563.19	% SZS status GaveUp for HL406589+5.p
122367.11/16563.19	% SZS status Ended for HL406589+5.p
122369.38/16563.42	% SZS status Started for HL406589+4.p
122369.38/16563.42	% SZS status GaveUp for HL406589+4.p
122369.38/16563.42	eprover: CPU time limit exceeded, terminating
122369.38/16563.42	% SZS status Ended for HL406589+4.p
122380.44/16564.81	% SZS status Started for HL406591+4.p
122380.44/16564.81	% SZS status GaveUp for HL406591+4.p
122380.44/16564.81	eprover: CPU time limit exceeded, terminating
122380.44/16564.81	% SZS status Ended for HL406591+4.p
122388.16/16565.81	% SZS status Started for HL406591+5.p
122388.16/16565.81	% SZS status GaveUp for HL406591+5.p
122388.16/16565.81	% SZS status Ended for HL406591+5.p
122388.69/16565.84	% SZS status Started for HL406592+5.p
122388.69/16565.84	% SZS status Theorem for HL406592+5.p
122388.69/16565.84	% SZS status Ended for HL406592+5.p
122432.59/16571.42	% SZS status Started for HL406593+5.p
122432.59/16571.42	% SZS status GaveUp for HL406593+5.p
122432.59/16571.42	% SZS status Ended for HL406593+5.p
122439.14/16572.27	% SZS status Started for HL406593+4.p
122439.14/16572.27	% SZS status GaveUp for HL406593+4.p
122439.14/16572.27	eprover: CPU time limit exceeded, terminating
122439.14/16572.27	% SZS status Ended for HL406593+4.p
122445.41/16573.02	% SZS status Started for HL406598+5.p
122445.41/16573.02	% SZS status GaveUp for HL406598+5.p
122445.41/16573.02	% SZS status Ended for HL406598+5.p
122447.44/16573.28	% SZS status Started for HL406598+4.p
122447.44/16573.28	% SZS status GaveUp for HL406598+4.p
122447.44/16573.28	eprover: CPU time limit exceeded, terminating
122447.44/16573.28	% SZS status Ended for HL406598+4.p
122455.03/16574.22	% SZS status Started for HL406599+4.p
122455.03/16574.22	% SZS status GaveUp for HL406599+4.p
122455.03/16574.22	eprover: CPU time limit exceeded, terminating
122455.03/16574.22	% SZS status Ended for HL406599+4.p
122458.45/16574.65	% SZS status Started for HL406599+5.p
122458.45/16574.65	% SZS status GaveUp for HL406599+5.p
122458.45/16574.65	% SZS status Ended for HL406599+5.p
122468.41/16575.91	% SZS status Started for HL406600+5.p
122468.41/16575.91	% SZS status GaveUp for HL406600+5.p
122468.41/16575.91	% SZS status Ended for HL406600+5.p
122473.00/16576.50	% SZS status Started for HL406600+4.p
122473.00/16576.50	% SZS status GaveUp for HL406600+4.p
122473.00/16576.50	eprover: CPU time limit exceeded, terminating
122473.00/16576.50	% SZS status Ended for HL406600+4.p
122517.21/16582.09	% SZS status Started for HL406601+5.p
122517.21/16582.09	% SZS status GaveUp for HL406601+5.p
122517.21/16582.09	% SZS status Ended for HL406601+5.p
122517.21/16582.10	% SZS status Started for HL406601+4.p
122517.21/16582.10	% SZS status GaveUp for HL406601+4.p
122517.21/16582.10	eprover: CPU time limit exceeded, terminating
122517.21/16582.10	% SZS status Ended for HL406601+4.p
122525.05/16583.10	% SZS status Started for HL406602+5.p
122525.05/16583.10	% SZS status GaveUp for HL406602+5.p
122525.05/16583.10	% SZS status Ended for HL406602+5.p
122531.45/16583.89	% SZS status Started for HL406602+4.p
122531.45/16583.89	% SZS status GaveUp for HL406602+4.p
122531.45/16583.89	eprover: CPU time limit exceeded, terminating
122531.45/16583.89	% SZS status Ended for HL406602+4.p
122537.38/16584.69	% SZS status Started for HL406603+5.p
122537.38/16584.69	% SZS status GaveUp for HL406603+5.p
122537.38/16584.69	% SZS status Ended for HL406603+5.p
122543.05/16585.36	% SZS status Started for HL406603+4.p
122543.05/16585.36	% SZS status GaveUp for HL406603+4.p
122543.05/16585.36	eprover: CPU time limit exceeded, terminating
122543.05/16585.36	% SZS status Ended for HL406603+4.p
122550.71/16586.32	% SZS status Started for HL406604+5.p
122550.71/16586.32	% SZS status GaveUp for HL406604+5.p
122550.71/16586.32	% SZS status Ended for HL406604+5.p
122555.29/16587.01	% SZS status Started for HL406604+4.p
122555.29/16587.01	% SZS status GaveUp for HL406604+4.p
122555.29/16587.01	eprover: CPU time limit exceeded, terminating
122555.29/16587.01	% SZS status Ended for HL406604+4.p
122592.59/16591.61	% SZS status Started for HL406605+5.p
122592.59/16591.61	% SZS status GaveUp for HL406605+5.p
122592.59/16591.61	% SZS status Ended for HL406605+5.p
122599.56/16592.47	% SZS status Started for HL406605+4.p
122599.56/16592.47	% SZS status GaveUp for HL406605+4.p
122599.56/16592.47	eprover: CPU time limit exceeded, terminating
122599.56/16592.47	% SZS status Ended for HL406605+4.p
122609.28/16593.65	% SZS status Started for HL406606+4.p
122609.28/16593.65	% SZS status GaveUp for HL406606+4.p
122609.28/16593.65	eprover: CPU time limit exceeded, terminating
122609.28/16593.65	% SZS status Ended for HL406606+4.p
122611.35/16593.94	% SZS status Started for HL406606+5.p
122611.35/16593.94	% SZS status GaveUp for HL406606+5.p
122611.35/16593.94	% SZS status Ended for HL406606+5.p
122618.34/16594.86	% SZS status Started for HL406608+5.p
122618.34/16594.86	% SZS status GaveUp for HL406608+5.p
122618.34/16594.86	% SZS status Ended for HL406608+5.p
122621.24/16595.18	% SZS status Started for HL406608+4.p
122621.24/16595.18	% SZS status GaveUp for HL406608+4.p
122621.24/16595.18	eprover: CPU time limit exceeded, terminating
122621.24/16595.18	% SZS status Ended for HL406608+4.p
122633.58/16596.82	% SZS status Started for HL406609+5.p
122633.58/16596.82	% SZS status GaveUp for HL406609+5.p
122633.58/16596.82	% SZS status Ended for HL406609+5.p
122634.41/16596.94	% SZS status Started for HL406609+4.p
122634.41/16596.94	% SZS status GaveUp for HL406609+4.p
122634.41/16596.94	eprover: CPU time limit exceeded, terminating
122634.41/16596.94	% SZS status Ended for HL406609+4.p
122676.09/16602.13	% SZS status Started for HL406610+4.p
122676.09/16602.13	% SZS status GaveUp for HL406610+4.p
122676.09/16602.13	eprover: CPU time limit exceeded, terminating
122676.09/16602.13	% SZS status Ended for HL406610+4.p
122676.95/16602.28	% SZS status Started for HL406610+5.p
122676.95/16602.28	% SZS status GaveUp for HL406610+5.p
122676.95/16602.28	% SZS status Ended for HL406610+5.p
122688.70/16603.69	% SZS status Started for HL406612+5.p
122688.70/16603.69	% SZS status GaveUp for HL406612+5.p
122688.70/16603.69	% SZS status Ended for HL406612+5.p
122690.02/16603.96	% SZS status Started for HL406612+4.p
122690.02/16603.96	% SZS status GaveUp for HL406612+4.p
122690.02/16603.96	eprover: CPU time limit exceeded, terminating
122690.02/16603.96	% SZS status Ended for HL406612+4.p
122698.95/16605.02	% SZS status Started for HL406613+5.p
122698.95/16605.02	% SZS status GaveUp for HL406613+5.p
122698.95/16605.02	% SZS status Ended for HL406613+5.p
122702.39/16605.46	% SZS status Started for HL406613+4.p
122702.39/16605.46	% SZS status GaveUp for HL406613+4.p
122702.39/16605.46	eprover: CPU time limit exceeded, terminating
122702.39/16605.46	% SZS status Ended for HL406613+4.p
122712.23/16606.72	% SZS status Started for HL406614+5.p
122712.23/16606.72	% SZS status GaveUp for HL406614+5.p
122712.23/16606.72	% SZS status Ended for HL406614+5.p
122716.23/16607.19	% SZS status Started for HL406614+4.p
122716.23/16607.19	% SZS status GaveUp for HL406614+4.p
122716.23/16607.19	eprover: CPU time limit exceeded, terminating
122716.23/16607.19	% SZS status Ended for HL406614+4.p
122747.88/16611.13	% SZS status Started for HL406616+5.p
122747.88/16611.13	% SZS status Theorem for HL406616+5.p
122747.88/16611.13	% SZS status Ended for HL406616+5.p
122756.63/16612.16	% SZS status Started for HL406615+5.p
122756.63/16612.16	% SZS status GaveUp for HL406615+5.p
122756.63/16612.16	% SZS status Ended for HL406615+5.p
122760.48/16612.68	% SZS status Started for HL406615+4.p
122760.48/16612.68	% SZS status GaveUp for HL406615+4.p
122760.48/16612.68	eprover: CPU time limit exceeded, terminating
122760.48/16612.68	% SZS status Ended for HL406615+4.p
122761.35/16612.85	% SZS status Started for HL406617+5.p
122761.35/16612.85	% SZS status Theorem for HL406617+5.p
122761.35/16612.85	% SZS status Ended for HL406617+5.p
122772.16/16614.17	% SZS status Started for HL406619+4.p
122772.16/16614.17	% SZS status GaveUp for HL406619+4.p
122772.16/16614.17	eprover: CPU time limit exceeded, terminating
122772.16/16614.17	% SZS status Ended for HL406619+4.p
122772.95/16614.20	% SZS status Started for HL406616+4.p
122772.95/16614.20	% SZS status GaveUp for HL406616+4.p
122772.95/16614.20	eprover: CPU time limit exceeded, terminating
122772.95/16614.20	% SZS status Ended for HL406616+4.p
122783.51/16615.59	% SZS status Started for HL406617+4.p
122783.51/16615.59	% SZS status GaveUp for HL406617+4.p
122783.51/16615.59	eprover: CPU time limit exceeded, terminating
122783.51/16615.59	% SZS status Ended for HL406617+4.p
122794.37/16616.95	% SZS status Started for HL406618+5.p
122794.37/16616.95	% SZS status GaveUp for HL406618+5.p
122794.37/16616.95	% SZS status Ended for HL406618+5.p
122796.48/16617.23	% SZS status Started for HL406618+4.p
122796.48/16617.23	% SZS status GaveUp for HL406618+4.p
122796.48/16617.23	eprover: CPU time limit exceeded, terminating
122796.48/16617.23	% SZS status Ended for HL406618+4.p
122834.59/16622.03	% SZS status Started for HL406619+5.p
122834.59/16622.03	% SZS status GaveUp for HL406619+5.p
122834.59/16622.03	% SZS status Ended for HL406619+5.p
122840.46/16622.71	% SZS status Started for HL406621+5.p
122840.46/16622.71	% SZS status GaveUp for HL406621+5.p
122840.46/16622.71	% SZS status Ended for HL406621+5.p
122844.19/16623.18	% SZS status Started for HL406621+4.p
122844.19/16623.18	% SZS status GaveUp for HL406621+4.p
122844.19/16623.18	eprover: CPU time limit exceeded, terminating
122844.19/16623.18	% SZS status Ended for HL406621+4.p
122850.53/16624.04	% SZS status Started for HL406622+5.p
122850.53/16624.04	% SZS status GaveUp for HL406622+5.p
122850.53/16624.04	% SZS status Ended for HL406622+5.p
122856.17/16624.65	% SZS status Started for HL406622+4.p
122856.17/16624.65	% SZS status GaveUp for HL406622+4.p
122856.17/16624.65	eprover: CPU time limit exceeded, terminating
122856.17/16624.65	% SZS status Ended for HL406622+4.p
122867.68/16626.13	% SZS status Started for HL406623+4.p
122867.68/16626.13	% SZS status GaveUp for HL406623+4.p
122867.68/16626.13	eprover: CPU time limit exceeded, terminating
122867.68/16626.13	% SZS status Ended for HL406623+4.p
122872.62/16626.78	% SZS status Started for HL406623+5.p
122872.62/16626.78	% SZS status GaveUp for HL406623+5.p
122872.62/16626.78	% SZS status Ended for HL406623+5.p
122883.02/16628.05	% SZS status Started for HL406624+4.p
122883.02/16628.05	% SZS status GaveUp for HL406624+4.p
122883.02/16628.05	eprover: CPU time limit exceeded, terminating
122883.02/16628.05	% SZS status Ended for HL406624+4.p
122900.17/16630.18	% SZS status Started for HL406625+5.p
122900.17/16630.18	% SZS status Theorem for HL406625+5.p
122900.17/16630.18	% SZS status Ended for HL406625+5.p
122913.15/16631.84	% SZS status Started for HL406624+5.p
122913.15/16631.84	% SZS status GaveUp for HL406624+5.p
122913.15/16631.84	% SZS status Ended for HL406624+5.p
122924.52/16633.26	% SZS status Started for HL406625+4.p
122924.52/16633.26	% SZS status GaveUp for HL406625+4.p
122924.52/16633.26	eprover: CPU time limit exceeded, terminating
122924.52/16633.26	% SZS status Ended for HL406625+4.p
122933.50/16634.43	% SZS status Started for HL406627+5.p
122933.50/16634.43	% SZS status GaveUp for HL406627+5.p
122933.50/16634.43	% SZS status Ended for HL406627+5.p
122934.95/16634.56	% SZS status Started for HL406627+4.p
122934.95/16634.56	% SZS status GaveUp for HL406627+4.p
122934.95/16634.56	eprover: CPU time limit exceeded, terminating
122934.95/16634.56	% SZS status Ended for HL406627+4.p
122950.72/16636.62	% SZS status Started for HL406628+5.p
122950.72/16636.62	% SZS status GaveUp for HL406628+5.p
122950.72/16636.62	% SZS status Ended for HL406628+5.p
122951.56/16636.76	% SZS status Started for HL406628+4.p
122951.56/16636.76	% SZS status GaveUp for HL406628+4.p
122951.56/16636.76	eprover: CPU time limit exceeded, terminating
122951.56/16636.76	% SZS status Ended for HL406628+4.p
122966.38/16638.57	% SZS status Started for HL406629+4.p
122966.38/16638.57	% SZS status GaveUp for HL406629+4.p
122966.38/16638.57	eprover: CPU time limit exceeded, terminating
122966.38/16638.57	% SZS status Ended for HL406629+4.p
122978.05/16640.11	% SZS status Started for HL406629+5.p
122978.05/16640.11	% SZS status GaveUp for HL406629+5.p
122978.05/16640.11	% SZS status Ended for HL406629+5.p
122990.03/16641.71	% SZS status Started for HL406633+4.p
122990.03/16641.71	% SZS status GaveUp for HL406633+4.p
122990.03/16641.71	eprover: CPU time limit exceeded, terminating
122990.03/16641.71	% SZS status Ended for HL406633+4.p
122997.12/16642.54	% SZS status Started for HL406630+4.p
122997.12/16642.54	% SZS status GaveUp for HL406630+4.p
122997.12/16642.54	eprover: CPU time limit exceeded, terminating
122997.12/16642.54	% SZS status Ended for HL406630+4.p
123000.48/16642.99	% SZS status Started for HL406630+5.p
123000.48/16642.99	% SZS status GaveUp for HL406630+5.p
123000.48/16642.99	% SZS status Ended for HL406630+5.p
123012.88/16644.57	% SZS status Started for HL406631+5.p
123012.88/16644.57	% SZS status GaveUp for HL406631+5.p
123012.88/16644.57	% SZS status Ended for HL406631+5.p
123016.80/16645.19	% SZS status Started for HL406631+4.p
123016.80/16645.19	% SZS status GaveUp for HL406631+4.p
123016.80/16645.19	eprover: CPU time limit exceeded, terminating
123016.80/16645.19	% SZS status Ended for HL406631+4.p
123034.38/16647.34	% SZS status Started for HL406632+5.p
123034.38/16647.34	% SZS status GaveUp for HL406632+5.p
123034.38/16647.34	% SZS status Ended for HL406632+5.p
123039.30/16647.88	% SZS status Started for HL406632+4.p
123039.30/16647.88	% SZS status GaveUp for HL406632+4.p
123039.30/16647.88	eprover: CPU time limit exceeded, terminating
123039.30/16647.88	% SZS status Ended for HL406632+4.p
123057.72/16650.22	% SZS status Started for HL406633+5.p
123057.72/16650.22	% SZS status GaveUp for HL406633+5.p
123057.72/16650.22	% SZS status Ended for HL406633+5.p
123070.76/16651.90	% SZS status Started for HL406639+5.p
123070.76/16651.90	% SZS status Theorem for HL406639+5.p
123070.76/16651.90	% SZS status Ended for HL406639+5.p
123074.51/16652.38	% SZS status Started for HL406636+5.p
123074.51/16652.38	% SZS status GaveUp for HL406636+5.p
123074.51/16652.38	% SZS status Ended for HL406636+5.p
123074.98/16652.44	% SZS status Started for HL406636+4.p
123074.98/16652.44	% SZS status GaveUp for HL406636+4.p
123074.98/16652.44	eprover: CPU time limit exceeded, terminating
123074.98/16652.44	% SZS status Ended for HL406636+4.p
123083.01/16653.43	% SZS status Started for HL406639+4.p
123083.01/16653.43	% SZS status GaveUp for HL406639+4.p
123083.01/16653.43	eprover: CPU time limit exceeded, terminating
123083.01/16653.43	% SZS status Ended for HL406639+4.p
123102.46/16655.85	% SZS status Started for HL406640+4.p
123102.46/16655.85	% SZS status GaveUp for HL406640+4.p
123102.46/16655.85	eprover: CPU time limit exceeded, terminating
123102.46/16655.85	% SZS status Ended for HL406640+4.p
123114.08/16657.37	% SZS status Started for HL406640+5.p
123114.08/16657.37	% SZS status GaveUp for HL406640+5.p
123114.08/16657.37	% SZS status Ended for HL406640+5.p
123122.18/16658.33	% SZS status Started for HL406641+4.p
123122.18/16658.33	% SZS status GaveUp for HL406641+4.p
123122.18/16658.33	eprover: CPU time limit exceeded, terminating
123122.18/16658.33	% SZS status Ended for HL406641+4.p
123135.34/16660.02	% SZS status Started for HL406641+5.p
123135.34/16660.02	% SZS status GaveUp for HL406641+5.p
123135.34/16660.02	% SZS status Ended for HL406641+5.p
123150.47/16661.97	% SZS status Started for HL406642+5.p
123150.47/16661.97	% SZS status GaveUp for HL406642+5.p
123150.47/16661.97	% SZS status Ended for HL406642+5.p
123155.57/16662.59	% SZS status Started for HL406642+4.p
123155.57/16662.59	% SZS status GaveUp for HL406642+4.p
123155.57/16662.59	eprover: CPU time limit exceeded, terminating
123155.57/16662.59	% SZS status Ended for HL406642+4.p
123161.73/16663.31	% SZS status Started for HL406643+5.p
123161.73/16663.31	% SZS status GaveUp for HL406643+5.p
123161.73/16663.31	% SZS status Ended for HL406643+5.p
123162.17/16663.38	% SZS status Started for HL406643+4.p
123162.17/16663.38	% SZS status GaveUp for HL406643+4.p
123162.17/16663.38	eprover: CPU time limit exceeded, terminating
123162.17/16663.38	% SZS status Ended for HL406643+4.p
123172.21/16664.65	% SZS status Started for HL406645+5.p
123172.21/16664.65	% SZS status Theorem for HL406645+5.p
123172.21/16664.65	% SZS status Ended for HL406645+5.p
123185.95/16666.48	% SZS status Started for HL406645+4.p
123185.95/16666.48	% SZS status GaveUp for HL406645+4.p
123185.95/16666.48	eprover: CPU time limit exceeded, terminating
123185.95/16666.48	% SZS status Ended for HL406645+4.p
123207.03/16669.11	% SZS status Started for HL406646+4.p
123207.03/16669.11	% SZS status GaveUp for HL406646+4.p
123207.03/16669.11	eprover: CPU time limit exceeded, terminating
123207.03/16669.11	% SZS status Ended for HL406646+4.p
123213.62/16669.91	% SZS status Started for HL406646+5.p
123213.62/16669.91	% SZS status GaveUp for HL406646+5.p
123213.62/16669.91	% SZS status Ended for HL406646+5.p
123232.80/16672.37	% SZS status Started for HL406647+5.p
123232.80/16672.37	% SZS status GaveUp for HL406647+5.p
123232.80/16672.37	% SZS status Ended for HL406647+5.p
123237.01/16673.02	% SZS status Started for HL406647+4.p
123237.01/16673.02	% SZS status GaveUp for HL406647+4.p
123237.01/16673.02	eprover: CPU time limit exceeded, terminating
123237.01/16673.02	% SZS status Ended for HL406647+4.p
123242.26/16673.64	% SZS status Started for HL406649+5.p
123242.26/16673.64	% SZS status GaveUp for HL406649+5.p
123242.26/16673.64	% SZS status Ended for HL406649+5.p
123245.11/16674.04	% SZS status Started for HL406649+4.p
123245.11/16674.04	% SZS status GaveUp for HL406649+4.p
123245.11/16674.04	eprover: CPU time limit exceeded, terminating
123245.11/16674.04	% SZS status Ended for HL406649+4.p
123257.02/16675.49	% SZS status Started for HL406650+4.p
123257.02/16675.49	% SZS status GaveUp for HL406650+4.p
123257.02/16675.49	eprover: CPU time limit exceeded, terminating
123257.02/16675.49	% SZS status Ended for HL406650+4.p
123267.31/16676.81	% SZS status Started for HL406650+5.p
123267.31/16676.81	% SZS status GaveUp for HL406650+5.p
123267.31/16676.81	% SZS status Ended for HL406650+5.p
123292.41/16680.01	% SZS status Started for HL406651+5.p
123292.41/16680.01	% SZS status GaveUp for HL406651+5.p
123292.41/16680.01	% SZS status Ended for HL406651+5.p
123293.47/16680.16	% SZS status Started for HL406651+4.p
123293.47/16680.16	% SZS status GaveUp for HL406651+4.p
123293.47/16680.16	eprover: CPU time limit exceeded, terminating
123293.47/16680.16	% SZS status Ended for HL406651+4.p
123316.45/16683.25	% SZS status Started for HL406652+4.p
123316.45/16683.25	% SZS status GaveUp for HL406652+4.p
123316.45/16683.25	eprover: CPU time limit exceeded, terminating
123316.45/16683.25	% SZS status Ended for HL406652+4.p
123318.27/16683.45	% SZS status Started for HL406652+5.p
123318.27/16683.45	% SZS status GaveUp for HL406652+5.p
123318.27/16683.45	% SZS status Ended for HL406652+5.p
123324.58/16684.24	% SZS status Started for HL406653+5.p
123324.58/16684.24	% SZS status GaveUp for HL406653+5.p
123324.58/16684.24	% SZS status Ended for HL406653+5.p
123325.45/16684.41	% SZS status Started for HL406654+5.p
123325.45/16684.41	% SZS status Theorem for HL406654+5.p
123325.45/16684.41	% SZS status Ended for HL406654+5.p
123328.48/16684.72	% SZS status Started for HL406653+4.p
123328.48/16684.72	% SZS status GaveUp for HL406653+4.p
123328.48/16684.72	eprover: CPU time limit exceeded, terminating
123328.48/16684.72	% SZS status Ended for HL406653+4.p
123346.04/16687.03	% SZS status Started for HL406654+4.p
123346.04/16687.03	% SZS status GaveUp for HL406654+4.p
123346.04/16687.03	eprover: CPU time limit exceeded, terminating
123346.04/16687.03	% SZS status Ended for HL406654+4.p
123357.29/16688.45	% SZS status Started for HL406655+5.p
123357.29/16688.45	% SZS status Theorem for HL406655+5.p
123357.29/16688.45	% SZS status Ended for HL406655+5.p
123363.09/16689.22	% SZS status Started for HL406660+5.p
123363.09/16689.22	% SZS status Theorem for HL406660+5.p
123363.09/16689.22	% SZS status Ended for HL406660+5.p
123381.15/16691.46	% SZS status Started for HL406655+4.p
123381.15/16691.46	% SZS status GaveUp for HL406655+4.p
123381.15/16691.46	eprover: CPU time limit exceeded, terminating
123381.15/16691.46	% SZS status Ended for HL406655+4.p
123390.72/16692.73	% SZS status Started for HL406657+5.p
123390.72/16692.73	% SZS status Theorem for HL406657+5.p
123390.72/16692.73	% SZS status Ended for HL406657+5.p
123400.27/16693.89	% SZS status Started for HL406656+5.p
123400.27/16693.89	% SZS status GaveUp for HL406656+5.p
123400.27/16693.89	% SZS status Ended for HL406656+5.p
123403.94/16694.37	% SZS status Started for HL406656+4.p
123403.94/16694.37	% SZS status GaveUp for HL406656+4.p
123403.94/16694.37	eprover: CPU time limit exceeded, terminating
123403.94/16694.37	% SZS status Ended for HL406656+4.p
123409.56/16695.10	% SZS status Started for HL406657+4.p
123409.56/16695.10	% SZS status GaveUp for HL406657+4.p
123409.56/16695.10	eprover: CPU time limit exceeded, terminating
123409.56/16695.10	% SZS status Ended for HL406657+4.p
123413.31/16695.63	% SZS status Started for HL406660+4.p
123413.31/16695.63	% SZS status GaveUp for HL406660+4.p
123413.31/16695.63	eprover: CPU time limit exceeded, terminating
123413.31/16695.63	% SZS status Ended for HL406660+4.p
123422.52/16696.75	% SZS status Started for HL406661+5.p
123422.52/16696.75	% SZS status Theorem for HL406661+5.p
123422.52/16696.75	% SZS status Ended for HL406661+5.p
123443.50/16699.75	% SZS status Started for HL406661+4.p
123443.50/16699.75	% SZS status GaveUp for HL406661+4.p
123443.50/16699.75	eprover: CPU time limit exceeded, terminating
123443.50/16699.75	% SZS status Ended for HL406661+4.p
123468.20/16702.93	% SZS status Started for HL406662+4.p
123468.20/16702.93	% SZS status GaveUp for HL406662+4.p
123468.20/16702.93	eprover: CPU time limit exceeded, terminating
123468.20/16702.93	% SZS status Ended for HL406662+4.p
123471.95/16703.34	% SZS status Started for HL406662+5.p
123471.95/16703.34	% SZS status GaveUp for HL406662+5.p
123471.95/16703.34	% SZS status Ended for HL406662+5.p
123472.87/16703.48	% SZS status Started for HL406664+5.p
123472.87/16703.48	% SZS status Theorem for HL406664+5.p
123472.87/16703.48	% SZS status Ended for HL406664+5.p
123484.08/16704.91	% SZS status Started for HL406663+4.p
123484.08/16704.91	% SZS status GaveUp for HL406663+4.p
123484.08/16704.91	eprover: CPU time limit exceeded, terminating
123484.08/16704.91	% SZS status Ended for HL406663+4.p
123484.08/16704.93	% SZS status Started for HL406663+5.p
123484.08/16704.93	% SZS status GaveUp for HL406663+5.p
123484.08/16704.93	% SZS status Ended for HL406663+5.p
123498.05/16706.63	% SZS status Started for HL406664+4.p
123498.05/16706.63	% SZS status GaveUp for HL406664+4.p
123498.05/16706.63	eprover: CPU time limit exceeded, terminating
123498.05/16706.63	% SZS status Ended for HL406664+4.p
123508.27/16708.01	% SZS status Started for HL406668+4.p
123508.27/16708.01	% SZS status GaveUp for HL406668+4.p
123508.27/16708.01	eprover: CPU time limit exceeded, terminating
123508.27/16708.01	% SZS status Ended for HL406668+4.p
123509.35/16708.07	% SZS status Started for HL406665+4.p
123509.35/16708.07	% SZS status GaveUp for HL406665+4.p
123509.35/16708.07	eprover: CPU time limit exceeded, terminating
123509.35/16708.07	% SZS status Ended for HL406665+4.p
123523.05/16709.84	% SZS status Started for HL406665+5.p
123523.05/16709.84	% SZS status GaveUp for HL406665+5.p
123523.05/16709.84	% SZS status Ended for HL406665+5.p
123543.00/16712.33	% SZS status Started for HL406669+5.p
123543.00/16712.33	% SZS status Theorem for HL406669+5.p
123543.00/16712.33	% SZS status Ended for HL406669+5.p
123549.79/16713.18	% SZS status Started for HL406666+5.p
123549.79/16713.18	% SZS status GaveUp for HL406666+5.p
123549.79/16713.18	% SZS status Ended for HL406666+5.p
123553.95/16713.67	% SZS status Started for HL406666+4.p
123553.95/16713.67	% SZS status GaveUp for HL406666+4.p
123553.95/16713.67	eprover: CPU time limit exceeded, terminating
123553.95/16713.67	% SZS status Ended for HL406666+4.p
123558.04/16714.20	% SZS status Started for HL406667+4.p
123558.04/16714.20	% SZS status GaveUp for HL406667+4.p
123558.04/16714.20	eprover: CPU time limit exceeded, terminating
123558.04/16714.20	% SZS status Ended for HL406667+4.p
123559.65/16714.44	% SZS status Started for HL406667+5.p
123559.65/16714.44	% SZS status GaveUp for HL406667+5.p
123559.65/16714.44	% SZS status Ended for HL406667+5.p
123576.54/16716.56	% SZS status Started for HL406668+5.p
123576.54/16716.56	% SZS status GaveUp for HL406668+5.p
123576.54/16716.56	% SZS status Ended for HL406668+5.p
123591.95/16718.56	% SZS status Started for HL406669+4.p
123591.95/16718.56	% SZS status GaveUp for HL406669+4.p
123591.95/16718.56	eprover: CPU time limit exceeded, terminating
123591.95/16718.56	% SZS status Ended for HL406669+4.p
123607.55/16720.50	% SZS status Started for HL406671+4.p
123607.55/16720.50	% SZS status GaveUp for HL406671+4.p
123607.55/16720.50	eprover: CPU time limit exceeded, terminating
123607.55/16720.50	% SZS status Ended for HL406671+4.p
123619.63/16722.01	% SZS status Started for HL406671+5.p
123619.63/16722.01	% SZS status GaveUp for HL406671+5.p
123619.63/16722.01	% SZS status Ended for HL406671+5.p
123632.17/16723.55	% SZS status Started for HL406672+5.p
123632.17/16723.55	% SZS status GaveUp for HL406672+5.p
123632.17/16723.55	% SZS status Ended for HL406672+5.p
123633.65/16723.82	% SZS status Started for HL406672+4.p
123633.65/16723.82	% SZS status GaveUp for HL406672+4.p
123633.65/16723.82	eprover: CPU time limit exceeded, terminating
123633.65/16723.82	% SZS status Ended for HL406672+4.p
123638.35/16724.37	% SZS status Started for HL406674+5.p
123638.35/16724.37	% SZS status GaveUp for HL406674+5.p
123638.35/16724.37	% SZS status Ended for HL406674+5.p
123644.88/16725.17	% SZS status Started for HL406674+4.p
123644.88/16725.17	% SZS status GaveUp for HL406674+4.p
123644.88/16725.17	eprover: CPU time limit exceeded, terminating
123644.88/16725.17	% SZS status Ended for HL406674+4.p
123661.49/16727.36	% SZS status Started for HL406675+4.p
123661.49/16727.36	% SZS status GaveUp for HL406675+4.p
123661.49/16727.36	eprover: CPU time limit exceeded, terminating
123661.49/16727.36	% SZS status Ended for HL406675+4.p
123664.11/16727.62	% SZS status Started for HL406678+5.p
123664.11/16727.62	% SZS status Theorem for HL406678+5.p
123664.11/16727.62	% SZS status Ended for HL406678+5.p
123671.91/16728.65	% SZS status Started for HL406675+5.p
123671.91/16728.65	% SZS status GaveUp for HL406675+5.p
123671.91/16728.65	% SZS status Ended for HL406675+5.p
123685.97/16730.43	% SZS status Started for HL406679+4.p
123685.97/16730.43	% SZS status GaveUp for HL406679+4.p
123685.97/16730.43	eprover: CPU time limit exceeded, terminating
123685.97/16730.43	% SZS status Ended for HL406679+4.p
123690.77/16731.03	% SZS status Started for HL406676+4.p
123690.77/16731.03	% SZS status GaveUp for HL406676+4.p
123690.77/16731.03	eprover: CPU time limit exceeded, terminating
123690.77/16731.03	% SZS status Ended for HL406676+4.p
123698.34/16731.98	% SZS status Started for HL406676+5.p
123698.34/16731.98	% SZS status GaveUp for HL406676+5.p
123698.34/16731.98	% SZS status Ended for HL406676+5.p
123700.22/16732.34	% SZS status Started for HL406679+5.p
123700.22/16732.34	% SZS status GaveUp for HL406679+5.p
123700.22/16732.34	% SZS status Ended for HL406679+5.p
123711.66/16733.64	% SZS status Started for HL406677+5.p
123711.66/16733.64	% SZS status GaveUp for HL406677+5.p
123711.66/16733.64	% SZS status Ended for HL406677+5.p
123717.82/16734.51	% SZS status Started for HL406677+4.p
123717.82/16734.51	% SZS status GaveUp for HL406677+4.p
123717.82/16734.51	eprover: CPU time limit exceeded, terminating
123717.82/16734.51	% SZS status Ended for HL406677+4.p
123725.06/16735.45	% SZS status Started for HL406678+4.p
123725.06/16735.45	% SZS status GaveUp for HL406678+4.p
123725.06/16735.45	eprover: CPU time limit exceeded, terminating
123725.06/16735.45	% SZS status Ended for HL406678+4.p
123756.55/16739.43	% SZS status Started for HL406680+4.p
123756.55/16739.43	% SZS status GaveUp for HL406680+4.p
123756.55/16739.43	eprover: CPU time limit exceeded, terminating
123756.55/16739.43	% SZS status Ended for HL406680+4.p
123762.63/16740.22	% SZS status Started for HL406680+5.p
123762.63/16740.22	% SZS status GaveUp for HL406680+5.p
123762.63/16740.22	% SZS status Ended for HL406680+5.p
123777.12/16742.23	% SZS status Started for HL406681+5.p
123777.12/16742.23	% SZS status GaveUp for HL406681+5.p
123777.12/16742.23	% SZS status Ended for HL406681+5.p
123777.58/16742.31	% SZS status Started for HL406681+4.p
123777.58/16742.31	% SZS status GaveUp for HL406681+4.p
123777.58/16742.31	eprover: CPU time limit exceeded, terminating
123777.58/16742.31	% SZS status Ended for HL406681+4.p
123789.06/16743.70	% SZS status Started for HL406682+4.p
123789.06/16743.70	% SZS status GaveUp for HL406682+4.p
123789.06/16743.70	eprover: CPU time limit exceeded, terminating
123789.06/16743.70	% SZS status Ended for HL406682+4.p
123790.99/16744.04	% SZS status Started for HL406682+5.p
123790.99/16744.04	% SZS status GaveUp for HL406682+5.p
123790.99/16744.04	% SZS status Ended for HL406682+5.p
123804.59/16745.79	% SZS status Started for HL406683+4.p
123804.59/16745.79	% SZS status GaveUp for HL406683+4.p
123804.59/16745.79	eprover: CPU time limit exceeded, terminating
123804.59/16745.79	% SZS status Ended for HL406683+4.p
123805.91/16745.97	% SZS status Started for HL406683+5.p
123805.91/16745.97	% SZS status GaveUp for HL406683+5.p
123805.91/16745.97	% SZS status Ended for HL406683+5.p
123820.55/16747.76	% SZS status Started for HL406684+5.p
123820.55/16747.76	% SZS status Theorem for HL406684+5.p
123820.55/16747.76	% SZS status Ended for HL406684+5.p
123822.77/16747.98	% SZS status Started for HL406685+5.p
123822.77/16747.98	% SZS status GaveUp for HL406685+5.p
123822.77/16747.98	% SZS status Ended for HL406685+5.p
123844.98/16750.84	% SZS status Started for HL406684+4.p
123844.98/16750.84	% SZS status GaveUp for HL406684+4.p
123844.98/16750.84	eprover: CPU time limit exceeded, terminating
123844.98/16750.84	% SZS status Ended for HL406684+4.p
123864.15/16753.34	% SZS status Started for HL406685+4.p
123864.15/16753.34	% SZS status GaveUp for HL406685+4.p
123864.15/16753.34	eprover: CPU time limit exceeded, terminating
123864.15/16753.34	% SZS status Ended for HL406685+4.p
123872.47/16754.38	% SZS status Started for HL406687+4.p
123872.47/16754.38	% SZS status GaveUp for HL406687+4.p
123872.47/16754.38	eprover: CPU time limit exceeded, terminating
123872.47/16754.38	% SZS status Ended for HL406687+4.p
123873.33/16754.52	% SZS status Started for HL406687+5.p
123873.33/16754.52	% SZS status GaveUp for HL406687+5.p
123873.33/16754.52	% SZS status Ended for HL406687+5.p
123887.29/16756.29	% SZS status Started for HL406689+5.p
123887.29/16756.29	% SZS status GaveUp for HL406689+5.p
123887.29/16756.29	% SZS status Ended for HL406689+5.p
123893.17/16756.91	% SZS status Started for HL406689+4.p
123893.17/16756.91	% SZS status GaveUp for HL406689+4.p
123893.17/16756.91	eprover: CPU time limit exceeded, terminating
123893.17/16756.91	% SZS status Ended for HL406689+4.p
123902.80/16758.19	% SZS status Started for HL406690+5.p
123902.80/16758.19	% SZS status GaveUp for HL406690+5.p
123902.80/16758.19	% SZS status Ended for HL406690+5.p
123903.66/16758.45	% SZS status Started for HL406690+4.p
123903.66/16758.45	% SZS status GaveUp for HL406690+4.p
123903.66/16758.45	eprover: CPU time limit exceeded, terminating
123903.66/16758.45	% SZS status Ended for HL406690+4.p
123929.84/16761.55	% SZS status Started for HL406691+4.p
123929.84/16761.55	% SZS status GaveUp for HL406691+4.p
123929.84/16761.55	eprover: CPU time limit exceeded, terminating
123929.84/16761.55	% SZS status Ended for HL406691+4.p
123942.12/16763.13	% SZS status Started for HL406691+5.p
123942.12/16763.13	% SZS status GaveUp for HL406691+5.p
123942.12/16763.13	% SZS status Ended for HL406691+5.p
123949.88/16764.45	% SZS status Started for HL406693+5.p
123949.88/16764.45	% SZS status GaveUp for HL406693+5.p
123949.88/16764.45	% SZS status Ended for HL406693+5.p
123956.49/16765.01	% SZS status Started for HL406693+4.p
123956.49/16765.01	% SZS status GaveUp for HL406693+4.p
123956.49/16765.01	eprover: CPU time limit exceeded, terminating
123956.49/16765.01	% SZS status Ended for HL406693+4.p
123971.11/16766.70	% SZS status Started for HL406694+5.p
123971.11/16766.70	% SZS status GaveUp for HL406694+5.p
123971.11/16766.70	% SZS status Ended for HL406694+5.p
123971.91/16766.88	% SZS status Started for HL406694+4.p
123971.91/16766.88	% SZS status GaveUp for HL406694+4.p
123971.91/16766.88	eprover: CPU time limit exceeded, terminating
123971.91/16766.88	% SZS status Ended for HL406694+4.p
123983.38/16768.33	% SZS status Started for HL406695+5.p
123983.38/16768.33	% SZS status GaveUp for HL406695+5.p
123983.38/16768.33	% SZS status Ended for HL406695+5.p
123987.18/16768.75	% SZS status Started for HL406695+4.p
123987.18/16768.75	% SZS status GaveUp for HL406695+4.p
123987.18/16768.75	eprover: CPU time limit exceeded, terminating
123987.18/16768.75	% SZS status Ended for HL406695+4.p
124014.02/16772.17	% SZS status Started for HL406697+4.p
124014.02/16772.17	% SZS status GaveUp for HL406697+4.p
124014.02/16772.17	eprover: CPU time limit exceeded, terminating
124014.02/16772.17	% SZS status Ended for HL406697+4.p
124020.97/16773.07	% SZS status Started for HL406697+5.p
124020.97/16773.07	% SZS status GaveUp for HL406697+5.p
124020.97/16773.07	% SZS status Ended for HL406697+5.p
124036.93/16775.05	% SZS status Started for HL406698+4.p
124036.93/16775.05	% SZS status GaveUp for HL406698+4.p
124036.93/16775.05	eprover: CPU time limit exceeded, terminating
124036.93/16775.05	% SZS status Ended for HL406698+4.p
124036.93/16775.05	% SZS status Started for HL406698+5.p
124036.93/16775.05	% SZS status GaveUp for HL406698+5.p
124036.93/16775.05	% SZS status Ended for HL406698+5.p
124038.12/16775.21	% SZS status Started for HL406702+4.p
124038.12/16775.21	% SZS status GaveUp for HL406702+4.p
124038.12/16775.21	eprover: CPU time limit exceeded, terminating
124038.12/16775.21	% SZS status Ended for HL406702+4.p
124051.07/16776.77	% SZS status Started for HL406699+5.p
124051.07/16776.77	% SZS status GaveUp for HL406699+5.p
124051.07/16776.77	% SZS status Ended for HL406699+5.p
124055.34/16777.33	% SZS status Started for HL406699+4.p
124055.34/16777.33	% SZS status GaveUp for HL406699+4.p
124055.34/16777.33	eprover: CPU time limit exceeded, terminating
124055.34/16777.33	% SZS status Ended for HL406699+4.p
124060.66/16778.08	% SZS status Started for HL406704+4.p
124060.66/16778.08	% SZS status GaveUp for HL406704+4.p
124060.66/16778.08	eprover: CPU time limit exceeded, terminating
124060.66/16778.08	% SZS status Ended for HL406704+4.p
124062.57/16778.25	% SZS status Started for HL406705+4.p
124062.57/16778.25	% SZS status GaveUp for HL406705+4.p
124062.57/16778.25	eprover: CPU time limit exceeded, terminating
124062.57/16778.25	% SZS status Ended for HL406705+4.p
124068.25/16778.98	% SZS status Started for HL406700+5.p
124068.25/16778.98	% SZS status GaveUp for HL406700+5.p
124068.25/16778.98	% SZS status Ended for HL406700+5.p
124069.25/16779.20	% SZS status Started for HL406700+4.p
124069.25/16779.20	% SZS status GaveUp for HL406700+4.p
124069.25/16779.20	eprover: CPU time limit exceeded, terminating
124069.25/16779.20	% SZS status Ended for HL406700+4.p
124078.43/16780.36	% SZS status Started for HL406706+4.p
124078.43/16780.36	% SZS status GaveUp for HL406706+4.p
124078.43/16780.36	eprover: CPU time limit exceeded, terminating
124078.43/16780.36	% SZS status Ended for HL406706+4.p
124084.52/16781.17	% SZS status Started for HL406702+5.p
124084.52/16781.17	% SZS status GaveUp for HL406702+5.p
124084.52/16781.17	% SZS status Ended for HL406702+5.p
124085.95/16781.31	% SZS status Started for HL406707+4.p
124085.95/16781.31	% SZS status GaveUp for HL406707+4.p
124085.95/16781.31	eprover: CPU time limit exceeded, terminating
124085.95/16781.31	% SZS status Ended for HL406707+4.p
124091.55/16782.00	% SZS status Started for HL406704+5.p
124091.55/16782.00	% SZS status GaveUp for HL406704+5.p
124091.55/16782.00	% SZS status Ended for HL406704+5.p
124092.76/16782.23	% SZS status Started for HL406708+4.p
124092.76/16782.23	% SZS status GaveUp for HL406708+4.p
124092.76/16782.23	eprover: CPU time limit exceeded, terminating
124092.76/16782.23	% SZS status Ended for HL406708+4.p
124104.52/16783.69	% SZS status Started for HL406705+5.p
124104.52/16783.69	% SZS status GaveUp for HL406705+5.p
124104.52/16783.69	% SZS status Ended for HL406705+5.p
124108.56/16784.21	% SZS status Started for HL406709+4.p
124108.56/16784.21	% SZS status GaveUp for HL406709+4.p
124108.56/16784.21	eprover: CPU time limit exceeded, terminating
124108.56/16784.21	% SZS status Ended for HL406709+4.p
124114.58/16785.03	% SZS status Started for HL406711+4.p
124114.58/16785.03	% SZS status GaveUp for HL406711+4.p
124114.58/16785.03	eprover: CPU time limit exceeded, terminating
124114.58/16785.03	% SZS status Ended for HL406711+4.p
124128.42/16786.74	% SZS status Started for HL406712+4.p
124128.42/16786.74	% SZS status GaveUp for HL406712+4.p
124128.42/16786.74	eprover: CPU time limit exceeded, terminating
124128.42/16786.74	% SZS status Ended for HL406712+4.p
124135.04/16787.53	% SZS status Started for HL406708+5.p
124135.04/16787.53	% SZS status GaveUp for HL406708+5.p
124135.04/16787.53	% SZS status Ended for HL406708+5.p
124138.27/16788.04	% SZS status Started for HL406709+5.p
124138.27/16788.04	% SZS status GaveUp for HL406709+5.p
124138.27/16788.04	% SZS status Ended for HL406709+5.p
124138.91/16788.19	% SZS status Started for HL406713+4.p
124138.91/16788.19	% SZS status GaveUp for HL406713+4.p
124138.91/16788.19	eprover: CPU time limit exceeded, terminating
124138.91/16788.19	% SZS status Ended for HL406713+4.p
124142.05/16788.58	% SZS status Started for HL406711+5.p
124142.05/16788.58	% SZS status GaveUp for HL406711+5.p
124142.05/16788.58	% SZS status Ended for HL406711+5.p
124146.19/16789.11	% SZS status Started for HL406706+5.p
124146.19/16789.11	% SZS status GaveUp for HL406706+5.p
124146.19/16789.11	% SZS status Ended for HL406706+5.p
124150.49/16789.73	% SZS status Started for HL406707+5.p
124150.49/16789.73	% SZS status GaveUp for HL406707+5.p
124150.49/16789.73	% SZS status Ended for HL406707+5.p
124157.17/16790.59	% SZS status Started for HL406712+5.p
124157.17/16790.59	% SZS status GaveUp for HL406712+5.p
124157.17/16790.59	% SZS status Ended for HL406712+5.p
124157.17/16790.64	% SZS status Started for HL406714+4.p
124157.17/16790.64	% SZS status GaveUp for HL406714+4.p
124157.17/16790.64	eprover: CPU time limit exceeded, terminating
124157.17/16790.64	% SZS status Ended for HL406714+4.p
124163.79/16791.39	% SZS status Started for HL406715+4.p
124163.79/16791.39	% SZS status GaveUp for HL406715+4.p
124163.79/16791.39	eprover: CPU time limit exceeded, terminating
124163.79/16791.39	% SZS status Ended for HL406715+4.p
124170.19/16792.31	% SZS status Started for HL406716+4.p
124170.19/16792.31	% SZS status GaveUp for HL406716+4.p
124170.19/16792.31	eprover: CPU time limit exceeded, terminating
124170.19/16792.31	% SZS status Ended for HL406716+4.p
124177.90/16793.21	% SZS status Started for HL406713+5.p
124177.90/16793.21	% SZS status GaveUp for HL406713+5.p
124177.90/16793.21	% SZS status Ended for HL406713+5.p
124180.81/16793.70	% SZS status Started for HL406717+4.p
124180.81/16793.70	% SZS status GaveUp for HL406717+4.p
124180.81/16793.70	eprover: CPU time limit exceeded, terminating
124180.81/16793.70	% SZS status Ended for HL406717+4.p
124185.95/16794.42	% SZS status Started for HL406719+4.p
124185.95/16794.42	% SZS status GaveUp for HL406719+4.p
124185.95/16794.42	eprover: CPU time limit exceeded, terminating
124185.95/16794.42	% SZS status Ended for HL406719+4.p
124188.17/16794.44	% SZS status Started for HL406714+5.p
124188.17/16794.44	% SZS status GaveUp for HL406714+5.p
124188.17/16794.44	% SZS status Ended for HL406714+5.p
124201.94/16796.24	% SZS status Started for HL406720+4.p
124201.94/16796.24	% SZS status GaveUp for HL406720+4.p
124201.94/16796.24	eprover: CPU time limit exceeded, terminating
124201.94/16796.24	% SZS status Ended for HL406720+4.p
124201.94/16796.26	% SZS status Started for HL406716+5.p
124201.94/16796.26	% SZS status GaveUp for HL406716+5.p
124201.94/16796.26	% SZS status Ended for HL406716+5.p
124208.87/16797.10	% SZS status Started for HL406717+5.p
124208.87/16797.10	% SZS status GaveUp for HL406717+5.p
124208.87/16797.10	% SZS status Ended for HL406717+5.p
124211.36/16797.46	% SZS status Started for HL406721+4.p
124211.36/16797.46	% SZS status GaveUp for HL406721+4.p
124211.36/16797.46	eprover: CPU time limit exceeded, terminating
124211.36/16797.46	% SZS status Ended for HL406721+4.p
124221.27/16798.67	% SZS status Started for HL406719+5.p
124221.27/16798.67	% SZS status GaveUp for HL406719+5.p
124221.27/16798.67	% SZS status Ended for HL406719+5.p
124224.75/16799.15	% SZS status Started for HL406715+5.p
124224.75/16799.15	% SZS status GaveUp for HL406715+5.p
124224.75/16799.15	% SZS status Ended for HL406715+5.p
124225.59/16799.29	% SZS status Started for HL406722+4.p
124225.59/16799.29	% SZS status GaveUp for HL406722+4.p
124225.59/16799.29	eprover: CPU time limit exceeded, terminating
124225.59/16799.29	% SZS status Ended for HL406722+4.p
124232.05/16800.18	% SZS status Started for HL406720+5.p
124232.05/16800.18	% SZS status GaveUp for HL406720+5.p
124232.05/16800.18	% SZS status Ended for HL406720+5.p
124234.66/16800.40	% SZS status Started for HL406723+4.p
124234.66/16800.40	% SZS status GaveUp for HL406723+4.p
124234.66/16800.40	eprover: CPU time limit exceeded, terminating
124234.66/16800.40	% SZS status Ended for HL406723+4.p
124240.19/16801.05	% SZS status Started for HL406721+5.p
124240.19/16801.05	% SZS status GaveUp for HL406721+5.p
124240.19/16801.05	% SZS status Ended for HL406721+5.p
124244.76/16801.71	% SZS status Started for HL406724+4.p
124244.76/16801.71	% SZS status GaveUp for HL406724+4.p
124244.76/16801.71	eprover: CPU time limit exceeded, terminating
124244.76/16801.71	% SZS status Ended for HL406724+4.p
124249.57/16802.33	% SZS status Started for HL406725+4.p
124249.57/16802.33	% SZS status GaveUp for HL406725+4.p
124249.57/16802.33	eprover: CPU time limit exceeded, terminating
124249.57/16802.33	% SZS status Ended for HL406725+4.p
124258.00/16803.31	% SZS status Started for HL406723+5.p
124258.00/16803.31	% SZS status GaveUp for HL406723+5.p
124258.00/16803.31	% SZS status Ended for HL406723+5.p
124258.51/16803.46	% SZS status Started for HL406722+5.p
124258.51/16803.46	% SZS status GaveUp for HL406722+5.p
124258.51/16803.46	% SZS status Ended for HL406722+5.p
124258.87/16803.53	% SZS status Started for HL406726+4.p
124258.87/16803.53	% SZS status GaveUp for HL406726+4.p
124258.87/16803.53	eprover: CPU time limit exceeded, terminating
124258.87/16803.53	% SZS status Ended for HL406726+4.p
124269.56/16804.76	% SZS status Started for HL406727+4.p
124269.56/16804.76	% SZS status GaveUp for HL406727+4.p
124269.56/16804.76	eprover: CPU time limit exceeded, terminating
124269.56/16804.76	% SZS status Ended for HL406727+4.p
124271.94/16805.23	% SZS status Started for HL406724+5.p
124271.94/16805.23	% SZS status GaveUp for HL406724+5.p
124271.94/16805.23	% SZS status Ended for HL406724+5.p
124279.31/16806.02	% SZS status Started for HL406725+5.p
124279.31/16806.02	% SZS status GaveUp for HL406725+5.p
124279.31/16806.02	% SZS status Ended for HL406725+5.p
124281.06/16806.35	% SZS status Started for HL406728+4.p
124281.06/16806.35	% SZS status GaveUp for HL406728+4.p
124281.06/16806.35	eprover: CPU time limit exceeded, terminating
124281.06/16806.35	% SZS status Ended for HL406728+4.p
124283.45/16806.57	% SZS status Started for HL406729+4.p
124283.45/16806.57	% SZS status GaveUp for HL406729+4.p
124283.45/16806.57	eprover: CPU time limit exceeded, terminating
124283.45/16806.57	% SZS status Ended for HL406729+4.p
124285.23/16806.89	% SZS status Started for HL406726+5.p
124285.23/16806.89	% SZS status GaveUp for HL406726+5.p
124285.23/16806.89	% SZS status Ended for HL406726+5.p
124296.86/16808.27	% SZS status Started for HL406730+4.p
124296.86/16808.27	% SZS status GaveUp for HL406730+4.p
124296.86/16808.27	eprover: CPU time limit exceeded, terminating
124296.86/16808.27	% SZS status Ended for HL406730+4.p
124302.48/16809.05	% SZS status Started for HL406727+5.p
124302.48/16809.05	% SZS status GaveUp for HL406727+5.p
124302.48/16809.05	% SZS status Ended for HL406727+5.p
124306.56/16809.49	% SZS status Started for HL406731+4.p
124306.56/16809.49	% SZS status GaveUp for HL406731+4.p
124306.56/16809.49	eprover: CPU time limit exceeded, terminating
124306.56/16809.49	% SZS status Ended for HL406731+4.p
124308.47/16809.92	% SZS status Started for HL406732+4.p
124308.47/16809.92	% SZS status GaveUp for HL406732+4.p
124308.47/16809.92	eprover: CPU time limit exceeded, terminating
124308.47/16809.92	% SZS status Ended for HL406732+4.p
124323.66/16811.85	% SZS status Started for HL406729+5.p
124323.66/16811.85	% SZS status GaveUp for HL406729+5.p
124323.66/16811.85	% SZS status Ended for HL406729+5.p
124324.83/16811.90	% SZS status Started for HL406728+5.p
124324.83/16811.90	% SZS status GaveUp for HL406728+5.p
124324.83/16811.90	% SZS status Ended for HL406728+5.p
124325.67/16812.04	% SZS status Started for HL406730+5.p
124325.67/16812.04	% SZS status GaveUp for HL406730+5.p
124325.67/16812.04	% SZS status Ended for HL406730+5.p
124325.98/16812.08	% SZS status Started for HL406733+4.p
124325.98/16812.08	% SZS status GaveUp for HL406733+4.p
124325.98/16812.08	eprover: CPU time limit exceeded, terminating
124325.98/16812.08	% SZS status Ended for HL406733+4.p
124332.75/16813.00	% SZS status Started for HL406734+4.p
124332.75/16813.00	% SZS status GaveUp for HL406734+4.p
124332.75/16813.00	eprover: CPU time limit exceeded, terminating
124332.75/16813.00	% SZS status Ended for HL406734+4.p
124344.27/16814.49	% SZS status Started for HL406731+5.p
124344.27/16814.49	% SZS status GaveUp for HL406731+5.p
124344.27/16814.49	% SZS status Ended for HL406731+5.p
124349.06/16815.11	% SZS status Started for HL406736+4.p
124349.06/16815.11	% SZS status GaveUp for HL406736+4.p
124349.06/16815.11	eprover: CPU time limit exceeded, terminating
124349.06/16815.11	% SZS status Ended for HL406736+4.p
124349.26/16815.20	% SZS status Started for HL406735+4.p
124349.26/16815.20	% SZS status GaveUp for HL406735+4.p
124349.26/16815.20	eprover: CPU time limit exceeded, terminating
124349.26/16815.20	% SZS status Ended for HL406735+4.p
124352.37/16815.48	% SZS status Started for HL406732+5.p
124352.37/16815.48	% SZS status GaveUp for HL406732+5.p
124352.37/16815.48	% SZS status Ended for HL406732+5.p
124366.88/16817.53	% SZS status Started for HL406737+4.p
124366.88/16817.53	% SZS status GaveUp for HL406737+4.p
124366.88/16817.53	eprover: CPU time limit exceeded, terminating
124366.88/16817.53	% SZS status Ended for HL406737+4.p
124371.81/16818.18	% SZS status Started for HL406734+5.p
124371.81/16818.18	% SZS status GaveUp for HL406734+5.p
124371.81/16818.18	% SZS status Ended for HL406734+5.p
124372.77/16818.30	% SZS status Started for HL406738+4.p
124372.77/16818.30	% SZS status GaveUp for HL406738+4.p
124372.77/16818.30	eprover: CPU time limit exceeded, terminating
124372.77/16818.30	% SZS status Ended for HL406738+4.p
124378.28/16818.83	% SZS status Started for HL406733+5.p
124378.28/16818.83	% SZS status GaveUp for HL406733+5.p
124378.28/16818.83	% SZS status Ended for HL406733+5.p
124387.84/16820.06	% SZS status Started for HL406736+5.p
124387.84/16820.06	% SZS status GaveUp for HL406736+5.p
124387.84/16820.06	% SZS status Ended for HL406736+5.p
124390.91/16820.35	% SZS status Started for HL406738+5.p
124390.91/16820.35	% SZS status GaveUp for HL406738+5.p
124390.91/16820.35	% SZS status Ended for HL406738+5.p
124392.23/16820.61	% SZS status Started for HL406735+5.p
124392.23/16820.61	% SZS status GaveUp for HL406735+5.p
124392.23/16820.61	% SZS status Ended for HL406735+5.p
124392.23/16820.63	% SZS status Started for HL406739+4.p
124392.23/16820.63	% SZS status GaveUp for HL406739+4.p
124392.23/16820.63	eprover: CPU time limit exceeded, terminating
124392.23/16820.63	% SZS status Ended for HL406739+4.p
124394.64/16820.85	% SZS status Started for HL406737+5.p
124394.64/16820.85	% SZS status GaveUp for HL406737+5.p
124394.64/16820.85	% SZS status Ended for HL406737+5.p
124397.78/16821.34	% SZS status Started for HL406740+4.p
124397.78/16821.34	% SZS status GaveUp for HL406740+4.p
124397.78/16821.34	eprover: CPU time limit exceeded, terminating
124397.78/16821.34	% SZS status Ended for HL406740+4.p
124413.35/16823.05	% SZS status Started for HL406739+5.p
124413.35/16823.05	% SZS status GaveUp for HL406739+5.p
124413.35/16823.05	% SZS status Ended for HL406739+5.p
124418.37/16823.10	% SZS status Started for HL406742+4.p
124418.37/16823.10	% SZS status GaveUp for HL406742+4.p
124418.37/16823.10	eprover: CPU time limit exceeded, terminating
124418.37/16823.10	% SZS status Ended for HL406742+4.p
124422.73/16823.65	% SZS status Started for HL406743+4.p
124422.73/16823.65	% SZS status GaveUp for HL406743+4.p
124422.73/16823.65	eprover: CPU time limit exceeded, terminating
124422.73/16823.65	% SZS status Ended for HL406743+4.p
124423.74/16823.92	% SZS status Started for HL406744+4.p
124423.74/16823.92	% SZS status GaveUp for HL406744+4.p
124423.74/16823.92	eprover: CPU time limit exceeded, terminating
124423.74/16823.92	% SZS status Ended for HL406744+4.p
124424.77/16824.12	% SZS status Started for HL406740+5.p
124424.77/16824.12	% SZS status GaveUp for HL406740+5.p
124424.77/16824.12	% SZS status Ended for HL406740+5.p
124440.49/16825.52	% SZS status Started for HL406742+5.p
124440.49/16825.52	% SZS status GaveUp for HL406742+5.p
124440.49/16825.52	% SZS status Ended for HL406742+5.p
124445.95/16826.19	% SZS status Started for HL406745+4.p
124445.95/16826.19	% SZS status GaveUp for HL406745+4.p
124445.95/16826.19	eprover: CPU time limit exceeded, terminating
124445.95/16826.19	% SZS status Ended for HL406745+4.p
124449.88/16826.68	% SZS status Started for HL406746+4.p
124449.88/16826.68	% SZS status GaveUp for HL406746+4.p
124449.88/16826.68	eprover: CPU time limit exceeded, terminating
124449.88/16826.68	% SZS status Ended for HL406746+4.p
124454.02/16827.16	% SZS status Started for HL406747+4.p
124454.02/16827.16	% SZS status GaveUp for HL406747+4.p
124454.02/16827.16	eprover: CPU time limit exceeded, terminating
124454.02/16827.16	% SZS status Ended for HL406747+4.p
124459.26/16827.92	% SZS status Started for HL406745+5.p
124459.26/16827.92	% SZS status GaveUp for HL406745+5.p
124459.26/16827.92	% SZS status Ended for HL406745+5.p
124465.81/16828.71	% SZS status Started for HL406744+5.p
124465.81/16828.71	% SZS status GaveUp for HL406744+5.p
124465.81/16828.71	% SZS status Ended for HL406744+5.p
124467.29/16828.85	% SZS status Started for HL406746+5.p
124467.29/16828.85	% SZS status GaveUp for HL406746+5.p
124467.29/16828.85	% SZS status Ended for HL406746+5.p
124470.41/16829.26	% SZS status Started for HL406748+4.p
124470.41/16829.26	% SZS status GaveUp for HL406748+4.p
124470.41/16829.26	eprover: CPU time limit exceeded, terminating
124470.41/16829.26	% SZS status Ended for HL406748+4.p
124472.76/16829.64	% SZS status Started for HL406743+5.p
124472.76/16829.64	% SZS status GaveUp for HL406743+5.p
124472.76/16829.64	% SZS status Ended for HL406743+5.p
124478.47/16830.29	% SZS status Started for HL406749+4.p
124478.47/16830.29	% SZS status GaveUp for HL406749+4.p
124478.47/16830.29	eprover: CPU time limit exceeded, terminating
124478.47/16830.29	% SZS status Ended for HL406749+4.p
124487.84/16831.74	% SZS status Started for HL406751+4.p
124487.84/16831.74	% SZS status GaveUp for HL406751+4.p
124487.84/16831.74	eprover: CPU time limit exceeded, terminating
124487.84/16831.74	% SZS status Ended for HL406751+4.p
124495.61/16832.36	% SZS status Started for HL406752+4.p
124495.61/16832.36	% SZS status GaveUp for HL406752+4.p
124495.61/16832.36	eprover: CPU time limit exceeded, terminating
124495.61/16832.36	% SZS status Ended for HL406752+4.p
124496.89/16832.55	% SZS status Started for HL406747+5.p
124496.89/16832.55	% SZS status GaveUp for HL406747+5.p
124496.89/16832.55	% SZS status Ended for HL406747+5.p
124502.30/16833.33	% SZS status Started for HL406753+4.p
124502.30/16833.33	% SZS status GaveUp for HL406753+4.p
124502.30/16833.33	eprover: CPU time limit exceeded, terminating
124502.30/16833.33	% SZS status Ended for HL406753+4.p
124506.02/16833.69	% SZS status Started for HL406748+5.p
124506.02/16833.69	% SZS status GaveUp for HL406748+5.p
124506.02/16833.69	% SZS status Ended for HL406748+5.p
124515.97/16835.00	% SZS status Started for HL406749+5.p
124515.97/16835.00	% SZS status GaveUp for HL406749+5.p
124515.97/16835.00	% SZS status Ended for HL406749+5.p
124519.28/16835.45	% SZS status Started for HL406754+4.p
124519.28/16835.45	% SZS status GaveUp for HL406754+4.p
124519.28/16835.45	eprover: CPU time limit exceeded, terminating
124519.28/16835.45	% SZS status Ended for HL406754+4.p
124527.22/16836.37	% SZS status Started for HL406755+4.p
124527.22/16836.37	% SZS status GaveUp for HL406755+4.p
124527.22/16836.37	eprover: CPU time limit exceeded, terminating
124527.22/16836.37	% SZS status Ended for HL406755+4.p
124528.04/16836.52	% SZS status Started for HL406751+5.p
124528.04/16836.52	% SZS status GaveUp for HL406751+5.p
124528.04/16836.52	% SZS status Ended for HL406751+5.p
124530.78/16836.82	% SZS status Started for HL406752+5.p
124530.78/16836.82	% SZS status GaveUp for HL406752+5.p
124530.78/16836.82	% SZS status Ended for HL406752+5.p
124540.55/16838.03	% SZS status Started for HL406756+4.p
124540.55/16838.03	% SZS status GaveUp for HL406756+4.p
124540.55/16838.03	eprover: CPU time limit exceeded, terminating
124540.55/16838.03	% SZS status Ended for HL406756+4.p
124545.13/16838.67	% SZS status Started for HL406753+5.p
124545.13/16838.67	% SZS status GaveUp for HL406753+5.p
124545.13/16838.67	% SZS status Ended for HL406753+5.p
124551.42/16839.54	% SZS status Started for HL406757+4.p
124551.42/16839.54	% SZS status GaveUp for HL406757+4.p
124551.42/16839.54	eprover: CPU time limit exceeded, terminating
124551.42/16839.54	% SZS status Ended for HL406757+4.p
124554.80/16839.86	% SZS status Started for HL406758+4.p
124554.80/16839.86	% SZS status GaveUp for HL406758+4.p
124554.80/16839.86	eprover: CPU time limit exceeded, terminating
124554.80/16839.86	% SZS status Ended for HL406758+4.p
124555.04/16839.90	% SZS status Started for HL406754+5.p
124555.04/16839.90	% SZS status GaveUp for HL406754+5.p
124555.04/16839.90	% SZS status Ended for HL406754+5.p
124565.41/16841.30	% SZS status Started for HL406755+5.p
124565.41/16841.30	% SZS status GaveUp for HL406755+5.p
124565.41/16841.30	% SZS status Ended for HL406755+5.p
124569.37/16841.72	% SZS status Started for HL406759+4.p
124569.37/16841.72	% SZS status GaveUp for HL406759+4.p
124569.37/16841.72	eprover: CPU time limit exceeded, terminating
124569.37/16841.72	% SZS status Ended for HL406759+4.p
124578.29/16842.95	% SZS status Started for HL406760+4.p
124578.29/16842.95	% SZS status GaveUp for HL406760+4.p
124578.29/16842.95	eprover: CPU time limit exceeded, terminating
124578.29/16842.95	% SZS status Ended for HL406760+4.p
124582.90/16843.43	% SZS status Started for HL406756+5.p
124582.90/16843.43	% SZS status GaveUp for HL406756+5.p
124582.90/16843.43	% SZS status Ended for HL406756+5.p
124589.98/16844.33	% SZS status Started for HL406762+4.p
124589.98/16844.33	% SZS status GaveUp for HL406762+4.p
124589.98/16844.33	eprover: CPU time limit exceeded, terminating
124589.98/16844.33	% SZS status Ended for HL406762+4.p
124597.14/16845.50	% SZS status Started for HL406758+5.p
124597.14/16845.50	% SZS status GaveUp for HL406758+5.p
124597.14/16845.50	% SZS status Ended for HL406758+5.p
124602.46/16845.98	% SZS status Started for HL406763+4.p
124602.46/16845.98	% SZS status GaveUp for HL406763+4.p
124602.46/16845.98	eprover: CPU time limit exceeded, terminating
124602.46/16845.98	% SZS status Ended for HL406763+4.p
124611.89/16847.07	% SZS status Started for HL406757+5.p
124611.89/16847.07	% SZS status GaveUp for HL406757+5.p
124611.89/16847.07	eprover: CPU time limit exceeded, terminating
124611.89/16847.07	% SZS status Ended for HL406757+5.p
124612.40/16847.13	% SZS status Started for HL406760+5.p
124612.40/16847.13	% SZS status GaveUp for HL406760+5.p
124612.40/16847.13	% SZS status Ended for HL406760+5.p
124612.69/16847.20	% SZS status Started for HL406759+5.p
124612.69/16847.20	% SZS status GaveUp for HL406759+5.p
124612.69/16847.20	% SZS status Ended for HL406759+5.p
124614.61/16847.38	% SZS status Started for HL406764+4.p
124614.61/16847.38	% SZS status GaveUp for HL406764+4.p
124614.61/16847.38	eprover: CPU time limit exceeded, terminating
124614.61/16847.38	% SZS status Ended for HL406764+4.p
124628.16/16849.40	% SZS status Started for HL406766+4.p
124628.16/16849.40	% SZS status GaveUp for HL406766+4.p
124628.16/16849.40	eprover: CPU time limit exceeded, terminating
124628.16/16849.40	% SZS status Ended for HL406766+4.p
124635.11/16850.17	% SZS status Started for HL406767+4.p
124635.11/16850.17	% SZS status GaveUp for HL406767+4.p
124635.11/16850.17	eprover: CPU time limit exceeded, terminating
124635.11/16850.17	% SZS status Ended for HL406767+4.p
124637.72/16850.61	% SZS status Started for HL406762+5.p
124637.72/16850.61	% SZS status GaveUp for HL406762+5.p
124637.72/16850.61	% SZS status Ended for HL406762+5.p
124640.06/16850.83	% SZS status Started for HL406768+4.p
124640.06/16850.83	% SZS status GaveUp for HL406768+4.p
124640.06/16850.83	eprover: CPU time limit exceeded, terminating
124640.06/16850.83	% SZS status Ended for HL406768+4.p
124640.66/16850.94	% SZS status Started for HL406763+5.p
124640.66/16850.94	% SZS status GaveUp for HL406763+5.p
124640.66/16850.94	% SZS status Ended for HL406763+5.p
124654.65/16852.67	% SZS status Started for HL406764+5.p
124654.65/16852.67	% SZS status GaveUp for HL406764+5.p
124654.65/16852.67	% SZS status Ended for HL406764+5.p
124659.14/16853.19	% SZS status Started for HL406769+4.p
124659.14/16853.19	% SZS status GaveUp for HL406769+4.p
124659.14/16853.19	eprover: CPU time limit exceeded, terminating
124659.14/16853.19	% SZS status Ended for HL406769+4.p
124664.24/16853.87	% SZS status Started for HL406771+4.p
124664.24/16853.87	% SZS status GaveUp for HL406771+4.p
124664.24/16853.87	eprover: CPU time limit exceeded, terminating
124664.24/16853.87	% SZS status Ended for HL406771+4.p
124667.80/16854.33	% SZS status Started for HL406767+5.p
124667.80/16854.33	% SZS status GaveUp for HL406767+5.p
124667.80/16854.33	% SZS status Ended for HL406767+5.p
124671.74/16854.75	% SZS status Started for HL406766+5.p
124671.74/16854.75	% SZS status GaveUp for HL406766+5.p
124671.74/16854.75	% SZS status Ended for HL406766+5.p
124680.53/16855.98	% SZS status Started for HL406772+4.p
124680.53/16855.98	% SZS status GaveUp for HL406772+4.p
124680.53/16855.98	eprover: CPU time limit exceeded, terminating
124680.53/16855.98	% SZS status Ended for HL406772+4.p
124685.27/16856.58	% SZS status Started for HL406768+5.p
124685.27/16856.58	% SZS status GaveUp for HL406768+5.p
124685.27/16856.58	% SZS status Ended for HL406768+5.p
124687.80/16856.90	% SZS status Started for HL406773+4.p
124687.80/16856.90	% SZS status GaveUp for HL406773+4.p
124687.80/16856.90	eprover: CPU time limit exceeded, terminating
124687.80/16856.90	% SZS status Ended for HL406773+4.p
124690.32/16857.34	% SZS status Started for HL406769+5.p
124690.32/16857.34	% SZS status GaveUp for HL406769+5.p
124690.32/16857.34	% SZS status Ended for HL406769+5.p
124695.32/16857.88	% SZS status Started for HL406771+5.p
124695.32/16857.88	% SZS status GaveUp for HL406771+5.p
124695.32/16857.88	% SZS status Ended for HL406771+5.p
124695.32/16857.90	% SZS status Started for HL406774+4.p
124695.32/16857.90	% SZS status GaveUp for HL406774+4.p
124695.32/16857.90	eprover: CPU time limit exceeded, terminating
124695.32/16857.90	% SZS status Ended for HL406774+4.p
124708.43/16859.61	% SZS status Started for HL406775+4.p
124708.43/16859.61	% SZS status GaveUp for HL406775+4.p
124708.43/16859.61	eprover: CPU time limit exceeded, terminating
124708.43/16859.61	% SZS status Ended for HL406775+4.p
124712.73/16860.15	% SZS status Started for HL406772+5.p
124712.73/16860.15	% SZS status GaveUp for HL406772+5.p
124712.73/16860.15	% SZS status Ended for HL406772+5.p
124716.90/16860.85	% SZS status Started for HL406776+4.p
124716.90/16860.85	% SZS status GaveUp for HL406776+4.p
124716.90/16860.85	eprover: CPU time limit exceeded, terminating
124716.90/16860.85	% SZS status Ended for HL406776+4.p
124718.76/16860.98	% SZS status Started for HL406777+4.p
124718.76/16860.98	% SZS status GaveUp for HL406777+4.p
124718.76/16860.98	eprover: CPU time limit exceeded, terminating
124718.76/16860.98	% SZS status Ended for HL406777+4.p
124719.22/16861.06	% SZS status Started for HL406773+5.p
124719.22/16861.06	% SZS status GaveUp for HL406773+5.p
124719.22/16861.06	% SZS status Ended for HL406773+5.p
124737.59/16863.37	% SZS status Started for HL406779+4.p
124737.59/16863.37	% SZS status GaveUp for HL406779+4.p
124737.59/16863.37	eprover: CPU time limit exceeded, terminating
124737.59/16863.37	% SZS status Ended for HL406779+4.p
124739.77/16863.81	% SZS status Started for HL406774+5.p
124739.77/16863.81	% SZS status GaveUp for HL406774+5.p
124739.77/16863.81	% SZS status Ended for HL406774+5.p
124743.02/16864.13	% SZS status Started for HL406781+4.p
124743.02/16864.13	% SZS status GaveUp for HL406781+4.p
124743.02/16864.13	eprover: CPU time limit exceeded, terminating
124743.02/16864.13	% SZS status Ended for HL406781+4.p
124752.38/16865.31	% SZS status Started for HL406775+5.p
124752.38/16865.31	% SZS status GaveUp for HL406775+5.p
124752.38/16865.31	% SZS status Ended for HL406775+5.p
124759.84/16866.24	% SZS status Started for HL406777+5.p
124759.84/16866.24	% SZS status GaveUp for HL406777+5.p
124759.84/16866.24	% SZS status Ended for HL406777+5.p
124759.84/16866.28	% SZS status Started for HL406776+5.p
124759.84/16866.28	% SZS status GaveUp for HL406776+5.p
124759.84/16866.28	% SZS status Ended for HL406776+5.p
124761.16/16866.40	% SZS status Started for HL406782+4.p
124761.16/16866.40	% SZS status GaveUp for HL406782+4.p
124761.16/16866.40	eprover: CPU time limit exceeded, terminating
124761.16/16866.40	% SZS status Ended for HL406782+4.p
124764.12/16866.89	% SZS status Started for HL406779+5.p
124764.12/16866.89	% SZS status GaveUp for HL406779+5.p
124764.12/16866.89	% SZS status Ended for HL406779+5.p
124767.59/16867.17	% SZS status Started for HL406783+4.p
124767.59/16867.17	% SZS status GaveUp for HL406783+4.p
124767.59/16867.17	eprover: CPU time limit exceeded, terminating
124767.59/16867.17	% SZS status Ended for HL406783+4.p
124772.49/16867.78	% SZS status Started for HL406781+5.p
124772.49/16867.78	% SZS status GaveUp for HL406781+5.p
124772.49/16867.78	% SZS status Ended for HL406781+5.p
124784.59/16869.32	% SZS status Started for HL406784+4.p
124784.59/16869.32	% SZS status GaveUp for HL406784+4.p
124784.59/16869.32	eprover: CPU time limit exceeded, terminating
124784.59/16869.32	% SZS status Ended for HL406784+4.p
124785.21/16869.44	% SZS status Started for HL406785+4.p
124785.21/16869.44	% SZS status GaveUp for HL406785+4.p
124785.21/16869.44	eprover: CPU time limit exceeded, terminating
124785.21/16869.44	% SZS status Ended for HL406785+4.p
124790.86/16870.24	% SZS status Started for HL406786+4.p
124790.86/16870.24	% SZS status GaveUp for HL406786+4.p
124790.86/16870.24	eprover: CPU time limit exceeded, terminating
124790.86/16870.24	% SZS status Ended for HL406786+4.p
124795.29/16870.73	% SZS status Started for HL406782+5.p
124795.29/16870.73	% SZS status GaveUp for HL406782+5.p
124795.29/16870.73	% SZS status Ended for HL406782+5.p
124808.02/16872.37	% SZS status Started for HL406787+4.p
124808.02/16872.37	% SZS status GaveUp for HL406787+4.p
124808.02/16872.37	eprover: CPU time limit exceeded, terminating
124808.02/16872.37	% SZS status Ended for HL406787+4.p
124813.66/16873.27	% SZS status Started for HL406788+4.p
124813.66/16873.27	% SZS status GaveUp for HL406788+4.p
124813.66/16873.27	eprover: CPU time limit exceeded, terminating
124813.66/16873.27	% SZS status Ended for HL406788+4.p
124823.28/16874.30	% SZS status Started for HL406784+5.p
124823.28/16874.30	% SZS status GaveUp for HL406784+5.p
124823.28/16874.30	% SZS status Ended for HL406784+5.p
124828.40/16874.99	% SZS status Started for HL406783+5.p
124828.40/16874.99	% SZS status GaveUp for HL406783+5.p
124828.40/16874.99	% SZS status Ended for HL406783+5.p
124829.01/16875.09	% SZS status Started for HL406785+5.p
124829.01/16875.09	% SZS status GaveUp for HL406785+5.p
124829.01/16875.09	% SZS status Ended for HL406785+5.p
124831.71/16875.43	% SZS status Started for HL406790+4.p
124831.71/16875.43	% SZS status GaveUp for HL406790+4.p
124831.71/16875.43	eprover: CPU time limit exceeded, terminating
124831.71/16875.43	% SZS status Ended for HL406790+4.p
124846.50/16877.33	% SZS status Started for HL406791+4.p
124846.50/16877.33	% SZS status GaveUp for HL406791+4.p
124846.50/16877.33	eprover: CPU time limit exceeded, terminating
124846.50/16877.33	% SZS status Ended for HL406791+4.p
124850.09/16877.74	% SZS status Started for HL406787+5.p
124850.09/16877.74	% SZS status GaveUp for HL406787+5.p
124850.09/16877.74	% SZS status Ended for HL406787+5.p
124853.68/16878.12	% SZS status Started for HL406792+4.p
124853.68/16878.12	% SZS status GaveUp for HL406792+4.p
124853.68/16878.12	eprover: CPU time limit exceeded, terminating
124853.68/16878.12	% SZS status Ended for HL406792+4.p
124854.59/16878.24	% SZS status Started for HL406788+5.p
124854.59/16878.24	% SZS status GaveUp for HL406788+5.p
124854.59/16878.24	% SZS status Ended for HL406788+5.p
124855.07/16878.35	% SZS status Started for HL406786+5.p
124855.07/16878.35	% SZS status GaveUp for HL406786+5.p
124855.07/16878.35	% SZS status Ended for HL406786+5.p
124871.79/16880.47	% SZS status Started for HL406794+4.p
124871.79/16880.47	% SZS status GaveUp for HL406794+4.p
124871.79/16880.47	eprover: CPU time limit exceeded, terminating
124871.79/16880.47	% SZS status Ended for HL406794+4.p
124877.34/16881.16	% SZS status Started for HL406795+4.p
124877.34/16881.16	% SZS status GaveUp for HL406795+4.p
124877.34/16881.16	eprover: CPU time limit exceeded, terminating
124877.34/16881.16	% SZS status Ended for HL406795+4.p
124879.16/16881.42	% SZS status Started for HL406796+4.p
124879.16/16881.42	% SZS status GaveUp for HL406796+4.p
124879.16/16881.42	eprover: CPU time limit exceeded, terminating
124879.16/16881.42	% SZS status Ended for HL406796+4.p
124887.57/16882.51	% SZS status Started for HL406794+5.p
124887.57/16882.51	% SZS status GaveUp for HL406794+5.p
124887.57/16882.51	% SZS status Ended for HL406794+5.p
124890.38/16882.76	% SZS status Started for HL406790+5.p
124890.38/16882.76	% SZS status GaveUp for HL406790+5.p
124890.38/16882.76	% SZS status Ended for HL406790+5.p
124892.45/16883.17	% SZS status Started for HL406795+5.p
124892.45/16883.17	% SZS status GaveUp for HL406795+5.p
124892.45/16883.17	% SZS status Ended for HL406795+5.p
124901.07/16884.19	% SZS status Started for HL406798+4.p
124901.07/16884.19	% SZS status GaveUp for HL406798+4.p
124901.07/16884.19	eprover: CPU time limit exceeded, terminating
124901.07/16884.19	% SZS status Ended for HL406798+4.p
124905.75/16884.77	% SZS status Started for HL406791+5.p
124905.75/16884.77	% SZS status GaveUp for HL406791+5.p
124905.75/16884.77	% SZS status Ended for HL406791+5.p
124909.27/16885.17	% SZS status Started for HL406796+5.p
124909.27/16885.17	% SZS status GaveUp for HL406796+5.p
124909.27/16885.17	% SZS status Ended for HL406796+5.p
124911.46/16885.52	% SZS status Started for HL406792+5.p
124911.46/16885.52	% SZS status GaveUp for HL406792+5.p
124911.46/16885.52	% SZS status Ended for HL406792+5.p
124913.23/16885.65	% SZS status Started for HL406799+4.p
124913.23/16885.65	% SZS status GaveUp for HL406799+4.p
124913.23/16885.65	eprover: CPU time limit exceeded, terminating
124913.23/16885.65	% SZS status Ended for HL406799+4.p
124917.45/16886.20	% SZS status Started for HL406800+4.p
124917.45/16886.20	% SZS status GaveUp for HL406800+4.p
124917.45/16886.20	eprover: CPU time limit exceeded, terminating
124917.45/16886.20	% SZS status Ended for HL406800+4.p
124917.97/16886.28	% SZS status Started for HL406798+5.p
124917.97/16886.28	% SZS status GaveUp for HL406798+5.p
124917.97/16886.28	% SZS status Ended for HL406798+5.p
124929.48/16887.80	% SZS status Started for HL406801+4.p
124929.48/16887.80	% SZS status GaveUp for HL406801+4.p
124929.48/16887.80	eprover: CPU time limit exceeded, terminating
124929.48/16887.80	% SZS status Ended for HL406801+4.p
124932.12/16888.22	% SZS status Started for HL406799+5.p
124932.12/16888.22	% SZS status GaveUp for HL406799+5.p
124932.12/16888.22	% SZS status Ended for HL406799+5.p
124936.10/16888.57	% SZS status Started for HL406802+4.p
124936.10/16888.57	% SZS status GaveUp for HL406802+4.p
124936.10/16888.57	eprover: CPU time limit exceeded, terminating
124936.10/16888.57	% SZS status Ended for HL406802+4.p
124940.10/16889.13	% SZS status Started for HL406800+5.p
124940.10/16889.13	% SZS status GaveUp for HL406800+5.p
124940.10/16889.13	% SZS status Ended for HL406800+5.p
124941.30/16889.27	% SZS status Started for HL406803+4.p
124941.30/16889.27	% SZS status GaveUp for HL406803+4.p
124941.30/16889.27	eprover: CPU time limit exceeded, terminating
124941.30/16889.27	% SZS status Ended for HL406803+4.p
124954.02/16890.83	% SZS status Started for HL406804+4.p
124954.02/16890.83	% SZS status GaveUp for HL406804+4.p
124954.02/16890.83	eprover: CPU time limit exceeded, terminating
124954.02/16890.83	% SZS status Ended for HL406804+4.p
124957.58/16891.30	% SZS status Started for HL406802+5.p
124957.58/16891.30	% SZS status GaveUp for HL406802+5.p
124957.58/16891.30	% SZS status Ended for HL406802+5.p
124958.09/16891.38	% SZS status Started for HL406803+5.p
124958.09/16891.38	% SZS status GaveUp for HL406803+5.p
124958.09/16891.38	% SZS status Ended for HL406803+5.p
124959.35/16891.60	% SZS status Started for HL406805+4.p
124959.35/16891.60	% SZS status GaveUp for HL406805+4.p
124959.35/16891.60	eprover: CPU time limit exceeded, terminating
124959.35/16891.60	% SZS status Ended for HL406805+4.p
124962.10/16891.83	% SZS status Started for HL406801+5.p
124962.10/16891.83	% SZS status GaveUp for HL406801+5.p
124962.10/16891.83	% SZS status Ended for HL406801+5.p
124966.27/16892.41	% SZS status Started for HL406806+4.p
124966.27/16892.41	% SZS status GaveUp for HL406806+4.p
124966.27/16892.41	eprover: CPU time limit exceeded, terminating
124966.27/16892.41	% SZS status Ended for HL406806+4.p
124975.71/16893.56	% SZS status Started for HL406804+5.p
124975.71/16893.56	% SZS status GaveUp for HL406804+5.p
124975.71/16893.56	% SZS status Ended for HL406804+5.p
125022.98/16899.50	% SZS status Started for HL406805+5.p
125022.98/16899.50	% SZS status GaveUp for HL406805+5.p
125022.98/16899.50	% SZS status Ended for HL406805+5.p
125029.84/16900.43	% SZS status Started for HL406806+5.p
125029.84/16900.43	% SZS status GaveUp for HL406806+5.p
125029.84/16900.43	% SZS status Ended for HL406806+5.p
125034.30/16900.94	% SZS status Started for HL406807+5.p
125034.30/16900.94	% SZS status GaveUp for HL406807+5.p
125034.30/16900.94	% SZS status Ended for HL406807+5.p
125037.86/16901.42	% SZS status Started for HL406808+5.p
125037.86/16901.42	% SZS status GaveUp for HL406808+5.p
125037.86/16901.42	% SZS status Ended for HL406808+5.p
125042.25/16901.96	% SZS status Started for HL406807+4.p
125042.25/16901.96	% SZS status GaveUp for HL406807+4.p
125042.25/16901.96	eprover: CPU time limit exceeded, terminating
125042.25/16901.96	% SZS status Ended for HL406807+4.p
125045.78/16902.35	% SZS status Started for HL406808+4.p
125045.78/16902.35	% SZS status GaveUp for HL406808+4.p
125045.78/16902.35	eprover: CPU time limit exceeded, terminating
125045.78/16902.35	% SZS status Ended for HL406808+4.p
125051.91/16903.18	% SZS status Started for HL406809+4.p
125051.91/16903.18	% SZS status GaveUp for HL406809+4.p
125051.91/16903.18	eprover: CPU time limit exceeded, terminating
125051.91/16903.18	% SZS status Ended for HL406809+4.p
125052.08/16903.20	% SZS status Started for HL406809+5.p
125052.08/16903.20	% SZS status GaveUp for HL406809+5.p
125052.08/16903.20	% SZS status Ended for HL406809+5.p
125106.45/16910.05	% SZS status Started for HL406811+5.p
125106.45/16910.05	% SZS status GaveUp for HL406811+5.p
125106.45/16910.05	% SZS status Ended for HL406811+5.p
125107.45/16910.20	% SZS status Started for HL406811+4.p
125107.45/16910.20	% SZS status GaveUp for HL406811+4.p
125107.45/16910.20	eprover: CPU time limit exceeded, terminating
125107.45/16910.20	% SZS status Ended for HL406811+4.p
125114.77/16911.12	% SZS status Started for HL406812+5.p
125114.77/16911.12	% SZS status GaveUp for HL406812+5.p
125114.77/16911.12	% SZS status Ended for HL406812+5.p
125120.33/16911.79	% SZS status Started for HL406812+4.p
125120.33/16911.79	% SZS status GaveUp for HL406812+4.p
125120.33/16911.79	eprover: CPU time limit exceeded, terminating
125120.33/16911.79	% SZS status Ended for HL406812+4.p
125124.95/16912.31	% SZS status Started for HL406813+5.p
125124.95/16912.31	% SZS status GaveUp for HL406813+5.p
125124.95/16912.31	% SZS status Ended for HL406813+5.p
125128.34/16912.74	% SZS status Started for HL406813+4.p
125128.34/16912.74	% SZS status GaveUp for HL406813+4.p
125128.34/16912.74	eprover: CPU time limit exceeded, terminating
125128.34/16912.74	% SZS status Ended for HL406813+4.p
125129.16/16912.95	% SZS status Started for HL406814+5.p
125129.16/16912.95	% SZS status GaveUp for HL406814+5.p
125129.16/16912.95	% SZS status Ended for HL406814+5.p
125140.60/16914.34	% SZS status Started for HL406814+4.p
125140.60/16914.34	% SZS status GaveUp for HL406814+4.p
125140.60/16914.34	eprover: CPU time limit exceeded, terminating
125140.60/16914.34	% SZS status Ended for HL406814+4.p
125186.69/16920.09	% SZS status Started for HL406815+5.p
125186.69/16920.09	% SZS status GaveUp for HL406815+5.p
125186.69/16920.09	% SZS status Ended for HL406815+5.p
125191.27/16920.73	% SZS status Started for HL406815+4.p
125191.27/16920.73	% SZS status GaveUp for HL406815+4.p
125191.27/16920.73	eprover: CPU time limit exceeded, terminating
125191.27/16920.73	% SZS status Ended for HL406815+4.p
125198.95/16921.63	% SZS status Started for HL406816+5.p
125198.95/16921.63	% SZS status GaveUp for HL406816+5.p
125198.95/16921.63	% SZS status Ended for HL406816+5.p
125200.06/16921.81	% SZS status Started for HL406816+4.p
125200.06/16921.81	% SZS status GaveUp for HL406816+4.p
125200.06/16921.81	eprover: CPU time limit exceeded, terminating
125200.06/16921.81	% SZS status Ended for HL406816+4.p
125205.02/16922.43	% SZS status Started for HL406817+5.p
125205.02/16922.43	% SZS status GaveUp for HL406817+5.p
125205.02/16922.43	% SZS status Ended for HL406817+5.p
125207.65/16922.80	% SZS status Started for HL406820+5.p
125207.65/16922.80	% SZS status Theorem for HL406820+5.p
125207.65/16922.80	% SZS status Ended for HL406820+5.p
125208.76/16922.99	% SZS status Started for HL406817+4.p
125208.76/16922.99	% SZS status GaveUp for HL406817+4.p
125208.76/16922.99	eprover: CPU time limit exceeded, terminating
125208.76/16922.99	% SZS status Ended for HL406817+4.p
125214.46/16923.72	% SZS status Started for HL406818+4.p
125214.46/16923.72	% SZS status GaveUp for HL406818+4.p
125214.46/16923.72	eprover: CPU time limit exceeded, terminating
125214.46/16923.72	% SZS status Ended for HL406818+4.p
125216.37/16923.83	% SZS status Started for HL406821+5.p
125216.37/16923.83	% SZS status Theorem for HL406821+5.p
125216.37/16923.83	% SZS status Ended for HL406821+5.p
125219.64/16924.34	% SZS status Started for HL406818+5.p
125219.64/16924.34	% SZS status GaveUp for HL406818+5.p
125219.64/16924.34	% SZS status Ended for HL406818+5.p
125222.13/16924.65	% SZS status Started for HL406822+5.p
125222.13/16924.65	% SZS status Theorem for HL406822+5.p
125222.13/16924.65	% SZS status Ended for HL406822+5.p
125233.27/16925.97	% SZS status Started for HL406824+5.p
125233.27/16925.97	% SZS status Theorem for HL406824+5.p
125233.27/16925.97	% SZS status Ended for HL406824+5.p
125248.44/16927.91	% SZS status Started for HL406825+5.p
125248.44/16927.91	% SZS status Theorem for HL406825+5.p
125248.44/16927.91	% SZS status Ended for HL406825+5.p
125267.82/16930.66	% SZS status Started for HL406820+4.p
125267.82/16930.66	% SZS status GaveUp for HL406820+4.p
125267.82/16930.66	eprover: CPU time limit exceeded, terminating
125267.82/16930.66	% SZS status Ended for HL406820+4.p
125282.81/16932.22	% SZS status Started for HL406821+4.p
125282.81/16932.22	% SZS status GaveUp for HL406821+4.p
125282.81/16932.22	eprover: CPU time limit exceeded, terminating
125282.81/16932.22	% SZS status Ended for HL406821+4.p
125283.74/16932.35	% SZS status Started for HL406826+5.p
125283.74/16932.35	% SZS status Theorem for HL406826+5.p
125283.74/16932.35	% SZS status Ended for HL406826+5.p
125290.67/16933.21	% SZS status Started for HL406823+4.p
125290.67/16933.21	% SZS status GaveUp for HL406823+4.p
125290.67/16933.21	eprover: CPU time limit exceeded, terminating
125290.67/16933.21	% SZS status Ended for HL406823+4.p
125290.91/16933.25	% SZS status Started for HL406822+4.p
125290.91/16933.25	% SZS status GaveUp for HL406822+4.p
125290.91/16933.25	eprover: CPU time limit exceeded, terminating
125290.91/16933.25	% SZS status Ended for HL406822+4.p
125291.77/16933.40	% SZS status Started for HL406823+5.p
125291.77/16933.40	% SZS status GaveUp for HL406823+5.p
125291.77/16933.40	% SZS status Ended for HL406823+5.p
125298.25/16934.20	% SZS status Started for HL406827+5.p
125298.25/16934.20	% SZS status Theorem for HL406827+5.p
125298.25/16934.20	% SZS status Ended for HL406827+5.p
125299.44/16934.32	% SZS status Started for HL406824+4.p
125299.44/16934.32	% SZS status GaveUp for HL406824+4.p
125299.44/16934.32	eprover: CPU time limit exceeded, terminating
125299.44/16934.32	% SZS status Ended for HL406824+4.p
125304.91/16935.06	% SZS status Started for HL406828+5.p
125304.91/16935.06	% SZS status Theorem for HL406828+5.p
125304.91/16935.06	% SZS status Ended for HL406828+5.p
125307.39/16935.30	% SZS status Started for HL406825+4.p
125307.39/16935.30	% SZS status GaveUp for HL406825+4.p
125307.39/16935.30	eprover: CPU time limit exceeded, terminating
125307.39/16935.30	% SZS status Ended for HL406825+4.p
125312.54/16936.07	% SZS status Started for HL406829+5.p
125312.54/16936.07	% SZS status Theorem for HL406829+5.p
125312.54/16936.07	% SZS status Ended for HL406829+5.p
125320.16/16936.91	% SZS status Started for HL406830+5.p
125320.16/16936.91	% SZS status Theorem for HL406830+5.p
125320.16/16936.91	% SZS status Ended for HL406830+5.p
125334.12/16938.67	% SZS status Started for HL406826+4.p
125334.12/16938.67	% SZS status GaveUp for HL406826+4.p
125334.12/16938.67	eprover: CPU time limit exceeded, terminating
125334.12/16938.67	% SZS status Ended for HL406826+4.p
125368.76/16943.05	% SZS status Started for HL406827+4.p
125368.76/16943.05	% SZS status GaveUp for HL406827+4.p
125368.76/16943.05	eprover: CPU time limit exceeded, terminating
125368.76/16943.05	% SZS status Ended for HL406827+4.p
125375.11/16943.88	% SZS status Started for HL406828+4.p
125375.11/16943.88	% SZS status GaveUp for HL406828+4.p
125375.11/16943.88	eprover: CPU time limit exceeded, terminating
125375.11/16943.88	% SZS status Ended for HL406828+4.p
125375.70/16943.99	% SZS status Started for HL406829+4.p
125375.70/16943.99	% SZS status GaveUp for HL406829+4.p
125375.70/16943.99	eprover: CPU time limit exceeded, terminating
125375.70/16943.99	% SZS status Ended for HL406829+4.p
125383.32/16944.91	% SZS status Started for HL406830+4.p
125383.32/16944.91	% SZS status GaveUp for HL406830+4.p
125383.32/16944.91	eprover: CPU time limit exceeded, terminating
125383.32/16944.91	% SZS status Ended for HL406830+4.p
125389.51/16945.80	% SZS status Started for HL406831+5.p
125389.51/16945.80	% SZS status GaveUp for HL406831+5.p
125389.51/16945.80	% SZS status Ended for HL406831+5.p
125389.51/16945.85	% SZS status Started for HL406831+4.p
125389.51/16945.85	% SZS status GaveUp for HL406831+4.p
125389.51/16945.85	eprover: CPU time limit exceeded, terminating
125389.51/16945.85	% SZS status Ended for HL406831+4.p
125408.34/16948.04	% SZS status Started for HL406832+4.p
125408.34/16948.04	% SZS status GaveUp for HL406832+4.p
125408.34/16948.04	eprover: CPU time limit exceeded, terminating
125408.34/16948.04	% SZS status Ended for HL406832+4.p
125411.62/16948.45	% SZS status Started for HL406832+5.p
125411.62/16948.45	% SZS status GaveUp for HL406832+5.p
125411.62/16948.45	% SZS status Ended for HL406832+5.p
125430.34/16950.83	% SZS status Started for HL406835+5.p
125430.34/16950.83	% SZS status Theorem for HL406835+5.p
125430.34/16950.83	% SZS status Ended for HL406835+5.p
125451.34/16953.55	% SZS status Started for HL406834+4.p
125451.34/16953.55	% SZS status GaveUp for HL406834+4.p
125451.34/16953.55	eprover: CPU time limit exceeded, terminating
125451.34/16953.55	% SZS status Ended for HL406834+4.p
125454.34/16953.83	% SZS status Started for HL406834+5.p
125454.34/16953.83	% SZS status GaveUp for HL406834+5.p
125454.34/16953.83	% SZS status Ended for HL406834+5.p
125459.83/16954.51	% SZS status Started for HL406835+4.p
125459.83/16954.51	% SZS status GaveUp for HL406835+4.p
125459.83/16954.51	eprover: CPU time limit exceeded, terminating
125459.83/16954.51	% SZS status Ended for HL406835+4.p
125467.97/16955.56	% SZS status Started for HL406836+5.p
125467.97/16955.56	% SZS status GaveUp for HL406836+5.p
125467.97/16955.56	% SZS status Ended for HL406836+5.p
125474.28/16956.41	% SZS status Started for HL406836+4.p
125474.28/16956.41	% SZS status GaveUp for HL406836+4.p
125474.28/16956.41	eprover: CPU time limit exceeded, terminating
125474.28/16956.41	% SZS status Ended for HL406836+4.p
125474.28/16956.41	% SZS status Started for HL406840+5.p
125474.28/16956.41	% SZS status Theorem for HL406840+5.p
125474.28/16956.41	% SZS status Ended for HL406840+5.p
125486.92/16958.08	% SZS status Started for HL406837+5.p
125486.92/16958.08	% SZS status GaveUp for HL406837+5.p
125486.92/16958.08	% SZS status Ended for HL406837+5.p
125491.62/16958.59	% SZS status Started for HL406837+4.p
125491.62/16958.59	% SZS status GaveUp for HL406837+4.p
125491.62/16958.59	eprover: CPU time limit exceeded, terminating
125491.62/16958.59	% SZS status Ended for HL406837+4.p
125500.43/16959.67	% SZS status Started for HL406839+5.p
125500.43/16959.67	% SZS status Theorem for HL406839+5.p
125500.43/16959.67	% SZS status Ended for HL406839+5.p
125516.46/16961.68	% SZS status Started for HL406839+4.p
125516.46/16961.68	% SZS status GaveUp for HL406839+4.p
125516.46/16961.68	eprover: CPU time limit exceeded, terminating
125516.46/16961.68	% SZS status Ended for HL406839+4.p
125522.88/16962.55	% SZS status Started for HL406841+5.p
125522.88/16962.55	% SZS status Theorem for HL406841+5.p
125522.88/16962.55	% SZS status Ended for HL406841+5.p
125536.92/16964.38	% SZS status Started for HL406840+4.p
125536.92/16964.38	% SZS status GaveUp for HL406840+4.p
125536.92/16964.38	eprover: CPU time limit exceeded, terminating
125536.92/16964.38	% SZS status Ended for HL406840+4.p
125537.20/16964.47	% SZS status Started for HL406842+5.p
125537.20/16964.47	% SZS status Theorem for HL406842+5.p
125537.20/16964.47	% SZS status Ended for HL406842+5.p
125552.85/16966.27	% SZS status Started for HL406841+4.p
125552.85/16966.27	% SZS status GaveUp for HL406841+4.p
125552.85/16966.27	eprover: CPU time limit exceeded, terminating
125552.85/16966.27	% SZS status Ended for HL406841+4.p
125559.53/16967.15	% SZS status Started for HL406842+4.p
125559.53/16967.15	% SZS status GaveUp for HL406842+4.p
125559.53/16967.15	eprover: CPU time limit exceeded, terminating
125559.53/16967.15	% SZS status Ended for HL406842+4.p
125574.68/16968.99	% SZS status Started for HL406848+5.p
125574.68/16968.99	% SZS status Theorem for HL406848+5.p
125574.68/16968.99	% SZS status Ended for HL406848+5.p
125575.20/16969.11	% SZS status Started for HL406843+4.p
125575.20/16969.11	% SZS status GaveUp for HL406843+4.p
125575.20/16969.11	eprover: CPU time limit exceeded, terminating
125575.20/16969.11	% SZS status Ended for HL406843+4.p
125579.09/16969.53	% SZS status Started for HL406843+5.p
125579.09/16969.53	% SZS status GaveUp for HL406843+5.p
125579.09/16969.53	% SZS status Ended for HL406843+5.p
125600.14/16972.31	% SZS status Started for HL406844+4.p
125600.14/16972.31	% SZS status GaveUp for HL406844+4.p
125600.14/16972.31	eprover: CPU time limit exceeded, terminating
125600.14/16972.31	% SZS status Ended for HL406844+4.p
125600.22/16972.34	% SZS status Started for HL406844+5.p
125600.22/16972.34	% SZS status GaveUp for HL406844+5.p
125600.22/16972.34	% SZS status Ended for HL406844+5.p
125614.91/16974.09	% SZS status Started for HL406846+5.p
125614.91/16974.09	% SZS status GaveUp for HL406846+5.p
125614.91/16974.09	% SZS status Ended for HL406846+5.p
125621.23/16974.93	% SZS status Started for HL406846+4.p
125621.23/16974.93	% SZS status GaveUp for HL406846+4.p
125621.23/16974.93	eprover: CPU time limit exceeded, terminating
125621.23/16974.93	% SZS status Ended for HL406846+4.p
125638.53/16977.07	% SZS status Started for HL406848+4.p
125638.53/16977.07	% SZS status GaveUp for HL406848+4.p
125638.53/16977.07	eprover: CPU time limit exceeded, terminating
125638.53/16977.07	% SZS status Ended for HL406848+4.p
125656.03/16979.21	% SZS status Started for HL406849+5.p
125656.03/16979.21	% SZS status GaveUp for HL406849+5.p
125656.03/16979.21	% SZS status Ended for HL406849+5.p
125658.20/16979.59	% SZS status Started for HL406849+4.p
125658.20/16979.59	% SZS status GaveUp for HL406849+4.p
125658.20/16979.59	eprover: CPU time limit exceeded, terminating
125658.20/16979.59	% SZS status Ended for HL406849+4.p
125663.19/16980.23	% SZS status Started for HL406850+4.p
125663.19/16980.23	% SZS status GaveUp for HL406850+4.p
125663.19/16980.23	eprover: CPU time limit exceeded, terminating
125663.19/16980.23	% SZS status Ended for HL406850+4.p
125671.95/16981.38	% SZS status Started for HL406854+5.p
125671.95/16981.38	% SZS status Theorem for HL406854+5.p
125671.95/16981.38	% SZS status Ended for HL406854+5.p
125677.91/16982.03	% SZS status Started for HL406850+5.p
125677.91/16982.03	% SZS status GaveUp for HL406850+5.p
125677.91/16982.03	% SZS status Ended for HL406850+5.p
125684.33/16982.87	% SZS status Started for HL406851+4.p
125684.33/16982.87	% SZS status GaveUp for HL406851+4.p
125684.33/16982.87	eprover: CPU time limit exceeded, terminating
125684.33/16982.87	% SZS status Ended for HL406851+4.p
125692.45/16983.79	% SZS status Started for HL406851+5.p
125692.45/16983.79	% SZS status GaveUp for HL406851+5.p
125692.45/16983.79	% SZS status Ended for HL406851+5.p
125699.16/16984.73	% SZS status Started for HL406858+5.p
125699.16/16984.73	% SZS status Theorem for HL406858+5.p
125699.16/16984.73	% SZS status Ended for HL406858+5.p
125706.73/16985.61	% SZS status Started for HL406852+4.p
125706.73/16985.61	% SZS status GaveUp for HL406852+4.p
125706.73/16985.61	eprover: CPU time limit exceeded, terminating
125706.73/16985.61	% SZS status Ended for HL406852+4.p
125718.94/16987.14	% SZS status Started for HL406852+5.p
125718.94/16987.14	% SZS status GaveUp for HL406852+5.p
125718.94/16987.14	% SZS status Ended for HL406852+5.p
125738.66/16989.79	% SZS status Started for HL406854+4.p
125738.66/16989.79	% SZS status GaveUp for HL406854+4.p
125738.66/16989.79	eprover: CPU time limit exceeded, terminating
125738.66/16989.79	% SZS status Ended for HL406854+4.p
125747.46/16990.75	% SZS status Started for HL406856+4.p
125747.46/16990.75	% SZS status GaveUp for HL406856+4.p
125747.46/16990.75	eprover: CPU time limit exceeded, terminating
125747.46/16990.75	% SZS status Ended for HL406856+4.p
125748.78/16990.99	% SZS status Started for HL406856+5.p
125748.78/16990.99	% SZS status GaveUp for HL406856+5.p
125748.78/16990.99	% SZS status Ended for HL406856+5.p
125761.95/16992.60	% SZS status Started for HL406858+4.p
125761.95/16992.60	% SZS status GaveUp for HL406858+4.p
125761.95/16992.60	eprover: CPU time limit exceeded, terminating
125761.95/16992.60	% SZS status Ended for HL406858+4.p
125776.66/16994.47	% SZS status Started for HL406859+4.p
125776.66/16994.47	% SZS status GaveUp for HL406859+4.p
125776.66/16994.47	eprover: CPU time limit exceeded, terminating
125776.66/16994.47	% SZS status Ended for HL406859+4.p
125777.30/16994.53	% SZS status Started for HL406859+5.p
125777.30/16994.53	% SZS status GaveUp for HL406859+5.p
125777.30/16994.53	% SZS status Ended for HL406859+5.p
125790.97/16996.22	% SZS status Started for HL406860+4.p
125790.97/16996.22	% SZS status GaveUp for HL406860+4.p
125790.97/16996.22	eprover: CPU time limit exceeded, terminating
125790.97/16996.22	% SZS status Ended for HL406860+4.p
125794.15/16996.79	% SZS status Started for HL406860+5.p
125794.15/16996.79	% SZS status GaveUp for HL406860+5.p
125794.15/16996.79	% SZS status Ended for HL406860+5.p
125823.91/17000.42	% SZS status Started for HL406861+4.p
125823.91/17000.42	% SZS status GaveUp for HL406861+4.p
125823.91/17000.42	eprover: CPU time limit exceeded, terminating
125823.91/17000.42	% SZS status Ended for HL406861+4.p
125832.59/17001.59	% SZS status Started for HL406862+4.p
125832.59/17001.59	% SZS status GaveUp for HL406862+4.p
125832.59/17001.59	eprover: CPU time limit exceeded, terminating
125832.59/17001.59	% SZS status Ended for HL406862+4.p
125861.88/17005.20	% SZS status Started for HL406863+4.p
125861.88/17005.20	% SZS status GaveUp for HL406863+4.p
125861.88/17005.20	eprover: CPU time limit exceeded, terminating
125861.88/17005.20	% SZS status Ended for HL406863+4.p
125886.30/17006.96	% SZS status Started for HL406864+4.p
125886.30/17006.96	% SZS status GaveUp for HL406864+4.p
125886.30/17006.96	eprover: CPU time limit exceeded, terminating
125886.30/17006.96	% SZS status Ended for HL406864+4.p
125919.09/17011.20	% SZS status Started for HL406865+4.p
125919.09/17011.20	% SZS status GaveUp for HL406865+4.p
125919.09/17011.20	eprover: CPU time limit exceeded, terminating
125919.09/17011.20	% SZS status Ended for HL406865+4.p
125958.26/17016.09	% SZS status Started for HL406866+4.p
125958.26/17016.09	% SZS status GaveUp for HL406866+4.p
125958.26/17016.09	eprover: CPU time limit exceeded, terminating
125958.26/17016.09	% SZS status Ended for HL406866+4.p
125961.92/17016.60	% SZS status Started for HL406861+5.p
125961.92/17016.60	% SZS status GaveUp for HL406861+5.p
125961.92/17016.60	eprover: CPU time limit exceeded, terminating
125961.92/17016.60	% SZS status Ended for HL406861+5.p
125975.41/17018.30	% SZS status Started for HL406862+5.p
125975.41/17018.30	% SZS status GaveUp for HL406862+5.p
125975.41/17018.30	eprover: CPU time limit exceeded, terminating
125975.41/17018.30	% SZS status Ended for HL406862+5.p
125990.28/17020.09	% SZS status Started for HL406863+5.p
125990.28/17020.09	% SZS status GaveUp for HL406863+5.p
125990.28/17020.09	eprover: CPU time limit exceeded, terminating
125990.28/17020.09	% SZS status Ended for HL406863+5.p
126004.77/17021.89	% SZS status Started for HL406867+4.p
126004.77/17021.89	% SZS status GaveUp for HL406867+4.p
126004.77/17021.89	eprover: CPU time limit exceeded, terminating
126004.77/17021.89	% SZS status Ended for HL406867+4.p
126009.36/17022.55	% SZS status Started for HL406864+5.p
126009.36/17022.55	% SZS status GaveUp for HL406864+5.p
126009.36/17022.55	eprover: CPU time limit exceeded, terminating
126009.36/17022.55	% SZS status Ended for HL406864+5.p
126046.94/17027.22	% SZS status Started for HL406868+4.p
126046.94/17027.22	% SZS status GaveUp for HL406868+4.p
126046.94/17027.22	eprover: CPU time limit exceeded, terminating
126046.94/17027.22	% SZS status Ended for HL406868+4.p
126048.17/17027.42	% SZS status Started for HL406865+5.p
126048.17/17027.42	% SZS status GaveUp for HL406865+5.p
126048.17/17027.42	eprover: CPU time limit exceeded, terminating
126048.17/17027.42	% SZS status Ended for HL406865+5.p
126074.54/17030.68	% SZS status Started for HL406869+4.p
126074.54/17030.68	% SZS status GaveUp for HL406869+4.p
126074.54/17030.68	eprover: CPU time limit exceeded, terminating
126074.54/17030.68	% SZS status Ended for HL406869+4.p
126089.91/17032.67	% SZS status Started for HL406866+5.p
126089.91/17032.67	% SZS status GaveUp for HL406866+5.p
126089.91/17032.67	eprover: CPU time limit exceeded, terminating
126089.91/17032.67	% SZS status Ended for HL406866+5.p
126094.41/17033.18	% SZS status Started for HL406870+4.p
126094.41/17033.18	% SZS status GaveUp for HL406870+4.p
126094.41/17033.18	eprover: CPU time limit exceeded, terminating
126094.41/17033.18	% SZS status Ended for HL406870+4.p
126132.62/17038.03	% SZS status Started for HL406871+4.p
126132.62/17038.03	% SZS status GaveUp for HL406871+4.p
126132.62/17038.03	eprover: CPU time limit exceeded, terminating
126132.62/17038.03	% SZS status Ended for HL406871+4.p
126164.87/17042.05	% SZS status Started for HL406867+5.p
126164.87/17042.05	% SZS status GaveUp for HL406867+5.p
126164.87/17042.05	eprover: CPU time limit exceeded, terminating
126164.87/17042.05	% SZS status Ended for HL406867+5.p
126175.56/17043.37	% SZS status Started for HL406874+4.p
126175.56/17043.37	% SZS status GaveUp for HL406874+4.p
126175.56/17043.37	eprover: CPU time limit exceeded, terminating
126175.56/17043.37	% SZS status Ended for HL406874+4.p
126182.81/17044.35	% SZS status Started for HL406868+5.p
126182.81/17044.35	% SZS status GaveUp for HL406868+5.p
126182.81/17044.35	eprover: CPU time limit exceeded, terminating
126182.81/17044.35	% SZS status Ended for HL406868+5.p
126199.41/17046.41	% SZS status Started for HL406876+4.p
126199.41/17046.41	% SZS status GaveUp for HL406876+4.p
126199.41/17046.41	eprover: CPU time limit exceeded, terminating
126199.41/17046.41	% SZS status Ended for HL406876+4.p
126211.48/17048.01	% SZS status Started for HL406869+5.p
126211.48/17048.01	% SZS status GaveUp for HL406869+5.p
126211.48/17048.01	eprover: CPU time limit exceeded, terminating
126211.48/17048.01	% SZS status Ended for HL406869+5.p
126221.15/17049.18	% SZS status Started for HL406875+4.p
126221.15/17049.18	% SZS status GaveUp for HL406875+4.p
126221.15/17049.18	eprover: CPU time limit exceeded, terminating
126221.15/17049.18	% SZS status Ended for HL406875+4.p
126223.19/17049.50	% SZS status Started for HL406877+4.p
126223.19/17049.50	% SZS status GaveUp for HL406877+4.p
126223.19/17049.50	eprover: CPU time limit exceeded, terminating
126223.19/17049.50	% SZS status Ended for HL406877+4.p
126244.90/17052.21	% SZS status Started for HL406878+4.p
126244.90/17052.21	% SZS status GaveUp for HL406878+4.p
126244.90/17052.21	eprover: CPU time limit exceeded, terminating
126244.90/17052.21	% SZS status Ended for HL406878+4.p
126246.09/17052.36	% SZS status Started for HL406875+5.p
126246.09/17052.36	% SZS status GaveUp for HL406875+5.p
126246.09/17052.36	eprover: CPU time limit exceeded, terminating
126246.09/17052.36	% SZS status Ended for HL406875+5.p
126251.86/17053.08	% SZS status Started for HL406870+5.p
126251.86/17053.08	% SZS status GaveUp for HL406870+5.p
126251.86/17053.08	eprover: CPU time limit exceeded, terminating
126251.86/17053.08	% SZS status Ended for HL406870+5.p
126264.62/17054.70	% SZS status Started for HL406876+5.p
126264.62/17054.70	% SZS status GaveUp for HL406876+5.p
126264.62/17054.70	eprover: CPU time limit exceeded, terminating
126264.62/17054.70	% SZS status Ended for HL406876+5.p
126268.70/17055.25	% SZS status Started for HL406879+4.p
126268.70/17055.25	% SZS status GaveUp for HL406879+4.p
126268.70/17055.25	eprover: CPU time limit exceeded, terminating
126268.70/17055.25	% SZS status Ended for HL406879+4.p
126279.34/17056.30	% SZS status Started for HL406880+4.p
126279.34/17056.30	% SZS status GaveUp for HL406880+4.p
126279.34/17056.30	eprover: CPU time limit exceeded, terminating
126279.34/17056.30	% SZS status Ended for HL406880+4.p
126281.53/17056.57	% SZS status Started for HL406871+5.p
126281.53/17056.57	% SZS status GaveUp for HL406871+5.p
126281.53/17056.57	eprover: CPU time limit exceeded, terminating
126281.53/17056.57	% SZS status Ended for HL406871+5.p
126295.34/17058.29	% SZS status Started for HL406884+4.p
126295.34/17058.29	% SZS status GaveUp for HL406884+4.p
126295.34/17058.29	eprover: CPU time limit exceeded, terminating
126295.34/17058.29	% SZS status Ended for HL406884+4.p
126296.78/17058.50	% SZS status Started for HL406877+5.p
126296.78/17058.50	% SZS status GaveUp for HL406877+5.p
126296.78/17058.50	eprover: CPU time limit exceeded, terminating
126296.78/17058.50	% SZS status Ended for HL406877+5.p
126300.58/17059.11	% SZS status Started for HL406874+5.p
126300.58/17059.11	% SZS status GaveUp for HL406874+5.p
126300.58/17059.11	eprover: CPU time limit exceeded, terminating
126300.58/17059.11	% SZS status Ended for HL406874+5.p
126305.30/17059.63	% SZS status Started for HL406885+4.p
126305.30/17059.63	% SZS status GaveUp for HL406885+4.p
126305.30/17059.63	eprover: CPU time limit exceeded, terminating
126305.30/17059.63	% SZS status Ended for HL406885+4.p
126308.20/17060.15	% SZS status Started for HL406878+5.p
126308.20/17060.15	% SZS status GaveUp for HL406878+5.p
126308.20/17060.15	eprover: CPU time limit exceeded, terminating
126308.20/17060.15	% SZS status Ended for HL406878+5.p
126321.18/17061.71	% SZS status Started for HL406886+4.p
126321.18/17061.71	% SZS status GaveUp for HL406886+4.p
126321.18/17061.71	eprover: CPU time limit exceeded, terminating
126321.18/17061.71	% SZS status Ended for HL406886+4.p
126329.08/17062.68	% SZS status Started for HL406887+4.p
126329.08/17062.68	% SZS status GaveUp for HL406887+4.p
126329.08/17062.68	eprover: CPU time limit exceeded, terminating
126329.08/17062.68	% SZS status Ended for HL406887+4.p
126331.45/17063.01	% SZS status Started for HL406879+5.p
126331.45/17063.01	% SZS status GaveUp for HL406879+5.p
126331.45/17063.01	eprover: CPU time limit exceeded, terminating
126331.45/17063.01	% SZS status Ended for HL406879+5.p
126345.40/17064.74	% SZS status Started for HL406888+4.p
126345.40/17064.74	% SZS status GaveUp for HL406888+4.p
126345.40/17064.74	eprover: CPU time limit exceeded, terminating
126345.40/17064.74	% SZS status Ended for HL406888+4.p
126348.84/17065.23	% SZS status Started for HL406880+5.p
126348.84/17065.23	% SZS status GaveUp for HL406880+5.p
126348.84/17065.23	eprover: CPU time limit exceeded, terminating
126348.84/17065.23	% SZS status Ended for HL406880+5.p
126357.48/17066.26	% SZS status Started for HL406889+4.p
126357.48/17066.26	% SZS status GaveUp for HL406889+4.p
126357.48/17066.26	eprover: CPU time limit exceeded, terminating
126357.48/17066.26	% SZS status Ended for HL406889+4.p
126360.15/17066.80	% SZS status Started for HL406884+5.p
126360.15/17066.80	% SZS status GaveUp for HL406884+5.p
126360.15/17066.80	eprover: CPU time limit exceeded, terminating
126360.15/17066.80	% SZS status Ended for HL406884+5.p
126372.16/17068.26	% SZS status Started for HL406890+4.p
126372.16/17068.26	% SZS status GaveUp for HL406890+4.p
126372.16/17068.26	eprover: CPU time limit exceeded, terminating
126372.16/17068.26	% SZS status Ended for HL406890+4.p
126375.52/17068.63	% SZS status Started for HL406885+5.p
126375.52/17068.63	% SZS status GaveUp for HL406885+5.p
126375.52/17068.63	eprover: CPU time limit exceeded, terminating
126375.52/17068.63	% SZS status Ended for HL406885+5.p
126383.05/17069.63	% SZS status Started for HL406886+5.p
126383.05/17069.63	% SZS status GaveUp for HL406886+5.p
126383.05/17069.63	eprover: CPU time limit exceeded, terminating
126383.05/17069.63	% SZS status Ended for HL406886+5.p
126385.66/17069.89	% SZS status Started for HL406891+4.p
126385.66/17069.89	% SZS status GaveUp for HL406891+4.p
126385.66/17069.89	eprover: CPU time limit exceeded, terminating
126385.66/17069.89	% SZS status Ended for HL406891+4.p
126390.42/17070.51	% SZS status Started for HL406887+5.p
126390.42/17070.51	% SZS status GaveUp for HL406887+5.p
126390.42/17070.51	eprover: CPU time limit exceeded, terminating
126390.42/17070.51	% SZS status Ended for HL406887+5.p
126399.24/17071.69	% SZS status Started for HL406893+4.p
126399.24/17071.69	% SZS status GaveUp for HL406893+4.p
126399.24/17071.69	eprover: CPU time limit exceeded, terminating
126399.24/17071.69	% SZS status Ended for HL406893+4.p
126409.17/17072.93	% SZS status Started for HL406894+4.p
126409.17/17072.93	% SZS status GaveUp for HL406894+4.p
126409.17/17072.93	eprover: CPU time limit exceeded, terminating
126409.17/17072.93	% SZS status Ended for HL406894+4.p
126424.18/17074.85	% SZS status Started for HL406895+4.p
126424.18/17074.85	% SZS status GaveUp for HL406895+4.p
126424.18/17074.85	eprover: CPU time limit exceeded, terminating
126424.18/17074.85	% SZS status Ended for HL406895+4.p
126425.84/17075.05	% SZS status Started for HL406889+5.p
126425.84/17075.05	% SZS status GaveUp for HL406889+5.p
126425.84/17075.05	eprover: CPU time limit exceeded, terminating
126425.84/17075.05	% SZS status Ended for HL406889+5.p
126448.60/17077.88	% SZS status Started for HL406896+4.p
126448.60/17077.88	% SZS status GaveUp for HL406896+4.p
126448.60/17077.88	eprover: CPU time limit exceeded, terminating
126448.60/17077.88	% SZS status Ended for HL406896+4.p
126454.59/17078.69	% SZS status Started for HL406891+5.p
126454.59/17078.69	% SZS status GaveUp for HL406891+5.p
126454.59/17078.69	eprover: CPU time limit exceeded, terminating
126454.59/17078.69	% SZS status Ended for HL406891+5.p
126467.56/17080.29	% SZS status Started for HL406893+5.p
126467.56/17080.29	% SZS status GaveUp for HL406893+5.p
126467.56/17080.29	eprover: CPU time limit exceeded, terminating
126467.56/17080.29	% SZS status Ended for HL406893+5.p
126472.09/17080.93	% SZS status Started for HL406897+4.p
126472.09/17080.93	% SZS status GaveUp for HL406897+4.p
126472.09/17080.93	eprover: CPU time limit exceeded, terminating
126472.09/17080.93	% SZS status Ended for HL406897+4.p
126491.59/17083.49	% SZS status Started for HL406898+4.p
126491.59/17083.49	% SZS status GaveUp for HL406898+4.p
126491.59/17083.49	eprover: CPU time limit exceeded, terminating
126491.59/17083.49	% SZS status Ended for HL406898+4.p
126491.59/17083.50	% SZS status Started for HL406895+5.p
126491.59/17083.50	% SZS status GaveUp for HL406895+5.p
126491.59/17083.50	eprover: CPU time limit exceeded, terminating
126491.59/17083.50	% SZS status Ended for HL406895+5.p
126507.81/17085.39	% SZS status Started for HL406896+5.p
126507.81/17085.39	% SZS status GaveUp for HL406896+5.p
126507.81/17085.39	eprover: CPU time limit exceeded, terminating
126507.81/17085.39	% SZS status Ended for HL406896+5.p
126516.66/17086.52	% SZS status Started for HL406899+4.p
126516.66/17086.52	% SZS status GaveUp for HL406899+4.p
126516.66/17086.52	eprover: CPU time limit exceeded, terminating
126516.66/17086.52	% SZS status Ended for HL406899+4.p
126531.27/17088.42	% SZS status Started for HL406900+4.p
126531.27/17088.42	% SZS status GaveUp for HL406900+4.p
126531.27/17088.42	eprover: CPU time limit exceeded, terminating
126531.27/17088.42	% SZS status Ended for HL406900+4.p
126532.52/17088.60	% SZS status Started for HL406890+5.p
126532.52/17088.60	% SZS status GaveUp for HL406890+5.p
126532.52/17088.60	eprover: CPU time limit exceeded, terminating
126532.52/17088.60	% SZS status Ended for HL406890+5.p
126539.04/17089.39	% SZS status Started for HL406888+5.p
126539.04/17089.39	% SZS status GaveUp for HL406888+5.p
126539.04/17089.39	eprover: CPU time limit exceeded, terminating
126539.04/17089.39	% SZS status Ended for HL406888+5.p
126540.15/17089.56	% SZS status Started for HL406897+5.p
126540.15/17089.56	% SZS status GaveUp for HL406897+5.p
126540.15/17089.56	eprover: CPU time limit exceeded, terminating
126540.15/17089.56	% SZS status Ended for HL406897+5.p
126551.95/17091.02	% SZS status Started for HL406894+5.p
126551.95/17091.02	% SZS status GaveUp for HL406894+5.p
126551.95/17091.02	eprover: CPU time limit exceeded, terminating
126551.95/17091.02	% SZS status Ended for HL406894+5.p
126553.48/17091.31	% SZS status Started for HL406898+5.p
126553.48/17091.31	% SZS status GaveUp for HL406898+5.p
126553.48/17091.31	eprover: CPU time limit exceeded, terminating
126553.48/17091.31	% SZS status Ended for HL406898+5.p
126555.71/17091.53	% SZS status Started for HL406901+4.p
126555.71/17091.53	% SZS status GaveUp for HL406901+4.p
126555.71/17091.53	eprover: CPU time limit exceeded, terminating
126555.71/17091.53	% SZS status Ended for HL406901+4.p
126561.84/17092.42	% SZS status Started for HL406902+4.p
126561.84/17092.42	% SZS status GaveUp for HL406902+4.p
126561.84/17092.42	eprover: CPU time limit exceeded, terminating
126561.84/17092.42	% SZS status Ended for HL406902+4.p
126575.22/17094.05	% SZS status Started for HL406899+5.p
126575.22/17094.05	% SZS status GaveUp for HL406899+5.p
126575.22/17094.05	eprover: CPU time limit exceeded, terminating
126575.22/17094.05	% SZS status Ended for HL406899+5.p
126578.08/17094.34	% SZS status Started for HL406903+4.p
126578.08/17094.34	% SZS status GaveUp for HL406903+4.p
126578.08/17094.34	eprover: CPU time limit exceeded, terminating
126578.08/17094.34	% SZS status Ended for HL406903+4.p
126581.23/17094.76	% SZS status Started for HL406904+4.p
126581.23/17094.76	% SZS status GaveUp for HL406904+4.p
126581.23/17094.76	eprover: CPU time limit exceeded, terminating
126581.23/17094.76	% SZS status Ended for HL406904+4.p
126597.16/17096.84	% SZS status Started for HL406900+5.p
126597.16/17096.84	% SZS status GaveUp for HL406900+5.p
126597.16/17096.84	eprover: CPU time limit exceeded, terminating
126597.16/17096.84	% SZS status Ended for HL406900+5.p
126599.73/17097.08	% SZS status Started for HL406906+4.p
126599.73/17097.08	% SZS status GaveUp for HL406906+4.p
126599.73/17097.08	eprover: CPU time limit exceeded, terminating
126599.73/17097.08	% SZS status Ended for HL406906+4.p
126604.67/17097.80	% SZS status Started for HL406907+4.p
126604.67/17097.80	% SZS status GaveUp for HL406907+4.p
126604.67/17097.80	eprover: CPU time limit exceeded, terminating
126604.67/17097.80	% SZS status Ended for HL406907+4.p
126616.88/17099.28	% SZS status Started for HL406901+5.p
126616.88/17099.28	% SZS status GaveUp for HL406901+5.p
126616.88/17099.28	eprover: CPU time limit exceeded, terminating
126616.88/17099.28	% SZS status Ended for HL406901+5.p
126622.37/17099.93	% SZS status Started for HL406902+5.p
126622.37/17099.93	% SZS status GaveUp for HL406902+5.p
126622.37/17099.93	eprover: CPU time limit exceeded, terminating
126622.37/17099.93	% SZS status Ended for HL406902+5.p
126623.62/17100.21	% SZS status Started for HL406908+4.p
126623.62/17100.21	% SZS status GaveUp for HL406908+4.p
126623.62/17100.21	eprover: CPU time limit exceeded, terminating
126623.62/17100.21	% SZS status Ended for HL406908+4.p
126635.95/17101.65	% SZS status Started for HL406903+5.p
126635.95/17101.65	% SZS status GaveUp for HL406903+5.p
126635.95/17101.65	eprover: CPU time limit exceeded, terminating
126635.95/17101.65	% SZS status Ended for HL406903+5.p
126641.28/17102.32	% SZS status Started for HL406910+4.p
126641.28/17102.32	% SZS status GaveUp for HL406910+4.p
126641.28/17102.32	eprover: CPU time limit exceeded, terminating
126641.28/17102.32	% SZS status Ended for HL406910+4.p
126644.37/17102.74	% SZS status Started for HL406904+5.p
126644.37/17102.74	% SZS status GaveUp for HL406904+5.p
126644.37/17102.74	eprover: CPU time limit exceeded, terminating
126644.37/17102.74	% SZS status Ended for HL406904+5.p
126648.63/17103.24	% SZS status Started for HL406911+4.p
126648.63/17103.24	% SZS status GaveUp for HL406911+4.p
126648.63/17103.24	eprover: CPU time limit exceeded, terminating
126648.63/17103.24	% SZS status Ended for HL406911+4.p
126659.70/17104.66	% SZS status Started for HL406906+5.p
126659.70/17104.66	% SZS status GaveUp for HL406906+5.p
126659.70/17104.66	eprover: CPU time limit exceeded, terminating
126659.70/17104.66	% SZS status Ended for HL406906+5.p
126664.50/17105.35	% SZS status Started for HL406912+4.p
126664.50/17105.35	% SZS status GaveUp for HL406912+4.p
126664.50/17105.35	eprover: CPU time limit exceeded, terminating
126664.50/17105.35	% SZS status Ended for HL406912+4.p
126672.13/17106.27	% SZS status Started for HL406913+4.p
126672.13/17106.27	% SZS status GaveUp for HL406913+4.p
126672.13/17106.27	eprover: CPU time limit exceeded, terminating
126672.13/17106.27	% SZS status Ended for HL406913+4.p
126678.79/17107.11	% SZS status Started for HL406907+5.p
126678.79/17107.11	% SZS status GaveUp for HL406907+5.p
126678.79/17107.11	eprover: CPU time limit exceeded, terminating
126678.79/17107.11	% SZS status Ended for HL406907+5.p
126686.91/17108.14	% SZS status Started for HL406908+5.p
126686.91/17108.14	% SZS status GaveUp for HL406908+5.p
126686.91/17108.14	eprover: CPU time limit exceeded, terminating
126686.91/17108.14	% SZS status Ended for HL406908+5.p
126689.59/17108.39	% SZS status Started for HL406914+4.p
126689.59/17108.39	% SZS status GaveUp for HL406914+4.p
126689.59/17108.39	eprover: CPU time limit exceeded, terminating
126689.59/17108.39	% SZS status Ended for HL406914+4.p
126703.05/17110.15	% SZS status Started for HL406915+4.p
126703.05/17110.15	% SZS status GaveUp for HL406915+4.p
126703.05/17110.15	eprover: CPU time limit exceeded, terminating
126703.05/17110.15	% SZS status Ended for HL406915+4.p
126708.08/17110.81	% SZS status Started for HL406910+5.p
126708.08/17110.81	% SZS status GaveUp for HL406910+5.p
126708.08/17110.81	eprover: CPU time limit exceeded, terminating
126708.08/17110.81	% SZS status Ended for HL406910+5.p
126714.01/17111.63	% SZS status Started for HL406916+4.p
126714.01/17111.63	% SZS status GaveUp for HL406916+4.p
126714.01/17111.63	eprover: CPU time limit exceeded, terminating
126714.01/17111.63	% SZS status Ended for HL406916+4.p
126717.34/17112.03	% SZS status Started for HL406911+5.p
126717.34/17112.03	% SZS status GaveUp for HL406911+5.p
126717.34/17112.03	eprover: CPU time limit exceeded, terminating
126717.34/17112.03	% SZS status Ended for HL406911+5.p
126725.35/17113.21	% SZS status Started for HL406912+5.p
126725.35/17113.21	% SZS status GaveUp for HL406912+5.p
126725.35/17113.21	eprover: CPU time limit exceeded, terminating
126725.35/17113.21	% SZS status Ended for HL406912+5.p
126732.66/17114.11	% SZS status Started for HL406917+4.p
126732.66/17114.11	% SZS status GaveUp for HL406917+4.p
126732.66/17114.11	eprover: CPU time limit exceeded, terminating
126732.66/17114.11	% SZS status Ended for HL406917+4.p
126740.17/17115.11	% SZS status Started for HL406913+5.p
126740.17/17115.11	% SZS status GaveUp for HL406913+5.p
126740.17/17115.11	eprover: CPU time limit exceeded, terminating
126740.17/17115.11	% SZS status Ended for HL406913+5.p
126745.26/17115.69	% SZS status Started for HL406918+4.p
126745.26/17115.69	% SZS status GaveUp for HL406918+4.p
126745.26/17115.69	eprover: CPU time limit exceeded, terminating
126745.26/17115.69	% SZS status Ended for HL406918+4.p
126756.68/17117.21	% SZS status Started for HL406919+4.p
126756.68/17117.21	% SZS status GaveUp for HL406919+4.p
126756.68/17117.21	eprover: CPU time limit exceeded, terminating
126756.68/17117.21	% SZS status Ended for HL406919+4.p
126759.29/17117.54	% SZS status Started for HL406914+5.p
126759.29/17117.54	% SZS status GaveUp for HL406914+5.p
126759.29/17117.54	eprover: CPU time limit exceeded, terminating
126759.29/17117.54	% SZS status Ended for HL406914+5.p
126768.32/17118.73	% SZS status Started for HL406920+4.p
126768.32/17118.73	% SZS status GaveUp for HL406920+4.p
126768.32/17118.73	eprover: CPU time limit exceeded, terminating
126768.32/17118.73	% SZS status Ended for HL406920+4.p
126769.11/17118.88	% SZS status Started for HL406915+5.p
126769.11/17118.88	% SZS status GaveUp for HL406915+5.p
126769.11/17118.88	eprover: CPU time limit exceeded, terminating
126769.11/17118.88	% SZS status Ended for HL406915+5.p
126782.53/17120.57	% SZS status Started for HL406923+4.p
126782.53/17120.57	% SZS status GaveUp for HL406923+4.p
126782.53/17120.57	eprover: CPU time limit exceeded, terminating
126782.53/17120.57	% SZS status Ended for HL406923+4.p
126785.23/17120.91	% SZS status Started for HL406916+5.p
126785.23/17120.91	% SZS status GaveUp for HL406916+5.p
126785.23/17120.91	eprover: CPU time limit exceeded, terminating
126785.23/17120.91	% SZS status Ended for HL406916+5.p
126794.02/17121.97	% SZS status Started for HL406924+4.p
126794.02/17121.97	% SZS status GaveUp for HL406924+4.p
126794.02/17121.97	eprover: CPU time limit exceeded, terminating
126794.02/17121.97	% SZS status Ended for HL406924+4.p
126809.11/17123.93	% SZS status Started for HL406918+5.p
126809.11/17123.93	% SZS status GaveUp for HL406918+5.p
126809.11/17123.93	eprover: CPU time limit exceeded, terminating
126809.11/17123.93	% SZS status Ended for HL406918+5.p
126809.11/17123.95	% SZS status Started for HL406925+4.p
126809.11/17123.95	% SZS status GaveUp for HL406925+4.p
126809.11/17123.95	eprover: CPU time limit exceeded, terminating
126809.11/17123.95	% SZS status Ended for HL406925+4.p
126821.91/17125.48	% SZS status Started for HL406919+5.p
126821.91/17125.48	% SZS status GaveUp for HL406919+5.p
126821.91/17125.48	eprover: CPU time limit exceeded, terminating
126821.91/17125.48	% SZS status Ended for HL406919+5.p
126833.09/17126.96	% SZS status Started for HL406926+4.p
126833.09/17126.96	% SZS status GaveUp for HL406926+4.p
126833.09/17126.96	eprover: CPU time limit exceeded, terminating
126833.09/17126.96	% SZS status Ended for HL406926+4.p
126841.91/17128.01	% SZS status Started for HL406920+5.p
126841.91/17128.01	% SZS status GaveUp for HL406920+5.p
126841.91/17128.01	eprover: CPU time limit exceeded, terminating
126841.91/17128.01	% SZS status Ended for HL406920+5.p
126845.70/17128.51	% SZS status Started for HL406927+4.p
126845.70/17128.51	% SZS status GaveUp for HL406927+4.p
126845.70/17128.51	eprover: CPU time limit exceeded, terminating
126845.70/17128.51	% SZS status Ended for HL406927+4.p
126850.02/17129.09	% SZS status Started for HL406923+5.p
126850.02/17129.09	% SZS status GaveUp for HL406923+5.p
126850.02/17129.09	eprover: CPU time limit exceeded, terminating
126850.02/17129.09	% SZS status Ended for HL406923+5.p
126864.95/17130.93	% SZS status Started for HL406924+5.p
126864.95/17130.93	% SZS status GaveUp for HL406924+5.p
126864.95/17130.93	eprover: CPU time limit exceeded, terminating
126864.95/17130.93	% SZS status Ended for HL406924+5.p
126865.48/17131.06	% SZS status Started for HL406929+4.p
126865.48/17131.06	% SZS status GaveUp for HL406929+4.p
126865.48/17131.06	eprover: CPU time limit exceeded, terminating
126865.48/17131.06	% SZS status Ended for HL406929+4.p
126874.02/17132.13	% SZS status Started for HL406930+4.p
126874.02/17132.13	% SZS status GaveUp for HL406930+4.p
126874.02/17132.13	eprover: CPU time limit exceeded, terminating
126874.02/17132.13	% SZS status Ended for HL406930+4.p
126877.46/17132.47	% SZS status Started for HL406925+5.p
126877.46/17132.47	% SZS status GaveUp for HL406925+5.p
126877.46/17132.47	eprover: CPU time limit exceeded, terminating
126877.46/17132.47	% SZS status Ended for HL406925+5.p
126890.30/17134.09	% SZS status Started for HL406931+4.p
126890.30/17134.09	% SZS status GaveUp for HL406931+4.p
126890.30/17134.09	eprover: CPU time limit exceeded, terminating
126890.30/17134.09	% SZS status Ended for HL406931+4.p
126891.77/17134.35	% SZS status Started for HL406926+5.p
126891.77/17134.35	% SZS status GaveUp for HL406926+5.p
126891.77/17134.35	eprover: CPU time limit exceeded, terminating
126891.77/17134.35	% SZS status Ended for HL406926+5.p
126901.31/17135.58	% SZS status Started for HL406932+4.p
126901.31/17135.58	% SZS status GaveUp for HL406932+4.p
126901.31/17135.58	eprover: CPU time limit exceeded, terminating
126901.31/17135.58	% SZS status Ended for HL406932+4.p
126915.38/17137.32	% SZS status Started for HL406927+5.p
126915.38/17137.32	% SZS status GaveUp for HL406927+5.p
126915.38/17137.32	eprover: CPU time limit exceeded, terminating
126915.38/17137.32	% SZS status Ended for HL406927+5.p
126916.88/17137.45	% SZS status Started for HL406933+4.p
126916.88/17137.45	% SZS status GaveUp for HL406933+4.p
126916.88/17137.45	eprover: CPU time limit exceeded, terminating
126916.88/17137.45	% SZS status Ended for HL406933+4.p
126921.05/17137.97	% SZS status Started for HL406917+5.p
126921.05/17137.97	% SZS status GaveUp for HL406917+5.p
126921.05/17137.97	eprover: CPU time limit exceeded, terminating
126921.05/17137.97	% SZS status Ended for HL406917+5.p
126928.55/17138.90	% SZS status Started for HL406929+5.p
126928.55/17138.90	% SZS status GaveUp for HL406929+5.p
126928.55/17138.90	eprover: CPU time limit exceeded, terminating
126928.55/17138.90	% SZS status Ended for HL406929+5.p
126939.61/17140.37	% SZS status Started for HL406935+4.p
126939.61/17140.37	% SZS status GaveUp for HL406935+4.p
126939.61/17140.37	eprover: CPU time limit exceeded, terminating
126939.61/17140.37	% SZS status Ended for HL406935+4.p
126944.63/17141.01	% SZS status Started for HL406936+4.p
126944.63/17141.01	% SZS status GaveUp for HL406936+4.p
126944.63/17141.01	eprover: CPU time limit exceeded, terminating
126944.63/17141.01	% SZS status Ended for HL406936+4.p
126948.04/17141.47	% SZS status Started for HL406930+5.p
126948.04/17141.47	% SZS status GaveUp for HL406930+5.p
126948.04/17141.47	eprover: CPU time limit exceeded, terminating
126948.04/17141.47	% SZS status Ended for HL406930+5.p
126955.43/17142.53	% SZS status Started for HL406931+5.p
126955.43/17142.53	% SZS status GaveUp for HL406931+5.p
126955.43/17142.53	eprover: CPU time limit exceeded, terminating
126955.43/17142.53	% SZS status Ended for HL406931+5.p
126963.75/17143.45	% SZS status Started for HL406938+4.p
126963.75/17143.45	% SZS status GaveUp for HL406938+4.p
126963.75/17143.45	eprover: CPU time limit exceeded, terminating
126963.75/17143.45	% SZS status Ended for HL406938+4.p
126971.56/17144.51	% SZS status Started for HL406939+4.p
126971.56/17144.51	% SZS status GaveUp for HL406939+4.p
126971.56/17144.51	eprover: CPU time limit exceeded, terminating
126971.56/17144.51	% SZS status Ended for HL406939+4.p
126974.41/17144.82	% SZS status Started for HL406932+5.p
126974.41/17144.82	% SZS status GaveUp for HL406932+5.p
126974.41/17144.82	eprover: CPU time limit exceeded, terminating
126974.41/17144.82	% SZS status Ended for HL406932+5.p
126984.37/17146.08	% SZS status Started for HL406933+5.p
126984.37/17146.08	% SZS status GaveUp for HL406933+5.p
126984.37/17146.08	eprover: CPU time limit exceeded, terminating
126984.37/17146.08	% SZS status Ended for HL406933+5.p
126986.98/17146.49	% SZS status Started for HL406941+4.p
126986.98/17146.49	% SZS status GaveUp for HL406941+4.p
126986.98/17146.49	eprover: CPU time limit exceeded, terminating
126986.98/17146.49	% SZS status Ended for HL406941+4.p
126998.81/17147.85	% SZS status Started for HL406942+4.p
126998.81/17147.85	% SZS status GaveUp for HL406942+4.p
126998.81/17147.85	eprover: CPU time limit exceeded, terminating
126998.81/17147.85	% SZS status Ended for HL406942+4.p
126999.32/17147.97	% SZS status Started for HL406935+5.p
126999.32/17147.97	% SZS status GaveUp for HL406935+5.p
126999.32/17147.97	eprover: CPU time limit exceeded, terminating
126999.32/17147.97	% SZS status Ended for HL406935+5.p
127010.11/17149.41	% SZS status Started for HL406936+5.p
127010.11/17149.41	% SZS status GaveUp for HL406936+5.p
127010.11/17149.41	eprover: CPU time limit exceeded, terminating
127010.11/17149.41	% SZS status Ended for HL406936+5.p
127013.80/17149.78	% SZS status Started for HL406944+4.p
127013.80/17149.78	% SZS status GaveUp for HL406944+4.p
127013.80/17149.78	eprover: CPU time limit exceeded, terminating
127013.80/17149.78	% SZS status Ended for HL406944+4.p
127023.04/17151.00	% SZS status Started for HL406946+4.p
127023.04/17151.00	% SZS status GaveUp for HL406946+4.p
127023.04/17151.00	eprover: CPU time limit exceeded, terminating
127023.04/17151.00	% SZS status Ended for HL406946+4.p
127027.02/17151.47	% SZS status Started for HL406938+5.p
127027.02/17151.47	% SZS status GaveUp for HL406938+5.p
127027.02/17151.47	eprover: CPU time limit exceeded, terminating
127027.02/17151.47	% SZS status Ended for HL406938+5.p
127037.67/17152.82	% SZS status Started for HL406947+4.p
127037.67/17152.82	% SZS status GaveUp for HL406947+4.p
127037.67/17152.82	eprover: CPU time limit exceeded, terminating
127037.67/17152.82	% SZS status Ended for HL406947+4.p
127039.60/17153.19	% SZS status Started for HL406939+5.p
127039.60/17153.19	% SZS status GaveUp for HL406939+5.p
127039.60/17153.19	eprover: CPU time limit exceeded, terminating
127039.60/17153.19	% SZS status Ended for HL406939+5.p
127051.73/17154.56	% SZS status Started for HL406948+4.p
127051.73/17154.56	% SZS status GaveUp for HL406948+4.p
127051.73/17154.56	eprover: CPU time limit exceeded, terminating
127051.73/17154.56	% SZS status Ended for HL406948+4.p
127053.70/17154.91	% SZS status Started for HL406941+5.p
127053.70/17154.91	% SZS status GaveUp for HL406941+5.p
127053.70/17154.91	eprover: CPU time limit exceeded, terminating
127053.70/17154.91	% SZS status Ended for HL406941+5.p
127064.00/17156.23	% SZS status Started for HL406949+4.p
127064.00/17156.23	% SZS status GaveUp for HL406949+4.p
127064.00/17156.23	eprover: CPU time limit exceeded, terminating
127064.00/17156.23	% SZS status Ended for HL406949+4.p
127068.74/17156.54	% SZS status Started for HL406942+5.p
127068.74/17156.54	% SZS status GaveUp for HL406942+5.p
127068.74/17156.54	eprover: CPU time limit exceeded, terminating
127068.74/17156.54	% SZS status Ended for HL406942+5.p
127081.88/17158.11	% SZS status Started for HL406950+4.p
127081.88/17158.11	% SZS status GaveUp for HL406950+4.p
127081.88/17158.11	eprover: CPU time limit exceeded, terminating
127081.88/17158.11	% SZS status Ended for HL406950+4.p
127093.93/17159.67	% SZS status Started for HL406951+4.p
127093.93/17159.67	% SZS status GaveUp for HL406951+4.p
127093.93/17159.67	eprover: CPU time limit exceeded, terminating
127093.93/17159.67	% SZS status Ended for HL406951+4.p
127095.30/17159.83	% SZS status Started for HL406946+5.p
127095.30/17159.83	% SZS status GaveUp for HL406946+5.p
127095.30/17159.83	eprover: CPU time limit exceeded, terminating
127095.30/17159.83	% SZS status Ended for HL406946+5.p
127107.88/17161.40	% SZS status Started for HL406947+5.p
127107.88/17161.40	% SZS status GaveUp for HL406947+5.p
127107.88/17161.40	eprover: CPU time limit exceeded, terminating
127107.88/17161.40	% SZS status Ended for HL406947+5.p
127123.27/17163.34	% SZS status Started for HL406948+5.p
127123.27/17163.34	% SZS status GaveUp for HL406948+5.p
127123.27/17163.34	eprover: CPU time limit exceeded, terminating
127123.27/17163.34	% SZS status Ended for HL406948+5.p
127134.09/17164.95	% SZS status Started for HL406949+5.p
127134.09/17164.95	% SZS status GaveUp for HL406949+5.p
127134.09/17164.95	eprover: CPU time limit exceeded, terminating
127134.09/17164.95	% SZS status Ended for HL406949+5.p
127148.77/17166.59	% SZS status Started for HL406950+5.p
127148.77/17166.59	% SZS status GaveUp for HL406950+5.p
127148.77/17166.59	eprover: CPU time limit exceeded, terminating
127148.77/17166.59	% SZS status Ended for HL406950+5.p
127163.18/17168.44	% SZS status Started for HL406951+5.p
127163.18/17168.44	% SZS status GaveUp for HL406951+5.p
127163.18/17168.44	eprover: CPU time limit exceeded, terminating
127163.18/17168.44	% SZS status Ended for HL406951+5.p
127181.42/17170.64	% SZS status Started for HL406952+4.p
127181.42/17170.64	% SZS status GaveUp for HL406952+4.p
127181.42/17170.64	eprover: CPU time limit exceeded, terminating
127181.42/17170.64	% SZS status Ended for HL406952+4.p
127194.23/17172.27	% SZS status Started for HL406953+4.p
127194.23/17172.27	% SZS status GaveUp for HL406953+4.p
127194.23/17172.27	eprover: CPU time limit exceeded, terminating
127194.23/17172.27	% SZS status Ended for HL406953+4.p
127209.84/17174.25	% SZS status Started for HL406944+5.p
127209.84/17174.25	% SZS status GaveUp for HL406944+5.p
127209.84/17174.25	eprover: CPU time limit exceeded, terminating
127209.84/17174.25	% SZS status Ended for HL406944+5.p
127222.85/17175.83	% SZS status Started for HL406954+4.p
127222.85/17175.83	% SZS status GaveUp for HL406954+4.p
127222.85/17175.83	eprover: CPU time limit exceeded, terminating
127222.85/17175.83	% SZS status Ended for HL406954+4.p
127250.78/17179.39	% SZS status Started for HL406955+4.p
127250.78/17179.39	% SZS status GaveUp for HL406955+4.p
127250.78/17179.39	eprover: CPU time limit exceeded, terminating
127250.78/17179.39	% SZS status Ended for HL406955+4.p
127281.26/17183.18	% SZS status Started for HL406956+4.p
127281.26/17183.18	% SZS status GaveUp for HL406956+4.p
127281.26/17183.18	eprover: CPU time limit exceeded, terminating
127281.26/17183.18	% SZS status Ended for HL406956+4.p
127299.29/17185.45	% SZS status Started for HL406952+5.p
127299.29/17185.45	% SZS status GaveUp for HL406952+5.p
127299.29/17185.45	eprover: CPU time limit exceeded, terminating
127299.29/17185.45	% SZS status Ended for HL406952+5.p
127308.91/17186.75	% SZS status Started for HL406957+4.p
127308.91/17186.75	% SZS status GaveUp for HL406957+4.p
127308.91/17186.75	eprover: CPU time limit exceeded, terminating
127308.91/17186.75	% SZS status Ended for HL406957+4.p
127330.60/17189.48	% SZS status Started for HL406953+5.p
127330.60/17189.48	% SZS status GaveUp for HL406953+5.p
127330.60/17189.48	eprover: CPU time limit exceeded, terminating
127330.60/17189.48	% SZS status Ended for HL406953+5.p
127332.66/17189.66	% SZS status Started for HL406957+5.p
127332.66/17189.66	% SZS status GaveUp for HL406957+5.p
127332.66/17189.66	eprover: CPU time limit exceeded, terminating
127332.66/17189.66	% SZS status Ended for HL406957+5.p
127352.95/17192.23	% SZS status Started for HL406954+5.p
127352.95/17192.23	% SZS status GaveUp for HL406954+5.p
127352.95/17192.23	eprover: CPU time limit exceeded, terminating
127352.95/17192.23	% SZS status Ended for HL406954+5.p
127367.84/17194.12	% SZS status Started for HL406958+4.p
127367.84/17194.12	% SZS status GaveUp for HL406958+4.p
127367.84/17194.12	eprover: CPU time limit exceeded, terminating
127367.84/17194.12	% SZS status Ended for HL406958+4.p
127385.44/17196.34	% SZS status Started for HL406955+5.p
127385.44/17196.34	% SZS status GaveUp for HL406955+5.p
127385.44/17196.34	eprover: CPU time limit exceeded, terminating
127385.44/17196.34	% SZS status Ended for HL406955+5.p
127396.57/17197.71	% SZS status Started for HL406960+4.p
127396.57/17197.71	% SZS status GaveUp for HL406960+4.p
127396.57/17197.71	eprover: CPU time limit exceeded, terminating
127396.57/17197.71	% SZS status Ended for HL406960+4.p
127416.40/17200.23	% SZS status Started for HL406956+5.p
127416.40/17200.23	% SZS status GaveUp for HL406956+5.p
127416.40/17200.23	eprover: CPU time limit exceeded, terminating
127416.40/17200.23	% SZS status Ended for HL406956+5.p
127421.21/17200.82	% SZS status Started for HL406961+4.p
127421.21/17200.82	% SZS status GaveUp for HL406961+4.p
127421.21/17200.82	eprover: CPU time limit exceeded, terminating
127421.21/17200.82	% SZS status Ended for HL406961+4.p
127456.36/17205.23	% SZS status Started for HL406962+4.p
127456.36/17205.23	% SZS status GaveUp for HL406962+4.p
127456.36/17205.23	eprover: CPU time limit exceeded, terminating
127456.36/17205.23	% SZS status Ended for HL406962+4.p
127483.05/17208.61	% SZS status Started for HL406963+4.p
127483.05/17208.61	% SZS status GaveUp for HL406963+4.p
127483.05/17208.61	eprover: CPU time limit exceeded, terminating
127483.05/17208.61	% SZS status Ended for HL406963+4.p
127505.16/17211.39	% SZS status Started for HL406958+5.p
127505.16/17211.39	% SZS status GaveUp for HL406958+5.p
127505.16/17211.39	eprover: CPU time limit exceeded, terminating
127505.16/17211.39	% SZS status Ended for HL406958+5.p
127507.62/17211.66	% SZS status Started for HL406965+4.p
127507.62/17211.66	% SZS status GaveUp for HL406965+4.p
127507.62/17211.66	eprover: CPU time limit exceeded, terminating
127507.62/17211.66	% SZS status Ended for HL406965+4.p
127508.30/17211.75	% SZS status Started for HL406964+4.p
127508.30/17211.75	% SZS status GaveUp for HL406964+4.p
127508.30/17211.75	eprover: CPU time limit exceeded, terminating
127508.30/17211.75	% SZS status Ended for HL406964+4.p
127535.21/17215.18	% SZS status Started for HL406960+5.p
127535.21/17215.18	% SZS status GaveUp for HL406960+5.p
127535.21/17215.18	eprover: CPU time limit exceeded, terminating
127535.21/17215.18	% SZS status Ended for HL406960+5.p
127558.12/17218.06	% SZS status Started for HL406961+5.p
127558.12/17218.06	% SZS status GaveUp for HL406961+5.p
127558.12/17218.06	eprover: CPU time limit exceeded, terminating
127558.12/17218.06	% SZS status Ended for HL406961+5.p
127591.40/17222.29	% SZS status Started for HL406962+5.p
127591.40/17222.29	% SZS status GaveUp for HL406962+5.p
127591.40/17222.29	eprover: CPU time limit exceeded, terminating
127591.40/17222.29	% SZS status Ended for HL406962+5.p
127593.88/17222.57	% SZS status Started for HL406966+4.p
127593.88/17222.57	% SZS status GaveUp for HL406966+4.p
127593.88/17222.57	eprover: CPU time limit exceeded, terminating
127593.88/17222.57	% SZS status Ended for HL406966+4.p
127620.20/17225.90	% SZS status Started for HL406963+5.p
127620.20/17225.90	% SZS status GaveUp for HL406963+5.p
127620.20/17225.90	eprover: CPU time limit exceeded, terminating
127620.20/17225.90	% SZS status Ended for HL406963+5.p
127621.58/17226.09	% SZS status Started for HL406968+4.p
127621.58/17226.09	% SZS status GaveUp for HL406968+4.p
127621.58/17226.09	eprover: CPU time limit exceeded, terminating
127621.58/17226.09	% SZS status Ended for HL406968+4.p
127644.91/17228.96	% SZS status Started for HL406970+4.p
127644.91/17228.96	% SZS status GaveUp for HL406970+4.p
127644.91/17228.96	eprover: CPU time limit exceeded, terminating
127644.91/17228.96	% SZS status Ended for HL406970+4.p
127661.48/17231.12	% SZS status Started for HL406964+5.p
127661.48/17231.12	% SZS status GaveUp for HL406964+5.p
127661.48/17231.12	eprover: CPU time limit exceeded, terminating
127661.48/17231.12	% SZS status Ended for HL406964+5.p
127678.30/17233.27	% SZS status Started for HL406969+4.p
127678.30/17233.27	% SZS status GaveUp for HL406969+4.p
127678.30/17233.27	eprover: CPU time limit exceeded, terminating
127678.30/17233.27	% SZS status Ended for HL406969+4.p
127713.21/17237.57	% SZS status Started for HL406966+5.p
127713.21/17237.57	% SZS status GaveUp for HL406966+5.p
127713.21/17237.57	eprover: CPU time limit exceeded, terminating
127713.21/17237.57	% SZS status Ended for HL406966+5.p
127713.21/17237.62	% SZS status Started for HL406965+5.p
127713.21/17237.62	% SZS status GaveUp for HL406965+5.p
127713.21/17237.62	eprover: CPU time limit exceeded, terminating
127713.21/17237.62	% SZS status Ended for HL406965+5.p
127732.41/17240.00	% SZS status Started for HL406971+4.p
127732.41/17240.00	% SZS status GaveUp for HL406971+4.p
127732.41/17240.00	eprover: CPU time limit exceeded, terminating
127732.41/17240.00	% SZS status Ended for HL406971+4.p
127763.27/17243.95	% SZS status Started for HL406968+5.p
127763.27/17243.95	% SZS status GaveUp for HL406968+5.p
127763.27/17243.95	eprover: CPU time limit exceeded, terminating
127763.27/17243.95	% SZS status Ended for HL406968+5.p
127765.85/17244.29	% SZS status Started for HL406972+4.p
127765.85/17244.29	% SZS status GaveUp for HL406972+4.p
127765.85/17244.29	eprover: CPU time limit exceeded, terminating
127765.85/17244.29	% SZS status Ended for HL406972+4.p
127798.60/17248.38	% SZS status Started for HL406969+5.p
127798.60/17248.38	% SZS status GaveUp for HL406969+5.p
127798.60/17248.38	eprover: CPU time limit exceeded, terminating
127798.60/17248.38	% SZS status Ended for HL406969+5.p
127801.59/17248.72	% SZS status Started for HL406973+4.p
127801.59/17248.72	% SZS status GaveUp for HL406973+4.p
127801.59/17248.72	eprover: CPU time limit exceeded, terminating
127801.59/17248.72	% SZS status Ended for HL406973+4.p
127823.06/17251.44	% SZS status Started for HL406976+4.p
127823.06/17251.44	% SZS status GaveUp for HL406976+4.p
127823.06/17251.44	eprover: CPU time limit exceeded, terminating
127823.06/17251.44	% SZS status Ended for HL406976+4.p
127827.88/17252.08	% SZS status Started for HL406970+5.p
127827.88/17252.08	% SZS status GaveUp for HL406970+5.p
127827.88/17252.08	eprover: CPU time limit exceeded, terminating
127827.88/17252.08	% SZS status Ended for HL406970+5.p
127851.59/17255.07	% SZS status Started for HL406975+4.p
127851.59/17255.07	% SZS status GaveUp for HL406975+4.p
127851.59/17255.07	eprover: CPU time limit exceeded, terminating
127851.59/17255.07	% SZS status Ended for HL406975+4.p
127868.30/17257.20	% SZS status Started for HL406971+5.p
127868.30/17257.20	% SZS status GaveUp for HL406971+5.p
127868.30/17257.20	eprover: CPU time limit exceeded, terminating
127868.30/17257.20	% SZS status Ended for HL406971+5.p
127909.53/17262.39	% SZS status Started for HL406977+4.p
127909.53/17262.39	% SZS status GaveUp for HL406977+4.p
127909.53/17262.39	eprover: CPU time limit exceeded, terminating
127909.53/17262.39	% SZS status Ended for HL406977+4.p
127917.66/17263.38	% SZS status Started for HL406972+5.p
127917.66/17263.38	% SZS status GaveUp for HL406972+5.p
127917.66/17263.38	eprover: CPU time limit exceeded, terminating
127917.66/17263.38	% SZS status Ended for HL406972+5.p
127936.12/17265.72	% SZS status Started for HL406973+5.p
127936.12/17265.72	% SZS status GaveUp for HL406973+5.p
127936.12/17265.72	eprover: CPU time limit exceeded, terminating
127936.12/17265.72	% SZS status Ended for HL406973+5.p
127939.12/17266.07	% SZS status Started for HL406978+4.p
127939.12/17266.07	% SZS status GaveUp for HL406978+4.p
127939.12/17266.07	eprover: CPU time limit exceeded, terminating
127939.12/17266.07	% SZS status Ended for HL406978+4.p
127969.75/17269.99	% SZS status Started for HL406975+5.p
127969.75/17269.99	% SZS status GaveUp for HL406975+5.p
127969.75/17269.99	eprover: CPU time limit exceeded, terminating
127969.75/17269.99	% SZS status Ended for HL406975+5.p
127997.78/17273.42	% SZS status Started for HL406979+4.p
127997.78/17273.42	% SZS status GaveUp for HL406979+4.p
127997.78/17273.42	eprover: CPU time limit exceeded, terminating
127997.78/17273.42	% SZS status Ended for HL406979+4.p
128001.30/17274.12	% SZS status Started for HL406981+4.p
128001.30/17274.12	% SZS status GaveUp for HL406981+4.p
128001.30/17274.12	eprover: CPU time limit exceeded, terminating
128001.30/17274.12	% SZS status Ended for HL406981+4.p
128006.94/17274.67	% SZS status Started for HL406976+5.p
128006.94/17274.67	% SZS status GaveUp for HL406976+5.p
128006.94/17274.67	eprover: CPU time limit exceeded, terminating
128006.94/17274.67	% SZS status Ended for HL406976+5.p
128024.05/17276.77	% SZS status Started for HL406980+4.p
128024.05/17276.77	% SZS status GaveUp for HL406980+4.p
128024.05/17276.77	eprover: CPU time limit exceeded, terminating
128024.05/17276.77	% SZS status Ended for HL406980+4.p
128027.14/17277.17	% SZS status Started for HL406983+4.p
128027.14/17277.17	% SZS status GaveUp for HL406983+4.p
128027.14/17277.17	eprover: CPU time limit exceeded, terminating
128027.14/17277.17	% SZS status Ended for HL406983+4.p
128036.30/17278.36	% SZS status Started for HL406977+5.p
128036.30/17278.36	% SZS status GaveUp for HL406977+5.p
128036.30/17278.36	eprover: CPU time limit exceeded, terminating
128036.30/17278.36	% SZS status Ended for HL406977+5.p
128072.71/17283.01	% SZS status Started for HL406978+5.p
128072.71/17283.01	% SZS status GaveUp for HL406978+5.p
128072.71/17283.01	eprover: CPU time limit exceeded, terminating
128072.71/17283.01	% SZS status Ended for HL406978+5.p
128111.71/17287.79	% SZS status Started for HL406984+4.p
128111.71/17287.79	% SZS status GaveUp for HL406984+4.p
128111.71/17287.79	eprover: CPU time limit exceeded, terminating
128111.71/17287.79	% SZS status Ended for HL406984+4.p
128124.14/17289.33	% SZS status Started for HL406985+4.p
128124.14/17289.33	% SZS status GaveUp for HL406985+4.p
128124.14/17289.33	eprover: CPU time limit exceeded, terminating
128124.14/17289.33	% SZS status Ended for HL406985+4.p
128124.67/17289.45	% SZS status Started for HL406979+5.p
128124.67/17289.45	% SZS status GaveUp for HL406979+5.p
128124.67/17289.45	eprover: CPU time limit exceeded, terminating
128124.67/17289.45	% SZS status Ended for HL406979+5.p
128144.26/17291.98	% SZS status Started for HL406980+5.p
128144.26/17291.98	% SZS status GaveUp for HL406980+5.p
128144.26/17291.98	eprover: CPU time limit exceeded, terminating
128144.26/17291.98	% SZS status Ended for HL406980+5.p
128149.10/17292.55	% SZS status Started for HL406987+4.p
128149.10/17292.55	% SZS status GaveUp for HL406987+4.p
128149.10/17292.55	eprover: CPU time limit exceeded, terminating
128149.10/17292.55	% SZS status Ended for HL406987+4.p
128176.36/17296.01	% SZS status Started for HL406986+4.p
128176.36/17296.01	% SZS status GaveUp for HL406986+4.p
128176.36/17296.01	eprover: CPU time limit exceeded, terminating
128176.36/17296.01	% SZS status Ended for HL406986+4.p
128203.10/17299.29	% SZS status Started for HL406981+5.p
128203.10/17299.29	% SZS status GaveUp for HL406981+5.p
128203.10/17299.29	eprover: CPU time limit exceeded, terminating
128203.10/17299.29	% SZS status Ended for HL406981+5.p
128213.38/17300.58	% SZS status Started for HL406983+5.p
128213.38/17300.58	% SZS status GaveUp for HL406983+5.p
128213.38/17300.58	eprover: CPU time limit exceeded, terminating
128213.38/17300.58	% SZS status Ended for HL406983+5.p
128233.10/17303.07	% SZS status Started for HL406984+5.p
128233.10/17303.07	% SZS status GaveUp for HL406984+5.p
128233.10/17303.07	eprover: CPU time limit exceeded, terminating
128233.10/17303.07	% SZS status Ended for HL406984+5.p
128236.31/17303.54	% SZS status Started for HL406988+4.p
128236.31/17303.54	% SZS status GaveUp for HL406988+4.p
128236.31/17303.54	eprover: CPU time limit exceeded, terminating
128236.31/17303.54	% SZS status Ended for HL406988+4.p
128278.73/17308.86	% SZS status Started for HL406985+5.p
128278.73/17308.86	% SZS status GaveUp for HL406985+5.p
128278.73/17308.86	eprover: CPU time limit exceeded, terminating
128278.73/17308.86	% SZS status Ended for HL406985+5.p
128290.94/17310.37	% SZS status Started for HL406989+4.p
128290.94/17310.37	% SZS status GaveUp for HL406989+4.p
128290.94/17310.37	eprover: CPU time limit exceeded, terminating
128290.94/17310.37	% SZS status Ended for HL406989+4.p
128320.55/17314.06	% SZS status Started for HL406991+4.p
128320.55/17314.06	% SZS status GaveUp for HL406991+4.p
128320.55/17314.06	eprover: CPU time limit exceeded, terminating
128320.55/17314.06	% SZS status Ended for HL406991+4.p
128328.93/17315.14	% SZS status Started for HL406986+5.p
128328.93/17315.14	% SZS status GaveUp for HL406986+5.p
128328.93/17315.14	eprover: CPU time limit exceeded, terminating
128328.93/17315.14	% SZS status Ended for HL406986+5.p
128349.19/17317.65	% SZS status Started for HL406987+5.p
128349.19/17317.65	% SZS status GaveUp for HL406987+5.p
128349.19/17317.65	eprover: CPU time limit exceeded, terminating
128349.19/17317.65	% SZS status Ended for HL406987+5.p
128367.39/17320.00	% SZS status Started for HL406992+4.p
128367.39/17320.00	% SZS status GaveUp for HL406992+4.p
128367.39/17320.00	eprover: CPU time limit exceeded, terminating
128367.39/17320.00	% SZS status Ended for HL406992+4.p
128382.25/17321.82	% SZS status Started for HL406988+5.p
128382.25/17321.82	% SZS status GaveUp for HL406988+5.p
128382.25/17321.82	eprover: CPU time limit exceeded, terminating
128382.25/17321.82	% SZS status Ended for HL406988+5.p
128407.27/17325.15	% SZS status Started for HL406993+4.p
128407.27/17325.15	% SZS status GaveUp for HL406993+4.p
128407.27/17325.15	eprover: CPU time limit exceeded, terminating
128407.27/17325.15	% SZS status Ended for HL406993+4.p
128417.81/17326.34	% SZS status Started for HL406989+5.p
128417.81/17326.34	% SZS status GaveUp for HL406989+5.p
128417.81/17326.34	eprover: CPU time limit exceeded, terminating
128417.81/17326.34	% SZS status Ended for HL406989+5.p
128436.33/17328.60	% SZS status Started for HL406994+4.p
128436.33/17328.60	% SZS status GaveUp for HL406994+4.p
128436.33/17328.60	eprover: CPU time limit exceeded, terminating
128436.33/17328.60	% SZS status Ended for HL406994+4.p
128443.16/17329.52	% SZS status Started for HL406991+5.p
128443.16/17329.52	% SZS status GaveUp for HL406991+5.p
128443.16/17329.52	eprover: CPU time limit exceeded, terminating
128443.16/17329.52	% SZS status Ended for HL406991+5.p
128470.25/17332.92	% SZS status Started for HL406995+4.p
128470.25/17332.92	% SZS status GaveUp for HL406995+4.p
128470.25/17332.92	eprover: CPU time limit exceeded, terminating
128470.25/17332.92	% SZS status Ended for HL406995+4.p
128497.48/17336.37	% SZS status Started for HL406992+5.p
128497.48/17336.37	% SZS status GaveUp for HL406992+5.p
128497.48/17336.37	eprover: CPU time limit exceeded, terminating
128497.48/17336.37	% SZS status Ended for HL406992+5.p
128504.95/17337.28	% SZS status Started for HL406997+4.p
128504.95/17337.28	% SZS status GaveUp for HL406997+4.p
128504.95/17337.28	eprover: CPU time limit exceeded, terminating
128504.95/17337.28	% SZS status Ended for HL406997+4.p
128530.34/17340.55	% SZS status Started for HL406998+4.p
128530.34/17340.55	% SZS status GaveUp for HL406998+4.p
128530.34/17340.55	eprover: CPU time limit exceeded, terminating
128530.34/17340.55	% SZS status Ended for HL406998+4.p
128533.66/17340.92	% SZS status Started for HL406993+5.p
128533.66/17340.92	% SZS status GaveUp for HL406993+5.p
128533.66/17340.92	eprover: CPU time limit exceeded, terminating
128533.66/17340.92	% SZS status Ended for HL406993+5.p
128573.67/17345.99	% SZS status Started for HL406994+5.p
128573.67/17345.99	% SZS status GaveUp for HL406994+5.p
128573.67/17345.99	eprover: CPU time limit exceeded, terminating
128573.67/17345.99	% SZS status Ended for HL406994+5.p
128585.03/17347.41	% SZS status Started for HL407000+4.p
128585.03/17347.41	% SZS status GaveUp for HL407000+4.p
128585.03/17347.41	eprover: CPU time limit exceeded, terminating
128585.03/17347.41	% SZS status Ended for HL407000+4.p
128614.12/17351.06	% SZS status Started for HL406995+5.p
128614.12/17351.06	% SZS status GaveUp for HL406995+5.p
128614.12/17351.06	eprover: CPU time limit exceeded, terminating
128614.12/17351.06	% SZS status Ended for HL406995+5.p
128618.45/17351.57	% SZS status Started for HL407001+4.p
128618.45/17351.57	% SZS status GaveUp for HL407001+4.p
128618.45/17351.57	eprover: CPU time limit exceeded, terminating
128618.45/17351.57	% SZS status Ended for HL407001+4.p
128638.61/17354.15	% SZS status Started for HL407003+4.p
128638.61/17354.15	% SZS status GaveUp for HL407003+4.p
128638.61/17354.15	eprover: CPU time limit exceeded, terminating
128638.61/17354.15	% SZS status Ended for HL407003+4.p
128643.61/17354.75	% SZS status Started for HL406997+5.p
128643.61/17354.75	% SZS status GaveUp for HL406997+5.p
128643.61/17354.75	eprover: CPU time limit exceeded, terminating
128643.61/17354.75	% SZS status Ended for HL406997+5.p
128661.52/17357.04	% SZS status Started for HL407002+4.p
128661.52/17357.04	% SZS status GaveUp for HL407002+4.p
128661.52/17357.04	eprover: CPU time limit exceeded, terminating
128661.52/17357.04	% SZS status Ended for HL407002+4.p
128662.65/17357.24	% SZS status Started for HL407005+4.p
128662.65/17357.24	% SZS status GaveUp for HL407005+4.p
128662.65/17357.24	eprover: CPU time limit exceeded, terminating
128662.65/17357.24	% SZS status Ended for HL407005+4.p
128674.64/17358.71	% SZS status Started for HL406998+5.p
128674.64/17358.71	% SZS status GaveUp for HL406998+5.p
128674.64/17358.71	eprover: CPU time limit exceeded, terminating
128674.64/17358.71	% SZS status Ended for HL406998+5.p
128709.62/17363.09	% SZS status Started for HL407000+5.p
128709.62/17363.09	% SZS status GaveUp for HL407000+5.p
128709.62/17363.09	eprover: CPU time limit exceeded, terminating
128709.62/17363.09	% SZS status Ended for HL407000+5.p
128738.18/17366.65	% SZS status Started for HL407001+5.p
128738.18/17366.65	% SZS status GaveUp for HL407001+5.p
128738.18/17366.65	eprover: CPU time limit exceeded, terminating
128738.18/17366.65	% SZS status Ended for HL407001+5.p
128749.05/17368.04	% SZS status Started for HL407007+4.p
128749.05/17368.04	% SZS status GaveUp for HL407007+4.p
128749.05/17368.04	eprover: CPU time limit exceeded, terminating
128749.05/17368.04	% SZS status Ended for HL407007+4.p
128762.14/17369.66	% SZS status Started for HL407008+4.p
128762.14/17369.66	% SZS status GaveUp for HL407008+4.p
128762.14/17369.66	eprover: CPU time limit exceeded, terminating
128762.14/17369.66	% SZS status Ended for HL407008+4.p
128789.88/17373.15	% SZS status Started for HL407002+5.p
128789.88/17373.15	% SZS status GaveUp for HL407002+5.p
128789.88/17373.15	eprover: CPU time limit exceeded, terminating
128789.88/17373.15	% SZS status Ended for HL407002+5.p
128823.82/17377.48	% SZS status Started for HL407003+5.p
128823.82/17377.48	% SZS status GaveUp for HL407003+5.p
128823.82/17377.48	eprover: CPU time limit exceeded, terminating
128823.82/17377.48	% SZS status Ended for HL407003+5.p
128824.52/17377.57	% SZS status Started for HL407009+4.p
128824.52/17377.57	% SZS status GaveUp for HL407009+4.p
128824.52/17377.57	eprover: CPU time limit exceeded, terminating
128824.52/17377.57	% SZS status Ended for HL407009+4.p
128848.46/17380.57	% SZS status Started for HL407011+4.p
128848.46/17380.57	% SZS status GaveUp for HL407011+4.p
128848.46/17380.57	eprover: CPU time limit exceeded, terminating
128848.46/17380.57	% SZS status Ended for HL407011+4.p
128849.02/17380.66	% SZS status Started for HL407010+4.p
128849.02/17380.66	% SZS status GaveUp for HL407010+4.p
128849.02/17380.66	eprover: CPU time limit exceeded, terminating
128849.02/17380.66	% SZS status Ended for HL407010+4.p
128849.77/17380.71	% SZS status Started for HL407005+5.p
128849.77/17380.71	% SZS status GaveUp for HL407005+5.p
128849.77/17380.71	eprover: CPU time limit exceeded, terminating
128849.77/17380.71	% SZS status Ended for HL407005+5.p
128868.27/17383.03	% SZS status Started for HL407007+5.p
128868.27/17383.03	% SZS status GaveUp for HL407007+5.p
128868.27/17383.03	eprover: CPU time limit exceeded, terminating
128868.27/17383.03	% SZS status Ended for HL407007+5.p
128913.15/17388.95	% SZS status Started for HL407008+5.p
128913.15/17388.95	% SZS status GaveUp for HL407008+5.p
128913.15/17388.95	eprover: CPU time limit exceeded, terminating
128913.15/17388.95	% SZS status Ended for HL407008+5.p
128936.27/17391.62	% SZS status Started for HL407013+4.p
128936.27/17391.62	% SZS status GaveUp for HL407013+4.p
128936.27/17391.62	eprover: CPU time limit exceeded, terminating
128936.27/17391.62	% SZS status Ended for HL407013+4.p
128936.91/17391.68	% SZS status Started for HL407012+4.p
128936.91/17391.68	% SZS status GaveUp for HL407012+4.p
128936.91/17391.68	eprover: CPU time limit exceeded, terminating
128936.91/17391.68	% SZS status Ended for HL407012+4.p
128956.29/17394.10	% SZS status Started for HL407009+5.p
128956.29/17394.10	% SZS status GaveUp for HL407009+5.p
128956.29/17394.10	eprover: CPU time limit exceeded, terminating
128956.29/17394.10	% SZS status Ended for HL407009+5.p
128993.86/17398.88	% SZS status Started for HL407010+5.p
128993.86/17398.88	% SZS status GaveUp for HL407010+5.p
128993.86/17398.88	eprover: CPU time limit exceeded, terminating
128993.86/17398.88	% SZS status Ended for HL407010+5.p
129002.48/17399.94	% SZS status Started for HL407014+4.p
129002.48/17399.94	% SZS status GaveUp for HL407014+4.p
129002.48/17399.94	eprover: CPU time limit exceeded, terminating
129002.48/17399.94	% SZS status Ended for HL407014+4.p
129018.03/17401.95	% SZS status Started for HL407016+4.p
129018.03/17401.95	% SZS status GaveUp for HL407016+4.p
129018.03/17401.95	eprover: CPU time limit exceeded, terminating
129018.03/17401.95	% SZS status Ended for HL407016+4.p
129024.84/17402.77	% SZS status Started for HL407015+4.p
129024.84/17402.77	% SZS status GaveUp for HL407015+4.p
129024.84/17402.77	eprover: CPU time limit exceeded, terminating
129024.84/17402.77	% SZS status Ended for HL407015+4.p
129031.62/17403.67	% SZS status Started for HL407011+5.p
129031.62/17403.67	% SZS status GaveUp for HL407011+5.p
129031.62/17403.67	eprover: CPU time limit exceeded, terminating
129031.62/17403.67	% SZS status Ended for HL407011+5.p
129078.45/17406.40	% SZS status Started for HL407012+5.p
129078.45/17406.40	% SZS status GaveUp for HL407012+5.p
129078.45/17406.40	eprover: CPU time limit exceeded, terminating
129078.45/17406.40	% SZS status Ended for HL407012+5.p
129097.20/17408.86	% SZS status Started for HL407013+5.p
129097.20/17408.86	% SZS status GaveUp for HL407013+5.p
129097.20/17408.86	eprover: CPU time limit exceeded, terminating
129097.20/17408.86	% SZS status Ended for HL407013+5.p
129110.54/17410.39	% SZS status Started for HL407016+5.p
129110.54/17410.39	% SZS status GaveUp for HL407016+5.p
129110.54/17410.39	eprover: CPU time limit exceeded, terminating
129110.54/17410.39	% SZS status Ended for HL407016+5.p
129130.14/17412.97	% SZS status Started for HL407017+4.p
129130.14/17412.97	% SZS status GaveUp for HL407017+4.p
129130.14/17412.97	eprover: CPU time limit exceeded, terminating
129130.14/17412.97	% SZS status Ended for HL407017+4.p
129144.63/17414.73	% SZS status Started for HL407018+4.p
129144.63/17414.73	% SZS status GaveUp for HL407018+4.p
129144.63/17414.73	eprover: CPU time limit exceeded, terminating
129144.63/17414.73	% SZS status Ended for HL407018+4.p
129163.61/17417.26	% SZS status Started for HL407014+5.p
129163.61/17417.26	% SZS status GaveUp for HL407014+5.p
129163.61/17417.26	eprover: CPU time limit exceeded, terminating
129163.61/17417.26	% SZS status Ended for HL407014+5.p
129186.19/17420.02	% SZS status Started for HL407021+4.p
129186.19/17420.02	% SZS status GaveUp for HL407021+4.p
129186.19/17420.02	eprover: CPU time limit exceeded, terminating
129186.19/17420.02	% SZS status Ended for HL407021+4.p
129186.19/17420.05	% SZS status Started for HL407015+5.p
129186.19/17420.05	% SZS status GaveUp for HL407015+5.p
129186.19/17420.05	eprover: CPU time limit exceeded, terminating
129186.19/17420.05	% SZS status Ended for HL407015+5.p
129218.36/17424.00	% SZS status Started for HL407023+4.p
129218.36/17424.00	% SZS status GaveUp for HL407023+4.p
129218.36/17424.00	eprover: CPU time limit exceeded, terminating
129218.36/17424.00	% SZS status Ended for HL407023+4.p
129253.24/17428.38	% SZS status Started for HL407024+4.p
129253.24/17428.38	% SZS status GaveUp for HL407024+4.p
129253.24/17428.38	eprover: CPU time limit exceeded, terminating
129253.24/17428.38	% SZS status Ended for HL407024+4.p
129253.59/17428.44	% SZS status Started for HL407017+5.p
129253.59/17428.44	% SZS status GaveUp for HL407017+5.p
129253.59/17428.44	eprover: CPU time limit exceeded, terminating
129253.59/17428.44	% SZS status Ended for HL407017+5.p
129276.16/17431.31	% SZS status Started for HL407025+4.p
129276.16/17431.31	% SZS status GaveUp for HL407025+4.p
129276.16/17431.31	eprover: CPU time limit exceeded, terminating
129276.16/17431.31	% SZS status Ended for HL407025+4.p
129283.80/17432.26	% SZS status Started for HL407018+5.p
129283.80/17432.26	% SZS status GaveUp for HL407018+5.p
129283.80/17432.26	eprover: CPU time limit exceeded, terminating
129283.80/17432.26	% SZS status Ended for HL407018+5.p
129314.92/17436.13	% SZS status Started for HL407021+5.p
129314.92/17436.13	% SZS status GaveUp for HL407021+5.p
129314.92/17436.13	eprover: CPU time limit exceeded, terminating
129314.92/17436.13	% SZS status Ended for HL407021+5.p
129339.85/17439.34	% SZS status Started for HL407026+4.p
129339.85/17439.34	% SZS status GaveUp for HL407026+4.p
129339.85/17439.34	eprover: CPU time limit exceeded, terminating
129339.85/17439.34	% SZS status Ended for HL407026+4.p
129351.45/17440.70	% SZS status Started for HL407023+5.p
129351.45/17440.70	% SZS status GaveUp for HL407023+5.p
129351.45/17440.70	eprover: CPU time limit exceeded, terminating
129351.45/17440.70	% SZS status Ended for HL407023+5.p
129363.39/17442.25	% SZS status Started for HL407027+4.p
129363.39/17442.25	% SZS status GaveUp for HL407027+4.p
129363.39/17442.25	eprover: CPU time limit exceeded, terminating
129363.39/17442.25	% SZS status Ended for HL407027+4.p
129391.75/17445.87	% SZS status Started for HL407024+5.p
129391.75/17445.87	% SZS status GaveUp for HL407024+5.p
129391.75/17445.87	eprover: CPU time limit exceeded, terminating
129391.75/17445.87	% SZS status Ended for HL407024+5.p
129402.61/17447.15	% SZS status Started for HL407028+4.p
129402.61/17447.15	% SZS status GaveUp for HL407028+4.p
129402.61/17447.15	eprover: CPU time limit exceeded, terminating
129402.61/17447.15	% SZS status Ended for HL407028+4.p
129415.71/17448.92	% SZS status Started for HL407030+4.p
129415.71/17448.92	% SZS status GaveUp for HL407030+4.p
129415.71/17448.92	eprover: CPU time limit exceeded, terminating
129415.71/17448.92	% SZS status Ended for HL407030+4.p
129421.63/17449.69	% SZS status Started for HL407025+5.p
129421.63/17449.69	% SZS status GaveUp for HL407025+5.p
129421.63/17449.69	eprover: CPU time limit exceeded, terminating
129421.63/17449.69	% SZS status Ended for HL407025+5.p
129436.39/17451.60	% SZS status Started for HL407029+4.p
129436.39/17451.60	% SZS status GaveUp for HL407029+4.p
129436.39/17451.60	eprover: CPU time limit exceeded, terminating
129436.39/17451.60	% SZS status Ended for HL407029+4.p
129439.95/17452.06	% SZS status Started for HL407031+4.p
129439.95/17452.06	% SZS status GaveUp for HL407031+4.p
129439.95/17452.06	eprover: CPU time limit exceeded, terminating
129439.95/17452.06	% SZS status Ended for HL407031+4.p
129458.07/17454.28	% SZS status Started for HL407026+5.p
129458.07/17454.28	% SZS status GaveUp for HL407026+5.p
129458.07/17454.28	eprover: CPU time limit exceeded, terminating
129458.07/17454.28	% SZS status Ended for HL407026+5.p
129460.61/17454.64	% SZS status Started for HL407032+4.p
129460.61/17454.64	% SZS status GaveUp for HL407032+4.p
129460.61/17454.64	eprover: CPU time limit exceeded, terminating
129460.61/17454.64	% SZS status Ended for HL407032+4.p
129483.74/17457.48	% SZS status Started for HL407033+4.p
129483.74/17457.48	% SZS status GaveUp for HL407033+4.p
129483.74/17457.48	eprover: CPU time limit exceeded, terminating
129483.74/17457.48	% SZS status Ended for HL407033+4.p
129487.30/17457.92	% SZS status Started for HL407030+5.p
129487.30/17457.92	% SZS status GaveUp for HL407030+5.p
129487.30/17457.92	eprover: CPU time limit exceeded, terminating
129487.30/17457.92	% SZS status Ended for HL407030+5.p
129487.30/17457.94	% SZS status Started for HL407027+5.p
129487.30/17457.94	% SZS status GaveUp for HL407027+5.p
129487.30/17457.94	eprover: CPU time limit exceeded, terminating
129487.30/17457.94	% SZS status Ended for HL407027+5.p
129504.33/17460.08	% SZS status Started for HL407031+5.p
129504.33/17460.08	% SZS status GaveUp for HL407031+5.p
129504.33/17460.08	eprover: CPU time limit exceeded, terminating
129504.33/17460.08	% SZS status Ended for HL407031+5.p
129507.89/17460.55	% SZS status Started for HL407034+4.p
129507.89/17460.55	% SZS status GaveUp for HL407034+4.p
129507.89/17460.55	eprover: CPU time limit exceeded, terminating
129507.89/17460.55	% SZS status Ended for HL407034+4.p
129511.60/17460.98	% SZS status Started for HL407035+4.p
129511.60/17460.98	% SZS status GaveUp for HL407035+4.p
129511.60/17460.98	eprover: CPU time limit exceeded, terminating
129511.60/17460.98	% SZS status Ended for HL407035+4.p
129522.60/17462.57	% SZS status Started for HL407032+5.p
129522.60/17462.57	% SZS status GaveUp for HL407032+5.p
129522.60/17462.57	eprover: CPU time limit exceeded, terminating
129522.60/17462.57	% SZS status Ended for HL407032+5.p
129531.05/17463.58	% SZS status Started for HL407036+4.p
129531.05/17463.58	% SZS status GaveUp for HL407036+4.p
129531.05/17463.58	eprover: CPU time limit exceeded, terminating
129531.05/17463.58	% SZS status Ended for HL407036+4.p
129546.22/17465.44	% SZS status Started for HL407033+5.p
129546.22/17465.44	% SZS status GaveUp for HL407033+5.p
129546.22/17465.44	eprover: CPU time limit exceeded, terminating
129546.22/17465.44	% SZS status Ended for HL407033+5.p
129548.44/17465.60	% SZS status Started for HL407037+4.p
129548.44/17465.60	% SZS status GaveUp for HL407037+4.p
129548.44/17465.60	eprover: CPU time limit exceeded, terminating
129548.44/17465.60	% SZS status Ended for HL407037+4.p
129549.83/17465.82	% SZS status Started for HL407028+5.p
129549.83/17465.82	% SZS status GaveUp for HL407028+5.p
129549.83/17465.82	eprover: CPU time limit exceeded, terminating
129549.83/17465.82	% SZS status Ended for HL407028+5.p
129567.37/17468.06	% SZS status Started for HL407029+5.p
129567.37/17468.06	% SZS status GaveUp for HL407029+5.p
129567.37/17468.06	eprover: CPU time limit exceeded, terminating
129567.37/17468.06	% SZS status Ended for HL407029+5.p
129569.52/17468.33	% SZS status Started for HL407034+5.p
129569.52/17468.33	% SZS status GaveUp for HL407034+5.p
129569.52/17468.33	eprover: CPU time limit exceeded, terminating
129569.52/17468.33	% SZS status Ended for HL407034+5.p
129570.21/17468.48	% SZS status Started for HL407038+4.p
129570.21/17468.48	% SZS status GaveUp for HL407038+4.p
129570.21/17468.48	eprover: CPU time limit exceeded, terminating
129570.21/17468.48	% SZS status Ended for HL407038+4.p
129574.05/17468.86	% SZS status Started for HL407039+4.p
129574.05/17468.86	% SZS status GaveUp for HL407039+4.p
129574.05/17468.86	eprover: CPU time limit exceeded, terminating
129574.05/17468.86	% SZS status Ended for HL407039+4.p
129586.35/17470.48	% SZS status Started for HL407035+5.p
129586.35/17470.48	% SZS status GaveUp for HL407035+5.p
129586.35/17470.48	eprover: CPU time limit exceeded, terminating
129586.35/17470.48	% SZS status Ended for HL407035+5.p
129594.09/17471.37	% SZS status Started for HL407040+4.p
129594.09/17471.37	% SZS status GaveUp for HL407040+4.p
129594.09/17471.37	eprover: CPU time limit exceeded, terminating
129594.09/17471.37	% SZS status Ended for HL407040+4.p
129594.09/17471.38	% SZS status Started for HL407036+5.p
129594.09/17471.38	% SZS status GaveUp for HL407036+5.p
129594.09/17471.38	eprover: CPU time limit exceeded, terminating
129594.09/17471.38	% SZS status Ended for HL407036+5.p
129597.92/17471.90	% SZS status Started for HL407042+4.p
129597.92/17471.90	% SZS status GaveUp for HL407042+4.p
129597.92/17471.90	eprover: CPU time limit exceeded, terminating
129597.92/17471.90	% SZS status Ended for HL407042+4.p
129618.27/17474.40	% SZS status Started for HL407043+4.p
129618.27/17474.40	% SZS status GaveUp for HL407043+4.p
129618.27/17474.40	eprover: CPU time limit exceeded, terminating
129618.27/17474.40	% SZS status Ended for HL407043+4.p
129618.55/17474.52	% SZS status Started for HL407037+5.p
129618.55/17474.52	% SZS status GaveUp for HL407037+5.p
129618.55/17474.52	eprover: CPU time limit exceeded, terminating
129618.55/17474.52	% SZS status Ended for HL407037+5.p
129620.96/17474.96	% SZS status Started for HL407044+4.p
129620.96/17474.96	% SZS status GaveUp for HL407044+4.p
129620.96/17474.96	eprover: CPU time limit exceeded, terminating
129620.96/17474.96	% SZS status Ended for HL407044+4.p
129631.67/17476.15	% SZS status Started for HL407038+5.p
129631.67/17476.15	% SZS status GaveUp for HL407038+5.p
129631.67/17476.15	eprover: CPU time limit exceeded, terminating
129631.67/17476.15	% SZS status Ended for HL407038+5.p
129642.94/17477.56	% SZS status Started for HL407045+4.p
129642.94/17477.56	% SZS status GaveUp for HL407045+4.p
129642.94/17477.56	eprover: CPU time limit exceeded, terminating
129642.94/17477.56	% SZS status Ended for HL407045+4.p
129650.12/17478.44	% SZS status Started for HL407039+5.p
129650.12/17478.44	% SZS status GaveUp for HL407039+5.p
129650.12/17478.44	eprover: CPU time limit exceeded, terminating
129650.12/17478.44	% SZS status Ended for HL407039+5.p
129653.59/17478.90	% SZS status Started for HL407040+5.p
129653.59/17478.90	% SZS status GaveUp for HL407040+5.p
129653.59/17478.90	eprover: CPU time limit exceeded, terminating
129653.59/17478.90	% SZS status Ended for HL407040+5.p
129656.29/17479.19	% SZS status Started for HL407046+4.p
129656.29/17479.19	% SZS status GaveUp for HL407046+4.p
129656.29/17479.19	eprover: CPU time limit exceeded, terminating
129656.29/17479.19	% SZS status Ended for HL407046+4.p
129669.06/17480.90	% SZS status Started for HL407042+5.p
129669.06/17480.90	% SZS status GaveUp for HL407042+5.p
129669.06/17480.90	eprover: CPU time limit exceeded, terminating
129669.06/17480.90	% SZS status Ended for HL407042+5.p
129674.01/17481.48	% SZS status Started for HL407047+4.p
129674.01/17481.48	% SZS status GaveUp for HL407047+4.p
129674.01/17481.48	eprover: CPU time limit exceeded, terminating
129674.01/17481.48	% SZS status Ended for HL407047+4.p
129676.58/17481.79	% SZS status Started for HL407043+5.p
129676.58/17481.79	% SZS status GaveUp for HL407043+5.p
129676.58/17481.79	eprover: CPU time limit exceeded, terminating
129676.58/17481.79	% SZS status Ended for HL407043+5.p
129678.97/17482.23	% SZS status Started for HL407048+4.p
129678.97/17482.23	% SZS status GaveUp for HL407048+4.p
129678.97/17482.23	eprover: CPU time limit exceeded, terminating
129678.97/17482.23	% SZS status Ended for HL407048+4.p
129697.66/17484.51	% SZS status Started for HL407049+4.p
129697.66/17484.51	% SZS status GaveUp for HL407049+4.p
129697.66/17484.51	eprover: CPU time limit exceeded, terminating
129697.66/17484.51	% SZS status Ended for HL407049+4.p
129700.16/17484.74	% SZS status Started for HL407044+5.p
129700.16/17484.74	% SZS status GaveUp for HL407044+5.p
129700.16/17484.74	eprover: CPU time limit exceeded, terminating
129700.16/17484.74	% SZS status Ended for HL407044+5.p
129704.41/17485.28	% SZS status Started for HL407050+4.p
129704.41/17485.28	% SZS status GaveUp for HL407050+4.p
129704.41/17485.28	eprover: CPU time limit exceeded, terminating
129704.41/17485.28	% SZS status Ended for HL407050+4.p
129705.72/17485.48	% SZS status Started for HL407045+5.p
129705.72/17485.48	% SZS status GaveUp for HL407045+5.p
129705.72/17485.48	eprover: CPU time limit exceeded, terminating
129705.72/17485.48	% SZS status Ended for HL407045+5.p
129723.91/17487.78	% SZS status Started for HL407051+4.p
129723.91/17487.78	% SZS status GaveUp for HL407051+4.p
129723.91/17487.78	eprover: CPU time limit exceeded, terminating
129723.91/17487.78	% SZS status Ended for HL407051+4.p
129724.76/17487.96	% SZS status Started for HL407046+5.p
129724.76/17487.96	% SZS status GaveUp for HL407046+5.p
129724.76/17487.96	eprover: CPU time limit exceeded, terminating
129724.76/17487.96	% SZS status Ended for HL407046+5.p
129729.60/17488.51	% SZS status Started for HL407052+4.p
129729.60/17488.51	% SZS status GaveUp for HL407052+4.p
129729.60/17488.51	eprover: CPU time limit exceeded, terminating
129729.60/17488.51	% SZS status Ended for HL407052+4.p
129741.00/17489.90	% SZS status Started for HL407047+5.p
129741.00/17489.90	% SZS status GaveUp for HL407047+5.p
129741.00/17489.90	eprover: CPU time limit exceeded, terminating
129741.00/17489.90	% SZS status Ended for HL407047+5.p
129749.79/17490.99	% SZS status Started for HL407053+4.p
129749.79/17490.99	% SZS status GaveUp for HL407053+4.p
129749.79/17490.99	eprover: CPU time limit exceeded, terminating
129749.79/17490.99	% SZS status Ended for HL407053+4.p
129751.04/17491.30	% SZS status Started for HL407048+5.p
129751.04/17491.30	% SZS status GaveUp for HL407048+5.p
129751.04/17491.30	eprover: CPU time limit exceeded, terminating
129751.04/17491.30	% SZS status Ended for HL407048+5.p
129759.30/17492.21	% SZS status Started for HL407049+5.p
129759.30/17492.21	% SZS status GaveUp for HL407049+5.p
129759.30/17492.21	eprover: CPU time limit exceeded, terminating
129759.30/17492.21	% SZS status Ended for HL407049+5.p
129764.89/17492.93	% SZS status Started for HL407054+4.p
129764.89/17492.93	% SZS status GaveUp for HL407054+4.p
129764.89/17492.93	eprover: CPU time limit exceeded, terminating
129764.89/17492.93	% SZS status Ended for HL407054+4.p
129776.43/17494.33	% SZS status Started for HL407056+4.p
129776.43/17494.33	% SZS status GaveUp for HL407056+4.p
129776.43/17494.33	eprover: CPU time limit exceeded, terminating
129776.43/17494.33	% SZS status Ended for HL407056+4.p
129780.65/17494.91	% SZS status Started for HL407050+5.p
129780.65/17494.91	% SZS status GaveUp for HL407050+5.p
129780.65/17494.91	eprover: CPU time limit exceeded, terminating
129780.65/17494.91	% SZS status Ended for HL407050+5.p
129786.91/17495.69	% SZS status Started for HL407051+5.p
129786.91/17495.69	% SZS status GaveUp for HL407051+5.p
129786.91/17495.69	eprover: CPU time limit exceeded, terminating
129786.91/17495.69	% SZS status Ended for HL407051+5.p
129789.41/17495.98	% SZS status Started for HL407057+4.p
129789.41/17495.98	% SZS status GaveUp for HL407057+4.p
129789.41/17495.98	eprover: CPU time limit exceeded, terminating
129789.41/17495.98	% SZS status Ended for HL407057+4.p
129807.56/17497.95	% SZS status Started for HL407058+4.p
129807.56/17497.95	% SZS status GaveUp for HL407058+4.p
129807.56/17497.95	eprover: CPU time limit exceeded, terminating
129807.56/17497.95	% SZS status Ended for HL407058+4.p
129808.89/17498.19	% SZS status Started for HL407052+5.p
129808.89/17498.19	% SZS status GaveUp for HL407052+5.p
129808.89/17498.19	eprover: CPU time limit exceeded, terminating
129808.89/17498.19	% SZS status Ended for HL407052+5.p
129814.66/17499.01	% SZS status Started for HL407059+4.p
129814.66/17499.01	% SZS status GaveUp for HL407059+4.p
129814.66/17499.01	eprover: CPU time limit exceeded, terminating
129814.66/17499.01	% SZS status Ended for HL407059+4.p
129818.49/17499.29	% SZS status Started for HL407053+5.p
129818.49/17499.29	% SZS status GaveUp for HL407053+5.p
129818.49/17499.29	eprover: CPU time limit exceeded, terminating
129818.49/17499.29	% SZS status Ended for HL407053+5.p
129834.07/17501.23	% SZS status Started for HL407060+4.p
129834.07/17501.23	% SZS status GaveUp for HL407060+4.p
129834.07/17501.23	eprover: CPU time limit exceeded, terminating
129834.07/17501.23	% SZS status Ended for HL407060+4.p
129834.90/17501.43	% SZS status Started for HL407054+5.p
129834.90/17501.43	% SZS status GaveUp for HL407054+5.p
129834.90/17501.43	eprover: CPU time limit exceeded, terminating
129834.90/17501.43	% SZS status Ended for HL407054+5.p
129842.52/17502.33	% SZS status Started for HL407061+4.p
129842.52/17502.33	% SZS status GaveUp for HL407061+4.p
129842.52/17502.33	eprover: CPU time limit exceeded, terminating
129842.52/17502.33	% SZS status Ended for HL407061+4.p
129844.84/17502.58	% SZS status Started for HL407056+5.p
129844.84/17502.58	% SZS status GaveUp for HL407056+5.p
129844.84/17502.58	eprover: CPU time limit exceeded, terminating
129844.84/17502.58	% SZS status Ended for HL407056+5.p
129859.00/17504.47	% SZS status Started for HL407063+4.p
129859.00/17504.47	% SZS status GaveUp for HL407063+4.p
129859.00/17504.47	eprover: CPU time limit exceeded, terminating
129859.00/17504.47	% SZS status Ended for HL407063+4.p
129861.73/17504.73	% SZS status Started for HL407057+5.p
129861.73/17504.73	% SZS status GaveUp for HL407057+5.p
129861.73/17504.73	eprover: CPU time limit exceeded, terminating
129861.73/17504.73	% SZS status Ended for HL407057+5.p
129868.16/17505.67	% SZS status Started for HL407064+4.p
129868.16/17505.67	% SZS status GaveUp for HL407064+4.p
129868.16/17505.67	eprover: CPU time limit exceeded, terminating
129868.16/17505.67	% SZS status Ended for HL407064+4.p
129875.06/17506.46	% SZS status Started for HL407058+5.p
129875.06/17506.46	% SZS status GaveUp for HL407058+5.p
129875.06/17506.46	eprover: CPU time limit exceeded, terminating
129875.06/17506.46	% SZS status Ended for HL407058+5.p
129885.52/17507.77	% SZS status Started for HL407065+4.p
129885.52/17507.77	% SZS status GaveUp for HL407065+4.p
129885.52/17507.77	eprover: CPU time limit exceeded, terminating
129885.52/17507.77	% SZS status Ended for HL407065+4.p
129890.20/17508.35	% SZS status Started for HL407059+5.p
129890.20/17508.35	% SZS status GaveUp for HL407059+5.p
129890.20/17508.35	eprover: CPU time limit exceeded, terminating
129890.20/17508.35	% SZS status Ended for HL407059+5.p
129898.63/17509.38	% SZS status Started for HL407060+5.p
129898.63/17509.38	% SZS status GaveUp for HL407060+5.p
129898.63/17509.38	eprover: CPU time limit exceeded, terminating
129898.63/17509.38	% SZS status Ended for HL407060+5.p
129899.45/17509.50	% SZS status Started for HL407066+4.p
129899.45/17509.50	% SZS status GaveUp for HL407066+4.p
129899.45/17509.50	eprover: CPU time limit exceeded, terminating
129899.45/17509.50	% SZS status Ended for HL407066+4.p
129914.02/17511.38	% SZS status Started for HL407067+4.p
129914.02/17511.38	% SZS status GaveUp for HL407067+4.p
129914.02/17511.38	eprover: CPU time limit exceeded, terminating
129914.02/17511.38	% SZS status Ended for HL407067+4.p
129916.32/17511.62	% SZS status Started for HL407061+5.p
129916.32/17511.62	% SZS status GaveUp for HL407061+5.p
129916.32/17511.62	eprover: CPU time limit exceeded, terminating
129916.32/17511.62	% SZS status Ended for HL407061+5.p
129922.98/17512.54	% SZS status Started for HL407068+4.p
129922.98/17512.54	% SZS status GaveUp for HL407068+4.p
129922.98/17512.54	eprover: CPU time limit exceeded, terminating
129922.98/17512.54	% SZS status Ended for HL407068+4.p
129926.02/17512.84	% SZS status Started for HL407063+5.p
129926.02/17512.84	% SZS status GaveUp for HL407063+5.p
129926.02/17512.84	eprover: CPU time limit exceeded, terminating
129926.02/17512.84	% SZS status Ended for HL407063+5.p
129940.45/17514.66	% SZS status Started for HL407069+4.p
129940.45/17514.66	% SZS status GaveUp for HL407069+4.p
129940.45/17514.66	eprover: CPU time limit exceeded, terminating
129940.45/17514.66	% SZS status Ended for HL407069+4.p
129942.24/17514.85	% SZS status Started for HL407064+5.p
129942.24/17514.85	% SZS status GaveUp for HL407064+5.p
129942.24/17514.85	eprover: CPU time limit exceeded, terminating
129942.24/17514.85	% SZS status Ended for HL407064+5.p
129949.41/17515.87	% SZS status Started for HL407070+4.p
129949.41/17515.87	% SZS status GaveUp for HL407070+4.p
129949.41/17515.87	eprover: CPU time limit exceeded, terminating
129949.41/17515.87	% SZS status Ended for HL407070+4.p
129954.16/17516.45	% SZS status Started for HL407065+5.p
129954.16/17516.45	% SZS status GaveUp for HL407065+5.p
129954.16/17516.45	eprover: CPU time limit exceeded, terminating
129954.16/17516.45	% SZS status Ended for HL407065+5.p
129965.85/17517.89	% SZS status Started for HL407071+4.p
129965.85/17517.89	% SZS status GaveUp for HL407071+4.p
129965.85/17517.89	eprover: CPU time limit exceeded, terminating
129965.85/17517.89	% SZS status Ended for HL407071+4.p
129967.19/17518.17	% SZS status Started for HL407066+5.p
129967.19/17518.17	% SZS status GaveUp for HL407066+5.p
129967.19/17518.17	eprover: CPU time limit exceeded, terminating
129967.19/17518.17	% SZS status Ended for HL407066+5.p
129979.06/17519.50	% SZS status Started for HL407072+4.p
129979.06/17519.50	% SZS status GaveUp for HL407072+4.p
129979.06/17519.50	eprover: CPU time limit exceeded, terminating
129979.06/17519.50	% SZS status Ended for HL407072+4.p
129980.95/17519.78	% SZS status Started for HL407067+5.p
129980.95/17519.78	% SZS status GaveUp for HL407067+5.p
129980.95/17519.78	eprover: CPU time limit exceeded, terminating
129980.95/17519.78	% SZS status Ended for HL407067+5.p
129992.34/17521.21	% SZS status Started for HL407073+4.p
129992.34/17521.21	% SZS status GaveUp for HL407073+4.p
129992.34/17521.21	eprover: CPU time limit exceeded, terminating
129992.34/17521.21	% SZS status Ended for HL407073+4.p
129997.21/17521.78	% SZS status Started for HL407068+5.p
129997.21/17521.78	% SZS status GaveUp for HL407068+5.p
129997.21/17521.78	eprover: CPU time limit exceeded, terminating
129997.21/17521.78	% SZS status Ended for HL407068+5.p
130005.32/17522.81	% SZS status Started for HL407074+4.p
130005.32/17522.81	% SZS status GaveUp for HL407074+4.p
130005.32/17522.81	eprover: CPU time limit exceeded, terminating
130005.32/17522.81	% SZS status Ended for HL407074+4.p
130011.05/17523.54	% SZS status Started for HL407069+5.p
130011.05/17523.54	% SZS status GaveUp for HL407069+5.p
130011.05/17523.54	eprover: CPU time limit exceeded, terminating
130011.05/17523.54	% SZS status Ended for HL407069+5.p
130020.84/17524.81	% SZS status Started for HL407075+4.p
130020.84/17524.81	% SZS status GaveUp for HL407075+4.p
130020.84/17524.81	eprover: CPU time limit exceeded, terminating
130020.84/17524.81	% SZS status Ended for HL407075+4.p
130021.84/17525.04	% SZS status Started for HL407070+5.p
130021.84/17525.04	% SZS status GaveUp for HL407070+5.p
130021.84/17525.04	eprover: CPU time limit exceeded, terminating
130021.84/17525.04	% SZS status Ended for HL407070+5.p
130033.13/17526.33	% SZS status Started for HL407071+5.p
130033.13/17526.33	% SZS status GaveUp for HL407071+5.p
130033.13/17526.33	eprover: CPU time limit exceeded, terminating
130033.13/17526.33	% SZS status Ended for HL407071+5.p
130036.10/17526.74	% SZS status Started for HL407076+4.p
130036.10/17526.74	% SZS status GaveUp for HL407076+4.p
130036.10/17526.74	eprover: CPU time limit exceeded, terminating
130036.10/17526.74	% SZS status Ended for HL407076+4.p
130047.17/17528.07	% SZS status Started for HL407077+4.p
130047.17/17528.07	% SZS status GaveUp for HL407077+4.p
130047.17/17528.07	eprover: CPU time limit exceeded, terminating
130047.17/17528.07	% SZS status Ended for HL407077+4.p
130048.16/17528.24	% SZS status Started for HL407072+5.p
130048.16/17528.24	% SZS status GaveUp for HL407072+5.p
130048.16/17528.24	eprover: CPU time limit exceeded, terminating
130048.16/17528.24	% SZS status Ended for HL407072+5.p
130061.35/17529.85	% SZS status Started for HL407078+4.p
130061.35/17529.85	% SZS status GaveUp for HL407078+4.p
130061.35/17529.85	eprover: CPU time limit exceeded, terminating
130061.35/17529.85	% SZS status Ended for HL407078+4.p
130062.62/17529.91	% SZS status Started for HL407073+5.p
130062.62/17529.91	% SZS status GaveUp for HL407073+5.p
130062.62/17529.91	eprover: CPU time limit exceeded, terminating
130062.62/17529.91	% SZS status Ended for HL407073+5.p
130073.87/17531.43	% SZS status Started for HL407079+4.p
130073.87/17531.43	% SZS status GaveUp for HL407079+4.p
130073.87/17531.43	eprover: CPU time limit exceeded, terminating
130073.87/17531.43	% SZS status Ended for HL407079+4.p
130076.10/17531.62	% SZS status Started for HL407074+5.p
130076.10/17531.62	% SZS status GaveUp for HL407074+5.p
130076.10/17531.62	eprover: CPU time limit exceeded, terminating
130076.10/17531.62	% SZS status Ended for HL407074+5.p
130087.23/17533.04	% SZS status Started for HL407080+4.p
130087.23/17533.04	% SZS status GaveUp for HL407080+4.p
130087.23/17533.04	eprover: CPU time limit exceeded, terminating
130087.23/17533.04	% SZS status Ended for HL407080+4.p
130088.16/17533.22	% SZS status Started for HL407075+5.p
130088.16/17533.22	% SZS status GaveUp for HL407075+5.p
130088.16/17533.22	eprover: CPU time limit exceeded, terminating
130088.16/17533.22	% SZS status Ended for HL407075+5.p
130100.54/17534.74	% SZS status Started for HL407081+4.p
130100.54/17534.74	% SZS status GaveUp for HL407081+4.p
130100.54/17534.74	eprover: CPU time limit exceeded, terminating
130100.54/17534.74	% SZS status Ended for HL407081+4.p
130104.89/17535.26	% SZS status Started for HL407076+5.p
130104.89/17535.26	% SZS status GaveUp for HL407076+5.p
130104.89/17535.26	eprover: CPU time limit exceeded, terminating
130104.89/17535.26	% SZS status Ended for HL407076+5.p
130113.70/17536.34	% SZS status Started for HL407082+4.p
130113.70/17536.34	% SZS status GaveUp for HL407082+4.p
130113.70/17536.34	eprover: CPU time limit exceeded, terminating
130113.70/17536.34	% SZS status Ended for HL407082+4.p
130116.43/17536.78	% SZS status Started for HL407077+5.p
130116.43/17536.78	% SZS status GaveUp for HL407077+5.p
130116.43/17536.78	eprover: CPU time limit exceeded, terminating
130116.43/17536.78	% SZS status Ended for HL407077+5.p
130129.08/17538.30	% SZS status Started for HL407083+4.p
130129.08/17538.30	% SZS status GaveUp for HL407083+4.p
130129.08/17538.30	eprover: CPU time limit exceeded, terminating
130129.08/17538.30	% SZS status Ended for HL407083+4.p
130130.10/17538.42	% SZS status Started for HL407078+5.p
130130.10/17538.42	% SZS status GaveUp for HL407078+5.p
130130.10/17538.42	eprover: CPU time limit exceeded, terminating
130130.10/17538.42	% SZS status Ended for HL407078+5.p
130141.77/17539.96	% SZS status Started for HL407084+4.p
130141.77/17539.96	% SZS status GaveUp for HL407084+4.p
130141.77/17539.96	eprover: CPU time limit exceeded, terminating
130141.77/17539.96	% SZS status Ended for HL407084+4.p
130144.59/17540.26	% SZS status Started for HL407079+5.p
130144.59/17540.26	% SZS status GaveUp for HL407079+5.p
130144.59/17540.26	eprover: CPU time limit exceeded, terminating
130144.59/17540.26	% SZS status Ended for HL407079+5.p
130154.29/17541.53	% SZS status Started for HL407085+4.p
130154.29/17541.53	% SZS status GaveUp for HL407085+4.p
130154.29/17541.53	eprover: CPU time limit exceeded, terminating
130154.29/17541.53	% SZS status Ended for HL407085+4.p
130155.97/17541.82	% SZS status Started for HL407080+5.p
130155.97/17541.82	% SZS status GaveUp for HL407080+5.p
130155.97/17541.82	eprover: CPU time limit exceeded, terminating
130155.97/17541.82	% SZS status Ended for HL407080+5.p
130168.27/17543.30	% SZS status Started for HL407086+4.p
130168.27/17543.30	% SZS status GaveUp for HL407086+4.p
130168.27/17543.30	eprover: CPU time limit exceeded, terminating
130168.27/17543.30	% SZS status Ended for HL407086+4.p
130171.80/17543.40	% SZS status Started for HL407081+5.p
130171.80/17543.40	% SZS status GaveUp for HL407081+5.p
130171.80/17543.40	eprover: CPU time limit exceeded, terminating
130171.80/17543.40	% SZS status Ended for HL407081+5.p
130183.48/17544.87	% SZS status Started for HL407088+4.p
130183.48/17544.87	% SZS status GaveUp for HL407088+4.p
130183.48/17544.87	eprover: CPU time limit exceeded, terminating
130183.48/17544.87	% SZS status Ended for HL407088+4.p
130184.42/17545.15	% SZS status Started for HL407082+5.p
130184.42/17545.15	% SZS status GaveUp for HL407082+5.p
130184.42/17545.15	eprover: CPU time limit exceeded, terminating
130184.42/17545.15	% SZS status Ended for HL407082+5.p
130196.14/17546.44	% SZS status Started for HL407090+4.p
130196.14/17546.44	% SZS status GaveUp for HL407090+4.p
130196.14/17546.44	eprover: CPU time limit exceeded, terminating
130196.14/17546.44	% SZS status Ended for HL407090+4.p
130197.78/17546.77	% SZS status Started for HL407083+5.p
130197.78/17546.77	% SZS status GaveUp for HL407083+5.p
130197.78/17546.77	eprover: CPU time limit exceeded, terminating
130197.78/17546.77	% SZS status Ended for HL407083+5.p
130210.10/17548.31	% SZS status Started for HL407091+4.p
130210.10/17548.31	% SZS status GaveUp for HL407091+4.p
130210.10/17548.31	eprover: CPU time limit exceeded, terminating
130210.10/17548.31	% SZS status Ended for HL407091+4.p
130214.98/17548.83	% SZS status Started for HL407084+5.p
130214.98/17548.83	% SZS status GaveUp for HL407084+5.p
130214.98/17548.83	eprover: CPU time limit exceeded, terminating
130214.98/17548.83	% SZS status Ended for HL407084+5.p
130222.73/17549.84	% SZS status Started for HL407092+4.p
130222.73/17549.84	% SZS status GaveUp for HL407092+4.p
130222.73/17549.84	eprover: CPU time limit exceeded, terminating
130222.73/17549.84	% SZS status Ended for HL407092+4.p
130227.59/17550.46	% SZS status Started for HL407085+5.p
130227.59/17550.46	% SZS status GaveUp for HL407085+5.p
130227.59/17550.46	eprover: CPU time limit exceeded, terminating
130227.59/17550.46	% SZS status Ended for HL407085+5.p
130238.63/17551.87	% SZS status Started for HL407093+4.p
130238.63/17551.87	% SZS status GaveUp for HL407093+4.p
130238.63/17551.87	eprover: CPU time limit exceeded, terminating
130238.63/17551.87	% SZS status Ended for HL407093+4.p
130239.05/17551.90	% SZS status Started for HL407086+5.p
130239.05/17551.90	% SZS status GaveUp for HL407086+5.p
130239.05/17551.90	eprover: CPU time limit exceeded, terminating
130239.05/17551.90	% SZS status Ended for HL407086+5.p
130253.00/17553.64	% SZS status Started for HL407088+5.p
130253.00/17553.64	% SZS status GaveUp for HL407088+5.p
130253.00/17553.64	eprover: CPU time limit exceeded, terminating
130253.00/17553.64	% SZS status Ended for HL407088+5.p
130253.00/17553.64	% SZS status Started for HL407094+4.p
130253.00/17553.64	% SZS status GaveUp for HL407094+4.p
130253.00/17553.64	eprover: CPU time limit exceeded, terminating
130253.00/17553.64	% SZS status Ended for HL407094+4.p
130263.73/17554.93	% SZS status Started for HL407095+4.p
130263.73/17554.93	% SZS status GaveUp for HL407095+4.p
130263.73/17554.93	eprover: CPU time limit exceeded, terminating
130263.73/17554.93	% SZS status Ended for HL407095+4.p
130265.77/17555.27	% SZS status Started for HL407090+5.p
130265.77/17555.27	% SZS status GaveUp for HL407090+5.p
130265.77/17555.27	eprover: CPU time limit exceeded, terminating
130265.77/17555.27	% SZS status Ended for HL407090+5.p
130276.46/17556.68	% SZS status Started for HL407096+4.p
130276.46/17556.68	% SZS status GaveUp for HL407096+4.p
130276.46/17556.68	eprover: CPU time limit exceeded, terminating
130276.46/17556.68	% SZS status Ended for HL407096+4.p
130278.77/17556.84	% SZS status Started for HL407091+5.p
130278.77/17556.84	% SZS status GaveUp for HL407091+5.p
130278.77/17556.84	eprover: CPU time limit exceeded, terminating
130278.77/17556.84	% SZS status Ended for HL407091+5.p
130290.35/17558.31	% SZS status Started for HL407097+4.p
130290.35/17558.31	% SZS status GaveUp for HL407097+4.p
130290.35/17558.31	eprover: CPU time limit exceeded, terminating
130290.35/17558.31	% SZS status Ended for HL407097+4.p
130293.24/17558.71	% SZS status Started for HL407092+5.p
130293.24/17558.71	% SZS status GaveUp for HL407092+5.p
130293.24/17558.71	eprover: CPU time limit exceeded, terminating
130293.24/17558.71	% SZS status Ended for HL407092+5.p
130302.75/17559.88	% SZS status Started for HL407098+4.p
130302.75/17559.88	% SZS status GaveUp for HL407098+4.p
130302.75/17559.88	eprover: CPU time limit exceeded, terminating
130302.75/17559.88	% SZS status Ended for HL407098+4.p
130305.70/17560.26	% SZS status Started for HL407093+5.p
130305.70/17560.26	% SZS status GaveUp for HL407093+5.p
130305.70/17560.26	eprover: CPU time limit exceeded, terminating
130305.70/17560.26	% SZS status Ended for HL407093+5.p
130317.70/17561.75	% SZS status Started for HL407099+4.p
130317.70/17561.75	% SZS status GaveUp for HL407099+4.p
130317.70/17561.75	eprover: CPU time limit exceeded, terminating
130317.70/17561.75	% SZS status Ended for HL407099+4.p
130322.59/17562.34	% SZS status Started for HL407094+5.p
130322.59/17562.34	% SZS status GaveUp for HL407094+5.p
130322.59/17562.34	eprover: CPU time limit exceeded, terminating
130322.59/17562.34	% SZS status Ended for HL407094+5.p
130329.84/17563.30	% SZS status Started for HL407100+4.p
130329.84/17563.30	% SZS status GaveUp for HL407100+4.p
130329.84/17563.30	eprover: CPU time limit exceeded, terminating
130329.84/17563.30	% SZS status Ended for HL407100+4.p
130340.03/17564.54	% SZS status Started for HL407095+5.p
130340.03/17564.54	% SZS status GaveUp for HL407095+5.p
130340.03/17564.54	eprover: CPU time limit exceeded, terminating
130340.03/17564.54	% SZS status Ended for HL407095+5.p
130346.23/17565.33	% SZS status Started for HL407096+5.p
130346.23/17565.33	% SZS status GaveUp for HL407096+5.p
130346.23/17565.33	eprover: CPU time limit exceeded, terminating
130346.23/17565.33	% SZS status Ended for HL407096+5.p
130346.23/17565.37	% SZS status Started for HL407101+4.p
130346.23/17565.37	% SZS status GaveUp for HL407101+4.p
130346.23/17565.37	eprover: CPU time limit exceeded, terminating
130346.23/17565.37	% SZS status Ended for HL407101+4.p
130360.05/17567.06	% SZS status Started for HL407097+5.p
130360.05/17567.06	% SZS status GaveUp for HL407097+5.p
130360.05/17567.06	eprover: CPU time limit exceeded, terminating
130360.05/17567.06	% SZS status Ended for HL407097+5.p
130371.66/17568.69	% SZS status Started for HL407098+5.p
130371.66/17568.69	% SZS status GaveUp for HL407098+5.p
130371.66/17568.69	eprover: CPU time limit exceeded, terminating
130371.66/17568.69	% SZS status Ended for HL407098+5.p
130384.97/17570.21	% SZS status Started for HL407099+5.p
130384.97/17570.21	% SZS status GaveUp for HL407099+5.p
130384.97/17570.21	eprover: CPU time limit exceeded, terminating
130384.97/17570.21	% SZS status Ended for HL407099+5.p
130400.34/17572.15	% SZS status Started for HL407100+5.p
130400.34/17572.15	% SZS status GaveUp for HL407100+5.p
130400.34/17572.15	eprover: CPU time limit exceeded, terminating
130400.34/17572.15	% SZS status Ended for HL407100+5.p
130411.48/17573.58	% SZS status Started for HL407101+5.p
130411.48/17573.58	% SZS status GaveUp for HL407101+5.p
130411.48/17573.58	eprover: CPU time limit exceeded, terminating
130411.48/17573.58	% SZS status Ended for HL407101+5.p
130428.45/17575.68	% SZS status Started for HL407102+4.p
130428.45/17575.68	% SZS status GaveUp for HL407102+4.p
130428.45/17575.68	eprover: CPU time limit exceeded, terminating
130428.45/17575.68	% SZS status Ended for HL407102+4.p
130433.91/17576.38	% SZS status Started for HL407103+4.p
130433.91/17576.38	% SZS status GaveUp for HL407103+4.p
130433.91/17576.38	eprover: CPU time limit exceeded, terminating
130433.91/17576.38	% SZS status Ended for HL407103+4.p
130460.20/17579.68	% SZS status Started for HL407105+4.p
130460.20/17579.68	% SZS status GaveUp for HL407105+4.p
130460.20/17579.68	eprover: CPU time limit exceeded, terminating
130460.20/17579.68	% SZS status Ended for HL407105+4.p
130483.38/17582.74	% SZS status Started for HL407109+4.p
130483.38/17582.74	% SZS status GaveUp for HL407109+4.p
130483.38/17582.74	eprover: CPU time limit exceeded, terminating
130483.38/17582.74	% SZS status Ended for HL407109+4.p
130487.64/17583.27	% SZS status Started for HL407106+4.p
130487.64/17583.27	% SZS status GaveUp for HL407106+4.p
130487.64/17583.27	eprover: CPU time limit exceeded, terminating
130487.64/17583.27	% SZS status Ended for HL407106+4.p
130511.38/17586.46	% SZS status Started for HL407110+4.p
130511.38/17586.46	% SZS status GaveUp for HL407110+4.p
130511.38/17586.46	eprover: CPU time limit exceeded, terminating
130511.38/17586.46	% SZS status Ended for HL407110+4.p
130515.45/17586.93	% SZS status Started for HL407107+4.p
130515.45/17586.93	% SZS status GaveUp for HL407107+4.p
130515.45/17586.93	eprover: CPU time limit exceeded, terminating
130515.45/17586.93	% SZS status Ended for HL407107+4.p
130538.06/17589.99	% SZS status Started for HL407111+4.p
130538.06/17589.99	% SZS status GaveUp for HL407111+4.p
130538.06/17589.99	eprover: CPU time limit exceeded, terminating
130538.06/17589.99	% SZS status Ended for HL407111+4.p
130546.72/17591.18	% SZS status Started for HL407102+5.p
130546.72/17591.18	% SZS status GaveUp for HL407102+5.p
130546.72/17591.18	eprover: CPU time limit exceeded, terminating
130546.72/17591.18	% SZS status Ended for HL407102+5.p
130564.92/17593.66	% SZS status Started for HL407103+5.p
130564.92/17593.66	% SZS status GaveUp for HL407103+5.p
130564.92/17593.66	eprover: CPU time limit exceeded, terminating
130564.92/17593.66	% SZS status Ended for HL407103+5.p
130568.93/17594.26	% SZS status Started for HL407112+4.p
130568.93/17594.26	% SZS status GaveUp for HL407112+4.p
130568.93/17594.26	eprover: CPU time limit exceeded, terminating
130568.93/17594.26	% SZS status Ended for HL407112+4.p
130573.20/17594.83	% SZS status Started for HL407109+5.p
130573.20/17594.83	% SZS status GaveUp for HL407109+5.p
130573.20/17594.83	eprover: CPU time limit exceeded, terminating
130573.20/17594.83	% SZS status Ended for HL407109+5.p
130586.71/17596.54	% SZS status Started for HL407105+5.p
130586.71/17596.54	% SZS status GaveUp for HL407105+5.p
130586.71/17596.54	eprover: CPU time limit exceeded, terminating
130586.71/17596.54	% SZS status Ended for HL407105+5.p
130595.63/17597.72	% SZS status Started for HL407113+4.p
130595.63/17597.72	% SZS status GaveUp for HL407113+4.p
130595.63/17597.72	eprover: CPU time limit exceeded, terminating
130595.63/17597.72	% SZS status Ended for HL407113+4.p
130610.05/17599.65	% SZS status Started for HL407114+4.p
130610.05/17599.65	% SZS status GaveUp for HL407114+4.p
130610.05/17599.65	eprover: CPU time limit exceeded, terminating
130610.05/17599.65	% SZS status Ended for HL407114+4.p
130616.52/17600.48	% SZS status Started for HL407106+5.p
130616.52/17600.48	% SZS status GaveUp for HL407106+5.p
130616.52/17600.48	eprover: CPU time limit exceeded, terminating
130616.52/17600.48	% SZS status Ended for HL407106+5.p
130623.76/17601.50	% SZS status Started for HL407111+5.p
130623.76/17601.50	% SZS status GaveUp for HL407111+5.p
130623.76/17601.50	eprover: CPU time limit exceeded, terminating
130623.76/17601.50	% SZS status Ended for HL407111+5.p
130633.74/17602.85	% SZS status Started for HL407115+4.p
130633.74/17602.85	% SZS status GaveUp for HL407115+4.p
130633.74/17602.85	eprover: CPU time limit exceeded, terminating
130633.74/17602.85	% SZS status Ended for HL407115+4.p
130641.02/17603.87	% SZS status Started for HL407107+5.p
130641.02/17603.87	% SZS status GaveUp for HL407107+5.p
130641.02/17603.87	eprover: CPU time limit exceeded, terminating
130641.02/17603.87	% SZS status Ended for HL407107+5.p
130645.49/17604.50	% SZS status Started for HL407112+5.p
130645.49/17604.50	% SZS status GaveUp for HL407112+5.p
130645.49/17604.50	eprover: CPU time limit exceeded, terminating
130645.49/17604.50	% SZS status Ended for HL407112+5.p
130645.89/17604.58	% SZS status Started for HL407116+4.p
130645.89/17604.58	% SZS status GaveUp for HL407116+4.p
130645.89/17604.58	eprover: CPU time limit exceeded, terminating
130645.89/17604.58	% SZS status Ended for HL407116+4.p
130659.45/17606.36	% SZS status Started for HL407113+5.p
130659.45/17606.36	% SZS status GaveUp for HL407113+5.p
130659.45/17606.36	eprover: CPU time limit exceeded, terminating
130659.45/17606.36	% SZS status Ended for HL407113+5.p
130672.99/17606.95	% SZS status Started for HL407117+4.p
130672.99/17606.95	% SZS status GaveUp for HL407117+4.p
130672.99/17606.95	eprover: CPU time limit exceeded, terminating
130672.99/17606.95	% SZS status Ended for HL407117+4.p
130681.62/17607.73	% SZS status Started for HL407118+4.p
130681.62/17607.73	% SZS status GaveUp for HL407118+4.p
130681.62/17607.73	eprover: CPU time limit exceeded, terminating
130681.62/17607.73	% SZS status Ended for HL407118+4.p
130690.80/17609.06	% SZS status Started for HL407114+5.p
130690.80/17609.06	% SZS status GaveUp for HL407114+5.p
130690.80/17609.06	eprover: CPU time limit exceeded, terminating
130690.80/17609.06	% SZS status Ended for HL407114+5.p
130697.95/17610.01	% SZS status Started for HL407119+4.p
130697.95/17610.01	% SZS status GaveUp for HL407119+4.p
130697.95/17610.01	eprover: CPU time limit exceeded, terminating
130697.95/17610.01	% SZS status Ended for HL407119+4.p
130714.63/17612.18	% SZS status Started for HL407121+4.p
130714.63/17612.18	% SZS status GaveUp for HL407121+4.p
130714.63/17612.18	eprover: CPU time limit exceeded, terminating
130714.63/17612.18	% SZS status Ended for HL407121+4.p
130719.86/17612.99	% SZS status Started for HL407115+5.p
130719.86/17612.99	% SZS status GaveUp for HL407115+5.p
130719.86/17612.99	eprover: CPU time limit exceeded, terminating
130719.86/17612.99	% SZS status Ended for HL407115+5.p
130725.77/17613.69	% SZS status Started for HL407116+5.p
130725.77/17613.69	% SZS status GaveUp for HL407116+5.p
130725.77/17613.69	eprover: CPU time limit exceeded, terminating
130725.77/17613.69	% SZS status Ended for HL407116+5.p
130727.74/17613.96	% SZS status Started for HL407110+5.p
130727.74/17613.96	% SZS status GaveUp for HL407110+5.p
130727.74/17613.96	eprover: CPU time limit exceeded, terminating
130727.74/17613.96	% SZS status Ended for HL407110+5.p
130737.02/17615.24	% SZS status Started for HL407122+4.p
130737.02/17615.24	% SZS status GaveUp for HL407122+4.p
130737.02/17615.24	eprover: CPU time limit exceeded, terminating
130737.02/17615.24	% SZS status Ended for HL407122+4.p
130745.81/17616.39	% SZS status Started for HL407117+5.p
130745.81/17616.39	% SZS status GaveUp for HL407117+5.p
130745.81/17616.39	eprover: CPU time limit exceeded, terminating
130745.81/17616.39	% SZS status Ended for HL407117+5.p
130749.13/17616.77	% SZS status Started for HL407123+4.p
130749.13/17616.77	% SZS status GaveUp for HL407123+4.p
130749.13/17616.77	eprover: CPU time limit exceeded, terminating
130749.13/17616.77	% SZS status Ended for HL407123+4.p
130760.26/17618.28	% SZS status Started for HL407124+4.p
130760.26/17618.28	% SZS status GaveUp for HL407124+4.p
130760.26/17618.28	eprover: CPU time limit exceeded, terminating
130760.26/17618.28	% SZS status Ended for HL407124+4.p
130762.52/17618.69	% SZS status Started for HL407119+5.p
130762.52/17618.69	% SZS status GaveUp for HL407119+5.p
130762.52/17618.69	eprover: CPU time limit exceeded, terminating
130762.52/17618.69	% SZS status Ended for HL407119+5.p
130774.03/17620.20	% SZS status Started for HL407125+4.p
130774.03/17620.20	% SZS status GaveUp for HL407125+4.p
130774.03/17620.20	eprover: CPU time limit exceeded, terminating
130774.03/17620.20	% SZS status Ended for HL407125+4.p
130783.45/17621.45	% SZS status Started for HL407118+5.p
130783.45/17621.45	% SZS status GaveUp for HL407118+5.p
130783.45/17621.45	eprover: CPU time limit exceeded, terminating
130783.45/17621.45	% SZS status Ended for HL407118+5.p
130786.48/17621.82	% SZS status Started for HL407126+4.p
130786.48/17621.82	% SZS status GaveUp for HL407126+4.p
130786.48/17621.82	eprover: CPU time limit exceeded, terminating
130786.48/17621.82	% SZS status Ended for HL407126+4.p
130805.55/17624.55	% SZS status Started for HL407128+4.p
130805.55/17624.55	% SZS status GaveUp for HL407128+4.p
130805.55/17624.55	eprover: CPU time limit exceeded, terminating
130805.55/17624.55	% SZS status Ended for HL407128+4.p
130816.25/17625.89	% SZS status Started for HL407123+5.p
130816.25/17625.89	% SZS status GaveUp for HL407123+5.p
130816.25/17625.89	eprover: CPU time limit exceeded, terminating
130816.25/17625.89	% SZS status Ended for HL407123+5.p
130827.34/17627.38	% SZS status Started for HL407124+5.p
130827.34/17627.38	% SZS status GaveUp for HL407124+5.p
130827.34/17627.38	eprover: CPU time limit exceeded, terminating
130827.34/17627.38	% SZS status Ended for HL407124+5.p
130829.54/17627.66	% SZS status Started for HL407130+4.p
130829.54/17627.66	% SZS status GaveUp for HL407130+4.p
130829.54/17627.66	eprover: CPU time limit exceeded, terminating
130829.54/17627.66	% SZS status Ended for HL407130+4.p
130849.91/17630.44	% SZS status Started for HL407131+4.p
130849.91/17630.44	% SZS status GaveUp for HL407131+4.p
130849.91/17630.44	eprover: CPU time limit exceeded, terminating
130849.91/17630.44	% SZS status Ended for HL407131+4.p
130851.47/17630.63	% SZS status Started for HL407125+5.p
130851.47/17630.63	% SZS status GaveUp for HL407125+5.p
130851.47/17630.63	eprover: CPU time limit exceeded, terminating
130851.47/17630.63	% SZS status Ended for HL407125+5.p
130852.48/17630.78	% SZS status Started for HL407126+5.p
130852.48/17630.78	% SZS status GaveUp for HL407126+5.p
130852.48/17630.78	eprover: CPU time limit exceeded, terminating
130852.48/17630.78	% SZS status Ended for HL407126+5.p
130871.95/17633.45	% SZS status Started for HL407128+5.p
130871.95/17633.45	% SZS status GaveUp for HL407128+5.p
130871.95/17633.45	eprover: CPU time limit exceeded, terminating
130871.95/17633.45	% SZS status Ended for HL407128+5.p
130875.98/17633.88	% SZS status Started for HL407135+4.p
130875.98/17633.88	% SZS status GaveUp for HL407135+4.p
130875.98/17633.88	eprover: CPU time limit exceeded, terminating
130875.98/17633.88	% SZS status Ended for HL407135+4.p
130876.12/17633.90	% SZS status Started for HL407133+4.p
130876.12/17633.90	% SZS status GaveUp for HL407133+4.p
130876.12/17633.90	eprover: CPU time limit exceeded, terminating
130876.12/17633.90	% SZS status Ended for HL407133+4.p
130896.45/17636.54	% SZS status Started for HL407130+5.p
130896.45/17636.54	% SZS status GaveUp for HL407130+5.p
130896.45/17636.54	eprover: CPU time limit exceeded, terminating
130896.45/17636.54	% SZS status Ended for HL407130+5.p
130899.26/17636.95	% SZS status Started for HL407137+4.p
130899.26/17636.95	% SZS status GaveUp for HL407137+4.p
130899.26/17636.95	eprover: CPU time limit exceeded, terminating
130899.26/17636.95	% SZS status Ended for HL407137+4.p
130902.59/17637.35	% SZS status Started for HL407121+5.p
130902.59/17637.35	% SZS status GaveUp for HL407121+5.p
130902.59/17637.35	eprover: CPU time limit exceeded, terminating
130902.59/17637.35	% SZS status Ended for HL407121+5.p
130913.84/17638.85	% SZS status Started for HL407131+5.p
130913.84/17638.85	% SZS status GaveUp for HL407131+5.p
130913.84/17638.85	eprover: CPU time limit exceeded, terminating
130913.84/17638.85	% SZS status Ended for HL407131+5.p
130920.00/17639.75	% SZS status Started for HL407138+4.p
130920.00/17639.75	% SZS status GaveUp for HL407138+4.p
130920.00/17639.75	eprover: CPU time limit exceeded, terminating
130920.00/17639.75	% SZS status Ended for HL407138+4.p
130923.87/17640.22	% SZS status Started for HL407122+5.p
130923.87/17640.22	% SZS status GaveUp for HL407122+5.p
130923.87/17640.22	eprover: CPU time limit exceeded, terminating
130923.87/17640.22	% SZS status Ended for HL407122+5.p
130926.88/17640.61	% SZS status Started for HL407139+4.p
130926.88/17640.61	% SZS status GaveUp for HL407139+4.p
130926.88/17640.61	eprover: CPU time limit exceeded, terminating
130926.88/17640.61	% SZS status Ended for HL407139+4.p
130936.55/17641.87	% SZS status Started for HL407133+5.p
130936.55/17641.87	% SZS status GaveUp for HL407133+5.p
130936.55/17641.87	eprover: CPU time limit exceeded, terminating
130936.55/17641.87	% SZS status Ended for HL407133+5.p
130944.84/17642.97	% SZS status Started for HL407141+4.p
130944.84/17642.97	% SZS status GaveUp for HL407141+4.p
130944.84/17642.97	eprover: CPU time limit exceeded, terminating
130944.84/17642.97	% SZS status Ended for HL407141+4.p
130949.93/17643.72	% SZS status Started for HL407142+4.p
130949.93/17643.72	% SZS status GaveUp for HL407142+4.p
130949.93/17643.72	eprover: CPU time limit exceeded, terminating
130949.93/17643.72	% SZS status Ended for HL407142+4.p
130955.73/17644.62	% SZS status Started for HL407135+5.p
130955.73/17644.62	% SZS status GaveUp for HL407135+5.p
130955.73/17644.62	eprover: CPU time limit exceeded, terminating
130955.73/17644.62	% SZS status Ended for HL407135+5.p
130960.27/17645.11	% SZS status Started for HL407137+5.p
130960.27/17645.11	% SZS status GaveUp for HL407137+5.p
130960.27/17645.11	eprover: CPU time limit exceeded, terminating
130960.27/17645.11	% SZS status Ended for HL407137+5.p
130969.77/17646.30	% SZS status Started for HL407145+4.p
130969.77/17646.30	% SZS status GaveUp for HL407145+4.p
130969.77/17646.30	eprover: CPU time limit exceeded, terminating
130969.77/17646.30	% SZS status Ended for HL407145+4.p
130980.95/17647.80	% SZS status Started for HL407146+4.p
130980.95/17647.80	% SZS status GaveUp for HL407146+4.p
130980.95/17647.80	eprover: CPU time limit exceeded, terminating
130980.95/17647.80	% SZS status Ended for HL407146+4.p
130983.40/17648.09	% SZS status Started for HL407138+5.p
130983.40/17648.09	% SZS status GaveUp for HL407138+5.p
130983.40/17648.09	eprover: CPU time limit exceeded, terminating
130983.40/17648.09	% SZS status Ended for HL407138+5.p
130993.62/17649.53	% SZS status Started for HL407147+4.p
130993.62/17649.53	% SZS status GaveUp for HL407147+4.p
130993.62/17649.53	eprover: CPU time limit exceeded, terminating
130993.62/17649.53	% SZS status Ended for HL407147+4.p
130999.16/17650.31	% SZS status Started for HL407139+5.p
130999.16/17650.31	% SZS status GaveUp for HL407139+5.p
130999.16/17650.31	eprover: CPU time limit exceeded, terminating
130999.16/17650.31	% SZS status Ended for HL407139+5.p
131006.81/17651.42	% SZS status Started for HL407150+4.p
131006.81/17651.42	% SZS status GaveUp for HL407150+4.p
131006.81/17651.42	eprover: CPU time limit exceeded, terminating
131006.81/17651.42	% SZS status Ended for HL407150+4.p
131010.44/17651.86	% SZS status Started for HL407141+5.p
131010.44/17651.86	% SZS status GaveUp for HL407141+5.p
131010.44/17651.86	eprover: CPU time limit exceeded, terminating
131010.44/17651.86	% SZS status Ended for HL407141+5.p
131019.08/17653.00	% SZS status Started for HL407142+5.p
131019.08/17653.00	% SZS status GaveUp for HL407142+5.p
131019.08/17653.00	eprover: CPU time limit exceeded, terminating
131019.08/17653.00	% SZS status Ended for HL407142+5.p
131022.06/17653.42	% SZS status Started for HL407151+4.p
131022.06/17653.42	% SZS status GaveUp for HL407151+4.p
131022.06/17653.42	eprover: CPU time limit exceeded, terminating
131022.06/17653.42	% SZS status Ended for HL407151+4.p
131032.40/17654.75	% SZS status Started for HL407145+5.p
131032.40/17654.75	% SZS status GaveUp for HL407145+5.p
131032.40/17654.75	eprover: CPU time limit exceeded, terminating
131032.40/17654.75	% SZS status Ended for HL407145+5.p
131035.05/17655.06	% SZS status Started for HL407152+4.p
131035.05/17655.06	% SZS status GaveUp for HL407152+4.p
131035.05/17655.06	eprover: CPU time limit exceeded, terminating
131035.05/17655.06	% SZS status Ended for HL407152+4.p
131043.99/17656.22	% SZS status Started for HL407146+5.p
131043.99/17656.22	% SZS status GaveUp for HL407146+5.p
131043.99/17656.22	eprover: CPU time limit exceeded, terminating
131043.99/17656.22	% SZS status Ended for HL407146+5.p
131045.12/17656.50	% SZS status Started for HL407153+4.p
131045.12/17656.50	% SZS status GaveUp for HL407153+4.p
131045.12/17656.50	eprover: CPU time limit exceeded, terminating
131045.12/17656.50	% SZS status Ended for HL407153+4.p
131060.17/17658.31	% SZS status Started for HL407154+4.p
131060.17/17658.31	% SZS status GaveUp for HL407154+4.p
131060.17/17658.31	eprover: CPU time limit exceeded, terminating
131060.17/17658.31	% SZS status Ended for HL407154+4.p
131061.77/17658.61	% SZS status Started for HL407147+5.p
131061.77/17658.61	% SZS status GaveUp for HL407147+5.p
131061.77/17658.61	eprover: CPU time limit exceeded, terminating
131061.77/17658.61	% SZS status Ended for HL407147+5.p
131069.84/17659.56	% SZS status Started for HL407155+4.p
131069.84/17659.56	% SZS status GaveUp for HL407155+4.p
131069.84/17659.56	eprover: CPU time limit exceeded, terminating
131069.84/17659.56	% SZS status Ended for HL407155+4.p
131075.81/17660.38	% SZS status Started for HL407150+5.p
131075.81/17660.38	% SZS status GaveUp for HL407150+5.p
131075.81/17660.38	eprover: CPU time limit exceeded, terminating
131075.81/17660.38	% SZS status Ended for HL407150+5.p
131086.61/17661.73	% SZS status Started for HL407156+4.p
131086.61/17661.73	% SZS status GaveUp for HL407156+4.p
131086.61/17661.73	eprover: CPU time limit exceeded, terminating
131086.61/17661.73	% SZS status Ended for HL407156+4.p
131089.77/17662.14	% SZS status Started for HL407151+5.p
131089.77/17662.14	% SZS status GaveUp for HL407151+5.p
131089.77/17662.14	eprover: CPU time limit exceeded, terminating
131089.77/17662.14	% SZS status Ended for HL407151+5.p
131098.80/17663.43	% SZS status Started for HL407159+4.p
131098.80/17663.43	% SZS status GaveUp for HL407159+4.p
131098.80/17663.43	eprover: CPU time limit exceeded, terminating
131098.80/17663.43	% SZS status Ended for HL407159+4.p
131105.09/17664.36	% SZS status Started for HL407152+5.p
131105.09/17664.36	% SZS status GaveUp for HL407152+5.p
131105.09/17664.36	eprover: CPU time limit exceeded, terminating
131105.09/17664.36	% SZS status Ended for HL407152+5.p
131113.91/17665.55	% SZS status Started for HL407160+4.p
131113.91/17665.55	% SZS status GaveUp for HL407160+4.p
131113.91/17665.55	eprover: CPU time limit exceeded, terminating
131113.91/17665.55	% SZS status Ended for HL407160+4.p
131126.41/17667.33	% SZS status Started for HL407154+5.p
131126.41/17667.33	% SZS status GaveUp for HL407154+5.p
131126.41/17667.33	eprover: CPU time limit exceeded, terminating
131126.41/17667.33	% SZS status Ended for HL407154+5.p
131129.08/17667.71	% SZS status Started for HL407161+4.p
131129.08/17667.71	% SZS status GaveUp for HL407161+4.p
131129.08/17667.71	eprover: CPU time limit exceeded, terminating
131129.08/17667.71	% SZS status Ended for HL407161+4.p
131149.55/17670.60	% SZS status Started for HL407156+5.p
131149.55/17670.60	% SZS status GaveUp for HL407156+5.p
131149.55/17670.60	eprover: CPU time limit exceeded, terminating
131149.55/17670.60	% SZS status Ended for HL407156+5.p
131151.23/17671.01	% SZS status Started for HL407163+4.p
131151.23/17671.01	% SZS status GaveUp for HL407163+4.p
131151.23/17671.01	eprover: CPU time limit exceeded, terminating
131151.23/17671.01	% SZS status Ended for HL407163+4.p
131164.14/17672.61	% SZS status Started for HL407159+5.p
131164.14/17672.61	% SZS status GaveUp for HL407159+5.p
131164.14/17672.61	eprover: CPU time limit exceeded, terminating
131164.14/17672.61	% SZS status Ended for HL407159+5.p
131172.20/17673.67	% SZS status Started for HL407165+4.p
131172.20/17673.67	% SZS status GaveUp for HL407165+4.p
131172.20/17673.67	eprover: CPU time limit exceeded, terminating
131172.20/17673.67	% SZS status Ended for HL407165+4.p
131185.59/17675.38	% SZS status Started for HL407160+5.p
131185.59/17675.38	% SZS status GaveUp for HL407160+5.p
131185.59/17675.38	eprover: CPU time limit exceeded, terminating
131185.59/17675.38	% SZS status Ended for HL407160+5.p
131188.14/17675.69	% SZS status Started for HL407166+4.p
131188.14/17675.69	% SZS status GaveUp for HL407166+4.p
131188.14/17675.69	eprover: CPU time limit exceeded, terminating
131188.14/17675.69	% SZS status Ended for HL407166+4.p
131196.73/17677.06	% SZS status Started for HL407161+5.p
131196.73/17677.06	% SZS status GaveUp for HL407161+5.p
131196.73/17677.06	eprover: CPU time limit exceeded, terminating
131196.73/17677.06	% SZS status Ended for HL407161+5.p
131207.81/17678.48	% SZS status Started for HL407167+4.p
131207.81/17678.48	% SZS status GaveUp for HL407167+4.p
131207.81/17678.48	eprover: CPU time limit exceeded, terminating
131207.81/17678.48	% SZS status Ended for HL407167+4.p
131209.64/17678.78	% SZS status Started for HL407163+5.p
131209.64/17678.78	% SZS status GaveUp for HL407163+5.p
131209.64/17678.78	eprover: CPU time limit exceeded, terminating
131209.64/17678.78	% SZS status Ended for HL407163+5.p
131221.69/17680.33	% SZS status Started for HL407168+4.p
131221.69/17680.33	% SZS status GaveUp for HL407168+4.p
131221.69/17680.33	eprover: CPU time limit exceeded, terminating
131221.69/17680.33	% SZS status Ended for HL407168+4.p
131235.67/17682.16	% SZS status Started for HL407170+4.p
131235.67/17682.16	% SZS status GaveUp for HL407170+4.p
131235.67/17682.16	eprover: CPU time limit exceeded, terminating
131235.67/17682.16	% SZS status Ended for HL407170+4.p
131238.14/17682.51	% SZS status Started for HL407153+5.p
131238.14/17682.51	% SZS status GaveUp for HL407153+5.p
131238.14/17682.51	eprover: CPU time limit exceeded, terminating
131238.14/17682.51	% SZS status Ended for HL407153+5.p
131241.41/17682.92	% SZS status Started for HL407165+5.p
131241.41/17682.92	% SZS status GaveUp for HL407165+5.p
131241.41/17682.92	eprover: CPU time limit exceeded, terminating
131241.41/17682.92	% SZS status Ended for HL407165+5.p
131259.66/17685.45	% SZS status Started for HL407171+4.p
131259.66/17685.45	% SZS status GaveUp for HL407171+4.p
131259.66/17685.45	eprover: CPU time limit exceeded, terminating
131259.66/17685.45	% SZS status Ended for HL407171+4.p
131263.17/17686.00	% SZS status Started for HL407172+4.p
131263.17/17686.00	% SZS status GaveUp for HL407172+4.p
131263.17/17686.00	eprover: CPU time limit exceeded, terminating
131263.17/17686.00	% SZS status Ended for HL407172+4.p
131263.89/17686.12	% SZS status Started for HL407166+5.p
131263.89/17686.12	% SZS status GaveUp for HL407166+5.p
131263.89/17686.12	eprover: CPU time limit exceeded, terminating
131263.89/17686.12	% SZS status Ended for HL407166+5.p
131267.33/17686.55	% SZS status Started for HL407155+5.p
131267.33/17686.55	% SZS status GaveUp for HL407155+5.p
131267.33/17686.55	eprover: CPU time limit exceeded, terminating
131267.33/17686.55	% SZS status Ended for HL407155+5.p
131286.58/17689.09	% SZS status Started for HL407173+4.p
131286.58/17689.09	% SZS status GaveUp for HL407173+4.p
131286.58/17689.09	eprover: CPU time limit exceeded, terminating
131286.58/17689.09	% SZS status Ended for HL407173+4.p
131288.88/17689.56	% SZS status Started for HL407168+5.p
131288.88/17689.56	% SZS status GaveUp for HL407168+5.p
131288.88/17689.56	eprover: CPU time limit exceeded, terminating
131288.88/17689.56	% SZS status Ended for HL407168+5.p
131289.19/17689.59	% SZS status Started for HL407174+4.p
131289.19/17689.59	% SZS status GaveUp for HL407174+4.p
131289.19/17689.59	eprover: CPU time limit exceeded, terminating
131289.19/17689.59	% SZS status Ended for HL407174+4.p
131305.86/17691.60	% SZS status Started for HL407170+5.p
131305.86/17691.60	% SZS status GaveUp for HL407170+5.p
131305.86/17691.60	eprover: CPU time limit exceeded, terminating
131305.86/17691.60	% SZS status Ended for HL407170+5.p
131314.95/17692.89	% SZS status Started for HL407175+4.p
131314.95/17692.89	% SZS status GaveUp for HL407175+4.p
131314.95/17692.89	eprover: CPU time limit exceeded, terminating
131314.95/17692.89	% SZS status Ended for HL407175+4.p
131320.42/17693.49	% SZS status Started for HL407171+5.p
131320.42/17693.49	% SZS status GaveUp for HL407171+5.p
131320.42/17693.49	eprover: CPU time limit exceeded, terminating
131320.42/17693.49	% SZS status Ended for HL407171+5.p
131329.58/17694.66	% SZS status Started for HL407176+4.p
131329.58/17694.66	% SZS status GaveUp for HL407176+4.p
131329.58/17694.66	eprover: CPU time limit exceeded, terminating
131329.58/17694.66	% SZS status Ended for HL407176+4.p
131343.09/17696.58	% SZS status Started for HL407177+4.p
131343.09/17696.58	% SZS status GaveUp for HL407177+4.p
131343.09/17696.58	eprover: CPU time limit exceeded, terminating
131343.09/17696.58	% SZS status Ended for HL407177+4.p
131344.97/17696.81	% SZS status Started for HL407172+5.p
131344.97/17696.81	% SZS status GaveUp for HL407172+5.p
131344.97/17696.81	eprover: CPU time limit exceeded, terminating
131344.97/17696.81	% SZS status Ended for HL407172+5.p
131346.66/17697.02	% SZS status Started for HL407173+5.p
131346.66/17697.02	% SZS status GaveUp for HL407173+5.p
131346.66/17697.02	eprover: CPU time limit exceeded, terminating
131346.66/17697.02	% SZS status Ended for HL407173+5.p
131366.75/17699.73	% SZS status Started for HL407178+4.p
131366.75/17699.73	% SZS status GaveUp for HL407178+4.p
131366.75/17699.73	eprover: CPU time limit exceeded, terminating
131366.75/17699.73	% SZS status Ended for HL407178+4.p
131367.95/17700.06	% SZS status Started for HL407180+4.p
131367.95/17700.06	% SZS status GaveUp for HL407180+4.p
131367.95/17700.06	eprover: CPU time limit exceeded, terminating
131367.95/17700.06	% SZS status Ended for HL407180+4.p
131372.59/17700.59	% SZS status Started for HL407174+5.p
131372.59/17700.59	% SZS status GaveUp for HL407174+5.p
131372.59/17700.59	eprover: CPU time limit exceeded, terminating
131372.59/17700.59	% SZS status Ended for HL407174+5.p
131373.23/17700.70	% SZS status Started for HL407175+5.p
131373.23/17700.70	% SZS status GaveUp for HL407175+5.p
131373.23/17700.70	eprover: CPU time limit exceeded, terminating
131373.23/17700.70	% SZS status Ended for HL407175+5.p
131395.00/17703.30	% SZS status Started for HL407176+5.p
131395.00/17703.30	% SZS status GaveUp for HL407176+5.p
131395.00/17703.30	eprover: CPU time limit exceeded, terminating
131395.00/17703.30	% SZS status Ended for HL407176+5.p
131395.31/17703.37	% SZS status Started for HL407167+5.p
131395.31/17703.37	% SZS status GaveUp for HL407167+5.p
131395.31/17703.37	eprover: CPU time limit exceeded, terminating
131395.31/17703.37	% SZS status Ended for HL407167+5.p
131414.23/17705.74	% SZS status Started for HL407177+5.p
131414.23/17705.74	% SZS status GaveUp for HL407177+5.p
131414.23/17705.74	eprover: CPU time limit exceeded, terminating
131414.23/17705.74	% SZS status Ended for HL407177+5.p
131427.34/17707.41	% SZS status Started for HL407178+5.p
131427.34/17707.41	% SZS status GaveUp for HL407178+5.p
131427.34/17707.41	eprover: CPU time limit exceeded, terminating
131427.34/17707.41	% SZS status Ended for HL407178+5.p
131452.61/17710.53	% SZS status Started for HL407185+4.p
131452.61/17710.53	% SZS status GaveUp for HL407185+4.p
131452.61/17710.53	eprover: CPU time limit exceeded, terminating
131452.61/17710.53	% SZS status Ended for HL407185+4.p
131457.88/17711.22	% SZS status Started for HL407181+4.p
131457.88/17711.22	% SZS status GaveUp for HL407181+4.p
131457.88/17711.22	eprover: CPU time limit exceeded, terminating
131457.88/17711.22	% SZS status Ended for HL407181+4.p
131461.55/17711.73	% SZS status Started for HL407183+4.p
131461.55/17711.73	% SZS status GaveUp for HL407183+4.p
131461.55/17711.73	eprover: CPU time limit exceeded, terminating
131461.55/17711.73	% SZS status Ended for HL407183+4.p
131484.91/17714.60	% SZS status Started for HL407184+4.p
131484.91/17714.60	% SZS status GaveUp for HL407184+4.p
131484.91/17714.60	eprover: CPU time limit exceeded, terminating
131484.91/17714.60	% SZS status Ended for HL407184+4.p
131546.67/17722.33	% SZS status Started for HL407186+4.p
131546.67/17722.33	% SZS status GaveUp for HL407186+4.p
131546.67/17722.33	eprover: CPU time limit exceeded, terminating
131546.67/17722.33	% SZS status Ended for HL407186+4.p
131572.52/17725.62	% SZS status Started for HL407180+5.p
131572.52/17725.62	% SZS status GaveUp for HL407180+5.p
131572.52/17725.62	eprover: CPU time limit exceeded, terminating
131572.52/17725.62	% SZS status Ended for HL407180+5.p
131573.20/17725.68	% SZS status Started for HL407187+4.p
131573.20/17725.68	% SZS status GaveUp for HL407187+4.p
131573.20/17725.68	eprover: CPU time limit exceeded, terminating
131573.20/17725.68	% SZS status Ended for HL407187+4.p
131578.16/17726.35	% SZS status Started for HL407181+5.p
131578.16/17726.35	% SZS status GaveUp for HL407181+5.p
131578.16/17726.35	eprover: CPU time limit exceeded, terminating
131578.16/17726.35	% SZS status Ended for HL407181+5.p
131596.88/17728.68	% SZS status Started for HL407188+4.p
131596.88/17728.68	% SZS status GaveUp for HL407188+4.p
131596.88/17728.68	eprover: CPU time limit exceeded, terminating
131596.88/17728.68	% SZS status Ended for HL407188+4.p
131599.61/17729.03	% SZS status Started for HL407183+5.p
131599.61/17729.03	% SZS status GaveUp for HL407183+5.p
131599.61/17729.03	eprover: CPU time limit exceeded, terminating
131599.61/17729.03	% SZS status Ended for HL407183+5.p
131619.78/17731.67	% SZS status Started for HL407184+5.p
131619.78/17731.67	% SZS status GaveUp for HL407184+5.p
131619.78/17731.67	eprover: CPU time limit exceeded, terminating
131619.78/17731.67	% SZS status Ended for HL407184+5.p
131623.31/17732.07	% SZS status Started for HL407190+4.p
131623.31/17732.07	% SZS status GaveUp for HL407190+4.p
131623.31/17732.07	eprover: CPU time limit exceeded, terminating
131623.31/17732.07	% SZS status Ended for HL407190+4.p
131657.45/17736.33	% SZS status Started for HL407185+5.p
131657.45/17736.33	% SZS status GaveUp for HL407185+5.p
131657.45/17736.33	eprover: CPU time limit exceeded, terminating
131657.45/17736.33	% SZS status Ended for HL407185+5.p
131666.16/17737.44	% SZS status Started for HL407189+4.p
131666.16/17737.44	% SZS status GaveUp for HL407189+4.p
131666.16/17737.44	eprover: CPU time limit exceeded, terminating
131666.16/17737.44	% SZS status Ended for HL407189+4.p
131670.88/17737.99	% SZS status Started for HL407186+5.p
131670.88/17737.99	% SZS status GaveUp for HL407186+5.p
131670.88/17737.99	eprover: CPU time limit exceeded, terminating
131670.88/17737.99	% SZS status Ended for HL407186+5.p
131691.08/17740.57	% SZS status Started for HL407194+4.p
131691.08/17740.57	% SZS status GaveUp for HL407194+4.p
131691.08/17740.57	eprover: CPU time limit exceeded, terminating
131691.08/17740.57	% SZS status Ended for HL407194+4.p
131712.02/17743.19	% SZS status Started for HL407191+4.p
131712.02/17743.19	% SZS status GaveUp for HL407191+4.p
131712.02/17743.19	eprover: CPU time limit exceeded, terminating
131712.02/17743.19	% SZS status Ended for HL407191+4.p
131715.56/17743.68	% SZS status Started for HL407195+4.p
131715.56/17743.68	% SZS status GaveUp for HL407195+4.p
131715.56/17743.68	eprover: CPU time limit exceeded, terminating
131715.56/17743.68	% SZS status Ended for HL407195+4.p
131741.41/17746.90	% SZS status Started for HL407196+4.p
131741.41/17746.90	% SZS status GaveUp for HL407196+4.p
131741.41/17746.90	eprover: CPU time limit exceeded, terminating
131741.41/17746.90	% SZS status Ended for HL407196+4.p
131752.53/17748.30	% SZS status Started for HL407187+5.p
131752.53/17748.30	% SZS status GaveUp for HL407187+5.p
131752.53/17748.30	eprover: CPU time limit exceeded, terminating
131752.53/17748.30	% SZS status Ended for HL407187+5.p
131777.27/17751.42	% SZS status Started for HL407197+4.p
131777.27/17751.42	% SZS status GaveUp for HL407197+4.p
131777.27/17751.42	eprover: CPU time limit exceeded, terminating
131777.27/17751.42	% SZS status Ended for HL407197+4.p
131778.61/17751.65	% SZS status Started for HL407188+5.p
131778.61/17751.65	% SZS status GaveUp for HL407188+5.p
131778.61/17751.65	eprover: CPU time limit exceeded, terminating
131778.61/17751.65	% SZS status Ended for HL407188+5.p
131793.88/17753.59	% SZS status Started for HL407195+5.p
131793.88/17753.59	% SZS status GaveUp for HL407195+5.p
131793.88/17753.59	eprover: CPU time limit exceeded, terminating
131793.88/17753.59	% SZS status Ended for HL407195+5.p
131802.00/17754.53	% SZS status Started for HL407189+5.p
131802.00/17754.53	% SZS status GaveUp for HL407189+5.p
131802.00/17754.53	eprover: CPU time limit exceeded, terminating
131802.00/17754.53	% SZS status Ended for HL407189+5.p
131826.27/17757.60	% SZS status Started for HL407190+5.p
131826.27/17757.60	% SZS status GaveUp for HL407190+5.p
131826.27/17757.60	eprover: CPU time limit exceeded, terminating
131826.27/17757.60	% SZS status Ended for HL407190+5.p
131826.88/17757.67	% SZS status Started for HL407199+4.p
131826.88/17757.67	% SZS status GaveUp for HL407199+4.p
131826.88/17757.67	eprover: CPU time limit exceeded, terminating
131826.88/17757.67	% SZS status Ended for HL407199+4.p
131851.09/17760.74	% SZS status Started for HL407201+4.p
131851.09/17760.74	% SZS status GaveUp for HL407201+4.p
131851.09/17760.74	eprover: CPU time limit exceeded, terminating
131851.09/17760.74	% SZS status Ended for HL407201+4.p
131863.25/17762.29	% SZS status Started for HL407191+5.p
131863.25/17762.29	% SZS status GaveUp for HL407191+5.p
131863.25/17762.29	eprover: CPU time limit exceeded, terminating
131863.25/17762.29	% SZS status Ended for HL407191+5.p
131867.95/17762.92	% SZS status Started for HL407198+4.p
131867.95/17762.92	% SZS status GaveUp for HL407198+4.p
131867.95/17762.92	eprover: CPU time limit exceeded, terminating
131867.95/17762.92	% SZS status Ended for HL407198+4.p
131876.34/17763.93	% SZS status Started for HL407194+5.p
131876.34/17763.93	% SZS status GaveUp for HL407194+5.p
131876.34/17763.93	eprover: CPU time limit exceeded, terminating
131876.34/17763.93	% SZS status Ended for HL407194+5.p
131887.06/17765.33	% SZS status Started for HL407202+4.p
131887.06/17765.33	% SZS status GaveUp for HL407202+4.p
131887.06/17765.33	eprover: CPU time limit exceeded, terminating
131887.06/17765.33	% SZS status Ended for HL407202+4.p
131901.48/17767.09	% SZS status Started for HL407203+4.p
131901.48/17767.09	% SZS status GaveUp for HL407203+4.p
131901.48/17767.09	eprover: CPU time limit exceeded, terminating
131901.48/17767.09	% SZS status Ended for HL407203+4.p
131925.64/17770.12	% SZS status Started for HL407205+4.p
131925.64/17770.12	% SZS status GaveUp for HL407205+4.p
131925.64/17770.12	eprover: CPU time limit exceeded, terminating
131925.64/17770.12	% SZS status Ended for HL407205+4.p
131948.77/17773.10	% SZS status Started for HL407196+5.p
131948.77/17773.10	% SZS status GaveUp for HL407196+5.p
131948.77/17773.10	eprover: CPU time limit exceeded, terminating
131948.77/17773.10	% SZS status Ended for HL407196+5.p
131981.77/17777.25	% SZS status Started for HL407197+5.p
131981.77/17777.25	% SZS status GaveUp for HL407197+5.p
131981.77/17777.25	eprover: CPU time limit exceeded, terminating
131981.77/17777.25	% SZS status Ended for HL407197+5.p
132000.19/17779.58	% SZS status Started for HL407198+5.p
132000.19/17779.58	% SZS status GaveUp for HL407198+5.p
132000.19/17779.58	eprover: CPU time limit exceeded, terminating
132000.19/17779.58	% SZS status Ended for HL407198+5.p
132031.25/17783.52	% SZS status Started for HL407199+5.p
132031.25/17783.52	% SZS status GaveUp for HL407199+5.p
132031.25/17783.52	eprover: CPU time limit exceeded, terminating
132031.25/17783.52	% SZS status Ended for HL407199+5.p
132036.98/17784.21	% SZS status Started for HL407206+4.p
132036.98/17784.21	% SZS status GaveUp for HL407206+4.p
132036.98/17784.21	eprover: CPU time limit exceeded, terminating
132036.98/17784.21	% SZS status Ended for HL407206+4.p
132056.78/17786.70	% SZS status Started for HL407201+5.p
132056.78/17786.70	% SZS status GaveUp for HL407201+5.p
132056.78/17786.70	eprover: CPU time limit exceeded, terminating
132056.78/17786.70	% SZS status Ended for HL407201+5.p
132061.56/17787.29	% SZS status Started for HL407208+4.p
132061.56/17787.29	% SZS status GaveUp for HL407208+4.p
132061.56/17787.29	eprover: CPU time limit exceeded, terminating
132061.56/17787.29	% SZS status Ended for HL407208+4.p
132073.91/17788.85	% SZS status Started for HL407202+5.p
132073.91/17788.85	% SZS status GaveUp for HL407202+5.p
132073.91/17788.85	eprover: CPU time limit exceeded, terminating
132073.91/17788.85	% SZS status Ended for HL407202+5.p
132085.73/17790.34	% SZS status Started for HL407209+4.p
132085.73/17790.34	% SZS status GaveUp for HL407209+4.p
132085.73/17790.34	eprover: CPU time limit exceeded, terminating
132085.73/17790.34	% SZS status Ended for HL407209+4.p
132089.20/17790.82	% SZS status Started for HL407207+4.p
132089.20/17790.82	% SZS status GaveUp for HL407207+4.p
132089.20/17790.82	eprover: CPU time limit exceeded, terminating
132089.20/17790.82	% SZS status Ended for HL407207+4.p
132094.02/17791.50	% SZS status Started for HL407203+5.p
132094.02/17791.50	% SZS status GaveUp for HL407203+5.p
132094.02/17791.50	eprover: CPU time limit exceeded, terminating
132094.02/17791.50	% SZS status Ended for HL407203+5.p
132118.58/17794.53	% SZS status Started for HL407212+4.p
132118.58/17794.53	% SZS status GaveUp for HL407212+4.p
132118.58/17794.53	eprover: CPU time limit exceeded, terminating
132118.58/17794.53	% SZS status Ended for HL407212+4.p
132133.30/17796.36	% SZS status Started for HL407205+5.p
132133.30/17796.36	% SZS status GaveUp for HL407205+5.p
132133.30/17796.36	eprover: CPU time limit exceeded, terminating
132133.30/17796.36	% SZS status Ended for HL407205+5.p
132156.08/17799.21	% SZS status Started for HL407209+5.p
132156.08/17799.21	% SZS status GaveUp for HL407209+5.p
132156.08/17799.21	eprover: CPU time limit exceeded, terminating
132156.08/17799.21	% SZS status Ended for HL407209+5.p
132174.38/17801.55	% SZS status Started for HL407210+4.p
132174.38/17801.55	% SZS status GaveUp for HL407210+4.p
132174.38/17801.55	eprover: CPU time limit exceeded, terminating
132174.38/17801.55	% SZS status Ended for HL407210+4.p
132190.97/17803.65	% SZS status Started for HL407206+5.p
132190.97/17803.65	% SZS status GaveUp for HL407206+5.p
132190.97/17803.65	eprover: CPU time limit exceeded, terminating
132190.97/17803.65	% SZS status Ended for HL407206+5.p
132198.92/17804.59	% SZS status Started for HL407214+4.p
132198.92/17804.59	% SZS status GaveUp for HL407214+4.p
132198.92/17804.59	eprover: CPU time limit exceeded, terminating
132198.92/17804.59	% SZS status Ended for HL407214+4.p
132222.95/17807.60	% SZS status Started for HL407213+4.p
132222.95/17807.60	% SZS status GaveUp for HL407213+4.p
132222.95/17807.60	eprover: CPU time limit exceeded, terminating
132222.95/17807.60	% SZS status Ended for HL407213+4.p
132222.95/17807.63	% SZS status Started for HL407215+4.p
132222.95/17807.63	% SZS status GaveUp for HL407215+4.p
132222.95/17807.63	eprover: CPU time limit exceeded, terminating
132222.95/17807.63	% SZS status Ended for HL407215+4.p
132236.50/17809.35	% SZS status Started for HL407207+5.p
132236.50/17809.35	% SZS status GaveUp for HL407207+5.p
132236.50/17809.35	eprover: CPU time limit exceeded, terminating
132236.50/17809.35	% SZS status Ended for HL407207+5.p
132247.33/17810.76	% SZS status Started for HL407216+4.p
132247.33/17810.76	% SZS status GaveUp for HL407216+4.p
132247.33/17810.76	eprover: CPU time limit exceeded, terminating
132247.33/17810.76	% SZS status Ended for HL407216+4.p
132262.02/17812.59	% SZS status Started for HL407208+5.p
132262.02/17812.59	% SZS status GaveUp for HL407208+5.p
132262.02/17812.59	eprover: CPU time limit exceeded, terminating
132262.02/17812.59	% SZS status Ended for HL407208+5.p
132272.77/17813.91	% SZS status Started for HL407217+4.p
132272.77/17813.91	% SZS status GaveUp for HL407217+4.p
132272.77/17813.91	eprover: CPU time limit exceeded, terminating
132272.77/17813.91	% SZS status Ended for HL407217+4.p
132294.55/17816.68	% SZS status Started for HL407210+5.p
132294.55/17816.68	% SZS status GaveUp for HL407210+5.p
132294.55/17816.68	eprover: CPU time limit exceeded, terminating
132294.55/17816.68	% SZS status Ended for HL407210+5.p
132324.53/17820.41	% SZS status Started for HL407212+5.p
132324.53/17820.41	% SZS status GaveUp for HL407212+5.p
132324.53/17820.41	eprover: CPU time limit exceeded, terminating
132324.53/17820.41	% SZS status Ended for HL407212+5.p
132359.84/17824.92	% SZS status Started for HL407213+5.p
132359.84/17824.92	% SZS status GaveUp for HL407213+5.p
132359.84/17824.92	eprover: CPU time limit exceeded, terminating
132359.84/17824.92	% SZS status Ended for HL407213+5.p
132361.03/17825.01	% SZS status Started for HL407218+4.p
132361.03/17825.01	% SZS status GaveUp for HL407218+4.p
132361.03/17825.01	eprover: CPU time limit exceeded, terminating
132361.03/17825.01	% SZS status Ended for HL407218+4.p
132395.78/17829.43	% SZS status Started for HL407214+5.p
132395.78/17829.43	% SZS status GaveUp for HL407214+5.p
132395.78/17829.43	eprover: CPU time limit exceeded, terminating
132395.78/17829.43	% SZS status Ended for HL407214+5.p
132412.66/17831.50	% SZS status Started for HL407219+4.p
132412.66/17831.50	% SZS status GaveUp for HL407219+4.p
132412.66/17831.50	eprover: CPU time limit exceeded, terminating
132412.66/17831.50	% SZS status Ended for HL407219+4.p
132427.50/17833.42	% SZS status Started for HL407215+5.p
132427.50/17833.42	% SZS status GaveUp for HL407215+5.p
132427.50/17833.42	eprover: CPU time limit exceeded, terminating
132427.50/17833.42	% SZS status Ended for HL407215+5.p
132437.28/17834.58	% SZS status Started for HL407222+4.p
132437.28/17834.58	% SZS status GaveUp for HL407222+4.p
132437.28/17834.58	eprover: CPU time limit exceeded, terminating
132437.28/17834.58	% SZS status Ended for HL407222+4.p
132442.38/17835.30	% SZS status Started for HL407216+5.p
132442.38/17835.30	% SZS status GaveUp for HL407216+5.p
132442.38/17835.30	eprover: CPU time limit exceeded, terminating
132442.38/17835.30	% SZS status Ended for HL407216+5.p
132442.38/17835.31	% SZS status Started for HL407219+5.p
132442.38/17835.31	% SZS status GaveUp for HL407219+5.p
132442.38/17835.31	eprover: CPU time limit exceeded, terminating
132442.38/17835.31	% SZS status Ended for HL407219+5.p
132449.08/17836.08	% SZS status Started for HL407220+4.p
132449.08/17836.08	% SZS status GaveUp for HL407220+4.p
132449.08/17836.08	eprover: CPU time limit exceeded, terminating
132449.08/17836.08	% SZS status Ended for HL407220+4.p
132472.19/17838.96	% SZS status Started for HL407217+5.p
132472.19/17838.96	% SZS status GaveUp for HL407217+5.p
132472.19/17838.96	eprover: CPU time limit exceeded, terminating
132472.19/17838.96	% SZS status Ended for HL407217+5.p
132500.50/17842.55	% SZS status Started for HL407218+5.p
132500.50/17842.55	% SZS status GaveUp for HL407218+5.p
132500.50/17842.55	eprover: CPU time limit exceeded, terminating
132500.50/17842.55	% SZS status Ended for HL407218+5.p
132525.92/17845.75	% SZS status Started for HL407223+4.p
132525.92/17845.75	% SZS status GaveUp for HL407223+4.p
132525.92/17845.75	eprover: CPU time limit exceeded, terminating
132525.92/17845.75	% SZS status Ended for HL407223+4.p
132530.31/17846.32	% SZS status Started for HL407225+4.p
132530.31/17846.32	% SZS status GaveUp for HL407225+4.p
132530.31/17846.32	eprover: CPU time limit exceeded, terminating
132530.31/17846.32	% SZS status Ended for HL407225+4.p
132560.44/17850.15	% SZS status Started for HL407227+4.p
132560.44/17850.15	% SZS status GaveUp for HL407227+4.p
132560.44/17850.15	eprover: CPU time limit exceeded, terminating
132560.44/17850.15	% SZS status Ended for HL407227+4.p
132603.38/17855.31	% SZS status Started for HL407220+5.p
132603.38/17855.31	% SZS status GaveUp for HL407220+5.p
132603.38/17855.31	eprover: CPU time limit exceeded, terminating
132603.38/17855.31	% SZS status Ended for HL407220+5.p
132641.92/17856.99	% SZS status Started for HL407229+4.p
132641.92/17856.99	% SZS status GaveUp for HL407229+4.p
132641.92/17856.99	eprover: CPU time limit exceeded, terminating
132641.92/17856.99	% SZS status Ended for HL407229+4.p
132660.42/17859.35	% SZS status Started for HL407222+5.p
132660.42/17859.35	% SZS status GaveUp for HL407222+5.p
132660.42/17859.35	eprover: CPU time limit exceeded, terminating
132660.42/17859.35	% SZS status Ended for HL407222+5.p
132666.22/17860.03	% SZS status Started for HL407232+4.p
132666.22/17860.03	% SZS status GaveUp for HL407232+4.p
132666.22/17860.03	eprover: CPU time limit exceeded, terminating
132666.22/17860.03	% SZS status Ended for HL407232+4.p
132675.03/17861.11	% SZS status Started for HL407223+5.p
132675.03/17861.11	% SZS status GaveUp for HL407223+5.p
132675.03/17861.11	eprover: CPU time limit exceeded, terminating
132675.03/17861.11	% SZS status Ended for HL407223+5.p
132675.73/17861.27	% SZS status Started for HL407230+4.p
132675.73/17861.27	% SZS status GaveUp for HL407230+4.p
132675.73/17861.27	eprover: CPU time limit exceeded, terminating
132675.73/17861.27	% SZS status Ended for HL407230+4.p
132681.52/17862.00	% SZS status Started for HL407225+5.p
132681.52/17862.00	% SZS status GaveUp for HL407225+5.p
132681.52/17862.00	eprover: CPU time limit exceeded, terminating
132681.52/17862.00	% SZS status Ended for HL407225+5.p
132700.20/17864.30	% SZS status Started for HL407235+4.p
132700.20/17864.30	% SZS status GaveUp for HL407235+4.p
132700.20/17864.30	eprover: CPU time limit exceeded, terminating
132700.20/17864.30	% SZS status Ended for HL407235+4.p
132725.16/17867.44	% SZS status Started for HL407236+4.p
132725.16/17867.44	% SZS status GaveUp for HL407236+4.p
132725.16/17867.44	eprover: CPU time limit exceeded, terminating
132725.16/17867.44	% SZS status Ended for HL407236+4.p
132731.66/17868.32	% SZS status Started for HL407227+5.p
132731.66/17868.32	% SZS status GaveUp for HL407227+5.p
132731.66/17868.32	eprover: CPU time limit exceeded, terminating
132731.66/17868.32	% SZS status Ended for HL407227+5.p
132754.17/17871.09	% SZS status Started for HL407234+4.p
132754.17/17871.09	% SZS status GaveUp for HL407234+4.p
132754.17/17871.09	eprover: CPU time limit exceeded, terminating
132754.17/17871.09	% SZS status Ended for HL407234+4.p
132762.27/17872.16	% SZS status Started for HL407229+5.p
132762.27/17872.16	% SZS status GaveUp for HL407229+5.p
132762.27/17872.16	eprover: CPU time limit exceeded, terminating
132762.27/17872.16	% SZS status Ended for HL407229+5.p
132805.95/17877.59	% SZS status Started for HL407237+4.p
132805.95/17877.59	% SZS status GaveUp for HL407237+4.p
132805.95/17877.59	eprover: CPU time limit exceeded, terminating
132805.95/17877.59	% SZS status Ended for HL407237+4.p
132834.61/17881.18	% SZS status Started for HL407230+5.p
132834.61/17881.18	% SZS status GaveUp for HL407230+5.p
132834.61/17881.18	eprover: CPU time limit exceeded, terminating
132834.61/17881.18	% SZS status Ended for HL407230+5.p
132850.92/17883.28	% SZS status Started for HL407239+4.p
132850.92/17883.28	% SZS status GaveUp for HL407239+4.p
132850.92/17883.28	eprover: CPU time limit exceeded, terminating
132850.92/17883.28	% SZS status Ended for HL407239+4.p
132858.31/17884.23	% SZS status Started for HL407240+4.p
132858.31/17884.23	% SZS status GaveUp for HL407240+4.p
132858.31/17884.23	eprover: CPU time limit exceeded, terminating
132858.31/17884.23	% SZS status Ended for HL407240+4.p
132867.59/17885.38	% SZS status Started for HL407232+5.p
132867.59/17885.38	% SZS status GaveUp for HL407232+5.p
132867.59/17885.38	eprover: CPU time limit exceeded, terminating
132867.59/17885.38	% SZS status Ended for HL407232+5.p
132881.50/17887.08	% SZS status Started for HL407234+5.p
132881.50/17887.08	% SZS status GaveUp for HL407234+5.p
132881.50/17887.08	eprover: CPU time limit exceeded, terminating
132881.50/17887.08	% SZS status Ended for HL407234+5.p
132882.56/17887.28	% SZS status Started for HL407241+4.p
132882.56/17887.28	% SZS status GaveUp for HL407241+4.p
132882.56/17887.28	eprover: CPU time limit exceeded, terminating
132882.56/17887.28	% SZS status Ended for HL407241+4.p
132887.69/17887.94	% SZS status Started for HL407235+5.p
132887.69/17887.94	% SZS status GaveUp for HL407235+5.p
132887.69/17887.94	eprover: CPU time limit exceeded, terminating
132887.69/17887.94	% SZS status Ended for HL407235+5.p
132930.72/17890.11	% SZS status Started for HL407244+4.p
132930.72/17890.11	% SZS status GaveUp for HL407244+4.p
132930.72/17890.11	eprover: CPU time limit exceeded, terminating
132930.72/17890.11	% SZS status Ended for HL407244+4.p
132956.00/17893.34	% SZS status Started for HL407236+5.p
132956.00/17893.34	% SZS status GaveUp for HL407236+5.p
132956.00/17893.34	eprover: CPU time limit exceeded, terminating
132956.00/17893.34	% SZS status Ended for HL407236+5.p
132980.20/17896.38	% SZS status Started for HL407246+4.p
132980.20/17896.38	% SZS status GaveUp for HL407246+4.p
132980.20/17896.38	eprover: CPU time limit exceeded, terminating
132980.20/17896.38	% SZS status Ended for HL407246+4.p
132985.80/17897.08	% SZS status Started for HL407237+5.p
132985.80/17897.08	% SZS status GaveUp for HL407237+5.p
132985.80/17897.08	eprover: CPU time limit exceeded, terminating
132985.80/17897.08	% SZS status Ended for HL407237+5.p
133001.86/17899.14	% SZS status Started for HL407245+4.p
133001.86/17899.14	% SZS status GaveUp for HL407245+4.p
133001.86/17899.14	eprover: CPU time limit exceeded, terminating
133001.86/17899.14	% SZS status Ended for HL407245+4.p
133010.62/17900.20	% SZS status Started for HL407247+4.p
133010.62/17900.20	% SZS status GaveUp for HL407247+4.p
133010.62/17900.20	eprover: CPU time limit exceeded, terminating
133010.62/17900.20	% SZS status Ended for HL407247+4.p
133034.95/17903.27	% SZS status Started for HL407248+4.p
133034.95/17903.27	% SZS status GaveUp for HL407248+4.p
133034.95/17903.27	eprover: CPU time limit exceeded, terminating
133034.95/17903.27	% SZS status Ended for HL407248+4.p
133037.34/17903.56	% SZS status Started for HL407239+5.p
133037.34/17903.56	% SZS status GaveUp for HL407239+5.p
133037.34/17903.56	eprover: CPU time limit exceeded, terminating
133037.34/17903.56	% SZS status Ended for HL407239+5.p
133082.31/17909.24	% SZS status Started for HL407240+5.p
133082.31/17909.24	% SZS status GaveUp for HL407240+5.p
133082.31/17909.24	eprover: CPU time limit exceeded, terminating
133082.31/17909.24	% SZS status Ended for HL407240+5.p
133099.73/17911.44	% SZS status Started for HL407241+5.p
133099.73/17911.44	% SZS status GaveUp for HL407241+5.p
133099.73/17911.44	eprover: CPU time limit exceeded, terminating
133099.73/17911.44	% SZS status Ended for HL407241+5.p
133112.75/17913.19	% SZS status Started for HL407244+5.p
133112.75/17913.19	% SZS status GaveUp for HL407244+5.p
133112.75/17913.19	eprover: CPU time limit exceeded, terminating
133112.75/17913.19	% SZS status Ended for HL407244+5.p
133124.27/17914.52	% SZS status Started for HL407252+4.p
133124.27/17914.52	% SZS status GaveUp for HL407252+4.p
133124.27/17914.52	eprover: CPU time limit exceeded, terminating
133124.27/17914.52	% SZS status Ended for HL407252+4.p
133125.41/17914.71	% SZS status Started for HL407251+4.p
133125.41/17914.71	% SZS status GaveUp for HL407251+4.p
133125.41/17914.71	eprover: CPU time limit exceeded, terminating
133125.41/17914.71	% SZS status Ended for HL407251+4.p
133135.69/17915.98	% SZS status Started for HL407245+5.p
133135.69/17915.98	% SZS status GaveUp for HL407245+5.p
133135.69/17915.98	eprover: CPU time limit exceeded, terminating
133135.69/17915.98	% SZS status Ended for HL407245+5.p
133148.83/17917.59	% SZS status Started for HL407253+4.p
133148.83/17917.59	% SZS status GaveUp for HL407253+4.p
133148.83/17917.59	eprover: CPU time limit exceeded, terminating
133148.83/17917.59	% SZS status Ended for HL407253+4.p
133184.72/17922.20	% SZS status Started for HL407246+5.p
133184.72/17922.20	% SZS status GaveUp for HL407246+5.p
133184.72/17922.20	eprover: CPU time limit exceeded, terminating
133184.72/17922.20	% SZS status Ended for HL407246+5.p
133208.06/17925.08	% SZS status Started for HL407247+5.p
133208.06/17925.08	% SZS status GaveUp for HL407247+5.p
133208.06/17925.08	eprover: CPU time limit exceeded, terminating
133208.06/17925.08	% SZS status Ended for HL407247+5.p
133209.44/17925.31	% SZS status Started for HL407258+4.p
133209.44/17925.31	% SZS status GaveUp for HL407258+4.p
133209.44/17925.31	eprover: CPU time limit exceeded, terminating
133209.44/17925.31	% SZS status Ended for HL407258+4.p
133224.81/17927.19	% SZS status Started for HL407254+4.p
133224.81/17927.19	% SZS status GaveUp for HL407254+4.p
133224.81/17927.19	eprover: CPU time limit exceeded, terminating
133224.81/17927.19	% SZS status Ended for HL407254+4.p
133234.94/17928.47	% SZS status Started for HL407260+4.p
133234.94/17928.47	% SZS status GaveUp for HL407260+4.p
133234.94/17928.47	eprover: CPU time limit exceeded, terminating
133234.94/17928.47	% SZS status Ended for HL407260+4.p
133239.75/17929.04	% SZS status Started for HL407248+5.p
133239.75/17929.04	% SZS status GaveUp for HL407248+5.p
133239.75/17929.04	eprover: CPU time limit exceeded, terminating
133239.75/17929.04	% SZS status Ended for HL407248+5.p
133288.41/17935.19	% SZS status Started for HL407251+5.p
133288.41/17935.19	% SZS status GaveUp for HL407251+5.p
133288.41/17935.19	eprover: CPU time limit exceeded, terminating
133288.41/17935.19	% SZS status Ended for HL407251+5.p
133318.16/17938.98	% SZS status Started for HL407252+5.p
133318.16/17938.98	% SZS status GaveUp for HL407252+5.p
133318.16/17938.98	eprover: CPU time limit exceeded, terminating
133318.16/17938.98	% SZS status Ended for HL407252+5.p
133324.25/17939.67	% SZS status Started for HL407261+4.p
133324.25/17939.67	% SZS status GaveUp for HL407261+4.p
133324.25/17939.67	eprover: CPU time limit exceeded, terminating
133324.25/17939.67	% SZS status Ended for HL407261+4.p
133333.02/17940.79	% SZS status Started for HL407253+5.p
133333.02/17940.79	% SZS status GaveUp for HL407253+5.p
133333.02/17940.79	eprover: CPU time limit exceeded, terminating
133333.02/17940.79	% SZS status Ended for HL407253+5.p
133353.33/17943.38	% SZS status Started for HL407254+5.p
133353.33/17943.38	% SZS status GaveUp for HL407254+5.p
133353.33/17943.38	eprover: CPU time limit exceeded, terminating
133353.33/17943.38	% SZS status Ended for HL407254+5.p
133377.00/17946.37	% SZS status Started for HL407262+4.p
133377.00/17946.37	% SZS status GaveUp for HL407262+4.p
133377.00/17946.37	eprover: CPU time limit exceeded, terminating
133377.00/17946.37	% SZS status Ended for HL407262+4.p
133377.61/17946.44	% SZS status Started for HL407264+4.p
133377.61/17946.44	% SZS status GaveUp for HL407264+4.p
133377.61/17946.44	eprover: CPU time limit exceeded, terminating
133377.61/17946.44	% SZS status Ended for HL407264+4.p
133413.67/17950.92	% SZS status Started for HL407258+5.p
133413.67/17950.92	% SZS status GaveUp for HL407258+5.p
133413.67/17950.92	eprover: CPU time limit exceeded, terminating
133413.67/17950.92	% SZS status Ended for HL407258+5.p
133413.97/17951.00	% SZS status Started for HL407263+4.p
133413.97/17951.00	% SZS status GaveUp for HL407263+4.p
133413.97/17951.00	eprover: CPU time limit exceeded, terminating
133413.97/17951.00	% SZS status Ended for HL407263+4.p
133429.09/17953.02	% SZS status Started for HL407260+5.p
133429.09/17953.02	% SZS status GaveUp for HL407260+5.p
133429.09/17953.02	eprover: CPU time limit exceeded, terminating
133429.09/17953.02	% SZS status Ended for HL407260+5.p
133446.23/17955.05	% SZS status Started for HL407261+5.p
133446.23/17955.05	% SZS status GaveUp for HL407261+5.p
133446.23/17955.05	eprover: CPU time limit exceeded, terminating
133446.23/17955.05	% SZS status Ended for HL407261+5.p
133467.12/17957.64	% SZS status Started for HL407265+4.p
133467.12/17957.64	% SZS status GaveUp for HL407265+4.p
133467.12/17957.64	eprover: CPU time limit exceeded, terminating
133467.12/17957.64	% SZS status Ended for HL407265+4.p
133471.52/17958.21	% SZS status Started for HL407267+4.p
133471.52/17958.21	% SZS status GaveUp for HL407267+4.p
133471.52/17958.21	eprover: CPU time limit exceeded, terminating
133471.52/17958.21	% SZS status Ended for HL407267+4.p
133495.42/17961.27	% SZS status Started for HL407268+4.p
133495.42/17961.27	% SZS status GaveUp for HL407268+4.p
133495.42/17961.27	eprover: CPU time limit exceeded, terminating
133495.42/17961.27	% SZS status Ended for HL407268+4.p
133502.83/17962.14	% SZS status Started for HL407266+4.p
133502.83/17962.14	% SZS status GaveUp for HL407266+4.p
133502.83/17962.14	eprover: CPU time limit exceeded, terminating
133502.83/17962.14	% SZS status Ended for HL407266+4.p
133524.23/17964.84	% SZS status Started for HL407262+5.p
133524.23/17964.84	% SZS status GaveUp for HL407262+5.p
133524.23/17964.84	eprover: CPU time limit exceeded, terminating
133524.23/17964.84	% SZS status Ended for HL407262+5.p
133526.50/17965.20	% SZS status Started for HL407269+4.p
133526.50/17965.20	% SZS status GaveUp for HL407269+4.p
133526.50/17965.20	eprover: CPU time limit exceeded, terminating
133526.50/17965.20	% SZS status Ended for HL407269+4.p
133537.56/17966.53	% SZS status Started for HL407263+5.p
133537.56/17966.53	% SZS status GaveUp for HL407263+5.p
133537.56/17966.53	eprover: CPU time limit exceeded, terminating
133537.56/17966.53	% SZS status Ended for HL407263+5.p
133584.34/17972.49	% SZS status Started for HL407264+5.p
133584.34/17972.49	% SZS status GaveUp for HL407264+5.p
133584.34/17972.49	eprover: CPU time limit exceeded, terminating
133584.34/17972.49	% SZS status Ended for HL407264+5.p
133615.45/17976.30	% SZS status Started for HL407270+4.p
133615.45/17976.30	% SZS status GaveUp for HL407270+4.p
133615.45/17976.30	eprover: CPU time limit exceeded, terminating
133615.45/17976.30	% SZS status Ended for HL407270+4.p
133623.45/17977.36	% SZS status Started for HL407265+5.p
133623.45/17977.36	% SZS status GaveUp for HL407265+5.p
133623.45/17977.36	eprover: CPU time limit exceeded, terminating
133623.45/17977.36	% SZS status Ended for HL407265+5.p
133635.58/17978.86	% SZS status Started for HL407266+5.p
133635.58/17978.86	% SZS status GaveUp for HL407266+5.p
133635.58/17978.86	eprover: CPU time limit exceeded, terminating
133635.58/17978.86	% SZS status Ended for HL407266+5.p
133648.25/17980.42	% SZS status Started for HL407272+4.p
133648.25/17980.42	% SZS status GaveUp for HL407272+4.p
133648.25/17980.42	eprover: CPU time limit exceeded, terminating
133648.25/17980.42	% SZS status Ended for HL407272+4.p
133673.50/17983.62	% SZS status Started for HL407271+4.p
133673.50/17983.62	% SZS status GaveUp for HL407271+4.p
133673.50/17983.62	eprover: CPU time limit exceeded, terminating
133673.50/17983.62	% SZS status Ended for HL407271+4.p
133675.75/17983.94	% SZS status Started for HL407267+5.p
133675.75/17983.94	% SZS status GaveUp for HL407267+5.p
133675.75/17983.94	eprover: CPU time limit exceeded, terminating
133675.75/17983.94	% SZS status Ended for HL407267+5.p
133699.88/17986.98	% SZS status Started for HL407274+4.p
133699.88/17986.98	% SZS status GaveUp for HL407274+4.p
133699.88/17986.98	eprover: CPU time limit exceeded, terminating
133699.88/17986.98	% SZS status Ended for HL407274+4.p
133699.88/17987.01	% SZS status Started for HL407268+5.p
133699.88/17987.01	% SZS status GaveUp for HL407268+5.p
133699.88/17987.01	eprover: CPU time limit exceeded, terminating
133699.88/17987.01	% SZS status Ended for HL407268+5.p
133729.12/17990.62	% SZS status Started for HL407269+5.p
133729.12/17990.62	% SZS status GaveUp for HL407269+5.p
133729.12/17990.62	eprover: CPU time limit exceeded, terminating
133729.12/17990.62	% SZS status Ended for HL407269+5.p
133736.19/17991.57	% SZS status Started for HL407273+4.p
133736.19/17991.57	% SZS status GaveUp for HL407273+4.p
133736.19/17991.57	eprover: CPU time limit exceeded, terminating
133736.19/17991.57	% SZS status Ended for HL407273+4.p
133745.05/17992.61	% SZS status Started for HL407270+5.p
133745.05/17992.61	% SZS status GaveUp for HL407270+5.p
133745.05/17992.61	eprover: CPU time limit exceeded, terminating
133745.05/17992.61	% SZS status Ended for HL407270+5.p
133760.91/17994.71	% SZS status Started for HL407277+4.p
133760.91/17994.71	% SZS status GaveUp for HL407277+4.p
133760.91/17994.71	eprover: CPU time limit exceeded, terminating
133760.91/17994.71	% SZS status Ended for HL407277+4.p
133788.61/17998.09	% SZS status Started for HL407275+4.p
133788.61/17998.09	% SZS status GaveUp for HL407275+4.p
133788.61/17998.09	eprover: CPU time limit exceeded, terminating
133788.61/17998.09	% SZS status Ended for HL407275+4.p
133810.59/18000.89	% SZS status Started for HL407275+5.p
133810.59/18000.89	% SZS status GaveUp for HL407275+5.p
133810.59/18000.89	eprover: CPU time limit exceeded, terminating
133810.59/18000.89	% SZS status Ended for HL407275+5.p
133820.78/18002.14	% SZS status Started for HL407271+5.p
133820.78/18002.14	% SZS status GaveUp for HL407271+5.p
133820.78/18002.14	eprover: CPU time limit exceeded, terminating
133820.78/18002.14	% SZS status Ended for HL407271+5.p
133834.36/18003.94	% SZS status Started for HL407280+4.p
133834.36/18003.94	% SZS status GaveUp for HL407280+4.p
133834.36/18003.94	eprover: CPU time limit exceeded, terminating
133834.36/18003.94	% SZS status Ended for HL407280+4.p
133843.02/18004.94	% SZS status Started for HL407272+5.p
133843.02/18004.94	% SZS status GaveUp for HL407272+5.p
133843.02/18004.94	eprover: CPU time limit exceeded, terminating
133843.02/18004.94	% SZS status Ended for HL407272+5.p
133850.08/18005.83	% SZS status Started for HL407279+4.p
133850.08/18005.83	% SZS status GaveUp for HL407279+4.p
133850.08/18005.83	eprover: CPU time limit exceeded, terminating
133850.08/18005.83	% SZS status Ended for HL407279+4.p
133873.86/18008.85	% SZS status Started for HL407283+4.p
133873.86/18008.85	% SZS status GaveUp for HL407283+4.p
133873.86/18008.85	eprover: CPU time limit exceeded, terminating
133873.86/18008.85	% SZS status Ended for HL407283+4.p
133875.38/18009.02	% SZS status Started for HL407282+4.p
133875.38/18009.02	% SZS status GaveUp for HL407282+4.p
133875.38/18009.02	eprover: CPU time limit exceeded, terminating
133875.38/18009.02	% SZS status Ended for HL407282+4.p
133878.69/18009.43	% SZS status Started for HL407273+5.p
133878.69/18009.43	% SZS status GaveUp for HL407273+5.p
133878.69/18009.43	eprover: CPU time limit exceeded, terminating
133878.69/18009.43	% SZS status Ended for HL407273+5.p
133905.09/18012.74	% SZS status Started for HL407274+5.p
133905.09/18012.74	% SZS status GaveUp for HL407274+5.p
133905.09/18012.74	eprover: CPU time limit exceeded, terminating
133905.09/18012.74	% SZS status Ended for HL407274+5.p
133929.31/18015.78	% SZS status Started for HL407286+4.p
133929.31/18015.78	% SZS status GaveUp for HL407286+4.p
133929.31/18015.78	eprover: CPU time limit exceeded, terminating
133929.31/18015.78	% SZS status Ended for HL407286+4.p
133949.47/18018.44	% SZS status Started for HL407277+5.p
133949.47/18018.44	% SZS status GaveUp for HL407277+5.p
133949.47/18018.44	eprover: CPU time limit exceeded, terminating
133949.47/18018.44	% SZS status Ended for HL407277+5.p
133963.11/18020.09	% SZS status Started for HL407285+4.p
133963.11/18020.09	% SZS status GaveUp for HL407285+4.p
133963.11/18020.09	eprover: CPU time limit exceeded, terminating
133963.11/18020.09	% SZS status Ended for HL407285+4.p
133974.61/18021.47	% SZS status Started for HL407288+4.p
133974.61/18021.47	% SZS status GaveUp for HL407288+4.p
133974.61/18021.47	eprover: CPU time limit exceeded, terminating
133974.61/18021.47	% SZS status Ended for HL407288+4.p
133995.92/18024.22	% SZS status Started for HL407279+5.p
133995.92/18024.22	% SZS status GaveUp for HL407279+5.p
133995.92/18024.22	eprover: CPU time limit exceeded, terminating
133995.92/18024.22	% SZS status Ended for HL407279+5.p
134007.06/18025.57	% SZS status Started for HL407289+4.p
134007.06/18025.57	% SZS status GaveUp for HL407289+4.p
134007.06/18025.57	eprover: CPU time limit exceeded, terminating
134007.06/18025.57	% SZS status Ended for HL407289+4.p
134027.78/18028.21	% SZS status Started for HL407280+5.p
134027.78/18028.21	% SZS status GaveUp for HL407280+5.p
134027.78/18028.21	eprover: CPU time limit exceeded, terminating
134027.78/18028.21	% SZS status Ended for HL407280+5.p
134030.81/18028.62	% SZS status Started for HL407290+4.p
134030.81/18028.62	% SZS status GaveUp for HL407290+4.p
134030.81/18028.62	eprover: CPU time limit exceeded, terminating
134030.81/18028.62	% SZS status Ended for HL407290+4.p
134049.39/18030.94	% SZS status Started for HL407282+5.p
134049.39/18030.94	% SZS status GaveUp for HL407282+5.p
134049.39/18030.94	eprover: CPU time limit exceeded, terminating
134049.39/18030.94	% SZS status Ended for HL407282+5.p
134056.30/18031.77	% SZS status Started for HL407291+4.p
134056.30/18031.77	% SZS status GaveUp for HL407291+4.p
134056.30/18031.77	eprover: CPU time limit exceeded, terminating
134056.30/18031.77	% SZS status Ended for HL407291+4.p
134080.84/18034.87	% SZS status Started for HL407283+5.p
134080.84/18034.87	% SZS status GaveUp for HL407283+5.p
134080.84/18034.87	eprover: CPU time limit exceeded, terminating
134080.84/18034.87	% SZS status Ended for HL407283+5.p
134080.84/18034.90	% SZS status Started for HL407293+4.p
134080.84/18034.90	% SZS status GaveUp for HL407293+4.p
134080.84/18034.90	eprover: CPU time limit exceeded, terminating
134080.84/18034.90	% SZS status Ended for HL407293+4.p
134082.52/18035.20	% SZS status Started for HL407285+5.p
134082.52/18035.20	% SZS status GaveUp for HL407285+5.p
134082.52/18035.20	eprover: CPU time limit exceeded, terminating
134082.52/18035.20	% SZS status Ended for HL407285+5.p
134108.16/18038.42	% SZS status Started for HL407290+5.p
134108.16/18038.42	% SZS status GaveUp for HL407290+5.p
134108.16/18038.42	eprover: CPU time limit exceeded, terminating
134108.16/18038.42	% SZS status Ended for HL407290+5.p
134136.50/18041.91	% SZS status Started for HL407286+5.p
134136.50/18041.91	% SZS status GaveUp for HL407286+5.p
134136.50/18041.91	eprover: CPU time limit exceeded, terminating
134136.50/18041.91	% SZS status Ended for HL407286+5.p
134168.80/18045.96	% SZS status Started for HL407294+5.p
134168.80/18045.96	% SZS status GaveUp for HL407294+5.p
134168.80/18045.96	eprover: CPU time limit exceeded, terminating
134168.80/18045.96	% SZS status Ended for HL407294+5.p
134168.80/18046.04	% SZS status Started for HL407294+4.p
134168.80/18046.04	% SZS status GaveUp for HL407294+4.p
134168.80/18046.04	eprover: CPU time limit exceeded, terminating
134168.80/18046.04	% SZS status Ended for HL407294+4.p
134169.58/18046.07	% SZS status Started for HL407288+5.p
134169.58/18046.07	% SZS status GaveUp for HL407288+5.p
134169.58/18046.07	eprover: CPU time limit exceeded, terminating
134169.58/18046.07	% SZS status Ended for HL407288+5.p
134199.84/18049.86	% SZS status Started for HL407295+4.p
134199.84/18049.86	% SZS status GaveUp for HL407295+4.p
134199.84/18049.86	eprover: CPU time limit exceeded, terminating
134199.84/18049.86	% SZS status Ended for HL407295+4.p
134201.05/18050.08	% SZS status Started for HL407289+5.p
134201.05/18050.08	% SZS status GaveUp for HL407289+5.p
134201.05/18050.08	eprover: CPU time limit exceeded, terminating
134201.05/18050.08	% SZS status Ended for HL407289+5.p
134256.59/18057.06	% SZS status Started for HL407296+4.p
134256.59/18057.06	% SZS status GaveUp for HL407296+4.p
134256.59/18057.06	eprover: CPU time limit exceeded, terminating
134256.59/18057.06	% SZS status Ended for HL407296+4.p
134256.59/18057.12	% SZS status Started for HL407297+4.p
134256.59/18057.12	% SZS status GaveUp for HL407297+4.p
134256.59/18057.12	eprover: CPU time limit exceeded, terminating
134256.59/18057.12	% SZS status Ended for HL407297+4.p
134258.81/18057.29	% SZS status Started for HL407291+5.p
134258.81/18057.29	% SZS status GaveUp for HL407291+5.p
134258.81/18057.29	eprover: CPU time limit exceeded, terminating
134258.81/18057.29	% SZS status Ended for HL407291+5.p
134281.42/18060.15	% SZS status Started for HL407300+4.p
134281.42/18060.15	% SZS status GaveUp for HL407300+4.p
134281.42/18060.15	eprover: CPU time limit exceeded, terminating
134281.42/18060.15	% SZS status Ended for HL407300+4.p
134285.89/18060.76	% SZS status Started for HL407293+5.p
134285.89/18060.76	% SZS status GaveUp for HL407293+5.p
134285.89/18060.76	eprover: CPU time limit exceeded, terminating
134285.89/18060.76	% SZS status Ended for HL407293+5.p
134289.45/18061.15	% SZS status Started for HL407298+4.p
134289.45/18061.15	% SZS status GaveUp for HL407298+4.p
134289.45/18061.15	eprover: CPU time limit exceeded, terminating
134289.45/18061.15	% SZS status Ended for HL407298+4.p
134313.08/18064.18	% SZS status Started for HL407303+4.p
134313.08/18064.18	% SZS status GaveUp for HL407303+4.p
134313.08/18064.18	eprover: CPU time limit exceeded, terminating
134313.08/18064.18	% SZS status Ended for HL407303+4.p
134340.94/18067.67	% SZS status Started for HL407295+5.p
134340.94/18067.67	% SZS status GaveUp for HL407295+5.p
134340.94/18067.67	eprover: CPU time limit exceeded, terminating
134340.94/18067.67	% SZS status Ended for HL407295+5.p
134365.41/18070.74	% SZS status Started for HL407305+4.p
134365.41/18070.74	% SZS status GaveUp for HL407305+4.p
134365.41/18070.74	eprover: CPU time limit exceeded, terminating
134365.41/18070.74	% SZS status Ended for HL407305+4.p
134368.78/18071.20	% SZS status Started for HL407301+4.p
134368.78/18071.20	% SZS status GaveUp for HL407301+4.p
134368.78/18071.20	eprover: CPU time limit exceeded, terminating
134368.78/18071.20	% SZS status Ended for HL407301+4.p
134369.47/18071.24	% SZS status Started for HL407301+5.p
134369.47/18071.24	% SZS status GaveUp for HL407301+5.p
134369.47/18071.24	eprover: CPU time limit exceeded, terminating
134369.47/18071.24	% SZS status Ended for HL407301+5.p
134375.69/18072.03	% SZS status Started for HL407296+5.p
134375.69/18072.03	% SZS status GaveUp for HL407296+5.p
134375.69/18072.03	eprover: CPU time limit exceeded, terminating
134375.69/18072.03	% SZS status Ended for HL407296+5.p
134393.30/18074.29	% SZS status Started for HL407306+4.p
134393.30/18074.29	% SZS status GaveUp for HL407306+4.p
134393.30/18074.29	eprover: CPU time limit exceeded, terminating
134393.30/18074.29	% SZS status Ended for HL407306+4.p
134406.88/18075.96	% SZS status Started for HL407297+5.p
134406.88/18075.96	% SZS status GaveUp for HL407297+5.p
134406.88/18075.96	eprover: CPU time limit exceeded, terminating
134406.88/18075.96	% SZS status Ended for HL407297+5.p
134462.50/18083.01	% SZS status Started for HL407298+5.p
134462.50/18083.01	% SZS status GaveUp for HL407298+5.p
134462.50/18083.01	eprover: CPU time limit exceeded, terminating
134462.50/18083.01	% SZS status Ended for HL407298+5.p
134463.78/18083.09	% SZS status Started for HL407307+4.p
134463.78/18083.09	% SZS status GaveUp for HL407307+4.p
134463.78/18083.09	eprover: CPU time limit exceeded, terminating
134463.78/18083.09	% SZS status Ended for HL407307+4.p
134464.41/18083.26	% SZS status Started for HL407300+5.p
134464.41/18083.26	% SZS status GaveUp for HL407300+5.p
134464.41/18083.26	eprover: CPU time limit exceeded, terminating
134464.41/18083.26	% SZS status Ended for HL407300+5.p
134487.66/18086.13	% SZS status Started for HL407309+4.p
134487.66/18086.13	% SZS status GaveUp for HL407309+4.p
134487.66/18086.13	eprover: CPU time limit exceeded, terminating
134487.66/18086.13	% SZS status Ended for HL407309+4.p
134494.95/18087.09	% SZS status Started for HL407308+4.p
134494.95/18087.09	% SZS status GaveUp for HL407308+4.p
134494.95/18087.09	eprover: CPU time limit exceeded, terminating
134494.95/18087.09	% SZS status Ended for HL407308+4.p
134511.86/18089.19	% SZS status Started for HL407311+4.p
134511.86/18089.19	% SZS status GaveUp for HL407311+4.p
134511.86/18089.19	eprover: CPU time limit exceeded, terminating
134511.86/18089.19	% SZS status Ended for HL407311+4.p
134518.23/18089.96	% SZS status Started for HL407303+5.p
134518.23/18089.96	% SZS status GaveUp for HL407303+5.p
134518.23/18089.96	eprover: CPU time limit exceeded, terminating
134518.23/18089.96	% SZS status Ended for HL407303+5.p
134535.89/18092.21	% SZS status Started for HL407312+4.p
134535.89/18092.21	% SZS status GaveUp for HL407312+4.p
134535.89/18092.21	eprover: CPU time limit exceeded, terminating
134535.89/18092.21	% SZS status Ended for HL407312+4.p
134573.84/18096.94	% SZS status Started for HL407305+5.p
134573.84/18096.94	% SZS status GaveUp for HL407305+5.p
134573.84/18096.94	eprover: CPU time limit exceeded, terminating
134573.84/18096.94	% SZS status Ended for HL407305+5.p
134573.84/18097.00	% SZS status Started for HL407306+5.p
134573.84/18097.00	% SZS status GaveUp for HL407306+5.p
134573.84/18097.00	eprover: CPU time limit exceeded, terminating
134573.84/18097.00	% SZS status Ended for HL407306+5.p
134598.38/18100.05	% SZS status Started for HL407315+4.p
134598.38/18100.05	% SZS status GaveUp for HL407315+4.p
134598.38/18100.05	eprover: CPU time limit exceeded, terminating
134598.38/18100.05	% SZS status Ended for HL407315+4.p
134599.27/18100.21	% SZS status Started for HL407307+5.p
134599.27/18100.21	% SZS status GaveUp for HL407307+5.p
134599.27/18100.21	eprover: CPU time limit exceeded, terminating
134599.27/18100.21	% SZS status Ended for HL407307+5.p
134625.91/18103.48	% SZS status Started for HL407313+4.p
134625.91/18103.48	% SZS status GaveUp for HL407313+4.p
134625.91/18103.48	eprover: CPU time limit exceeded, terminating
134625.91/18103.48	% SZS status Ended for HL407313+4.p
134670.34/18109.07	% SZS status Started for HL407309+5.p
134670.34/18109.07	% SZS status GaveUp for HL407309+5.p
134670.34/18109.07	eprover: CPU time limit exceeded, terminating
134670.34/18109.07	% SZS status Ended for HL407309+5.p
134671.00/18109.16	% SZS status Started for HL407308+5.p
134671.00/18109.16	% SZS status GaveUp for HL407308+5.p
134671.00/18109.16	eprover: CPU time limit exceeded, terminating
134671.00/18109.16	% SZS status Ended for HL407308+5.p
134688.19/18111.31	% SZS status Started for HL407316+4.p
134688.19/18111.31	% SZS status GaveUp for HL407316+4.p
134688.19/18111.31	eprover: CPU time limit exceeded, terminating
134688.19/18111.31	% SZS status Ended for HL407316+4.p
134702.33/18113.11	% SZS status Started for HL407311+5.p
134702.33/18113.11	% SZS status GaveUp for HL407311+5.p
134702.33/18113.11	eprover: CPU time limit exceeded, terminating
134702.33/18113.11	% SZS status Ended for HL407311+5.p
134726.98/18116.23	% SZS status Started for HL407312+5.p
134726.98/18116.23	% SZS status GaveUp for HL407312+5.p
134726.98/18116.23	eprover: CPU time limit exceeded, terminating
134726.98/18116.23	% SZS status Ended for HL407312+5.p
134758.69/18120.18	% SZS status Started for HL407317+4.p
134758.69/18120.18	% SZS status GaveUp for HL407317+4.p
134758.69/18120.18	eprover: CPU time limit exceeded, terminating
134758.69/18120.18	% SZS status Ended for HL407317+4.p
134778.14/18122.62	% SZS status Started for HL407318+4.p
134778.14/18122.62	% SZS status GaveUp for HL407318+4.p
134778.14/18122.62	eprover: CPU time limit exceeded, terminating
134778.14/18122.62	% SZS status Ended for HL407318+4.p
134778.69/18122.69	% SZS status Started for HL407313+5.p
134778.69/18122.69	% SZS status GaveUp for HL407313+5.p
134778.69/18122.69	eprover: CPU time limit exceeded, terminating
134778.69/18122.69	% SZS status Ended for HL407313+5.p
134801.80/18125.66	% SZS status Started for HL407320+4.p
134801.80/18125.66	% SZS status GaveUp for HL407320+4.p
134801.80/18125.66	eprover: CPU time limit exceeded, terminating
134801.80/18125.66	% SZS status Ended for HL407320+4.p
134805.94/18126.15	% SZS status Started for HL407315+5.p
134805.94/18126.15	% SZS status GaveUp for HL407315+5.p
134805.94/18126.15	eprover: CPU time limit exceeded, terminating
134805.94/18126.15	% SZS status Ended for HL407315+5.p
134815.50/18127.35	% SZS status Started for HL407319+4.p
134815.50/18127.35	% SZS status GaveUp for HL407319+4.p
134815.50/18127.35	eprover: CPU time limit exceeded, terminating
134815.50/18127.35	% SZS status Ended for HL407319+4.p
134826.34/18128.71	% SZS status Started for HL407321+4.p
134826.34/18128.71	% SZS status GaveUp for HL407321+4.p
134826.34/18128.71	eprover: CPU time limit exceeded, terminating
134826.34/18128.71	% SZS status Ended for HL407321+4.p
134832.77/18129.57	% SZS status Started for HL407316+5.p
134832.77/18129.57	% SZS status GaveUp for HL407316+5.p
134832.77/18129.57	eprover: CPU time limit exceeded, terminating
134832.77/18129.57	% SZS status Ended for HL407316+5.p
134839.48/18130.40	% SZS status Started for HL407322+4.p
134839.48/18130.40	% SZS status GaveUp for HL407322+4.p
134839.48/18130.40	eprover: CPU time limit exceeded, terminating
134839.48/18130.40	% SZS status Ended for HL407322+4.p
134856.92/18132.60	% SZS status Started for HL407323+4.p
134856.92/18132.60	% SZS status GaveUp for HL407323+4.p
134856.92/18132.60	eprover: CPU time limit exceeded, terminating
134856.92/18132.60	% SZS status Ended for HL407323+4.p
134875.19/18134.95	% SZS status Started for HL407317+5.p
134875.19/18134.95	% SZS status GaveUp for HL407317+5.p
134875.19/18134.95	eprover: CPU time limit exceeded, terminating
134875.19/18134.95	% SZS status Ended for HL407317+5.p
134880.89/18135.64	% SZS status Started for HL407324+4.p
134880.89/18135.64	% SZS status GaveUp for HL407324+4.p
134880.89/18135.64	eprover: CPU time limit exceeded, terminating
134880.89/18135.64	% SZS status Ended for HL407324+4.p
134892.98/18137.12	% SZS status Started for HL407321+5.p
134892.98/18137.12	% SZS status GaveUp for HL407321+5.p
134892.98/18137.12	eprover: CPU time limit exceeded, terminating
134892.98/18137.12	% SZS status Ended for HL407321+5.p
134905.14/18138.78	% SZS status Started for HL407325+4.p
134905.14/18138.78	% SZS status GaveUp for HL407325+4.p
134905.14/18138.78	eprover: CPU time limit exceeded, terminating
134905.14/18138.78	% SZS status Ended for HL407325+4.p
134907.38/18138.97	% SZS status Started for HL407318+5.p
134907.38/18138.97	% SZS status GaveUp for HL407318+5.p
134907.38/18138.97	eprover: CPU time limit exceeded, terminating
134907.38/18138.97	% SZS status Ended for HL407318+5.p
134910.12/18139.37	% SZS status Started for HL407322+5.p
134910.12/18139.37	% SZS status GaveUp for HL407322+5.p
134910.12/18139.37	eprover: CPU time limit exceeded, terminating
134910.12/18139.37	% SZS status Ended for HL407322+5.p
134923.14/18140.95	% SZS status Started for HL407323+5.p
134923.14/18140.95	% SZS status GaveUp for HL407323+5.p
134923.14/18140.95	eprover: CPU time limit exceeded, terminating
134923.14/18140.95	% SZS status Ended for HL407323+5.p
134929.75/18141.83	% SZS status Started for HL407327+4.p
134929.75/18141.83	% SZS status GaveUp for HL407327+4.p
134929.75/18141.83	eprover: CPU time limit exceeded, terminating
134929.75/18141.83	% SZS status Ended for HL407327+4.p
134935.02/18142.43	% SZS status Started for HL407328+4.p
134935.02/18142.43	% SZS status GaveUp for HL407328+4.p
134935.02/18142.43	eprover: CPU time limit exceeded, terminating
134935.02/18142.43	% SZS status Ended for HL407328+4.p
134954.20/18144.86	% SZS status Started for HL407329+4.p
134954.20/18144.86	% SZS status GaveUp for HL407329+4.p
134954.20/18144.86	eprover: CPU time limit exceeded, terminating
134954.20/18144.86	% SZS status Ended for HL407329+4.p
134959.05/18145.47	% SZS status Started for HL407324+5.p
134959.05/18145.47	% SZS status GaveUp for HL407324+5.p
134959.05/18145.47	eprover: CPU time limit exceeded, terminating
134959.05/18145.47	% SZS status Ended for HL407324+5.p
134962.91/18146.04	% SZS status Started for HL407319+5.p
134962.91/18146.04	% SZS status GaveUp for HL407319+5.p
134962.91/18146.04	eprover: CPU time limit exceeded, terminating
134962.91/18146.04	% SZS status Ended for HL407319+5.p
134975.86/18147.58	% SZS status Started for HL407325+5.p
134975.86/18147.58	% SZS status GaveUp for HL407325+5.p
134975.86/18147.58	eprover: CPU time limit exceeded, terminating
134975.86/18147.58	% SZS status Ended for HL407325+5.p
134977.98/18147.90	% SZS status Started for HL407330+4.p
134977.98/18147.90	% SZS status GaveUp for HL407330+4.p
134977.98/18147.90	eprover: CPU time limit exceeded, terminating
134977.98/18147.90	% SZS status Ended for HL407330+4.p
134982.97/18148.49	% SZS status Started for HL407320+5.p
134982.97/18148.49	% SZS status GaveUp for HL407320+5.p
134982.97/18148.49	eprover: CPU time limit exceeded, terminating
134982.97/18148.49	% SZS status Ended for HL407320+5.p
134986.92/18149.07	% SZS status Started for HL407331+4.p
134986.92/18149.07	% SZS status GaveUp for HL407331+4.p
134986.92/18149.07	eprover: CPU time limit exceeded, terminating
134986.92/18149.07	% SZS status Ended for HL407331+4.p
134994.62/18149.98	% SZS status Started for HL407327+5.p
134994.62/18149.98	% SZS status GaveUp for HL407327+5.p
134994.62/18149.98	eprover: CPU time limit exceeded, terminating
134994.62/18149.98	% SZS status Ended for HL407327+5.p
135001.39/18150.99	% SZS status Started for HL407332+4.p
135001.39/18150.99	% SZS status GaveUp for HL407332+4.p
135001.39/18150.99	eprover: CPU time limit exceeded, terminating
135001.39/18150.99	% SZS status Ended for HL407332+4.p
135006.38/18151.55	% SZS status Started for HL407328+5.p
135006.38/18151.55	% SZS status GaveUp for HL407328+5.p
135006.38/18151.55	eprover: CPU time limit exceeded, terminating
135006.38/18151.55	% SZS status Ended for HL407328+5.p
135011.28/18152.23	% SZS status Started for HL407333+4.p
135011.28/18152.23	% SZS status GaveUp for HL407333+4.p
135011.28/18152.23	eprover: CPU time limit exceeded, terminating
135011.28/18152.23	% SZS status Ended for HL407333+4.p
135018.52/18153.05	% SZS status Started for HL407329+5.p
135018.52/18153.05	% SZS status GaveUp for HL407329+5.p
135018.52/18153.05	eprover: CPU time limit exceeded, terminating
135018.52/18153.05	% SZS status Ended for HL407329+5.p
135025.34/18154.05	% SZS status Started for HL407334+4.p
135025.34/18154.05	% SZS status GaveUp for HL407334+4.p
135025.34/18154.05	eprover: CPU time limit exceeded, terminating
135025.34/18154.05	% SZS status Ended for HL407334+4.p
135034.88/18155.26	% SZS status Started for HL407335+4.p
135034.88/18155.26	% SZS status GaveUp for HL407335+4.p
135034.88/18155.26	eprover: CPU time limit exceeded, terminating
135034.88/18155.26	% SZS status Ended for HL407335+4.p
135042.02/18156.03	% SZS status Started for HL407330+5.p
135042.02/18156.03	% SZS status GaveUp for HL407330+5.p
135042.02/18156.03	eprover: CPU time limit exceeded, terminating
135042.02/18156.03	% SZS status Ended for HL407330+5.p
135050.06/18157.09	% SZS status Started for HL407337+4.p
135050.06/18157.09	% SZS status GaveUp for HL407337+4.p
135050.06/18157.09	eprover: CPU time limit exceeded, terminating
135050.06/18157.09	% SZS status Ended for HL407337+4.p
135059.44/18158.31	% SZS status Started for HL407331+5.p
135059.44/18158.31	% SZS status GaveUp for HL407331+5.p
135059.44/18158.31	eprover: CPU time limit exceeded, terminating
135059.44/18158.31	% SZS status Ended for HL407331+5.p
135065.95/18159.10	% SZS status Started for HL407332+5.p
135065.95/18159.10	% SZS status GaveUp for HL407332+5.p
135065.95/18159.10	eprover: CPU time limit exceeded, terminating
135065.95/18159.10	% SZS status Ended for HL407332+5.p
135066.84/18159.24	% SZS status Started for HL407339+4.p
135066.84/18159.24	% SZS status GaveUp for HL407339+4.p
135066.84/18159.24	eprover: CPU time limit exceeded, terminating
135066.84/18159.24	% SZS status Ended for HL407339+4.p
135078.23/18160.65	% SZS status Started for HL407333+5.p
135078.23/18160.65	% SZS status GaveUp for HL407333+5.p
135078.23/18160.65	eprover: CPU time limit exceeded, terminating
135078.23/18160.65	% SZS status Ended for HL407333+5.p
135083.56/18161.34	% SZS status Started for HL407340+4.p
135083.56/18161.34	% SZS status GaveUp for HL407340+4.p
135083.56/18161.34	eprover: CPU time limit exceeded, terminating
135083.56/18161.34	% SZS status Ended for HL407340+4.p
135089.41/18162.02	% SZS status Started for HL407334+5.p
135089.41/18162.02	% SZS status GaveUp for HL407334+5.p
135089.41/18162.02	eprover: CPU time limit exceeded, terminating
135089.41/18162.02	% SZS status Ended for HL407334+5.p
135091.34/18162.28	% SZS status Started for HL407341+4.p
135091.34/18162.28	% SZS status GaveUp for HL407341+4.p
135091.34/18162.28	eprover: CPU time limit exceeded, terminating
135091.34/18162.28	% SZS status Ended for HL407341+4.p
135101.92/18163.61	% SZS status Started for HL407335+5.p
135101.92/18163.61	% SZS status GaveUp for HL407335+5.p
135101.92/18163.61	eprover: CPU time limit exceeded, terminating
135101.92/18163.61	% SZS status Ended for HL407335+5.p
135108.70/18164.45	% SZS status Started for HL407342+4.p
135108.70/18164.45	% SZS status GaveUp for HL407342+4.p
135108.70/18164.45	eprover: CPU time limit exceeded, terminating
135108.70/18164.45	% SZS status Ended for HL407342+4.p
135115.62/18165.40	% SZS status Started for HL407344+4.p
135115.62/18165.40	% SZS status GaveUp for HL407344+4.p
135115.62/18165.40	eprover: CPU time limit exceeded, terminating
135115.62/18165.40	% SZS status Ended for HL407344+4.p
135118.91/18165.75	% SZS status Started for HL407337+5.p
135118.91/18165.75	% SZS status GaveUp for HL407337+5.p
135118.91/18165.75	eprover: CPU time limit exceeded, terminating
135118.91/18165.75	% SZS status Ended for HL407337+5.p
135133.50/18167.62	% SZS status Started for HL407339+5.p
135133.50/18167.62	% SZS status GaveUp for HL407339+5.p
135133.50/18167.62	eprover: CPU time limit exceeded, terminating
135133.50/18167.62	% SZS status Ended for HL407339+5.p
135133.50/18167.62	% SZS status Started for HL407345+4.p
135133.50/18167.62	% SZS status GaveUp for HL407345+4.p
135133.50/18167.62	eprover: CPU time limit exceeded, terminating
135133.50/18167.62	% SZS status Ended for HL407345+4.p
135143.12/18168.79	% SZS status Started for HL407347+4.p
135143.12/18168.79	% SZS status GaveUp for HL407347+4.p
135143.12/18168.79	eprover: CPU time limit exceeded, terminating
135143.12/18168.79	% SZS status Ended for HL407347+4.p
135149.05/18169.61	% SZS status Started for HL407340+5.p
135149.05/18169.61	% SZS status GaveUp for HL407340+5.p
135149.05/18169.61	eprover: CPU time limit exceeded, terminating
135149.05/18169.61	% SZS status Ended for HL407340+5.p
135157.95/18170.69	% SZS status Started for HL407348+4.p
135157.95/18170.69	% SZS status GaveUp for HL407348+4.p
135157.95/18170.69	eprover: CPU time limit exceeded, terminating
135157.95/18170.69	% SZS status Ended for HL407348+4.p
135161.53/18171.14	% SZS status Started for HL407341+5.p
135161.53/18171.14	% SZS status GaveUp for HL407341+5.p
135161.53/18171.14	eprover: CPU time limit exceeded, terminating
135161.53/18171.14	% SZS status Ended for HL407341+5.p
135172.25/18172.47	% SZS status Started for HL407342+5.p
135172.25/18172.47	% SZS status GaveUp for HL407342+5.p
135172.25/18172.47	eprover: CPU time limit exceeded, terminating
135172.25/18172.47	% SZS status Ended for HL407342+5.p
135173.45/18172.64	% SZS status Started for HL407349+4.p
135173.45/18172.64	% SZS status GaveUp for HL407349+4.p
135173.45/18172.64	eprover: CPU time limit exceeded, terminating
135173.45/18172.64	% SZS status Ended for HL407349+4.p
135184.83/18174.10	% SZS status Started for HL407344+5.p
135184.83/18174.10	% SZS status GaveUp for HL407344+5.p
135184.83/18174.10	eprover: CPU time limit exceeded, terminating
135184.83/18174.10	% SZS status Ended for HL407344+5.p
135185.47/18174.17	% SZS status Started for HL407350+4.p
135185.47/18174.17	% SZS status GaveUp for HL407350+4.p
135185.47/18174.17	eprover: CPU time limit exceeded, terminating
135185.47/18174.17	% SZS status Ended for HL407350+4.p
135196.55/18175.68	% SZS status Started for HL407351+4.p
135196.55/18175.68	% SZS status GaveUp for HL407351+4.p
135196.55/18175.68	eprover: CPU time limit exceeded, terminating
135196.55/18175.68	% SZS status Ended for HL407351+4.p
135198.80/18175.84	% SZS status Started for HL407345+5.p
135198.80/18175.84	% SZS status GaveUp for HL407345+5.p
135198.80/18175.84	eprover: CPU time limit exceeded, terminating
135198.80/18175.84	% SZS status Ended for HL407345+5.p
135209.73/18177.21	% SZS status Started for HL407353+4.p
135209.73/18177.21	% SZS status GaveUp for HL407353+4.p
135209.73/18177.21	eprover: CPU time limit exceeded, terminating
135209.73/18177.21	% SZS status Ended for HL407353+4.p
135219.62/18178.51	% SZS status Started for HL407347+5.p
135219.62/18178.51	% SZS status GaveUp for HL407347+5.p
135219.62/18178.51	eprover: CPU time limit exceeded, terminating
135219.62/18178.51	% SZS status Ended for HL407347+5.p
135222.84/18178.87	% SZS status Started for HL407354+4.p
135222.84/18178.87	% SZS status GaveUp for HL407354+4.p
135222.84/18178.87	eprover: CPU time limit exceeded, terminating
135222.84/18178.87	% SZS status Ended for HL407354+4.p
135224.91/18179.26	% SZS status Started for HL407348+5.p
135224.91/18179.26	% SZS status GaveUp for HL407348+5.p
135224.91/18179.26	eprover: CPU time limit exceeded, terminating
135224.91/18179.26	% SZS status Ended for HL407348+5.p
135240.94/18181.11	% SZS status Started for HL407349+5.p
135240.94/18181.11	% SZS status GaveUp for HL407349+5.p
135240.94/18181.11	eprover: CPU time limit exceeded, terminating
135240.94/18181.11	% SZS status Ended for HL407349+5.p
135243.58/18181.57	% SZS status Started for HL407355+4.p
135243.58/18181.57	% SZS status GaveUp for HL407355+4.p
135243.58/18181.57	eprover: CPU time limit exceeded, terminating
135243.58/18181.57	% SZS status Ended for HL407355+4.p
135252.00/18182.51	% SZS status Started for HL407356+4.p
135252.00/18182.51	% SZS status GaveUp for HL407356+4.p
135252.00/18182.51	eprover: CPU time limit exceeded, terminating
135252.00/18182.51	% SZS status Ended for HL407356+4.p
135254.06/18182.90	% SZS status Started for HL407350+5.p
135254.06/18182.90	% SZS status GaveUp for HL407350+5.p
135254.06/18182.90	eprover: CPU time limit exceeded, terminating
135254.06/18182.90	% SZS status Ended for HL407350+5.p
135267.58/18184.51	% SZS status Started for HL407351+5.p
135267.58/18184.51	% SZS status GaveUp for HL407351+5.p
135267.58/18184.51	eprover: CPU time limit exceeded, terminating
135267.58/18184.51	% SZS status Ended for HL407351+5.p
135268.70/18184.68	% SZS status Started for HL407357+4.p
135268.70/18184.68	% SZS status GaveUp for HL407357+4.p
135268.70/18184.68	eprover: CPU time limit exceeded, terminating
135268.70/18184.68	% SZS status Ended for HL407357+4.p
135278.30/18185.94	% SZS status Started for HL407358+4.p
135278.30/18185.94	% SZS status GaveUp for HL407358+4.p
135278.30/18185.94	eprover: CPU time limit exceeded, terminating
135278.30/18185.94	% SZS status Ended for HL407358+4.p
135279.92/18186.07	% SZS status Started for HL407353+5.p
135279.92/18186.07	% SZS status GaveUp for HL407353+5.p
135279.92/18186.07	eprover: CPU time limit exceeded, terminating
135279.92/18186.07	% SZS status Ended for HL407353+5.p
135292.47/18187.63	% SZS status Started for HL407354+5.p
135292.47/18187.63	% SZS status GaveUp for HL407354+5.p
135292.47/18187.63	eprover: CPU time limit exceeded, terminating
135292.47/18187.63	% SZS status Ended for HL407354+5.p
135292.80/18187.71	% SZS status Started for HL407359+4.p
135292.80/18187.71	% SZS status GaveUp for HL407359+4.p
135292.80/18187.71	eprover: CPU time limit exceeded, terminating
135292.80/18187.71	% SZS status Ended for HL407359+4.p
135304.56/18189.11	% SZS status Started for HL407360+4.p
135304.56/18189.11	% SZS status GaveUp for HL407360+4.p
135304.56/18189.11	eprover: CPU time limit exceeded, terminating
135304.56/18189.11	% SZS status Ended for HL407360+4.p
135305.70/18189.29	% SZS status Started for HL407355+5.p
135305.70/18189.29	% SZS status GaveUp for HL407355+5.p
135305.70/18189.29	eprover: CPU time limit exceeded, terminating
135305.70/18189.29	% SZS status Ended for HL407355+5.p
135316.08/18190.75	% SZS status Started for HL407361+4.p
135316.08/18190.75	% SZS status GaveUp for HL407361+4.p
135316.08/18190.75	eprover: CPU time limit exceeded, terminating
135316.08/18190.75	% SZS status Ended for HL407361+4.p
135323.55/18191.53	% SZS status Started for HL407356+5.p
135323.55/18191.53	% SZS status GaveUp for HL407356+5.p
135323.55/18191.53	eprover: CPU time limit exceeded, terminating
135323.55/18191.53	% SZS status Ended for HL407356+5.p
135329.80/18192.34	% SZS status Started for HL407362+4.p
135329.80/18192.34	% SZS status GaveUp for HL407362+4.p
135329.80/18192.34	eprover: CPU time limit exceeded, terminating
135329.80/18192.34	% SZS status Ended for HL407362+4.p
135338.19/18193.46	% SZS status Started for HL407357+5.p
135338.19/18193.46	% SZS status GaveUp for HL407357+5.p
135338.19/18193.46	eprover: CPU time limit exceeded, terminating
135338.19/18193.46	% SZS status Ended for HL407357+5.p
135347.77/18194.57	% SZS status Started for HL407365+4.p
135347.77/18194.57	% SZS status GaveUp for HL407365+4.p
135347.77/18194.57	eprover: CPU time limit exceeded, terminating
135347.77/18194.57	% SZS status Ended for HL407365+4.p
135350.45/18194.90	% SZS status Started for HL407358+5.p
135350.45/18194.90	% SZS status GaveUp for HL407358+5.p
135350.45/18194.90	eprover: CPU time limit exceeded, terminating
135350.45/18194.90	% SZS status Ended for HL407358+5.p
135361.62/18196.36	% SZS status Started for HL407359+5.p
135361.62/18196.36	% SZS status GaveUp for HL407359+5.p
135361.62/18196.36	eprover: CPU time limit exceeded, terminating
135361.62/18196.36	% SZS status Ended for HL407359+5.p
135363.38/18196.65	% SZS status Started for HL407366+4.p
135363.38/18196.65	% SZS status GaveUp for HL407366+4.p
135363.38/18196.65	eprover: CPU time limit exceeded, terminating
135363.38/18196.65	% SZS status Ended for HL407366+4.p
135373.69/18197.94	% SZS status Started for HL407367+4.p
135373.69/18197.94	% SZS status GaveUp for HL407367+4.p
135373.69/18197.94	eprover: CPU time limit exceeded, terminating
135373.69/18197.94	% SZS status Ended for HL407367+4.p
135375.50/18198.06	% SZS status Started for HL407360+5.p
135375.50/18198.06	% SZS status GaveUp for HL407360+5.p
135375.50/18198.06	eprover: CPU time limit exceeded, terminating
135375.50/18198.06	% SZS status Ended for HL407360+5.p
135386.83/18199.53	% SZS status Started for HL407361+5.p
135386.83/18199.53	% SZS status GaveUp for HL407361+5.p
135386.83/18199.53	eprover: CPU time limit exceeded, terminating
135386.83/18199.53	% SZS status Ended for HL407361+5.p
135387.67/18199.69	% SZS status Started for HL407368+4.p
135387.67/18199.69	% SZS status GaveUp for HL407368+4.p
135387.67/18199.69	eprover: CPU time limit exceeded, terminating
135387.67/18199.69	% SZS status Ended for HL407368+4.p
135399.83/18201.10	% SZS status Started for HL407369+4.p
135399.83/18201.10	% SZS status GaveUp for HL407369+4.p
135399.83/18201.10	eprover: CPU time limit exceeded, terminating
135399.83/18201.10	% SZS status Ended for HL407369+4.p
135400.78/18201.26	% SZS status Started for HL407362+5.p
135400.78/18201.26	% SZS status GaveUp for HL407362+5.p
135400.78/18201.26	eprover: CPU time limit exceeded, terminating
135400.78/18201.26	% SZS status Ended for HL407362+5.p
135412.39/18202.73	% SZS status Started for HL407370+4.p
135412.39/18202.73	% SZS status GaveUp for HL407370+4.p
135412.39/18202.73	eprover: CPU time limit exceeded, terminating
135412.39/18202.73	% SZS status Ended for HL407370+4.p
135412.39/18202.76	% SZS status Started for HL407365+5.p
135412.39/18202.76	% SZS status GaveUp for HL407365+5.p
135412.39/18202.76	eprover: CPU time limit exceeded, terminating
135412.39/18202.76	% SZS status Ended for HL407365+5.p
135423.89/18204.29	% SZS status Started for HL407371+4.p
135423.89/18204.29	% SZS status GaveUp for HL407371+4.p
135423.89/18204.29	eprover: CPU time limit exceeded, terminating
135423.89/18204.29	% SZS status Ended for HL407371+4.p
135431.97/18205.01	% SZS status Started for HL407366+5.p
135431.97/18205.01	% SZS status GaveUp for HL407366+5.p
135431.97/18205.01	eprover: CPU time limit exceeded, terminating
135431.97/18205.01	% SZS status Ended for HL407366+5.p
135438.77/18205.80	% SZS status Started for HL407372+4.p
135438.77/18205.80	% SZS status GaveUp for HL407372+4.p
135438.77/18205.80	eprover: CPU time limit exceeded, terminating
135438.77/18205.80	% SZS status Ended for HL407372+4.p
135448.09/18207.09	% SZS status Started for HL407367+5.p
135448.09/18207.09	% SZS status GaveUp for HL407367+5.p
135448.09/18207.09	eprover: CPU time limit exceeded, terminating
135448.09/18207.09	% SZS status Ended for HL407367+5.p
135456.33/18208.05	% SZS status Started for HL407373+4.p
135456.33/18208.05	% SZS status GaveUp for HL407373+4.p
135456.33/18208.05	eprover: CPU time limit exceeded, terminating
135456.33/18208.05	% SZS status Ended for HL407373+4.p
135458.20/18208.40	% SZS status Started for HL407368+5.p
135458.20/18208.40	% SZS status GaveUp for HL407368+5.p
135458.20/18208.40	eprover: CPU time limit exceeded, terminating
135458.20/18208.40	% SZS status Ended for HL407368+5.p
135472.70/18210.18	% SZS status Started for HL407369+5.p
135472.70/18210.18	% SZS status GaveUp for HL407369+5.p
135472.70/18210.18	eprover: CPU time limit exceeded, terminating
135472.70/18210.18	% SZS status Ended for HL407369+5.p
135474.36/18210.29	% SZS status Started for HL407374+4.p
135474.36/18210.29	% SZS status GaveUp for HL407374+4.p
135474.36/18210.29	eprover: CPU time limit exceeded, terminating
135474.36/18210.29	% SZS status Ended for HL407374+4.p
135482.81/18211.45	% SZS status Started for HL407375+4.p
135482.81/18211.45	% SZS status GaveUp for HL407375+4.p
135482.81/18211.45	eprover: CPU time limit exceeded, terminating
135482.81/18211.45	% SZS status Ended for HL407375+4.p
135483.27/18211.54	% SZS status Started for HL407370+5.p
135483.27/18211.54	% SZS status GaveUp for HL407370+5.p
135483.27/18211.54	eprover: CPU time limit exceeded, terminating
135483.27/18211.54	% SZS status Ended for HL407370+5.p
135497.19/18213.17	% SZS status Started for HL407371+5.p
135497.19/18213.17	% SZS status GaveUp for HL407371+5.p
135497.19/18213.17	eprover: CPU time limit exceeded, terminating
135497.19/18213.17	% SZS status Ended for HL407371+5.p
135498.19/18213.33	% SZS status Started for HL407376+4.p
135498.19/18213.33	% SZS status GaveUp for HL407376+4.p
135498.19/18213.33	eprover: CPU time limit exceeded, terminating
135498.19/18213.33	% SZS status Ended for HL407376+4.p
135507.72/18214.58	% SZS status Started for HL407377+4.p
135507.72/18214.58	% SZS status GaveUp for HL407377+4.p
135507.72/18214.58	eprover: CPU time limit exceeded, terminating
135507.72/18214.58	% SZS status Ended for HL407377+4.p
135509.59/18214.75	% SZS status Started for HL407372+5.p
135509.59/18214.75	% SZS status GaveUp for HL407372+5.p
135509.59/18214.75	eprover: CPU time limit exceeded, terminating
135509.59/18214.75	% SZS status Ended for HL407372+5.p
135521.28/18216.24	% SZS status Started for HL407373+5.p
135521.28/18216.24	% SZS status GaveUp for HL407373+5.p
135521.28/18216.24	eprover: CPU time limit exceeded, terminating
135521.28/18216.24	% SZS status Ended for HL407373+5.p
135522.58/18216.37	% SZS status Started for HL407379+4.p
135522.58/18216.37	% SZS status GaveUp for HL407379+4.p
135522.58/18216.37	eprover: CPU time limit exceeded, terminating
135522.58/18216.37	% SZS status Ended for HL407379+4.p
135534.00/18217.79	% SZS status Started for HL407380+4.p
135534.00/18217.79	% SZS status GaveUp for HL407380+4.p
135534.00/18217.79	eprover: CPU time limit exceeded, terminating
135534.00/18217.79	% SZS status Ended for HL407380+4.p
135540.41/18218.63	% SZS status Started for HL407374+5.p
135540.41/18218.63	% SZS status GaveUp for HL407374+5.p
135540.41/18218.63	eprover: CPU time limit exceeded, terminating
135540.41/18218.63	% SZS status Ended for HL407374+5.p
135546.91/18219.40	% SZS status Started for HL407381+4.p
135546.91/18219.40	% SZS status GaveUp for HL407381+4.p
135546.91/18219.40	eprover: CPU time limit exceeded, terminating
135546.91/18219.40	% SZS status Ended for HL407381+4.p
135558.25/18220.84	% SZS status Started for HL407375+5.p
135558.25/18220.84	% SZS status GaveUp for HL407375+5.p
135558.25/18220.84	eprover: CPU time limit exceeded, terminating
135558.25/18220.84	% SZS status Ended for HL407375+5.p
135564.83/18221.70	% SZS status Started for HL407382+4.p
135564.83/18221.70	% SZS status GaveUp for HL407382+4.p
135564.83/18221.70	eprover: CPU time limit exceeded, terminating
135564.83/18221.70	% SZS status Ended for HL407382+4.p
135568.98/18221.86	% SZS status Started for HL407376+5.p
135568.98/18221.86	% SZS status GaveUp for HL407376+5.p
135568.98/18221.86	eprover: CPU time limit exceeded, terminating
135568.98/18221.86	% SZS status Ended for HL407376+5.p
135582.80/18223.62	% SZS status Started for HL407377+5.p
135582.80/18223.62	% SZS status GaveUp for HL407377+5.p
135582.80/18223.62	eprover: CPU time limit exceeded, terminating
135582.80/18223.62	% SZS status Ended for HL407377+5.p
135585.91/18224.01	% SZS status Started for HL407383+4.p
135585.91/18224.01	% SZS status GaveUp for HL407383+4.p
135585.91/18224.01	eprover: CPU time limit exceeded, terminating
135585.91/18224.01	% SZS status Ended for HL407383+4.p
135592.83/18224.91	% SZS status Started for HL407384+4.p
135592.83/18224.91	% SZS status GaveUp for HL407384+4.p
135592.83/18224.91	eprover: CPU time limit exceeded, terminating
135592.83/18224.91	% SZS status Ended for HL407384+4.p
135593.61/18224.98	% SZS status Started for HL407379+5.p
135593.61/18224.98	% SZS status GaveUp for HL407379+5.p
135593.61/18224.98	eprover: CPU time limit exceeded, terminating
135593.61/18224.98	% SZS status Ended for HL407379+5.p
135607.67/18226.69	% SZS status Started for HL407380+5.p
135607.67/18226.69	% SZS status GaveUp for HL407380+5.p
135607.67/18226.69	eprover: CPU time limit exceeded, terminating
135607.67/18226.69	% SZS status Ended for HL407380+5.p
135610.08/18227.05	% SZS status Started for HL407385+4.p
135610.08/18227.05	% SZS status GaveUp for HL407385+4.p
135610.08/18227.05	eprover: CPU time limit exceeded, terminating
135610.08/18227.05	% SZS status Ended for HL407385+4.p
135618.05/18228.02	% SZS status Started for HL407387+4.p
135618.05/18228.02	% SZS status GaveUp for HL407387+4.p
135618.05/18228.02	eprover: CPU time limit exceeded, terminating
135618.05/18228.02	% SZS status Ended for HL407387+4.p
135619.00/18228.20	% SZS status Started for HL407381+5.p
135619.00/18228.20	% SZS status GaveUp for HL407381+5.p
135619.00/18228.20	eprover: CPU time limit exceeded, terminating
135619.00/18228.20	% SZS status Ended for HL407381+5.p
135632.95/18229.92	% SZS status Started for HL407382+5.p
135632.95/18229.92	% SZS status GaveUp for HL407382+5.p
135632.95/18229.92	eprover: CPU time limit exceeded, terminating
135632.95/18229.92	% SZS status Ended for HL407382+5.p
135634.33/18230.09	% SZS status Started for HL407390+4.p
135634.33/18230.09	% SZS status GaveUp for HL407390+4.p
135634.33/18230.09	eprover: CPU time limit exceeded, terminating
135634.33/18230.09	% SZS status Ended for HL407390+4.p
135643.34/18231.24	% SZS status Started for HL407392+4.p
135643.34/18231.24	% SZS status GaveUp for HL407392+4.p
135643.34/18231.24	eprover: CPU time limit exceeded, terminating
135643.34/18231.24	% SZS status Ended for HL407392+4.p
135652.50/18232.52	% SZS status Started for HL407383+5.p
135652.50/18232.52	% SZS status GaveUp for HL407383+5.p
135652.50/18232.52	eprover: CPU time limit exceeded, terminating
135652.50/18232.52	% SZS status Ended for HL407383+5.p
135658.41/18233.12	% SZS status Started for HL407393+4.p
135658.41/18233.12	% SZS status GaveUp for HL407393+4.p
135658.41/18233.12	eprover: CPU time limit exceeded, terminating
135658.41/18233.12	% SZS status Ended for HL407393+4.p
135666.52/18234.09	% SZS status Started for HL407384+5.p
135666.52/18234.09	% SZS status GaveUp for HL407384+5.p
135666.52/18234.09	eprover: CPU time limit exceeded, terminating
135666.52/18234.09	% SZS status Ended for HL407384+5.p
135676.64/18235.43	% SZS status Started for HL407385+5.p
135676.64/18235.43	% SZS status GaveUp for HL407385+5.p
135676.64/18235.43	eprover: CPU time limit exceeded, terminating
135676.64/18235.43	% SZS status Ended for HL407385+5.p
135677.88/18235.56	% SZS status Started for HL407394+4.p
135677.88/18235.56	% SZS status GaveUp for HL407394+4.p
135677.88/18235.56	eprover: CPU time limit exceeded, terminating
135677.88/18235.56	% SZS status Ended for HL407394+4.p
135690.30/18237.13	% SZS status Started for HL407395+4.p
135690.30/18237.13	% SZS status GaveUp for HL407395+4.p
135690.30/18237.13	eprover: CPU time limit exceeded, terminating
135690.30/18237.13	% SZS status Ended for HL407395+4.p
135690.62/18237.17	% SZS status Started for HL407387+5.p
135690.62/18237.17	% SZS status GaveUp for HL407387+5.p
135690.62/18237.17	eprover: CPU time limit exceeded, terminating
135690.62/18237.17	% SZS status Ended for HL407387+5.p
135701.20/18238.51	% SZS status Started for HL407390+5.p
135701.20/18238.51	% SZS status GaveUp for HL407390+5.p
135701.20/18238.51	eprover: CPU time limit exceeded, terminating
135701.20/18238.51	% SZS status Ended for HL407390+5.p
135702.84/18238.60	% SZS status Started for HL407396+4.p
135702.84/18238.60	% SZS status GaveUp for HL407396+4.p
135702.84/18238.60	eprover: CPU time limit exceeded, terminating
135702.84/18238.60	% SZS status Ended for HL407396+4.p
135715.56/18240.21	% SZS status Started for HL407397+4.p
135715.56/18240.21	% SZS status GaveUp for HL407397+4.p
135715.56/18240.21	eprover: CPU time limit exceeded, terminating
135715.56/18240.21	% SZS status Ended for HL407397+4.p
135716.72/18240.37	% SZS status Started for HL407392+5.p
135716.72/18240.37	% SZS status GaveUp for HL407392+5.p
135716.72/18240.37	eprover: CPU time limit exceeded, terminating
135716.72/18240.37	% SZS status Ended for HL407392+5.p
135726.70/18241.63	% SZS status Started for HL407398+4.p
135726.70/18241.63	% SZS status GaveUp for HL407398+4.p
135726.70/18241.63	eprover: CPU time limit exceeded, terminating
135726.70/18241.63	% SZS status Ended for HL407398+4.p
135730.22/18242.04	% SZS status Started for HL407393+5.p
135730.22/18242.04	% SZS status GaveUp for HL407393+5.p
135730.22/18242.04	eprover: CPU time limit exceeded, terminating
135730.22/18242.04	% SZS status Ended for HL407393+5.p
135741.17/18243.45	% SZS status Started for HL407399+4.p
135741.17/18243.45	% SZS status GaveUp for HL407399+4.p
135741.17/18243.45	eprover: CPU time limit exceeded, terminating
135741.17/18243.45	% SZS status Ended for HL407399+4.p
135742.39/18243.60	% SZS status Started for HL407394+5.p
135742.39/18243.60	% SZS status GaveUp for HL407394+5.p
135742.39/18243.60	eprover: CPU time limit exceeded, terminating
135742.39/18243.60	% SZS status Ended for HL407394+5.p
135753.36/18245.07	% SZS status Started for HL407400+4.p
135753.36/18245.07	% SZS status GaveUp for HL407400+4.p
135753.36/18245.07	eprover: CPU time limit exceeded, terminating
135753.36/18245.07	% SZS status Ended for HL407400+4.p
135760.28/18245.85	% SZS status Started for HL407395+5.p
135760.28/18245.85	% SZS status GaveUp for HL407395+5.p
135760.28/18245.85	eprover: CPU time limit exceeded, terminating
135760.28/18245.85	% SZS status Ended for HL407395+5.p
135766.56/18246.65	% SZS status Started for HL407401+4.p
135766.56/18246.65	% SZS status GaveUp for HL407401+4.p
135766.56/18246.65	eprover: CPU time limit exceeded, terminating
135766.56/18246.65	% SZS status Ended for HL407401+4.p
135774.95/18247.66	% SZS status Started for HL407396+5.p
135774.95/18247.66	% SZS status GaveUp for HL407396+5.p
135774.95/18247.66	eprover: CPU time limit exceeded, terminating
135774.95/18247.66	% SZS status Ended for HL407396+5.p
135784.23/18248.93	% SZS status Started for HL407397+5.p
135784.23/18248.93	% SZS status GaveUp for HL407397+5.p
135784.23/18248.93	eprover: CPU time limit exceeded, terminating
135784.23/18248.93	% SZS status Ended for HL407397+5.p
135798.33/18250.61	% SZS status Started for HL407398+5.p
135798.33/18250.61	% SZS status GaveUp for HL407398+5.p
135798.33/18250.61	eprover: CPU time limit exceeded, terminating
135798.33/18250.61	% SZS status Ended for HL407398+5.p
135811.19/18252.21	% SZS status Started for HL407399+5.p
135811.19/18252.21	% SZS status GaveUp for HL407399+5.p
135811.19/18252.21	eprover: CPU time limit exceeded, terminating
135811.19/18252.21	% SZS status Ended for HL407399+5.p
135848.91/18257.03	% SZS status Started for HL407403+4.p
135848.91/18257.03	% SZS status GaveUp for HL407403+4.p
135848.91/18257.03	eprover: CPU time limit exceeded, terminating
135848.91/18257.03	% SZS status Ended for HL407403+4.p
135862.30/18258.75	% SZS status Started for HL407404+4.p
135862.30/18258.75	% SZS status GaveUp for HL407404+4.p
135862.30/18258.75	eprover: CPU time limit exceeded, terminating
135862.30/18258.75	% SZS status Ended for HL407404+4.p
135872.64/18260.08	% SZS status Started for HL407406+4.p
135872.64/18260.08	% SZS status GaveUp for HL407406+4.p
135872.64/18260.08	eprover: CPU time limit exceeded, terminating
135872.64/18260.08	% SZS status Ended for HL407406+4.p
135886.27/18261.76	% SZS status Started for HL407405+4.p
135886.27/18261.76	% SZS status GaveUp for HL407405+4.p
135886.27/18261.76	eprover: CPU time limit exceeded, terminating
135886.27/18261.76	% SZS status Ended for HL407405+4.p
135897.12/18263.11	% SZS status Started for HL407408+4.p
135897.12/18263.11	% SZS status GaveUp for HL407408+4.p
135897.12/18263.11	eprover: CPU time limit exceeded, terminating
135897.12/18263.11	% SZS status Ended for HL407408+4.p
135920.80/18266.14	% SZS status Started for HL407409+4.p
135920.80/18266.14	% SZS status GaveUp for HL407409+4.p
135920.80/18266.14	eprover: CPU time limit exceeded, terminating
135920.80/18266.14	% SZS status Ended for HL407409+4.p
135944.98/18269.24	% SZS status Started for HL407406+5.p
135944.98/18269.24	% SZS status GaveUp for HL407406+5.p
135944.98/18269.24	eprover: CPU time limit exceeded, terminating
135944.98/18269.24	% SZS status Ended for HL407406+5.p
135947.78/18269.53	% SZS status Started for HL407400+5.p
135947.78/18269.53	% SZS status GaveUp for HL407400+5.p
135947.78/18269.53	eprover: CPU time limit exceeded, terminating
135947.78/18269.53	% SZS status Ended for HL407400+5.p
135958.30/18270.89	% SZS status Started for HL407401+5.p
135958.30/18270.89	% SZS status GaveUp for HL407401+5.p
135958.30/18270.89	eprover: CPU time limit exceeded, terminating
135958.30/18270.89	% SZS status Ended for HL407401+5.p
135969.84/18272.42	% SZS status Started for HL407410+4.p
135969.84/18272.42	% SZS status GaveUp for HL407410+4.p
135969.84/18272.42	eprover: CPU time limit exceeded, terminating
135969.84/18272.42	% SZS status Ended for HL407410+4.p
135972.30/18272.60	% SZS status Started for HL407408+5.p
135972.30/18272.60	% SZS status GaveUp for HL407408+5.p
135972.30/18272.60	eprover: CPU time limit exceeded, terminating
135972.30/18272.60	% SZS status Ended for HL407408+5.p
135974.94/18273.09	% SZS status Started for HL407403+5.p
135974.94/18273.09	% SZS status GaveUp for HL407403+5.p
135974.94/18273.09	eprover: CPU time limit exceeded, terminating
135974.94/18273.09	% SZS status Ended for HL407403+5.p
135984.22/18273.93	% SZS status Started for HL407411+4.p
135984.22/18273.93	% SZS status GaveUp for HL407411+4.p
135984.22/18273.93	eprover: CPU time limit exceeded, terminating
135984.22/18273.93	% SZS status Ended for HL407411+4.p
135993.09/18275.02	% SZS status Started for HL407404+5.p
135993.09/18275.02	% SZS status GaveUp for HL407404+5.p
135993.09/18275.02	eprover: CPU time limit exceeded, terminating
135993.09/18275.02	% SZS status Ended for HL407404+5.p
135997.91/18275.63	% SZS status Started for HL407412+4.p
135997.91/18275.63	% SZS status GaveUp for HL407412+4.p
135997.91/18275.63	eprover: CPU time limit exceeded, terminating
135997.91/18275.63	% SZS status Ended for HL407412+4.p
136006.09/18276.64	% SZS status Started for HL407409+5.p
136006.09/18276.64	% SZS status GaveUp for HL407409+5.p
136006.09/18276.64	eprover: CPU time limit exceeded, terminating
136006.09/18276.64	% SZS status Ended for HL407409+5.p
136008.11/18276.97	% SZS status Started for HL407414+4.p
136008.11/18276.97	% SZS status GaveUp for HL407414+4.p
136008.11/18276.97	eprover: CPU time limit exceeded, terminating
136008.11/18276.97	% SZS status Ended for HL407414+4.p
136016.64/18278.04	% SZS status Started for HL407405+5.p
136016.64/18278.04	% SZS status GaveUp for HL407405+5.p
136016.64/18278.04	eprover: CPU time limit exceeded, terminating
136016.64/18278.04	% SZS status Ended for HL407405+5.p
136021.61/18278.68	% SZS status Started for HL407415+4.p
136021.61/18278.68	% SZS status GaveUp for HL407415+4.p
136021.61/18278.68	eprover: CPU time limit exceeded, terminating
136021.61/18278.68	% SZS status Ended for HL407415+4.p
136032.39/18280.03	% SZS status Started for HL407410+5.p
136032.39/18280.03	% SZS status GaveUp for HL407410+5.p
136032.39/18280.03	eprover: CPU time limit exceeded, terminating
136032.39/18280.03	% SZS status Ended for HL407410+5.p
136033.75/18280.11	% SZS status Started for HL407417+4.p
136033.75/18280.11	% SZS status GaveUp for HL407417+4.p
136033.75/18280.11	eprover: CPU time limit exceeded, terminating
136033.75/18280.11	% SZS status Ended for HL407417+4.p
136045.47/18281.71	% SZS status Started for HL407418+4.p
136045.47/18281.71	% SZS status GaveUp for HL407418+4.p
136045.47/18281.71	eprover: CPU time limit exceeded, terminating
136045.47/18281.71	% SZS status Ended for HL407418+4.p
136058.31/18282.96	% SZS status Started for HL407411+5.p
136058.31/18282.96	% SZS status GaveUp for HL407411+5.p
136058.31/18282.96	eprover: CPU time limit exceeded, terminating
136058.31/18282.96	% SZS status Ended for HL407411+5.p
136059.53/18283.15	% SZS status Started for HL407419+4.p
136059.53/18283.15	% SZS status GaveUp for HL407419+4.p
136059.53/18283.15	eprover: CPU time limit exceeded, terminating
136059.53/18283.15	% SZS status Ended for HL407419+4.p
136064.39/18283.80	% SZS status Started for HL407412+5.p
136064.39/18283.80	% SZS status GaveUp for HL407412+5.p
136064.39/18283.80	eprover: CPU time limit exceeded, terminating
136064.39/18283.80	% SZS status Ended for HL407412+5.p
136077.86/18285.46	% SZS status Started for HL407414+5.p
136077.86/18285.46	% SZS status GaveUp for HL407414+5.p
136077.86/18285.46	eprover: CPU time limit exceeded, terminating
136077.86/18285.46	% SZS status Ended for HL407414+5.p
136082.34/18286.01	% SZS status Started for HL407420+4.p
136082.34/18286.01	% SZS status GaveUp for HL407420+4.p
136082.34/18286.01	eprover: CPU time limit exceeded, terminating
136082.34/18286.01	% SZS status Ended for HL407420+4.p
136088.20/18286.83	% SZS status Started for HL407421+4.p
136088.20/18286.83	% SZS status GaveUp for HL407421+4.p
136088.20/18286.83	eprover: CPU time limit exceeded, terminating
136088.20/18286.83	% SZS status Ended for HL407421+4.p
136090.72/18287.08	% SZS status Started for HL407415+5.p
136090.72/18287.08	% SZS status GaveUp for HL407415+5.p
136090.72/18287.08	eprover: CPU time limit exceeded, terminating
136090.72/18287.08	% SZS status Ended for HL407415+5.p
136101.83/18288.54	% SZS status Started for HL407417+5.p
136101.83/18288.54	% SZS status GaveUp for HL407417+5.p
136101.83/18288.54	eprover: CPU time limit exceeded, terminating
136101.83/18288.54	% SZS status Ended for HL407417+5.p
136105.64/18289.05	% SZS status Started for HL407422+4.p
136105.64/18289.05	% SZS status GaveUp for HL407422+4.p
136105.64/18289.05	eprover: CPU time limit exceeded, terminating
136105.64/18289.05	% SZS status Ended for HL407422+4.p
136116.25/18290.34	% SZS status Started for HL407423+4.p
136116.25/18290.34	% SZS status GaveUp for HL407423+4.p
136116.25/18290.34	eprover: CPU time limit exceeded, terminating
136116.25/18290.34	% SZS status Ended for HL407423+4.p
136119.75/18290.79	% SZS status Started for HL407418+5.p
136119.75/18290.79	% SZS status GaveUp for HL407418+5.p
136119.75/18290.79	eprover: CPU time limit exceeded, terminating
136119.75/18290.79	% SZS status Ended for HL407418+5.p
136130.69/18292.16	% SZS status Started for HL407419+5.p
136130.69/18292.16	% SZS status GaveUp for HL407419+5.p
136130.69/18292.16	eprover: CPU time limit exceeded, terminating
136130.69/18292.16	% SZS status Ended for HL407419+5.p
136130.69/18292.17	% SZS status Started for HL407424+4.p
136130.69/18292.17	% SZS status GaveUp for HL407424+4.p
136130.69/18292.17	eprover: CPU time limit exceeded, terminating
136130.69/18292.17	% SZS status Ended for HL407424+4.p
136142.14/18293.62	% SZS status Started for HL407420+5.p
136142.14/18293.62	% SZS status GaveUp for HL407420+5.p
136142.14/18293.62	eprover: CPU time limit exceeded, terminating
136142.14/18293.62	% SZS status Ended for HL407420+5.p
136143.50/18293.83	% SZS status Started for HL407426+4.p
136143.50/18293.83	% SZS status GaveUp for HL407426+4.p
136143.50/18293.83	eprover: CPU time limit exceeded, terminating
136143.50/18293.83	% SZS status Ended for HL407426+4.p
136155.84/18295.34	% SZS status Started for HL407428+4.p
136155.84/18295.34	% SZS status GaveUp for HL407428+4.p
136155.84/18295.34	eprover: CPU time limit exceeded, terminating
136155.84/18295.34	% SZS status Ended for HL407428+4.p
136161.48/18296.00	% SZS status Started for HL407421+5.p
136161.48/18296.00	% SZS status GaveUp for HL407421+5.p
136161.48/18296.00	eprover: CPU time limit exceeded, terminating
136161.48/18296.00	% SZS status Ended for HL407421+5.p
136167.67/18296.87	% SZS status Started for HL407429+4.p
136167.67/18296.87	% SZS status GaveUp for HL407429+4.p
136167.67/18296.87	eprover: CPU time limit exceeded, terminating
136167.67/18296.87	% SZS status Ended for HL407429+4.p
136172.52/18297.38	% SZS status Started for HL407422+5.p
136172.52/18297.38	% SZS status GaveUp for HL407422+5.p
136172.52/18297.38	eprover: CPU time limit exceeded, terminating
136172.52/18297.38	% SZS status Ended for HL407422+5.p
136185.00/18298.97	% SZS status Started for HL407423+5.p
136185.00/18298.97	% SZS status GaveUp for HL407423+5.p
136185.00/18298.97	eprover: CPU time limit exceeded, terminating
136185.00/18298.97	% SZS status Ended for HL407423+5.p
136185.59/18299.07	% SZS status Started for HL407430+4.p
136185.59/18299.07	% SZS status GaveUp for HL407430+4.p
136185.59/18299.07	eprover: CPU time limit exceeded, terminating
136185.59/18299.07	% SZS status Ended for HL407430+4.p
136196.59/18300.41	% SZS status Started for HL407431+4.p
136196.59/18300.41	% SZS status GaveUp for HL407431+4.p
136196.59/18300.41	eprover: CPU time limit exceeded, terminating
136196.59/18300.41	% SZS status Ended for HL407431+4.p
136198.97/18300.78	% SZS status Started for HL407424+5.p
136198.97/18300.78	% SZS status GaveUp for HL407424+5.p
136198.97/18300.78	eprover: CPU time limit exceeded, terminating
136198.97/18300.78	% SZS status Ended for HL407424+5.p
136209.92/18302.11	% SZS status Started for HL407432+4.p
136209.92/18302.11	% SZS status GaveUp for HL407432+4.p
136209.92/18302.11	eprover: CPU time limit exceeded, terminating
136209.92/18302.11	% SZS status Ended for HL407432+4.p
136213.77/18302.58	% SZS status Started for HL407426+5.p
136213.77/18302.58	% SZS status GaveUp for HL407426+5.p
136213.77/18302.58	eprover: CPU time limit exceeded, terminating
136213.77/18302.58	% SZS status Ended for HL407426+5.p
136223.38/18303.82	% SZS status Started for HL407433+4.p
136223.38/18303.82	% SZS status GaveUp for HL407433+4.p
136223.38/18303.82	eprover: CPU time limit exceeded, terminating
136223.38/18303.82	% SZS status Ended for HL407433+4.p
136224.42/18304.06	% SZS status Started for HL407428+5.p
136224.42/18304.06	% SZS status GaveUp for HL407428+5.p
136224.42/18304.06	eprover: CPU time limit exceeded, terminating
136224.42/18304.06	% SZS status Ended for HL407428+5.p
136237.69/18305.62	% SZS status Started for HL407435+4.p
136237.69/18305.62	% SZS status GaveUp for HL407435+4.p
136237.69/18305.62	eprover: CPU time limit exceeded, terminating
136237.69/18305.62	% SZS status Ended for HL407435+4.p
136238.88/18305.81	% SZS status Started for HL407429+5.p
136238.88/18305.81	% SZS status GaveUp for HL407429+5.p
136238.88/18305.81	eprover: CPU time limit exceeded, terminating
136238.88/18305.81	% SZS status Ended for HL407429+5.p
136249.11/18307.10	% SZS status Started for HL407436+4.p
136249.11/18307.10	% SZS status GaveUp for HL407436+4.p
136249.11/18307.10	eprover: CPU time limit exceeded, terminating
136249.11/18307.10	% SZS status Ended for HL407436+4.p
136254.98/18307.97	% SZS status Started for HL407430+5.p
136254.98/18307.97	% SZS status GaveUp for HL407430+5.p
136254.98/18307.97	eprover: CPU time limit exceeded, terminating
136254.98/18307.97	% SZS status Ended for HL407430+5.p
136263.06/18308.85	% SZS status Started for HL407437+4.p
136263.06/18308.85	% SZS status GaveUp for HL407437+4.p
136263.06/18308.85	eprover: CPU time limit exceeded, terminating
136263.06/18308.85	% SZS status Ended for HL407437+4.p
136267.27/18309.39	% SZS status Started for HL407431+5.p
136267.27/18309.39	% SZS status GaveUp for HL407431+5.p
136267.27/18309.39	eprover: CPU time limit exceeded, terminating
136267.27/18309.39	% SZS status Ended for HL407431+5.p
136279.84/18310.90	% SZS status Started for HL407432+5.p
136279.84/18310.90	% SZS status GaveUp for HL407432+5.p
136279.84/18310.90	eprover: CPU time limit exceeded, terminating
136279.84/18310.90	% SZS status Ended for HL407432+5.p
136281.64/18311.19	% SZS status Started for HL407438+4.p
136281.64/18311.19	% SZS status GaveUp for HL407438+4.p
136281.64/18311.19	eprover: CPU time limit exceeded, terminating
136281.64/18311.19	% SZS status Ended for HL407438+4.p
136291.28/18312.43	% SZS status Started for HL407439+4.p
136291.28/18312.43	% SZS status GaveUp for HL407439+4.p
136291.28/18312.43	eprover: CPU time limit exceeded, terminating
136291.28/18312.43	% SZS status Ended for HL407439+4.p
136291.97/18312.55	% SZS status Started for HL407433+5.p
136291.97/18312.55	% SZS status GaveUp for HL407433+5.p
136291.97/18312.55	eprover: CPU time limit exceeded, terminating
136291.97/18312.55	% SZS status Ended for HL407433+5.p
136306.27/18314.23	% SZS status Started for HL407440+4.p
136306.27/18314.23	% SZS status GaveUp for HL407440+4.p
136306.27/18314.23	eprover: CPU time limit exceeded, terminating
136306.27/18314.23	% SZS status Ended for HL407440+4.p
136306.42/18314.27	% SZS status Started for HL407435+5.p
136306.42/18314.27	% SZS status GaveUp for HL407435+5.p
136306.42/18314.27	eprover: CPU time limit exceeded, terminating
136306.42/18314.27	% SZS status Ended for HL407435+5.p
136316.92/18315.59	% SZS status Started for HL407441+4.p
136316.92/18315.59	% SZS status GaveUp for HL407441+4.p
136316.92/18315.59	eprover: CPU time limit exceeded, terminating
136316.92/18315.59	% SZS status Ended for HL407441+4.p
136320.58/18316.05	% SZS status Started for HL407436+5.p
136320.58/18316.05	% SZS status GaveUp for HL407436+5.p
136320.58/18316.05	eprover: CPU time limit exceeded, terminating
136320.58/18316.05	% SZS status Ended for HL407436+5.p
136330.72/18317.31	% SZS status Started for HL407442+4.p
136330.72/18317.31	% SZS status GaveUp for HL407442+4.p
136330.72/18317.31	eprover: CPU time limit exceeded, terminating
136330.72/18317.31	% SZS status Ended for HL407442+4.p
136332.11/18317.54	% SZS status Started for HL407437+5.p
136332.11/18317.54	% SZS status GaveUp for HL407437+5.p
136332.11/18317.54	eprover: CPU time limit exceeded, terminating
136332.11/18317.54	% SZS status Ended for HL407437+5.p
136344.42/18319.08	% SZS status Started for HL407443+4.p
136344.42/18319.08	% SZS status GaveUp for HL407443+4.p
136344.42/18319.08	eprover: CPU time limit exceeded, terminating
136344.42/18319.08	% SZS status Ended for HL407443+4.p
136346.25/18319.29	% SZS status Started for HL407438+5.p
136346.25/18319.29	% SZS status GaveUp for HL407438+5.p
136346.25/18319.29	eprover: CPU time limit exceeded, terminating
136346.25/18319.29	% SZS status Ended for HL407438+5.p
136356.30/18320.57	% SZS status Started for HL407445+4.p
136356.30/18320.57	% SZS status GaveUp for HL407445+4.p
136356.30/18320.57	eprover: CPU time limit exceeded, terminating
136356.30/18320.57	% SZS status Ended for HL407445+4.p
136366.44/18321.85	% SZS status Started for HL407439+5.p
136366.44/18321.85	% SZS status GaveUp for HL407439+5.p
136366.44/18321.85	eprover: CPU time limit exceeded, terminating
136366.44/18321.85	% SZS status Ended for HL407439+5.p
136370.34/18322.33	% SZS status Started for HL407446+4.p
136370.34/18322.33	% SZS status GaveUp for HL407446+4.p
136370.34/18322.33	eprover: CPU time limit exceeded, terminating
136370.34/18322.33	% SZS status Ended for HL407446+4.p
136374.19/18322.86	% SZS status Started for HL407440+5.p
136374.19/18322.86	% SZS status GaveUp for HL407440+5.p
136374.19/18322.86	eprover: CPU time limit exceeded, terminating
136374.19/18322.86	% SZS status Ended for HL407440+5.p
136389.36/18324.72	% SZS status Started for HL407441+5.p
136389.36/18324.72	% SZS status GaveUp for HL407441+5.p
136389.36/18324.72	eprover: CPU time limit exceeded, terminating
136389.36/18324.72	% SZS status Ended for HL407441+5.p
136390.94/18325.03	% SZS status Started for HL407447+4.p
136390.94/18325.03	% SZS status GaveUp for HL407447+4.p
136390.94/18325.03	eprover: CPU time limit exceeded, terminating
136390.94/18325.03	% SZS status Ended for HL407447+4.p
136398.42/18325.90	% SZS status Started for HL407448+4.p
136398.42/18325.90	% SZS status GaveUp for HL407448+4.p
136398.42/18325.90	eprover: CPU time limit exceeded, terminating
136398.42/18325.90	% SZS status Ended for HL407448+4.p
136399.27/18326.03	% SZS status Started for HL407442+5.p
136399.27/18326.03	% SZS status GaveUp for HL407442+5.p
136399.27/18326.03	eprover: CPU time limit exceeded, terminating
136399.27/18326.03	% SZS status Ended for HL407442+5.p
136413.03/18327.74	% SZS status Started for HL407443+5.p
136413.03/18327.74	% SZS status GaveUp for HL407443+5.p
136413.03/18327.74	eprover: CPU time limit exceeded, terminating
136413.03/18327.74	% SZS status Ended for HL407443+5.p
136416.62/18328.12	% SZS status Started for HL407449+4.p
136416.62/18328.12	% SZS status GaveUp for HL407449+4.p
136416.62/18328.12	eprover: CPU time limit exceeded, terminating
136416.62/18328.12	% SZS status Ended for HL407449+4.p
136423.66/18329.07	% SZS status Started for HL407450+4.p
136423.66/18329.07	% SZS status GaveUp for HL407450+4.p
136423.66/18329.07	eprover: CPU time limit exceeded, terminating
136423.66/18329.07	% SZS status Ended for HL407450+4.p
136427.55/18329.50	% SZS status Started for HL407445+5.p
136427.55/18329.50	% SZS status GaveUp for HL407445+5.p
136427.55/18329.50	eprover: CPU time limit exceeded, terminating
136427.55/18329.50	% SZS status Ended for HL407445+5.p
136440.44/18331.10	% SZS status Started for HL407446+5.p
136440.44/18331.10	% SZS status GaveUp for HL407446+5.p
136440.44/18331.10	eprover: CPU time limit exceeded, terminating
136440.44/18331.10	% SZS status Ended for HL407446+5.p
136440.55/18331.16	% SZS status Started for HL407451+4.p
136440.55/18331.16	% SZS status GaveUp for HL407451+4.p
136440.55/18331.16	eprover: CPU time limit exceeded, terminating
136440.55/18331.16	% SZS status Ended for HL407451+4.p
136451.25/18332.54	% SZS status Started for HL407452+4.p
136451.25/18332.54	% SZS status GaveUp for HL407452+4.p
136451.25/18332.54	eprover: CPU time limit exceeded, terminating
136451.25/18332.54	% SZS status Ended for HL407452+4.p
136452.61/18332.76	% SZS status Started for HL407447+5.p
136452.61/18332.76	% SZS status GaveUp for HL407447+5.p
136452.61/18332.76	eprover: CPU time limit exceeded, terminating
136452.61/18332.76	% SZS status Ended for HL407447+5.p
136464.83/18334.20	% SZS status Started for HL407453+4.p
136464.83/18334.20	% SZS status GaveUp for HL407453+4.p
136464.83/18334.20	eprover: CPU time limit exceeded, terminating
136464.83/18334.20	% SZS status Ended for HL407453+4.p
136471.80/18335.16	% SZS status Started for HL407448+5.p
136471.80/18335.16	% SZS status GaveUp for HL407448+5.p
136471.80/18335.16	eprover: CPU time limit exceeded, terminating
136471.80/18335.16	% SZS status Ended for HL407448+5.p
136477.03/18335.80	% SZS status Started for HL407455+4.p
136477.03/18335.80	% SZS status GaveUp for HL407455+4.p
136477.03/18335.80	eprover: CPU time limit exceeded, terminating
136477.03/18335.80	% SZS status Ended for HL407455+4.p
136486.05/18336.85	% SZS status Started for HL407449+5.p
136486.05/18336.85	% SZS status GaveUp for HL407449+5.p
136486.05/18336.85	eprover: CPU time limit exceeded, terminating
136486.05/18336.85	% SZS status Ended for HL407449+5.p
136496.50/18338.20	% SZS status Started for HL407456+4.p
136496.50/18338.20	% SZS status GaveUp for HL407456+4.p
136496.50/18338.20	eprover: CPU time limit exceeded, terminating
136496.50/18338.20	% SZS status Ended for HL407456+4.p
136497.03/18338.29	% SZS status Started for HL407450+5.p
136497.03/18338.29	% SZS status GaveUp for HL407450+5.p
136497.03/18338.29	eprover: CPU time limit exceeded, terminating
136497.03/18338.29	% SZS status Ended for HL407450+5.p
136506.97/18339.52	% SZS status Started for HL407451+5.p
136506.97/18339.52	% SZS status GaveUp for HL407451+5.p
136506.97/18339.52	eprover: CPU time limit exceeded, terminating
136506.97/18339.52	% SZS status Ended for HL407451+5.p
136511.09/18340.03	% SZS status Started for HL407457+4.p
136511.09/18340.03	% SZS status GaveUp for HL407457+4.p
136511.09/18340.03	eprover: CPU time limit exceeded, terminating
136511.09/18340.03	% SZS status Ended for HL407457+4.p
136521.12/18341.32	% SZS status Started for HL407458+4.p
136521.12/18341.32	% SZS status GaveUp for HL407458+4.p
136521.12/18341.32	eprover: CPU time limit exceeded, terminating
136521.12/18341.32	% SZS status Ended for HL407458+4.p
136523.00/18341.53	% SZS status Started for HL407452+5.p
136523.00/18341.53	% SZS status GaveUp for HL407452+5.p
136523.00/18341.53	eprover: CPU time limit exceeded, terminating
136523.00/18341.53	% SZS status Ended for HL407452+5.p
136534.81/18343.06	% SZS status Started for HL407453+5.p
136534.81/18343.06	% SZS status GaveUp for HL407453+5.p
136534.81/18343.06	eprover: CPU time limit exceeded, terminating
136534.81/18343.06	% SZS status Ended for HL407453+5.p
136535.45/18343.12	% SZS status Started for HL407460+4.p
136535.45/18343.12	% SZS status GaveUp for HL407460+4.p
136535.45/18343.12	eprover: CPU time limit exceeded, terminating
136535.45/18343.12	% SZS status Ended for HL407460+4.p
136547.50/18344.64	% SZS status Started for HL407455+5.p
136547.50/18344.64	% SZS status GaveUp for HL407455+5.p
136547.50/18344.64	eprover: CPU time limit exceeded, terminating
136547.50/18344.64	% SZS status Ended for HL407455+5.p
136547.84/18344.69	% SZS status Started for HL407461+4.p
136547.84/18344.69	% SZS status GaveUp for HL407461+4.p
136547.84/18344.69	eprover: CPU time limit exceeded, terminating
136547.84/18344.69	% SZS status Ended for HL407461+4.p
136559.41/18346.17	% SZS status Started for HL407462+4.p
136559.41/18346.17	% SZS status GaveUp for HL407462+4.p
136559.41/18346.17	eprover: CPU time limit exceeded, terminating
136559.41/18346.17	% SZS status Ended for HL407462+4.p
136560.69/18346.30	% SZS status Started for HL407456+5.p
136560.69/18346.30	% SZS status GaveUp for HL407456+5.p
136560.69/18346.30	eprover: CPU time limit exceeded, terminating
136560.69/18346.30	% SZS status Ended for HL407456+5.p
136573.28/18347.81	% SZS status Started for HL407463+4.p
136573.28/18347.81	% SZS status GaveUp for HL407463+4.p
136573.28/18347.81	eprover: CPU time limit exceeded, terminating
136573.28/18347.81	% SZS status Ended for HL407463+4.p
136579.12/18348.64	% SZS status Started for HL407457+5.p
136579.12/18348.64	% SZS status GaveUp for HL407457+5.p
136579.12/18348.64	eprover: CPU time limit exceeded, terminating
136579.12/18348.64	% SZS status Ended for HL407457+5.p
136586.55/18349.50	% SZS status Started for HL407465+4.p
136586.55/18349.50	% SZS status GaveUp for HL407465+4.p
136586.55/18349.50	eprover: CPU time limit exceeded, terminating
136586.55/18349.50	% SZS status Ended for HL407465+4.p
136589.05/18349.96	% SZS status Started for HL407458+5.p
136589.05/18349.96	% SZS status GaveUp for HL407458+5.p
136589.05/18349.96	eprover: CPU time limit exceeded, terminating
136589.05/18349.96	% SZS status Ended for HL407458+5.p
136603.45/18351.68	% SZS status Started for HL407466+4.p
136603.45/18351.68	% SZS status GaveUp for HL407466+4.p
136603.45/18351.68	eprover: CPU time limit exceeded, terminating
136603.45/18351.68	% SZS status Ended for HL407466+4.p
136604.48/18351.78	% SZS status Started for HL407460+5.p
136604.48/18351.78	% SZS status GaveUp for HL407460+5.p
136604.48/18351.78	eprover: CPU time limit exceeded, terminating
136604.48/18351.78	% SZS status Ended for HL407460+5.p
136614.72/18353.07	% SZS status Started for HL407468+4.p
136614.72/18353.07	% SZS status GaveUp for HL407468+4.p
136614.72/18353.07	eprover: CPU time limit exceeded, terminating
136614.72/18353.07	% SZS status Ended for HL407468+4.p
136618.00/18353.49	% SZS status Started for HL407461+5.p
136618.00/18353.49	% SZS status GaveUp for HL407461+5.p
136618.00/18353.49	eprover: CPU time limit exceeded, terminating
136618.00/18353.49	% SZS status Ended for HL407461+5.p
136628.53/18354.82	% SZS status Started for HL407469+4.p
136628.53/18354.82	% SZS status GaveUp for HL407469+4.p
136628.53/18354.82	eprover: CPU time limit exceeded, terminating
136628.53/18354.82	% SZS status Ended for HL407469+4.p
136629.72/18355.08	% SZS status Started for HL407462+5.p
136629.72/18355.08	% SZS status GaveUp for HL407462+5.p
136629.72/18355.08	eprover: CPU time limit exceeded, terminating
136629.72/18355.08	% SZS status Ended for HL407462+5.p
136641.72/18356.53	% SZS status Started for HL407470+4.p
136641.72/18356.53	% SZS status GaveUp for HL407470+4.p
136641.72/18356.53	eprover: CPU time limit exceeded, terminating
136641.72/18356.53	% SZS status Ended for HL407470+4.p
136642.03/18356.60	% SZS status Started for HL407463+5.p
136642.03/18356.60	% SZS status GaveUp for HL407463+5.p
136642.03/18356.60	eprover: CPU time limit exceeded, terminating
136642.03/18356.60	% SZS status Ended for HL407463+5.p
136655.28/18358.19	% SZS status Started for HL407472+4.p
136655.28/18358.19	% SZS status GaveUp for HL407472+4.p
136655.28/18358.19	eprover: CPU time limit exceeded, terminating
136655.28/18358.19	% SZS status Ended for HL407472+4.p
136655.78/18358.25	% SZS status Started for HL407465+5.p
136655.78/18358.25	% SZS status GaveUp for HL407465+5.p
136655.78/18358.25	eprover: CPU time limit exceeded, terminating
136655.78/18358.25	% SZS status Ended for HL407465+5.p
136666.64/18359.63	% SZS status Started for HL407473+4.p
136666.64/18359.63	% SZS status GaveUp for HL407473+4.p
136666.64/18359.63	eprover: CPU time limit exceeded, terminating
136666.64/18359.63	% SZS status Ended for HL407473+4.p
136669.36/18359.99	% SZS status Started for HL407466+5.p
136669.36/18359.99	% SZS status GaveUp for HL407466+5.p
136669.36/18359.99	eprover: CPU time limit exceeded, terminating
136669.36/18359.99	% SZS status Ended for HL407466+5.p
136680.22/18361.29	% SZS status Started for HL407474+4.p
136680.22/18361.29	% SZS status GaveUp for HL407474+4.p
136680.22/18361.29	eprover: CPU time limit exceeded, terminating
136680.22/18361.29	% SZS status Ended for HL407474+4.p
136691.19/18362.70	% SZS status Started for HL407468+5.p
136691.19/18362.70	% SZS status GaveUp for HL407468+5.p
136691.19/18362.70	eprover: CPU time limit exceeded, terminating
136691.19/18362.70	% SZS status Ended for HL407468+5.p
136692.34/18363.03	% SZS status Started for HL407475+4.p
136692.34/18363.03	% SZS status GaveUp for HL407475+4.p
136692.34/18363.03	eprover: CPU time limit exceeded, terminating
136692.34/18363.03	% SZS status Ended for HL407475+4.p
136700.28/18363.56	% SZS status Started for HL407469+5.p
136700.28/18363.56	% SZS status GaveUp for HL407469+5.p
136700.28/18363.56	eprover: CPU time limit exceeded, terminating
136700.28/18363.56	% SZS status Ended for HL407469+5.p
136713.77/18365.27	% SZS status Started for HL407470+5.p
136713.77/18365.27	% SZS status GaveUp for HL407470+5.p
136713.77/18365.27	eprover: CPU time limit exceeded, terminating
136713.77/18365.27	% SZS status Ended for HL407470+5.p
136718.77/18365.85	% SZS status Started for HL407476+4.p
136718.77/18365.85	% SZS status GaveUp for HL407476+4.p
136718.77/18365.85	eprover: CPU time limit exceeded, terminating
136718.77/18365.85	% SZS status Ended for HL407476+4.p
136724.58/18366.60	% SZS status Started for HL407478+4.p
136724.58/18366.60	% SZS status GaveUp for HL407478+4.p
136724.58/18366.60	eprover: CPU time limit exceeded, terminating
136724.58/18366.60	% SZS status Ended for HL407478+4.p
136727.72/18366.98	% SZS status Started for HL407472+5.p
136727.72/18366.98	% SZS status GaveUp for HL407472+5.p
136727.72/18366.98	eprover: CPU time limit exceeded, terminating
136727.72/18366.98	% SZS status Ended for HL407472+5.p
136741.14/18368.64	% SZS status Started for HL407473+5.p
136741.14/18368.64	% SZS status GaveUp for HL407473+5.p
136741.14/18368.64	eprover: CPU time limit exceeded, terminating
136741.14/18368.64	% SZS status Ended for HL407473+5.p
136743.81/18369.02	% SZS status Started for HL407479+4.p
136743.81/18369.02	% SZS status GaveUp for HL407479+4.p
136743.81/18369.02	eprover: CPU time limit exceeded, terminating
136743.81/18369.02	% SZS status Ended for HL407479+4.p
136752.19/18370.01	% SZS status Started for HL407480+4.p
136752.19/18370.01	% SZS status GaveUp for HL407480+4.p
136752.19/18370.01	eprover: CPU time limit exceeded, terminating
136752.19/18370.01	% SZS status Ended for HL407480+4.p
136752.19/18370.08	% SZS status Started for HL407474+5.p
136752.19/18370.08	% SZS status GaveUp for HL407474+5.p
136752.19/18370.08	eprover: CPU time limit exceeded, terminating
136752.19/18370.08	% SZS status Ended for HL407474+5.p
136765.77/18371.75	% SZS status Started for HL407475+5.p
136765.77/18371.75	% SZS status GaveUp for HL407475+5.p
136765.77/18371.75	eprover: CPU time limit exceeded, terminating
136765.77/18371.75	% SZS status Ended for HL407475+5.p
136767.72/18372.06	% SZS status Started for HL407481+4.p
136767.72/18372.06	% SZS status GaveUp for HL407481+4.p
136767.72/18372.06	eprover: CPU time limit exceeded, terminating
136767.72/18372.06	% SZS status Ended for HL407481+4.p
136778.08/18373.35	% SZS status Started for HL407483+4.p
136778.08/18373.35	% SZS status GaveUp for HL407483+4.p
136778.08/18373.35	eprover: CPU time limit exceeded, terminating
136778.08/18373.35	% SZS status Ended for HL407483+4.p
136778.89/18373.47	% SZS status Started for HL407476+5.p
136778.89/18373.47	% SZS status GaveUp for HL407476+5.p
136778.89/18373.47	eprover: CPU time limit exceeded, terminating
136778.89/18373.47	% SZS status Ended for HL407476+5.p
136792.89/18375.18	% SZS status Started for HL407484+4.p
136792.89/18375.18	% SZS status GaveUp for HL407484+4.p
136792.89/18375.18	eprover: CPU time limit exceeded, terminating
136792.89/18375.18	% SZS status Ended for HL407484+4.p
136797.08/18375.73	% SZS status Started for HL407478+5.p
136797.08/18375.73	% SZS status GaveUp for HL407478+5.p
136797.08/18375.73	eprover: CPU time limit exceeded, terminating
136797.08/18375.73	% SZS status Ended for HL407478+5.p
136802.39/18376.51	% SZS status Started for HL407485+4.p
136802.39/18376.51	% SZS status GaveUp for HL407485+4.p
136802.39/18376.51	eprover: CPU time limit exceeded, terminating
136802.39/18376.51	% SZS status Ended for HL407485+4.p
136807.53/18377.03	% SZS status Started for HL407479+5.p
136807.53/18377.03	% SZS status GaveUp for HL407479+5.p
136807.53/18377.03	eprover: CPU time limit exceeded, terminating
136807.53/18377.03	% SZS status Ended for HL407479+5.p
136824.67/18379.17	% SZS status Started for HL407480+5.p
136824.67/18379.17	% SZS status GaveUp for HL407480+5.p
136824.67/18379.17	eprover: CPU time limit exceeded, terminating
136824.67/18379.17	% SZS status Ended for HL407480+5.p
136834.91/18380.43	% SZS status Started for HL407481+5.p
136834.91/18380.43	% SZS status GaveUp for HL407481+5.p
136834.91/18380.43	eprover: CPU time limit exceeded, terminating
136834.91/18380.43	% SZS status Ended for HL407481+5.p
136847.84/18382.15	% SZS status Started for HL407483+5.p
136847.84/18382.15	% SZS status GaveUp for HL407483+5.p
136847.84/18382.15	eprover: CPU time limit exceeded, terminating
136847.84/18382.15	% SZS status Ended for HL407483+5.p
136859.47/18383.56	% SZS status Started for HL407484+5.p
136859.47/18383.56	% SZS status GaveUp for HL407484+5.p
136859.47/18383.56	eprover: CPU time limit exceeded, terminating
136859.47/18383.56	% SZS status Ended for HL407484+5.p
136865.56/18384.46	% SZS status Started for HL407489+4.p
136865.56/18384.46	% SZS status GaveUp for HL407489+4.p
136865.56/18384.46	eprover: CPU time limit exceeded, terminating
136865.56/18384.46	% SZS status Ended for HL407489+4.p
136886.56/18386.94	% SZS status Started for HL407487+4.p
136886.56/18386.94	% SZS status GaveUp for HL407487+4.p
136886.56/18386.94	eprover: CPU time limit exceeded, terminating
136886.56/18386.94	% SZS status Ended for HL407487+4.p
136895.56/18388.12	% SZS status Started for HL407488+4.p
136895.56/18388.12	% SZS status GaveUp for HL407488+4.p
136895.56/18388.12	eprover: CPU time limit exceeded, terminating
136895.56/18388.12	% SZS status Ended for HL407488+4.p
136911.11/18390.00	% SZS status Started for HL407491+4.p
136911.11/18390.00	% SZS status GaveUp for HL407491+4.p
136911.11/18390.00	eprover: CPU time limit exceeded, terminating
136911.11/18390.00	% SZS status Ended for HL407491+4.p
136934.89/18393.06	% SZS status Started for HL407492+4.p
136934.89/18393.06	% SZS status GaveUp for HL407492+4.p
136934.89/18393.06	eprover: CPU time limit exceeded, terminating
136934.89/18393.06	% SZS status Ended for HL407492+4.p
136948.50/18394.71	% SZS status Started for HL407490+4.p
136948.50/18394.71	% SZS status GaveUp for HL407490+4.p
136948.50/18394.71	eprover: CPU time limit exceeded, terminating
136948.50/18394.71	% SZS status Ended for HL407490+4.p
136989.16/18399.82	% SZS status Started for HL407493+4.p
136989.16/18399.82	% SZS status GaveUp for HL407493+4.p
136989.16/18399.82	eprover: CPU time limit exceeded, terminating
136989.16/18399.82	% SZS status Ended for HL407493+4.p
136998.23/18401.03	% SZS status Started for HL407485+5.p
136998.23/18401.03	% SZS status GaveUp for HL407485+5.p
136998.23/18401.03	eprover: CPU time limit exceeded, terminating
136998.23/18401.03	% SZS status Ended for HL407485+5.p
137010.06/18402.50	% SZS status Started for HL407487+5.p
137010.06/18402.50	% SZS status GaveUp for HL407487+5.p
137010.06/18402.50	eprover: CPU time limit exceeded, terminating
137010.06/18402.50	% SZS status Ended for HL407487+5.p
137015.83/18403.25	% SZS status Started for HL407492+5.p
137015.83/18403.25	% SZS status GaveUp for HL407492+5.p
137015.83/18403.25	eprover: CPU time limit exceeded, terminating
137015.83/18403.25	% SZS status Ended for HL407492+5.p
137023.27/18404.14	% SZS status Started for HL407494+4.p
137023.27/18404.14	% SZS status GaveUp for HL407494+4.p
137023.27/18404.14	eprover: CPU time limit exceeded, terminating
137023.27/18404.14	% SZS status Ended for HL407494+4.p
137029.98/18405.02	% SZS status Started for HL407488+5.p
137029.98/18405.02	% SZS status GaveUp for HL407488+5.p
137029.98/18405.02	eprover: CPU time limit exceeded, terminating
137029.98/18405.02	% SZS status Ended for HL407488+5.p
137053.91/18408.01	% SZS status Started for HL407489+5.p
137053.91/18408.01	% SZS status GaveUp for HL407489+5.p
137053.91/18408.01	eprover: CPU time limit exceeded, terminating
137053.91/18408.01	% SZS status Ended for HL407489+5.p
137054.38/18408.05	% SZS status Started for HL407496+4.p
137054.38/18408.05	% SZS status GaveUp for HL407496+4.p
137054.38/18408.05	eprover: CPU time limit exceeded, terminating
137054.38/18408.05	% SZS status Ended for HL407496+4.p
137071.17/18410.23	% SZS status Started for HL407493+5.p
137071.17/18410.23	% SZS status GaveUp for HL407493+5.p
137071.17/18410.23	eprover: CPU time limit exceeded, terminating
137071.17/18410.23	% SZS status Ended for HL407493+5.p
137072.11/18410.31	% SZS status Started for HL407490+5.p
137072.11/18410.31	% SZS status GaveUp for HL407490+5.p
137072.11/18410.31	eprover: CPU time limit exceeded, terminating
137072.11/18410.31	% SZS status Ended for HL407490+5.p
137096.16/18413.35	% SZS status Started for HL407498+4.p
137096.16/18413.35	% SZS status GaveUp for HL407498+4.p
137096.16/18413.35	eprover: CPU time limit exceeded, terminating
137096.16/18413.35	% SZS status Ended for HL407498+4.p
137103.72/18414.34	% SZS status Started for HL407491+5.p
137103.72/18414.34	% SZS status GaveUp for HL407491+5.p
137103.72/18414.34	eprover: CPU time limit exceeded, terminating
137103.72/18414.34	% SZS status Ended for HL407491+5.p
137106.27/18414.62	% SZS status Started for HL407495+4.p
137106.27/18414.62	% SZS status GaveUp for HL407495+4.p
137106.27/18414.62	eprover: CPU time limit exceeded, terminating
137106.27/18414.62	% SZS status Ended for HL407495+4.p
137128.09/18417.44	% SZS status Started for HL407499+4.p
137128.09/18417.44	% SZS status GaveUp for HL407499+4.p
137128.09/18417.44	eprover: CPU time limit exceeded, terminating
137128.09/18417.44	% SZS status Ended for HL407499+4.p
137136.31/18418.53	% SZS status Started for HL407496+5.p
137136.31/18418.53	% SZS status GaveUp for HL407496+5.p
137136.31/18418.53	eprover: CPU time limit exceeded, terminating
137136.31/18418.53	% SZS status Ended for HL407496+5.p
137142.44/18419.16	% SZS status Started for HL407497+4.p
137142.44/18419.16	% SZS status GaveUp for HL407497+4.p
137142.44/18419.16	eprover: CPU time limit exceeded, terminating
137142.44/18419.16	% SZS status Ended for HL407497+4.p
137166.86/18422.25	% SZS status Started for HL407501+4.p
137166.86/18422.25	% SZS status GaveUp for HL407501+4.p
137166.86/18422.25	eprover: CPU time limit exceeded, terminating
137166.86/18422.25	% SZS status Ended for HL407501+4.p
137215.66/18428.41	% SZS status Started for HL407494+5.p
137215.66/18428.41	% SZS status GaveUp for HL407494+5.p
137215.66/18428.41	eprover: CPU time limit exceeded, terminating
137215.66/18428.41	% SZS status Ended for HL407494+5.p
137216.78/18428.66	% SZS status Started for HL407500+4.p
137216.78/18428.66	% SZS status GaveUp for HL407500+4.p
137216.78/18428.66	eprover: CPU time limit exceeded, terminating
137216.78/18428.66	% SZS status Ended for HL407500+4.p
137230.47/18430.30	% SZS status Started for HL407495+5.p
137230.47/18430.30	% SZS status GaveUp for HL407495+5.p
137230.47/18430.30	eprover: CPU time limit exceeded, terminating
137230.47/18430.30	% SZS status Ended for HL407495+5.p
137239.38/18431.44	% SZS status Started for HL407502+4.p
137239.38/18431.44	% SZS status GaveUp for HL407502+4.p
137239.38/18431.44	eprover: CPU time limit exceeded, terminating
137239.38/18431.44	% SZS status Ended for HL407502+4.p
137254.33/18433.37	% SZS status Started for HL407503+4.p
137254.33/18433.37	% SZS status GaveUp for HL407503+4.p
137254.33/18433.37	eprover: CPU time limit exceeded, terminating
137254.33/18433.37	% SZS status Ended for HL407503+4.p
137276.92/18436.15	% SZS status Started for HL407497+5.p
137276.92/18436.15	% SZS status GaveUp for HL407497+5.p
137276.92/18436.15	eprover: CPU time limit exceeded, terminating
137276.92/18436.15	% SZS status Ended for HL407497+5.p
137279.34/18436.43	% SZS status Started for HL407504+4.p
137279.34/18436.43	% SZS status GaveUp for HL407504+4.p
137279.34/18436.43	eprover: CPU time limit exceeded, terminating
137279.34/18436.43	% SZS status Ended for HL407504+4.p
137301.62/18439.22	% SZS status Started for HL407498+5.p
137301.62/18439.22	% SZS status GaveUp for HL407498+5.p
137301.62/18439.22	eprover: CPU time limit exceeded, terminating
137301.62/18439.22	% SZS status Ended for HL407498+5.p
137303.20/18439.57	% SZS status Started for HL407507+4.p
137303.20/18439.57	% SZS status GaveUp for HL407507+4.p
137303.20/18439.57	eprover: CPU time limit exceeded, terminating
137303.20/18439.57	% SZS status Ended for HL407507+4.p
137311.94/18440.52	% SZS status Started for HL407499+5.p
137311.94/18440.52	% SZS status GaveUp for HL407499+5.p
137311.94/18440.52	eprover: CPU time limit exceeded, terminating
137311.94/18440.52	% SZS status Ended for HL407499+5.p
137328.83/18442.72	% SZS status Started for HL407508+4.p
137328.83/18442.72	% SZS status GaveUp for HL407508+4.p
137328.83/18442.72	eprover: CPU time limit exceeded, terminating
137328.83/18442.72	% SZS status Ended for HL407508+4.p
137341.80/18444.33	% SZS status Started for HL407500+5.p
137341.80/18444.33	% SZS status GaveUp for HL407500+5.p
137341.80/18444.33	eprover: CPU time limit exceeded, terminating
137341.80/18444.33	% SZS status Ended for HL407500+5.p
137353.98/18445.85	% SZS status Started for HL407510+4.p
137353.98/18445.85	% SZS status GaveUp for HL407510+4.p
137353.98/18445.85	eprover: CPU time limit exceeded, terminating
137353.98/18445.85	% SZS status Ended for HL407510+4.p
137373.80/18448.32	% SZS status Started for HL407501+5.p
137373.80/18448.32	% SZS status GaveUp for HL407501+5.p
137373.80/18448.32	eprover: CPU time limit exceeded, terminating
137373.80/18448.32	% SZS status Ended for HL407501+5.p
137378.17/18448.88	% SZS status Started for HL407512+4.p
137378.17/18448.88	% SZS status GaveUp for HL407512+4.p
137378.17/18448.88	eprover: CPU time limit exceeded, terminating
137378.17/18448.88	% SZS status Ended for HL407512+4.p
137402.50/18451.92	% SZS status Started for HL407513+4.p
137402.50/18451.92	% SZS status GaveUp for HL407513+4.p
137402.50/18451.92	eprover: CPU time limit exceeded, terminating
137402.50/18451.92	% SZS status Ended for HL407513+4.p
137424.33/18454.72	% SZS status Started for HL407502+5.p
137424.33/18454.72	% SZS status GaveUp for HL407502+5.p
137424.33/18454.72	eprover: CPU time limit exceeded, terminating
137424.33/18454.72	% SZS status Ended for HL407502+5.p
137444.92/18457.32	% SZS status Started for HL407503+5.p
137444.92/18457.32	% SZS status GaveUp for HL407503+5.p
137444.92/18457.32	eprover: CPU time limit exceeded, terminating
137444.92/18457.32	% SZS status Ended for HL407503+5.p
137448.80/18457.77	% SZS status Started for HL407514+4.p
137448.80/18457.77	% SZS status GaveUp for HL407514+4.p
137448.80/18457.77	eprover: CPU time limit exceeded, terminating
137448.80/18457.77	% SZS status Ended for HL407514+4.p
137482.08/18461.94	% SZS status Started for HL407504+5.p
137482.08/18461.94	% SZS status GaveUp for HL407504+5.p
137482.08/18461.94	eprover: CPU time limit exceeded, terminating
137482.08/18461.94	% SZS status Ended for HL407504+5.p
137485.23/18462.39	% SZS status Started for HL407513+5.p
137485.23/18462.39	% SZS status GaveUp for HL407513+5.p
137485.23/18462.39	eprover: CPU time limit exceeded, terminating
137485.23/18462.39	% SZS status Ended for HL407513+5.p
137507.86/18465.31	% SZS status Started for HL407507+5.p
137507.86/18465.31	% SZS status GaveUp for HL407507+5.p
137507.86/18465.31	eprover: CPU time limit exceeded, terminating
137507.86/18465.31	% SZS status Ended for HL407507+5.p
137509.58/18465.43	% SZS status Started for HL407517+4.p
137509.58/18465.43	% SZS status GaveUp for HL407517+4.p
137509.58/18465.43	eprover: CPU time limit exceeded, terminating
137509.58/18465.43	% SZS status Ended for HL407517+4.p
137517.30/18466.43	% SZS status Started for HL407508+5.p
137517.30/18466.43	% SZS status GaveUp for HL407508+5.p
137517.30/18466.43	eprover: CPU time limit exceeded, terminating
137517.30/18466.43	% SZS status Ended for HL407508+5.p
137528.95/18467.87	% SZS status Started for HL407516+4.p
137528.95/18467.87	% SZS status GaveUp for HL407516+4.p
137528.95/18467.87	eprover: CPU time limit exceeded, terminating
137528.95/18467.87	% SZS status Ended for HL407516+4.p
137533.47/18468.46	% SZS status Started for HL407518+4.p
137533.47/18468.46	% SZS status GaveUp for HL407518+4.p
137533.47/18468.46	eprover: CPU time limit exceeded, terminating
137533.47/18468.46	% SZS status Ended for HL407518+4.p
137548.09/18470.42	% SZS status Started for HL407510+5.p
137548.09/18470.42	% SZS status GaveUp for HL407510+5.p
137548.09/18470.42	eprover: CPU time limit exceeded, terminating
137548.09/18470.42	% SZS status Ended for HL407510+5.p
137573.59/18473.48	% SZS status Started for HL407520+4.p
137573.59/18473.48	% SZS status GaveUp for HL407520+4.p
137573.59/18473.48	eprover: CPU time limit exceeded, terminating
137573.59/18473.48	% SZS status Ended for HL407520+4.p
137579.14/18474.22	% SZS status Started for HL407512+5.p
137579.14/18474.22	% SZS status GaveUp for HL407512+5.p
137579.14/18474.22	eprover: CPU time limit exceeded, terminating
137579.14/18474.22	% SZS status Ended for HL407512+5.p
137603.50/18477.30	% SZS status Started for HL407521+4.p
137603.50/18477.30	% SZS status GaveUp for HL407521+4.p
137603.50/18477.30	eprover: CPU time limit exceeded, terminating
137603.50/18477.30	% SZS status Ended for HL407521+4.p
137618.22/18479.14	% SZS status Started for HL407519+4.p
137618.22/18479.14	% SZS status GaveUp for HL407519+4.p
137618.22/18479.14	eprover: CPU time limit exceeded, terminating
137618.22/18479.14	% SZS status Ended for HL407519+4.p
137642.97/18482.27	% SZS status Started for HL407522+4.p
137642.97/18482.27	% SZS status GaveUp for HL407522+4.p
137642.97/18482.27	eprover: CPU time limit exceeded, terminating
137642.97/18482.27	% SZS status Ended for HL407522+4.p
137652.77/18483.53	% SZS status Started for HL407514+5.p
137652.77/18483.53	% SZS status GaveUp for HL407514+5.p
137652.77/18483.53	eprover: CPU time limit exceeded, terminating
137652.77/18483.53	% SZS status Ended for HL407514+5.p
137677.39/18486.58	% SZS status Started for HL407525+4.p
137677.39/18486.58	% SZS status GaveUp for HL407525+4.p
137677.39/18486.58	eprover: CPU time limit exceeded, terminating
137677.39/18486.58	% SZS status Ended for HL407525+4.p
137688.98/18488.06	% SZS status Started for HL407516+5.p
137688.98/18488.06	% SZS status GaveUp for HL407516+5.p
137688.98/18488.06	eprover: CPU time limit exceeded, terminating
137688.98/18488.06	% SZS status Ended for HL407516+5.p
137712.98/18491.09	% SZS status Started for HL407526+4.p
137712.98/18491.09	% SZS status GaveUp for HL407526+4.p
137712.98/18491.09	eprover: CPU time limit exceeded, terminating
137712.98/18491.09	% SZS status Ended for HL407526+4.p
137713.94/18491.25	% SZS status Started for HL407517+5.p
137713.94/18491.25	% SZS status GaveUp for HL407517+5.p
137713.94/18491.25	eprover: CPU time limit exceeded, terminating
137713.94/18491.25	% SZS status Ended for HL407517+5.p
137724.31/18492.47	% SZS status Started for HL407518+5.p
137724.31/18492.47	% SZS status GaveUp for HL407518+5.p
137724.31/18492.47	eprover: CPU time limit exceeded, terminating
137724.31/18492.47	% SZS status Ended for HL407518+5.p
137738.80/18494.34	% SZS status Started for HL407519+5.p
137738.80/18494.34	% SZS status GaveUp for HL407519+5.p
137738.80/18494.34	eprover: CPU time limit exceeded, terminating
137738.80/18494.34	% SZS status Ended for HL407519+5.p
137762.36/18497.39	% SZS status Started for HL407529+4.p
137762.36/18497.39	% SZS status GaveUp for HL407529+4.p
137762.36/18497.39	eprover: CPU time limit exceeded, terminating
137762.36/18497.39	% SZS status Ended for HL407529+4.p
137782.45/18499.88	% SZS status Started for HL407520+5.p
137782.45/18499.88	% SZS status GaveUp for HL407520+5.p
137782.45/18499.88	eprover: CPU time limit exceeded, terminating
137782.45/18499.88	% SZS status Ended for HL407520+5.p
137802.78/18502.39	% SZS status Started for HL407527+4.p
137802.78/18502.39	% SZS status GaveUp for HL407527+4.p
137802.78/18502.39	eprover: CPU time limit exceeded, terminating
137802.78/18502.39	% SZS status Ended for HL407527+4.p
137806.28/18502.93	% SZS status Started for HL407530+4.p
137806.28/18502.93	% SZS status GaveUp for HL407530+4.p
137806.28/18502.93	eprover: CPU time limit exceeded, terminating
137806.28/18502.93	% SZS status Ended for HL407530+4.p
137809.45/18503.23	% SZS status Started for HL407521+5.p
137809.45/18503.23	% SZS status GaveUp for HL407521+5.p
137809.45/18503.23	eprover: CPU time limit exceeded, terminating
137809.45/18503.23	% SZS status Ended for HL407521+5.p
137831.06/18505.96	% SZS status Started for HL407532+4.p
137831.06/18505.96	% SZS status GaveUp for HL407532+4.p
137831.06/18505.96	eprover: CPU time limit exceeded, terminating
137831.06/18505.96	% SZS status Ended for HL407532+4.p
137851.72/18508.60	% SZS status Started for HL407522+5.p
137851.72/18508.60	% SZS status GaveUp for HL407522+5.p
137851.72/18508.60	eprover: CPU time limit exceeded, terminating
137851.72/18508.60	% SZS status Ended for HL407522+5.p
137855.09/18508.98	% SZS status Started for HL407533+4.p
137855.09/18508.98	% SZS status GaveUp for HL407533+4.p
137855.09/18508.98	eprover: CPU time limit exceeded, terminating
137855.09/18508.98	% SZS status Ended for HL407533+4.p
137878.98/18512.01	% SZS status Started for HL407534+4.p
137878.98/18512.01	% SZS status GaveUp for HL407534+4.p
137878.98/18512.01	eprover: CPU time limit exceeded, terminating
137878.98/18512.01	% SZS status Ended for HL407534+4.p
137883.08/18512.54	% SZS status Started for HL407525+5.p
137883.08/18512.54	% SZS status GaveUp for HL407525+5.p
137883.08/18512.54	eprover: CPU time limit exceeded, terminating
137883.08/18512.54	% SZS status Ended for HL407525+5.p
137907.33/18515.57	% SZS status Started for HL407535+4.p
137907.33/18515.57	% SZS status GaveUp for HL407535+4.p
137907.33/18515.57	eprover: CPU time limit exceeded, terminating
137907.33/18515.57	% SZS status Ended for HL407535+4.p
137921.23/18517.32	% SZS status Started for HL407526+5.p
137921.23/18517.32	% SZS status GaveUp for HL407526+5.p
137921.23/18517.32	eprover: CPU time limit exceeded, terminating
137921.23/18517.32	% SZS status Ended for HL407526+5.p
137929.84/18518.44	% SZS status Started for HL407527+5.p
137929.84/18518.44	% SZS status GaveUp for HL407527+5.p
137929.84/18518.44	eprover: CPU time limit exceeded, terminating
137929.84/18518.44	% SZS status Ended for HL407527+5.p
137944.66/18520.35	% SZS status Started for HL407536+4.p
137944.66/18520.35	% SZS status GaveUp for HL407536+4.p
137944.66/18520.35	eprover: CPU time limit exceeded, terminating
137944.66/18520.35	% SZS status Ended for HL407536+4.p
137968.67/18523.38	% SZS status Started for HL407537+4.p
137968.67/18523.38	% SZS status GaveUp for HL407537+4.p
137968.67/18523.38	eprover: CPU time limit exceeded, terminating
137968.67/18523.38	% SZS status Ended for HL407537+4.p
137969.83/18523.43	% SZS status Started for HL407529+5.p
137969.83/18523.43	% SZS status GaveUp for HL407529+5.p
137969.83/18523.43	eprover: CPU time limit exceeded, terminating
137969.83/18523.43	% SZS status Ended for HL407529+5.p
137993.69/18526.45	% SZS status Started for HL407538+4.p
137993.69/18526.45	% SZS status GaveUp for HL407538+4.p
137993.69/18526.45	eprover: CPU time limit exceeded, terminating
137993.69/18526.45	% SZS status Ended for HL407538+4.p
138009.33/18528.41	% SZS status Started for HL407530+5.p
138009.33/18528.41	% SZS status GaveUp for HL407530+5.p
138009.33/18528.41	eprover: CPU time limit exceeded, terminating
138009.33/18528.41	% SZS status Ended for HL407530+5.p
138014.97/18529.18	% SZS status Started for HL407532+5.p
138014.97/18529.18	% SZS status GaveUp for HL407532+5.p
138014.97/18529.18	eprover: CPU time limit exceeded, terminating
138014.97/18529.18	% SZS status Ended for HL407532+5.p
138032.95/18531.48	% SZS status Started for HL407539+4.p
138032.95/18531.48	% SZS status GaveUp for HL407539+4.p
138032.95/18531.48	eprover: CPU time limit exceeded, terminating
138032.95/18531.48	% SZS status Ended for HL407539+4.p
138058.95/18534.64	% SZS status Started for HL407540+4.p
138058.95/18534.64	% SZS status GaveUp for HL407540+4.p
138058.95/18534.64	eprover: CPU time limit exceeded, terminating
138058.95/18534.64	% SZS status Ended for HL407540+4.p
138059.30/18534.72	% SZS status Started for HL407533+5.p
138059.30/18534.72	% SZS status GaveUp for HL407533+5.p
138059.30/18534.72	eprover: CPU time limit exceeded, terminating
138059.30/18534.72	% SZS status Ended for HL407533+5.p
138083.36/18537.76	% SZS status Started for HL407542+4.p
138083.36/18537.76	% SZS status GaveUp for HL407542+4.p
138083.36/18537.76	eprover: CPU time limit exceeded, terminating
138083.36/18537.76	% SZS status Ended for HL407542+4.p
138085.11/18537.97	% SZS status Started for HL407534+5.p
138085.11/18537.97	% SZS status GaveUp for HL407534+5.p
138085.11/18537.97	eprover: CPU time limit exceeded, terminating
138085.11/18537.97	% SZS status Ended for HL407534+5.p
138109.34/18541.05	% SZS status Started for HL407543+4.p
138109.34/18541.05	% SZS status GaveUp for HL407543+4.p
138109.34/18541.05	eprover: CPU time limit exceeded, terminating
138109.34/18541.05	% SZS status Ended for HL407543+4.p
138112.86/18541.45	% SZS status Started for HL407535+5.p
138112.86/18541.45	% SZS status GaveUp for HL407535+5.p
138112.86/18541.45	eprover: CPU time limit exceeded, terminating
138112.86/18541.45	% SZS status Ended for HL407535+5.p
138136.12/18544.40	% SZS status Started for HL407536+5.p
138136.12/18544.40	% SZS status GaveUp for HL407536+5.p
138136.12/18544.40	eprover: CPU time limit exceeded, terminating
138136.12/18544.40	% SZS status Ended for HL407536+5.p
138136.81/18544.49	% SZS status Started for HL407544+4.p
138136.81/18544.49	% SZS status GaveUp for HL407544+4.p
138136.81/18544.49	eprover: CPU time limit exceeded, terminating
138136.81/18544.49	% SZS status Ended for HL407544+4.p
138161.19/18547.54	% SZS status Started for HL407545+4.p
138161.19/18547.54	% SZS status GaveUp for HL407545+4.p
138161.19/18547.54	eprover: CPU time limit exceeded, terminating
138161.19/18547.54	% SZS status Ended for HL407545+4.p
138174.66/18549.25	% SZS status Started for HL407537+5.p
138174.66/18549.25	% SZS status GaveUp for HL407537+5.p
138174.66/18549.25	eprover: CPU time limit exceeded, terminating
138174.66/18549.25	% SZS status Ended for HL407537+5.p
138199.03/18552.30	% SZS status Started for HL407546+4.p
138199.03/18552.30	% SZS status GaveUp for HL407546+4.p
138199.03/18552.30	eprover: CPU time limit exceeded, terminating
138199.03/18552.30	% SZS status Ended for HL407546+4.p
138200.30/18552.48	% SZS status Started for HL407538+5.p
138200.30/18552.48	% SZS status GaveUp for HL407538+5.p
138200.30/18552.48	eprover: CPU time limit exceeded, terminating
138200.30/18552.48	% SZS status Ended for HL407538+5.p
138220.44/18555.02	% SZS status Started for HL407539+5.p
138220.44/18555.02	% SZS status GaveUp for HL407539+5.p
138220.44/18555.02	eprover: CPU time limit exceeded, terminating
138220.44/18555.02	% SZS status Ended for HL407539+5.p
138225.23/18555.61	% SZS status Started for HL407547+4.p
138225.23/18555.61	% SZS status GaveUp for HL407547+4.p
138225.23/18555.61	eprover: CPU time limit exceeded, terminating
138225.23/18555.61	% SZS status Ended for HL407547+4.p
138249.58/18558.68	% SZS status Started for HL407548+4.p
138249.58/18558.68	% SZS status GaveUp for HL407548+4.p
138249.58/18558.68	eprover: CPU time limit exceeded, terminating
138249.58/18558.68	% SZS status Ended for HL407548+4.p
138265.48/18560.70	% SZS status Started for HL407540+5.p
138265.48/18560.70	% SZS status GaveUp for HL407540+5.p
138265.48/18560.70	eprover: CPU time limit exceeded, terminating
138265.48/18560.70	% SZS status Ended for HL407540+5.p
138288.42/18563.56	% SZS status Started for HL407542+5.p
138288.42/18563.56	% SZS status GaveUp for HL407542+5.p
138288.42/18563.56	eprover: CPU time limit exceeded, terminating
138288.42/18563.56	% SZS status Ended for HL407542+5.p
138290.66/18563.85	% SZS status Started for HL407549+4.p
138290.66/18563.85	% SZS status GaveUp for HL407549+4.p
138290.66/18563.85	eprover: CPU time limit exceeded, terminating
138290.66/18563.85	% SZS status Ended for HL407549+4.p
138314.84/18566.90	% SZS status Started for HL407550+4.p
138314.84/18566.90	% SZS status GaveUp for HL407550+4.p
138314.84/18566.90	eprover: CPU time limit exceeded, terminating
138314.84/18566.90	% SZS status Ended for HL407550+4.p
138315.73/18567.02	% SZS status Started for HL407543+5.p
138315.73/18567.02	% SZS status GaveUp for HL407543+5.p
138315.73/18567.02	eprover: CPU time limit exceeded, terminating
138315.73/18567.02	% SZS status Ended for HL407543+5.p
138340.05/18570.05	% SZS status Started for HL407551+4.p
138340.05/18570.05	% SZS status GaveUp for HL407551+4.p
138340.05/18570.05	eprover: CPU time limit exceeded, terminating
138340.05/18570.05	% SZS status Ended for HL407551+4.p
138343.64/18570.51	% SZS status Started for HL407544+5.p
138343.64/18570.51	% SZS status GaveUp for HL407544+5.p
138343.64/18570.51	eprover: CPU time limit exceeded, terminating
138343.64/18570.51	% SZS status Ended for HL407544+5.p
138367.53/18573.53	% SZS status Started for HL407545+5.p
138367.53/18573.53	% SZS status GaveUp for HL407545+5.p
138367.53/18573.53	eprover: CPU time limit exceeded, terminating
138367.53/18573.53	% SZS status Ended for HL407545+5.p
138367.53/18573.56	% SZS status Started for HL407552+4.p
138367.53/18573.56	% SZS status GaveUp for HL407552+4.p
138367.53/18573.56	eprover: CPU time limit exceeded, terminating
138367.53/18573.56	% SZS status Ended for HL407552+4.p
138391.69/18576.59	% SZS status Started for HL407553+4.p
138391.69/18576.59	% SZS status GaveUp for HL407553+4.p
138391.69/18576.59	eprover: CPU time limit exceeded, terminating
138391.69/18576.59	% SZS status Ended for HL407553+4.p
138398.45/18577.43	% SZS status Started for HL407550+5.p
138398.45/18577.43	% SZS status GaveUp for HL407550+5.p
138398.45/18577.43	eprover: CPU time limit exceeded, terminating
138398.45/18577.43	% SZS status Ended for HL407550+5.p
138405.12/18578.25	% SZS status Started for HL407546+5.p
138405.12/18578.25	% SZS status GaveUp for HL407546+5.p
138405.12/18578.25	eprover: CPU time limit exceeded, terminating
138405.12/18578.25	% SZS status Ended for HL407546+5.p
138422.41/18580.49	% SZS status Started for HL407554+4.p
138422.41/18580.49	% SZS status GaveUp for HL407554+4.p
138422.41/18580.49	eprover: CPU time limit exceeded, terminating
138422.41/18580.49	% SZS status Ended for HL407554+4.p
138425.80/18580.83	% SZS status Started for HL407547+5.p
138425.80/18580.83	% SZS status GaveUp for HL407547+5.p
138425.80/18580.83	eprover: CPU time limit exceeded, terminating
138425.80/18580.83	% SZS status Ended for HL407547+5.p
138447.34/18583.55	% SZS status Started for HL407555+4.p
138447.34/18583.55	% SZS status GaveUp for HL407555+4.p
138447.34/18583.55	eprover: CPU time limit exceeded, terminating
138447.34/18583.55	% SZS status Ended for HL407555+4.p
138454.73/18584.48	% SZS status Started for HL407548+5.p
138454.73/18584.48	% SZS status GaveUp for HL407548+5.p
138454.73/18584.48	eprover: CPU time limit exceeded, terminating
138454.73/18584.48	% SZS status Ended for HL407548+5.p
138471.38/18586.61	% SZS status Started for HL407556+4.p
138471.38/18586.61	% SZS status GaveUp for HL407556+4.p
138471.38/18586.61	eprover: CPU time limit exceeded, terminating
138471.38/18586.61	% SZS status Ended for HL407556+4.p
138493.31/18589.40	% SZS status Started for HL407549+5.p
138493.31/18589.40	% SZS status GaveUp for HL407549+5.p
138493.31/18589.40	eprover: CPU time limit exceeded, terminating
138493.31/18589.40	% SZS status Ended for HL407549+5.p
138496.34/18589.74	% SZS status Started for HL407557+4.p
138496.34/18589.74	% SZS status GaveUp for HL407557+4.p
138496.34/18589.74	eprover: CPU time limit exceeded, terminating
138496.34/18589.74	% SZS status Ended for HL407557+4.p
138504.44/18590.74	% SZS status Started for HL407553+5.p
138504.44/18590.74	% SZS status GaveUp for HL407553+5.p
138504.44/18590.74	eprover: CPU time limit exceeded, terminating
138504.44/18590.74	% SZS status Ended for HL407553+5.p
138521.34/18592.89	% SZS status Started for HL407558+4.p
138521.34/18592.89	% SZS status GaveUp for HL407558+4.p
138521.34/18592.89	eprover: CPU time limit exceeded, terminating
138521.34/18592.89	% SZS status Ended for HL407558+4.p
138545.08/18595.88	% SZS status Started for HL407551+5.p
138545.08/18595.88	% SZS status GaveUp for HL407551+5.p
138545.08/18595.88	eprover: CPU time limit exceeded, terminating
138545.08/18595.88	% SZS status Ended for HL407551+5.p
138545.53/18595.94	% SZS status Started for HL407559+4.p
138545.53/18595.94	% SZS status GaveUp for HL407559+4.p
138545.53/18595.94	eprover: CPU time limit exceeded, terminating
138545.53/18595.94	% SZS status Ended for HL407559+4.p
138569.62/18599.02	% SZS status Started for HL407561+4.p
138569.62/18599.02	% SZS status GaveUp for HL407561+4.p
138569.62/18599.02	eprover: CPU time limit exceeded, terminating
138569.62/18599.02	% SZS status Ended for HL407561+4.p
138572.66/18599.47	% SZS status Started for HL407552+5.p
138572.66/18599.47	% SZS status GaveUp for HL407552+5.p
138572.66/18599.47	eprover: CPU time limit exceeded, terminating
138572.66/18599.47	% SZS status Ended for HL407552+5.p
138575.86/18599.73	% SZS status Started for HL407557+5.p
138575.86/18599.73	% SZS status GaveUp for HL407557+5.p
138575.86/18599.73	eprover: CPU time limit exceeded, terminating
138575.86/18599.73	% SZS status Ended for HL407557+5.p
138597.80/18602.50	% SZS status Started for HL407562+4.p
138597.80/18602.50	% SZS status GaveUp for HL407562+4.p
138597.80/18602.50	eprover: CPU time limit exceeded, terminating
138597.80/18602.50	% SZS status Ended for HL407562+4.p
138611.61/18604.27	% SZS status Started for HL407554+5.p
138611.61/18604.27	% SZS status GaveUp for HL407554+5.p
138611.61/18604.27	eprover: CPU time limit exceeded, terminating
138611.61/18604.27	% SZS status Ended for HL407554+5.p
138621.62/18605.56	% SZS status Started for HL407563+4.p
138621.62/18605.56	% SZS status GaveUp for HL407563+4.p
138621.62/18605.56	eprover: CPU time limit exceeded, terminating
138621.62/18605.56	% SZS status Ended for HL407563+4.p
138625.72/18606.10	% SZS status Started for HL407559+5.p
138625.72/18606.10	% SZS status GaveUp for HL407559+5.p
138625.72/18606.10	eprover: CPU time limit exceeded, terminating
138625.72/18606.10	% SZS status Ended for HL407559+5.p
138633.05/18607.00	% SZS status Started for HL407555+5.p
138633.05/18607.00	% SZS status GaveUp for HL407555+5.p
138633.05/18607.00	eprover: CPU time limit exceeded, terminating
138633.05/18607.00	% SZS status Ended for HL407555+5.p
138646.09/18608.61	% SZS status Started for HL407565+4.p
138646.09/18608.61	% SZS status GaveUp for HL407565+4.p
138646.09/18608.61	eprover: CPU time limit exceeded, terminating
138646.09/18608.61	% SZS status Ended for HL407565+4.p
138657.39/18610.04	% SZS status Started for HL407566+4.p
138657.39/18610.04	% SZS status GaveUp for HL407566+4.p
138657.39/18610.04	eprover: CPU time limit exceeded, terminating
138657.39/18610.04	% SZS status Ended for HL407566+4.p
138660.03/18610.35	% SZS status Started for HL407556+5.p
138660.03/18610.35	% SZS status GaveUp for HL407556+5.p
138660.03/18610.35	eprover: CPU time limit exceeded, terminating
138660.03/18610.35	% SZS status Ended for HL407556+5.p
138681.88/18613.10	% SZS status Started for HL407567+4.p
138681.88/18613.10	% SZS status GaveUp for HL407567+4.p
138681.88/18613.10	eprover: CPU time limit exceeded, terminating
138681.88/18613.10	% SZS status Ended for HL407567+4.p
138705.61/18616.14	% SZS status Started for HL407568+4.p
138705.61/18616.14	% SZS status GaveUp for HL407568+4.p
138705.61/18616.14	eprover: CPU time limit exceeded, terminating
138705.61/18616.14	% SZS status Ended for HL407568+4.p
138710.47/18616.77	% SZS status Started for HL407558+5.p
138710.47/18616.77	% SZS status GaveUp for HL407558+5.p
138710.47/18616.77	eprover: CPU time limit exceeded, terminating
138710.47/18616.77	% SZS status Ended for HL407558+5.p
138734.67/18619.81	% SZS status Started for HL407569+4.p
138734.67/18619.81	% SZS status GaveUp for HL407569+4.p
138734.67/18619.81	eprover: CPU time limit exceeded, terminating
138734.67/18619.81	% SZS status Ended for HL407569+4.p
138774.89/18624.86	% SZS status Started for HL407561+5.p
138774.89/18624.86	% SZS status GaveUp for HL407561+5.p
138774.89/18624.86	eprover: CPU time limit exceeded, terminating
138774.89/18624.86	% SZS status Ended for HL407561+5.p
138782.17/18625.74	% SZS status Started for HL407562+5.p
138782.17/18625.74	% SZS status GaveUp for HL407562+5.p
138782.17/18625.74	eprover: CPU time limit exceeded, terminating
138782.17/18625.74	% SZS status Ended for HL407562+5.p
138799.42/18627.92	% SZS status Started for HL407570+4.p
138799.42/18627.92	% SZS status GaveUp for HL407570+4.p
138799.42/18627.92	eprover: CPU time limit exceeded, terminating
138799.42/18627.92	% SZS status Ended for HL407570+4.p
138818.48/18630.29	% SZS status Started for HL407563+5.p
138818.48/18630.29	% SZS status GaveUp for HL407563+5.p
138818.48/18630.29	eprover: CPU time limit exceeded, terminating
138818.48/18630.29	% SZS status Ended for HL407563+5.p
138823.14/18630.95	% SZS status Started for HL407571+4.p
138823.14/18630.95	% SZS status GaveUp for HL407571+4.p
138823.14/18630.95	eprover: CPU time limit exceeded, terminating
138823.14/18630.95	% SZS status Ended for HL407571+4.p
138833.97/18632.29	% SZS status Started for HL407565+5.p
138833.97/18632.29	% SZS status GaveUp for HL407565+5.p
138833.97/18632.29	eprover: CPU time limit exceeded, terminating
138833.97/18632.29	% SZS status Ended for HL407565+5.p
138846.53/18634.00	% SZS status Started for HL407572+4.p
138846.53/18634.00	% SZS status GaveUp for HL407572+4.p
138846.53/18634.00	eprover: CPU time limit exceeded, terminating
138846.53/18634.00	% SZS status Ended for HL407572+4.p
138852.42/18634.59	% SZS status Started for HL407566+5.p
138852.42/18634.59	% SZS status GaveUp for HL407566+5.p
138852.42/18634.59	eprover: CPU time limit exceeded, terminating
138852.42/18634.59	% SZS status Ended for HL407566+5.p
138867.98/18636.61	% SZS status Started for HL407567+5.p
138867.98/18636.61	% SZS status GaveUp for HL407567+5.p
138867.98/18636.61	eprover: CPU time limit exceeded, terminating
138867.98/18636.61	% SZS status Ended for HL407567+5.p
138871.77/18637.06	% SZS status Started for HL407574+4.p
138871.77/18637.06	% SZS status GaveUp for HL407574+4.p
138871.77/18637.06	eprover: CPU time limit exceeded, terminating
138871.77/18637.06	% SZS status Ended for HL407574+4.p
138891.88/18639.65	% SZS status Started for HL407575+4.p
138891.88/18639.65	% SZS status GaveUp for HL407575+4.p
138891.88/18639.65	eprover: CPU time limit exceeded, terminating
138891.88/18639.65	% SZS status Ended for HL407575+4.p
138913.64/18642.29	% SZS status Started for HL407568+5.p
138913.64/18642.29	% SZS status GaveUp for HL407568+5.p
138913.64/18642.29	eprover: CPU time limit exceeded, terminating
138913.64/18642.29	% SZS status Ended for HL407568+5.p
138917.09/18642.76	% SZS status Started for HL407576+4.p
138917.09/18642.76	% SZS status GaveUp for HL407576+4.p
138917.09/18642.76	eprover: CPU time limit exceeded, terminating
138917.09/18642.76	% SZS status Ended for HL407576+4.p
138940.44/18645.67	% SZS status Started for HL407569+5.p
138940.44/18645.67	% SZS status GaveUp for HL407569+5.p
138940.44/18645.67	eprover: CPU time limit exceeded, terminating
138940.44/18645.67	% SZS status Ended for HL407569+5.p
138941.16/18645.79	% SZS status Started for HL407578+4.p
138941.16/18645.79	% SZS status GaveUp for HL407578+4.p
138941.16/18645.79	eprover: CPU time limit exceeded, terminating
138941.16/18645.79	% SZS status Ended for HL407578+4.p
138964.91/18648.82	% SZS status Started for HL407579+4.p
138964.91/18648.82	% SZS status GaveUp for HL407579+4.p
138964.91/18648.82	eprover: CPU time limit exceeded, terminating
138964.91/18648.82	% SZS status Ended for HL407579+4.p
138989.03/18651.76	% SZS status Started for HL407570+5.p
138989.03/18651.76	% SZS status GaveUp for HL407570+5.p
138989.03/18651.76	eprover: CPU time limit exceeded, terminating
138989.03/18651.76	% SZS status Ended for HL407570+5.p
139012.97/18654.81	% SZS status Started for HL407580+4.p
139012.97/18654.81	% SZS status GaveUp for HL407580+4.p
139012.97/18654.81	eprover: CPU time limit exceeded, terminating
139012.97/18654.81	% SZS status Ended for HL407580+4.p
139024.23/18656.23	% SZS status Started for HL407571+5.p
139024.23/18656.23	% SZS status GaveUp for HL407571+5.p
139024.23/18656.23	eprover: CPU time limit exceeded, terminating
139024.23/18656.23	% SZS status Ended for HL407571+5.p
139040.83/18658.29	% SZS status Started for HL407572+5.p
139040.83/18658.29	% SZS status GaveUp for HL407572+5.p
139040.83/18658.29	eprover: CPU time limit exceeded, terminating
139040.83/18658.29	% SZS status Ended for HL407572+5.p
139049.09/18659.31	% SZS status Started for HL407581+4.p
139049.09/18659.31	% SZS status GaveUp for HL407581+4.p
139049.09/18659.31	eprover: CPU time limit exceeded, terminating
139049.09/18659.31	% SZS status Ended for HL407581+4.p
139057.66/18660.42	% SZS status Started for HL407574+5.p
139057.66/18660.42	% SZS status GaveUp for HL407574+5.p
139057.66/18660.42	eprover: CPU time limit exceeded, terminating
139057.66/18660.42	% SZS status Ended for HL407574+5.p
139073.11/18662.35	% SZS status Started for HL407582+4.p
139073.11/18662.35	% SZS status GaveUp for HL407582+4.p
139073.11/18662.35	eprover: CPU time limit exceeded, terminating
139073.11/18662.35	% SZS status Ended for HL407582+4.p
139076.20/18662.88	% SZS status Started for HL407575+5.p
139076.20/18662.88	% SZS status GaveUp for HL407575+5.p
139076.20/18662.88	eprover: CPU time limit exceeded, terminating
139076.20/18662.88	% SZS status Ended for HL407575+5.p
139097.61/18665.43	% SZS status Started for HL407583+4.p
139097.61/18665.43	% SZS status GaveUp for HL407583+4.p
139097.61/18665.43	eprover: CPU time limit exceeded, terminating
139097.61/18665.43	% SZS status Ended for HL407583+4.p
139120.72/18668.38	% SZS status Started for HL407576+5.p
139120.72/18668.38	% SZS status GaveUp for HL407576+5.p
139120.72/18668.38	eprover: CPU time limit exceeded, terminating
139120.72/18668.38	% SZS status Ended for HL407576+5.p
139122.14/18668.48	% SZS status Started for HL407584+4.p
139122.14/18668.48	% SZS status GaveUp for HL407584+4.p
139122.14/18668.48	eprover: CPU time limit exceeded, terminating
139122.14/18668.48	% SZS status Ended for HL407584+4.p
139145.80/18671.53	% SZS status Started for HL407585+4.p
139145.80/18671.53	% SZS status GaveUp for HL407585+4.p
139145.80/18671.53	eprover: CPU time limit exceeded, terminating
139145.80/18671.53	% SZS status Ended for HL407585+4.p
139146.25/18671.58	% SZS status Started for HL407578+5.p
139146.25/18671.58	% SZS status GaveUp for HL407578+5.p
139146.25/18671.58	eprover: CPU time limit exceeded, terminating
139146.25/18671.58	% SZS status Ended for HL407578+5.p
139159.42/18673.19	% SZS status Started for HL407583+5.p
139159.42/18673.19	% SZS status GaveUp for HL407583+5.p
139159.42/18673.19	eprover: CPU time limit exceeded, terminating
139159.42/18673.19	% SZS status Ended for HL407583+5.p
139170.52/18674.64	% SZS status Started for HL407586+4.p
139170.52/18674.64	% SZS status GaveUp for HL407586+4.p
139170.52/18674.64	eprover: CPU time limit exceeded, terminating
139170.52/18674.64	% SZS status Ended for HL407586+4.p
139170.52/18674.65	% SZS status Started for HL407579+5.p
139170.52/18674.65	% SZS status GaveUp for HL407579+5.p
139170.52/18674.65	eprover: CPU time limit exceeded, terminating
139170.52/18674.65	% SZS status Ended for HL407579+5.p
139195.31/18677.73	% SZS status Started for HL407587+4.p
139195.31/18677.73	% SZS status GaveUp for HL407587+4.p
139195.31/18677.73	eprover: CPU time limit exceeded, terminating
139195.31/18677.73	% SZS status Ended for HL407587+4.p
139203.45/18678.73	% SZS status Started for HL407584+5.p
139203.45/18678.73	% SZS status GaveUp for HL407584+5.p
139203.45/18678.73	eprover: CPU time limit exceeded, terminating
139203.45/18678.73	% SZS status Ended for HL407584+5.p
139219.31/18680.80	% SZS status Started for HL407588+4.p
139219.31/18680.80	% SZS status GaveUp for HL407588+4.p
139219.31/18680.80	eprover: CPU time limit exceeded, terminating
139219.31/18680.80	% SZS status Ended for HL407588+4.p
139220.48/18680.89	% SZS status Started for HL407580+5.p
139220.48/18680.89	% SZS status GaveUp for HL407580+5.p
139220.48/18680.89	eprover: CPU time limit exceeded, terminating
139220.48/18680.89	% SZS status Ended for HL407580+5.p
139243.88/18683.87	% SZS status Started for HL407589+4.p
139243.88/18683.87	% SZS status GaveUp for HL407589+4.p
139243.88/18683.87	eprover: CPU time limit exceeded, terminating
139243.88/18683.87	% SZS status Ended for HL407589+4.p
139248.33/18684.41	% SZS status Started for HL407581+5.p
139248.33/18684.41	% SZS status GaveUp for HL407581+5.p
139248.33/18684.41	eprover: CPU time limit exceeded, terminating
139248.33/18684.41	% SZS status Ended for HL407581+5.p
139263.14/18686.28	% SZS status Started for HL407582+5.p
139263.14/18686.28	% SZS status GaveUp for HL407582+5.p
139263.14/18686.28	eprover: CPU time limit exceeded, terminating
139263.14/18686.28	% SZS status Ended for HL407582+5.p
139267.47/18686.92	% SZS status Started for HL407590+4.p
139267.47/18686.92	% SZS status GaveUp for HL407590+4.p
139267.47/18686.92	eprover: CPU time limit exceeded, terminating
139267.47/18686.92	% SZS status Ended for HL407590+4.p
139287.48/18689.32	% SZS status Started for HL407591+4.p
139287.48/18689.32	% SZS status GaveUp for HL407591+4.p
139287.48/18689.32	eprover: CPU time limit exceeded, terminating
139287.48/18689.32	% SZS status Ended for HL407591+4.p
139312.20/18692.44	% SZS status Started for HL407592+4.p
139312.20/18692.44	% SZS status GaveUp for HL407592+4.p
139312.20/18692.44	eprover: CPU time limit exceeded, terminating
139312.20/18692.44	% SZS status Ended for HL407592+4.p
139350.86/18697.31	% SZS status Started for HL407585+5.p
139350.86/18697.31	% SZS status GaveUp for HL407585+5.p
139350.86/18697.31	eprover: CPU time limit exceeded, terminating
139350.86/18697.31	% SZS status Ended for HL407585+5.p
139367.20/18699.34	% SZS status Started for HL407586+5.p
139367.20/18699.34	% SZS status GaveUp for HL407586+5.p
139367.20/18699.34	eprover: CPU time limit exceeded, terminating
139367.20/18699.34	% SZS status Ended for HL407586+5.p
139375.30/18700.39	% SZS status Started for HL407593+4.p
139375.30/18700.39	% SZS status GaveUp for HL407593+4.p
139375.30/18700.39	eprover: CPU time limit exceeded, terminating
139375.30/18700.39	% SZS status Ended for HL407593+4.p
139376.59/18700.59	% SZS status Started for HL407587+5.p
139376.59/18700.59	% SZS status GaveUp for HL407587+5.p
139376.59/18700.59	eprover: CPU time limit exceeded, terminating
139376.59/18700.59	% SZS status Ended for HL407587+5.p
139400.12/18703.50	% SZS status Started for HL407594+4.p
139400.12/18703.50	% SZS status GaveUp for HL407594+4.p
139400.12/18703.50	eprover: CPU time limit exceeded, terminating
139400.12/18703.50	% SZS status Ended for HL407594+4.p
139410.39/18704.83	% SZS status Started for HL407588+5.p
139410.39/18704.83	% SZS status GaveUp for HL407588+5.p
139410.39/18704.83	eprover: CPU time limit exceeded, terminating
139410.39/18704.83	% SZS status Ended for HL407588+5.p
139424.09/18706.54	% SZS status Started for HL407595+4.p
139424.09/18706.54	% SZS status GaveUp for HL407595+4.p
139424.09/18706.54	eprover: CPU time limit exceeded, terminating
139424.09/18706.54	% SZS status Ended for HL407595+4.p
139424.94/18706.72	% SZS status Started for HL407589+5.p
139424.94/18706.72	% SZS status GaveUp for HL407589+5.p
139424.94/18706.72	eprover: CPU time limit exceeded, terminating
139424.94/18706.72	% SZS status Ended for HL407589+5.p
139448.23/18709.57	% SZS status Started for HL407596+4.p
139448.23/18709.57	% SZS status GaveUp for HL407596+4.p
139448.23/18709.57	eprover: CPU time limit exceeded, terminating
139448.23/18709.57	% SZS status Ended for HL407596+4.p
139456.00/18710.53	% SZS status Started for HL407590+5.p
139456.00/18710.53	% SZS status GaveUp for HL407590+5.p
139456.00/18710.53	eprover: CPU time limit exceeded, terminating
139456.00/18710.53	% SZS status Ended for HL407590+5.p
139472.20/18712.60	% SZS status Started for HL407598+4.p
139472.20/18712.60	% SZS status GaveUp for HL407598+4.p
139472.20/18712.60	eprover: CPU time limit exceeded, terminating
139472.20/18712.60	% SZS status Ended for HL407598+4.p
139474.55/18712.96	% SZS status Started for HL407591+5.p
139474.55/18712.96	% SZS status GaveUp for HL407591+5.p
139474.55/18712.96	eprover: CPU time limit exceeded, terminating
139474.55/18712.96	% SZS status Ended for HL407591+5.p
139496.30/18715.64	% SZS status Started for HL407599+4.p
139496.30/18715.64	% SZS status GaveUp for HL407599+4.p
139496.30/18715.64	eprover: CPU time limit exceeded, terminating
139496.30/18715.64	% SZS status Ended for HL407599+4.p
139508.47/18717.12	% SZS status Started for HL407596+5.p
139508.47/18717.12	% SZS status GaveUp for HL407596+5.p
139508.47/18717.12	eprover: CPU time limit exceeded, terminating
139508.47/18717.12	% SZS status Ended for HL407596+5.p
139519.02/18718.50	% SZS status Started for HL407592+5.p
139519.02/18718.50	% SZS status GaveUp for HL407592+5.p
139519.02/18718.50	eprover: CPU time limit exceeded, terminating
139519.02/18718.50	% SZS status Ended for HL407592+5.p
139520.72/18718.68	% SZS status Started for HL407600+4.p
139520.72/18718.68	% SZS status GaveUp for HL407600+4.p
139520.72/18718.68	eprover: CPU time limit exceeded, terminating
139520.72/18718.68	% SZS status Ended for HL407600+4.p
139543.62/18721.57	% SZS status Started for HL407602+4.p
139543.62/18721.57	% SZS status GaveUp for HL407602+4.p
139543.62/18721.57	eprover: CPU time limit exceeded, terminating
139543.62/18721.57	% SZS status Ended for HL407602+4.p
139567.30/18724.61	% SZS status Started for HL407604+4.p
139567.30/18724.61	% SZS status GaveUp for HL407604+4.p
139567.30/18724.61	eprover: CPU time limit exceeded, terminating
139567.30/18724.61	% SZS status Ended for HL407604+4.p
139573.53/18725.34	% SZS status Started for HL407593+5.p
139573.53/18725.34	% SZS status GaveUp for HL407593+5.p
139573.53/18725.34	eprover: CPU time limit exceeded, terminating
139573.53/18725.34	% SZS status Ended for HL407593+5.p
139582.00/18726.42	% SZS status Started for HL407594+5.p
139582.00/18726.42	% SZS status GaveUp for HL407594+5.p
139582.00/18726.42	eprover: CPU time limit exceeded, terminating
139582.00/18726.42	% SZS status Ended for HL407594+5.p
139597.55/18728.38	% SZS status Started for HL407606+4.p
139597.55/18728.38	% SZS status GaveUp for HL407606+4.p
139597.55/18728.38	eprover: CPU time limit exceeded, terminating
139597.55/18728.38	% SZS status Ended for HL407606+4.p
139617.27/18730.90	% SZS status Started for HL407595+5.p
139617.27/18730.90	% SZS status GaveUp for HL407595+5.p
139617.27/18730.90	eprover: CPU time limit exceeded, terminating
139617.27/18730.90	% SZS status Ended for HL407595+5.p
139620.64/18731.42	% SZS status Started for HL407607+4.p
139620.64/18731.42	% SZS status GaveUp for HL407607+4.p
139620.64/18731.42	eprover: CPU time limit exceeded, terminating
139620.64/18731.42	% SZS status Ended for HL407607+4.p
139645.59/18734.45	% SZS status Started for HL407608+4.p
139645.59/18734.45	% SZS status GaveUp for HL407608+4.p
139645.59/18734.45	eprover: CPU time limit exceeded, terminating
139645.59/18734.45	% SZS status Ended for HL407608+4.p
139661.62/18736.48	% SZS status Started for HL407598+5.p
139661.62/18736.48	% SZS status GaveUp for HL407598+5.p
139661.62/18736.48	eprover: CPU time limit exceeded, terminating
139661.62/18736.48	% SZS status Ended for HL407598+5.p
139682.45/18739.07	% SZS status Started for HL407599+5.p
139682.45/18739.07	% SZS status GaveUp for HL407599+5.p
139682.45/18739.07	eprover: CPU time limit exceeded, terminating
139682.45/18739.07	% SZS status Ended for HL407599+5.p
139686.44/18739.51	% SZS status Started for HL407609+4.p
139686.44/18739.51	% SZS status GaveUp for HL407609+4.p
139686.44/18739.51	eprover: CPU time limit exceeded, terminating
139686.44/18739.51	% SZS status Ended for HL407609+4.p
139710.39/18742.58	% SZS status Started for HL407611+4.p
139710.39/18742.58	% SZS status GaveUp for HL407611+4.p
139710.39/18742.58	eprover: CPU time limit exceeded, terminating
139710.39/18742.58	% SZS status Ended for HL407611+4.p
139713.14/18742.95	% SZS status Started for HL407600+5.p
139713.14/18742.95	% SZS status GaveUp for HL407600+5.p
139713.14/18742.95	eprover: CPU time limit exceeded, terminating
139713.14/18742.95	% SZS status Ended for HL407600+5.p
139728.36/18744.87	% SZS status Started for HL407602+5.p
139728.36/18744.87	% SZS status GaveUp for HL407602+5.p
139728.36/18744.87	eprover: CPU time limit exceeded, terminating
139728.36/18744.87	% SZS status Ended for HL407602+5.p
139737.36/18746.00	% SZS status Started for HL407612+4.p
139737.36/18746.00	% SZS status GaveUp for HL407612+4.p
139737.36/18746.00	eprover: CPU time limit exceeded, terminating
139737.36/18746.00	% SZS status Ended for HL407612+4.p
139761.56/18749.04	% SZS status Started for HL407613+4.p
139761.56/18749.04	% SZS status GaveUp for HL407613+4.p
139761.56/18749.04	eprover: CPU time limit exceeded, terminating
139761.56/18749.04	% SZS status Ended for HL407613+4.p
139772.45/18750.48	% SZS status Started for HL407604+5.p
139772.45/18750.48	% SZS status GaveUp for HL407604+5.p
139772.45/18750.48	eprover: CPU time limit exceeded, terminating
139772.45/18750.48	% SZS status Ended for HL407604+5.p
139788.62/18752.45	% SZS status Started for HL407606+5.p
139788.62/18752.45	% SZS status GaveUp for HL407606+5.p
139788.62/18752.45	eprover: CPU time limit exceeded, terminating
139788.62/18752.45	% SZS status Ended for HL407606+5.p
139796.91/18753.53	% SZS status Started for HL407614+4.p
139796.91/18753.53	% SZS status GaveUp for HL407614+4.p
139796.91/18753.53	eprover: CPU time limit exceeded, terminating
139796.91/18753.53	% SZS status Ended for HL407614+4.p
139820.81/18756.59	% SZS status Started for HL407615+4.p
139820.81/18756.59	% SZS status GaveUp for HL407615+4.p
139820.81/18756.59	eprover: CPU time limit exceeded, terminating
139820.81/18756.59	% SZS status Ended for HL407615+4.p
139824.30/18756.97	% SZS status Started for HL407607+5.p
139824.30/18756.97	% SZS status GaveUp for HL407607+5.p
139824.30/18756.97	eprover: CPU time limit exceeded, terminating
139824.30/18756.97	% SZS status Ended for HL407607+5.p
139848.14/18760.00	% SZS status Started for HL407617+4.p
139848.14/18760.00	% SZS status GaveUp for HL407617+4.p
139848.14/18760.00	eprover: CPU time limit exceeded, terminating
139848.14/18760.00	% SZS status Ended for HL407617+4.p
139852.25/18760.44	% SZS status Started for HL407608+5.p
139852.25/18760.44	% SZS status GaveUp for HL407608+5.p
139852.25/18760.44	eprover: CPU time limit exceeded, terminating
139852.25/18760.44	% SZS status Ended for HL407608+5.p
139877.47/18763.63	% SZS status Started for HL407618+4.p
139877.47/18763.63	% SZS status GaveUp for HL407618+4.p
139877.47/18763.63	eprover: CPU time limit exceeded, terminating
139877.47/18763.63	% SZS status Ended for HL407618+4.p
139888.42/18765.13	% SZS status Started for HL407609+5.p
139888.42/18765.13	% SZS status GaveUp for HL407609+5.p
139888.42/18765.13	eprover: CPU time limit exceeded, terminating
139888.42/18765.13	% SZS status Ended for HL407609+5.p
139912.25/18768.16	% SZS status Started for HL407619+4.p
139912.25/18768.16	% SZS status GaveUp for HL407619+4.p
139912.25/18768.16	eprover: CPU time limit exceeded, terminating
139912.25/18768.16	% SZS status Ended for HL407619+4.p
139917.05/18768.59	% SZS status Started for HL407611+5.p
139917.05/18768.59	% SZS status GaveUp for HL407611+5.p
139917.05/18768.59	eprover: CPU time limit exceeded, terminating
139917.05/18768.59	% SZS status Ended for HL407611+5.p
139934.16/18770.81	% SZS status Started for HL407612+5.p
139934.16/18770.81	% SZS status GaveUp for HL407612+5.p
139934.16/18770.81	eprover: CPU time limit exceeded, terminating
139934.16/18770.81	% SZS status Ended for HL407612+5.p
139941.16/18771.63	% SZS status Started for HL407620+4.p
139941.16/18771.63	% SZS status GaveUp for HL407620+4.p
139941.16/18771.63	eprover: CPU time limit exceeded, terminating
139941.16/18771.63	% SZS status Ended for HL407620+4.p
139959.78/18774.03	% SZS status Started for HL407618+5.p
139959.78/18774.03	% SZS status GaveUp for HL407618+5.p
139959.78/18774.03	eprover: CPU time limit exceeded, terminating
139959.78/18774.03	% SZS status Ended for HL407618+5.p
139964.72/18774.66	% SZS status Started for HL407621+4.p
139964.72/18774.66	% SZS status GaveUp for HL407621+4.p
139964.72/18774.66	eprover: CPU time limit exceeded, terminating
139964.72/18774.66	% SZS status Ended for HL407621+4.p
139970.80/18775.35	% SZS status Started for HL407613+5.p
139970.80/18775.35	% SZS status GaveUp for HL407613+5.p
139970.80/18775.35	eprover: CPU time limit exceeded, terminating
139970.80/18775.35	% SZS status Ended for HL407613+5.p
139989.64/18777.72	% SZS status Started for HL407622+4.p
139989.64/18777.72	% SZS status GaveUp for HL407622+4.p
139989.64/18777.72	eprover: CPU time limit exceeded, terminating
139989.64/18777.72	% SZS status Ended for HL407622+4.p
139994.56/18778.35	% SZS status Started for HL407614+5.p
139994.56/18778.35	% SZS status GaveUp for HL407614+5.p
139994.56/18778.35	eprover: CPU time limit exceeded, terminating
139994.56/18778.35	% SZS status Ended for HL407614+5.p
139995.08/18778.43	% SZS status Started for HL407619+5.p
139995.08/18778.43	% SZS status GaveUp for HL407619+5.p
139995.08/18778.43	eprover: CPU time limit exceeded, terminating
139995.08/18778.43	% SZS status Ended for HL407619+5.p
140013.41/18780.75	% SZS status Started for HL407623+4.p
140013.41/18780.75	% SZS status GaveUp for HL407623+4.p
140013.41/18780.75	eprover: CPU time limit exceeded, terminating
140013.41/18780.75	% SZS status Ended for HL407623+4.p
140019.91/18781.57	% SZS status Started for HL407624+4.p
140019.91/18781.57	% SZS status GaveUp for HL407624+4.p
140019.91/18781.57	eprover: CPU time limit exceeded, terminating
140019.91/18781.57	% SZS status Ended for HL407624+4.p
140031.69/18783.06	% SZS status Started for HL407615+5.p
140031.69/18783.06	% SZS status GaveUp for HL407615+5.p
140031.69/18783.06	eprover: CPU time limit exceeded, terminating
140031.69/18783.06	% SZS status Ended for HL407615+5.p
140044.45/18784.59	% SZS status Started for HL407625+4.p
140044.45/18784.59	% SZS status GaveUp for HL407625+4.p
140044.45/18784.59	eprover: CPU time limit exceeded, terminating
140044.45/18784.59	% SZS status Ended for HL407625+4.p
140054.88/18785.95	% SZS status Started for HL407617+5.p
140054.88/18785.95	% SZS status GaveUp for HL407617+5.p
140054.88/18785.95	eprover: CPU time limit exceeded, terminating
140054.88/18785.95	% SZS status Ended for HL407617+5.p
140068.41/18787.66	% SZS status Started for HL407626+4.p
140068.41/18787.66	% SZS status GaveUp for HL407626+4.p
140068.41/18787.66	eprover: CPU time limit exceeded, terminating
140068.41/18787.66	% SZS status Ended for HL407626+4.p
140092.86/18790.72	% SZS status Started for HL407627+4.p
140092.86/18790.72	% SZS status GaveUp for HL407627+4.p
140092.86/18790.72	eprover: CPU time limit exceeded, terminating
140092.86/18790.72	% SZS status Ended for HL407627+4.p
140140.56/18796.68	% SZS status Started for HL407620+5.p
140140.56/18796.68	% SZS status GaveUp for HL407620+5.p
140140.56/18796.68	eprover: CPU time limit exceeded, terminating
140140.56/18796.68	% SZS status Ended for HL407620+5.p
140164.38/18799.71	% SZS status Started for HL407628+4.p
140164.38/18799.71	% SZS status GaveUp for HL407628+4.p
140164.38/18799.71	eprover: CPU time limit exceeded, terminating
140164.38/18799.71	% SZS status Ended for HL407628+4.p
140166.81/18800.04	% SZS status Started for HL407621+5.p
140166.81/18800.04	% SZS status GaveUp for HL407621+5.p
140166.81/18800.04	eprover: CPU time limit exceeded, terminating
140166.81/18800.04	% SZS status Ended for HL407621+5.p
140176.62/18801.24	% SZS status Started for HL407622+5.p
140176.62/18801.24	% SZS status GaveUp for HL407622+5.p
140176.62/18801.24	eprover: CPU time limit exceeded, terminating
140176.62/18801.24	% SZS status Ended for HL407622+5.p
140191.59/18803.15	% SZS status Started for HL407630+4.p
140191.59/18803.15	% SZS status GaveUp for HL407630+4.p
140191.59/18803.15	eprover: CPU time limit exceeded, terminating
140191.59/18803.15	% SZS status Ended for HL407630+4.p
140200.52/18804.21	% SZS status Started for HL407623+5.p
140200.52/18804.21	% SZS status GaveUp for HL407623+5.p
140200.52/18804.21	eprover: CPU time limit exceeded, terminating
140200.52/18804.21	% SZS status Ended for HL407623+5.p
140215.28/18806.24	% SZS status Started for HL407631+4.p
140215.28/18806.24	% SZS status GaveUp for HL407631+4.p
140215.28/18806.24	eprover: CPU time limit exceeded, terminating
140215.28/18806.24	% SZS status Ended for HL407631+4.p
140219.58/18806.66	% SZS status Started for HL407624+5.p
140219.58/18806.66	% SZS status GaveUp for HL407624+5.p
140219.58/18806.66	eprover: CPU time limit exceeded, terminating
140219.58/18806.66	% SZS status Ended for HL407624+5.p
140238.50/18809.04	% SZS status Started for HL407625+5.p
140238.50/18809.04	% SZS status GaveUp for HL407625+5.p
140238.50/18809.04	eprover: CPU time limit exceeded, terminating
140238.50/18809.04	% SZS status Ended for HL407625+5.p
140239.34/18809.28	% SZS status Started for HL407632+4.p
140239.34/18809.28	% SZS status GaveUp for HL407632+4.p
140239.34/18809.28	eprover: CPU time limit exceeded, terminating
140239.34/18809.28	% SZS status Ended for HL407632+4.p
140261.70/18812.06	% SZS status Started for HL407633+4.p
140261.70/18812.06	% SZS status GaveUp for HL407633+4.p
140261.70/18812.06	eprover: CPU time limit exceeded, terminating
140261.70/18812.06	% SZS status Ended for HL407633+4.p
140263.30/18812.18	% SZS status Started for HL407626+5.p
140263.30/18812.18	% SZS status GaveUp for HL407626+5.p
140263.30/18812.18	eprover: CPU time limit exceeded, terminating
140263.30/18812.18	% SZS status Ended for HL407626+5.p
140286.27/18815.09	% SZS status Started for HL407635+4.p
140286.27/18815.09	% SZS status GaveUp for HL407635+4.p
140286.27/18815.09	eprover: CPU time limit exceeded, terminating
140286.27/18815.09	% SZS status Ended for HL407635+4.p
140298.47/18816.64	% SZS status Started for HL407627+5.p
140298.47/18816.64	% SZS status GaveUp for HL407627+5.p
140298.47/18816.64	eprover: CPU time limit exceeded, terminating
140298.47/18816.64	% SZS status Ended for HL407627+5.p
140310.69/18818.27	% SZS status Started for HL407636+4.p
140310.69/18818.27	% SZS status GaveUp for HL407636+4.p
140310.69/18818.27	eprover: CPU time limit exceeded, terminating
140310.69/18818.27	% SZS status Ended for HL407636+4.p
140335.89/18821.31	% SZS status Started for HL407637+4.p
140335.89/18821.31	% SZS status GaveUp for HL407637+4.p
140335.89/18821.31	eprover: CPU time limit exceeded, terminating
140335.89/18821.31	% SZS status Ended for HL407637+4.p
140369.94/18825.65	% SZS status Started for HL407628+5.p
140369.94/18825.65	% SZS status GaveUp for HL407628+5.p
140369.94/18825.65	eprover: CPU time limit exceeded, terminating
140369.94/18825.65	% SZS status Ended for HL407628+5.p
140382.33/18827.15	% SZS status Started for HL407630+5.p
140382.33/18827.15	% SZS status GaveUp for HL407630+5.p
140382.33/18827.15	eprover: CPU time limit exceeded, terminating
140382.33/18827.15	% SZS status Ended for HL407630+5.p
140394.55/18828.72	% SZS status Started for HL407638+4.p
140394.55/18828.72	% SZS status GaveUp for HL407638+4.p
140394.55/18828.72	eprover: CPU time limit exceeded, terminating
140394.55/18828.72	% SZS status Ended for HL407638+4.p
140406.23/18830.22	% SZS status Started for HL407631+5.p
140406.23/18830.22	% SZS status GaveUp for HL407631+5.p
140406.23/18830.22	eprover: CPU time limit exceeded, terminating
140406.23/18830.22	% SZS status Ended for HL407631+5.p
140419.06/18831.78	% SZS status Started for HL407639+4.p
140419.06/18831.78	% SZS status GaveUp for HL407639+4.p
140419.06/18831.78	eprover: CPU time limit exceeded, terminating
140419.06/18831.78	% SZS status Ended for HL407639+4.p
140430.08/18833.16	% SZS status Started for HL407632+5.p
140430.08/18833.16	% SZS status GaveUp for HL407632+5.p
140430.08/18833.16	eprover: CPU time limit exceeded, terminating
140430.08/18833.16	% SZS status Ended for HL407632+5.p
140443.41/18834.87	% SZS status Started for HL407640+4.p
140443.41/18834.87	% SZS status GaveUp for HL407640+4.p
140443.41/18834.87	eprover: CPU time limit exceeded, terminating
140443.41/18834.87	% SZS status Ended for HL407640+4.p
140446.44/18835.32	% SZS status Started for HL407633+5.p
140446.44/18835.32	% SZS status GaveUp for HL407633+5.p
140446.44/18835.32	eprover: CPU time limit exceeded, terminating
140446.44/18835.32	% SZS status Ended for HL407633+5.p
140467.61/18837.90	% SZS status Started for HL407641+4.p
140467.61/18837.90	% SZS status GaveUp for HL407641+4.p
140467.61/18837.90	eprover: CPU time limit exceeded, terminating
140467.61/18837.90	% SZS status Ended for HL407641+4.p
140468.56/18838.07	% SZS status Started for HL407635+5.p
140468.56/18838.07	% SZS status GaveUp for HL407635+5.p
140468.56/18838.07	eprover: CPU time limit exceeded, terminating
140468.56/18838.07	% SZS status Ended for HL407635+5.p
140491.34/18840.94	% SZS status Started for HL407642+4.p
140491.34/18840.94	% SZS status GaveUp for HL407642+4.p
140491.34/18840.94	eprover: CPU time limit exceeded, terminating
140491.34/18840.94	% SZS status Ended for HL407642+4.p
140506.05/18842.78	% SZS status Started for HL407636+5.p
140506.05/18842.78	% SZS status GaveUp for HL407636+5.p
140506.05/18842.78	eprover: CPU time limit exceeded, terminating
140506.05/18842.78	% SZS status Ended for HL407636+5.p
140515.89/18843.98	% SZS status Started for HL407643+4.p
140515.89/18843.98	% SZS status GaveUp for HL407643+4.p
140515.89/18843.98	eprover: CPU time limit exceeded, terminating
140515.89/18843.98	% SZS status Ended for HL407643+4.p
140539.91/18847.03	% SZS status Started for HL407644+4.p
140539.91/18847.03	% SZS status GaveUp for HL407644+4.p
140539.91/18847.03	eprover: CPU time limit exceeded, terminating
140539.91/18847.03	% SZS status Ended for HL407644+4.p
140545.38/18847.55	% SZS status Started for HL407637+5.p
140545.38/18847.55	% SZS status GaveUp for HL407637+5.p
140545.38/18847.55	eprover: CPU time limit exceeded, terminating
140545.38/18847.55	% SZS status Ended for HL407637+5.p
140570.62/18850.59	% SZS status Started for HL407645+4.p
140570.62/18850.59	% SZS status GaveUp for HL407645+4.p
140570.62/18850.59	eprover: CPU time limit exceeded, terminating
140570.62/18850.59	% SZS status Ended for HL407645+4.p
140594.02/18853.17	% SZS status Started for HL407638+5.p
140594.02/18853.17	% SZS status GaveUp for HL407638+5.p
140594.02/18853.17	eprover: CPU time limit exceeded, terminating
140594.02/18853.17	% SZS status Ended for HL407638+5.p
140617.89/18856.19	% SZS status Started for HL407646+4.p
140617.89/18856.19	% SZS status GaveUp for HL407646+4.p
140617.89/18856.19	eprover: CPU time limit exceeded, terminating
140617.89/18856.19	% SZS status Ended for HL407646+4.p
140618.55/18856.31	% SZS status Started for HL407639+5.p
140618.55/18856.31	% SZS status GaveUp for HL407639+5.p
140618.55/18856.31	eprover: CPU time limit exceeded, terminating
140618.55/18856.31	% SZS status Ended for HL407639+5.p
140640.95/18859.09	% SZS status Started for HL407640+5.p
140640.95/18859.09	% SZS status GaveUp for HL407640+5.p
140640.95/18859.09	eprover: CPU time limit exceeded, terminating
140640.95/18859.09	% SZS status Ended for HL407640+5.p
140643.25/18859.39	% SZS status Started for HL407647+4.p
140643.25/18859.39	% SZS status GaveUp for HL407647+4.p
140643.25/18859.39	eprover: CPU time limit exceeded, terminating
140643.25/18859.39	% SZS status Ended for HL407647+4.p
140657.62/18861.16	% SZS status Started for HL407641+5.p
140657.62/18861.16	% SZS status GaveUp for HL407641+5.p
140657.62/18861.16	eprover: CPU time limit exceeded, terminating
140657.62/18861.16	% SZS status Ended for HL407641+5.p
140667.38/18862.44	% SZS status Started for HL407648+4.p
140667.38/18862.44	% SZS status GaveUp for HL407648+4.p
140667.38/18862.44	eprover: CPU time limit exceeded, terminating
140667.38/18862.44	% SZS status Ended for HL407648+4.p
140680.53/18864.17	% SZS status Started for HL407642+5.p
140680.53/18864.17	% SZS status GaveUp for HL407642+5.p
140680.53/18864.17	eprover: CPU time limit exceeded, terminating
140680.53/18864.17	% SZS status Ended for HL407642+5.p
140691.58/18865.48	% SZS status Started for HL407650+4.p
140691.58/18865.48	% SZS status GaveUp for HL407650+4.p
140691.58/18865.48	eprover: CPU time limit exceeded, terminating
140691.58/18865.48	% SZS status Ended for HL407650+4.p
140715.88/18868.53	% SZS status Started for HL407651+4.p
140715.88/18868.53	% SZS status GaveUp for HL407651+4.p
140715.88/18868.53	eprover: CPU time limit exceeded, terminating
140715.88/18868.53	% SZS status Ended for HL407651+4.p
140716.34/18868.62	% SZS status Started for HL407643+5.p
140716.34/18868.62	% SZS status GaveUp for HL407643+5.p
140716.34/18868.62	eprover: CPU time limit exceeded, terminating
140716.34/18868.62	% SZS status Ended for HL407643+5.p
140739.84/18871.50	% SZS status Started for HL407648+5.p
140739.84/18871.50	% SZS status GaveUp for HL407648+5.p
140739.84/18871.50	eprover: CPU time limit exceeded, terminating
140739.84/18871.50	% SZS status Ended for HL407648+5.p
140740.59/18871.65	% SZS status Started for HL407652+4.p
140740.59/18871.65	% SZS status GaveUp for HL407652+4.p
140740.59/18871.65	eprover: CPU time limit exceeded, terminating
140740.59/18871.65	% SZS status Ended for HL407652+4.p
140751.62/18873.01	% SZS status Started for HL407644+5.p
140751.62/18873.01	% SZS status GaveUp for HL407644+5.p
140751.62/18873.01	eprover: CPU time limit exceeded, terminating
140751.62/18873.01	% SZS status Ended for HL407644+5.p
140764.64/18874.69	% SZS status Started for HL407653+4.p
140764.64/18874.69	% SZS status GaveUp for HL407653+4.p
140764.64/18874.69	eprover: CPU time limit exceeded, terminating
140764.64/18874.69	% SZS status Ended for HL407653+4.p
140781.47/18876.82	% SZS status Started for HL407645+5.p
140781.47/18876.82	% SZS status GaveUp for HL407645+5.p
140781.47/18876.82	eprover: CPU time limit exceeded, terminating
140781.47/18876.82	% SZS status Ended for HL407645+5.p
140789.22/18877.73	% SZS status Started for HL407654+4.p
140789.22/18877.73	% SZS status GaveUp for HL407654+4.p
140789.22/18877.73	eprover: CPU time limit exceeded, terminating
140789.22/18877.73	% SZS status Ended for HL407654+4.p
140813.12/18880.76	% SZS status Started for HL407655+4.p
140813.12/18880.76	% SZS status GaveUp for HL407655+4.p
140813.12/18880.76	eprover: CPU time limit exceeded, terminating
140813.12/18880.76	% SZS status Ended for HL407655+4.p
140827.02/18882.58	% SZS status Started for HL407646+5.p
140827.02/18882.58	% SZS status GaveUp for HL407646+5.p
140827.02/18882.58	eprover: CPU time limit exceeded, terminating
140827.02/18882.58	% SZS status Ended for HL407646+5.p
140846.44/18884.93	% SZS status Started for HL407647+5.p
140846.44/18884.93	% SZS status GaveUp for HL407647+5.p
140846.44/18884.93	eprover: CPU time limit exceeded, terminating
140846.44/18884.93	% SZS status Ended for HL407647+5.p
140851.81/18885.68	% SZS status Started for HL407656+4.p
140851.81/18885.68	% SZS status GaveUp for HL407656+4.p
140851.81/18885.68	eprover: CPU time limit exceeded, terminating
140851.81/18885.68	% SZS status Ended for HL407656+4.p
140876.05/18888.71	% SZS status Started for HL407657+4.p
140876.05/18888.71	% SZS status GaveUp for HL407657+4.p
140876.05/18888.71	eprover: CPU time limit exceeded, terminating
140876.05/18888.71	% SZS status Ended for HL407657+4.p
140887.48/18890.20	% SZS status Started for HL407650+5.p
140887.48/18890.20	% SZS status GaveUp for HL407650+5.p
140887.48/18890.20	eprover: CPU time limit exceeded, terminating
140887.48/18890.20	% SZS status Ended for HL407650+5.p
140912.34/18893.28	% SZS status Started for HL407658+4.p
140912.34/18893.28	% SZS status GaveUp for HL407658+4.p
140912.34/18893.28	eprover: CPU time limit exceeded, terminating
140912.34/18893.28	% SZS status Ended for HL407658+4.p
140920.84/18894.34	% SZS status Started for HL407651+5.p
140920.84/18894.34	% SZS status GaveUp for HL407651+5.p
140920.84/18894.34	eprover: CPU time limit exceeded, terminating
140920.84/18894.34	% SZS status Ended for HL407651+5.p
140945.47/18897.40	% SZS status Started for HL407659+4.p
140945.47/18897.40	% SZS status GaveUp for HL407659+4.p
140945.47/18897.40	eprover: CPU time limit exceeded, terminating
140945.47/18897.40	% SZS status Ended for HL407659+4.p
140946.69/18897.57	% SZS status Started for HL407652+5.p
140946.69/18897.57	% SZS status GaveUp for HL407652+5.p
140946.69/18897.57	eprover: CPU time limit exceeded, terminating
140946.69/18897.57	% SZS status Ended for HL407652+5.p
140957.31/18898.90	% SZS status Started for HL407653+5.p
140957.31/18898.90	% SZS status GaveUp for HL407653+5.p
140957.31/18898.90	eprover: CPU time limit exceeded, terminating
140957.31/18898.90	% SZS status Ended for HL407653+5.p
140971.17/18900.65	% SZS status Started for HL407660+4.p
140971.17/18900.65	% SZS status GaveUp for HL407660+4.p
140971.17/18900.65	eprover: CPU time limit exceeded, terminating
140971.17/18900.65	% SZS status Ended for HL407660+4.p
140986.84/18902.62	% SZS status Started for HL407654+5.p
140986.84/18902.62	% SZS status GaveUp for HL407654+5.p
140986.84/18902.62	eprover: CPU time limit exceeded, terminating
140986.84/18902.62	% SZS status Ended for HL407654+5.p
140995.16/18903.69	% SZS status Started for HL407661+4.p
140995.16/18903.69	% SZS status GaveUp for HL407661+4.p
140995.16/18903.69	eprover: CPU time limit exceeded, terminating
140995.16/18903.69	% SZS status Ended for HL407661+4.p
141019.69/18906.72	% SZS status Started for HL407662+4.p
141019.69/18906.72	% SZS status GaveUp for HL407662+4.p
141019.69/18906.72	eprover: CPU time limit exceeded, terminating
141019.69/18906.72	% SZS status Ended for HL407662+4.p
141020.28/18906.87	% SZS status Started for HL407655+5.p
141020.28/18906.87	% SZS status GaveUp for HL407655+5.p
141020.28/18906.87	eprover: CPU time limit exceeded, terminating
141020.28/18906.87	% SZS status Ended for HL407655+5.p
141044.39/18909.90	% SZS status Started for HL407663+4.p
141044.39/18909.90	% SZS status GaveUp for HL407663+4.p
141044.39/18909.90	eprover: CPU time limit exceeded, terminating
141044.39/18909.90	% SZS status Ended for HL407663+4.p
141053.03/18910.90	% SZS status Started for HL407656+5.p
141053.03/18910.90	% SZS status GaveUp for HL407656+5.p
141053.03/18910.90	eprover: CPU time limit exceeded, terminating
141053.03/18910.90	% SZS status Ended for HL407656+5.p
141077.11/18913.94	% SZS status Started for HL407664+4.p
141077.11/18913.94	% SZS status GaveUp for HL407664+4.p
141077.11/18913.94	eprover: CPU time limit exceeded, terminating
141077.11/18913.94	% SZS status Ended for HL407664+4.p
141083.28/18914.77	% SZS status Started for HL407657+5.p
141083.28/18914.77	% SZS status GaveUp for HL407657+5.p
141083.28/18914.77	eprover: CPU time limit exceeded, terminating
141083.28/18914.77	% SZS status Ended for HL407657+5.p
141107.02/18917.80	% SZS status Started for HL407665+4.p
141107.02/18917.80	% SZS status GaveUp for HL407665+4.p
141107.02/18917.80	eprover: CPU time limit exceeded, terminating
141107.02/18917.80	% SZS status Ended for HL407665+4.p
141119.66/18919.31	% SZS status Started for HL407658+5.p
141119.66/18919.31	% SZS status GaveUp for HL407658+5.p
141119.66/18919.31	eprover: CPU time limit exceeded, terminating
141119.66/18919.31	% SZS status Ended for HL407658+5.p
141143.77/18922.34	% SZS status Started for HL407666+4.p
141143.77/18922.34	% SZS status GaveUp for HL407666+4.p
141143.77/18922.34	eprover: CPU time limit exceeded, terminating
141143.77/18922.34	% SZS status Ended for HL407666+4.p
141152.33/18923.47	% SZS status Started for HL407659+5.p
141152.33/18923.47	% SZS status GaveUp for HL407659+5.p
141152.33/18923.47	eprover: CPU time limit exceeded, terminating
141152.33/18923.47	% SZS status Ended for HL407659+5.p
141163.41/18924.82	% SZS status Started for HL407660+5.p
141163.41/18924.82	% SZS status GaveUp for HL407660+5.p
141163.41/18924.82	eprover: CPU time limit exceeded, terminating
141163.41/18924.82	% SZS status Ended for HL407660+5.p
141176.72/18926.50	% SZS status Started for HL407667+4.p
141176.72/18926.50	% SZS status GaveUp for HL407667+4.p
141176.72/18926.50	eprover: CPU time limit exceeded, terminating
141176.72/18926.50	% SZS status Ended for HL407667+4.p
141194.73/18928.75	% SZS status Started for HL407661+5.p
141194.73/18928.75	% SZS status GaveUp for HL407661+5.p
141194.73/18928.75	eprover: CPU time limit exceeded, terminating
141194.73/18928.75	% SZS status Ended for HL407661+5.p
141200.61/18929.55	% SZS status Started for HL407669+4.p
141200.61/18929.55	% SZS status GaveUp for HL407669+4.p
141200.61/18929.55	eprover: CPU time limit exceeded, terminating
141200.61/18929.55	% SZS status Ended for HL407669+4.p
141227.58/18932.62	% SZS status Started for HL407670+4.p
141227.58/18932.62	% SZS status GaveUp for HL407670+4.p
141227.58/18932.62	eprover: CPU time limit exceeded, terminating
141227.58/18932.62	% SZS status Ended for HL407670+4.p
141228.70/18932.77	% SZS status Started for HL407662+5.p
141228.70/18932.77	% SZS status GaveUp for HL407662+5.p
141228.70/18932.77	eprover: CPU time limit exceeded, terminating
141228.70/18932.77	% SZS status Ended for HL407662+5.p
141252.66/18935.80	% SZS status Started for HL407663+5.p
141252.66/18935.80	% SZS status GaveUp for HL407663+5.p
141252.66/18935.80	eprover: CPU time limit exceeded, terminating
141252.66/18935.80	% SZS status Ended for HL407663+5.p
141252.66/18935.83	% SZS status Started for HL407671+4.p
141252.66/18935.83	% SZS status GaveUp for HL407671+4.p
141252.66/18935.83	eprover: CPU time limit exceeded, terminating
141252.66/18935.83	% SZS status Ended for HL407671+4.p
141277.19/18938.89	% SZS status Started for HL407672+4.p
141277.19/18938.89	% SZS status GaveUp for HL407672+4.p
141277.19/18938.89	eprover: CPU time limit exceeded, terminating
141277.19/18938.89	% SZS status Ended for HL407672+4.p
141285.14/18939.87	% SZS status Started for HL407664+5.p
141285.14/18939.87	% SZS status GaveUp for HL407664+5.p
141285.14/18939.87	eprover: CPU time limit exceeded, terminating
141285.14/18939.87	% SZS status Ended for HL407664+5.p
141308.36/18942.89	% SZS status Started for HL407673+4.p
141308.36/18942.89	% SZS status GaveUp for HL407673+4.p
141308.36/18942.89	eprover: CPU time limit exceeded, terminating
141308.36/18942.89	% SZS status Ended for HL407673+4.p
141318.06/18944.11	% SZS status Started for HL407665+5.p
141318.06/18944.11	% SZS status GaveUp for HL407665+5.p
141318.06/18944.11	eprover: CPU time limit exceeded, terminating
141318.06/18944.11	% SZS status Ended for HL407665+5.p
141342.89/18947.14	% SZS status Started for HL407674+4.p
141342.89/18947.14	% SZS status GaveUp for HL407674+4.p
141342.89/18947.14	eprover: CPU time limit exceeded, terminating
141342.89/18947.14	% SZS status Ended for HL407674+4.p
141352.56/18948.48	% SZS status Started for HL407666+5.p
141352.56/18948.48	% SZS status GaveUp for HL407666+5.p
141352.56/18948.48	eprover: CPU time limit exceeded, terminating
141352.56/18948.48	% SZS status Ended for HL407666+5.p
141372.34/18950.84	% SZS status Started for HL407667+5.p
141372.34/18950.84	% SZS status GaveUp for HL407667+5.p
141372.34/18950.84	eprover: CPU time limit exceeded, terminating
141372.34/18950.84	% SZS status Ended for HL407667+5.p
141377.83/18951.52	% SZS status Started for HL407676+4.p
141377.83/18951.52	% SZS status GaveUp for HL407676+4.p
141377.83/18951.52	eprover: CPU time limit exceeded, terminating
141377.83/18951.52	% SZS status Ended for HL407676+4.p
141401.66/18954.59	% SZS status Started for HL407669+5.p
141401.66/18954.59	% SZS status GaveUp for HL407669+5.p
141401.66/18954.59	eprover: CPU time limit exceeded, terminating
141401.66/18954.59	% SZS status Ended for HL407669+5.p
141402.48/18954.62	% SZS status Started for HL407677+4.p
141402.48/18954.62	% SZS status GaveUp for HL407677+4.p
141402.48/18954.62	eprover: CPU time limit exceeded, terminating
141402.48/18954.62	% SZS status Ended for HL407677+4.p
141427.23/18957.80	% SZS status Started for HL407678+4.p
141427.23/18957.80	% SZS status GaveUp for HL407678+4.p
141427.23/18957.80	eprover: CPU time limit exceeded, terminating
141427.23/18957.80	% SZS status Ended for HL407678+4.p
141433.31/18958.50	% SZS status Started for HL407670+5.p
141433.31/18958.50	% SZS status GaveUp for HL407670+5.p
141433.31/18958.50	eprover: CPU time limit exceeded, terminating
141433.31/18958.50	% SZS status Ended for HL407670+5.p
141457.47/18961.55	% SZS status Started for HL407679+4.p
141457.47/18961.55	% SZS status GaveUp for HL407679+4.p
141457.47/18961.55	eprover: CPU time limit exceeded, terminating
141457.47/18961.55	% SZS status Ended for HL407679+4.p
141458.14/18961.65	% SZS status Started for HL407671+5.p
141458.14/18961.65	% SZS status GaveUp for HL407671+5.p
141458.14/18961.65	eprover: CPU time limit exceeded, terminating
141458.14/18961.65	% SZS status Ended for HL407671+5.p
141482.22/18964.68	% SZS status Started for HL407680+4.p
141482.22/18964.68	% SZS status GaveUp for HL407680+4.p
141482.22/18964.68	eprover: CPU time limit exceeded, terminating
141482.22/18964.68	% SZS status Ended for HL407680+4.p
141487.50/18965.33	% SZS status Started for HL407672+5.p
141487.50/18965.33	% SZS status GaveUp for HL407672+5.p
141487.50/18965.33	eprover: CPU time limit exceeded, terminating
141487.50/18965.33	% SZS status Ended for HL407672+5.p
141510.33/18968.37	% SZS status Started for HL407681+4.p
141510.33/18968.37	% SZS status GaveUp for HL407681+4.p
141510.33/18968.37	eprover: CPU time limit exceeded, terminating
141510.33/18968.37	% SZS status Ended for HL407681+4.p
141516.58/18969.08	% SZS status Started for HL407673+5.p
141516.58/18969.08	% SZS status GaveUp for HL407673+5.p
141516.58/18969.08	eprover: CPU time limit exceeded, terminating
141516.58/18969.08	% SZS status Ended for HL407673+5.p
141541.98/18972.24	% SZS status Started for HL407683+4.p
141541.98/18972.24	% SZS status GaveUp for HL407683+4.p
141541.98/18972.24	eprover: CPU time limit exceeded, terminating
141541.98/18972.24	% SZS status Ended for HL407683+4.p
141548.48/18973.07	% SZS status Started for HL407674+5.p
141548.48/18973.07	% SZS status GaveUp for HL407674+5.p
141548.48/18973.07	eprover: CPU time limit exceeded, terminating
141548.48/18973.07	% SZS status Ended for HL407674+5.p
141564.02/18975.00	% SZS status Started for HL407680+5.p
141564.02/18975.00	% SZS status GaveUp for HL407680+5.p
141564.02/18975.00	eprover: CPU time limit exceeded, terminating
141564.02/18975.00	% SZS status Ended for HL407680+5.p
141573.17/18976.16	% SZS status Started for HL407684+4.p
141573.17/18976.16	% SZS status GaveUp for HL407684+4.p
141573.17/18976.16	eprover: CPU time limit exceeded, terminating
141573.17/18976.16	% SZS status Ended for HL407684+4.p
141578.52/18976.83	% SZS status Started for HL407676+5.p
141578.52/18976.83	% SZS status GaveUp for HL407676+5.p
141578.52/18976.83	eprover: CPU time limit exceeded, terminating
141578.52/18976.83	% SZS status Ended for HL407676+5.p
141597.19/18979.20	% SZS status Started for HL407686+4.p
141597.19/18979.20	% SZS status GaveUp for HL407686+4.p
141597.19/18979.20	eprover: CPU time limit exceeded, terminating
141597.19/18979.20	% SZS status Ended for HL407686+4.p
141607.91/18980.53	% SZS status Started for HL407677+5.p
141607.91/18980.53	% SZS status GaveUp for HL407677+5.p
141607.91/18980.53	eprover: CPU time limit exceeded, terminating
141607.91/18980.53	% SZS status Ended for HL407677+5.p
141621.67/18982.24	% SZS status Started for HL407688+4.p
141621.67/18982.24	% SZS status GaveUp for HL407688+4.p
141621.67/18982.24	eprover: CPU time limit exceeded, terminating
141621.67/18982.24	% SZS status Ended for HL407688+4.p
141634.45/18983.85	% SZS status Started for HL407678+5.p
141634.45/18983.85	% SZS status GaveUp for HL407678+5.p
141634.45/18983.85	eprover: CPU time limit exceeded, terminating
141634.45/18983.85	% SZS status Ended for HL407678+5.p
141646.30/18985.34	% SZS status Started for HL407689+4.p
141646.30/18985.34	% SZS status GaveUp for HL407689+4.p
141646.30/18985.34	eprover: CPU time limit exceeded, terminating
141646.30/18985.34	% SZS status Ended for HL407689+4.p
141664.05/18987.56	% SZS status Started for HL407679+5.p
141664.05/18987.56	% SZS status GaveUp for HL407679+5.p
141664.05/18987.56	eprover: CPU time limit exceeded, terminating
141664.05/18987.56	% SZS status Ended for HL407679+5.p
141670.33/18988.39	% SZS status Started for HL407690+4.p
141670.33/18988.39	% SZS status GaveUp for HL407690+4.p
141670.33/18988.39	eprover: CPU time limit exceeded, terminating
141670.33/18988.39	% SZS status Ended for HL407690+4.p
141694.08/18991.42	% SZS status Started for HL407691+4.p
141694.08/18991.42	% SZS status GaveUp for HL407691+4.p
141694.08/18991.42	eprover: CPU time limit exceeded, terminating
141694.08/18991.42	% SZS status Ended for HL407691+4.p
141717.86/18994.33	% SZS status Started for HL407681+5.p
141717.86/18994.33	% SZS status GaveUp for HL407681+5.p
141717.86/18994.33	eprover: CPU time limit exceeded, terminating
141717.86/18994.33	% SZS status Ended for HL407681+5.p
141741.98/18997.37	% SZS status Started for HL407692+4.p
141741.98/18997.37	% SZS status GaveUp for HL407692+4.p
141741.98/18997.37	eprover: CPU time limit exceeded, terminating
141741.98/18997.37	% SZS status Ended for HL407692+4.p
141748.22/18998.18	% SZS status Started for HL407683+5.p
141748.22/18998.18	% SZS status GaveUp for HL407683+5.p
141748.22/18998.18	eprover: CPU time limit exceeded, terminating
141748.22/18998.18	% SZS status Ended for HL407683+5.p
141772.70/19001.24	% SZS status Started for HL407693+4.p
141772.70/19001.24	% SZS status GaveUp for HL407693+4.p
141772.70/19001.24	eprover: CPU time limit exceeded, terminating
141772.70/19001.24	% SZS status Ended for HL407693+4.p
141773.03/19001.26	% SZS status Started for HL407684+5.p
141773.03/19001.26	% SZS status GaveUp for HL407684+5.p
141773.03/19001.26	eprover: CPU time limit exceeded, terminating
141773.03/19001.26	% SZS status Ended for HL407684+5.p
141785.17/19002.87	% SZS status Started for HL407686+5.p
141785.17/19002.87	% SZS status GaveUp for HL407686+5.p
141785.17/19002.87	eprover: CPU time limit exceeded, terminating
141785.17/19002.87	% SZS status Ended for HL407686+5.p
141796.59/19004.30	% SZS status Started for HL407694+4.p
141796.59/19004.30	% SZS status GaveUp for HL407694+4.p
141796.59/19004.30	eprover: CPU time limit exceeded, terminating
141796.59/19004.30	% SZS status Ended for HL407694+4.p
141814.67/19006.52	% SZS status Started for HL407688+5.p
141814.67/19006.52	% SZS status GaveUp for HL407688+5.p
141814.67/19006.52	eprover: CPU time limit exceeded, terminating
141814.67/19006.52	% SZS status Ended for HL407688+5.p
141820.77/19007.33	% SZS status Started for HL407695+4.p
141820.77/19007.33	% SZS status GaveUp for HL407695+4.p
141820.77/19007.33	eprover: CPU time limit exceeded, terminating
141820.77/19007.33	% SZS status Ended for HL407695+4.p
141840.78/19009.81	% SZS status Started for HL407689+5.p
141840.78/19009.81	% SZS status GaveUp for HL407689+5.p
141840.78/19009.81	eprover: CPU time limit exceeded, terminating
141840.78/19009.81	% SZS status Ended for HL407689+5.p
141844.30/19010.37	% SZS status Started for HL407696+4.p
141844.30/19010.37	% SZS status GaveUp for HL407696+4.p
141844.30/19010.37	eprover: CPU time limit exceeded, terminating
141844.30/19010.37	% SZS status Ended for HL407696+4.p
141869.41/19013.41	% SZS status Started for HL407697+4.p
141869.41/19013.41	% SZS status GaveUp for HL407697+4.p
141869.41/19013.41	eprover: CPU time limit exceeded, terminating
141869.41/19013.41	% SZS status Ended for HL407697+4.p
141870.56/19013.56	% SZS status Started for HL407690+5.p
141870.56/19013.56	% SZS status GaveUp for HL407690+5.p
141870.56/19013.56	eprover: CPU time limit exceeded, terminating
141870.56/19013.56	% SZS status Ended for HL407690+5.p
141894.70/19016.59	% SZS status Started for HL407698+4.p
141894.70/19016.59	% SZS status GaveUp for HL407698+4.p
141894.70/19016.59	eprover: CPU time limit exceeded, terminating
141894.70/19016.59	% SZS status Ended for HL407698+4.p
141900.20/19017.30	% SZS status Started for HL407691+5.p
141900.20/19017.30	% SZS status GaveUp for HL407691+5.p
141900.20/19017.30	eprover: CPU time limit exceeded, terminating
141900.20/19017.30	% SZS status Ended for HL407691+5.p
141924.23/19020.35	% SZS status Started for HL407699+4.p
141924.23/19020.35	% SZS status GaveUp for HL407699+4.p
141924.23/19020.35	eprover: CPU time limit exceeded, terminating
141924.23/19020.35	% SZS status Ended for HL407699+4.p
141948.88/19023.47	% SZS status Started for HL407692+5.p
141948.88/19023.47	% SZS status GaveUp for HL407692+5.p
141948.88/19023.47	eprover: CPU time limit exceeded, terminating
141948.88/19023.47	% SZS status Ended for HL407692+5.p
141974.33/19026.66	% SZS status Started for HL407700+4.p
141974.33/19026.66	% SZS status GaveUp for HL407700+4.p
141974.33/19026.66	eprover: CPU time limit exceeded, terminating
141974.33/19026.66	% SZS status Ended for HL407700+4.p
141977.84/19027.21	% SZS status Started for HL407693+5.p
141977.84/19027.21	% SZS status GaveUp for HL407693+5.p
141977.84/19027.21	eprover: CPU time limit exceeded, terminating
141977.84/19027.21	% SZS status Ended for HL407693+5.p
141991.38/19028.82	% SZS status Started for HL407694+5.p
141991.38/19028.82	% SZS status GaveUp for HL407694+5.p
141991.38/19028.82	eprover: CPU time limit exceeded, terminating
141991.38/19028.82	% SZS status Ended for HL407694+5.p
142002.64/19030.27	% SZS status Started for HL407701+4.p
142002.64/19030.27	% SZS status GaveUp for HL407701+4.p
142002.64/19030.27	eprover: CPU time limit exceeded, terminating
142002.64/19030.27	% SZS status Ended for HL407701+4.p
142022.28/19032.72	% SZS status Started for HL407695+5.p
142022.28/19032.72	% SZS status GaveUp for HL407695+5.p
142022.28/19032.72	eprover: CPU time limit exceeded, terminating
142022.28/19032.72	% SZS status Ended for HL407695+5.p
142026.69/19033.30	% SZS status Started for HL407702+4.p
142026.69/19033.30	% SZS status GaveUp for HL407702+4.p
142026.69/19033.30	eprover: CPU time limit exceeded, terminating
142026.69/19033.30	% SZS status Ended for HL407702+4.p
142047.83/19035.91	% SZS status Started for HL407696+5.p
142047.83/19035.91	% SZS status GaveUp for HL407696+5.p
142047.83/19035.91	eprover: CPU time limit exceeded, terminating
142047.83/19035.91	% SZS status Ended for HL407696+5.p
142051.58/19036.37	% SZS status Started for HL407703+4.p
142051.58/19036.37	% SZS status GaveUp for HL407703+4.p
142051.58/19036.37	eprover: CPU time limit exceeded, terminating
142051.58/19036.37	% SZS status Ended for HL407703+4.p
142075.33/19039.41	% SZS status Started for HL407704+4.p
142075.33/19039.41	% SZS status GaveUp for HL407704+4.p
142075.33/19039.41	eprover: CPU time limit exceeded, terminating
142075.33/19039.41	% SZS status Ended for HL407704+4.p
142075.95/19039.46	% SZS status Started for HL407697+5.p
142075.95/19039.46	% SZS status GaveUp for HL407697+5.p
142075.95/19039.46	eprover: CPU time limit exceeded, terminating
142075.95/19039.46	% SZS status Ended for HL407697+5.p
142100.59/19042.53	% SZS status Started for HL407705+4.p
142100.59/19042.53	% SZS status GaveUp for HL407705+4.p
142100.59/19042.53	eprover: CPU time limit exceeded, terminating
142100.59/19042.53	% SZS status Ended for HL407705+4.p
142100.59/19042.56	% SZS status Started for HL407698+5.p
142100.59/19042.56	% SZS status GaveUp for HL407698+5.p
142100.59/19042.56	eprover: CPU time limit exceeded, terminating
142100.59/19042.56	% SZS status Ended for HL407698+5.p
142124.48/19045.59	% SZS status Started for HL407706+4.p
142124.48/19045.59	% SZS status GaveUp for HL407706+4.p
142124.48/19045.59	eprover: CPU time limit exceeded, terminating
142124.48/19045.59	% SZS status Ended for HL407706+4.p
142130.12/19046.29	% SZS status Started for HL407699+5.p
142130.12/19046.29	% SZS status GaveUp for HL407699+5.p
142130.12/19046.29	eprover: CPU time limit exceeded, terminating
142130.12/19046.29	% SZS status Ended for HL407699+5.p
142154.56/19049.32	% SZS status Started for HL407707+4.p
142154.56/19049.32	% SZS status GaveUp for HL407707+4.p
142154.56/19049.32	eprover: CPU time limit exceeded, terminating
142154.56/19049.32	% SZS status Ended for HL407707+4.p
142179.53/19052.51	% SZS status Started for HL407700+5.p
142179.53/19052.51	% SZS status GaveUp for HL407700+5.p
142179.53/19052.51	eprover: CPU time limit exceeded, terminating
142179.53/19052.51	% SZS status Ended for HL407700+5.p
142200.02/19055.05	% SZS status Started for HL407701+5.p
142200.02/19055.05	% SZS status GaveUp for HL407701+5.p
142200.02/19055.05	eprover: CPU time limit exceeded, terminating
142200.02/19055.05	% SZS status Ended for HL407701+5.p
142204.02/19055.55	% SZS status Started for HL407709+4.p
142204.02/19055.55	% SZS status GaveUp for HL407709+4.p
142204.02/19055.55	eprover: CPU time limit exceeded, terminating
142204.02/19055.55	% SZS status Ended for HL407709+4.p
142228.30/19058.62	% SZS status Started for HL407710+4.p
142228.30/19058.62	% SZS status GaveUp for HL407710+4.p
142228.30/19058.62	eprover: CPU time limit exceeded, terminating
142228.30/19058.62	% SZS status Ended for HL407710+4.p
142228.30/19058.64	% SZS status Started for HL407702+5.p
142228.30/19058.64	% SZS status GaveUp for HL407702+5.p
142228.30/19058.64	eprover: CPU time limit exceeded, terminating
142228.30/19058.64	% SZS status Ended for HL407702+5.p
142252.55/19061.68	% SZS status Started for HL407711+4.p
142252.55/19061.68	% SZS status GaveUp for HL407711+4.p
142252.55/19061.68	eprover: CPU time limit exceeded, terminating
142252.55/19061.68	% SZS status Ended for HL407711+4.p
142255.31/19062.07	% SZS status Started for HL407703+5.p
142255.31/19062.07	% SZS status GaveUp for HL407703+5.p
142255.31/19062.07	eprover: CPU time limit exceeded, terminating
142255.31/19062.07	% SZS status Ended for HL407703+5.p
142279.69/19065.11	% SZS status Started for HL407712+4.p
142279.69/19065.11	% SZS status GaveUp for HL407712+4.p
142279.69/19065.11	eprover: CPU time limit exceeded, terminating
142279.69/19065.11	% SZS status Ended for HL407712+4.p
142282.38/19065.43	% SZS status Started for HL407704+5.p
142282.38/19065.43	% SZS status GaveUp for HL407704+5.p
142282.38/19065.43	eprover: CPU time limit exceeded, terminating
142282.38/19065.43	% SZS status Ended for HL407704+5.p
142305.84/19068.45	% SZS status Started for HL407713+4.p
142305.84/19068.45	% SZS status GaveUp for HL407713+4.p
142305.84/19068.45	eprover: CPU time limit exceeded, terminating
142305.84/19068.45	% SZS status Ended for HL407713+4.p
142307.03/19068.57	% SZS status Started for HL407705+5.p
142307.03/19068.57	% SZS status GaveUp for HL407705+5.p
142307.03/19068.57	eprover: CPU time limit exceeded, terminating
142307.03/19068.57	% SZS status Ended for HL407705+5.p
142331.06/19071.58	% SZS status Started for HL407706+5.p
142331.06/19071.58	% SZS status GaveUp for HL407706+5.p
142331.06/19071.58	eprover: CPU time limit exceeded, terminating
142331.06/19071.58	% SZS status Ended for HL407706+5.p
142331.23/19071.59	% SZS status Started for HL407714+4.p
142331.23/19071.59	% SZS status GaveUp for HL407714+4.p
142331.23/19071.59	eprover: CPU time limit exceeded, terminating
142331.23/19071.59	% SZS status Ended for HL407714+4.p
142355.75/19074.70	% SZS status Started for HL407715+4.p
142355.75/19074.70	% SZS status GaveUp for HL407715+4.p
142355.75/19074.70	eprover: CPU time limit exceeded, terminating
142355.75/19074.70	% SZS status Ended for HL407715+4.p
142362.17/19075.51	% SZS status Started for HL407707+5.p
142362.17/19075.51	% SZS status GaveUp for HL407707+5.p
142362.17/19075.51	eprover: CPU time limit exceeded, terminating
142362.17/19075.51	% SZS status Ended for HL407707+5.p
142386.20/19078.57	% SZS status Started for HL407716+4.p
142386.20/19078.57	% SZS status GaveUp for HL407716+4.p
142386.20/19078.57	eprover: CPU time limit exceeded, terminating
142386.20/19078.57	% SZS status Ended for HL407716+4.p
142406.58/19081.11	% SZS status Started for HL407709+5.p
142406.58/19081.11	% SZS status GaveUp for HL407709+5.p
142406.58/19081.11	eprover: CPU time limit exceeded, terminating
142406.58/19081.11	% SZS status Ended for HL407709+5.p
142431.19/19084.20	% SZS status Started for HL407717+4.p
142431.19/19084.20	% SZS status GaveUp for HL407717+4.p
142431.19/19084.20	eprover: CPU time limit exceeded, terminating
142431.19/19084.20	% SZS status Ended for HL407717+4.p
142434.72/19084.69	% SZS status Started for HL407710+5.p
142434.72/19084.69	% SZS status GaveUp for HL407710+5.p
142434.72/19084.69	eprover: CPU time limit exceeded, terminating
142434.72/19084.69	% SZS status Ended for HL407710+5.p
142438.34/19085.11	% SZS status Started for HL407715+5.p
142438.34/19085.11	% SZS status GaveUp for HL407715+5.p
142438.34/19085.11	eprover: CPU time limit exceeded, terminating
142438.34/19085.11	% SZS status Ended for HL407715+5.p
142458.98/19087.72	% SZS status Started for HL407718+4.p
142458.98/19087.72	% SZS status GaveUp for HL407718+4.p
142458.98/19087.72	eprover: CPU time limit exceeded, terminating
142458.98/19087.72	% SZS status Ended for HL407718+4.p
142458.98/19087.74	% SZS status Started for HL407711+5.p
142458.98/19087.74	% SZS status GaveUp for HL407711+5.p
142458.98/19087.74	eprover: CPU time limit exceeded, terminating
142458.98/19087.74	% SZS status Ended for HL407711+5.p
142483.08/19090.75	% SZS status Started for HL407719+4.p
142483.08/19090.75	% SZS status GaveUp for HL407719+4.p
142483.08/19090.75	eprover: CPU time limit exceeded, terminating
142483.08/19090.75	% SZS status Ended for HL407719+4.p
142486.73/19091.21	% SZS status Started for HL407712+5.p
142486.73/19091.21	% SZS status GaveUp for HL407712+5.p
142486.73/19091.21	eprover: CPU time limit exceeded, terminating
142486.73/19091.21	% SZS status Ended for HL407712+5.p
142507.08/19093.80	% SZS status Started for HL407720+4.p
142507.08/19093.80	% SZS status GaveUp for HL407720+4.p
142507.08/19093.80	eprover: CPU time limit exceeded, terminating
142507.08/19093.80	% SZS status Ended for HL407720+4.p
142512.62/19094.44	% SZS status Started for HL407713+5.p
142512.62/19094.44	% SZS status GaveUp for HL407713+5.p
142512.62/19094.44	eprover: CPU time limit exceeded, terminating
142512.62/19094.44	% SZS status Ended for HL407713+5.p
142522.80/19095.77	% SZS status Started for HL407718+5.p
142522.80/19095.77	% SZS status GaveUp for HL407718+5.p
142522.80/19095.77	eprover: CPU time limit exceeded, terminating
142522.80/19095.77	% SZS status Ended for HL407718+5.p
142531.53/19096.84	% SZS status Started for HL407721+4.p
142531.53/19096.84	% SZS status GaveUp for HL407721+4.p
142531.53/19096.84	eprover: CPU time limit exceeded, terminating
142531.53/19096.84	% SZS status Ended for HL407721+4.p
142536.98/19097.55	% SZS status Started for HL407714+5.p
142536.98/19097.55	% SZS status GaveUp for HL407714+5.p
142536.98/19097.55	eprover: CPU time limit exceeded, terminating
142536.98/19097.55	% SZS status Ended for HL407714+5.p
142548.02/19098.90	% SZS status Started for HL407722+4.p
142548.02/19098.90	% SZS status GaveUp for HL407722+4.p
142548.02/19098.90	eprover: CPU time limit exceeded, terminating
142548.02/19098.90	% SZS status Ended for HL407722+4.p
142561.52/19100.63	% SZS status Started for HL407723+4.p
142561.52/19100.63	% SZS status GaveUp for HL407723+4.p
142561.52/19100.63	eprover: CPU time limit exceeded, terminating
142561.52/19100.63	% SZS status Ended for HL407723+4.p
142585.20/19103.68	% SZS status Started for HL407724+4.p
142585.20/19103.68	% SZS status GaveUp for HL407724+4.p
142585.20/19103.68	eprover: CPU time limit exceeded, terminating
142585.20/19103.68	% SZS status Ended for HL407724+4.p
142593.28/19104.68	% SZS status Started for HL407716+5.p
142593.28/19104.68	% SZS status GaveUp for HL407716+5.p
142593.28/19104.68	eprover: CPU time limit exceeded, terminating
142593.28/19104.68	% SZS status Ended for HL407716+5.p
142617.47/19107.72	% SZS status Started for HL407725+4.p
142617.47/19107.72	% SZS status GaveUp for HL407725+4.p
142617.47/19107.72	eprover: CPU time limit exceeded, terminating
142617.47/19107.72	% SZS status Ended for HL407725+4.p
142636.02/19110.08	% SZS status Started for HL407717+5.p
142636.02/19110.08	% SZS status GaveUp for HL407717+5.p
142636.02/19110.08	eprover: CPU time limit exceeded, terminating
142636.02/19110.08	% SZS status Ended for HL407717+5.p
142660.53/19113.15	% SZS status Started for HL407728+4.p
142660.53/19113.15	% SZS status GaveUp for HL407728+4.p
142660.53/19113.15	eprover: CPU time limit exceeded, terminating
142660.53/19113.15	% SZS status Ended for HL407728+4.p
142666.06/19113.81	% SZS status Started for HL407719+5.p
142666.06/19113.81	% SZS status GaveUp for HL407719+5.p
142666.06/19113.81	eprover: CPU time limit exceeded, terminating
142666.06/19113.81	% SZS status Ended for HL407719+5.p
142689.97/19116.84	% SZS status Started for HL407730+4.p
142689.97/19116.84	% SZS status GaveUp for HL407730+4.p
142689.97/19116.84	eprover: CPU time limit exceeded, terminating
142689.97/19116.84	% SZS status Ended for HL407730+4.p
142692.59/19117.27	% SZS status Started for HL407720+5.p
142692.59/19117.27	% SZS status GaveUp for HL407720+5.p
142692.59/19117.27	eprover: CPU time limit exceeded, terminating
142692.59/19117.27	% SZS status Ended for HL407720+5.p
142717.34/19120.36	% SZS status Started for HL407731+4.p
142717.34/19120.36	% SZS status GaveUp for HL407731+4.p
142717.34/19120.36	eprover: CPU time limit exceeded, terminating
142717.34/19120.36	% SZS status Ended for HL407731+4.p
142718.56/19120.56	% SZS status Started for HL407721+5.p
142718.56/19120.56	% SZS status GaveUp for HL407721+5.p
142718.56/19120.56	eprover: CPU time limit exceeded, terminating
142718.56/19120.56	% SZS status Ended for HL407721+5.p
142739.11/19123.06	% SZS status Started for HL407722+5.p
142739.11/19123.06	% SZS status GaveUp for HL407722+5.p
142739.11/19123.06	eprover: CPU time limit exceeded, terminating
142739.11/19123.06	% SZS status Ended for HL407722+5.p
142742.78/19123.59	% SZS status Started for HL407732+4.p
142742.78/19123.59	% SZS status GaveUp for HL407732+4.p
142742.78/19123.59	eprover: CPU time limit exceeded, terminating
142742.78/19123.59	% SZS status Ended for HL407732+4.p
142754.94/19125.06	% SZS status Started for HL407723+5.p
142754.94/19125.06	% SZS status GaveUp for HL407723+5.p
142754.94/19125.06	eprover: CPU time limit exceeded, terminating
142754.94/19125.06	% SZS status Ended for HL407723+5.p
142767.64/19126.62	% SZS status Started for HL407733+4.p
142767.64/19126.62	% SZS status GaveUp for HL407733+4.p
142767.64/19126.62	eprover: CPU time limit exceeded, terminating
142767.64/19126.62	% SZS status Ended for HL407733+4.p
142790.78/19129.59	% SZS status Started for HL407724+5.p
142790.78/19129.59	% SZS status GaveUp for HL407724+5.p
142790.78/19129.59	eprover: CPU time limit exceeded, terminating
142790.78/19129.59	% SZS status Ended for HL407724+5.p
142792.58/19129.79	% SZS status Started for HL407734+4.p
142792.58/19129.79	% SZS status GaveUp for HL407734+4.p
142792.58/19129.79	eprover: CPU time limit exceeded, terminating
142792.58/19129.79	% SZS status Ended for HL407734+4.p
142817.20/19132.89	% SZS status Started for HL407736+4.p
142817.20/19132.89	% SZS status GaveUp for HL407736+4.p
142817.20/19132.89	eprover: CPU time limit exceeded, terminating
142817.20/19132.89	% SZS status Ended for HL407736+4.p
142824.06/19133.68	% SZS status Started for HL407725+5.p
142824.06/19133.68	% SZS status GaveUp for HL407725+5.p
142824.06/19133.68	eprover: CPU time limit exceeded, terminating
142824.06/19133.68	% SZS status Ended for HL407725+5.p
142848.09/19136.73	% SZS status Started for HL407737+4.p
142848.09/19136.73	% SZS status GaveUp for HL407737+4.p
142848.09/19136.73	eprover: CPU time limit exceeded, terminating
142848.09/19136.73	% SZS status Ended for HL407737+4.p
142866.33/19139.04	% SZS status Started for HL407728+5.p
142866.33/19139.04	% SZS status GaveUp for HL407728+5.p
142866.33/19139.04	eprover: CPU time limit exceeded, terminating
142866.33/19139.04	% SZS status Ended for HL407728+5.p
142890.64/19142.08	% SZS status Started for HL407738+4.p
142890.64/19142.08	% SZS status GaveUp for HL407738+4.p
142890.64/19142.08	eprover: CPU time limit exceeded, terminating
142890.64/19142.08	% SZS status Ended for HL407738+4.p
142896.72/19142.89	% SZS status Started for HL407730+5.p
142896.72/19142.89	% SZS status GaveUp for HL407730+5.p
142896.72/19142.89	eprover: CPU time limit exceeded, terminating
142896.72/19142.89	% SZS status Ended for HL407730+5.p
142922.02/19146.04	% SZS status Started for HL407739+4.p
142922.02/19146.04	% SZS status GaveUp for HL407739+4.p
142922.02/19146.04	eprover: CPU time limit exceeded, terminating
142922.02/19146.04	% SZS status Ended for HL407739+4.p
142923.23/19146.23	% SZS status Started for HL407731+5.p
142923.23/19146.23	% SZS status GaveUp for HL407731+5.p
142923.23/19146.23	eprover: CPU time limit exceeded, terminating
142923.23/19146.23	% SZS status Ended for HL407731+5.p
142947.73/19149.26	% SZS status Started for HL407740+4.p
142947.73/19149.26	% SZS status GaveUp for HL407740+4.p
142947.73/19149.26	eprover: CPU time limit exceeded, terminating
142947.73/19149.26	% SZS status Ended for HL407740+4.p
142947.73/19149.29	% SZS status Started for HL407732+5.p
142947.73/19149.29	% SZS status GaveUp for HL407732+5.p
142947.73/19149.29	eprover: CPU time limit exceeded, terminating
142947.73/19149.29	% SZS status Ended for HL407732+5.p
142962.02/19151.07	% SZS status Started for HL407733+5.p
142962.02/19151.07	% SZS status GaveUp for HL407733+5.p
142962.02/19151.07	eprover: CPU time limit exceeded, terminating
142962.02/19151.07	% SZS status Ended for HL407733+5.p
142971.56/19152.32	% SZS status Started for HL407741+4.p
142971.56/19152.32	% SZS status GaveUp for HL407741+4.p
142971.56/19152.32	eprover: CPU time limit exceeded, terminating
142971.56/19152.32	% SZS status Ended for HL407741+4.p
142996.48/19155.41	% SZS status Started for HL407742+4.p
142996.48/19155.41	% SZS status GaveUp for HL407742+4.p
142996.48/19155.41	eprover: CPU time limit exceeded, terminating
142996.48/19155.41	% SZS status Ended for HL407742+4.p
142997.59/19155.57	% SZS status Started for HL407734+5.p
142997.59/19155.57	% SZS status GaveUp for HL407734+5.p
142997.59/19155.57	eprover: CPU time limit exceeded, terminating
142997.59/19155.57	% SZS status Ended for HL407734+5.p
143004.23/19156.40	% SZS status Started for HL407739+5.p
143004.23/19156.40	% SZS status GaveUp for HL407739+5.p
143004.23/19156.40	eprover: CPU time limit exceeded, terminating
143004.23/19156.40	% SZS status Ended for HL407739+5.p
143022.17/19158.68	% SZS status Started for HL407743+4.p
143022.17/19158.68	% SZS status GaveUp for HL407743+4.p
143022.17/19158.68	eprover: CPU time limit exceeded, terminating
143022.17/19158.68	% SZS status Ended for HL407743+4.p
143022.88/19158.73	% SZS status Started for HL407736+5.p
143022.88/19158.73	% SZS status GaveUp for HL407736+5.p
143022.88/19158.73	eprover: CPU time limit exceeded, terminating
143022.88/19158.73	% SZS status Ended for HL407736+5.p
143046.75/19161.74	% SZS status Started for HL407744+4.p
143046.75/19161.74	% SZS status GaveUp for HL407744+4.p
143046.75/19161.74	eprover: CPU time limit exceeded, terminating
143046.75/19161.74	% SZS status Ended for HL407744+4.p
143057.47/19162.75	% SZS status Started for HL407737+5.p
143057.47/19162.75	% SZS status GaveUp for HL407737+5.p
143057.47/19162.75	eprover: CPU time limit exceeded, terminating
143057.47/19162.75	% SZS status Ended for HL407737+5.p
143074.45/19164.87	% SZS status Started for HL407746+4.p
143074.45/19164.87	% SZS status GaveUp for HL407746+4.p
143074.45/19164.87	eprover: CPU time limit exceeded, terminating
143074.45/19164.87	% SZS status Ended for HL407746+4.p
143099.00/19167.97	% SZS status Started for HL407747+4.p
143099.00/19167.97	% SZS status GaveUp for HL407747+4.p
143099.00/19167.97	eprover: CPU time limit exceeded, terminating
143099.00/19167.97	% SZS status Ended for HL407747+4.p
143100.84/19168.20	% SZS status Started for HL407738+5.p
143100.84/19168.20	% SZS status GaveUp for HL407738+5.p
143100.84/19168.20	eprover: CPU time limit exceeded, terminating
143100.84/19168.20	% SZS status Ended for HL407738+5.p
143124.45/19171.25	% SZS status Started for HL407748+4.p
143124.45/19171.25	% SZS status GaveUp for HL407748+4.p
143124.45/19171.25	eprover: CPU time limit exceeded, terminating
143124.45/19171.25	% SZS status Ended for HL407748+4.p
143157.05/19175.31	% SZS status Started for HL407740+5.p
143157.05/19175.31	% SZS status GaveUp for HL407740+5.p
143157.05/19175.31	eprover: CPU time limit exceeded, terminating
143157.05/19175.31	% SZS status Ended for HL407740+5.p
143170.09/19176.97	% SZS status Started for HL407741+5.p
143170.09/19176.97	% SZS status GaveUp for HL407741+5.p
143170.09/19176.97	eprover: CPU time limit exceeded, terminating
143170.09/19176.97	% SZS status Ended for HL407741+5.p
143180.30/19178.20	% SZS status Started for HL407747+5.p
143180.30/19178.20	% SZS status GaveUp for HL407747+5.p
143180.30/19178.20	eprover: CPU time limit exceeded, terminating
143180.30/19178.20	% SZS status Ended for HL407747+5.p
143181.73/19178.42	% SZS status Started for HL407749+4.p
143181.73/19178.42	% SZS status GaveUp for HL407749+4.p
143181.73/19178.42	eprover: CPU time limit exceeded, terminating
143181.73/19178.42	% SZS status Ended for HL407749+4.p
143204.45/19181.23	% SZS status Started for HL407750+4.p
143204.45/19181.23	% SZS status GaveUp for HL407750+4.p
143204.45/19181.23	eprover: CPU time limit exceeded, terminating
143204.45/19181.23	% SZS status Ended for HL407750+4.p
143206.61/19181.52	% SZS status Started for HL407742+5.p
143206.61/19181.52	% SZS status GaveUp for HL407742+5.p
143206.61/19181.52	eprover: CPU time limit exceeded, terminating
143206.61/19181.52	% SZS status Ended for HL407742+5.p
143214.27/19182.48	% SZS status Started for HL407743+5.p
143214.27/19182.48	% SZS status GaveUp for HL407743+5.p
143214.27/19182.48	eprover: CPU time limit exceeded, terminating
143214.27/19182.48	% SZS status Ended for HL407743+5.p
143228.36/19184.26	% SZS status Started for HL407751+4.p
143228.36/19184.26	% SZS status GaveUp for HL407751+4.p
143228.36/19184.26	eprover: CPU time limit exceeded, terminating
143228.36/19184.26	% SZS status Ended for HL407751+4.p
143233.75/19184.95	% SZS status Started for HL407744+5.p
143233.75/19184.95	% SZS status GaveUp for HL407744+5.p
143233.75/19184.95	eprover: CPU time limit exceeded, terminating
143233.75/19184.95	% SZS status Ended for HL407744+5.p
143238.64/19185.53	% SZS status Started for HL407752+4.p
143238.64/19185.53	% SZS status GaveUp for HL407752+4.p
143238.64/19185.53	eprover: CPU time limit exceeded, terminating
143238.64/19185.53	% SZS status Ended for HL407752+4.p
143258.44/19188.08	% SZS status Started for HL407754+4.p
143258.44/19188.08	% SZS status GaveUp for HL407754+4.p
143258.44/19188.08	eprover: CPU time limit exceeded, terminating
143258.44/19188.08	% SZS status Ended for HL407754+4.p
143263.86/19188.76	% SZS status Started for HL407746+5.p
143263.86/19188.76	% SZS status GaveUp for HL407746+5.p
143263.86/19188.76	eprover: CPU time limit exceeded, terminating
143263.86/19188.76	% SZS status Ended for HL407746+5.p
143283.25/19191.19	% SZS status Started for HL407755+4.p
143283.25/19191.19	% SZS status GaveUp for HL407755+4.p
143283.25/19191.19	eprover: CPU time limit exceeded, terminating
143283.25/19191.19	% SZS status Ended for HL407755+4.p
143307.72/19194.22	% SZS status Started for HL407756+4.p
143307.72/19194.22	% SZS status GaveUp for HL407756+4.p
143307.72/19194.22	eprover: CPU time limit exceeded, terminating
143307.72/19194.22	% SZS status Ended for HL407756+4.p
143331.00/19197.17	% SZS status Started for HL407748+5.p
143331.00/19197.17	% SZS status GaveUp for HL407748+5.p
143331.00/19197.17	eprover: CPU time limit exceeded, terminating
143331.00/19197.17	% SZS status Ended for HL407748+5.p
143355.75/19200.25	% SZS status Started for HL407757+4.p
143355.75/19200.25	% SZS status GaveUp for HL407757+4.p
143355.75/19200.25	eprover: CPU time limit exceeded, terminating
143355.75/19200.25	% SZS status Ended for HL407757+4.p
143376.53/19202.89	% SZS status Started for HL407749+5.p
143376.53/19202.89	% SZS status GaveUp for HL407749+5.p
143376.53/19202.89	eprover: CPU time limit exceeded, terminating
143376.53/19202.89	% SZS status Ended for HL407749+5.p
143388.52/19204.40	% SZS status Started for HL407750+5.p
143388.52/19204.40	% SZS status GaveUp for HL407750+5.p
143388.52/19204.40	eprover: CPU time limit exceeded, terminating
143388.52/19204.40	% SZS status Ended for HL407750+5.p
143400.38/19205.92	% SZS status Started for HL407759+4.p
143400.38/19205.92	% SZS status GaveUp for HL407759+4.p
143400.38/19205.92	eprover: CPU time limit exceeded, terminating
143400.38/19205.92	% SZS status Ended for HL407759+4.p
143414.12/19207.65	% SZS status Started for HL407751+5.p
143414.12/19207.65	% SZS status GaveUp for HL407751+5.p
143414.12/19207.65	eprover: CPU time limit exceeded, terminating
143414.12/19207.65	% SZS status Ended for HL407751+5.p
143424.53/19208.94	% SZS status Started for HL407760+4.p
143424.53/19208.94	% SZS status GaveUp for HL407760+4.p
143424.53/19208.94	eprover: CPU time limit exceeded, terminating
143424.53/19208.94	% SZS status Ended for HL407760+4.p
143435.17/19210.24	% SZS status Started for HL407752+5.p
143435.17/19210.24	% SZS status GaveUp for HL407752+5.p
143435.17/19210.24	eprover: CPU time limit exceeded, terminating
143435.17/19210.24	% SZS status Ended for HL407752+5.p
143444.39/19211.42	% SZS status Started for HL407754+5.p
143444.39/19211.42	% SZS status GaveUp for HL407754+5.p
143444.39/19211.42	eprover: CPU time limit exceeded, terminating
143444.39/19211.42	% SZS status Ended for HL407754+5.p
143448.58/19211.98	% SZS status Started for HL407761+4.p
143448.58/19211.98	% SZS status GaveUp for HL407761+4.p
143448.58/19211.98	eprover: CPU time limit exceeded, terminating
143448.58/19211.98	% SZS status Ended for HL407761+4.p
143468.78/19214.48	% SZS status Started for HL407762+4.p
143468.78/19214.48	% SZS status GaveUp for HL407762+4.p
143468.78/19214.48	eprover: CPU time limit exceeded, terminating
143468.78/19214.48	% SZS status Ended for HL407762+4.p
143472.08/19214.94	% SZS status Started for HL407755+5.p
143472.08/19214.94	% SZS status GaveUp for HL407755+5.p
143472.08/19214.94	eprover: CPU time limit exceeded, terminating
143472.08/19214.94	% SZS status Ended for HL407755+5.p
143493.22/19217.55	% SZS status Started for HL407763+4.p
143493.22/19217.55	% SZS status GaveUp for HL407763+4.p
143493.22/19217.55	eprover: CPU time limit exceeded, terminating
143493.22/19217.55	% SZS status Ended for HL407763+4.p
143514.11/19220.20	% SZS status Started for HL407756+5.p
143514.11/19220.20	% SZS status GaveUp for HL407756+5.p
143514.11/19220.20	eprover: CPU time limit exceeded, terminating
143514.11/19220.20	% SZS status Ended for HL407756+5.p
143516.53/19220.59	% SZS status Started for HL407764+4.p
143516.53/19220.59	% SZS status GaveUp for HL407764+4.p
143516.53/19220.59	eprover: CPU time limit exceeded, terminating
143516.53/19220.59	% SZS status Ended for HL407764+4.p
143541.50/19223.68	% SZS status Started for HL407765+4.p
143541.50/19223.68	% SZS status GaveUp for HL407765+4.p
143541.50/19223.68	eprover: CPU time limit exceeded, terminating
143541.50/19223.68	% SZS status Ended for HL407765+4.p
143557.44/19225.69	% SZS status Started for HL407763+5.p
143557.44/19225.69	% SZS status GaveUp for HL407763+5.p
143557.44/19225.69	eprover: CPU time limit exceeded, terminating
143557.44/19225.69	% SZS status Ended for HL407763+5.p
143562.41/19226.28	% SZS status Started for HL407757+5.p
143562.41/19226.28	% SZS status GaveUp for HL407757+5.p
143562.41/19226.28	eprover: CPU time limit exceeded, terminating
143562.41/19226.28	% SZS status Ended for HL407757+5.p
143582.39/19228.77	% SZS status Started for HL407768+4.p
143582.39/19228.77	% SZS status GaveUp for HL407768+4.p
143582.39/19228.77	eprover: CPU time limit exceeded, terminating
143582.39/19228.77	% SZS status Ended for HL407768+4.p
143594.77/19230.40	% SZS status Started for HL407759+5.p
143594.77/19230.40	% SZS status GaveUp for HL407759+5.p
143594.77/19230.40	eprover: CPU time limit exceeded, terminating
143594.77/19230.40	% SZS status Ended for HL407759+5.p
143606.47/19231.82	% SZS status Started for HL407770+4.p
143606.47/19231.82	% SZS status GaveUp for HL407770+4.p
143606.47/19231.82	eprover: CPU time limit exceeded, terminating
143606.47/19231.82	% SZS status Ended for HL407770+4.p
143621.59/19233.72	% SZS status Started for HL407760+5.p
143621.59/19233.72	% SZS status GaveUp for HL407760+5.p
143621.59/19233.72	eprover: CPU time limit exceeded, terminating
143621.59/19233.72	% SZS status Ended for HL407760+5.p
143630.14/19234.90	% SZS status Started for HL407771+4.p
143630.14/19234.90	% SZS status GaveUp for HL407771+4.p
143630.14/19234.90	eprover: CPU time limit exceeded, terminating
143630.14/19234.90	% SZS status Ended for HL407771+4.p
143642.09/19236.31	% SZS status Started for HL407761+5.p
143642.09/19236.31	% SZS status GaveUp for HL407761+5.p
143642.09/19236.31	eprover: CPU time limit exceeded, terminating
143642.09/19236.31	% SZS status Ended for HL407761+5.p
143654.11/19237.86	% SZS status Started for HL407762+5.p
143654.11/19237.86	% SZS status GaveUp for HL407762+5.p
143654.11/19237.86	eprover: CPU time limit exceeded, terminating
143654.11/19237.86	% SZS status Ended for HL407762+5.p
143654.83/19237.96	% SZS status Started for HL407772+4.p
143654.83/19237.96	% SZS status GaveUp for HL407772+4.p
143654.83/19237.96	eprover: CPU time limit exceeded, terminating
143654.83/19237.96	% SZS status Ended for HL407772+4.p
143678.56/19240.98	% SZS status Started for HL407773+4.p
143678.56/19240.98	% SZS status GaveUp for HL407773+4.p
143678.56/19240.98	eprover: CPU time limit exceeded, terminating
143678.56/19240.98	% SZS status Ended for HL407773+4.p
143702.66/19244.03	% SZS status Started for HL407774+4.p
143702.66/19244.03	% SZS status GaveUp for HL407774+4.p
143702.66/19244.03	eprover: CPU time limit exceeded, terminating
143702.66/19244.03	% SZS status Ended for HL407774+4.p
143703.89/19244.15	% SZS status Started for HL407771+5.p
143703.89/19244.15	% SZS status GaveUp for HL407771+5.p
143703.89/19244.15	eprover: CPU time limit exceeded, terminating
143703.89/19244.15	% SZS status Ended for HL407771+5.p
143721.03/19246.28	% SZS status Started for HL407764+5.p
143721.03/19246.28	% SZS status GaveUp for HL407764+5.p
143721.03/19246.28	eprover: CPU time limit exceeded, terminating
143721.03/19246.28	% SZS status Ended for HL407764+5.p
143728.44/19247.24	% SZS status Started for HL407776+4.p
143728.44/19247.24	% SZS status GaveUp for HL407776+4.p
143728.44/19247.24	eprover: CPU time limit exceeded, terminating
143728.44/19247.24	% SZS status Ended for HL407776+4.p
143747.98/19249.77	% SZS status Started for HL407765+5.p
143747.98/19249.77	% SZS status GaveUp for HL407765+5.p
143747.98/19249.77	eprover: CPU time limit exceeded, terminating
143747.98/19249.77	% SZS status Ended for HL407765+5.p
143752.19/19250.28	% SZS status Started for HL407777+4.p
143752.19/19250.28	% SZS status GaveUp for HL407777+4.p
143752.19/19250.28	eprover: CPU time limit exceeded, terminating
143752.19/19250.28	% SZS status Ended for HL407777+4.p
143768.27/19252.38	% SZS status Started for HL407768+5.p
143768.27/19252.38	% SZS status GaveUp for HL407768+5.p
143768.27/19252.38	eprover: CPU time limit exceeded, terminating
143768.27/19252.38	% SZS status Ended for HL407768+5.p
143776.59/19253.32	% SZS status Started for HL407778+4.p
143776.59/19253.32	% SZS status GaveUp for HL407778+4.p
143776.59/19253.32	eprover: CPU time limit exceeded, terminating
143776.59/19253.32	% SZS status Ended for HL407778+4.p
143801.00/19256.38	% SZS status Started for HL407780+4.p
143801.00/19256.38	% SZS status GaveUp for HL407780+4.p
143801.00/19256.38	eprover: CPU time limit exceeded, terminating
143801.00/19256.38	% SZS status Ended for HL407780+4.p
143802.80/19256.57	% SZS status Started for HL407770+5.p
143802.80/19256.57	% SZS status GaveUp for HL407770+5.p
143802.80/19256.57	eprover: CPU time limit exceeded, terminating
143802.80/19256.57	% SZS status Ended for HL407770+5.p
143827.06/19259.71	% SZS status Started for HL407781+4.p
143827.06/19259.71	% SZS status GaveUp for HL407781+4.p
143827.06/19259.71	eprover: CPU time limit exceeded, terminating
143827.06/19259.71	% SZS status Ended for HL407781+4.p
143847.77/19262.29	% SZS status Started for HL407772+5.p
143847.77/19262.29	% SZS status GaveUp for HL407772+5.p
143847.77/19262.29	eprover: CPU time limit exceeded, terminating
143847.77/19262.29	% SZS status Ended for HL407772+5.p
143861.09/19264.00	% SZS status Started for HL407773+5.p
143861.09/19264.00	% SZS status GaveUp for HL407773+5.p
143861.09/19264.00	eprover: CPU time limit exceeded, terminating
143861.09/19264.00	% SZS status Ended for HL407773+5.p
143871.97/19265.32	% SZS status Started for HL407782+4.p
143871.97/19265.32	% SZS status GaveUp for HL407782+4.p
143871.97/19265.32	eprover: CPU time limit exceeded, terminating
143871.97/19265.32	% SZS status Ended for HL407782+4.p
143895.59/19268.34	% SZS status Started for HL407783+4.p
143895.59/19268.34	% SZS status GaveUp for HL407783+4.p
143895.59/19268.34	eprover: CPU time limit exceeded, terminating
143895.59/19268.34	% SZS status Ended for HL407783+4.p
143908.03/19269.91	% SZS status Started for HL407774+5.p
143908.03/19269.91	% SZS status GaveUp for HL407774+5.p
143908.03/19269.91	eprover: CPU time limit exceeded, terminating
143908.03/19269.91	% SZS status Ended for HL407774+5.p
143928.17/19272.42	% SZS status Started for HL407776+5.p
143928.17/19272.42	% SZS status GaveUp for HL407776+5.p
143928.17/19272.42	eprover: CPU time limit exceeded, terminating
143928.17/19272.42	% SZS status Ended for HL407776+5.p
143933.67/19273.06	% SZS status Started for HL407785+4.p
143933.67/19273.06	% SZS status GaveUp for HL407785+4.p
143933.67/19273.06	eprover: CPU time limit exceeded, terminating
143933.67/19273.06	% SZS status Ended for HL407785+4.p
143955.52/19275.83	% SZS status Started for HL407777+5.p
143955.52/19275.83	% SZS status GaveUp for HL407777+5.p
143955.52/19275.83	eprover: CPU time limit exceeded, terminating
143955.52/19275.83	% SZS status Ended for HL407777+5.p
143958.08/19276.15	% SZS status Started for HL407786+4.p
143958.08/19276.15	% SZS status GaveUp for HL407786+4.p
143958.08/19276.15	eprover: CPU time limit exceeded, terminating
143958.08/19276.15	% SZS status Ended for HL407786+4.p
143977.08/19278.61	% SZS status Started for HL407778+5.p
143977.08/19278.61	% SZS status GaveUp for HL407778+5.p
143977.08/19278.61	eprover: CPU time limit exceeded, terminating
143977.08/19278.61	% SZS status Ended for HL407778+5.p
143982.78/19279.30	% SZS status Started for HL407787+4.p
143982.78/19279.30	% SZS status GaveUp for HL407787+4.p
143982.78/19279.30	eprover: CPU time limit exceeded, terminating
143982.78/19279.30	% SZS status Ended for HL407787+4.p
144007.25/19282.35	% SZS status Started for HL407789+4.p
144007.25/19282.35	% SZS status GaveUp for HL407789+4.p
144007.25/19282.35	eprover: CPU time limit exceeded, terminating
144007.25/19282.35	% SZS status Ended for HL407789+4.p
144007.95/19282.45	% SZS status Started for HL407780+5.p
144007.95/19282.45	% SZS status GaveUp for HL407780+5.p
144007.95/19282.45	eprover: CPU time limit exceeded, terminating
144007.95/19282.45	% SZS status Ended for HL407780+5.p
144032.72/19285.61	% SZS status Started for HL407790+4.p
144032.72/19285.61	% SZS status GaveUp for HL407790+4.p
144032.72/19285.61	eprover: CPU time limit exceeded, terminating
144032.72/19285.61	% SZS status Ended for HL407790+4.p
144033.50/19285.70	% SZS status Started for HL407781+5.p
144033.50/19285.70	% SZS status GaveUp for HL407781+5.p
144033.50/19285.70	eprover: CPU time limit exceeded, terminating
144033.50/19285.70	% SZS status Ended for HL407781+5.p
144057.39/19288.73	% SZS status Started for HL407791+4.p
144057.39/19288.73	% SZS status GaveUp for HL407791+4.p
144057.39/19288.73	eprover: CPU time limit exceeded, terminating
144057.39/19288.73	% SZS status Ended for HL407791+4.p
144068.95/19290.14	% SZS status Started for HL407782+5.p
144068.95/19290.14	% SZS status GaveUp for HL407782+5.p
144068.95/19290.14	eprover: CPU time limit exceeded, terminating
144068.95/19290.14	% SZS status Ended for HL407782+5.p
144089.88/19292.84	% SZS status Started for HL407789+5.p
144089.88/19292.84	% SZS status GaveUp for HL407789+5.p
144089.88/19292.84	eprover: CPU time limit exceeded, terminating
144089.88/19292.84	% SZS status Ended for HL407789+5.p
144093.69/19293.26	% SZS status Started for HL407792+4.p
144093.69/19293.26	% SZS status GaveUp for HL407792+4.p
144093.69/19293.26	eprover: CPU time limit exceeded, terminating
144093.69/19293.26	% SZS status Ended for HL407792+4.p
144101.55/19294.25	% SZS status Started for HL407783+5.p
144101.55/19294.25	% SZS status GaveUp for HL407783+5.p
144101.55/19294.25	eprover: CPU time limit exceeded, terminating
144101.55/19294.25	% SZS status Ended for HL407783+5.p
144117.23/19296.29	% SZS status Started for HL407793+4.p
144117.23/19296.29	% SZS status GaveUp for HL407793+4.p
144117.23/19296.29	eprover: CPU time limit exceeded, terminating
144117.23/19296.29	% SZS status Ended for HL407793+4.p
144137.52/19298.78	% SZS status Started for HL407785+5.p
144137.52/19298.78	% SZS status GaveUp for HL407785+5.p
144137.52/19298.78	eprover: CPU time limit exceeded, terminating
144137.52/19298.78	% SZS status Ended for HL407785+5.p
144141.91/19299.34	% SZS status Started for HL407795+4.p
144141.91/19299.34	% SZS status GaveUp for HL407795+4.p
144141.91/19299.34	eprover: CPU time limit exceeded, terminating
144141.91/19299.34	% SZS status Ended for HL407795+4.p
144162.48/19301.99	% SZS status Started for HL407786+5.p
144162.48/19301.99	% SZS status GaveUp for HL407786+5.p
144162.48/19301.99	eprover: CPU time limit exceeded, terminating
144162.48/19301.99	% SZS status Ended for HL407786+5.p
144165.59/19302.39	% SZS status Started for HL407796+4.p
144165.59/19302.39	% SZS status GaveUp for HL407796+4.p
144165.59/19302.39	eprover: CPU time limit exceeded, terminating
144165.59/19302.39	% SZS status Ended for HL407796+4.p
144183.67/19304.63	% SZS status Started for HL407787+5.p
144183.67/19304.63	% SZS status GaveUp for HL407787+5.p
144183.67/19304.63	eprover: CPU time limit exceeded, terminating
144183.67/19304.63	% SZS status Ended for HL407787+5.p
144189.89/19305.42	% SZS status Started for HL407797+4.p
144189.89/19305.42	% SZS status GaveUp for HL407797+4.p
144189.89/19305.42	eprover: CPU time limit exceeded, terminating
144189.89/19305.42	% SZS status Ended for HL407797+4.p
144213.89/19308.46	% SZS status Started for HL407798+4.p
144213.89/19308.46	% SZS status GaveUp for HL407798+4.p
144213.89/19308.46	eprover: CPU time limit exceeded, terminating
144213.89/19308.46	% SZS status Ended for HL407798+4.p
144238.72/19311.53	% SZS status Started for HL407790+5.p
144238.72/19311.53	% SZS status GaveUp for HL407790+5.p
144238.72/19311.53	eprover: CPU time limit exceeded, terminating
144238.72/19311.53	% SZS status Ended for HL407790+5.p
144262.45/19314.57	% SZS status Started for HL407799+4.p
144262.45/19314.57	% SZS status GaveUp for HL407799+4.p
144262.45/19314.57	eprover: CPU time limit exceeded, terminating
144262.45/19314.57	% SZS status Ended for HL407799+4.p
144265.12/19314.88	% SZS status Started for HL407791+5.p
144265.12/19314.88	% SZS status GaveUp for HL407791+5.p
144265.12/19314.88	eprover: CPU time limit exceeded, terminating
144265.12/19314.88	% SZS status Ended for HL407791+5.p
144289.77/19317.94	% SZS status Started for HL407800+4.p
144289.77/19317.94	% SZS status GaveUp for HL407800+4.p
144289.77/19317.94	eprover: CPU time limit exceeded, terminating
144289.77/19317.94	% SZS status Ended for HL407800+4.p
144297.08/19318.86	% SZS status Started for HL407792+5.p
144297.08/19318.86	% SZS status GaveUp for HL407792+5.p
144297.08/19318.86	eprover: CPU time limit exceeded, terminating
144297.08/19318.86	% SZS status Ended for HL407792+5.p
144309.06/19320.41	% SZS status Started for HL407793+5.p
144309.06/19320.41	% SZS status GaveUp for HL407793+5.p
144309.06/19320.41	eprover: CPU time limit exceeded, terminating
144309.06/19320.41	% SZS status Ended for HL407793+5.p
144321.17/19321.96	% SZS status Started for HL407801+4.p
144321.17/19321.96	% SZS status GaveUp for HL407801+4.p
144321.17/19321.96	eprover: CPU time limit exceeded, terminating
144321.17/19321.96	% SZS status Ended for HL407801+4.p
144344.81/19324.88	% SZS status Started for HL407795+5.p
144344.81/19324.88	% SZS status GaveUp for HL407795+5.p
144344.81/19324.88	eprover: CPU time limit exceeded, terminating
144344.81/19324.88	% SZS status Ended for HL407795+5.p
144346.16/19325.10	% SZS status Started for HL407802+4.p
144346.16/19325.10	% SZS status GaveUp for HL407802+4.p
144346.16/19325.10	eprover: CPU time limit exceeded, terminating
144346.16/19325.10	% SZS status Ended for HL407802+4.p
144371.11/19327.91	% SZS status Started for HL407796+5.p
144371.11/19327.91	% SZS status GaveUp for HL407796+5.p
144371.11/19327.91	eprover: CPU time limit exceeded, terminating
144371.11/19327.91	% SZS status Ended for HL407796+5.p
144372.94/19328.14	% SZS status Started for HL407803+4.p
144372.94/19328.14	% SZS status GaveUp for HL407803+4.p
144372.94/19328.14	eprover: CPU time limit exceeded, terminating
144372.94/19328.14	% SZS status Ended for HL407803+4.p
144395.03/19330.91	% SZS status Started for HL407797+5.p
144395.03/19330.91	% SZS status GaveUp for HL407797+5.p
144395.03/19330.91	eprover: CPU time limit exceeded, terminating
144395.03/19330.91	% SZS status Ended for HL407797+5.p
144396.92/19331.17	% SZS status Started for HL407805+4.p
144396.92/19331.17	% SZS status GaveUp for HL407805+4.p
144396.92/19331.17	eprover: CPU time limit exceeded, terminating
144396.92/19331.17	% SZS status Ended for HL407805+4.p
144421.66/19334.22	% SZS status Started for HL407807+4.p
144421.66/19334.22	% SZS status GaveUp for HL407807+4.p
144421.66/19334.22	eprover: CPU time limit exceeded, terminating
144421.66/19334.22	% SZS status Ended for HL407807+4.p
144422.58/19334.37	% SZS status Started for HL407798+5.p
144422.58/19334.37	% SZS status GaveUp for HL407798+5.p
144422.58/19334.37	eprover: CPU time limit exceeded, terminating
144422.58/19334.37	% SZS status Ended for HL407798+5.p
144446.72/19337.42	% SZS status Started for HL407808+4.p
144446.72/19337.42	% SZS status GaveUp for HL407808+4.p
144446.72/19337.42	eprover: CPU time limit exceeded, terminating
144446.72/19337.42	% SZS status Ended for HL407808+4.p
144473.86/19340.81	% SZS status Started for HL407799+5.p
144473.86/19340.81	% SZS status GaveUp for HL407799+5.p
144473.86/19340.81	eprover: CPU time limit exceeded, terminating
144473.86/19340.81	% SZS status Ended for HL407799+5.p
144497.16/19343.85	% SZS status Started for HL407800+5.p
144497.16/19343.85	% SZS status GaveUp for HL407800+5.p
144497.16/19343.85	eprover: CPU time limit exceeded, terminating
144497.16/19343.85	% SZS status Ended for HL407800+5.p
144498.44/19343.90	% SZS status Started for HL407809+4.p
144498.44/19343.90	% SZS status GaveUp for HL407809+4.p
144498.44/19343.90	eprover: CPU time limit exceeded, terminating
144498.44/19343.90	% SZS status Ended for HL407809+4.p
144517.78/19346.38	% SZS status Started for HL407801+5.p
144517.78/19346.38	% SZS status GaveUp for HL407801+5.p
144517.78/19346.38	eprover: CPU time limit exceeded, terminating
144517.78/19346.38	% SZS status Ended for HL407801+5.p
144522.61/19346.94	% SZS status Started for HL407810+4.p
144522.61/19346.94	% SZS status GaveUp for HL407810+4.p
144522.61/19346.94	eprover: CPU time limit exceeded, terminating
144522.61/19346.94	% SZS status Ended for HL407810+4.p
144547.06/19350.01	% SZS status Started for HL407812+4.p
144547.06/19350.01	% SZS status GaveUp for HL407812+4.p
144547.06/19350.01	eprover: CPU time limit exceeded, terminating
144547.06/19350.01	% SZS status Ended for HL407812+4.p
144554.05/19350.91	% SZS status Started for HL407802+5.p
144554.05/19350.91	% SZS status GaveUp for HL407802+5.p
144554.05/19350.91	eprover: CPU time limit exceeded, terminating
144554.05/19350.91	% SZS status Ended for HL407802+5.p
144576.75/19353.76	% SZS status Started for HL407803+5.p
144576.75/19353.76	% SZS status GaveUp for HL407803+5.p
144576.75/19353.76	eprover: CPU time limit exceeded, terminating
144576.75/19353.76	% SZS status Ended for HL407803+5.p
144578.28/19353.95	% SZS status Started for HL407813+4.p
144578.28/19353.95	% SZS status GaveUp for HL407813+4.p
144578.28/19353.95	eprover: CPU time limit exceeded, terminating
144578.28/19353.95	% SZS status Ended for HL407813+4.p
144602.27/19356.98	% SZS status Started for HL407814+4.p
144602.27/19356.98	% SZS status GaveUp for HL407814+4.p
144602.27/19356.98	eprover: CPU time limit exceeded, terminating
144602.27/19356.98	% SZS status Ended for HL407814+4.p
144603.62/19357.18	% SZS status Started for HL407805+5.p
144603.62/19357.18	% SZS status GaveUp for HL407805+5.p
144603.62/19357.18	eprover: CPU time limit exceeded, terminating
144603.62/19357.18	% SZS status Ended for HL407805+5.p
144627.62/19360.19	% SZS status Started for HL407807+5.p
144627.62/19360.19	% SZS status GaveUp for HL407807+5.p
144627.62/19360.19	eprover: CPU time limit exceeded, terminating
144627.62/19360.19	% SZS status Ended for HL407807+5.p
144628.39/19360.27	% SZS status Started for HL407815+4.p
144628.39/19360.27	% SZS status GaveUp for HL407815+4.p
144628.39/19360.27	eprover: CPU time limit exceeded, terminating
144628.39/19360.27	% SZS status Ended for HL407815+4.p
144652.28/19363.28	% SZS status Started for HL407808+5.p
144652.28/19363.28	% SZS status GaveUp for HL407808+5.p
144652.28/19363.28	eprover: CPU time limit exceeded, terminating
144652.28/19363.28	% SZS status Ended for HL407808+5.p
144652.28/19363.31	% SZS status Started for HL407816+4.p
144652.28/19363.31	% SZS status GaveUp for HL407816+4.p
144652.28/19363.31	eprover: CPU time limit exceeded, terminating
144652.28/19363.31	% SZS status Ended for HL407816+4.p
144676.94/19366.40	% SZS status Started for HL407817+4.p
144676.94/19366.40	% SZS status GaveUp for HL407817+4.p
144676.94/19366.40	eprover: CPU time limit exceeded, terminating
144676.94/19366.40	% SZS status Ended for HL407817+4.p
144684.73/19367.33	% SZS status Started for HL407814+5.p
144684.73/19367.33	% SZS status GaveUp for HL407814+5.p
144684.73/19367.33	eprover: CPU time limit exceeded, terminating
144684.73/19367.33	% SZS status Ended for HL407814+5.p
144704.92/19369.91	% SZS status Started for HL407809+5.p
144704.92/19369.91	% SZS status GaveUp for HL407809+5.p
144704.92/19369.91	eprover: CPU time limit exceeded, terminating
144704.92/19369.91	% SZS status Ended for HL407809+5.p
144709.58/19370.48	% SZS status Started for HL407818+4.p
144709.58/19370.48	% SZS status GaveUp for HL407818+4.p
144709.58/19370.48	eprover: CPU time limit exceeded, terminating
144709.58/19370.48	% SZS status Ended for HL407818+4.p
144727.09/19372.75	% SZS status Started for HL407810+5.p
144727.09/19372.75	% SZS status GaveUp for HL407810+5.p
144727.09/19372.75	eprover: CPU time limit exceeded, terminating
144727.09/19372.75	% SZS status Ended for HL407810+5.p
144733.98/19373.53	% SZS status Started for HL407820+4.p
144733.98/19373.53	% SZS status GaveUp for HL407820+4.p
144733.98/19373.53	eprover: CPU time limit exceeded, terminating
144733.98/19373.53	% SZS status Ended for HL407820+4.p
144752.59/19375.92	% SZS status Started for HL407812+5.p
144752.59/19375.92	% SZS status GaveUp for HL407812+5.p
144752.59/19375.92	eprover: CPU time limit exceeded, terminating
144752.59/19375.92	% SZS status Ended for HL407812+5.p
144758.12/19376.56	% SZS status Started for HL407821+4.p
144758.12/19376.56	% SZS status GaveUp for HL407821+4.p
144758.12/19376.56	eprover: CPU time limit exceeded, terminating
144758.12/19376.56	% SZS status Ended for HL407821+4.p
144781.86/19379.59	% SZS status Started for HL407822+4.p
144781.86/19379.59	% SZS status GaveUp for HL407822+4.p
144781.86/19379.59	eprover: CPU time limit exceeded, terminating
144781.86/19379.59	% SZS status Ended for HL407822+4.p
144781.86/19379.61	% SZS status Started for HL407813+5.p
144781.86/19379.61	% SZS status GaveUp for HL407813+5.p
144781.86/19379.61	eprover: CPU time limit exceeded, terminating
144781.86/19379.61	% SZS status Ended for HL407813+5.p
144806.36/19382.65	% SZS status Started for HL407825+4.p
144806.36/19382.65	% SZS status GaveUp for HL407825+4.p
144806.36/19382.65	eprover: CPU time limit exceeded, terminating
144806.36/19382.65	% SZS status Ended for HL407825+4.p
144833.72/19386.08	% SZS status Started for HL407815+5.p
144833.72/19386.08	% SZS status GaveUp for HL407815+5.p
144833.72/19386.08	eprover: CPU time limit exceeded, terminating
144833.72/19386.08	% SZS status Ended for HL407815+5.p
144858.47/19389.23	% SZS status Started for HL407826+4.p
144858.47/19389.23	% SZS status GaveUp for HL407826+4.p
144858.47/19389.23	eprover: CPU time limit exceeded, terminating
144858.47/19389.23	% SZS status Ended for HL407826+4.p
144859.38/19389.35	% SZS status Started for HL407816+5.p
144859.38/19389.35	% SZS status GaveUp for HL407816+5.p
144859.38/19389.35	eprover: CPU time limit exceeded, terminating
144859.38/19389.35	% SZS status Ended for HL407816+5.p
144883.34/19392.39	% SZS status Started for HL407827+4.p
144883.34/19392.39	% SZS status GaveUp for HL407827+4.p
144883.34/19392.39	eprover: CPU time limit exceeded, terminating
144883.34/19392.39	% SZS status Ended for HL407827+4.p
144884.94/19392.60	% SZS status Started for HL407817+5.p
144884.94/19392.60	% SZS status GaveUp for HL407817+5.p
144884.94/19392.60	eprover: CPU time limit exceeded, terminating
144884.94/19392.60	% SZS status Ended for HL407817+5.p
144909.47/19395.66	% SZS status Started for HL407828+4.p
144909.47/19395.66	% SZS status GaveUp for HL407828+4.p
144909.47/19395.66	eprover: CPU time limit exceeded, terminating
144909.47/19395.66	% SZS status Ended for HL407828+4.p
144911.22/19395.88	% SZS status Started for HL407818+5.p
144911.22/19395.88	% SZS status GaveUp for HL407818+5.p
144911.22/19395.88	eprover: CPU time limit exceeded, terminating
144911.22/19395.88	% SZS status Ended for HL407818+5.p
144936.09/19399.02	% SZS status Started for HL407829+4.p
144936.09/19399.02	% SZS status GaveUp for HL407829+4.p
144936.09/19399.02	eprover: CPU time limit exceeded, terminating
144936.09/19399.02	% SZS status Ended for HL407829+4.p
144936.09/19399.04	% SZS status Started for HL407820+5.p
144936.09/19399.04	% SZS status GaveUp for HL407820+5.p
144936.09/19399.04	eprover: CPU time limit exceeded, terminating
144936.09/19399.04	% SZS status Ended for HL407820+5.p
144962.41/19401.99	% SZS status Started for HL407821+5.p
144962.41/19401.99	% SZS status GaveUp for HL407821+5.p
144962.41/19401.99	eprover: CPU time limit exceeded, terminating
144962.41/19401.99	% SZS status Ended for HL407821+5.p
144963.09/19402.09	% SZS status Started for HL407831+4.p
144963.09/19402.09	% SZS status GaveUp for HL407831+4.p
144963.09/19402.09	eprover: CPU time limit exceeded, terminating
144963.09/19402.09	% SZS status Ended for HL407831+4.p
144987.69/19405.16	% SZS status Started for HL407832+4.p
144987.69/19405.16	% SZS status GaveUp for HL407832+4.p
144987.69/19405.16	eprover: CPU time limit exceeded, terminating
144987.69/19405.16	% SZS status Ended for HL407832+4.p
144991.73/19405.67	% SZS status Started for HL407822+5.p
144991.73/19405.67	% SZS status GaveUp for HL407822+5.p
144991.73/19405.67	eprover: CPU time limit exceeded, terminating
144991.73/19405.67	% SZS status Ended for HL407822+5.p
145015.64/19408.66	% SZS status Started for HL407825+5.p
145015.64/19408.66	% SZS status GaveUp for HL407825+5.p
145015.64/19408.66	eprover: CPU time limit exceeded, terminating
145015.64/19408.66	% SZS status Ended for HL407825+5.p
145016.02/19408.71	% SZS status Started for HL407833+4.p
145016.02/19408.71	% SZS status GaveUp for HL407833+4.p
145016.02/19408.71	eprover: CPU time limit exceeded, terminating
145016.02/19408.71	% SZS status Ended for HL407833+4.p
145039.81/19411.75	% SZS status Started for HL407834+4.p
145039.81/19411.75	% SZS status GaveUp for HL407834+4.p
145039.81/19411.75	eprover: CPU time limit exceeded, terminating
145039.81/19411.75	% SZS status Ended for HL407834+4.p
145043.50/19412.19	% SZS status Started for HL407831+5.p
145043.50/19412.19	% SZS status GaveUp for HL407831+5.p
145043.50/19412.19	eprover: CPU time limit exceeded, terminating
145043.50/19412.19	% SZS status Ended for HL407831+5.p
145067.00/19415.16	% SZS status Started for HL407826+5.p
145067.00/19415.16	% SZS status GaveUp for HL407826+5.p
145067.00/19415.16	eprover: CPU time limit exceeded, terminating
145067.00/19415.16	% SZS status Ended for HL407826+5.p
145067.31/19415.23	% SZS status Started for HL407835+4.p
145067.31/19415.23	% SZS status GaveUp for HL407835+4.p
145067.31/19415.23	eprover: CPU time limit exceeded, terminating
145067.31/19415.23	% SZS status Ended for HL407835+4.p
145091.62/19418.27	% SZS status Started for HL407836+4.p
145091.62/19418.27	% SZS status GaveUp for HL407836+4.p
145091.62/19418.27	eprover: CPU time limit exceeded, terminating
145091.62/19418.27	% SZS status Ended for HL407836+4.p
145093.22/19418.50	% SZS status Started for HL407827+5.p
145093.22/19418.50	% SZS status GaveUp for HL407827+5.p
145093.22/19418.50	eprover: CPU time limit exceeded, terminating
145093.22/19418.50	% SZS status Ended for HL407827+5.p
145117.41/19421.54	% SZS status Started for HL407837+4.p
145117.41/19421.54	% SZS status GaveUp for HL407837+4.p
145117.41/19421.54	eprover: CPU time limit exceeded, terminating
145117.41/19421.54	% SZS status Ended for HL407837+4.p
145120.30/19421.92	% SZS status Started for HL407828+5.p
145120.30/19421.92	% SZS status GaveUp for HL407828+5.p
145120.30/19421.92	eprover: CPU time limit exceeded, terminating
145120.30/19421.92	% SZS status Ended for HL407828+5.p
145144.84/19424.99	% SZS status Started for HL407829+5.p
145144.84/19424.99	% SZS status GaveUp for HL407829+5.p
145144.84/19424.99	eprover: CPU time limit exceeded, terminating
145144.84/19424.99	% SZS status Ended for HL407829+5.p
145145.44/19425.05	% SZS status Started for HL407839+4.p
145145.44/19425.05	% SZS status GaveUp for HL407839+4.p
145145.44/19425.05	eprover: CPU time limit exceeded, terminating
145145.44/19425.05	% SZS status Ended for HL407839+4.p
145169.73/19428.11	% SZS status Started for HL407840+4.p
145169.73/19428.11	% SZS status GaveUp for HL407840+4.p
145169.73/19428.11	eprover: CPU time limit exceeded, terminating
145169.73/19428.11	% SZS status Ended for HL407840+4.p
145195.67/19431.42	% SZS status Started for HL407832+5.p
145195.67/19431.42	% SZS status GaveUp for HL407832+5.p
145195.67/19431.42	eprover: CPU time limit exceeded, terminating
145195.67/19431.42	% SZS status Ended for HL407832+5.p
145220.02/19434.47	% SZS status Started for HL407841+4.p
145220.02/19434.47	% SZS status GaveUp for HL407841+4.p
145220.02/19434.47	eprover: CPU time limit exceeded, terminating
145220.02/19434.47	% SZS status Ended for HL407841+4.p
145220.97/19434.65	% SZS status Started for HL407833+5.p
145220.97/19434.65	% SZS status GaveUp for HL407833+5.p
145220.97/19434.65	eprover: CPU time limit exceeded, terminating
145220.97/19434.65	% SZS status Ended for HL407833+5.p
145245.55/19437.68	% SZS status Started for HL407834+5.p
145245.55/19437.68	% SZS status GaveUp for HL407834+5.p
145245.55/19437.68	eprover: CPU time limit exceeded, terminating
145245.55/19437.68	% SZS status Ended for HL407834+5.p
145245.55/19437.69	% SZS status Started for HL407844+4.p
145245.55/19437.69	% SZS status GaveUp for HL407844+4.p
145245.55/19437.69	eprover: CPU time limit exceeded, terminating
145245.55/19437.69	% SZS status Ended for HL407844+4.p
145278.02/19438.57	% SZS status Started for HL407840+5.p
145278.02/19438.57	% SZS status GaveUp for HL407840+5.p
145278.02/19438.57	eprover: CPU time limit exceeded, terminating
145278.02/19438.57	% SZS status Ended for HL407840+5.p
145295.00/19440.71	% SZS status Started for HL407845+4.p
145295.00/19440.71	% SZS status GaveUp for HL407845+4.p
145295.00/19440.71	eprover: CPU time limit exceeded, terminating
145295.00/19440.71	% SZS status Ended for HL407845+4.p
145299.22/19441.22	% SZS status Started for HL407835+5.p
145299.22/19441.22	% SZS status GaveUp for HL407835+5.p
145299.22/19441.22	eprover: CPU time limit exceeded, terminating
145299.22/19441.22	% SZS status Ended for HL407835+5.p
145319.14/19443.75	% SZS status Started for HL407846+4.p
145319.14/19443.75	% SZS status GaveUp for HL407846+4.p
145319.14/19443.75	eprover: CPU time limit exceeded, terminating
145319.14/19443.75	% SZS status Ended for HL407846+4.p
145325.50/19444.52	% SZS status Started for HL407836+5.p
145325.50/19444.52	% SZS status GaveUp for HL407836+5.p
145325.50/19444.52	eprover: CPU time limit exceeded, terminating
145325.50/19444.52	% SZS status Ended for HL407836+5.p
145343.45/19446.80	% SZS status Started for HL407847+4.p
145343.45/19446.80	% SZS status GaveUp for HL407847+4.p
145343.45/19446.80	eprover: CPU time limit exceeded, terminating
145343.45/19446.80	% SZS status Ended for HL407847+4.p
145349.64/19447.54	% SZS status Started for HL407837+5.p
145349.64/19447.54	% SZS status GaveUp for HL407837+5.p
145349.64/19447.54	eprover: CPU time limit exceeded, terminating
145349.64/19447.54	% SZS status Ended for HL407837+5.p
145352.08/19447.90	% SZS status Started for HL407844+5.p
145352.08/19447.90	% SZS status GaveUp for HL407844+5.p
145352.08/19447.90	eprover: CPU time limit exceeded, terminating
145352.08/19447.90	% SZS status Ended for HL407844+5.p
145368.53/19449.90	% SZS status Started for HL407849+4.p
145368.53/19449.90	% SZS status GaveUp for HL407849+4.p
145368.53/19449.90	eprover: CPU time limit exceeded, terminating
145368.53/19449.90	% SZS status Ended for HL407849+4.p
145376.89/19450.94	% SZS status Started for HL407850+4.p
145376.89/19450.94	% SZS status GaveUp for HL407850+4.p
145376.89/19450.94	eprover: CPU time limit exceeded, terminating
145376.89/19450.94	% SZS status Ended for HL407850+4.p
145376.89/19450.97	% SZS status Started for HL407839+5.p
145376.89/19450.97	% SZS status GaveUp for HL407839+5.p
145376.89/19450.97	eprover: CPU time limit exceeded, terminating
145376.89/19450.97	% SZS status Ended for HL407839+5.p
145401.25/19454.03	% SZS status Started for HL407851+4.p
145401.25/19454.03	% SZS status GaveUp for HL407851+4.p
145401.25/19454.03	eprover: CPU time limit exceeded, terminating
145401.25/19454.03	% SZS status Ended for HL407851+4.p
145425.22/19457.07	% SZS status Started for HL407854+4.p
145425.22/19457.07	% SZS status GaveUp for HL407854+4.p
145425.22/19457.07	eprover: CPU time limit exceeded, terminating
145425.22/19457.07	% SZS status Ended for HL407854+4.p
145452.19/19460.41	% SZS status Started for HL407841+5.p
145452.19/19460.41	% SZS status GaveUp for HL407841+5.p
145452.19/19460.41	eprover: CPU time limit exceeded, terminating
145452.19/19460.41	% SZS status Ended for HL407841+5.p
145476.22/19463.44	% SZS status Started for HL407855+4.p
145476.22/19463.44	% SZS status GaveUp for HL407855+4.p
145476.22/19463.44	eprover: CPU time limit exceeded, terminating
145476.22/19463.44	% SZS status Ended for HL407855+4.p
145486.44/19464.74	% SZS status Started for HL407845+5.p
145486.44/19464.74	% SZS status GaveUp for HL407845+5.p
145486.44/19464.74	eprover: CPU time limit exceeded, terminating
145486.44/19464.74	% SZS status Ended for HL407845+5.p
145505.19/19467.17	% SZS status Started for HL407846+5.p
145505.19/19467.17	% SZS status GaveUp for HL407846+5.p
145505.19/19467.17	eprover: CPU time limit exceeded, terminating
145505.19/19467.17	% SZS status Ended for HL407846+5.p
145510.16/19467.78	% SZS status Started for HL407859+4.p
145510.16/19467.78	% SZS status GaveUp for HL407859+4.p
145510.16/19467.78	eprover: CPU time limit exceeded, terminating
145510.16/19467.78	% SZS status Ended for HL407859+4.p
145531.55/19470.44	% SZS status Started for HL407847+5.p
145531.55/19470.44	% SZS status GaveUp for HL407847+5.p
145531.55/19470.44	eprover: CPU time limit exceeded, terminating
145531.55/19470.44	% SZS status Ended for HL407847+5.p
145534.95/19470.83	% SZS status Started for HL407860+4.p
145534.95/19470.83	% SZS status GaveUp for HL407860+4.p
145534.95/19470.83	eprover: CPU time limit exceeded, terminating
145534.95/19470.83	% SZS status Ended for HL407860+4.p
145556.06/19473.58	% SZS status Started for HL407849+5.p
145556.06/19473.58	% SZS status GaveUp for HL407849+5.p
145556.06/19473.58	eprover: CPU time limit exceeded, terminating
145556.06/19473.58	% SZS status Ended for HL407849+5.p
145558.55/19473.86	% SZS status Started for HL407861+4.p
145558.55/19473.86	% SZS status GaveUp for HL407861+4.p
145558.55/19473.86	eprover: CPU time limit exceeded, terminating
145558.55/19473.86	% SZS status Ended for HL407861+4.p
145577.27/19476.16	% SZS status Started for HL407850+5.p
145577.27/19476.16	% SZS status GaveUp for HL407850+5.p
145577.27/19476.16	eprover: CPU time limit exceeded, terminating
145577.27/19476.16	% SZS status Ended for HL407850+5.p
145582.66/19476.87	% SZS status Started for HL407851+5.p
145582.66/19476.87	% SZS status GaveUp for HL407851+5.p
145582.66/19476.87	eprover: CPU time limit exceeded, terminating
145582.66/19476.87	% SZS status Ended for HL407851+5.p
145583.45/19476.97	% SZS status Started for HL407862+4.p
145583.45/19476.97	% SZS status GaveUp for HL407862+4.p
145583.45/19476.97	eprover: CPU time limit exceeded, terminating
145583.45/19476.97	% SZS status Ended for HL407862+4.p
145607.09/19479.91	% SZS status Started for HL407863+4.p
145607.09/19479.91	% SZS status GaveUp for HL407863+4.p
145607.09/19479.91	eprover: CPU time limit exceeded, terminating
145607.09/19479.91	% SZS status Ended for HL407863+4.p
145631.23/19482.98	% SZS status Started for HL407864+4.p
145631.23/19482.98	% SZS status GaveUp for HL407864+4.p
145631.23/19482.98	eprover: CPU time limit exceeded, terminating
145631.23/19482.98	% SZS status Ended for HL407864+4.p
145632.28/19483.08	% SZS status Started for HL407854+5.p
145632.28/19483.08	% SZS status GaveUp for HL407854+5.p
145632.28/19483.08	eprover: CPU time limit exceeded, terminating
145632.28/19483.08	% SZS status Ended for HL407854+5.p
145655.81/19486.12	% SZS status Started for HL407865+4.p
145655.81/19486.12	% SZS status GaveUp for HL407865+4.p
145655.81/19486.12	eprover: CPU time limit exceeded, terminating
145655.81/19486.12	% SZS status Ended for HL407865+4.p
145682.44/19489.41	% SZS status Started for HL407855+5.p
145682.44/19489.41	% SZS status GaveUp for HL407855+5.p
145682.44/19489.41	eprover: CPU time limit exceeded, terminating
145682.44/19489.41	% SZS status Ended for HL407855+5.p
145706.47/19492.46	% SZS status Started for HL407866+4.p
145706.47/19492.46	% SZS status GaveUp for HL407866+4.p
145706.47/19492.46	eprover: CPU time limit exceeded, terminating
145706.47/19492.46	% SZS status Ended for HL407866+4.p
145711.55/19493.10	% SZS status Started for HL407859+5.p
145711.55/19493.10	% SZS status GaveUp for HL407859+5.p
145711.55/19493.10	eprover: CPU time limit exceeded, terminating
145711.55/19493.10	% SZS status Ended for HL407859+5.p
145717.95/19493.88	% SZS status Started for HL407864+5.p
145717.95/19493.88	% SZS status GaveUp for HL407864+5.p
145717.95/19493.88	eprover: CPU time limit exceeded, terminating
145717.95/19493.88	% SZS status Ended for HL407864+5.p
145736.11/19496.19	% SZS status Started for HL407867+4.p
145736.11/19496.19	% SZS status GaveUp for HL407867+4.p
145736.11/19496.19	eprover: CPU time limit exceeded, terminating
145736.11/19496.19	% SZS status Ended for HL407867+4.p
145737.23/19496.32	% SZS status Started for HL407860+5.p
145737.23/19496.32	% SZS status GaveUp for HL407860+5.p
145737.23/19496.32	eprover: CPU time limit exceeded, terminating
145737.23/19496.32	% SZS status Ended for HL407860+5.p
145760.58/19499.23	% SZS status Started for HL407868+4.p
145760.58/19499.23	% SZS status GaveUp for HL407868+4.p
145760.58/19499.23	eprover: CPU time limit exceeded, terminating
145760.58/19499.23	% SZS status Ended for HL407868+4.p
145762.95/19499.53	% SZS status Started for HL407861+5.p
145762.95/19499.53	% SZS status GaveUp for HL407861+5.p
145762.95/19499.53	eprover: CPU time limit exceeded, terminating
145762.95/19499.53	% SZS status Ended for HL407861+5.p
145784.41/19502.28	% SZS status Started for HL407869+4.p
145784.41/19502.28	% SZS status GaveUp for HL407869+4.p
145784.41/19502.28	eprover: CPU time limit exceeded, terminating
145784.41/19502.28	% SZS status Ended for HL407869+4.p
145785.55/19502.44	% SZS status Started for HL407862+5.p
145785.55/19502.44	% SZS status GaveUp for HL407862+5.p
145785.55/19502.44	eprover: CPU time limit exceeded, terminating
145785.55/19502.44	% SZS status Ended for HL407862+5.p
145789.16/19502.93	% SZS status Started for HL407863+5.p
145789.16/19502.93	% SZS status GaveUp for HL407863+5.p
145789.16/19502.93	eprover: CPU time limit exceeded, terminating
145789.16/19502.93	% SZS status Ended for HL407863+5.p
145808.59/19505.33	% SZS status Started for HL407870+4.p
145808.59/19505.33	% SZS status GaveUp for HL407870+4.p
145808.59/19505.33	eprover: CPU time limit exceeded, terminating
145808.59/19505.33	% SZS status Ended for HL407870+4.p
145813.61/19505.97	% SZS status Started for HL407871+4.p
145813.61/19505.97	% SZS status GaveUp for HL407871+4.p
145813.61/19505.97	eprover: CPU time limit exceeded, terminating
145813.61/19505.97	% SZS status Ended for HL407871+4.p
145820.14/19506.78	% SZS status Started for HL407868+5.p
145820.14/19506.78	% SZS status GaveUp for HL407868+5.p
145820.14/19506.78	eprover: CPU time limit exceeded, terminating
145820.14/19506.78	% SZS status Ended for HL407868+5.p
145838.88/19509.09	% SZS status Started for HL407873+4.p
145838.88/19509.09	% SZS status GaveUp for HL407873+4.p
145838.88/19509.09	eprover: CPU time limit exceeded, terminating
145838.88/19509.09	% SZS status Ended for HL407873+4.p
145862.98/19512.14	% SZS status Started for HL407874+4.p
145862.98/19512.14	% SZS status GaveUp for HL407874+4.p
145862.98/19512.14	eprover: CPU time limit exceeded, terminating
145862.98/19512.14	% SZS status Ended for HL407874+4.p
145862.98/19512.19	% SZS status Started for HL407865+5.p
145862.98/19512.19	% SZS status GaveUp for HL407865+5.p
145862.98/19512.19	eprover: CPU time limit exceeded, terminating
145862.98/19512.19	% SZS status Ended for HL407865+5.p
145887.31/19515.24	% SZS status Started for HL407875+4.p
145887.31/19515.24	% SZS status GaveUp for HL407875+4.p
145887.31/19515.24	eprover: CPU time limit exceeded, terminating
145887.31/19515.24	% SZS status Ended for HL407875+4.p
145913.00/19518.48	% SZS status Started for HL407866+5.p
145913.00/19518.48	% SZS status GaveUp for HL407866+5.p
145913.00/19518.48	eprover: CPU time limit exceeded, terminating
145913.00/19518.48	% SZS status Ended for HL407866+5.p
145924.58/19519.90	% SZS status Started for HL407867+5.p
145924.58/19519.90	% SZS status GaveUp for HL407867+5.p
145924.58/19519.90	eprover: CPU time limit exceeded, terminating
145924.58/19519.90	% SZS status Ended for HL407867+5.p
145937.72/19521.57	% SZS status Started for HL407877+4.p
145937.72/19521.57	% SZS status GaveUp for HL407877+4.p
145937.72/19521.57	eprover: CPU time limit exceeded, terminating
145937.72/19521.57	% SZS status Ended for HL407877+4.p
145961.48/19524.60	% SZS status Started for HL407878+4.p
145961.48/19524.60	% SZS status GaveUp for HL407878+4.p
145961.48/19524.60	eprover: CPU time limit exceeded, terminating
145961.48/19524.60	% SZS status Ended for HL407878+4.p
145970.41/19525.74	% SZS status Started for HL407869+5.p
145970.41/19525.74	% SZS status GaveUp for HL407869+5.p
145970.41/19525.74	eprover: CPU time limit exceeded, terminating
145970.41/19525.74	% SZS status Ended for HL407869+5.p
145993.64/19528.62	% SZS status Started for HL407870+5.p
145993.64/19528.62	% SZS status GaveUp for HL407870+5.p
145993.64/19528.62	eprover: CPU time limit exceeded, terminating
145993.64/19528.62	% SZS status Ended for HL407870+5.p
145994.83/19528.81	% SZS status Started for HL407879+4.p
145994.83/19528.81	% SZS status GaveUp for HL407879+4.p
145994.83/19528.81	eprover: CPU time limit exceeded, terminating
145994.83/19528.81	% SZS status Ended for HL407879+4.p
146016.59/19531.51	% SZS status Started for HL407871+5.p
146016.59/19531.51	% SZS status GaveUp for HL407871+5.p
146016.59/19531.51	eprover: CPU time limit exceeded, terminating
146016.59/19531.51	% SZS status Ended for HL407871+5.p
146019.09/19531.87	% SZS status Started for HL407880+4.p
146019.09/19531.87	% SZS status GaveUp for HL407880+4.p
146019.09/19531.87	eprover: CPU time limit exceeded, terminating
146019.09/19531.87	% SZS status Ended for HL407880+4.p
146027.55/19532.92	% SZS status Started for HL407873+5.p
146027.55/19532.92	% SZS status GaveUp for HL407873+5.p
146027.55/19532.92	eprover: CPU time limit exceeded, terminating
146027.55/19532.92	% SZS status Ended for HL407873+5.p
146043.86/19534.94	% SZS status Started for HL407881+4.p
146043.86/19534.94	% SZS status GaveUp for HL407881+4.p
146043.86/19534.94	eprover: CPU time limit exceeded, terminating
146043.86/19534.94	% SZS status Ended for HL407881+4.p
146067.72/19537.99	% SZS status Started for HL407882+4.p
146067.72/19537.99	% SZS status GaveUp for HL407882+4.p
146067.72/19537.99	eprover: CPU time limit exceeded, terminating
146067.72/19537.99	% SZS status Ended for HL407882+4.p
146067.95/19538.02	% SZS status Started for HL407874+5.p
146067.95/19538.02	% SZS status GaveUp for HL407874+5.p
146067.95/19538.02	eprover: CPU time limit exceeded, terminating
146067.95/19538.02	% SZS status Ended for HL407874+5.p
146077.83/19539.22	% SZS status Started for HL407879+5.p
146077.83/19539.22	% SZS status GaveUp for HL407879+5.p
146077.83/19539.22	eprover: CPU time limit exceeded, terminating
146077.83/19539.22	% SZS status Ended for HL407879+5.p
146093.20/19541.20	% SZS status Started for HL407883+4.p
146093.20/19541.20	% SZS status GaveUp for HL407883+4.p
146093.20/19541.20	eprover: CPU time limit exceeded, terminating
146093.20/19541.20	% SZS status Ended for HL407883+4.p
146093.61/19541.25	% SZS status Started for HL407875+5.p
146093.61/19541.25	% SZS status GaveUp for HL407875+5.p
146093.61/19541.25	eprover: CPU time limit exceeded, terminating
146093.61/19541.25	% SZS status Ended for HL407875+5.p
146116.69/19544.24	% SZS status Started for HL407884+4.p
146116.69/19544.24	% SZS status GaveUp for HL407884+4.p
146116.69/19544.24	eprover: CPU time limit exceeded, terminating
146116.69/19544.24	% SZS status Ended for HL407884+4.p
146131.67/19546.00	% SZS status Started for HL407877+5.p
146131.67/19546.00	% SZS status GaveUp for HL407877+5.p
146131.67/19546.00	eprover: CPU time limit exceeded, terminating
146131.67/19546.00	% SZS status Ended for HL407877+5.p
146141.53/19547.27	% SZS status Started for HL407885+4.p
146141.53/19547.27	% SZS status GaveUp for HL407885+4.p
146141.53/19547.27	eprover: CPU time limit exceeded, terminating
146141.53/19547.27	% SZS status Ended for HL407885+4.p
146165.67/19550.31	% SZS status Started for HL407886+4.p
146165.67/19550.31	% SZS status GaveUp for HL407886+4.p
146165.67/19550.31	eprover: CPU time limit exceeded, terminating
146165.67/19550.31	% SZS status Ended for HL407886+4.p
146168.53/19550.69	% SZS status Started for HL407878+5.p
146168.53/19550.69	% SZS status GaveUp for HL407878+5.p
146168.53/19550.69	eprover: CPU time limit exceeded, terminating
146168.53/19550.69	% SZS status Ended for HL407878+5.p
146192.55/19553.72	% SZS status Started for HL407887+4.p
146192.55/19553.72	% SZS status GaveUp for HL407887+4.p
146192.55/19553.72	eprover: CPU time limit exceeded, terminating
146192.55/19553.72	% SZS status Ended for HL407887+4.p
146224.81/19557.77	% SZS status Started for HL407880+5.p
146224.81/19557.77	% SZS status GaveUp for HL407880+5.p
146224.81/19557.77	eprover: CPU time limit exceeded, terminating
146224.81/19557.77	% SZS status Ended for HL407880+5.p
146235.69/19559.13	% SZS status Started for HL407881+5.p
146235.69/19559.13	% SZS status GaveUp for HL407881+5.p
146235.69/19559.13	eprover: CPU time limit exceeded, terminating
146235.69/19559.13	% SZS status Ended for HL407881+5.p
146248.81/19560.82	% SZS status Started for HL407888+4.p
146248.81/19560.82	% SZS status GaveUp for HL407888+4.p
146248.81/19560.82	eprover: CPU time limit exceeded, terminating
146248.81/19560.82	% SZS status Ended for HL407888+4.p
146273.34/19563.86	% SZS status Started for HL407889+4.p
146273.34/19563.86	% SZS status GaveUp for HL407889+4.p
146273.34/19563.86	eprover: CPU time limit exceeded, terminating
146273.34/19563.86	% SZS status Ended for HL407889+4.p
146274.03/19563.99	% SZS status Started for HL407882+5.p
146274.03/19563.99	% SZS status GaveUp for HL407882+5.p
146274.03/19563.99	eprover: CPU time limit exceeded, terminating
146274.03/19563.99	% SZS status Ended for HL407882+5.p
146284.56/19565.28	% SZS status Started for HL407883+5.p
146284.56/19565.28	% SZS status GaveUp for HL407883+5.p
146284.56/19565.28	eprover: CPU time limit exceeded, terminating
146284.56/19565.28	% SZS status Ended for HL407883+5.p
146298.81/19567.09	% SZS status Started for HL407890+4.p
146298.81/19567.09	% SZS status GaveUp for HL407890+4.p
146298.81/19567.09	eprover: CPU time limit exceeded, terminating
146298.81/19567.09	% SZS status Ended for HL407890+4.p
146300.97/19567.37	% SZS status Started for HL407884+5.p
146300.97/19567.37	% SZS status GaveUp for HL407884+5.p
146300.97/19567.37	eprover: CPU time limit exceeded, terminating
146300.97/19567.37	% SZS status Ended for HL407884+5.p
146323.08/19570.13	% SZS status Started for HL407891+4.p
146323.08/19570.13	% SZS status GaveUp for HL407891+4.p
146323.08/19570.13	eprover: CPU time limit exceeded, terminating
146323.08/19570.13	% SZS status Ended for HL407891+4.p
146337.53/19572.03	% SZS status Started for HL407885+5.p
146337.53/19572.03	% SZS status GaveUp for HL407885+5.p
146337.53/19572.03	eprover: CPU time limit exceeded, terminating
146337.53/19572.03	% SZS status Ended for HL407885+5.p
146346.92/19573.17	% SZS status Started for HL407892+4.p
146346.92/19573.17	% SZS status GaveUp for HL407892+4.p
146346.92/19573.17	eprover: CPU time limit exceeded, terminating
146346.92/19573.17	% SZS status Ended for HL407892+4.p
146370.59/19576.21	% SZS status Started for HL407894+4.p
146370.59/19576.21	% SZS status GaveUp for HL407894+4.p
146370.59/19576.21	eprover: CPU time limit exceeded, terminating
146370.59/19576.21	% SZS status Ended for HL407894+4.p
146372.58/19576.42	% SZS status Started for HL407886+5.p
146372.58/19576.42	% SZS status GaveUp for HL407886+5.p
146372.58/19576.42	eprover: CPU time limit exceeded, terminating
146372.58/19576.42	% SZS status Ended for HL407886+5.p
146397.34/19579.53	% SZS status Started for HL407895+4.p
146397.34/19579.53	% SZS status GaveUp for HL407895+4.p
146397.34/19579.53	eprover: CPU time limit exceeded, terminating
146397.34/19579.53	% SZS status Ended for HL407895+4.p
146397.88/19579.68	% SZS status Started for HL407887+5.p
146397.88/19579.68	% SZS status GaveUp for HL407887+5.p
146397.88/19579.68	eprover: CPU time limit exceeded, terminating
146397.88/19579.68	% SZS status Ended for HL407887+5.p
146422.86/19582.71	% SZS status Started for HL407896+4.p
146422.86/19582.71	% SZS status GaveUp for HL407896+4.p
146422.86/19582.71	eprover: CPU time limit exceeded, terminating
146422.86/19582.71	% SZS status Ended for HL407896+4.p
146442.64/19585.26	% SZS status Started for HL407888+5.p
146442.64/19585.26	% SZS status GaveUp for HL407888+5.p
146442.64/19585.26	eprover: CPU time limit exceeded, terminating
146442.64/19585.26	% SZS status Ended for HL407888+5.p
146466.95/19588.29	% SZS status Started for HL407898+4.p
146466.95/19588.29	% SZS status GaveUp for HL407898+4.p
146466.95/19588.29	eprover: CPU time limit exceeded, terminating
146466.95/19588.29	% SZS status Ended for HL407898+4.p
146480.48/19589.93	% SZS status Started for HL407889+5.p
146480.48/19589.93	% SZS status GaveUp for HL407889+5.p
146480.48/19589.93	eprover: CPU time limit exceeded, terminating
146480.48/19589.93	% SZS status Ended for HL407889+5.p
146492.34/19591.42	% SZS status Started for HL407890+5.p
146492.34/19591.42	% SZS status GaveUp for HL407890+5.p
146492.34/19591.42	eprover: CPU time limit exceeded, terminating
146492.34/19591.42	% SZS status Ended for HL407890+5.p
146504.45/19592.98	% SZS status Started for HL407899+4.p
146504.45/19592.98	% SZS status GaveUp for HL407899+4.p
146504.45/19592.98	eprover: CPU time limit exceeded, terminating
146504.45/19592.98	% SZS status Ended for HL407899+4.p
146509.66/19593.67	% SZS status Started for HL407891+5.p
146509.66/19593.67	% SZS status GaveUp for HL407891+5.p
146509.66/19593.67	eprover: CPU time limit exceeded, terminating
146509.66/19593.67	% SZS status Ended for HL407891+5.p
146528.39/19596.01	% SZS status Started for HL407900+4.p
146528.39/19596.01	% SZS status GaveUp for HL407900+4.p
146528.39/19596.01	eprover: CPU time limit exceeded, terminating
146528.39/19596.01	% SZS status Ended for HL407900+4.p
146544.62/19598.01	% SZS status Started for HL407892+5.p
146544.62/19598.01	% SZS status GaveUp for HL407892+5.p
146544.62/19598.01	eprover: CPU time limit exceeded, terminating
146544.62/19598.01	% SZS status Ended for HL407892+5.p
146551.75/19599.04	% SZS status Started for HL407901+4.p
146551.75/19599.04	% SZS status GaveUp for HL407901+4.p
146551.75/19599.04	eprover: CPU time limit exceeded, terminating
146551.75/19599.04	% SZS status Ended for HL407901+4.p
146577.50/19602.15	% SZS status Started for HL407904+4.p
146577.50/19602.15	% SZS status GaveUp for HL407904+4.p
146577.50/19602.15	eprover: CPU time limit exceeded, terminating
146577.50/19602.15	% SZS status Ended for HL407904+4.p
146579.12/19602.48	% SZS status Started for HL407894+5.p
146579.12/19602.48	% SZS status GaveUp for HL407894+5.p
146579.12/19602.48	eprover: CPU time limit exceeded, terminating
146579.12/19602.48	% SZS status Ended for HL407894+5.p
146603.33/19605.49	% SZS status Started for HL407895+5.p
146603.33/19605.49	% SZS status GaveUp for HL407895+5.p
146603.33/19605.49	eprover: CPU time limit exceeded, terminating
146603.33/19605.49	% SZS status Ended for HL407895+5.p
146604.06/19605.52	% SZS status Started for HL407905+4.p
146604.06/19605.52	% SZS status GaveUp for HL407905+4.p
146604.06/19605.52	eprover: CPU time limit exceeded, terminating
146604.06/19605.52	% SZS status Ended for HL407905+4.p
146627.84/19608.57	% SZS status Started for HL407906+4.p
146627.84/19608.57	% SZS status GaveUp for HL407906+4.p
146627.84/19608.57	eprover: CPU time limit exceeded, terminating
146627.84/19608.57	% SZS status Ended for HL407906+4.p
146628.30/19608.64	% SZS status Started for HL407896+5.p
146628.30/19608.64	% SZS status GaveUp for HL407896+5.p
146628.30/19608.64	eprover: CPU time limit exceeded, terminating
146628.30/19608.64	% SZS status Ended for HL407896+5.p
146653.38/19611.78	% SZS status Started for HL407907+4.p
146653.38/19611.78	% SZS status GaveUp for HL407907+4.p
146653.38/19611.78	eprover: CPU time limit exceeded, terminating
146653.38/19611.78	% SZS status Ended for HL407907+4.p
146675.20/19614.49	% SZS status Started for HL407898+5.p
146675.20/19614.49	% SZS status GaveUp for HL407898+5.p
146675.20/19614.49	eprover: CPU time limit exceeded, terminating
146675.20/19614.49	% SZS status Ended for HL407898+5.p
146698.11/19617.36	% SZS status Started for HL407899+5.p
146698.11/19617.36	% SZS status GaveUp for HL407899+5.p
146698.11/19617.36	eprover: CPU time limit exceeded, terminating
146698.11/19617.36	% SZS status Ended for HL407899+5.p
146699.47/19617.55	% SZS status Started for HL407908+4.p
146699.47/19617.55	% SZS status GaveUp for HL407908+4.p
146699.47/19617.55	eprover: CPU time limit exceeded, terminating
146699.47/19617.55	% SZS status Ended for HL407908+4.p
146717.81/19619.86	% SZS status Started for HL407900+5.p
146717.81/19619.86	% SZS status GaveUp for HL407900+5.p
146717.81/19619.86	eprover: CPU time limit exceeded, terminating
146717.81/19619.86	% SZS status Ended for HL407900+5.p
146723.59/19620.61	% SZS status Started for HL407909+4.p
146723.59/19620.61	% SZS status GaveUp for HL407909+4.p
146723.59/19620.61	eprover: CPU time limit exceeded, terminating
146723.59/19620.61	% SZS status Ended for HL407909+4.p
146747.59/19623.65	% SZS status Started for HL407911+4.p
146747.59/19623.65	% SZS status GaveUp for HL407911+4.p
146747.59/19623.65	eprover: CPU time limit exceeded, terminating
146747.59/19623.65	% SZS status Ended for HL407911+4.p
146750.30/19624.03	% SZS status Started for HL407901+5.p
146750.30/19624.03	% SZS status GaveUp for HL407901+5.p
146750.30/19624.03	eprover: CPU time limit exceeded, terminating
146750.30/19624.03	% SZS status Ended for HL407901+5.p
146775.19/19627.07	% SZS status Started for HL407912+4.p
146775.19/19627.07	% SZS status GaveUp for HL407912+4.p
146775.19/19627.07	eprover: CPU time limit exceeded, terminating
146775.19/19627.07	% SZS status Ended for HL407912+4.p
146785.44/19628.37	% SZS status Started for HL407904+5.p
146785.44/19628.37	% SZS status GaveUp for HL407904+5.p
146785.44/19628.37	eprover: CPU time limit exceeded, terminating
146785.44/19628.37	% SZS status Ended for HL407904+5.p
146809.39/19631.40	% SZS status Started for HL407913+4.p
146809.39/19631.40	% SZS status GaveUp for HL407913+4.p
146809.39/19631.40	eprover: CPU time limit exceeded, terminating
146809.39/19631.40	% SZS status Ended for HL407913+4.p
146810.17/19631.50	% SZS status Started for HL407905+5.p
146810.17/19631.50	% SZS status GaveUp for HL407905+5.p
146810.17/19631.50	eprover: CPU time limit exceeded, terminating
146810.17/19631.50	% SZS status Ended for HL407905+5.p
146833.55/19634.46	% SZS status Started for HL407906+5.p
146833.55/19634.46	% SZS status GaveUp for HL407906+5.p
146833.55/19634.46	eprover: CPU time limit exceeded, terminating
146833.55/19634.46	% SZS status Ended for HL407906+5.p
146833.94/19634.53	% SZS status Started for HL407915+4.p
146833.94/19634.53	% SZS status GaveUp for HL407915+4.p
146833.94/19634.53	eprover: CPU time limit exceeded, terminating
146833.94/19634.53	% SZS status Ended for HL407915+4.p
146857.05/19637.40	% SZS status Started for HL407912+5.p
146857.05/19637.40	% SZS status GaveUp for HL407912+5.p
146857.05/19637.40	eprover: CPU time limit exceeded, terminating
146857.05/19637.40	% SZS status Ended for HL407912+5.p
146858.50/19637.58	% SZS status Started for HL407916+4.p
146858.50/19637.58	% SZS status GaveUp for HL407916+4.p
146858.50/19637.58	eprover: CPU time limit exceeded, terminating
146858.50/19637.58	% SZS status Ended for HL407916+4.p
146862.27/19638.06	% SZS status Started for HL407907+5.p
146862.27/19638.06	% SZS status GaveUp for HL407907+5.p
146862.27/19638.06	eprover: CPU time limit exceeded, terminating
146862.27/19638.06	% SZS status Ended for HL407907+5.p
146882.58/19640.65	% SZS status Started for HL407917+4.p
146882.58/19640.65	% SZS status GaveUp for HL407917+4.p
146882.58/19640.65	eprover: CPU time limit exceeded, terminating
146882.58/19640.65	% SZS status Ended for HL407917+4.p
146907.00/19643.67	% SZS status Started for HL407908+5.p
146907.00/19643.67	% SZS status GaveUp for HL407908+5.p
146907.00/19643.67	eprover: CPU time limit exceeded, terminating
146907.00/19643.67	% SZS status Ended for HL407908+5.p
146907.00/19643.71	% SZS status Started for HL407918+4.p
146907.00/19643.71	% SZS status GaveUp for HL407918+4.p
146907.00/19643.71	eprover: CPU time limit exceeded, terminating
146907.00/19643.71	% SZS status Ended for HL407918+4.p
146923.75/19645.80	% SZS status Started for HL407909+5.p
146923.75/19645.80	% SZS status GaveUp for HL407909+5.p
146923.75/19645.80	eprover: CPU time limit exceeded, terminating
146923.75/19645.80	% SZS status Ended for HL407909+5.p
146931.62/19646.83	% SZS status Started for HL407919+4.p
146931.62/19646.83	% SZS status GaveUp for HL407919+4.p
146931.62/19646.83	eprover: CPU time limit exceeded, terminating
146931.62/19646.83	% SZS status Ended for HL407919+4.p
146955.69/19649.84	% SZS status Started for HL407911+5.p
146955.69/19649.84	% SZS status GaveUp for HL407911+5.p
146955.69/19649.84	eprover: CPU time limit exceeded, terminating
146955.69/19649.84	% SZS status Ended for HL407911+5.p
146956.11/19649.90	% SZS status Started for HL407920+4.p
146956.11/19649.90	% SZS status GaveUp for HL407920+4.p
146956.11/19649.90	eprover: CPU time limit exceeded, terminating
146956.11/19649.90	% SZS status Ended for HL407920+4.p
146980.44/19652.98	% SZS status Started for HL407921+4.p
146980.44/19652.98	% SZS status GaveUp for HL407921+4.p
146980.44/19652.98	eprover: CPU time limit exceeded, terminating
146980.44/19652.98	% SZS status Ended for HL407921+4.p
147018.06/19657.39	% SZS status Started for HL407913+5.p
147018.06/19657.39	% SZS status GaveUp for HL407913+5.p
147018.06/19657.39	eprover: CPU time limit exceeded, terminating
147018.06/19657.39	% SZS status Ended for HL407913+5.p
147042.36/19660.44	% SZS status Started for HL407922+4.p
147042.36/19660.44	% SZS status GaveUp for HL407922+4.p
147042.36/19660.44	eprover: CPU time limit exceeded, terminating
147042.36/19660.44	% SZS status Ended for HL407922+4.p
147043.20/19660.56	% SZS status Started for HL407915+5.p
147043.20/19660.56	% SZS status GaveUp for HL407915+5.p
147043.20/19660.56	eprover: CPU time limit exceeded, terminating
147043.20/19660.56	% SZS status Ended for HL407915+5.p
147067.09/19663.58	% SZS status Started for HL407916+5.p
147067.09/19663.58	% SZS status GaveUp for HL407916+5.p
147067.09/19663.58	eprover: CPU time limit exceeded, terminating
147067.09/19663.58	% SZS status Ended for HL407916+5.p
147067.75/19663.66	% SZS status Started for HL407923+4.p
147067.75/19663.66	% SZS status GaveUp for HL407923+4.p
147067.75/19663.66	eprover: CPU time limit exceeded, terminating
147067.75/19663.66	% SZS status Ended for HL407923+4.p
147071.38/19664.20	% SZS status Started for HL407917+5.p
147071.38/19664.20	% SZS status GaveUp for HL407917+5.p
147071.38/19664.20	eprover: CPU time limit exceeded, terminating
147071.38/19664.20	% SZS status Ended for HL407917+5.p
147091.69/19666.69	% SZS status Started for HL407924+4.p
147091.69/19666.69	% SZS status GaveUp for HL407924+4.p
147091.69/19666.69	eprover: CPU time limit exceeded, terminating
147091.69/19666.69	% SZS status Ended for HL407924+4.p
147115.77/19669.71	% SZS status Started for HL407925+4.p
147115.77/19669.71	% SZS status GaveUp for HL407925+4.p
147115.77/19669.71	eprover: CPU time limit exceeded, terminating
147115.77/19669.71	% SZS status Ended for HL407925+4.p
147116.33/19669.77	% SZS status Started for HL407918+5.p
147116.33/19669.77	% SZS status GaveUp for HL407918+5.p
147116.33/19669.77	eprover: CPU time limit exceeded, terminating
147116.33/19669.77	% SZS status Ended for HL407918+5.p
147132.86/19671.85	% SZS status Started for HL407919+5.p
147132.86/19671.85	% SZS status GaveUp for HL407919+5.p
147132.86/19671.85	eprover: CPU time limit exceeded, terminating
147132.86/19671.85	% SZS status Ended for HL407919+5.p
147140.12/19672.80	% SZS status Started for HL407926+4.p
147140.12/19672.80	% SZS status GaveUp for HL407926+4.p
147140.12/19672.80	eprover: CPU time limit exceeded, terminating
147140.12/19672.80	% SZS status Ended for HL407926+4.p
147164.45/19675.88	% SZS status Started for HL407927+4.p
147164.45/19675.88	% SZS status GaveUp for HL407927+4.p
147164.45/19675.88	eprover: CPU time limit exceeded, terminating
147164.45/19675.88	% SZS status Ended for HL407927+4.p
147166.92/19676.17	% SZS status Started for HL407920+5.p
147166.92/19676.17	% SZS status GaveUp for HL407920+5.p
147166.92/19676.17	eprover: CPU time limit exceeded, terminating
147166.92/19676.17	% SZS status Ended for HL407920+5.p
147189.98/19679.13	% SZS status Started for HL407921+5.p
147189.98/19679.13	% SZS status GaveUp for HL407921+5.p
147189.98/19679.13	eprover: CPU time limit exceeded, terminating
147189.98/19679.13	% SZS status Ended for HL407921+5.p
147190.97/19679.23	% SZS status Started for HL407929+4.p
147190.97/19679.23	% SZS status GaveUp for HL407929+4.p
147190.97/19679.23	eprover: CPU time limit exceeded, terminating
147190.97/19679.23	% SZS status Ended for HL407929+4.p
147215.20/19682.26	% SZS status Started for HL407930+4.p
147215.20/19682.26	% SZS status GaveUp for HL407930+4.p
147215.20/19682.26	eprover: CPU time limit exceeded, terminating
147215.20/19682.26	% SZS status Ended for HL407930+4.p
147247.66/19686.41	% SZS status Started for HL407922+5.p
147247.66/19686.41	% SZS status GaveUp for HL407922+5.p
147247.66/19686.41	eprover: CPU time limit exceeded, terminating
147247.66/19686.41	% SZS status Ended for HL407922+5.p
147271.86/19689.44	% SZS status Started for HL407931+4.p
147271.86/19689.44	% SZS status GaveUp for HL407931+4.p
147271.86/19689.44	eprover: CPU time limit exceeded, terminating
147271.86/19689.44	% SZS status Ended for HL407931+4.p
147273.27/19689.60	% SZS status Started for HL407929+5.p
147273.27/19689.60	% SZS status GaveUp for HL407929+5.p
147273.27/19689.60	eprover: CPU time limit exceeded, terminating
147273.27/19689.60	% SZS status Ended for HL407929+5.p
147274.41/19689.81	% SZS status Started for HL407923+5.p
147274.41/19689.81	% SZS status GaveUp for HL407923+5.p
147274.41/19689.81	eprover: CPU time limit exceeded, terminating
147274.41/19689.81	% SZS status Ended for HL407923+5.p
147278.84/19690.27	% SZS status Started for HL407924+5.p
147278.84/19690.27	% SZS status GaveUp for HL407924+5.p
147278.84/19690.27	eprover: CPU time limit exceeded, terminating
147278.84/19690.27	% SZS status Ended for HL407924+5.p
147297.44/19692.63	% SZS status Started for HL407932+4.p
147297.44/19692.63	% SZS status GaveUp for HL407932+4.p
147297.44/19692.63	eprover: CPU time limit exceeded, terminating
147297.44/19692.63	% SZS status Ended for HL407932+4.p
147302.48/19693.32	% SZS status Started for HL407933+4.p
147302.48/19693.32	% SZS status GaveUp for HL407933+4.p
147302.48/19693.32	eprover: CPU time limit exceeded, terminating
147302.48/19693.32	% SZS status Ended for HL407933+4.p
147321.64/19695.69	% SZS status Started for HL407925+5.p
147321.64/19695.69	% SZS status GaveUp for HL407925+5.p
147321.64/19695.69	eprover: CPU time limit exceeded, terminating
147321.64/19695.69	% SZS status Ended for HL407925+5.p
147326.38/19696.35	% SZS status Started for HL407935+4.p
147326.38/19696.35	% SZS status GaveUp for HL407935+4.p
147326.38/19696.35	eprover: CPU time limit exceeded, terminating
147326.38/19696.35	% SZS status Ended for HL407935+4.p
147339.45/19697.94	% SZS status Started for HL407926+5.p
147339.45/19697.94	% SZS status GaveUp for HL407926+5.p
147339.45/19697.94	eprover: CPU time limit exceeded, terminating
147339.45/19697.94	% SZS status Ended for HL407926+5.p
147351.72/19699.46	% SZS status Started for HL407937+4.p
147351.72/19699.46	% SZS status GaveUp for HL407937+4.p
147351.72/19699.46	eprover: CPU time limit exceeded, terminating
147351.72/19699.46	% SZS status Ended for HL407937+4.p
147372.47/19702.06	% SZS status Started for HL407927+5.p
147372.47/19702.06	% SZS status GaveUp for HL407927+5.p
147372.47/19702.06	eprover: CPU time limit exceeded, terminating
147372.47/19702.06	% SZS status Ended for HL407927+5.p
147375.75/19702.62	% SZS status Started for HL407938+4.p
147375.75/19702.62	% SZS status GaveUp for HL407938+4.p
147375.75/19702.62	eprover: CPU time limit exceeded, terminating
147375.75/19702.62	% SZS status Ended for HL407938+4.p
147401.34/19705.72	% SZS status Started for HL407939+4.p
147401.34/19705.72	% SZS status GaveUp for HL407939+4.p
147401.34/19705.72	eprover: CPU time limit exceeded, terminating
147401.34/19705.72	% SZS status Ended for HL407939+4.p
147422.00/19708.31	% SZS status Started for HL407930+5.p
147422.00/19708.31	% SZS status GaveUp for HL407930+5.p
147422.00/19708.31	eprover: CPU time limit exceeded, terminating
147422.00/19708.31	% SZS status Ended for HL407930+5.p
147445.48/19711.34	% SZS status Started for HL407940+4.p
147445.48/19711.34	% SZS status GaveUp for HL407940+4.p
147445.48/19711.34	eprover: CPU time limit exceeded, terminating
147445.48/19711.34	% SZS status Ended for HL407940+4.p
147480.98/19715.46	% SZS status Started for HL407931+5.p
147480.98/19715.46	% SZS status GaveUp for HL407931+5.p
147480.98/19715.46	eprover: CPU time limit exceeded, terminating
147480.98/19715.46	% SZS status Ended for HL407931+5.p
147485.31/19715.99	% SZS status Started for HL407932+5.p
147485.31/19715.99	% SZS status GaveUp for HL407932+5.p
147485.31/19715.99	eprover: CPU time limit exceeded, terminating
147485.31/19715.99	% SZS status Ended for HL407932+5.p
147505.25/19718.49	% SZS status Started for HL407941+4.p
147505.25/19718.49	% SZS status GaveUp for HL407941+4.p
147505.25/19718.49	eprover: CPU time limit exceeded, terminating
147505.25/19718.49	% SZS status Ended for HL407941+4.p
147505.25/19718.56	% SZS status Started for HL407933+5.p
147505.25/19718.56	% SZS status GaveUp for HL407933+5.p
147505.25/19718.56	eprover: CPU time limit exceeded, terminating
147505.25/19718.56	% SZS status Ended for HL407933+5.p
147529.16/19721.52	% SZS status Started for HL407942+4.p
147529.16/19721.52	% SZS status GaveUp for HL407942+4.p
147529.16/19721.52	eprover: CPU time limit exceeded, terminating
147529.16/19721.52	% SZS status Ended for HL407942+4.p
147530.91/19721.73	% SZS status Started for HL407935+5.p
147530.91/19721.73	% SZS status GaveUp for HL407935+5.p
147530.91/19721.73	eprover: CPU time limit exceeded, terminating
147530.91/19721.73	% SZS status Ended for HL407935+5.p
147548.72/19724.01	% SZS status Started for HL407937+5.p
147548.72/19724.01	% SZS status GaveUp for HL407937+5.p
147548.72/19724.01	eprover: CPU time limit exceeded, terminating
147548.72/19724.01	% SZS status Ended for HL407937+5.p
147553.58/19724.56	% SZS status Started for HL407943+4.p
147553.58/19724.56	% SZS status GaveUp for HL407943+4.p
147553.58/19724.56	eprover: CPU time limit exceeded, terminating
147553.58/19724.56	% SZS status Ended for HL407943+4.p
147572.78/19727.05	% SZS status Started for HL407944+4.p
147572.78/19727.05	% SZS status GaveUp for HL407944+4.p
147572.78/19727.05	eprover: CPU time limit exceeded, terminating
147572.78/19727.05	% SZS status Ended for HL407944+4.p
147582.17/19728.17	% SZS status Started for HL407938+5.p
147582.17/19728.17	% SZS status GaveUp for HL407938+5.p
147582.17/19728.17	eprover: CPU time limit exceeded, terminating
147582.17/19728.17	% SZS status Ended for HL407938+5.p
147596.00/19730.09	% SZS status Started for HL407945+4.p
147596.00/19730.09	% SZS status GaveUp for HL407945+4.p
147596.00/19730.09	eprover: CPU time limit exceeded, terminating
147596.00/19730.09	% SZS status Ended for HL407945+4.p
147611.56/19731.95	% SZS status Started for HL407939+5.p
147611.56/19731.95	% SZS status GaveUp for HL407939+5.p
147611.56/19731.95	eprover: CPU time limit exceeded, terminating
147611.56/19731.95	% SZS status Ended for HL407939+5.p
147621.30/19733.13	% SZS status Started for HL407946+4.p
147621.30/19733.13	% SZS status GaveUp for HL407946+4.p
147621.30/19733.13	eprover: CPU time limit exceeded, terminating
147621.30/19733.13	% SZS status Ended for HL407946+4.p
147635.48/19734.92	% SZS status Started for HL407944+5.p
147635.48/19734.92	% SZS status GaveUp for HL407944+5.p
147635.48/19734.92	eprover: CPU time limit exceeded, terminating
147635.48/19734.92	% SZS status Ended for HL407944+5.p
147644.80/19736.16	% SZS status Started for HL407947+4.p
147644.80/19736.16	% SZS status GaveUp for HL407947+4.p
147644.80/19736.16	eprover: CPU time limit exceeded, terminating
147644.80/19736.16	% SZS status Ended for HL407947+4.p
147654.17/19737.29	% SZS status Started for HL407940+5.p
147654.17/19737.29	% SZS status GaveUp for HL407940+5.p
147654.17/19737.29	eprover: CPU time limit exceeded, terminating
147654.17/19737.29	% SZS status Ended for HL407940+5.p
147666.39/19738.86	% SZS status Started for HL407945+5.p
147666.39/19738.86	% SZS status GaveUp for HL407945+5.p
147666.39/19738.86	eprover: CPU time limit exceeded, terminating
147666.39/19738.86	% SZS status Ended for HL407945+5.p
147669.83/19739.20	% SZS status Started for HL407948+4.p
147669.83/19739.20	% SZS status GaveUp for HL407948+4.p
147669.83/19739.20	eprover: CPU time limit exceeded, terminating
147669.83/19739.20	% SZS status Ended for HL407948+4.p
147690.61/19741.89	% SZS status Started for HL407949+4.p
147690.61/19741.89	% SZS status GaveUp for HL407949+4.p
147690.61/19741.89	eprover: CPU time limit exceeded, terminating
147690.61/19741.89	% SZS status Ended for HL407949+4.p
147690.67/19741.95	% SZS status Started for HL407941+5.p
147690.67/19741.95	% SZS status GaveUp for HL407941+5.p
147690.67/19741.95	eprover: CPU time limit exceeded, terminating
147690.67/19741.95	% SZS status Ended for HL407941+5.p
147701.53/19743.23	% SZS status Started for HL407946+5.p
147701.53/19743.23	% SZS status GaveUp for HL407946+5.p
147701.53/19743.23	eprover: CPU time limit exceeded, terminating
147701.53/19743.23	% SZS status Ended for HL407946+5.p
147714.31/19744.89	% SZS status Started for HL407942+5.p
147714.31/19744.89	% SZS status GaveUp for HL407942+5.p
147714.31/19744.89	eprover: CPU time limit exceeded, terminating
147714.31/19744.89	% SZS status Ended for HL407942+5.p
147714.31/19744.93	% SZS status Started for HL407950+4.p
147714.31/19744.93	% SZS status GaveUp for HL407950+4.p
147714.31/19744.93	eprover: CPU time limit exceeded, terminating
147714.31/19744.93	% SZS status Ended for HL407950+4.p
147720.78/19745.64	% SZS status Started for HL407947+5.p
147720.78/19745.64	% SZS status GaveUp for HL407947+5.p
147720.78/19745.64	eprover: CPU time limit exceeded, terminating
147720.78/19745.64	% SZS status Ended for HL407947+5.p
147725.34/19746.28	% SZS status Started for HL407953+4.p
147725.34/19746.28	% SZS status GaveUp for HL407953+4.p
147725.34/19746.28	eprover: CPU time limit exceeded, terminating
147725.34/19746.28	% SZS status Ended for HL407953+4.p
147737.59/19747.73	% SZS status Started for HL407943+5.p
147737.59/19747.73	% SZS status GaveUp for HL407943+5.p
147737.59/19747.73	eprover: CPU time limit exceeded, terminating
147737.59/19747.73	% SZS status Ended for HL407943+5.p
147739.12/19747.97	% SZS status Started for HL407954+4.p
147739.12/19747.97	% SZS status GaveUp for HL407954+4.p
147739.12/19747.97	eprover: CPU time limit exceeded, terminating
147739.12/19747.97	% SZS status Ended for HL407954+4.p
147739.12/19747.98	% SZS status Started for HL407948+5.p
147739.12/19747.98	% SZS status GaveUp for HL407948+5.p
147739.12/19747.98	eprover: CPU time limit exceeded, terminating
147739.12/19747.98	% SZS status Ended for HL407948+5.p
147751.30/19749.47	% SZS status Started for HL407956+4.p
147751.30/19749.47	% SZS status GaveUp for HL407956+4.p
147751.30/19749.47	eprover: CPU time limit exceeded, terminating
147751.30/19749.47	% SZS status Ended for HL407956+4.p
147753.91/19749.88	% SZS status Started for HL407949+5.p
147753.91/19749.88	% SZS status GaveUp for HL407949+5.p
147753.91/19749.88	eprover: CPU time limit exceeded, terminating
147753.91/19749.88	% SZS status Ended for HL407949+5.p
147763.56/19751.01	% SZS status Started for HL407957+4.p
147763.56/19751.01	% SZS status GaveUp for HL407957+4.p
147763.56/19751.01	eprover: CPU time limit exceeded, terminating
147763.56/19751.01	% SZS status Ended for HL407957+4.p
147776.03/19752.66	% SZS status Started for HL407958+4.p
147776.03/19752.66	% SZS status GaveUp for HL407958+4.p
147776.03/19752.66	eprover: CPU time limit exceeded, terminating
147776.03/19752.66	% SZS status Ended for HL407958+4.p
147776.88/19752.85	% SZS status Started for HL407950+5.p
147776.88/19752.85	% SZS status GaveUp for HL407950+5.p
147776.88/19752.85	eprover: CPU time limit exceeded, terminating
147776.88/19752.85	% SZS status Ended for HL407950+5.p
147786.39/19754.08	% SZS status Started for HL407959+4.p
147786.39/19754.08	% SZS status GaveUp for HL407959+4.p
147786.39/19754.08	eprover: CPU time limit exceeded, terminating
147786.39/19754.08	% SZS status Ended for HL407959+4.p
147799.25/19755.56	% SZS status Started for HL407953+5.p
147799.25/19755.56	% SZS status GaveUp for HL407953+5.p
147799.25/19755.56	eprover: CPU time limit exceeded, terminating
147799.25/19755.56	% SZS status Ended for HL407953+5.p
147802.41/19755.97	% SZS status Started for HL407960+4.p
147802.41/19755.97	% SZS status GaveUp for HL407960+4.p
147802.41/19755.97	eprover: CPU time limit exceeded, terminating
147802.41/19755.97	% SZS status Ended for HL407960+4.p
147805.77/19756.32	% SZS status Started for HL407954+5.p
147805.77/19756.32	% SZS status GaveUp for HL407954+5.p
147805.77/19756.32	eprover: CPU time limit exceeded, terminating
147805.77/19756.32	% SZS status Ended for HL407954+5.p
147821.50/19758.37	% SZS status Started for HL407956+5.p
147821.50/19758.37	% SZS status GaveUp for HL407956+5.p
147821.50/19758.37	eprover: CPU time limit exceeded, terminating
147821.50/19758.37	% SZS status Ended for HL407956+5.p
147833.30/19758.60	% SZS status Started for HL407961+4.p
147833.30/19758.60	% SZS status GaveUp for HL407961+4.p
147833.30/19758.60	eprover: CPU time limit exceeded, terminating
147833.30/19758.60	% SZS status Ended for HL407961+4.p
147833.53/19758.64	% SZS status Started for HL407957+5.p
147833.53/19758.64	% SZS status GaveUp for HL407957+5.p
147833.53/19758.64	eprover: CPU time limit exceeded, terminating
147833.53/19758.64	% SZS status Ended for HL407957+5.p
147840.52/19759.51	% SZS status Started for HL407962+4.p
147840.52/19759.51	% SZS status GaveUp for HL407962+4.p
147840.52/19759.51	eprover: CPU time limit exceeded, terminating
147840.52/19759.51	% SZS status Ended for HL407962+4.p
147848.80/19760.53	% SZS status Started for HL407958+5.p
147848.80/19760.53	% SZS status GaveUp for HL407958+5.p
147848.80/19760.53	eprover: CPU time limit exceeded, terminating
147848.80/19760.53	% SZS status Ended for HL407958+5.p
147857.98/19761.63	% SZS status Started for HL407963+4.p
147857.98/19761.63	% SZS status GaveUp for HL407963+4.p
147857.98/19761.63	eprover: CPU time limit exceeded, terminating
147857.98/19761.63	% SZS status Ended for HL407963+4.p
147865.17/19762.55	% SZS status Started for HL407964+4.p
147865.17/19762.55	% SZS status GaveUp for HL407964+4.p
147865.17/19762.55	eprover: CPU time limit exceeded, terminating
147865.17/19762.55	% SZS status Ended for HL407964+4.p
147870.48/19763.30	% SZS status Started for HL407959+5.p
147870.48/19763.30	% SZS status GaveUp for HL407959+5.p
147870.48/19763.30	eprover: CPU time limit exceeded, terminating
147870.48/19763.30	% SZS status Ended for HL407959+5.p
147881.53/19764.66	% SZS status Started for HL407965+4.p
147881.53/19764.66	% SZS status GaveUp for HL407965+4.p
147881.53/19764.66	eprover: CPU time limit exceeded, terminating
147881.53/19764.66	% SZS status Ended for HL407965+4.p
147882.56/19764.80	% SZS status Started for HL407960+5.p
147882.56/19764.80	% SZS status GaveUp for HL407960+5.p
147882.56/19764.80	eprover: CPU time limit exceeded, terminating
147882.56/19764.80	% SZS status Ended for HL407960+5.p
147895.33/19766.34	% SZS status Started for HL407966+4.p
147895.33/19766.34	% SZS status GaveUp for HL407966+4.p
147895.33/19766.34	eprover: CPU time limit exceeded, terminating
147895.33/19766.34	% SZS status Ended for HL407966+4.p
147897.36/19766.66	% SZS status Started for HL407961+5.p
147897.36/19766.66	% SZS status GaveUp for HL407961+5.p
147897.36/19766.66	eprover: CPU time limit exceeded, terminating
147897.36/19766.66	% SZS status Ended for HL407961+5.p
147906.88/19767.84	% SZS status Started for HL407968+4.p
147906.88/19767.84	% SZS status GaveUp for HL407968+4.p
147906.88/19767.84	eprover: CPU time limit exceeded, terminating
147906.88/19767.84	% SZS status Ended for HL407968+4.p
147916.03/19768.98	% SZS status Started for HL407962+5.p
147916.03/19768.98	% SZS status GaveUp for HL407962+5.p
147916.03/19768.98	eprover: CPU time limit exceeded, terminating
147916.03/19768.98	% SZS status Ended for HL407962+5.p
147920.94/19769.58	% SZS status Started for HL407963+5.p
147920.94/19769.58	% SZS status GaveUp for HL407963+5.p
147920.94/19769.58	eprover: CPU time limit exceeded, terminating
147920.94/19769.58	% SZS status Ended for HL407963+5.p
147921.78/19769.69	% SZS status Started for HL407969+4.p
147921.78/19769.69	% SZS status GaveUp for HL407969+4.p
147921.78/19769.69	eprover: CPU time limit exceeded, terminating
147921.78/19769.69	% SZS status Ended for HL407969+4.p
147933.27/19771.15	% SZS status Started for HL407964+5.p
147933.27/19771.15	% SZS status GaveUp for HL407964+5.p
147933.27/19771.15	eprover: CPU time limit exceeded, terminating
147933.27/19771.15	% SZS status Ended for HL407964+5.p
147939.92/19772.02	% SZS status Started for HL407970+4.p
147939.92/19772.02	% SZS status GaveUp for HL407970+4.p
147939.92/19772.02	eprover: CPU time limit exceeded, terminating
147939.92/19772.02	% SZS status Ended for HL407970+4.p
147946.12/19772.73	% SZS status Started for HL407972+4.p
147946.12/19772.73	% SZS status GaveUp for HL407972+4.p
147946.12/19772.73	eprover: CPU time limit exceeded, terminating
147946.12/19772.73	% SZS status Ended for HL407972+4.p
147948.52/19773.18	% SZS status Started for HL407965+5.p
147948.52/19773.18	% SZS status GaveUp for HL407965+5.p
147948.52/19773.18	eprover: CPU time limit exceeded, terminating
147948.52/19773.18	% SZS status Ended for HL407965+5.p
147964.95/19775.15	% SZS status Started for HL407974+4.p
147964.95/19775.15	% SZS status GaveUp for HL407974+4.p
147964.95/19775.15	eprover: CPU time limit exceeded, terminating
147964.95/19775.15	% SZS status Ended for HL407974+4.p
147970.22/19775.78	% SZS status Started for HL407966+5.p
147970.22/19775.78	% SZS status GaveUp for HL407966+5.p
147970.22/19775.78	eprover: CPU time limit exceeded, terminating
147970.22/19775.78	% SZS status Ended for HL407966+5.p
147974.22/19776.28	% SZS status Started for HL407976+4.p
147974.22/19776.28	% SZS status GaveUp for HL407976+4.p
147974.22/19776.28	eprover: CPU time limit exceeded, terminating
147974.22/19776.28	% SZS status Ended for HL407976+4.p
147979.73/19776.99	% SZS status Started for HL407968+5.p
147979.73/19776.99	% SZS status GaveUp for HL407968+5.p
147979.73/19776.99	eprover: CPU time limit exceeded, terminating
147979.73/19776.99	% SZS status Ended for HL407968+5.p
147990.94/19778.45	% SZS status Started for HL407969+5.p
147990.94/19778.45	% SZS status GaveUp for HL407969+5.p
147990.94/19778.45	eprover: CPU time limit exceeded, terminating
147990.94/19778.45	% SZS status Ended for HL407969+5.p
147994.86/19778.94	% SZS status Started for HL407977+4.p
147994.86/19778.94	% SZS status GaveUp for HL407977+4.p
147994.86/19778.94	eprover: CPU time limit exceeded, terminating
147994.86/19778.94	% SZS status Ended for HL407977+4.p
148003.70/19780.03	% SZS status Started for HL407978+4.p
148003.70/19780.03	% SZS status GaveUp for HL407978+4.p
148003.70/19780.03	eprover: CPU time limit exceeded, terminating
148003.70/19780.03	% SZS status Ended for HL407978+4.p
148004.70/19780.22	% SZS status Started for HL407970+5.p
148004.70/19780.22	% SZS status GaveUp for HL407970+5.p
148004.70/19780.22	eprover: CPU time limit exceeded, terminating
148004.70/19780.22	% SZS status Ended for HL407970+5.p
148018.20/19781.85	% SZS status Started for HL407972+5.p
148018.20/19781.85	% SZS status GaveUp for HL407972+5.p
148018.20/19781.85	eprover: CPU time limit exceeded, terminating
148018.20/19781.85	% SZS status Ended for HL407972+5.p
148018.86/19781.98	% SZS status Started for HL407979+4.p
148018.86/19781.98	% SZS status GaveUp for HL407979+4.p
148018.86/19781.98	eprover: CPU time limit exceeded, terminating
148018.86/19781.98	% SZS status Ended for HL407979+4.p
148029.06/19783.26	% SZS status Started for HL407980+4.p
148029.06/19783.26	% SZS status GaveUp for HL407980+4.p
148029.06/19783.26	eprover: CPU time limit exceeded, terminating
148029.06/19783.26	% SZS status Ended for HL407980+4.p
148029.39/19783.35	% SZS status Started for HL407974+5.p
148029.39/19783.35	% SZS status GaveUp for HL407974+5.p
148029.39/19783.35	eprover: CPU time limit exceeded, terminating
148029.39/19783.35	% SZS status Ended for HL407974+5.p
148043.09/19785.08	% SZS status Started for HL407981+4.p
148043.09/19785.08	% SZS status GaveUp for HL407981+4.p
148043.09/19785.08	eprover: CPU time limit exceeded, terminating
148043.09/19785.08	% SZS status Ended for HL407981+4.p
148050.12/19785.83	% SZS status Started for HL407976+5.p
148050.12/19785.83	% SZS status GaveUp for HL407976+5.p
148050.12/19785.83	eprover: CPU time limit exceeded, terminating
148050.12/19785.83	% SZS status Ended for HL407976+5.p
148054.42/19786.39	% SZS status Started for HL407983+4.p
148054.42/19786.39	% SZS status GaveUp for HL407983+4.p
148054.42/19786.39	eprover: CPU time limit exceeded, terminating
148054.42/19786.39	% SZS status Ended for HL407983+4.p
148058.91/19786.93	% SZS status Started for HL407977+5.p
148058.91/19786.93	% SZS status GaveUp for HL407977+5.p
148058.91/19786.93	eprover: CPU time limit exceeded, terminating
148058.91/19786.93	% SZS status Ended for HL407977+5.p
148073.69/19788.86	% SZS status Started for HL407984+4.p
148073.69/19788.86	% SZS status GaveUp for HL407984+4.p
148073.69/19788.86	eprover: CPU time limit exceeded, terminating
148073.69/19788.86	% SZS status Ended for HL407984+4.p
148075.77/19789.20	% SZS status Started for HL407978+5.p
148075.77/19789.20	% SZS status GaveUp for HL407978+5.p
148075.77/19789.20	eprover: CPU time limit exceeded, terminating
148075.77/19789.20	% SZS status Ended for HL407978+5.p
148081.97/19789.97	% SZS status Started for HL407985+4.p
148081.97/19789.97	% SZS status GaveUp for HL407985+4.p
148081.97/19789.97	eprover: CPU time limit exceeded, terminating
148081.97/19789.97	% SZS status Ended for HL407985+4.p
148088.69/19790.67	% SZS status Started for HL407979+5.p
148088.69/19790.67	% SZS status GaveUp for HL407979+5.p
148088.69/19790.67	eprover: CPU time limit exceeded, terminating
148088.69/19790.67	% SZS status Ended for HL407979+5.p
148100.38/19792.23	% SZS status Started for HL407986+4.p
148100.38/19792.23	% SZS status GaveUp for HL407986+4.p
148100.38/19792.23	eprover: CPU time limit exceeded, terminating
148100.38/19792.23	% SZS status Ended for HL407986+4.p
148103.30/19792.51	% SZS status Started for HL407980+5.p
148103.30/19792.51	% SZS status GaveUp for HL407980+5.p
148103.30/19792.51	eprover: CPU time limit exceeded, terminating
148103.30/19792.51	% SZS status Ended for HL407980+5.p
148113.03/19793.80	% SZS status Started for HL407987+4.p
148113.03/19793.80	% SZS status GaveUp for HL407987+4.p
148113.03/19793.80	eprover: CPU time limit exceeded, terminating
148113.03/19793.80	% SZS status Ended for HL407987+4.p
148115.16/19794.05	% SZS status Started for HL407981+5.p
148115.16/19794.05	% SZS status GaveUp for HL407981+5.p
148115.16/19794.05	eprover: CPU time limit exceeded, terminating
148115.16/19794.05	% SZS status Ended for HL407981+5.p
148127.33/19795.55	% SZS status Started for HL407988+4.p
148127.33/19795.55	% SZS status GaveUp for HL407988+4.p
148127.33/19795.55	eprover: CPU time limit exceeded, terminating
148127.33/19795.55	% SZS status Ended for HL407988+4.p
148131.08/19796.06	% SZS status Started for HL407983+5.p
148131.08/19796.06	% SZS status GaveUp for HL407983+5.p
148131.08/19796.06	eprover: CPU time limit exceeded, terminating
148131.08/19796.06	% SZS status Ended for HL407983+5.p
148138.58/19797.05	% SZS status Started for HL407984+5.p
148138.58/19797.05	% SZS status GaveUp for HL407984+5.p
148138.58/19797.05	eprover: CPU time limit exceeded, terminating
148138.58/19797.05	% SZS status Ended for HL407984+5.p
148138.58/19797.08	% SZS status Started for HL407989+4.p
148138.58/19797.08	% SZS status GaveUp for HL407989+4.p
148138.58/19797.08	eprover: CPU time limit exceeded, terminating
148138.58/19797.08	% SZS status Ended for HL407989+4.p
148156.17/19799.25	% SZS status Started for HL407990+4.p
148156.17/19799.25	% SZS status GaveUp for HL407990+4.p
148156.17/19799.25	eprover: CPU time limit exceeded, terminating
148156.17/19799.25	% SZS status Ended for HL407990+4.p
148157.38/19799.49	% SZS status Started for HL407985+5.p
148157.38/19799.49	% SZS status GaveUp for HL407985+5.p
148157.38/19799.49	eprover: CPU time limit exceeded, terminating
148157.38/19799.49	% SZS status Ended for HL407985+5.p
148163.48/19800.15	% SZS status Started for HL407991+4.p
148163.48/19800.15	% SZS status GaveUp for HL407991+4.p
148163.48/19800.15	eprover: CPU time limit exceeded, terminating
148163.48/19800.15	% SZS status Ended for HL407991+4.p
148167.36/19800.60	% SZS status Started for HL407986+5.p
148167.36/19800.60	% SZS status GaveUp for HL407986+5.p
148167.36/19800.60	eprover: CPU time limit exceeded, terminating
148167.36/19800.60	% SZS status Ended for HL407986+5.p
148183.53/19802.65	% SZS status Started for HL407992+4.p
148183.53/19802.65	% SZS status GaveUp for HL407992+4.p
148183.53/19802.65	eprover: CPU time limit exceeded, terminating
148183.53/19802.65	% SZS status Ended for HL407992+4.p
148186.16/19803.06	% SZS status Started for HL407987+5.p
148186.16/19803.06	% SZS status GaveUp for HL407987+5.p
148186.16/19803.06	eprover: CPU time limit exceeded, terminating
148186.16/19803.06	% SZS status Ended for HL407987+5.p
148191.95/19803.70	% SZS status Started for HL407993+4.p
148191.95/19803.70	% SZS status GaveUp for HL407993+4.p
148191.95/19803.70	eprover: CPU time limit exceeded, terminating
148191.95/19803.70	% SZS status Ended for HL407993+4.p
148197.45/19804.45	% SZS status Started for HL407988+5.p
148197.45/19804.45	% SZS status GaveUp for HL407988+5.p
148197.45/19804.45	eprover: CPU time limit exceeded, terminating
148197.45/19804.45	% SZS status Ended for HL407988+5.p
148211.86/19806.21	% SZS status Started for HL407989+5.p
148211.86/19806.21	% SZS status GaveUp for HL407989+5.p
148211.86/19806.21	eprover: CPU time limit exceeded, terminating
148211.86/19806.21	% SZS status Ended for HL407989+5.p
148211.86/19806.22	% SZS status Started for HL407994+4.p
148211.86/19806.22	% SZS status GaveUp for HL407994+4.p
148211.86/19806.22	eprover: CPU time limit exceeded, terminating
148211.86/19806.22	% SZS status Ended for HL407994+4.p
148221.91/19807.54	% SZS status Started for HL407995+4.p
148221.91/19807.54	% SZS status GaveUp for HL407995+4.p
148221.91/19807.54	eprover: CPU time limit exceeded, terminating
148221.91/19807.54	% SZS status Ended for HL407995+4.p
148223.48/19807.70	% SZS status Started for HL407990+5.p
148223.48/19807.70	% SZS status GaveUp for HL407990+5.p
148223.48/19807.70	eprover: CPU time limit exceeded, terminating
148223.48/19807.70	% SZS status Ended for HL407990+5.p
148236.03/19809.26	% SZS status Started for HL407996+4.p
148236.03/19809.26	% SZS status GaveUp for HL407996+4.p
148236.03/19809.26	eprover: CPU time limit exceeded, terminating
148236.03/19809.26	% SZS status Ended for HL407996+4.p
148241.05/19809.90	% SZS status Started for HL407991+5.p
148241.05/19809.90	% SZS status GaveUp for HL407991+5.p
148241.05/19809.90	eprover: CPU time limit exceeded, terminating
148241.05/19809.90	% SZS status Ended for HL407991+5.p
148248.11/19810.74	% SZS status Started for HL407999+4.p
148248.11/19810.74	% SZS status GaveUp for HL407999+4.p
148248.11/19810.74	eprover: CPU time limit exceeded, terminating
148248.11/19810.74	% SZS status Ended for HL407999+4.p
148248.61/19810.81	% SZS status Started for HL407992+5.p
148248.61/19810.81	% SZS status GaveUp for HL407992+5.p
148248.61/19810.81	eprover: CPU time limit exceeded, terminating
148248.61/19810.81	% SZS status Ended for HL407992+5.p
148264.81/19812.93	% SZS status Started for HL408001+4.p
148264.81/19812.93	% SZS status GaveUp for HL408001+4.p
148264.81/19812.93	eprover: CPU time limit exceeded, terminating
148264.81/19812.93	% SZS status Ended for HL408001+4.p
148268.28/19813.26	% SZS status Started for HL407993+5.p
148268.28/19813.26	% SZS status GaveUp for HL407993+5.p
148268.28/19813.26	eprover: CPU time limit exceeded, terminating
148268.28/19813.26	% SZS status Ended for HL407993+5.p
148272.64/19813.85	% SZS status Started for HL408002+4.p
148272.64/19813.85	% SZS status GaveUp for HL408002+4.p
148272.64/19813.85	eprover: CPU time limit exceeded, terminating
148272.64/19813.85	% SZS status Ended for HL408002+4.p
148276.69/19814.35	% SZS status Started for HL407994+5.p
148276.69/19814.35	% SZS status GaveUp for HL407994+5.p
148276.69/19814.35	eprover: CPU time limit exceeded, terminating
148276.69/19814.35	% SZS status Ended for HL407994+5.p
148292.31/19816.30	% SZS status Started for HL408003+4.p
148292.31/19816.30	% SZS status GaveUp for HL408003+4.p
148292.31/19816.30	eprover: CPU time limit exceeded, terminating
148292.31/19816.30	% SZS status Ended for HL408003+4.p
148296.97/19816.87	% SZS status Started for HL407995+5.p
148296.97/19816.87	% SZS status GaveUp for HL407995+5.p
148296.97/19816.87	eprover: CPU time limit exceeded, terminating
148296.97/19816.87	% SZS status Ended for HL407995+5.p
148301.25/19817.45	% SZS status Started for HL408004+4.p
148301.25/19817.45	% SZS status GaveUp for HL408004+4.p
148301.25/19817.45	eprover: CPU time limit exceeded, terminating
148301.25/19817.45	% SZS status Ended for HL408004+4.p
148310.09/19818.70	% SZS status Started for HL407996+5.p
148310.09/19818.70	% SZS status GaveUp for HL407996+5.p
148310.09/19818.70	eprover: CPU time limit exceeded, terminating
148310.09/19818.70	% SZS status Ended for HL407996+5.p
148321.00/19819.90	% SZS status Started for HL407999+5.p
148321.00/19819.90	% SZS status GaveUp for HL407999+5.p
148321.00/19819.90	eprover: CPU time limit exceeded, terminating
148321.00/19819.90	% SZS status Ended for HL407999+5.p
148321.00/19819.92	% SZS status Started for HL408006+4.p
148321.00/19819.92	% SZS status GaveUp for HL408006+4.p
148321.00/19819.92	eprover: CPU time limit exceeded, terminating
148321.00/19819.92	% SZS status Ended for HL408006+4.p
148332.39/19821.40	% SZS status Started for HL408001+5.p
148332.39/19821.40	% SZS status GaveUp for HL408001+5.p
148332.39/19821.40	eprover: CPU time limit exceeded, terminating
148332.39/19821.40	% SZS status Ended for HL408001+5.p
148335.39/19821.73	% SZS status Started for HL408007+4.p
148335.39/19821.73	% SZS status GaveUp for HL408007+4.p
148335.39/19821.73	eprover: CPU time limit exceeded, terminating
148335.39/19821.73	% SZS status Ended for HL408007+4.p
148345.67/19823.07	% SZS status Started for HL408008+4.p
148345.67/19823.07	% SZS status GaveUp for HL408008+4.p
148345.67/19823.07	eprover: CPU time limit exceeded, terminating
148345.67/19823.07	% SZS status Ended for HL408008+4.p
148350.69/19823.73	% SZS status Started for HL408002+5.p
148350.69/19823.73	% SZS status GaveUp for HL408002+5.p
148350.69/19823.73	eprover: CPU time limit exceeded, terminating
148350.69/19823.73	% SZS status Ended for HL408002+5.p
148357.03/19824.53	% SZS status Started for HL408003+5.p
148357.03/19824.53	% SZS status GaveUp for HL408003+5.p
148357.03/19824.53	eprover: CPU time limit exceeded, terminating
148357.03/19824.53	% SZS status Ended for HL408003+5.p
148360.03/19824.85	% SZS status Started for HL408009+4.p
148360.03/19824.85	% SZS status GaveUp for HL408009+4.p
148360.03/19824.85	eprover: CPU time limit exceeded, terminating
148360.03/19824.85	% SZS status Ended for HL408009+4.p
148375.42/19826.77	% SZS status Started for HL408010+4.p
148375.42/19826.77	% SZS status GaveUp for HL408010+4.p
148375.42/19826.77	eprover: CPU time limit exceeded, terminating
148375.42/19826.77	% SZS status Ended for HL408010+4.p
148376.72/19827.01	% SZS status Started for HL408004+5.p
148376.72/19827.01	% SZS status GaveUp for HL408004+5.p
148376.72/19827.01	eprover: CPU time limit exceeded, terminating
148376.72/19827.01	% SZS status Ended for HL408004+5.p
148384.27/19827.89	% SZS status Started for HL408011+4.p
148384.27/19827.89	% SZS status GaveUp for HL408011+4.p
148384.27/19827.89	eprover: CPU time limit exceeded, terminating
148384.27/19827.89	% SZS status Ended for HL408011+4.p
148385.45/19828.10	% SZS status Started for HL408006+5.p
148385.45/19828.10	% SZS status GaveUp for HL408006+5.p
148385.45/19828.10	eprover: CPU time limit exceeded, terminating
148385.45/19828.10	% SZS status Ended for HL408006+5.p
148400.72/19830.05	% SZS status Started for HL408012+4.p
148400.72/19830.05	% SZS status GaveUp for HL408012+4.p
148400.72/19830.05	eprover: CPU time limit exceeded, terminating
148400.72/19830.05	% SZS status Ended for HL408012+4.p
148405.28/19830.53	% SZS status Started for HL408007+5.p
148405.28/19830.53	% SZS status GaveUp for HL408007+5.p
148405.28/19830.53	eprover: CPU time limit exceeded, terminating
148405.28/19830.53	% SZS status Ended for HL408007+5.p
148410.05/19831.15	% SZS status Started for HL408013+4.p
148410.05/19831.15	% SZS status GaveUp for HL408013+4.p
148410.05/19831.15	eprover: CPU time limit exceeded, terminating
148410.05/19831.15	% SZS status Ended for HL408013+4.p
148416.91/19832.06	% SZS status Started for HL408008+5.p
148416.91/19832.06	% SZS status GaveUp for HL408008+5.p
148416.91/19832.06	eprover: CPU time limit exceeded, terminating
148416.91/19832.06	% SZS status Ended for HL408008+5.p
148429.23/19833.57	% SZS status Started for HL408014+4.p
148429.23/19833.57	% SZS status GaveUp for HL408014+4.p
148429.23/19833.57	eprover: CPU time limit exceeded, terminating
148429.23/19833.57	% SZS status Ended for HL408014+4.p
148429.92/19833.71	% SZS status Started for HL408009+5.p
148429.92/19833.71	% SZS status GaveUp for HL408009+5.p
148429.92/19833.71	eprover: CPU time limit exceeded, terminating
148429.92/19833.71	% SZS status Ended for HL408009+5.p
148440.06/19835.10	% SZS status Started for HL408015+4.p
148440.06/19835.10	% SZS status GaveUp for HL408015+4.p
148440.06/19835.10	eprover: CPU time limit exceeded, terminating
148440.06/19835.10	% SZS status Ended for HL408015+4.p
148445.52/19835.72	% SZS status Started for HL408010+5.p
148445.52/19835.72	% SZS status GaveUp for HL408010+5.p
148445.52/19835.72	eprover: CPU time limit exceeded, terminating
148445.52/19835.72	% SZS status Ended for HL408010+5.p
148454.22/19836.75	% SZS status Started for HL408016+4.p
148454.22/19836.75	% SZS status GaveUp for HL408016+4.p
148454.22/19836.75	eprover: CPU time limit exceeded, terminating
148454.22/19836.75	% SZS status Ended for HL408016+4.p
148460.08/19837.42	% SZS status Started for HL408011+5.p
148460.08/19837.42	% SZS status GaveUp for HL408011+5.p
148460.08/19837.42	eprover: CPU time limit exceeded, terminating
148460.08/19837.42	% SZS status Ended for HL408011+5.p
148467.69/19838.56	% SZS status Started for HL408012+5.p
148467.69/19838.56	% SZS status GaveUp for HL408012+5.p
148467.69/19838.56	eprover: CPU time limit exceeded, terminating
148467.69/19838.56	% SZS status Ended for HL408012+5.p
148470.41/19838.75	% SZS status Started for HL408017+4.p
148470.41/19838.75	% SZS status GaveUp for HL408017+4.p
148470.41/19838.75	eprover: CPU time limit exceeded, terminating
148470.41/19838.75	% SZS status Ended for HL408017+4.p
148483.45/19840.46	% SZS status Started for HL408018+4.p
148483.45/19840.46	% SZS status GaveUp for HL408018+4.p
148483.45/19840.46	eprover: CPU time limit exceeded, terminating
148483.45/19840.46	% SZS status Ended for HL408018+4.p
148485.58/19840.69	% SZS status Started for HL408013+5.p
148485.58/19840.69	% SZS status GaveUp for HL408013+5.p
148485.58/19840.69	eprover: CPU time limit exceeded, terminating
148485.58/19840.69	% SZS status Ended for HL408013+5.p
148494.44/19841.79	% SZS status Started for HL408019+4.p
148494.44/19841.79	% SZS status GaveUp for HL408019+4.p
148494.44/19841.79	eprover: CPU time limit exceeded, terminating
148494.44/19841.79	% SZS status Ended for HL408019+4.p
148495.19/19841.87	% SZS status Started for HL408014+5.p
148495.19/19841.87	% SZS status GaveUp for HL408014+5.p
148495.19/19841.87	eprover: CPU time limit exceeded, terminating
148495.19/19841.87	% SZS status Ended for HL408014+5.p
148509.91/19843.73	% SZS status Started for HL408020+4.p
148509.91/19843.73	% SZS status GaveUp for HL408020+4.p
148509.91/19843.73	eprover: CPU time limit exceeded, terminating
148509.91/19843.73	% SZS status Ended for HL408020+4.p
148513.67/19844.20	% SZS status Started for HL408015+5.p
148513.67/19844.20	% SZS status GaveUp for HL408015+5.p
148513.67/19844.20	eprover: CPU time limit exceeded, terminating
148513.67/19844.20	% SZS status Ended for HL408015+5.p
148519.31/19844.92	% SZS status Started for HL408021+4.p
148519.31/19844.92	% SZS status GaveUp for HL408021+4.p
148519.31/19844.92	eprover: CPU time limit exceeded, terminating
148519.31/19844.92	% SZS status Ended for HL408021+4.p
148527.30/19845.90	% SZS status Started for HL408016+5.p
148527.30/19845.90	% SZS status GaveUp for HL408016+5.p
148527.30/19845.90	eprover: CPU time limit exceeded, terminating
148527.30/19845.90	% SZS status Ended for HL408016+5.p
148537.78/19847.23	% SZS status Started for HL408022+4.p
148537.78/19847.23	% SZS status GaveUp for HL408022+4.p
148537.78/19847.23	eprover: CPU time limit exceeded, terminating
148537.78/19847.23	% SZS status Ended for HL408022+4.p
148542.44/19847.81	% SZS status Started for HL408017+5.p
148542.44/19847.81	% SZS status GaveUp for HL408017+5.p
148542.44/19847.81	eprover: CPU time limit exceeded, terminating
148542.44/19847.81	% SZS status Ended for HL408017+5.p
148551.28/19848.92	% SZS status Started for HL408023+4.p
148551.28/19848.92	% SZS status GaveUp for HL408023+4.p
148551.28/19848.92	eprover: CPU time limit exceeded, terminating
148551.28/19848.92	% SZS status Ended for HL408023+4.p
148552.80/19849.20	% SZS status Started for HL408018+5.p
148552.80/19849.20	% SZS status GaveUp for HL408018+5.p
148552.80/19849.20	eprover: CPU time limit exceeded, terminating
148552.80/19849.20	% SZS status Ended for HL408018+5.p
148565.56/19850.84	% SZS status Started for HL408024+4.p
148565.56/19850.84	% SZS status GaveUp for HL408024+4.p
148565.56/19850.84	eprover: CPU time limit exceeded, terminating
148565.56/19850.84	% SZS status Ended for HL408024+4.p
148569.48/19851.24	% SZS status Started for HL408019+5.p
148569.48/19851.24	% SZS status GaveUp for HL408019+5.p
148569.48/19851.24	eprover: CPU time limit exceeded, terminating
148569.48/19851.24	% SZS status Ended for HL408019+5.p
148577.84/19852.29	% SZS status Started for HL408025+4.p
148577.84/19852.29	% SZS status GaveUp for HL408025+4.p
148577.84/19852.29	eprover: CPU time limit exceeded, terminating
148577.84/19852.29	% SZS status Ended for HL408025+4.p
148579.33/19852.43	% SZS status Started for HL408020+5.p
148579.33/19852.43	% SZS status GaveUp for HL408020+5.p
148579.33/19852.43	eprover: CPU time limit exceeded, terminating
148579.33/19852.43	% SZS status Ended for HL408020+5.p
148591.52/19853.97	% SZS status Started for HL408021+5.p
148591.52/19853.97	% SZS status GaveUp for HL408021+5.p
148591.52/19853.97	eprover: CPU time limit exceeded, terminating
148591.52/19853.97	% SZS status Ended for HL408021+5.p
148593.08/19854.27	% SZS status Started for HL408027+4.p
148593.08/19854.27	% SZS status GaveUp for HL408027+4.p
148593.08/19854.27	eprover: CPU time limit exceeded, terminating
148593.08/19854.27	% SZS status Ended for HL408027+4.p
148603.36/19855.46	% SZS status Started for HL408028+4.p
148603.36/19855.46	% SZS status GaveUp for HL408028+4.p
148603.36/19855.46	eprover: CPU time limit exceeded, terminating
148603.36/19855.46	% SZS status Ended for HL408028+4.p
148617.27/19857.33	% SZS status Started for HL408029+4.p
148617.27/19857.33	% SZS status GaveUp for HL408029+4.p
148617.27/19857.33	eprover: CPU time limit exceeded, terminating
148617.27/19857.33	% SZS status Ended for HL408029+4.p
148619.97/19857.53	% SZS status Started for HL408023+5.p
148619.97/19857.53	% SZS status GaveUp for HL408023+5.p
148619.97/19857.53	eprover: CPU time limit exceeded, terminating
148619.97/19857.53	% SZS status Ended for HL408023+5.p
148642.50/19860.45	% SZS status Started for HL408030+4.p
148642.50/19860.45	% SZS status GaveUp for HL408030+4.p
148642.50/19860.45	eprover: CPU time limit exceeded, terminating
148642.50/19860.45	% SZS status Ended for HL408030+4.p
148666.62/19863.47	% SZS status Started for HL408031+4.p
148666.62/19863.47	% SZS status GaveUp for HL408031+4.p
148666.62/19863.47	eprover: CPU time limit exceeded, terminating
148666.62/19863.47	% SZS status Ended for HL408031+4.p
148727.88/19870.90	% SZS status Started for HL408022+5.p
148727.88/19870.90	% SZS status GaveUp for HL408022+5.p
148727.88/19870.90	eprover: CPU time limit exceeded, terminating
148727.88/19870.90	% SZS status Ended for HL408022+5.p
148752.22/19873.96	% SZS status Started for HL408032+4.p
148752.22/19873.96	% SZS status GaveUp for HL408032+4.p
148752.22/19873.96	eprover: CPU time limit exceeded, terminating
148752.22/19873.96	% SZS status Ended for HL408032+4.p
148762.09/19875.15	% SZS status Started for HL408024+5.p
148762.09/19875.15	% SZS status GaveUp for HL408024+5.p
148762.09/19875.15	eprover: CPU time limit exceeded, terminating
148762.09/19875.15	% SZS status Ended for HL408024+5.p
148775.86/19876.90	% SZS status Started for HL408025+5.p
148775.86/19876.90	% SZS status GaveUp for HL408025+5.p
148775.86/19876.90	eprover: CPU time limit exceeded, terminating
148775.86/19876.90	% SZS status Ended for HL408025+5.p
148786.17/19878.21	% SZS status Started for HL408033+4.p
148786.17/19878.21	% SZS status GaveUp for HL408033+4.p
148786.17/19878.21	eprover: CPU time limit exceeded, terminating
148786.17/19878.21	% SZS status Ended for HL408033+4.p
148788.89/19878.63	% SZS status Started for HL408027+5.p
148788.89/19878.63	% SZS status GaveUp for HL408027+5.p
148788.89/19878.63	eprover: CPU time limit exceeded, terminating
148788.89/19878.63	% SZS status Ended for HL408027+5.p
148799.69/19879.90	% SZS status Started for HL408028+5.p
148799.69/19879.90	% SZS status GaveUp for HL408028+5.p
148799.69/19879.90	eprover: CPU time limit exceeded, terminating
148799.69/19879.90	% SZS status Ended for HL408028+5.p
148810.52/19881.26	% SZS status Started for HL408034+4.p
148810.52/19881.26	% SZS status GaveUp for HL408034+4.p
148810.52/19881.26	eprover: CPU time limit exceeded, terminating
148810.52/19881.26	% SZS status Ended for HL408034+4.p
148811.81/19881.47	% SZS status Started for HL408029+5.p
148811.81/19881.47	% SZS status GaveUp for HL408029+5.p
148811.81/19881.47	eprover: CPU time limit exceeded, terminating
148811.81/19881.47	% SZS status Ended for HL408029+5.p
148823.95/19882.97	% SZS status Started for HL408035+4.p
148823.95/19882.97	% SZS status GaveUp for HL408035+4.p
148823.95/19882.97	eprover: CPU time limit exceeded, terminating
148823.95/19882.97	% SZS status Ended for HL408035+4.p
148829.14/19883.63	% SZS status Started for HL408030+5.p
148829.14/19883.63	% SZS status GaveUp for HL408030+5.p
148829.14/19883.63	eprover: CPU time limit exceeded, terminating
148829.14/19883.63	% SZS status Ended for HL408030+5.p
148835.55/19884.52	% SZS status Started for HL408036+4.p
148835.55/19884.52	% SZS status GaveUp for HL408036+4.p
148835.55/19884.52	eprover: CPU time limit exceeded, terminating
148835.55/19884.52	% SZS status Ended for HL408036+4.p
148839.48/19884.94	% SZS status Started for HL408032+5.p
148839.48/19884.94	% SZS status GaveUp for HL408032+5.p
148839.48/19884.94	eprover: CPU time limit exceeded, terminating
148839.48/19884.94	% SZS status Ended for HL408032+5.p
148852.59/19886.77	% SZS status Started for HL408038+4.p
148852.59/19886.77	% SZS status GaveUp for HL408038+4.p
148852.59/19886.77	eprover: CPU time limit exceeded, terminating
148852.59/19886.77	% SZS status Ended for HL408038+4.p
148860.14/19887.64	% SZS status Started for HL408033+5.p
148860.14/19887.64	% SZS status GaveUp for HL408033+5.p
148860.14/19887.64	eprover: CPU time limit exceeded, terminating
148860.14/19887.64	% SZS status Ended for HL408033+5.p
148862.56/19887.98	% SZS status Started for HL408041+4.p
148862.56/19887.98	% SZS status GaveUp for HL408041+4.p
148862.56/19887.98	eprover: CPU time limit exceeded, terminating
148862.56/19887.98	% SZS status Ended for HL408041+4.p
148874.03/19889.40	% SZS status Started for HL408034+5.p
148874.03/19889.40	% SZS status GaveUp for HL408034+5.p
148874.03/19889.40	eprover: CPU time limit exceeded, terminating
148874.03/19889.40	% SZS status Ended for HL408034+5.p
148875.41/19889.63	% SZS status Started for HL408031+5.p
148875.41/19889.63	% SZS status GaveUp for HL408031+5.p
148875.41/19889.63	eprover: CPU time limit exceeded, terminating
148875.41/19889.63	% SZS status Ended for HL408031+5.p
148883.61/19890.67	% SZS status Started for HL408042+4.p
148883.61/19890.67	% SZS status GaveUp for HL408042+4.p
148883.61/19890.67	eprover: CPU time limit exceeded, terminating
148883.61/19890.67	% SZS status Ended for HL408042+4.p
148897.47/19892.37	% SZS status Started for HL408035+5.p
148897.47/19892.37	% SZS status GaveUp for HL408035+5.p
148897.47/19892.37	eprover: CPU time limit exceeded, terminating
148897.47/19892.37	% SZS status Ended for HL408035+5.p
148897.97/19892.43	% SZS status Started for HL408043+4.p
148897.97/19892.43	% SZS status GaveUp for HL408043+4.p
148897.97/19892.43	eprover: CPU time limit exceeded, terminating
148897.97/19892.43	% SZS status Ended for HL408043+4.p
148907.11/19893.69	% SZS status Started for HL408036+5.p
148907.11/19893.69	% SZS status GaveUp for HL408036+5.p
148907.11/19893.69	eprover: CPU time limit exceeded, terminating
148907.11/19893.69	% SZS status Ended for HL408036+5.p
148908.70/19893.80	% SZS status Started for HL408044+4.p
148908.70/19893.80	% SZS status GaveUp for HL408044+4.p
148908.70/19893.80	eprover: CPU time limit exceeded, terminating
148908.70/19893.80	% SZS status Ended for HL408044+4.p
148922.06/19895.48	% SZS status Started for HL408038+5.p
148922.06/19895.48	% SZS status GaveUp for HL408038+5.p
148922.06/19895.48	eprover: CPU time limit exceeded, terminating
148922.06/19895.48	% SZS status Ended for HL408038+5.p
148922.59/19895.58	% SZS status Started for HL408046+4.p
148922.59/19895.58	% SZS status GaveUp for HL408046+4.p
148922.59/19895.58	eprover: CPU time limit exceeded, terminating
148922.59/19895.58	% SZS status Ended for HL408046+4.p
148933.03/19896.92	% SZS status Started for HL408048+4.p
148933.03/19896.92	% SZS status GaveUp for HL408048+4.p
148933.03/19896.92	eprover: CPU time limit exceeded, terminating
148933.03/19896.92	% SZS status Ended for HL408048+4.p
148937.91/19897.55	% SZS status Started for HL408041+5.p
148937.91/19897.55	% SZS status GaveUp for HL408041+5.p
148937.91/19897.55	eprover: CPU time limit exceeded, terminating
148937.91/19897.55	% SZS status Ended for HL408041+5.p
148946.91/19898.76	% SZS status Started for HL408049+4.p
148946.91/19898.76	% SZS status GaveUp for HL408049+4.p
148946.91/19898.76	eprover: CPU time limit exceeded, terminating
148946.91/19898.76	% SZS status Ended for HL408049+4.p
148947.69/19898.88	% SZS status Started for HL408042+5.p
148947.69/19898.88	% SZS status GaveUp for HL408042+5.p
148947.69/19898.88	eprover: CPU time limit exceeded, terminating
148947.69/19898.88	% SZS status Ended for HL408042+5.p
148959.75/19900.45	% SZS status Started for HL408043+5.p
148959.75/19900.45	% SZS status GaveUp for HL408043+5.p
148959.75/19900.45	eprover: CPU time limit exceeded, terminating
148959.75/19900.45	% SZS status Ended for HL408043+5.p
148963.22/19900.77	% SZS status Started for HL408050+4.p
148963.22/19900.77	% SZS status GaveUp for HL408050+4.p
148963.22/19900.77	eprover: CPU time limit exceeded, terminating
148963.22/19900.77	% SZS status Ended for HL408050+4.p
148973.09/19902.15	% SZS status Started for HL408051+4.p
148973.09/19902.15	% SZS status GaveUp for HL408051+4.p
148973.09/19902.15	eprover: CPU time limit exceeded, terminating
148973.09/19902.15	% SZS status Ended for HL408051+4.p
148979.53/19903.06	% SZS status Started for HL408044+5.p
148979.53/19903.06	% SZS status GaveUp for HL408044+5.p
148979.53/19903.06	eprover: CPU time limit exceeded, terminating
148979.53/19903.06	% SZS status Ended for HL408044+5.p
148985.08/19903.80	% SZS status Started for HL408052+4.p
148985.08/19903.80	% SZS status GaveUp for HL408052+4.p
148985.08/19903.80	eprover: CPU time limit exceeded, terminating
148985.08/19903.80	% SZS status Ended for HL408052+4.p
148992.36/19904.76	% SZS status Started for HL408046+5.p
148992.36/19904.76	% SZS status GaveUp for HL408046+5.p
148992.36/19904.76	eprover: CPU time limit exceeded, terminating
148992.36/19904.76	% SZS status Ended for HL408046+5.p
149002.61/19906.20	% SZS status Started for HL408053+4.p
149002.61/19906.20	% SZS status GaveUp for HL408053+4.p
149002.61/19906.20	eprover: CPU time limit exceeded, terminating
149002.61/19906.20	% SZS status Ended for HL408053+4.p
149010.17/19907.08	% SZS status Started for HL408048+5.p
149010.17/19907.08	% SZS status GaveUp for HL408048+5.p
149010.17/19907.08	eprover: CPU time limit exceeded, terminating
149010.17/19907.08	% SZS status Ended for HL408048+5.p
149015.11/19907.81	% SZS status Started for HL408049+5.p
149015.11/19907.81	% SZS status GaveUp for HL408049+5.p
149015.11/19907.81	eprover: CPU time limit exceeded, terminating
149015.11/19907.81	% SZS status Ended for HL408049+5.p
149016.52/19907.96	% SZS status Started for HL408054+4.p
149016.52/19907.96	% SZS status GaveUp for HL408054+4.p
149016.52/19907.96	eprover: CPU time limit exceeded, terminating
149016.52/19907.96	% SZS status Ended for HL408054+4.p
149035.25/19910.39	% SZS status Started for HL408056+4.p
149035.25/19910.39	% SZS status GaveUp for HL408056+4.p
149035.25/19910.39	eprover: CPU time limit exceeded, terminating
149035.25/19910.39	% SZS status Ended for HL408056+4.p
149035.72/19910.46	% SZS status Started for HL408050+5.p
149035.72/19910.46	% SZS status GaveUp for HL408050+5.p
149035.72/19910.46	eprover: CPU time limit exceeded, terminating
149035.72/19910.46	% SZS status Ended for HL408050+5.p
149040.86/19911.20	% SZS status Started for HL408057+4.p
149040.86/19911.20	% SZS status GaveUp for HL408057+4.p
149040.86/19911.20	eprover: CPU time limit exceeded, terminating
149040.86/19911.20	% SZS status Ended for HL408057+4.p
149042.47/19911.42	% SZS status Started for HL408051+5.p
149042.47/19911.42	% SZS status GaveUp for HL408051+5.p
149042.47/19911.42	eprover: CPU time limit exceeded, terminating
149042.47/19911.42	% SZS status Ended for HL408051+5.p
149055.75/19913.03	% SZS status Started for HL408052+5.p
149055.75/19913.03	% SZS status GaveUp for HL408052+5.p
149055.75/19913.03	eprover: CPU time limit exceeded, terminating
149055.75/19913.03	% SZS status Ended for HL408052+5.p
149059.44/19913.50	% SZS status Started for HL408058+4.p
149059.44/19913.50	% SZS status GaveUp for HL408058+4.p
149059.44/19913.50	eprover: CPU time limit exceeded, terminating
149059.44/19913.50	% SZS status Ended for HL408058+4.p
149066.64/19914.48	% SZS status Started for HL408059+4.p
149066.64/19914.48	% SZS status GaveUp for HL408059+4.p
149066.64/19914.48	eprover: CPU time limit exceeded, terminating
149066.64/19914.48	% SZS status Ended for HL408059+4.p
149070.41/19915.01	% SZS status Started for HL408053+5.p
149070.41/19915.01	% SZS status GaveUp for HL408053+5.p
149070.41/19915.01	eprover: CPU time limit exceeded, terminating
149070.41/19915.01	% SZS status Ended for HL408053+5.p
149084.42/19916.80	% SZS status Started for HL408060+4.p
149084.42/19916.80	% SZS status GaveUp for HL408060+4.p
149084.42/19916.80	eprover: CPU time limit exceeded, terminating
149084.42/19916.80	% SZS status Ended for HL408060+4.p
149088.59/19917.36	% SZS status Started for HL408054+5.p
149088.59/19917.36	% SZS status GaveUp for HL408054+5.p
149088.59/19917.36	eprover: CPU time limit exceeded, terminating
149088.59/19917.36	% SZS status Ended for HL408054+5.p
149095.03/19918.09	% SZS status Started for HL408061+4.p
149095.03/19918.09	% SZS status GaveUp for HL408061+4.p
149095.03/19918.09	eprover: CPU time limit exceeded, terminating
149095.03/19918.09	% SZS status Ended for HL408061+4.p
149099.77/19918.80	% SZS status Started for HL408056+5.p
149099.77/19918.80	% SZS status GaveUp for HL408056+5.p
149099.77/19918.80	eprover: CPU time limit exceeded, terminating
149099.77/19918.80	% SZS status Ended for HL408056+5.p
149112.67/19920.39	% SZS status Started for HL408062+4.p
149112.67/19920.39	% SZS status GaveUp for HL408062+4.p
149112.67/19920.39	eprover: CPU time limit exceeded, terminating
149112.67/19920.39	% SZS status Ended for HL408062+4.p
149121.73/19921.54	% SZS status Started for HL408057+5.p
149121.73/19921.54	% SZS status GaveUp for HL408057+5.p
149121.73/19921.54	eprover: CPU time limit exceeded, terminating
149121.73/19921.54	% SZS status Ended for HL408057+5.p
149124.05/19921.96	% SZS status Started for HL408058+5.p
149124.05/19921.96	% SZS status GaveUp for HL408058+5.p
149124.05/19921.96	eprover: CPU time limit exceeded, terminating
149124.05/19921.96	% SZS status Ended for HL408058+5.p
149124.58/19921.99	% SZS status Started for HL408063+4.p
149124.58/19921.99	% SZS status GaveUp for HL408063+4.p
149124.58/19921.99	eprover: CPU time limit exceeded, terminating
149124.58/19921.99	% SZS status Ended for HL408063+4.p
149139.42/19923.88	% SZS status Started for HL408059+5.p
149139.42/19923.88	% SZS status GaveUp for HL408059+5.p
149139.42/19923.88	eprover: CPU time limit exceeded, terminating
149139.42/19923.88	% SZS status Ended for HL408059+5.p
149147.78/19925.04	% SZS status Started for HL408064+4.p
149147.78/19925.04	% SZS status GaveUp for HL408064+4.p
149147.78/19925.04	eprover: CPU time limit exceeded, terminating
149147.78/19925.04	% SZS status Ended for HL408064+4.p
149148.28/19925.08	% SZS status Started for HL408065+4.p
149148.28/19925.08	% SZS status GaveUp for HL408065+4.p
149148.28/19925.08	eprover: CPU time limit exceeded, terminating
149148.28/19925.08	% SZS status Ended for HL408065+4.p
149151.03/19925.40	% SZS status Started for HL408060+5.p
149151.03/19925.40	% SZS status GaveUp for HL408060+5.p
149151.03/19925.40	eprover: CPU time limit exceeded, terminating
149151.03/19925.40	% SZS status Ended for HL408060+5.p
149168.47/19927.64	% SZS status Started for HL408061+5.p
149168.47/19927.64	% SZS status GaveUp for HL408061+5.p
149168.47/19927.64	eprover: CPU time limit exceeded, terminating
149168.47/19927.64	% SZS status Ended for HL408061+5.p
149171.86/19928.08	% SZS status Started for HL408066+4.p
149171.86/19928.08	% SZS status GaveUp for HL408066+4.p
149171.86/19928.08	eprover: CPU time limit exceeded, terminating
149171.86/19928.08	% SZS status Ended for HL408066+4.p
149175.27/19928.51	% SZS status Started for HL408067+4.p
149175.27/19928.51	% SZS status GaveUp for HL408067+4.p
149175.27/19928.51	eprover: CPU time limit exceeded, terminating
149175.27/19928.51	% SZS status Ended for HL408067+4.p
149182.84/19929.10	% SZS status Started for HL408062+5.p
149182.84/19929.10	% SZS status GaveUp for HL408062+5.p
149182.84/19929.10	eprover: CPU time limit exceeded, terminating
149182.84/19929.10	% SZS status Ended for HL408062+5.p
149198.27/19931.04	% SZS status Started for HL408063+5.p
149198.27/19931.04	% SZS status GaveUp for HL408063+5.p
149198.27/19931.04	eprover: CPU time limit exceeded, terminating
149198.27/19931.04	% SZS status Ended for HL408063+5.p
149199.14/19931.22	% SZS status Started for HL408068+4.p
149199.14/19931.22	% SZS status GaveUp for HL408068+4.p
149199.14/19931.22	eprover: CPU time limit exceeded, terminating
149199.14/19931.22	% SZS status Ended for HL408068+4.p
149206.50/19932.14	% SZS status Started for HL408069+4.p
149206.50/19932.14	% SZS status GaveUp for HL408069+4.p
149206.50/19932.14	eprover: CPU time limit exceeded, terminating
149206.50/19932.14	% SZS status Ended for HL408069+4.p
149213.28/19933.05	% SZS status Started for HL408064+5.p
149213.28/19933.05	% SZS status GaveUp for HL408064+5.p
149213.28/19933.05	eprover: CPU time limit exceeded, terminating
149213.28/19933.05	% SZS status Ended for HL408064+5.p
149223.94/19934.35	% SZS status Started for HL408071+4.p
149223.94/19934.35	% SZS status GaveUp for HL408071+4.p
149223.94/19934.35	eprover: CPU time limit exceeded, terminating
149223.94/19934.35	% SZS status Ended for HL408071+4.p
149227.25/19934.76	% SZS status Started for HL408065+5.p
149227.25/19934.76	% SZS status GaveUp for HL408065+5.p
149227.25/19934.76	eprover: CPU time limit exceeded, terminating
149227.25/19934.76	% SZS status Ended for HL408065+5.p
149234.30/19935.77	% SZS status Started for HL408066+5.p
149234.30/19935.77	% SZS status GaveUp for HL408066+5.p
149234.30/19935.77	eprover: CPU time limit exceeded, terminating
149234.30/19935.77	% SZS status Ended for HL408066+5.p
149237.61/19936.12	% SZS status Started for HL408072+4.p
149237.61/19936.12	% SZS status GaveUp for HL408072+4.p
149237.61/19936.12	eprover: CPU time limit exceeded, terminating
149237.61/19936.12	% SZS status Ended for HL408072+4.p
149251.84/19937.87	% SZS status Started for HL408073+4.p
149251.84/19937.87	% SZS status GaveUp for HL408073+4.p
149251.84/19937.87	eprover: CPU time limit exceeded, terminating
149251.84/19937.87	% SZS status Ended for HL408073+4.p
149256.69/19938.49	% SZS status Started for HL408067+5.p
149256.69/19938.49	% SZS status GaveUp for HL408067+5.p
149256.69/19938.49	eprover: CPU time limit exceeded, terminating
149256.69/19938.49	% SZS status Ended for HL408067+5.p
149261.19/19939.15	% SZS status Started for HL408074+4.p
149261.19/19939.15	% SZS status GaveUp for HL408074+4.p
149261.19/19939.15	eprover: CPU time limit exceeded, terminating
149261.19/19939.15	% SZS status Ended for HL408074+4.p
149261.69/19939.26	% SZS status Started for HL408068+5.p
149261.69/19939.26	% SZS status GaveUp for HL408068+5.p
149261.69/19939.26	eprover: CPU time limit exceeded, terminating
149261.69/19939.26	% SZS status Ended for HL408068+5.p
149281.31/19941.71	% SZS status Started for HL408069+5.p
149281.31/19941.71	% SZS status GaveUp for HL408069+5.p
149281.31/19941.71	eprover: CPU time limit exceeded, terminating
149281.31/19941.71	% SZS status Ended for HL408069+5.p
149282.59/19941.85	% SZS status Started for HL408075+4.p
149282.59/19941.85	% SZS status GaveUp for HL408075+4.p
149282.59/19941.85	eprover: CPU time limit exceeded, terminating
149282.59/19941.85	% SZS status Ended for HL408075+4.p
149286.84/19942.39	% SZS status Started for HL408077+4.p
149286.84/19942.39	% SZS status GaveUp for HL408077+4.p
149286.84/19942.39	eprover: CPU time limit exceeded, terminating
149286.84/19942.39	% SZS status Ended for HL408077+4.p
149291.33/19942.99	% SZS status Started for HL408071+5.p
149291.33/19942.99	% SZS status GaveUp for HL408071+5.p
149291.33/19942.99	eprover: CPU time limit exceeded, terminating
149291.33/19942.99	% SZS status Ended for HL408071+5.p
149306.11/19944.90	% SZS status Started for HL408078+4.p
149306.11/19944.90	% SZS status GaveUp for HL408078+4.p
149306.11/19944.90	eprover: CPU time limit exceeded, terminating
149306.11/19944.90	% SZS status Ended for HL408078+4.p
149309.09/19945.25	% SZS status Started for HL408072+5.p
149309.09/19945.25	% SZS status GaveUp for HL408072+5.p
149309.09/19945.25	eprover: CPU time limit exceeded, terminating
149309.09/19945.25	% SZS status Ended for HL408072+5.p
149315.05/19946.03	% SZS status Started for HL408079+4.p
149315.05/19946.03	% SZS status GaveUp for HL408079+4.p
149315.05/19946.03	eprover: CPU time limit exceeded, terminating
149315.05/19946.03	% SZS status Ended for HL408079+4.p
149320.44/19946.71	% SZS status Started for HL408073+5.p
149320.44/19946.71	% SZS status GaveUp for HL408073+5.p
149320.44/19946.71	eprover: CPU time limit exceeded, terminating
149320.44/19946.71	% SZS status Ended for HL408073+5.p
149333.12/19948.30	% SZS status Started for HL408080+4.p
149333.12/19948.30	% SZS status GaveUp for HL408080+4.p
149333.12/19948.30	eprover: CPU time limit exceeded, terminating
149333.12/19948.30	% SZS status Ended for HL408080+4.p
149335.39/19948.63	% SZS status Started for HL408074+5.p
149335.39/19948.63	% SZS status GaveUp for HL408074+5.p
149335.39/19948.63	eprover: CPU time limit exceeded, terminating
149335.39/19948.63	% SZS status Ended for HL408074+5.p
149345.31/19949.96	% SZS status Started for HL408075+5.p
149345.31/19949.96	% SZS status GaveUp for HL408075+5.p
149345.31/19949.96	eprover: CPU time limit exceeded, terminating
149345.31/19949.96	% SZS status Ended for HL408075+5.p
149346.39/19950.13	% SZS status Started for HL408081+4.p
149346.39/19950.13	% SZS status GaveUp for HL408081+4.p
149346.39/19950.13	eprover: CPU time limit exceeded, terminating
149346.39/19950.13	% SZS status Ended for HL408081+4.p
149362.56/19951.87	% SZS status Started for HL408083+4.p
149362.56/19951.87	% SZS status GaveUp for HL408083+4.p
149362.56/19951.87	eprover: CPU time limit exceeded, terminating
149362.56/19951.87	% SZS status Ended for HL408083+4.p
149367.84/19952.63	% SZS status Started for HL408077+5.p
149367.84/19952.63	% SZS status GaveUp for HL408077+5.p
149367.84/19952.63	eprover: CPU time limit exceeded, terminating
149367.84/19952.63	% SZS status Ended for HL408077+5.p
149373.28/19953.30	% SZS status Started for HL408084+4.p
149373.28/19953.30	% SZS status GaveUp for HL408084+4.p
149373.28/19953.30	eprover: CPU time limit exceeded, terminating
149373.28/19953.30	% SZS status Ended for HL408084+4.p
149377.67/19954.05	% SZS status Started for HL408078+5.p
149377.67/19954.05	% SZS status GaveUp for HL408078+5.p
149377.67/19954.05	eprover: CPU time limit exceeded, terminating
149377.67/19954.05	% SZS status Ended for HL408078+5.p
149392.00/19955.77	% SZS status Started for HL408079+5.p
149392.00/19955.77	% SZS status GaveUp for HL408079+5.p
149392.00/19955.77	eprover: CPU time limit exceeded, terminating
149392.00/19955.77	% SZS status Ended for HL408079+5.p
149394.30/19956.20	% SZS status Started for HL408086+4.p
149394.30/19956.20	% SZS status GaveUp for HL408086+4.p
149394.30/19956.20	eprover: CPU time limit exceeded, terminating
149394.30/19956.20	% SZS status Ended for HL408086+4.p
149401.98/19957.08	% SZS status Started for HL408087+4.p
149401.98/19957.08	% SZS status GaveUp for HL408087+4.p
149401.98/19957.08	eprover: CPU time limit exceeded, terminating
149401.98/19957.08	% SZS status Ended for HL408087+4.p
149402.59/19957.09	% SZS status Started for HL408080+5.p
149402.59/19957.09	% SZS status GaveUp for HL408080+5.p
149402.59/19957.09	eprover: CPU time limit exceeded, terminating
149402.59/19957.09	% SZS status Ended for HL408080+5.p
149416.80/19959.08	% SZS status Started for HL408081+5.p
149416.80/19959.08	% SZS status GaveUp for HL408081+5.p
149416.80/19959.08	eprover: CPU time limit exceeded, terminating
149416.80/19959.08	% SZS status Ended for HL408081+5.p
149420.88/19959.62	% SZS status Started for HL408088+4.p
149420.88/19959.62	% SZS status GaveUp for HL408088+4.p
149420.88/19959.62	eprover: CPU time limit exceeded, terminating
149420.88/19959.62	% SZS status Ended for HL408088+4.p
149426.83/19960.45	% SZS status Started for HL408090+4.p
149426.83/19960.45	% SZS status GaveUp for HL408090+4.p
149426.83/19960.45	eprover: CPU time limit exceeded, terminating
149426.83/19960.45	% SZS status Ended for HL408090+4.p
149431.06/19961.01	% SZS status Started for HL408083+5.p
149431.06/19961.01	% SZS status GaveUp for HL408083+5.p
149431.06/19961.01	eprover: CPU time limit exceeded, terminating
149431.06/19961.01	% SZS status Ended for HL408083+5.p
149443.08/19962.57	% SZS status Started for HL408084+5.p
149443.08/19962.57	% SZS status GaveUp for HL408084+5.p
149443.08/19962.57	eprover: CPU time limit exceeded, terminating
149443.08/19962.57	% SZS status Ended for HL408084+5.p
149454.86/19962.76	% SZS status Started for HL408091+4.p
149454.86/19962.76	% SZS status GaveUp for HL408091+4.p
149454.86/19962.76	eprover: CPU time limit exceeded, terminating
149454.86/19962.76	% SZS status Ended for HL408091+4.p
149465.41/19964.10	% SZS status Started for HL408092+4.p
149465.41/19964.10	% SZS status GaveUp for HL408092+4.p
149465.41/19964.10	eprover: CPU time limit exceeded, terminating
149465.41/19964.10	% SZS status Ended for HL408092+4.p
149465.84/19964.19	% SZS status Started for HL408086+5.p
149465.84/19964.19	% SZS status GaveUp for HL408086+5.p
149465.84/19964.19	eprover: CPU time limit exceeded, terminating
149465.84/19964.19	% SZS status Ended for HL408086+5.p
149479.25/19965.81	% SZS status Started for HL408093+4.p
149479.25/19965.81	% SZS status GaveUp for HL408093+4.p
149479.25/19965.81	eprover: CPU time limit exceeded, terminating
149479.25/19965.81	% SZS status Ended for HL408093+4.p
149486.17/19966.72	% SZS status Started for HL408087+5.p
149486.17/19966.72	% SZS status GaveUp for HL408087+5.p
149486.17/19966.72	eprover: CPU time limit exceeded, terminating
149486.17/19966.72	% SZS status Ended for HL408087+5.p
149490.66/19967.32	% SZS status Started for HL408094+4.p
149490.66/19967.32	% SZS status GaveUp for HL408094+4.p
149490.66/19967.32	eprover: CPU time limit exceeded, terminating
149490.66/19967.32	% SZS status Ended for HL408094+4.p
149496.83/19968.29	% SZS status Started for HL408088+5.p
149496.83/19968.29	% SZS status GaveUp for HL408088+5.p
149496.83/19968.29	eprover: CPU time limit exceeded, terminating
149496.83/19968.29	% SZS status Ended for HL408088+5.p
149509.33/19969.84	% SZS status Started for HL408095+4.p
149509.33/19969.84	% SZS status GaveUp for HL408095+4.p
149509.33/19969.84	eprover: CPU time limit exceeded, terminating
149509.33/19969.84	% SZS status Ended for HL408095+4.p
149515.06/19970.61	% SZS status Started for HL408090+5.p
149515.06/19970.61	% SZS status GaveUp for HL408090+5.p
149515.06/19970.61	eprover: CPU time limit exceeded, terminating
149515.06/19970.61	% SZS status Ended for HL408090+5.p
149519.16/19971.18	% SZS status Started for HL408091+5.p
149519.16/19971.18	% SZS status GaveUp for HL408091+5.p
149519.16/19971.18	eprover: CPU time limit exceeded, terminating
149519.16/19971.18	% SZS status Ended for HL408091+5.p
149520.48/19971.38	% SZS status Started for HL408096+4.p
149520.48/19971.38	% SZS status GaveUp for HL408096+4.p
149520.48/19971.38	eprover: CPU time limit exceeded, terminating
149520.48/19971.38	% SZS status Ended for HL408096+4.p
149539.83/19973.75	% SZS status Started for HL408092+5.p
149539.83/19973.75	% SZS status GaveUp for HL408092+5.p
149539.83/19973.75	eprover: CPU time limit exceeded, terminating
149539.83/19973.75	% SZS status Ended for HL408092+5.p
149540.64/19973.89	% SZS status Started for HL408097+4.p
149540.64/19973.89	% SZS status GaveUp for HL408097+4.p
149540.64/19973.89	eprover: CPU time limit exceeded, terminating
149540.64/19973.89	% SZS status Ended for HL408097+4.p
149544.89/19974.43	% SZS status Started for HL408098+4.p
149544.89/19974.43	% SZS status GaveUp for HL408098+4.p
149544.89/19974.43	eprover: CPU time limit exceeded, terminating
149544.89/19974.43	% SZS status Ended for HL408098+4.p
149548.58/19974.93	% SZS status Started for HL408093+5.p
149548.58/19974.93	% SZS status GaveUp for HL408093+5.p
149548.58/19974.93	eprover: CPU time limit exceeded, terminating
149548.58/19974.93	% SZS status Ended for HL408093+5.p
149563.14/19976.93	% SZS status Started for HL408099+4.p
149563.14/19976.93	% SZS status GaveUp for HL408099+4.p
149563.14/19976.93	eprover: CPU time limit exceeded, terminating
149563.14/19976.93	% SZS status Ended for HL408099+4.p
149568.08/19977.54	% SZS status Started for HL408094+5.p
149568.08/19977.54	% SZS status GaveUp for HL408094+5.p
149568.08/19977.54	eprover: CPU time limit exceeded, terminating
149568.08/19977.54	% SZS status Ended for HL408094+5.p
149572.34/19978.01	% SZS status Started for HL408095+5.p
149572.34/19978.01	% SZS status GaveUp for HL408095+5.p
149572.34/19978.01	eprover: CPU time limit exceeded, terminating
149572.34/19978.01	% SZS status Ended for HL408095+5.p
149572.34/19978.05	% SZS status Started for HL408100+4.p
149572.34/19978.05	% SZS status GaveUp for HL408100+4.p
149572.34/19978.05	eprover: CPU time limit exceeded, terminating
149572.34/19978.05	% SZS status Ended for HL408100+4.p
149592.36/19980.80	% SZS status Started for HL408096+5.p
149592.36/19980.80	% SZS status GaveUp for HL408096+5.p
149592.36/19980.80	eprover: CPU time limit exceeded, terminating
149592.36/19980.80	% SZS status Ended for HL408096+5.p
149592.52/19980.91	% SZS status Started for HL408101+4.p
149592.52/19980.91	% SZS status GaveUp for HL408101+4.p
149592.52/19980.91	eprover: CPU time limit exceeded, terminating
149592.52/19980.91	% SZS status Ended for HL408101+4.p
149596.81/19981.33	% SZS status Started for HL408103+4.p
149596.81/19981.33	% SZS status GaveUp for HL408103+4.p
149596.81/19981.33	eprover: CPU time limit exceeded, terminating
149596.81/19981.33	% SZS status Ended for HL408103+4.p
149606.11/19982.45	% SZS status Started for HL408097+5.p
149606.11/19982.45	% SZS status GaveUp for HL408097+5.p
149606.11/19982.45	eprover: CPU time limit exceeded, terminating
149606.11/19982.45	% SZS status Ended for HL408097+5.p
149618.28/19983.98	% SZS status Started for HL408104+4.p
149618.28/19983.98	% SZS status GaveUp for HL408104+4.p
149618.28/19983.98	eprover: CPU time limit exceeded, terminating
149618.28/19983.98	% SZS status Ended for HL408104+4.p
149623.62/19984.67	% SZS status Started for HL408098+5.p
149623.62/19984.67	% SZS status GaveUp for HL408098+5.p
149623.62/19984.67	eprover: CPU time limit exceeded, terminating
149623.62/19984.67	% SZS status Ended for HL408098+5.p
149627.55/19985.18	% SZS status Started for HL408099+5.p
149627.55/19985.18	% SZS status GaveUp for HL408099+5.p
149627.55/19985.18	eprover: CPU time limit exceeded, terminating
149627.55/19985.18	% SZS status Ended for HL408099+5.p
149629.89/19985.48	% SZS status Started for HL408106+4.p
149629.89/19985.48	% SZS status GaveUp for HL408106+4.p
149629.89/19985.48	eprover: CPU time limit exceeded, terminating
149629.89/19985.48	% SZS status Ended for HL408106+4.p
149648.09/19987.69	% SZS status Started for HL408100+5.p
149648.09/19987.69	% SZS status GaveUp for HL408100+5.p
149648.09/19987.69	eprover: CPU time limit exceeded, terminating
149648.09/19987.69	% SZS status Ended for HL408100+5.p
149648.52/19987.74	% SZS status Started for HL408108+4.p
149648.52/19987.74	% SZS status GaveUp for HL408108+4.p
149648.52/19987.74	eprover: CPU time limit exceeded, terminating
149648.52/19987.74	% SZS status Ended for HL408108+4.p
149654.11/19988.50	% SZS status Started for HL408109+4.p
149654.11/19988.50	% SZS status GaveUp for HL408109+4.p
149654.11/19988.50	eprover: CPU time limit exceeded, terminating
149654.11/19988.50	% SZS status Ended for HL408109+4.p
149655.44/19988.67	% SZS status Started for HL408101+5.p
149655.44/19988.67	% SZS status GaveUp for HL408101+5.p
149655.44/19988.67	eprover: CPU time limit exceeded, terminating
149655.44/19988.67	% SZS status Ended for HL408101+5.p
149672.77/19990.77	% SZS status Started for HL408110+4.p
149672.77/19990.77	% SZS status GaveUp for HL408110+4.p
149672.77/19990.77	eprover: CPU time limit exceeded, terminating
149672.77/19990.77	% SZS status Ended for HL408110+4.p
149679.52/19991.70	% SZS status Started for HL408111+4.p
149679.52/19991.70	% SZS status GaveUp for HL408111+4.p
149679.52/19991.70	eprover: CPU time limit exceeded, terminating
149679.52/19991.70	% SZS status Ended for HL408111+4.p
149704.08/19994.73	% SZS status Started for HL408112+4.p
149704.08/19994.73	% SZS status GaveUp for HL408112+4.p
149704.08/19994.73	eprover: CPU time limit exceeded, terminating
149704.08/19994.73	% SZS status Ended for HL408112+4.p
149800.06/20006.86	% SZS status Started for HL408103+5.p
149800.06/20006.86	% SZS status GaveUp for HL408103+5.p
149800.06/20006.86	eprover: CPU time limit exceeded, terminating
149800.06/20006.86	% SZS status Ended for HL408103+5.p
149803.50/20007.28	% SZS status Started for HL408104+5.p
149803.50/20007.28	% SZS status GaveUp for HL408104+5.p
149803.50/20007.28	eprover: CPU time limit exceeded, terminating
149803.50/20007.28	% SZS status Ended for HL408104+5.p
149824.36/20009.89	% SZS status Started for HL408113+4.p
149824.36/20009.89	% SZS status GaveUp for HL408113+4.p
149824.36/20009.89	eprover: CPU time limit exceeded, terminating
149824.36/20009.89	% SZS status Ended for HL408113+4.p
149828.97/20010.45	% SZS status Started for HL408106+5.p
149828.97/20010.45	% SZS status GaveUp for HL408106+5.p
149828.97/20010.45	eprover: CPU time limit exceeded, terminating
149828.97/20010.45	% SZS status Ended for HL408106+5.p
149833.48/20011.11	% SZS status Started for HL408108+5.p
149833.48/20011.11	% SZS status GaveUp for HL408108+5.p
149833.48/20011.11	eprover: CPU time limit exceeded, terminating
149833.48/20011.11	% SZS status Ended for HL408108+5.p
149848.91/20012.92	% SZS status Started for HL408114+4.p
149848.91/20012.92	% SZS status GaveUp for HL408114+4.p
149848.91/20012.92	eprover: CPU time limit exceeded, terminating
149848.91/20012.92	% SZS status Ended for HL408114+4.p
149854.11/20013.65	% SZS status Started for HL408109+5.p
149854.11/20013.65	% SZS status GaveUp for HL408109+5.p
149854.11/20013.65	eprover: CPU time limit exceeded, terminating
149854.11/20013.65	% SZS status Ended for HL408109+5.p
149858.22/20014.15	% SZS status Started for HL408115+4.p
149858.22/20014.15	% SZS status GaveUp for HL408115+4.p
149858.22/20014.15	eprover: CPU time limit exceeded, terminating
149858.22/20014.15	% SZS status Ended for HL408115+4.p
149860.44/20014.53	% SZS status Started for HL408110+5.p
149860.44/20014.53	% SZS status GaveUp for HL408110+5.p
149860.44/20014.53	eprover: CPU time limit exceeded, terminating
149860.44/20014.53	% SZS status Ended for HL408110+5.p
149878.59/20016.69	% SZS status Started for HL408116+4.p
149878.59/20016.69	% SZS status GaveUp for HL408116+4.p
149878.59/20016.69	eprover: CPU time limit exceeded, terminating
149878.59/20016.69	% SZS status Ended for HL408116+4.p
149879.12/20016.77	% SZS status Started for HL408111+5.p
149879.12/20016.77	% SZS status GaveUp for HL408111+5.p
149879.12/20016.77	eprover: CPU time limit exceeded, terminating
149879.12/20016.77	% SZS status Ended for HL408111+5.p
149885.45/20017.57	% SZS status Started for HL408117+4.p
149885.45/20017.57	% SZS status GaveUp for HL408117+4.p
149885.45/20017.57	eprover: CPU time limit exceeded, terminating
149885.45/20017.57	% SZS status Ended for HL408117+4.p
149888.05/20018.06	% SZS status Started for HL408113+5.p
149888.05/20018.06	% SZS status GaveUp for HL408113+5.p
149888.05/20018.06	eprover: CPU time limit exceeded, terminating
149888.05/20018.06	% SZS status Ended for HL408113+5.p
149903.02/20019.80	% SZS status Started for HL408118+4.p
149903.02/20019.80	% SZS status GaveUp for HL408118+4.p
149903.02/20019.80	eprover: CPU time limit exceeded, terminating
149903.02/20019.80	% SZS status Ended for HL408118+4.p
149909.86/20020.67	% SZS status Started for HL408112+5.p
149909.86/20020.67	% SZS status GaveUp for HL408112+5.p
149909.86/20020.67	eprover: CPU time limit exceeded, terminating
149909.86/20020.67	% SZS status Ended for HL408112+5.p
149912.14/20021.10	% SZS status Started for HL408119+4.p
149912.14/20021.10	% SZS status GaveUp for HL408119+4.p
149912.14/20021.10	eprover: CPU time limit exceeded, terminating
149912.14/20021.10	% SZS status Ended for HL408119+4.p
149917.34/20021.66	% SZS status Started for HL408114+5.p
149917.34/20021.66	% SZS status GaveUp for HL408114+5.p
149917.34/20021.66	eprover: CPU time limit exceeded, terminating
149917.34/20021.66	% SZS status Ended for HL408114+5.p
149933.56/20023.70	% SZS status Started for HL408120+4.p
149933.56/20023.70	% SZS status GaveUp for HL408120+4.p
149933.56/20023.70	eprover: CPU time limit exceeded, terminating
149933.56/20023.70	% SZS status Ended for HL408120+4.p
149935.31/20023.82	% SZS status Started for HL408115+5.p
149935.31/20023.82	% SZS status GaveUp for HL408115+5.p
149935.31/20023.82	eprover: CPU time limit exceeded, terminating
149935.31/20023.82	% SZS status Ended for HL408115+5.p
149941.55/20024.69	% SZS status Started for HL408121+4.p
149941.55/20024.69	% SZS status GaveUp for HL408121+4.p
149941.55/20024.69	eprover: CPU time limit exceeded, terminating
149941.55/20024.69	% SZS status Ended for HL408121+4.p
149944.16/20024.92	% SZS status Started for HL408116+5.p
149944.16/20024.92	% SZS status GaveUp for HL408116+5.p
149944.16/20024.92	eprover: CPU time limit exceeded, terminating
149944.16/20024.92	% SZS status Ended for HL408116+5.p
149960.52/20027.00	% SZS status Started for HL408122+4.p
149960.52/20027.00	% SZS status GaveUp for HL408122+4.p
149960.52/20027.00	eprover: CPU time limit exceeded, terminating
149960.52/20027.00	% SZS status Ended for HL408122+4.p
149963.59/20027.40	% SZS status Started for HL408117+5.p
149963.59/20027.40	% SZS status GaveUp for HL408117+5.p
149963.59/20027.40	eprover: CPU time limit exceeded, terminating
149963.59/20027.40	% SZS status Ended for HL408117+5.p
149968.23/20028.00	% SZS status Started for HL408123+4.p
149968.23/20028.00	% SZS status GaveUp for HL408123+4.p
149968.23/20028.00	eprover: CPU time limit exceeded, terminating
149968.23/20028.00	% SZS status Ended for HL408123+4.p
149970.64/20028.35	% SZS status Started for HL408118+5.p
149970.64/20028.35	% SZS status GaveUp for HL408118+5.p
149970.64/20028.35	eprover: CPU time limit exceeded, terminating
149970.64/20028.35	% SZS status Ended for HL408118+5.p
149988.33/20030.53	% SZS status Started for HL408124+4.p
149988.33/20030.53	% SZS status GaveUp for HL408124+4.p
149988.33/20030.53	eprover: CPU time limit exceeded, terminating
149988.33/20030.53	% SZS status Ended for HL408124+4.p
149988.33/20030.59	% SZS status Started for HL408119+5.p
149988.33/20030.59	% SZS status GaveUp for HL408119+5.p
149988.33/20030.59	eprover: CPU time limit exceeded, terminating
149988.33/20030.59	% SZS status Ended for HL408119+5.p
150005.17/20031.39	% SZS status Started for HL408125+4.p
150005.17/20031.39	% SZS status GaveUp for HL408125+4.p
150005.17/20031.39	eprover: CPU time limit exceeded, terminating
150005.17/20031.39	% SZS status Ended for HL408125+4.p
150008.91/20031.86	% SZS status Started for HL408120+5.p
150008.91/20031.86	% SZS status GaveUp for HL408120+5.p
150008.91/20031.86	eprover: CPU time limit exceeded, terminating
150008.91/20031.86	% SZS status Ended for HL408120+5.p
150023.08/20033.65	% SZS status Started for HL408126+4.p
150023.08/20033.65	% SZS status GaveUp for HL408126+4.p
150023.08/20033.65	eprover: CPU time limit exceeded, terminating
150023.08/20033.65	% SZS status Ended for HL408126+4.p
150029.42/20034.47	% SZS status Started for HL408121+5.p
150029.42/20034.47	% SZS status GaveUp for HL408121+5.p
150029.42/20034.47	eprover: CPU time limit exceeded, terminating
150029.42/20034.47	% SZS status Ended for HL408121+5.p
150033.23/20034.98	% SZS status Started for HL408127+4.p
150033.23/20034.98	% SZS status GaveUp for HL408127+4.p
150033.23/20034.98	eprover: CPU time limit exceeded, terminating
150033.23/20034.98	% SZS status Ended for HL408127+4.p
150037.27/20035.44	% SZS status Started for HL408122+5.p
150037.27/20035.44	% SZS status GaveUp for HL408122+5.p
150037.27/20035.44	eprover: CPU time limit exceeded, terminating
150037.27/20035.44	% SZS status Ended for HL408122+5.p
150052.95/20037.52	% SZS status Started for HL408129+4.p
150052.95/20037.52	% SZS status GaveUp for HL408129+4.p
150052.95/20037.52	eprover: CPU time limit exceeded, terminating
150052.95/20037.52	% SZS status Ended for HL408129+4.p
150056.20/20037.79	% SZS status Started for HL408123+5.p
150056.20/20037.79	% SZS status GaveUp for HL408123+5.p
150056.20/20037.79	eprover: CPU time limit exceeded, terminating
150056.20/20037.79	% SZS status Ended for HL408123+5.p
150061.22/20038.47	% SZS status Started for HL408130+4.p
150061.22/20038.47	% SZS status GaveUp for HL408130+4.p
150061.22/20038.47	eprover: CPU time limit exceeded, terminating
150061.22/20038.47	% SZS status Ended for HL408130+4.p
150063.44/20038.75	% SZS status Started for HL408124+5.p
150063.44/20038.75	% SZS status GaveUp for HL408124+5.p
150063.44/20038.75	eprover: CPU time limit exceeded, terminating
150063.44/20038.75	% SZS status Ended for HL408124+5.p
150080.06/20040.82	% SZS status Started for HL408131+4.p
150080.06/20040.82	% SZS status GaveUp for HL408131+4.p
150080.06/20040.82	eprover: CPU time limit exceeded, terminating
150080.06/20040.82	% SZS status Ended for HL408131+4.p
150083.69/20041.27	% SZS status Started for HL408125+5.p
150083.69/20041.27	% SZS status GaveUp for HL408125+5.p
150083.69/20041.27	eprover: CPU time limit exceeded, terminating
150083.69/20041.27	% SZS status Ended for HL408125+5.p
150087.92/20041.78	% SZS status Started for HL408132+4.p
150087.92/20041.78	% SZS status GaveUp for HL408132+4.p
150087.92/20041.78	eprover: CPU time limit exceeded, terminating
150087.92/20041.78	% SZS status Ended for HL408132+4.p
150090.48/20042.17	% SZS status Started for HL408126+5.p
150090.48/20042.17	% SZS status GaveUp for HL408126+5.p
150090.48/20042.17	eprover: CPU time limit exceeded, terminating
150090.48/20042.17	% SZS status Ended for HL408126+5.p
150107.73/20044.30	% SZS status Started for HL408134+4.p
150107.73/20044.30	% SZS status GaveUp for HL408134+4.p
150107.73/20044.30	eprover: CPU time limit exceeded, terminating
150107.73/20044.30	% SZS status Ended for HL408134+4.p
150108.20/20044.41	% SZS status Started for HL408127+5.p
150108.20/20044.41	% SZS status GaveUp for HL408127+5.p
150108.20/20044.41	eprover: CPU time limit exceeded, terminating
150108.20/20044.41	% SZS status Ended for HL408127+5.p
150115.02/20045.21	% SZS status Started for HL408135+4.p
150115.02/20045.21	% SZS status GaveUp for HL408135+4.p
150115.02/20045.21	eprover: CPU time limit exceeded, terminating
150115.02/20045.21	% SZS status Ended for HL408135+4.p
150123.55/20046.25	% SZS status Started for HL408129+5.p
150123.55/20046.25	% SZS status GaveUp for HL408129+5.p
150123.55/20046.25	eprover: CPU time limit exceeded, terminating
150123.55/20046.25	% SZS status Ended for HL408129+5.p
150132.58/20047.45	% SZS status Started for HL408136+4.p
150132.58/20047.45	% SZS status GaveUp for HL408136+4.p
150132.58/20047.45	eprover: CPU time limit exceeded, terminating
150132.58/20047.45	% SZS status Ended for HL408136+4.p
150139.55/20048.28	% SZS status Started for HL408130+5.p
150139.55/20048.28	% SZS status GaveUp for HL408130+5.p
150139.55/20048.28	eprover: CPU time limit exceeded, terminating
150139.55/20048.28	% SZS status Ended for HL408130+5.p
150147.72/20049.33	% SZS status Started for HL408131+5.p
150147.72/20049.33	% SZS status GaveUp for HL408131+5.p
150147.72/20049.33	eprover: CPU time limit exceeded, terminating
150147.72/20049.33	% SZS status Ended for HL408131+5.p
150148.17/20049.39	% SZS status Started for HL408137+4.p
150148.17/20049.39	% SZS status GaveUp for HL408137+4.p
150148.17/20049.39	eprover: CPU time limit exceeded, terminating
150148.17/20049.39	% SZS status Ended for HL408137+4.p
150163.02/20051.37	% SZS status Started for HL408139+4.p
150163.02/20051.37	% SZS status GaveUp for HL408139+4.p
150163.02/20051.37	eprover: CPU time limit exceeded, terminating
150163.02/20051.37	% SZS status Ended for HL408139+4.p
150165.33/20051.57	% SZS status Started for HL408132+5.p
150165.33/20051.57	% SZS status GaveUp for HL408132+5.p
150165.33/20051.57	eprover: CPU time limit exceeded, terminating
150165.33/20051.57	% SZS status Ended for HL408132+5.p
150172.28/20052.43	% SZS status Started for HL408140+4.p
150172.28/20052.43	% SZS status GaveUp for HL408140+4.p
150172.28/20052.43	eprover: CPU time limit exceeded, terminating
150172.28/20052.43	% SZS status Ended for HL408140+4.p
150172.72/20052.55	% SZS status Started for HL408134+5.p
150172.72/20052.55	% SZS status GaveUp for HL408134+5.p
150172.72/20052.55	eprover: CPU time limit exceeded, terminating
150172.72/20052.55	% SZS status Ended for HL408134+5.p
150188.75/20054.60	% SZS status Started for HL408141+4.p
150188.75/20054.60	% SZS status GaveUp for HL408141+4.p
150188.75/20054.60	eprover: CPU time limit exceeded, terminating
150188.75/20054.60	% SZS status Ended for HL408141+4.p
150193.34/20055.07	% SZS status Started for HL408135+5.p
150193.34/20055.07	% SZS status GaveUp for HL408135+5.p
150193.34/20055.07	eprover: CPU time limit exceeded, terminating
150193.34/20055.07	% SZS status Ended for HL408135+5.p
150197.11/20055.58	% SZS status Started for HL408142+4.p
150197.11/20055.58	% SZS status GaveUp for HL408142+4.p
150197.11/20055.58	eprover: CPU time limit exceeded, terminating
150197.11/20055.58	% SZS status Ended for HL408142+4.p
150200.38/20055.96	% SZS status Started for HL408136+5.p
150200.38/20055.96	% SZS status GaveUp for HL408136+5.p
150200.38/20055.96	eprover: CPU time limit exceeded, terminating
150200.38/20055.96	% SZS status Ended for HL408136+5.p
150217.23/20058.10	% SZS status Started for HL408143+4.p
150217.23/20058.10	% SZS status GaveUp for HL408143+4.p
150217.23/20058.10	eprover: CPU time limit exceeded, terminating
150217.23/20058.10	% SZS status Ended for HL408143+4.p
150218.91/20058.27	% SZS status Started for HL408137+5.p
150218.91/20058.27	% SZS status GaveUp for HL408137+5.p
150218.91/20058.27	eprover: CPU time limit exceeded, terminating
150218.91/20058.27	% SZS status Ended for HL408137+5.p
150224.58/20058.99	% SZS status Started for HL408144+4.p
150224.58/20058.99	% SZS status GaveUp for HL408144+4.p
150224.58/20058.99	eprover: CPU time limit exceeded, terminating
150224.58/20058.99	% SZS status Ended for HL408144+4.p
150234.56/20060.32	% SZS status Started for HL408139+5.p
150234.56/20060.32	% SZS status GaveUp for HL408139+5.p
150234.56/20060.32	eprover: CPU time limit exceeded, terminating
150234.56/20060.32	% SZS status Ended for HL408139+5.p
150242.16/20061.31	% SZS status Started for HL408145+4.p
150242.16/20061.31	% SZS status GaveUp for HL408145+4.p
150242.16/20061.31	eprover: CPU time limit exceeded, terminating
150242.16/20061.31	% SZS status Ended for HL408145+4.p
150250.38/20062.13	% SZS status Started for HL408140+5.p
150250.38/20062.13	% SZS status GaveUp for HL408140+5.p
150250.38/20062.13	eprover: CPU time limit exceeded, terminating
150250.38/20062.13	% SZS status Ended for HL408140+5.p
150258.70/20063.19	% SZS status Started for HL408141+5.p
150258.70/20063.19	% SZS status GaveUp for HL408141+5.p
150258.70/20063.19	eprover: CPU time limit exceeded, terminating
150258.70/20063.19	% SZS status Ended for HL408141+5.p
150259.89/20063.35	% SZS status Started for HL408146+4.p
150259.89/20063.35	% SZS status GaveUp for HL408146+4.p
150259.89/20063.35	eprover: CPU time limit exceeded, terminating
150259.89/20063.35	% SZS status Ended for HL408146+4.p
150274.11/20065.16	% SZS status Started for HL408147+4.p
150274.11/20065.16	% SZS status GaveUp for HL408147+4.p
150274.11/20065.16	eprover: CPU time limit exceeded, terminating
150274.11/20065.16	% SZS status Ended for HL408147+4.p
150278.69/20065.73	% SZS status Started for HL408142+5.p
150278.69/20065.73	% SZS status GaveUp for HL408142+5.p
150278.69/20065.73	eprover: CPU time limit exceeded, terminating
150278.69/20065.73	% SZS status Ended for HL408142+5.p
150283.95/20066.39	% SZS status Started for HL408148+4.p
150283.95/20066.39	% SZS status GaveUp for HL408148+4.p
150283.95/20066.39	eprover: CPU time limit exceeded, terminating
150283.95/20066.39	% SZS status Ended for HL408148+4.p
150284.95/20066.51	% SZS status Started for HL408143+5.p
150284.95/20066.51	% SZS status GaveUp for HL408143+5.p
150284.95/20066.51	eprover: CPU time limit exceeded, terminating
150284.95/20066.51	% SZS status Ended for HL408143+5.p
150302.86/20068.76	% SZS status Started for HL408149+4.p
150302.86/20068.76	% SZS status GaveUp for HL408149+4.p
150302.86/20068.76	eprover: CPU time limit exceeded, terminating
150302.86/20068.76	% SZS status Ended for HL408149+4.p
150306.34/20068.85	% SZS status Started for HL408144+5.p
150306.34/20068.85	% SZS status GaveUp for HL408144+5.p
150306.34/20068.85	eprover: CPU time limit exceeded, terminating
150306.34/20068.85	% SZS status Ended for HL408144+5.p
150312.19/20069.57	% SZS status Started for HL408150+4.p
150312.19/20069.57	% SZS status GaveUp for HL408150+4.p
150312.19/20069.57	eprover: CPU time limit exceeded, terminating
150312.19/20069.57	% SZS status Ended for HL408150+4.p
150313.45/20069.76	% SZS status Started for HL408145+5.p
150313.45/20069.76	% SZS status GaveUp for HL408145+5.p
150313.45/20069.76	eprover: CPU time limit exceeded, terminating
150313.45/20069.76	% SZS status Ended for HL408145+5.p
150331.14/20071.95	% SZS status Started for HL408151+4.p
150331.14/20071.95	% SZS status GaveUp for HL408151+4.p
150331.14/20071.95	eprover: CPU time limit exceeded, terminating
150331.14/20071.95	% SZS status Ended for HL408151+4.p
150332.14/20072.09	% SZS status Started for HL408146+5.p
150332.14/20072.09	% SZS status GaveUp for HL408146+5.p
150332.14/20072.09	eprover: CPU time limit exceeded, terminating
150332.14/20072.09	% SZS status Ended for HL408146+5.p
150337.72/20072.79	% SZS status Started for HL408152+4.p
150337.72/20072.79	% SZS status GaveUp for HL408152+4.p
150337.72/20072.79	eprover: CPU time limit exceeded, terminating
150337.72/20072.79	% SZS status Ended for HL408152+4.p
150344.70/20073.94	% SZS status Started for HL408147+5.p
150344.70/20073.94	% SZS status GaveUp for HL408147+5.p
150344.70/20073.94	eprover: CPU time limit exceeded, terminating
150344.70/20073.94	% SZS status Ended for HL408147+5.p
150356.05/20075.12	% SZS status Started for HL408153+4.p
150356.05/20075.12	% SZS status GaveUp for HL408153+4.p
150356.05/20075.12	eprover: CPU time limit exceeded, terminating
150356.05/20075.12	% SZS status Ended for HL408153+4.p
150362.30/20075.94	% SZS status Started for HL408148+5.p
150362.30/20075.94	% SZS status GaveUp for HL408148+5.p
150362.30/20075.94	eprover: CPU time limit exceeded, terminating
150362.30/20075.94	% SZS status Ended for HL408148+5.p
150371.80/20077.13	% SZS status Started for HL408154+4.p
150371.80/20077.13	% SZS status GaveUp for HL408154+4.p
150371.80/20077.13	eprover: CPU time limit exceeded, terminating
150371.80/20077.13	% SZS status Ended for HL408154+4.p
150373.47/20077.28	% SZS status Started for HL408149+5.p
150373.47/20077.28	% SZS status GaveUp for HL408149+5.p
150373.47/20077.28	eprover: CPU time limit exceeded, terminating
150373.47/20077.28	% SZS status Ended for HL408149+5.p
150386.98/20078.97	% SZS status Started for HL408156+4.p
150386.98/20078.97	% SZS status GaveUp for HL408156+4.p
150386.98/20078.97	eprover: CPU time limit exceeded, terminating
150386.98/20078.97	% SZS status Ended for HL408156+4.p
150390.86/20079.52	% SZS status Started for HL408150+5.p
150390.86/20079.52	% SZS status GaveUp for HL408150+5.p
150390.86/20079.52	eprover: CPU time limit exceeded, terminating
150390.86/20079.52	% SZS status Ended for HL408150+5.p
150398.38/20080.40	% SZS status Started for HL408157+4.p
150398.38/20080.40	% SZS status GaveUp for HL408157+4.p
150398.38/20080.40	eprover: CPU time limit exceeded, terminating
150398.38/20080.40	% SZS status Ended for HL408157+4.p
150398.78/20080.47	% SZS status Started for HL408151+5.p
150398.78/20080.47	% SZS status GaveUp for HL408151+5.p
150398.78/20080.47	eprover: CPU time limit exceeded, terminating
150398.78/20080.47	% SZS status Ended for HL408151+5.p
150415.17/20082.55	% SZS status Started for HL408158+4.p
150415.17/20082.55	% SZS status GaveUp for HL408158+4.p
150415.17/20082.55	eprover: CPU time limit exceeded, terminating
150415.17/20082.55	% SZS status Ended for HL408158+4.p
150416.00/20082.72	% SZS status Started for HL408152+5.p
150416.00/20082.72	% SZS status GaveUp for HL408152+5.p
150416.00/20082.72	eprover: CPU time limit exceeded, terminating
150416.00/20082.72	% SZS status Ended for HL408152+5.p
150422.45/20083.50	% SZS status Started for HL408159+4.p
150422.45/20083.50	% SZS status GaveUp for HL408159+4.p
150422.45/20083.50	eprover: CPU time limit exceeded, terminating
150422.45/20083.50	% SZS status Ended for HL408159+4.p
150422.45/20083.56	% SZS status Started for HL408153+5.p
150422.45/20083.56	% SZS status GaveUp for HL408153+5.p
150422.45/20083.56	eprover: CPU time limit exceeded, terminating
150422.45/20083.56	% SZS status Ended for HL408153+5.p
150440.94/20085.76	% SZS status Started for HL408161+4.p
150440.94/20085.76	% SZS status GaveUp for HL408161+4.p
150440.94/20085.76	eprover: CPU time limit exceeded, terminating
150440.94/20085.76	% SZS status Ended for HL408161+4.p
150441.61/20085.90	% SZS status Started for HL408154+5.p
150441.61/20085.90	% SZS status GaveUp for HL408154+5.p
150441.61/20085.90	eprover: CPU time limit exceeded, terminating
150441.61/20085.90	% SZS status Ended for HL408154+5.p
150457.73/20086.59	% SZS status Started for HL408162+4.p
150457.73/20086.59	% SZS status GaveUp for HL408162+4.p
150457.73/20086.59	eprover: CPU time limit exceeded, terminating
150457.73/20086.59	% SZS status Ended for HL408162+4.p
150467.83/20087.91	% SZS status Started for HL408156+5.p
150467.83/20087.91	% SZS status GaveUp for HL408156+5.p
150467.83/20087.91	eprover: CPU time limit exceeded, terminating
150467.83/20087.91	% SZS status Ended for HL408156+5.p
150475.78/20088.93	% SZS status Started for HL408163+4.p
150475.78/20088.93	% SZS status GaveUp for HL408163+4.p
150475.78/20088.93	eprover: CPU time limit exceeded, terminating
150475.78/20088.93	% SZS status Ended for HL408163+4.p
150486.81/20090.28	% SZS status Started for HL408157+5.p
150486.81/20090.28	% SZS status GaveUp for HL408157+5.p
150486.81/20090.28	eprover: CPU time limit exceeded, terminating
150486.81/20090.28	% SZS status Ended for HL408157+5.p
150491.42/20090.94	% SZS status Started for HL408164+4.p
150491.42/20090.94	% SZS status GaveUp for HL408164+4.p
150491.42/20090.94	eprover: CPU time limit exceeded, terminating
150491.42/20090.94	% SZS status Ended for HL408164+4.p
150494.09/20091.16	% SZS status Started for HL408158+5.p
150494.09/20091.16	% SZS status GaveUp for HL408158+5.p
150494.09/20091.16	eprover: CPU time limit exceeded, terminating
150494.09/20091.16	% SZS status Ended for HL408158+5.p
150511.03/20093.31	% SZS status Started for HL408159+5.p
150511.03/20093.31	% SZS status GaveUp for HL408159+5.p
150511.03/20093.31	eprover: CPU time limit exceeded, terminating
150511.03/20093.31	% SZS status Ended for HL408159+5.p
150511.44/20093.47	% SZS status Started for HL408165+4.p
150511.44/20093.47	% SZS status GaveUp for HL408165+4.p
150511.44/20093.47	eprover: CPU time limit exceeded, terminating
150511.44/20093.47	% SZS status Ended for HL408165+4.p
150517.83/20094.20	% SZS status Started for HL408166+4.p
150517.83/20094.20	% SZS status GaveUp for HL408166+4.p
150517.83/20094.20	eprover: CPU time limit exceeded, terminating
150517.83/20094.20	% SZS status Ended for HL408166+4.p
150518.59/20094.25	% SZS status Started for HL408161+5.p
150518.59/20094.25	% SZS status GaveUp for HL408161+5.p
150518.59/20094.25	eprover: CPU time limit exceeded, terminating
150518.59/20094.25	% SZS status Ended for HL408161+5.p
150535.88/20096.50	% SZS status Started for HL408167+4.p
150535.88/20096.50	% SZS status GaveUp for HL408167+4.p
150535.88/20096.50	eprover: CPU time limit exceeded, terminating
150535.88/20096.50	% SZS status Ended for HL408167+4.p
150536.88/20096.56	% SZS status Started for HL408162+5.p
150536.88/20096.56	% SZS status GaveUp for HL408162+5.p
150536.88/20096.56	eprover: CPU time limit exceeded, terminating
150536.88/20096.56	% SZS status Ended for HL408162+5.p
150542.25/20097.28	% SZS status Started for HL408168+4.p
150542.25/20097.28	% SZS status GaveUp for HL408168+4.p
150542.25/20097.28	eprover: CPU time limit exceeded, terminating
150542.25/20097.28	% SZS status Ended for HL408168+4.p
150542.62/20097.34	% SZS status Started for HL408163+5.p
150542.62/20097.34	% SZS status GaveUp for HL408163+5.p
150542.62/20097.34	eprover: CPU time limit exceeded, terminating
150542.62/20097.34	% SZS status Ended for HL408163+5.p
150560.61/20099.59	% SZS status Started for HL408171+4.p
150560.61/20099.59	% SZS status GaveUp for HL408171+4.p
150560.61/20099.59	eprover: CPU time limit exceeded, terminating
150560.61/20099.59	% SZS status Ended for HL408171+4.p
150561.80/20099.70	% SZS status Started for HL408164+5.p
150561.80/20099.70	% SZS status GaveUp for HL408164+5.p
150561.80/20099.70	eprover: CPU time limit exceeded, terminating
150561.80/20099.70	% SZS status Ended for HL408164+5.p
150566.62/20100.38	% SZS status Started for HL408172+4.p
150566.62/20100.38	% SZS status GaveUp for HL408172+4.p
150566.62/20100.38	eprover: CPU time limit exceeded, terminating
150566.62/20100.38	% SZS status Ended for HL408172+4.p
150580.30/20101.71	% SZS status Started for HL408165+5.p
150580.30/20101.71	% SZS status GaveUp for HL408165+5.p
150580.30/20101.71	eprover: CPU time limit exceeded, terminating
150580.30/20101.71	% SZS status Ended for HL408165+5.p
150586.95/20102.73	% SZS status Started for HL408174+4.p
150586.95/20102.73	% SZS status GaveUp for HL408174+4.p
150586.95/20102.73	eprover: CPU time limit exceeded, terminating
150586.95/20102.73	% SZS status Ended for HL408174+4.p
150603.30/20104.58	% SZS status Started for HL408166+5.p
150603.30/20104.58	% SZS status GaveUp for HL408166+5.p
150603.30/20104.58	eprover: CPU time limit exceeded, terminating
150603.30/20104.58	% SZS status Ended for HL408166+5.p
150604.33/20104.74	% SZS status Started for HL408175+4.p
150604.33/20104.74	% SZS status GaveUp for HL408175+4.p
150604.33/20104.74	eprover: CPU time limit exceeded, terminating
150604.33/20104.74	% SZS status Ended for HL408175+4.p
150605.64/20104.95	% SZS status Started for HL408167+5.p
150605.64/20104.95	% SZS status GaveUp for HL408167+5.p
150605.64/20104.95	eprover: CPU time limit exceeded, terminating
150605.64/20104.95	% SZS status Ended for HL408167+5.p
150623.98/20107.24	% SZS status Started for HL408168+5.p
150623.98/20107.24	% SZS status GaveUp for HL408168+5.p
150623.98/20107.24	eprover: CPU time limit exceeded, terminating
150623.98/20107.24	% SZS status Ended for HL408168+5.p
150636.30/20107.62	% SZS status Started for HL408176+4.p
150636.30/20107.62	% SZS status GaveUp for HL408176+4.p
150636.30/20107.62	eprover: CPU time limit exceeded, terminating
150636.30/20107.62	% SZS status Ended for HL408176+4.p
150640.34/20108.00	% SZS status Started for HL408177+4.p
150640.34/20108.00	% SZS status GaveUp for HL408177+4.p
150640.34/20108.00	eprover: CPU time limit exceeded, terminating
150640.34/20108.00	% SZS status Ended for HL408177+4.p
150641.75/20108.23	% SZS status Started for HL408171+5.p
150641.75/20108.23	% SZS status GaveUp for HL408171+5.p
150641.75/20108.23	eprover: CPU time limit exceeded, terminating
150641.75/20108.23	% SZS status Ended for HL408171+5.p
150658.72/20110.32	% SZS status Started for HL408172+5.p
150658.72/20110.32	% SZS status GaveUp for HL408172+5.p
150658.72/20110.32	eprover: CPU time limit exceeded, terminating
150658.72/20110.32	% SZS status Ended for HL408172+5.p
150660.78/20110.65	% SZS status Started for HL408178+4.p
150660.78/20110.65	% SZS status GaveUp for HL408178+4.p
150660.78/20110.65	eprover: CPU time limit exceeded, terminating
150660.78/20110.65	% SZS status Ended for HL408178+4.p
150664.84/20111.13	% SZS status Started for HL408174+5.p
150664.84/20111.13	% SZS status GaveUp for HL408174+5.p
150664.84/20111.13	eprover: CPU time limit exceeded, terminating
150664.84/20111.13	% SZS status Ended for HL408174+5.p
150666.77/20111.41	% SZS status Started for HL408179+4.p
150666.77/20111.41	% SZS status GaveUp for HL408179+4.p
150666.77/20111.41	eprover: CPU time limit exceeded, terminating
150666.77/20111.41	% SZS status Ended for HL408179+4.p
150684.09/20113.51	% SZS status Started for HL408175+5.p
150684.09/20113.51	% SZS status GaveUp for HL408175+5.p
150684.09/20113.51	eprover: CPU time limit exceeded, terminating
150684.09/20113.51	% SZS status Ended for HL408175+5.p
150685.44/20113.68	% SZS status Started for HL408180+4.p
150685.44/20113.68	% SZS status GaveUp for HL408180+4.p
150685.44/20113.68	eprover: CPU time limit exceeded, terminating
150685.44/20113.68	% SZS status Ended for HL408180+4.p
150692.75/20114.61	% SZS status Started for HL408181+4.p
150692.75/20114.61	% SZS status GaveUp for HL408181+4.p
150692.75/20114.61	eprover: CPU time limit exceeded, terminating
150692.75/20114.61	% SZS status Ended for HL408181+4.p
150700.14/20115.53	% SZS status Started for HL408176+5.p
150700.14/20115.53	% SZS status GaveUp for HL408176+5.p
150700.14/20115.53	eprover: CPU time limit exceeded, terminating
150700.14/20115.53	% SZS status Ended for HL408176+5.p
150709.06/20116.72	% SZS status Started for HL408182+4.p
150709.06/20116.72	% SZS status GaveUp for HL408182+4.p
150709.06/20116.72	eprover: CPU time limit exceeded, terminating
150709.06/20116.72	% SZS status Ended for HL408182+4.p
150720.34/20118.04	% SZS status Started for HL408177+5.p
150720.34/20118.04	% SZS status GaveUp for HL408177+5.p
150720.34/20118.04	eprover: CPU time limit exceeded, terminating
150720.34/20118.04	% SZS status Ended for HL408177+5.p
150725.17/20118.66	% SZS status Started for HL408183+4.p
150725.17/20118.66	% SZS status GaveUp for HL408183+4.p
150725.17/20118.66	eprover: CPU time limit exceeded, terminating
150725.17/20118.66	% SZS status Ended for HL408183+4.p
150725.67/20118.76	% SZS status Started for HL408178+5.p
150725.67/20118.76	% SZS status GaveUp for HL408178+5.p
150725.67/20118.76	eprover: CPU time limit exceeded, terminating
150725.67/20118.76	% SZS status Ended for HL408178+5.p
150744.34/20121.08	% SZS status Started for HL408179+5.p
150744.34/20121.08	% SZS status GaveUp for HL408179+5.p
150744.34/20121.08	eprover: CPU time limit exceeded, terminating
150744.34/20121.08	% SZS status Ended for HL408179+5.p
150744.34/20121.09	% SZS status Started for HL408184+4.p
150744.34/20121.09	% SZS status GaveUp for HL408184+4.p
150744.34/20121.09	eprover: CPU time limit exceeded, terminating
150744.34/20121.09	% SZS status Ended for HL408184+4.p
150751.12/20121.89	% SZS status Started for HL408180+5.p
150751.12/20121.89	% SZS status GaveUp for HL408180+5.p
150751.12/20121.89	eprover: CPU time limit exceeded, terminating
150751.12/20121.89	% SZS status Ended for HL408180+5.p
150751.12/20121.92	% SZS status Started for HL408185+4.p
150751.12/20121.92	% SZS status GaveUp for HL408185+4.p
150751.12/20121.92	eprover: CPU time limit exceeded, terminating
150751.12/20121.92	% SZS status Ended for HL408185+4.p
150768.47/20124.13	% SZS status Started for HL408186+4.p
150768.47/20124.13	% SZS status GaveUp for HL408186+4.p
150768.47/20124.13	eprover: CPU time limit exceeded, terminating
150768.47/20124.13	% SZS status Ended for HL408186+4.p
150770.09/20124.33	% SZS status Started for HL408181+5.p
150770.09/20124.33	% SZS status GaveUp for HL408181+5.p
150770.09/20124.33	eprover: CPU time limit exceeded, terminating
150770.09/20124.33	% SZS status Ended for HL408181+5.p
150775.39/20125.00	% SZS status Started for HL408187+4.p
150775.39/20125.00	% SZS status GaveUp for HL408187+4.p
150775.39/20125.00	eprover: CPU time limit exceeded, terminating
150775.39/20125.00	% SZS status Ended for HL408187+4.p
150778.72/20125.37	% SZS status Started for HL408182+5.p
150778.72/20125.37	% SZS status GaveUp for HL408182+5.p
150778.72/20125.37	eprover: CPU time limit exceeded, terminating
150778.72/20125.37	% SZS status Ended for HL408182+5.p
150794.38/20127.36	% SZS status Started for HL408189+4.p
150794.38/20127.36	% SZS status GaveUp for HL408189+4.p
150794.38/20127.36	eprover: CPU time limit exceeded, terminating
150794.38/20127.36	% SZS status Ended for HL408189+4.p
150794.80/20127.44	% SZS status Started for HL408183+5.p
150794.80/20127.44	% SZS status GaveUp for HL408183+5.p
150794.80/20127.44	eprover: CPU time limit exceeded, terminating
150794.80/20127.44	% SZS status Ended for HL408183+5.p
150802.39/20128.44	% SZS status Started for HL408190+4.p
150802.39/20128.44	% SZS status GaveUp for HL408190+4.p
150802.39/20128.44	eprover: CPU time limit exceeded, terminating
150802.39/20128.44	% SZS status Ended for HL408190+4.p
150808.77/20129.19	% SZS status Started for HL408184+5.p
150808.77/20129.19	% SZS status GaveUp for HL408184+5.p
150808.77/20129.19	eprover: CPU time limit exceeded, terminating
150808.77/20129.19	% SZS status Ended for HL408184+5.p
150819.30/20130.50	% SZS status Started for HL408191+4.p
150819.30/20130.50	% SZS status GaveUp for HL408191+4.p
150819.30/20130.50	eprover: CPU time limit exceeded, terminating
150819.30/20130.50	% SZS status Ended for HL408191+4.p
150833.20/20132.23	% SZS status Started for HL408192+4.p
150833.20/20132.23	% SZS status GaveUp for HL408192+4.p
150833.20/20132.23	eprover: CPU time limit exceeded, terminating
150833.20/20132.23	% SZS status Ended for HL408192+4.p
150857.19/20135.26	% SZS status Started for HL408194+4.p
150857.19/20135.26	% SZS status GaveUp for HL408194+4.p
150857.19/20135.26	eprover: CPU time limit exceeded, terminating
150857.19/20135.26	% SZS status Ended for HL408194+4.p
150904.77/20141.27	% SZS status Started for HL408192+5.p
150904.77/20141.27	% SZS status GaveUp for HL408192+5.p
150904.77/20141.27	eprover: CPU time limit exceeded, terminating
150904.77/20141.27	% SZS status Ended for HL408192+5.p
150928.55/20144.30	% SZS status Started for HL408195+4.p
150928.55/20144.30	% SZS status GaveUp for HL408195+4.p
150928.55/20144.30	eprover: CPU time limit exceeded, terminating
150928.55/20144.30	% SZS status Ended for HL408195+4.p
150942.33/20146.03	% SZS status Started for HL408194+5.p
150942.33/20146.03	% SZS status GaveUp for HL408194+5.p
150942.33/20146.03	eprover: CPU time limit exceeded, terminating
150942.33/20146.03	% SZS status Ended for HL408194+5.p
150951.16/20147.12	% SZS status Started for HL408185+5.p
150951.16/20147.12	% SZS status GaveUp for HL408185+5.p
150951.16/20147.12	eprover: CPU time limit exceeded, terminating
150951.16/20147.12	% SZS status Ended for HL408185+5.p
150957.50/20147.92	% SZS status Started for HL408186+5.p
150957.50/20147.92	% SZS status GaveUp for HL408186+5.p
150957.50/20147.92	eprover: CPU time limit exceeded, terminating
150957.50/20147.92	% SZS status Ended for HL408186+5.p
150966.89/20149.07	% SZS status Started for HL408196+4.p
150966.89/20149.07	% SZS status GaveUp for HL408196+4.p
150966.89/20149.07	eprover: CPU time limit exceeded, terminating
150966.89/20149.07	% SZS status Ended for HL408196+4.p
150981.47/20150.94	% SZS status Started for HL408189+5.p
150981.47/20150.94	% SZS status GaveUp for HL408189+5.p
150981.47/20150.94	eprover: CPU time limit exceeded, terminating
150981.47/20150.94	% SZS status Ended for HL408189+5.p
150981.73/20150.96	% SZS status Started for HL408197+4.p
150981.73/20150.96	% SZS status GaveUp for HL408197+4.p
150981.73/20150.96	eprover: CPU time limit exceeded, terminating
150981.73/20150.96	% SZS status Ended for HL408197+4.p
150984.19/20151.26	% SZS status Started for HL408187+5.p
150984.19/20151.26	% SZS status GaveUp for HL408187+5.p
150984.19/20151.26	eprover: CPU time limit exceeded, terminating
150984.19/20151.26	% SZS status Ended for HL408187+5.p
151000.53/20153.38	% SZS status Started for HL408190+5.p
151000.53/20153.38	% SZS status GaveUp for HL408190+5.p
151000.53/20153.38	eprover: CPU time limit exceeded, terminating
151000.53/20153.38	% SZS status Ended for HL408190+5.p
151004.75/20153.97	% SZS status Started for HL408198+4.p
151004.75/20153.97	% SZS status GaveUp for HL408198+4.p
151004.75/20153.97	eprover: CPU time limit exceeded, terminating
151004.75/20153.97	% SZS status Ended for HL408198+4.p
151008.67/20154.40	% SZS status Started for HL408199+4.p
151008.67/20154.40	% SZS status GaveUp for HL408199+4.p
151008.67/20154.40	eprover: CPU time limit exceeded, terminating
151008.67/20154.40	% SZS status Ended for HL408199+4.p
151009.06/20154.42	% SZS status Started for HL408191+5.p
151009.06/20154.42	% SZS status GaveUp for HL408191+5.p
151009.06/20154.42	eprover: CPU time limit exceeded, terminating
151009.06/20154.42	% SZS status Ended for HL408191+5.p
151013.92/20155.06	% SZS status Started for HL408195+5.p
151013.92/20155.06	% SZS status GaveUp for HL408195+5.p
151013.92/20155.06	eprover: CPU time limit exceeded, terminating
151013.92/20155.06	% SZS status Ended for HL408195+5.p
151030.14/20157.03	% SZS status Started for HL408200+4.p
151030.14/20157.03	% SZS status GaveUp for HL408200+4.p
151030.14/20157.03	eprover: CPU time limit exceeded, terminating
151030.14/20157.03	% SZS status Ended for HL408200+4.p
151033.02/20157.49	% SZS status Started for HL408201+4.p
151033.02/20157.49	% SZS status GaveUp for HL408201+4.p
151033.02/20157.49	eprover: CPU time limit exceeded, terminating
151033.02/20157.49	% SZS status Ended for HL408201+4.p
151036.22/20157.84	% SZS status Started for HL408196+5.p
151036.22/20157.84	% SZS status GaveUp for HL408196+5.p
151036.22/20157.84	eprover: CPU time limit exceeded, terminating
151036.22/20157.84	% SZS status Ended for HL408196+5.p
151051.97/20159.82	% SZS status Started for HL408197+5.p
151051.97/20159.82	% SZS status GaveUp for HL408197+5.p
151051.97/20159.82	eprover: CPU time limit exceeded, terminating
151051.97/20159.82	% SZS status Ended for HL408197+5.p
151064.80/20160.22	% SZS status Started for HL408202+4.p
151064.80/20160.22	% SZS status GaveUp for HL408202+4.p
151064.80/20160.22	eprover: CPU time limit exceeded, terminating
151064.80/20160.22	% SZS status Ended for HL408202+4.p
151070.77/20160.88	% SZS status Started for HL408203+4.p
151070.77/20160.88	% SZS status GaveUp for HL408203+4.p
151070.77/20160.88	eprover: CPU time limit exceeded, terminating
151070.77/20160.88	% SZS status Ended for HL408203+4.p
151077.20/20161.68	% SZS status Started for HL408198+5.p
151077.20/20161.68	% SZS status GaveUp for HL408198+5.p
151077.20/20161.68	eprover: CPU time limit exceeded, terminating
151077.20/20161.68	% SZS status Ended for HL408198+5.p
151089.78/20163.26	% SZS status Started for HL408204+4.p
151089.78/20163.26	% SZS status GaveUp for HL408204+4.p
151089.78/20163.26	eprover: CPU time limit exceeded, terminating
151089.78/20163.26	% SZS status Ended for HL408204+4.p
151096.38/20164.13	% SZS status Started for HL408199+5.p
151096.38/20164.13	% SZS status GaveUp for HL408199+5.p
151096.38/20164.13	eprover: CPU time limit exceeded, terminating
151096.38/20164.13	% SZS status Ended for HL408199+5.p
151101.00/20164.72	% SZS status Started for HL408207+4.p
151101.00/20164.72	% SZS status GaveUp for HL408207+4.p
151101.00/20164.72	eprover: CPU time limit exceeded, terminating
151101.00/20164.72	% SZS status Ended for HL408207+4.p
151103.75/20165.01	% SZS status Started for HL408200+5.p
151103.75/20165.01	% SZS status GaveUp for HL408200+5.p
151103.75/20165.01	eprover: CPU time limit exceeded, terminating
151103.75/20165.01	% SZS status Ended for HL408200+5.p
151110.62/20165.90	% SZS status Started for HL408201+5.p
151110.62/20165.90	% SZS status GaveUp for HL408201+5.p
151110.62/20165.90	eprover: CPU time limit exceeded, terminating
151110.62/20165.90	% SZS status Ended for HL408201+5.p
151120.17/20167.16	% SZS status Started for HL408208+4.p
151120.17/20167.16	% SZS status GaveUp for HL408208+4.p
151120.17/20167.16	eprover: CPU time limit exceeded, terminating
151120.17/20167.16	% SZS status Ended for HL408208+4.p
151127.94/20168.05	% SZS status Started for HL408209+4.p
151127.94/20168.05	% SZS status GaveUp for HL408209+4.p
151127.94/20168.05	eprover: CPU time limit exceeded, terminating
151127.94/20168.05	% SZS status Ended for HL408209+4.p
151128.77/20168.20	% SZS status Started for HL408202+5.p
151128.77/20168.20	% SZS status GaveUp for HL408202+5.p
151128.77/20168.20	eprover: CPU time limit exceeded, terminating
151128.77/20168.20	% SZS status Ended for HL408202+5.p
151144.78/20170.19	% SZS status Started for HL408210+4.p
151144.78/20170.19	% SZS status GaveUp for HL408210+4.p
151144.78/20170.19	eprover: CPU time limit exceeded, terminating
151144.78/20170.19	% SZS status Ended for HL408210+4.p
151151.34/20171.07	% SZS status Started for HL408203+5.p
151151.34/20171.07	% SZS status GaveUp for HL408203+5.p
151151.34/20171.07	eprover: CPU time limit exceeded, terminating
151151.34/20171.07	% SZS status Ended for HL408203+5.p
151153.17/20171.25	% SZS status Started for HL408211+4.p
151153.17/20171.25	% SZS status GaveUp for HL408211+4.p
151153.17/20171.25	eprover: CPU time limit exceeded, terminating
151153.17/20171.25	% SZS status Ended for HL408211+4.p
151155.30/20171.59	% SZS status Started for HL408204+5.p
151155.30/20171.59	% SZS status GaveUp for HL408204+5.p
151155.30/20171.59	eprover: CPU time limit exceeded, terminating
151155.30/20171.59	% SZS status Ended for HL408204+5.p
151173.94/20173.96	% SZS status Started for HL408207+5.p
151173.94/20173.96	% SZS status GaveUp for HL408207+5.p
151173.94/20173.96	eprover: CPU time limit exceeded, terminating
151173.94/20173.96	% SZS status Ended for HL408207+5.p
151174.56/20174.10	% SZS status Started for HL408212+4.p
151174.56/20174.10	% SZS status GaveUp for HL408212+4.p
151174.56/20174.10	eprover: CPU time limit exceeded, terminating
151174.56/20174.10	% SZS status Ended for HL408212+4.p
151179.19/20174.63	% SZS status Started for HL408213+4.p
151179.19/20174.63	% SZS status GaveUp for HL408213+4.p
151179.19/20174.63	eprover: CPU time limit exceeded, terminating
151179.19/20174.63	% SZS status Ended for HL408213+4.p
151185.50/20175.34	% SZS status Started for HL408208+5.p
151185.50/20175.34	% SZS status GaveUp for HL408208+5.p
151185.50/20175.34	eprover: CPU time limit exceeded, terminating
151185.50/20175.34	% SZS status Ended for HL408208+5.p
151196.58/20176.77	% SZS status Started for HL408209+5.p
151196.58/20176.77	% SZS status GaveUp for HL408209+5.p
151196.58/20176.77	eprover: CPU time limit exceeded, terminating
151196.58/20176.77	% SZS status Ended for HL408209+5.p
151199.77/20177.14	% SZS status Started for HL408214+4.p
151199.77/20177.14	% SZS status GaveUp for HL408214+4.p
151199.77/20177.14	eprover: CPU time limit exceeded, terminating
151199.77/20177.14	% SZS status Ended for HL408214+4.p
151209.88/20178.38	% SZS status Started for HL408216+4.p
151209.88/20178.38	% SZS status GaveUp for HL408216+4.p
151209.88/20178.38	eprover: CPU time limit exceeded, terminating
151209.88/20178.38	% SZS status Ended for HL408216+4.p
151213.84/20178.88	% SZS status Started for HL408210+5.p
151213.84/20178.88	% SZS status GaveUp for HL408210+5.p
151213.84/20178.88	eprover: CPU time limit exceeded, terminating
151213.84/20178.88	% SZS status Ended for HL408210+5.p
151223.50/20180.18	% SZS status Started for HL408217+4.p
151223.50/20180.18	% SZS status GaveUp for HL408217+4.p
151223.50/20180.18	eprover: CPU time limit exceeded, terminating
151223.50/20180.18	% SZS status Ended for HL408217+4.p
151230.47/20181.08	% SZS status Started for HL408211+5.p
151230.47/20181.08	% SZS status GaveUp for HL408211+5.p
151230.47/20181.08	eprover: CPU time limit exceeded, terminating
151230.47/20181.08	% SZS status Ended for HL408211+5.p
151236.48/20181.92	% SZS status Started for HL408218+4.p
151236.48/20181.92	% SZS status GaveUp for HL408218+4.p
151236.48/20181.92	eprover: CPU time limit exceeded, terminating
151236.48/20181.92	% SZS status Ended for HL408218+4.p
151236.48/20181.97	% SZS status Started for HL408212+5.p
151236.48/20181.97	% SZS status GaveUp for HL408212+5.p
151236.48/20181.97	eprover: CPU time limit exceeded, terminating
151236.48/20181.97	% SZS status Ended for HL408212+5.p
151254.83/20184.12	% SZS status Started for HL408219+4.p
151254.83/20184.12	% SZS status GaveUp for HL408219+4.p
151254.83/20184.12	eprover: CPU time limit exceeded, terminating
151254.83/20184.12	% SZS status Ended for HL408219+4.p
151259.20/20184.84	% SZS status Started for HL408213+5.p
151259.20/20184.84	% SZS status GaveUp for HL408213+5.p
151259.20/20184.84	eprover: CPU time limit exceeded, terminating
151259.20/20184.84	% SZS status Ended for HL408213+5.p
151262.59/20185.02	% SZS status Started for HL408220+4.p
151262.59/20185.02	% SZS status GaveUp for HL408220+4.p
151262.59/20185.02	eprover: CPU time limit exceeded, terminating
151262.59/20185.02	% SZS status Ended for HL408220+4.p
151265.14/20185.37	% SZS status Started for HL408214+5.p
151265.14/20185.37	% SZS status GaveUp for HL408214+5.p
151265.14/20185.37	eprover: CPU time limit exceeded, terminating
151265.14/20185.37	% SZS status Ended for HL408214+5.p
151281.78/20187.47	% SZS status Started for HL408216+5.p
151281.78/20187.47	% SZS status GaveUp for HL408216+5.p
151281.78/20187.47	eprover: CPU time limit exceeded, terminating
151281.78/20187.47	% SZS status Ended for HL408216+5.p
151284.83/20187.87	% SZS status Started for HL408222+4.p
151284.83/20187.87	% SZS status GaveUp for HL408222+4.p
151284.83/20187.87	eprover: CPU time limit exceeded, terminating
151284.83/20187.87	% SZS status Ended for HL408222+4.p
151289.09/20188.41	% SZS status Started for HL408223+4.p
151289.09/20188.41	% SZS status GaveUp for HL408223+4.p
151289.09/20188.41	eprover: CPU time limit exceeded, terminating
151289.09/20188.41	% SZS status Ended for HL408223+4.p
151299.22/20189.67	% SZS status Started for HL408217+5.p
151299.22/20189.67	% SZS status GaveUp for HL408217+5.p
151299.22/20189.67	eprover: CPU time limit exceeded, terminating
151299.22/20189.67	% SZS status Ended for HL408217+5.p
151308.28/20190.83	% SZS status Started for HL408218+5.p
151308.28/20190.83	% SZS status GaveUp for HL408218+5.p
151308.28/20190.83	eprover: CPU time limit exceeded, terminating
151308.28/20190.83	% SZS status Ended for HL408218+5.p
151308.59/20190.94	% SZS status Started for HL408224+4.p
151308.59/20190.94	% SZS status GaveUp for HL408224+4.p
151308.59/20190.94	eprover: CPU time limit exceeded, terminating
151308.59/20190.94	% SZS status Ended for HL408224+4.p
151323.12/20192.64	% SZS status Started for HL408219+5.p
151323.12/20192.64	% SZS status GaveUp for HL408219+5.p
151323.12/20192.64	eprover: CPU time limit exceeded, terminating
151323.12/20192.64	% SZS status Ended for HL408219+5.p
151323.91/20192.75	% SZS status Started for HL408225+4.p
151323.91/20192.75	% SZS status GaveUp for HL408225+4.p
151323.91/20192.75	eprover: CPU time limit exceeded, terminating
151323.91/20192.75	% SZS status Ended for HL408225+4.p
151335.03/20194.16	% SZS status Started for HL408226+4.p
151335.03/20194.16	% SZS status GaveUp for HL408226+4.p
151335.03/20194.16	eprover: CPU time limit exceeded, terminating
151335.03/20194.16	% SZS status Ended for HL408226+4.p
151340.48/20194.83	% SZS status Started for HL408220+5.p
151340.48/20194.83	% SZS status GaveUp for HL408220+5.p
151340.48/20194.83	eprover: CPU time limit exceeded, terminating
151340.48/20194.83	% SZS status Ended for HL408220+5.p
151347.75/20195.74	% SZS status Started for HL408222+5.p
151347.75/20195.74	% SZS status GaveUp for HL408222+5.p
151347.75/20195.74	eprover: CPU time limit exceeded, terminating
151347.75/20195.74	% SZS status Ended for HL408222+5.p
151348.72/20195.89	% SZS status Started for HL408227+4.p
151348.72/20195.89	% SZS status GaveUp for HL408227+4.p
151348.72/20195.89	eprover: CPU time limit exceeded, terminating
151348.72/20195.89	% SZS status Ended for HL408227+4.p
151364.62/20197.87	% SZS status Started for HL408228+4.p
151364.62/20197.87	% SZS status GaveUp for HL408228+4.p
151364.62/20197.87	eprover: CPU time limit exceeded, terminating
151364.62/20197.87	% SZS status Ended for HL408228+4.p
151367.14/20198.26	% SZS status Started for HL408223+5.p
151367.14/20198.26	% SZS status GaveUp for HL408223+5.p
151367.14/20198.26	eprover: CPU time limit exceeded, terminating
151367.14/20198.26	% SZS status Ended for HL408223+5.p
151373.00/20198.94	% SZS status Started for HL408229+4.p
151373.00/20198.94	% SZS status GaveUp for HL408229+4.p
151373.00/20198.94	eprover: CPU time limit exceeded, terminating
151373.00/20198.94	% SZS status Ended for HL408229+4.p
151374.08/20199.08	% SZS status Started for HL408224+5.p
151374.08/20199.08	% SZS status GaveUp for HL408224+5.p
151374.08/20199.08	eprover: CPU time limit exceeded, terminating
151374.08/20199.08	% SZS status Ended for HL408224+5.p
151391.61/20201.29	% SZS status Started for HL408230+4.p
151391.61/20201.29	% SZS status GaveUp for HL408230+4.p
151391.61/20201.29	eprover: CPU time limit exceeded, terminating
151391.61/20201.29	% SZS status Ended for HL408230+4.p
151392.86/20201.54	% SZS status Started for HL408225+5.p
151392.86/20201.54	% SZS status GaveUp for HL408225+5.p
151392.86/20201.54	eprover: CPU time limit exceeded, terminating
151392.86/20201.54	% SZS status Ended for HL408225+5.p
151397.97/20202.12	% SZS status Started for HL408231+4.p
151397.97/20202.12	% SZS status GaveUp for HL408231+4.p
151397.97/20202.12	eprover: CPU time limit exceeded, terminating
151397.97/20202.12	% SZS status Ended for HL408231+4.p
151408.08/20203.34	% SZS status Started for HL408226+5.p
151408.08/20203.34	% SZS status GaveUp for HL408226+5.p
151408.08/20203.34	eprover: CPU time limit exceeded, terminating
151408.08/20203.34	% SZS status Ended for HL408226+5.p
151417.91/20204.58	% SZS status Started for HL408232+4.p
151417.91/20204.58	% SZS status GaveUp for HL408232+4.p
151417.91/20204.58	eprover: CPU time limit exceeded, terminating
151417.91/20204.58	% SZS status Ended for HL408232+4.p
151419.20/20204.91	% SZS status Started for HL408227+5.p
151419.20/20204.91	% SZS status GaveUp for HL408227+5.p
151419.20/20204.91	eprover: CPU time limit exceeded, terminating
151419.20/20204.91	% SZS status Ended for HL408227+5.p
151432.70/20206.48	% SZS status Started for HL408228+5.p
151432.70/20206.48	% SZS status GaveUp for HL408228+5.p
151432.70/20206.48	eprover: CPU time limit exceeded, terminating
151432.70/20206.48	% SZS status Ended for HL408228+5.p
151433.28/20206.52	% SZS status Started for HL408233+4.p
151433.28/20206.52	% SZS status GaveUp for HL408233+4.p
151433.28/20206.52	eprover: CPU time limit exceeded, terminating
151433.28/20206.52	% SZS status Ended for HL408233+4.p
151444.11/20207.94	% SZS status Started for HL408234+4.p
151444.11/20207.94	% SZS status GaveUp for HL408234+4.p
151444.11/20207.94	eprover: CPU time limit exceeded, terminating
151444.11/20207.94	% SZS status Ended for HL408234+4.p
151451.75/20208.90	% SZS status Started for HL408229+5.p
151451.75/20208.90	% SZS status GaveUp for HL408229+5.p
151451.75/20208.90	eprover: CPU time limit exceeded, terminating
151451.75/20208.90	% SZS status Ended for HL408229+5.p
151457.81/20209.64	% SZS status Started for HL408235+4.p
151457.81/20209.64	% SZS status GaveUp for HL408235+4.p
151457.81/20209.64	eprover: CPU time limit exceeded, terminating
151457.81/20209.64	% SZS status Ended for HL408235+4.p
151458.39/20209.66	% SZS status Started for HL408230+5.p
151458.39/20209.66	% SZS status GaveUp for HL408230+5.p
151458.39/20209.66	eprover: CPU time limit exceeded, terminating
151458.39/20209.66	% SZS status Ended for HL408230+5.p
151476.80/20212.00	% SZS status Started for HL408231+5.p
151476.80/20212.00	% SZS status GaveUp for HL408231+5.p
151476.80/20212.00	eprover: CPU time limit exceeded, terminating
151476.80/20212.00	% SZS status Ended for HL408231+5.p
151476.97/20212.12	% SZS status Started for HL408236+4.p
151476.97/20212.12	% SZS status GaveUp for HL408236+4.p
151476.97/20212.12	eprover: CPU time limit exceeded, terminating
151476.97/20212.12	% SZS status Ended for HL408236+4.p
151482.06/20212.70	% SZS status Started for HL408238+4.p
151482.06/20212.70	% SZS status GaveUp for HL408238+4.p
151482.06/20212.70	eprover: CPU time limit exceeded, terminating
151482.06/20212.70	% SZS status Ended for HL408238+4.p
151483.02/20212.83	% SZS status Started for HL408232+5.p
151483.02/20212.83	% SZS status GaveUp for HL408232+5.p
151483.02/20212.83	eprover: CPU time limit exceeded, terminating
151483.02/20212.83	% SZS status Ended for HL408232+5.p
151501.83/20215.17	% SZS status Started for HL408239+4.p
151501.83/20215.17	% SZS status GaveUp for HL408239+4.p
151501.83/20215.17	eprover: CPU time limit exceeded, terminating
151501.83/20215.17	% SZS status Ended for HL408239+4.p
151502.92/20215.32	% SZS status Started for HL408233+5.p
151502.92/20215.32	% SZS status GaveUp for HL408233+5.p
151502.92/20215.32	eprover: CPU time limit exceeded, terminating
151502.92/20215.32	% SZS status Ended for HL408233+5.p
151507.61/20215.88	% SZS status Started for HL408240+4.p
151507.61/20215.88	% SZS status GaveUp for HL408240+4.p
151507.61/20215.88	eprover: CPU time limit exceeded, terminating
151507.61/20215.88	% SZS status Ended for HL408240+4.p
151520.39/20217.47	% SZS status Started for HL408234+5.p
151520.39/20217.47	% SZS status GaveUp for HL408234+5.p
151520.39/20217.47	eprover: CPU time limit exceeded, terminating
151520.39/20217.47	% SZS status Ended for HL408234+5.p
151526.92/20218.36	% SZS status Started for HL408241+4.p
151526.92/20218.36	% SZS status GaveUp for HL408241+4.p
151526.92/20218.36	eprover: CPU time limit exceeded, terminating
151526.92/20218.36	% SZS status Ended for HL408241+4.p
151529.36/20218.65	% SZS status Started for HL408235+5.p
151529.36/20218.65	% SZS status GaveUp for HL408235+5.p
151529.36/20218.65	eprover: CPU time limit exceeded, terminating
151529.36/20218.65	% SZS status Ended for HL408235+5.p
151543.33/20220.36	% SZS status Started for HL408236+5.p
151543.33/20220.36	% SZS status GaveUp for HL408236+5.p
151543.33/20220.36	eprover: CPU time limit exceeded, terminating
151543.33/20220.36	% SZS status Ended for HL408236+5.p
151545.08/20220.66	% SZS status Started for HL408242+4.p
151545.08/20220.66	% SZS status GaveUp for HL408242+4.p
151545.08/20220.66	eprover: CPU time limit exceeded, terminating
151545.08/20220.66	% SZS status Ended for HL408242+4.p
151553.81/20221.70	% SZS status Started for HL408244+4.p
151553.81/20221.70	% SZS status GaveUp for HL408244+4.p
151553.81/20221.70	eprover: CPU time limit exceeded, terminating
151553.81/20221.70	% SZS status Ended for HL408244+4.p
151561.45/20222.74	% SZS status Started for HL408238+5.p
151561.45/20222.74	% SZS status GaveUp for HL408238+5.p
151561.45/20222.74	eprover: CPU time limit exceeded, terminating
151561.45/20222.74	% SZS status Ended for HL408238+5.p
151567.94/20223.50	% SZS status Started for HL408239+5.p
151567.94/20223.50	% SZS status GaveUp for HL408239+5.p
151567.94/20223.50	eprover: CPU time limit exceeded, terminating
151567.94/20223.50	% SZS status Ended for HL408239+5.p
151569.94/20223.75	% SZS status Started for HL408246+4.p
151569.94/20223.75	% SZS status GaveUp for HL408246+4.p
151569.94/20223.75	eprover: CPU time limit exceeded, terminating
151569.94/20223.75	% SZS status Ended for HL408246+4.p
151585.89/20225.77	% SZS status Started for HL408247+4.p
151585.89/20225.77	% SZS status GaveUp for HL408247+4.p
151585.89/20225.77	eprover: CPU time limit exceeded, terminating
151585.89/20225.77	% SZS status Ended for HL408247+4.p
151587.28/20225.92	% SZS status Started for HL408240+5.p
151587.28/20225.92	% SZS status GaveUp for HL408240+5.p
151587.28/20225.92	eprover: CPU time limit exceeded, terminating
151587.28/20225.92	% SZS status Ended for HL408240+5.p
151592.64/20226.61	% SZS status Started for HL408241+5.p
151592.64/20226.61	% SZS status GaveUp for HL408241+5.p
151592.64/20226.61	eprover: CPU time limit exceeded, terminating
151592.64/20226.61	% SZS status Ended for HL408241+5.p
151593.80/20226.79	% SZS status Started for HL408249+4.p
151593.80/20226.79	% SZS status GaveUp for HL408249+4.p
151593.80/20226.79	eprover: CPU time limit exceeded, terminating
151593.80/20226.79	% SZS status Ended for HL408249+4.p
151611.38/20228.95	% SZS status Started for HL408250+4.p
151611.38/20228.95	% SZS status GaveUp for HL408250+4.p
151611.38/20228.95	eprover: CPU time limit exceeded, terminating
151611.38/20228.95	% SZS status Ended for HL408250+4.p
151612.17/20229.01	% SZS status Started for HL408242+5.p
151612.17/20229.01	% SZS status GaveUp for HL408242+5.p
151612.17/20229.01	eprover: CPU time limit exceeded, terminating
151612.17/20229.01	% SZS status Ended for HL408242+5.p
151616.94/20229.83	% SZS status Started for HL408251+4.p
151616.94/20229.83	% SZS status GaveUp for HL408251+4.p
151616.94/20229.83	eprover: CPU time limit exceeded, terminating
151616.94/20229.83	% SZS status Ended for HL408251+4.p
151628.58/20231.12	% SZS status Started for HL408244+5.p
151628.58/20231.12	% SZS status GaveUp for HL408244+5.p
151628.58/20231.12	eprover: CPU time limit exceeded, terminating
151628.58/20231.12	% SZS status Ended for HL408244+5.p
151635.36/20232.04	% SZS status Started for HL408253+4.p
151635.36/20232.04	% SZS status GaveUp for HL408253+4.p
151635.36/20232.04	eprover: CPU time limit exceeded, terminating
151635.36/20232.04	% SZS status Ended for HL408253+4.p
151639.75/20232.66	% SZS status Started for HL408246+5.p
151639.75/20232.66	% SZS status GaveUp for HL408246+5.p
151639.75/20232.66	eprover: CPU time limit exceeded, terminating
151639.75/20232.66	% SZS status Ended for HL408246+5.p
151652.55/20234.16	% SZS status Started for HL408254+4.p
151652.55/20234.16	% SZS status GaveUp for HL408254+4.p
151652.55/20234.16	eprover: CPU time limit exceeded, terminating
151652.55/20234.16	% SZS status Ended for HL408254+4.p
151658.55/20235.01	% SZS status Started for HL408247+5.p
151658.55/20235.01	% SZS status GaveUp for HL408247+5.p
151658.55/20235.01	eprover: CPU time limit exceeded, terminating
151658.55/20235.01	% SZS status Ended for HL408247+5.p
151665.00/20235.70	% SZS status Started for HL408256+4.p
151665.00/20235.70	% SZS status GaveUp for HL408256+4.p
151665.00/20235.70	eprover: CPU time limit exceeded, terminating
151665.00/20235.70	% SZS status Ended for HL408256+4.p
151671.27/20236.50	% SZS status Started for HL408249+5.p
151671.27/20236.50	% SZS status GaveUp for HL408249+5.p
151671.27/20236.50	eprover: CPU time limit exceeded, terminating
151671.27/20236.50	% SZS status Ended for HL408249+5.p
151678.16/20237.35	% SZS status Started for HL408250+5.p
151678.16/20237.35	% SZS status GaveUp for HL408250+5.p
151678.16/20237.35	eprover: CPU time limit exceeded, terminating
151678.16/20237.35	% SZS status Ended for HL408250+5.p
151682.64/20238.06	% SZS status Started for HL408257+4.p
151682.64/20238.06	% SZS status GaveUp for HL408257+4.p
151682.64/20238.06	eprover: CPU time limit exceeded, terminating
151682.64/20238.06	% SZS status Ended for HL408257+4.p
151695.38/20239.54	% SZS status Started for HL408258+4.p
151695.38/20239.54	% SZS status GaveUp for HL408258+4.p
151695.38/20239.54	eprover: CPU time limit exceeded, terminating
151695.38/20239.54	% SZS status Ended for HL408258+4.p
151696.55/20239.68	% SZS status Started for HL408251+5.p
151696.55/20239.68	% SZS status GaveUp for HL408251+5.p
151696.55/20239.68	eprover: CPU time limit exceeded, terminating
151696.55/20239.68	% SZS status Ended for HL408251+5.p
151705.28/20240.75	% SZS status Started for HL408253+5.p
151705.28/20240.75	% SZS status GaveUp for HL408253+5.p
151705.28/20240.75	eprover: CPU time limit exceeded, terminating
151705.28/20240.75	% SZS status Ended for HL408253+5.p
151707.81/20241.10	% SZS status Started for HL408259+4.p
151707.81/20241.10	% SZS status GaveUp for HL408259+4.p
151707.81/20241.10	eprover: CPU time limit exceeded, terminating
151707.81/20241.10	% SZS status Ended for HL408259+4.p
151720.75/20242.71	% SZS status Started for HL408260+4.p
151720.75/20242.71	% SZS status GaveUp for HL408260+4.p
151720.75/20242.71	eprover: CPU time limit exceeded, terminating
151720.75/20242.71	% SZS status Ended for HL408260+4.p
151721.12/20242.76	% SZS status Started for HL408254+5.p
151721.12/20242.76	% SZS status GaveUp for HL408254+5.p
151721.12/20242.76	eprover: CPU time limit exceeded, terminating
151721.12/20242.76	% SZS status Ended for HL408254+5.p
151732.48/20244.29	% SZS status Started for HL408261+4.p
151732.48/20244.29	% SZS status GaveUp for HL408261+4.p
151732.48/20244.29	eprover: CPU time limit exceeded, terminating
151732.48/20244.29	% SZS status Ended for HL408261+4.p
151737.34/20244.85	% SZS status Started for HL408256+5.p
151737.34/20244.85	% SZS status GaveUp for HL408256+5.p
151737.34/20244.85	eprover: CPU time limit exceeded, terminating
151737.34/20244.85	% SZS status Ended for HL408256+5.p
151745.33/20245.80	% SZS status Started for HL408262+4.p
151745.33/20245.80	% SZS status GaveUp for HL408262+4.p
151745.33/20245.80	eprover: CPU time limit exceeded, terminating
151745.33/20245.80	% SZS status Ended for HL408262+4.p
151749.81/20246.40	% SZS status Started for HL408257+5.p
151749.81/20246.40	% SZS status GaveUp for HL408257+5.p
151749.81/20246.40	eprover: CPU time limit exceeded, terminating
151749.81/20246.40	% SZS status Ended for HL408257+5.p
151761.75/20247.88	% SZS status Started for HL408264+4.p
151761.75/20247.88	% SZS status GaveUp for HL408264+4.p
151761.75/20247.88	eprover: CPU time limit exceeded, terminating
151761.75/20247.88	% SZS status Ended for HL408264+4.p
151763.05/20248.08	% SZS status Started for HL408258+5.p
151763.05/20248.08	% SZS status GaveUp for HL408258+5.p
151763.05/20248.08	eprover: CPU time limit exceeded, terminating
151763.05/20248.08	% SZS status Ended for HL408258+5.p
151774.05/20249.44	% SZS status Started for HL408265+4.p
151774.05/20249.44	% SZS status GaveUp for HL408265+4.p
151774.05/20249.44	eprover: CPU time limit exceeded, terminating
151774.05/20249.44	% SZS status Ended for HL408265+4.p
151780.39/20250.26	% SZS status Started for HL408259+5.p
151780.39/20250.26	% SZS status GaveUp for HL408259+5.p
151780.39/20250.26	eprover: CPU time limit exceeded, terminating
151780.39/20250.26	% SZS status Ended for HL408259+5.p
151787.53/20251.14	% SZS status Started for HL408266+4.p
151787.53/20251.14	% SZS status GaveUp for HL408266+4.p
151787.53/20251.14	eprover: CPU time limit exceeded, terminating
151787.53/20251.14	% SZS status Ended for HL408266+4.p
151792.00/20251.67	% SZS status Started for HL408260+5.p
151792.00/20251.67	% SZS status GaveUp for HL408260+5.p
151792.00/20251.67	eprover: CPU time limit exceeded, terminating
151792.00/20251.67	% SZS status Ended for HL408260+5.p
151804.42/20253.31	% SZS status Started for HL408267+4.p
151804.42/20253.31	% SZS status GaveUp for HL408267+4.p
151804.42/20253.31	eprover: CPU time limit exceeded, terminating
151804.42/20253.31	% SZS status Ended for HL408267+4.p
151805.58/20253.43	% SZS status Started for HL408261+5.p
151805.58/20253.43	% SZS status GaveUp for HL408261+5.p
151805.58/20253.43	eprover: CPU time limit exceeded, terminating
151805.58/20253.43	% SZS status Ended for HL408261+5.p
151815.06/20254.70	% SZS status Started for HL408269+4.p
151815.06/20254.70	% SZS status GaveUp for HL408269+4.p
151815.06/20254.70	eprover: CPU time limit exceeded, terminating
151815.06/20254.70	% SZS status Ended for HL408269+4.p
151819.78/20255.22	% SZS status Started for HL408262+5.p
151819.78/20255.22	% SZS status GaveUp for HL408262+5.p
151819.78/20255.22	eprover: CPU time limit exceeded, terminating
151819.78/20255.22	% SZS status Ended for HL408262+5.p
151829.14/20256.46	% SZS status Started for HL408271+4.p
151829.14/20256.46	% SZS status GaveUp for HL408271+4.p
151829.14/20256.46	eprover: CPU time limit exceeded, terminating
151829.14/20256.46	% SZS status Ended for HL408271+4.p
151829.70/20256.48	% SZS status Started for HL408264+5.p
151829.70/20256.48	% SZS status GaveUp for HL408264+5.p
151829.70/20256.48	eprover: CPU time limit exceeded, terminating
151829.70/20256.48	% SZS status Ended for HL408264+5.p
151844.48/20258.28	% SZS status Started for HL408272+4.p
151844.48/20258.28	% SZS status GaveUp for HL408272+4.p
151844.48/20258.28	eprover: CPU time limit exceeded, terminating
151844.48/20258.28	% SZS status Ended for HL408272+4.p
151845.52/20258.46	% SZS status Started for HL408265+5.p
151845.52/20258.46	% SZS status GaveUp for HL408265+5.p
151845.52/20258.46	eprover: CPU time limit exceeded, terminating
151845.52/20258.46	% SZS status Ended for HL408265+5.p
151854.34/20259.52	% SZS status Started for HL408273+4.p
151854.34/20259.52	% SZS status GaveUp for HL408273+4.p
151854.34/20259.52	eprover: CPU time limit exceeded, terminating
151854.34/20259.52	% SZS status Ended for HL408273+4.p
151869.31/20261.51	% SZS status Started for HL408274+4.p
151869.31/20261.51	% SZS status GaveUp for HL408274+4.p
151869.31/20261.51	eprover: CPU time limit exceeded, terminating
151869.31/20261.51	% SZS status Ended for HL408274+4.p
151893.73/20264.54	% SZS status Started for HL408275+4.p
151893.73/20264.54	% SZS status GaveUp for HL408275+4.p
151893.73/20264.54	eprover: CPU time limit exceeded, terminating
151893.73/20264.54	% SZS status Ended for HL408275+4.p
151984.69/20275.74	% SZS status Started for HL408266+5.p
151984.69/20275.74	% SZS status GaveUp for HL408266+5.p
151984.69/20275.74	eprover: CPU time limit exceeded, terminating
151984.69/20275.74	% SZS status Ended for HL408266+5.p
151997.67/20277.30	% SZS status Started for HL408267+5.p
151997.67/20277.30	% SZS status GaveUp for HL408267+5.p
151997.67/20277.30	eprover: CPU time limit exceeded, terminating
151997.67/20277.30	% SZS status Ended for HL408267+5.p
152009.45/20278.85	% SZS status Started for HL408276+4.p
152009.45/20278.85	% SZS status GaveUp for HL408276+4.p
152009.45/20278.85	eprover: CPU time limit exceeded, terminating
152009.45/20278.85	% SZS status Ended for HL408276+4.p
152014.62/20279.45	% SZS status Started for HL408269+5.p
152014.62/20279.45	% SZS status GaveUp for HL408269+5.p
152014.62/20279.45	eprover: CPU time limit exceeded, terminating
152014.62/20279.45	% SZS status Ended for HL408269+5.p
152024.77/20280.77	% SZS status Started for HL408271+5.p
152024.77/20280.77	% SZS status GaveUp for HL408271+5.p
152024.77/20280.77	eprover: CPU time limit exceeded, terminating
152024.77/20280.77	% SZS status Ended for HL408271+5.p
152033.73/20281.89	% SZS status Started for HL408277+4.p
152033.73/20281.89	% SZS status GaveUp for HL408277+4.p
152033.73/20281.89	eprover: CPU time limit exceeded, terminating
152033.73/20281.89	% SZS status Ended for HL408277+4.p
152038.94/20282.50	% SZS status Started for HL408272+5.p
152038.94/20282.50	% SZS status GaveUp for HL408272+5.p
152038.94/20282.50	eprover: CPU time limit exceeded, terminating
152038.94/20282.50	% SZS status Ended for HL408272+5.p
152049.53/20283.86	% SZS status Started for HL408278+4.p
152049.53/20283.86	% SZS status GaveUp for HL408278+4.p
152049.53/20283.86	eprover: CPU time limit exceeded, terminating
152049.53/20283.86	% SZS status Ended for HL408278+4.p
152051.52/20284.22	% SZS status Started for HL408273+5.p
152051.52/20284.22	% SZS status GaveUp for HL408273+5.p
152051.52/20284.22	eprover: CPU time limit exceeded, terminating
152051.52/20284.22	% SZS status Ended for HL408273+5.p
152062.34/20285.50	% SZS status Started for HL408274+5.p
152062.34/20285.50	% SZS status GaveUp for HL408274+5.p
152062.34/20285.50	eprover: CPU time limit exceeded, terminating
152062.34/20285.50	% SZS status Ended for HL408274+5.p
152062.34/20285.54	% SZS status Started for HL408279+4.p
152062.34/20285.54	% SZS status GaveUp for HL408279+4.p
152062.34/20285.54	eprover: CPU time limit exceeded, terminating
152062.34/20285.54	% SZS status Ended for HL408279+4.p
152076.66/20287.26	% SZS status Started for HL408280+4.p
152076.66/20287.26	% SZS status GaveUp for HL408280+4.p
152076.66/20287.26	eprover: CPU time limit exceeded, terminating
152076.66/20287.26	% SZS status Ended for HL408280+4.p
152087.30/20288.57	% SZS status Started for HL408282+4.p
152087.30/20288.57	% SZS status GaveUp for HL408282+4.p
152087.30/20288.57	eprover: CPU time limit exceeded, terminating
152087.30/20288.57	% SZS status Ended for HL408282+4.p
152097.94/20289.93	% SZS status Started for HL408277+5.p
152097.94/20289.93	% SZS status GaveUp for HL408277+5.p
152097.94/20289.93	eprover: CPU time limit exceeded, terminating
152097.94/20289.93	% SZS status Ended for HL408277+5.p
152104.27/20290.72	% SZS status Started for HL408275+5.p
152104.27/20290.72	% SZS status GaveUp for HL408275+5.p
152104.27/20290.72	eprover: CPU time limit exceeded, terminating
152104.27/20290.72	% SZS status Ended for HL408275+5.p
152111.64/20291.65	% SZS status Started for HL408283+4.p
152111.64/20291.65	% SZS status GaveUp for HL408283+4.p
152111.64/20291.65	eprover: CPU time limit exceeded, terminating
152111.64/20291.65	% SZS status Ended for HL408283+4.p
152127.83/20293.76	% SZS status Started for HL408284+4.p
152127.83/20293.76	% SZS status GaveUp for HL408284+4.p
152127.83/20293.76	eprover: CPU time limit exceeded, terminating
152127.83/20293.76	% SZS status Ended for HL408284+4.p
152151.28/20296.79	% SZS status Started for HL408285+4.p
152151.28/20296.79	% SZS status GaveUp for HL408285+4.p
152151.28/20296.79	eprover: CPU time limit exceeded, terminating
152151.28/20296.79	% SZS status Ended for HL408285+4.p
152181.78/20300.47	% SZS status Started for HL408283+5.p
152181.78/20300.47	% SZS status GaveUp for HL408283+5.p
152181.78/20300.47	eprover: CPU time limit exceeded, terminating
152181.78/20300.47	% SZS status Ended for HL408283+5.p
152203.91/20303.28	% SZS status Started for HL408276+5.p
152203.91/20303.28	% SZS status GaveUp for HL408276+5.p
152203.91/20303.28	eprover: CPU time limit exceeded, terminating
152203.91/20303.28	% SZS status Ended for HL408276+5.p
152206.53/20303.64	% SZS status Started for HL408286+4.p
152206.53/20303.64	% SZS status GaveUp for HL408286+4.p
152206.53/20303.64	eprover: CPU time limit exceeded, terminating
152206.53/20303.64	% SZS status Ended for HL408286+4.p
152231.44/20306.71	% SZS status Started for HL408287+4.p
152231.44/20306.71	% SZS status GaveUp for HL408287+4.p
152231.44/20306.71	eprover: CPU time limit exceeded, terminating
152231.44/20306.71	% SZS status Ended for HL408287+4.p
152241.84/20308.02	% SZS status Started for HL408278+5.p
152241.84/20308.02	% SZS status GaveUp for HL408278+5.p
152241.84/20308.02	eprover: CPU time limit exceeded, terminating
152241.84/20308.02	% SZS status Ended for HL408278+5.p
152257.50/20309.99	% SZS status Started for HL408279+5.p
152257.50/20309.99	% SZS status GaveUp for HL408279+5.p
152257.50/20309.99	eprover: CPU time limit exceeded, terminating
152257.50/20309.99	% SZS status Ended for HL408279+5.p
152265.88/20311.07	% SZS status Started for HL408288+4.p
152265.88/20311.07	% SZS status GaveUp for HL408288+4.p
152265.88/20311.07	eprover: CPU time limit exceeded, terminating
152265.88/20311.07	% SZS status Ended for HL408288+4.p
152269.97/20311.55	% SZS status Started for HL408280+5.p
152269.97/20311.55	% SZS status GaveUp for HL408280+5.p
152269.97/20311.55	eprover: CPU time limit exceeded, terminating
152269.97/20311.55	% SZS status Ended for HL408280+5.p
152284.45/20313.42	% SZS status Started for HL408282+5.p
152284.45/20313.42	% SZS status GaveUp for HL408282+5.p
152284.45/20313.42	eprover: CPU time limit exceeded, terminating
152284.45/20313.42	% SZS status Ended for HL408282+5.p
152289.95/20314.13	% SZS status Started for HL408289+4.p
152289.95/20314.13	% SZS status GaveUp for HL408289+4.p
152289.95/20314.13	eprover: CPU time limit exceeded, terminating
152289.95/20314.13	% SZS status Ended for HL408289+4.p
152309.31/20316.54	% SZS status Started for HL408290+4.p
152309.31/20316.54	% SZS status GaveUp for HL408290+4.p
152309.31/20316.54	eprover: CPU time limit exceeded, terminating
152309.31/20316.54	% SZS status Ended for HL408290+4.p
152318.39/20317.66	% SZS status Started for HL408284+5.p
152318.39/20317.66	% SZS status GaveUp for HL408284+5.p
152318.39/20317.66	eprover: CPU time limit exceeded, terminating
152318.39/20317.66	% SZS status Ended for HL408284+5.p
152333.64/20319.57	% SZS status Started for HL408291+4.p
152333.64/20319.57	% SZS status GaveUp for HL408291+4.p
152333.64/20319.57	eprover: CPU time limit exceeded, terminating
152333.64/20319.57	% SZS status Ended for HL408291+4.p
152357.30/20322.60	% SZS status Started for HL408292+4.p
152357.30/20322.60	% SZS status GaveUp for HL408292+4.p
152357.30/20322.60	eprover: CPU time limit exceeded, terminating
152357.30/20322.60	% SZS status Ended for HL408292+4.p
152359.95/20322.92	% SZS status Started for HL408285+5.p
152359.95/20322.92	% SZS status GaveUp for HL408285+5.p
152359.95/20322.92	eprover: CPU time limit exceeded, terminating
152359.95/20322.92	% SZS status Ended for HL408285+5.p
152384.30/20325.96	% SZS status Started for HL408293+4.p
152384.30/20325.96	% SZS status GaveUp for HL408293+4.p
152384.30/20325.96	eprover: CPU time limit exceeded, terminating
152384.30/20325.96	% SZS status Ended for HL408293+4.p
152410.91/20329.32	% SZS status Started for HL408286+5.p
152410.91/20329.32	% SZS status GaveUp for HL408286+5.p
152410.91/20329.32	eprover: CPU time limit exceeded, terminating
152410.91/20329.32	% SZS status Ended for HL408286+5.p
152436.12/20332.47	% SZS status Started for HL408294+4.p
152436.12/20332.47	% SZS status GaveUp for HL408294+4.p
152436.12/20332.47	eprover: CPU time limit exceeded, terminating
152436.12/20332.47	% SZS status Ended for HL408294+4.p
152437.44/20332.71	% SZS status Started for HL408287+5.p
152437.44/20332.71	% SZS status GaveUp for HL408287+5.p
152437.44/20332.71	eprover: CPU time limit exceeded, terminating
152437.44/20332.71	% SZS status Ended for HL408287+5.p
152463.09/20335.89	% SZS status Started for HL408295+4.p
152463.09/20335.89	% SZS status GaveUp for HL408295+4.p
152463.09/20335.89	eprover: CPU time limit exceeded, terminating
152463.09/20335.89	% SZS status Ended for HL408295+4.p
152465.53/20336.20	% SZS status Started for HL408288+5.p
152465.53/20336.20	% SZS status GaveUp for HL408288+5.p
152465.53/20336.20	eprover: CPU time limit exceeded, terminating
152465.53/20336.20	% SZS status Ended for HL408288+5.p
152476.95/20337.65	% SZS status Started for HL408289+5.p
152476.95/20337.65	% SZS status GaveUp for HL408289+5.p
152476.95/20337.65	eprover: CPU time limit exceeded, terminating
152476.95/20337.65	% SZS status Ended for HL408289+5.p
152489.27/20339.23	% SZS status Started for HL408296+4.p
152489.27/20339.23	% SZS status GaveUp for HL408296+4.p
152489.27/20339.23	eprover: CPU time limit exceeded, terminating
152489.27/20339.23	% SZS status Ended for HL408296+4.p
152496.58/20340.09	% SZS status Started for HL408290+5.p
152496.58/20340.09	% SZS status GaveUp for HL408290+5.p
152496.58/20340.09	eprover: CPU time limit exceeded, terminating
152496.58/20340.09	% SZS status Ended for HL408290+5.p
152514.02/20342.26	% SZS status Started for HL408297+4.p
152514.02/20342.26	% SZS status GaveUp for HL408297+4.p
152514.02/20342.26	eprover: CPU time limit exceeded, terminating
152514.02/20342.26	% SZS status Ended for HL408297+4.p
152526.81/20343.96	% SZS status Started for HL408291+5.p
152526.81/20343.96	% SZS status GaveUp for HL408291+5.p
152526.81/20343.96	eprover: CPU time limit exceeded, terminating
152526.81/20343.96	% SZS status Ended for HL408291+5.p
152538.34/20345.38	% SZS status Started for HL408298+4.p
152538.34/20345.38	% SZS status GaveUp for HL408298+4.p
152538.34/20345.38	eprover: CPU time limit exceeded, terminating
152538.34/20345.38	% SZS status Ended for HL408298+4.p
152562.88/20348.42	% SZS status Started for HL408299+4.p
152562.88/20348.42	% SZS status GaveUp for HL408299+4.p
152562.88/20348.42	eprover: CPU time limit exceeded, terminating
152562.88/20348.42	% SZS status Ended for HL408299+4.p
152564.70/20348.66	% SZS status Started for HL408292+5.p
152564.70/20348.66	% SZS status GaveUp for HL408292+5.p
152564.70/20348.66	eprover: CPU time limit exceeded, terminating
152564.70/20348.66	% SZS status Ended for HL408292+5.p
152589.03/20351.72	% SZS status Started for HL408300+4.p
152589.03/20351.72	% SZS status GaveUp for HL408300+4.p
152589.03/20351.72	eprover: CPU time limit exceeded, terminating
152589.03/20351.72	% SZS status Ended for HL408300+4.p
152592.55/20352.17	% SZS status Started for HL408293+5.p
152592.55/20352.17	% SZS status GaveUp for HL408293+5.p
152592.55/20352.17	eprover: CPU time limit exceeded, terminating
152592.55/20352.17	% SZS status Ended for HL408293+5.p
152616.80/20355.30	% SZS status Started for HL408301+4.p
152616.80/20355.30	% SZS status GaveUp for HL408301+4.p
152616.80/20355.30	eprover: CPU time limit exceeded, terminating
152616.80/20355.30	% SZS status Ended for HL408301+4.p
152643.94/20358.64	% SZS status Started for HL408294+5.p
152643.94/20358.64	% SZS status GaveUp for HL408294+5.p
152643.94/20358.64	eprover: CPU time limit exceeded, terminating
152643.94/20358.64	% SZS status Ended for HL408294+5.p
152669.08/20361.81	% SZS status Started for HL408302+4.p
152669.08/20361.81	% SZS status GaveUp for HL408302+4.p
152669.08/20361.81	eprover: CPU time limit exceeded, terminating
152669.08/20361.81	% SZS status Ended for HL408302+4.p
152669.83/20361.92	% SZS status Started for HL408295+5.p
152669.83/20361.92	% SZS status GaveUp for HL408295+5.p
152669.83/20361.92	eprover: CPU time limit exceeded, terminating
152669.83/20361.92	% SZS status Ended for HL408295+5.p
152688.17/20364.28	% SZS status Started for HL408296+5.p
152688.17/20364.28	% SZS status GaveUp for HL408296+5.p
152688.17/20364.28	eprover: CPU time limit exceeded, terminating
152688.17/20364.28	% SZS status Ended for HL408296+5.p
152693.72/20364.94	% SZS status Started for HL408303+4.p
152693.72/20364.94	% SZS status GaveUp for HL408303+4.p
152693.72/20364.94	eprover: CPU time limit exceeded, terminating
152693.72/20364.94	% SZS status Ended for HL408303+4.p
152702.52/20366.05	% SZS status Started for HL408297+5.p
152702.52/20366.05	% SZS status GaveUp for HL408297+5.p
152702.52/20366.05	eprover: CPU time limit exceeded, terminating
152702.52/20366.05	% SZS status Ended for HL408297+5.p
152718.27/20368.04	% SZS status Started for HL408304+4.p
152718.27/20368.04	% SZS status GaveUp for HL408304+4.p
152718.27/20368.04	eprover: CPU time limit exceeded, terminating
152718.27/20368.04	% SZS status Ended for HL408304+4.p
152733.62/20369.99	% SZS status Started for HL408298+5.p
152733.62/20369.99	% SZS status GaveUp for HL408298+5.p
152733.62/20369.99	eprover: CPU time limit exceeded, terminating
152733.62/20369.99	% SZS status Ended for HL408298+5.p
152742.28/20371.09	% SZS status Started for HL408305+4.p
152742.28/20371.09	% SZS status GaveUp for HL408305+4.p
152742.28/20371.09	eprover: CPU time limit exceeded, terminating
152742.28/20371.09	% SZS status Ended for HL408305+4.p
152766.75/20374.13	% SZS status Started for HL408306+4.p
152766.75/20374.13	% SZS status GaveUp for HL408306+4.p
152766.75/20374.13	eprover: CPU time limit exceeded, terminating
152766.75/20374.13	% SZS status Ended for HL408306+4.p
152769.19/20374.50	% SZS status Started for HL408299+5.p
152769.19/20374.50	% SZS status GaveUp for HL408299+5.p
152769.19/20374.50	eprover: CPU time limit exceeded, terminating
152769.19/20374.50	% SZS status Ended for HL408299+5.p
152786.11/20376.52	% SZS status Started for HL408304+5.p
152786.11/20376.52	% SZS status GaveUp for HL408304+5.p
152786.11/20376.52	eprover: CPU time limit exceeded, terminating
152786.11/20376.52	% SZS status Ended for HL408304+5.p
152793.89/20377.54	% SZS status Started for HL408307+4.p
152793.89/20377.54	% SZS status GaveUp for HL408307+4.p
152793.89/20377.54	eprover: CPU time limit exceeded, terminating
152793.89/20377.54	% SZS status Ended for HL408307+4.p
152794.50/20377.65	% SZS status Started for HL408300+5.p
152794.50/20377.65	% SZS status GaveUp for HL408300+5.p
152794.50/20377.65	eprover: CPU time limit exceeded, terminating
152794.50/20377.65	% SZS status Ended for HL408300+5.p
152816.95/20380.42	% SZS status Started for HL408305+5.p
152816.95/20380.42	% SZS status GaveUp for HL408305+5.p
152816.95/20380.42	eprover: CPU time limit exceeded, terminating
152816.95/20380.42	% SZS status Ended for HL408305+5.p
152818.11/20380.57	% SZS status Started for HL408308+4.p
152818.11/20380.57	% SZS status GaveUp for HL408308+4.p
152818.11/20380.57	eprover: CPU time limit exceeded, terminating
152818.11/20380.57	% SZS status Ended for HL408308+4.p
152824.17/20381.32	% SZS status Started for HL408301+5.p
152824.17/20381.32	% SZS status GaveUp for HL408301+5.p
152824.17/20381.32	eprover: CPU time limit exceeded, terminating
152824.17/20381.32	% SZS status Ended for HL408301+5.p
152840.36/20383.44	% SZS status Started for HL408309+4.p
152840.36/20383.44	% SZS status GaveUp for HL408309+4.p
152840.36/20383.44	eprover: CPU time limit exceeded, terminating
152840.36/20383.44	% SZS status Ended for HL408309+4.p
152847.81/20384.35	% SZS status Started for HL408310+4.p
152847.81/20384.35	% SZS status GaveUp for HL408310+4.p
152847.81/20384.35	eprover: CPU time limit exceeded, terminating
152847.81/20384.35	% SZS status Ended for HL408310+4.p
152871.95/20387.38	% SZS status Started for HL408311+4.p
152871.95/20387.38	% SZS status GaveUp for HL408311+4.p
152871.95/20387.38	eprover: CPU time limit exceeded, terminating
152871.95/20387.38	% SZS status Ended for HL408311+4.p
152877.95/20388.14	% SZS status Started for HL408302+5.p
152877.95/20388.14	% SZS status GaveUp for HL408302+5.p
152877.95/20388.14	eprover: CPU time limit exceeded, terminating
152877.95/20388.14	% SZS status Ended for HL408302+5.p
152895.28/20390.28	% SZS status Started for HL408303+5.p
152895.28/20390.28	% SZS status GaveUp for HL408303+5.p
152895.28/20390.28	eprover: CPU time limit exceeded, terminating
152895.28/20390.28	% SZS status Ended for HL408303+5.p
152900.70/20390.94	% SZS status Started for HL408309+5.p
152900.70/20390.94	% SZS status GaveUp for HL408309+5.p
152900.70/20390.94	eprover: CPU time limit exceeded, terminating
152900.70/20390.94	% SZS status Ended for HL408309+5.p
152902.61/20391.18	% SZS status Started for HL408312+4.p
152902.61/20391.18	% SZS status GaveUp for HL408312+4.p
152902.61/20391.18	eprover: CPU time limit exceeded, terminating
152902.61/20391.18	% SZS status Ended for HL408312+4.p
152924.92/20393.98	% SZS status Started for HL408313+4.p
152924.92/20393.98	% SZS status GaveUp for HL408313+4.p
152924.92/20393.98	eprover: CPU time limit exceeded, terminating
152924.92/20393.98	% SZS status Ended for HL408313+4.p
152948.88/20397.04	% SZS status Started for HL408315+4.p
152948.88/20397.04	% SZS status GaveUp for HL408315+4.p
152948.88/20397.04	eprover: CPU time limit exceeded, terminating
152948.88/20397.04	% SZS status Ended for HL408315+4.p
152974.41/20400.21	% SZS status Started for HL408306+5.p
152974.41/20400.21	% SZS status GaveUp for HL408306+5.p
152974.41/20400.21	eprover: CPU time limit exceeded, terminating
152974.41/20400.21	% SZS status Ended for HL408306+5.p
152992.72/20402.56	% SZS status Started for HL408307+5.p
152992.72/20402.56	% SZS status GaveUp for HL408307+5.p
152992.72/20402.56	eprover: CPU time limit exceeded, terminating
152992.72/20402.56	% SZS status Ended for HL408307+5.p
152998.00/20403.25	% SZS status Started for HL408316+4.p
152998.00/20403.25	% SZS status GaveUp for HL408316+4.p
152998.00/20403.25	eprover: CPU time limit exceeded, terminating
152998.00/20403.25	% SZS status Ended for HL408316+4.p
153002.91/20403.81	% SZS status Started for HL408308+5.p
153002.91/20403.81	% SZS status GaveUp for HL408308+5.p
153002.91/20403.81	eprover: CPU time limit exceeded, terminating
153002.91/20403.81	% SZS status Ended for HL408308+5.p
153021.94/20406.29	% SZS status Started for HL408317+4.p
153021.94/20406.29	% SZS status GaveUp for HL408317+4.p
153021.94/20406.29	eprover: CPU time limit exceeded, terminating
153021.94/20406.29	% SZS status Ended for HL408317+4.p
153047.41/20409.41	% SZS status Started for HL408318+4.p
153047.41/20409.41	% SZS status GaveUp for HL408318+4.p
153047.41/20409.41	eprover: CPU time limit exceeded, terminating
153047.41/20409.41	% SZS status Ended for HL408318+4.p
153048.70/20409.66	% SZS status Started for HL408310+5.p
153048.70/20409.66	% SZS status GaveUp for HL408310+5.p
153048.70/20409.66	eprover: CPU time limit exceeded, terminating
153048.70/20409.66	% SZS status Ended for HL408310+5.p
153073.48/20412.73	% SZS status Started for HL408319+4.p
153073.48/20412.73	% SZS status GaveUp for HL408319+4.p
153073.48/20412.73	eprover: CPU time limit exceeded, terminating
153073.48/20412.73	% SZS status Ended for HL408319+4.p
153079.14/20413.47	% SZS status Started for HL408311+5.p
153079.14/20413.47	% SZS status GaveUp for HL408311+5.p
153079.14/20413.47	eprover: CPU time limit exceeded, terminating
153079.14/20413.47	% SZS status Ended for HL408311+5.p
153103.11/20416.42	% SZS status Started for HL408312+5.p
153103.11/20416.42	% SZS status GaveUp for HL408312+5.p
153103.11/20416.42	eprover: CPU time limit exceeded, terminating
153103.11/20416.42	% SZS status Ended for HL408312+5.p
153103.64/20416.50	% SZS status Started for HL408321+4.p
153103.64/20416.50	% SZS status GaveUp for HL408321+4.p
153103.64/20416.50	eprover: CPU time limit exceeded, terminating
153103.64/20416.50	% SZS status Ended for HL408321+4.p
153108.36/20417.14	% SZS status Started for HL408313+5.p
153108.36/20417.14	% SZS status GaveUp for HL408313+5.p
153108.36/20417.14	eprover: CPU time limit exceeded, terminating
153108.36/20417.14	% SZS status Ended for HL408313+5.p
153127.42/20419.54	% SZS status Started for HL408323+4.p
153127.42/20419.54	% SZS status GaveUp for HL408323+4.p
153127.42/20419.54	eprover: CPU time limit exceeded, terminating
153127.42/20419.54	% SZS status Ended for HL408323+4.p
153151.48/20422.56	% SZS status Started for HL408324+4.p
153151.48/20422.56	% SZS status GaveUp for HL408324+4.p
153151.48/20422.56	eprover: CPU time limit exceeded, terminating
153151.48/20422.56	% SZS status Ended for HL408324+4.p
153156.33/20423.17	% SZS status Started for HL408315+5.p
153156.33/20423.17	% SZS status GaveUp for HL408315+5.p
153156.33/20423.17	eprover: CPU time limit exceeded, terminating
153156.33/20423.17	% SZS status Ended for HL408315+5.p
153180.28/20426.22	% SZS status Started for HL408325+4.p
153180.28/20426.22	% SZS status GaveUp for HL408325+4.p
153180.28/20426.22	eprover: CPU time limit exceeded, terminating
153180.28/20426.22	% SZS status Ended for HL408325+4.p
153199.03/20428.67	% SZS status Started for HL408316+5.p
153199.03/20428.67	% SZS status GaveUp for HL408316+5.p
153199.03/20428.67	eprover: CPU time limit exceeded, terminating
153199.03/20428.67	% SZS status Ended for HL408316+5.p
153208.61/20429.76	% SZS status Started for HL408317+5.p
153208.61/20429.76	% SZS status GaveUp for HL408317+5.p
153208.61/20429.76	eprover: CPU time limit exceeded, terminating
153208.61/20429.76	% SZS status Ended for HL408317+5.p
153224.42/20431.73	% SZS status Started for HL408326+4.p
153224.42/20431.73	% SZS status GaveUp for HL408326+4.p
153224.42/20431.73	eprover: CPU time limit exceeded, terminating
153224.42/20431.73	% SZS status Ended for HL408326+4.p
153248.64/20434.81	% SZS status Started for HL408328+4.p
153248.64/20434.81	% SZS status GaveUp for HL408328+4.p
153248.64/20434.81	eprover: CPU time limit exceeded, terminating
153248.64/20434.81	% SZS status Ended for HL408328+4.p
153255.42/20435.61	% SZS status Started for HL408318+5.p
153255.42/20435.61	% SZS status GaveUp for HL408318+5.p
153255.42/20435.61	eprover: CPU time limit exceeded, terminating
153255.42/20435.61	% SZS status Ended for HL408318+5.p
153279.47/20438.65	% SZS status Started for HL408329+4.p
153279.47/20438.65	% SZS status GaveUp for HL408329+4.p
153279.47/20438.65	eprover: CPU time limit exceeded, terminating
153279.47/20438.65	% SZS status Ended for HL408329+4.p
153281.52/20438.88	% SZS status Started for HL408319+5.p
153281.52/20438.88	% SZS status GaveUp for HL408319+5.p
153281.52/20438.88	eprover: CPU time limit exceeded, terminating
153281.52/20438.88	% SZS status Ended for HL408319+5.p
153306.28/20441.99	% SZS status Started for HL408330+4.p
153306.28/20441.99	% SZS status GaveUp for HL408330+4.p
153306.28/20441.99	eprover: CPU time limit exceeded, terminating
153306.28/20441.99	% SZS status Ended for HL408330+4.p
153310.80/20442.61	% SZS status Started for HL408321+5.p
153310.80/20442.61	% SZS status GaveUp for HL408321+5.p
153310.80/20442.61	eprover: CPU time limit exceeded, terminating
153310.80/20442.61	% SZS status Ended for HL408321+5.p
153316.75/20443.34	% SZS status Started for HL408323+5.p
153316.75/20443.34	% SZS status GaveUp for HL408323+5.p
153316.75/20443.34	eprover: CPU time limit exceeded, terminating
153316.75/20443.34	% SZS status Ended for HL408323+5.p
153334.83/20445.68	% SZS status Started for HL408331+4.p
153334.83/20445.68	% SZS status GaveUp for HL408331+4.p
153334.83/20445.68	eprover: CPU time limit exceeded, terminating
153334.83/20445.68	% SZS status Ended for HL408331+4.p
153359.28/20448.70	% SZS status Started for HL408324+5.p
153359.28/20448.70	% SZS status GaveUp for HL408324+5.p
153359.28/20448.70	eprover: CPU time limit exceeded, terminating
153359.28/20448.70	% SZS status Ended for HL408324+5.p
153359.28/20448.71	% SZS status Started for HL408332+4.p
153359.28/20448.71	% SZS status GaveUp for HL408332+4.p
153359.28/20448.71	eprover: CPU time limit exceeded, terminating
153359.28/20448.71	% SZS status Ended for HL408332+4.p
153383.61/20451.78	% SZS status Started for HL408333+4.p
153383.61/20451.78	% SZS status GaveUp for HL408333+4.p
153383.61/20451.78	eprover: CPU time limit exceeded, terminating
153383.61/20451.78	% SZS status Ended for HL408333+4.p
153387.73/20452.32	% SZS status Started for HL408325+5.p
153387.73/20452.32	% SZS status GaveUp for HL408325+5.p
153387.73/20452.32	eprover: CPU time limit exceeded, terminating
153387.73/20452.32	% SZS status Ended for HL408325+5.p
153411.48/20455.37	% SZS status Started for HL408334+4.p
153411.48/20455.37	% SZS status GaveUp for HL408334+4.p
153411.48/20455.37	eprover: CPU time limit exceeded, terminating
153411.48/20455.37	% SZS status Ended for HL408334+4.p
153416.73/20456.00	% SZS status Started for HL408326+5.p
153416.73/20456.00	% SZS status GaveUp for HL408326+5.p
153416.73/20456.00	eprover: CPU time limit exceeded, terminating
153416.73/20456.00	% SZS status Ended for HL408326+5.p
153440.92/20459.03	% SZS status Started for HL408335+4.p
153440.92/20459.03	% SZS status GaveUp for HL408335+4.p
153440.92/20459.03	eprover: CPU time limit exceeded, terminating
153440.92/20459.03	% SZS status Ended for HL408335+4.p
153443.02/20459.25	% SZS status Started for HL408332+5.p
153443.02/20459.25	% SZS status GaveUp for HL408332+5.p
153443.02/20459.25	eprover: CPU time limit exceeded, terminating
153443.02/20459.25	% SZS status Ended for HL408332+5.p
153456.58/20460.97	% SZS status Started for HL408328+5.p
153456.58/20460.97	% SZS status GaveUp for HL408328+5.p
153456.58/20460.97	eprover: CPU time limit exceeded, terminating
153456.58/20460.97	% SZS status Ended for HL408328+5.p
153466.84/20462.28	% SZS status Started for HL408336+4.p
153466.84/20462.28	% SZS status GaveUp for HL408336+4.p
153466.84/20462.28	eprover: CPU time limit exceeded, terminating
153466.84/20462.28	% SZS status Ended for HL408336+4.p
153487.48/20464.85	% SZS status Started for HL408329+5.p
153487.48/20464.85	% SZS status GaveUp for HL408329+5.p
153487.48/20464.85	eprover: CPU time limit exceeded, terminating
153487.48/20464.85	% SZS status Ended for HL408329+5.p
153491.34/20465.32	% SZS status Started for HL408337+4.p
153491.34/20465.32	% SZS status GaveUp for HL408337+4.p
153491.34/20465.32	eprover: CPU time limit exceeded, terminating
153491.34/20465.32	% SZS status Ended for HL408337+4.p
153514.58/20468.24	% SZS status Started for HL408330+5.p
153514.58/20468.24	% SZS status GaveUp for HL408330+5.p
153514.58/20468.24	eprover: CPU time limit exceeded, terminating
153514.58/20468.24	% SZS status Ended for HL408330+5.p
153515.11/20468.35	% SZS status Started for HL408338+4.p
153515.11/20468.35	% SZS status GaveUp for HL408338+4.p
153515.11/20468.35	eprover: CPU time limit exceeded, terminating
153515.11/20468.35	% SZS status Ended for HL408338+4.p
153523.83/20469.43	% SZS status Started for HL408331+5.p
153523.83/20469.43	% SZS status GaveUp for HL408331+5.p
153523.83/20469.43	eprover: CPU time limit exceeded, terminating
153523.83/20469.43	% SZS status Ended for HL408331+5.p
153524.02/20469.44	% SZS status Started for HL408335+5.p
153524.02/20469.44	% SZS status GaveUp for HL408335+5.p
153524.02/20469.44	eprover: CPU time limit exceeded, terminating
153524.02/20469.44	% SZS status Ended for HL408335+5.p
153539.33/20471.43	% SZS status Started for HL408339+4.p
153539.33/20471.43	% SZS status GaveUp for HL408339+4.p
153539.33/20471.43	eprover: CPU time limit exceeded, terminating
153539.33/20471.43	% SZS status Ended for HL408339+4.p
153548.06/20472.47	% SZS status Started for HL408341+4.p
153548.06/20472.47	% SZS status GaveUp for HL408341+4.p
153548.06/20472.47	eprover: CPU time limit exceeded, terminating
153548.06/20472.47	% SZS status Ended for HL408341+4.p
153572.38/20475.53	% SZS status Started for HL408342+4.p
153572.38/20475.53	% SZS status GaveUp for HL408342+4.p
153572.38/20475.53	eprover: CPU time limit exceeded, terminating
153572.38/20475.53	% SZS status Ended for HL408342+4.p
153592.50/20478.11	% SZS status Started for HL408333+5.p
153592.50/20478.11	% SZS status GaveUp for HL408333+5.p
153592.50/20478.11	eprover: CPU time limit exceeded, terminating
153592.50/20478.11	% SZS status Ended for HL408333+5.p
153616.97/20481.16	% SZS status Started for HL408343+4.p
153616.97/20481.16	% SZS status GaveUp for HL408343+4.p
153616.97/20481.16	eprover: CPU time limit exceeded, terminating
153616.97/20481.16	% SZS status Ended for HL408343+4.p
153619.44/20481.54	% SZS status Started for HL408334+5.p
153619.44/20481.54	% SZS status GaveUp for HL408334+5.p
153619.44/20481.54	eprover: CPU time limit exceeded, terminating
153619.44/20481.54	% SZS status Ended for HL408334+5.p
153644.70/20484.66	% SZS status Started for HL408344+4.p
153644.70/20484.66	% SZS status GaveUp for HL408344+4.p
153644.70/20484.66	eprover: CPU time limit exceeded, terminating
153644.70/20484.66	% SZS status Ended for HL408344+4.p
153665.58/20487.30	% SZS status Started for HL408336+5.p
153665.58/20487.30	% SZS status GaveUp for HL408336+5.p
153665.58/20487.30	eprover: CPU time limit exceeded, terminating
153665.58/20487.30	% SZS status Ended for HL408336+5.p
153690.69/20490.43	% SZS status Started for HL408345+4.p
153690.69/20490.43	% SZS status GaveUp for HL408345+4.p
153690.69/20490.43	eprover: CPU time limit exceeded, terminating
153690.69/20490.43	% SZS status Ended for HL408345+4.p
153695.97/20491.10	% SZS status Started for HL408337+5.p
153695.97/20491.10	% SZS status GaveUp for HL408337+5.p
153695.97/20491.10	eprover: CPU time limit exceeded, terminating
153695.97/20491.10	% SZS status Ended for HL408337+5.p
153719.70/20494.13	% SZS status Started for HL408347+4.p
153719.70/20494.13	% SZS status GaveUp for HL408347+4.p
153719.70/20494.13	eprover: CPU time limit exceeded, terminating
153719.70/20494.13	% SZS status Ended for HL408347+4.p
153720.47/20494.21	% SZS status Started for HL408338+5.p
153720.47/20494.21	% SZS status GaveUp for HL408338+5.p
153720.47/20494.21	eprover: CPU time limit exceeded, terminating
153720.47/20494.21	% SZS status Ended for HL408338+5.p
153730.30/20495.45	% SZS status Started for HL408339+5.p
153730.30/20495.45	% SZS status GaveUp for HL408339+5.p
153730.30/20495.45	eprover: CPU time limit exceeded, terminating
153730.30/20495.45	% SZS status Ended for HL408339+5.p
153744.56/20497.25	% SZS status Started for HL408348+4.p
153744.56/20497.25	% SZS status GaveUp for HL408348+4.p
153744.56/20497.25	eprover: CPU time limit exceeded, terminating
153744.56/20497.25	% SZS status Ended for HL408348+4.p
153746.27/20497.53	% SZS status Started for HL408341+5.p
153746.27/20497.53	% SZS status GaveUp for HL408341+5.p
153746.27/20497.53	eprover: CPU time limit exceeded, terminating
153746.27/20497.53	% SZS status Ended for HL408341+5.p
153768.39/20500.29	% SZS status Started for HL408352+4.p
153768.39/20500.29	% SZS status GaveUp for HL408352+4.p
153768.39/20500.29	eprover: CPU time limit exceeded, terminating
153768.39/20500.29	% SZS status Ended for HL408352+4.p
153772.59/20500.84	% SZS status Started for HL408345+5.p
153772.59/20500.84	% SZS status GaveUp for HL408345+5.p
153772.59/20500.84	eprover: CPU time limit exceeded, terminating
153772.59/20500.84	% SZS status Ended for HL408345+5.p
153779.31/20501.63	% SZS status Started for HL408342+5.p
153779.31/20501.63	% SZS status GaveUp for HL408342+5.p
153779.31/20501.63	eprover: CPU time limit exceeded, terminating
153779.31/20501.63	% SZS status Ended for HL408342+5.p
153792.69/20503.32	% SZS status Started for HL408353+4.p
153792.69/20503.32	% SZS status GaveUp for HL408353+4.p
153792.69/20503.32	eprover: CPU time limit exceeded, terminating
153792.69/20503.32	% SZS status Ended for HL408353+4.p
153803.45/20504.68	% SZS status Started for HL408354+4.p
153803.45/20504.68	% SZS status GaveUp for HL408354+4.p
153803.45/20504.68	eprover: CPU time limit exceeded, terminating
153803.45/20504.68	% SZS status Ended for HL408354+4.p
153826.22/20507.51	% SZS status Started for HL408343+5.p
153826.22/20507.51	% SZS status GaveUp for HL408343+5.p
153826.22/20507.51	eprover: CPU time limit exceeded, terminating
153826.22/20507.51	% SZS status Ended for HL408343+5.p
153827.36/20507.71	% SZS status Started for HL408355+4.p
153827.36/20507.71	% SZS status GaveUp for HL408355+4.p
153827.36/20507.71	eprover: CPU time limit exceeded, terminating
153827.36/20507.71	% SZS status Ended for HL408355+4.p
153851.47/20510.74	% SZS status Started for HL408356+4.p
153851.47/20510.74	% SZS status GaveUp for HL408356+4.p
153851.47/20510.74	eprover: CPU time limit exceeded, terminating
153851.47/20510.74	% SZS status Ended for HL408356+4.p
153852.31/20510.85	% SZS status Started for HL408344+5.p
153852.31/20510.85	% SZS status GaveUp for HL408344+5.p
153852.31/20510.85	eprover: CPU time limit exceeded, terminating
153852.31/20510.85	% SZS status Ended for HL408344+5.p
153873.86/20513.59	% SZS status Started for HL408354+5.p
153873.86/20513.59	% SZS status GaveUp for HL408354+5.p
153873.86/20513.59	eprover: CPU time limit exceeded, terminating
153873.86/20513.59	% SZS status Ended for HL408354+5.p
153876.27/20513.89	% SZS status Started for HL408357+4.p
153876.27/20513.89	% SZS status GaveUp for HL408357+4.p
153876.27/20513.89	eprover: CPU time limit exceeded, terminating
153876.27/20513.89	% SZS status Ended for HL408357+4.p
153901.25/20517.01	% SZS status Started for HL408358+4.p
153901.25/20517.01	% SZS status GaveUp for HL408358+4.p
153901.25/20517.01	eprover: CPU time limit exceeded, terminating
153901.25/20517.01	% SZS status Ended for HL408358+4.p
153927.78/20520.30	% SZS status Started for HL408347+5.p
153927.78/20520.30	% SZS status GaveUp for HL408347+5.p
153927.78/20520.30	eprover: CPU time limit exceeded, terminating
153927.78/20520.30	% SZS status Ended for HL408347+5.p
153935.20/20521.27	% SZS status Started for HL408356+5.p
153935.20/20521.27	% SZS status GaveUp for HL408356+5.p
153935.20/20521.27	eprover: CPU time limit exceeded, terminating
153935.20/20521.27	% SZS status Ended for HL408356+5.p
153936.02/20521.37	% SZS status Started for HL408348+5.p
153936.02/20521.37	% SZS status GaveUp for HL408348+5.p
153936.02/20521.37	eprover: CPU time limit exceeded, terminating
153936.02/20521.37	% SZS status Ended for HL408348+5.p
153952.47/20523.38	% SZS status Started for HL408359+4.p
153952.47/20523.38	% SZS status GaveUp for HL408359+4.p
153952.47/20523.38	eprover: CPU time limit exceeded, terminating
153952.47/20523.38	% SZS status Ended for HL408359+4.p
153955.53/20523.83	% SZS status Started for HL408352+5.p
153955.53/20523.83	% SZS status GaveUp for HL408352+5.p
153955.53/20523.83	eprover: CPU time limit exceeded, terminating
153955.53/20523.83	% SZS status Ended for HL408352+5.p
153960.70/20524.42	% SZS status Started for HL408360+4.p
153960.70/20524.42	% SZS status GaveUp for HL408360+4.p
153960.70/20524.42	eprover: CPU time limit exceeded, terminating
153960.70/20524.42	% SZS status Ended for HL408360+4.p
153979.89/20526.86	% SZS status Started for HL408361+4.p
153979.89/20526.86	% SZS status GaveUp for HL408361+4.p
153979.89/20526.86	eprover: CPU time limit exceeded, terminating
153979.89/20526.86	% SZS status Ended for HL408361+4.p
153980.36/20526.95	% SZS status Started for HL408353+5.p
153980.36/20526.95	% SZS status GaveUp for HL408353+5.p
153980.36/20526.95	eprover: CPU time limit exceeded, terminating
153980.36/20526.95	% SZS status Ended for HL408353+5.p
154003.78/20529.89	% SZS status Started for HL408362+4.p
154003.78/20529.89	% SZS status GaveUp for HL408362+4.p
154003.78/20529.89	eprover: CPU time limit exceeded, terminating
154003.78/20529.89	% SZS status Ended for HL408362+4.p
154028.41/20532.93	% SZS status Started for HL408364+4.p
154028.41/20532.93	% SZS status GaveUp for HL408364+4.p
154028.41/20532.93	eprover: CPU time limit exceeded, terminating
154028.41/20532.93	% SZS status Ended for HL408364+4.p
154032.45/20533.53	% SZS status Started for HL408355+5.p
154032.45/20533.53	% SZS status GaveUp for HL408355+5.p
154032.45/20533.53	eprover: CPU time limit exceeded, terminating
154032.45/20533.53	% SZS status Ended for HL408355+5.p
154056.92/20536.62	% SZS status Started for HL408369+4.p
154056.92/20536.62	% SZS status GaveUp for HL408369+4.p
154056.92/20536.62	eprover: CPU time limit exceeded, terminating
154056.92/20536.62	% SZS status Ended for HL408369+4.p
154082.33/20539.77	% SZS status Started for HL408357+5.p
154082.33/20539.77	% SZS status GaveUp for HL408357+5.p
154082.33/20539.77	eprover: CPU time limit exceeded, terminating
154082.33/20539.77	% SZS status Ended for HL408357+5.p
154106.81/20542.82	% SZS status Started for HL408370+4.p
154106.81/20542.82	% SZS status GaveUp for HL408370+4.p
154106.81/20542.82	eprover: CPU time limit exceeded, terminating
154106.81/20542.82	% SZS status Ended for HL408370+4.p
154108.45/20543.07	% SZS status Started for HL408358+5.p
154108.45/20543.07	% SZS status GaveUp for HL408358+5.p
154108.45/20543.07	eprover: CPU time limit exceeded, terminating
154108.45/20543.07	% SZS status Ended for HL408358+5.p
154133.42/20546.15	% SZS status Started for HL408372+4.p
154133.42/20546.15	% SZS status GaveUp for HL408372+4.p
154133.42/20546.15	eprover: CPU time limit exceeded, terminating
154133.42/20546.15	% SZS status Ended for HL408372+4.p
154143.50/20547.46	% SZS status Started for HL408359+5.p
154143.50/20547.46	% SZS status GaveUp for HL408359+5.p
154143.50/20547.46	eprover: CPU time limit exceeded, terminating
154143.50/20547.46	% SZS status Ended for HL408359+5.p
154159.66/20549.48	% SZS status Started for HL408360+5.p
154159.66/20549.48	% SZS status GaveUp for HL408360+5.p
154159.66/20549.48	eprover: CPU time limit exceeded, terminating
154159.66/20549.48	% SZS status Ended for HL408360+5.p
154167.19/20550.44	% SZS status Started for HL408361+5.p
154167.19/20550.44	% SZS status GaveUp for HL408361+5.p
154167.19/20550.44	eprover: CPU time limit exceeded, terminating
154167.19/20550.44	% SZS status Ended for HL408361+5.p
154167.70/20550.51	% SZS status Started for HL408374+4.p
154167.70/20550.51	% SZS status GaveUp for HL408374+4.p
154167.70/20550.51	eprover: CPU time limit exceeded, terminating
154167.70/20550.51	% SZS status Ended for HL408374+4.p
154189.70/20553.24	% SZS status Started for HL408362+5.p
154189.70/20553.24	% SZS status GaveUp for HL408362+5.p
154189.70/20553.24	eprover: CPU time limit exceeded, terminating
154189.70/20553.24	% SZS status Ended for HL408362+5.p
154191.25/20553.46	% SZS status Started for HL408375+4.p
154191.25/20553.46	% SZS status GaveUp for HL408375+4.p
154191.25/20553.46	eprover: CPU time limit exceeded, terminating
154191.25/20553.46	% SZS status Ended for HL408375+4.p
154214.20/20556.31	% SZS status Started for HL408376+4.p
154214.20/20556.31	% SZS status GaveUp for HL408376+4.p
154214.20/20556.31	eprover: CPU time limit exceeded, terminating
154214.20/20556.31	% SZS status Ended for HL408376+4.p
154235.75/20559.01	% SZS status Started for HL408364+5.p
154235.75/20559.01	% SZS status GaveUp for HL408364+5.p
154235.75/20559.01	eprover: CPU time limit exceeded, terminating
154235.75/20559.01	% SZS status Ended for HL408364+5.p
154237.92/20559.35	% SZS status Started for HL408377+4.p
154237.92/20559.35	% SZS status GaveUp for HL408377+4.p
154237.92/20559.35	eprover: CPU time limit exceeded, terminating
154237.92/20559.35	% SZS status Ended for HL408377+4.p
154262.78/20562.40	% SZS status Started for HL408379+4.p
154262.78/20562.40	% SZS status GaveUp for HL408379+4.p
154262.78/20562.40	eprover: CPU time limit exceeded, terminating
154262.78/20562.40	% SZS status Ended for HL408379+4.p
154264.97/20562.74	% SZS status Started for HL408369+5.p
154264.97/20562.74	% SZS status GaveUp for HL408369+5.p
154264.97/20562.74	eprover: CPU time limit exceeded, terminating
154264.97/20562.74	% SZS status Ended for HL408369+5.p
154289.66/20565.80	% SZS status Started for HL408380+4.p
154289.66/20565.80	% SZS status GaveUp for HL408380+4.p
154289.66/20565.80	eprover: CPU time limit exceeded, terminating
154289.66/20565.80	% SZS status Ended for HL408380+4.p
154314.33/20568.91	% SZS status Started for HL408370+5.p
154314.33/20568.91	% SZS status GaveUp for HL408370+5.p
154314.33/20568.91	eprover: CPU time limit exceeded, terminating
154314.33/20568.91	% SZS status Ended for HL408370+5.p
154339.03/20572.04	% SZS status Started for HL408381+4.p
154339.03/20572.04	% SZS status GaveUp for HL408381+4.p
154339.03/20572.04	eprover: CPU time limit exceeded, terminating
154339.03/20572.04	% SZS status Ended for HL408381+4.p
154341.19/20572.35	% SZS status Started for HL408372+5.p
154341.19/20572.35	% SZS status GaveUp for HL408372+5.p
154341.19/20572.35	eprover: CPU time limit exceeded, terminating
154341.19/20572.35	% SZS status Ended for HL408372+5.p
154366.17/20575.49	% SZS status Started for HL408382+4.p
154366.17/20575.49	% SZS status GaveUp for HL408382+4.p
154366.17/20575.49	eprover: CPU time limit exceeded, terminating
154366.17/20575.49	% SZS status Ended for HL408382+4.p
154369.67/20576.01	% SZS status Started for HL408374+5.p
154369.67/20576.01	% SZS status GaveUp for HL408374+5.p
154369.67/20576.01	eprover: CPU time limit exceeded, terminating
154369.67/20576.01	% SZS status Ended for HL408374+5.p
154377.11/20576.81	% SZS status Started for HL408375+5.p
154377.11/20576.81	% SZS status GaveUp for HL408375+5.p
154377.11/20576.81	eprover: CPU time limit exceeded, terminating
154377.11/20576.81	% SZS status Ended for HL408375+5.p
154394.64/20579.08	% SZS status Started for HL408383+4.p
154394.64/20579.08	% SZS status GaveUp for HL408383+4.p
154394.64/20579.08	eprover: CPU time limit exceeded, terminating
154394.64/20579.08	% SZS status Ended for HL408383+4.p
154397.48/20579.58	% SZS status Started for HL408376+5.p
154397.48/20579.58	% SZS status GaveUp for HL408376+5.p
154397.48/20579.58	eprover: CPU time limit exceeded, terminating
154397.48/20579.58	% SZS status Ended for HL408376+5.p
154419.75/20582.22	% SZS status Started for HL408386+4.p
154419.75/20582.22	% SZS status GaveUp for HL408386+4.p
154419.75/20582.22	eprover: CPU time limit exceeded, terminating
154419.75/20582.22	% SZS status Ended for HL408386+4.p
154423.98/20582.80	% SZS status Started for HL408381+5.p
154423.98/20582.80	% SZS status GaveUp for HL408381+5.p
154423.98/20582.80	eprover: CPU time limit exceeded, terminating
154423.98/20582.80	% SZS status Ended for HL408381+5.p
154442.70/20585.11	% SZS status Started for HL408377+5.p
154442.70/20585.11	% SZS status GaveUp for HL408377+5.p
154442.70/20585.11	eprover: CPU time limit exceeded, terminating
154442.70/20585.11	% SZS status Ended for HL408377+5.p
154444.36/20585.38	% SZS status Started for HL408387+4.p
154444.36/20585.38	% SZS status GaveUp for HL408387+4.p
154444.36/20585.38	eprover: CPU time limit exceeded, terminating
154444.36/20585.38	% SZS status Ended for HL408387+4.p
154467.41/20588.22	% SZS status Started for HL408389+4.p
154467.41/20588.22	% SZS status GaveUp for HL408389+4.p
154467.41/20588.22	eprover: CPU time limit exceeded, terminating
154467.41/20588.22	% SZS status Ended for HL408389+4.p
154471.00/20588.66	% SZS status Started for HL408379+5.p
154471.00/20588.66	% SZS status GaveUp for HL408379+5.p
154471.00/20588.66	eprover: CPU time limit exceeded, terminating
154471.00/20588.66	% SZS status Ended for HL408379+5.p
154479.81/20589.80	% SZS status Started for HL408386+5.p
154479.81/20589.80	% SZS status GaveUp for HL408386+5.p
154479.81/20589.80	eprover: CPU time limit exceeded, terminating
154479.81/20589.80	% SZS status Ended for HL408386+5.p
154491.36/20591.25	% SZS status Started for HL408390+4.p
154491.36/20591.25	% SZS status GaveUp for HL408390+4.p
154491.36/20591.25	eprover: CPU time limit exceeded, terminating
154491.36/20591.25	% SZS status Ended for HL408390+4.p
154496.75/20591.95	% SZS status Started for HL408380+5.p
154496.75/20591.95	% SZS status GaveUp for HL408380+5.p
154496.75/20591.95	eprover: CPU time limit exceeded, terminating
154496.75/20591.95	% SZS status Ended for HL408380+5.p
154504.45/20592.89	% SZS status Started for HL408391+4.p
154504.45/20592.89	% SZS status GaveUp for HL408391+4.p
154504.45/20592.89	eprover: CPU time limit exceeded, terminating
154504.45/20592.89	% SZS status Ended for HL408391+4.p
154520.55/20594.99	% SZS status Started for HL408392+4.p
154520.55/20594.99	% SZS status GaveUp for HL408392+4.p
154520.55/20594.99	eprover: CPU time limit exceeded, terminating
154520.55/20594.99	% SZS status Ended for HL408392+4.p
154529.84/20596.17	% SZS status Started for HL408389+5.p
154529.84/20596.17	% SZS status GaveUp for HL408389+5.p
154529.84/20596.17	eprover: CPU time limit exceeded, terminating
154529.84/20596.17	% SZS status Ended for HL408389+5.p
154545.20/20598.07	% SZS status Started for HL408393+4.p
154545.20/20598.07	% SZS status GaveUp for HL408393+4.p
154545.20/20598.07	eprover: CPU time limit exceeded, terminating
154545.20/20598.07	% SZS status Ended for HL408393+4.p
154569.14/20601.13	% SZS status Started for HL408394+4.p
154569.14/20601.13	% SZS status GaveUp for HL408394+4.p
154569.14/20601.13	eprover: CPU time limit exceeded, terminating
154569.14/20601.13	% SZS status Ended for HL408394+4.p
154575.75/20601.90	% SZS status Started for HL408382+5.p
154575.75/20601.90	% SZS status GaveUp for HL408382+5.p
154575.75/20601.90	eprover: CPU time limit exceeded, terminating
154575.75/20601.90	% SZS status Ended for HL408382+5.p
154576.92/20602.05	% SZS status Started for HL408391+5.p
154576.92/20602.05	% SZS status GaveUp for HL408391+5.p
154576.92/20602.05	eprover: CPU time limit exceeded, terminating
154576.92/20602.05	% SZS status Ended for HL408391+5.p
154582.67/20602.84	% SZS status Started for HL408383+5.p
154582.67/20602.84	% SZS status GaveUp for HL408383+5.p
154582.67/20602.84	eprover: CPU time limit exceeded, terminating
154582.67/20602.84	% SZS status Ended for HL408383+5.p
154599.89/20604.93	% SZS status Started for HL408395+4.p
154599.89/20604.93	% SZS status GaveUp for HL408395+4.p
154599.89/20604.93	eprover: CPU time limit exceeded, terminating
154599.89/20604.93	% SZS status Ended for HL408395+4.p
154607.11/20605.88	% SZS status Started for HL408396+4.p
154607.11/20605.88	% SZS status GaveUp for HL408396+4.p
154607.11/20605.88	eprover: CPU time limit exceeded, terminating
154607.11/20605.88	% SZS status Ended for HL408396+4.p
154631.28/20608.96	% SZS status Started for HL408398+4.p
154631.28/20608.96	% SZS status GaveUp for HL408398+4.p
154631.28/20608.96	eprover: CPU time limit exceeded, terminating
154631.28/20608.96	% SZS status Ended for HL408398+4.p
154632.55/20609.10	% SZS status Started for HL408387+5.p
154632.55/20609.10	% SZS status GaveUp for HL408387+5.p
154632.55/20609.10	eprover: CPU time limit exceeded, terminating
154632.55/20609.10	% SZS status Ended for HL408387+5.p
154657.12/20612.14	% SZS status Started for HL408399+4.p
154657.12/20612.14	% SZS status GaveUp for HL408399+4.p
154657.12/20612.14	eprover: CPU time limit exceeded, terminating
154657.12/20612.14	% SZS status Ended for HL408399+4.p
154678.81/20614.86	% SZS status Started for HL408390+5.p
154678.81/20614.86	% SZS status GaveUp for HL408390+5.p
154678.81/20614.86	eprover: CPU time limit exceeded, terminating
154678.81/20614.86	% SZS status Ended for HL408390+5.p
154702.73/20617.93	% SZS status Started for HL408400+4.p
154702.73/20617.93	% SZS status GaveUp for HL408400+4.p
154702.73/20617.93	eprover: CPU time limit exceeded, terminating
154702.73/20617.93	% SZS status Ended for HL408400+4.p
154711.31/20618.98	% SZS status Started for HL408392+5.p
154711.31/20618.98	% SZS status GaveUp for HL408392+5.p
154711.31/20618.98	eprover: CPU time limit exceeded, terminating
154711.31/20618.98	% SZS status Ended for HL408392+5.p
154735.53/20622.01	% SZS status Started for HL408403+4.p
154735.53/20622.01	% SZS status GaveUp for HL408403+4.p
154735.53/20622.01	eprover: CPU time limit exceeded, terminating
154735.53/20622.01	% SZS status Ended for HL408403+4.p
154736.25/20622.13	% SZS status Started for HL408393+5.p
154736.25/20622.13	% SZS status GaveUp for HL408393+5.p
154736.25/20622.13	eprover: CPU time limit exceeded, terminating
154736.25/20622.13	% SZS status Ended for HL408393+5.p
154760.34/20625.18	% SZS status Started for HL408404+4.p
154760.34/20625.18	% SZS status GaveUp for HL408404+4.p
154760.34/20625.18	eprover: CPU time limit exceeded, terminating
154760.34/20625.18	% SZS status Ended for HL408404+4.p
154776.55/20627.24	% SZS status Started for HL408394+5.p
154776.55/20627.24	% SZS status GaveUp for HL408394+5.p
154776.55/20627.24	eprover: CPU time limit exceeded, terminating
154776.55/20627.24	% SZS status Ended for HL408394+5.p
154785.34/20628.39	% SZS status Started for HL408395+5.p
154785.34/20628.39	% SZS status GaveUp for HL408395+5.p
154785.34/20628.39	eprover: CPU time limit exceeded, terminating
154785.34/20628.39	% SZS status Ended for HL408395+5.p
154801.22/20630.27	% SZS status Started for HL408405+4.p
154801.22/20630.27	% SZS status GaveUp for HL408405+4.p
154801.22/20630.27	eprover: CPU time limit exceeded, terminating
154801.22/20630.27	% SZS status Ended for HL408405+4.p
154807.06/20631.08	% SZS status Started for HL408396+5.p
154807.06/20631.08	% SZS status GaveUp for HL408396+5.p
154807.06/20631.08	eprover: CPU time limit exceeded, terminating
154807.06/20631.08	% SZS status Ended for HL408396+5.p
154824.88/20633.33	% SZS status Started for HL408407+4.p
154824.88/20633.33	% SZS status GaveUp for HL408407+4.p
154824.88/20633.33	eprover: CPU time limit exceeded, terminating
154824.88/20633.33	% SZS status Ended for HL408407+4.p
154838.08/20634.92	% SZS status Started for HL408398+5.p
154838.08/20634.92	% SZS status GaveUp for HL408398+5.p
154838.08/20634.92	eprover: CPU time limit exceeded, terminating
154838.08/20634.92	% SZS status Ended for HL408398+5.p
154849.62/20636.37	% SZS status Started for HL408408+4.p
154849.62/20636.37	% SZS status GaveUp for HL408408+4.p
154849.62/20636.37	eprover: CPU time limit exceeded, terminating
154849.62/20636.37	% SZS status Ended for HL408408+4.p
154867.75/20638.68	% SZS status Started for HL408399+5.p
154867.75/20638.68	% SZS status GaveUp for HL408399+5.p
154867.75/20638.68	eprover: CPU time limit exceeded, terminating
154867.75/20638.68	% SZS status Ended for HL408399+5.p
154873.61/20639.41	% SZS status Started for HL408409+4.p
154873.61/20639.41	% SZS status GaveUp for HL408409+4.p
154873.61/20639.41	eprover: CPU time limit exceeded, terminating
154873.61/20639.41	% SZS status Ended for HL408409+4.p
154897.23/20642.47	% SZS status Started for HL408410+4.p
154897.23/20642.47	% SZS status GaveUp for HL408410+4.p
154897.23/20642.47	eprover: CPU time limit exceeded, terminating
154897.23/20642.47	% SZS status Ended for HL408410+4.p
154909.44/20643.95	% SZS status Started for HL408400+5.p
154909.44/20643.95	% SZS status GaveUp for HL408400+5.p
154909.44/20643.95	eprover: CPU time limit exceeded, terminating
154909.44/20643.95	% SZS status Ended for HL408400+5.p
154933.62/20646.99	% SZS status Started for HL408411+4.p
154933.62/20646.99	% SZS status GaveUp for HL408411+4.p
154933.62/20646.99	eprover: CPU time limit exceeded, terminating
154933.62/20646.99	% SZS status Ended for HL408411+4.p
154941.62/20648.04	% SZS status Started for HL408403+5.p
154941.62/20648.04	% SZS status GaveUp for HL408403+5.p
154941.62/20648.04	eprover: CPU time limit exceeded, terminating
154941.62/20648.04	% SZS status Ended for HL408403+5.p
154948.86/20648.94	% SZS status Started for HL408409+5.p
154948.86/20648.94	% SZS status GaveUp for HL408409+5.p
154948.86/20648.94	eprover: CPU time limit exceeded, terminating
154948.86/20648.94	% SZS status Ended for HL408409+5.p
154966.67/20651.13	% SZS status Started for HL408412+4.p
154966.67/20651.13	% SZS status GaveUp for HL408412+4.p
154966.67/20651.13	eprover: CPU time limit exceeded, terminating
154966.67/20651.13	% SZS status Ended for HL408412+4.p
154967.66/20651.35	% SZS status Started for HL408404+5.p
154967.66/20651.35	% SZS status GaveUp for HL408404+5.p
154967.66/20651.35	eprover: CPU time limit exceeded, terminating
154967.66/20651.35	% SZS status Ended for HL408404+5.p
154990.36/20654.16	% SZS status Started for HL408413+4.p
154990.36/20654.16	% SZS status GaveUp for HL408413+4.p
154990.36/20654.16	eprover: CPU time limit exceeded, terminating
154990.36/20654.16	% SZS status Ended for HL408413+4.p
154996.05/20654.84	% SZS status Started for HL408405+5.p
154996.05/20654.84	% SZS status GaveUp for HL408405+5.p
154996.05/20654.84	eprover: CPU time limit exceeded, terminating
154996.05/20654.84	% SZS status Ended for HL408405+5.p
155015.03/20657.22	% SZS status Started for HL408414+4.p
155015.03/20657.22	% SZS status GaveUp for HL408414+4.p
155015.03/20657.22	eprover: CPU time limit exceeded, terminating
155015.03/20657.22	% SZS status Ended for HL408414+4.p
155015.50/20657.32	% SZS status Started for HL408407+5.p
155015.50/20657.32	% SZS status GaveUp for HL408407+5.p
155015.50/20657.32	eprover: CPU time limit exceeded, terminating
155015.50/20657.32	% SZS status Ended for HL408407+5.p
155038.34/20660.26	% SZS status Started for HL408415+4.p
155038.34/20660.26	% SZS status GaveUp for HL408415+4.p
155038.34/20660.26	eprover: CPU time limit exceeded, terminating
155038.34/20660.26	% SZS status Ended for HL408415+4.p
155045.59/20661.06	% SZS status Started for HL408408+5.p
155045.59/20661.06	% SZS status GaveUp for HL408408+5.p
155045.59/20661.06	eprover: CPU time limit exceeded, terminating
155045.59/20661.06	% SZS status Ended for HL408408+5.p
155063.80/20663.33	% SZS status Started for HL408416+4.p
155063.80/20663.33	% SZS status GaveUp for HL408416+4.p
155063.80/20663.33	eprover: CPU time limit exceeded, terminating
155063.80/20663.33	% SZS status Ended for HL408416+4.p
155087.88/20666.37	% SZS status Started for HL408417+4.p
155087.88/20666.37	% SZS status GaveUp for HL408417+4.p
155087.88/20666.37	eprover: CPU time limit exceeded, terminating
155087.88/20666.37	% SZS status Ended for HL408417+4.p
155105.05/20668.55	% SZS status Started for HL408410+5.p
155105.05/20668.55	% SZS status GaveUp for HL408410+5.p
155105.05/20668.55	eprover: CPU time limit exceeded, terminating
155105.05/20668.55	% SZS status Ended for HL408410+5.p
155128.91/20671.59	% SZS status Started for HL408419+4.p
155128.91/20671.59	% SZS status GaveUp for HL408419+4.p
155128.91/20671.59	eprover: CPU time limit exceeded, terminating
155128.91/20671.59	% SZS status Ended for HL408419+4.p
155143.08/20673.33	% SZS status Started for HL408411+5.p
155143.08/20673.33	% SZS status GaveUp for HL408411+5.p
155143.08/20673.33	eprover: CPU time limit exceeded, terminating
155143.08/20673.33	% SZS status Ended for HL408411+5.p
155156.53/20675.00	% SZS status Started for HL408412+5.p
155156.53/20675.00	% SZS status GaveUp for HL408412+5.p
155156.53/20675.00	eprover: CPU time limit exceeded, terminating
155156.53/20675.00	% SZS status Ended for HL408412+5.p
155167.59/20676.45	% SZS status Started for HL408420+4.p
155167.59/20676.45	% SZS status GaveUp for HL408420+4.p
155167.59/20676.45	eprover: CPU time limit exceeded, terminating
155167.59/20676.45	% SZS status Ended for HL408420+4.p
155175.09/20677.34	% SZS status Started for HL408413+5.p
155175.09/20677.34	% SZS status GaveUp for HL408413+5.p
155175.09/20677.34	eprover: CPU time limit exceeded, terminating
155175.09/20677.34	% SZS status Ended for HL408413+5.p
155191.67/20679.49	% SZS status Started for HL408421+4.p
155191.67/20679.49	% SZS status GaveUp for HL408421+4.p
155191.67/20679.49	eprover: CPU time limit exceeded, terminating
155191.67/20679.49	% SZS status Ended for HL408421+4.p
155204.86/20681.12	% SZS status Started for HL408414+5.p
155204.86/20681.12	% SZS status GaveUp for HL408414+5.p
155204.86/20681.12	eprover: CPU time limit exceeded, terminating
155204.86/20681.12	% SZS status Ended for HL408414+5.p
155216.06/20682.53	% SZS status Started for HL408422+4.p
155216.06/20682.53	% SZS status GaveUp for HL408422+4.p
155216.06/20682.53	eprover: CPU time limit exceeded, terminating
155216.06/20682.53	% SZS status Ended for HL408422+4.p
155216.64/20682.56	% SZS status Started for HL408419+5.p
155216.64/20682.56	% SZS status GaveUp for HL408419+5.p
155216.64/20682.56	eprover: CPU time limit exceeded, terminating
155216.64/20682.56	% SZS status Ended for HL408419+5.p
155226.00/20683.84	% SZS status Started for HL408415+5.p
155226.00/20683.84	% SZS status GaveUp for HL408415+5.p
155226.00/20683.84	eprover: CPU time limit exceeded, terminating
155226.00/20683.84	% SZS status Ended for HL408415+5.p
155239.42/20685.56	% SZS status Started for HL408424+4.p
155239.42/20685.56	% SZS status GaveUp for HL408424+4.p
155239.42/20685.56	eprover: CPU time limit exceeded, terminating
155239.42/20685.56	% SZS status Ended for HL408424+4.p
155242.03/20685.81	% SZS status Started for HL408420+5.p
155242.03/20685.81	% SZS status GaveUp for HL408420+5.p
155242.03/20685.81	eprover: CPU time limit exceeded, terminating
155242.03/20685.81	% SZS status Ended for HL408420+5.p
155249.97/20686.89	% SZS status Started for HL408425+4.p
155249.97/20686.89	% SZS status GaveUp for HL408425+4.p
155249.97/20686.89	eprover: CPU time limit exceeded, terminating
155249.97/20686.89	% SZS status Ended for HL408425+4.p
155253.12/20687.15	% SZS status Started for HL408416+5.p
155253.12/20687.15	% SZS status GaveUp for HL408416+5.p
155253.12/20687.15	eprover: CPU time limit exceeded, terminating
155253.12/20687.15	% SZS status Ended for HL408416+5.p
155260.50/20688.15	% SZS status Started for HL408421+5.p
155260.50/20688.15	% SZS status GaveUp for HL408421+5.p
155260.50/20688.15	eprover: CPU time limit exceeded, terminating
155260.50/20688.15	% SZS status Ended for HL408421+5.p
155265.81/20688.85	% SZS status Started for HL408426+4.p
155265.81/20688.85	% SZS status GaveUp for HL408426+4.p
155265.81/20688.85	eprover: CPU time limit exceeded, terminating
155265.81/20688.85	% SZS status Ended for HL408426+4.p
155276.91/20690.20	% SZS status Started for HL408428+4.p
155276.91/20690.20	% SZS status GaveUp for HL408428+4.p
155276.91/20690.20	eprover: CPU time limit exceeded, terminating
155276.91/20690.20	% SZS status Ended for HL408428+4.p
155290.25/20691.90	% SZS status Started for HL408429+4.p
155290.25/20691.90	% SZS status GaveUp for HL408429+4.p
155290.25/20691.90	eprover: CPU time limit exceeded, terminating
155290.25/20691.90	% SZS status Ended for HL408429+4.p
155290.38/20691.93	% SZS status Started for HL408422+5.p
155290.38/20691.93	% SZS status GaveUp for HL408422+5.p
155290.38/20691.93	eprover: CPU time limit exceeded, terminating
155290.38/20691.93	% SZS status Ended for HL408422+5.p
155294.19/20692.45	% SZS status Started for HL408417+5.p
155294.19/20692.45	% SZS status GaveUp for HL408417+5.p
155294.19/20692.45	eprover: CPU time limit exceeded, terminating
155294.19/20692.45	% SZS status Ended for HL408417+5.p
155305.83/20693.80	% SZS status Started for HL408424+5.p
155305.83/20693.80	% SZS status GaveUp for HL408424+5.p
155305.83/20693.80	eprover: CPU time limit exceeded, terminating
155305.83/20693.80	% SZS status Ended for HL408424+5.p
155314.67/20694.95	% SZS status Started for HL408430+4.p
155314.67/20694.95	% SZS status GaveUp for HL408430+4.p
155314.67/20694.95	eprover: CPU time limit exceeded, terminating
155314.67/20694.95	% SZS status Ended for HL408430+4.p
155319.16/20695.48	% SZS status Started for HL408431+4.p
155319.16/20695.48	% SZS status GaveUp for HL408431+4.p
155319.16/20695.48	eprover: CPU time limit exceeded, terminating
155319.16/20695.48	% SZS status Ended for HL408431+4.p
155326.00/20696.38	% SZS status Started for HL408425+5.p
155326.00/20696.38	% SZS status GaveUp for HL408425+5.p
155326.00/20696.38	eprover: CPU time limit exceeded, terminating
155326.00/20696.38	% SZS status Ended for HL408425+5.p
155336.28/20697.67	% SZS status Started for HL408426+5.p
155336.28/20697.67	% SZS status GaveUp for HL408426+5.p
155336.28/20697.67	eprover: CPU time limit exceeded, terminating
155336.28/20697.67	% SZS status Ended for HL408426+5.p
155338.56/20698.03	% SZS status Started for HL408432+4.p
155338.56/20698.03	% SZS status GaveUp for HL408432+4.p
155338.56/20698.03	eprover: CPU time limit exceeded, terminating
155338.56/20698.03	% SZS status Ended for HL408432+4.p
155347.41/20699.07	% SZS status Started for HL408428+5.p
155347.41/20699.07	% SZS status GaveUp for HL408428+5.p
155347.41/20699.07	eprover: CPU time limit exceeded, terminating
155347.41/20699.07	% SZS status Ended for HL408428+5.p
155350.73/20699.46	% SZS status Started for HL408433+4.p
155350.73/20699.46	% SZS status GaveUp for HL408433+4.p
155350.73/20699.46	eprover: CPU time limit exceeded, terminating
155350.73/20699.46	% SZS status Ended for HL408433+4.p
155362.75/20701.04	% SZS status Started for HL408429+5.p
155362.75/20701.04	% SZS status GaveUp for HL408429+5.p
155362.75/20701.04	eprover: CPU time limit exceeded, terminating
155362.75/20701.04	% SZS status Ended for HL408429+5.p
155363.42/20701.06	% SZS status Started for HL408435+4.p
155363.42/20701.06	% SZS status GaveUp for HL408435+4.p
155363.42/20701.06	eprover: CPU time limit exceeded, terminating
155363.42/20701.06	% SZS status Ended for HL408435+4.p
155374.25/20702.50	% SZS status Started for HL408436+4.p
155374.25/20702.50	% SZS status GaveUp for HL408436+4.p
155374.25/20702.50	eprover: CPU time limit exceeded, terminating
155374.25/20702.50	% SZS status Ended for HL408436+4.p
155375.50/20702.72	% SZS status Started for HL408430+5.p
155375.50/20702.72	% SZS status GaveUp for HL408430+5.p
155375.50/20702.72	eprover: CPU time limit exceeded, terminating
155375.50/20702.72	% SZS status Ended for HL408430+5.p
155387.08/20704.10	% SZS status Started for HL408437+4.p
155387.08/20704.10	% SZS status GaveUp for HL408437+4.p
155387.08/20704.10	eprover: CPU time limit exceeded, terminating
155387.08/20704.10	% SZS status Ended for HL408437+4.p
155390.89/20704.56	% SZS status Started for HL408431+5.p
155390.89/20704.56	% SZS status GaveUp for HL408431+5.p
155390.89/20704.56	eprover: CPU time limit exceeded, terminating
155390.89/20704.56	% SZS status Ended for HL408431+5.p
155401.16/20705.83	% SZS status Started for HL408438+4.p
155401.16/20705.83	% SZS status GaveUp for HL408438+4.p
155401.16/20705.83	eprover: CPU time limit exceeded, terminating
155401.16/20705.83	% SZS status Ended for HL408438+4.p
155404.67/20706.24	% SZS status Started for HL408432+5.p
155404.67/20706.24	% SZS status GaveUp for HL408432+5.p
155404.67/20706.24	eprover: CPU time limit exceeded, terminating
155404.67/20706.24	% SZS status Ended for HL408432+5.p
155415.55/20707.66	% SZS status Started for HL408439+4.p
155415.55/20707.66	% SZS status GaveUp for HL408439+4.p
155415.55/20707.66	eprover: CPU time limit exceeded, terminating
155415.55/20707.66	% SZS status Ended for HL408439+4.p
155423.75/20708.71	% SZS status Started for HL408433+5.p
155423.75/20708.71	% SZS status GaveUp for HL408433+5.p
155423.75/20708.71	eprover: CPU time limit exceeded, terminating
155423.75/20708.71	% SZS status Ended for HL408433+5.p
155428.84/20709.34	% SZS status Started for HL408441+4.p
155428.84/20709.34	% SZS status GaveUp for HL408441+4.p
155428.84/20709.34	eprover: CPU time limit exceeded, terminating
155428.84/20709.34	% SZS status Ended for HL408441+4.p
155432.50/20709.84	% SZS status Started for HL408435+5.p
155432.50/20709.84	% SZS status GaveUp for HL408435+5.p
155432.50/20709.84	eprover: CPU time limit exceeded, terminating
155432.50/20709.84	% SZS status Ended for HL408435+5.p
155447.25/20711.75	% SZS status Started for HL408442+4.p
155447.25/20711.75	% SZS status GaveUp for HL408442+4.p
155447.25/20711.75	eprover: CPU time limit exceeded, terminating
155447.25/20711.75	% SZS status Ended for HL408442+4.p
155449.20/20711.85	% SZS status Started for HL408436+5.p
155449.20/20711.85	% SZS status GaveUp for HL408436+5.p
155449.20/20711.85	eprover: CPU time limit exceeded, terminating
155449.20/20711.85	% SZS status Ended for HL408436+5.p
155456.67/20712.88	% SZS status Started for HL408443+4.p
155456.67/20712.88	% SZS status GaveUp for HL408443+4.p
155456.67/20712.88	eprover: CPU time limit exceeded, terminating
155456.67/20712.88	% SZS status Ended for HL408443+4.p
155459.98/20713.26	% SZS status Started for HL408437+5.p
155459.98/20713.26	% SZS status GaveUp for HL408437+5.p
155459.98/20713.26	eprover: CPU time limit exceeded, terminating
155459.98/20713.26	% SZS status Ended for HL408437+5.p
155471.92/20714.88	% SZS status Started for HL408438+5.p
155471.92/20714.88	% SZS status GaveUp for HL408438+5.p
155471.92/20714.88	eprover: CPU time limit exceeded, terminating
155471.92/20714.88	% SZS status Ended for HL408438+5.p
155471.92/20714.90	% SZS status Started for HL408444+4.p
155471.92/20714.90	% SZS status GaveUp for HL408444+4.p
155471.92/20714.90	eprover: CPU time limit exceeded, terminating
155471.92/20714.90	% SZS status Ended for HL408444+4.p
155484.42/20716.30	% SZS status Started for HL408447+4.p
155484.42/20716.30	% SZS status GaveUp for HL408447+4.p
155484.42/20716.30	eprover: CPU time limit exceeded, terminating
155484.42/20716.30	% SZS status Ended for HL408447+4.p
155486.97/20716.61	% SZS status Started for HL408439+5.p
155486.97/20716.61	% SZS status GaveUp for HL408439+5.p
155486.97/20716.61	eprover: CPU time limit exceeded, terminating
155486.97/20716.61	% SZS status Ended for HL408439+5.p
155497.53/20717.95	% SZS status Started for HL408448+4.p
155497.53/20717.95	% SZS status GaveUp for HL408448+4.p
155497.53/20717.95	eprover: CPU time limit exceeded, terminating
155497.53/20717.95	% SZS status Ended for HL408448+4.p
155503.28/20718.73	% SZS status Started for HL408441+5.p
155503.28/20718.73	% SZS status GaveUp for HL408441+5.p
155503.28/20718.73	eprover: CPU time limit exceeded, terminating
155503.28/20718.73	% SZS status Ended for HL408441+5.p
155510.38/20719.65	% SZS status Started for HL408451+4.p
155510.38/20719.65	% SZS status GaveUp for HL408451+4.p
155510.38/20719.65	eprover: CPU time limit exceeded, terminating
155510.38/20719.65	% SZS status Ended for HL408451+4.p
155514.44/20720.16	% SZS status Started for HL408442+5.p
155514.44/20720.16	% SZS status GaveUp for HL408442+5.p
155514.44/20720.16	eprover: CPU time limit exceeded, terminating
155514.44/20720.16	% SZS status Ended for HL408442+5.p
155527.59/20721.77	% SZS status Started for HL408453+4.p
155527.59/20721.77	% SZS status GaveUp for HL408453+4.p
155527.59/20721.77	eprover: CPU time limit exceeded, terminating
155527.59/20721.77	% SZS status Ended for HL408453+4.p
155533.62/20722.55	% SZS status Started for HL408443+5.p
155533.62/20722.55	% SZS status GaveUp for HL408443+5.p
155533.62/20722.55	eprover: CPU time limit exceeded, terminating
155533.62/20722.55	% SZS status Ended for HL408443+5.p
155539.12/20723.20	% SZS status Started for HL408454+4.p
155539.12/20723.20	% SZS status GaveUp for HL408454+4.p
155539.12/20723.20	eprover: CPU time limit exceeded, terminating
155539.12/20723.20	% SZS status Ended for HL408454+4.p
155546.94/20724.18	% SZS status Started for HL408444+5.p
155546.94/20724.18	% SZS status GaveUp for HL408444+5.p
155546.94/20724.18	eprover: CPU time limit exceeded, terminating
155546.94/20724.18	% SZS status Ended for HL408444+5.p
155558.05/20725.59	% SZS status Started for HL408455+4.p
155558.05/20725.59	% SZS status GaveUp for HL408455+4.p
155558.05/20725.59	eprover: CPU time limit exceeded, terminating
155558.05/20725.59	% SZS status Ended for HL408455+4.p
155558.36/20725.69	% SZS status Started for HL408447+5.p
155558.36/20725.69	% SZS status GaveUp for HL408447+5.p
155558.36/20725.69	eprover: CPU time limit exceeded, terminating
155558.36/20725.69	% SZS status Ended for HL408447+5.p
155570.42/20727.11	% SZS status Started for HL408448+5.p
155570.42/20727.11	% SZS status GaveUp for HL408448+5.p
155570.42/20727.11	eprover: CPU time limit exceeded, terminating
155570.42/20727.11	% SZS status Ended for HL408448+5.p
155571.33/20727.28	% SZS status Started for HL408456+4.p
155571.33/20727.28	% SZS status GaveUp for HL408456+4.p
155571.33/20727.28	eprover: CPU time limit exceeded, terminating
155571.33/20727.28	% SZS status Ended for HL408456+4.p
155582.64/20728.75	% SZS status Started for HL408451+5.p
155582.64/20728.75	% SZS status GaveUp for HL408451+5.p
155582.64/20728.75	eprover: CPU time limit exceeded, terminating
155582.64/20728.75	% SZS status Ended for HL408451+5.p
155584.47/20728.88	% SZS status Started for HL408457+4.p
155584.47/20728.88	% SZS status GaveUp for HL408457+4.p
155584.47/20728.88	eprover: CPU time limit exceeded, terminating
155584.47/20728.88	% SZS status Ended for HL408457+4.p
155595.83/20730.33	% SZS status Started for HL408458+4.p
155595.83/20730.33	% SZS status GaveUp for HL408458+4.p
155595.83/20730.33	eprover: CPU time limit exceeded, terminating
155595.83/20730.33	% SZS status Ended for HL408458+4.p
155596.55/20730.48	% SZS status Started for HL408453+5.p
155596.55/20730.48	% SZS status GaveUp for HL408453+5.p
155596.55/20730.48	eprover: CPU time limit exceeded, terminating
155596.55/20730.48	% SZS status Ended for HL408453+5.p
155607.75/20731.92	% SZS status Started for HL408459+4.p
155607.75/20731.92	% SZS status GaveUp for HL408459+4.p
155607.75/20731.92	eprover: CPU time limit exceeded, terminating
155607.75/20731.92	% SZS status Ended for HL408459+4.p
155612.70/20732.57	% SZS status Started for HL408454+5.p
155612.70/20732.57	% SZS status GaveUp for HL408454+5.p
155612.70/20732.57	eprover: CPU time limit exceeded, terminating
155612.70/20732.57	% SZS status Ended for HL408454+5.p
155621.23/20733.52	% SZS status Started for HL408460+4.p
155621.23/20733.52	% SZS status GaveUp for HL408460+4.p
155621.23/20733.52	eprover: CPU time limit exceeded, terminating
155621.23/20733.52	% SZS status Ended for HL408460+4.p
155624.81/20734.05	% SZS status Started for HL408455+5.p
155624.81/20734.05	% SZS status GaveUp for HL408455+5.p
155624.81/20734.05	eprover: CPU time limit exceeded, terminating
155624.81/20734.05	% SZS status Ended for HL408455+5.p
155638.02/20735.61	% SZS status Started for HL408461+4.p
155638.02/20735.61	% SZS status GaveUp for HL408461+4.p
155638.02/20735.61	eprover: CPU time limit exceeded, terminating
155638.02/20735.61	% SZS status Ended for HL408461+4.p
155643.88/20736.39	% SZS status Started for HL408456+5.p
155643.88/20736.39	% SZS status GaveUp for HL408456+5.p
155643.88/20736.39	eprover: CPU time limit exceeded, terminating
155643.88/20736.39	% SZS status Ended for HL408456+5.p
155649.42/20737.08	% SZS status Started for HL408462+4.p
155649.42/20737.08	% SZS status GaveUp for HL408462+4.p
155649.42/20737.08	eprover: CPU time limit exceeded, terminating
155649.42/20737.08	% SZS status Ended for HL408462+4.p
155655.41/20737.88	% SZS status Started for HL408457+5.p
155655.41/20737.88	% SZS status GaveUp for HL408457+5.p
155655.41/20737.88	eprover: CPU time limit exceeded, terminating
155655.41/20737.88	% SZS status Ended for HL408457+5.p
155667.91/20739.43	% SZS status Started for HL408463+4.p
155667.91/20739.43	% SZS status GaveUp for HL408463+4.p
155667.91/20739.43	eprover: CPU time limit exceeded, terminating
155667.91/20739.43	% SZS status Ended for HL408463+4.p
155674.00/20740.17	% SZS status Started for HL408458+5.p
155674.00/20740.17	% SZS status GaveUp for HL408458+5.p
155674.00/20740.17	eprover: CPU time limit exceeded, terminating
155674.00/20740.17	% SZS status Ended for HL408458+5.p
155680.02/20740.93	% SZS status Started for HL408464+4.p
155680.02/20740.93	% SZS status GaveUp for HL408464+4.p
155680.02/20740.93	eprover: CPU time limit exceeded, terminating
155680.02/20740.93	% SZS status Ended for HL408464+4.p
155681.56/20741.15	% SZS status Started for HL408459+5.p
155681.56/20741.15	% SZS status GaveUp for HL408459+5.p
155681.56/20741.15	eprover: CPU time limit exceeded, terminating
155681.56/20741.15	% SZS status Ended for HL408459+5.p
155693.45/20742.75	% SZS status Started for HL408460+5.p
155693.45/20742.75	% SZS status GaveUp for HL408460+5.p
155693.45/20742.75	eprover: CPU time limit exceeded, terminating
155693.45/20742.75	% SZS status Ended for HL408460+5.p
155698.48/20743.34	% SZS status Started for HL408465+4.p
155698.48/20743.34	% SZS status GaveUp for HL408465+4.p
155698.48/20743.34	eprover: CPU time limit exceeded, terminating
155698.48/20743.34	% SZS status Ended for HL408465+4.p
155706.14/20744.19	% SZS status Started for HL408466+4.p
155706.14/20744.19	% SZS status GaveUp for HL408466+4.p
155706.14/20744.19	eprover: CPU time limit exceeded, terminating
155706.14/20744.19	% SZS status Ended for HL408466+4.p
155707.17/20744.35	% SZS status Started for HL408461+5.p
155707.17/20744.35	% SZS status GaveUp for HL408461+5.p
155707.17/20744.35	eprover: CPU time limit exceeded, terminating
155707.17/20744.35	% SZS status Ended for HL408461+5.p
155723.28/20746.37	% SZS status Started for HL408467+4.p
155723.28/20746.37	% SZS status GaveUp for HL408467+4.p
155723.28/20746.37	eprover: CPU time limit exceeded, terminating
155723.28/20746.37	% SZS status Ended for HL408467+4.p
155723.77/20746.43	% SZS status Started for HL408462+5.p
155723.77/20746.43	% SZS status GaveUp for HL408462+5.p
155723.77/20746.43	eprover: CPU time limit exceeded, terminating
155723.77/20746.43	% SZS status Ended for HL408462+5.p
155731.23/20747.39	% SZS status Started for HL408468+4.p
155731.23/20747.39	% SZS status GaveUp for HL408468+4.p
155731.23/20747.39	eprover: CPU time limit exceeded, terminating
155731.23/20747.39	% SZS status Ended for HL408468+4.p
155734.69/20747.82	% SZS status Started for HL408463+5.p
155734.69/20747.82	% SZS status GaveUp for HL408463+5.p
155734.69/20747.82	eprover: CPU time limit exceeded, terminating
155734.69/20747.82	% SZS status Ended for HL408463+5.p
155746.83/20749.48	% SZS status Started for HL408470+4.p
155746.83/20749.48	% SZS status GaveUp for HL408470+4.p
155746.83/20749.48	eprover: CPU time limit exceeded, terminating
155746.83/20749.48	% SZS status Ended for HL408470+4.p
155754.28/20750.31	% SZS status Started for HL408464+5.p
155754.28/20750.31	% SZS status GaveUp for HL408464+5.p
155754.28/20750.31	eprover: CPU time limit exceeded, terminating
155754.28/20750.31	% SZS status Ended for HL408464+5.p
155759.00/20750.86	% SZS status Started for HL408472+4.p
155759.00/20750.86	% SZS status GaveUp for HL408472+4.p
155759.00/20750.86	eprover: CPU time limit exceeded, terminating
155759.00/20750.86	% SZS status Ended for HL408472+4.p
155766.14/20751.82	% SZS status Started for HL408465+5.p
155766.14/20751.82	% SZS status GaveUp for HL408465+5.p
155766.14/20751.82	eprover: CPU time limit exceeded, terminating
155766.14/20751.82	% SZS status Ended for HL408465+5.p
155778.08/20753.35	% SZS status Started for HL408473+4.p
155778.08/20753.35	% SZS status GaveUp for HL408473+4.p
155778.08/20753.35	eprover: CPU time limit exceeded, terminating
155778.08/20753.35	% SZS status Ended for HL408473+4.p
155782.89/20753.87	% SZS status Started for HL408466+5.p
155782.89/20753.87	% SZS status GaveUp for HL408466+5.p
155782.89/20753.87	eprover: CPU time limit exceeded, terminating
155782.89/20753.87	% SZS status Ended for HL408466+5.p
155790.91/20754.85	% SZS status Started for HL408474+4.p
155790.91/20754.85	% SZS status GaveUp for HL408474+4.p
155790.91/20754.85	eprover: CPU time limit exceeded, terminating
155790.91/20754.85	% SZS status Ended for HL408474+4.p
155796.44/20755.64	% SZS status Started for HL408467+5.p
155796.44/20755.64	% SZS status GaveUp for HL408467+5.p
155796.44/20755.64	eprover: CPU time limit exceeded, terminating
155796.44/20755.64	% SZS status Ended for HL408467+5.p
155805.94/20756.91	% SZS status Started for HL408475+4.p
155805.94/20756.91	% SZS status GaveUp for HL408475+4.p
155805.94/20756.91	eprover: CPU time limit exceeded, terminating
155805.94/20756.91	% SZS status Ended for HL408475+4.p
155808.69/20757.23	% SZS status Started for HL408468+5.p
155808.69/20757.23	% SZS status GaveUp for HL408468+5.p
155808.69/20757.23	eprover: CPU time limit exceeded, terminating
155808.69/20757.23	% SZS status Ended for HL408468+5.p
155818.16/20758.41	% SZS status Started for HL408470+5.p
155818.16/20758.41	% SZS status GaveUp for HL408470+5.p
155818.16/20758.41	eprover: CPU time limit exceeded, terminating
155818.16/20758.41	% SZS status Ended for HL408470+5.p
155819.86/20758.68	% SZS status Started for HL408476+4.p
155819.86/20758.68	% SZS status GaveUp for HL408476+4.p
155819.86/20758.68	eprover: CPU time limit exceeded, terminating
155819.86/20758.68	% SZS status Ended for HL408476+4.p
155833.14/20760.27	% SZS status Started for HL408477+4.p
155833.14/20760.27	% SZS status GaveUp for HL408477+4.p
155833.14/20760.27	eprover: CPU time limit exceeded, terminating
155833.14/20760.27	% SZS status Ended for HL408477+4.p
155833.73/20760.34	% SZS status Started for HL408472+5.p
155833.73/20760.34	% SZS status GaveUp for HL408472+5.p
155833.73/20760.34	eprover: CPU time limit exceeded, terminating
155833.73/20760.34	% SZS status Ended for HL408472+5.p
155843.22/20761.63	% SZS status Started for HL408473+5.p
155843.22/20761.63	% SZS status GaveUp for HL408473+5.p
155843.22/20761.63	eprover: CPU time limit exceeded, terminating
155843.22/20761.63	% SZS status Ended for HL408473+5.p
155844.39/20761.71	% SZS status Started for HL408478+4.p
155844.39/20761.71	% SZS status GaveUp for HL408478+4.p
155844.39/20761.71	eprover: CPU time limit exceeded, terminating
155844.39/20761.71	% SZS status Ended for HL408478+4.p
155857.22/20763.38	% SZS status Started for HL408479+4.p
155857.22/20763.38	% SZS status GaveUp for HL408479+4.p
155857.22/20763.38	eprover: CPU time limit exceeded, terminating
155857.22/20763.38	% SZS status Ended for HL408479+4.p
155864.03/20764.21	% SZS status Started for HL408474+5.p
155864.03/20764.21	% SZS status GaveUp for HL408474+5.p
155864.03/20764.21	eprover: CPU time limit exceeded, terminating
155864.03/20764.21	% SZS status Ended for HL408474+5.p
155868.75/20764.75	% SZS status Started for HL408480+4.p
155868.75/20764.75	% SZS status GaveUp for HL408480+4.p
155868.75/20764.75	eprover: CPU time limit exceeded, terminating
155868.75/20764.75	% SZS status Ended for HL408480+4.p
155881.80/20766.41	% SZS status Started for HL408475+5.p
155881.80/20766.41	% SZS status GaveUp for HL408475+5.p
155881.80/20766.41	eprover: CPU time limit exceeded, terminating
155881.80/20766.41	% SZS status Ended for HL408475+5.p
155888.41/20767.25	% SZS status Started for HL408481+4.p
155888.41/20767.25	% SZS status GaveUp for HL408481+4.p
155888.41/20767.25	eprover: CPU time limit exceeded, terminating
155888.41/20767.25	% SZS status Ended for HL408481+4.p
155892.17/20767.76	% SZS status Started for HL408476+5.p
155892.17/20767.76	% SZS status GaveUp for HL408476+5.p
155892.17/20767.76	eprover: CPU time limit exceeded, terminating
155892.17/20767.76	% SZS status Ended for HL408476+5.p
155904.88/20769.38	% SZS status Started for HL408477+5.p
155904.88/20769.38	% SZS status GaveUp for HL408477+5.p
155904.88/20769.38	eprover: CPU time limit exceeded, terminating
155904.88/20769.38	% SZS status Ended for HL408477+5.p
155905.31/20769.45	% SZS status Started for HL408482+4.p
155905.31/20769.45	% SZS status GaveUp for HL408482+4.p
155905.31/20769.45	eprover: CPU time limit exceeded, terminating
155905.31/20769.45	% SZS status Ended for HL408482+4.p
155916.34/20770.79	% SZS status Started for HL408483+4.p
155916.34/20770.79	% SZS status GaveUp for HL408483+4.p
155916.34/20770.79	eprover: CPU time limit exceeded, terminating
155916.34/20770.79	% SZS status Ended for HL408483+4.p
155918.78/20771.13	% SZS status Started for HL408478+5.p
155918.78/20771.13	% SZS status GaveUp for HL408478+5.p
155918.78/20771.13	eprover: CPU time limit exceeded, terminating
155918.78/20771.13	% SZS status Ended for HL408478+5.p
155929.11/20772.49	% SZS status Started for HL408484+4.p
155929.11/20772.49	% SZS status GaveUp for HL408484+4.p
155929.11/20772.49	eprover: CPU time limit exceeded, terminating
155929.11/20772.49	% SZS status Ended for HL408484+4.p
155930.55/20772.51	% SZS status Started for HL408479+5.p
155930.55/20772.51	% SZS status GaveUp for HL408479+5.p
155930.55/20772.51	eprover: CPU time limit exceeded, terminating
155930.55/20772.51	% SZS status Ended for HL408479+5.p
155943.00/20774.18	% SZS status Started for HL408485+4.p
155943.00/20774.18	% SZS status GaveUp for HL408485+4.p
155943.00/20774.18	eprover: CPU time limit exceeded, terminating
155943.00/20774.18	% SZS status Ended for HL408485+4.p
155944.44/20774.27	% SZS status Started for HL408480+5.p
155944.44/20774.27	% SZS status GaveUp for HL408480+5.p
155944.44/20774.27	eprover: CPU time limit exceeded, terminating
155944.44/20774.27	% SZS status Ended for HL408480+5.p
155954.94/20775.70	% SZS status Started for HL408486+4.p
155954.94/20775.70	% SZS status GaveUp for HL408486+4.p
155954.94/20775.70	eprover: CPU time limit exceeded, terminating
155954.94/20775.70	% SZS status Ended for HL408486+4.p
155955.91/20775.84	% SZS status Started for HL408481+5.p
155955.91/20775.84	% SZS status GaveUp for HL408481+5.p
155955.91/20775.84	eprover: CPU time limit exceeded, terminating
155955.91/20775.84	% SZS status Ended for HL408481+5.p
155968.03/20777.32	% SZS status Started for HL408487+4.p
155968.03/20777.32	% SZS status GaveUp for HL408487+4.p
155968.03/20777.32	eprover: CPU time limit exceeded, terminating
155968.03/20777.32	% SZS status Ended for HL408487+4.p
155974.06/20778.10	% SZS status Started for HL408482+5.p
155974.06/20778.10	% SZS status GaveUp for HL408482+5.p
155974.06/20778.10	eprover: CPU time limit exceeded, terminating
155974.06/20778.10	% SZS status Ended for HL408482+5.p
155980.72/20778.88	% SZS status Started for HL408488+4.p
155980.72/20778.88	% SZS status GaveUp for HL408488+4.p
155980.72/20778.88	eprover: CPU time limit exceeded, terminating
155980.72/20778.88	% SZS status Ended for HL408488+4.p
155991.25/20780.19	% SZS status Started for HL408483+5.p
155991.25/20780.19	% SZS status GaveUp for HL408483+5.p
155991.25/20780.19	eprover: CPU time limit exceeded, terminating
155991.25/20780.19	% SZS status Ended for HL408483+5.p
155998.61/20781.14	% SZS status Started for HL408489+4.p
155998.61/20781.14	% SZS status GaveUp for HL408489+4.p
155998.61/20781.14	eprover: CPU time limit exceeded, terminating
155998.61/20781.14	% SZS status Ended for HL408489+4.p
156003.64/20781.75	% SZS status Started for HL408484+5.p
156003.64/20781.75	% SZS status GaveUp for HL408484+5.p
156003.64/20781.75	eprover: CPU time limit exceeded, terminating
156003.64/20781.75	% SZS status Ended for HL408484+5.p
156015.16/20783.22	% SZS status Started for HL408490+4.p
156015.16/20783.22	% SZS status GaveUp for HL408490+4.p
156015.16/20783.22	eprover: CPU time limit exceeded, terminating
156015.16/20783.22	% SZS status Ended for HL408490+4.p
156016.14/20783.38	% SZS status Started for HL408485+5.p
156016.14/20783.38	% SZS status GaveUp for HL408485+5.p
156016.14/20783.38	eprover: CPU time limit exceeded, terminating
156016.14/20783.38	% SZS status Ended for HL408485+5.p
156027.72/20784.79	% SZS status Started for HL408491+4.p
156027.72/20784.79	% SZS status GaveUp for HL408491+4.p
156027.72/20784.79	eprover: CPU time limit exceeded, terminating
156027.72/20784.79	% SZS status Ended for HL408491+4.p
156029.36/20785.05	% SZS status Started for HL408486+5.p
156029.36/20785.05	% SZS status GaveUp for HL408486+5.p
156029.36/20785.05	eprover: CPU time limit exceeded, terminating
156029.36/20785.05	% SZS status Ended for HL408486+5.p
156039.97/20786.43	% SZS status Started for HL408493+4.p
156039.97/20786.43	% SZS status GaveUp for HL408493+4.p
156039.97/20786.43	eprover: CPU time limit exceeded, terminating
156039.97/20786.43	% SZS status Ended for HL408493+4.p
156046.31/20787.12	% SZS status Started for HL408487+5.p
156046.31/20787.12	% SZS status GaveUp for HL408487+5.p
156046.31/20787.12	eprover: CPU time limit exceeded, terminating
156046.31/20787.12	% SZS status Ended for HL408487+5.p
156054.06/20788.09	% SZS status Started for HL408494+4.p
156054.06/20788.09	% SZS status GaveUp for HL408494+4.p
156054.06/20788.09	eprover: CPU time limit exceeded, terminating
156054.06/20788.09	% SZS status Ended for HL408494+4.p
156054.86/20788.18	% SZS status Started for HL408488+5.p
156054.86/20788.18	% SZS status GaveUp for HL408488+5.p
156054.86/20788.18	eprover: CPU time limit exceeded, terminating
156054.86/20788.18	% SZS status Ended for HL408488+5.p
156067.23/20789.76	% SZS status Started for HL408489+5.p
156067.23/20789.76	% SZS status GaveUp for HL408489+5.p
156067.23/20789.76	eprover: CPU time limit exceeded, terminating
156067.23/20789.76	% SZS status Ended for HL408489+5.p
156070.28/20790.21	% SZS status Started for HL408496+4.p
156070.28/20790.21	% SZS status GaveUp for HL408496+4.p
156070.28/20790.21	eprover: CPU time limit exceeded, terminating
156070.28/20790.21	% SZS status Ended for HL408496+4.p
156078.89/20791.22	% SZS status Started for HL408497+4.p
156078.89/20791.22	% SZS status GaveUp for HL408497+4.p
156078.89/20791.22	eprover: CPU time limit exceeded, terminating
156078.89/20791.22	% SZS status Ended for HL408497+4.p
156084.38/20792.01	% SZS status Started for HL408490+5.p
156084.38/20792.01	% SZS status GaveUp for HL408490+5.p
156084.38/20792.01	eprover: CPU time limit exceeded, terminating
156084.38/20792.01	% SZS status Ended for HL408490+5.p
156095.02/20793.25	% SZS status Started for HL408498+4.p
156095.02/20793.25	% SZS status GaveUp for HL408498+4.p
156095.02/20793.25	eprover: CPU time limit exceeded, terminating
156095.02/20793.25	% SZS status Ended for HL408498+4.p
156100.56/20793.97	% SZS status Started for HL408491+5.p
156100.56/20793.97	% SZS status GaveUp for HL408491+5.p
156100.56/20793.97	eprover: CPU time limit exceeded, terminating
156100.56/20793.97	% SZS status Ended for HL408491+5.p
156109.59/20795.04	% SZS status Started for HL408499+4.p
156109.59/20795.04	% SZS status GaveUp for HL408499+4.p
156109.59/20795.04	eprover: CPU time limit exceeded, terminating
156109.59/20795.04	% SZS status Ended for HL408499+4.p
156114.28/20795.66	% SZS status Started for HL408493+5.p
156114.28/20795.66	% SZS status GaveUp for HL408493+5.p
156114.28/20795.66	eprover: CPU time limit exceeded, terminating
156114.28/20795.66	% SZS status Ended for HL408493+5.p
156125.16/20797.00	% SZS status Started for HL408500+4.p
156125.16/20797.00	% SZS status GaveUp for HL408500+4.p
156125.16/20797.00	eprover: CPU time limit exceeded, terminating
156125.16/20797.00	% SZS status Ended for HL408500+4.p
156126.72/20797.41	% SZS status Started for HL408494+5.p
156126.72/20797.41	% SZS status GaveUp for HL408494+5.p
156126.72/20797.41	eprover: CPU time limit exceeded, terminating
156126.72/20797.41	% SZS status Ended for HL408494+5.p
156138.81/20798.70	% SZS status Started for HL408501+4.p
156138.81/20798.70	% SZS status GaveUp for HL408501+4.p
156138.81/20798.70	eprover: CPU time limit exceeded, terminating
156138.81/20798.70	% SZS status Ended for HL408501+4.p
156140.06/20798.91	% SZS status Started for HL408496+5.p
156140.06/20798.91	% SZS status GaveUp for HL408496+5.p
156140.06/20798.91	eprover: CPU time limit exceeded, terminating
156140.06/20798.91	% SZS status Ended for HL408496+5.p
156148.50/20799.98	% SZS status Started for HL408497+5.p
156148.50/20799.98	% SZS status GaveUp for HL408497+5.p
156148.50/20799.98	eprover: CPU time limit exceeded, terminating
156148.50/20799.98	% SZS status Ended for HL408497+5.p
156152.41/20800.47	% SZS status Started for HL408502+4.p
156152.41/20800.47	% SZS status GaveUp for HL408502+4.p
156152.41/20800.47	eprover: CPU time limit exceeded, terminating
156152.41/20800.47	% SZS status Ended for HL408502+4.p
156164.20/20801.94	% SZS status Started for HL408504+4.p
156164.20/20801.94	% SZS status GaveUp for HL408504+4.p
156164.20/20801.94	eprover: CPU time limit exceeded, terminating
156164.20/20801.94	% SZS status Ended for HL408504+4.p
156177.08/20803.50	% SZS status Started for HL408505+4.p
156177.08/20803.50	% SZS status GaveUp for HL408505+4.p
156177.08/20803.50	eprover: CPU time limit exceeded, terminating
156177.08/20803.50	% SZS status Ended for HL408505+4.p
156201.08/20806.57	% SZS status Started for HL408506+4.p
156201.08/20806.57	% SZS status GaveUp for HL408506+4.p
156201.08/20806.57	eprover: CPU time limit exceeded, terminating
156201.08/20806.57	% SZS status Ended for HL408506+4.p
156281.39/20816.75	% SZS status Started for HL408506+5.p
156281.39/20816.75	% SZS status GaveUp for HL408506+5.p
156281.39/20816.75	eprover: CPU time limit exceeded, terminating
156281.39/20816.75	% SZS status Ended for HL408506+5.p
156286.88/20817.44	% SZS status Started for HL408498+5.p
156286.88/20817.44	% SZS status GaveUp for HL408498+5.p
156286.88/20817.44	eprover: CPU time limit exceeded, terminating
156286.88/20817.44	% SZS status Ended for HL408498+5.p
156301.69/20819.26	% SZS status Started for HL408499+5.p
156301.69/20819.26	% SZS status GaveUp for HL408499+5.p
156301.69/20819.26	eprover: CPU time limit exceeded, terminating
156301.69/20819.26	% SZS status Ended for HL408499+5.p
156305.81/20819.77	% SZS status Started for HL408507+4.p
156305.81/20819.77	% SZS status GaveUp for HL408507+4.p
156305.81/20819.77	eprover: CPU time limit exceeded, terminating
156305.81/20819.77	% SZS status Ended for HL408507+4.p
156317.11/20821.17	% SZS status Started for HL408500+5.p
156317.11/20821.17	% SZS status GaveUp for HL408500+5.p
156317.11/20821.17	eprover: CPU time limit exceeded, terminating
156317.11/20821.17	% SZS status Ended for HL408500+5.p
156325.75/20822.30	% SZS status Started for HL408508+4.p
156325.75/20822.30	% SZS status GaveUp for HL408508+4.p
156325.75/20822.30	eprover: CPU time limit exceeded, terminating
156325.75/20822.30	% SZS status Ended for HL408508+4.p
156335.44/20823.55	% SZS status Started for HL408501+5.p
156335.44/20823.55	% SZS status GaveUp for HL408501+5.p
156335.44/20823.55	eprover: CPU time limit exceeded, terminating
156335.44/20823.55	% SZS status Ended for HL408501+5.p
156341.03/20824.19	% SZS status Started for HL408509+4.p
156341.03/20824.19	% SZS status GaveUp for HL408509+4.p
156341.03/20824.19	eprover: CPU time limit exceeded, terminating
156341.03/20824.19	% SZS status Ended for HL408509+4.p
156346.56/20824.92	% SZS status Started for HL408502+5.p
156346.56/20824.92	% SZS status GaveUp for HL408502+5.p
156346.56/20824.92	eprover: CPU time limit exceeded, terminating
156346.56/20824.92	% SZS status Ended for HL408502+5.p
156355.14/20826.08	% SZS status Started for HL408504+5.p
156355.14/20826.08	% SZS status GaveUp for HL408504+5.p
156355.14/20826.08	eprover: CPU time limit exceeded, terminating
156355.14/20826.08	% SZS status Ended for HL408504+5.p
156358.84/20826.58	% SZS status Started for HL408511+4.p
156358.84/20826.58	% SZS status GaveUp for HL408511+4.p
156358.84/20826.58	eprover: CPU time limit exceeded, terminating
156358.84/20826.58	% SZS status Ended for HL408511+4.p
156370.42/20827.96	% SZS status Started for HL408512+4.p
156370.42/20827.96	% SZS status GaveUp for HL408512+4.p
156370.42/20827.96	eprover: CPU time limit exceeded, terminating
156370.42/20827.96	% SZS status Ended for HL408512+4.p
156372.17/20828.17	% SZS status Started for HL408505+5.p
156372.17/20828.17	% SZS status GaveUp for HL408505+5.p
156372.17/20828.17	eprover: CPU time limit exceeded, terminating
156372.17/20828.17	% SZS status Ended for HL408505+5.p
156384.30/20829.63	% SZS status Started for HL408513+4.p
156384.30/20829.63	% SZS status GaveUp for HL408513+4.p
156384.30/20829.63	eprover: CPU time limit exceeded, terminating
156384.30/20829.63	% SZS status Ended for HL408513+4.p
156389.83/20830.31	% SZS status Started for HL408508+5.p
156389.83/20830.31	% SZS status GaveUp for HL408508+5.p
156389.83/20830.31	eprover: CPU time limit exceeded, terminating
156389.83/20830.31	% SZS status Ended for HL408508+5.p
156397.00/20831.27	% SZS status Started for HL408514+4.p
156397.00/20831.27	% SZS status GaveUp for HL408514+4.p
156397.00/20831.27	eprover: CPU time limit exceeded, terminating
156397.00/20831.27	% SZS status Ended for HL408514+4.p
156413.75/20833.36	% SZS status Started for HL408515+4.p
156413.75/20833.36	% SZS status GaveUp for HL408515+4.p
156413.75/20833.36	eprover: CPU time limit exceeded, terminating
156413.75/20833.36	% SZS status Ended for HL408515+4.p
156438.64/20836.51	% SZS status Started for HL408517+4.p
156438.64/20836.51	% SZS status GaveUp for HL408517+4.p
156438.64/20836.51	eprover: CPU time limit exceeded, terminating
156438.64/20836.51	% SZS status Ended for HL408517+4.p
156495.14/20843.59	% SZS status Started for HL408507+5.p
156495.14/20843.59	% SZS status GaveUp for HL408507+5.p
156495.14/20843.59	eprover: CPU time limit exceeded, terminating
156495.14/20843.59	% SZS status Ended for HL408507+5.p
156519.09/20846.63	% SZS status Started for HL408518+4.p
156519.09/20846.63	% SZS status GaveUp for HL408518+4.p
156519.09/20846.63	eprover: CPU time limit exceeded, terminating
156519.09/20846.63	% SZS status Ended for HL408518+4.p
156534.83/20848.63	% SZS status Started for HL408509+5.p
156534.83/20848.63	% SZS status GaveUp for HL408509+5.p
156534.83/20848.63	eprover: CPU time limit exceeded, terminating
156534.83/20848.63	% SZS status Ended for HL408509+5.p
156548.41/20850.32	% SZS status Started for HL408511+5.p
156548.41/20850.32	% SZS status GaveUp for HL408511+5.p
156548.41/20850.32	eprover: CPU time limit exceeded, terminating
156548.41/20850.32	% SZS status Ended for HL408511+5.p
156559.09/20851.70	% SZS status Started for HL408519+4.p
156559.09/20851.70	% SZS status GaveUp for HL408519+4.p
156559.09/20851.70	eprover: CPU time limit exceeded, terminating
156559.09/20851.70	% SZS status Ended for HL408519+4.p
156563.98/20852.27	% SZS status Started for HL408512+5.p
156563.98/20852.27	% SZS status GaveUp for HL408512+5.p
156563.98/20852.27	eprover: CPU time limit exceeded, terminating
156563.98/20852.27	% SZS status Ended for HL408512+5.p
156579.77/20854.23	% SZS status Started for HL408513+5.p
156579.77/20854.23	% SZS status GaveUp for HL408513+5.p
156579.77/20854.23	eprover: CPU time limit exceeded, terminating
156579.77/20854.23	% SZS status Ended for HL408513+5.p
156583.19/20854.81	% SZS status Started for HL408520+4.p
156583.19/20854.81	% SZS status GaveUp for HL408520+4.p
156583.19/20854.81	eprover: CPU time limit exceeded, terminating
156583.19/20854.81	% SZS status Ended for HL408520+4.p
156593.05/20855.91	% SZS status Started for HL408514+5.p
156593.05/20855.91	% SZS status GaveUp for HL408514+5.p
156593.05/20855.91	eprover: CPU time limit exceeded, terminating
156593.05/20855.91	% SZS status Ended for HL408514+5.p
156603.72/20857.29	% SZS status Started for HL408521+4.p
156603.72/20857.29	% SZS status GaveUp for HL408521+4.p
156603.72/20857.29	eprover: CPU time limit exceeded, terminating
156603.72/20857.29	% SZS status Ended for HL408521+4.p
156605.62/20857.53	% SZS status Started for HL408515+5.p
156605.62/20857.53	% SZS status GaveUp for HL408515+5.p
156605.62/20857.53	eprover: CPU time limit exceeded, terminating
156605.62/20857.53	% SZS status Ended for HL408515+5.p
156616.56/20858.95	% SZS status Started for HL408522+4.p
156616.56/20858.95	% SZS status GaveUp for HL408522+4.p
156616.56/20858.95	eprover: CPU time limit exceeded, terminating
156616.56/20858.95	% SZS status Ended for HL408522+4.p
156630.64/20860.64	% SZS status Started for HL408523+4.p
156630.64/20860.64	% SZS status GaveUp for HL408523+4.p
156630.64/20860.64	eprover: CPU time limit exceeded, terminating
156630.64/20860.64	% SZS status Ended for HL408523+4.p
156645.22/20862.53	% SZS status Started for HL408520+5.p
156645.22/20862.53	% SZS status GaveUp for HL408520+5.p
156645.22/20862.53	eprover: CPU time limit exceeded, terminating
156645.22/20862.53	% SZS status Ended for HL408520+5.p
156646.22/20862.67	% SZS status Started for HL408517+5.p
156646.22/20862.67	% SZS status GaveUp for HL408517+5.p
156646.22/20862.67	eprover: CPU time limit exceeded, terminating
156646.22/20862.67	% SZS status Ended for HL408517+5.p
156654.92/20863.71	% SZS status Started for HL408525+4.p
156654.92/20863.71	% SZS status GaveUp for HL408525+4.p
156654.92/20863.71	eprover: CPU time limit exceeded, terminating
156654.92/20863.71	% SZS status Ended for HL408525+4.p
156666.28/20865.22	% SZS status Started for HL408521+5.p
156666.28/20865.22	% SZS status GaveUp for HL408521+5.p
156666.28/20865.22	eprover: CPU time limit exceeded, terminating
156666.28/20865.22	% SZS status Ended for HL408521+5.p
156670.20/20865.71	% SZS status Started for HL408526+4.p
156670.20/20865.71	% SZS status GaveUp for HL408526+4.p
156670.20/20865.71	eprover: CPU time limit exceeded, terminating
156670.20/20865.71	% SZS status Ended for HL408526+4.p
156690.80/20868.26	% SZS status Started for HL408527+4.p
156690.80/20868.26	% SZS status GaveUp for HL408527+4.p
156690.80/20868.26	eprover: CPU time limit exceeded, terminating
156690.80/20868.26	% SZS status Ended for HL408527+4.p
156714.69/20871.33	% SZS status Started for HL408528+4.p
156714.69/20871.33	% SZS status GaveUp for HL408528+4.p
156714.69/20871.33	eprover: CPU time limit exceeded, terminating
156714.69/20871.33	% SZS status Ended for HL408528+4.p
156726.47/20872.75	% SZS status Started for HL408518+5.p
156726.47/20872.75	% SZS status GaveUp for HL408518+5.p
156726.47/20872.75	eprover: CPU time limit exceeded, terminating
156726.47/20872.75	% SZS status Ended for HL408518+5.p
156750.88/20875.82	% SZS status Started for HL408529+4.p
156750.88/20875.82	% SZS status GaveUp for HL408529+4.p
156750.88/20875.82	eprover: CPU time limit exceeded, terminating
156750.88/20875.82	% SZS status Ended for HL408529+4.p
156756.98/20876.65	% SZS status Started for HL408519+5.p
156756.98/20876.65	% SZS status GaveUp for HL408519+5.p
156756.98/20876.65	eprover: CPU time limit exceeded, terminating
156756.98/20876.65	% SZS status Ended for HL408519+5.p
156780.77/20879.69	% SZS status Started for HL408531+4.p
156780.77/20879.69	% SZS status GaveUp for HL408531+4.p
156780.77/20879.69	eprover: CPU time limit exceeded, terminating
156780.77/20879.69	% SZS status Ended for HL408531+4.p
156812.69/20883.65	% SZS status Started for HL408522+5.p
156812.69/20883.65	% SZS status GaveUp for HL408522+5.p
156812.69/20883.65	eprover: CPU time limit exceeded, terminating
156812.69/20883.65	% SZS status Ended for HL408522+5.p
156824.83/20885.15	% SZS status Started for HL408523+5.p
156824.83/20885.15	% SZS status GaveUp for HL408523+5.p
156824.83/20885.15	eprover: CPU time limit exceeded, terminating
156824.83/20885.15	% SZS status Ended for HL408523+5.p
156837.39/20886.72	% SZS status Started for HL408532+4.p
156837.39/20886.72	% SZS status GaveUp for HL408532+4.p
156837.39/20886.72	eprover: CPU time limit exceeded, terminating
156837.39/20886.72	% SZS status Ended for HL408532+4.p
156853.45/20888.71	% SZS status Started for HL408525+5.p
156853.45/20888.71	% SZS status GaveUp for HL408525+5.p
156853.45/20888.71	eprover: CPU time limit exceeded, terminating
156853.45/20888.71	% SZS status Ended for HL408525+5.p
156861.47/20889.76	% SZS status Started for HL408533+4.p
156861.47/20889.76	% SZS status GaveUp for HL408533+4.p
156861.47/20889.76	eprover: CPU time limit exceeded, terminating
156861.47/20889.76	% SZS status Ended for HL408533+4.p
156862.50/20889.90	% SZS status Started for HL408526+5.p
156862.50/20889.90	% SZS status GaveUp for HL408526+5.p
156862.50/20889.90	eprover: CPU time limit exceeded, terminating
156862.50/20889.90	% SZS status Ended for HL408526+5.p
156879.50/20892.00	% SZS status Started for HL408527+5.p
156879.50/20892.00	% SZS status GaveUp for HL408527+5.p
156879.50/20892.00	eprover: CPU time limit exceeded, terminating
156879.50/20892.00	% SZS status Ended for HL408527+5.p
156886.28/20892.85	% SZS status Started for HL408534+4.p
156886.28/20892.85	% SZS status GaveUp for HL408534+4.p
156886.28/20892.85	eprover: CPU time limit exceeded, terminating
156886.28/20892.85	% SZS status Ended for HL408534+4.p
156903.70/20895.06	% SZS status Started for HL408535+4.p
156903.70/20895.06	% SZS status GaveUp for HL408535+4.p
156903.70/20895.06	eprover: CPU time limit exceeded, terminating
156903.70/20895.06	% SZS status Ended for HL408535+4.p
156922.69/20897.47	% SZS status Started for HL408528+5.p
156922.69/20897.47	% SZS status GaveUp for HL408528+5.p
156922.69/20897.47	eprover: CPU time limit exceeded, terminating
156922.69/20897.47	% SZS status Ended for HL408528+5.p
156927.52/20898.10	% SZS status Started for HL408537+4.p
156927.52/20898.10	% SZS status GaveUp for HL408537+4.p
156927.52/20898.10	eprover: CPU time limit exceeded, terminating
156927.52/20898.10	% SZS status Ended for HL408537+4.p
156951.78/20901.14	% SZS status Started for HL408538+4.p
156951.78/20901.14	% SZS status GaveUp for HL408538+4.p
156951.78/20901.14	eprover: CPU time limit exceeded, terminating
156951.78/20901.14	% SZS status Ended for HL408538+4.p
156959.91/20902.18	% SZS status Started for HL408529+5.p
156959.91/20902.18	% SZS status GaveUp for HL408529+5.p
156959.91/20902.18	eprover: CPU time limit exceeded, terminating
156959.91/20902.18	% SZS status Ended for HL408529+5.p
156984.42/20905.27	% SZS status Started for HL408539+4.p
156984.42/20905.27	% SZS status GaveUp for HL408539+4.p
156984.42/20905.27	eprover: CPU time limit exceeded, terminating
156984.42/20905.27	% SZS status Ended for HL408539+4.p
156989.55/20905.94	% SZS status Started for HL408531+5.p
156989.55/20905.94	% SZS status GaveUp for HL408531+5.p
156989.55/20905.94	eprover: CPU time limit exceeded, terminating
156989.55/20905.94	% SZS status Ended for HL408531+5.p
157013.78/20909.04	% SZS status Started for HL408541+4.p
157013.78/20909.04	% SZS status GaveUp for HL408541+4.p
157013.78/20909.04	eprover: CPU time limit exceeded, terminating
157013.78/20909.04	% SZS status Ended for HL408541+4.p
157032.92/20911.33	% SZS status Started for HL408532+5.p
157032.92/20911.33	% SZS status GaveUp for HL408532+5.p
157032.92/20911.33	eprover: CPU time limit exceeded, terminating
157032.92/20911.33	% SZS status Ended for HL408532+5.p
157055.17/20914.13	% SZS status Started for HL408534+5.p
157055.17/20914.13	% SZS status GaveUp for HL408534+5.p
157055.17/20914.13	eprover: CPU time limit exceeded, terminating
157055.17/20914.13	% SZS status Ended for HL408534+5.p
157056.50/20914.36	% SZS status Started for HL408542+4.p
157056.50/20914.36	% SZS status GaveUp for HL408542+4.p
157056.50/20914.36	eprover: CPU time limit exceeded, terminating
157056.50/20914.36	% SZS status Ended for HL408542+4.p
157062.84/20915.23	% SZS status Started for HL408533+5.p
157062.84/20915.23	% SZS status GaveUp for HL408533+5.p
157062.84/20915.23	eprover: CPU time limit exceeded, terminating
157062.84/20915.23	% SZS status Ended for HL408533+5.p
157068.47/20915.82	% SZS status Started for HL408539+5.p
157068.47/20915.82	% SZS status GaveUp for HL408539+5.p
157068.47/20915.82	eprover: CPU time limit exceeded, terminating
157068.47/20915.82	% SZS status Ended for HL408539+5.p
157080.59/20917.40	% SZS status Started for HL408544+4.p
157080.59/20917.40	% SZS status GaveUp for HL408544+4.p
157080.59/20917.40	eprover: CPU time limit exceeded, terminating
157080.59/20917.40	% SZS status Ended for HL408544+4.p
157092.02/20918.89	% SZS status Started for HL408545+4.p
157092.02/20918.89	% SZS status GaveUp for HL408545+4.p
157092.02/20918.89	eprover: CPU time limit exceeded, terminating
157092.02/20918.89	% SZS status Ended for HL408545+4.p
157094.91/20919.17	% SZS status Started for HL408535+5.p
157094.91/20919.17	% SZS status GaveUp for HL408535+5.p
157094.91/20919.17	eprover: CPU time limit exceeded, terminating
157094.91/20919.17	% SZS status Ended for HL408535+5.p
157116.70/20921.93	% SZS status Started for HL408546+4.p
157116.70/20921.93	% SZS status GaveUp for HL408546+4.p
157116.70/20921.93	eprover: CPU time limit exceeded, terminating
157116.70/20921.93	% SZS status Ended for HL408546+4.p
157131.31/20923.71	% SZS status Started for HL408537+5.p
157131.31/20923.71	% SZS status GaveUp for HL408537+5.p
157131.31/20923.71	eprover: CPU time limit exceeded, terminating
157131.31/20923.71	% SZS status Ended for HL408537+5.p
157140.92/20924.95	% SZS status Started for HL408547+4.p
157140.92/20924.95	% SZS status GaveUp for HL408547+4.p
157140.92/20924.95	eprover: CPU time limit exceeded, terminating
157140.92/20924.95	% SZS status Ended for HL408547+4.p
157161.19/20927.53	% SZS status Started for HL408538+5.p
157161.19/20927.53	% SZS status GaveUp for HL408538+5.p
157161.19/20927.53	eprover: CPU time limit exceeded, terminating
157161.19/20927.53	% SZS status Ended for HL408538+5.p
157165.12/20927.98	% SZS status Started for HL408548+4.p
157165.12/20927.98	% SZS status GaveUp for HL408548+4.p
157165.12/20927.98	eprover: CPU time limit exceeded, terminating
157165.12/20927.98	% SZS status Ended for HL408548+4.p
157189.56/20931.02	% SZS status Started for HL408549+4.p
157189.56/20931.02	% SZS status GaveUp for HL408549+4.p
157189.56/20931.02	eprover: CPU time limit exceeded, terminating
157189.56/20931.02	% SZS status Ended for HL408549+4.p
157224.48/20935.42	% SZS status Started for HL408541+5.p
157224.48/20935.42	% SZS status GaveUp for HL408541+5.p
157224.48/20935.42	eprover: CPU time limit exceeded, terminating
157224.48/20935.42	% SZS status Ended for HL408541+5.p
157248.97/20938.49	% SZS status Started for HL408550+4.p
157248.97/20938.49	% SZS status GaveUp for HL408550+4.p
157248.97/20938.49	eprover: CPU time limit exceeded, terminating
157248.97/20938.49	% SZS status Ended for HL408550+4.p
157262.84/20940.26	% SZS status Started for HL408542+5.p
157262.84/20940.26	% SZS status GaveUp for HL408542+5.p
157262.84/20940.26	eprover: CPU time limit exceeded, terminating
157262.84/20940.26	% SZS status Ended for HL408542+5.p
157272.11/20941.46	% SZS status Started for HL408544+5.p
157272.11/20941.46	% SZS status GaveUp for HL408544+5.p
157272.11/20941.46	eprover: CPU time limit exceeded, terminating
157272.11/20941.46	% SZS status Ended for HL408544+5.p
157287.27/20943.31	% SZS status Started for HL408551+4.p
157287.27/20943.31	% SZS status GaveUp for HL408551+4.p
157287.27/20943.31	eprover: CPU time limit exceeded, terminating
157287.27/20943.31	% SZS status Ended for HL408551+4.p
157287.61/20943.43	% SZS status Started for HL408545+5.p
157287.61/20943.43	% SZS status GaveUp for HL408545+5.p
157287.61/20943.43	eprover: CPU time limit exceeded, terminating
157287.61/20943.43	% SZS status Ended for HL408545+5.p
157304.86/20945.26	% SZS status Started for HL408546+5.p
157304.86/20945.26	% SZS status GaveUp for HL408546+5.p
157304.86/20945.26	eprover: CPU time limit exceeded, terminating
157304.86/20945.26	% SZS status Ended for HL408546+5.p
157313.53/20946.34	% SZS status Started for HL408552+4.p
157313.53/20946.34	% SZS status GaveUp for HL408552+4.p
157313.53/20946.34	eprover: CPU time limit exceeded, terminating
157313.53/20946.34	% SZS status Ended for HL408552+4.p
157329.03/20948.30	% SZS status Started for HL408553+4.p
157329.03/20948.30	% SZS status GaveUp for HL408553+4.p
157329.03/20948.30	eprover: CPU time limit exceeded, terminating
157329.03/20948.30	% SZS status Ended for HL408553+4.p
157340.56/20949.78	% SZS status Started for HL408547+5.p
157340.56/20949.78	% SZS status GaveUp for HL408547+5.p
157340.56/20949.78	eprover: CPU time limit exceeded, terminating
157340.56/20949.78	% SZS status Ended for HL408547+5.p
157353.20/20951.33	% SZS status Started for HL408554+4.p
157353.20/20951.33	% SZS status GaveUp for HL408554+4.p
157353.20/20951.33	eprover: CPU time limit exceeded, terminating
157353.20/20951.33	% SZS status Ended for HL408554+4.p
157373.05/20953.81	% SZS status Started for HL408548+5.p
157373.05/20953.81	% SZS status GaveUp for HL408548+5.p
157373.05/20953.81	eprover: CPU time limit exceeded, terminating
157373.05/20953.81	% SZS status Ended for HL408548+5.p
157377.00/20954.36	% SZS status Started for HL408555+4.p
157377.00/20954.36	% SZS status GaveUp for HL408555+4.p
157377.00/20954.36	eprover: CPU time limit exceeded, terminating
157377.00/20954.36	% SZS status Ended for HL408555+4.p
157398.59/20957.07	% SZS status Started for HL408553+5.p
157398.59/20957.07	% SZS status GaveUp for HL408553+5.p
157398.59/20957.07	eprover: CPU time limit exceeded, terminating
157398.59/20957.07	% SZS status Ended for HL408553+5.p
157399.38/20957.14	% SZS status Started for HL408549+5.p
157399.38/20957.14	% SZS status GaveUp for HL408549+5.p
157399.38/20957.14	eprover: CPU time limit exceeded, terminating
157399.38/20957.14	% SZS status Ended for HL408549+5.p
157401.86/20957.42	% SZS status Started for HL408557+4.p
157401.86/20957.42	% SZS status GaveUp for HL408557+4.p
157401.86/20957.42	eprover: CPU time limit exceeded, terminating
157401.86/20957.42	% SZS status Ended for HL408557+4.p
157424.08/20960.30	% SZS status Started for HL408558+4.p
157424.08/20960.30	% SZS status GaveUp for HL408558+4.p
157424.08/20960.30	eprover: CPU time limit exceeded, terminating
157424.08/20960.30	% SZS status Ended for HL408558+4.p
157449.59/20963.45	% SZS status Started for HL408559+4.p
157449.59/20963.45	% SZS status GaveUp for HL408559+4.p
157449.59/20963.45	eprover: CPU time limit exceeded, terminating
157449.59/20963.45	% SZS status Ended for HL408559+4.p
157458.88/20964.63	% SZS status Started for HL408550+5.p
157458.88/20964.63	% SZS status GaveUp for HL408550+5.p
157458.88/20964.63	eprover: CPU time limit exceeded, terminating
157458.88/20964.63	% SZS status Ended for HL408550+5.p
157482.62/20967.67	% SZS status Started for HL408560+4.p
157482.62/20967.67	% SZS status GaveUp for HL408560+4.p
157482.62/20967.67	eprover: CPU time limit exceeded, terminating
157482.62/20967.67	% SZS status Ended for HL408560+4.p
157483.55/20967.75	% SZS status Started for HL408551+5.p
157483.55/20967.75	% SZS status GaveUp for HL408551+5.p
157483.55/20967.75	eprover: CPU time limit exceeded, terminating
157483.55/20967.75	% SZS status Ended for HL408551+5.p
157499.09/20969.66	% SZS status Started for HL408552+5.p
157499.09/20969.66	% SZS status GaveUp for HL408552+5.p
157499.09/20969.66	eprover: CPU time limit exceeded, terminating
157499.09/20969.66	% SZS status Ended for HL408552+5.p
157508.94/20970.92	% SZS status Started for HL408561+4.p
157508.94/20970.92	% SZS status GaveUp for HL408561+4.p
157508.94/20970.92	eprover: CPU time limit exceeded, terminating
157508.94/20970.92	% SZS status Ended for HL408561+4.p
157533.42/20973.98	% SZS status Started for HL408562+4.p
157533.42/20973.98	% SZS status GaveUp for HL408562+4.p
157533.42/20973.98	eprover: CPU time limit exceeded, terminating
157533.42/20973.98	% SZS status Ended for HL408562+4.p
157548.28/20975.94	% SZS status Started for HL408554+5.p
157548.28/20975.94	% SZS status GaveUp for HL408554+5.p
157548.28/20975.94	eprover: CPU time limit exceeded, terminating
157548.28/20975.94	% SZS status Ended for HL408554+5.p
157572.36/20978.98	% SZS status Started for HL408563+4.p
157572.36/20978.98	% SZS status GaveUp for HL408563+4.p
157572.36/20978.98	eprover: CPU time limit exceeded, terminating
157572.36/20978.98	% SZS status Ended for HL408563+4.p
157580.41/20979.94	% SZS status Started for HL408555+5.p
157580.41/20979.94	% SZS status GaveUp for HL408555+5.p
157580.41/20979.94	eprover: CPU time limit exceeded, terminating
157580.41/20979.94	% SZS status Ended for HL408555+5.p
157604.23/20982.97	% SZS status Started for HL408564+4.p
157604.23/20982.97	% SZS status GaveUp for HL408564+4.p
157604.23/20982.97	eprover: CPU time limit exceeded, terminating
157604.23/20982.97	% SZS status Ended for HL408564+4.p
157605.73/20983.12	% SZS status Started for HL408557+5.p
157605.73/20983.12	% SZS status GaveUp for HL408557+5.p
157605.73/20983.12	eprover: CPU time limit exceeded, terminating
157605.73/20983.12	% SZS status Ended for HL408557+5.p
157610.56/20983.75	% SZS status Started for HL408558+5.p
157610.56/20983.75	% SZS status GaveUp for HL408558+5.p
157610.56/20983.75	eprover: CPU time limit exceeded, terminating
157610.56/20983.75	% SZS status Ended for HL408558+5.p
157614.80/20984.28	% SZS status Started for HL408562+5.p
157614.80/20984.28	% SZS status GaveUp for HL408562+5.p
157614.80/20984.28	eprover: CPU time limit exceeded, terminating
157614.80/20984.28	% SZS status Ended for HL408562+5.p
157629.77/20986.19	% SZS status Started for HL408565+4.p
157629.77/20986.19	% SZS status GaveUp for HL408565+4.p
157629.77/20986.19	eprover: CPU time limit exceeded, terminating
157629.77/20986.19	% SZS status Ended for HL408565+4.p
157638.27/20987.33	% SZS status Started for HL408566+4.p
157638.27/20987.33	% SZS status GaveUp for HL408566+4.p
157638.27/20987.33	eprover: CPU time limit exceeded, terminating
157638.27/20987.33	% SZS status Ended for HL408566+4.p
157657.58/20989.64	% SZS status Started for HL408559+5.p
157657.58/20989.64	% SZS status GaveUp for HL408559+5.p
157657.58/20989.64	eprover: CPU time limit exceeded, terminating
157657.58/20989.64	% SZS status Ended for HL408559+5.p
157663.55/20990.40	% SZS status Started for HL408567+4.p
157663.55/20990.40	% SZS status GaveUp for HL408567+4.p
157663.55/20990.40	eprover: CPU time limit exceeded, terminating
157663.55/20990.40	% SZS status Ended for HL408567+4.p
157686.98/20993.43	% SZS status Started for HL408569+4.p
157686.98/20993.43	% SZS status GaveUp for HL408569+4.p
157686.98/20993.43	eprover: CPU time limit exceeded, terminating
157686.98/20993.43	% SZS status Ended for HL408569+4.p
157690.58/20993.81	% SZS status Started for HL408560+5.p
157690.58/20993.81	% SZS status GaveUp for HL408560+5.p
157690.58/20993.81	eprover: CPU time limit exceeded, terminating
157690.58/20993.81	% SZS status Ended for HL408560+5.p
157707.14/20995.95	% SZS status Started for HL408561+5.p
157707.14/20995.95	% SZS status GaveUp for HL408561+5.p
157707.14/20995.95	eprover: CPU time limit exceeded, terminating
157707.14/20995.95	% SZS status Ended for HL408561+5.p
157714.06/20996.85	% SZS status Started for HL408570+4.p
157714.06/20996.85	% SZS status GaveUp for HL408570+4.p
157714.06/20996.85	eprover: CPU time limit exceeded, terminating
157714.06/20996.85	% SZS status Ended for HL408570+4.p
157740.06/20999.89	% SZS status Started for HL408571+4.p
157740.06/20999.89	% SZS status GaveUp for HL408571+4.p
157740.06/20999.89	eprover: CPU time limit exceeded, terminating
157740.06/20999.89	% SZS status Ended for HL408571+4.p
157783.59/21005.29	% SZS status Started for HL408563+5.p
157783.59/21005.29	% SZS status GaveUp for HL408563+5.p
157783.59/21005.29	eprover: CPU time limit exceeded, terminating
157783.59/21005.29	% SZS status Ended for HL408563+5.p
157807.28/21008.32	% SZS status Started for HL408572+4.p
157807.28/21008.32	% SZS status GaveUp for HL408572+4.p
157807.28/21008.32	eprover: CPU time limit exceeded, terminating
157807.28/21008.32	% SZS status Ended for HL408572+4.p
157812.88/21009.01	% SZS status Started for HL408564+5.p
157812.88/21009.01	% SZS status GaveUp for HL408564+5.p
157812.88/21009.01	eprover: CPU time limit exceeded, terminating
157812.88/21009.01	% SZS status Ended for HL408564+5.p
157821.12/21010.05	% SZS status Started for HL408565+5.p
157821.12/21010.05	% SZS status GaveUp for HL408565+5.p
157821.12/21010.05	eprover: CPU time limit exceeded, terminating
157821.12/21010.05	% SZS status Ended for HL408565+5.p
157840.25/21012.11	% SZS status Started for HL408574+4.p
157840.25/21012.11	% SZS status GaveUp for HL408574+4.p
157840.25/21012.11	eprover: CPU time limit exceeded, terminating
157840.25/21012.11	% SZS status Ended for HL408574+4.p
157843.75/21012.55	% SZS status Started for HL408566+5.p
157843.75/21012.55	% SZS status GaveUp for HL408566+5.p
157843.75/21012.55	eprover: CPU time limit exceeded, terminating
157843.75/21012.55	% SZS status Ended for HL408566+5.p
157864.59/21015.15	% SZS status Started for HL408575+4.p
157864.59/21015.15	% SZS status GaveUp for HL408575+4.p
157864.59/21015.15	eprover: CPU time limit exceeded, terminating
157864.59/21015.15	% SZS status Ended for HL408575+4.p
157869.23/21015.79	% SZS status Started for HL408567+5.p
157869.23/21015.79	% SZS status GaveUp for HL408567+5.p
157869.23/21015.79	eprover: CPU time limit exceeded, terminating
157869.23/21015.79	% SZS status Ended for HL408567+5.p
157888.22/21018.22	% SZS status Started for HL408576+4.p
157888.22/21018.22	% SZS status GaveUp for HL408576+4.p
157888.22/21018.22	eprover: CPU time limit exceeded, terminating
157888.22/21018.22	% SZS status Ended for HL408576+4.p
157898.62/21019.49	% SZS status Started for HL408569+5.p
157898.62/21019.49	% SZS status GaveUp for HL408569+5.p
157898.62/21019.49	eprover: CPU time limit exceeded, terminating
157898.62/21019.49	% SZS status Ended for HL408569+5.p
157913.97/21021.39	% SZS status Started for HL408577+4.p
157913.97/21021.39	% SZS status GaveUp for HL408577+4.p
157913.97/21021.39	eprover: CPU time limit exceeded, terminating
157913.97/21021.39	% SZS status Ended for HL408577+4.p
157920.06/21022.14	% SZS status Started for HL408570+5.p
157920.06/21022.14	% SZS status GaveUp for HL408570+5.p
157920.06/21022.14	eprover: CPU time limit exceeded, terminating
157920.06/21022.14	% SZS status Ended for HL408570+5.p
157926.31/21022.94	% SZS status Started for HL408575+5.p
157926.31/21022.94	% SZS status GaveUp for HL408575+5.p
157926.31/21022.94	eprover: CPU time limit exceeded, terminating
157926.31/21022.94	% SZS status Ended for HL408575+5.p
157938.16/21024.50	% SZS status Started for HL408578+4.p
157938.16/21024.50	% SZS status GaveUp for HL408578+4.p
157938.16/21024.50	eprover: CPU time limit exceeded, terminating
157938.16/21024.50	% SZS status Ended for HL408578+4.p
157950.73/21026.06	% SZS status Started for HL408579+4.p
157950.73/21026.06	% SZS status GaveUp for HL408579+4.p
157950.73/21026.06	eprover: CPU time limit exceeded, terminating
157950.73/21026.06	% SZS status Ended for HL408579+4.p
157951.80/21026.15	% SZS status Started for HL408571+5.p
157951.80/21026.15	% SZS status GaveUp for HL408571+5.p
157951.80/21026.15	eprover: CPU time limit exceeded, terminating
157951.80/21026.15	% SZS status Ended for HL408571+5.p
157974.83/21029.10	% SZS status Started for HL408580+4.p
157974.83/21029.10	% SZS status GaveUp for HL408580+4.p
157974.83/21029.10	eprover: CPU time limit exceeded, terminating
157974.83/21029.10	% SZS status Ended for HL408580+4.p
157999.28/21032.13	% SZS status Started for HL408581+4.p
157999.28/21032.13	% SZS status GaveUp for HL408581+4.p
157999.28/21032.13	eprover: CPU time limit exceeded, terminating
157999.28/21032.13	% SZS status Ended for HL408581+4.p
158017.80/21034.48	% SZS status Started for HL408572+5.p
158017.80/21034.48	% SZS status GaveUp for HL408572+5.p
158017.80/21034.48	eprover: CPU time limit exceeded, terminating
158017.80/21034.48	% SZS status Ended for HL408572+5.p
158019.50/21034.73	% SZS status Started for HL408579+5.p
158019.50/21034.73	% SZS status GaveUp for HL408579+5.p
158019.50/21034.73	eprover: CPU time limit exceeded, terminating
158019.50/21034.73	% SZS status Ended for HL408579+5.p
158034.67/21036.61	% SZS status Started for HL408574+5.p
158034.67/21036.61	% SZS status GaveUp for HL408574+5.p
158034.67/21036.61	eprover: CPU time limit exceeded, terminating
158034.67/21036.61	% SZS status Ended for HL408574+5.p
158039.41/21037.24	% SZS status Started for HL408580+5.p
158039.41/21037.24	% SZS status GaveUp for HL408580+5.p
158039.41/21037.24	eprover: CPU time limit exceeded, terminating
158039.41/21037.24	% SZS status Ended for HL408580+5.p
158041.27/21037.55	% SZS status Started for HL408582+4.p
158041.27/21037.55	% SZS status GaveUp for HL408582+4.p
158041.27/21037.55	eprover: CPU time limit exceeded, terminating
158041.27/21037.55	% SZS status Ended for HL408582+4.p
158057.86/21039.65	% SZS status Started for HL408584+4.p
158057.86/21039.65	% SZS status GaveUp for HL408584+4.p
158057.86/21039.65	eprover: CPU time limit exceeded, terminating
158057.86/21039.65	% SZS status Ended for HL408584+4.p
158066.23/21040.58	% SZS status Started for HL408585+4.p
158066.23/21040.58	% SZS status GaveUp for HL408585+4.p
158066.23/21040.58	eprover: CPU time limit exceeded, terminating
158066.23/21040.58	% SZS status Ended for HL408585+4.p
158077.95/21042.06	% SZS status Started for HL408576+5.p
158077.95/21042.06	% SZS status GaveUp for HL408576+5.p
158077.95/21042.06	eprover: CPU time limit exceeded, terminating
158077.95/21042.06	% SZS status Ended for HL408576+5.p
158090.72/21043.63	% SZS status Started for HL408586+4.p
158090.72/21043.63	% SZS status GaveUp for HL408586+4.p
158090.72/21043.63	eprover: CPU time limit exceeded, terminating
158090.72/21043.63	% SZS status Ended for HL408586+4.p
158105.75/21045.54	% SZS status Started for HL408577+5.p
158105.75/21045.54	% SZS status GaveUp for HL408577+5.p
158105.75/21045.54	eprover: CPU time limit exceeded, terminating
158105.75/21045.54	% SZS status Ended for HL408577+5.p
158114.64/21046.66	% SZS status Started for HL408587+4.p
158114.64/21046.66	% SZS status GaveUp for HL408587+4.p
158114.64/21046.66	eprover: CPU time limit exceeded, terminating
158114.64/21046.66	% SZS status Ended for HL408587+4.p
158127.56/21048.30	% SZS status Started for HL408578+5.p
158127.56/21048.30	% SZS status GaveUp for HL408578+5.p
158127.56/21048.30	eprover: CPU time limit exceeded, terminating
158127.56/21048.30	% SZS status Ended for HL408578+5.p
158138.91/21049.71	% SZS status Started for HL408588+4.p
158138.91/21049.71	% SZS status GaveUp for HL408588+4.p
158138.91/21049.71	eprover: CPU time limit exceeded, terminating
158138.91/21049.71	% SZS status Ended for HL408588+4.p
158165.69/21052.75	% SZS status Started for HL408589+4.p
158165.69/21052.75	% SZS status GaveUp for HL408589+4.p
158165.69/21052.75	eprover: CPU time limit exceeded, terminating
158165.69/21052.75	% SZS status Ended for HL408589+4.p
158189.78/21055.81	% SZS status Started for HL408587+5.p
158189.78/21055.81	% SZS status GaveUp for HL408587+5.p
158189.78/21055.81	eprover: CPU time limit exceeded, terminating
158189.78/21055.81	% SZS status Ended for HL408587+5.p
158209.70/21058.29	% SZS status Started for HL408581+5.p
158209.70/21058.29	% SZS status GaveUp for HL408581+5.p
158209.70/21058.29	eprover: CPU time limit exceeded, terminating
158209.70/21058.29	% SZS status Ended for HL408581+5.p
158214.27/21058.83	% SZS status Started for HL408590+4.p
158214.27/21058.83	% SZS status GaveUp for HL408590+4.p
158214.27/21058.83	eprover: CPU time limit exceeded, terminating
158214.27/21058.83	% SZS status Ended for HL408590+4.p
158228.69/21060.80	% SZS status Started for HL408582+5.p
158228.69/21060.80	% SZS status GaveUp for HL408582+5.p
158228.69/21060.80	eprover: CPU time limit exceeded, terminating
158228.69/21060.80	% SZS status Ended for HL408582+5.p
158238.84/21061.94	% SZS status Started for HL408591+4.p
158238.84/21061.94	% SZS status GaveUp for HL408591+4.p
158238.84/21061.94	eprover: CPU time limit exceeded, terminating
158238.84/21061.94	% SZS status Ended for HL408591+4.p
158250.59/21063.44	% SZS status Started for HL408584+5.p
158250.59/21063.44	% SZS status GaveUp for HL408584+5.p
158250.59/21063.44	eprover: CPU time limit exceeded, terminating
158250.59/21063.44	% SZS status Ended for HL408584+5.p
158263.11/21064.97	% SZS status Started for HL408592+4.p
158263.11/21064.97	% SZS status GaveUp for HL408592+4.p
158263.11/21064.97	eprover: CPU time limit exceeded, terminating
158263.11/21064.97	% SZS status Ended for HL408592+4.p
158272.00/21066.10	% SZS status Started for HL408585+5.p
158272.00/21066.10	% SZS status GaveUp for HL408585+5.p
158272.00/21066.10	eprover: CPU time limit exceeded, terminating
158272.00/21066.10	% SZS status Ended for HL408585+5.p
158286.56/21068.02	% SZS status Started for HL408593+4.p
158286.56/21068.02	% SZS status GaveUp for HL408593+4.p
158286.56/21068.02	eprover: CPU time limit exceeded, terminating
158286.56/21068.02	% SZS status Ended for HL408593+4.p
158289.84/21068.37	% SZS status Started for HL408586+5.p
158289.84/21068.37	% SZS status GaveUp for HL408586+5.p
158289.84/21068.37	eprover: CPU time limit exceeded, terminating
158289.84/21068.37	% SZS status Ended for HL408586+5.p
158290.27/21068.47	% SZS status Started for HL408590+5.p
158290.27/21068.47	% SZS status GaveUp for HL408590+5.p
158290.27/21068.47	eprover: CPU time limit exceeded, terminating
158290.27/21068.47	% SZS status Ended for HL408590+5.p
158311.80/21071.09	% SZS status Started for HL408596+4.p
158311.80/21071.09	% SZS status GaveUp for HL408596+4.p
158311.80/21071.09	eprover: CPU time limit exceeded, terminating
158311.80/21071.09	% SZS status Ended for HL408596+4.p
158315.39/21071.54	% SZS status Started for HL408597+4.p
158315.39/21071.54	% SZS status GaveUp for HL408597+4.p
158315.39/21071.54	eprover: CPU time limit exceeded, terminating
158315.39/21071.54	% SZS status Ended for HL408597+4.p
158337.56/21074.38	% SZS status Started for HL408588+5.p
158337.56/21074.38	% SZS status GaveUp for HL408588+5.p
158337.56/21074.38	eprover: CPU time limit exceeded, terminating
158337.56/21074.38	% SZS status Ended for HL408588+5.p
158339.38/21074.58	% SZS status Started for HL408598+4.p
158339.38/21074.58	% SZS status GaveUp for HL408598+4.p
158339.38/21074.58	eprover: CPU time limit exceeded, terminating
158339.38/21074.58	% SZS status Ended for HL408598+4.p
158363.14/21077.62	% SZS status Started for HL408599+4.p
158363.14/21077.62	% SZS status GaveUp for HL408599+4.p
158363.14/21077.62	eprover: CPU time limit exceeded, terminating
158363.14/21077.62	% SZS status Ended for HL408599+4.p
158376.12/21079.22	% SZS status Started for HL408589+5.p
158376.12/21079.22	% SZS status GaveUp for HL408589+5.p
158376.12/21079.22	eprover: CPU time limit exceeded, terminating
158376.12/21079.22	% SZS status Ended for HL408589+5.p
158399.84/21082.24	% SZS status Started for HL408600+4.p
158399.84/21082.24	% SZS status GaveUp for HL408600+4.p
158399.84/21082.24	eprover: CPU time limit exceeded, terminating
158399.84/21082.24	% SZS status Ended for HL408600+4.p
158438.17/21087.06	% SZS status Started for HL408591+5.p
158438.17/21087.06	% SZS status GaveUp for HL408591+5.p
158438.17/21087.06	eprover: CPU time limit exceeded, terminating
158438.17/21087.06	% SZS status Ended for HL408591+5.p
158459.00/21089.65	% SZS status Started for HL408592+5.p
158459.00/21089.65	% SZS status GaveUp for HL408592+5.p
158459.00/21089.65	eprover: CPU time limit exceeded, terminating
158459.00/21089.65	% SZS status Ended for HL408592+5.p
158462.23/21090.09	% SZS status Started for HL408601+4.p
158462.23/21090.09	% SZS status GaveUp for HL408601+4.p
158462.23/21090.09	eprover: CPU time limit exceeded, terminating
158462.23/21090.09	% SZS status Ended for HL408601+4.p
158482.86/21092.67	% SZS status Started for HL408593+5.p
158482.86/21092.67	% SZS status GaveUp for HL408593+5.p
158482.86/21092.67	eprover: CPU time limit exceeded, terminating
158482.86/21092.67	% SZS status Ended for HL408593+5.p
158486.39/21093.12	% SZS status Started for HL408602+4.p
158486.39/21093.12	% SZS status GaveUp for HL408602+4.p
158486.39/21093.12	eprover: CPU time limit exceeded, terminating
158486.39/21093.12	% SZS status Ended for HL408602+4.p
158497.58/21094.51	% SZS status Started for HL408596+5.p
158497.58/21094.51	% SZS status GaveUp for HL408596+5.p
158497.58/21094.51	eprover: CPU time limit exceeded, terminating
158497.58/21094.51	% SZS status Ended for HL408596+5.p
158510.78/21096.15	% SZS status Started for HL408603+4.p
158510.78/21096.15	% SZS status GaveUp for HL408603+4.p
158510.78/21096.15	eprover: CPU time limit exceeded, terminating
158510.78/21096.15	% SZS status Ended for HL408603+4.p
158522.31/21097.61	% SZS status Started for HL408597+5.p
158522.31/21097.61	% SZS status GaveUp for HL408597+5.p
158522.31/21097.61	eprover: CPU time limit exceeded, terminating
158522.31/21097.61	% SZS status Ended for HL408597+5.p
158534.38/21099.19	% SZS status Started for HL408604+4.p
158534.38/21099.19	% SZS status GaveUp for HL408604+4.p
158534.38/21099.19	eprover: CPU time limit exceeded, terminating
158534.38/21099.19	% SZS status Ended for HL408604+4.p
158542.19/21099.82	% SZS status Started for HL408599+5.p
158542.19/21099.82	% SZS status GaveUp for HL408599+5.p
158542.19/21099.82	eprover: CPU time limit exceeded, terminating
158542.19/21099.82	% SZS status Ended for HL408599+5.p
158548.53/21100.59	% SZS status Started for HL408598+5.p
158548.53/21100.59	% SZS status GaveUp for HL408598+5.p
158548.53/21100.59	eprover: CPU time limit exceeded, terminating
158548.53/21100.59	% SZS status Ended for HL408598+5.p
158561.61/21102.24	% SZS status Started for HL408605+4.p
158561.61/21102.24	% SZS status GaveUp for HL408605+4.p
158561.61/21102.24	eprover: CPU time limit exceeded, terminating
158561.61/21102.24	% SZS status Ended for HL408605+4.p
158572.06/21103.63	% SZS status Started for HL408606+4.p
158572.06/21103.63	% SZS status GaveUp for HL408606+4.p
158572.06/21103.63	eprover: CPU time limit exceeded, terminating
158572.06/21103.63	% SZS status Ended for HL408606+4.p
158585.12/21105.24	% SZS status Started for HL408603+5.p
158585.12/21105.24	% SZS status GaveUp for HL408603+5.p
158585.12/21105.24	eprover: CPU time limit exceeded, terminating
158585.12/21105.24	% SZS status Ended for HL408603+5.p
158596.59/21106.67	% SZS status Started for HL408608+4.p
158596.59/21106.67	% SZS status GaveUp for HL408608+4.p
158596.59/21106.67	eprover: CPU time limit exceeded, terminating
158596.59/21106.67	% SZS status Ended for HL408608+4.p
158606.64/21107.99	% SZS status Started for HL408604+5.p
158606.64/21107.99	% SZS status GaveUp for HL408604+5.p
158606.64/21107.99	eprover: CPU time limit exceeded, terminating
158606.64/21107.99	% SZS status Ended for HL408604+5.p
158611.56/21108.55	% SZS status Started for HL408600+5.p
158611.56/21108.55	% SZS status GaveUp for HL408600+5.p
158611.56/21108.55	eprover: CPU time limit exceeded, terminating
158611.56/21108.55	% SZS status Ended for HL408600+5.p
158621.31/21109.76	% SZS status Started for HL408609+4.p
158621.31/21109.76	% SZS status GaveUp for HL408609+4.p
158621.31/21109.76	eprover: CPU time limit exceeded, terminating
158621.31/21109.76	% SZS status Ended for HL408609+4.p
158635.58/21111.58	% SZS status Started for HL408610+4.p
158635.58/21111.58	% SZS status GaveUp for HL408610+4.p
158635.58/21111.58	eprover: CPU time limit exceeded, terminating
158635.58/21111.58	% SZS status Ended for HL408610+4.p
158659.83/21114.62	% SZS status Started for HL408611+4.p
158659.83/21114.62	% SZS status GaveUp for HL408611+4.p
158659.83/21114.62	eprover: CPU time limit exceeded, terminating
158659.83/21114.62	% SZS status Ended for HL408611+4.p
158669.42/21115.84	% SZS status Started for HL408601+5.p
158669.42/21115.84	% SZS status GaveUp for HL408601+5.p
158669.42/21115.84	eprover: CPU time limit exceeded, terminating
158669.42/21115.84	% SZS status Ended for HL408601+5.p
158693.61/21118.95	% SZS status Started for HL408613+4.p
158693.61/21118.95	% SZS status GaveUp for HL408613+4.p
158693.61/21118.95	eprover: CPU time limit exceeded, terminating
158693.61/21118.95	% SZS status Ended for HL408613+4.p
158694.31/21118.97	% SZS status Started for HL408602+5.p
158694.31/21118.97	% SZS status GaveUp for HL408602+5.p
158694.31/21118.97	eprover: CPU time limit exceeded, terminating
158694.31/21118.97	% SZS status Ended for HL408602+5.p
158718.64/21122.03	% SZS status Started for HL408614+4.p
158718.64/21122.03	% SZS status GaveUp for HL408614+4.p
158718.64/21122.03	eprover: CPU time limit exceeded, terminating
158718.64/21122.03	% SZS status Ended for HL408614+4.p
158749.98/21126.08	% SZS status Started for HL408605+5.p
158749.98/21126.08	% SZS status GaveUp for HL408605+5.p
158749.98/21126.08	eprover: CPU time limit exceeded, terminating
158749.98/21126.08	% SZS status Ended for HL408605+5.p
158769.20/21128.43	% SZS status Started for HL408606+5.p
158769.20/21128.43	% SZS status GaveUp for HL408606+5.p
158769.20/21128.43	eprover: CPU time limit exceeded, terminating
158769.20/21128.43	% SZS status Ended for HL408606+5.p
158774.92/21129.12	% SZS status Started for HL408615+4.p
158774.92/21129.12	% SZS status GaveUp for HL408615+4.p
158774.92/21129.12	eprover: CPU time limit exceeded, terminating
158774.92/21129.12	% SZS status Ended for HL408615+4.p
158774.92/21129.15	% SZS status Started for HL408613+5.p
158774.92/21129.15	% SZS status GaveUp for HL408613+5.p
158774.92/21129.15	eprover: CPU time limit exceeded, terminating
158774.92/21129.15	% SZS status Ended for HL408613+5.p
158793.98/21131.52	% SZS status Started for HL408608+5.p
158793.98/21131.52	% SZS status GaveUp for HL408608+5.p
158793.98/21131.52	eprover: CPU time limit exceeded, terminating
158793.98/21131.52	% SZS status Ended for HL408608+5.p
158798.73/21132.16	% SZS status Started for HL408616+4.p
158798.73/21132.16	% SZS status GaveUp for HL408616+4.p
158798.73/21132.16	eprover: CPU time limit exceeded, terminating
158798.73/21132.16	% SZS status Ended for HL408616+4.p
158815.28/21134.29	% SZS status Started for HL408609+5.p
158815.28/21134.29	% SZS status GaveUp for HL408609+5.p
158815.28/21134.29	eprover: CPU time limit exceeded, terminating
158815.28/21134.29	% SZS status Ended for HL408609+5.p
158817.89/21134.56	% SZS status Started for HL408617+4.p
158817.89/21134.56	% SZS status GaveUp for HL408617+4.p
158817.89/21134.56	eprover: CPU time limit exceeded, terminating
158817.89/21134.56	% SZS status Ended for HL408617+4.p
158828.17/21135.89	% SZS status Started for HL408610+5.p
158828.17/21135.89	% SZS status GaveUp for HL408610+5.p
158828.17/21135.89	eprover: CPU time limit exceeded, terminating
158828.17/21135.89	% SZS status Ended for HL408610+5.p
158839.81/21137.39	% SZS status Started for HL408618+4.p
158839.81/21137.39	% SZS status GaveUp for HL408618+4.p
158839.81/21137.39	eprover: CPU time limit exceeded, terminating
158839.81/21137.39	% SZS status Ended for HL408618+4.p
158852.64/21138.95	% SZS status Started for HL408619+4.p
158852.64/21138.95	% SZS status GaveUp for HL408619+4.p
158852.64/21138.95	eprover: CPU time limit exceeded, terminating
158852.64/21138.95	% SZS status Ended for HL408619+4.p
158869.28/21140.98	% SZS status Started for HL408611+5.p
158869.28/21140.98	% SZS status GaveUp for HL408611+5.p
158869.28/21140.98	eprover: CPU time limit exceeded, terminating
158869.28/21140.98	% SZS status Ended for HL408611+5.p
158876.73/21141.97	% SZS status Started for HL408620+4.p
158876.73/21141.97	% SZS status GaveUp for HL408620+4.p
158876.73/21141.97	eprover: CPU time limit exceeded, terminating
158876.73/21141.97	% SZS status Ended for HL408620+4.p
158900.58/21144.92	% SZS status Started for HL408618+5.p
158900.58/21144.92	% SZS status GaveUp for HL408618+5.p
158900.58/21144.92	eprover: CPU time limit exceeded, terminating
158900.58/21144.92	% SZS status Ended for HL408618+5.p
158901.30/21145.04	% SZS status Started for HL408621+4.p
158901.30/21145.04	% SZS status GaveUp for HL408621+4.p
158901.30/21145.04	eprover: CPU time limit exceeded, terminating
158901.30/21145.04	% SZS status Ended for HL408621+4.p
158925.86/21148.12	% SZS status Started for HL408622+4.p
158925.86/21148.12	% SZS status GaveUp for HL408622+4.p
158925.86/21148.12	eprover: CPU time limit exceeded, terminating
158925.86/21148.12	% SZS status Ended for HL408622+4.p
158929.16/21148.61	% SZS status Started for HL408614+5.p
158929.16/21148.61	% SZS status GaveUp for HL408614+5.p
158929.16/21148.61	eprover: CPU time limit exceeded, terminating
158929.16/21148.61	% SZS status Ended for HL408614+5.p
158953.78/21151.67	% SZS status Started for HL408623+4.p
158953.78/21151.67	% SZS status GaveUp for HL408623+4.p
158953.78/21151.67	eprover: CPU time limit exceeded, terminating
158953.78/21151.67	% SZS status Ended for HL408623+4.p
158979.14/21154.81	% SZS status Started for HL408615+5.p
158979.14/21154.81	% SZS status GaveUp for HL408615+5.p
158979.14/21154.81	eprover: CPU time limit exceeded, terminating
158979.14/21154.81	% SZS status Ended for HL408615+5.p
158982.08/21155.36	% SZS status Started for HL408616+5.p
158982.08/21155.36	% SZS status GaveUp for HL408616+5.p
158982.08/21155.36	eprover: CPU time limit exceeded, terminating
158982.08/21155.36	% SZS status Ended for HL408616+5.p
159002.69/21157.84	% SZS status Started for HL408625+4.p
159002.69/21157.84	% SZS status GaveUp for HL408625+4.p
159002.69/21157.84	eprover: CPU time limit exceeded, terminating
159002.69/21157.84	% SZS status Ended for HL408625+4.p
159006.33/21158.28	% SZS status Started for HL408617+5.p
159006.33/21158.28	% SZS status GaveUp for HL408617+5.p
159006.33/21158.28	eprover: CPU time limit exceeded, terminating
159006.33/21158.28	% SZS status Ended for HL408617+5.p
159026.55/21160.87	% SZS status Started for HL408626+4.p
159026.55/21160.87	% SZS status GaveUp for HL408626+4.p
159026.55/21160.87	eprover: CPU time limit exceeded, terminating
159026.55/21160.87	% SZS status Ended for HL408626+4.p
159049.45/21163.72	% SZS status Started for HL408619+5.p
159049.45/21163.72	% SZS status GaveUp for HL408619+5.p
159049.45/21163.72	eprover: CPU time limit exceeded, terminating
159049.45/21163.72	% SZS status Ended for HL408619+5.p
159051.39/21163.93	% SZS status Started for HL408627+4.p
159051.39/21163.93	% SZS status GaveUp for HL408627+4.p
159051.39/21163.93	eprover: CPU time limit exceeded, terminating
159051.39/21163.93	% SZS status Ended for HL408627+4.p
159063.47/21165.58	% SZS status Started for HL408625+5.p
159063.47/21165.58	% SZS status GaveUp for HL408625+5.p
159063.47/21165.58	eprover: CPU time limit exceeded, terminating
159063.47/21165.58	% SZS status Ended for HL408625+5.p
159074.83/21166.96	% SZS status Started for HL408628+4.p
159074.83/21166.96	% SZS status GaveUp for HL408628+4.p
159074.83/21166.96	eprover: CPU time limit exceeded, terminating
159074.83/21166.96	% SZS status Ended for HL408628+4.p
159076.77/21167.11	% SZS status Started for HL408620+5.p
159076.77/21167.11	% SZS status GaveUp for HL408620+5.p
159076.77/21167.11	eprover: CPU time limit exceeded, terminating
159076.77/21167.11	% SZS status Ended for HL408620+5.p
159099.88/21169.99	% SZS status Started for HL408630+4.p
159099.88/21169.99	% SZS status GaveUp for HL408630+4.p
159099.88/21169.99	eprover: CPU time limit exceeded, terminating
159099.88/21169.99	% SZS status Ended for HL408630+4.p
159109.66/21171.29	% SZS status Started for HL408621+5.p
159109.66/21171.29	% SZS status GaveUp for HL408621+5.p
159109.66/21171.29	eprover: CPU time limit exceeded, terminating
159109.66/21171.29	% SZS status Ended for HL408621+5.p
159123.36/21173.02	% SZS status Started for HL408631+4.p
159123.36/21173.02	% SZS status GaveUp for HL408631+4.p
159123.36/21173.02	eprover: CPU time limit exceeded, terminating
159123.36/21173.02	% SZS status Ended for HL408631+4.p
159133.55/21174.22	% SZS status Started for HL408622+5.p
159133.55/21174.22	% SZS status GaveUp for HL408622+5.p
159133.55/21174.22	eprover: CPU time limit exceeded, terminating
159133.55/21174.22	% SZS status Ended for HL408622+5.p
159148.48/21176.11	% SZS status Started for HL408633+4.p
159148.48/21176.11	% SZS status GaveUp for HL408633+4.p
159148.48/21176.11	eprover: CPU time limit exceeded, terminating
159148.48/21176.11	% SZS status Ended for HL408633+4.p
159161.92/21177.83	% SZS status Started for HL408623+5.p
159161.92/21177.83	% SZS status GaveUp for HL408623+5.p
159161.92/21177.83	eprover: CPU time limit exceeded, terminating
159161.92/21177.83	% SZS status Ended for HL408623+5.p
159172.23/21179.14	% SZS status Started for HL408635+4.p
159172.23/21179.14	% SZS status GaveUp for HL408635+4.p
159172.23/21179.14	eprover: CPU time limit exceeded, terminating
159172.23/21179.14	% SZS status Ended for HL408635+4.p
159196.05/21182.18	% SZS status Started for HL408636+4.p
159196.05/21182.18	% SZS status GaveUp for HL408636+4.p
159196.05/21182.18	eprover: CPU time limit exceeded, terminating
159196.05/21182.18	% SZS status Ended for HL408636+4.p
159216.91/21184.74	% SZS status Started for HL408626+5.p
159216.91/21184.74	% SZS status GaveUp for HL408626+5.p
159216.91/21184.74	eprover: CPU time limit exceeded, terminating
159216.91/21184.74	% SZS status Ended for HL408626+5.p
159240.55/21187.77	% SZS status Started for HL408637+4.p
159240.55/21187.77	% SZS status GaveUp for HL408637+4.p
159240.55/21187.77	eprover: CPU time limit exceeded, terminating
159240.55/21187.77	% SZS status Ended for HL408637+4.p
159242.62/21188.06	% SZS status Started for HL408635+5.p
159242.62/21188.06	% SZS status GaveUp for HL408635+5.p
159242.62/21188.06	eprover: CPU time limit exceeded, terminating
159242.62/21188.06	% SZS status Ended for HL408635+5.p
159257.38/21189.85	% SZS status Started for HL408627+5.p
159257.38/21189.85	% SZS status GaveUp for HL408627+5.p
159257.38/21189.85	eprover: CPU time limit exceeded, terminating
159257.38/21189.85	% SZS status Ended for HL408627+5.p
159266.72/21191.09	% SZS status Started for HL408638+4.p
159266.72/21191.09	% SZS status GaveUp for HL408638+4.p
159266.72/21191.09	eprover: CPU time limit exceeded, terminating
159266.72/21191.09	% SZS status Ended for HL408638+4.p
159273.83/21191.95	% SZS status Started for HL408628+5.p
159273.83/21191.95	% SZS status GaveUp for HL408628+5.p
159273.83/21191.95	eprover: CPU time limit exceeded, terminating
159273.83/21191.95	% SZS status Ended for HL408628+5.p
159278.81/21192.57	% SZS status Started for HL408636+5.p
159278.81/21192.57	% SZS status GaveUp for HL408636+5.p
159278.81/21192.57	eprover: CPU time limit exceeded, terminating
159278.81/21192.57	% SZS status Ended for HL408636+5.p
159284.91/21193.31	% SZS status Started for HL408630+5.p
159284.91/21193.31	% SZS status GaveUp for HL408630+5.p
159284.91/21193.31	eprover: CPU time limit exceeded, terminating
159284.91/21193.31	% SZS status Ended for HL408630+5.p
159291.34/21194.11	% SZS status Started for HL408639+4.p
159291.34/21194.11	% SZS status GaveUp for HL408639+4.p
159291.34/21194.11	eprover: CPU time limit exceeded, terminating
159291.34/21194.11	% SZS status Ended for HL408639+4.p
159302.56/21195.59	% SZS status Started for HL408640+4.p
159302.56/21195.59	% SZS status GaveUp for HL408640+4.p
159302.56/21195.59	eprover: CPU time limit exceeded, terminating
159302.56/21195.59	% SZS status Ended for HL408640+4.p
159315.25/21197.18	% SZS status Started for HL408641+4.p
159315.25/21197.18	% SZS status GaveUp for HL408641+4.p
159315.25/21197.18	eprover: CPU time limit exceeded, terminating
159315.25/21197.18	% SZS status Ended for HL408641+4.p
159317.00/21197.44	% SZS status Started for HL408631+5.p
159317.00/21197.44	% SZS status GaveUp for HL408631+5.p
159317.00/21197.44	eprover: CPU time limit exceeded, terminating
159317.00/21197.44	% SZS status Ended for HL408631+5.p
159339.70/21200.21	% SZS status Started for HL408642+4.p
159339.70/21200.21	% SZS status GaveUp for HL408642+4.p
159339.70/21200.21	eprover: CPU time limit exceeded, terminating
159339.70/21200.21	% SZS status Ended for HL408642+4.p
159340.42/21200.34	% SZS status Started for HL408638+5.p
159340.42/21200.34	% SZS status GaveUp for HL408638+5.p
159340.42/21200.34	eprover: CPU time limit exceeded, terminating
159340.42/21200.34	% SZS status Ended for HL408638+5.p
159342.34/21200.55	% SZS status Started for HL408633+5.p
159342.34/21200.55	% SZS status GaveUp for HL408633+5.p
159342.34/21200.55	eprover: CPU time limit exceeded, terminating
159342.34/21200.55	% SZS status Ended for HL408633+5.p
159354.98/21202.19	% SZS status Started for HL408639+5.p
159354.98/21202.19	% SZS status GaveUp for HL408639+5.p
159354.98/21202.19	eprover: CPU time limit exceeded, terminating
159354.98/21202.19	% SZS status Ended for HL408639+5.p
159363.47/21203.25	% SZS status Started for HL408643+4.p
159363.47/21203.25	% SZS status GaveUp for HL408643+4.p
159363.47/21203.25	eprover: CPU time limit exceeded, terminating
159363.47/21203.25	% SZS status Ended for HL408643+4.p
159365.92/21203.56	% SZS status Started for HL408640+5.p
159365.92/21203.56	% SZS status GaveUp for HL408640+5.p
159365.92/21203.56	eprover: CPU time limit exceeded, terminating
159365.92/21203.56	% SZS status Ended for HL408640+5.p
159366.61/21203.60	% SZS status Started for HL408645+4.p
159366.61/21203.60	% SZS status GaveUp for HL408645+4.p
159366.61/21203.60	eprover: CPU time limit exceeded, terminating
159366.61/21203.60	% SZS status Ended for HL408645+4.p
159387.64/21206.28	% SZS status Started for HL408646+4.p
159387.64/21206.28	% SZS status GaveUp for HL408646+4.p
159387.64/21206.28	eprover: CPU time limit exceeded, terminating
159387.64/21206.28	% SZS status Ended for HL408646+4.p
159390.75/21206.62	% SZS status Started for HL408648+4.p
159390.75/21206.62	% SZS status GaveUp for HL408648+4.p
159390.75/21206.62	eprover: CPU time limit exceeded, terminating
159390.75/21206.62	% SZS status Ended for HL408648+4.p
159414.66/21209.65	% SZS status Started for HL408649+4.p
159414.66/21209.65	% SZS status GaveUp for HL408649+4.p
159414.66/21209.65	eprover: CPU time limit exceeded, terminating
159414.66/21209.65	% SZS status Ended for HL408649+4.p
159449.91/21214.11	% SZS status Started for HL408637+5.p
159449.91/21214.11	% SZS status GaveUp for HL408637+5.p
159449.91/21214.11	eprover: CPU time limit exceeded, terminating
159449.91/21214.11	% SZS status Ended for HL408637+5.p
159474.33/21217.14	% SZS status Started for HL408650+4.p
159474.33/21217.14	% SZS status GaveUp for HL408650+4.p
159474.33/21217.14	eprover: CPU time limit exceeded, terminating
159474.33/21217.14	% SZS status Ended for HL408650+4.p
159497.41/21220.05	% SZS status Started for HL408649+5.p
159497.41/21220.05	% SZS status GaveUp for HL408649+5.p
159497.41/21220.05	eprover: CPU time limit exceeded, terminating
159497.41/21220.05	% SZS status Ended for HL408649+5.p
159510.72/21221.75	% SZS status Started for HL408641+5.p
159510.72/21221.75	% SZS status GaveUp for HL408641+5.p
159510.72/21221.75	eprover: CPU time limit exceeded, terminating
159510.72/21221.75	% SZS status Ended for HL408641+5.p
159521.55/21223.09	% SZS status Started for HL408652+4.p
159521.55/21223.09	% SZS status GaveUp for HL408652+4.p
159521.55/21223.09	eprover: CPU time limit exceeded, terminating
159521.55/21223.09	% SZS status Ended for HL408652+4.p
159527.41/21223.87	% SZS status Started for HL408642+5.p
159527.41/21223.87	% SZS status GaveUp for HL408642+5.p
159527.41/21223.87	eprover: CPU time limit exceeded, terminating
159527.41/21223.87	% SZS status Ended for HL408642+5.p
159545.27/21226.12	% SZS status Started for HL408653+4.p
159545.27/21226.12	% SZS status GaveUp for HL408653+4.p
159545.27/21226.12	eprover: CPU time limit exceeded, terminating
159545.27/21226.12	% SZS status Ended for HL408653+4.p
159548.27/21226.58	% SZS status Started for HL408643+5.p
159548.27/21226.58	% SZS status GaveUp for HL408643+5.p
159548.27/21226.58	eprover: CPU time limit exceeded, terminating
159548.27/21226.58	% SZS status Ended for HL408643+5.p
159562.11/21228.22	% SZS status Started for HL408650+5.p
159562.11/21228.22	% SZS status GaveUp for HL408650+5.p
159562.11/21228.22	eprover: CPU time limit exceeded, terminating
159562.11/21228.22	% SZS status Ended for HL408650+5.p
159562.78/21228.31	% SZS status Started for HL408645+5.p
159562.78/21228.31	% SZS status GaveUp for HL408645+5.p
159562.78/21228.31	eprover: CPU time limit exceeded, terminating
159562.78/21228.31	% SZS status Ended for HL408645+5.p
159569.94/21229.17	% SZS status Started for HL408654+4.p
159569.94/21229.17	% SZS status GaveUp for HL408654+4.p
159569.94/21229.17	eprover: CPU time limit exceeded, terminating
159569.94/21229.17	% SZS status Ended for HL408654+4.p
159576.95/21230.17	% SZS status Started for HL408646+5.p
159576.95/21230.17	% SZS status GaveUp for HL408646+5.p
159576.95/21230.17	eprover: CPU time limit exceeded, terminating
159576.95/21230.17	% SZS status Ended for HL408646+5.p
159611.12/21231.26	% SZS status Started for HL408656+4.p
159611.12/21231.26	% SZS status GaveUp for HL408656+4.p
159611.12/21231.26	eprover: CPU time limit exceeded, terminating
159611.12/21231.26	% SZS status Ended for HL408656+4.p
159618.52/21232.20	% SZS status Started for HL408657+4.p
159618.52/21232.20	% SZS status GaveUp for HL408657+4.p
159618.52/21232.20	eprover: CPU time limit exceeded, terminating
159618.52/21232.20	% SZS status Ended for HL408657+4.p
159620.23/21232.39	% SZS status Started for HL408648+5.p
159620.23/21232.39	% SZS status GaveUp for HL408648+5.p
159620.23/21232.39	eprover: CPU time limit exceeded, terminating
159620.23/21232.39	% SZS status Ended for HL408648+5.p
159623.41/21232.80	% SZS status Started for HL408652+5.p
159623.41/21232.80	% SZS status GaveUp for HL408652+5.p
159623.41/21232.80	eprover: CPU time limit exceeded, terminating
159623.41/21232.80	% SZS status Ended for HL408652+5.p
159634.67/21234.29	% SZS status Started for HL408658+4.p
159634.67/21234.29	% SZS status GaveUp for HL408658+4.p
159634.67/21234.29	eprover: CPU time limit exceeded, terminating
159634.67/21234.29	% SZS status Ended for HL408658+4.p
159641.52/21235.04	% SZS status Started for HL408653+5.p
159641.52/21235.04	% SZS status GaveUp for HL408653+5.p
159641.52/21235.04	eprover: CPU time limit exceeded, terminating
159641.52/21235.04	% SZS status Ended for HL408653+5.p
159643.50/21235.43	% SZS status Started for HL408659+4.p
159643.50/21235.43	% SZS status GaveUp for HL408659+4.p
159643.50/21235.43	eprover: CPU time limit exceeded, terminating
159643.50/21235.43	% SZS status Ended for HL408659+4.p
159659.41/21237.33	% SZS status Started for HL408660+4.p
159659.41/21237.33	% SZS status GaveUp for HL408660+4.p
159659.41/21237.33	eprover: CPU time limit exceeded, terminating
159659.41/21237.33	% SZS status Ended for HL408660+4.p
159664.28/21237.94	% SZS status Started for HL408654+5.p
159664.28/21237.94	% SZS status GaveUp for HL408654+5.p
159664.28/21237.94	eprover: CPU time limit exceeded, terminating
159664.28/21237.94	% SZS status Ended for HL408654+5.p
159668.61/21238.47	% SZS status Started for HL408661+4.p
159668.61/21238.47	% SZS status GaveUp for HL408661+4.p
159668.61/21238.47	eprover: CPU time limit exceeded, terminating
159668.61/21238.47	% SZS status Ended for HL408661+4.p
159675.34/21239.34	% SZS status Started for HL408656+5.p
159675.34/21239.34	% SZS status GaveUp for HL408656+5.p
159675.34/21239.34	eprover: CPU time limit exceeded, terminating
159675.34/21239.34	% SZS status Ended for HL408656+5.p
159688.70/21240.98	% SZS status Started for HL408663+4.p
159688.70/21240.98	% SZS status GaveUp for HL408663+4.p
159688.70/21240.98	eprover: CPU time limit exceeded, terminating
159688.70/21240.98	% SZS status Ended for HL408663+4.p
159689.91/21241.19	% SZS status Started for HL408657+5.p
159689.91/21241.19	% SZS status GaveUp for HL408657+5.p
159689.91/21241.19	eprover: CPU time limit exceeded, terminating
159689.91/21241.19	% SZS status Ended for HL408657+5.p
159699.70/21242.38	% SZS status Started for HL408665+4.p
159699.70/21242.38	% SZS status GaveUp for HL408665+4.p
159699.70/21242.38	eprover: CPU time limit exceeded, terminating
159699.70/21242.38	% SZS status Ended for HL408665+4.p
159706.02/21243.24	% SZS status Started for HL408658+5.p
159706.02/21243.24	% SZS status GaveUp for HL408658+5.p
159706.02/21243.24	eprover: CPU time limit exceeded, terminating
159706.02/21243.24	% SZS status Ended for HL408658+5.p
159713.11/21244.06	% SZS status Started for HL408659+5.p
159713.11/21244.06	% SZS status GaveUp for HL408659+5.p
159713.11/21244.06	eprover: CPU time limit exceeded, terminating
159713.11/21244.06	% SZS status Ended for HL408659+5.p
159714.22/21244.23	% SZS status Started for HL408666+4.p
159714.22/21244.23	% SZS status GaveUp for HL408666+4.p
159714.22/21244.23	eprover: CPU time limit exceeded, terminating
159714.22/21244.23	% SZS status Ended for HL408666+4.p
159730.14/21246.27	% SZS status Started for HL408668+4.p
159730.14/21246.27	% SZS status GaveUp for HL408668+4.p
159730.14/21246.27	eprover: CPU time limit exceeded, terminating
159730.14/21246.27	% SZS status Ended for HL408668+4.p
159732.06/21246.41	% SZS status Started for HL408660+5.p
159732.06/21246.41	% SZS status GaveUp for HL408660+5.p
159732.06/21246.41	eprover: CPU time limit exceeded, terminating
159732.06/21246.41	% SZS status Ended for HL408660+5.p
159738.62/21247.27	% SZS status Started for HL408669+4.p
159738.62/21247.27	% SZS status GaveUp for HL408669+4.p
159738.62/21247.27	eprover: CPU time limit exceeded, terminating
159738.62/21247.27	% SZS status Ended for HL408669+4.p
159747.09/21248.34	% SZS status Started for HL408661+5.p
159747.09/21248.34	% SZS status GaveUp for HL408661+5.p
159747.09/21248.34	eprover: CPU time limit exceeded, terminating
159747.09/21248.34	% SZS status Ended for HL408661+5.p
159756.09/21249.47	% SZS status Started for HL408663+5.p
159756.09/21249.47	% SZS status GaveUp for HL408663+5.p
159756.09/21249.47	eprover: CPU time limit exceeded, terminating
159756.09/21249.47	% SZS status Ended for HL408663+5.p
159756.56/21249.60	% SZS status Started for HL408670+4.p
159756.56/21249.60	% SZS status GaveUp for HL408670+4.p
159756.56/21249.60	eprover: CPU time limit exceeded, terminating
159756.56/21249.60	% SZS status Ended for HL408670+4.p
159770.06/21251.37	% SZS status Started for HL408671+4.p
159770.06/21251.37	% SZS status GaveUp for HL408671+4.p
159770.06/21251.37	eprover: CPU time limit exceeded, terminating
159770.06/21251.37	% SZS status Ended for HL408671+4.p
159776.73/21252.04	% SZS status Started for HL408665+5.p
159776.73/21252.04	% SZS status GaveUp for HL408665+5.p
159776.73/21252.04	eprover: CPU time limit exceeded, terminating
159776.73/21252.04	% SZS status Ended for HL408665+5.p
159781.50/21252.66	% SZS status Started for HL408673+4.p
159781.50/21252.66	% SZS status GaveUp for HL408673+4.p
159781.50/21252.66	eprover: CPU time limit exceeded, terminating
159781.50/21252.66	% SZS status Ended for HL408673+4.p
159787.11/21253.37	% SZS status Started for HL408666+5.p
159787.11/21253.37	% SZS status GaveUp for HL408666+5.p
159787.11/21253.37	eprover: CPU time limit exceeded, terminating
159787.11/21253.37	% SZS status Ended for HL408666+5.p
159800.67/21255.07	% SZS status Started for HL408668+5.p
159800.67/21255.07	% SZS status GaveUp for HL408668+5.p
159800.67/21255.07	eprover: CPU time limit exceeded, terminating
159800.67/21255.07	% SZS status Ended for HL408668+5.p
159800.67/21255.09	% SZS status Started for HL408674+4.p
159800.67/21255.09	% SZS status GaveUp for HL408674+4.p
159800.67/21255.09	eprover: CPU time limit exceeded, terminating
159800.67/21255.09	% SZS status Ended for HL408674+4.p
159810.84/21256.40	% SZS status Started for HL408675+4.p
159810.84/21256.40	% SZS status GaveUp for HL408675+4.p
159810.84/21256.40	eprover: CPU time limit exceeded, terminating
159810.84/21256.40	% SZS status Ended for HL408675+4.p
159818.23/21257.28	% SZS status Started for HL408669+5.p
159818.23/21257.28	% SZS status GaveUp for HL408669+5.p
159818.23/21257.28	eprover: CPU time limit exceeded, terminating
159818.23/21257.28	% SZS status Ended for HL408669+5.p
159824.47/21258.13	% SZS status Started for HL408676+4.p
159824.47/21258.13	% SZS status GaveUp for HL408676+4.p
159824.47/21258.13	eprover: CPU time limit exceeded, terminating
159824.47/21258.13	% SZS status Ended for HL408676+4.p
159825.95/21258.26	% SZS status Started for HL408670+5.p
159825.95/21258.26	% SZS status GaveUp for HL408670+5.p
159825.95/21258.26	eprover: CPU time limit exceeded, terminating
159825.95/21258.26	% SZS status Ended for HL408670+5.p
159842.69/21260.35	% SZS status Started for HL408678+4.p
159842.69/21260.35	% SZS status GaveUp for HL408678+4.p
159842.69/21260.35	eprover: CPU time limit exceeded, terminating
159842.69/21260.35	% SZS status Ended for HL408678+4.p
159843.25/21260.52	% SZS status Started for HL408671+5.p
159843.25/21260.52	% SZS status GaveUp for HL408671+5.p
159843.25/21260.52	eprover: CPU time limit exceeded, terminating
159843.25/21260.52	% SZS status Ended for HL408671+5.p
159850.00/21261.30	% SZS status Started for HL408679+4.p
159850.00/21261.30	% SZS status GaveUp for HL408679+4.p
159850.00/21261.30	eprover: CPU time limit exceeded, terminating
159850.00/21261.30	% SZS status Ended for HL408679+4.p
159858.31/21262.37	% SZS status Started for HL408673+5.p
159858.31/21262.37	% SZS status GaveUp for HL408673+5.p
159858.31/21262.37	eprover: CPU time limit exceeded, terminating
159858.31/21262.37	% SZS status Ended for HL408673+5.p
159868.11/21263.56	% SZS status Started for HL408681+4.p
159868.11/21263.56	% SZS status GaveUp for HL408681+4.p
159868.11/21263.56	eprover: CPU time limit exceeded, terminating
159868.11/21263.56	% SZS status Ended for HL408681+4.p
159870.23/21263.87	% SZS status Started for HL408674+5.p
159870.23/21263.87	% SZS status GaveUp for HL408674+5.p
159870.23/21263.87	eprover: CPU time limit exceeded, terminating
159870.23/21263.87	% SZS status Ended for HL408674+5.p
159882.19/21265.41	% SZS status Started for HL408682+4.p
159882.19/21265.41	% SZS status GaveUp for HL408682+4.p
159882.19/21265.41	eprover: CPU time limit exceeded, terminating
159882.19/21265.41	% SZS status Ended for HL408682+4.p
159887.75/21266.08	% SZS status Started for HL408675+5.p
159887.75/21266.08	% SZS status GaveUp for HL408675+5.p
159887.75/21266.08	eprover: CPU time limit exceeded, terminating
159887.75/21266.08	% SZS status Ended for HL408675+5.p
159893.55/21266.91	% SZS status Started for HL408684+4.p
159893.55/21266.91	% SZS status GaveUp for HL408684+4.p
159893.55/21266.91	eprover: CPU time limit exceeded, terminating
159893.55/21266.91	% SZS status Ended for HL408684+4.p
159898.30/21267.44	% SZS status Started for HL408676+5.p
159898.30/21267.44	% SZS status GaveUp for HL408676+5.p
159898.30/21267.44	eprover: CPU time limit exceeded, terminating
159898.30/21267.44	% SZS status Ended for HL408676+5.p
159911.98/21269.11	% SZS status Started for HL408685+4.p
159911.98/21269.11	% SZS status GaveUp for HL408685+4.p
159911.98/21269.11	eprover: CPU time limit exceeded, terminating
159911.98/21269.11	% SZS status Ended for HL408685+4.p
159917.00/21269.71	% SZS status Started for HL408678+5.p
159917.00/21269.71	% SZS status GaveUp for HL408678+5.p
159917.00/21269.71	eprover: CPU time limit exceeded, terminating
159917.00/21269.71	% SZS status Ended for HL408678+5.p
159922.36/21270.47	% SZS status Started for HL408686+4.p
159922.36/21270.47	% SZS status GaveUp for HL408686+4.p
159922.36/21270.47	eprover: CPU time limit exceeded, terminating
159922.36/21270.47	% SZS status Ended for HL408686+4.p
159929.98/21271.36	% SZS status Started for HL408679+5.p
159929.98/21271.36	% SZS status GaveUp for HL408679+5.p
159929.98/21271.36	eprover: CPU time limit exceeded, terminating
159929.98/21271.36	% SZS status Ended for HL408679+5.p
159937.66/21272.33	% SZS status Started for HL408681+5.p
159937.66/21272.33	% SZS status GaveUp for HL408681+5.p
159937.66/21272.33	eprover: CPU time limit exceeded, terminating
159937.66/21272.33	% SZS status Ended for HL408681+5.p
159940.20/21272.77	% SZS status Started for HL408687+4.p
159940.20/21272.77	% SZS status GaveUp for HL408687+4.p
159940.20/21272.77	eprover: CPU time limit exceeded, terminating
159940.20/21272.77	% SZS status Ended for HL408687+4.p
159954.28/21274.39	% SZS status Started for HL408688+4.p
159954.28/21274.39	% SZS status GaveUp for HL408688+4.p
159954.28/21274.39	eprover: CPU time limit exceeded, terminating
159954.28/21274.39	% SZS status Ended for HL408688+4.p
159955.44/21274.66	% SZS status Started for HL408682+5.p
159955.44/21274.66	% SZS status GaveUp for HL408682+5.p
159955.44/21274.66	eprover: CPU time limit exceeded, terminating
159955.44/21274.66	% SZS status Ended for HL408682+5.p
159964.80/21275.81	% SZS status Started for HL408689+4.p
159964.80/21275.81	% SZS status GaveUp for HL408689+4.p
159964.80/21275.81	eprover: CPU time limit exceeded, terminating
159964.80/21275.81	% SZS status Ended for HL408689+4.p
159968.94/21276.41	% SZS status Started for HL408684+5.p
159968.94/21276.41	% SZS status GaveUp for HL408684+5.p
159968.94/21276.41	eprover: CPU time limit exceeded, terminating
159968.94/21276.41	% SZS status Ended for HL408684+5.p
159979.30/21277.69	% SZS status Started for HL408690+4.p
159979.30/21277.69	% SZS status GaveUp for HL408690+4.p
159979.30/21277.69	eprover: CPU time limit exceeded, terminating
159979.30/21277.69	% SZS status Ended for HL408690+4.p
159982.34/21277.91	% SZS status Started for HL408685+5.p
159982.34/21277.91	% SZS status GaveUp for HL408685+5.p
159982.34/21277.91	eprover: CPU time limit exceeded, terminating
159982.34/21277.91	% SZS status Ended for HL408685+5.p
159994.09/21279.44	% SZS status Started for HL408691+4.p
159994.09/21279.44	% SZS status GaveUp for HL408691+4.p
159994.09/21279.44	eprover: CPU time limit exceeded, terminating
159994.09/21279.44	% SZS status Ended for HL408691+4.p
159998.77/21280.09	% SZS status Started for HL408686+5.p
159998.77/21280.09	% SZS status GaveUp for HL408686+5.p
159998.77/21280.09	eprover: CPU time limit exceeded, terminating
159998.77/21280.09	% SZS status Ended for HL408686+5.p
160006.45/21280.95	% SZS status Started for HL408693+4.p
160006.45/21280.95	% SZS status GaveUp for HL408693+4.p
160006.45/21280.95	eprover: CPU time limit exceeded, terminating
160006.45/21280.95	% SZS status Ended for HL408693+4.p
160014.84/21282.01	% SZS status Started for HL408687+5.p
160014.84/21282.01	% SZS status GaveUp for HL408687+5.p
160014.84/21282.01	eprover: CPU time limit exceeded, terminating
160014.84/21282.01	% SZS status Ended for HL408687+5.p
160022.81/21283.12	% SZS status Started for HL408694+4.p
160022.81/21283.12	% SZS status GaveUp for HL408694+4.p
160022.81/21283.12	eprover: CPU time limit exceeded, terminating
160022.81/21283.12	% SZS status Ended for HL408694+4.p
160025.31/21283.32	% SZS status Started for HL408688+5.p
160025.31/21283.32	% SZS status GaveUp for HL408688+5.p
160025.31/21283.32	eprover: CPU time limit exceeded, terminating
160025.31/21283.32	% SZS status Ended for HL408688+5.p
160039.62/21285.20	% SZS status Started for HL408696+4.p
160039.62/21285.20	% SZS status GaveUp for HL408696+4.p
160039.62/21285.20	eprover: CPU time limit exceeded, terminating
160039.62/21285.20	% SZS status Ended for HL408696+4.p
160041.52/21285.39	% SZS status Started for HL408689+5.p
160041.52/21285.39	% SZS status GaveUp for HL408689+5.p
160041.52/21285.39	eprover: CPU time limit exceeded, terminating
160041.52/21285.39	% SZS status Ended for HL408689+5.p
160047.17/21286.36	% SZS status Started for HL408697+4.p
160047.17/21286.36	% SZS status GaveUp for HL408697+4.p
160047.17/21286.36	eprover: CPU time limit exceeded, terminating
160047.17/21286.36	% SZS status Ended for HL408697+4.p
160053.09/21286.84	% SZS status Started for HL408690+5.p
160053.09/21286.84	% SZS status GaveUp for HL408690+5.p
160053.09/21286.84	eprover: CPU time limit exceeded, terminating
160053.09/21286.84	% SZS status Ended for HL408690+5.p
160065.86/21288.46	% SZS status Started for HL408698+4.p
160065.86/21288.46	% SZS status GaveUp for HL408698+4.p
160065.86/21288.46	eprover: CPU time limit exceeded, terminating
160065.86/21288.46	% SZS status Ended for HL408698+4.p
160067.19/21288.71	% SZS status Started for HL408691+5.p
160067.19/21288.71	% SZS status GaveUp for HL408691+5.p
160067.19/21288.71	eprover: CPU time limit exceeded, terminating
160067.19/21288.71	% SZS status Ended for HL408691+5.p
160076.00/21289.88	% SZS status Started for HL408700+4.p
160076.00/21289.88	% SZS status GaveUp for HL408700+4.p
160076.00/21289.88	eprover: CPU time limit exceeded, terminating
160076.00/21289.88	% SZS status Ended for HL408700+4.p
160081.62/21290.44	% SZS status Started for HL408693+5.p
160081.62/21290.44	% SZS status GaveUp for HL408693+5.p
160081.62/21290.44	eprover: CPU time limit exceeded, terminating
160081.62/21290.44	% SZS status Ended for HL408693+5.p
160091.52/21291.75	% SZS status Started for HL408702+4.p
160091.52/21291.75	% SZS status GaveUp for HL408702+4.p
160091.52/21291.75	eprover: CPU time limit exceeded, terminating
160091.52/21291.75	% SZS status Ended for HL408702+4.p
160093.06/21291.98	% SZS status Started for HL408694+5.p
160093.06/21291.98	% SZS status GaveUp for HL408694+5.p
160093.06/21291.98	eprover: CPU time limit exceeded, terminating
160093.06/21291.98	% SZS status Ended for HL408694+5.p
160115.31/21293.48	% SZS status Started for HL408703+4.p
160115.31/21293.48	% SZS status GaveUp for HL408703+4.p
160115.31/21293.48	eprover: CPU time limit exceeded, terminating
160115.31/21293.48	% SZS status Ended for HL408703+4.p
160120.98/21294.14	% SZS status Started for HL408696+5.p
160120.98/21294.14	% SZS status GaveUp for HL408696+5.p
160120.98/21294.14	eprover: CPU time limit exceeded, terminating
160120.98/21294.14	% SZS status Ended for HL408696+5.p
160127.55/21295.02	% SZS status Started for HL408706+4.p
160127.55/21295.02	% SZS status GaveUp for HL408706+4.p
160127.55/21295.02	eprover: CPU time limit exceeded, terminating
160127.55/21295.02	% SZS status Ended for HL408706+4.p
160137.53/21296.22	% SZS status Started for HL408697+5.p
160137.53/21296.22	% SZS status GaveUp for HL408697+5.p
160137.53/21296.22	eprover: CPU time limit exceeded, terminating
160137.53/21296.22	% SZS status Ended for HL408697+5.p
160143.70/21297.17	% SZS status Started for HL408707+4.p
160143.70/21297.17	% SZS status GaveUp for HL408707+4.p
160143.70/21297.17	eprover: CPU time limit exceeded, terminating
160143.70/21297.17	% SZS status Ended for HL408707+4.p
160151.31/21297.94	% SZS status Started for HL408698+5.p
160151.31/21297.94	% SZS status GaveUp for HL408698+5.p
160151.31/21297.94	eprover: CPU time limit exceeded, terminating
160151.31/21297.94	% SZS status Ended for HL408698+5.p
160161.38/21299.25	% SZS status Started for HL408708+4.p
160161.38/21299.25	% SZS status GaveUp for HL408708+4.p
160161.38/21299.25	eprover: CPU time limit exceeded, terminating
160161.38/21299.25	% SZS status Ended for HL408708+4.p
160163.02/21299.47	% SZS status Started for HL408700+5.p
160163.02/21299.47	% SZS status GaveUp for HL408700+5.p
160163.02/21299.47	eprover: CPU time limit exceeded, terminating
160163.02/21299.47	% SZS status Ended for HL408700+5.p
160173.53/21300.89	% SZS status Started for HL408702+5.p
160173.53/21300.89	% SZS status GaveUp for HL408702+5.p
160173.53/21300.89	eprover: CPU time limit exceeded, terminating
160173.53/21300.89	% SZS status Ended for HL408702+5.p
160175.98/21301.13	% SZS status Started for HL408709+4.p
160175.98/21301.13	% SZS status GaveUp for HL408709+4.p
160175.98/21301.13	eprover: CPU time limit exceeded, terminating
160175.98/21301.13	% SZS status Ended for HL408709+4.p
160186.72/21302.50	% SZS status Started for HL408710+4.p
160186.72/21302.50	% SZS status GaveUp for HL408710+4.p
160186.72/21302.50	eprover: CPU time limit exceeded, terminating
160186.72/21302.50	% SZS status Ended for HL408710+4.p
160187.58/21302.75	% SZS status Started for HL408703+5.p
160187.58/21302.75	% SZS status GaveUp for HL408703+5.p
160187.58/21302.75	eprover: CPU time limit exceeded, terminating
160187.58/21302.75	% SZS status Ended for HL408703+5.p
160200.38/21304.16	% SZS status Started for HL408711+4.p
160200.38/21304.16	% SZS status GaveUp for HL408711+4.p
160200.38/21304.16	eprover: CPU time limit exceeded, terminating
160200.38/21304.16	% SZS status Ended for HL408711+4.p
160201.97/21304.48	% SZS status Started for HL408706+5.p
160201.97/21304.48	% SZS status GaveUp for HL408706+5.p
160201.97/21304.48	eprover: CPU time limit exceeded, terminating
160201.97/21304.48	% SZS status Ended for HL408706+5.p
160213.14/21305.78	% SZS status Started for HL408712+4.p
160213.14/21305.78	% SZS status GaveUp for HL408712+4.p
160213.14/21305.78	eprover: CPU time limit exceeded, terminating
160213.14/21305.78	% SZS status Ended for HL408712+4.p
160214.97/21306.02	% SZS status Started for HL408707+5.p
160214.97/21306.02	% SZS status GaveUp for HL408707+5.p
160214.97/21306.02	eprover: CPU time limit exceeded, terminating
160214.97/21306.02	% SZS status Ended for HL408707+5.p
160225.44/21307.52	% SZS status Started for HL408713+4.p
160225.44/21307.52	% SZS status GaveUp for HL408713+4.p
160225.44/21307.52	eprover: CPU time limit exceeded, terminating
160225.44/21307.52	% SZS status Ended for HL408713+4.p
160234.72/21308.20	% SZS status Started for HL408708+5.p
160234.72/21308.20	% SZS status GaveUp for HL408708+5.p
160234.72/21308.20	eprover: CPU time limit exceeded, terminating
160234.72/21308.20	% SZS status Ended for HL408708+5.p
160242.14/21309.05	% SZS status Started for HL408714+4.p
160242.14/21309.05	% SZS status GaveUp for HL408714+4.p
160242.14/21309.05	eprover: CPU time limit exceeded, terminating
160242.14/21309.05	% SZS status Ended for HL408714+4.p
160251.47/21310.25	% SZS status Started for HL408709+5.p
160251.47/21310.25	% SZS status GaveUp for HL408709+5.p
160251.47/21310.25	eprover: CPU time limit exceeded, terminating
160251.47/21310.25	% SZS status Ended for HL408709+5.p
160258.92/21311.25	% SZS status Started for HL408716+4.p
160258.92/21311.25	% SZS status GaveUp for HL408716+4.p
160258.92/21311.25	eprover: CPU time limit exceeded, terminating
160258.92/21311.25	% SZS status Ended for HL408716+4.p
160268.70/21312.40	% SZS status Started for HL408710+5.p
160268.70/21312.40	% SZS status GaveUp for HL408710+5.p
160268.70/21312.40	eprover: CPU time limit exceeded, terminating
160268.70/21312.40	% SZS status Ended for HL408710+5.p
160275.44/21313.29	% SZS status Started for HL408719+4.p
160275.44/21313.29	% SZS status GaveUp for HL408719+4.p
160275.44/21313.29	eprover: CPU time limit exceeded, terminating
160275.44/21313.29	% SZS status Ended for HL408719+4.p
160277.30/21313.47	% SZS status Started for HL408711+5.p
160277.30/21313.47	% SZS status GaveUp for HL408711+5.p
160277.30/21313.47	eprover: CPU time limit exceeded, terminating
160277.30/21313.47	% SZS status Ended for HL408711+5.p
160290.62/21315.16	% SZS status Started for HL408712+5.p
160290.62/21315.16	% SZS status GaveUp for HL408712+5.p
160290.62/21315.16	eprover: CPU time limit exceeded, terminating
160290.62/21315.16	% SZS status Ended for HL408712+5.p
160292.23/21315.43	% SZS status Started for HL408720+4.p
160292.23/21315.43	% SZS status GaveUp for HL408720+4.p
160292.23/21315.43	eprover: CPU time limit exceeded, terminating
160292.23/21315.43	% SZS status Ended for HL408720+4.p
160301.19/21316.50	% SZS status Started for HL408721+4.p
160301.19/21316.50	% SZS status GaveUp for HL408721+4.p
160301.19/21316.50	eprover: CPU time limit exceeded, terminating
160301.19/21316.50	% SZS status Ended for HL408721+4.p
160303.28/21316.81	% SZS status Started for HL408713+5.p
160303.28/21316.81	% SZS status GaveUp for HL408713+5.p
160303.28/21316.81	eprover: CPU time limit exceeded, terminating
160303.28/21316.81	% SZS status Ended for HL408713+5.p
160316.17/21318.47	% SZS status Started for HL408722+4.p
160316.17/21318.47	% SZS status GaveUp for HL408722+4.p
160316.17/21318.47	eprover: CPU time limit exceeded, terminating
160316.17/21318.47	% SZS status Ended for HL408722+4.p
160319.98/21318.82	% SZS status Started for HL408714+5.p
160319.98/21318.82	% SZS status GaveUp for HL408714+5.p
160319.98/21318.82	eprover: CPU time limit exceeded, terminating
160319.98/21318.82	% SZS status Ended for HL408714+5.p
160328.52/21319.92	% SZS status Started for HL408724+4.p
160328.52/21319.92	% SZS status GaveUp for HL408724+4.p
160328.52/21319.92	eprover: CPU time limit exceeded, terminating
160328.52/21319.92	% SZS status Ended for HL408724+4.p
160328.86/21320.03	% SZS status Started for HL408716+5.p
160328.86/21320.03	% SZS status GaveUp for HL408716+5.p
160328.86/21320.03	eprover: CPU time limit exceeded, terminating
160328.86/21320.03	% SZS status Ended for HL408716+5.p
160343.67/21321.87	% SZS status Started for HL408725+4.p
160343.67/21321.87	% SZS status GaveUp for HL408725+4.p
160343.67/21321.87	eprover: CPU time limit exceeded, terminating
160343.67/21321.87	% SZS status Ended for HL408725+4.p
160346.86/21322.24	% SZS status Started for HL408719+5.p
160346.86/21322.24	% SZS status GaveUp for HL408719+5.p
160346.86/21322.24	eprover: CPU time limit exceeded, terminating
160346.86/21322.24	% SZS status Ended for HL408719+5.p
160353.78/21323.15	% SZS status Started for HL408726+4.p
160353.78/21323.15	% SZS status GaveUp for HL408726+4.p
160353.78/21323.15	eprover: CPU time limit exceeded, terminating
160353.78/21323.15	% SZS status Ended for HL408726+4.p
160362.92/21324.31	% SZS status Started for HL408720+5.p
160362.92/21324.31	% SZS status GaveUp for HL408720+5.p
160362.92/21324.31	eprover: CPU time limit exceeded, terminating
160362.92/21324.31	% SZS status Ended for HL408720+5.p
160371.39/21325.30	% SZS status Started for HL408729+4.p
160371.39/21325.30	% SZS status GaveUp for HL408729+4.p
160371.39/21325.30	eprover: CPU time limit exceeded, terminating
160371.39/21325.30	% SZS status Ended for HL408729+4.p
160377.19/21326.13	% SZS status Started for HL408721+5.p
160377.19/21326.13	% SZS status GaveUp for HL408721+5.p
160377.19/21326.13	eprover: CPU time limit exceeded, terminating
160377.19/21326.13	% SZS status Ended for HL408721+5.p
160387.59/21327.40	% SZS status Started for HL408730+4.p
160387.59/21327.40	% SZS status GaveUp for HL408730+4.p
160387.59/21327.40	eprover: CPU time limit exceeded, terminating
160387.59/21327.40	% SZS status Ended for HL408730+4.p
160388.61/21327.53	% SZS status Started for HL408722+5.p
160388.61/21327.53	% SZS status GaveUp for HL408722+5.p
160388.61/21327.53	eprover: CPU time limit exceeded, terminating
160388.61/21327.53	% SZS status Ended for HL408722+5.p
160401.34/21329.16	% SZS status Started for HL408731+4.p
160401.34/21329.16	% SZS status GaveUp for HL408731+4.p
160401.34/21329.16	eprover: CPU time limit exceeded, terminating
160401.34/21329.16	% SZS status Ended for HL408731+4.p
160404.03/21329.47	% SZS status Started for HL408724+5.p
160404.03/21329.47	% SZS status GaveUp for HL408724+5.p
160404.03/21329.47	eprover: CPU time limit exceeded, terminating
160404.03/21329.47	% SZS status Ended for HL408724+5.p
160413.27/21330.57	% SZS status Started for HL408732+4.p
160413.27/21330.57	% SZS status GaveUp for HL408732+4.p
160413.27/21330.57	eprover: CPU time limit exceeded, terminating
160413.27/21330.57	% SZS status Ended for HL408732+4.p
160415.33/21330.91	% SZS status Started for HL408725+5.p
160415.33/21330.91	% SZS status GaveUp for HL408725+5.p
160415.33/21330.91	eprover: CPU time limit exceeded, terminating
160415.33/21330.91	% SZS status Ended for HL408725+5.p
160428.59/21332.52	% SZS status Started for HL408733+4.p
160428.59/21332.52	% SZS status GaveUp for HL408733+4.p
160428.59/21332.52	eprover: CPU time limit exceeded, terminating
160428.59/21332.52	% SZS status Ended for HL408733+4.p
160430.23/21332.88	% SZS status Started for HL408726+5.p
160430.23/21332.88	% SZS status GaveUp for HL408726+5.p
160430.23/21332.88	eprover: CPU time limit exceeded, terminating
160430.23/21332.88	% SZS status Ended for HL408726+5.p
160440.22/21333.99	% SZS status Started for HL408736+4.p
160440.22/21333.99	% SZS status GaveUp for HL408736+4.p
160440.22/21333.99	eprover: CPU time limit exceeded, terminating
160440.22/21333.99	% SZS status Ended for HL408736+4.p
160442.12/21334.19	% SZS status Started for HL408729+5.p
160442.12/21334.19	% SZS status GaveUp for HL408729+5.p
160442.12/21334.19	eprover: CPU time limit exceeded, terminating
160442.12/21334.19	% SZS status Ended for HL408729+5.p
160454.00/21335.93	% SZS status Started for HL408737+4.p
160454.00/21335.93	% SZS status GaveUp for HL408737+4.p
160454.00/21335.93	eprover: CPU time limit exceeded, terminating
160454.00/21335.93	% SZS status Ended for HL408737+4.p
160460.14/21336.47	% SZS status Started for HL408730+5.p
160460.14/21336.47	% SZS status GaveUp for HL408730+5.p
160460.14/21336.47	eprover: CPU time limit exceeded, terminating
160460.14/21336.47	% SZS status Ended for HL408730+5.p
160465.97/21337.23	% SZS status Started for HL408739+4.p
160465.97/21337.23	% SZS status GaveUp for HL408739+4.p
160465.97/21337.23	eprover: CPU time limit exceeded, terminating
160465.97/21337.23	% SZS status Ended for HL408739+4.p
160475.11/21338.33	% SZS status Started for HL408731+5.p
160475.11/21338.33	% SZS status GaveUp for HL408731+5.p
160475.11/21338.33	eprover: CPU time limit exceeded, terminating
160475.11/21338.33	% SZS status Ended for HL408731+5.p
160483.89/21339.57	% SZS status Started for HL408740+4.p
160483.89/21339.57	% SZS status GaveUp for HL408740+4.p
160483.89/21339.57	eprover: CPU time limit exceeded, terminating
160483.89/21339.57	% SZS status Ended for HL408740+4.p
160484.50/21339.70	% SZS status Started for HL408732+5.p
160484.50/21339.70	% SZS status GaveUp for HL408732+5.p
160484.50/21339.70	eprover: CPU time limit exceeded, terminating
160484.50/21339.70	% SZS status Ended for HL408732+5.p
160499.19/21341.36	% SZS status Started for HL408741+4.p
160499.19/21341.36	% SZS status GaveUp for HL408741+4.p
160499.19/21341.36	eprover: CPU time limit exceeded, terminating
160499.19/21341.36	% SZS status Ended for HL408741+4.p
160509.58/21342.72	% SZS status Started for HL408742+4.p
160509.58/21342.72	% SZS status GaveUp for HL408742+4.p
160509.58/21342.72	eprover: CPU time limit exceeded, terminating
160509.58/21342.72	% SZS status Ended for HL408742+4.p
160534.09/21345.76	% SZS status Started for HL408743+4.p
160534.09/21345.76	% SZS status GaveUp for HL408743+4.p
160534.09/21345.76	eprover: CPU time limit exceeded, terminating
160534.09/21345.76	% SZS status Ended for HL408743+4.p
160621.55/21356.76	% SZS status Started for HL408733+5.p
160621.55/21356.76	% SZS status GaveUp for HL408733+5.p
160621.55/21356.76	eprover: CPU time limit exceeded, terminating
160621.55/21356.76	% SZS status Ended for HL408733+5.p
160637.27/21358.75	% SZS status Started for HL408736+5.p
160637.27/21358.75	% SZS status GaveUp for HL408736+5.p
160637.27/21358.75	eprover: CPU time limit exceeded, terminating
160637.27/21358.75	% SZS status Ended for HL408736+5.p
160645.80/21359.83	% SZS status Started for HL408745+4.p
160645.80/21359.83	% SZS status GaveUp for HL408745+4.p
160645.80/21359.83	eprover: CPU time limit exceeded, terminating
160645.80/21359.83	% SZS status Ended for HL408745+4.p
160648.28/21360.23	% SZS status Started for HL408737+5.p
160648.28/21360.23	% SZS status GaveUp for HL408737+5.p
160648.28/21360.23	eprover: CPU time limit exceeded, terminating
160648.28/21360.23	% SZS status Ended for HL408737+5.p
160664.88/21362.23	% SZS status Started for HL408739+5.p
160664.88/21362.23	% SZS status GaveUp for HL408739+5.p
160664.88/21362.23	eprover: CPU time limit exceeded, terminating
160664.88/21362.23	% SZS status Ended for HL408739+5.p
160669.70/21362.87	% SZS status Started for HL408746+4.p
160669.70/21362.87	% SZS status GaveUp for HL408746+4.p
160669.70/21362.87	eprover: CPU time limit exceeded, terminating
160669.70/21362.87	% SZS status Ended for HL408746+4.p
160673.98/21363.35	% SZS status Started for HL408740+5.p
160673.98/21363.35	% SZS status GaveUp for HL408740+5.p
160673.98/21363.35	eprover: CPU time limit exceeded, terminating
160673.98/21363.35	% SZS status Ended for HL408740+5.p
160689.30/21365.29	% SZS status Started for HL408747+4.p
160689.30/21365.29	% SZS status GaveUp for HL408747+4.p
160689.30/21365.29	eprover: CPU time limit exceeded, terminating
160689.30/21365.29	% SZS status Ended for HL408747+4.p
160693.56/21365.85	% SZS status Started for HL408741+5.p
160693.56/21365.85	% SZS status GaveUp for HL408741+5.p
160693.56/21365.85	eprover: CPU time limit exceeded, terminating
160693.56/21365.85	% SZS status Ended for HL408741+5.p
160697.56/21366.38	% SZS status Started for HL408748+4.p
160697.56/21366.38	% SZS status GaveUp for HL408748+4.p
160697.56/21366.38	eprover: CPU time limit exceeded, terminating
160697.56/21366.38	% SZS status Ended for HL408748+4.p
160707.70/21367.61	% SZS status Started for HL408742+5.p
160707.70/21367.61	% SZS status GaveUp for HL408742+5.p
160707.70/21367.61	eprover: CPU time limit exceeded, terminating
160707.70/21367.61	% SZS status Ended for HL408742+5.p
160717.69/21368.88	% SZS status Started for HL408749+4.p
160717.69/21368.88	% SZS status GaveUp for HL408749+4.p
160717.69/21368.88	eprover: CPU time limit exceeded, terminating
160717.69/21368.88	% SZS status Ended for HL408749+4.p
160732.44/21370.70	% SZS status Started for HL408750+4.p
160732.44/21370.70	% SZS status GaveUp for HL408750+4.p
160732.44/21370.70	eprover: CPU time limit exceeded, terminating
160732.44/21370.70	% SZS status Ended for HL408750+4.p
160742.98/21372.03	% SZS status Started for HL408743+5.p
160742.98/21372.03	% SZS status GaveUp for HL408743+5.p
160742.98/21372.03	eprover: CPU time limit exceeded, terminating
160742.98/21372.03	% SZS status Ended for HL408743+5.p
160751.55/21373.10	% SZS status Started for HL408747+5.p
160751.55/21373.10	% SZS status GaveUp for HL408747+5.p
160751.55/21373.10	eprover: CPU time limit exceeded, terminating
160751.55/21373.10	% SZS status Ended for HL408747+5.p
160756.12/21373.73	% SZS status Started for HL408752+4.p
160756.12/21373.73	% SZS status GaveUp for HL408752+4.p
160756.12/21373.73	eprover: CPU time limit exceeded, terminating
160756.12/21373.73	% SZS status Ended for HL408752+4.p
160774.94/21376.14	% SZS status Started for HL408753+4.p
160774.94/21376.14	% SZS status GaveUp for HL408753+4.p
160774.94/21376.14	eprover: CPU time limit exceeded, terminating
160774.94/21376.14	% SZS status Ended for HL408753+4.p
160798.88/21379.17	% SZS status Started for HL408754+4.p
160798.88/21379.17	% SZS status GaveUp for HL408754+4.p
160798.88/21379.17	eprover: CPU time limit exceeded, terminating
160798.88/21379.17	% SZS status Ended for HL408754+4.p
160845.45/21384.95	% SZS status Started for HL408745+5.p
160845.45/21384.95	% SZS status GaveUp for HL408745+5.p
160845.45/21384.95	eprover: CPU time limit exceeded, terminating
160845.45/21384.95	% SZS status Ended for HL408745+5.p
160857.02/21386.45	% SZS status Started for HL408746+5.p
160857.02/21386.45	% SZS status GaveUp for HL408746+5.p
160857.02/21386.45	eprover: CPU time limit exceeded, terminating
160857.02/21386.45	% SZS status Ended for HL408746+5.p
160869.98/21388.05	% SZS status Started for HL408755+4.p
160869.98/21388.05	% SZS status GaveUp for HL408755+4.p
160869.98/21388.05	eprover: CPU time limit exceeded, terminating
160869.98/21388.05	% SZS status Ended for HL408755+4.p
160893.70/21391.07	% SZS status Started for HL408756+4.p
160893.70/21391.07	% SZS status GaveUp for HL408756+4.p
160893.70/21391.07	eprover: CPU time limit exceeded, terminating
160893.70/21391.07	% SZS status Ended for HL408756+4.p
160897.30/21391.56	% SZS status Started for HL408748+5.p
160897.30/21391.56	% SZS status GaveUp for HL408748+5.p
160897.30/21391.56	eprover: CPU time limit exceeded, terminating
160897.30/21391.56	% SZS status Ended for HL408748+5.p
160904.91/21392.48	% SZS status Started for HL408749+5.p
160904.91/21392.48	% SZS status GaveUp for HL408749+5.p
160904.91/21392.48	eprover: CPU time limit exceeded, terminating
160904.91/21392.48	% SZS status Ended for HL408749+5.p
160922.44/21394.64	% SZS status Started for HL408757+4.p
160922.44/21394.64	% SZS status GaveUp for HL408757+4.p
160922.44/21394.64	eprover: CPU time limit exceeded, terminating
160922.44/21394.64	% SZS status Ended for HL408757+4.p
160927.81/21395.36	% SZS status Started for HL408750+5.p
160927.81/21395.36	% SZS status GaveUp for HL408750+5.p
160927.81/21395.36	eprover: CPU time limit exceeded, terminating
160927.81/21395.36	% SZS status Ended for HL408750+5.p
160945.86/21397.72	% SZS status Started for HL408758+4.p
160945.86/21397.72	% SZS status GaveUp for HL408758+4.p
160945.86/21397.72	eprover: CPU time limit exceeded, terminating
160945.86/21397.72	% SZS status Ended for HL408758+4.p
160951.92/21398.36	% SZS status Started for HL408752+5.p
160951.92/21398.36	% SZS status GaveUp for HL408752+5.p
160951.92/21398.36	eprover: CPU time limit exceeded, terminating
160951.92/21398.36	% SZS status Ended for HL408752+5.p
160964.98/21400.01	% SZS status Started for HL408753+5.p
160964.98/21400.01	% SZS status GaveUp for HL408753+5.p
160964.98/21400.01	eprover: CPU time limit exceeded, terminating
160964.98/21400.01	% SZS status Ended for HL408753+5.p
160970.95/21400.79	% SZS status Started for HL408760+4.p
160970.95/21400.79	% SZS status GaveUp for HL408760+4.p
160970.95/21400.79	eprover: CPU time limit exceeded, terminating
160970.95/21400.79	% SZS status Ended for HL408760+4.p
160989.25/21403.13	% SZS status Started for HL408762+4.p
160989.25/21403.13	% SZS status GaveUp for HL408762+4.p
160989.25/21403.13	eprover: CPU time limit exceeded, terminating
160989.25/21403.13	% SZS status Ended for HL408762+4.p
161008.20/21405.45	% SZS status Started for HL408754+5.p
161008.20/21405.45	% SZS status GaveUp for HL408754+5.p
161008.20/21405.45	eprover: CPU time limit exceeded, terminating
161008.20/21405.45	% SZS status Ended for HL408754+5.p
161013.72/21406.17	% SZS status Started for HL408763+4.p
161013.72/21406.17	% SZS status GaveUp for HL408763+4.p
161013.72/21406.17	eprover: CPU time limit exceeded, terminating
161013.72/21406.17	% SZS status Ended for HL408763+4.p
161037.56/21409.22	% SZS status Started for HL408764+4.p
161037.56/21409.22	% SZS status GaveUp for HL408764+4.p
161037.56/21409.22	eprover: CPU time limit exceeded, terminating
161037.56/21409.22	% SZS status Ended for HL408764+4.p
161054.70/21411.35	% SZS status Started for HL408762+5.p
161054.70/21411.35	% SZS status GaveUp for HL408762+5.p
161054.70/21411.35	eprover: CPU time limit exceeded, terminating
161054.70/21411.35	% SZS status Ended for HL408762+5.p
161065.08/21412.67	% SZS status Started for HL408755+5.p
161065.08/21412.67	% SZS status GaveUp for HL408755+5.p
161065.08/21412.67	eprover: CPU time limit exceeded, terminating
161065.08/21412.67	% SZS status Ended for HL408755+5.p
161079.42/21414.48	% SZS status Started for HL408765+4.p
161079.42/21414.48	% SZS status GaveUp for HL408765+4.p
161079.42/21414.48	eprover: CPU time limit exceeded, terminating
161079.42/21414.48	% SZS status Ended for HL408765+4.p
161089.67/21415.85	% SZS status Started for HL408763+5.p
161089.67/21415.85	% SZS status GaveUp for HL408763+5.p
161089.67/21415.85	eprover: CPU time limit exceeded, terminating
161089.67/21415.85	% SZS status Ended for HL408763+5.p
161096.77/21416.65	% SZS status Started for HL408760+5.p
161096.77/21416.65	% SZS status GaveUp for HL408760+5.p
161096.77/21416.65	eprover: CPU time limit exceeded, terminating
161096.77/21416.65	% SZS status Ended for HL408760+5.p
161102.70/21417.36	% SZS status Started for HL408756+5.p
161102.70/21417.36	% SZS status GaveUp for HL408756+5.p
161102.70/21417.36	eprover: CPU time limit exceeded, terminating
161102.70/21417.36	% SZS status Ended for HL408756+5.p
161103.97/21417.58	% SZS status Started for HL408766+4.p
161103.97/21417.58	% SZS status GaveUp for HL408766+4.p
161103.97/21417.58	eprover: CPU time limit exceeded, terminating
161103.97/21417.58	% SZS status Ended for HL408766+4.p
161112.27/21418.58	% SZS status Started for HL408757+5.p
161112.27/21418.58	% SZS status GaveUp for HL408757+5.p
161112.27/21418.58	eprover: CPU time limit exceeded, terminating
161112.27/21418.58	% SZS status Ended for HL408757+5.p
161120.77/21419.68	% SZS status Started for HL408767+4.p
161120.77/21419.68	% SZS status GaveUp for HL408767+4.p
161120.77/21419.68	eprover: CPU time limit exceeded, terminating
161120.77/21419.68	% SZS status Ended for HL408767+4.p
161128.61/21420.61	% SZS status Started for HL408768+4.p
161128.61/21420.61	% SZS status GaveUp for HL408768+4.p
161128.61/21420.61	eprover: CPU time limit exceeded, terminating
161128.61/21420.61	% SZS status Ended for HL408768+4.p
161136.06/21421.64	% SZS status Started for HL408758+5.p
161136.06/21421.64	% SZS status GaveUp for HL408758+5.p
161136.06/21421.64	eprover: CPU time limit exceeded, terminating
161136.06/21421.64	% SZS status Ended for HL408758+5.p
161144.59/21422.74	% SZS status Started for HL408769+4.p
161144.59/21422.74	% SZS status GaveUp for HL408769+4.p
161144.59/21422.74	eprover: CPU time limit exceeded, terminating
161144.59/21422.74	% SZS status Ended for HL408769+4.p
161146.33/21422.85	% SZS status Started for HL408765+5.p
161146.33/21422.85	% SZS status GaveUp for HL408765+5.p
161146.33/21422.85	eprover: CPU time limit exceeded, terminating
161146.33/21422.85	% SZS status Ended for HL408765+5.p
161160.80/21424.67	% SZS status Started for HL408770+4.p
161160.80/21424.67	% SZS status GaveUp for HL408770+4.p
161160.80/21424.67	eprover: CPU time limit exceeded, terminating
161160.80/21424.67	% SZS status Ended for HL408770+4.p
161170.33/21425.87	% SZS status Started for HL408771+4.p
161170.33/21425.87	% SZS status GaveUp for HL408771+4.p
161170.33/21425.87	eprover: CPU time limit exceeded, terminating
161170.33/21425.87	% SZS status Ended for HL408771+4.p
161175.16/21426.48	% SZS status Started for HL408766+5.p
161175.16/21426.48	% SZS status GaveUp for HL408766+5.p
161175.16/21426.48	eprover: CPU time limit exceeded, terminating
161175.16/21426.48	% SZS status Ended for HL408766+5.p
161194.02/21428.90	% SZS status Started for HL408772+4.p
161194.02/21428.90	% SZS status GaveUp for HL408772+4.p
161194.02/21428.90	eprover: CPU time limit exceeded, terminating
161194.02/21428.90	% SZS status Ended for HL408772+4.p
161218.67/21431.96	% SZS status Started for HL408773+4.p
161218.67/21431.96	% SZS status GaveUp for HL408773+4.p
161218.67/21431.96	eprover: CPU time limit exceeded, terminating
161218.67/21431.96	% SZS status Ended for HL408773+4.p
161246.88/21435.55	% SZS status Started for HL408764+5.p
161246.88/21435.55	% SZS status GaveUp for HL408764+5.p
161246.88/21435.55	eprover: CPU time limit exceeded, terminating
161246.88/21435.55	% SZS status Ended for HL408764+5.p
161271.12/21438.63	% SZS status Started for HL408776+4.p
161271.12/21438.63	% SZS status GaveUp for HL408776+4.p
161271.12/21438.63	eprover: CPU time limit exceeded, terminating
161271.12/21438.63	% SZS status Ended for HL408776+4.p
161309.61/21443.48	% SZS status Started for HL408767+5.p
161309.61/21443.48	% SZS status GaveUp for HL408767+5.p
161309.61/21443.48	eprover: CPU time limit exceeded, terminating
161309.61/21443.48	% SZS status Ended for HL408767+5.p
161320.44/21444.82	% SZS status Started for HL408768+5.p
161320.44/21444.82	% SZS status GaveUp for HL408768+5.p
161320.44/21444.82	eprover: CPU time limit exceeded, terminating
161320.44/21444.82	% SZS status Ended for HL408768+5.p
161334.58/21446.57	% SZS status Started for HL408778+4.p
161334.58/21446.57	% SZS status GaveUp for HL408778+4.p
161334.58/21446.57	eprover: CPU time limit exceeded, terminating
161334.58/21446.57	% SZS status Ended for HL408778+4.p
161339.81/21447.29	% SZS status Started for HL408769+5.p
161339.81/21447.29	% SZS status GaveUp for HL408769+5.p
161339.81/21447.29	eprover: CPU time limit exceeded, terminating
161339.81/21447.29	% SZS status Ended for HL408769+5.p
161352.48/21448.86	% SZS status Started for HL408770+5.p
161352.48/21448.86	% SZS status GaveUp for HL408770+5.p
161352.48/21448.86	eprover: CPU time limit exceeded, terminating
161352.48/21448.86	% SZS status Ended for HL408770+5.p
161359.23/21449.72	% SZS status Started for HL408779+4.p
161359.23/21449.72	% SZS status GaveUp for HL408779+4.p
161359.23/21449.72	eprover: CPU time limit exceeded, terminating
161359.23/21449.72	% SZS status Ended for HL408779+4.p
161368.67/21450.87	% SZS status Started for HL408771+5.p
161368.67/21450.87	% SZS status GaveUp for HL408771+5.p
161368.67/21450.87	eprover: CPU time limit exceeded, terminating
161368.67/21450.87	% SZS status Ended for HL408771+5.p
161376.70/21451.92	% SZS status Started for HL408780+4.p
161376.70/21451.92	% SZS status GaveUp for HL408780+4.p
161376.70/21451.92	eprover: CPU time limit exceeded, terminating
161376.70/21451.92	% SZS status Ended for HL408780+4.p
161382.67/21452.67	% SZS status Started for HL408772+5.p
161382.67/21452.67	% SZS status GaveUp for HL408772+5.p
161382.67/21452.67	eprover: CPU time limit exceeded, terminating
161382.67/21452.67	% SZS status Ended for HL408772+5.p
161392.94/21453.95	% SZS status Started for HL408781+4.p
161392.94/21453.95	% SZS status GaveUp for HL408781+4.p
161392.94/21453.95	eprover: CPU time limit exceeded, terminating
161392.94/21453.95	% SZS status Ended for HL408781+4.p
161406.62/21455.70	% SZS status Started for HL408782+4.p
161406.62/21455.70	% SZS status GaveUp for HL408782+4.p
161406.62/21455.70	eprover: CPU time limit exceeded, terminating
161406.62/21455.70	% SZS status Ended for HL408782+4.p
161428.47/21458.47	% SZS status Started for HL408773+5.p
161428.47/21458.47	% SZS status GaveUp for HL408773+5.p
161428.47/21458.47	eprover: CPU time limit exceeded, terminating
161428.47/21458.47	% SZS status Ended for HL408773+5.p
161430.36/21458.76	% SZS status Started for HL408783+4.p
161430.36/21458.76	% SZS status GaveUp for HL408783+4.p
161430.36/21458.76	eprover: CPU time limit exceeded, terminating
161430.36/21458.76	% SZS status Ended for HL408783+4.p
161442.98/21460.25	% SZS status Started for HL408780+5.p
161442.98/21460.25	% SZS status GaveUp for HL408780+5.p
161442.98/21460.25	eprover: CPU time limit exceeded, terminating
161442.98/21460.25	% SZS status Ended for HL408780+5.p
161455.61/21461.85	% SZS status Started for HL408784+4.p
161455.61/21461.85	% SZS status GaveUp for HL408784+4.p
161455.61/21461.85	eprover: CPU time limit exceeded, terminating
161455.61/21461.85	% SZS status Ended for HL408784+4.p
161475.03/21464.29	% SZS status Started for HL408782+5.p
161475.03/21464.29	% SZS status GaveUp for HL408782+5.p
161475.03/21464.29	eprover: CPU time limit exceeded, terminating
161475.03/21464.29	% SZS status Ended for HL408782+5.p
161480.22/21464.95	% SZS status Started for HL408776+5.p
161480.22/21464.95	% SZS status GaveUp for HL408776+5.p
161480.22/21464.95	eprover: CPU time limit exceeded, terminating
161480.22/21464.95	% SZS status Ended for HL408776+5.p
161480.48/21464.97	% SZS status Started for HL408786+4.p
161480.48/21464.97	% SZS status GaveUp for HL408786+4.p
161480.48/21464.97	eprover: CPU time limit exceeded, terminating
161480.48/21464.97	% SZS status Ended for HL408786+4.p
161504.20/21467.98	% SZS status Started for HL408787+4.p
161504.20/21467.98	% SZS status GaveUp for HL408787+4.p
161504.20/21467.98	eprover: CPU time limit exceeded, terminating
161504.20/21467.98	% SZS status Ended for HL408787+4.p
161523.55/21470.41	% SZS status Started for HL408784+5.p
161523.55/21470.41	% SZS status GaveUp for HL408784+5.p
161523.55/21470.41	eprover: CPU time limit exceeded, terminating
161523.55/21470.41	% SZS status Ended for HL408784+5.p
161528.20/21471.02	% SZS status Started for HL408788+4.p
161528.20/21471.02	% SZS status GaveUp for HL408788+4.p
161528.20/21471.02	eprover: CPU time limit exceeded, terminating
161528.20/21471.02	% SZS status Ended for HL408788+4.p
161528.92/21471.10	% SZS status Started for HL408778+5.p
161528.92/21471.10	% SZS status GaveUp for HL408778+5.p
161528.92/21471.10	eprover: CPU time limit exceeded, terminating
161528.92/21471.10	% SZS status Ended for HL408778+5.p
161548.00/21473.47	% SZS status Started for HL408779+5.p
161548.00/21473.47	% SZS status GaveUp for HL408779+5.p
161548.00/21473.47	eprover: CPU time limit exceeded, terminating
161548.00/21473.47	% SZS status Ended for HL408779+5.p
161552.78/21474.06	% SZS status Started for HL408789+4.p
161552.78/21474.06	% SZS status GaveUp for HL408789+4.p
161552.78/21474.06	eprover: CPU time limit exceeded, terminating
161552.78/21474.06	% SZS status Ended for HL408789+4.p
161553.69/21474.19	% SZS status Started for HL408781+5.p
161553.69/21474.19	% SZS status GaveUp for HL408781+5.p
161553.69/21474.19	eprover: CPU time limit exceeded, terminating
161553.69/21474.19	% SZS status Ended for HL408781+5.p
161570.66/21476.50	% SZS status Started for HL408790+4.p
161570.66/21476.50	% SZS status GaveUp for HL408790+4.p
161570.66/21476.50	eprover: CPU time limit exceeded, terminating
161570.66/21476.50	% SZS status Ended for HL408790+4.p
161577.41/21477.23	% SZS status Started for HL408791+4.p
161577.41/21477.23	% SZS status GaveUp for HL408791+4.p
161577.41/21477.23	eprover: CPU time limit exceeded, terminating
161577.41/21477.23	% SZS status Ended for HL408791+4.p
161602.42/21480.33	% SZS status Started for HL408792+4.p
161602.42/21480.33	% SZS status GaveUp for HL408792+4.p
161602.42/21480.33	eprover: CPU time limit exceeded, terminating
161602.42/21480.33	% SZS status Ended for HL408792+4.p
161637.33/21484.75	% SZS status Started for HL408783+5.p
161637.33/21484.75	% SZS status GaveUp for HL408783+5.p
161637.33/21484.75	eprover: CPU time limit exceeded, terminating
161637.33/21484.75	% SZS status Ended for HL408783+5.p
161661.23/21487.80	% SZS status Started for HL408793+4.p
161661.23/21487.80	% SZS status GaveUp for HL408793+4.p
161661.23/21487.80	eprover: CPU time limit exceeded, terminating
161661.23/21487.80	% SZS status Ended for HL408793+4.p
161684.56/21490.67	% SZS status Started for HL408786+5.p
161684.56/21490.67	% SZS status GaveUp for HL408786+5.p
161684.56/21490.67	eprover: CPU time limit exceeded, terminating
161684.56/21490.67	% SZS status Ended for HL408786+5.p
161688.95/21491.19	% SZS status Started for HL408787+5.p
161688.95/21491.19	% SZS status GaveUp for HL408787+5.p
161688.95/21491.19	eprover: CPU time limit exceeded, terminating
161688.95/21491.19	% SZS status Ended for HL408787+5.p
161709.06/21493.76	% SZS status Started for HL408794+4.p
161709.06/21493.76	% SZS status GaveUp for HL408794+4.p
161709.06/21493.76	eprover: CPU time limit exceeded, terminating
161709.06/21493.76	% SZS status Ended for HL408794+4.p
161731.61/21496.63	% SZS status Started for HL408788+5.p
161731.61/21496.63	% SZS status GaveUp for HL408788+5.p
161731.61/21496.63	eprover: CPU time limit exceeded, terminating
161731.61/21496.63	% SZS status Ended for HL408788+5.p
161732.50/21496.85	% SZS status Started for HL408795+4.p
161732.50/21496.85	% SZS status GaveUp for HL408795+4.p
161732.50/21496.85	eprover: CPU time limit exceeded, terminating
161732.50/21496.85	% SZS status Ended for HL408795+4.p
161737.92/21497.43	% SZS status Started for HL408789+5.p
161737.92/21497.43	% SZS status GaveUp for HL408789+5.p
161737.92/21497.43	eprover: CPU time limit exceeded, terminating
161737.92/21497.43	% SZS status Ended for HL408789+5.p
161757.50/21499.90	% SZS status Started for HL408796+4.p
161757.50/21499.90	% SZS status GaveUp for HL408796+4.p
161757.50/21499.90	eprover: CPU time limit exceeded, terminating
161757.50/21499.90	% SZS status Ended for HL408796+4.p
161760.14/21500.22	% SZS status Started for HL408790+5.p
161760.14/21500.22	% SZS status GaveUp for HL408790+5.p
161760.14/21500.22	eprover: CPU time limit exceeded, terminating
161760.14/21500.22	% SZS status Ended for HL408790+5.p
161779.52/21502.71	% SZS status Started for HL408791+5.p
161779.52/21502.71	% SZS status GaveUp for HL408791+5.p
161779.52/21502.71	eprover: CPU time limit exceeded, terminating
161779.52/21502.71	% SZS status Ended for HL408791+5.p
161781.66/21502.93	% SZS status Started for HL408797+4.p
161781.66/21502.93	% SZS status GaveUp for HL408797+4.p
161781.66/21502.93	eprover: CPU time limit exceeded, terminating
161781.66/21502.93	% SZS status Ended for HL408797+4.p
161804.48/21505.79	% SZS status Started for HL408798+4.p
161804.48/21505.79	% SZS status GaveUp for HL408798+4.p
161804.48/21505.79	eprover: CPU time limit exceeded, terminating
161804.48/21505.79	% SZS status Ended for HL408798+4.p
161810.52/21506.62	% SZS status Started for HL408792+5.p
161810.52/21506.62	% SZS status GaveUp for HL408792+5.p
161810.52/21506.62	eprover: CPU time limit exceeded, terminating
161810.52/21506.62	% SZS status Ended for HL408792+5.p
161816.08/21507.23	% SZS status Started for HL408795+5.p
161816.08/21507.23	% SZS status GaveUp for HL408795+5.p
161816.08/21507.23	eprover: CPU time limit exceeded, terminating
161816.08/21507.23	% SZS status Ended for HL408795+5.p
161819.45/21507.72	% SZS status Started for HL408796+5.p
161819.45/21507.72	% SZS status GaveUp for HL408796+5.p
161819.45/21507.72	eprover: CPU time limit exceeded, terminating
161819.45/21507.72	% SZS status Ended for HL408796+5.p
161827.83/21508.82	% SZS status Started for HL408799+4.p
161827.83/21508.82	% SZS status GaveUp for HL408799+4.p
161827.83/21508.82	eprover: CPU time limit exceeded, terminating
161827.83/21508.82	% SZS status Ended for HL408799+4.p
161839.84/21510.28	% SZS status Started for HL408803+4.p
161839.84/21510.28	% SZS status GaveUp for HL408803+4.p
161839.84/21510.28	eprover: CPU time limit exceeded, terminating
161839.84/21510.28	% SZS status Ended for HL408803+4.p
161852.75/21511.86	% SZS status Started for HL408805+4.p
161852.75/21511.86	% SZS status GaveUp for HL408805+4.p
161852.75/21511.86	eprover: CPU time limit exceeded, terminating
161852.75/21511.86	% SZS status Ended for HL408805+4.p
161869.70/21514.02	% SZS status Started for HL408793+5.p
161869.70/21514.02	% SZS status GaveUp for HL408793+5.p
161869.70/21514.02	eprover: CPU time limit exceeded, terminating
161869.70/21514.02	% SZS status Ended for HL408793+5.p
161876.34/21514.88	% SZS status Started for HL408806+4.p
161876.34/21514.88	% SZS status GaveUp for HL408806+4.p
161876.34/21514.88	eprover: CPU time limit exceeded, terminating
161876.34/21514.88	% SZS status Ended for HL408806+4.p
161896.91/21517.44	% SZS status Started for HL408794+5.p
161896.91/21517.44	% SZS status GaveUp for HL408794+5.p
161896.91/21517.44	eprover: CPU time limit exceeded, terminating
161896.91/21517.44	% SZS status Ended for HL408794+5.p
161900.75/21517.93	% SZS status Started for HL408807+4.p
161900.75/21517.93	% SZS status GaveUp for HL408807+4.p
161900.75/21517.93	eprover: CPU time limit exceeded, terminating
161900.75/21517.93	% SZS status Ended for HL408807+4.p
161925.09/21520.96	% SZS status Started for HL408808+4.p
161925.09/21520.96	% SZS status GaveUp for HL408808+4.p
161925.09/21520.96	eprover: CPU time limit exceeded, terminating
161925.09/21520.96	% SZS status Ended for HL408808+4.p
161967.69/21526.43	% SZS status Started for HL408797+5.p
161967.69/21526.43	% SZS status GaveUp for HL408797+5.p
161967.69/21526.43	eprover: CPU time limit exceeded, terminating
161967.69/21526.43	% SZS status Ended for HL408797+5.p
161989.09/21529.02	% SZS status Started for HL408798+5.p
161989.09/21529.02	% SZS status GaveUp for HL408798+5.p
161989.09/21529.02	eprover: CPU time limit exceeded, terminating
161989.09/21529.02	% SZS status Ended for HL408798+5.p
161992.64/21529.48	% SZS status Started for HL408809+4.p
161992.64/21529.48	% SZS status GaveUp for HL408809+4.p
161992.64/21529.48	eprover: CPU time limit exceeded, terminating
161992.64/21529.48	% SZS status Ended for HL408809+4.p
162001.30/21530.59	% SZS status Started for HL408805+5.p
162001.30/21530.59	% SZS status GaveUp for HL408805+5.p
162001.30/21530.59	eprover: CPU time limit exceeded, terminating
162001.30/21530.59	% SZS status Ended for HL408805+5.p
162017.48/21532.62	% SZS status Started for HL408810+4.p
162017.48/21532.62	% SZS status GaveUp for HL408810+4.p
162017.48/21532.62	eprover: CPU time limit exceeded, terminating
162017.48/21532.62	% SZS status Ended for HL408810+4.p
162018.12/21532.69	% SZS status Started for HL408799+5.p
162018.12/21532.69	% SZS status GaveUp for HL408799+5.p
162018.12/21532.69	eprover: CPU time limit exceeded, terminating
162018.12/21532.69	% SZS status Ended for HL408799+5.p
162032.52/21534.53	% SZS status Started for HL408803+5.p
162032.52/21534.53	% SZS status GaveUp for HL408803+5.p
162032.52/21534.53	eprover: CPU time limit exceeded, terminating
162032.52/21534.53	% SZS status Ended for HL408803+5.p
162041.38/21535.65	% SZS status Started for HL408811+4.p
162041.38/21535.65	% SZS status GaveUp for HL408811+4.p
162041.38/21535.65	eprover: CPU time limit exceeded, terminating
162041.38/21535.65	% SZS status Ended for HL408811+4.p
162056.53/21537.57	% SZS status Started for HL408812+4.p
162056.53/21537.57	% SZS status GaveUp for HL408812+4.p
162056.53/21537.57	eprover: CPU time limit exceeded, terminating
162056.53/21537.57	% SZS status Ended for HL408812+4.p
162071.02/21539.32	% SZS status Started for HL408809+5.p
162071.02/21539.32	% SZS status GaveUp for HL408809+5.p
162071.02/21539.32	eprover: CPU time limit exceeded, terminating
162071.02/21539.32	% SZS status Ended for HL408809+5.p
162078.39/21540.27	% SZS status Started for HL408806+5.p
162078.39/21540.27	% SZS status GaveUp for HL408806+5.p
162078.39/21540.27	eprover: CPU time limit exceeded, terminating
162078.39/21540.27	% SZS status Ended for HL408806+5.p
162080.84/21540.60	% SZS status Started for HL408813+4.p
162080.84/21540.60	% SZS status GaveUp for HL408813+4.p
162080.84/21540.60	eprover: CPU time limit exceeded, terminating
162080.84/21540.60	% SZS status Ended for HL408813+4.p
162102.22/21543.31	% SZS status Started for HL408814+4.p
162102.22/21543.31	% SZS status GaveUp for HL408814+4.p
162102.22/21543.31	eprover: CPU time limit exceeded, terminating
162102.22/21543.31	% SZS status Ended for HL408814+4.p
162104.36/21543.58	% SZS status Started for HL408807+5.p
162104.36/21543.58	% SZS status GaveUp for HL408807+5.p
162104.36/21543.58	eprover: CPU time limit exceeded, terminating
162104.36/21543.58	% SZS status Ended for HL408807+5.p
162126.48/21546.38	% SZS status Started for HL408815+4.p
162126.48/21546.38	% SZS status GaveUp for HL408815+4.p
162126.48/21546.38	eprover: CPU time limit exceeded, terminating
162126.48/21546.38	% SZS status Ended for HL408815+4.p
162135.50/21547.16	% SZS status Started for HL408808+5.p
162135.50/21547.16	% SZS status GaveUp for HL408808+5.p
162135.50/21547.16	eprover: CPU time limit exceeded, terminating
162135.50/21547.16	% SZS status Ended for HL408808+5.p
162153.45/21549.49	% SZS status Started for HL408817+4.p
162153.45/21549.49	% SZS status GaveUp for HL408817+4.p
162153.45/21549.49	eprover: CPU time limit exceeded, terminating
162153.45/21549.49	% SZS status Ended for HL408817+4.p
162170.61/21551.65	% SZS status Started for HL408813+5.p
162170.61/21551.65	% SZS status GaveUp for HL408813+5.p
162170.61/21551.65	eprover: CPU time limit exceeded, terminating
162170.61/21551.65	% SZS status Ended for HL408813+5.p
162179.44/21552.70	% SZS status Started for HL408818+4.p
162179.44/21552.70	% SZS status GaveUp for HL408818+4.p
162179.44/21552.70	eprover: CPU time limit exceeded, terminating
162179.44/21552.70	% SZS status Ended for HL408818+4.p
162202.61/21555.73	% SZS status Started for HL408819+4.p
162202.61/21555.73	% SZS status GaveUp for HL408819+4.p
162202.61/21555.73	eprover: CPU time limit exceeded, terminating
162202.61/21555.73	% SZS status Ended for HL408819+4.p
162212.50/21556.91	% SZS status Started for HL408810+5.p
162212.50/21556.91	% SZS status GaveUp for HL408810+5.p
162212.50/21556.91	eprover: CPU time limit exceeded, terminating
162212.50/21556.91	% SZS status Ended for HL408810+5.p
162228.41/21558.87	% SZS status Started for HL408811+5.p
162228.41/21558.87	% SZS status GaveUp for HL408811+5.p
162228.41/21558.87	eprover: CPU time limit exceeded, terminating
162228.41/21558.87	% SZS status Ended for HL408811+5.p
162236.77/21559.95	% SZS status Started for HL408820+4.p
162236.77/21559.95	% SZS status GaveUp for HL408820+4.p
162236.77/21559.95	eprover: CPU time limit exceeded, terminating
162236.77/21559.95	% SZS status Ended for HL408820+4.p
162252.33/21561.90	% SZS status Started for HL408812+5.p
162252.33/21561.90	% SZS status GaveUp for HL408812+5.p
162252.33/21561.90	eprover: CPU time limit exceeded, terminating
162252.33/21561.90	% SZS status Ended for HL408812+5.p
162260.66/21562.99	% SZS status Started for HL408821+4.p
162260.66/21562.99	% SZS status GaveUp for HL408821+4.p
162260.66/21562.99	eprover: CPU time limit exceeded, terminating
162260.66/21562.99	% SZS status Ended for HL408821+4.p
162285.34/21566.12	% SZS status Started for HL408822+4.p
162285.34/21566.12	% SZS status GaveUp for HL408822+4.p
162285.34/21566.12	eprover: CPU time limit exceeded, terminating
162285.34/21566.12	% SZS status Ended for HL408822+4.p
162294.38/21567.23	% SZS status Started for HL408814+5.p
162294.38/21567.23	% SZS status GaveUp for HL408814+5.p
162294.38/21567.23	eprover: CPU time limit exceeded, terminating
162294.38/21567.23	% SZS status Ended for HL408814+5.p
162317.08/21570.08	% SZS status Started for HL408815+5.p
162317.08/21570.08	% SZS status GaveUp for HL408815+5.p
162317.08/21570.08	eprover: CPU time limit exceeded, terminating
162317.08/21570.08	% SZS status Ended for HL408815+5.p
162318.16/21570.30	% SZS status Started for HL408823+4.p
162318.16/21570.30	% SZS status GaveUp for HL408823+4.p
162318.16/21570.30	eprover: CPU time limit exceeded, terminating
162318.16/21570.30	% SZS status Ended for HL408823+4.p
162343.09/21573.33	% SZS status Started for HL408824+4.p
162343.09/21573.33	% SZS status GaveUp for HL408824+4.p
162343.09/21573.33	eprover: CPU time limit exceeded, terminating
162343.09/21573.33	% SZS status Ended for HL408824+4.p
162344.41/21573.51	% SZS status Started for HL408817+5.p
162344.41/21573.51	% SZS status GaveUp for HL408817+5.p
162344.41/21573.51	eprover: CPU time limit exceeded, terminating
162344.41/21573.51	% SZS status Ended for HL408817+5.p
162368.73/21576.61	% SZS status Started for HL408825+4.p
162368.73/21576.61	% SZS status GaveUp for HL408825+4.p
162368.73/21576.61	eprover: CPU time limit exceeded, terminating
162368.73/21576.61	% SZS status Ended for HL408825+4.p
162379.70/21577.94	% SZS status Started for HL408818+5.p
162379.70/21577.94	% SZS status GaveUp for HL408818+5.p
162379.70/21577.94	eprover: CPU time limit exceeded, terminating
162379.70/21577.94	% SZS status Ended for HL408818+5.p
162404.08/21581.01	% SZS status Started for HL408826+4.p
162404.08/21581.01	% SZS status GaveUp for HL408826+4.p
162404.08/21581.01	eprover: CPU time limit exceeded, terminating
162404.08/21581.01	% SZS status Ended for HL408826+4.p
162409.47/21581.83	% SZS status Started for HL408819+5.p
162409.47/21581.83	% SZS status GaveUp for HL408819+5.p
162409.47/21581.83	eprover: CPU time limit exceeded, terminating
162409.47/21581.83	% SZS status Ended for HL408819+5.p
162434.62/21584.86	% SZS status Started for HL408827+4.p
162434.62/21584.86	% SZS status GaveUp for HL408827+4.p
162434.62/21584.86	eprover: CPU time limit exceeded, terminating
162434.62/21584.86	% SZS status Ended for HL408827+4.p
162436.11/21585.08	% SZS status Started for HL408820+5.p
162436.11/21585.08	% SZS status GaveUp for HL408820+5.p
162436.11/21585.08	eprover: CPU time limit exceeded, terminating
162436.11/21585.08	% SZS status Ended for HL408820+5.p
162452.78/21587.20	% SZS status Started for HL408825+5.p
162452.78/21587.20	% SZS status GaveUp for HL408825+5.p
162452.78/21587.20	eprover: CPU time limit exceeded, terminating
162452.78/21587.20	% SZS status Ended for HL408825+5.p
162460.27/21588.11	% SZS status Started for HL408821+5.p
162460.27/21588.11	% SZS status GaveUp for HL408821+5.p
162460.27/21588.11	eprover: CPU time limit exceeded, terminating
162460.27/21588.11	% SZS status Ended for HL408821+5.p
162460.27/21588.11	% SZS status Started for HL408829+4.p
162460.27/21588.11	% SZS status GaveUp for HL408829+4.p
162460.27/21588.11	eprover: CPU time limit exceeded, terminating
162460.27/21588.11	% SZS status Ended for HL408829+4.p
162483.81/21591.13	% SZS status Started for HL408830+4.p
162483.81/21591.13	% SZS status GaveUp for HL408830+4.p
162483.81/21591.13	eprover: CPU time limit exceeded, terminating
162483.81/21591.13	% SZS status Ended for HL408830+4.p
162485.12/21591.31	% SZS status Started for HL408826+5.p
162485.12/21591.31	% SZS status GaveUp for HL408826+5.p
162485.12/21591.31	eprover: CPU time limit exceeded, terminating
162485.12/21591.31	% SZS status Ended for HL408826+5.p
162493.67/21592.35	% SZS status Started for HL408822+5.p
162493.67/21592.35	% SZS status GaveUp for HL408822+5.p
162493.67/21592.35	eprover: CPU time limit exceeded, terminating
162493.67/21592.35	% SZS status Ended for HL408822+5.p
162508.34/21594.16	% SZS status Started for HL408831+4.p
162508.34/21594.16	% SZS status GaveUp for HL408831+4.p
162508.34/21594.16	eprover: CPU time limit exceeded, terminating
162508.34/21594.16	% SZS status Ended for HL408831+4.p
162515.06/21595.04	% SZS status Started for HL408827+5.p
162515.06/21595.04	% SZS status GaveUp for HL408827+5.p
162515.06/21595.04	eprover: CPU time limit exceeded, terminating
162515.06/21595.04	% SZS status Ended for HL408827+5.p
162517.92/21595.38	% SZS status Started for HL408832+4.p
162517.92/21595.38	% SZS status GaveUp for HL408832+4.p
162517.92/21595.38	eprover: CPU time limit exceeded, terminating
162517.92/21595.38	% SZS status Ended for HL408832+4.p
162526.22/21596.47	% SZS status Started for HL408823+5.p
162526.22/21596.47	% SZS status GaveUp for HL408823+5.p
162526.22/21596.47	eprover: CPU time limit exceeded, terminating
162526.22/21596.47	% SZS status Ended for HL408823+5.p
162539.83/21598.10	% SZS status Started for HL408833+4.p
162539.83/21598.10	% SZS status GaveUp for HL408833+4.p
162539.83/21598.10	eprover: CPU time limit exceeded, terminating
162539.83/21598.10	% SZS status Ended for HL408833+4.p
162550.75/21599.52	% SZS status Started for HL408834+4.p
162550.75/21599.52	% SZS status GaveUp for HL408834+4.p
162550.75/21599.52	eprover: CPU time limit exceeded, terminating
162550.75/21599.52	% SZS status Ended for HL408834+4.p
162551.34/21599.58	% SZS status Started for HL408824+5.p
162551.34/21599.58	% SZS status GaveUp for HL408824+5.p
162551.34/21599.58	eprover: CPU time limit exceeded, terminating
162551.34/21599.58	% SZS status Ended for HL408824+5.p
162566.22/21601.47	% SZS status Started for HL408831+5.p
162566.22/21601.47	% SZS status GaveUp for HL408831+5.p
162566.22/21601.47	eprover: CPU time limit exceeded, terminating
162566.22/21601.47	% SZS status Ended for HL408831+5.p
162574.77/21602.56	% SZS status Started for HL408835+4.p
162574.77/21602.56	% SZS status GaveUp for HL408835+4.p
162574.77/21602.56	eprover: CPU time limit exceeded, terminating
162574.77/21602.56	% SZS status Ended for HL408835+4.p
162589.55/21604.37	% SZS status Started for HL408832+5.p
162589.55/21604.37	% SZS status GaveUp for HL408832+5.p
162589.55/21604.37	eprover: CPU time limit exceeded, terminating
162589.55/21604.37	% SZS status Ended for HL408832+5.p
162590.34/21604.50	% SZS status Started for HL408836+4.p
162590.34/21604.50	% SZS status GaveUp for HL408836+4.p
162590.34/21604.50	eprover: CPU time limit exceeded, terminating
162590.34/21604.50	% SZS status Ended for HL408836+4.p
162614.36/21607.48	% SZS status Started for HL408837+4.p
162614.36/21607.48	% SZS status GaveUp for HL408837+4.p
162614.36/21607.48	eprover: CPU time limit exceeded, terminating
162614.36/21607.48	% SZS status Ended for HL408837+4.p
162638.31/21610.51	% SZS status Started for HL408838+4.p
162638.31/21610.51	% SZS status GaveUp for HL408838+4.p
162638.31/21610.51	eprover: CPU time limit exceeded, terminating
162638.31/21610.51	% SZS status Ended for HL408838+4.p
162662.69/21613.56	% SZS status Started for HL408829+5.p
162662.69/21613.56	% SZS status GaveUp for HL408829+5.p
162662.69/21613.56	eprover: CPU time limit exceeded, terminating
162662.69/21613.56	% SZS status Ended for HL408829+5.p
162668.59/21614.31	% SZS status Started for HL408830+5.p
162668.59/21614.31	% SZS status GaveUp for HL408830+5.p
162668.59/21614.31	eprover: CPU time limit exceeded, terminating
162668.59/21614.31	% SZS status Ended for HL408830+5.p
162686.81/21616.59	% SZS status Started for HL408839+4.p
162686.81/21616.59	% SZS status GaveUp for HL408839+4.p
162686.81/21616.59	eprover: CPU time limit exceeded, terminating
162686.81/21616.59	% SZS status Ended for HL408839+4.p
162710.45/21619.62	% SZS status Started for HL408840+4.p
162710.45/21619.62	% SZS status GaveUp for HL408840+4.p
162710.45/21619.62	eprover: CPU time limit exceeded, terminating
162710.45/21619.62	% SZS status Ended for HL408840+4.p
162726.95/21621.66	% SZS status Started for HL408833+5.p
162726.95/21621.66	% SZS status GaveUp for HL408833+5.p
162726.95/21621.66	eprover: CPU time limit exceeded, terminating
162726.95/21621.66	% SZS status Ended for HL408833+5.p
162747.88/21624.28	% SZS status Started for HL408834+5.p
162747.88/21624.28	% SZS status GaveUp for HL408834+5.p
162747.88/21624.28	eprover: CPU time limit exceeded, terminating
162747.88/21624.28	% SZS status Ended for HL408834+5.p
162751.66/21624.79	% SZS status Started for HL408841+4.p
162751.66/21624.79	% SZS status GaveUp for HL408841+4.p
162751.66/21624.79	eprover: CPU time limit exceeded, terminating
162751.66/21624.79	% SZS status Ended for HL408841+4.p
162760.72/21625.94	% SZS status Started for HL408835+5.p
162760.72/21625.94	% SZS status GaveUp for HL408835+5.p
162760.72/21625.94	eprover: CPU time limit exceeded, terminating
162760.72/21625.94	% SZS status Ended for HL408835+5.p
162775.80/21627.86	% SZS status Started for HL408842+4.p
162775.80/21627.86	% SZS status GaveUp for HL408842+4.p
162775.80/21627.86	eprover: CPU time limit exceeded, terminating
162775.80/21627.86	% SZS status Ended for HL408842+4.p
162783.41/21628.78	% SZS status Started for HL408836+5.p
162783.41/21628.78	% SZS status GaveUp for HL408836+5.p
162783.41/21628.78	eprover: CPU time limit exceeded, terminating
162783.41/21628.78	% SZS status Ended for HL408836+5.p
162797.59/21630.62	% SZS status Started for HL408837+5.p
162797.59/21630.62	% SZS status GaveUp for HL408837+5.p
162797.59/21630.62	eprover: CPU time limit exceeded, terminating
162797.59/21630.62	% SZS status Ended for HL408837+5.p
162800.05/21630.91	% SZS status Started for HL408843+4.p
162800.05/21630.91	% SZS status GaveUp for HL408843+4.p
162800.05/21630.91	eprover: CPU time limit exceeded, terminating
162800.05/21630.91	% SZS status Ended for HL408843+4.p
162822.28/21633.65	% SZS status Started for HL408845+4.p
162822.28/21633.65	% SZS status GaveUp for HL408845+4.p
162822.28/21633.65	eprover: CPU time limit exceeded, terminating
162822.28/21633.65	% SZS status Ended for HL408845+4.p
162837.67/21635.79	% SZS status Started for HL408840+5.p
162837.67/21635.79	% SZS status GaveUp for HL408840+5.p
162837.67/21635.79	eprover: CPU time limit exceeded, terminating
162837.67/21635.79	% SZS status Ended for HL408840+5.p
162843.06/21636.29	% SZS status Started for HL408842+5.p
162843.06/21636.29	% SZS status GaveUp for HL408842+5.p
162843.06/21636.29	eprover: CPU time limit exceeded, terminating
162843.06/21636.29	% SZS status Ended for HL408842+5.p
162846.92/21636.74	% SZS status Started for HL408846+4.p
162846.92/21636.74	% SZS status GaveUp for HL408846+4.p
162846.92/21636.74	eprover: CPU time limit exceeded, terminating
162846.92/21636.74	% SZS status Ended for HL408846+4.p
162848.42/21636.96	% SZS status Started for HL408838+5.p
162848.42/21636.96	% SZS status GaveUp for HL408838+5.p
162848.42/21636.96	eprover: CPU time limit exceeded, terminating
162848.42/21636.96	% SZS status Ended for HL408838+5.p
162867.12/21639.34	% SZS status Started for HL408851+4.p
162867.12/21639.34	% SZS status GaveUp for HL408851+4.p
162867.12/21639.34	eprover: CPU time limit exceeded, terminating
162867.12/21639.34	% SZS status Ended for HL408851+4.p
162872.44/21639.99	% SZS status Started for HL408852+4.p
162872.44/21639.99	% SZS status GaveUp for HL408852+4.p
162872.44/21639.99	eprover: CPU time limit exceeded, terminating
162872.44/21639.99	% SZS status Ended for HL408852+4.p
162876.25/21640.50	% SZS status Started for HL408839+5.p
162876.25/21640.50	% SZS status GaveUp for HL408839+5.p
162876.25/21640.50	eprover: CPU time limit exceeded, terminating
162876.25/21640.50	% SZS status Ended for HL408839+5.p
162883.44/21641.43	% SZS status Started for HL408845+5.p
162883.44/21641.43	% SZS status GaveUp for HL408845+5.p
162883.44/21641.43	eprover: CPU time limit exceeded, terminating
162883.44/21641.43	% SZS status Ended for HL408845+5.p
162897.16/21643.08	% SZS status Started for HL408853+4.p
162897.16/21643.08	% SZS status GaveUp for HL408853+4.p
162897.16/21643.08	eprover: CPU time limit exceeded, terminating
162897.16/21643.08	% SZS status Ended for HL408853+4.p
162907.80/21644.47	% SZS status Started for HL408854+4.p
162907.80/21644.47	% SZS status GaveUp for HL408854+4.p
162907.80/21644.47	eprover: CPU time limit exceeded, terminating
162907.80/21644.47	% SZS status Ended for HL408854+4.p
162929.31/21647.19	% SZS status Started for HL408851+5.p
162929.31/21647.19	% SZS status GaveUp for HL408851+5.p
162929.31/21647.19	eprover: CPU time limit exceeded, terminating
162929.31/21647.19	% SZS status Ended for HL408851+5.p
162931.52/21647.52	% SZS status Started for HL408856+4.p
162931.52/21647.52	% SZS status GaveUp for HL408856+4.p
162931.52/21647.52	eprover: CPU time limit exceeded, terminating
162931.52/21647.52	% SZS status Ended for HL408856+4.p
162954.98/21650.39	% SZS status Started for HL408841+5.p
162954.98/21650.39	% SZS status GaveUp for HL408841+5.p
162954.98/21650.39	eprover: CPU time limit exceeded, terminating
162954.98/21650.39	% SZS status Ended for HL408841+5.p
162956.12/21650.55	% SZS status Started for HL408857+4.p
162956.12/21650.55	% SZS status GaveUp for HL408857+4.p
162956.12/21650.55	eprover: CPU time limit exceeded, terminating
162956.12/21650.55	% SZS status Ended for HL408857+4.p
162978.31/21653.38	% SZS status Started for HL408854+5.p
162978.31/21653.38	% SZS status GaveUp for HL408854+5.p
162978.31/21653.38	eprover: CPU time limit exceeded, terminating
162978.31/21653.38	% SZS status Ended for HL408854+5.p
162980.38/21653.59	% SZS status Started for HL408858+4.p
162980.38/21653.59	% SZS status GaveUp for HL408858+4.p
162980.38/21653.59	eprover: CPU time limit exceeded, terminating
162980.38/21653.59	% SZS status Ended for HL408858+4.p
162993.64/21655.35	% SZS status Started for HL408843+5.p
162993.64/21655.35	% SZS status GaveUp for HL408843+5.p
162993.64/21655.35	eprover: CPU time limit exceeded, terminating
162993.64/21655.35	% SZS status Ended for HL408843+5.p
163004.98/21656.68	% SZS status Started for HL408859+4.p
163004.98/21656.68	% SZS status GaveUp for HL408859+4.p
163004.98/21656.68	eprover: CPU time limit exceeded, terminating
163004.98/21656.68	% SZS status Ended for HL408859+4.p
163028.48/21659.70	% SZS status Started for HL408860+4.p
163028.48/21659.70	% SZS status GaveUp for HL408860+4.p
163028.48/21659.70	eprover: CPU time limit exceeded, terminating
163028.48/21659.70	% SZS status Ended for HL408860+4.p
163047.72/21662.08	% SZS status Started for HL408846+5.p
163047.72/21662.08	% SZS status GaveUp for HL408846+5.p
163047.72/21662.08	eprover: CPU time limit exceeded, terminating
163047.72/21662.08	% SZS status Ended for HL408846+5.p
163059.56/21663.63	% SZS status Started for HL408858+5.p
163059.56/21663.63	% SZS status GaveUp for HL408858+5.p
163059.56/21663.63	eprover: CPU time limit exceeded, terminating
163059.56/21663.63	% SZS status Ended for HL408858+5.p
163071.55/21665.12	% SZS status Started for HL408861+4.p
163071.55/21665.12	% SZS status GaveUp for HL408861+4.p
163071.55/21665.12	eprover: CPU time limit exceeded, terminating
163071.55/21665.12	% SZS status Ended for HL408861+4.p
163076.03/21665.66	% SZS status Started for HL408852+5.p
163076.03/21665.66	% SZS status GaveUp for HL408852+5.p
163076.03/21665.66	eprover: CPU time limit exceeded, terminating
163076.03/21665.66	% SZS status Ended for HL408852+5.p
163085.44/21666.92	% SZS status Started for HL408853+5.p
163085.44/21666.92	% SZS status GaveUp for HL408853+5.p
163085.44/21666.92	eprover: CPU time limit exceeded, terminating
163085.44/21666.92	% SZS status Ended for HL408853+5.p
163096.62/21668.26	% SZS status Started for HL408862+4.p
163096.62/21668.26	% SZS status GaveUp for HL408862+4.p
163096.62/21668.26	eprover: CPU time limit exceeded, terminating
163096.62/21668.26	% SZS status Ended for HL408862+4.p
163110.66/21670.03	% SZS status Started for HL408863+4.p
163110.66/21670.03	% SZS status GaveUp for HL408863+4.p
163110.66/21670.03	eprover: CPU time limit exceeded, terminating
163110.66/21670.03	% SZS status Ended for HL408863+4.p
163134.78/21673.11	% SZS status Started for HL408864+4.p
163134.78/21673.11	% SZS status GaveUp for HL408864+4.p
163134.78/21673.11	eprover: CPU time limit exceeded, terminating
163134.78/21673.11	% SZS status Ended for HL408864+4.p
163138.11/21673.56	% SZS status Started for HL408856+5.p
163138.11/21673.56	% SZS status GaveUp for HL408856+5.p
163138.11/21673.56	eprover: CPU time limit exceeded, terminating
163138.11/21673.56	% SZS status Ended for HL408856+5.p
163163.02/21676.61	% SZS status Started for HL408865+4.p
163163.02/21676.61	% SZS status GaveUp for HL408865+4.p
163163.02/21676.61	eprover: CPU time limit exceeded, terminating
163163.02/21676.61	% SZS status Ended for HL408865+4.p
163163.36/21676.70	% SZS status Started for HL408857+5.p
163163.36/21676.70	% SZS status GaveUp for HL408857+5.p
163163.36/21676.70	eprover: CPU time limit exceeded, terminating
163163.36/21676.70	% SZS status Ended for HL408857+5.p
163187.56/21679.78	% SZS status Started for HL408866+4.p
163187.56/21679.78	% SZS status GaveUp for HL408866+4.p
163187.56/21679.78	eprover: CPU time limit exceeded, terminating
163187.56/21679.78	% SZS status Ended for HL408866+4.p
163203.30/21681.73	% SZS status Started for HL408859+5.p
163203.30/21681.73	% SZS status GaveUp for HL408859+5.p
163203.30/21681.73	eprover: CPU time limit exceeded, terminating
163203.30/21681.73	% SZS status Ended for HL408859+5.p
163228.22/21684.89	% SZS status Started for HL408867+4.p
163228.22/21684.89	% SZS status GaveUp for HL408867+4.p
163228.22/21684.89	eprover: CPU time limit exceeded, terminating
163228.22/21684.89	% SZS status Ended for HL408867+4.p
163237.69/21686.02	% SZS status Started for HL408860+5.p
163237.69/21686.02	% SZS status GaveUp for HL408860+5.p
163237.69/21686.02	eprover: CPU time limit exceeded, terminating
163237.69/21686.02	% SZS status Ended for HL408860+5.p
163262.05/21689.14	% SZS status Started for HL408868+4.p
163262.05/21689.14	% SZS status GaveUp for HL408868+4.p
163262.05/21689.14	eprover: CPU time limit exceeded, terminating
163262.05/21689.14	% SZS status Ended for HL408868+4.p
163267.33/21689.77	% SZS status Started for HL408861+5.p
163267.33/21689.77	% SZS status GaveUp for HL408861+5.p
163267.33/21689.77	eprover: CPU time limit exceeded, terminating
163267.33/21689.77	% SZS status Ended for HL408861+5.p
163282.30/21691.74	% SZS status Started for HL408862+5.p
163282.30/21691.74	% SZS status GaveUp for HL408862+5.p
163282.30/21691.74	eprover: CPU time limit exceeded, terminating
163282.30/21691.74	% SZS status Ended for HL408862+5.p
163291.78/21692.85	% SZS status Started for HL408869+4.p
163291.78/21692.85	% SZS status GaveUp for HL408869+4.p
163291.78/21692.85	eprover: CPU time limit exceeded, terminating
163291.78/21692.85	% SZS status Ended for HL408869+4.p
163305.00/21694.60	% SZS status Started for HL408863+5.p
163305.00/21694.60	% SZS status GaveUp for HL408863+5.p
163305.00/21694.60	eprover: CPU time limit exceeded, terminating
163305.00/21694.60	% SZS status Ended for HL408863+5.p
163315.70/21695.93	% SZS status Started for HL408870+4.p
163315.70/21695.93	% SZS status GaveUp for HL408870+4.p
163315.70/21695.93	eprover: CPU time limit exceeded, terminating
163315.70/21695.93	% SZS status Ended for HL408870+4.p
163340.36/21698.96	% SZS status Started for HL408871+4.p
163340.36/21698.96	% SZS status GaveUp for HL408871+4.p
163340.36/21698.96	eprover: CPU time limit exceeded, terminating
163340.36/21698.96	% SZS status Ended for HL408871+4.p
163346.78/21699.77	% SZS status Started for HL408864+5.p
163346.78/21699.77	% SZS status GaveUp for HL408864+5.p
163346.78/21699.77	eprover: CPU time limit exceeded, terminating
163346.78/21699.77	% SZS status Ended for HL408864+5.p
163370.89/21702.85	% SZS status Started for HL408872+4.p
163370.89/21702.85	% SZS status GaveUp for HL408872+4.p
163370.89/21702.85	eprover: CPU time limit exceeded, terminating
163370.89/21702.85	% SZS status Ended for HL408872+4.p
163371.55/21702.89	% SZS status Started for HL408865+5.p
163371.55/21702.89	% SZS status GaveUp for HL408865+5.p
163371.55/21702.89	eprover: CPU time limit exceeded, terminating
163371.55/21702.89	% SZS status Ended for HL408865+5.p
163386.41/21704.78	% SZS status Started for HL408870+5.p
163386.41/21704.78	% SZS status GaveUp for HL408870+5.p
163386.41/21704.78	eprover: CPU time limit exceeded, terminating
163386.41/21704.78	% SZS status Ended for HL408870+5.p
163395.75/21706.01	% SZS status Started for HL408866+5.p
163395.75/21706.01	% SZS status GaveUp for HL408866+5.p
163395.75/21706.01	eprover: CPU time limit exceeded, terminating
163395.75/21706.01	% SZS status Ended for HL408866+5.p
163395.75/21706.03	% SZS status Started for HL408873+4.p
163395.75/21706.03	% SZS status GaveUp for HL408873+4.p
163395.75/21706.03	eprover: CPU time limit exceeded, terminating
163395.75/21706.03	% SZS status Ended for HL408873+4.p
163420.70/21709.08	% SZS status Started for HL408874+4.p
163420.70/21709.08	% SZS status GaveUp for HL408874+4.p
163420.70/21709.08	eprover: CPU time limit exceeded, terminating
163420.70/21709.08	% SZS status Ended for HL408874+4.p
163436.08/21711.06	% SZS status Started for HL408867+5.p
163436.08/21711.06	% SZS status GaveUp for HL408867+5.p
163436.08/21711.06	eprover: CPU time limit exceeded, terminating
163436.08/21711.06	% SZS status Ended for HL408867+5.p
163445.58/21712.22	% SZS status Started for HL408875+4.p
163445.58/21712.22	% SZS status GaveUp for HL408875+4.p
163445.58/21712.22	eprover: CPU time limit exceeded, terminating
163445.58/21712.22	% SZS status Ended for HL408875+4.p
163468.66/21715.24	% SZS status Started for HL408868+5.p
163468.66/21715.24	% SZS status GaveUp for HL408868+5.p
163468.66/21715.24	eprover: CPU time limit exceeded, terminating
163468.66/21715.24	% SZS status Ended for HL408868+5.p
163469.84/21715.29	% SZS status Started for HL408877+4.p
163469.84/21715.29	% SZS status GaveUp for HL408877+4.p
163469.84/21715.29	eprover: CPU time limit exceeded, terminating
163469.84/21715.29	% SZS status Ended for HL408877+4.p
163479.34/21716.48	% SZS status Started for HL408874+5.p
163479.34/21716.48	% SZS status GaveUp for HL408874+5.p
163479.34/21716.48	eprover: CPU time limit exceeded, terminating
163479.34/21716.48	% SZS status Ended for HL408874+5.p
163490.33/21717.86	% SZS status Started for HL408869+5.p
163490.33/21717.86	% SZS status GaveUp for HL408869+5.p
163490.33/21717.86	eprover: CPU time limit exceeded, terminating
163490.33/21717.86	% SZS status Ended for HL408869+5.p
163493.52/21718.32	% SZS status Started for HL408878+4.p
163493.52/21718.32	% SZS status GaveUp for HL408878+4.p
163493.52/21718.32	eprover: CPU time limit exceeded, terminating
163493.52/21718.32	% SZS status Ended for HL408878+4.p
163514.58/21720.95	% SZS status Started for HL408879+4.p
163514.58/21720.95	% SZS status GaveUp for HL408879+4.p
163514.58/21720.95	eprover: CPU time limit exceeded, terminating
163514.58/21720.95	% SZS status Ended for HL408879+4.p
163539.30/21724.06	% SZS status Started for HL408880+4.p
163539.30/21724.06	% SZS status GaveUp for HL408880+4.p
163539.30/21724.06	eprover: CPU time limit exceeded, terminating
163539.30/21724.06	% SZS status Ended for HL408880+4.p
163548.36/21725.20	% SZS status Started for HL408871+5.p
163548.36/21725.20	% SZS status GaveUp for HL408871+5.p
163548.36/21725.20	eprover: CPU time limit exceeded, terminating
163548.36/21725.20	% SZS status Ended for HL408871+5.p
163572.27/21728.26	% SZS status Started for HL408882+4.p
163572.27/21728.26	% SZS status GaveUp for HL408882+4.p
163572.27/21728.26	eprover: CPU time limit exceeded, terminating
163572.27/21728.26	% SZS status Ended for HL408882+4.p
163581.77/21729.40	% SZS status Started for HL408872+5.p
163581.77/21729.40	% SZS status GaveUp for HL408872+5.p
163581.77/21729.40	eprover: CPU time limit exceeded, terminating
163581.77/21729.40	% SZS status Ended for HL408872+5.p
163594.89/21731.08	% SZS status Started for HL408873+5.p
163594.89/21731.08	% SZS status GaveUp for HL408873+5.p
163594.89/21731.08	eprover: CPU time limit exceeded, terminating
163594.89/21731.08	% SZS status Ended for HL408873+5.p
163605.91/21732.44	% SZS status Started for HL408883+4.p
163605.91/21732.44	% SZS status GaveUp for HL408883+4.p
163605.91/21732.44	eprover: CPU time limit exceeded, terminating
163605.91/21732.44	% SZS status Ended for HL408883+4.p
163621.05/21734.37	% SZS status Started for HL408880+5.p
163621.05/21734.37	% SZS status GaveUp for HL408880+5.p
163621.05/21734.37	eprover: CPU time limit exceeded, terminating
163621.05/21734.37	% SZS status Ended for HL408880+5.p
163629.67/21735.47	% SZS status Started for HL408884+4.p
163629.67/21735.47	% SZS status GaveUp for HL408884+4.p
163629.67/21735.47	eprover: CPU time limit exceeded, terminating
163629.67/21735.47	% SZS status Ended for HL408884+4.p
163644.02/21737.26	% SZS status Started for HL408875+5.p
163644.02/21737.26	% SZS status GaveUp for HL408875+5.p
163644.02/21737.26	eprover: CPU time limit exceeded, terminating
163644.02/21737.26	% SZS status Ended for HL408875+5.p
163653.78/21738.52	% SZS status Started for HL408885+4.p
163653.78/21738.52	% SZS status GaveUp for HL408885+4.p
163653.78/21738.52	eprover: CPU time limit exceeded, terminating
163653.78/21738.52	% SZS status Ended for HL408885+4.p
163676.42/21741.35	% SZS status Started for HL408877+5.p
163676.42/21741.35	% SZS status GaveUp for HL408877+5.p
163676.42/21741.35	eprover: CPU time limit exceeded, terminating
163676.42/21741.35	% SZS status Ended for HL408877+5.p
163677.88/21741.56	% SZS status Started for HL408886+4.p
163677.88/21741.56	% SZS status GaveUp for HL408886+4.p
163677.88/21741.56	eprover: CPU time limit exceeded, terminating
163677.88/21741.56	% SZS status Ended for HL408886+4.p
163686.31/21742.64	% SZS status Started for HL408878+5.p
163686.31/21742.64	% SZS status GaveUp for HL408878+5.p
163686.31/21742.64	eprover: CPU time limit exceeded, terminating
163686.31/21742.64	% SZS status Ended for HL408878+5.p
163702.83/21744.59	% SZS status Started for HL408887+4.p
163702.83/21744.59	% SZS status GaveUp for HL408887+4.p
163702.83/21744.59	eprover: CPU time limit exceeded, terminating
163702.83/21744.59	% SZS status Ended for HL408887+4.p
163703.02/21744.60	% SZS status Started for HL408879+5.p
163703.02/21744.60	% SZS status GaveUp for HL408879+5.p
163703.02/21744.60	eprover: CPU time limit exceeded, terminating
163703.02/21744.60	% SZS status Ended for HL408879+5.p
163706.92/21745.13	% SZS status Started for HL408884+5.p
163706.92/21745.13	% SZS status GaveUp for HL408884+5.p
163706.92/21745.13	eprover: CPU time limit exceeded, terminating
163706.92/21745.13	% SZS status Ended for HL408884+5.p
163727.09/21747.61	% SZS status Started for HL408888+4.p
163727.09/21747.61	% SZS status GaveUp for HL408888+4.p
163727.09/21747.61	eprover: CPU time limit exceeded, terminating
163727.09/21747.61	% SZS status Ended for HL408888+4.p
163730.02/21748.17	% SZS status Started for HL408889+4.p
163730.02/21748.17	% SZS status GaveUp for HL408889+4.p
163730.02/21748.17	eprover: CPU time limit exceeded, terminating
163730.02/21748.17	% SZS status Ended for HL408889+4.p
163755.14/21751.20	% SZS status Started for HL408890+4.p
163755.14/21751.20	% SZS status GaveUp for HL408890+4.p
163755.14/21751.20	eprover: CPU time limit exceeded, terminating
163755.14/21751.20	% SZS status Ended for HL408890+4.p
163768.31/21752.82	% SZS status Started for HL408887+5.p
163768.31/21752.82	% SZS status GaveUp for HL408887+5.p
163768.31/21752.82	eprover: CPU time limit exceeded, terminating
163768.31/21752.82	% SZS status Ended for HL408887+5.p
163781.34/21754.51	% SZS status Started for HL408882+5.p
163781.34/21754.51	% SZS status GaveUp for HL408882+5.p
163781.34/21754.51	eprover: CPU time limit exceeded, terminating
163781.34/21754.51	% SZS status Ended for HL408882+5.p
163792.39/21755.86	% SZS status Started for HL408892+4.p
163792.39/21755.86	% SZS status GaveUp for HL408892+4.p
163792.39/21755.86	eprover: CPU time limit exceeded, terminating
163792.39/21755.86	% SZS status Ended for HL408892+4.p
163805.20/21757.56	% SZS status Started for HL408883+5.p
163805.20/21757.56	% SZS status GaveUp for HL408883+5.p
163805.20/21757.56	eprover: CPU time limit exceeded, terminating
163805.20/21757.56	% SZS status Ended for HL408883+5.p
163816.56/21758.89	% SZS status Started for HL408893+4.p
163816.56/21758.89	% SZS status GaveUp for HL408893+4.p
163816.56/21758.89	eprover: CPU time limit exceeded, terminating
163816.56/21758.89	% SZS status Ended for HL408893+4.p
163840.78/21761.92	% SZS status Started for HL408894+4.p
163840.78/21761.92	% SZS status GaveUp for HL408894+4.p
163840.78/21761.92	eprover: CPU time limit exceeded, terminating
163840.78/21761.92	% SZS status Ended for HL408894+4.p
163842.67/21762.28	% SZS status Started for HL408890+5.p
163842.67/21762.28	% SZS status GaveUp for HL408890+5.p
163842.67/21762.28	eprover: CPU time limit exceeded, terminating
163842.67/21762.28	% SZS status Ended for HL408890+5.p
163852.58/21763.42	% SZS status Started for HL408885+5.p
163852.58/21763.42	% SZS status GaveUp for HL408885+5.p
163852.58/21763.42	eprover: CPU time limit exceeded, terminating
163852.58/21763.42	% SZS status Ended for HL408885+5.p
163866.08/21765.31	% SZS status Started for HL408895+4.p
163866.08/21765.31	% SZS status GaveUp for HL408895+4.p
163866.08/21765.31	eprover: CPU time limit exceeded, terminating
163866.08/21765.31	% SZS status Ended for HL408895+4.p
163869.42/21765.56	% SZS status Started for HL408892+5.p
163869.42/21765.56	% SZS status GaveUp for HL408892+5.p
163869.42/21765.56	eprover: CPU time limit exceeded, terminating
163869.42/21765.56	% SZS status Ended for HL408892+5.p
163884.75/21767.46	% SZS status Started for HL408886+5.p
163884.75/21767.46	% SZS status GaveUp for HL408886+5.p
163884.75/21767.46	eprover: CPU time limit exceeded, terminating
163884.75/21767.46	% SZS status Ended for HL408886+5.p
163890.73/21768.34	% SZS status Started for HL408896+4.p
163890.73/21768.34	% SZS status GaveUp for HL408896+4.p
163890.73/21768.34	eprover: CPU time limit exceeded, terminating
163890.73/21768.34	% SZS status Ended for HL408896+4.p
163898.02/21769.11	% SZS status Started for HL408893+5.p
163898.02/21769.11	% SZS status GaveUp for HL408893+5.p
163898.02/21769.11	eprover: CPU time limit exceeded, terminating
163898.02/21769.11	% SZS status Ended for HL408893+5.p
163908.80/21770.50	% SZS status Started for HL408897+4.p
163908.80/21770.50	% SZS status GaveUp for HL408897+4.p
163908.80/21770.50	eprover: CPU time limit exceeded, terminating
163908.80/21770.50	% SZS status Ended for HL408897+4.p
163913.58/21771.08	% SZS status Started for HL408888+5.p
163913.58/21771.08	% SZS status GaveUp for HL408888+5.p
163913.58/21771.08	eprover: CPU time limit exceeded, terminating
163913.58/21771.08	% SZS status Ended for HL408888+5.p
163922.00/21772.15	% SZS status Started for HL408898+4.p
163922.00/21772.15	% SZS status GaveUp for HL408898+4.p
163922.00/21772.15	eprover: CPU time limit exceeded, terminating
163922.00/21772.15	% SZS status Ended for HL408898+4.p
163928.08/21772.94	% SZS status Started for HL408894+5.p
163928.08/21772.94	% SZS status GaveUp for HL408894+5.p
163928.08/21772.94	eprover: CPU time limit exceeded, terminating
163928.08/21772.94	% SZS status Ended for HL408894+5.p
163933.89/21773.79	% SZS status Started for HL408889+5.p
163933.89/21773.79	% SZS status GaveUp for HL408889+5.p
163933.89/21773.79	eprover: CPU time limit exceeded, terminating
163933.89/21773.79	% SZS status Ended for HL408889+5.p
163937.59/21774.12	% SZS status Started for HL408899+4.p
163937.59/21774.12	% SZS status GaveUp for HL408899+4.p
163937.59/21774.12	eprover: CPU time limit exceeded, terminating
163937.59/21774.12	% SZS status Ended for HL408899+4.p
163939.72/21774.44	% SZS status Started for HL408895+5.p
163939.72/21774.44	% SZS status GaveUp for HL408895+5.p
163939.72/21774.44	eprover: CPU time limit exceeded, terminating
163939.72/21774.44	% SZS status Ended for HL408895+5.p
163952.25/21775.98	% SZS status Started for HL408900+4.p
163952.25/21775.98	% SZS status GaveUp for HL408900+4.p
163952.25/21775.98	eprover: CPU time limit exceeded, terminating
163952.25/21775.98	% SZS status Ended for HL408900+4.p
163957.28/21776.61	% SZS status Started for HL408896+5.p
163957.28/21776.61	% SZS status GaveUp for HL408896+5.p
163957.28/21776.61	eprover: CPU time limit exceeded, terminating
163957.28/21776.61	% SZS status Ended for HL408896+5.p
163961.61/21777.15	% SZS status Started for HL408902+4.p
163961.61/21777.15	% SZS status GaveUp for HL408902+4.p
163961.61/21777.15	eprover: CPU time limit exceeded, terminating
163961.61/21777.15	% SZS status Ended for HL408902+4.p
163976.66/21779.01	% SZS status Started for HL408903+4.p
163976.66/21779.01	% SZS status GaveUp for HL408903+4.p
163976.66/21779.01	eprover: CPU time limit exceeded, terminating
163976.66/21779.01	% SZS status Ended for HL408903+4.p
163982.16/21779.83	% SZS status Started for HL408897+5.p
163982.16/21779.83	% SZS status GaveUp for HL408897+5.p
163982.16/21779.83	eprover: CPU time limit exceeded, terminating
163982.16/21779.83	% SZS status Ended for HL408897+5.p
163985.27/21780.18	% SZS status Started for HL408904+4.p
163985.27/21780.18	% SZS status GaveUp for HL408904+4.p
163985.27/21780.18	eprover: CPU time limit exceeded, terminating
163985.27/21780.18	% SZS status Ended for HL408904+4.p
163996.45/21781.53	% SZS status Started for HL408898+5.p
163996.45/21781.53	% SZS status GaveUp for HL408898+5.p
163996.45/21781.53	eprover: CPU time limit exceeded, terminating
163996.45/21781.53	% SZS status Ended for HL408898+5.p
164007.33/21782.87	% SZS status Started for HL408905+4.p
164007.33/21782.87	% SZS status GaveUp for HL408905+4.p
164007.33/21782.87	eprover: CPU time limit exceeded, terminating
164007.33/21782.87	% SZS status Ended for HL408905+4.p
164008.50/21783.15	% SZS status Started for HL408899+5.p
164008.50/21783.15	% SZS status GaveUp for HL408899+5.p
164008.50/21783.15	eprover: CPU time limit exceeded, terminating
164008.50/21783.15	% SZS status Ended for HL408899+5.p
164020.31/21784.56	% SZS status Started for HL408906+4.p
164020.31/21784.56	% SZS status GaveUp for HL408906+4.p
164020.31/21784.56	eprover: CPU time limit exceeded, terminating
164020.31/21784.56	% SZS status Ended for HL408906+4.p
164021.92/21784.80	% SZS status Started for HL408900+5.p
164021.92/21784.80	% SZS status GaveUp for HL408900+5.p
164021.92/21784.80	eprover: CPU time limit exceeded, terminating
164021.92/21784.80	% SZS status Ended for HL408900+5.p
164027.55/21785.45	% SZS status Started for HL408902+5.p
164027.55/21785.45	% SZS status GaveUp for HL408902+5.p
164027.55/21785.45	eprover: CPU time limit exceeded, terminating
164027.55/21785.45	% SZS status Ended for HL408902+5.p
164034.67/21786.34	% SZS status Started for HL408907+4.p
164034.67/21786.34	% SZS status GaveUp for HL408907+4.p
164034.67/21786.34	eprover: CPU time limit exceeded, terminating
164034.67/21786.34	% SZS status Ended for HL408907+4.p
164044.30/21787.61	% SZS status Started for HL408903+5.p
164044.30/21787.61	% SZS status GaveUp for HL408903+5.p
164044.30/21787.61	eprover: CPU time limit exceeded, terminating
164044.30/21787.61	% SZS status Ended for HL408903+5.p
164046.20/21787.83	% SZS status Started for HL408908+4.p
164046.20/21787.83	% SZS status GaveUp for HL408908+4.p
164046.20/21787.83	eprover: CPU time limit exceeded, terminating
164046.20/21787.83	% SZS status Ended for HL408908+4.p
164058.94/21789.38	% SZS status Started for HL408909+4.p
164058.94/21789.38	% SZS status GaveUp for HL408909+4.p
164058.94/21789.38	eprover: CPU time limit exceeded, terminating
164058.94/21789.38	% SZS status Ended for HL408909+4.p
164063.67/21790.01	% SZS status Started for HL408904+5.p
164063.67/21790.01	% SZS status GaveUp for HL408904+5.p
164063.67/21790.01	eprover: CPU time limit exceeded, terminating
164063.67/21790.01	% SZS status Ended for HL408904+5.p
164069.69/21790.86	% SZS status Started for HL408910+4.p
164069.69/21790.86	% SZS status GaveUp for HL408910+4.p
164069.69/21790.86	eprover: CPU time limit exceeded, terminating
164069.69/21790.86	% SZS status Ended for HL408910+4.p
164075.70/21791.32	% SZS status Started for HL408905+5.p
164075.70/21791.32	% SZS status GaveUp for HL408905+5.p
164075.70/21791.32	eprover: CPU time limit exceeded, terminating
164075.70/21791.32	% SZS status Ended for HL408905+5.p
164089.34/21793.04	% SZS status Started for HL408911+4.p
164089.34/21793.04	% SZS status GaveUp for HL408911+4.p
164089.34/21793.04	eprover: CPU time limit exceeded, terminating
164089.34/21793.04	% SZS status Ended for HL408911+4.p
164096.31/21793.86	% SZS status Started for HL408906+5.p
164096.31/21793.86	% SZS status GaveUp for HL408906+5.p
164096.31/21793.86	eprover: CPU time limit exceeded, terminating
164096.31/21793.86	% SZS status Ended for HL408906+5.p
164098.72/21794.36	% SZS status Started for HL408912+4.p
164098.72/21794.36	% SZS status GaveUp for HL408912+4.p
164098.72/21794.36	eprover: CPU time limit exceeded, terminating
164098.72/21794.36	% SZS status Ended for HL408912+4.p
164109.52/21795.60	% SZS status Started for HL408907+5.p
164109.52/21795.60	% SZS status GaveUp for HL408907+5.p
164109.52/21795.60	eprover: CPU time limit exceeded, terminating
164109.52/21795.60	% SZS status Ended for HL408907+5.p
164120.23/21796.86	% SZS status Started for HL408908+5.p
164120.23/21796.86	% SZS status GaveUp for HL408908+5.p
164120.23/21796.86	eprover: CPU time limit exceeded, terminating
164120.23/21796.86	% SZS status Ended for HL408908+5.p
164120.23/21796.89	% SZS status Started for HL408913+4.p
164120.23/21796.89	% SZS status GaveUp for HL408913+4.p
164120.23/21796.89	eprover: CPU time limit exceeded, terminating
164120.23/21796.89	% SZS status Ended for HL408913+4.p
164134.39/21798.64	% SZS status Started for HL408909+5.p
164134.39/21798.64	% SZS status GaveUp for HL408909+5.p
164134.39/21798.64	eprover: CPU time limit exceeded, terminating
164134.39/21798.64	% SZS status Ended for HL408909+5.p
164135.34/21798.79	% SZS status Started for HL408914+4.p
164135.34/21798.79	% SZS status GaveUp for HL408914+4.p
164135.34/21798.79	eprover: CPU time limit exceeded, terminating
164135.34/21798.79	% SZS status Ended for HL408914+4.p
164144.14/21799.92	% SZS status Started for HL408915+4.p
164144.14/21799.92	% SZS status GaveUp for HL408915+4.p
164144.14/21799.92	eprover: CPU time limit exceeded, terminating
164144.14/21799.92	% SZS status Ended for HL408915+4.p
164147.97/21800.38	% SZS status Started for HL408910+5.p
164147.97/21800.38	% SZS status GaveUp for HL408910+5.p
164147.97/21800.38	eprover: CPU time limit exceeded, terminating
164147.97/21800.38	% SZS status Ended for HL408910+5.p
164159.48/21801.88	% SZS status Started for HL408917+4.p
164159.48/21801.88	% SZS status GaveUp for HL408917+4.p
164159.48/21801.88	eprover: CPU time limit exceeded, terminating
164159.48/21801.88	% SZS status Ended for HL408917+4.p
164159.48/21801.89	% SZS status Started for HL408911+5.p
164159.48/21801.89	% SZS status GaveUp for HL408911+5.p
164159.48/21801.89	eprover: CPU time limit exceeded, terminating
164159.48/21801.89	% SZS status Ended for HL408911+5.p
164173.75/21803.42	% SZS status Started for HL408918+4.p
164173.75/21803.42	% SZS status GaveUp for HL408918+4.p
164173.75/21803.42	eprover: CPU time limit exceeded, terminating
164173.75/21803.42	% SZS status Ended for HL408918+4.p
164179.44/21804.10	% SZS status Started for HL408912+5.p
164179.44/21804.10	% SZS status GaveUp for HL408912+5.p
164179.44/21804.10	eprover: CPU time limit exceeded, terminating
164179.44/21804.10	% SZS status Ended for HL408912+5.p
164186.02/21804.92	% SZS status Started for HL408919+4.p
164186.02/21804.92	% SZS status GaveUp for HL408919+4.p
164186.02/21804.92	eprover: CPU time limit exceeded, terminating
164186.02/21804.92	% SZS status Ended for HL408919+4.p
164190.03/21805.37	% SZS status Started for HL408913+5.p
164190.03/21805.37	% SZS status GaveUp for HL408913+5.p
164190.03/21805.37	eprover: CPU time limit exceeded, terminating
164190.03/21805.37	% SZS status Ended for HL408913+5.p
164203.95/21807.13	% SZS status Started for HL408921+4.p
164203.95/21807.13	% SZS status GaveUp for HL408921+4.p
164203.95/21807.13	eprover: CPU time limit exceeded, terminating
164203.95/21807.13	% SZS status Ended for HL408921+4.p
164213.17/21808.29	% SZS status Started for HL408914+5.p
164213.17/21808.29	% SZS status GaveUp for HL408914+5.p
164213.17/21808.29	eprover: CPU time limit exceeded, terminating
164213.17/21808.29	% SZS status Ended for HL408914+5.p
164213.89/21808.40	% SZS status Started for HL408922+4.p
164213.89/21808.40	% SZS status GaveUp for HL408922+4.p
164213.89/21808.40	eprover: CPU time limit exceeded, terminating
164213.89/21808.40	% SZS status Ended for HL408922+4.p
164223.45/21809.63	% SZS status Started for HL408915+5.p
164223.45/21809.63	% SZS status GaveUp for HL408915+5.p
164223.45/21809.63	eprover: CPU time limit exceeded, terminating
164223.45/21809.63	% SZS status Ended for HL408915+5.p
164233.38/21810.94	% SZS status Started for HL408917+5.p
164233.38/21810.94	% SZS status GaveUp for HL408917+5.p
164233.38/21810.94	eprover: CPU time limit exceeded, terminating
164233.38/21810.94	% SZS status Ended for HL408917+5.p
164236.78/21811.33	% SZS status Started for HL408923+4.p
164236.78/21811.33	% SZS status GaveUp for HL408923+4.p
164236.78/21811.33	eprover: CPU time limit exceeded, terminating
164236.78/21811.33	% SZS status Ended for HL408923+4.p
164248.52/21812.72	% SZS status Started for HL408924+4.p
164248.52/21812.72	% SZS status GaveUp for HL408924+4.p
164248.52/21812.72	eprover: CPU time limit exceeded, terminating
164248.52/21812.72	% SZS status Ended for HL408924+4.p
164249.20/21812.89	% SZS status Started for HL408918+5.p
164249.20/21812.89	% SZS status GaveUp for HL408918+5.p
164249.20/21812.89	eprover: CPU time limit exceeded, terminating
164249.20/21812.89	% SZS status Ended for HL408918+5.p
164261.05/21814.43	% SZS status Started for HL408928+4.p
164261.05/21814.43	% SZS status GaveUp for HL408928+4.p
164261.05/21814.43	eprover: CPU time limit exceeded, terminating
164261.05/21814.43	% SZS status Ended for HL408928+4.p
164262.67/21814.49	% SZS status Started for HL408919+5.p
164262.67/21814.49	% SZS status GaveUp for HL408919+5.p
164262.67/21814.49	eprover: CPU time limit exceeded, terminating
164262.67/21814.49	% SZS status Ended for HL408919+5.p
164273.59/21815.92	% SZS status Started for HL408929+4.p
164273.59/21815.92	% SZS status GaveUp for HL408929+4.p
164273.59/21815.92	eprover: CPU time limit exceeded, terminating
164273.59/21815.92	% SZS status Ended for HL408929+4.p
164273.59/21815.96	% SZS status Started for HL408921+5.p
164273.59/21815.96	% SZS status GaveUp for HL408921+5.p
164273.59/21815.96	eprover: CPU time limit exceeded, terminating
164273.59/21815.96	% SZS status Ended for HL408921+5.p
164286.09/21817.53	% SZS status Started for HL408930+4.p
164286.09/21817.53	% SZS status GaveUp for HL408930+4.p
164286.09/21817.53	eprover: CPU time limit exceeded, terminating
164286.09/21817.53	% SZS status Ended for HL408930+4.p
164291.09/21818.15	% SZS status Started for HL408922+5.p
164291.09/21818.15	% SZS status GaveUp for HL408922+5.p
164291.09/21818.15	eprover: CPU time limit exceeded, terminating
164291.09/21818.15	% SZS status Ended for HL408922+5.p
164297.84/21818.99	% SZS status Started for HL408931+4.p
164297.84/21818.99	% SZS status GaveUp for HL408931+4.p
164297.84/21818.99	eprover: CPU time limit exceeded, terminating
164297.84/21818.99	% SZS status Ended for HL408931+4.p
164301.66/21819.46	% SZS status Started for HL408923+5.p
164301.66/21819.46	% SZS status GaveUp for HL408923+5.p
164301.66/21819.46	eprover: CPU time limit exceeded, terminating
164301.66/21819.46	% SZS status Ended for HL408923+5.p
164314.84/21821.18	% SZS status Started for HL408932+4.p
164314.84/21821.18	% SZS status GaveUp for HL408932+4.p
164314.84/21821.18	eprover: CPU time limit exceeded, terminating
164314.84/21821.18	% SZS status Ended for HL408932+4.p
164320.66/21821.95	% SZS status Started for HL408924+5.p
164320.66/21821.95	% SZS status GaveUp for HL408924+5.p
164320.66/21821.95	eprover: CPU time limit exceeded, terminating
164320.66/21821.95	% SZS status Ended for HL408924+5.p
164326.14/21822.50	% SZS status Started for HL408933+4.p
164326.14/21822.50	% SZS status GaveUp for HL408933+4.p
164326.14/21822.50	eprover: CPU time limit exceeded, terminating
164326.14/21822.50	% SZS status Ended for HL408933+4.p
164342.67/21824.22	% SZS status Started for HL408928+5.p
164342.67/21824.22	% SZS status GaveUp for HL408928+5.p
164342.67/21824.22	eprover: CPU time limit exceeded, terminating
164342.67/21824.22	% SZS status Ended for HL408928+5.p
164348.62/21824.98	% SZS status Started for HL408934+4.p
164348.62/21824.98	% SZS status GaveUp for HL408934+4.p
164348.62/21824.98	eprover: CPU time limit exceeded, terminating
164348.62/21824.98	% SZS status Ended for HL408934+4.p
164351.92/21825.46	% SZS status Started for HL408929+5.p
164351.92/21825.46	% SZS status GaveUp for HL408929+5.p
164351.92/21825.46	eprover: CPU time limit exceeded, terminating
164351.92/21825.46	% SZS status Ended for HL408929+5.p
164363.33/21826.93	% SZS status Started for HL408930+5.p
164363.33/21826.93	% SZS status GaveUp for HL408930+5.p
164363.33/21826.93	eprover: CPU time limit exceeded, terminating
164363.33/21826.93	% SZS status Ended for HL408930+5.p
164367.12/21827.29	% SZS status Started for HL408935+4.p
164367.12/21827.29	% SZS status GaveUp for HL408935+4.p
164367.12/21827.29	eprover: CPU time limit exceeded, terminating
164367.12/21827.29	% SZS status Ended for HL408935+4.p
164376.91/21828.49	% SZS status Started for HL408936+4.p
164376.91/21828.49	% SZS status GaveUp for HL408936+4.p
164376.91/21828.49	eprover: CPU time limit exceeded, terminating
164376.91/21828.49	% SZS status Ended for HL408936+4.p
164377.11/21828.55	% SZS status Started for HL408931+5.p
164377.11/21828.55	% SZS status GaveUp for HL408931+5.p
164377.11/21828.55	eprover: CPU time limit exceeded, terminating
164377.11/21828.55	% SZS status Ended for HL408931+5.p
164388.97/21830.03	% SZS status Started for HL408932+5.p
164388.97/21830.03	% SZS status GaveUp for HL408932+5.p
164388.97/21830.03	eprover: CPU time limit exceeded, terminating
164388.97/21830.03	% SZS status Ended for HL408932+5.p
164390.88/21830.32	% SZS status Started for HL408937+4.p
164390.88/21830.32	% SZS status GaveUp for HL408937+4.p
164390.88/21830.32	eprover: CPU time limit exceeded, terminating
164390.88/21830.32	% SZS status Ended for HL408937+4.p
164400.64/21831.58	% SZS status Started for HL408938+4.p
164400.64/21831.58	% SZS status GaveUp for HL408938+4.p
164400.64/21831.58	eprover: CPU time limit exceeded, terminating
164400.64/21831.58	% SZS status Ended for HL408938+4.p
164406.02/21832.22	% SZS status Started for HL408933+5.p
164406.02/21832.22	% SZS status GaveUp for HL408933+5.p
164406.02/21832.22	eprover: CPU time limit exceeded, terminating
164406.02/21832.22	% SZS status Ended for HL408933+5.p
164414.84/21833.36	% SZS status Started for HL408939+4.p
164414.84/21833.36	% SZS status GaveUp for HL408939+4.p
164414.84/21833.36	eprover: CPU time limit exceeded, terminating
164414.84/21833.36	% SZS status Ended for HL408939+4.p
164416.92/21833.53	% SZS status Started for HL408934+5.p
164416.92/21833.53	% SZS status GaveUp for HL408934+5.p
164416.92/21833.53	eprover: CPU time limit exceeded, terminating
164416.92/21833.53	% SZS status Ended for HL408934+5.p
164430.22/21835.25	% SZS status Started for HL408940+4.p
164430.22/21835.25	% SZS status GaveUp for HL408940+4.p
164430.22/21835.25	eprover: CPU time limit exceeded, terminating
164430.22/21835.25	% SZS status Ended for HL408940+4.p
164439.56/21836.44	% SZS status Started for HL408935+5.p
164439.56/21836.44	% SZS status GaveUp for HL408935+5.p
164439.56/21836.44	eprover: CPU time limit exceeded, terminating
164439.56/21836.44	% SZS status Ended for HL408935+5.p
164440.34/21836.57	% SZS status Started for HL408941+4.p
164440.34/21836.57	% SZS status GaveUp for HL408941+4.p
164440.34/21836.57	eprover: CPU time limit exceeded, terminating
164440.34/21836.57	% SZS status Ended for HL408941+4.p
164453.02/21838.08	% SZS status Started for HL408936+5.p
164453.02/21838.08	% SZS status GaveUp for HL408936+5.p
164453.02/21838.08	eprover: CPU time limit exceeded, terminating
164453.02/21838.08	% SZS status Ended for HL408936+5.p
164463.08/21839.47	% SZS status Started for HL408942+4.p
164463.08/21839.47	% SZS status GaveUp for HL408942+4.p
164463.08/21839.47	eprover: CPU time limit exceeded, terminating
164463.08/21839.47	% SZS status Ended for HL408942+4.p
164463.08/21839.51	% SZS status Started for HL408937+5.p
164463.08/21839.51	% SZS status GaveUp for HL408937+5.p
164463.08/21839.51	eprover: CPU time limit exceeded, terminating
164463.08/21839.51	% SZS status Ended for HL408937+5.p
164475.42/21841.04	% SZS status Started for HL408938+5.p
164475.42/21841.04	% SZS status GaveUp for HL408938+5.p
164475.42/21841.04	eprover: CPU time limit exceeded, terminating
164475.42/21841.04	% SZS status Ended for HL408938+5.p
164475.92/21841.17	% SZS status Started for HL408943+4.p
164475.92/21841.17	% SZS status GaveUp for HL408943+4.p
164475.92/21841.17	eprover: CPU time limit exceeded, terminating
164475.92/21841.17	% SZS status Ended for HL408943+4.p
164488.36/21842.55	% SZS status Started for HL408944+4.p
164488.36/21842.55	% SZS status GaveUp for HL408944+4.p
164488.36/21842.55	eprover: CPU time limit exceeded, terminating
164488.36/21842.55	% SZS status Ended for HL408944+4.p
164488.81/21842.58	% SZS status Started for HL408939+5.p
164488.81/21842.58	% SZS status GaveUp for HL408939+5.p
164488.81/21842.58	eprover: CPU time limit exceeded, terminating
164488.81/21842.58	% SZS status Ended for HL408939+5.p
164501.06/21844.20	% SZS status Started for HL408945+4.p
164501.06/21844.20	% SZS status GaveUp for HL408945+4.p
164501.06/21844.20	eprover: CPU time limit exceeded, terminating
164501.06/21844.20	% SZS status Ended for HL408945+4.p
164504.72/21844.37	% SZS status Started for HL408940+5.p
164504.72/21844.37	% SZS status GaveUp for HL408940+5.p
164504.72/21844.37	eprover: CPU time limit exceeded, terminating
164504.72/21844.37	% SZS status Ended for HL408940+5.p
164515.36/21845.68	% SZS status Started for HL408946+4.p
164515.36/21845.68	% SZS status GaveUp for HL408946+4.p
164515.36/21845.68	eprover: CPU time limit exceeded, terminating
164515.36/21845.68	% SZS status Ended for HL408946+4.p
164520.39/21846.26	% SZS status Started for HL408941+5.p
164520.39/21846.26	% SZS status GaveUp for HL408941+5.p
164520.39/21846.26	eprover: CPU time limit exceeded, terminating
164520.39/21846.26	% SZS status Ended for HL408941+5.p
164529.12/21847.40	% SZS status Started for HL408948+4.p
164529.12/21847.40	% SZS status GaveUp for HL408948+4.p
164529.12/21847.40	eprover: CPU time limit exceeded, terminating
164529.12/21847.40	% SZS status Ended for HL408948+4.p
164530.30/21847.61	% SZS status Started for HL408942+5.p
164530.30/21847.61	% SZS status GaveUp for HL408942+5.p
164530.30/21847.61	eprover: CPU time limit exceeded, terminating
164530.30/21847.61	% SZS status Ended for HL408942+5.p
164544.36/21849.35	% SZS status Started for HL408949+4.p
164544.36/21849.35	% SZS status GaveUp for HL408949+4.p
164544.36/21849.35	eprover: CPU time limit exceeded, terminating
164544.36/21849.35	% SZS status Ended for HL408949+4.p
164554.12/21850.71	% SZS status Started for HL408951+4.p
164554.12/21850.71	% SZS status GaveUp for HL408951+4.p
164554.12/21850.71	eprover: CPU time limit exceeded, terminating
164554.12/21850.71	% SZS status Ended for HL408951+4.p
164557.86/21850.81	% SZS status Started for HL408943+5.p
164557.86/21850.81	% SZS status GaveUp for HL408943+5.p
164557.86/21850.81	eprover: CPU time limit exceeded, terminating
164557.86/21850.81	% SZS status Ended for HL408943+5.p
164567.73/21852.05	% SZS status Started for HL408944+5.p
164567.73/21852.05	% SZS status GaveUp for HL408944+5.p
164567.73/21852.05	eprover: CPU time limit exceeded, terminating
164567.73/21852.05	% SZS status Ended for HL408944+5.p
164579.28/21853.55	% SZS status Started for HL408945+5.p
164579.28/21853.55	% SZS status GaveUp for HL408945+5.p
164579.28/21853.55	eprover: CPU time limit exceeded, terminating
164579.28/21853.55	% SZS status Ended for HL408945+5.p
164580.38/21853.74	% SZS status Started for HL408953+4.p
164580.38/21853.74	% SZS status GaveUp for HL408953+4.p
164580.38/21853.74	eprover: CPU time limit exceeded, terminating
164580.38/21853.74	% SZS status Ended for HL408953+4.p
164590.78/21855.08	% SZS status Started for HL408954+4.p
164590.78/21855.08	% SZS status GaveUp for HL408954+4.p
164590.78/21855.08	eprover: CPU time limit exceeded, terminating
164590.78/21855.08	% SZS status Ended for HL408954+4.p
164593.06/21855.24	% SZS status Started for HL408946+5.p
164593.06/21855.24	% SZS status GaveUp for HL408946+5.p
164593.06/21855.24	eprover: CPU time limit exceeded, terminating
164593.06/21855.24	% SZS status Ended for HL408946+5.p
164604.16/21856.72	% SZS status Started for HL408948+5.p
164604.16/21856.72	% SZS status GaveUp for HL408948+5.p
164604.16/21856.72	eprover: CPU time limit exceeded, terminating
164604.16/21856.72	% SZS status Ended for HL408948+5.p
164604.47/21856.78	% SZS status Started for HL408955+4.p
164604.47/21856.78	% SZS status GaveUp for HL408955+4.p
164604.47/21856.78	eprover: CPU time limit exceeded, terminating
164604.47/21856.78	% SZS status Ended for HL408955+4.p
164616.89/21858.28	% SZS status Started for HL408956+4.p
164616.89/21858.28	% SZS status GaveUp for HL408956+4.p
164616.89/21858.28	eprover: CPU time limit exceeded, terminating
164616.89/21858.28	% SZS status Ended for HL408956+4.p
164618.25/21858.45	% SZS status Started for HL408949+5.p
164618.25/21858.45	% SZS status GaveUp for HL408949+5.p
164618.25/21858.45	eprover: CPU time limit exceeded, terminating
164618.25/21858.45	% SZS status Ended for HL408949+5.p
164629.05/21859.81	% SZS status Started for HL408957+4.p
164629.05/21859.81	% SZS status GaveUp for HL408957+4.p
164629.05/21859.81	eprover: CPU time limit exceeded, terminating
164629.05/21859.81	% SZS status Ended for HL408957+4.p
164637.97/21860.87	% SZS status Started for HL408951+5.p
164637.97/21860.87	% SZS status GaveUp for HL408951+5.p
164637.97/21860.87	eprover: CPU time limit exceeded, terminating
164637.97/21860.87	% SZS status Ended for HL408951+5.p
164642.78/21861.48	% SZS status Started for HL408958+4.p
164642.78/21861.48	% SZS status GaveUp for HL408958+4.p
164642.78/21861.48	eprover: CPU time limit exceeded, terminating
164642.78/21861.48	% SZS status Ended for HL408958+4.p
164644.81/21861.86	% SZS status Started for HL408953+5.p
164644.81/21861.86	% SZS status GaveUp for HL408953+5.p
164644.81/21861.86	eprover: CPU time limit exceeded, terminating
164644.81/21861.86	% SZS status Ended for HL408953+5.p
164661.36/21863.93	% SZS status Started for HL408960+4.p
164661.36/21863.93	% SZS status GaveUp for HL408960+4.p
164661.36/21863.93	eprover: CPU time limit exceeded, terminating
164661.36/21863.93	% SZS status Ended for HL408960+4.p
164666.83/21864.56	% SZS status Started for HL408954+5.p
164666.83/21864.56	% SZS status GaveUp for HL408954+5.p
164666.83/21864.56	eprover: CPU time limit exceeded, terminating
164666.83/21864.56	% SZS status Ended for HL408954+5.p
164670.19/21864.99	% SZS status Started for HL408961+4.p
164670.19/21864.99	% SZS status GaveUp for HL408961+4.p
164670.19/21864.99	eprover: CPU time limit exceeded, terminating
164670.19/21864.99	% SZS status Ended for HL408961+4.p
164678.94/21866.12	% SZS status Started for HL408955+5.p
164678.94/21866.12	% SZS status GaveUp for HL408955+5.p
164678.94/21866.12	eprover: CPU time limit exceeded, terminating
164678.94/21866.12	% SZS status Ended for HL408955+5.p
164691.45/21867.71	% SZS status Started for HL408962+4.p
164691.45/21867.71	% SZS status GaveUp for HL408962+4.p
164691.45/21867.71	eprover: CPU time limit exceeded, terminating
164691.45/21867.71	% SZS status Ended for HL408962+4.p
164691.45/21867.73	% SZS status Started for HL408956+5.p
164691.45/21867.73	% SZS status GaveUp for HL408956+5.p
164691.45/21867.73	eprover: CPU time limit exceeded, terminating
164691.45/21867.73	% SZS status Ended for HL408956+5.p
164703.28/21869.15	% SZS status Started for HL408963+4.p
164703.28/21869.15	% SZS status GaveUp for HL408963+4.p
164703.28/21869.15	eprover: CPU time limit exceeded, terminating
164703.28/21869.15	% SZS status Ended for HL408963+4.p
164704.38/21869.30	% SZS status Started for HL408957+5.p
164704.38/21869.30	% SZS status GaveUp for HL408957+5.p
164704.38/21869.30	eprover: CPU time limit exceeded, terminating
164704.38/21869.30	% SZS status Ended for HL408957+5.p
164716.50/21870.75	% SZS status Started for HL408964+4.p
164716.50/21870.75	% SZS status GaveUp for HL408964+4.p
164716.50/21870.75	eprover: CPU time limit exceeded, terminating
164716.50/21870.75	% SZS status Ended for HL408964+4.p
164716.94/21870.84	% SZS status Started for HL408958+5.p
164716.94/21870.84	% SZS status GaveUp for HL408958+5.p
164716.94/21870.84	eprover: CPU time limit exceeded, terminating
164716.94/21870.84	% SZS status Ended for HL408958+5.p
164727.72/21872.33	% SZS status Started for HL408965+4.p
164727.72/21872.33	% SZS status GaveUp for HL408965+4.p
164727.72/21872.33	eprover: CPU time limit exceeded, terminating
164727.72/21872.33	% SZS status Ended for HL408965+4.p
164732.28/21872.60	% SZS status Started for HL408960+5.p
164732.28/21872.60	% SZS status GaveUp for HL408960+5.p
164732.28/21872.60	eprover: CPU time limit exceeded, terminating
164732.28/21872.60	% SZS status Ended for HL408960+5.p
164742.56/21873.87	% SZS status Started for HL408966+4.p
164742.56/21873.87	% SZS status GaveUp for HL408966+4.p
164742.56/21873.87	eprover: CPU time limit exceeded, terminating
164742.56/21873.87	% SZS status Ended for HL408966+4.p
164750.78/21874.93	% SZS status Started for HL408961+5.p
164750.78/21874.93	% SZS status GaveUp for HL408961+5.p
164750.78/21874.93	eprover: CPU time limit exceeded, terminating
164750.78/21874.93	% SZS status Ended for HL408961+5.p
164757.03/21875.69	% SZS status Started for HL408967+4.p
164757.03/21875.69	% SZS status GaveUp for HL408967+4.p
164757.03/21875.69	eprover: CPU time limit exceeded, terminating
164757.03/21875.69	% SZS status Ended for HL408967+4.p
164759.33/21876.03	% SZS status Started for HL408962+5.p
164759.33/21876.03	% SZS status GaveUp for HL408962+5.p
164759.33/21876.03	eprover: CPU time limit exceeded, terminating
164759.33/21876.03	% SZS status Ended for HL408962+5.p
164775.50/21877.98	% SZS status Started for HL408968+4.p
164775.50/21877.98	% SZS status GaveUp for HL408968+4.p
164775.50/21877.98	eprover: CPU time limit exceeded, terminating
164775.50/21877.98	% SZS status Ended for HL408968+4.p
164780.86/21878.67	% SZS status Started for HL408963+5.p
164780.86/21878.67	% SZS status GaveUp for HL408963+5.p
164780.86/21878.67	eprover: CPU time limit exceeded, terminating
164780.86/21878.67	% SZS status Ended for HL408963+5.p
164784.66/21879.16	% SZS status Started for HL408969+4.p
164784.66/21879.16	% SZS status GaveUp for HL408969+4.p
164784.66/21879.16	eprover: CPU time limit exceeded, terminating
164784.66/21879.16	% SZS status Ended for HL408969+4.p
164786.83/21879.47	% SZS status Started for HL408964+5.p
164786.83/21879.47	% SZS status GaveUp for HL408964+5.p
164786.83/21879.47	eprover: CPU time limit exceeded, terminating
164786.83/21879.47	% SZS status Ended for HL408964+5.p
164805.25/21881.73	% SZS status Started for HL408970+4.p
164805.25/21881.73	% SZS status GaveUp for HL408970+4.p
164805.25/21881.73	eprover: CPU time limit exceeded, terminating
164805.25/21881.73	% SZS status Ended for HL408970+4.p
164811.67/21882.51	% SZS status Started for HL408971+4.p
164811.67/21882.51	% SZS status GaveUp for HL408971+4.p
164811.67/21882.51	eprover: CPU time limit exceeded, terminating
164811.67/21882.51	% SZS status Ended for HL408971+4.p
164835.81/21885.59	% SZS status Started for HL408972+4.p
164835.81/21885.59	% SZS status GaveUp for HL408972+4.p
164835.81/21885.59	eprover: CPU time limit exceeded, terminating
164835.81/21885.59	% SZS status Ended for HL408972+4.p
164855.14/21888.02	% SZS status Started for HL408967+5.p
164855.14/21888.02	% SZS status GaveUp for HL408967+5.p
164855.14/21888.02	eprover: CPU time limit exceeded, terminating
164855.14/21888.02	% SZS status Ended for HL408967+5.p
164859.44/21888.64	% SZS status Started for HL408972+5.p
164859.44/21888.64	% SZS status GaveUp for HL408972+5.p
164859.44/21888.64	eprover: CPU time limit exceeded, terminating
164859.44/21888.64	% SZS status Ended for HL408972+5.p
164880.72/21891.23	% SZS status Started for HL408974+4.p
164880.72/21891.23	% SZS status GaveUp for HL408974+4.p
164880.72/21891.23	eprover: CPU time limit exceeded, terminating
164880.72/21891.23	% SZS status Ended for HL408974+4.p
164906.41/21894.44	% SZS status Started for HL408975+4.p
164906.41/21894.44	% SZS status GaveUp for HL408975+4.p
164906.41/21894.44	eprover: CPU time limit exceeded, terminating
164906.41/21894.44	% SZS status Ended for HL408975+4.p
164925.80/21896.89	% SZS status Started for HL408965+5.p
164925.80/21896.89	% SZS status GaveUp for HL408965+5.p
164925.80/21896.89	eprover: CPU time limit exceeded, terminating
164925.80/21896.89	% SZS status Ended for HL408965+5.p
164937.78/21898.47	% SZS status Started for HL408966+5.p
164937.78/21898.47	% SZS status GaveUp for HL408966+5.p
164937.78/21898.47	eprover: CPU time limit exceeded, terminating
164937.78/21898.47	% SZS status Ended for HL408966+5.p
164948.33/21899.78	% SZS status Started for HL408974+5.p
164948.33/21899.78	% SZS status GaveUp for HL408974+5.p
164948.33/21899.78	eprover: CPU time limit exceeded, terminating
164948.33/21899.78	% SZS status Ended for HL408974+5.p
164948.80/21899.93	% SZS status Started for HL408976+4.p
164948.80/21899.93	% SZS status GaveUp for HL408976+4.p
164948.80/21899.93	eprover: CPU time limit exceeded, terminating
164948.80/21899.93	% SZS status Ended for HL408976+4.p
164964.73/21901.83	% SZS status Started for HL408968+5.p
164964.73/21901.83	% SZS status GaveUp for HL408968+5.p
164964.73/21901.83	eprover: CPU time limit exceeded, terminating
164964.73/21901.83	% SZS status Ended for HL408968+5.p
164971.83/21902.81	% SZS status Started for HL408979+4.p
164971.83/21902.81	% SZS status GaveUp for HL408979+4.p
164971.83/21902.81	eprover: CPU time limit exceeded, terminating
164971.83/21902.81	% SZS status Ended for HL408979+4.p
164985.23/21904.36	% SZS status Started for HL408969+5.p
164985.23/21904.36	% SZS status GaveUp for HL408969+5.p
164985.23/21904.36	eprover: CPU time limit exceeded, terminating
164985.23/21904.36	% SZS status Ended for HL408969+5.p
164989.52/21904.90	% SZS status Started for HL408980+4.p
164989.52/21904.90	% SZS status GaveUp for HL408980+4.p
164989.52/21904.90	eprover: CPU time limit exceeded, terminating
164989.52/21904.90	% SZS status Ended for HL408980+4.p
164994.38/21905.55	% SZS status Started for HL408970+5.p
164994.38/21905.55	% SZS status GaveUp for HL408970+5.p
164994.38/21905.55	eprover: CPU time limit exceeded, terminating
164994.38/21905.55	% SZS status Ended for HL408970+5.p
164995.02/21905.60	% SZS status Started for HL408975+5.p
164995.02/21905.60	% SZS status GaveUp for HL408975+5.p
164995.02/21905.60	eprover: CPU time limit exceeded, terminating
164995.02/21905.60	% SZS status Ended for HL408975+5.p
165009.11/21907.39	% SZS status Started for HL408981+4.p
165009.11/21907.39	% SZS status GaveUp for HL408981+4.p
165009.11/21907.39	eprover: CPU time limit exceeded, terminating
165009.11/21907.39	% SZS status Ended for HL408981+4.p
165013.47/21907.92	% SZS status Started for HL408971+5.p
165013.47/21907.92	% SZS status GaveUp for HL408971+5.p
165013.47/21907.92	eprover: CPU time limit exceeded, terminating
165013.47/21907.92	% SZS status Ended for HL408971+5.p
165018.30/21908.59	% SZS status Started for HL408982+4.p
165018.30/21908.59	% SZS status GaveUp for HL408982+4.p
165018.30/21908.59	eprover: CPU time limit exceeded, terminating
165018.30/21908.59	% SZS status Ended for HL408982+4.p
165025.23/21909.59	% SZS status Started for HL408976+5.p
165025.23/21909.59	% SZS status GaveUp for HL408976+5.p
165025.23/21909.59	eprover: CPU time limit exceeded, terminating
165025.23/21909.59	% SZS status Ended for HL408976+5.p
165033.17/21910.42	% SZS status Started for HL408983+4.p
165033.17/21910.42	% SZS status GaveUp for HL408983+4.p
165033.17/21910.42	eprover: CPU time limit exceeded, terminating
165033.17/21910.42	% SZS status Ended for HL408983+4.p
165038.53/21911.14	% SZS status Started for HL408979+5.p
165038.53/21911.14	% SZS status GaveUp for HL408979+5.p
165038.53/21911.14	eprover: CPU time limit exceeded, terminating
165038.53/21911.14	% SZS status Ended for HL408979+5.p
165042.72/21911.62	% SZS status Started for HL408984+4.p
165042.72/21911.62	% SZS status GaveUp for HL408984+4.p
165042.72/21911.62	eprover: CPU time limit exceeded, terminating
165042.72/21911.62	% SZS status Ended for HL408984+4.p
165056.95/21913.46	% SZS status Started for HL408985+4.p
165056.95/21913.46	% SZS status GaveUp for HL408985+4.p
165056.95/21913.46	eprover: CPU time limit exceeded, terminating
165056.95/21913.46	% SZS status Ended for HL408985+4.p
165062.25/21914.13	% SZS status Started for HL408980+5.p
165062.25/21914.13	% SZS status GaveUp for HL408980+5.p
165062.25/21914.13	eprover: CPU time limit exceeded, terminating
165062.25/21914.13	% SZS status Ended for HL408980+5.p
165066.69/21914.66	% SZS status Started for HL408987+4.p
165066.69/21914.66	% SZS status GaveUp for HL408987+4.p
165066.69/21914.66	eprover: CPU time limit exceeded, terminating
165066.69/21914.66	% SZS status Ended for HL408987+4.p
165080.75/21916.46	% SZS status Started for HL408981+5.p
165080.75/21916.46	% SZS status GaveUp for HL408981+5.p
165080.75/21916.46	eprover: CPU time limit exceeded, terminating
165080.75/21916.46	% SZS status Ended for HL408981+5.p
165083.30/21916.71	% SZS status Started for HL408982+5.p
165083.30/21916.71	% SZS status GaveUp for HL408982+5.p
165083.30/21916.71	eprover: CPU time limit exceeded, terminating
165083.30/21916.71	% SZS status Ended for HL408982+5.p
165085.28/21917.17	% SZS status Started for HL408988+4.p
165085.28/21917.17	% SZS status GaveUp for HL408988+4.p
165085.28/21917.17	eprover: CPU time limit exceeded, terminating
165085.28/21917.17	% SZS status Ended for HL408988+4.p
165101.84/21918.97	% SZS status Started for HL408983+5.p
165101.84/21918.97	% SZS status GaveUp for HL408983+5.p
165101.84/21918.97	eprover: CPU time limit exceeded, terminating
165101.84/21918.97	% SZS status Ended for HL408983+5.p
165107.30/21919.66	% SZS status Started for HL408989+4.p
165107.30/21919.66	% SZS status GaveUp for HL408989+4.p
165107.30/21919.66	eprover: CPU time limit exceeded, terminating
165107.30/21919.66	% SZS status Ended for HL408989+4.p
165112.02/21920.21	% SZS status Started for HL408991+4.p
165112.02/21920.21	% SZS status GaveUp for HL408991+4.p
165112.02/21920.21	eprover: CPU time limit exceeded, terminating
165112.02/21920.21	% SZS status Ended for HL408991+4.p
165114.98/21920.68	% SZS status Started for HL408984+5.p
165114.98/21920.68	% SZS status GaveUp for HL408984+5.p
165114.98/21920.68	eprover: CPU time limit exceeded, terminating
165114.98/21920.68	% SZS status Ended for HL408984+5.p
165129.34/21922.34	% SZS status Started for HL408985+5.p
165129.34/21922.34	% SZS status GaveUp for HL408985+5.p
165129.34/21922.34	eprover: CPU time limit exceeded, terminating
165129.34/21922.34	% SZS status Ended for HL408985+5.p
165132.03/21922.69	% SZS status Started for HL408993+4.p
165132.03/21922.69	% SZS status GaveUp for HL408993+4.p
165132.03/21922.69	eprover: CPU time limit exceeded, terminating
165132.03/21922.69	% SZS status Ended for HL408993+4.p
165140.77/21923.80	% SZS status Started for HL408995+4.p
165140.77/21923.80	% SZS status GaveUp for HL408995+4.p
165140.77/21923.80	eprover: CPU time limit exceeded, terminating
165140.77/21923.80	% SZS status Ended for HL408995+4.p
165146.75/21924.58	% SZS status Started for HL408987+5.p
165146.75/21924.58	% SZS status GaveUp for HL408987+5.p
165146.75/21924.58	eprover: CPU time limit exceeded, terminating
165146.75/21924.58	% SZS status Ended for HL408987+5.p
165156.00/21925.73	% SZS status Started for HL408988+5.p
165156.00/21925.73	% SZS status GaveUp for HL408988+5.p
165156.00/21925.73	eprover: CPU time limit exceeded, terminating
165156.00/21925.73	% SZS status Ended for HL408988+5.p
165157.11/21925.84	% SZS status Started for HL408999+4.p
165157.11/21925.84	% SZS status GaveUp for HL408999+4.p
165157.11/21925.84	eprover: CPU time limit exceeded, terminating
165157.11/21925.84	% SZS status Ended for HL408999+4.p
165171.16/21927.62	% SZS status Started for HL409002+4.p
165171.16/21927.62	% SZS status GaveUp for HL409002+4.p
165171.16/21927.62	eprover: CPU time limit exceeded, terminating
165171.16/21927.62	% SZS status Ended for HL409002+4.p
165172.28/21927.76	% SZS status Started for HL408989+5.p
165172.28/21927.76	% SZS status GaveUp for HL408989+5.p
165172.28/21927.76	eprover: CPU time limit exceeded, terminating
165172.28/21927.76	% SZS status Ended for HL408989+5.p
165181.70/21928.96	% SZS status Started for HL409003+4.p
165181.70/21928.96	% SZS status GaveUp for HL409003+4.p
165181.70/21928.96	eprover: CPU time limit exceeded, terminating
165181.70/21928.96	% SZS status Ended for HL409003+4.p
165190.05/21930.01	% SZS status Started for HL408991+5.p
165190.05/21930.01	% SZS status GaveUp for HL408991+5.p
165190.05/21930.01	eprover: CPU time limit exceeded, terminating
165190.05/21930.01	% SZS status Ended for HL408991+5.p
165196.95/21930.95	% SZS status Started for HL409006+4.p
165196.95/21930.95	% SZS status GaveUp for HL409006+4.p
165196.95/21930.95	eprover: CPU time limit exceeded, terminating
165196.95/21930.95	% SZS status Ended for HL409006+4.p
165199.84/21931.26	% SZS status Started for HL408993+5.p
165199.84/21931.26	% SZS status GaveUp for HL408993+5.p
165199.84/21931.26	eprover: CPU time limit exceeded, terminating
165199.84/21931.26	% SZS status Ended for HL408993+5.p
165215.06/21933.15	% SZS status Started for HL409007+4.p
165215.06/21933.15	% SZS status GaveUp for HL409007+4.p
165215.06/21933.15	eprover: CPU time limit exceeded, terminating
165215.06/21933.15	% SZS status Ended for HL409007+4.p
165216.23/21933.38	% SZS status Started for HL408995+5.p
165216.23/21933.38	% SZS status GaveUp for HL408995+5.p
165216.23/21933.38	eprover: CPU time limit exceeded, terminating
165216.23/21933.38	% SZS status Ended for HL408995+5.p
165234.06/21934.30	% SZS status Started for HL409008+4.p
165234.06/21934.30	% SZS status GaveUp for HL409008+4.p
165234.06/21934.30	eprover: CPU time limit exceeded, terminating
165234.06/21934.30	% SZS status Ended for HL409008+4.p
165238.50/21934.85	% SZS status Started for HL408999+5.p
165238.50/21934.85	% SZS status GaveUp for HL408999+5.p
165238.50/21934.85	eprover: CPU time limit exceeded, terminating
165238.50/21934.85	% SZS status Ended for HL408999+5.p
165250.70/21936.41	% SZS status Started for HL409009+4.p
165250.70/21936.41	% SZS status GaveUp for HL409009+4.p
165250.70/21936.41	eprover: CPU time limit exceeded, terminating
165250.70/21936.41	% SZS status Ended for HL409009+4.p
165253.48/21936.78	% SZS status Started for HL409002+5.p
165253.48/21936.78	% SZS status GaveUp for HL409002+5.p
165253.48/21936.78	eprover: CPU time limit exceeded, terminating
165253.48/21936.78	% SZS status Ended for HL409002+5.p
165262.34/21937.89	% SZS status Started for HL409010+4.p
165262.34/21937.89	% SZS status GaveUp for HL409010+4.p
165262.34/21937.89	eprover: CPU time limit exceeded, terminating
165262.34/21937.89	% SZS status Ended for HL409010+4.p
165268.33/21938.64	% SZS status Started for HL409003+5.p
165268.33/21938.64	% SZS status GaveUp for HL409003+5.p
165268.33/21938.64	eprover: CPU time limit exceeded, terminating
165268.33/21938.64	% SZS status Ended for HL409003+5.p
165277.72/21939.82	% SZS status Started for HL409014+4.p
165277.72/21939.82	% SZS status GaveUp for HL409014+4.p
165277.72/21939.82	eprover: CPU time limit exceeded, terminating
165277.72/21939.82	% SZS status Ended for HL409014+4.p
165279.38/21940.06	% SZS status Started for HL409006+5.p
165279.38/21940.06	% SZS status GaveUp for HL409006+5.p
165279.38/21940.06	eprover: CPU time limit exceeded, terminating
165279.38/21940.06	% SZS status Ended for HL409006+5.p
165293.64/21941.80	% SZS status Started for HL409015+4.p
165293.64/21941.80	% SZS status GaveUp for HL409015+4.p
165293.64/21941.80	eprover: CPU time limit exceeded, terminating
165293.64/21941.80	% SZS status Ended for HL409015+4.p
165295.27/21941.99	% SZS status Started for HL409007+5.p
165295.27/21941.99	% SZS status GaveUp for HL409007+5.p
165295.27/21941.99	eprover: CPU time limit exceeded, terminating
165295.27/21941.99	% SZS status Ended for HL409007+5.p
165304.84/21943.18	% SZS status Started for HL409016+4.p
165304.84/21943.18	% SZS status GaveUp for HL409016+4.p
165304.84/21943.18	eprover: CPU time limit exceeded, terminating
165304.84/21943.18	% SZS status Ended for HL409016+4.p
165314.83/21944.45	% SZS status Started for HL409008+5.p
165314.83/21944.45	% SZS status GaveUp for HL409008+5.p
165314.83/21944.45	eprover: CPU time limit exceeded, terminating
165314.83/21944.45	% SZS status Ended for HL409008+5.p
165319.11/21945.03	% SZS status Started for HL409017+4.p
165319.11/21945.03	% SZS status GaveUp for HL409017+4.p
165319.11/21945.03	eprover: CPU time limit exceeded, terminating
165319.11/21945.03	% SZS status Ended for HL409017+4.p
165323.28/21945.51	% SZS status Started for HL409009+5.p
165323.28/21945.51	% SZS status GaveUp for HL409009+5.p
165323.28/21945.51	eprover: CPU time limit exceeded, terminating
165323.28/21945.51	% SZS status Ended for HL409009+5.p
165338.70/21947.50	% SZS status Started for HL409010+5.p
165338.70/21947.50	% SZS status GaveUp for HL409010+5.p
165338.70/21947.50	eprover: CPU time limit exceeded, terminating
165338.70/21947.50	% SZS status Ended for HL409010+5.p
165338.70/21947.53	% SZS status Started for HL409018+4.p
165338.70/21947.53	% SZS status GaveUp for HL409018+4.p
165338.70/21947.53	eprover: CPU time limit exceeded, terminating
165338.70/21947.53	% SZS status Ended for HL409018+4.p
165347.84/21948.60	% SZS status Started for HL409019+4.p
165347.84/21948.60	% SZS status GaveUp for HL409019+4.p
165347.84/21948.60	eprover: CPU time limit exceeded, terminating
165347.84/21948.60	% SZS status Ended for HL409019+4.p
165350.69/21949.01	% SZS status Started for HL409014+5.p
165350.69/21949.01	% SZS status GaveUp for HL409014+5.p
165350.69/21949.01	eprover: CPU time limit exceeded, terminating
165350.69/21949.01	% SZS status Ended for HL409014+5.p
165362.48/21950.56	% SZS status Started for HL409024+4.p
165362.48/21950.56	% SZS status GaveUp for HL409024+4.p
165362.48/21950.56	eprover: CPU time limit exceeded, terminating
165362.48/21950.56	% SZS status Ended for HL409024+4.p
165364.20/21950.93	% SZS status Started for HL409015+5.p
165364.20/21950.93	% SZS status GaveUp for HL409015+5.p
165364.20/21950.93	eprover: CPU time limit exceeded, terminating
165364.20/21950.93	% SZS status Ended for HL409015+5.p
165375.28/21952.05	% SZS status Started for HL409025+4.p
165375.28/21952.05	% SZS status GaveUp for HL409025+4.p
165375.28/21952.05	eprover: CPU time limit exceeded, terminating
165375.28/21952.05	% SZS status Ended for HL409025+4.p
165382.17/21952.93	% SZS status Started for HL409016+5.p
165382.17/21952.93	% SZS status GaveUp for HL409016+5.p
165382.17/21952.93	eprover: CPU time limit exceeded, terminating
165382.17/21952.93	% SZS status Ended for HL409016+5.p
165390.34/21953.97	% SZS status Started for HL409026+4.p
165390.34/21953.97	% SZS status GaveUp for HL409026+4.p
165390.34/21953.97	eprover: CPU time limit exceeded, terminating
165390.34/21953.97	% SZS status Ended for HL409026+4.p
165393.88/21954.37	% SZS status Started for HL409017+5.p
165393.88/21954.37	% SZS status GaveUp for HL409017+5.p
165393.88/21954.37	eprover: CPU time limit exceeded, terminating
165393.88/21954.37	% SZS status Ended for HL409017+5.p
165405.56/21955.97	% SZS status Started for HL409027+4.p
165405.56/21955.97	% SZS status GaveUp for HL409027+4.p
165405.56/21955.97	eprover: CPU time limit exceeded, terminating
165405.56/21955.97	% SZS status Ended for HL409027+4.p
165410.75/21956.36	% SZS status Started for HL409018+5.p
165410.75/21956.36	% SZS status GaveUp for HL409018+5.p
165410.75/21956.36	eprover: CPU time limit exceeded, terminating
165410.75/21956.36	% SZS status Ended for HL409018+5.p
165419.81/21957.40	% SZS status Started for HL409030+4.p
165419.81/21957.40	% SZS status GaveUp for HL409030+4.p
165419.81/21957.40	eprover: CPU time limit exceeded, terminating
165419.81/21957.40	% SZS status Ended for HL409030+4.p
165428.77/21958.57	% SZS status Started for HL409019+5.p
165428.77/21958.57	% SZS status GaveUp for HL409019+5.p
165428.77/21958.57	eprover: CPU time limit exceeded, terminating
165428.77/21958.57	% SZS status Ended for HL409019+5.p
165435.75/21959.41	% SZS status Started for HL409031+4.p
165435.75/21959.41	% SZS status GaveUp for HL409031+4.p
165435.75/21959.41	eprover: CPU time limit exceeded, terminating
165435.75/21959.41	% SZS status Ended for HL409031+4.p
165438.47/21959.78	% SZS status Started for HL409024+5.p
165438.47/21959.78	% SZS status GaveUp for HL409024+5.p
165438.47/21959.78	eprover: CPU time limit exceeded, terminating
165438.47/21959.78	% SZS status Ended for HL409024+5.p
165452.23/21961.61	% SZS status Started for HL409032+4.p
165452.23/21961.61	% SZS status GaveUp for HL409032+4.p
165452.23/21961.61	eprover: CPU time limit exceeded, terminating
165452.23/21961.61	% SZS status Ended for HL409032+4.p
165455.95/21961.94	% SZS status Started for HL409025+5.p
165455.95/21961.94	% SZS status GaveUp for HL409025+5.p
165455.95/21961.94	eprover: CPU time limit exceeded, terminating
165455.95/21961.94	% SZS status Ended for HL409025+5.p
165464.00/21962.99	% SZS status Started for HL409033+4.p
165464.00/21962.99	% SZS status GaveUp for HL409033+4.p
165464.00/21962.99	eprover: CPU time limit exceeded, terminating
165464.00/21962.99	% SZS status Ended for HL409033+4.p
165464.77/21963.09	% SZS status Started for HL409026+5.p
165464.77/21963.09	% SZS status GaveUp for HL409026+5.p
165464.77/21963.09	eprover: CPU time limit exceeded, terminating
165464.77/21963.09	% SZS status Ended for HL409026+5.p
165479.98/21964.98	% SZS status Started for HL409034+4.p
165479.98/21964.98	% SZS status GaveUp for HL409034+4.p
165479.98/21964.98	eprover: CPU time limit exceeded, terminating
165479.98/21964.98	% SZS status Ended for HL409034+4.p
165480.41/21965.04	% SZS status Started for HL409027+5.p
165480.41/21965.04	% SZS status GaveUp for HL409027+5.p
165480.41/21965.04	eprover: CPU time limit exceeded, terminating
165480.41/21965.04	% SZS status Ended for HL409027+5.p
165488.66/21966.13	% SZS status Started for HL409035+4.p
165488.66/21966.13	% SZS status GaveUp for HL409035+4.p
165488.66/21966.13	eprover: CPU time limit exceeded, terminating
165488.66/21966.13	% SZS status Ended for HL409035+4.p
165497.72/21967.20	% SZS status Started for HL409030+5.p
165497.72/21967.20	% SZS status GaveUp for HL409030+5.p
165497.72/21967.20	eprover: CPU time limit exceeded, terminating
165497.72/21967.20	% SZS status Ended for HL409030+5.p
165504.59/21968.08	% SZS status Started for HL409036+4.p
165504.59/21968.08	% SZS status GaveUp for HL409036+4.p
165504.59/21968.08	eprover: CPU time limit exceeded, terminating
165504.59/21968.08	% SZS status Ended for HL409036+4.p
165507.12/21968.48	% SZS status Started for HL409031+5.p
165507.12/21968.48	% SZS status GaveUp for HL409031+5.p
165507.12/21968.48	eprover: CPU time limit exceeded, terminating
165507.12/21968.48	% SZS status Ended for HL409031+5.p
165520.83/21970.23	% SZS status Started for HL409037+4.p
165520.83/21970.23	% SZS status GaveUp for HL409037+4.p
165520.83/21970.23	eprover: CPU time limit exceeded, terminating
165520.83/21970.23	% SZS status Ended for HL409037+4.p
165524.84/21970.46	% SZS status Started for HL409032+5.p
165524.84/21970.46	% SZS status GaveUp for HL409032+5.p
165524.84/21970.46	eprover: CPU time limit exceeded, terminating
165524.84/21970.46	% SZS status Ended for HL409032+5.p
165533.64/21971.52	% SZS status Started for HL409039+4.p
165533.64/21971.52	% SZS status GaveUp for HL409039+4.p
165533.64/21971.52	eprover: CPU time limit exceeded, terminating
165533.64/21971.52	% SZS status Ended for HL409039+4.p
165542.95/21972.70	% SZS status Started for HL409033+5.p
165542.95/21972.70	% SZS status GaveUp for HL409033+5.p
165542.95/21972.70	eprover: CPU time limit exceeded, terminating
165542.95/21972.70	% SZS status Ended for HL409033+5.p
165548.97/21973.50	% SZS status Started for HL409040+4.p
165548.97/21973.50	% SZS status GaveUp for HL409040+4.p
165548.97/21973.50	eprover: CPU time limit exceeded, terminating
165548.97/21973.50	% SZS status Ended for HL409040+4.p
165558.98/21974.70	% SZS status Started for HL409034+5.p
165558.98/21974.70	% SZS status GaveUp for HL409034+5.p
165558.98/21974.70	eprover: CPU time limit exceeded, terminating
165558.98/21974.70	% SZS status Ended for HL409034+5.p
165566.83/21975.73	% SZS status Started for HL409042+4.p
165566.83/21975.73	% SZS status GaveUp for HL409042+4.p
165566.83/21975.73	eprover: CPU time limit exceeded, terminating
165566.83/21975.73	% SZS status Ended for HL409042+4.p
165569.62/21976.05	% SZS status Started for HL409035+5.p
165569.62/21976.05	% SZS status GaveUp for HL409035+5.p
165569.62/21976.05	eprover: CPU time limit exceeded, terminating
165569.62/21976.05	% SZS status Ended for HL409035+5.p
165579.09/21977.25	% SZS status Started for HL409036+5.p
165579.09/21977.25	% SZS status GaveUp for HL409036+5.p
165579.09/21977.25	eprover: CPU time limit exceeded, terminating
165579.09/21977.25	% SZS status Ended for HL409036+5.p
165583.50/21977.79	% SZS status Started for HL409043+4.p
165583.50/21977.79	% SZS status GaveUp for HL409043+4.p
165583.50/21977.79	eprover: CPU time limit exceeded, terminating
165583.50/21977.79	% SZS status Ended for HL409043+4.p
165594.44/21979.14	% SZS status Started for HL409044+4.p
165594.44/21979.14	% SZS status GaveUp for HL409044+4.p
165594.44/21979.14	eprover: CPU time limit exceeded, terminating
165594.44/21979.14	% SZS status Ended for HL409044+4.p
165594.44/21979.17	% SZS status Started for HL409037+5.p
165594.44/21979.17	% SZS status GaveUp for HL409037+5.p
165594.44/21979.17	eprover: CPU time limit exceeded, terminating
165594.44/21979.17	% SZS status Ended for HL409037+5.p
165608.14/21980.98	% SZS status Started for HL409046+4.p
165608.14/21980.98	% SZS status GaveUp for HL409046+4.p
165608.14/21980.98	eprover: CPU time limit exceeded, terminating
165608.14/21980.98	% SZS status Ended for HL409046+4.p
165611.66/21981.31	% SZS status Started for HL409039+5.p
165611.66/21981.31	% SZS status GaveUp for HL409039+5.p
165611.66/21981.31	eprover: CPU time limit exceeded, terminating
165611.66/21981.31	% SZS status Ended for HL409039+5.p
165618.59/21982.21	% SZS status Started for HL409047+4.p
165618.59/21982.21	% SZS status GaveUp for HL409047+4.p
165618.59/21982.21	eprover: CPU time limit exceeded, terminating
165618.59/21982.21	% SZS status Ended for HL409047+4.p
165621.55/21982.58	% SZS status Started for HL409040+5.p
165621.55/21982.58	% SZS status GaveUp for HL409040+5.p
165621.55/21982.58	eprover: CPU time limit exceeded, terminating
165621.55/21982.58	% SZS status Ended for HL409040+5.p
165635.23/21984.42	% SZS status Started for HL409048+4.p
165635.23/21984.42	% SZS status GaveUp for HL409048+4.p
165635.23/21984.42	eprover: CPU time limit exceeded, terminating
165635.23/21984.42	% SZS status Ended for HL409048+4.p
165636.22/21984.56	% SZS status Started for HL409042+5.p
165636.22/21984.56	% SZS status GaveUp for HL409042+5.p
165636.22/21984.56	eprover: CPU time limit exceeded, terminating
165636.22/21984.56	% SZS status Ended for HL409042+5.p
165646.42/21985.67	% SZS status Started for HL409049+4.p
165646.42/21985.67	% SZS status GaveUp for HL409049+4.p
165646.42/21985.67	eprover: CPU time limit exceeded, terminating
165646.42/21985.67	% SZS status Ended for HL409049+4.p
165655.52/21986.81	% SZS status Started for HL409043+5.p
165655.52/21986.81	% SZS status GaveUp for HL409043+5.p
165655.52/21986.81	eprover: CPU time limit exceeded, terminating
165655.52/21986.81	% SZS status Ended for HL409043+5.p
165660.30/21987.60	% SZS status Started for HL409050+4.p
165660.30/21987.60	% SZS status GaveUp for HL409050+4.p
165660.30/21987.60	eprover: CPU time limit exceeded, terminating
165660.30/21987.60	% SZS status Ended for HL409050+4.p
165667.48/21988.34	% SZS status Started for HL409044+5.p
165667.48/21988.34	% SZS status GaveUp for HL409044+5.p
165667.48/21988.34	eprover: CPU time limit exceeded, terminating
165667.48/21988.34	% SZS status Ended for HL409044+5.p
165679.61/21989.85	% SZS status Started for HL409051+4.p
165679.61/21989.85	% SZS status GaveUp for HL409051+4.p
165679.61/21989.85	eprover: CPU time limit exceeded, terminating
165679.61/21989.85	% SZS status Ended for HL409051+4.p
165682.09/21990.18	% SZS status Started for HL409046+5.p
165682.09/21990.18	% SZS status GaveUp for HL409046+5.p
165682.09/21990.18	eprover: CPU time limit exceeded, terminating
165682.09/21990.18	% SZS status Ended for HL409046+5.p
165691.23/21991.37	% SZS status Started for HL409052+4.p
165691.23/21991.37	% SZS status GaveUp for HL409052+4.p
165691.23/21991.37	eprover: CPU time limit exceeded, terminating
165691.23/21991.37	% SZS status Ended for HL409052+4.p
165697.64/21992.17	% SZS status Started for HL409047+5.p
165697.64/21992.17	% SZS status GaveUp for HL409047+5.p
165697.64/21992.17	eprover: CPU time limit exceeded, terminating
165697.64/21992.17	% SZS status Ended for HL409047+5.p
165705.77/21993.22	% SZS status Started for HL409053+4.p
165705.77/21993.22	% SZS status GaveUp for HL409053+4.p
165705.77/21993.22	eprover: CPU time limit exceeded, terminating
165705.77/21993.22	% SZS status Ended for HL409053+4.p
165705.77/21993.24	% SZS status Started for HL409048+5.p
165705.77/21993.24	% SZS status GaveUp for HL409048+5.p
165705.77/21993.24	eprover: CPU time limit exceeded, terminating
165705.77/21993.24	% SZS status Ended for HL409048+5.p
165722.20/21995.22	% SZS status Started for HL409054+4.p
165722.20/21995.22	% SZS status GaveUp for HL409054+4.p
165722.20/21995.22	eprover: CPU time limit exceeded, terminating
165722.20/21995.22	% SZS status Ended for HL409054+4.p
165723.58/21995.49	% SZS status Started for HL409049+5.p
165723.58/21995.49	% SZS status GaveUp for HL409049+5.p
165723.58/21995.49	eprover: CPU time limit exceeded, terminating
165723.58/21995.49	% SZS status Ended for HL409049+5.p
165730.52/21996.29	% SZS status Started for HL409055+4.p
165730.52/21996.29	% SZS status GaveUp for HL409055+4.p
165730.52/21996.29	eprover: CPU time limit exceeded, terminating
165730.52/21996.29	% SZS status Ended for HL409055+4.p
165737.92/21997.30	% SZS status Started for HL409050+5.p
165737.92/21997.30	% SZS status GaveUp for HL409050+5.p
165737.92/21997.30	eprover: CPU time limit exceeded, terminating
165737.92/21997.30	% SZS status Ended for HL409050+5.p
165748.56/21998.53	% SZS status Started for HL409056+4.p
165748.56/21998.53	% SZS status GaveUp for HL409056+4.p
165748.56/21998.53	eprover: CPU time limit exceeded, terminating
165748.56/21998.53	% SZS status Ended for HL409056+4.p
165749.41/21998.65	% SZS status Started for HL409051+5.p
165749.41/21998.65	% SZS status GaveUp for HL409051+5.p
165749.41/21998.65	eprover: CPU time limit exceeded, terminating
165749.41/21998.65	% SZS status Ended for HL409051+5.p
165762.59/22000.35	% SZS status Started for HL409058+4.p
165762.59/22000.35	% SZS status GaveUp for HL409058+4.p
165762.59/22000.35	eprover: CPU time limit exceeded, terminating
165762.59/22000.35	% SZS status Ended for HL409058+4.p
165767.48/22000.92	% SZS status Started for HL409052+5.p
165767.48/22000.92	% SZS status GaveUp for HL409052+5.p
165767.48/22000.92	eprover: CPU time limit exceeded, terminating
165767.48/22000.92	% SZS status Ended for HL409052+5.p
165772.73/22001.69	% SZS status Started for HL409059+4.p
165772.73/22001.69	% SZS status GaveUp for HL409059+4.p
165772.73/22001.69	eprover: CPU time limit exceeded, terminating
165772.73/22001.69	% SZS status Ended for HL409059+4.p
165778.61/22002.42	% SZS status Started for HL409053+5.p
165778.61/22002.42	% SZS status GaveUp for HL409053+5.p
165778.61/22002.42	eprover: CPU time limit exceeded, terminating
165778.61/22002.42	% SZS status Ended for HL409053+5.p
165791.45/22003.96	% SZS status Started for HL409060+4.p
165791.45/22003.96	% SZS status GaveUp for HL409060+4.p
165791.45/22003.96	eprover: CPU time limit exceeded, terminating
165791.45/22003.96	% SZS status Ended for HL409060+4.p
165793.73/22004.27	% SZS status Started for HL409054+5.p
165793.73/22004.27	% SZS status GaveUp for HL409054+5.p
165793.73/22004.27	eprover: CPU time limit exceeded, terminating
165793.73/22004.27	% SZS status Ended for HL409054+5.p
165803.27/22005.49	% SZS status Started for HL409062+4.p
165803.27/22005.49	% SZS status GaveUp for HL409062+4.p
165803.27/22005.49	eprover: CPU time limit exceeded, terminating
165803.27/22005.49	% SZS status Ended for HL409062+4.p
165810.48/22006.35	% SZS status Started for HL409055+5.p
165810.48/22006.35	% SZS status GaveUp for HL409055+5.p
165810.48/22006.35	eprover: CPU time limit exceeded, terminating
165810.48/22006.35	% SZS status Ended for HL409055+5.p
165818.06/22007.31	% SZS status Started for HL409063+4.p
165818.06/22007.31	% SZS status GaveUp for HL409063+4.p
165818.06/22007.31	eprover: CPU time limit exceeded, terminating
165818.06/22007.31	% SZS status Ended for HL409063+4.p
165818.06/22007.33	% SZS status Started for HL409056+5.p
165818.06/22007.33	% SZS status GaveUp for HL409056+5.p
165818.06/22007.33	eprover: CPU time limit exceeded, terminating
165818.06/22007.33	% SZS status Ended for HL409056+5.p
165834.50/22009.40	% SZS status Started for HL409064+4.p
165834.50/22009.40	% SZS status GaveUp for HL409064+4.p
165834.50/22009.40	eprover: CPU time limit exceeded, terminating
165834.50/22009.40	% SZS status Ended for HL409064+4.p
165838.55/22009.92	% SZS status Started for HL409058+5.p
165838.55/22009.92	% SZS status GaveUp for HL409058+5.p
165838.55/22009.92	eprover: CPU time limit exceeded, terminating
165838.55/22009.92	% SZS status Ended for HL409058+5.p
165842.73/22010.38	% SZS status Started for HL409065+4.p
165842.73/22010.38	% SZS status GaveUp for HL409065+4.p
165842.73/22010.38	eprover: CPU time limit exceeded, terminating
165842.73/22010.38	% SZS status Ended for HL409065+4.p
165850.61/22011.38	% SZS status Started for HL409059+5.p
165850.61/22011.38	% SZS status GaveUp for HL409059+5.p
165850.61/22011.38	eprover: CPU time limit exceeded, terminating
165850.61/22011.38	% SZS status Ended for HL409059+5.p
165861.64/22012.77	% SZS status Started for HL409060+5.p
165861.64/22012.77	% SZS status GaveUp for HL409060+5.p
165861.64/22012.77	eprover: CPU time limit exceeded, terminating
165861.64/22012.77	% SZS status Ended for HL409060+5.p
165863.44/22012.99	% SZS status Started for HL409066+4.p
165863.44/22012.99	% SZS status GaveUp for HL409066+4.p
165863.44/22012.99	eprover: CPU time limit exceeded, terminating
165863.44/22012.99	% SZS status Ended for HL409066+4.p
165874.44/22014.40	% SZS status Started for HL409062+5.p
165874.44/22014.40	% SZS status GaveUp for HL409062+5.p
165874.44/22014.40	eprover: CPU time limit exceeded, terminating
165874.44/22014.40	% SZS status Ended for HL409062+5.p
165874.44/22014.42	% SZS status Started for HL409069+4.p
165874.44/22014.42	% SZS status GaveUp for HL409069+4.p
165874.44/22014.42	eprover: CPU time limit exceeded, terminating
165874.44/22014.42	% SZS status Ended for HL409069+4.p
165884.08/22015.67	% SZS status Started for HL409063+5.p
165884.08/22015.67	% SZS status GaveUp for HL409063+5.p
165884.08/22015.67	eprover: CPU time limit exceeded, terminating
165884.08/22015.67	% SZS status Ended for HL409063+5.p
165887.62/22016.04	% SZS status Started for HL409070+4.p
165887.62/22016.04	% SZS status GaveUp for HL409070+4.p
165887.62/22016.04	eprover: CPU time limit exceeded, terminating
165887.62/22016.04	% SZS status Ended for HL409070+4.p
165898.95/22017.47	% SZS status Started for HL409071+4.p
165898.95/22017.47	% SZS status GaveUp for HL409071+4.p
165898.95/22017.47	eprover: CPU time limit exceeded, terminating
165898.95/22017.47	% SZS status Ended for HL409071+4.p
165911.95/22019.06	% SZS status Started for HL409072+4.p
165911.95/22019.06	% SZS status GaveUp for HL409072+4.p
165911.95/22019.06	eprover: CPU time limit exceeded, terminating
165911.95/22019.06	% SZS status Ended for HL409072+4.p
165935.88/22022.09	% SZS status Started for HL409073+4.p
165935.88/22022.09	% SZS status GaveUp for HL409073+4.p
165935.88/22022.09	eprover: CPU time limit exceeded, terminating
165935.88/22022.09	% SZS status Ended for HL409073+4.p
165942.50/22022.99	% SZS status Started for HL409069+5.p
165942.50/22022.99	% SZS status GaveUp for HL409069+5.p
165942.50/22022.99	eprover: CPU time limit exceeded, terminating
165942.50/22022.99	% SZS status Ended for HL409069+5.p
165955.52/22024.61	% SZS status Started for HL409070+5.p
165955.52/22024.61	% SZS status GaveUp for HL409070+5.p
165955.52/22024.61	eprover: CPU time limit exceeded, terminating
165955.52/22024.61	% SZS status Ended for HL409070+5.p
165959.81/22025.14	% SZS status Started for HL409073+5.p
165959.81/22025.14	% SZS status GaveUp for HL409073+5.p
165959.81/22025.14	eprover: CPU time limit exceeded, terminating
165959.81/22025.14	% SZS status Ended for HL409073+5.p
165967.19/22026.03	% SZS status Started for HL409074+4.p
165967.19/22026.03	% SZS status GaveUp for HL409074+4.p
165967.19/22026.03	eprover: CPU time limit exceeded, terminating
165967.19/22026.03	% SZS status Ended for HL409074+4.p
165983.92/22028.18	% SZS status Started for HL409075+4.p
165983.92/22028.18	% SZS status GaveUp for HL409075+4.p
165983.92/22028.18	eprover: CPU time limit exceeded, terminating
165983.92/22028.18	% SZS status Ended for HL409075+4.p
166008.22/22031.21	% SZS status Started for HL409076+4.p
166008.22/22031.21	% SZS status GaveUp for HL409076+4.p
166008.22/22031.21	eprover: CPU time limit exceeded, terminating
166008.22/22031.21	% SZS status Ended for HL409076+4.p
166025.55/22033.40	% SZS status Started for HL409064+5.p
166025.55/22033.40	% SZS status GaveUp for HL409064+5.p
166025.55/22033.40	eprover: CPU time limit exceeded, terminating
166025.55/22033.40	% SZS status Ended for HL409064+5.p
166043.89/22035.74	% SZS status Started for HL409074+5.p
166043.89/22035.74	% SZS status GaveUp for HL409074+5.p
166043.89/22035.74	eprover: CPU time limit exceeded, terminating
166043.89/22035.74	% SZS status Ended for HL409074+5.p
166049.06/22036.41	% SZS status Started for HL409065+5.p
166049.06/22036.41	% SZS status GaveUp for HL409065+5.p
166049.06/22036.41	eprover: CPU time limit exceeded, terminating
166049.06/22036.41	% SZS status Ended for HL409065+5.p
166049.06/22036.43	% SZS status Started for HL409078+4.p
166049.06/22036.43	% SZS status GaveUp for HL409078+4.p
166049.06/22036.43	eprover: CPU time limit exceeded, terminating
166049.06/22036.43	% SZS status Ended for HL409078+4.p
166049.88/22036.59	% SZS status Started for HL409066+5.p
166049.88/22036.59	% SZS status GaveUp for HL409066+5.p
166049.88/22036.59	eprover: CPU time limit exceeded, terminating
166049.88/22036.59	% SZS status Ended for HL409066+5.p
166055.16/22037.14	% SZS status Started for HL409075+5.p
166055.16/22037.14	% SZS status GaveUp for HL409075+5.p
166055.16/22037.14	eprover: CPU time limit exceeded, terminating
166055.16/22037.14	% SZS status Ended for HL409075+5.p
166074.14/22039.59	% SZS status Started for HL409079+4.p
166074.14/22039.59	% SZS status GaveUp for HL409079+4.p
166074.14/22039.59	eprover: CPU time limit exceeded, terminating
166074.14/22039.59	% SZS status Ended for HL409079+4.p
166074.50/22039.63	% SZS status Started for HL409080+4.p
166074.50/22039.63	% SZS status GaveUp for HL409080+4.p
166074.50/22039.63	eprover: CPU time limit exceeded, terminating
166074.50/22039.63	% SZS status Ended for HL409080+4.p
166080.44/22040.33	% SZS status Started for HL409076+5.p
166080.44/22040.33	% SZS status GaveUp for HL409076+5.p
166080.44/22040.33	eprover: CPU time limit exceeded, terminating
166080.44/22040.33	% SZS status Ended for HL409076+5.p
166092.27/22041.85	% SZS status Started for HL409071+5.p
166092.27/22041.85	% SZS status GaveUp for HL409071+5.p
166092.27/22041.85	eprover: CPU time limit exceeded, terminating
166092.27/22041.85	% SZS status Ended for HL409071+5.p
166098.33/22042.62	% SZS status Started for HL409082+4.p
166098.33/22042.62	% SZS status GaveUp for HL409082+4.p
166098.33/22042.62	eprover: CPU time limit exceeded, terminating
166098.33/22042.62	% SZS status Ended for HL409082+4.p
166104.91/22043.37	% SZS status Started for HL409084+4.p
166104.91/22043.37	% SZS status GaveUp for HL409084+4.p
166104.91/22043.37	eprover: CPU time limit exceeded, terminating
166104.91/22043.37	% SZS status Ended for HL409084+4.p
166106.05/22043.65	% SZS status Started for HL409072+5.p
166106.05/22043.65	% SZS status GaveUp for HL409072+5.p
166106.05/22043.65	eprover: CPU time limit exceeded, terminating
166106.05/22043.65	% SZS status Ended for HL409072+5.p
166122.44/22045.66	% SZS status Started for HL409085+4.p
166122.44/22045.66	% SZS status GaveUp for HL409085+4.p
166122.44/22045.66	eprover: CPU time limit exceeded, terminating
166122.44/22045.66	% SZS status Ended for HL409085+4.p
166131.02/22046.69	% SZS status Started for HL409086+4.p
166131.02/22046.69	% SZS status GaveUp for HL409086+4.p
166131.02/22046.69	eprover: CPU time limit exceeded, terminating
166131.02/22046.69	% SZS status Ended for HL409086+4.p
166131.86/22046.84	% SZS status Started for HL409078+5.p
166131.86/22046.84	% SZS status GaveUp for HL409078+5.p
166131.86/22046.84	eprover: CPU time limit exceeded, terminating
166131.86/22046.84	% SZS status Ended for HL409078+5.p
166137.56/22047.52	% SZS status Started for HL409079+5.p
166137.56/22047.52	% SZS status GaveUp for HL409079+5.p
166137.56/22047.52	eprover: CPU time limit exceeded, terminating
166137.56/22047.52	% SZS status Ended for HL409079+5.p
166145.64/22048.58	% SZS status Started for HL409080+5.p
166145.64/22048.58	% SZS status GaveUp for HL409080+5.p
166145.64/22048.58	eprover: CPU time limit exceeded, terminating
166145.64/22048.58	% SZS status Ended for HL409080+5.p
166155.33/22049.73	% SZS status Started for HL409087+4.p
166155.33/22049.73	% SZS status GaveUp for HL409087+4.p
166155.33/22049.73	eprover: CPU time limit exceeded, terminating
166155.33/22049.73	% SZS status Ended for HL409087+4.p
166161.75/22050.56	% SZS status Started for HL409088+4.p
166161.75/22050.56	% SZS status GaveUp for HL409088+4.p
166161.75/22050.56	eprover: CPU time limit exceeded, terminating
166161.75/22050.56	% SZS status Ended for HL409088+4.p
166162.64/22050.75	% SZS status Started for HL409082+5.p
166162.64/22050.75	% SZS status GaveUp for HL409082+5.p
166162.64/22050.75	eprover: CPU time limit exceeded, terminating
166162.64/22050.75	% SZS status Ended for HL409082+5.p
166178.94/22052.77	% SZS status Started for HL409089+4.p
166178.94/22052.77	% SZS status GaveUp for HL409089+4.p
166178.94/22052.77	eprover: CPU time limit exceeded, terminating
166178.94/22052.77	% SZS status Ended for HL409089+4.p
166180.09/22052.94	% SZS status Started for HL409084+5.p
166180.09/22052.94	% SZS status GaveUp for HL409084+5.p
166180.09/22052.94	eprover: CPU time limit exceeded, terminating
166180.09/22052.94	% SZS status Ended for HL409084+5.p
166188.88/22053.94	% SZS status Started for HL409091+4.p
166188.88/22053.94	% SZS status GaveUp for HL409091+4.p
166188.88/22053.94	eprover: CPU time limit exceeded, terminating
166188.88/22053.94	% SZS status Ended for HL409091+4.p
166191.64/22054.44	% SZS status Started for HL409085+5.p
166191.64/22054.44	% SZS status GaveUp for HL409085+5.p
166191.64/22054.44	eprover: CPU time limit exceeded, terminating
166191.64/22054.44	% SZS status Ended for HL409085+5.p
166204.31/22055.98	% SZS status Started for HL409092+4.p
166204.31/22055.98	% SZS status GaveUp for HL409092+4.p
166204.31/22055.98	eprover: CPU time limit exceeded, terminating
166204.31/22055.98	% SZS status Ended for HL409092+4.p
166211.58/22057.01	% SZS status Started for HL409086+5.p
166211.58/22057.01	% SZS status GaveUp for HL409086+5.p
166211.58/22057.01	eprover: CPU time limit exceeded, terminating
166211.58/22057.01	% SZS status Ended for HL409086+5.p
166217.42/22057.62	% SZS status Started for HL409094+4.p
166217.42/22057.62	% SZS status GaveUp for HL409094+4.p
166217.42/22057.62	eprover: CPU time limit exceeded, terminating
166217.42/22057.62	% SZS status Ended for HL409094+4.p
166220.61/22057.99	% SZS status Started for HL409087+5.p
166220.61/22057.99	% SZS status GaveUp for HL409087+5.p
166220.61/22057.99	eprover: CPU time limit exceeded, terminating
166220.61/22057.99	% SZS status Ended for HL409087+5.p
166233.83/22059.65	% SZS status Started for HL409088+5.p
166233.83/22059.65	% SZS status GaveUp for HL409088+5.p
166233.83/22059.65	eprover: CPU time limit exceeded, terminating
166233.83/22059.65	% SZS status Ended for HL409088+5.p
166236.02/22060.04	% SZS status Started for HL409095+4.p
166236.02/22060.04	% SZS status GaveUp for HL409095+4.p
166236.02/22060.04	eprover: CPU time limit exceeded, terminating
166236.02/22060.04	% SZS status Ended for HL409095+4.p
166244.94/22061.02	% SZS status Started for HL409096+4.p
166244.94/22061.02	% SZS status GaveUp for HL409096+4.p
166244.94/22061.02	eprover: CPU time limit exceeded, terminating
166244.94/22061.02	% SZS status Ended for HL409096+4.p
166250.39/22061.72	% SZS status Started for HL409089+5.p
166250.39/22061.72	% SZS status GaveUp for HL409089+5.p
166250.39/22061.72	eprover: CPU time limit exceeded, terminating
166250.39/22061.72	% SZS status Ended for HL409089+5.p
166260.47/22063.07	% SZS status Started for HL409097+4.p
166260.47/22063.07	% SZS status GaveUp for HL409097+4.p
166260.47/22063.07	eprover: CPU time limit exceeded, terminating
166260.47/22063.07	% SZS status Ended for HL409097+4.p
166267.34/22063.82	% SZS status Started for HL409091+5.p
166267.34/22063.82	% SZS status GaveUp for HL409091+5.p
166267.34/22063.82	eprover: CPU time limit exceeded, terminating
166267.34/22063.82	% SZS status Ended for HL409091+5.p
166274.45/22064.75	% SZS status Started for HL409098+4.p
166274.45/22064.75	% SZS status GaveUp for HL409098+4.p
166274.45/22064.75	eprover: CPU time limit exceeded, terminating
166274.45/22064.75	% SZS status Ended for HL409098+4.p
166275.88/22065.00	% SZS status Started for HL409092+5.p
166275.88/22065.00	% SZS status GaveUp for HL409092+5.p
166275.88/22065.00	eprover: CPU time limit exceeded, terminating
166275.88/22065.00	% SZS status Ended for HL409092+5.p
166291.16/22066.85	% SZS status Started for HL409099+4.p
166291.16/22066.85	% SZS status GaveUp for HL409099+4.p
166291.16/22066.85	eprover: CPU time limit exceeded, terminating
166291.16/22066.85	% SZS status Ended for HL409099+4.p
166292.64/22067.03	% SZS status Started for HL409094+5.p
166292.64/22067.03	% SZS status GaveUp for HL409094+5.p
166292.64/22067.03	eprover: CPU time limit exceeded, terminating
166292.64/22067.03	% SZS status Ended for HL409094+5.p
166299.86/22068.04	% SZS status Started for HL409102+4.p
166299.86/22068.04	% SZS status GaveUp for HL409102+4.p
166299.86/22068.04	eprover: CPU time limit exceeded, terminating
166299.86/22068.04	% SZS status Ended for HL409102+4.p
166306.25/22068.82	% SZS status Started for HL409095+5.p
166306.25/22068.82	% SZS status GaveUp for HL409095+5.p
166306.25/22068.82	eprover: CPU time limit exceeded, terminating
166306.25/22068.82	% SZS status Ended for HL409095+5.p
166315.72/22070.07	% SZS status Started for HL409103+4.p
166315.72/22070.07	% SZS status GaveUp for HL409103+4.p
166315.72/22070.07	eprover: CPU time limit exceeded, terminating
166315.72/22070.07	% SZS status Ended for HL409103+4.p
166322.02/22070.70	% SZS status Started for HL409096+5.p
166322.02/22070.70	% SZS status GaveUp for HL409096+5.p
166322.02/22070.70	eprover: CPU time limit exceeded, terminating
166322.02/22070.70	% SZS status Ended for HL409096+5.p
166330.53/22071.86	% SZS status Started for HL409104+4.p
166330.53/22071.86	% SZS status GaveUp for HL409104+4.p
166330.53/22071.86	eprover: CPU time limit exceeded, terminating
166330.53/22071.86	% SZS status Ended for HL409104+4.p
166335.05/22072.47	% SZS status Started for HL409097+5.p
166335.05/22072.47	% SZS status GaveUp for HL409097+5.p
166335.05/22072.47	eprover: CPU time limit exceeded, terminating
166335.05/22072.47	% SZS status Ended for HL409097+5.p
166346.25/22073.78	% SZS status Started for HL409105+4.p
166346.25/22073.78	% SZS status GaveUp for HL409105+4.p
166346.25/22073.78	eprover: CPU time limit exceeded, terminating
166346.25/22073.78	% SZS status Ended for HL409105+4.p
166348.61/22074.12	% SZS status Started for HL409098+5.p
166348.61/22074.12	% SZS status GaveUp for HL409098+5.p
166348.61/22074.12	eprover: CPU time limit exceeded, terminating
166348.61/22074.12	% SZS status Ended for HL409098+5.p
166359.73/22075.50	% SZS status Started for HL409106+4.p
166359.73/22075.50	% SZS status GaveUp for HL409106+4.p
166359.73/22075.50	eprover: CPU time limit exceeded, terminating
166359.73/22075.50	% SZS status Ended for HL409106+4.p
166361.95/22075.80	% SZS status Started for HL409099+5.p
166361.95/22075.80	% SZS status GaveUp for HL409099+5.p
166361.95/22075.80	eprover: CPU time limit exceeded, terminating
166361.95/22075.80	% SZS status Ended for HL409099+5.p
166373.16/22077.15	% SZS status Started for HL409107+4.p
166373.16/22077.15	% SZS status GaveUp for HL409107+4.p
166373.16/22077.15	eprover: CPU time limit exceeded, terminating
166373.16/22077.15	% SZS status Ended for HL409107+4.p
166379.39/22077.95	% SZS status Started for HL409102+5.p
166379.39/22077.95	% SZS status GaveUp for HL409102+5.p
166379.39/22077.95	eprover: CPU time limit exceeded, terminating
166379.39/22077.95	% SZS status Ended for HL409102+5.p
166386.12/22078.86	% SZS status Started for HL409108+4.p
166386.12/22078.86	% SZS status GaveUp for HL409108+4.p
166386.12/22078.86	eprover: CPU time limit exceeded, terminating
166386.12/22078.86	% SZS status Ended for HL409108+4.p
166388.28/22079.11	% SZS status Started for HL409103+5.p
166388.28/22079.11	% SZS status GaveUp for HL409103+5.p
166388.28/22079.11	eprover: CPU time limit exceeded, terminating
166388.28/22079.11	% SZS status Ended for HL409103+5.p
166403.39/22081.00	% SZS status Started for HL409109+4.p
166403.39/22081.00	% SZS status GaveUp for HL409109+4.p
166403.39/22081.00	eprover: CPU time limit exceeded, terminating
166403.39/22081.00	% SZS status Ended for HL409109+4.p
166405.45/22081.21	% SZS status Started for HL409104+5.p
166405.45/22081.21	% SZS status GaveUp for HL409104+5.p
166405.45/22081.21	eprover: CPU time limit exceeded, terminating
166405.45/22081.21	% SZS status Ended for HL409104+5.p
166412.17/22082.15	% SZS status Started for HL409110+4.p
166412.17/22082.15	% SZS status GaveUp for HL409110+4.p
166412.17/22082.15	eprover: CPU time limit exceeded, terminating
166412.17/22082.15	% SZS status Ended for HL409110+4.p
166422.39/22083.33	% SZS status Started for HL409105+5.p
166422.39/22083.33	% SZS status GaveUp for HL409105+5.p
166422.39/22083.33	eprover: CPU time limit exceeded, terminating
166422.39/22083.33	% SZS status Ended for HL409105+5.p
166429.25/22084.25	% SZS status Started for HL409111+4.p
166429.25/22084.25	% SZS status GaveUp for HL409111+4.p
166429.25/22084.25	eprover: CPU time limit exceeded, terminating
166429.25/22084.25	% SZS status Ended for HL409111+4.p
166434.73/22084.90	% SZS status Started for HL409106+5.p
166434.73/22084.90	% SZS status GaveUp for HL409106+5.p
166434.73/22084.90	eprover: CPU time limit exceeded, terminating
166434.73/22084.90	% SZS status Ended for HL409106+5.p
166446.11/22086.37	% SZS status Started for HL409112+4.p
166446.11/22086.37	% SZS status GaveUp for HL409112+4.p
166446.11/22086.37	eprover: CPU time limit exceeded, terminating
166446.11/22086.37	% SZS status Ended for HL409112+4.p
166448.05/22086.59	% SZS status Started for HL409107+5.p
166448.05/22086.59	% SZS status GaveUp for HL409107+5.p
166448.05/22086.59	eprover: CPU time limit exceeded, terminating
166448.05/22086.59	% SZS status Ended for HL409107+5.p
166458.48/22087.94	% SZS status Started for HL409114+4.p
166458.48/22087.94	% SZS status GaveUp for HL409114+4.p
166458.48/22087.94	eprover: CPU time limit exceeded, terminating
166458.48/22087.94	% SZS status Ended for HL409114+4.p
166465.58/22088.76	% SZS status Started for HL409108+5.p
166465.58/22088.76	% SZS status GaveUp for HL409108+5.p
166465.58/22088.76	eprover: CPU time limit exceeded, terminating
166465.58/22088.76	% SZS status Ended for HL409108+5.p
166471.48/22089.64	% SZS status Started for HL409115+4.p
166471.48/22089.64	% SZS status GaveUp for HL409115+4.p
166471.48/22089.64	eprover: CPU time limit exceeded, terminating
166471.48/22089.64	% SZS status Ended for HL409115+4.p
166475.17/22089.97	% SZS status Started for HL409109+5.p
166475.17/22089.97	% SZS status GaveUp for HL409109+5.p
166475.17/22089.97	eprover: CPU time limit exceeded, terminating
166475.17/22089.97	% SZS status Ended for HL409109+5.p
166490.91/22091.95	% SZS status Started for HL409116+4.p
166490.91/22091.95	% SZS status GaveUp for HL409116+4.p
166490.91/22091.95	eprover: CPU time limit exceeded, terminating
166490.91/22091.95	% SZS status Ended for HL409116+4.p
166491.55/22092.07	% SZS status Started for HL409110+5.p
166491.55/22092.07	% SZS status GaveUp for HL409110+5.p
166491.55/22092.07	eprover: CPU time limit exceeded, terminating
166491.55/22092.07	% SZS status Ended for HL409110+5.p
166498.91/22093.01	% SZS status Started for HL409117+4.p
166498.91/22093.01	% SZS status GaveUp for HL409117+4.p
166498.91/22093.01	eprover: CPU time limit exceeded, terminating
166498.91/22093.01	% SZS status Ended for HL409117+4.p
166500.61/22093.26	% SZS status Started for HL409111+5.p
166500.61/22093.26	% SZS status GaveUp for HL409111+5.p
166500.61/22093.26	eprover: CPU time limit exceeded, terminating
166500.61/22093.26	% SZS status Ended for HL409111+5.p
166515.59/22095.11	% SZS status Started for HL409118+4.p
166515.59/22095.11	% SZS status GaveUp for HL409118+4.p
166515.59/22095.11	eprover: CPU time limit exceeded, terminating
166515.59/22095.11	% SZS status Ended for HL409118+4.p
166517.31/22095.36	% SZS status Started for HL409112+5.p
166517.31/22095.36	% SZS status GaveUp for HL409112+5.p
166517.31/22095.36	eprover: CPU time limit exceeded, terminating
166517.31/22095.36	% SZS status Ended for HL409112+5.p
166526.45/22096.46	% SZS status Started for HL409119+4.p
166526.45/22096.46	% SZS status GaveUp for HL409119+4.p
166526.45/22096.46	eprover: CPU time limit exceeded, terminating
166526.45/22096.46	% SZS status Ended for HL409119+4.p
166534.27/22097.50	% SZS status Started for HL409114+5.p
166534.27/22097.50	% SZS status GaveUp for HL409114+5.p
166534.27/22097.50	eprover: CPU time limit exceeded, terminating
166534.27/22097.50	% SZS status Ended for HL409114+5.p
166542.59/22098.51	% SZS status Started for HL409120+4.p
166542.59/22098.51	% SZS status GaveUp for HL409120+4.p
166542.59/22098.51	eprover: CPU time limit exceeded, terminating
166542.59/22098.51	% SZS status Ended for HL409120+4.p
166547.02/22099.04	% SZS status Started for HL409115+5.p
166547.02/22099.04	% SZS status GaveUp for HL409115+5.p
166547.02/22099.04	eprover: CPU time limit exceeded, terminating
166547.02/22099.04	% SZS status Ended for HL409115+5.p
166559.02/22100.53	% SZS status Started for HL409121+4.p
166559.02/22100.53	% SZS status GaveUp for HL409121+4.p
166559.02/22100.53	eprover: CPU time limit exceeded, terminating
166559.02/22100.53	% SZS status Ended for HL409121+4.p
166560.28/22100.74	% SZS status Started for HL409116+5.p
166560.28/22100.74	% SZS status GaveUp for HL409116+5.p
166560.28/22100.74	eprover: CPU time limit exceeded, terminating
166560.28/22100.74	% SZS status Ended for HL409116+5.p
166571.36/22102.15	% SZS status Started for HL409122+4.p
166571.36/22102.15	% SZS status GaveUp for HL409122+4.p
166571.36/22102.15	eprover: CPU time limit exceeded, terminating
166571.36/22102.15	% SZS status Ended for HL409122+4.p
166579.30/22103.13	% SZS status Started for HL409117+5.p
166579.30/22103.13	% SZS status GaveUp for HL409117+5.p
166579.30/22103.13	eprover: CPU time limit exceeded, terminating
166579.30/22103.13	% SZS status Ended for HL409117+5.p
166584.77/22103.94	% SZS status Started for HL409123+4.p
166584.77/22103.94	% SZS status GaveUp for HL409123+4.p
166584.77/22103.94	eprover: CPU time limit exceeded, terminating
166584.77/22103.94	% SZS status Ended for HL409123+4.p
166586.95/22104.09	% SZS status Started for HL409118+5.p
166586.95/22104.09	% SZS status GaveUp for HL409118+5.p
166586.95/22104.09	eprover: CPU time limit exceeded, terminating
166586.95/22104.09	% SZS status Ended for HL409118+5.p
166603.48/22106.17	% SZS status Started for HL409124+4.p
166603.48/22106.17	% SZS status GaveUp for HL409124+4.p
166603.48/22106.17	eprover: CPU time limit exceeded, terminating
166603.48/22106.17	% SZS status Ended for HL409124+4.p
166603.48/22106.17	% SZS status Started for HL409119+5.p
166603.48/22106.17	% SZS status GaveUp for HL409119+5.p
166603.48/22106.17	eprover: CPU time limit exceeded, terminating
166603.48/22106.17	% SZS status Ended for HL409119+5.p
166611.08/22107.13	% SZS status Started for HL409125+4.p
166611.08/22107.13	% SZS status GaveUp for HL409125+4.p
166611.08/22107.13	eprover: CPU time limit exceeded, terminating
166611.08/22107.13	% SZS status Ended for HL409125+4.p
166614.77/22107.55	% SZS status Started for HL409120+5.p
166614.77/22107.55	% SZS status GaveUp for HL409120+5.p
166614.77/22107.55	eprover: CPU time limit exceeded, terminating
166614.77/22107.55	% SZS status Ended for HL409120+5.p
166627.52/22109.20	% SZS status Started for HL409126+4.p
166627.52/22109.20	% SZS status GaveUp for HL409126+4.p
166627.52/22109.20	eprover: CPU time limit exceeded, terminating
166627.52/22109.20	% SZS status Ended for HL409126+4.p
166631.23/22109.62	% SZS status Started for HL409121+5.p
166631.23/22109.62	% SZS status GaveUp for HL409121+5.p
166631.23/22109.62	eprover: CPU time limit exceeded, terminating
166631.23/22109.62	% SZS status Ended for HL409121+5.p
166638.73/22110.59	% SZS status Started for HL409127+4.p
166638.73/22110.59	% SZS status GaveUp for HL409127+4.p
166638.73/22110.59	eprover: CPU time limit exceeded, terminating
166638.73/22110.59	% SZS status Ended for HL409127+4.p
166647.19/22111.63	% SZS status Started for HL409122+5.p
166647.19/22111.63	% SZS status GaveUp for HL409122+5.p
166647.19/22111.63	eprover: CPU time limit exceeded, terminating
166647.19/22111.63	% SZS status Ended for HL409122+5.p
166655.31/22112.66	% SZS status Started for HL409128+4.p
166655.31/22112.66	% SZS status GaveUp for HL409128+4.p
166655.31/22112.66	eprover: CPU time limit exceeded, terminating
166655.31/22112.66	% SZS status Ended for HL409128+4.p
166661.11/22113.44	% SZS status Started for HL409123+5.p
166661.11/22113.44	% SZS status GaveUp for HL409123+5.p
166661.11/22113.44	eprover: CPU time limit exceeded, terminating
166661.11/22113.44	% SZS status Ended for HL409123+5.p
166671.00/22114.66	% SZS status Started for HL409129+4.p
166671.00/22114.66	% SZS status GaveUp for HL409129+4.p
166671.00/22114.66	eprover: CPU time limit exceeded, terminating
166671.00/22114.66	% SZS status Ended for HL409129+4.p
166676.12/22115.35	% SZS status Started for HL409124+5.p
166676.12/22115.35	% SZS status GaveUp for HL409124+5.p
166676.12/22115.35	eprover: CPU time limit exceeded, terminating
166676.12/22115.35	% SZS status Ended for HL409124+5.p
166685.00/22116.53	% SZS status Started for HL409130+4.p
166685.00/22116.53	% SZS status GaveUp for HL409130+4.p
166685.00/22116.53	eprover: CPU time limit exceeded, terminating
166685.00/22116.53	% SZS status Ended for HL409130+4.p
166691.69/22117.25	% SZS status Started for HL409125+5.p
166691.69/22117.25	% SZS status GaveUp for HL409125+5.p
166691.69/22117.25	eprover: CPU time limit exceeded, terminating
166691.69/22117.25	% SZS status Ended for HL409125+5.p
166698.91/22118.19	% SZS status Started for HL409126+5.p
166698.91/22118.19	% SZS status GaveUp for HL409126+5.p
166698.91/22118.19	eprover: CPU time limit exceeded, terminating
166698.91/22118.19	% SZS status Ended for HL409126+5.p
166700.66/22118.39	% SZS status Started for HL409132+4.p
166700.66/22118.39	% SZS status GaveUp for HL409132+4.p
166700.66/22118.39	eprover: CPU time limit exceeded, terminating
166700.66/22118.39	% SZS status Ended for HL409132+4.p
166715.86/22120.26	% SZS status Started for HL409127+5.p
166715.86/22120.26	% SZS status GaveUp for HL409127+5.p
166715.86/22120.26	eprover: CPU time limit exceeded, terminating
166715.86/22120.26	% SZS status Ended for HL409127+5.p
166715.86/22120.28	% SZS status Started for HL409133+4.p
166715.86/22120.28	% SZS status GaveUp for HL409133+4.p
166715.86/22120.28	eprover: CPU time limit exceeded, terminating
166715.86/22120.28	% SZS status Ended for HL409133+4.p
166724.45/22121.43	% SZS status Started for HL409134+4.p
166724.45/22121.43	% SZS status GaveUp for HL409134+4.p
166724.45/22121.43	eprover: CPU time limit exceeded, terminating
166724.45/22121.43	% SZS status Ended for HL409134+4.p
166726.27/22121.65	% SZS status Started for HL409128+5.p
166726.27/22121.65	% SZS status GaveUp for HL409128+5.p
166726.27/22121.65	eprover: CPU time limit exceeded, terminating
166726.27/22121.65	% SZS status Ended for HL409128+5.p
166739.58/22123.32	% SZS status Started for HL409135+4.p
166739.58/22123.32	% SZS status GaveUp for HL409135+4.p
166739.58/22123.32	eprover: CPU time limit exceeded, terminating
166739.58/22123.32	% SZS status Ended for HL409135+4.p
166743.14/22123.73	% SZS status Started for HL409129+5.p
166743.14/22123.73	% SZS status GaveUp for HL409129+5.p
166743.14/22123.73	eprover: CPU time limit exceeded, terminating
166743.14/22123.73	% SZS status Ended for HL409129+5.p
166751.72/22124.84	% SZS status Started for HL409137+4.p
166751.72/22124.84	% SZS status GaveUp for HL409137+4.p
166751.72/22124.84	eprover: CPU time limit exceeded, terminating
166751.72/22124.84	% SZS status Ended for HL409137+4.p
166762.25/22126.12	% SZS status Started for HL409130+5.p
166762.25/22126.12	% SZS status GaveUp for HL409130+5.p
166762.25/22126.12	eprover: CPU time limit exceeded, terminating
166762.25/22126.12	% SZS status Ended for HL409130+5.p
166766.86/22126.76	% SZS status Started for HL409139+4.p
166766.86/22126.76	% SZS status GaveUp for HL409139+4.p
166766.86/22126.76	eprover: CPU time limit exceeded, terminating
166766.86/22126.76	% SZS status Ended for HL409139+4.p
166772.80/22127.61	% SZS status Started for HL409132+5.p
166772.80/22127.61	% SZS status GaveUp for HL409132+5.p
166772.80/22127.61	eprover: CPU time limit exceeded, terminating
166772.80/22127.61	% SZS status Ended for HL409132+5.p
166786.16/22129.25	% SZS status Started for HL409133+5.p
166786.16/22129.25	% SZS status GaveUp for HL409133+5.p
166786.16/22129.25	eprover: CPU time limit exceeded, terminating
166786.16/22129.25	% SZS status Ended for HL409133+5.p
166787.16/22129.32	% SZS status Started for HL409140+4.p
166787.16/22129.32	% SZS status GaveUp for HL409140+4.p
166787.16/22129.32	eprover: CPU time limit exceeded, terminating
166787.16/22129.32	% SZS status Ended for HL409140+4.p
166797.25/22130.65	% SZS status Started for HL409141+4.p
166797.25/22130.65	% SZS status GaveUp for HL409141+4.p
166797.25/22130.65	eprover: CPU time limit exceeded, terminating
166797.25/22130.65	% SZS status Ended for HL409141+4.p
166804.16/22131.38	% SZS status Started for HL409134+5.p
166804.16/22131.38	% SZS status GaveUp for HL409134+5.p
166804.16/22131.38	eprover: CPU time limit exceeded, terminating
166804.16/22131.38	% SZS status Ended for HL409134+5.p
166812.61/22132.50	% SZS status Started for HL409135+5.p
166812.61/22132.50	% SZS status GaveUp for HL409135+5.p
166812.61/22132.50	eprover: CPU time limit exceeded, terminating
166812.61/22132.50	% SZS status Ended for HL409135+5.p
166812.95/22132.52	% SZS status Started for HL409142+4.p
166812.95/22132.52	% SZS status GaveUp for HL409142+4.p
166812.95/22132.52	eprover: CPU time limit exceeded, terminating
166812.95/22132.52	% SZS status Ended for HL409142+4.p
166828.03/22134.42	% SZS status Started for HL409143+4.p
166828.03/22134.42	% SZS status GaveUp for HL409143+4.p
166828.03/22134.42	eprover: CPU time limit exceeded, terminating
166828.03/22134.42	% SZS status Ended for HL409143+4.p
166828.03/22134.42	% SZS status Started for HL409137+5.p
166828.03/22134.42	% SZS status GaveUp for HL409137+5.p
166828.03/22134.42	eprover: CPU time limit exceeded, terminating
166828.03/22134.42	% SZS status Ended for HL409137+5.p
166836.77/22135.57	% SZS status Started for HL409144+4.p
166836.77/22135.57	% SZS status GaveUp for HL409144+4.p
166836.77/22135.57	eprover: CPU time limit exceeded, terminating
166836.77/22135.57	% SZS status Ended for HL409144+4.p
166840.00/22135.93	% SZS status Started for HL409139+5.p
166840.00/22135.93	% SZS status GaveUp for HL409139+5.p
166840.00/22135.93	eprover: CPU time limit exceeded, terminating
166840.00/22135.93	% SZS status Ended for HL409139+5.p
166851.77/22137.45	% SZS status Started for HL409145+4.p
166851.77/22137.45	% SZS status GaveUp for HL409145+4.p
166851.77/22137.45	eprover: CPU time limit exceeded, terminating
166851.77/22137.45	% SZS status Ended for HL409145+4.p
166855.05/22137.84	% SZS status Started for HL409140+5.p
166855.05/22137.84	% SZS status GaveUp for HL409140+5.p
166855.05/22137.84	eprover: CPU time limit exceeded, terminating
166855.05/22137.84	% SZS status Ended for HL409140+5.p
166863.72/22138.97	% SZS status Started for HL409146+4.p
166863.72/22138.97	% SZS status GaveUp for HL409146+4.p
166863.72/22138.97	eprover: CPU time limit exceeded, terminating
166863.72/22138.97	% SZS status Ended for HL409146+4.p
166874.17/22140.32	% SZS status Started for HL409141+5.p
166874.17/22140.32	% SZS status GaveUp for HL409141+5.p
166874.17/22140.32	eprover: CPU time limit exceeded, terminating
166874.17/22140.32	% SZS status Ended for HL409141+5.p
166879.31/22140.88	% SZS status Started for HL409147+4.p
166879.31/22140.88	% SZS status GaveUp for HL409147+4.p
166879.31/22140.88	eprover: CPU time limit exceeded, terminating
166879.31/22140.88	% SZS status Ended for HL409147+4.p
166885.94/22141.73	% SZS status Started for HL409142+5.p
166885.94/22141.73	% SZS status GaveUp for HL409142+5.p
166885.94/22141.73	eprover: CPU time limit exceeded, terminating
166885.94/22141.73	% SZS status Ended for HL409142+5.p
166899.19/22143.38	% SZS status Started for HL409148+4.p
166899.19/22143.38	% SZS status GaveUp for HL409148+4.p
166899.19/22143.38	eprover: CPU time limit exceeded, terminating
166899.19/22143.38	% SZS status Ended for HL409148+4.p
166904.59/22144.02	% SZS status Started for HL409143+5.p
166904.59/22144.02	% SZS status GaveUp for HL409143+5.p
166904.59/22144.02	eprover: CPU time limit exceeded, terminating
166904.59/22144.02	% SZS status Ended for HL409143+5.p
166909.00/22144.75	% SZS status Started for HL409149+4.p
166909.00/22144.75	% SZS status GaveUp for HL409149+4.p
166909.00/22144.75	eprover: CPU time limit exceeded, terminating
166909.00/22144.75	% SZS status Ended for HL409149+4.p
166915.36/22145.45	% SZS status Started for HL409144+5.p
166915.36/22145.45	% SZS status GaveUp for HL409144+5.p
166915.36/22145.45	eprover: CPU time limit exceeded, terminating
166915.36/22145.45	% SZS status Ended for HL409144+5.p
166924.23/22146.55	% SZS status Started for HL409145+5.p
166924.23/22146.55	% SZS status GaveUp for HL409145+5.p
166924.23/22146.55	eprover: CPU time limit exceeded, terminating
166924.23/22146.55	% SZS status Ended for HL409145+5.p
166928.28/22147.06	% SZS status Started for HL409150+4.p
166928.28/22147.06	% SZS status GaveUp for HL409150+4.p
166928.28/22147.06	eprover: CPU time limit exceeded, terminating
166928.28/22147.06	% SZS status Ended for HL409150+4.p
166939.53/22148.40	% SZS status Started for HL409146+5.p
166939.53/22148.40	% SZS status GaveUp for HL409146+5.p
166939.53/22148.40	eprover: CPU time limit exceeded, terminating
166939.53/22148.40	% SZS status Ended for HL409146+5.p
166939.97/22148.51	% SZS status Started for HL409151+4.p
166939.97/22148.51	% SZS status GaveUp for HL409151+4.p
166939.97/22148.51	eprover: CPU time limit exceeded, terminating
166939.97/22148.51	% SZS status Ended for HL409151+4.p
166946.92/22149.44	% SZS status Started for HL409147+5.p
166946.92/22149.44	% SZS status GaveUp for HL409147+5.p
166946.92/22149.44	eprover: CPU time limit exceeded, terminating
166946.92/22149.44	% SZS status Ended for HL409147+5.p
166953.22/22150.13	% SZS status Started for HL409152+4.p
166953.22/22150.13	% SZS status GaveUp for HL409152+4.p
166953.22/22150.13	eprover: CPU time limit exceeded, terminating
166953.22/22150.13	% SZS status Ended for HL409152+4.p
166964.14/22151.53	% SZS status Started for HL409153+4.p
166964.14/22151.53	% SZS status GaveUp for HL409153+4.p
166964.14/22151.53	eprover: CPU time limit exceeded, terminating
166964.14/22151.53	% SZS status Ended for HL409153+4.p
166977.34/22153.16	% SZS status Started for HL409154+4.p
166977.34/22153.16	% SZS status GaveUp for HL409154+4.p
166977.34/22153.16	eprover: CPU time limit exceeded, terminating
166977.34/22153.16	% SZS status Ended for HL409154+4.p
166980.30/22153.59	% SZS status Started for HL409149+5.p
166980.30/22153.59	% SZS status GaveUp for HL409149+5.p
166980.30/22153.59	eprover: CPU time limit exceeded, terminating
166980.30/22153.59	% SZS status Ended for HL409149+5.p
167000.61/22156.19	% SZS status Started for HL409155+4.p
167000.61/22156.19	% SZS status GaveUp for HL409155+4.p
167000.61/22156.19	eprover: CPU time limit exceeded, terminating
167000.61/22156.19	% SZS status Ended for HL409155+4.p
167006.28/22156.84	% SZS status Started for HL409151+5.p
167006.28/22156.84	% SZS status GaveUp for HL409151+5.p
167006.28/22156.84	eprover: CPU time limit exceeded, terminating
167006.28/22156.84	% SZS status Ended for HL409151+5.p
167025.81/22159.25	% SZS status Started for HL409156+4.p
167025.81/22159.25	% SZS status GaveUp for HL409156+4.p
167025.81/22159.25	eprover: CPU time limit exceeded, terminating
167025.81/22159.25	% SZS status Ended for HL409156+4.p
167049.81/22162.28	% SZS status Started for HL409157+4.p
167049.81/22162.28	% SZS status GaveUp for HL409157+4.p
167049.81/22162.28	eprover: CPU time limit exceeded, terminating
167049.81/22162.28	% SZS status Ended for HL409157+4.p
167087.06/22167.01	% SZS status Started for HL409148+5.p
167087.06/22167.01	% SZS status GaveUp for HL409148+5.p
167087.06/22167.01	eprover: CPU time limit exceeded, terminating
167087.06/22167.01	% SZS status Ended for HL409148+5.p
167111.77/22170.06	% SZS status Started for HL409159+4.p
167111.77/22170.06	% SZS status GaveUp for HL409159+4.p
167111.77/22170.06	eprover: CPU time limit exceeded, terminating
167111.77/22170.06	% SZS status Ended for HL409159+4.p
167119.89/22171.13	% SZS status Started for HL409150+5.p
167119.89/22171.13	% SZS status GaveUp for HL409150+5.p
167119.89/22171.13	eprover: CPU time limit exceeded, terminating
167119.89/22171.13	% SZS status Ended for HL409150+5.p
167134.05/22172.93	% SZS status Started for HL409157+5.p
167134.05/22172.93	% SZS status GaveUp for HL409157+5.p
167134.05/22172.93	eprover: CPU time limit exceeded, terminating
167134.05/22172.93	% SZS status Ended for HL409157+5.p
167144.27/22174.17	% SZS status Started for HL409160+4.p
167144.27/22174.17	% SZS status GaveUp for HL409160+4.p
167144.27/22174.17	eprover: CPU time limit exceeded, terminating
167144.27/22174.17	% SZS status Ended for HL409160+4.p
167147.52/22174.57	% SZS status Started for HL409152+5.p
167147.52/22174.57	% SZS status GaveUp for HL409152+5.p
167147.52/22174.57	eprover: CPU time limit exceeded, terminating
167147.52/22174.57	% SZS status Ended for HL409152+5.p
167156.55/22175.73	% SZS status Started for HL409153+5.p
167156.55/22175.73	% SZS status GaveUp for HL409153+5.p
167156.55/22175.73	eprover: CPU time limit exceeded, terminating
167156.55/22175.73	% SZS status Ended for HL409153+5.p
167167.16/22177.22	% SZS status Started for HL409161+4.p
167167.16/22177.22	% SZS status GaveUp for HL409161+4.p
167167.16/22177.22	eprover: CPU time limit exceeded, terminating
167167.16/22177.22	% SZS status Ended for HL409161+4.p
167171.86/22177.65	% SZS status Started for HL409154+5.p
167171.86/22177.65	% SZS status GaveUp for HL409154+5.p
167171.86/22177.65	eprover: CPU time limit exceeded, terminating
167171.86/22177.65	% SZS status Ended for HL409154+5.p
167180.45/22178.79	% SZS status Started for HL409162+4.p
167180.45/22178.79	% SZS status GaveUp for HL409162+4.p
167180.45/22178.79	eprover: CPU time limit exceeded, terminating
167180.45/22178.79	% SZS status Ended for HL409162+4.p
167189.91/22179.94	% SZS status Started for HL409155+5.p
167189.91/22179.94	% SZS status GaveUp for HL409155+5.p
167189.91/22179.94	eprover: CPU time limit exceeded, terminating
167189.91/22179.94	% SZS status Ended for HL409155+5.p
167194.77/22180.56	% SZS status Started for HL409159+5.p
167194.77/22180.56	% SZS status GaveUp for HL409159+5.p
167194.77/22180.56	eprover: CPU time limit exceeded, terminating
167194.77/22180.56	% SZS status Ended for HL409159+5.p
167196.03/22180.69	% SZS status Started for HL409164+4.p
167196.03/22180.69	% SZS status GaveUp for HL409164+4.p
167196.03/22180.69	eprover: CPU time limit exceeded, terminating
167196.03/22180.69	% SZS status Ended for HL409164+4.p
167214.16/22182.99	% SZS status Started for HL409165+4.p
167214.16/22182.99	% SZS status GaveUp for HL409165+4.p
167214.16/22182.99	eprover: CPU time limit exceeded, terminating
167214.16/22182.99	% SZS status Ended for HL409165+4.p
167214.16/22183.05	% SZS status Started for HL409156+5.p
167214.16/22183.05	% SZS status GaveUp for HL409156+5.p
167214.16/22183.05	eprover: CPU time limit exceeded, terminating
167214.16/22183.05	% SZS status Ended for HL409156+5.p
167215.28/22183.22	% SZS status Started for HL409160+5.p
167215.28/22183.22	% SZS status GaveUp for HL409160+5.p
167215.28/22183.22	eprover: CPU time limit exceeded, terminating
167215.28/22183.22	% SZS status Ended for HL409160+5.p
167220.28/22183.77	% SZS status Started for HL409166+4.p
167220.28/22183.77	% SZS status GaveUp for HL409166+4.p
167220.28/22183.77	eprover: CPU time limit exceeded, terminating
167220.28/22183.77	% SZS status Ended for HL409166+4.p
167229.95/22185.00	% SZS status Started for HL409161+5.p
167229.95/22185.00	% SZS status GaveUp for HL409161+5.p
167229.95/22185.00	eprover: CPU time limit exceeded, terminating
167229.95/22185.00	% SZS status Ended for HL409161+5.p
167238.91/22186.10	% SZS status Started for HL409167+4.p
167238.91/22186.10	% SZS status GaveUp for HL409167+4.p
167238.91/22186.10	eprover: CPU time limit exceeded, terminating
167238.91/22186.10	% SZS status Ended for HL409167+4.p
167244.06/22186.80	% SZS status Started for HL409168+4.p
167244.06/22186.80	% SZS status GaveUp for HL409168+4.p
167244.06/22186.80	eprover: CPU time limit exceeded, terminating
167244.06/22186.80	% SZS status Ended for HL409168+4.p
167249.56/22187.44	% SZS status Started for HL409162+5.p
167249.56/22187.44	% SZS status GaveUp for HL409162+5.p
167249.56/22187.44	eprover: CPU time limit exceeded, terminating
167249.56/22187.44	% SZS status Ended for HL409162+5.p
167261.86/22189.02	% SZS status Started for HL409164+5.p
167261.86/22189.02	% SZS status GaveUp for HL409164+5.p
167261.86/22189.02	eprover: CPU time limit exceeded, terminating
167261.86/22189.02	% SZS status Ended for HL409164+5.p
167262.94/22189.15	% SZS status Started for HL409169+4.p
167262.94/22189.15	% SZS status GaveUp for HL409169+4.p
167262.94/22189.15	eprover: CPU time limit exceeded, terminating
167262.94/22189.15	% SZS status Ended for HL409169+4.p
167273.22/22190.54	% SZS status Started for HL409170+4.p
167273.22/22190.54	% SZS status GaveUp for HL409170+4.p
167273.22/22190.54	eprover: CPU time limit exceeded, terminating
167273.22/22190.54	% SZS status Ended for HL409170+4.p
167287.62/22192.26	% SZS status Started for HL409171+4.p
167287.62/22192.26	% SZS status GaveUp for HL409171+4.p
167287.62/22192.26	eprover: CPU time limit exceeded, terminating
167287.62/22192.26	% SZS status Ended for HL409171+4.p
167311.50/22195.33	% SZS status Started for HL409168+5.p
167311.50/22195.33	% SZS status GaveUp for HL409168+5.p
167311.50/22195.33	eprover: CPU time limit exceeded, terminating
167311.50/22195.33	% SZS status Ended for HL409168+5.p
167312.25/22195.35	% SZS status Started for HL409172+4.p
167312.25/22195.35	% SZS status GaveUp for HL409172+4.p
167312.25/22195.35	eprover: CPU time limit exceeded, terminating
167312.25/22195.35	% SZS status Ended for HL409172+4.p
167326.78/22197.18	% SZS status Started for HL409169+5.p
167326.78/22197.18	% SZS status GaveUp for HL409169+5.p
167326.78/22197.18	eprover: CPU time limit exceeded, terminating
167326.78/22197.18	% SZS status Ended for HL409169+5.p
167336.42/22198.39	% SZS status Started for HL409173+4.p
167336.42/22198.39	% SZS status GaveUp for HL409173+4.p
167336.42/22198.39	eprover: CPU time limit exceeded, terminating
167336.42/22198.39	% SZS status Ended for HL409173+4.p
167345.73/22199.54	% SZS status Started for HL409170+5.p
167345.73/22199.54	% SZS status GaveUp for HL409170+5.p
167345.73/22199.54	eprover: CPU time limit exceeded, terminating
167345.73/22199.54	% SZS status Ended for HL409170+5.p
167355.34/22200.82	% SZS status Started for HL409171+5.p
167355.34/22200.82	% SZS status GaveUp for HL409171+5.p
167355.34/22200.82	eprover: CPU time limit exceeded, terminating
167355.34/22200.82	% SZS status Ended for HL409171+5.p
167360.09/22201.41	% SZS status Started for HL409174+4.p
167360.09/22201.41	% SZS status GaveUp for HL409174+4.p
167360.09/22201.41	eprover: CPU time limit exceeded, terminating
167360.09/22201.41	% SZS status Ended for HL409174+4.p
167377.48/22203.86	% SZS status Started for HL409177+4.p
167377.48/22203.86	% SZS status GaveUp for HL409177+4.p
167377.48/22203.86	eprover: CPU time limit exceeded, terminating
167377.48/22203.86	% SZS status Ended for HL409177+4.p
167404.11/22206.92	% SZS status Started for HL409178+4.p
167404.11/22206.92	% SZS status GaveUp for HL409178+4.p
167404.11/22206.92	eprover: CPU time limit exceeded, terminating
167404.11/22206.92	% SZS status Ended for HL409178+4.p
167404.11/22206.95	% SZS status Started for HL409165+5.p
167404.11/22206.95	% SZS status GaveUp for HL409165+5.p
167404.11/22206.95	eprover: CPU time limit exceeded, terminating
167404.11/22206.95	% SZS status Ended for HL409165+5.p
167408.70/22207.53	% SZS status Started for HL409173+5.p
167408.70/22207.53	% SZS status GaveUp for HL409173+5.p
167408.70/22207.53	eprover: CPU time limit exceeded, terminating
167408.70/22207.53	% SZS status Ended for HL409173+5.p
167422.62/22209.20	% SZS status Started for HL409166+5.p
167422.62/22209.20	% SZS status GaveUp for HL409166+5.p
167422.62/22209.20	eprover: CPU time limit exceeded, terminating
167422.62/22209.20	% SZS status Ended for HL409166+5.p
167423.56/22209.37	% SZS status Started for HL409167+5.p
167423.56/22209.37	% SZS status GaveUp for HL409167+5.p
167423.56/22209.37	eprover: CPU time limit exceeded, terminating
167423.56/22209.37	% SZS status Ended for HL409167+5.p
167428.05/22209.98	% SZS status Started for HL409179+4.p
167428.05/22209.98	% SZS status GaveUp for HL409179+4.p
167428.05/22209.98	eprover: CPU time limit exceeded, terminating
167428.05/22209.98	% SZS status Ended for HL409179+4.p
167432.06/22210.45	% SZS status Started for HL409174+5.p
167432.06/22210.45	% SZS status GaveUp for HL409174+5.p
167432.06/22210.45	eprover: CPU time limit exceeded, terminating
167432.06/22210.45	% SZS status Ended for HL409174+5.p
167440.67/22211.54	% SZS status Started for HL409177+5.p
167440.67/22211.54	% SZS status GaveUp for HL409177+5.p
167440.67/22211.54	eprover: CPU time limit exceeded, terminating
167440.67/22211.54	% SZS status Ended for HL409177+5.p
167446.61/22212.23	% SZS status Started for HL409180+4.p
167446.61/22212.23	% SZS status GaveUp for HL409180+4.p
167446.61/22212.23	eprover: CPU time limit exceeded, terminating
167446.61/22212.23	% SZS status Ended for HL409180+4.p
167452.61/22213.02	% SZS status Started for HL409181+4.p
167452.61/22213.02	% SZS status GaveUp for HL409181+4.p
167452.61/22213.02	eprover: CPU time limit exceeded, terminating
167452.61/22213.02	% SZS status Ended for HL409181+4.p
167464.58/22214.57	% SZS status Started for HL409182+4.p
167464.58/22214.57	% SZS status GaveUp for HL409182+4.p
167464.58/22214.57	eprover: CPU time limit exceeded, terminating
167464.58/22214.57	% SZS status Ended for HL409182+4.p
167476.28/22216.05	% SZS status Started for HL409183+4.p
167476.28/22216.05	% SZS status GaveUp for HL409183+4.p
167476.28/22216.05	eprover: CPU time limit exceeded, terminating
167476.28/22216.05	% SZS status Ended for HL409183+4.p
167485.78/22217.28	% SZS status Started for HL409178+5.p
167485.78/22217.28	% SZS status GaveUp for HL409178+5.p
167485.78/22217.28	eprover: CPU time limit exceeded, terminating
167485.78/22217.28	% SZS status Ended for HL409178+5.p
167491.80/22218.01	% SZS status Started for HL409179+5.p
167491.80/22218.01	% SZS status GaveUp for HL409179+5.p
167491.80/22218.01	eprover: CPU time limit exceeded, terminating
167491.80/22218.01	% SZS status Ended for HL409179+5.p
167501.36/22219.15	% SZS status Started for HL409184+4.p
167501.36/22219.15	% SZS status GaveUp for HL409184+4.p
167501.36/22219.15	eprover: CPU time limit exceeded, terminating
167501.36/22219.15	% SZS status Ended for HL409184+4.p
167505.86/22219.75	% SZS status Started for HL409180+5.p
167505.86/22219.75	% SZS status GaveUp for HL409180+5.p
167505.86/22219.75	eprover: CPU time limit exceeded, terminating
167505.86/22219.75	% SZS status Ended for HL409180+5.p
167516.28/22221.06	% SZS status Started for HL409185+4.p
167516.28/22221.06	% SZS status GaveUp for HL409185+4.p
167516.28/22221.06	eprover: CPU time limit exceeded, terminating
167516.28/22221.06	% SZS status Ended for HL409185+4.p
167519.92/22221.51	% SZS status Started for HL409172+5.p
167519.92/22221.51	% SZS status GaveUp for HL409172+5.p
167519.92/22221.51	eprover: CPU time limit exceeded, terminating
167519.92/22221.51	% SZS status Ended for HL409172+5.p
167527.00/22222.42	% SZS status Started for HL409182+5.p
167527.00/22222.42	% SZS status GaveUp for HL409182+5.p
167527.00/22222.42	eprover: CPU time limit exceeded, terminating
167527.00/22222.42	% SZS status Ended for HL409182+5.p
167530.03/22222.78	% SZS status Started for HL409186+4.p
167530.03/22222.78	% SZS status GaveUp for HL409186+4.p
167530.03/22222.78	eprover: CPU time limit exceeded, terminating
167530.03/22222.78	% SZS status Ended for HL409186+4.p
167543.80/22224.60	% SZS status Started for HL409187+4.p
167543.80/22224.60	% SZS status GaveUp for HL409187+4.p
167543.80/22224.60	eprover: CPU time limit exceeded, terminating
167543.80/22224.60	% SZS status Ended for HL409187+4.p
167553.83/22225.82	% SZS status Started for HL409188+4.p
167553.83/22225.82	% SZS status GaveUp for HL409188+4.p
167553.83/22225.82	eprover: CPU time limit exceeded, terminating
167553.83/22225.82	% SZS status Ended for HL409188+4.p
167578.45/22228.87	% SZS status Started for HL409190+4.p
167578.45/22228.87	% SZS status GaveUp for HL409190+4.p
167578.45/22228.87	eprover: CPU time limit exceeded, terminating
167578.45/22228.87	% SZS status Ended for HL409190+4.p
167583.27/22229.48	% SZS status Started for HL409185+5.p
167583.27/22229.48	% SZS status GaveUp for HL409185+5.p
167583.27/22229.48	eprover: CPU time limit exceeded, terminating
167583.27/22229.48	% SZS status Ended for HL409185+5.p
167598.36/22231.41	% SZS status Started for HL409186+5.p
167598.36/22231.41	% SZS status GaveUp for HL409186+5.p
167598.36/22231.41	eprover: CPU time limit exceeded, terminating
167598.36/22231.41	% SZS status Ended for HL409186+5.p
167607.59/22232.52	% SZS status Started for HL409191+4.p
167607.59/22232.52	% SZS status GaveUp for HL409191+4.p
167607.59/22232.52	eprover: CPU time limit exceeded, terminating
167607.59/22232.52	% SZS status Ended for HL409191+4.p
167631.08/22235.59	% SZS status Started for HL409192+4.p
167631.08/22235.59	% SZS status GaveUp for HL409192+4.p
167631.08/22235.59	eprover: CPU time limit exceeded, terminating
167631.08/22235.59	% SZS status Ended for HL409192+4.p
167639.59/22236.65	% SZS status Started for HL409181+5.p
167639.59/22236.65	% SZS status GaveUp for HL409181+5.p
167639.59/22236.65	eprover: CPU time limit exceeded, terminating
167639.59/22236.65	% SZS status Ended for HL409181+5.p
167655.42/22238.61	% SZS status Started for HL409187+5.p
167655.42/22238.61	% SZS status GaveUp for HL409187+5.p
167655.42/22238.61	eprover: CPU time limit exceeded, terminating
167655.42/22238.61	% SZS status Ended for HL409187+5.p
167661.27/22239.30	% SZS status Started for HL409190+5.p
167661.27/22239.30	% SZS status GaveUp for HL409190+5.p
167661.27/22239.30	eprover: CPU time limit exceeded, terminating
167661.27/22239.30	% SZS status Ended for HL409190+5.p
167665.00/22239.80	% SZS status Started for HL409193+4.p
167665.00/22239.80	% SZS status GaveUp for HL409193+4.p
167665.00/22239.80	eprover: CPU time limit exceeded, terminating
167665.00/22239.80	% SZS status Ended for HL409193+4.p
167672.16/22240.77	% SZS status Started for HL409183+5.p
167672.16/22240.77	% SZS status GaveUp for HL409183+5.p
167672.16/22240.77	eprover: CPU time limit exceeded, terminating
167672.16/22240.77	% SZS status Ended for HL409183+5.p
167679.59/22241.63	% SZS status Started for HL409191+5.p
167679.59/22241.63	% SZS status GaveUp for HL409191+5.p
167679.59/22241.63	eprover: CPU time limit exceeded, terminating
167679.59/22241.63	% SZS status Ended for HL409191+5.p
167685.36/22242.35	% SZS status Started for HL409194+4.p
167685.36/22242.35	% SZS status GaveUp for HL409194+4.p
167685.36/22242.35	eprover: CPU time limit exceeded, terminating
167685.36/22242.35	% SZS status Ended for HL409194+4.p
167694.83/22243.58	% SZS status Started for HL409184+5.p
167694.83/22243.58	% SZS status GaveUp for HL409184+5.p
167694.83/22243.58	eprover: CPU time limit exceeded, terminating
167694.83/22243.58	% SZS status Ended for HL409184+5.p
167696.97/22243.89	% SZS status Started for HL409195+4.p
167696.97/22243.89	% SZS status GaveUp for HL409195+4.p
167696.97/22243.89	eprover: CPU time limit exceeded, terminating
167696.97/22243.89	% SZS status Ended for HL409195+4.p
167709.11/22245.40	% SZS status Started for HL409196+4.p
167709.11/22245.40	% SZS status GaveUp for HL409196+4.p
167709.11/22245.40	eprover: CPU time limit exceeded, terminating
167709.11/22245.40	% SZS status Ended for HL409196+4.p
167712.17/22245.78	% SZS status Started for HL409192+5.p
167712.17/22245.78	% SZS status GaveUp for HL409192+5.p
167712.17/22245.78	eprover: CPU time limit exceeded, terminating
167712.17/22245.78	% SZS status Ended for HL409192+5.p
167721.28/22246.93	% SZS status Started for HL409197+4.p
167721.28/22246.93	% SZS status GaveUp for HL409197+4.p
167721.28/22246.93	eprover: CPU time limit exceeded, terminating
167721.28/22246.93	% SZS status Ended for HL409197+4.p
167735.53/22248.84	% SZS status Started for HL409199+4.p
167735.53/22248.84	% SZS status GaveUp for HL409199+4.p
167735.53/22248.84	eprover: CPU time limit exceeded, terminating
167735.53/22248.84	% SZS status Ended for HL409199+4.p
167745.41/22250.05	% SZS status Started for HL409194+5.p
167745.41/22250.05	% SZS status GaveUp for HL409194+5.p
167745.41/22250.05	eprover: CPU time limit exceeded, terminating
167745.41/22250.05	% SZS status Ended for HL409194+5.p
167754.27/22251.14	% SZS status Started for HL409188+5.p
167754.27/22251.14	% SZS status GaveUp for HL409188+5.p
167754.27/22251.14	eprover: CPU time limit exceeded, terminating
167754.27/22251.14	% SZS status Ended for HL409188+5.p
167759.80/22251.79	% SZS status Started for HL409195+5.p
167759.80/22251.79	% SZS status GaveUp for HL409195+5.p
167759.80/22251.79	eprover: CPU time limit exceeded, terminating
167759.80/22251.79	% SZS status Ended for HL409195+5.p
167760.34/22251.89	% SZS status Started for HL409200+4.p
167760.34/22251.89	% SZS status GaveUp for HL409200+4.p
167760.34/22251.89	eprover: CPU time limit exceeded, terminating
167760.34/22251.89	% SZS status Ended for HL409200+4.p
167778.31/22254.18	% SZS status Started for HL409201+4.p
167778.31/22254.18	% SZS status GaveUp for HL409201+4.p
167778.31/22254.18	eprover: CPU time limit exceeded, terminating
167778.31/22254.18	% SZS status Ended for HL409201+4.p
167785.03/22254.92	% SZS status Started for HL409202+4.p
167785.03/22254.92	% SZS status GaveUp for HL409202+4.p
167785.03/22254.92	eprover: CPU time limit exceeded, terminating
167785.03/22254.92	% SZS status Ended for HL409202+4.p
167791.67/22255.78	% SZS status Started for HL409197+5.p
167791.67/22255.78	% SZS status GaveUp for HL409197+5.p
167791.67/22255.78	eprover: CPU time limit exceeded, terminating
167791.67/22255.78	% SZS status Ended for HL409197+5.p
167807.67/22257.96	% SZS status Started for HL409203+4.p
167807.67/22257.96	% SZS status GaveUp for HL409203+4.p
167807.67/22257.96	eprover: CPU time limit exceeded, terminating
167807.67/22257.96	% SZS status Ended for HL409203+4.p
167830.41/22260.62	% SZS status Started for HL409200+5.p
167830.41/22260.62	% SZS status GaveUp for HL409200+5.p
167830.41/22260.62	eprover: CPU time limit exceeded, terminating
167830.41/22260.62	% SZS status Ended for HL409200+5.p
167832.81/22260.99	% SZS status Started for HL409204+4.p
167832.81/22260.99	% SZS status GaveUp for HL409204+4.p
167832.81/22260.99	eprover: CPU time limit exceeded, terminating
167832.81/22260.99	% SZS status Ended for HL409204+4.p
167847.64/22262.69	% SZS status Started for HL409201+5.p
167847.64/22262.69	% SZS status GaveUp for HL409201+5.p
167847.64/22262.69	eprover: CPU time limit exceeded, terminating
167847.64/22262.69	% SZS status Ended for HL409201+5.p
167858.11/22264.03	% SZS status Started for HL409205+4.p
167858.11/22264.03	% SZS status GaveUp for HL409205+4.p
167858.11/22264.03	eprover: CPU time limit exceeded, terminating
167858.11/22264.03	% SZS status Ended for HL409205+4.p
167863.45/22264.67	% SZS status Started for HL409202+5.p
167863.45/22264.67	% SZS status GaveUp for HL409202+5.p
167863.45/22264.67	eprover: CPU time limit exceeded, terminating
167863.45/22264.67	% SZS status Ended for HL409202+5.p
167866.38/22265.05	% SZS status Started for HL409193+5.p
167866.38/22265.05	% SZS status GaveUp for HL409193+5.p
167866.38/22265.05	eprover: CPU time limit exceeded, terminating
167866.38/22265.05	% SZS status Ended for HL409193+5.p
167873.45/22266.02	% SZS status Started for HL409203+5.p
167873.45/22266.02	% SZS status GaveUp for HL409203+5.p
167873.45/22266.02	eprover: CPU time limit exceeded, terminating
167873.45/22266.02	% SZS status Ended for HL409203+5.p
167881.86/22267.06	% SZS status Started for HL409206+4.p
167881.86/22267.06	% SZS status GaveUp for HL409206+4.p
167881.86/22267.06	eprover: CPU time limit exceeded, terminating
167881.86/22267.06	% SZS status Ended for HL409206+4.p
167890.27/22268.09	% SZS status Started for HL409207+4.p
167890.27/22268.09	% SZS status GaveUp for HL409207+4.p
167890.27/22268.09	eprover: CPU time limit exceeded, terminating
167890.27/22268.09	% SZS status Ended for HL409207+4.p
167907.72/22269.91	% SZS status Started for HL409196+5.p
167907.72/22269.91	% SZS status GaveUp for HL409196+5.p
167907.72/22269.91	eprover: CPU time limit exceeded, terminating
167907.72/22269.91	% SZS status Ended for HL409196+5.p
167909.16/22270.09	% SZS status Started for HL409209+4.p
167909.16/22270.09	% SZS status GaveUp for HL409209+4.p
167909.16/22270.09	eprover: CPU time limit exceeded, terminating
167909.16/22270.09	% SZS status Ended for HL409209+4.p
167915.12/22270.89	% SZS status Started for HL409204+5.p
167915.12/22270.89	% SZS status GaveUp for HL409204+5.p
167915.12/22270.89	eprover: CPU time limit exceeded, terminating
167915.12/22270.89	% SZS status Ended for HL409204+5.p
167932.59/22273.03	% SZS status Started for HL409210+4.p
167932.59/22273.03	% SZS status GaveUp for HL409210+4.p
167932.59/22273.03	eprover: CPU time limit exceeded, terminating
167932.59/22273.03	% SZS status Ended for HL409210+4.p
167934.56/22273.34	% SZS status Started for HL409199+5.p
167934.56/22273.34	% SZS status GaveUp for HL409199+5.p
167934.56/22273.34	eprover: CPU time limit exceeded, terminating
167934.56/22273.34	% SZS status Ended for HL409199+5.p
167934.86/22273.47	% SZS status Started for HL409205+5.p
167934.86/22273.47	% SZS status GaveUp for HL409205+5.p
167934.86/22273.47	eprover: CPU time limit exceeded, terminating
167934.86/22273.47	% SZS status Ended for HL409205+5.p
167948.56/22273.92	% SZS status Started for HL409211+4.p
167948.56/22273.92	% SZS status GaveUp for HL409211+4.p
167948.56/22273.92	eprover: CPU time limit exceeded, terminating
167948.56/22273.92	% SZS status Ended for HL409211+4.p
167957.55/22275.08	% SZS status Started for HL409206+5.p
167957.55/22275.08	% SZS status GaveUp for HL409206+5.p
167957.55/22275.08	eprover: CPU time limit exceeded, terminating
167957.55/22275.08	% SZS status Ended for HL409206+5.p
167967.39/22276.38	% SZS status Started for HL409212+4.p
167967.39/22276.38	% SZS status GaveUp for HL409212+4.p
167967.39/22276.38	eprover: CPU time limit exceeded, terminating
167967.39/22276.38	% SZS status Ended for HL409212+4.p
167973.14/22276.98	% SZS status Started for HL409215+4.p
167973.14/22276.98	% SZS status GaveUp for HL409215+4.p
167973.14/22276.98	eprover: CPU time limit exceeded, terminating
167973.14/22276.98	% SZS status Ended for HL409215+4.p
167973.31/22277.02	% SZS status Started for HL409207+5.p
167973.31/22277.02	% SZS status GaveUp for HL409207+5.p
167973.31/22277.02	eprover: CPU time limit exceeded, terminating
167973.31/22277.02	% SZS status Ended for HL409207+5.p
167983.92/22278.40	% SZS status Started for HL409209+5.p
167983.92/22278.40	% SZS status GaveUp for HL409209+5.p
167983.92/22278.40	eprover: CPU time limit exceeded, terminating
167983.92/22278.40	% SZS status Ended for HL409209+5.p
167992.06/22279.42	% SZS status Started for HL409216+4.p
167992.06/22279.42	% SZS status GaveUp for HL409216+4.p
167992.06/22279.42	eprover: CPU time limit exceeded, terminating
167992.06/22279.42	% SZS status Ended for HL409216+4.p
167997.34/22280.05	% SZS status Started for HL409217+4.p
167997.34/22280.05	% SZS status GaveUp for HL409217+4.p
167997.34/22280.05	eprover: CPU time limit exceeded, terminating
167997.34/22280.05	% SZS status Ended for HL409217+4.p
167999.98/22280.39	% SZS status Started for HL409210+5.p
167999.98/22280.39	% SZS status GaveUp for HL409210+5.p
167999.98/22280.39	eprover: CPU time limit exceeded, terminating
167999.98/22280.39	% SZS status Ended for HL409210+5.p
168015.66/22282.47	% SZS status Started for HL409218+4.p
168015.66/22282.47	% SZS status GaveUp for HL409218+4.p
168015.66/22282.47	eprover: CPU time limit exceeded, terminating
168015.66/22282.47	% SZS status Ended for HL409218+4.p
168024.25/22283.44	% SZS status Started for HL409219+4.p
168024.25/22283.44	% SZS status GaveUp for HL409219+4.p
168024.25/22283.44	eprover: CPU time limit exceeded, terminating
168024.25/22283.44	% SZS status Ended for HL409219+4.p
168027.55/22283.85	% SZS status Started for HL409212+5.p
168027.55/22283.85	% SZS status GaveUp for HL409212+5.p
168027.55/22283.85	eprover: CPU time limit exceeded, terminating
168027.55/22283.85	% SZS status Ended for HL409212+5.p
168038.67/22285.27	% SZS status Started for HL409215+5.p
168038.67/22285.27	% SZS status GaveUp for HL409215+5.p
168038.67/22285.27	eprover: CPU time limit exceeded, terminating
168038.67/22285.27	% SZS status Ended for HL409215+5.p
168048.05/22286.47	% SZS status Started for HL409220+4.p
168048.05/22286.47	% SZS status GaveUp for HL409220+4.p
168048.05/22286.47	eprover: CPU time limit exceeded, terminating
168048.05/22286.47	% SZS status Ended for HL409220+4.p
168054.95/22287.30	% SZS status Started for HL409216+5.p
168054.95/22287.30	% SZS status GaveUp for HL409216+5.p
168054.95/22287.30	eprover: CPU time limit exceeded, terminating
168054.95/22287.30	% SZS status Ended for HL409216+5.p
168063.22/22288.30	% SZS status Started for HL409221+4.p
168063.22/22288.30	% SZS status GaveUp for HL409221+4.p
168063.22/22288.30	eprover: CPU time limit exceeded, terminating
168063.22/22288.30	% SZS status Ended for HL409221+4.p
168079.28/22290.33	% SZS status Started for HL409222+4.p
168079.28/22290.33	% SZS status GaveUp for HL409222+4.p
168079.28/22290.33	eprover: CPU time limit exceeded, terminating
168079.28/22290.33	% SZS status Ended for HL409222+4.p
168103.41/22293.38	% SZS status Started for HL409223+4.p
168103.41/22293.38	% SZS status GaveUp for HL409223+4.p
168103.41/22293.38	eprover: CPU time limit exceeded, terminating
168103.41/22293.38	% SZS status Ended for HL409223+4.p
168143.75/22298.46	% SZS status Started for HL409222+5.p
168143.75/22298.46	% SZS status GaveUp for HL409222+5.p
168143.75/22298.46	eprover: CPU time limit exceeded, terminating
168143.75/22298.46	% SZS status Ended for HL409222+5.p
168150.92/22299.36	% SZS status Started for HL409211+5.p
168150.92/22299.36	% SZS status GaveUp for HL409211+5.p
168150.92/22299.36	eprover: CPU time limit exceeded, terminating
168150.92/22299.36	% SZS status Ended for HL409211+5.p
168168.28/22301.51	% SZS status Started for HL409224+4.p
168168.28/22301.51	% SZS status GaveUp for HL409224+4.p
168168.28/22301.51	eprover: CPU time limit exceeded, terminating
168168.28/22301.51	% SZS status Ended for HL409224+4.p
168177.14/22302.59	% SZS status Started for HL409217+5.p
168177.14/22302.59	% SZS status GaveUp for HL409217+5.p
168177.14/22302.59	eprover: CPU time limit exceeded, terminating
168177.14/22302.59	% SZS status Ended for HL409217+5.p
168184.66/22303.61	% SZS status Started for HL409223+5.p
168184.66/22303.61	% SZS status GaveUp for HL409223+5.p
168184.66/22303.61	eprover: CPU time limit exceeded, terminating
168184.66/22303.61	% SZS status Ended for HL409223+5.p
168191.95/22304.54	% SZS status Started for HL409226+4.p
168191.95/22304.54	% SZS status GaveUp for HL409226+4.p
168191.95/22304.54	eprover: CPU time limit exceeded, terminating
168191.95/22304.54	% SZS status Ended for HL409226+4.p
168205.31/22306.23	% SZS status Started for HL409218+5.p
168205.31/22306.23	% SZS status GaveUp for HL409218+5.p
168205.31/22306.23	eprover: CPU time limit exceeded, terminating
168205.31/22306.23	% SZS status Ended for HL409218+5.p
168209.19/22306.64	% SZS status Started for HL409228+4.p
168209.19/22306.64	% SZS status GaveUp for HL409228+4.p
168209.19/22306.64	eprover: CPU time limit exceeded, terminating
168209.19/22306.64	% SZS status Ended for HL409228+4.p
168226.20/22308.83	% SZS status Started for HL409219+5.p
168226.20/22308.83	% SZS status GaveUp for HL409219+5.p
168226.20/22308.83	eprover: CPU time limit exceeded, terminating
168226.20/22308.83	% SZS status Ended for HL409219+5.p
168229.77/22309.26	% SZS status Started for HL409229+4.p
168229.77/22309.26	% SZS status GaveUp for HL409229+4.p
168229.77/22309.26	eprover: CPU time limit exceeded, terminating
168229.77/22309.26	% SZS status Ended for HL409229+4.p
168237.69/22310.21	% SZS status Started for HL409220+5.p
168237.69/22310.21	% SZS status GaveUp for HL409220+5.p
168237.69/22310.21	eprover: CPU time limit exceeded, terminating
168237.69/22310.21	% SZS status Ended for HL409220+5.p
168250.64/22311.92	% SZS status Started for HL409230+4.p
168250.64/22311.92	% SZS status GaveUp for HL409230+4.p
168250.64/22311.92	eprover: CPU time limit exceeded, terminating
168250.64/22311.92	% SZS status Ended for HL409230+4.p
168256.38/22312.69	% SZS status Started for HL409221+5.p
168256.38/22312.69	% SZS status GaveUp for HL409221+5.p
168256.38/22312.69	eprover: CPU time limit exceeded, terminating
168256.38/22312.69	% SZS status Ended for HL409221+5.p
168258.61/22312.91	% SZS status Started for HL409226+5.p
168258.61/22312.91	% SZS status GaveUp for HL409226+5.p
168258.61/22312.91	eprover: CPU time limit exceeded, terminating
168258.61/22312.91	% SZS status Ended for HL409226+5.p
168260.17/22313.27	% SZS status Started for HL409231+4.p
168260.17/22313.27	% SZS status GaveUp for HL409231+4.p
168260.17/22313.27	eprover: CPU time limit exceeded, terminating
168260.17/22313.27	% SZS status Ended for HL409231+4.p
168272.31/22314.72	% SZS status Started for HL409228+5.p
168272.31/22314.72	% SZS status GaveUp for HL409228+5.p
168272.31/22314.72	eprover: CPU time limit exceeded, terminating
168272.31/22314.72	% SZS status Ended for HL409228+5.p
168281.25/22315.85	% SZS status Started for HL409232+4.p
168281.25/22315.85	% SZS status GaveUp for HL409232+4.p
168281.25/22315.85	eprover: CPU time limit exceeded, terminating
168281.25/22315.85	% SZS status Ended for HL409232+4.p
168286.03/22316.38	% SZS status Started for HL409233+4.p
168286.03/22316.38	% SZS status GaveUp for HL409233+4.p
168286.03/22316.38	eprover: CPU time limit exceeded, terminating
168286.03/22316.38	% SZS status Ended for HL409233+4.p
168305.81/22318.88	% SZS status Started for HL409229+5.p
168305.81/22318.88	% SZS status GaveUp for HL409229+5.p
168305.81/22318.88	eprover: CPU time limit exceeded, terminating
168305.81/22318.88	% SZS status Ended for HL409229+5.p
168305.81/22318.89	% SZS status Started for HL409234+4.p
168305.81/22318.89	% SZS status GaveUp for HL409234+4.p
168305.81/22318.89	eprover: CPU time limit exceeded, terminating
168305.81/22318.89	% SZS status Ended for HL409234+4.p
168310.00/22319.41	% SZS status Started for HL409230+5.p
168310.00/22319.41	% SZS status GaveUp for HL409230+5.p
168310.00/22319.41	eprover: CPU time limit exceeded, terminating
168310.00/22319.41	% SZS status Ended for HL409230+5.p
168312.48/22319.69	% SZS status Started for HL409224+5.p
168312.48/22319.69	% SZS status GaveUp for HL409224+5.p
168312.48/22319.69	eprover: CPU time limit exceeded, terminating
168312.48/22319.69	% SZS status Ended for HL409224+5.p
168330.55/22321.94	% SZS status Started for HL409235+4.p
168330.55/22321.94	% SZS status GaveUp for HL409235+4.p
168330.55/22321.94	eprover: CPU time limit exceeded, terminating
168330.55/22321.94	% SZS status Ended for HL409235+4.p
168334.70/22322.47	% SZS status Started for HL409236+4.p
168334.70/22322.47	% SZS status GaveUp for HL409236+4.p
168334.70/22322.47	eprover: CPU time limit exceeded, terminating
168334.70/22322.47	% SZS status Ended for HL409236+4.p
168335.92/22322.67	% SZS status Started for HL409231+5.p
168335.92/22322.67	% SZS status GaveUp for HL409231+5.p
168335.92/22322.67	eprover: CPU time limit exceeded, terminating
168335.92/22322.67	% SZS status Ended for HL409231+5.p
168354.92/22325.05	% SZS status Started for HL409237+4.p
168354.92/22325.05	% SZS status GaveUp for HL409237+4.p
168354.92/22325.05	eprover: CPU time limit exceeded, terminating
168354.92/22325.05	% SZS status Ended for HL409237+4.p
168360.23/22325.74	% SZS status Started for HL409238+4.p
168360.23/22325.74	% SZS status GaveUp for HL409238+4.p
168360.23/22325.74	eprover: CPU time limit exceeded, terminating
168360.23/22325.74	% SZS status Ended for HL409238+4.p
168384.30/22328.78	% SZS status Started for HL409239+4.p
168384.30/22328.78	% SZS status GaveUp for HL409239+4.p
168384.30/22328.78	eprover: CPU time limit exceeded, terminating
168384.30/22328.78	% SZS status Ended for HL409239+4.p
168409.45/22331.90	% SZS status Started for HL409236+5.p
168409.45/22331.90	% SZS status GaveUp for HL409236+5.p
168409.45/22331.90	eprover: CPU time limit exceeded, terminating
168409.45/22331.90	% SZS status Ended for HL409236+5.p
168414.83/22332.63	% SZS status Started for HL409237+5.p
168414.83/22332.63	% SZS status GaveUp for HL409237+5.p
168414.83/22332.63	eprover: CPU time limit exceeded, terminating
168414.83/22332.63	% SZS status Ended for HL409237+5.p
168433.27/22334.93	% SZS status Started for HL409240+4.p
168433.27/22334.93	% SZS status GaveUp for HL409240+4.p
168433.27/22334.93	eprover: CPU time limit exceeded, terminating
168433.27/22334.93	% SZS status Ended for HL409240+4.p
168440.77/22335.86	% SZS status Started for HL409238+5.p
168440.77/22335.86	% SZS status GaveUp for HL409238+5.p
168440.77/22335.86	eprover: CPU time limit exceeded, terminating
168440.77/22335.86	% SZS status Ended for HL409238+5.p
168456.97/22337.95	% SZS status Started for HL409241+4.p
168456.97/22337.95	% SZS status GaveUp for HL409241+4.p
168456.97/22337.95	eprover: CPU time limit exceeded, terminating
168456.97/22337.95	% SZS status Ended for HL409241+4.p
168468.12/22338.98	% SZS status Started for HL409239+5.p
168468.12/22338.98	% SZS status GaveUp for HL409239+5.p
168468.12/22338.98	eprover: CPU time limit exceeded, terminating
168468.12/22338.98	% SZS status Ended for HL409239+5.p
168470.36/22339.25	% SZS status Started for HL409232+5.p
168470.36/22339.25	% SZS status GaveUp for HL409232+5.p
168470.36/22339.25	eprover: CPU time limit exceeded, terminating
168470.36/22339.25	% SZS status Ended for HL409232+5.p
168483.80/22340.95	% SZS status Started for HL409233+5.p
168483.80/22340.95	% SZS status GaveUp for HL409233+5.p
168483.80/22340.95	eprover: CPU time limit exceeded, terminating
168483.80/22340.95	% SZS status Ended for HL409233+5.p
168483.80/22341.00	% SZS status Started for HL409242+4.p
168483.80/22341.00	% SZS status GaveUp for HL409242+4.p
168483.80/22341.00	eprover: CPU time limit exceeded, terminating
168483.80/22341.00	% SZS status Ended for HL409242+4.p
168486.36/22341.34	% SZS status Started for HL409235+5.p
168486.36/22341.34	% SZS status GaveUp for HL409235+5.p
168486.36/22341.34	eprover: CPU time limit exceeded, terminating
168486.36/22341.34	% SZS status Ended for HL409235+5.p
168493.84/22342.29	% SZS status Started for HL409243+4.p
168493.84/22342.29	% SZS status GaveUp for HL409243+4.p
168493.84/22342.29	eprover: CPU time limit exceeded, terminating
168493.84/22342.29	% SZS status Ended for HL409243+4.p
168499.19/22342.88	% SZS status Started for HL409234+5.p
168499.19/22342.88	% SZS status GaveUp for HL409234+5.p
168499.19/22342.88	eprover: CPU time limit exceeded, terminating
168499.19/22342.88	% SZS status Ended for HL409234+5.p
168499.75/22342.99	% SZS status Started for HL409240+5.p
168499.75/22342.99	% SZS status GaveUp for HL409240+5.p
168499.75/22342.99	eprover: CPU time limit exceeded, terminating
168499.75/22342.99	% SZS status Ended for HL409240+5.p
168508.42/22344.09	% SZS status Started for HL409244+4.p
168508.42/22344.09	% SZS status GaveUp for HL409244+4.p
168508.42/22344.09	eprover: CPU time limit exceeded, terminating
168508.42/22344.09	% SZS status Ended for HL409244+4.p
168518.28/22345.35	% SZS status Started for HL409245+4.p
168518.28/22345.35	% SZS status GaveUp for HL409245+4.p
168518.28/22345.35	eprover: CPU time limit exceeded, terminating
168518.28/22345.35	% SZS status Ended for HL409245+4.p
168523.94/22346.07	% SZS status Started for HL409241+5.p
168523.94/22346.07	% SZS status GaveUp for HL409241+5.p
168523.94/22346.07	eprover: CPU time limit exceeded, terminating
168523.94/22346.07	% SZS status Ended for HL409241+5.p
168524.30/22346.09	% SZS status Started for HL409246+4.p
168524.30/22346.09	% SZS status GaveUp for HL409246+4.p
168524.30/22346.09	eprover: CPU time limit exceeded, terminating
168524.30/22346.09	% SZS status Ended for HL409246+4.p
168542.84/22348.43	% SZS status Started for HL409248+4.p
168542.84/22348.43	% SZS status GaveUp for HL409248+4.p
168542.84/22348.43	eprover: CPU time limit exceeded, terminating
168542.84/22348.43	% SZS status Ended for HL409248+4.p
168548.39/22349.20	% SZS status Started for HL409249+4.p
168548.39/22349.20	% SZS status GaveUp for HL409249+4.p
168548.39/22349.20	eprover: CPU time limit exceeded, terminating
168548.39/22349.20	% SZS status Ended for HL409249+4.p
168552.98/22349.74	% SZS status Started for HL409242+5.p
168552.98/22349.74	% SZS status GaveUp for HL409242+5.p
168552.98/22349.74	eprover: CPU time limit exceeded, terminating
168552.98/22349.74	% SZS status Ended for HL409242+5.p
168566.73/22351.54	% SZS status Started for HL409244+5.p
168566.73/22351.54	% SZS status GaveUp for HL409244+5.p
168566.73/22351.54	eprover: CPU time limit exceeded, terminating
168566.73/22351.54	% SZS status Ended for HL409244+5.p
168573.11/22352.23	% SZS status Started for HL409250+4.p
168573.11/22352.23	% SZS status GaveUp for HL409250+4.p
168573.11/22352.23	eprover: CPU time limit exceeded, terminating
168573.11/22352.23	% SZS status Ended for HL409250+4.p
168579.81/22353.08	% SZS status Started for HL409245+5.p
168579.81/22353.08	% SZS status GaveUp for HL409245+5.p
168579.81/22353.08	eprover: CPU time limit exceeded, terminating
168579.81/22353.08	% SZS status Ended for HL409245+5.p
168591.69/22354.60	% SZS status Started for HL409251+4.p
168591.69/22354.60	% SZS status GaveUp for HL409251+4.p
168591.69/22354.60	eprover: CPU time limit exceeded, terminating
168591.69/22354.60	% SZS status Ended for HL409251+4.p
168603.70/22356.12	% SZS status Started for HL409252+4.p
168603.70/22356.12	% SZS status GaveUp for HL409252+4.p
168603.70/22356.12	eprover: CPU time limit exceeded, terminating
168603.70/22356.12	% SZS status Ended for HL409252+4.p
168604.83/22356.24	% SZS status Started for HL409248+5.p
168604.83/22356.24	% SZS status GaveUp for HL409248+5.p
168604.83/22356.24	eprover: CPU time limit exceeded, terminating
168604.83/22356.24	% SZS status Ended for HL409248+5.p
168623.67/22358.68	% SZS status Started for HL409249+5.p
168623.67/22358.68	% SZS status GaveUp for HL409249+5.p
168623.67/22358.68	eprover: CPU time limit exceeded, terminating
168623.67/22358.68	% SZS status Ended for HL409249+5.p
168628.03/22359.18	% SZS status Started for HL409253+4.p
168628.03/22359.18	% SZS status GaveUp for HL409253+4.p
168628.03/22359.18	eprover: CPU time limit exceeded, terminating
168628.03/22359.18	% SZS status Ended for HL409253+4.p
168637.92/22360.46	% SZS status Started for HL409250+5.p
168637.92/22360.46	% SZS status GaveUp for HL409250+5.p
168637.92/22360.46	eprover: CPU time limit exceeded, terminating
168637.92/22360.46	% SZS status Ended for HL409250+5.p
168647.61/22361.71	% SZS status Started for HL409254+4.p
168647.61/22361.71	% SZS status GaveUp for HL409254+4.p
168647.61/22361.71	eprover: CPU time limit exceeded, terminating
168647.61/22361.71	% SZS status Ended for HL409254+4.p
168662.38/22363.52	% SZS status Started for HL409256+4.p
168662.38/22363.52	% SZS status GaveUp for HL409256+4.p
168662.38/22363.52	eprover: CPU time limit exceeded, terminating
168662.38/22363.52	% SZS status Ended for HL409256+4.p
168672.23/22364.80	% SZS status Started for HL409252+5.p
168672.23/22364.80	% SZS status GaveUp for HL409252+5.p
168672.23/22364.80	eprover: CPU time limit exceeded, terminating
168672.23/22364.80	% SZS status Ended for HL409252+5.p
168686.66/22366.58	% SZS status Started for HL409257+4.p
168686.66/22366.58	% SZS status GaveUp for HL409257+4.p
168686.66/22366.58	eprover: CPU time limit exceeded, terminating
168686.66/22366.58	% SZS status Ended for HL409257+4.p
168691.98/22367.27	% SZS status Started for HL409253+5.p
168691.98/22367.27	% SZS status GaveUp for HL409253+5.p
168691.98/22367.27	eprover: CPU time limit exceeded, terminating
168691.98/22367.27	% SZS status Ended for HL409253+5.p
168691.98/22367.33	% SZS status Started for HL409243+5.p
168691.98/22367.33	% SZS status GaveUp for HL409243+5.p
168691.98/22367.33	eprover: CPU time limit exceeded, terminating
168691.98/22367.33	% SZS status Ended for HL409243+5.p
168710.75/22369.63	% SZS status Started for HL409258+4.p
168710.75/22369.63	% SZS status GaveUp for HL409258+4.p
168710.75/22369.63	eprover: CPU time limit exceeded, terminating
168710.75/22369.63	% SZS status Ended for HL409258+4.p
168716.92/22370.36	% SZS status Started for HL409259+4.p
168716.92/22370.36	% SZS status GaveUp for HL409259+4.p
168716.92/22370.36	eprover: CPU time limit exceeded, terminating
168716.92/22370.36	% SZS status Ended for HL409259+4.p
168717.22/22370.40	% SZS status Started for HL409246+5.p
168717.22/22370.40	% SZS status GaveUp for HL409246+5.p
168717.22/22370.40	eprover: CPU time limit exceeded, terminating
168717.22/22370.40	% SZS status Ended for HL409246+5.p
168729.09/22371.91	% SZS status Started for HL409256+5.p
168729.09/22371.91	% SZS status GaveUp for HL409256+5.p
168729.09/22371.91	eprover: CPU time limit exceeded, terminating
168729.09/22371.91	% SZS status Ended for HL409256+5.p
168741.44/22373.47	% SZS status Started for HL409260+4.p
168741.44/22373.47	% SZS status GaveUp for HL409260+4.p
168741.44/22373.47	eprover: CPU time limit exceeded, terminating
168741.44/22373.47	% SZS status Ended for HL409260+4.p
168752.92/22374.96	% SZS status Started for HL409262+4.p
168752.92/22374.96	% SZS status GaveUp for HL409262+4.p
168752.92/22374.96	eprover: CPU time limit exceeded, terminating
168752.92/22374.96	% SZS status Ended for HL409262+4.p
168754.00/22375.09	% SZS status Started for HL409257+5.p
168754.00/22375.09	% SZS status GaveUp for HL409257+5.p
168754.00/22375.09	eprover: CPU time limit exceeded, terminating
168754.00/22375.09	% SZS status Ended for HL409257+5.p
168777.89/22378.06	% SZS status Started for HL409263+4.p
168777.89/22378.06	% SZS status GaveUp for HL409263+4.p
168777.89/22378.06	eprover: CPU time limit exceeded, terminating
168777.89/22378.06	% SZS status Ended for HL409263+4.p
168782.83/22378.75	% SZS status Started for HL409251+5.p
168782.83/22378.75	% SZS status GaveUp for HL409251+5.p
168782.83/22378.75	eprover: CPU time limit exceeded, terminating
168782.83/22378.75	% SZS status Ended for HL409251+5.p
168798.41/22380.71	% SZS status Started for HL409260+5.p
168798.41/22380.71	% SZS status GaveUp for HL409260+5.p
168798.41/22380.71	eprover: CPU time limit exceeded, terminating
168798.41/22380.71	% SZS status Ended for HL409260+5.p
168800.62/22381.08	% SZS status Started for HL409264+4.p
168800.62/22381.08	% SZS status GaveUp for HL409264+4.p
168800.62/22381.08	eprover: CPU time limit exceeded, terminating
168800.62/22381.08	% SZS status Ended for HL409264+4.p
168820.70/22383.46	% SZS status Started for HL409254+5.p
168820.70/22383.46	% SZS status GaveUp for HL409254+5.p
168820.70/22383.46	eprover: CPU time limit exceeded, terminating
168820.70/22383.46	% SZS status Ended for HL409254+5.p
168822.83/22383.76	% SZS status Started for HL409265+4.p
168822.83/22383.76	% SZS status GaveUp for HL409265+4.p
168822.83/22383.76	eprover: CPU time limit exceeded, terminating
168822.83/22383.76	% SZS status Ended for HL409265+4.p
168823.25/22383.81	% SZS status Started for HL409262+5.p
168823.25/22383.81	% SZS status GaveUp for HL409262+5.p
168823.25/22383.81	eprover: CPU time limit exceeded, terminating
168823.25/22383.81	% SZS status Ended for HL409262+5.p
168835.56/22385.37	% SZS status Started for HL409263+5.p
168835.56/22385.37	% SZS status GaveUp for HL409263+5.p
168835.56/22385.37	eprover: CPU time limit exceeded, terminating
168835.56/22385.37	% SZS status Ended for HL409263+5.p
168845.06/22386.54	% SZS status Started for HL409266+4.p
168845.06/22386.54	% SZS status GaveUp for HL409266+4.p
168845.06/22386.54	eprover: CPU time limit exceeded, terminating
168845.06/22386.54	% SZS status Ended for HL409266+4.p
168847.45/22386.84	% SZS status Started for HL409267+4.p
168847.45/22386.84	% SZS status GaveUp for HL409267+4.p
168847.45/22386.84	eprover: CPU time limit exceeded, terminating
168847.45/22386.84	% SZS status Ended for HL409267+4.p
168864.97/22389.09	% SZS status Started for HL409264+5.p
168864.97/22389.09	% SZS status GaveUp for HL409264+5.p
168864.97/22389.09	eprover: CPU time limit exceeded, terminating
168864.97/22389.09	% SZS status Ended for HL409264+5.p
168869.12/22389.61	% SZS status Started for HL409268+4.p
168869.12/22389.61	% SZS status GaveUp for HL409268+4.p
168869.12/22389.61	eprover: CPU time limit exceeded, terminating
168869.12/22389.61	% SZS status Ended for HL409268+4.p
168883.55/22391.43	% SZS status Started for HL409265+5.p
168883.55/22391.43	% SZS status GaveUp for HL409265+5.p
168883.55/22391.43	eprover: CPU time limit exceeded, terminating
168883.55/22391.43	% SZS status Ended for HL409265+5.p
168889.88/22392.17	% SZS status Started for HL409269+4.p
168889.88/22392.17	% SZS status GaveUp for HL409269+4.p
168889.88/22392.17	eprover: CPU time limit exceeded, terminating
168889.88/22392.17	% SZS status Ended for HL409269+4.p
168901.58/22393.64	% SZS status Started for HL409258+5.p
168901.58/22393.64	% SZS status GaveUp for HL409258+5.p
168901.58/22393.64	eprover: CPU time limit exceeded, terminating
168901.58/22393.64	% SZS status Ended for HL409258+5.p
168907.61/22394.46	% SZS status Started for HL409270+4.p
168907.61/22394.46	% SZS status GaveUp for HL409270+4.p
168907.61/22394.46	eprover: CPU time limit exceeded, terminating
168907.61/22394.46	% SZS status Ended for HL409270+4.p
168917.98/22395.80	% SZS status Started for HL409267+5.p
168917.98/22395.80	% SZS status GaveUp for HL409267+5.p
168917.98/22395.80	eprover: CPU time limit exceeded, terminating
168917.98/22395.80	% SZS status Ended for HL409267+5.p
168919.17/22395.94	% SZS status Started for HL409259+5.p
168919.17/22395.94	% SZS status GaveUp for HL409259+5.p
168919.17/22395.94	eprover: CPU time limit exceeded, terminating
168919.17/22395.94	% SZS status Ended for HL409259+5.p
168926.09/22396.72	% SZS status Started for HL409271+4.p
168926.09/22396.72	% SZS status GaveUp for HL409271+4.p
168926.09/22396.72	eprover: CPU time limit exceeded, terminating
168926.09/22396.72	% SZS status Ended for HL409271+4.p
168935.23/22397.90	% SZS status Started for HL409266+5.p
168935.23/22397.90	% SZS status GaveUp for HL409266+5.p
168935.23/22397.90	eprover: CPU time limit exceeded, terminating
168935.23/22397.90	% SZS status Ended for HL409266+5.p
168942.84/22398.85	% SZS status Started for HL409272+4.p
168942.84/22398.85	% SZS status GaveUp for HL409272+4.p
168942.84/22398.85	eprover: CPU time limit exceeded, terminating
168942.84/22398.85	% SZS status Ended for HL409272+4.p
168950.17/22399.81	% SZS status Started for HL409273+4.p
168950.17/22399.81	% SZS status GaveUp for HL409273+4.p
168950.17/22399.81	eprover: CPU time limit exceeded, terminating
168950.17/22399.81	% SZS status Ended for HL409273+4.p
168951.52/22399.93	% SZS status Started for HL409269+5.p
168951.52/22399.93	% SZS status GaveUp for HL409269+5.p
168951.52/22399.93	eprover: CPU time limit exceeded, terminating
168951.52/22399.93	% SZS status Ended for HL409269+5.p
168966.80/22401.88	% SZS status Started for HL409275+4.p
168966.80/22401.88	% SZS status GaveUp for HL409275+4.p
168966.80/22401.88	eprover: CPU time limit exceeded, terminating
168966.80/22401.88	% SZS status Ended for HL409275+4.p
168969.67/22402.44	% SZS status Started for HL409270+5.p
168969.67/22402.44	% SZS status GaveUp for HL409270+5.p
168969.67/22402.44	eprover: CPU time limit exceeded, terminating
168969.67/22402.44	% SZS status Ended for HL409270+5.p
168976.36/22403.04	% SZS status Started for HL409276+4.p
168976.36/22403.04	% SZS status GaveUp for HL409276+4.p
168976.36/22403.04	eprover: CPU time limit exceeded, terminating
168976.36/22403.04	% SZS status Ended for HL409276+4.p
168992.55/22405.13	% SZS status Started for HL409271+5.p
168992.55/22405.13	% SZS status GaveUp for HL409271+5.p
168992.55/22405.13	eprover: CPU time limit exceeded, terminating
168992.55/22405.13	% SZS status Ended for HL409271+5.p
168995.75/22405.47	% SZS status Started for HL409277+4.p
168995.75/22405.47	% SZS status GaveUp for HL409277+4.p
168995.75/22405.47	eprover: CPU time limit exceeded, terminating
168995.75/22405.47	% SZS status Ended for HL409277+4.p
169003.75/22406.51	% SZS status Started for HL409272+5.p
169003.75/22406.51	% SZS status GaveUp for HL409272+5.p
169003.75/22406.51	eprover: CPU time limit exceeded, terminating
169003.75/22406.51	% SZS status Ended for HL409272+5.p
169016.83/22408.17	% SZS status Started for HL409278+4.p
169016.83/22408.17	% SZS status GaveUp for HL409278+4.p
169016.83/22408.17	eprover: CPU time limit exceeded, terminating
169016.83/22408.17	% SZS status Ended for HL409278+4.p
169024.94/22409.16	% SZS status Started for HL409268+5.p
169024.94/22409.16	% SZS status GaveUp for HL409268+5.p
169024.94/22409.16	eprover: CPU time limit exceeded, terminating
169024.94/22409.16	% SZS status Ended for HL409268+5.p
169028.30/22409.62	% SZS status Started for HL409280+4.p
169028.30/22409.62	% SZS status GaveUp for HL409280+4.p
169028.30/22409.62	eprover: CPU time limit exceeded, terminating
169028.30/22409.62	% SZS status Ended for HL409280+4.p
169031.45/22410.11	% SZS status Started for HL409275+5.p
169031.45/22410.11	% SZS status GaveUp for HL409275+5.p
169031.45/22410.11	eprover: CPU time limit exceeded, terminating
169031.45/22410.11	% SZS status Ended for HL409275+5.p
169047.83/22412.11	% SZS status Started for HL409276+5.p
169047.83/22412.11	% SZS status GaveUp for HL409276+5.p
169047.83/22412.11	eprover: CPU time limit exceeded, terminating
169047.83/22412.11	% SZS status Ended for HL409276+5.p
169048.52/22412.23	% SZS status Started for HL409281+4.p
169048.52/22412.23	% SZS status GaveUp for HL409281+4.p
169048.52/22412.23	eprover: CPU time limit exceeded, terminating
169048.52/22412.23	% SZS status Ended for HL409281+4.p
169056.31/22413.17	% SZS status Started for HL409282+4.p
169056.31/22413.17	% SZS status GaveUp for HL409282+4.p
169056.31/22413.17	eprover: CPU time limit exceeded, terminating
169056.31/22413.17	% SZS status Ended for HL409282+4.p
169063.83/22414.06	% SZS status Started for HL409273+5.p
169063.83/22414.06	% SZS status GaveUp for HL409273+5.p
169063.83/22414.06	eprover: CPU time limit exceeded, terminating
169063.83/22414.06	% SZS status Ended for HL409273+5.p
169073.72/22415.33	% SZS status Started for HL409283+4.p
169073.72/22415.33	% SZS status GaveUp for HL409283+4.p
169073.72/22415.33	eprover: CPU time limit exceeded, terminating
169073.72/22415.33	% SZS status Ended for HL409283+4.p
169077.11/22415.78	% SZS status Started for HL409278+5.p
169077.11/22415.78	% SZS status GaveUp for HL409278+5.p
169077.11/22415.78	eprover: CPU time limit exceeded, terminating
169077.11/22415.78	% SZS status Ended for HL409278+5.p
169087.70/22417.10	% SZS status Started for HL409284+4.p
169087.70/22417.10	% SZS status GaveUp for HL409284+4.p
169087.70/22417.10	eprover: CPU time limit exceeded, terminating
169087.70/22417.10	% SZS status Ended for HL409284+4.p
169101.09/22418.81	% SZS status Started for HL409285+4.p
169101.09/22418.81	% SZS status GaveUp for HL409285+4.p
169101.09/22418.81	eprover: CPU time limit exceeded, terminating
169101.09/22418.81	% SZS status Ended for HL409285+4.p
169111.38/22420.07	% SZS status Started for HL409281+5.p
169111.38/22420.07	% SZS status GaveUp for HL409281+5.p
169111.38/22420.07	eprover: CPU time limit exceeded, terminating
169111.38/22420.07	% SZS status Ended for HL409281+5.p
169125.42/22421.89	% SZS status Started for HL409286+4.p
169125.42/22421.89	% SZS status GaveUp for HL409286+4.p
169125.42/22421.89	eprover: CPU time limit exceeded, terminating
169125.42/22421.89	% SZS status Ended for HL409286+4.p
169128.69/22422.26	% SZS status Started for HL409282+5.p
169128.69/22422.26	% SZS status GaveUp for HL409282+5.p
169128.69/22422.26	eprover: CPU time limit exceeded, terminating
169128.69/22422.26	% SZS status Ended for HL409282+5.p
169140.25/22423.76	% SZS status Started for HL409283+5.p
169140.25/22423.76	% SZS status GaveUp for HL409283+5.p
169140.25/22423.76	eprover: CPU time limit exceeded, terminating
169140.25/22423.76	% SZS status Ended for HL409283+5.p
169149.22/22424.91	% SZS status Started for HL409287+4.p
169149.22/22424.91	% SZS status GaveUp for HL409287+4.p
169149.22/22424.91	eprover: CPU time limit exceeded, terminating
169149.22/22424.91	% SZS status Ended for HL409287+4.p
169164.09/22426.80	% SZS status Started for HL409290+4.p
169164.09/22426.80	% SZS status GaveUp for HL409290+4.p
169164.09/22426.80	eprover: CPU time limit exceeded, terminating
169164.09/22426.80	% SZS status Ended for HL409290+4.p
169167.69/22427.21	% SZS status Started for HL409277+5.p
169167.69/22427.21	% SZS status GaveUp for HL409277+5.p
169167.69/22427.21	eprover: CPU time limit exceeded, terminating
169167.69/22427.21	% SZS status Ended for HL409277+5.p
169172.17/22427.78	% SZS status Started for HL409285+5.p
169172.17/22427.78	% SZS status GaveUp for HL409285+5.p
169172.17/22427.78	eprover: CPU time limit exceeded, terminating
169172.17/22427.78	% SZS status Ended for HL409285+5.p
169188.41/22429.83	% SZS status Started for HL409291+4.p
169188.41/22429.83	% SZS status GaveUp for HL409291+4.p
169188.41/22429.83	eprover: CPU time limit exceeded, terminating
169188.41/22429.83	% SZS status Ended for HL409291+4.p
169192.95/22430.34	% SZS status Started for HL409286+5.p
169192.95/22430.34	% SZS status GaveUp for HL409286+5.p
169192.95/22430.34	eprover: CPU time limit exceeded, terminating
169192.95/22430.34	% SZS status Ended for HL409286+5.p
169196.52/22430.83	% SZS status Started for HL409292+4.p
169196.52/22430.83	% SZS status GaveUp for HL409292+4.p
169196.52/22430.83	eprover: CPU time limit exceeded, terminating
169196.52/22430.83	% SZS status Ended for HL409292+4.p
169209.84/22432.53	% SZS status Started for HL409280+5.p
169209.84/22432.53	% SZS status GaveUp for HL409280+5.p
169209.84/22432.53	eprover: CPU time limit exceeded, terminating
169209.84/22432.53	% SZS status Ended for HL409280+5.p
169211.34/22432.73	% SZS status Started for HL409287+5.p
169211.34/22432.73	% SZS status GaveUp for HL409287+5.p
169211.34/22432.73	eprover: CPU time limit exceeded, terminating
169211.34/22432.73	% SZS status Ended for HL409287+5.p
169217.08/22433.37	% SZS status Started for HL409293+4.p
169217.08/22433.37	% SZS status GaveUp for HL409293+4.p
169217.08/22433.37	eprover: CPU time limit exceeded, terminating
169217.08/22433.37	% SZS status Ended for HL409293+4.p
169234.09/22435.57	% SZS status Started for HL409294+4.p
169234.09/22435.57	% SZS status GaveUp for HL409294+4.p
169234.09/22435.57	eprover: CPU time limit exceeded, terminating
169234.09/22435.57	% SZS status Ended for HL409294+4.p
169234.83/22435.66	% SZS status Started for HL409290+5.p
169234.83/22435.66	% SZS status GaveUp for HL409290+5.p
169234.83/22435.66	eprover: CPU time limit exceeded, terminating
169234.83/22435.66	% SZS status Ended for HL409290+5.p
169240.98/22436.39	% SZS status Started for HL409295+4.p
169240.98/22436.39	% SZS status GaveUp for HL409295+4.p
169240.98/22436.39	eprover: CPU time limit exceeded, terminating
169240.98/22436.39	% SZS status Ended for HL409295+4.p
169259.39/22438.71	% SZS status Started for HL409296+4.p
169259.39/22438.71	% SZS status GaveUp for HL409296+4.p
169259.39/22438.71	eprover: CPU time limit exceeded, terminating
169259.39/22438.71	% SZS status Ended for HL409296+4.p
169270.23/22440.12	% SZS status Started for HL409292+5.p
169270.23/22440.12	% SZS status GaveUp for HL409292+5.p
169270.23/22440.12	eprover: CPU time limit exceeded, terminating
169270.23/22440.12	% SZS status Ended for HL409292+5.p
169277.97/22441.05	% SZS status Started for HL409293+5.p
169277.97/22441.05	% SZS status GaveUp for HL409293+5.p
169277.97/22441.05	eprover: CPU time limit exceeded, terminating
169277.97/22441.05	% SZS status Ended for HL409293+5.p
169281.75/22441.54	% SZS status Started for HL409284+5.p
169281.75/22441.54	% SZS status GaveUp for HL409284+5.p
169281.75/22441.54	eprover: CPU time limit exceeded, terminating
169281.75/22441.54	% SZS status Ended for HL409284+5.p
169283.64/22441.80	% SZS status Started for HL409297+4.p
169283.64/22441.80	% SZS status GaveUp for HL409297+4.p
169283.64/22441.80	eprover: CPU time limit exceeded, terminating
169283.64/22441.80	% SZS status Ended for HL409297+4.p
169292.88/22442.95	% SZS status Started for HL409294+5.p
169292.88/22442.95	% SZS status GaveUp for HL409294+5.p
169292.88/22442.95	eprover: CPU time limit exceeded, terminating
169292.88/22442.95	% SZS status Ended for HL409294+5.p
169302.53/22444.16	% SZS status Started for HL409299+4.p
169302.53/22444.16	% SZS status GaveUp for HL409299+4.p
169302.53/22444.16	eprover: CPU time limit exceeded, terminating
169302.53/22444.16	% SZS status Ended for HL409299+4.p
169308.34/22444.93	% SZS status Started for HL409300+4.p
169308.34/22444.93	% SZS status GaveUp for HL409300+4.p
169308.34/22444.93	eprover: CPU time limit exceeded, terminating
169308.34/22444.93	% SZS status Ended for HL409300+4.p
169326.27/22447.20	% SZS status Started for HL409301+4.p
169326.27/22447.20	% SZS status GaveUp for HL409301+4.p
169326.27/22447.20	eprover: CPU time limit exceeded, terminating
169326.27/22447.20	% SZS status Ended for HL409301+4.p
169350.66/22450.26	% SZS status Started for HL409302+4.p
169350.66/22450.26	% SZS status GaveUp for HL409302+4.p
169350.66/22450.26	eprover: CPU time limit exceeded, terminating
169350.66/22450.26	% SZS status Ended for HL409302+4.p
169351.33/22450.44	% SZS status Started for HL409297+5.p
169351.33/22450.44	% SZS status GaveUp for HL409297+5.p
169351.33/22450.44	eprover: CPU time limit exceeded, terminating
169351.33/22450.44	% SZS status Ended for HL409297+5.p
169365.83/22452.14	% SZS status Started for HL409299+5.p
169365.83/22452.14	% SZS status GaveUp for HL409299+5.p
169365.83/22452.14	eprover: CPU time limit exceeded, terminating
169365.83/22452.14	% SZS status Ended for HL409299+5.p
169369.62/22452.61	% SZS status Started for HL409296+5.p
169369.62/22452.61	% SZS status GaveUp for HL409296+5.p
169369.62/22452.61	eprover: CPU time limit exceeded, terminating
169369.62/22452.61	% SZS status Ended for HL409296+5.p
169376.42/22453.47	% SZS status Started for HL409303+4.p
169376.42/22453.47	% SZS status GaveUp for HL409303+4.p
169376.42/22453.47	eprover: CPU time limit exceeded, terminating
169376.42/22453.47	% SZS status Ended for HL409303+4.p
169377.14/22453.55	% SZS status Started for HL409300+5.p
169377.14/22453.55	% SZS status GaveUp for HL409300+5.p
169377.14/22453.55	eprover: CPU time limit exceeded, terminating
169377.14/22453.55	% SZS status Ended for HL409300+5.p
169377.14/22453.58	% SZS status Started for HL409291+5.p
169377.14/22453.58	% SZS status GaveUp for HL409291+5.p
169377.14/22453.58	eprover: CPU time limit exceeded, terminating
169377.14/22453.58	% SZS status Ended for HL409291+5.p
169390.33/22455.23	% SZS status Started for HL409301+5.p
169390.33/22455.23	% SZS status GaveUp for HL409301+5.p
169390.33/22455.23	eprover: CPU time limit exceeded, terminating
169390.33/22455.23	% SZS status Ended for HL409301+5.p
169393.05/22455.65	% SZS status Started for HL409304+4.p
169393.05/22455.65	% SZS status GaveUp for HL409304+4.p
169393.05/22455.65	eprover: CPU time limit exceeded, terminating
169393.05/22455.65	% SZS status Ended for HL409304+4.p
169401.44/22456.63	% SZS status Started for HL409305+4.p
169401.44/22456.63	% SZS status GaveUp for HL409305+4.p
169401.44/22456.63	eprover: CPU time limit exceeded, terminating
169401.44/22456.63	% SZS status Ended for HL409305+4.p
169413.83/22458.26	% SZS status Started for HL409306+4.p
169413.83/22458.26	% SZS status GaveUp for HL409306+4.p
169413.83/22458.26	eprover: CPU time limit exceeded, terminating
169413.83/22458.26	% SZS status Ended for HL409306+4.p
169424.81/22459.68	% SZS status Started for HL409307+4.p
169424.81/22459.68	% SZS status GaveUp for HL409307+4.p
169424.81/22459.68	eprover: CPU time limit exceeded, terminating
169424.81/22459.68	% SZS status Ended for HL409307+4.p
169434.44/22460.86	% SZS status Started for HL409302+5.p
169434.44/22460.86	% SZS status GaveUp for HL409302+5.p
169434.44/22460.86	eprover: CPU time limit exceeded, terminating
169434.44/22460.86	% SZS status Ended for HL409302+5.p
169442.08/22461.85	% SZS status Started for HL409295+5.p
169442.08/22461.85	% SZS status GaveUp for HL409295+5.p
169442.08/22461.85	eprover: CPU time limit exceeded, terminating
169442.08/22461.85	% SZS status Ended for HL409295+5.p
169449.64/22462.71	% SZS status Started for HL409308+4.p
169449.64/22462.71	% SZS status GaveUp for HL409308+4.p
169449.64/22462.71	eprover: CPU time limit exceeded, terminating
169449.64/22462.71	% SZS status Ended for HL409308+4.p
169458.09/22463.78	% SZS status Started for HL409304+5.p
169458.09/22463.78	% SZS status GaveUp for HL409304+5.p
169458.09/22463.78	eprover: CPU time limit exceeded, terminating
169458.09/22463.78	% SZS status Ended for HL409304+5.p
169458.55/22463.87	% SZS status Started for HL409305+5.p
169458.55/22463.87	% SZS status GaveUp for HL409305+5.p
169458.55/22463.87	eprover: CPU time limit exceeded, terminating
169458.55/22463.87	% SZS status Ended for HL409305+5.p
169466.98/22464.97	% SZS status Started for HL409309+4.p
169466.98/22464.97	% SZS status GaveUp for HL409309+4.p
169466.98/22464.97	eprover: CPU time limit exceeded, terminating
169466.98/22464.97	% SZS status Ended for HL409309+4.p
169476.86/22466.17	% SZS status Started for HL409306+5.p
169476.86/22466.17	% SZS status GaveUp for HL409306+5.p
169476.86/22466.17	eprover: CPU time limit exceeded, terminating
169476.86/22466.17	% SZS status Ended for HL409306+5.p
169482.03/22466.81	% SZS status Started for HL409310+4.p
169482.03/22466.81	% SZS status GaveUp for HL409310+4.p
169482.03/22466.81	eprover: CPU time limit exceeded, terminating
169482.03/22466.81	% SZS status Ended for HL409310+4.p
169492.22/22468.16	% SZS status Started for HL409311+4.p
169492.22/22468.16	% SZS status GaveUp for HL409311+4.p
169492.22/22468.16	eprover: CPU time limit exceeded, terminating
169492.22/22468.16	% SZS status Ended for HL409311+4.p
169494.89/22468.46	% SZS status Started for HL409307+5.p
169494.89/22468.46	% SZS status GaveUp for HL409307+5.p
169494.89/22468.46	eprover: CPU time limit exceeded, terminating
169494.89/22468.46	% SZS status Ended for HL409307+5.p
169505.64/22469.84	% SZS status Started for HL409313+4.p
169505.64/22469.84	% SZS status GaveUp for HL409313+4.p
169505.64/22469.84	eprover: CPU time limit exceeded, terminating
169505.64/22469.84	% SZS status Ended for HL409313+4.p
169515.34/22471.08	% SZS status Started for HL409308+5.p
169515.34/22471.08	% SZS status GaveUp for HL409308+5.p
169515.34/22471.08	eprover: CPU time limit exceeded, terminating
169515.34/22471.08	% SZS status Ended for HL409308+5.p
169520.03/22471.62	% SZS status Started for HL409314+4.p
169520.03/22471.62	% SZS status GaveUp for HL409314+4.p
169520.03/22471.62	eprover: CPU time limit exceeded, terminating
169520.03/22471.62	% SZS status Ended for HL409314+4.p
169530.84/22473.06	% SZS status Started for HL409309+5.p
169530.84/22473.06	% SZS status GaveUp for HL409309+5.p
169530.84/22473.06	eprover: CPU time limit exceeded, terminating
169530.84/22473.06	% SZS status Ended for HL409309+5.p
169539.30/22474.10	% SZS status Started for HL409316+4.p
169539.30/22474.10	% SZS status GaveUp for HL409316+4.p
169539.30/22474.10	eprover: CPU time limit exceeded, terminating
169539.30/22474.10	% SZS status Ended for HL409316+4.p
169539.97/22474.16	% SZS status Started for HL409310+5.p
169539.97/22474.16	% SZS status GaveUp for HL409310+5.p
169539.97/22474.16	eprover: CPU time limit exceeded, terminating
169539.97/22474.16	% SZS status Ended for HL409310+5.p
169554.92/22476.10	% SZS status Started for HL409317+4.p
169554.92/22476.10	% SZS status GaveUp for HL409317+4.p
169554.92/22476.10	eprover: CPU time limit exceeded, terminating
169554.92/22476.10	% SZS status Ended for HL409317+4.p
169560.22/22476.78	% SZS status Started for HL409311+5.p
169560.22/22476.78	% SZS status GaveUp for HL409311+5.p
169560.22/22476.78	eprover: CPU time limit exceeded, terminating
169560.22/22476.78	% SZS status Ended for HL409311+5.p
169564.36/22477.25	% SZS status Started for HL409318+4.p
169564.36/22477.25	% SZS status GaveUp for HL409318+4.p
169564.36/22477.25	eprover: CPU time limit exceeded, terminating
169564.36/22477.25	% SZS status Ended for HL409318+4.p
169573.20/22478.40	% SZS status Started for HL409313+5.p
169573.20/22478.40	% SZS status GaveUp for HL409313+5.p
169573.20/22478.40	eprover: CPU time limit exceeded, terminating
169573.20/22478.40	% SZS status Ended for HL409313+5.p
169573.36/22478.47	% SZS status Started for HL409303+5.p
169573.36/22478.47	% SZS status GaveUp for HL409303+5.p
169573.36/22478.47	eprover: CPU time limit exceeded, terminating
169573.36/22478.47	% SZS status Ended for HL409303+5.p
169583.61/22479.83	% SZS status Started for HL409320+4.p
169583.61/22479.83	% SZS status GaveUp for HL409320+4.p
169583.61/22479.83	eprover: CPU time limit exceeded, terminating
169583.61/22479.83	% SZS status Ended for HL409320+4.p
169586.64/22480.03	% SZS status Started for HL409314+5.p
169586.64/22480.03	% SZS status GaveUp for HL409314+5.p
169586.64/22480.03	eprover: CPU time limit exceeded, terminating
169586.64/22480.03	% SZS status Ended for HL409314+5.p
169597.53/22481.44	% SZS status Started for HL409321+4.p
169597.53/22481.44	% SZS status GaveUp for HL409321+4.p
169597.53/22481.44	eprover: CPU time limit exceeded, terminating
169597.53/22481.44	% SZS status Ended for HL409321+4.p
169601.05/22481.89	% SZS status Started for HL409316+5.p
169601.05/22481.89	% SZS status GaveUp for HL409316+5.p
169601.05/22481.89	eprover: CPU time limit exceeded, terminating
169601.05/22481.89	% SZS status Ended for HL409316+5.p
169607.45/22482.89	% SZS status Started for HL409322+4.p
169607.45/22482.89	% SZS status GaveUp for HL409322+4.p
169607.45/22482.89	eprover: CPU time limit exceeded, terminating
169607.45/22482.89	% SZS status Ended for HL409322+4.p
169621.42/22484.41	% SZS status Started for HL409317+5.p
169621.42/22484.41	% SZS status GaveUp for HL409317+5.p
169621.42/22484.41	eprover: CPU time limit exceeded, terminating
169621.42/22484.41	% SZS status Ended for HL409317+5.p
169621.42/22484.47	% SZS status Started for HL409324+4.p
169621.42/22484.47	% SZS status GaveUp for HL409324+4.p
169621.42/22484.47	eprover: CPU time limit exceeded, terminating
169621.42/22484.47	% SZS status Ended for HL409324+4.p
169633.88/22486.02	% SZS status Started for HL409325+4.p
169633.88/22486.02	% SZS status GaveUp for HL409325+4.p
169633.88/22486.02	eprover: CPU time limit exceeded, terminating
169633.88/22486.02	% SZS status Ended for HL409325+4.p
169637.00/22486.47	% SZS status Started for HL409318+5.p
169637.00/22486.47	% SZS status GaveUp for HL409318+5.p
169637.00/22486.47	eprover: CPU time limit exceeded, terminating
169637.00/22486.47	% SZS status Ended for HL409318+5.p
169645.34/22487.49	% SZS status Started for HL409326+4.p
169645.34/22487.49	% SZS status GaveUp for HL409326+4.p
169645.34/22487.49	eprover: CPU time limit exceeded, terminating
169645.34/22487.49	% SZS status Ended for HL409326+4.p
169646.09/22487.53	% SZS status Started for HL409320+5.p
169646.09/22487.53	% SZS status GaveUp for HL409320+5.p
169646.09/22487.53	eprover: CPU time limit exceeded, terminating
169646.09/22487.53	% SZS status Ended for HL409320+5.p
169655.61/22488.71	% SZS status Started for HL409321+5.p
169655.61/22488.71	% SZS status GaveUp for HL409321+5.p
169655.61/22488.71	eprover: CPU time limit exceeded, terminating
169655.61/22488.71	% SZS status Ended for HL409321+5.p
169662.31/22489.59	% SZS status Started for HL409327+4.p
169662.31/22489.59	% SZS status GaveUp for HL409327+4.p
169662.31/22489.59	eprover: CPU time limit exceeded, terminating
169662.31/22489.59	% SZS status Ended for HL409327+4.p
169667.27/22490.23	% SZS status Started for HL409322+5.p
169667.27/22490.23	% SZS status GaveUp for HL409322+5.p
169667.27/22490.23	eprover: CPU time limit exceeded, terminating
169667.27/22490.23	% SZS status Ended for HL409322+5.p
169669.98/22490.56	% SZS status Started for HL409328+4.p
169669.98/22490.56	% SZS status GaveUp for HL409328+4.p
169669.98/22490.56	eprover: CPU time limit exceeded, terminating
169669.98/22490.56	% SZS status Ended for HL409328+4.p
169682.08/22492.13	% SZS status Started for HL409324+5.p
169682.08/22492.13	% SZS status GaveUp for HL409324+5.p
169682.08/22492.13	eprover: CPU time limit exceeded, terminating
169682.08/22492.13	% SZS status Ended for HL409324+5.p
169686.58/22492.73	% SZS status Started for HL409329+4.p
169686.58/22492.73	% SZS status GaveUp for HL409329+4.p
169686.58/22492.73	eprover: CPU time limit exceeded, terminating
169686.58/22492.73	% SZS status Ended for HL409329+4.p
169693.97/22493.61	% SZS status Started for HL409331+4.p
169693.97/22493.61	% SZS status GaveUp for HL409331+4.p
169693.97/22493.61	eprover: CPU time limit exceeded, terminating
169693.97/22493.61	% SZS status Ended for HL409331+4.p
169704.81/22495.08	% SZS status Started for HL409325+5.p
169704.81/22495.08	% SZS status GaveUp for HL409325+5.p
169704.81/22495.08	eprover: CPU time limit exceeded, terminating
169704.81/22495.08	% SZS status Ended for HL409325+5.p
169711.42/22495.83	% SZS status Started for HL409332+4.p
169711.42/22495.83	% SZS status GaveUp for HL409332+4.p
169711.42/22495.83	eprover: CPU time limit exceeded, terminating
169711.42/22495.83	% SZS status Ended for HL409332+4.p
169716.27/22496.41	% SZS status Started for HL409326+5.p
169716.27/22496.41	% SZS status GaveUp for HL409326+5.p
169716.27/22496.41	eprover: CPU time limit exceeded, terminating
169716.27/22496.41	% SZS status Ended for HL409326+5.p
169728.08/22497.94	% SZS status Started for HL409327+5.p
169728.08/22497.94	% SZS status GaveUp for HL409327+5.p
169728.08/22497.94	eprover: CPU time limit exceeded, terminating
169728.08/22497.94	% SZS status Ended for HL409327+5.p
169729.41/22498.11	% SZS status Started for HL409333+4.p
169729.41/22498.11	% SZS status GaveUp for HL409333+4.p
169729.41/22498.11	eprover: CPU time limit exceeded, terminating
169729.41/22498.11	% SZS status Ended for HL409333+4.p
169737.55/22499.07	% SZS status Started for HL409328+5.p
169737.55/22499.07	% SZS status GaveUp for HL409328+5.p
169737.55/22499.07	eprover: CPU time limit exceeded, terminating
169737.55/22499.07	% SZS status Ended for HL409328+5.p
169740.83/22499.51	% SZS status Started for HL409334+4.p
169740.83/22499.51	% SZS status GaveUp for HL409334+4.p
169740.83/22499.51	eprover: CPU time limit exceeded, terminating
169740.83/22499.51	% SZS status Ended for HL409334+4.p
169750.72/22500.74	% SZS status Started for HL409329+5.p
169750.72/22500.74	% SZS status GaveUp for HL409329+5.p
169750.72/22500.74	eprover: CPU time limit exceeded, terminating
169750.72/22500.74	% SZS status Ended for HL409329+5.p
169753.84/22501.19	% SZS status Started for HL409335+4.p
169753.84/22501.19	% SZS status GaveUp for HL409335+4.p
169753.84/22501.19	eprover: CPU time limit exceeded, terminating
169753.84/22501.19	% SZS status Ended for HL409335+4.p
169765.20/22502.58	% SZS status Started for HL409337+4.p
169765.20/22502.58	% SZS status GaveUp for HL409337+4.p
169765.20/22502.58	eprover: CPU time limit exceeded, terminating
169765.20/22502.58	% SZS status Ended for HL409337+4.p
169768.62/22502.66	% SZS status Started for HL409331+5.p
169768.62/22502.66	% SZS status GaveUp for HL409331+5.p
169768.62/22502.66	eprover: CPU time limit exceeded, terminating
169768.62/22502.66	% SZS status Ended for HL409331+5.p
169779.52/22504.03	% SZS status Started for HL409332+5.p
169779.52/22504.03	% SZS status GaveUp for HL409332+5.p
169779.52/22504.03	eprover: CPU time limit exceeded, terminating
169779.52/22504.03	% SZS status Ended for HL409332+5.p
169782.59/22504.39	% SZS status Started for HL409341+4.p
169782.59/22504.39	% SZS status GaveUp for HL409341+4.p
169782.59/22504.39	eprover: CPU time limit exceeded, terminating
169782.59/22504.39	% SZS status Ended for HL409341+4.p
169793.27/22505.72	% SZS status Started for HL409342+4.p
169793.27/22505.72	% SZS status GaveUp for HL409342+4.p
169793.27/22505.72	eprover: CPU time limit exceeded, terminating
169793.27/22505.72	% SZS status Ended for HL409342+4.p
169794.86/22506.01	% SZS status Started for HL409333+5.p
169794.86/22506.01	% SZS status GaveUp for HL409333+5.p
169794.86/22506.01	eprover: CPU time limit exceeded, terminating
169794.86/22506.01	% SZS status Ended for HL409333+5.p
169806.27/22507.47	% SZS status Started for HL409343+4.p
169806.27/22507.47	% SZS status GaveUp for HL409343+4.p
169806.27/22507.47	eprover: CPU time limit exceeded, terminating
169806.27/22507.47	% SZS status Ended for HL409343+4.p
169814.88/22508.49	% SZS status Started for HL409334+5.p
169814.88/22508.49	% SZS status GaveUp for HL409334+5.p
169814.88/22508.49	eprover: CPU time limit exceeded, terminating
169814.88/22508.49	% SZS status Ended for HL409334+5.p
169819.27/22509.05	% SZS status Started for HL409344+4.p
169819.27/22509.05	% SZS status GaveUp for HL409344+4.p
169819.27/22509.05	eprover: CPU time limit exceeded, terminating
169819.27/22509.05	% SZS status Ended for HL409344+4.p
169819.98/22509.19	% SZS status Started for HL409335+5.p
169819.98/22509.19	% SZS status GaveUp for HL409335+5.p
169819.98/22509.19	eprover: CPU time limit exceeded, terminating
169819.98/22509.19	% SZS status Ended for HL409335+5.p
169834.89/22511.00	% SZS status Started for HL409337+5.p
169834.89/22511.00	% SZS status GaveUp for HL409337+5.p
169834.89/22511.00	eprover: CPU time limit exceeded, terminating
169834.89/22511.00	% SZS status Ended for HL409337+5.p
169838.47/22511.52	% SZS status Started for HL409345+4.p
169838.47/22511.52	% SZS status GaveUp for HL409345+4.p
169838.47/22511.52	eprover: CPU time limit exceeded, terminating
169838.47/22511.52	% SZS status Ended for HL409345+4.p
169844.48/22512.25	% SZS status Started for HL409346+4.p
169844.48/22512.25	% SZS status GaveUp for HL409346+4.p
169844.48/22512.25	eprover: CPU time limit exceeded, terminating
169844.48/22512.25	% SZS status Ended for HL409346+4.p
169853.64/22513.40	% SZS status Started for HL409341+5.p
169853.64/22513.40	% SZS status GaveUp for HL409341+5.p
169853.64/22513.40	eprover: CPU time limit exceeded, terminating
169853.64/22513.40	% SZS status Ended for HL409341+5.p
169861.06/22514.33	% SZS status Started for HL409342+5.p
169861.06/22514.33	% SZS status GaveUp for HL409342+5.p
169861.06/22514.33	eprover: CPU time limit exceeded, terminating
169861.06/22514.33	% SZS status Ended for HL409342+5.p
169863.33/22514.54	% SZS status Started for HL409347+4.p
169863.33/22514.54	% SZS status GaveUp for HL409347+4.p
169863.33/22514.54	eprover: CPU time limit exceeded, terminating
169863.33/22514.54	% SZS status Ended for HL409347+4.p
169874.47/22515.97	% SZS status Started for HL409343+5.p
169874.47/22515.97	% SZS status GaveUp for HL409343+5.p
169874.47/22515.97	eprover: CPU time limit exceeded, terminating
169874.47/22515.97	% SZS status Ended for HL409343+5.p
169877.94/22516.46	% SZS status Started for HL409348+4.p
169877.94/22516.46	% SZS status GaveUp for HL409348+4.p
169877.94/22516.46	eprover: CPU time limit exceeded, terminating
169877.94/22516.46	% SZS status Ended for HL409348+4.p
169887.09/22517.60	% SZS status Started for HL409350+4.p
169887.09/22517.60	% SZS status GaveUp for HL409350+4.p
169887.09/22517.60	eprover: CPU time limit exceeded, terminating
169887.09/22517.60	% SZS status Ended for HL409350+4.p
169889.81/22517.90	% SZS status Started for HL409344+5.p
169889.81/22517.90	% SZS status GaveUp for HL409344+5.p
169889.81/22517.90	eprover: CPU time limit exceeded, terminating
169889.81/22517.90	% SZS status Ended for HL409344+5.p
169900.56/22519.28	% SZS status Started for HL409345+5.p
169900.56/22519.28	% SZS status GaveUp for HL409345+5.p
169900.56/22519.28	eprover: CPU time limit exceeded, terminating
169900.56/22519.28	% SZS status Ended for HL409345+5.p
169902.38/22519.55	% SZS status Started for HL409351+4.p
169902.38/22519.55	% SZS status GaveUp for HL409351+4.p
169902.38/22519.55	eprover: CPU time limit exceeded, terminating
169902.38/22519.55	% SZS status Ended for HL409351+4.p
169913.56/22520.93	% SZS status Started for HL409352+4.p
169913.56/22520.93	% SZS status GaveUp for HL409352+4.p
169913.56/22520.93	eprover: CPU time limit exceeded, terminating
169913.56/22520.93	% SZS status Ended for HL409352+4.p
169918.58/22521.59	% SZS status Started for HL409346+5.p
169918.58/22521.59	% SZS status GaveUp for HL409346+5.p
169918.58/22521.59	eprover: CPU time limit exceeded, terminating
169918.58/22521.59	% SZS status Ended for HL409346+5.p
169925.25/22522.45	% SZS status Started for HL409347+5.p
169925.25/22522.45	% SZS status GaveUp for HL409347+5.p
169925.25/22522.45	eprover: CPU time limit exceeded, terminating
169925.25/22522.45	% SZS status Ended for HL409347+5.p
169926.61/22522.62	% SZS status Started for HL409353+4.p
169926.61/22522.62	% SZS status GaveUp for HL409353+4.p
169926.61/22522.62	eprover: CPU time limit exceeded, terminating
169926.61/22522.62	% SZS status Ended for HL409353+4.p
169942.34/22524.67	% SZS status Started for HL409355+4.p
169942.34/22524.67	% SZS status GaveUp for HL409355+4.p
169942.34/22524.67	eprover: CPU time limit exceeded, terminating
169942.34/22524.67	% SZS status Ended for HL409355+4.p
169944.11/22524.80	% SZS status Started for HL409348+5.p
169944.11/22524.80	% SZS status GaveUp for HL409348+5.p
169944.11/22524.80	eprover: CPU time limit exceeded, terminating
169944.11/22524.80	% SZS status Ended for HL409348+5.p
169950.20/22525.67	% SZS status Started for HL409356+4.p
169950.20/22525.67	% SZS status GaveUp for HL409356+4.p
169950.20/22525.67	eprover: CPU time limit exceeded, terminating
169950.20/22525.67	% SZS status Ended for HL409356+4.p
169957.03/22526.41	% SZS status Started for HL409350+5.p
169957.03/22526.41	% SZS status GaveUp for HL409350+5.p
169957.03/22526.41	eprover: CPU time limit exceeded, terminating
169957.03/22526.41	% SZS status Ended for HL409350+5.p
169967.83/22527.87	% SZS status Started for HL409357+4.p
169967.83/22527.87	% SZS status GaveUp for HL409357+4.p
169967.83/22527.87	eprover: CPU time limit exceeded, terminating
169967.83/22527.87	% SZS status Ended for HL409357+4.p
169971.53/22528.29	% SZS status Started for HL409351+5.p
169971.53/22528.29	% SZS status GaveUp for HL409351+5.p
169971.53/22528.29	eprover: CPU time limit exceeded, terminating
169971.53/22528.29	% SZS status Ended for HL409351+5.p
169981.33/22529.54	% SZS status Started for HL409358+4.p
169981.33/22529.54	% SZS status GaveUp for HL409358+4.p
169981.33/22529.54	eprover: CPU time limit exceeded, terminating
169981.33/22529.54	% SZS status Ended for HL409358+4.p
169981.77/22529.59	% SZS status Started for HL409352+5.p
169981.77/22529.59	% SZS status GaveUp for HL409352+5.p
169981.77/22529.59	eprover: CPU time limit exceeded, terminating
169981.77/22529.59	% SZS status Ended for HL409352+5.p
169994.14/22531.15	% SZS status Started for HL409353+5.p
169994.14/22531.15	% SZS status GaveUp for HL409353+5.p
169994.14/22531.15	eprover: CPU time limit exceeded, terminating
169994.14/22531.15	% SZS status Ended for HL409353+5.p
169995.67/22531.36	% SZS status Started for HL409359+4.p
169995.67/22531.36	% SZS status GaveUp for HL409359+4.p
169995.67/22531.36	eprover: CPU time limit exceeded, terminating
169995.67/22531.36	% SZS status Ended for HL409359+4.p
170005.91/22532.65	% SZS status Started for HL409355+5.p
170005.91/22532.65	% SZS status GaveUp for HL409355+5.p
170005.91/22532.65	eprover: CPU time limit exceeded, terminating
170005.91/22532.65	% SZS status Ended for HL409355+5.p
170006.69/22532.69	% SZS status Started for HL409360+4.p
170006.69/22532.69	% SZS status GaveUp for HL409360+4.p
170006.69/22532.69	eprover: CPU time limit exceeded, terminating
170006.69/22532.69	% SZS status Ended for HL409360+4.p
170020.53/22534.43	% SZS status Started for HL409361+4.p
170020.53/22534.43	% SZS status GaveUp for HL409361+4.p
170020.53/22534.43	eprover: CPU time limit exceeded, terminating
170020.53/22534.43	% SZS status Ended for HL409361+4.p
170027.56/22535.45	% SZS status Started for HL409356+5.p
170027.56/22535.45	% SZS status GaveUp for HL409356+5.p
170027.56/22535.45	eprover: CPU time limit exceeded, terminating
170027.56/22535.45	% SZS status Ended for HL409356+5.p
170030.75/22535.76	% SZS status Started for HL409362+4.p
170030.75/22535.76	% SZS status GaveUp for HL409362+4.p
170030.75/22535.76	eprover: CPU time limit exceeded, terminating
170030.75/22535.76	% SZS status Ended for HL409362+4.p
170031.53/22535.90	% SZS status Started for HL409357+5.p
170031.53/22535.90	% SZS status GaveUp for HL409357+5.p
170031.53/22535.90	eprover: CPU time limit exceeded, terminating
170031.53/22535.90	% SZS status Ended for HL409357+5.p
170049.67/22538.25	% SZS status Started for HL409358+5.p
170049.67/22538.25	% SZS status GaveUp for HL409358+5.p
170049.67/22538.25	eprover: CPU time limit exceeded, terminating
170049.67/22538.25	% SZS status Ended for HL409358+5.p
170052.73/22538.51	% SZS status Started for HL409363+4.p
170052.73/22538.51	% SZS status GaveUp for HL409363+4.p
170052.73/22538.51	eprover: CPU time limit exceeded, terminating
170052.73/22538.51	% SZS status Ended for HL409363+4.p
170056.36/22538.96	% SZS status Started for HL409364+4.p
170056.36/22538.96	% SZS status GaveUp for HL409364+4.p
170056.36/22538.96	eprover: CPU time limit exceeded, terminating
170056.36/22538.96	% SZS status Ended for HL409364+4.p
170064.62/22540.06	% SZS status Started for HL409359+5.p
170064.62/22540.06	% SZS status GaveUp for HL409359+5.p
170064.62/22540.06	eprover: CPU time limit exceeded, terminating
170064.62/22540.06	% SZS status Ended for HL409359+5.p
170076.98/22541.59	% SZS status Started for HL409366+4.p
170076.98/22541.59	% SZS status GaveUp for HL409366+4.p
170076.98/22541.59	eprover: CPU time limit exceeded, terminating
170076.98/22541.59	% SZS status Ended for HL409366+4.p
170079.16/22541.83	% SZS status Started for HL409360+5.p
170079.16/22541.83	% SZS status GaveUp for HL409360+5.p
170079.16/22541.83	eprover: CPU time limit exceeded, terminating
170079.16/22541.83	% SZS status Ended for HL409360+5.p
170088.72/22543.03	% SZS status Started for HL409361+5.p
170088.72/22543.03	% SZS status GaveUp for HL409361+5.p
170088.72/22543.03	eprover: CPU time limit exceeded, terminating
170088.72/22543.03	% SZS status Ended for HL409361+5.p
170089.30/22543.11	% SZS status Started for HL409367+4.p
170089.30/22543.11	% SZS status GaveUp for HL409367+4.p
170089.30/22543.11	eprover: CPU time limit exceeded, terminating
170089.30/22543.11	% SZS status Ended for HL409367+4.p
170103.64/22544.91	% SZS status Started for HL409368+4.p
170103.64/22544.91	% SZS status GaveUp for HL409368+4.p
170103.64/22544.91	eprover: CPU time limit exceeded, terminating
170103.64/22544.91	% SZS status Ended for HL409368+4.p
170103.80/22544.97	% SZS status Started for HL409362+5.p
170103.80/22544.97	% SZS status GaveUp for HL409362+5.p
170103.80/22544.97	eprover: CPU time limit exceeded, terminating
170103.80/22544.97	% SZS status Ended for HL409362+5.p
170113.14/22546.14	% SZS status Started for HL409370+4.p
170113.14/22546.14	% SZS status GaveUp for HL409370+4.p
170113.14/22546.14	eprover: CPU time limit exceeded, terminating
170113.14/22546.14	% SZS status Ended for HL409370+4.p
170113.47/22546.21	% SZS status Started for HL409363+5.p
170113.47/22546.21	% SZS status GaveUp for HL409363+5.p
170113.47/22546.21	eprover: CPU time limit exceeded, terminating
170113.47/22546.21	% SZS status Ended for HL409363+5.p
170127.95/22548.00	% SZS status Started for HL409371+4.p
170127.95/22548.00	% SZS status GaveUp for HL409371+4.p
170127.95/22548.00	eprover: CPU time limit exceeded, terminating
170127.95/22548.00	% SZS status Ended for HL409371+4.p
170132.36/22548.52	% SZS status Started for HL409364+5.p
170132.36/22548.52	% SZS status GaveUp for HL409364+5.p
170132.36/22548.52	eprover: CPU time limit exceeded, terminating
170132.36/22548.52	% SZS status Ended for HL409364+5.p
170137.58/22549.21	% SZS status Started for HL409366+5.p
170137.58/22549.21	% SZS status GaveUp for HL409366+5.p
170137.58/22549.21	eprover: CPU time limit exceeded, terminating
170137.58/22549.21	% SZS status Ended for HL409366+5.p
170138.41/22549.30	% SZS status Started for HL409372+4.p
170138.41/22549.30	% SZS status GaveUp for HL409372+4.p
170138.41/22549.30	eprover: CPU time limit exceeded, terminating
170138.41/22549.30	% SZS status Ended for HL409372+4.p
170156.20/22551.58	% SZS status Started for HL409373+4.p
170156.20/22551.58	% SZS status GaveUp for HL409373+4.p
170156.20/22551.58	eprover: CPU time limit exceeded, terminating
170156.20/22551.58	% SZS status Ended for HL409373+4.p
170157.53/22551.94	% SZS status Started for HL409367+5.p
170157.53/22551.94	% SZS status GaveUp for HL409367+5.p
170157.53/22551.94	eprover: CPU time limit exceeded, terminating
170157.53/22551.94	% SZS status Ended for HL409367+5.p
170161.91/22552.32	% SZS status Started for HL409376+4.p
170161.91/22552.32	% SZS status GaveUp for HL409376+4.p
170161.91/22552.32	eprover: CPU time limit exceeded, terminating
170161.91/22552.32	% SZS status Ended for HL409376+4.p
170173.44/22553.72	% SZS status Started for HL409368+5.p
170173.44/22553.72	% SZS status GaveUp for HL409368+5.p
170173.44/22553.72	eprover: CPU time limit exceeded, terminating
170173.44/22553.72	% SZS status Ended for HL409368+5.p
170182.77/22554.98	% SZS status Started for HL409377+4.p
170182.77/22554.98	% SZS status GaveUp for HL409377+4.p
170182.77/22554.98	eprover: CPU time limit exceeded, terminating
170182.77/22554.98	% SZS status Ended for HL409377+4.p
170185.81/22555.31	% SZS status Started for HL409370+5.p
170185.81/22555.31	% SZS status GaveUp for HL409370+5.p
170185.81/22555.31	eprover: CPU time limit exceeded, terminating
170185.81/22555.31	% SZS status Ended for HL409370+5.p
170194.45/22556.36	% SZS status Started for HL409371+5.p
170194.45/22556.36	% SZS status GaveUp for HL409371+5.p
170194.45/22556.36	eprover: CPU time limit exceeded, terminating
170194.45/22556.36	% SZS status Ended for HL409371+5.p
170198.47/22556.88	% SZS status Started for HL409378+4.p
170198.47/22556.88	% SZS status GaveUp for HL409378+4.p
170198.47/22556.88	eprover: CPU time limit exceeded, terminating
170198.47/22556.88	% SZS status Ended for HL409378+4.p
170209.17/22558.20	% SZS status Started for HL409372+5.p
170209.17/22558.20	% SZS status GaveUp for HL409372+5.p
170209.17/22558.20	eprover: CPU time limit exceeded, terminating
170209.17/22558.20	% SZS status Ended for HL409372+5.p
170209.69/22558.34	% SZS status Started for HL409380+4.p
170209.69/22558.34	% SZS status GaveUp for HL409380+4.p
170209.69/22558.34	eprover: CPU time limit exceeded, terminating
170209.69/22558.34	% SZS status Ended for HL409380+4.p
170219.11/22559.54	% SZS status Started for HL409373+5.p
170219.11/22559.54	% SZS status GaveUp for HL409373+5.p
170219.11/22559.54	eprover: CPU time limit exceeded, terminating
170219.11/22559.54	% SZS status Ended for HL409373+5.p
170222.64/22559.93	% SZS status Started for HL409383+4.p
170222.64/22559.93	% SZS status GaveUp for HL409383+4.p
170222.64/22559.93	eprover: CPU time limit exceeded, terminating
170222.64/22559.93	% SZS status Ended for HL409383+4.p
170234.75/22561.41	% SZS status Started for HL409384+4.p
170234.75/22561.41	% SZS status GaveUp for HL409384+4.p
170234.75/22561.41	eprover: CPU time limit exceeded, terminating
170234.75/22561.41	% SZS status Ended for HL409384+4.p
170240.86/22562.18	% SZS status Started for HL409376+5.p
170240.86/22562.18	% SZS status GaveUp for HL409376+5.p
170240.86/22562.18	eprover: CPU time limit exceeded, terminating
170240.86/22562.18	% SZS status Ended for HL409376+5.p
170244.41/22562.69	% SZS status Started for HL409377+5.p
170244.41/22562.69	% SZS status GaveUp for HL409377+5.p
170244.41/22562.69	eprover: CPU time limit exceeded, terminating
170244.41/22562.69	% SZS status Ended for HL409377+5.p
170245.70/22562.98	% SZS status Started for HL409385+4.p
170245.70/22562.98	% SZS status GaveUp for HL409385+4.p
170245.70/22562.98	eprover: CPU time limit exceeded, terminating
170245.70/22562.98	% SZS status Ended for HL409385+4.p
170263.41/22565.21	% SZS status Started for HL409386+4.p
170263.41/22565.21	% SZS status GaveUp for HL409386+4.p
170263.41/22565.21	eprover: CPU time limit exceeded, terminating
170263.41/22565.21	% SZS status Ended for HL409386+4.p
170263.41/22565.23	% SZS status Started for HL409378+5.p
170263.41/22565.23	% SZS status GaveUp for HL409378+5.p
170263.41/22565.23	eprover: CPU time limit exceeded, terminating
170263.41/22565.23	% SZS status Ended for HL409378+5.p
170271.56/22566.07	% SZS status Started for HL409387+4.p
170271.56/22566.07	% SZS status GaveUp for HL409387+4.p
170271.56/22566.07	eprover: CPU time limit exceeded, terminating
170271.56/22566.07	% SZS status Ended for HL409387+4.p
170276.14/22566.67	% SZS status Started for HL409380+5.p
170276.14/22566.67	% SZS status GaveUp for HL409380+5.p
170276.14/22566.67	eprover: CPU time limit exceeded, terminating
170276.14/22566.67	% SZS status Ended for HL409380+5.p
170288.98/22568.26	% SZS status Started for HL409388+4.p
170288.98/22568.26	% SZS status GaveUp for HL409388+4.p
170288.98/22568.26	eprover: CPU time limit exceeded, terminating
170288.98/22568.26	% SZS status Ended for HL409388+4.p
170291.06/22568.62	% SZS status Started for HL409383+5.p
170291.06/22568.62	% SZS status GaveUp for HL409383+5.p
170291.06/22568.62	eprover: CPU time limit exceeded, terminating
170291.06/22568.62	% SZS status Ended for HL409383+5.p
170299.97/22569.70	% SZS status Started for HL409389+4.p
170299.97/22569.70	% SZS status GaveUp for HL409389+4.p
170299.97/22569.70	eprover: CPU time limit exceeded, terminating
170299.97/22569.70	% SZS status Ended for HL409389+4.p
170300.52/22569.77	% SZS status Started for HL409384+5.p
170300.52/22569.77	% SZS status GaveUp for HL409384+5.p
170300.52/22569.77	eprover: CPU time limit exceeded, terminating
170300.52/22569.77	% SZS status Ended for HL409384+5.p
170315.23/22571.56	% SZS status Started for HL409385+5.p
170315.23/22571.56	% SZS status GaveUp for HL409385+5.p
170315.23/22571.56	eprover: CPU time limit exceeded, terminating
170315.23/22571.56	% SZS status Ended for HL409385+5.p
170315.94/22571.65	% SZS status Started for HL409390+4.p
170315.94/22571.65	% SZS status GaveUp for HL409390+4.p
170315.94/22571.65	eprover: CPU time limit exceeded, terminating
170315.94/22571.65	% SZS status Ended for HL409390+4.p
170325.55/22572.84	% SZS status Started for HL409391+4.p
170325.55/22572.84	% SZS status GaveUp for HL409391+4.p
170325.55/22572.84	eprover: CPU time limit exceeded, terminating
170325.55/22572.84	% SZS status Ended for HL409391+4.p
170329.08/22572.95	% SZS status Started for HL409386+5.p
170329.08/22572.95	% SZS status GaveUp for HL409386+5.p
170329.08/22572.95	eprover: CPU time limit exceeded, terminating
170329.08/22572.95	% SZS status Ended for HL409386+5.p
170342.45/22574.68	% SZS status Started for HL409392+4.p
170342.45/22574.68	% SZS status GaveUp for HL409392+4.p
170342.45/22574.68	eprover: CPU time limit exceeded, terminating
170342.45/22574.68	% SZS status Ended for HL409392+4.p
170348.59/22575.47	% SZS status Started for HL409387+5.p
170348.59/22575.47	% SZS status GaveUp for HL409387+5.p
170348.59/22575.47	eprover: CPU time limit exceeded, terminating
170348.59/22575.47	% SZS status Ended for HL409387+5.p
170353.38/22575.98	% SZS status Started for HL409393+4.p
170353.38/22575.98	% SZS status GaveUp for HL409393+4.p
170353.38/22575.98	eprover: CPU time limit exceeded, terminating
170353.38/22575.98	% SZS status Ended for HL409393+4.p
170355.39/22576.39	% SZS status Started for HL409388+5.p
170355.39/22576.39	% SZS status GaveUp for HL409388+5.p
170355.39/22576.39	eprover: CPU time limit exceeded, terminating
170355.39/22576.39	% SZS status Ended for HL409388+5.p
170373.09/22578.49	% SZS status Started for HL409389+5.p
170373.09/22578.49	% SZS status GaveUp for HL409389+5.p
170373.09/22578.49	eprover: CPU time limit exceeded, terminating
170373.09/22578.49	% SZS status Ended for HL409389+5.p
170373.09/22578.56	% SZS status Started for HL409394+4.p
170373.09/22578.56	% SZS status GaveUp for HL409394+4.p
170373.09/22578.56	eprover: CPU time limit exceeded, terminating
170373.09/22578.56	% SZS status Ended for HL409394+4.p
170380.53/22579.49	% SZS status Started for HL409396+4.p
170380.53/22579.49	% SZS status GaveUp for HL409396+4.p
170380.53/22579.49	eprover: CPU time limit exceeded, terminating
170380.53/22579.49	% SZS status Ended for HL409396+4.p
170383.97/22580.07	% SZS status Started for HL409390+5.p
170383.97/22580.07	% SZS status GaveUp for HL409390+5.p
170383.97/22580.07	eprover: CPU time limit exceeded, terminating
170383.97/22580.07	% SZS status Ended for HL409390+5.p
170395.92/22581.82	% SZS status Started for HL409391+5.p
170395.92/22581.82	% SZS status GaveUp for HL409391+5.p
170395.92/22581.82	eprover: CPU time limit exceeded, terminating
170395.92/22581.82	% SZS status Ended for HL409391+5.p
170396.36/22581.84	% SZS status Started for HL409397+4.p
170396.36/22581.84	% SZS status GaveUp for HL409397+4.p
170396.36/22581.84	eprover: CPU time limit exceeded, terminating
170396.36/22581.84	% SZS status Ended for HL409397+4.p
170403.23/22582.54	% SZS status Started for HL409397+5.p
170403.23/22582.54	% SZS status GaveUp for HL409397+5.p
170403.23/22582.54	eprover: CPU time limit exceeded, terminating
170403.23/22582.54	% SZS status Ended for HL409397+5.p
170410.84/22583.58	% SZS status Started for HL409392+5.p
170410.84/22583.58	% SZS status GaveUp for HL409392+5.p
170410.84/22583.58	eprover: CPU time limit exceeded, terminating
170410.84/22583.58	% SZS status Ended for HL409392+5.p
170412.84/22583.91	% SZS status Started for HL409398+4.p
170412.84/22583.91	% SZS status GaveUp for HL409398+4.p
170412.84/22583.91	eprover: CPU time limit exceeded, terminating
170412.84/22583.91	% SZS status Ended for HL409398+4.p
170420.94/22584.96	% SZS status Started for HL409400+4.p
170420.94/22584.96	% SZS status GaveUp for HL409400+4.p
170420.94/22584.96	eprover: CPU time limit exceeded, terminating
170420.94/22584.96	% SZS status Ended for HL409400+4.p
170429.31/22586.08	% SZS status Started for HL409393+5.p
170429.31/22586.08	% SZS status GaveUp for HL409393+5.p
170429.31/22586.08	eprover: CPU time limit exceeded, terminating
170429.31/22586.08	% SZS status Ended for HL409393+5.p
170433.73/22586.66	% SZS status Started for HL409402+4.p
170433.73/22586.66	% SZS status GaveUp for HL409402+4.p
170433.73/22586.66	eprover: CPU time limit exceeded, terminating
170433.73/22586.66	% SZS status Ended for HL409402+4.p
170434.86/22586.81	% SZS status Started for HL409394+5.p
170434.86/22586.81	% SZS status GaveUp for HL409394+5.p
170434.86/22586.81	eprover: CPU time limit exceeded, terminating
170434.86/22586.81	% SZS status Ended for HL409394+5.p
170444.69/22588.10	% SZS status Started for HL409403+4.p
170444.69/22588.10	% SZS status GaveUp for HL409403+4.p
170444.69/22588.10	eprover: CPU time limit exceeded, terminating
170444.69/22588.10	% SZS status Ended for HL409403+4.p
170457.59/22589.72	% SZS status Started for HL409404+4.p
170457.59/22589.72	% SZS status GaveUp for HL409404+4.p
170457.59/22589.72	eprover: CPU time limit exceeded, terminating
170457.59/22589.72	% SZS status Ended for HL409404+4.p
170459.95/22590.04	% SZS status Started for HL409396+5.p
170459.95/22590.04	% SZS status GaveUp for HL409396+5.p
170459.95/22590.04	eprover: CPU time limit exceeded, terminating
170459.95/22590.04	% SZS status Ended for HL409396+5.p
170468.64/22591.26	% SZS status Started for HL409406+4.p
170468.64/22591.26	% SZS status GaveUp for HL409406+4.p
170468.64/22591.26	eprover: CPU time limit exceeded, terminating
170468.64/22591.26	% SZS status Ended for HL409406+4.p
170484.06/22593.29	% SZS status Started for HL409408+4.p
170484.06/22593.29	% SZS status GaveUp for HL409408+4.p
170484.06/22593.29	eprover: CPU time limit exceeded, terminating
170484.06/22593.29	% SZS status Ended for HL409408+4.p
170485.45/22593.47	% SZS status Started for HL409398+5.p
170485.45/22593.47	% SZS status GaveUp for HL409398+5.p
170485.45/22593.47	eprover: CPU time limit exceeded, terminating
170485.45/22593.47	% SZS status Ended for HL409398+5.p
170487.31/22593.71	% SZS status Started for HL409400+5.p
170487.31/22593.71	% SZS status GaveUp for HL409400+5.p
170487.31/22593.71	eprover: CPU time limit exceeded, terminating
170487.31/22593.71	% SZS status Ended for HL409400+5.p
170503.22/22595.76	% SZS status Started for HL409402+5.p
170503.22/22595.76	% SZS status GaveUp for HL409402+5.p
170503.22/22595.76	eprover: CPU time limit exceeded, terminating
170503.22/22595.76	% SZS status Ended for HL409402+5.p
170506.03/22596.41	% SZS status Started for HL409409+4.p
170506.03/22596.41	% SZS status GaveUp for HL409409+4.p
170506.03/22596.41	eprover: CPU time limit exceeded, terminating
170506.03/22596.41	% SZS status Ended for HL409409+4.p
170511.36/22596.86	% SZS status Started for HL409410+4.p
170511.36/22596.86	% SZS status GaveUp for HL409410+4.p
170511.36/22596.86	eprover: CPU time limit exceeded, terminating
170511.36/22596.86	% SZS status Ended for HL409410+4.p
170520.98/22598.08	% SZS status Started for HL409403+5.p
170520.98/22598.08	% SZS status GaveUp for HL409403+5.p
170520.98/22598.08	eprover: CPU time limit exceeded, terminating
170520.98/22598.08	% SZS status Ended for HL409403+5.p
170521.92/22598.24	% SZS status Started for HL409404+5.p
170521.92/22598.24	% SZS status GaveUp for HL409404+5.p
170521.92/22598.24	eprover: CPU time limit exceeded, terminating
170521.92/22598.24	% SZS status Ended for HL409404+5.p
170526.67/22598.86	% SZS status Started for HL409410+5.p
170526.67/22598.86	% SZS status GaveUp for HL409410+5.p
170526.67/22598.86	eprover: CPU time limit exceeded, terminating
170526.67/22598.86	% SZS status Ended for HL409410+5.p
170531.84/22599.57	% SZS status Started for HL409412+4.p
170531.84/22599.57	% SZS status GaveUp for HL409412+4.p
170531.84/22599.57	eprover: CPU time limit exceeded, terminating
170531.84/22599.57	% SZS status Ended for HL409412+4.p
170534.36/22599.96	% SZS status Started for HL409412+5.p
170534.36/22599.96	% SZS status GaveUp for HL409412+5.p
170534.36/22599.96	eprover: CPU time limit exceeded, terminating
170534.36/22599.96	% SZS status Ended for HL409412+5.p
170543.61/22601.15	% SZS status Started for HL409406+5.p
170543.61/22601.15	% SZS status GaveUp for HL409406+5.p
170543.61/22601.15	eprover: CPU time limit exceeded, terminating
170543.61/22601.15	% SZS status Ended for HL409406+5.p
170545.28/22601.36	% SZS status Started for HL409413+5.p
170545.28/22601.36	% SZS status GaveUp for HL409413+5.p
170545.28/22601.36	eprover: CPU time limit exceeded, terminating
170545.28/22601.36	% SZS status Ended for HL409413+5.p
170545.72/22601.42	% SZS status Started for HL409413+4.p
170545.72/22601.42	% SZS status GaveUp for HL409413+4.p
170545.72/22601.42	eprover: CPU time limit exceeded, terminating
170545.72/22601.42	% SZS status Ended for HL409413+4.p
170549.73/22601.96	% SZS status Started for HL409415+4.p
170549.73/22601.96	% SZS status GaveUp for HL409415+4.p
170549.73/22601.96	eprover: CPU time limit exceeded, terminating
170549.73/22601.96	% SZS status Ended for HL409415+4.p
170556.00/22602.71	% SZS status Started for HL409408+5.p
170556.00/22602.71	% SZS status GaveUp for HL409408+5.p
170556.00/22602.71	eprover: CPU time limit exceeded, terminating
170556.00/22602.71	% SZS status Ended for HL409408+5.p
170557.98/22603.01	% SZS status Started for HL409416+4.p
170557.98/22603.01	% SZS status GaveUp for HL409416+4.p
170557.98/22603.01	eprover: CPU time limit exceeded, terminating
170557.98/22603.01	% SZS status Ended for HL409416+4.p
170569.22/22604.44	% SZS status Started for HL409418+4.p
170569.22/22604.44	% SZS status GaveUp for HL409418+4.p
170569.22/22604.44	eprover: CPU time limit exceeded, terminating
170569.22/22604.44	% SZS status Ended for HL409418+4.p
170573.17/22604.94	% SZS status Started for HL409409+5.p
170573.17/22604.94	% SZS status GaveUp for HL409409+5.p
170573.17/22604.94	eprover: CPU time limit exceeded, terminating
170573.17/22604.94	% SZS status Ended for HL409409+5.p
170574.17/22605.09	% SZS status Started for HL409419+4.p
170574.17/22605.09	% SZS status GaveUp for HL409419+4.p
170574.17/22605.09	eprover: CPU time limit exceeded, terminating
170574.17/22605.09	% SZS status Ended for HL409419+4.p
170582.39/22606.10	% SZS status Started for HL409420+4.p
170582.39/22606.10	% SZS status GaveUp for HL409420+4.p
170582.39/22606.10	eprover: CPU time limit exceeded, terminating
170582.39/22606.10	% SZS status Ended for HL409420+4.p
170596.59/22608.02	% SZS status Started for HL409421+4.p
170596.59/22608.02	% SZS status GaveUp for HL409421+4.p
170596.59/22608.02	eprover: CPU time limit exceeded, terminating
170596.59/22608.02	% SZS status Ended for HL409421+4.p
170605.98/22609.36	% SZS status Started for HL409422+4.p
170605.98/22609.36	% SZS status GaveUp for HL409422+4.p
170605.98/22609.36	eprover: CPU time limit exceeded, terminating
170605.98/22609.36	% SZS status Ended for HL409422+4.p
170619.97/22611.11	% SZS status Started for HL409415+5.p
170619.97/22611.11	% SZS status GaveUp for HL409415+5.p
170619.97/22611.11	eprover: CPU time limit exceeded, terminating
170619.97/22611.11	% SZS status Ended for HL409415+5.p
170629.97/22612.38	% SZS status Started for HL409418+5.p
170629.97/22612.38	% SZS status GaveUp for HL409418+5.p
170629.97/22612.38	eprover: CPU time limit exceeded, terminating
170629.97/22612.38	% SZS status Ended for HL409418+5.p
170631.41/22612.57	% SZS status Started for HL409423+4.p
170631.41/22612.57	% SZS status GaveUp for HL409423+4.p
170631.41/22612.57	eprover: CPU time limit exceeded, terminating
170631.41/22612.57	% SZS status Ended for HL409423+4.p
170632.09/22612.69	% SZS status Started for HL409416+5.p
170632.09/22612.69	% SZS status GaveUp for HL409416+5.p
170632.09/22612.69	eprover: CPU time limit exceeded, terminating
170632.09/22612.69	% SZS status Ended for HL409416+5.p
170643.14/22614.11	% SZS status Started for HL409419+5.p
170643.14/22614.11	% SZS status GaveUp for HL409419+5.p
170643.14/22614.11	eprover: CPU time limit exceeded, terminating
170643.14/22614.11	% SZS status Ended for HL409419+5.p
170650.02/22615.01	% SZS status Started for HL409420+5.p
170650.02/22615.01	% SZS status GaveUp for HL409420+5.p
170650.02/22615.01	eprover: CPU time limit exceeded, terminating
170650.02/22615.01	% SZS status Ended for HL409420+5.p
170654.80/22615.64	% SZS status Started for HL409426+4.p
170654.80/22615.64	% SZS status GaveUp for HL409426+4.p
170654.80/22615.64	eprover: CPU time limit exceeded, terminating
170654.80/22615.64	% SZS status Ended for HL409426+4.p
170656.19/22615.83	% SZS status Started for HL409427+4.p
170656.19/22615.83	% SZS status GaveUp for HL409427+4.p
170656.19/22615.83	eprover: CPU time limit exceeded, terminating
170656.19/22615.83	% SZS status Ended for HL409427+4.p
170661.56/22616.56	% SZS status Started for HL409421+5.p
170661.56/22616.56	% SZS status GaveUp for HL409421+5.p
170661.56/22616.56	eprover: CPU time limit exceeded, terminating
170661.56/22616.56	% SZS status Ended for HL409421+5.p
170674.45/22618.16	% SZS status Started for HL409428+4.p
170674.45/22618.16	% SZS status GaveUp for HL409428+4.p
170674.45/22618.16	eprover: CPU time limit exceeded, terminating
170674.45/22618.16	% SZS status Ended for HL409428+4.p
170680.88/22619.00	% SZS status Started for HL409429+4.p
170680.88/22619.00	% SZS status GaveUp for HL409429+4.p
170680.88/22619.00	eprover: CPU time limit exceeded, terminating
170680.88/22619.00	% SZS status Ended for HL409429+4.p
170682.12/22619.15	% SZS status Started for HL409422+5.p
170682.12/22619.15	% SZS status GaveUp for HL409422+5.p
170682.12/22619.15	eprover: CPU time limit exceeded, terminating
170682.12/22619.15	% SZS status Ended for HL409422+5.p
170698.16/22621.23	% SZS status Started for HL409430+4.p
170698.16/22621.23	% SZS status GaveUp for HL409430+4.p
170698.16/22621.23	eprover: CPU time limit exceeded, terminating
170698.16/22621.23	% SZS status Ended for HL409430+4.p
170706.17/22622.19	% SZS status Started for HL409423+5.p
170706.17/22622.19	% SZS status GaveUp for HL409423+5.p
170706.17/22622.19	eprover: CPU time limit exceeded, terminating
170706.17/22622.19	% SZS status Ended for HL409423+5.p
170706.58/22622.22	% SZS status Started for HL409431+4.p
170706.58/22622.22	% SZS status GaveUp for HL409431+4.p
170706.58/22622.22	eprover: CPU time limit exceeded, terminating
170706.58/22622.22	% SZS status Ended for HL409431+4.p
170714.59/22623.27	% SZS status Started for HL409426+5.p
170714.59/22623.27	% SZS status GaveUp for HL409426+5.p
170714.59/22623.27	eprover: CPU time limit exceeded, terminating
170714.59/22623.27	% SZS status Ended for HL409426+5.p
170726.19/22624.95	% SZS status Started for HL409427+5.p
170726.19/22624.95	% SZS status GaveUp for HL409427+5.p
170726.19/22624.95	eprover: CPU time limit exceeded, terminating
170726.19/22624.95	% SZS status Ended for HL409427+5.p
170733.14/22625.98	% SZS status Started for HL409432+4.p
170733.14/22625.98	% SZS status GaveUp for HL409432+4.p
170733.14/22625.98	eprover: CPU time limit exceeded, terminating
170733.14/22625.98	% SZS status Ended for HL409432+4.p
170738.48/22626.63	% SZS status Started for HL409434+4.p
170738.48/22626.63	% SZS status GaveUp for HL409434+4.p
170738.48/22626.63	eprover: CPU time limit exceeded, terminating
170738.48/22626.63	% SZS status Ended for HL409434+4.p
170739.53/22626.86	% SZS status Started for HL409428+5.p
170739.53/22626.86	% SZS status GaveUp for HL409428+5.p
170739.53/22626.86	eprover: CPU time limit exceeded, terminating
170739.53/22626.86	% SZS status Ended for HL409428+5.p
170745.59/22627.50	% SZS status Started for HL409429+5.p
170745.59/22627.50	% SZS status GaveUp for HL409429+5.p
170745.59/22627.50	eprover: CPU time limit exceeded, terminating
170745.59/22627.50	% SZS status Ended for HL409429+5.p
170757.27/22629.07	% SZS status Started for HL409435+4.p
170757.27/22629.07	% SZS status GaveUp for HL409435+4.p
170757.27/22629.07	eprover: CPU time limit exceeded, terminating
170757.27/22629.07	% SZS status Ended for HL409435+4.p
170764.92/22630.03	% SZS status Started for HL409436+4.p
170764.92/22630.03	% SZS status GaveUp for HL409436+4.p
170764.92/22630.03	eprover: CPU time limit exceeded, terminating
170764.92/22630.03	% SZS status Ended for HL409436+4.p
170765.77/22630.19	% SZS status Started for HL409430+5.p
170765.77/22630.19	% SZS status GaveUp for HL409430+5.p
170765.77/22630.19	eprover: CPU time limit exceeded, terminating
170765.77/22630.19	% SZS status Ended for HL409430+5.p
170769.64/22630.68	% SZS status Started for HL409436+5.p
170769.64/22630.68	% SZS status GaveUp for HL409436+5.p
170769.64/22630.68	eprover: CPU time limit exceeded, terminating
170769.64/22630.68	% SZS status Ended for HL409436+5.p
170781.22/22632.25	% SZS status Started for HL409431+5.p
170781.22/22632.25	% SZS status GaveUp for HL409431+5.p
170781.22/22632.25	eprover: CPU time limit exceeded, terminating
170781.22/22632.25	% SZS status Ended for HL409431+5.p
170781.92/22632.26	% SZS status Started for HL409437+4.p
170781.92/22632.26	% SZS status GaveUp for HL409437+4.p
170781.92/22632.26	eprover: CPU time limit exceeded, terminating
170781.92/22632.26	% SZS status Ended for HL409437+4.p
170788.88/22633.26	% SZS status Started for HL409432+5.p
170788.88/22633.26	% SZS status GaveUp for HL409432+5.p
170788.88/22633.26	eprover: CPU time limit exceeded, terminating
170788.88/22633.26	% SZS status Ended for HL409432+5.p
170790.75/22633.45	% SZS status Started for HL409438+4.p
170790.75/22633.45	% SZS status GaveUp for HL409438+4.p
170790.75/22633.45	eprover: CPU time limit exceeded, terminating
170790.75/22633.45	% SZS status Ended for HL409438+4.p
170803.97/22635.29	% SZS status Started for HL409442+4.p
170803.97/22635.29	% SZS status GaveUp for HL409442+4.p
170803.97/22635.29	eprover: CPU time limit exceeded, terminating
170803.97/22635.29	% SZS status Ended for HL409442+4.p
170812.00/22636.28	% SZS status Started for HL409434+5.p
170812.00/22636.28	% SZS status GaveUp for HL409434+5.p
170812.00/22636.28	eprover: CPU time limit exceeded, terminating
170812.00/22636.28	% SZS status Ended for HL409434+5.p
170812.28/22636.38	% SZS status Started for HL409443+4.p
170812.28/22636.38	% SZS status GaveUp for HL409443+4.p
170812.28/22636.38	eprover: CPU time limit exceeded, terminating
170812.28/22636.38	% SZS status Ended for HL409443+4.p
170826.22/22638.12	% SZS status Started for HL409435+5.p
170826.22/22638.12	% SZS status GaveUp for HL409435+5.p
170826.22/22638.12	eprover: CPU time limit exceeded, terminating
170826.22/22638.12	% SZS status Ended for HL409435+5.p
170828.00/22638.40	% SZS status Started for HL409444+4.p
170828.00/22638.40	% SZS status GaveUp for HL409444+4.p
170828.00/22638.40	eprover: CPU time limit exceeded, terminating
170828.00/22638.40	% SZS status Ended for HL409444+4.p
170836.28/22639.42	% SZS status Started for HL409445+4.p
170836.28/22639.42	% SZS status GaveUp for HL409445+4.p
170836.28/22639.42	eprover: CPU time limit exceeded, terminating
170836.28/22639.42	% SZS status Ended for HL409445+4.p
170849.27/22641.26	% SZS status Started for HL409437+5.p
170849.27/22641.26	% SZS status GaveUp for HL409437+5.p
170849.27/22641.26	eprover: CPU time limit exceeded, terminating
170849.27/22641.26	% SZS status Ended for HL409437+5.p
170851.84/22641.49	% SZS status Started for HL409446+4.p
170851.84/22641.49	% SZS status GaveUp for HL409446+4.p
170851.84/22641.49	eprover: CPU time limit exceeded, terminating
170851.84/22641.49	% SZS status Ended for HL409446+4.p
170854.55/22641.95	% SZS status Started for HL409438+5.p
170854.55/22641.95	% SZS status GaveUp for HL409438+5.p
170854.55/22641.95	eprover: CPU time limit exceeded, terminating
170854.55/22641.95	% SZS status Ended for HL409438+5.p
170867.45/22643.46	% SZS status Started for HL409442+5.p
170867.45/22643.46	% SZS status GaveUp for HL409442+5.p
170867.45/22643.46	eprover: CPU time limit exceeded, terminating
170867.45/22643.46	% SZS status Ended for HL409442+5.p
170873.70/22644.31	% SZS status Started for HL409447+4.p
170873.70/22644.31	% SZS status GaveUp for HL409447+4.p
170873.70/22644.31	eprover: CPU time limit exceeded, terminating
170873.70/22644.31	% SZS status Ended for HL409447+4.p
170875.78/22644.54	% SZS status Started for HL409443+5.p
170875.78/22644.54	% SZS status GaveUp for HL409443+5.p
170875.78/22644.54	eprover: CPU time limit exceeded, terminating
170875.78/22644.54	% SZS status Ended for HL409443+5.p
170879.66/22645.18	% SZS status Started for HL409448+4.p
170879.66/22645.18	% SZS status GaveUp for HL409448+4.p
170879.66/22645.18	eprover: CPU time limit exceeded, terminating
170879.66/22645.18	% SZS status Ended for HL409448+4.p
170891.28/22646.56	% SZS status Started for HL409448+5.p
170891.28/22646.56	% SZS status GaveUp for HL409448+5.p
170891.28/22646.56	eprover: CPU time limit exceeded, terminating
170891.28/22646.56	% SZS status Ended for HL409448+5.p
170897.44/22647.44	% SZS status Started for HL409449+4.p
170897.44/22647.44	% SZS status GaveUp for HL409449+4.p
170897.44/22647.44	eprover: CPU time limit exceeded, terminating
170897.44/22647.44	% SZS status Ended for HL409449+4.p
170898.31/22647.57	% SZS status Started for HL409444+5.p
170898.31/22647.57	% SZS status GaveUp for HL409444+5.p
170898.31/22647.57	eprover: CPU time limit exceeded, terminating
170898.31/22647.57	% SZS status Ended for HL409444+5.p
170903.92/22648.24	% SZS status Started for HL409450+4.p
170903.92/22648.24	% SZS status GaveUp for HL409450+4.p
170903.92/22648.24	eprover: CPU time limit exceeded, terminating
170903.92/22648.24	% SZS status Ended for HL409450+4.p
170911.14/22649.27	% SZS status Started for HL409445+5.p
170911.14/22649.27	% SZS status GaveUp for HL409445+5.p
170911.14/22649.27	eprover: CPU time limit exceeded, terminating
170911.14/22649.27	% SZS status Ended for HL409445+5.p
170921.00/22650.60	% SZS status Started for HL409451+4.p
170921.00/22650.60	% SZS status GaveUp for HL409451+4.p
170921.00/22650.60	eprover: CPU time limit exceeded, terminating
170921.00/22650.60	% SZS status Ended for HL409451+4.p
170925.12/22651.09	% SZS status Started for HL409446+5.p
170925.12/22651.09	% SZS status GaveUp for HL409446+5.p
170925.12/22651.09	eprover: CPU time limit exceeded, terminating
170925.12/22651.09	% SZS status Ended for HL409446+5.p
170926.00/22651.29	% SZS status Started for HL409452+4.p
170926.00/22651.29	% SZS status GaveUp for HL409452+4.p
170926.00/22651.29	eprover: CPU time limit exceeded, terminating
170926.00/22651.29	% SZS status Ended for HL409452+4.p
170941.86/22653.37	% SZS status Started for HL409447+5.p
170941.86/22653.37	% SZS status GaveUp for HL409447+5.p
170941.86/22653.37	eprover: CPU time limit exceeded, terminating
170941.86/22653.37	% SZS status Ended for HL409447+5.p
170945.33/22653.88	% SZS status Started for HL409454+4.p
170945.33/22653.88	% SZS status GaveUp for HL409454+4.p
170945.33/22653.88	eprover: CPU time limit exceeded, terminating
170945.33/22653.88	% SZS status Ended for HL409454+4.p
170954.16/22655.13	% SZS status Started for HL409455+4.p
170954.16/22655.13	% SZS status GaveUp for HL409455+4.p
170954.16/22655.13	eprover: CPU time limit exceeded, terminating
170954.16/22655.13	% SZS status Ended for HL409455+4.p
170967.06/22656.94	% SZS status Started for HL409449+5.p
170967.06/22656.94	% SZS status GaveUp for HL409449+5.p
170967.06/22656.94	eprover: CPU time limit exceeded, terminating
170967.06/22656.94	% SZS status Ended for HL409449+5.p
170969.31/22657.22	% SZS status Started for HL409456+4.p
170969.31/22657.22	% SZS status GaveUp for HL409456+4.p
170969.31/22657.22	eprover: CPU time limit exceeded, terminating
170969.31/22657.22	% SZS status Ended for HL409456+4.p
170974.80/22657.96	% SZS status Started for HL409450+5.p
170974.80/22657.96	% SZS status GaveUp for HL409450+5.p
170974.80/22657.96	eprover: CPU time limit exceeded, terminating
170974.80/22657.96	% SZS status Ended for HL409450+5.p
170984.00/22659.30	% SZS status Started for HL409451+5.p
170984.00/22659.30	% SZS status GaveUp for HL409451+5.p
170984.00/22659.30	eprover: CPU time limit exceeded, terminating
170984.00/22659.30	% SZS status Ended for HL409451+5.p
170990.45/22660.21	% SZS status Started for HL409457+4.p
170990.45/22660.21	% SZS status GaveUp for HL409457+4.p
170990.45/22660.21	eprover: CPU time limit exceeded, terminating
170990.45/22660.21	% SZS status Ended for HL409457+4.p
170994.41/22660.78	% SZS status Started for HL409452+5.p
170994.41/22660.78	% SZS status GaveUp for HL409452+5.p
170994.41/22660.78	eprover: CPU time limit exceeded, terminating
170994.41/22660.78	% SZS status Ended for HL409452+5.p
171002.83/22661.93	% SZS status Started for HL409458+4.p
171002.83/22661.93	% SZS status GaveUp for HL409458+4.p
171002.83/22661.93	eprover: CPU time limit exceeded, terminating
171002.83/22661.93	% SZS status Ended for HL409458+4.p
171012.50/22663.28	% SZS status Started for HL409459+4.p
171012.50/22663.28	% SZS status GaveUp for HL409459+4.p
171012.50/22663.28	eprover: CPU time limit exceeded, terminating
171012.50/22663.28	% SZS status Ended for HL409459+4.p
171015.33/22663.71	% SZS status Started for HL409454+5.p
171015.33/22663.71	% SZS status GaveUp for HL409454+5.p
171015.33/22663.71	eprover: CPU time limit exceeded, terminating
171015.33/22663.71	% SZS status Ended for HL409454+5.p
171027.89/22665.34	% SZS status Started for HL409460+4.p
171027.89/22665.34	% SZS status GaveUp for HL409460+4.p
171027.89/22665.34	eprover: CPU time limit exceeded, terminating
171027.89/22665.34	% SZS status Ended for HL409460+4.p
171036.17/22666.34	% SZS status Started for HL409455+5.p
171036.17/22666.34	% SZS status GaveUp for HL409455+5.p
171036.17/22666.34	eprover: CPU time limit exceeded, terminating
171036.17/22666.34	% SZS status Ended for HL409455+5.p
171037.67/22666.62	% SZS status Started for HL409456+5.p
171037.67/22666.62	% SZS status GaveUp for HL409456+5.p
171037.67/22666.62	eprover: CPU time limit exceeded, terminating
171037.67/22666.62	% SZS status Ended for HL409456+5.p
171040.36/22666.89	% SZS status Started for HL409462+4.p
171040.36/22666.89	% SZS status GaveUp for HL409462+4.p
171040.36/22666.89	eprover: CPU time limit exceeded, terminating
171040.36/22666.89	% SZS status Ended for HL409462+4.p
171051.89/22668.39	% SZS status Started for HL409457+5.p
171051.89/22668.39	% SZS status GaveUp for HL409457+5.p
171051.89/22668.39	eprover: CPU time limit exceeded, terminating
171051.89/22668.39	% SZS status Ended for HL409457+5.p
171060.06/22669.40	% SZS status Started for HL409463+4.p
171060.06/22669.40	% SZS status GaveUp for HL409463+4.p
171060.06/22669.40	eprover: CPU time limit exceeded, terminating
171060.06/22669.40	% SZS status Ended for HL409463+4.p
171064.78/22670.01	% SZS status Started for HL409464+4.p
171064.78/22670.01	% SZS status GaveUp for HL409464+4.p
171064.78/22670.01	eprover: CPU time limit exceeded, terminating
171064.78/22670.01	% SZS status Ended for HL409464+4.p
171067.94/22670.48	% SZS status Started for HL409458+5.p
171067.94/22670.48	% SZS status GaveUp for HL409458+5.p
171067.94/22670.48	eprover: CPU time limit exceeded, terminating
171067.94/22670.48	% SZS status Ended for HL409458+5.p
171081.80/22672.28	% SZS status Started for HL409459+5.p
171081.80/22672.28	% SZS status GaveUp for HL409459+5.p
171081.80/22672.28	eprover: CPU time limit exceeded, terminating
171081.80/22672.28	% SZS status Ended for HL409459+5.p
171083.89/22672.55	% SZS status Started for HL409466+4.p
171083.89/22672.55	% SZS status GaveUp for HL409466+4.p
171083.89/22672.55	eprover: CPU time limit exceeded, terminating
171083.89/22672.55	% SZS status Ended for HL409466+4.p
171091.78/22673.53	% SZS status Started for HL409467+4.p
171091.78/22673.53	% SZS status GaveUp for HL409467+4.p
171091.78/22673.53	eprover: CPU time limit exceeded, terminating
171091.78/22673.53	% SZS status Ended for HL409467+4.p
171095.83/22674.05	% SZS status Started for HL409460+5.p
171095.83/22674.05	% SZS status GaveUp for HL409460+5.p
171095.83/22674.05	eprover: CPU time limit exceeded, terminating
171095.83/22674.05	% SZS status Ended for HL409460+5.p
171107.52/22675.77	% SZS status Started for HL409468+4.p
171107.52/22675.77	% SZS status GaveUp for HL409468+4.p
171107.52/22675.77	eprover: CPU time limit exceeded, terminating
171107.52/22675.77	% SZS status Ended for HL409468+4.p
171110.88/22676.16	% SZS status Started for HL409462+5.p
171110.88/22676.16	% SZS status GaveUp for HL409462+5.p
171110.88/22676.16	eprover: CPU time limit exceeded, terminating
171110.88/22676.16	% SZS status Ended for HL409462+5.p
171114.70/22676.61	% SZS status Started for HL409468+5.p
171114.70/22676.61	% SZS status GaveUp for HL409468+5.p
171114.70/22676.61	eprover: CPU time limit exceeded, terminating
171114.70/22676.61	% SZS status Ended for HL409468+5.p
171118.94/22677.19	% SZS status Started for HL409469+4.p
171118.94/22677.19	% SZS status GaveUp for HL409469+4.p
171118.94/22677.19	eprover: CPU time limit exceeded, terminating
171118.94/22677.19	% SZS status Ended for HL409469+4.p
171125.05/22678.10	% SZS status Started for HL409463+5.p
171125.05/22678.10	% SZS status GaveUp for HL409463+5.p
171125.05/22678.10	eprover: CPU time limit exceeded, terminating
171125.05/22678.10	% SZS status Ended for HL409463+5.p
171134.86/22679.31	% SZS status Started for HL409471+4.p
171134.86/22679.31	% SZS status GaveUp for HL409471+4.p
171134.86/22679.31	eprover: CPU time limit exceeded, terminating
171134.86/22679.31	% SZS status Ended for HL409471+4.p
171136.56/22679.60	% SZS status Started for HL409464+5.p
171136.56/22679.60	% SZS status GaveUp for HL409464+5.p
171136.56/22679.60	eprover: CPU time limit exceeded, terminating
171136.56/22679.60	% SZS status Ended for HL409464+5.p
171142.97/22680.43	% SZS status Started for HL409472+4.p
171142.97/22680.43	% SZS status GaveUp for HL409472+4.p
171142.97/22680.43	eprover: CPU time limit exceeded, terminating
171142.97/22680.43	% SZS status Ended for HL409472+4.p
171151.92/22681.64	% SZS status Started for HL409466+5.p
171151.92/22681.64	% SZS status GaveUp for HL409466+5.p
171151.92/22681.64	eprover: CPU time limit exceeded, terminating
171151.92/22681.64	% SZS status Ended for HL409466+5.p
171158.64/22682.51	% SZS status Started for HL409473+4.p
171158.64/22682.51	% SZS status GaveUp for HL409473+4.p
171158.64/22682.51	eprover: CPU time limit exceeded, terminating
171158.64/22682.51	% SZS status Ended for HL409473+4.p
171166.30/22683.51	% SZS status Started for HL409474+4.p
171166.30/22683.51	% SZS status GaveUp for HL409474+4.p
171166.30/22683.51	eprover: CPU time limit exceeded, terminating
171166.30/22683.51	% SZS status Ended for HL409474+4.p
171173.44/22684.35	% SZS status Started for HL409467+5.p
171173.44/22684.35	% SZS status GaveUp for HL409467+5.p
171173.44/22684.35	eprover: CPU time limit exceeded, terminating
171173.44/22684.35	% SZS status Ended for HL409467+5.p
171182.47/22685.58	% SZS status Started for HL409475+4.p
171182.47/22685.58	% SZS status GaveUp for HL409475+4.p
171182.47/22685.58	eprover: CPU time limit exceeded, terminating
171182.47/22685.58	% SZS status Ended for HL409475+4.p
171195.52/22687.26	% SZS status Started for HL409469+5.p
171195.52/22687.26	% SZS status GaveUp for HL409469+5.p
171195.52/22687.26	eprover: CPU time limit exceeded, terminating
171195.52/22687.26	% SZS status Ended for HL409469+5.p
171197.00/22687.47	% SZS status Started for HL409476+4.p
171197.00/22687.47	% SZS status GaveUp for HL409476+4.p
171197.00/22687.47	eprover: CPU time limit exceeded, terminating
171197.00/22687.47	% SZS status Ended for HL409476+4.p
171203.34/22688.27	% SZS status Started for HL409471+5.p
171203.34/22688.27	% SZS status GaveUp for HL409471+5.p
171203.34/22688.27	eprover: CPU time limit exceeded, terminating
171203.34/22688.27	% SZS status Ended for HL409471+5.p
171210.25/22689.30	% SZS status Started for HL409472+5.p
171210.25/22689.30	% SZS status GaveUp for HL409472+5.p
171210.25/22689.30	eprover: CPU time limit exceeded, terminating
171210.25/22689.30	% SZS status Ended for HL409472+5.p
171218.89/22690.36	% SZS status Started for HL409477+4.p
171218.89/22690.36	% SZS status GaveUp for HL409477+4.p
171218.89/22690.36	eprover: CPU time limit exceeded, terminating
171218.89/22690.36	% SZS status Ended for HL409477+4.p
171220.44/22690.55	% SZS status Started for HL409477+5.p
171220.44/22690.55	% SZS status GaveUp for HL409477+5.p
171220.44/22690.55	eprover: CPU time limit exceeded, terminating
171220.44/22690.55	% SZS status Ended for HL409477+5.p
171222.38/22690.80	% SZS status Started for HL409473+5.p
171222.38/22690.80	% SZS status GaveUp for HL409473+5.p
171222.38/22690.80	eprover: CPU time limit exceeded, terminating
171222.38/22690.80	% SZS status Ended for HL409473+5.p
171228.66/22691.59	% SZS status Started for HL409478+4.p
171228.66/22691.59	% SZS status GaveUp for HL409478+4.p
171228.66/22691.59	eprover: CPU time limit exceeded, terminating
171228.66/22691.59	% SZS status Ended for HL409478+4.p
171238.73/22692.97	% SZS status Started for HL409474+5.p
171238.73/22692.97	% SZS status GaveUp for HL409474+5.p
171238.73/22692.97	eprover: CPU time limit exceeded, terminating
171238.73/22692.97	% SZS status Ended for HL409474+5.p
171242.27/22693.44	% SZS status Started for HL409479+4.p
171242.27/22693.44	% SZS status GaveUp for HL409479+4.p
171242.27/22693.44	eprover: CPU time limit exceeded, terminating
171242.27/22693.44	% SZS status Ended for HL409479+4.p
171246.31/22693.90	% SZS status Started for HL409480+4.p
171246.31/22693.90	% SZS status GaveUp for HL409480+4.p
171246.31/22693.90	eprover: CPU time limit exceeded, terminating
171246.31/22693.90	% SZS status Ended for HL409480+4.p
171255.86/22695.26	% SZS status Started for HL409475+5.p
171255.86/22695.26	% SZS status GaveUp for HL409475+5.p
171255.86/22695.26	eprover: CPU time limit exceeded, terminating
171255.86/22695.26	% SZS status Ended for HL409475+5.p
171261.72/22696.07	% SZS status Started for HL409481+4.p
171261.72/22696.07	% SZS status GaveUp for HL409481+4.p
171261.72/22696.07	eprover: CPU time limit exceeded, terminating
171261.72/22696.07	% SZS status Ended for HL409481+4.p
171267.00/22696.68	% SZS status Started for HL409476+5.p
171267.00/22696.68	% SZS status GaveUp for HL409476+5.p
171267.00/22696.68	eprover: CPU time limit exceeded, terminating
171267.00/22696.68	% SZS status Ended for HL409476+5.p
171268.94/22696.92	% SZS status Started for HL409479+5.p
171268.94/22696.92	% SZS status GaveUp for HL409479+5.p
171268.94/22696.92	eprover: CPU time limit exceeded, terminating
171268.94/22696.92	% SZS status Ended for HL409479+5.p
171269.56/22696.99	% SZS status Started for HL409482+4.p
171269.56/22696.99	% SZS status GaveUp for HL409482+4.p
171269.56/22696.99	eprover: CPU time limit exceeded, terminating
171269.56/22696.99	% SZS status Ended for HL409482+4.p
171286.56/22699.13	% SZS status Started for HL409484+4.p
171286.56/22699.13	% SZS status GaveUp for HL409484+4.p
171286.56/22699.13	eprover: CPU time limit exceeded, terminating
171286.56/22699.13	% SZS status Ended for HL409484+4.p
171293.00/22699.95	% SZS status Started for HL409485+4.p
171293.00/22699.95	% SZS status GaveUp for HL409485+4.p
171293.00/22699.95	eprover: CPU time limit exceeded, terminating
171293.00/22699.95	% SZS status Ended for HL409485+4.p
171297.67/22700.51	% SZS status Started for HL409478+5.p
171297.67/22700.51	% SZS status GaveUp for HL409478+5.p
171297.67/22700.51	eprover: CPU time limit exceeded, terminating
171297.67/22700.51	% SZS status Ended for HL409478+5.p
171310.44/22702.17	% SZS status Started for HL409486+4.p
171310.44/22702.17	% SZS status GaveUp for HL409486+4.p
171310.44/22702.17	eprover: CPU time limit exceeded, terminating
171310.44/22702.17	% SZS status Ended for HL409486+4.p
171318.12/22703.12	% SZS status Started for HL409480+5.p
171318.12/22703.12	% SZS status GaveUp for HL409480+5.p
171318.12/22703.12	eprover: CPU time limit exceeded, terminating
171318.12/22703.12	% SZS status Ended for HL409480+5.p
171321.86/22703.54	% SZS status Started for HL409487+4.p
171321.86/22703.54	% SZS status GaveUp for HL409487+4.p
171321.86/22703.54	eprover: CPU time limit exceeded, terminating
171321.86/22703.54	% SZS status Ended for HL409487+4.p
171326.88/22704.21	% SZS status Started for HL409481+5.p
171326.88/22704.21	% SZS status GaveUp for HL409481+5.p
171326.88/22704.21	eprover: CPU time limit exceeded, terminating
171326.88/22704.21	% SZS status Ended for HL409481+5.p
171339.00/22705.68	% SZS status Started for HL409482+5.p
171339.00/22705.68	% SZS status GaveUp for HL409482+5.p
171339.00/22705.68	eprover: CPU time limit exceeded, terminating
171339.00/22705.68	% SZS status Ended for HL409482+5.p
171342.59/22706.15	% SZS status Started for HL409488+4.p
171342.59/22706.15	% SZS status GaveUp for HL409488+4.p
171342.59/22706.15	eprover: CPU time limit exceeded, terminating
171342.59/22706.15	% SZS status Ended for HL409488+4.p
171348.83/22706.94	% SZS status Started for HL409484+5.p
171348.83/22706.94	% SZS status GaveUp for HL409484+5.p
171348.83/22706.94	eprover: CPU time limit exceeded, terminating
171348.83/22706.94	% SZS status Ended for HL409484+5.p
171351.28/22707.26	% SZS status Started for HL409489+4.p
171351.28/22707.26	% SZS status GaveUp for HL409489+4.p
171351.28/22707.26	eprover: CPU time limit exceeded, terminating
171351.28/22707.26	% SZS status Ended for HL409489+4.p
171351.84/22707.35	% SZS status Started for HL409485+5.p
171351.84/22707.35	% SZS status GaveUp for HL409485+5.p
171351.84/22707.35	eprover: CPU time limit exceeded, terminating
171351.84/22707.35	% SZS status Ended for HL409485+5.p
171365.78/22709.17	% SZS status Started for HL409490+4.p
171365.78/22709.17	% SZS status GaveUp for HL409490+4.p
171365.78/22709.17	eprover: CPU time limit exceeded, terminating
171365.78/22709.17	% SZS status Ended for HL409490+4.p
171374.36/22710.18	% SZS status Started for HL409486+5.p
171374.36/22710.18	% SZS status GaveUp for HL409486+5.p
171374.36/22710.18	eprover: CPU time limit exceeded, terminating
171374.36/22710.18	% SZS status Ended for HL409486+5.p
171376.00/22710.35	% SZS status Started for HL409491+4.p
171376.00/22710.35	% SZS status GaveUp for HL409491+4.p
171376.00/22710.35	eprover: CPU time limit exceeded, terminating
171376.00/22710.35	% SZS status Ended for HL409491+4.p
171390.70/22712.20	% SZS status Started for HL409493+4.p
171390.70/22712.20	% SZS status GaveUp for HL409493+4.p
171390.70/22712.20	eprover: CPU time limit exceeded, terminating
171390.70/22712.20	% SZS status Ended for HL409493+4.p
171391.94/22712.43	% SZS status Started for HL409487+5.p
171391.94/22712.43	% SZS status GaveUp for HL409487+5.p
171391.94/22712.43	eprover: CPU time limit exceeded, terminating
171391.94/22712.43	% SZS status Ended for HL409487+5.p
171399.38/22713.35	% SZS status Started for HL409493+5.p
171399.38/22713.35	% SZS status GaveUp for HL409493+5.p
171399.38/22713.35	eprover: CPU time limit exceeded, terminating
171399.38/22713.35	% SZS status Ended for HL409493+5.p
171400.06/22713.38	% SZS status Started for HL409494+4.p
171400.06/22713.38	% SZS status GaveUp for HL409494+4.p
171400.06/22713.38	eprover: CPU time limit exceeded, terminating
171400.06/22713.38	% SZS status Ended for HL409494+4.p
171403.70/22713.81	% SZS status Started for HL409488+5.p
171403.70/22713.81	% SZS status GaveUp for HL409488+5.p
171403.70/22713.81	eprover: CPU time limit exceeded, terminating
171403.70/22713.81	% SZS status Ended for HL409488+5.p
171414.52/22715.26	% SZS status Started for HL409494+5.p
171414.52/22715.26	% SZS status GaveUp for HL409494+5.p
171414.52/22715.26	eprover: CPU time limit exceeded, terminating
171414.52/22715.26	% SZS status Ended for HL409494+5.p
171417.64/22715.60	% SZS status Started for HL409495+4.p
171417.64/22715.60	% SZS status GaveUp for HL409495+4.p
171417.64/22715.60	eprover: CPU time limit exceeded, terminating
171417.64/22715.60	% SZS status Ended for HL409495+4.p
171419.41/22715.96	% SZS status Started for HL409489+5.p
171419.41/22715.96	% SZS status GaveUp for HL409489+5.p
171419.41/22715.96	eprover: CPU time limit exceeded, terminating
171419.41/22715.96	% SZS status Ended for HL409489+5.p
171423.28/22716.41	% SZS status Started for HL409496+4.p
171423.28/22716.41	% SZS status GaveUp for HL409496+4.p
171423.28/22716.41	eprover: CPU time limit exceeded, terminating
171423.28/22716.41	% SZS status Ended for HL409496+4.p
171423.28/22716.45	% SZS status Started for HL409495+5.p
171423.28/22716.45	% SZS status GaveUp for HL409495+5.p
171423.28/22716.45	eprover: CPU time limit exceeded, terminating
171423.28/22716.45	% SZS status Ended for HL409495+5.p
171426.59/22716.85	% SZS status Started for HL409496+5.p
171426.59/22716.85	% SZS status GaveUp for HL409496+5.p
171426.59/22716.85	eprover: CPU time limit exceeded, terminating
171426.59/22716.85	% SZS status Ended for HL409496+5.p
171430.11/22717.26	% SZS status Started for HL409490+5.p
171430.11/22717.26	% SZS status GaveUp for HL409490+5.p
171430.11/22717.26	eprover: CPU time limit exceeded, terminating
171430.11/22717.26	% SZS status Ended for HL409490+5.p
171433.00/22717.63	% SZS status Started for HL409491+5.p
171433.00/22717.63	% SZS status GaveUp for HL409491+5.p
171433.00/22717.63	eprover: CPU time limit exceeded, terminating
171433.00/22717.63	% SZS status Ended for HL409491+5.p
171441.20/22718.68	% SZS status Started for HL409497+4.p
171441.20/22718.68	% SZS status GaveUp for HL409497+4.p
171441.20/22718.68	eprover: CPU time limit exceeded, terminating
171441.20/22718.68	% SZS status Ended for HL409497+4.p
171444.14/22719.10	% SZS status Started for HL409498+4.p
171444.14/22719.10	% SZS status GaveUp for HL409498+4.p
171444.14/22719.10	eprover: CPU time limit exceeded, terminating
171444.14/22719.10	% SZS status Ended for HL409498+4.p
171446.95/22719.44	% SZS status Started for HL409498+5.p
171446.95/22719.44	% SZS status GaveUp for HL409498+5.p
171446.95/22719.44	eprover: CPU time limit exceeded, terminating
171446.95/22719.44	% SZS status Ended for HL409498+5.p
171446.95/22719.48	% SZS status Started for HL409499+4.p
171446.95/22719.48	% SZS status GaveUp for HL409499+4.p
171446.95/22719.48	eprover: CPU time limit exceeded, terminating
171446.95/22719.48	% SZS status Ended for HL409499+4.p
171450.69/22719.88	% SZS status Started for HL409499+5.p
171450.69/22719.88	% SZS status GaveUp for HL409499+5.p
171450.69/22719.88	eprover: CPU time limit exceeded, terminating
171450.69/22719.88	% SZS status Ended for HL409499+5.p
171453.59/22720.30	% SZS status Started for HL409500+4.p
171453.59/22720.30	% SZS status GaveUp for HL409500+4.p
171453.59/22720.30	eprover: CPU time limit exceeded, terminating
171453.59/22720.30	% SZS status Ended for HL409500+4.p
171465.25/22721.71	% SZS status Started for HL409501+4.p
171465.25/22721.71	% SZS status GaveUp for HL409501+4.p
171465.25/22721.71	eprover: CPU time limit exceeded, terminating
171465.25/22721.71	% SZS status Ended for HL409501+4.p
171468.48/22722.13	% SZS status Started for HL409501+5.p
171468.48/22722.13	% SZS status GaveUp for HL409501+5.p
171468.48/22722.13	eprover: CPU time limit exceeded, terminating
171468.48/22722.13	% SZS status Ended for HL409501+5.p
171469.78/22722.46	% SZS status Started for HL409502+4.p
171469.78/22722.46	% SZS status GaveUp for HL409502+4.p
171469.78/22722.46	eprover: CPU time limit exceeded, terminating
171469.78/22722.46	% SZS status Ended for HL409502+4.p
171470.47/22722.54	% SZS status Started for HL409502+5.p
171470.47/22722.54	% SZS status GaveUp for HL409502+5.p
171470.47/22722.54	eprover: CPU time limit exceeded, terminating
171470.47/22722.54	% SZS status Ended for HL409502+5.p
171474.33/22722.92	% SZS status Started for HL409503+4.p
171474.33/22722.92	% SZS status GaveUp for HL409503+4.p
171474.33/22722.92	eprover: CPU time limit exceeded, terminating
171474.33/22722.92	% SZS status Ended for HL409503+4.p
171476.69/22723.34	% SZS status Started for HL409503+5.p
171476.69/22723.34	% SZS status GaveUp for HL409503+5.p
171476.69/22723.34	eprover: CPU time limit exceeded, terminating
171476.69/22723.34	% SZS status Ended for HL409503+5.p
171488.62/22724.74	% SZS status Started for HL409504+4.p
171488.62/22724.74	% SZS status GaveUp for HL409504+4.p
171488.62/22724.74	eprover: CPU time limit exceeded, terminating
171488.62/22724.74	% SZS status Ended for HL409504+4.p
171494.31/22725.55	% SZS status Started for HL409505+4.p
171494.31/22725.55	% SZS status GaveUp for HL409505+4.p
171494.31/22725.55	eprover: CPU time limit exceeded, terminating
171494.31/22725.55	% SZS status Ended for HL409505+4.p
171499.06/22726.09	% SZS status Started for HL409506+4.p
171499.06/22726.09	% SZS status GaveUp for HL409506+4.p
171499.06/22726.09	eprover: CPU time limit exceeded, terminating
171499.06/22726.09	% SZS status Ended for HL409506+4.p
171507.09/22727.11	% SZS status Started for HL409497+5.p
171507.09/22727.11	% SZS status GaveUp for HL409497+5.p
171507.09/22727.11	eprover: CPU time limit exceeded, terminating
171507.09/22727.11	% SZS status Ended for HL409497+5.p
171512.39/22727.78	% SZS status Started for HL409507+4.p
171512.39/22727.78	% SZS status GaveUp for HL409507+4.p
171512.39/22727.78	eprover: CPU time limit exceeded, terminating
171512.39/22727.78	% SZS status Ended for HL409507+4.p
171520.14/22728.72	% SZS status Started for HL409507+5.p
171520.14/22728.72	% SZS status GaveUp for HL409507+5.p
171520.14/22728.72	eprover: CPU time limit exceeded, terminating
171520.14/22728.72	% SZS status Ended for HL409507+5.p
171522.58/22729.12	% SZS status Started for HL409508+4.p
171522.58/22729.12	% SZS status GaveUp for HL409508+4.p
171522.58/22729.12	eprover: CPU time limit exceeded, terminating
171522.58/22729.12	% SZS status Ended for HL409508+4.p
171523.19/22729.23	% SZS status Started for HL409500+5.p
171523.19/22729.23	% SZS status GaveUp for HL409500+5.p
171523.19/22729.23	eprover: CPU time limit exceeded, terminating
171523.19/22729.23	% SZS status Ended for HL409500+5.p
171531.61/22730.15	% SZS status Started for HL409508+5.p
171531.61/22730.15	% SZS status GaveUp for HL409508+5.p
171531.61/22730.15	eprover: CPU time limit exceeded, terminating
171531.61/22730.15	% SZS status Ended for HL409508+5.p
171537.34/22730.89	% SZS status Started for HL409509+4.p
171537.34/22730.89	% SZS status GaveUp for HL409509+4.p
171537.34/22730.89	eprover: CPU time limit exceeded, terminating
171537.34/22730.89	% SZS status Ended for HL409509+4.p
171544.31/22731.75	% SZS status Started for HL409509+5.p
171544.31/22731.75	% SZS status GaveUp for HL409509+5.p
171544.31/22731.75	eprover: CPU time limit exceeded, terminating
171544.31/22731.75	% SZS status Ended for HL409509+5.p
171547.50/22732.15	% SZS status Started for HL409510+4.p
171547.50/22732.15	% SZS status GaveUp for HL409510+4.p
171547.50/22732.15	eprover: CPU time limit exceeded, terminating
171547.50/22732.15	% SZS status Ended for HL409510+4.p
171548.08/22732.27	% SZS status Started for HL409510+5.p
171548.08/22732.27	% SZS status GaveUp for HL409510+5.p
171548.08/22732.27	eprover: CPU time limit exceeded, terminating
171548.08/22732.27	% SZS status Ended for HL409510+5.p
171555.52/22733.19	% SZS status Started for HL409511+4.p
171555.52/22733.19	% SZS status GaveUp for HL409511+4.p
171555.52/22733.19	eprover: CPU time limit exceeded, terminating
171555.52/22733.19	% SZS status Ended for HL409511+4.p
171557.80/22733.46	% SZS status Started for HL409504+5.p
171557.80/22733.46	% SZS status GaveUp for HL409504+5.p
171557.80/22733.46	eprover: CPU time limit exceeded, terminating
171557.80/22733.46	% SZS status Ended for HL409504+5.p
171559.88/22733.83	% SZS status Started for HL409505+5.p
171559.88/22733.83	% SZS status GaveUp for HL409505+5.p
171559.88/22733.83	eprover: CPU time limit exceeded, terminating
171559.88/22733.83	% SZS status Ended for HL409505+5.p
171562.44/22734.06	% SZS status Started for HL409511+5.p
171562.44/22734.06	% SZS status GaveUp for HL409511+5.p
171562.44/22734.06	eprover: CPU time limit exceeded, terminating
171562.44/22734.06	% SZS status Ended for HL409511+5.p
171565.14/22734.41	% SZS status Started for HL409506+5.p
171565.14/22734.41	% SZS status GaveUp for HL409506+5.p
171565.14/22734.41	eprover: CPU time limit exceeded, terminating
171565.14/22734.41	% SZS status Ended for HL409506+5.p
171568.03/22734.79	% SZS status Started for HL409512+4.p
171568.03/22734.79	% SZS status GaveUp for HL409512+4.p
171568.03/22734.79	eprover: CPU time limit exceeded, terminating
171568.03/22734.79	% SZS status Ended for HL409512+4.p
171572.56/22735.28	% SZS status Started for HL409512+5.p
171572.56/22735.28	% SZS status GaveUp for HL409512+5.p
171572.56/22735.28	eprover: CPU time limit exceeded, terminating
171572.56/22735.28	% SZS status Ended for HL409512+5.p
171572.56/22735.30	% SZS status Started for HL409513+4.p
171572.56/22735.30	% SZS status GaveUp for HL409513+4.p
171572.56/22735.30	eprover: CPU time limit exceeded, terminating
171572.56/22735.30	% SZS status Ended for HL409513+4.p
171580.09/22736.22	% SZS status Started for HL409513+5.p
171580.09/22736.22	% SZS status GaveUp for HL409513+5.p
171580.09/22736.22	eprover: CPU time limit exceeded, terminating
171580.09/22736.22	% SZS status Ended for HL409513+5.p
171581.59/22736.49	% SZS status Started for HL409514+4.p
171581.59/22736.49	% SZS status GaveUp for HL409514+4.p
171581.59/22736.49	eprover: CPU time limit exceeded, terminating
171581.59/22736.49	% SZS status Ended for HL409514+4.p
171584.97/22736.86	% SZS status Started for HL409514+5.p
171584.97/22736.86	% SZS status GaveUp for HL409514+5.p
171584.97/22736.86	eprover: CPU time limit exceeded, terminating
171584.97/22736.86	% SZS status Ended for HL409514+5.p
171586.67/22737.10	% SZS status Started for HL409515+4.p
171586.67/22737.10	% SZS status GaveUp for HL409515+4.p
171586.67/22737.10	eprover: CPU time limit exceeded, terminating
171586.67/22737.10	% SZS status Ended for HL409515+4.p
171589.56/22737.44	% SZS status Started for HL409515+5.p
171589.56/22737.44	% SZS status GaveUp for HL409515+5.p
171589.56/22737.44	eprover: CPU time limit exceeded, terminating
171589.56/22737.44	% SZS status Ended for HL409515+5.p
171593.50/22737.94	% SZS status Started for HL409518+4.p
171593.50/22737.94	% SZS status GaveUp for HL409518+4.p
171593.50/22737.94	eprover: CPU time limit exceeded, terminating
171593.50/22737.94	% SZS status Ended for HL409518+4.p
171596.06/22738.31	% SZS status Started for HL409518+5.p
171596.06/22738.31	% SZS status GaveUp for HL409518+5.p
171596.06/22738.31	eprover: CPU time limit exceeded, terminating
171596.06/22738.31	% SZS status Ended for HL409518+5.p
171596.06/22738.33	% SZS status Started for HL409519+4.p
171596.06/22738.33	% SZS status GaveUp for HL409519+4.p
171596.06/22738.33	eprover: CPU time limit exceeded, terminating
171596.06/22738.33	% SZS status Ended for HL409519+4.p
171604.00/22739.26	% SZS status Started for HL409519+5.p
171604.00/22739.26	% SZS status GaveUp for HL409519+5.p
171604.00/22739.26	eprover: CPU time limit exceeded, terminating
171604.00/22739.26	% SZS status Ended for HL409519+5.p
171605.86/22739.52	% SZS status Started for HL409520+4.p
171605.86/22739.52	% SZS status GaveUp for HL409520+4.p
171605.86/22739.52	eprover: CPU time limit exceeded, terminating
171605.86/22739.52	% SZS status Ended for HL409520+4.p
171608.62/22739.90	% SZS status Started for HL409520+5.p
171608.62/22739.90	% SZS status GaveUp for HL409520+5.p
171608.62/22739.90	eprover: CPU time limit exceeded, terminating
171608.62/22739.90	% SZS status Ended for HL409520+5.p
171610.78/22740.13	% SZS status Started for HL409521+4.p
171610.78/22740.13	% SZS status GaveUp for HL409521+4.p
171610.78/22740.13	eprover: CPU time limit exceeded, terminating
171610.78/22740.13	% SZS status Ended for HL409521+4.p
171613.42/22740.48	% SZS status Started for HL409521+5.p
171613.42/22740.48	% SZS status GaveUp for HL409521+5.p
171613.42/22740.48	eprover: CPU time limit exceeded, terminating
171613.42/22740.48	% SZS status Ended for HL409521+5.p
171618.72/22741.10	% SZS status Started for HL409523+4.p
171618.72/22741.10	% SZS status GaveUp for HL409523+4.p
171618.72/22741.10	eprover: CPU time limit exceeded, terminating
171618.72/22741.10	% SZS status Ended for HL409523+4.p
171620.67/22741.35	% SZS status Started for HL409523+5.p
171620.67/22741.35	% SZS status GaveUp for HL409523+5.p
171620.67/22741.35	eprover: CPU time limit exceeded, terminating
171620.67/22741.35	% SZS status Ended for HL409523+5.p
171620.67/22741.36	% SZS status Started for HL409524+4.p
171620.67/22741.36	% SZS status GaveUp for HL409524+4.p
171620.67/22741.36	eprover: CPU time limit exceeded, terminating
171620.67/22741.36	% SZS status Ended for HL409524+4.p
171628.00/22742.29	% SZS status Started for HL409524+5.p
171628.00/22742.29	% SZS status GaveUp for HL409524+5.p
171628.00/22742.29	eprover: CPU time limit exceeded, terminating
171628.00/22742.29	% SZS status Ended for HL409524+5.p
171629.98/22742.59	% SZS status Started for HL409525+4.p
171629.98/22742.59	% SZS status GaveUp for HL409525+4.p
171629.98/22742.59	eprover: CPU time limit exceeded, terminating
171629.98/22742.59	% SZS status Ended for HL409525+4.p
171634.19/22743.16	% SZS status Started for HL409525+5.p
171634.19/22743.16	% SZS status GaveUp for HL409525+5.p
171634.19/22743.16	eprover: CPU time limit exceeded, terminating
171634.19/22743.16	% SZS status Ended for HL409525+5.p
171635.22/22743.32	% SZS status Started for HL409526+4.p
171635.22/22743.32	% SZS status GaveUp for HL409526+4.p
171635.22/22743.32	eprover: CPU time limit exceeded, terminating
171635.22/22743.32	% SZS status Ended for HL409526+4.p
171636.77/22743.51	% SZS status Started for HL409526+5.p
171636.77/22743.51	% SZS status GaveUp for HL409526+5.p
171636.77/22743.51	eprover: CPU time limit exceeded, terminating
171636.77/22743.51	% SZS status Ended for HL409526+5.p
171641.77/22744.15	% SZS status Started for HL409529+4.p
171641.77/22744.15	% SZS status GaveUp for HL409529+4.p
171641.77/22744.15	eprover: CPU time limit exceeded, terminating
171641.77/22744.15	% SZS status Ended for HL409529+4.p
171643.39/22744.38	% SZS status Started for HL409529+5.p
171643.39/22744.38	% SZS status GaveUp for HL409529+5.p
171643.39/22744.38	eprover: CPU time limit exceeded, terminating
171643.39/22744.38	% SZS status Ended for HL409529+5.p
171646.09/22744.65	% SZS status Started for HL409530+4.p
171646.09/22744.65	% SZS status GaveUp for HL409530+4.p
171646.09/22744.65	eprover: CPU time limit exceeded, terminating
171646.09/22744.65	% SZS status Ended for HL409530+4.p
171651.91/22745.40	% SZS status Started for HL409530+5.p
171651.91/22745.40	% SZS status GaveUp for HL409530+5.p
171651.91/22745.40	eprover: CPU time limit exceeded, terminating
171651.91/22745.40	% SZS status Ended for HL409530+5.p
171654.97/22745.83	% SZS status Started for HL409531+4.p
171654.97/22745.83	% SZS status GaveUp for HL409531+4.p
171654.97/22745.83	eprover: CPU time limit exceeded, terminating
171654.97/22745.83	% SZS status Ended for HL409531+4.p
171659.09/22746.34	% SZS status Started for HL409531+5.p
171659.09/22746.34	% SZS status GaveUp for HL409531+5.p
171659.09/22746.34	eprover: CPU time limit exceeded, terminating
171659.09/22746.34	% SZS status Ended for HL409531+5.p
171659.09/22746.35	% SZS status Started for HL409533+4.p
171659.09/22746.35	% SZS status GaveUp for HL409533+4.p
171659.09/22746.35	eprover: CPU time limit exceeded, terminating
171659.09/22746.35	% SZS status Ended for HL409533+4.p
171660.56/22746.55	% SZS status Started for HL409533+5.p
171660.56/22746.55	% SZS status GaveUp for HL409533+5.p
171660.56/22746.55	eprover: CPU time limit exceeded, terminating
171660.56/22746.55	% SZS status Ended for HL409533+5.p
171666.23/22747.18	% SZS status Started for HL409535+4.p
171666.23/22747.18	% SZS status GaveUp for HL409535+4.p
171666.23/22747.18	eprover: CPU time limit exceeded, terminating
171666.23/22747.18	% SZS status Ended for HL409535+4.p
171667.44/22747.41	% SZS status Started for HL409535+5.p
171667.44/22747.41	% SZS status GaveUp for HL409535+5.p
171667.44/22747.41	eprover: CPU time limit exceeded, terminating
171667.44/22747.41	% SZS status Ended for HL409535+5.p
171669.91/22747.69	% SZS status Started for HL409537+4.p
171669.91/22747.69	% SZS status GaveUp for HL409537+4.p
171669.91/22747.69	eprover: CPU time limit exceeded, terminating
171669.91/22747.69	% SZS status Ended for HL409537+4.p
171675.92/22748.43	% SZS status Started for HL409537+5.p
171675.92/22748.43	% SZS status GaveUp for HL409537+5.p
171675.92/22748.43	eprover: CPU time limit exceeded, terminating
171675.92/22748.43	% SZS status Ended for HL409537+5.p
171680.36/22748.96	% SZS status Started for HL409539+4.p
171680.36/22748.96	% SZS status GaveUp for HL409539+4.p
171680.36/22748.96	eprover: CPU time limit exceeded, terminating
171680.36/22748.96	% SZS status Ended for HL409539+4.p
171683.52/22749.37	% SZS status Started for HL409539+5.p
171683.52/22749.37	% SZS status GaveUp for HL409539+5.p
171683.52/22749.37	eprover: CPU time limit exceeded, terminating
171683.52/22749.37	% SZS status Ended for HL409539+5.p
171683.52/22749.37	% SZS status Started for HL409540+4.p
171683.52/22749.37	% SZS status GaveUp for HL409540+4.p
171683.52/22749.37	eprover: CPU time limit exceeded, terminating
171683.52/22749.37	% SZS status Ended for HL409540+4.p
171684.81/22749.58	% SZS status Started for HL409540+5.p
171684.81/22749.58	% SZS status GaveUp for HL409540+5.p
171684.81/22749.58	eprover: CPU time limit exceeded, terminating
171684.81/22749.58	% SZS status Ended for HL409540+5.p
171689.72/22750.21	% SZS status Started for HL409541+4.p
171689.72/22750.21	% SZS status GaveUp for HL409541+4.p
171689.72/22750.21	eprover: CPU time limit exceeded, terminating
171689.72/22750.21	% SZS status Ended for HL409541+4.p
171691.92/22750.44	% SZS status Started for HL409541+5.p
171691.92/22750.44	% SZS status GaveUp for HL409541+5.p
171691.92/22750.44	eprover: CPU time limit exceeded, terminating
171691.92/22750.44	% SZS status Ended for HL409541+5.p
171694.08/22750.72	% SZS status Started for HL409542+4.p
171694.08/22750.72	% SZS status GaveUp for HL409542+4.p
171694.08/22750.72	eprover: CPU time limit exceeded, terminating
171694.08/22750.72	% SZS status Ended for HL409542+4.p
171701.30/22751.60	% SZS status Started for HL409542+5.p
171701.30/22751.60	% SZS status GaveUp for HL409542+5.p
171701.30/22751.60	eprover: CPU time limit exceeded, terminating
171701.30/22751.60	% SZS status Ended for HL409542+5.p
171703.80/22752.02	% SZS status Started for HL409543+4.p
171703.80/22752.02	% SZS status GaveUp for HL409543+4.p
171703.80/22752.02	eprover: CPU time limit exceeded, terminating
171703.80/22752.02	% SZS status Ended for HL409543+4.p
171706.83/22752.40	% SZS status Started for HL409543+5.p
171706.83/22752.40	% SZS status GaveUp for HL409543+5.p
171706.83/22752.40	eprover: CPU time limit exceeded, terminating
171706.83/22752.40	% SZS status Ended for HL409543+5.p
171707.25/22752.43	% SZS status Started for HL409544+4.p
171707.25/22752.43	% SZS status GaveUp for HL409544+4.p
171707.25/22752.43	eprover: CPU time limit exceeded, terminating
171707.25/22752.43	% SZS status Ended for HL409544+4.p
171708.08/22752.62	% SZS status Started for HL409544+5.p
171708.08/22752.62	% SZS status GaveUp for HL409544+5.p
171708.08/22752.62	eprover: CPU time limit exceeded, terminating
171708.08/22752.62	% SZS status Ended for HL409544+5.p
171716.92/22753.74	% SZS status Started for HL409545+4.p
171716.92/22753.74	% SZS status GaveUp for HL409545+4.p
171716.92/22753.74	eprover: CPU time limit exceeded, terminating
171716.92/22753.74	% SZS status Ended for HL409545+4.p
171717.31/22753.81	% SZS status Started for HL409546+4.p
171717.31/22753.81	% SZS status GaveUp for HL409546+4.p
171717.31/22753.81	eprover: CPU time limit exceeded, terminating
171717.31/22753.81	% SZS status Ended for HL409546+4.p
171728.36/22755.26	% SZS status Started for HL409547+4.p
171728.36/22755.26	% SZS status GaveUp for HL409547+4.p
171728.36/22755.26	eprover: CPU time limit exceeded, terminating
171728.36/22755.26	% SZS status Ended for HL409547+4.p
171729.03/22755.44	% SZS status Started for HL409547+5.p
171729.03/22755.44	% SZS status GaveUp for HL409547+5.p
171729.03/22755.44	eprover: CPU time limit exceeded, terminating
171729.03/22755.44	% SZS status Ended for HL409547+5.p
171730.22/22755.48	% SZS status Started for HL409549+4.p
171730.22/22755.48	% SZS status GaveUp for HL409549+4.p
171730.22/22755.48	eprover: CPU time limit exceeded, terminating
171730.22/22755.48	% SZS status Ended for HL409549+4.p
171740.92/22756.85	% SZS status Started for HL409550+5.p
171740.92/22756.85	% SZS status GaveUp for HL409550+5.p
171740.92/22756.85	eprover: CPU time limit exceeded, terminating
171740.92/22756.85	% SZS status Ended for HL409550+5.p
171741.97/22756.95	% SZS status Started for HL409550+4.p
171741.97/22756.95	% SZS status GaveUp for HL409550+4.p
171741.97/22756.95	eprover: CPU time limit exceeded, terminating
171741.97/22756.95	% SZS status Ended for HL409550+4.p
171752.48/22758.28	% SZS status Started for HL409551+4.p
171752.48/22758.28	% SZS status GaveUp for HL409551+4.p
171752.48/22758.28	eprover: CPU time limit exceeded, terminating
171752.48/22758.28	% SZS status Ended for HL409551+4.p
171753.64/22758.57	% SZS status Started for HL409552+4.p
171753.64/22758.57	% SZS status GaveUp for HL409552+4.p
171753.64/22758.57	eprover: CPU time limit exceeded, terminating
171753.64/22758.57	% SZS status Ended for HL409552+4.p
171753.94/22758.66	% SZS status Started for HL409551+5.p
171753.94/22758.66	% SZS status GaveUp for HL409551+5.p
171753.94/22758.66	eprover: CPU time limit exceeded, terminating
171753.94/22758.66	% SZS status Ended for HL409551+5.p
171765.61/22760.02	% SZS status Started for HL409552+5.p
171765.61/22760.02	% SZS status GaveUp for HL409552+5.p
171765.61/22760.02	eprover: CPU time limit exceeded, terminating
171765.61/22760.02	% SZS status Ended for HL409552+5.p
171765.61/22760.03	% SZS status Started for HL409553+4.p
171765.61/22760.03	% SZS status GaveUp for HL409553+4.p
171765.61/22760.03	eprover: CPU time limit exceeded, terminating
171765.61/22760.03	% SZS status Ended for HL409553+4.p
171777.41/22761.49	% SZS status Started for HL409553+5.p
171777.41/22761.49	% SZS status GaveUp for HL409553+5.p
171777.41/22761.49	eprover: CPU time limit exceeded, terminating
171777.41/22761.49	% SZS status Ended for HL409553+5.p
171778.03/22761.52	% SZS status Started for HL409545+5.p
171778.03/22761.52	% SZS status GaveUp for HL409545+5.p
171778.03/22761.52	eprover: CPU time limit exceeded, terminating
171778.03/22761.52	% SZS status Ended for HL409545+5.p
171778.52/22761.59	% SZS status Started for HL409554+4.p
171778.52/22761.59	% SZS status GaveUp for HL409554+4.p
171778.52/22761.59	eprover: CPU time limit exceeded, terminating
171778.52/22761.59	% SZS status Ended for HL409554+4.p
171779.16/22761.70	% SZS status Started for HL409554+5.p
171779.16/22761.70	% SZS status GaveUp for HL409554+5.p
171779.16/22761.70	eprover: CPU time limit exceeded, terminating
171779.16/22761.70	% SZS status Ended for HL409554+5.p
171790.09/22763.04	% SZS status Started for HL409555+4.p
171790.09/22763.04	% SZS status GaveUp for HL409555+4.p
171790.09/22763.04	eprover: CPU time limit exceeded, terminating
171790.09/22763.04	% SZS status Ended for HL409555+4.p
171790.09/22763.06	% SZS status Started for HL409555+5.p
171790.09/22763.06	% SZS status GaveUp for HL409555+5.p
171790.09/22763.06	eprover: CPU time limit exceeded, terminating
171790.09/22763.06	% SZS status Ended for HL409555+5.p
171790.69/22763.13	% SZS status Started for HL409546+5.p
171790.69/22763.13	% SZS status GaveUp for HL409546+5.p
171790.69/22763.13	eprover: CPU time limit exceeded, terminating
171790.69/22763.13	% SZS status Ended for HL409546+5.p
171797.81/22764.03	% SZS status Started for HL409549+5.p
171797.81/22764.03	% SZS status GaveUp for HL409549+5.p
171797.81/22764.03	eprover: CPU time limit exceeded, terminating
171797.81/22764.03	% SZS status Ended for HL409549+5.p
171801.09/22764.52	% SZS status Started for HL409556+4.p
171801.09/22764.52	% SZS status GaveUp for HL409556+4.p
171801.09/22764.52	eprover: CPU time limit exceeded, terminating
171801.09/22764.52	% SZS status Ended for HL409556+4.p
171801.09/22764.55	% SZS status Started for HL409556+5.p
171801.09/22764.55	% SZS status GaveUp for HL409556+5.p
171801.09/22764.55	eprover: CPU time limit exceeded, terminating
171801.09/22764.55	% SZS status Ended for HL409556+5.p
171804.45/22764.62	% SZS status Started for HL409557+4.p
171804.45/22764.62	% SZS status GaveUp for HL409557+4.p
171804.45/22764.62	eprover: CPU time limit exceeded, terminating
171804.45/22764.62	% SZS status Ended for HL409557+4.p
171805.86/22764.89	% SZS status Started for HL409557+5.p
171805.86/22764.89	% SZS status GaveUp for HL409557+5.p
171805.86/22764.89	eprover: CPU time limit exceeded, terminating
171805.86/22764.89	% SZS status Ended for HL409557+5.p
171815.97/22766.07	% SZS status Started for HL409558+4.p
171815.97/22766.07	% SZS status GaveUp for HL409558+4.p
171815.97/22766.07	eprover: CPU time limit exceeded, terminating
171815.97/22766.07	% SZS status Ended for HL409558+4.p
171816.25/22766.09	% SZS status Started for HL409558+5.p
171816.25/22766.09	% SZS status GaveUp for HL409558+5.p
171816.25/22766.09	eprover: CPU time limit exceeded, terminating
171816.25/22766.09	% SZS status Ended for HL409558+5.p
171816.61/22766.16	% SZS status Started for HL409559+4.p
171816.61/22766.16	% SZS status GaveUp for HL409559+4.p
171816.61/22766.16	eprover: CPU time limit exceeded, terminating
171816.61/22766.16	% SZS status Ended for HL409559+4.p
171823.25/22767.06	% SZS status Started for HL409559+5.p
171823.25/22767.06	% SZS status GaveUp for HL409559+5.p
171823.25/22767.06	eprover: CPU time limit exceeded, terminating
171823.25/22767.06	% SZS status Ended for HL409559+5.p
171827.77/22767.57	% SZS status Started for HL409560+4.p
171827.77/22767.57	% SZS status GaveUp for HL409560+4.p
171827.77/22767.57	eprover: CPU time limit exceeded, terminating
171827.77/22767.57	% SZS status Ended for HL409560+4.p
171829.25/22767.84	% SZS status Started for HL409561+4.p
171829.25/22767.84	% SZS status GaveUp for HL409561+4.p
171829.25/22767.84	eprover: CPU time limit exceeded, terminating
171829.25/22767.84	% SZS status Ended for HL409561+4.p
171829.47/22767.93	% SZS status Started for HL409561+5.p
171829.47/22767.93	% SZS status GaveUp for HL409561+5.p
171829.47/22767.93	eprover: CPU time limit exceeded, terminating
171829.47/22767.93	% SZS status Ended for HL409561+5.p
171839.34/22769.10	% SZS status Started for HL409563+4.p
171839.34/22769.10	% SZS status GaveUp for HL409563+4.p
171839.34/22769.10	eprover: CPU time limit exceeded, terminating
171839.34/22769.10	% SZS status Ended for HL409563+4.p
171840.12/22769.20	% SZS status Started for HL409564+4.p
171840.12/22769.20	% SZS status GaveUp for HL409564+4.p
171840.12/22769.20	eprover: CPU time limit exceeded, terminating
171840.12/22769.20	% SZS status Ended for HL409564+4.p
171840.56/22769.27	% SZS status Started for HL409563+5.p
171840.56/22769.27	% SZS status GaveUp for HL409563+5.p
171840.56/22769.27	eprover: CPU time limit exceeded, terminating
171840.56/22769.27	% SZS status Ended for HL409563+5.p
171845.31/22769.83	% SZS status Started for HL409560+5.p
171845.31/22769.83	% SZS status GaveUp for HL409560+5.p
171845.31/22769.83	eprover: CPU time limit exceeded, terminating
171845.31/22769.83	% SZS status Ended for HL409560+5.p
171847.12/22770.10	% SZS status Started for HL409564+5.p
171847.12/22770.10	% SZS status GaveUp for HL409564+5.p
171847.12/22770.10	eprover: CPU time limit exceeded, terminating
171847.12/22770.10	% SZS status Ended for HL409564+5.p
171852.77/22770.82	% SZS status Started for HL409565+4.p
171852.77/22770.82	% SZS status GaveUp for HL409565+4.p
171852.77/22770.82	eprover: CPU time limit exceeded, terminating
171852.77/22770.82	% SZS status Ended for HL409565+4.p
171854.06/22770.95	% SZS status Started for HL409566+4.p
171854.06/22770.95	% SZS status GaveUp for HL409566+4.p
171854.06/22770.95	eprover: CPU time limit exceeded, terminating
171854.06/22770.95	% SZS status Ended for HL409566+4.p
171854.06/22771.02	% SZS status Started for HL409565+5.p
171854.06/22771.02	% SZS status GaveUp for HL409565+5.p
171854.06/22771.02	eprover: CPU time limit exceeded, terminating
171854.06/22771.02	% SZS status Ended for HL409565+5.p
171863.19/22772.13	% SZS status Started for HL409566+5.p
171863.19/22772.13	% SZS status GaveUp for HL409566+5.p
171863.19/22772.13	eprover: CPU time limit exceeded, terminating
171863.19/22772.13	% SZS status Ended for HL409566+5.p
171864.25/22772.23	% SZS status Started for HL409567+4.p
171864.25/22772.23	% SZS status GaveUp for HL409567+4.p
171864.25/22772.23	eprover: CPU time limit exceeded, terminating
171864.25/22772.23	% SZS status Ended for HL409567+4.p
171864.50/22772.31	% SZS status Started for HL409567+5.p
171864.50/22772.31	% SZS status GaveUp for HL409567+5.p
171864.50/22772.31	eprover: CPU time limit exceeded, terminating
171864.50/22772.31	% SZS status Ended for HL409567+5.p
171869.22/22772.86	% SZS status Started for HL409568+4.p
171869.22/22772.86	% SZS status GaveUp for HL409568+4.p
171869.22/22772.86	eprover: CPU time limit exceeded, terminating
171869.22/22772.86	% SZS status Ended for HL409568+4.p
171871.09/22773.14	% SZS status Started for HL409568+5.p
171871.09/22773.14	% SZS status GaveUp for HL409568+5.p
171871.09/22773.14	eprover: CPU time limit exceeded, terminating
171871.09/22773.14	% SZS status Ended for HL409568+5.p
171877.25/22773.85	% SZS status Started for HL409569+4.p
171877.25/22773.85	% SZS status GaveUp for HL409569+4.p
171877.25/22773.85	eprover: CPU time limit exceeded, terminating
171877.25/22773.85	% SZS status Ended for HL409569+4.p
171878.25/22773.99	% SZS status Started for HL409569+5.p
171878.25/22773.99	% SZS status GaveUp for HL409569+5.p
171878.25/22773.99	eprover: CPU time limit exceeded, terminating
171878.25/22773.99	% SZS status Ended for HL409569+5.p
171879.44/22774.17	% SZS status Started for HL409570+4.p
171879.44/22774.17	% SZS status GaveUp for HL409570+4.p
171879.44/22774.17	eprover: CPU time limit exceeded, terminating
171879.44/22774.17	% SZS status Ended for HL409570+4.p
171890.33/22775.17	% SZS status Started for HL409570+5.p
171890.33/22775.17	% SZS status GaveUp for HL409570+5.p
171890.33/22775.17	eprover: CPU time limit exceeded, terminating
171890.33/22775.17	% SZS status Ended for HL409570+5.p
171891.09/22775.26	% SZS status Started for HL409571+4.p
171891.09/22775.26	% SZS status GaveUp for HL409571+4.p
171891.09/22775.26	eprover: CPU time limit exceeded, terminating
171891.09/22775.26	% SZS status Ended for HL409571+4.p
171891.77/22775.35	% SZS status Started for HL409571+5.p
171891.77/22775.35	% SZS status GaveUp for HL409571+5.p
171891.77/22775.35	eprover: CPU time limit exceeded, terminating
171891.77/22775.35	% SZS status Ended for HL409571+5.p
171895.98/22775.90	% SZS status Started for HL409572+4.p
171895.98/22775.90	% SZS status GaveUp for HL409572+4.p
171895.98/22775.90	eprover: CPU time limit exceeded, terminating
171895.98/22775.90	% SZS status Ended for HL409572+4.p
171898.81/22776.29	% SZS status Started for HL409572+5.p
171898.81/22776.29	% SZS status GaveUp for HL409572+5.p
171898.81/22776.29	eprover: CPU time limit exceeded, terminating
171898.81/22776.29	% SZS status Ended for HL409572+5.p
171903.88/22776.88	% SZS status Started for HL409573+4.p
171903.88/22776.88	% SZS status GaveUp for HL409573+4.p
171903.88/22776.88	eprover: CPU time limit exceeded, terminating
171903.88/22776.88	% SZS status Ended for HL409573+4.p
171904.89/22777.02	% SZS status Started for HL409573+5.p
171904.89/22777.02	% SZS status GaveUp for HL409573+5.p
171904.89/22777.02	eprover: CPU time limit exceeded, terminating
171904.89/22777.02	% SZS status Ended for HL409573+5.p
171906.03/22777.21	% SZS status Started for HL409575+4.p
171906.03/22777.21	% SZS status GaveUp for HL409575+4.p
171906.03/22777.21	eprover: CPU time limit exceeded, terminating
171906.03/22777.21	% SZS status Ended for HL409575+4.p
171913.89/22778.19	% SZS status Started for HL409575+5.p
171913.89/22778.19	% SZS status GaveUp for HL409575+5.p
171913.89/22778.19	eprover: CPU time limit exceeded, terminating
171913.89/22778.19	% SZS status Ended for HL409575+5.p
171915.14/22778.29	% SZS status Started for HL409576+4.p
171915.14/22778.29	% SZS status GaveUp for HL409576+4.p
171915.14/22778.29	eprover: CPU time limit exceeded, terminating
171915.14/22778.29	% SZS status Ended for HL409576+4.p
171915.72/22778.38	% SZS status Started for HL409576+5.p
171915.72/22778.38	% SZS status GaveUp for HL409576+5.p
171915.72/22778.38	eprover: CPU time limit exceeded, terminating
171915.72/22778.38	% SZS status Ended for HL409576+5.p
171921.17/22779.05	% SZS status Started for HL409577+4.p
171921.17/22779.05	% SZS status GaveUp for HL409577+4.p
171921.17/22779.05	eprover: CPU time limit exceeded, terminating
171921.17/22779.05	% SZS status Ended for HL409577+4.p
171923.30/22779.32	% SZS status Started for HL409577+5.p
171923.30/22779.32	% SZS status GaveUp for HL409577+5.p
171923.30/22779.32	eprover: CPU time limit exceeded, terminating
171923.30/22779.32	% SZS status Ended for HL409577+5.p
171927.81/22779.91	% SZS status Started for HL409578+4.p
171927.81/22779.91	% SZS status GaveUp for HL409578+4.p
171927.81/22779.91	eprover: CPU time limit exceeded, terminating
171927.81/22779.91	% SZS status Ended for HL409578+4.p
171928.88/22780.05	% SZS status Started for HL409578+5.p
171928.88/22780.05	% SZS status GaveUp for HL409578+5.p
171928.88/22780.05	eprover: CPU time limit exceeded, terminating
171928.88/22780.05	% SZS status Ended for HL409578+5.p
171930.17/22780.24	% SZS status Started for HL409579+4.p
171930.17/22780.24	% SZS status GaveUp for HL409579+4.p
171930.17/22780.24	eprover: CPU time limit exceeded, terminating
171930.17/22780.24	% SZS status Ended for HL409579+4.p
171938.34/22781.23	% SZS status Started for HL409579+5.p
171938.34/22781.23	% SZS status GaveUp for HL409579+5.p
171938.34/22781.23	eprover: CPU time limit exceeded, terminating
171938.34/22781.23	% SZS status Ended for HL409579+5.p
171939.00/22781.33	% SZS status Started for HL409580+4.p
171939.00/22781.33	% SZS status GaveUp for HL409580+4.p
171939.00/22781.33	eprover: CPU time limit exceeded, terminating
171939.00/22781.33	% SZS status Ended for HL409580+4.p
171939.80/22781.42	% SZS status Started for HL409580+5.p
171939.80/22781.42	% SZS status GaveUp for HL409580+5.p
171939.80/22781.42	eprover: CPU time limit exceeded, terminating
171939.80/22781.42	% SZS status Ended for HL409580+5.p
171946.31/22782.22	% SZS status Started for HL409582+4.p
171946.31/22782.22	% SZS status GaveUp for HL409582+4.p
171946.31/22782.22	eprover: CPU time limit exceeded, terminating
171946.31/22782.22	% SZS status Ended for HL409582+4.p
171947.48/22782.38	% SZS status Started for HL409582+5.p
171947.48/22782.38	% SZS status GaveUp for HL409582+5.p
171947.48/22782.38	eprover: CPU time limit exceeded, terminating
171947.48/22782.38	% SZS status Ended for HL409582+5.p
171951.78/22782.94	% SZS status Started for HL409583+4.p
171951.78/22782.94	% SZS status GaveUp for HL409583+4.p
171951.78/22782.94	eprover: CPU time limit exceeded, terminating
171951.78/22782.94	% SZS status Ended for HL409583+4.p
171952.77/22783.08	% SZS status Started for HL409583+5.p
171952.77/22783.08	% SZS status GaveUp for HL409583+5.p
171952.77/22783.08	eprover: CPU time limit exceeded, terminating
171952.77/22783.08	% SZS status Ended for HL409583+5.p
171954.09/22783.28	% SZS status Started for HL409584+4.p
171954.09/22783.28	% SZS status GaveUp for HL409584+4.p
171954.09/22783.28	eprover: CPU time limit exceeded, terminating
171954.09/22783.28	% SZS status Ended for HL409584+4.p
171961.55/22784.26	% SZS status Started for HL409584+5.p
171961.55/22784.26	% SZS status GaveUp for HL409584+5.p
171961.55/22784.26	eprover: CPU time limit exceeded, terminating
171961.55/22784.26	% SZS status Ended for HL409584+5.p
171962.72/22784.36	% SZS status Started for HL409585+4.p
171962.72/22784.36	% SZS status GaveUp for HL409585+4.p
171962.72/22784.36	eprover: CPU time limit exceeded, terminating
171962.72/22784.36	% SZS status Ended for HL409585+4.p
171971.34/22785.41	% SZS status Started for HL409586+5.p
171971.34/22785.41	% SZS status GaveUp for HL409586+5.p
171971.34/22785.41	eprover: CPU time limit exceeded, terminating
171971.34/22785.41	% SZS status Ended for HL409586+5.p
171971.34/22785.43	% SZS status Started for HL409586+4.p
171971.34/22785.43	% SZS status GaveUp for HL409586+4.p
171971.34/22785.43	eprover: CPU time limit exceeded, terminating
171971.34/22785.43	% SZS status Ended for HL409586+4.p
171975.33/22785.98	% SZS status Started for HL409587+4.p
171975.33/22785.98	% SZS status GaveUp for HL409587+4.p
171975.33/22785.98	eprover: CPU time limit exceeded, terminating
171975.33/22785.98	% SZS status Ended for HL409587+4.p
171976.08/22786.11	% SZS status Started for HL409587+5.p
171976.08/22786.11	% SZS status GaveUp for HL409587+5.p
171976.08/22786.11	eprover: CPU time limit exceeded, terminating
171976.08/22786.11	% SZS status Ended for HL409587+5.p
171979.64/22786.46	% SZS status Started for HL409588+4.p
171979.64/22786.46	% SZS status GaveUp for HL409588+4.p
171979.64/22786.46	eprover: CPU time limit exceeded, terminating
171979.64/22786.46	% SZS status Ended for HL409588+4.p
171986.14/22787.29	% SZS status Started for HL409588+5.p
171986.14/22787.29	% SZS status GaveUp for HL409588+5.p
171986.14/22787.29	eprover: CPU time limit exceeded, terminating
171986.14/22787.29	% SZS status Ended for HL409588+5.p
171986.95/22787.39	% SZS status Started for HL409589+4.p
171986.95/22787.39	% SZS status GaveUp for HL409589+4.p
171986.95/22787.39	eprover: CPU time limit exceeded, terminating
171986.95/22787.39	% SZS status Ended for HL409589+4.p
171995.42/22788.44	% SZS status Started for HL409589+5.p
171995.42/22788.44	% SZS status GaveUp for HL409589+5.p
171995.42/22788.44	eprover: CPU time limit exceeded, terminating
171995.42/22788.44	% SZS status Ended for HL409589+5.p
171995.42/22788.45	% SZS status Started for HL409590+4.p
171995.42/22788.45	% SZS status GaveUp for HL409590+4.p
171995.42/22788.45	eprover: CPU time limit exceeded, terminating
171995.42/22788.45	% SZS status Ended for HL409590+4.p
172000.39/22789.09	% SZS status Started for HL409590+5.p
172000.39/22789.09	% SZS status GaveUp for HL409590+5.p
172000.39/22789.09	eprover: CPU time limit exceeded, terminating
172000.39/22789.09	% SZS status Ended for HL409590+5.p
172001.06/22789.20	% SZS status Started for HL409591+4.p
172001.06/22789.20	% SZS status GaveUp for HL409591+4.p
172001.06/22789.20	eprover: CPU time limit exceeded, terminating
172001.06/22789.20	% SZS status Ended for HL409591+4.p
172002.97/22789.50	% SZS status Started for HL409591+5.p
172002.97/22789.50	% SZS status GaveUp for HL409591+5.p
172002.97/22789.50	eprover: CPU time limit exceeded, terminating
172002.97/22789.50	% SZS status Ended for HL409591+5.p
172010.02/22790.32	% SZS status Started for HL409592+4.p
172010.02/22790.32	% SZS status GaveUp for HL409592+4.p
172010.02/22790.32	eprover: CPU time limit exceeded, terminating
172010.02/22790.32	% SZS status Ended for HL409592+4.p
172011.14/22790.43	% SZS status Started for HL409592+5.p
172011.14/22790.43	% SZS status GaveUp for HL409592+5.p
172011.14/22790.43	eprover: CPU time limit exceeded, terminating
172011.14/22790.43	% SZS status Ended for HL409592+5.p
172018.95/22791.49	% SZS status Started for HL409593+5.p
172018.95/22791.49	% SZS status GaveUp for HL409593+5.p
172018.95/22791.49	eprover: CPU time limit exceeded, terminating
172018.95/22791.49	% SZS status Ended for HL409593+5.p
172018.95/22791.50	% SZS status Started for HL409593+4.p
172018.95/22791.50	% SZS status GaveUp for HL409593+4.p
172018.95/22791.50	eprover: CPU time limit exceeded, terminating
172018.95/22791.50	% SZS status Ended for HL409593+4.p
172024.30/22792.18	% SZS status Started for HL409596+4.p
172024.30/22792.18	% SZS status GaveUp for HL409596+4.p
172024.30/22792.18	eprover: CPU time limit exceeded, terminating
172024.30/22792.18	% SZS status Ended for HL409596+4.p
172027.30/22792.53	% SZS status Started for HL409597+4.p
172027.30/22792.53	% SZS status GaveUp for HL409597+4.p
172027.30/22792.53	eprover: CPU time limit exceeded, terminating
172027.30/22792.53	% SZS status Ended for HL409597+4.p
172031.36/22793.03	% SZS status Started for HL409585+5.p
172031.36/22793.03	% SZS status GaveUp for HL409585+5.p
172031.36/22793.03	eprover: CPU time limit exceeded, terminating
172031.36/22793.03	% SZS status Ended for HL409585+5.p
172033.47/22793.36	% SZS status Started for HL409597+5.p
172033.47/22793.36	% SZS status GaveUp for HL409597+5.p
172033.47/22793.36	eprover: CPU time limit exceeded, terminating
172033.47/22793.36	% SZS status Ended for HL409597+5.p
172034.33/22793.47	% SZS status Started for HL409598+4.p
172034.33/22793.47	% SZS status GaveUp for HL409598+4.p
172034.33/22793.47	eprover: CPU time limit exceeded, terminating
172034.33/22793.47	% SZS status Ended for HL409598+4.p
172043.31/22794.55	% SZS status Started for HL409599+4.p
172043.31/22794.55	% SZS status GaveUp for HL409599+4.p
172043.31/22794.55	eprover: CPU time limit exceeded, terminating
172043.31/22794.55	% SZS status Ended for HL409599+4.p
172043.50/22794.58	% SZS status Started for HL409598+5.p
172043.50/22794.58	% SZS status GaveUp for HL409598+5.p
172043.50/22794.58	eprover: CPU time limit exceeded, terminating
172043.50/22794.58	% SZS status Ended for HL409598+5.p
172048.47/22795.24	% SZS status Started for HL409599+5.p
172048.47/22795.24	% SZS status GaveUp for HL409599+5.p
172048.47/22795.24	eprover: CPU time limit exceeded, terminating
172048.47/22795.24	% SZS status Ended for HL409599+5.p
172051.36/22795.62	% SZS status Started for HL409600+4.p
172051.36/22795.62	% SZS status GaveUp for HL409600+4.p
172051.36/22795.62	eprover: CPU time limit exceeded, terminating
172051.36/22795.62	% SZS status Ended for HL409600+4.p
172055.27/22796.05	% SZS status Started for HL409600+5.p
172055.27/22796.05	% SZS status GaveUp for HL409600+5.p
172055.27/22796.05	eprover: CPU time limit exceeded, terminating
172055.27/22796.05	% SZS status Ended for HL409600+5.p
172057.88/22796.38	% SZS status Started for HL409601+4.p
172057.88/22796.38	% SZS status GaveUp for HL409601+4.p
172057.88/22796.38	eprover: CPU time limit exceeded, terminating
172057.88/22796.38	% SZS status Ended for HL409601+4.p
172059.52/22796.60	% SZS status Started for HL409601+5.p
172059.52/22796.60	% SZS status GaveUp for HL409601+5.p
172059.52/22796.60	eprover: CPU time limit exceeded, terminating
172059.52/22796.60	% SZS status Ended for HL409601+5.p
172067.59/22797.58	% SZS status Started for HL409602+4.p
172067.59/22797.58	% SZS status GaveUp for HL409602+4.p
172067.59/22797.58	eprover: CPU time limit exceeded, terminating
172067.59/22797.58	% SZS status Ended for HL409602+4.p
172067.59/22797.62	% SZS status Started for HL409602+5.p
172067.59/22797.62	% SZS status GaveUp for HL409602+5.p
172067.59/22797.62	eprover: CPU time limit exceeded, terminating
172067.59/22797.62	% SZS status Ended for HL409602+5.p
172073.00/22798.27	% SZS status Started for HL409604+4.p
172073.00/22798.27	% SZS status GaveUp for HL409604+4.p
172073.00/22798.27	eprover: CPU time limit exceeded, terminating
172073.00/22798.27	% SZS status Ended for HL409604+4.p
172075.48/22798.65	% SZS status Started for HL409604+5.p
172075.48/22798.65	% SZS status GaveUp for HL409604+5.p
172075.48/22798.65	eprover: CPU time limit exceeded, terminating
172075.48/22798.65	% SZS status Ended for HL409604+5.p
172078.95/22799.09	% SZS status Started for HL409605+4.p
172078.95/22799.09	% SZS status GaveUp for HL409605+4.p
172078.95/22799.09	eprover: CPU time limit exceeded, terminating
172078.95/22799.09	% SZS status Ended for HL409605+4.p
172082.23/22799.42	% SZS status Started for HL409605+5.p
172082.23/22799.42	% SZS status GaveUp for HL409605+5.p
172082.23/22799.42	eprover: CPU time limit exceeded, terminating
172082.23/22799.42	% SZS status Ended for HL409605+5.p
172083.58/22799.69	% SZS status Started for HL409607+4.p
172083.58/22799.69	% SZS status GaveUp for HL409607+4.p
172083.58/22799.69	eprover: CPU time limit exceeded, terminating
172083.58/22799.69	% SZS status Ended for HL409607+4.p
172090.36/22800.45	% SZS status Started for HL409596+5.p
172090.36/22800.45	% SZS status GaveUp for HL409596+5.p
172090.36/22800.45	eprover: CPU time limit exceeded, terminating
172090.36/22800.45	% SZS status Ended for HL409596+5.p
172091.58/22800.61	% SZS status Started for HL409607+5.p
172091.58/22800.61	% SZS status GaveUp for HL409607+5.p
172091.58/22800.61	eprover: CPU time limit exceeded, terminating
172091.58/22800.61	% SZS status Ended for HL409607+5.p
172091.84/22800.68	% SZS status Started for HL409608+4.p
172091.84/22800.68	% SZS status GaveUp for HL409608+4.p
172091.84/22800.68	eprover: CPU time limit exceeded, terminating
172091.84/22800.68	% SZS status Ended for HL409608+4.p
172096.95/22801.32	% SZS status Started for HL409608+5.p
172096.95/22801.32	% SZS status GaveUp for HL409608+5.p
172096.95/22801.32	eprover: CPU time limit exceeded, terminating
172096.95/22801.32	% SZS status Ended for HL409608+5.p
172099.91/22801.69	% SZS status Started for HL409609+4.p
172099.91/22801.69	% SZS status GaveUp for HL409609+4.p
172099.91/22801.69	eprover: CPU time limit exceeded, terminating
172099.91/22801.69	% SZS status Ended for HL409609+4.p
172103.73/22802.14	% SZS status Started for HL409609+5.p
172103.73/22802.14	% SZS status GaveUp for HL409609+5.p
172103.73/22802.14	eprover: CPU time limit exceeded, terminating
172103.73/22802.14	% SZS status Ended for HL409609+5.p
172106.75/22802.57	% SZS status Started for HL409610+4.p
172106.75/22802.57	% SZS status GaveUp for HL409610+4.p
172106.75/22802.57	eprover: CPU time limit exceeded, terminating
172106.75/22802.57	% SZS status Ended for HL409610+4.p
172108.41/22802.72	% SZS status Started for HL409610+5.p
172108.41/22802.72	% SZS status GaveUp for HL409610+5.p
172108.41/22802.72	eprover: CPU time limit exceeded, terminating
172108.41/22802.72	% SZS status Ended for HL409610+5.p
172114.12/22803.48	% SZS status Started for HL409611+4.p
172114.12/22803.48	% SZS status GaveUp for HL409611+4.p
172114.12/22803.48	eprover: CPU time limit exceeded, terminating
172114.12/22803.48	% SZS status Ended for HL409611+4.p
172115.39/22803.64	% SZS status Started for HL409611+5.p
172115.39/22803.64	% SZS status GaveUp for HL409611+5.p
172115.39/22803.64	eprover: CPU time limit exceeded, terminating
172115.39/22803.64	% SZS status Ended for HL409611+5.p
172115.95/22803.72	% SZS status Started for HL409612+4.p
172115.95/22803.72	% SZS status GaveUp for HL409612+4.p
172115.95/22803.72	eprover: CPU time limit exceeded, terminating
172115.95/22803.72	% SZS status Ended for HL409612+4.p
172121.72/22804.39	% SZS status Started for HL409612+5.p
172121.72/22804.39	% SZS status GaveUp for HL409612+5.p
172121.72/22804.39	eprover: CPU time limit exceeded, terminating
172121.72/22804.39	% SZS status Ended for HL409612+5.p
172123.81/22804.72	% SZS status Started for HL409613+4.p
172123.81/22804.72	% SZS status GaveUp for HL409613+4.p
172123.81/22804.72	eprover: CPU time limit exceeded, terminating
172123.81/22804.72	% SZS status Ended for HL409613+4.p
172127.58/22805.17	% SZS status Started for HL409613+5.p
172127.58/22805.17	% SZS status GaveUp for HL409613+5.p
172127.58/22805.17	eprover: CPU time limit exceeded, terminating
172127.58/22805.17	% SZS status Ended for HL409613+5.p
172132.44/22805.73	% SZS status Started for HL409614+4.p
172132.44/22805.73	% SZS status GaveUp for HL409614+4.p
172132.44/22805.73	eprover: CPU time limit exceeded, terminating
172132.44/22805.73	% SZS status Ended for HL409614+4.p
172132.56/22805.76	% SZS status Started for HL409614+5.p
172132.56/22805.76	% SZS status GaveUp for HL409614+5.p
172132.56/22805.76	eprover: CPU time limit exceeded, terminating
172132.56/22805.76	% SZS status Ended for HL409614+5.p
172137.95/22806.51	% SZS status Started for HL409615+4.p
172137.95/22806.51	% SZS status GaveUp for HL409615+4.p
172137.95/22806.51	eprover: CPU time limit exceeded, terminating
172137.95/22806.51	% SZS status Ended for HL409615+4.p
172139.61/22806.67	% SZS status Started for HL409615+5.p
172139.61/22806.67	% SZS status GaveUp for HL409615+5.p
172139.61/22806.67	eprover: CPU time limit exceeded, terminating
172139.61/22806.67	% SZS status Ended for HL409615+5.p
172140.30/22806.75	% SZS status Started for HL409616+4.p
172140.30/22806.75	% SZS status GaveUp for HL409616+4.p
172140.30/22806.75	eprover: CPU time limit exceeded, terminating
172140.30/22806.75	% SZS status Ended for HL409616+4.p
172145.77/22807.44	% SZS status Started for HL409616+5.p
172145.77/22807.44	% SZS status GaveUp for HL409616+5.p
172145.77/22807.44	eprover: CPU time limit exceeded, terminating
172145.77/22807.44	% SZS status Ended for HL409616+5.p
172147.77/22807.75	% SZS status Started for HL409617+4.p
172147.77/22807.75	% SZS status GaveUp for HL409617+4.p
172147.77/22807.75	eprover: CPU time limit exceeded, terminating
172147.77/22807.75	% SZS status Ended for HL409617+4.p
172150.98/22808.20	% SZS status Started for HL409617+5.p
172150.98/22808.20	% SZS status GaveUp for HL409617+5.p
172150.98/22808.20	eprover: CPU time limit exceeded, terminating
172150.98/22808.20	% SZS status Ended for HL409617+5.p
172158.00/22808.99	% SZS status Started for HL409618+4.p
172158.00/22808.99	% SZS status GaveUp for HL409618+4.p
172158.00/22808.99	eprover: CPU time limit exceeded, terminating
172158.00/22808.99	% SZS status Ended for HL409618+4.p
172162.22/22809.54	% SZS status Started for HL409619+4.p
172162.22/22809.54	% SZS status GaveUp for HL409619+4.p
172162.22/22809.54	eprover: CPU time limit exceeded, terminating
172162.22/22809.54	% SZS status Ended for HL409619+4.p
172163.58/22809.73	% SZS status Started for HL409619+5.p
172163.58/22809.73	% SZS status GaveUp for HL409619+5.p
172163.58/22809.73	eprover: CPU time limit exceeded, terminating
172163.58/22809.73	% SZS status Ended for HL409619+5.p
172163.91/22809.80	% SZS status Started for HL409620+4.p
172163.91/22809.80	% SZS status GaveUp for HL409620+4.p
172163.91/22809.80	eprover: CPU time limit exceeded, terminating
172163.91/22809.80	% SZS status Ended for HL409620+4.p
172169.53/22810.48	% SZS status Started for HL409620+5.p
172169.53/22810.48	% SZS status GaveUp for HL409620+5.p
172169.53/22810.48	eprover: CPU time limit exceeded, terminating
172169.53/22810.48	% SZS status Ended for HL409620+5.p
172171.98/22810.78	% SZS status Started for HL409622+4.p
172171.98/22810.78	% SZS status GaveUp for HL409622+4.p
172171.98/22810.78	eprover: CPU time limit exceeded, terminating
172171.98/22810.78	% SZS status Ended for HL409622+4.p
172176.27/22811.33	% SZS status Started for HL409622+5.p
172176.27/22811.33	% SZS status GaveUp for HL409622+5.p
172176.27/22811.33	eprover: CPU time limit exceeded, terminating
172176.27/22811.33	% SZS status Ended for HL409622+5.p
172181.50/22812.06	% SZS status Started for HL409623+4.p
172181.50/22812.06	% SZS status GaveUp for HL409623+4.p
172181.50/22812.06	eprover: CPU time limit exceeded, terminating
172181.50/22812.06	% SZS status Ended for HL409623+4.p
172186.09/22812.57	% SZS status Started for HL409623+5.p
172186.09/22812.57	% SZS status GaveUp for HL409623+5.p
172186.09/22812.57	eprover: CPU time limit exceeded, terminating
172186.09/22812.57	% SZS status Ended for HL409623+5.p
172187.70/22812.79	% SZS status Started for HL409624+4.p
172187.70/22812.79	% SZS status GaveUp for HL409624+4.p
172187.70/22812.79	eprover: CPU time limit exceeded, terminating
172187.70/22812.79	% SZS status Ended for HL409624+4.p
172191.50/22812.93	% SZS status Started for HL409624+5.p
172191.50/22812.93	% SZS status GaveUp for HL409624+5.p
172191.50/22812.93	eprover: CPU time limit exceeded, terminating
172191.50/22812.93	% SZS status Ended for HL409624+5.p
172195.98/22813.51	% SZS status Started for HL409625+4.p
172195.98/22813.51	% SZS status GaveUp for HL409625+4.p
172195.98/22813.51	eprover: CPU time limit exceeded, terminating
172195.98/22813.51	% SZS status Ended for HL409625+4.p
172198.17/22813.81	% SZS status Started for HL409625+5.p
172198.17/22813.81	% SZS status GaveUp for HL409625+5.p
172198.17/22813.81	eprover: CPU time limit exceeded, terminating
172198.17/22813.81	% SZS status Ended for HL409625+5.p
172203.72/22814.47	% SZS status Started for HL409626+4.p
172203.72/22814.47	% SZS status GaveUp for HL409626+4.p
172203.72/22814.47	eprover: CPU time limit exceeded, terminating
172203.72/22814.47	% SZS status Ended for HL409626+4.p
172208.97/22815.10	% SZS status Started for HL409626+5.p
172208.97/22815.10	% SZS status GaveUp for HL409626+5.p
172208.97/22815.10	eprover: CPU time limit exceeded, terminating
172208.97/22815.10	% SZS status Ended for HL409626+5.p
172212.25/22815.60	% SZS status Started for HL409627+4.p
172212.25/22815.60	% SZS status GaveUp for HL409627+4.p
172212.25/22815.60	eprover: CPU time limit exceeded, terminating
172212.25/22815.60	% SZS status Ended for HL409627+4.p
172214.03/22815.82	% SZS status Started for HL409627+5.p
172214.03/22815.82	% SZS status GaveUp for HL409627+5.p
172214.03/22815.82	eprover: CPU time limit exceeded, terminating
172214.03/22815.82	% SZS status Ended for HL409627+5.p
172215.62/22815.98	% SZS status Started for HL409628+4.p
172215.62/22815.98	% SZS status GaveUp for HL409628+4.p
172215.62/22815.98	eprover: CPU time limit exceeded, terminating
172215.62/22815.98	% SZS status Ended for HL409628+4.p
172220.22/22816.54	% SZS status Started for HL409628+5.p
172220.22/22816.54	% SZS status GaveUp for HL409628+5.p
172220.22/22816.54	eprover: CPU time limit exceeded, terminating
172220.22/22816.54	% SZS status Ended for HL409628+5.p
172222.33/22816.84	% SZS status Started for HL409618+5.p
172222.33/22816.84	% SZS status GaveUp for HL409618+5.p
172222.33/22816.84	eprover: CPU time limit exceeded, terminating
172222.33/22816.84	% SZS status Ended for HL409618+5.p
172222.33/22816.84	% SZS status Started for HL409629+4.p
172222.33/22816.84	% SZS status GaveUp for HL409629+4.p
172222.33/22816.84	eprover: CPU time limit exceeded, terminating
172222.33/22816.84	% SZS status Ended for HL409629+4.p
172228.52/22817.56	% SZS status Started for HL409629+5.p
172228.52/22817.56	% SZS status GaveUp for HL409629+5.p
172228.52/22817.56	eprover: CPU time limit exceeded, terminating
172228.52/22817.56	% SZS status Ended for HL409629+5.p
172232.72/22818.13	% SZS status Started for HL409630+4.p
172232.72/22818.13	% SZS status GaveUp for HL409630+4.p
172232.72/22818.13	eprover: CPU time limit exceeded, terminating
172232.72/22818.13	% SZS status Ended for HL409630+4.p
172236.03/22818.63	% SZS status Started for HL409630+5.p
172236.03/22818.63	% SZS status GaveUp for HL409630+5.p
172236.03/22818.63	eprover: CPU time limit exceeded, terminating
172236.03/22818.63	% SZS status Ended for HL409630+5.p
172238.09/22818.86	% SZS status Started for HL409631+4.p
172238.09/22818.86	% SZS status GaveUp for HL409631+4.p
172238.09/22818.86	eprover: CPU time limit exceeded, terminating
172238.09/22818.86	% SZS status Ended for HL409631+4.p
172240.00/22819.08	% SZS status Started for HL409631+5.p
172240.00/22819.08	% SZS status GaveUp for HL409631+5.p
172240.00/22819.08	eprover: CPU time limit exceeded, terminating
172240.00/22819.08	% SZS status Ended for HL409631+5.p
172244.34/22819.57	% SZS status Started for HL409634+4.p
172244.34/22819.57	% SZS status GaveUp for HL409634+4.p
172244.34/22819.57	eprover: CPU time limit exceeded, terminating
172244.34/22819.57	% SZS status Ended for HL409634+4.p
172246.97/22819.88	% SZS status Started for HL409634+5.p
172246.97/22819.88	% SZS status GaveUp for HL409634+5.p
172246.97/22819.88	eprover: CPU time limit exceeded, terminating
172246.97/22819.88	% SZS status Ended for HL409634+5.p
172247.33/22819.93	% SZS status Started for HL409635+4.p
172247.33/22819.93	% SZS status GaveUp for HL409635+4.p
172247.33/22819.93	eprover: CPU time limit exceeded, terminating
172247.33/22819.93	% SZS status Ended for HL409635+4.p
172252.09/22820.59	% SZS status Started for HL409635+5.p
172252.09/22820.59	% SZS status GaveUp for HL409635+5.p
172252.09/22820.59	eprover: CPU time limit exceeded, terminating
172252.09/22820.59	% SZS status Ended for HL409635+5.p
172257.06/22821.16	% SZS status Started for HL409636+4.p
172257.06/22821.16	% SZS status GaveUp for HL409636+4.p
172257.06/22821.16	eprover: CPU time limit exceeded, terminating
172257.06/22821.16	% SZS status Ended for HL409636+4.p
172260.98/22821.67	% SZS status Started for HL409636+5.p
172260.98/22821.67	% SZS status GaveUp for HL409636+5.p
172260.98/22821.67	eprover: CPU time limit exceeded, terminating
172260.98/22821.67	% SZS status Ended for HL409636+5.p
172262.56/22821.89	% SZS status Started for HL409637+4.p
172262.56/22821.89	% SZS status GaveUp for HL409637+4.p
172262.56/22821.89	eprover: CPU time limit exceeded, terminating
172262.56/22821.89	% SZS status Ended for HL409637+4.p
172264.64/22822.13	% SZS status Started for HL409637+5.p
172264.64/22822.13	% SZS status GaveUp for HL409637+5.p
172264.64/22822.13	eprover: CPU time limit exceeded, terminating
172264.64/22822.13	% SZS status Ended for HL409637+5.p
172269.95/22822.79	% SZS status Started for HL409638+4.p
172269.95/22822.79	% SZS status GaveUp for HL409638+4.p
172269.95/22822.79	eprover: CPU time limit exceeded, terminating
172269.95/22822.79	% SZS status Ended for HL409638+4.p
172270.62/22822.91	% SZS status Started for HL409638+5.p
172270.62/22822.91	% SZS status GaveUp for HL409638+5.p
172270.62/22822.91	eprover: CPU time limit exceeded, terminating
172270.62/22822.91	% SZS status Ended for HL409638+5.p
172271.20/22822.97	% SZS status Started for HL409639+4.p
172271.20/22822.97	% SZS status GaveUp for HL409639+4.p
172271.20/22822.97	eprover: CPU time limit exceeded, terminating
172271.20/22822.97	% SZS status Ended for HL409639+4.p
172276.69/22823.64	% SZS status Started for HL409639+5.p
172276.69/22823.64	% SZS status GaveUp for HL409639+5.p
172276.69/22823.64	eprover: CPU time limit exceeded, terminating
172276.69/22823.64	% SZS status Ended for HL409639+5.p
172281.03/22824.19	% SZS status Started for HL409640+4.p
172281.03/22824.19	% SZS status GaveUp for HL409640+4.p
172281.03/22824.19	eprover: CPU time limit exceeded, terminating
172281.03/22824.19	% SZS status Ended for HL409640+4.p
172284.73/22824.70	% SZS status Started for HL409640+5.p
172284.73/22824.70	% SZS status GaveUp for HL409640+5.p
172284.73/22824.70	eprover: CPU time limit exceeded, terminating
172284.73/22824.70	% SZS status Ended for HL409640+5.p
172286.88/22824.92	% SZS status Started for HL409641+4.p
172286.88/22824.92	% SZS status GaveUp for HL409641+4.p
172286.88/22824.92	eprover: CPU time limit exceeded, terminating
172286.88/22824.92	% SZS status Ended for HL409641+4.p
172288.45/22825.18	% SZS status Started for HL409641+5.p
172288.45/22825.18	% SZS status GaveUp for HL409641+5.p
172288.45/22825.18	eprover: CPU time limit exceeded, terminating
172288.45/22825.18	% SZS status Ended for HL409641+5.p
172294.64/22825.93	% SZS status Started for HL409642+4.p
172294.64/22825.93	% SZS status GaveUp for HL409642+4.p
172294.64/22825.93	eprover: CPU time limit exceeded, terminating
172294.64/22825.93	% SZS status Ended for HL409642+4.p
172295.33/22825.98	% SZS status Started for HL409642+5.p
172295.33/22825.98	% SZS status GaveUp for HL409642+5.p
172295.33/22825.98	eprover: CPU time limit exceeded, terminating
172295.33/22825.98	% SZS status Ended for HL409642+5.p
172295.33/22826.00	% SZS status Started for HL409643+4.p
172295.33/22826.00	% SZS status GaveUp for HL409643+4.p
172295.33/22826.00	eprover: CPU time limit exceeded, terminating
172295.33/22826.00	% SZS status Ended for HL409643+4.p
172300.56/22826.67	% SZS status Started for HL409643+5.p
172300.56/22826.67	% SZS status GaveUp for HL409643+5.p
172300.56/22826.67	eprover: CPU time limit exceeded, terminating
172300.56/22826.67	% SZS status Ended for HL409643+5.p
172304.84/22827.22	% SZS status Started for HL409644+4.p
172304.84/22827.22	% SZS status GaveUp for HL409644+4.p
172304.84/22827.22	eprover: CPU time limit exceeded, terminating
172304.84/22827.22	% SZS status Ended for HL409644+4.p
172308.72/22827.73	% SZS status Started for HL409644+5.p
172308.72/22827.73	% SZS status GaveUp for HL409644+5.p
172308.72/22827.73	eprover: CPU time limit exceeded, terminating
172308.72/22827.73	% SZS status Ended for HL409644+5.p
172310.81/22827.95	% SZS status Started for HL409645+4.p
172310.81/22827.95	% SZS status GaveUp for HL409645+4.p
172310.81/22827.95	eprover: CPU time limit exceeded, terminating
172310.81/22827.95	% SZS status Ended for HL409645+4.p
172313.52/22828.32	% SZS status Started for HL409645+5.p
172313.52/22828.32	% SZS status GaveUp for HL409645+5.p
172313.52/22828.32	eprover: CPU time limit exceeded, terminating
172313.52/22828.32	% SZS status Ended for HL409645+5.p
172319.03/22828.97	% SZS status Started for HL409646+4.p
172319.03/22828.97	% SZS status GaveUp for HL409646+4.p
172319.03/22828.97	eprover: CPU time limit exceeded, terminating
172319.03/22828.97	% SZS status Ended for HL409646+4.p
172319.50/22829.04	% SZS status Started for HL409647+4.p
172319.50/22829.04	% SZS status GaveUp for HL409647+4.p
172319.50/22829.04	eprover: CPU time limit exceeded, terminating
172319.50/22829.04	% SZS status Ended for HL409647+4.p
172324.53/22829.70	% SZS status Started for HL409647+5.p
172324.53/22829.70	% SZS status GaveUp for HL409647+5.p
172324.53/22829.70	eprover: CPU time limit exceeded, terminating
172324.53/22829.70	% SZS status Ended for HL409647+5.p
172328.88/22830.26	% SZS status Started for HL409648+4.p
172328.88/22830.26	% SZS status GaveUp for HL409648+4.p
172328.88/22830.26	eprover: CPU time limit exceeded, terminating
172328.88/22830.26	% SZS status Ended for HL409648+4.p
172335.66/22831.08	% SZS status Started for HL409649+4.p
172335.66/22831.08	% SZS status GaveUp for HL409649+4.p
172335.66/22831.08	eprover: CPU time limit exceeded, terminating
172335.66/22831.08	% SZS status Ended for HL409649+4.p
172342.27/22832.02	% SZS status Started for HL409650+4.p
172342.27/22832.02	% SZS status GaveUp for HL409650+4.p
172342.27/22832.02	eprover: CPU time limit exceeded, terminating
172342.27/22832.02	% SZS status Ended for HL409650+4.p
172348.42/22832.73	% SZS status Started for HL409651+4.p
172348.42/22832.73	% SZS status GaveUp for HL409651+4.p
172348.42/22832.73	eprover: CPU time limit exceeded, terminating
172348.42/22832.73	% SZS status Ended for HL409651+4.p
172359.47/22834.11	% SZS status Started for HL409652+4.p
172359.47/22834.11	% SZS status GaveUp for HL409652+4.p
172359.47/22834.11	eprover: CPU time limit exceeded, terminating
172359.47/22834.11	% SZS status Ended for HL409652+4.p
172372.50/22835.76	% SZS status Started for HL409653+4.p
172372.50/22835.76	% SZS status GaveUp for HL409653+4.p
172372.50/22835.76	eprover: CPU time limit exceeded, terminating
172372.50/22835.76	% SZS status Ended for HL409653+4.p
172383.16/22837.04	% SZS status Started for HL409646+5.p
172383.16/22837.04	% SZS status GaveUp for HL409646+5.p
172383.16/22837.04	eprover: CPU time limit exceeded, terminating
172383.16/22837.04	% SZS status Ended for HL409646+5.p
172397.08/22838.80	% SZS status Started for HL409648+5.p
172397.08/22838.80	% SZS status GaveUp for HL409648+5.p
172397.08/22838.80	eprover: CPU time limit exceeded, terminating
172397.08/22838.80	% SZS status Ended for HL409648+5.p
172397.08/22838.80	% SZS status Started for HL409654+4.p
172397.08/22838.80	% SZS status GaveUp for HL409654+4.p
172397.08/22838.80	eprover: CPU time limit exceeded, terminating
172397.08/22838.80	% SZS status Ended for HL409654+4.p
172398.95/22839.13	% SZS status Started for HL409649+5.p
172398.95/22839.13	% SZS status GaveUp for HL409649+5.p
172398.95/22839.13	eprover: CPU time limit exceeded, terminating
172398.95/22839.13	% SZS status Ended for HL409649+5.p
172402.86/22839.66	% SZS status Started for HL409650+5.p
172402.86/22839.66	% SZS status GaveUp for HL409650+5.p
172402.86/22839.66	eprover: CPU time limit exceeded, terminating
172402.86/22839.66	% SZS status Ended for HL409650+5.p
172411.19/22840.60	% SZS status Started for HL409651+5.p
172411.19/22840.60	% SZS status GaveUp for HL409651+5.p
172411.19/22840.60	eprover: CPU time limit exceeded, terminating
172411.19/22840.60	% SZS status Ended for HL409651+5.p
172420.83/22841.84	% SZS status Started for HL409655+4.p
172420.83/22841.84	% SZS status GaveUp for HL409655+4.p
172420.83/22841.84	eprover: CPU time limit exceeded, terminating
172420.83/22841.84	% SZS status Ended for HL409655+4.p
172423.84/22842.21	% SZS status Started for HL409657+4.p
172423.84/22842.21	% SZS status GaveUp for HL409657+4.p
172423.84/22842.21	eprover: CPU time limit exceeded, terminating
172423.84/22842.21	% SZS status Ended for HL409657+4.p
172424.92/22842.35	% SZS status Started for HL409652+5.p
172424.92/22842.35	% SZS status GaveUp for HL409652+5.p
172424.92/22842.35	eprover: CPU time limit exceeded, terminating
172424.92/22842.35	% SZS status Ended for HL409652+5.p
172434.27/22843.63	% SZS status Started for HL409659+4.p
172434.27/22843.63	% SZS status GaveUp for HL409659+4.p
172434.27/22843.63	eprover: CPU time limit exceeded, terminating
172434.27/22843.63	% SZS status Ended for HL409659+4.p
172441.47/22844.38	% SZS status Started for HL409653+5.p
172441.47/22844.38	% SZS status GaveUp for HL409653+5.p
172441.47/22844.38	eprover: CPU time limit exceeded, terminating
172441.47/22844.38	% SZS status Ended for HL409653+5.p
172447.58/22845.25	% SZS status Started for HL409660+4.p
172447.58/22845.25	% SZS status GaveUp for HL409660+4.p
172447.58/22845.25	eprover: CPU time limit exceeded, terminating
172447.58/22845.25	% SZS status Ended for HL409660+4.p
172461.14/22846.71	% SZS status Started for HL409661+4.p
172461.14/22846.71	% SZS status GaveUp for HL409661+4.p
172461.14/22846.71	eprover: CPU time limit exceeded, terminating
172461.14/22846.71	% SZS status Ended for HL409661+4.p
172466.78/22847.42	% SZS status Started for HL409654+5.p
172466.78/22847.42	% SZS status GaveUp for HL409654+5.p
172466.78/22847.42	eprover: CPU time limit exceeded, terminating
172466.78/22847.42	% SZS status Ended for HL409654+5.p
172473.97/22848.30	% SZS status Started for HL409662+4.p
172473.97/22848.30	% SZS status GaveUp for HL409662+4.p
172473.97/22848.30	eprover: CPU time limit exceeded, terminating
172473.97/22848.30	% SZS status Ended for HL409662+4.p
172479.77/22849.20	% SZS status Started for HL409655+5.p
172479.77/22849.20	% SZS status GaveUp for HL409655+5.p
172479.77/22849.20	eprover: CPU time limit exceeded, terminating
172479.77/22849.20	% SZS status Ended for HL409655+5.p
172487.09/22849.92	% SZS status Started for HL409657+5.p
172487.09/22849.92	% SZS status GaveUp for HL409657+5.p
172487.09/22849.92	eprover: CPU time limit exceeded, terminating
172487.09/22849.92	% SZS status Ended for HL409657+5.p
172491.56/22850.46	% SZS status Started for HL409663+4.p
172491.56/22850.46	% SZS status GaveUp for HL409663+4.p
172491.56/22850.46	eprover: CPU time limit exceeded, terminating
172491.56/22850.46	% SZS status Ended for HL409663+4.p
172504.86/22852.14	% SZS status Started for HL409659+5.p
172504.86/22852.14	% SZS status GaveUp for HL409659+5.p
172504.86/22852.14	eprover: CPU time limit exceeded, terminating
172504.86/22852.14	% SZS status Ended for HL409659+5.p
172505.31/22852.25	% SZS status Started for HL409664+4.p
172505.31/22852.25	% SZS status GaveUp for HL409664+4.p
172505.31/22852.25	eprover: CPU time limit exceeded, terminating
172505.31/22852.25	% SZS status Ended for HL409664+4.p
172507.84/22852.71	% SZS status Started for HL409660+5.p
172507.84/22852.71	% SZS status GaveUp for HL409660+5.p
172507.84/22852.71	eprover: CPU time limit exceeded, terminating
172507.84/22852.71	% SZS status Ended for HL409660+5.p
172515.41/22853.49	% SZS status Started for HL409665+4.p
172515.41/22853.49	% SZS status GaveUp for HL409665+4.p
172515.41/22853.49	eprover: CPU time limit exceeded, terminating
172515.41/22853.49	% SZS status Ended for HL409665+4.p
172525.59/22854.74	% SZS status Started for HL409661+5.p
172525.59/22854.74	% SZS status GaveUp for HL409661+5.p
172525.59/22854.74	eprover: CPU time limit exceeded, terminating
172525.59/22854.74	% SZS status Ended for HL409661+5.p
172530.58/22855.40	% SZS status Started for HL409666+4.p
172530.58/22855.40	% SZS status GaveUp for HL409666+4.p
172530.58/22855.40	eprover: CPU time limit exceeded, terminating
172530.58/22855.40	% SZS status Ended for HL409666+4.p
172539.16/22856.51	% SZS status Started for HL409667+4.p
172539.16/22856.51	% SZS status GaveUp for HL409667+4.p
172539.16/22856.51	eprover: CPU time limit exceeded, terminating
172539.16/22856.51	% SZS status Ended for HL409667+4.p
172543.50/22857.01	% SZS status Started for HL409662+5.p
172543.50/22857.01	% SZS status GaveUp for HL409662+5.p
172543.50/22857.01	eprover: CPU time limit exceeded, terminating
172543.50/22857.01	% SZS status Ended for HL409662+5.p
172554.84/22858.42	% SZS status Started for HL409668+4.p
172554.84/22858.42	% SZS status GaveUp for HL409668+4.p
172554.84/22858.42	eprover: CPU time limit exceeded, terminating
172554.84/22858.42	% SZS status Ended for HL409668+4.p
172556.23/22858.62	% SZS status Started for HL409663+5.p
172556.23/22858.62	% SZS status GaveUp for HL409663+5.p
172556.23/22858.62	eprover: CPU time limit exceeded, terminating
172556.23/22858.62	% SZS status Ended for HL409663+5.p
172567.23/22860.04	% SZS status Started for HL409669+4.p
172567.23/22860.04	% SZS status GaveUp for HL409669+4.p
172567.23/22860.04	eprover: CPU time limit exceeded, terminating
172567.23/22860.04	% SZS status Ended for HL409669+4.p
172570.42/22860.41	% SZS status Started for HL409664+5.p
172570.42/22860.41	% SZS status GaveUp for HL409664+5.p
172570.42/22860.41	eprover: CPU time limit exceeded, terminating
172570.42/22860.41	% SZS status Ended for HL409664+5.p
172580.53/22861.68	% SZS status Started for HL409670+4.p
172580.53/22861.68	% SZS status GaveUp for HL409670+4.p
172580.53/22861.68	eprover: CPU time limit exceeded, terminating
172580.53/22861.68	% SZS status Ended for HL409670+4.p
172587.77/22862.59	% SZS status Started for HL409665+5.p
172587.77/22862.59	% SZS status GaveUp for HL409665+5.p
172587.77/22862.59	eprover: CPU time limit exceeded, terminating
172587.77/22862.59	% SZS status Ended for HL409665+5.p
172590.20/22863.05	% SZS status Started for HL409666+5.p
172590.20/22863.05	% SZS status GaveUp for HL409666+5.p
172590.20/22863.05	eprover: CPU time limit exceeded, terminating
172590.20/22863.05	% SZS status Ended for HL409666+5.p
172594.28/22863.46	% SZS status Started for HL409671+4.p
172594.28/22863.46	% SZS status GaveUp for HL409671+4.p
172594.28/22863.46	eprover: CPU time limit exceeded, terminating
172594.28/22863.46	% SZS status Ended for HL409671+4.p
172612.02/22865.68	% SZS status Started for HL409673+4.p
172612.02/22865.68	% SZS status GaveUp for HL409673+4.p
172612.02/22865.68	eprover: CPU time limit exceeded, terminating
172612.02/22865.68	% SZS status Ended for HL409673+4.p
172613.12/22865.94	% SZS status Started for HL409667+5.p
172613.12/22865.94	% SZS status GaveUp for HL409667+5.p
172613.12/22865.94	eprover: CPU time limit exceeded, terminating
172613.12/22865.94	% SZS status Ended for HL409667+5.p
172619.31/22866.58	% SZS status Started for HL409674+4.p
172619.31/22866.58	% SZS status GaveUp for HL409674+4.p
172619.31/22866.58	eprover: CPU time limit exceeded, terminating
172619.31/22866.58	% SZS status Ended for HL409674+4.p
172620.77/22866.83	% SZS status Started for HL409668+5.p
172620.77/22866.83	% SZS status GaveUp for HL409668+5.p
172620.77/22866.83	eprover: CPU time limit exceeded, terminating
172620.77/22866.83	% SZS status Ended for HL409668+5.p
172635.16/22868.68	% SZS status Started for HL409669+5.p
172635.16/22868.68	% SZS status GaveUp for HL409669+5.p
172635.16/22868.68	eprover: CPU time limit exceeded, terminating
172635.16/22868.68	% SZS status Ended for HL409669+5.p
172638.30/22869.00	% SZS status Started for HL409675+4.p
172638.30/22869.00	% SZS status GaveUp for HL409675+4.p
172638.30/22869.00	eprover: CPU time limit exceeded, terminating
172638.30/22869.00	% SZS status Ended for HL409675+4.p
172643.97/22869.86	% SZS status Started for HL409676+4.p
172643.97/22869.86	% SZS status GaveUp for HL409676+4.p
172643.97/22869.86	eprover: CPU time limit exceeded, terminating
172643.97/22869.86	% SZS status Ended for HL409676+4.p
172650.12/22870.49	% SZS status Started for HL409670+5.p
172650.12/22870.49	% SZS status GaveUp for HL409670+5.p
172650.12/22870.49	eprover: CPU time limit exceeded, terminating
172650.12/22870.49	% SZS status Ended for HL409670+5.p
172662.36/22872.03	% SZS status Started for HL409678+4.p
172662.36/22872.03	% SZS status GaveUp for HL409678+4.p
172662.36/22872.03	eprover: CPU time limit exceeded, terminating
172662.36/22872.03	% SZS status Ended for HL409678+4.p
172665.19/22872.42	% SZS status Started for HL409671+5.p
172665.19/22872.42	% SZS status GaveUp for HL409671+5.p
172665.19/22872.42	eprover: CPU time limit exceeded, terminating
172665.19/22872.42	% SZS status Ended for HL409671+5.p
172674.69/22873.53	% SZS status Started for HL409679+4.p
172674.69/22873.53	% SZS status GaveUp for HL409679+4.p
172674.69/22873.53	eprover: CPU time limit exceeded, terminating
172674.69/22873.53	% SZS status Ended for HL409679+4.p
172674.69/22873.58	% SZS status Started for HL409673+5.p
172674.69/22873.58	% SZS status GaveUp for HL409673+5.p
172674.69/22873.58	eprover: CPU time limit exceeded, terminating
172674.69/22873.58	% SZS status Ended for HL409673+5.p
172690.61/22875.57	% SZS status Started for HL409680+4.p
172690.61/22875.57	% SZS status GaveUp for HL409680+4.p
172690.61/22875.57	eprover: CPU time limit exceeded, terminating
172690.61/22875.57	% SZS status Ended for HL409680+4.p
172695.70/22876.20	% SZS status Started for HL409674+5.p
172695.70/22876.20	% SZS status GaveUp for HL409674+5.p
172695.70/22876.20	eprover: CPU time limit exceeded, terminating
172695.70/22876.20	% SZS status Ended for HL409674+5.p
172697.83/22876.62	% SZS status Started for HL409681+4.p
172697.83/22876.62	% SZS status GaveUp for HL409681+4.p
172697.83/22876.62	eprover: CPU time limit exceeded, terminating
172697.83/22876.62	% SZS status Ended for HL409681+4.p
172700.42/22876.84	% SZS status Started for HL409675+5.p
172700.42/22876.84	% SZS status GaveUp for HL409675+5.p
172700.42/22876.84	eprover: CPU time limit exceeded, terminating
172700.42/22876.84	% SZS status Ended for HL409675+5.p
172718.14/22879.10	% SZS status Started for HL409676+5.p
172718.14/22879.10	% SZS status GaveUp for HL409676+5.p
172718.14/22879.10	eprover: CPU time limit exceeded, terminating
172718.14/22879.10	% SZS status Ended for HL409676+5.p
172719.45/22879.26	% SZS status Started for HL409682+4.p
172719.45/22879.26	% SZS status GaveUp for HL409682+4.p
172719.45/22879.26	eprover: CPU time limit exceeded, terminating
172719.45/22879.26	% SZS status Ended for HL409682+4.p
172724.66/22879.90	% SZS status Started for HL409683+4.p
172724.66/22879.90	% SZS status GaveUp for HL409683+4.p
172724.66/22879.90	eprover: CPU time limit exceeded, terminating
172724.66/22879.90	% SZS status Ended for HL409683+4.p
172728.12/22880.32	% SZS status Started for HL409678+5.p
172728.12/22880.32	% SZS status GaveUp for HL409678+5.p
172728.12/22880.32	eprover: CPU time limit exceeded, terminating
172728.12/22880.32	% SZS status Ended for HL409678+5.p
172744.08/22882.31	% SZS status Started for HL409684+4.p
172744.08/22882.31	% SZS status GaveUp for HL409684+4.p
172744.08/22882.31	eprover: CPU time limit exceeded, terminating
172744.08/22882.31	% SZS status Ended for HL409684+4.p
172748.95/22882.93	% SZS status Started for HL409679+5.p
172748.95/22882.93	% SZS status GaveUp for HL409679+5.p
172748.95/22882.93	eprover: CPU time limit exceeded, terminating
172748.95/22882.93	% SZS status Ended for HL409679+5.p
172750.95/22883.34	% SZS status Started for HL409685+4.p
172750.95/22883.34	% SZS status GaveUp for HL409685+4.p
172750.95/22883.34	eprover: CPU time limit exceeded, terminating
172750.95/22883.34	% SZS status Ended for HL409685+4.p
172756.25/22883.92	% SZS status Started for HL409680+5.p
172756.25/22883.92	% SZS status GaveUp for HL409680+5.p
172756.25/22883.92	eprover: CPU time limit exceeded, terminating
172756.25/22883.92	% SZS status Ended for HL409680+5.p
172773.17/22885.95	% SZS status Started for HL409686+4.p
172773.17/22885.95	% SZS status GaveUp for HL409686+4.p
172773.17/22885.95	eprover: CPU time limit exceeded, terminating
172773.17/22885.95	% SZS status Ended for HL409686+4.p
172776.34/22886.37	% SZS status Started for HL409681+5.p
172776.34/22886.37	% SZS status GaveUp for HL409681+5.p
172776.34/22886.37	eprover: CPU time limit exceeded, terminating
172776.34/22886.37	% SZS status Ended for HL409681+5.p
172780.98/22886.96	% SZS status Started for HL409687+4.p
172780.98/22886.96	% SZS status GaveUp for HL409687+4.p
172780.98/22886.96	eprover: CPU time limit exceeded, terminating
172780.98/22886.96	% SZS status Ended for HL409687+4.p
172782.11/22887.14	% SZS status Started for HL409682+5.p
172782.11/22887.14	% SZS status GaveUp for HL409682+5.p
172782.11/22887.14	eprover: CPU time limit exceeded, terminating
172782.11/22887.14	% SZS status Ended for HL409682+5.p
172799.92/22889.41	% SZS status Started for HL409683+5.p
172799.92/22889.41	% SZS status GaveUp for HL409683+5.p
172799.92/22889.41	eprover: CPU time limit exceeded, terminating
172799.92/22889.41	% SZS status Ended for HL409683+5.p
172800.83/22889.51	% SZS status Started for HL409688+4.p
172800.83/22889.51	% SZS status GaveUp for HL409688+4.p
172800.83/22889.51	eprover: CPU time limit exceeded, terminating
172800.83/22889.51	% SZS status Ended for HL409688+4.p
172806.39/22890.16	% SZS status Started for HL409689+4.p
172806.39/22890.16	% SZS status GaveUp for HL409689+4.p
172806.39/22890.16	eprover: CPU time limit exceeded, terminating
172806.39/22890.16	% SZS status Ended for HL409689+4.p
172806.39/22890.18	% SZS status Started for HL409684+5.p
172806.39/22890.18	% SZS status GaveUp for HL409684+5.p
172806.39/22890.18	eprover: CPU time limit exceeded, terminating
172806.39/22890.18	% SZS status Ended for HL409684+5.p
172825.95/22892.67	% SZS status Started for HL409690+4.p
172825.95/22892.67	% SZS status GaveUp for HL409690+4.p
172825.95/22892.67	eprover: CPU time limit exceeded, terminating
172825.95/22892.67	% SZS status Ended for HL409690+4.p
172826.61/22892.84	% SZS status Started for HL409685+5.p
172826.61/22892.84	% SZS status GaveUp for HL409685+5.p
172826.61/22892.84	eprover: CPU time limit exceeded, terminating
172826.61/22892.84	% SZS status Ended for HL409685+5.p
172830.67/22893.26	% SZS status Started for HL409691+4.p
172830.67/22893.26	% SZS status GaveUp for HL409691+4.p
172830.67/22893.26	eprover: CPU time limit exceeded, terminating
172830.67/22893.26	% SZS status Ended for HL409691+4.p
172834.84/22893.80	% SZS status Started for HL409686+5.p
172834.84/22893.80	% SZS status GaveUp for HL409686+5.p
172834.84/22893.80	eprover: CPU time limit exceeded, terminating
172834.84/22893.80	% SZS status Ended for HL409686+5.p
172850.53/22895.90	% SZS status Started for HL409693+4.p
172850.53/22895.90	% SZS status GaveUp for HL409693+4.p
172850.53/22895.90	eprover: CPU time limit exceeded, terminating
172850.53/22895.90	% SZS status Ended for HL409693+4.p
172854.81/22896.32	% SZS status Started for HL409687+5.p
172854.81/22896.32	% SZS status GaveUp for HL409687+5.p
172854.81/22896.32	eprover: CPU time limit exceeded, terminating
172854.81/22896.32	% SZS status Ended for HL409687+5.p
172859.06/22896.90	% SZS status Started for HL409694+4.p
172859.06/22896.90	% SZS status GaveUp for HL409694+4.p
172859.06/22896.90	eprover: CPU time limit exceeded, terminating
172859.06/22896.90	% SZS status Ended for HL409694+4.p
172863.14/22897.38	% SZS status Started for HL409688+5.p
172863.14/22897.38	% SZS status GaveUp for HL409688+5.p
172863.14/22897.38	eprover: CPU time limit exceeded, terminating
172863.14/22897.38	% SZS status Ended for HL409688+5.p
172878.31/22899.35	% SZS status Started for HL409695+4.p
172878.31/22899.35	% SZS status GaveUp for HL409695+4.p
172878.31/22899.35	eprover: CPU time limit exceeded, terminating
172878.31/22899.35	% SZS status Ended for HL409695+4.p
172881.69/22899.71	% SZS status Started for HL409689+5.p
172881.69/22899.71	% SZS status GaveUp for HL409689+5.p
172881.69/22899.71	eprover: CPU time limit exceeded, terminating
172881.69/22899.71	% SZS status Ended for HL409689+5.p
172887.17/22900.48	% SZS status Started for HL409696+4.p
172887.17/22900.48	% SZS status GaveUp for HL409696+4.p
172887.17/22900.48	eprover: CPU time limit exceeded, terminating
172887.17/22900.48	% SZS status Ended for HL409696+4.p
172888.89/22900.59	% SZS status Started for HL409690+5.p
172888.89/22900.59	% SZS status GaveUp for HL409690+5.p
172888.89/22900.59	eprover: CPU time limit exceeded, terminating
172888.89/22900.59	% SZS status Ended for HL409690+5.p
172905.94/22902.77	% SZS status Started for HL409697+4.p
172905.94/22902.77	% SZS status GaveUp for HL409697+4.p
172905.94/22902.77	eprover: CPU time limit exceeded, terminating
172905.94/22902.77	% SZS status Ended for HL409697+4.p
172907.39/22902.96	% SZS status Started for HL409691+5.p
172907.39/22902.96	% SZS status GaveUp for HL409691+5.p
172907.39/22902.96	eprover: CPU time limit exceeded, terminating
172907.39/22902.96	% SZS status Ended for HL409691+5.p
172912.59/22903.63	% SZS status Started for HL409698+4.p
172912.59/22903.63	% SZS status GaveUp for HL409698+4.p
172912.59/22903.63	eprover: CPU time limit exceeded, terminating
172912.59/22903.63	% SZS status Ended for HL409698+4.p
172913.83/22903.80	% SZS status Started for HL409693+5.p
172913.83/22903.80	% SZS status GaveUp for HL409693+5.p
172913.83/22903.80	eprover: CPU time limit exceeded, terminating
172913.83/22903.80	% SZS status Ended for HL409693+5.p
172931.36/22905.99	% SZS status Started for HL409699+4.p
172931.36/22905.99	% SZS status GaveUp for HL409699+4.p
172931.36/22905.99	eprover: CPU time limit exceeded, terminating
172931.36/22905.99	% SZS status Ended for HL409699+4.p
172932.31/22906.17	% SZS status Started for HL409694+5.p
172932.31/22906.17	% SZS status GaveUp for HL409694+5.p
172932.31/22906.17	eprover: CPU time limit exceeded, terminating
172932.31/22906.17	% SZS status Ended for HL409694+5.p
172937.98/22906.83	% SZS status Started for HL409700+4.p
172937.98/22906.83	% SZS status GaveUp for HL409700+4.p
172937.98/22906.83	eprover: CPU time limit exceeded, terminating
172937.98/22906.83	% SZS status Ended for HL409700+4.p
172941.14/22907.18	% SZS status Started for HL409695+5.p
172941.14/22907.18	% SZS status GaveUp for HL409695+5.p
172941.14/22907.18	eprover: CPU time limit exceeded, terminating
172941.14/22907.18	% SZS status Ended for HL409695+5.p
172956.81/22909.26	% SZS status Started for HL409701+4.p
172956.81/22909.26	% SZS status GaveUp for HL409701+4.p
172956.81/22909.26	eprover: CPU time limit exceeded, terminating
172956.81/22909.26	% SZS status Ended for HL409701+4.p
172961.12/22909.71	% SZS status Started for HL409696+5.p
172961.12/22909.71	% SZS status GaveUp for HL409696+5.p
172961.12/22909.71	eprover: CPU time limit exceeded, terminating
172961.12/22909.71	% SZS status Ended for HL409696+5.p
172963.33/22910.23	% SZS status Started for HL409702+4.p
172963.33/22910.23	% SZS status GaveUp for HL409702+4.p
172963.33/22910.23	eprover: CPU time limit exceeded, terminating
172963.33/22910.23	% SZS status Ended for HL409702+4.p
172970.47/22910.90	% SZS status Started for HL409697+5.p
172970.47/22910.90	% SZS status GaveUp for HL409697+5.p
172970.47/22910.90	eprover: CPU time limit exceeded, terminating
172970.47/22910.90	% SZS status Ended for HL409697+5.p
172984.94/22912.73	% SZS status Started for HL409703+4.p
172984.94/22912.73	% SZS status GaveUp for HL409703+4.p
172984.94/22912.73	eprover: CPU time limit exceeded, terminating
172984.94/22912.73	% SZS status Ended for HL409703+4.p
172988.62/22913.18	% SZS status Started for HL409698+5.p
172988.62/22913.18	% SZS status GaveUp for HL409698+5.p
172988.62/22913.18	eprover: CPU time limit exceeded, terminating
172988.62/22913.18	% SZS status Ended for HL409698+5.p
172995.00/22913.95	% SZS status Started for HL409704+4.p
172995.00/22913.95	% SZS status GaveUp for HL409704+4.p
172995.00/22913.95	eprover: CPU time limit exceeded, terminating
172995.00/22913.95	% SZS status Ended for HL409704+4.p
172995.36/22913.99	% SZS status Started for HL409699+5.p
172995.36/22913.99	% SZS status GaveUp for HL409699+5.p
172995.36/22913.99	eprover: CPU time limit exceeded, terminating
172995.36/22913.99	% SZS status Ended for HL409699+5.p
173012.45/22916.21	% SZS status Started for HL409705+4.p
173012.45/22916.21	% SZS status GaveUp for HL409705+4.p
173012.45/22916.21	eprover: CPU time limit exceeded, terminating
173012.45/22916.21	% SZS status Ended for HL409705+4.p
173014.89/22916.58	% SZS status Started for HL409700+5.p
173014.89/22916.58	% SZS status GaveUp for HL409700+5.p
173014.89/22916.58	eprover: CPU time limit exceeded, terminating
173014.89/22916.58	% SZS status Ended for HL409700+5.p
173018.19/22917.02	% SZS status Started for HL409706+4.p
173018.19/22917.02	% SZS status GaveUp for HL409706+4.p
173018.19/22917.02	eprover: CPU time limit exceeded, terminating
173018.19/22917.02	% SZS status Ended for HL409706+4.p
173025.25/22917.78	% SZS status Started for HL409701+5.p
173025.25/22917.78	% SZS status GaveUp for HL409701+5.p
173025.25/22917.78	eprover: CPU time limit exceeded, terminating
173025.25/22917.78	% SZS status Ended for HL409701+5.p
173039.34/22919.63	% SZS status Started for HL409708+4.p
173039.34/22919.63	% SZS status GaveUp for HL409708+4.p
173039.34/22919.63	eprover: CPU time limit exceeded, terminating
173039.34/22919.63	% SZS status Ended for HL409708+4.p
173040.11/22919.71	% SZS status Started for HL409702+5.p
173040.11/22919.71	% SZS status GaveUp for HL409702+5.p
173040.11/22919.71	eprover: CPU time limit exceeded, terminating
173040.11/22919.71	% SZS status Ended for HL409702+5.p
173049.69/22920.92	% SZS status Started for HL409709+4.p
173049.69/22920.92	% SZS status GaveUp for HL409709+4.p
173049.69/22920.92	eprover: CPU time limit exceeded, terminating
173049.69/22920.92	% SZS status Ended for HL409709+4.p
173049.69/22920.93	% SZS status Started for HL409703+5.p
173049.69/22920.93	% SZS status GaveUp for HL409703+5.p
173049.69/22920.93	eprover: CPU time limit exceeded, terminating
173049.69/22920.93	% SZS status Ended for HL409703+5.p
173064.62/22922.75	% SZS status Started for HL409711+4.p
173064.62/22922.75	% SZS status GaveUp for HL409711+4.p
173064.62/22922.75	eprover: CPU time limit exceeded, terminating
173064.62/22922.75	% SZS status Ended for HL409711+4.p
173067.86/22923.16	% SZS status Started for HL409704+5.p
173067.86/22923.16	% SZS status GaveUp for HL409704+5.p
173067.86/22923.16	eprover: CPU time limit exceeded, terminating
173067.86/22923.16	% SZS status Ended for HL409704+5.p
173074.17/22924.00	% SZS status Started for HL409712+4.p
173074.17/22924.00	% SZS status GaveUp for HL409712+4.p
173074.17/22924.00	eprover: CPU time limit exceeded, terminating
173074.17/22924.00	% SZS status Ended for HL409712+4.p
173081.58/22924.86	% SZS status Started for HL409705+5.p
173081.58/22924.86	% SZS status GaveUp for HL409705+5.p
173081.58/22924.86	eprover: CPU time limit exceeded, terminating
173081.58/22924.86	% SZS status Ended for HL409705+5.p
173092.06/22926.19	% SZS status Started for HL409713+4.p
173092.06/22926.19	% SZS status GaveUp for HL409713+4.p
173092.06/22926.19	eprover: CPU time limit exceeded, terminating
173092.06/22926.19	% SZS status Ended for HL409713+4.p
173093.88/22926.57	% SZS status Started for HL409706+5.p
173093.88/22926.57	% SZS status GaveUp for HL409706+5.p
173093.88/22926.57	eprover: CPU time limit exceeded, terminating
173093.88/22926.57	% SZS status Ended for HL409706+5.p
173100.56/22927.26	% SZS status Started for HL409708+5.p
173100.56/22927.26	% SZS status GaveUp for HL409708+5.p
173100.56/22927.26	eprover: CPU time limit exceeded, terminating
173100.56/22927.26	% SZS status Ended for HL409708+5.p
173105.77/22927.94	% SZS status Started for HL409714+4.p
173105.77/22927.94	% SZS status GaveUp for HL409714+4.p
173105.77/22927.94	eprover: CPU time limit exceeded, terminating
173105.77/22927.94	% SZS status Ended for HL409714+4.p
173118.92/22929.61	% SZS status Started for HL409715+4.p
173118.92/22929.61	% SZS status GaveUp for HL409715+4.p
173118.92/22929.61	eprover: CPU time limit exceeded, terminating
173118.92/22929.61	% SZS status Ended for HL409715+4.p
173120.80/22929.90	% SZS status Started for HL409709+5.p
173120.80/22929.90	% SZS status GaveUp for HL409709+5.p
173120.80/22929.90	eprover: CPU time limit exceeded, terminating
173120.80/22929.90	% SZS status Ended for HL409709+5.p
173130.02/22930.99	% SZS status Started for HL409717+4.p
173130.02/22930.99	% SZS status GaveUp for HL409717+4.p
173130.02/22930.99	eprover: CPU time limit exceeded, terminating
173130.02/22930.99	% SZS status Ended for HL409717+4.p
173132.70/22931.30	% SZS status Started for HL409711+5.p
173132.70/22931.30	% SZS status GaveUp for HL409711+5.p
173132.70/22931.30	eprover: CPU time limit exceeded, terminating
173132.70/22931.30	% SZS status Ended for HL409711+5.p
173145.83/22932.95	% SZS status Started for HL409719+4.p
173145.83/22932.95	% SZS status GaveUp for HL409719+4.p
173145.83/22932.95	eprover: CPU time limit exceeded, terminating
173145.83/22932.95	% SZS status Ended for HL409719+4.p
173152.27/22933.78	% SZS status Started for HL409712+5.p
173152.27/22933.78	% SZS status GaveUp for HL409712+5.p
173152.27/22933.78	eprover: CPU time limit exceeded, terminating
173152.27/22933.78	% SZS status Ended for HL409712+5.p
173156.75/22934.34	% SZS status Started for HL409720+4.p
173156.75/22934.34	% SZS status GaveUp for HL409720+4.p
173156.75/22934.34	eprover: CPU time limit exceeded, terminating
173156.75/22934.34	% SZS status Ended for HL409720+4.p
173157.53/22934.49	% SZS status Started for HL409713+5.p
173157.53/22934.49	% SZS status GaveUp for HL409713+5.p
173157.53/22934.49	eprover: CPU time limit exceeded, terminating
173157.53/22934.49	% SZS status Ended for HL409713+5.p
173175.81/22936.82	% SZS status Started for HL409721+4.p
173175.81/22936.82	% SZS status GaveUp for HL409721+4.p
173175.81/22936.82	eprover: CPU time limit exceeded, terminating
173175.81/22936.82	% SZS status Ended for HL409721+4.p
173178.59/22937.12	% SZS status Started for HL409714+5.p
173178.59/22937.12	% SZS status GaveUp for HL409714+5.p
173178.59/22937.12	eprover: CPU time limit exceeded, terminating
173178.59/22937.12	% SZS status Ended for HL409714+5.p
173182.42/22937.59	% SZS status Started for HL409715+5.p
173182.42/22937.59	% SZS status GaveUp for HL409715+5.p
173182.42/22937.59	eprover: CPU time limit exceeded, terminating
173182.42/22937.59	% SZS status Ended for HL409715+5.p
173182.42/22937.61	% SZS status Started for HL409722+4.p
173182.42/22937.61	% SZS status GaveUp for HL409722+4.p
173182.42/22937.61	eprover: CPU time limit exceeded, terminating
173182.42/22937.61	% SZS status Ended for HL409722+4.p
173202.11/22940.07	% SZS status Started for HL409717+5.p
173202.11/22940.07	% SZS status GaveUp for HL409717+5.p
173202.11/22940.07	eprover: CPU time limit exceeded, terminating
173202.11/22940.07	% SZS status Ended for HL409717+5.p
173202.70/22940.15	% SZS status Started for HL409723+4.p
173202.70/22940.15	% SZS status GaveUp for HL409723+4.p
173202.70/22940.15	eprover: CPU time limit exceeded, terminating
173202.70/22940.15	% SZS status Ended for HL409723+4.p
173206.84/22940.69	% SZS status Started for HL409724+4.p
173206.84/22940.69	% SZS status GaveUp for HL409724+4.p
173206.84/22940.69	eprover: CPU time limit exceeded, terminating
173206.84/22940.69	% SZS status Ended for HL409724+4.p
173211.33/22941.25	% SZS status Started for HL409719+5.p
173211.33/22941.25	% SZS status GaveUp for HL409719+5.p
173211.33/22941.25	eprover: CPU time limit exceeded, terminating
173211.33/22941.25	% SZS status Ended for HL409719+5.p
173226.06/22943.23	% SZS status Started for HL409725+4.p
173226.06/22943.23	% SZS status GaveUp for HL409725+4.p
173226.06/22943.23	eprover: CPU time limit exceeded, terminating
173226.06/22943.23	% SZS status Ended for HL409725+4.p
173228.98/22943.46	% SZS status Started for HL409720+5.p
173228.98/22943.46	% SZS status GaveUp for HL409720+5.p
173228.98/22943.46	eprover: CPU time limit exceeded, terminating
173228.98/22943.46	% SZS status Ended for HL409720+5.p
173235.53/22944.31	% SZS status Started for HL409726+4.p
173235.53/22944.31	% SZS status GaveUp for HL409726+4.p
173235.53/22944.31	eprover: CPU time limit exceeded, terminating
173235.53/22944.31	% SZS status Ended for HL409726+4.p
173237.98/22944.62	% SZS status Started for HL409721+5.p
173237.98/22944.62	% SZS status GaveUp for HL409721+5.p
173237.98/22944.62	eprover: CPU time limit exceeded, terminating
173237.98/22944.62	% SZS status Ended for HL409721+5.p
173252.95/22946.51	% SZS status Started for HL409727+4.p
173252.95/22946.51	% SZS status GaveUp for HL409727+4.p
173252.95/22946.51	eprover: CPU time limit exceeded, terminating
173252.95/22946.51	% SZS status Ended for HL409727+4.p
173260.05/22947.43	% SZS status Started for HL409722+5.p
173260.05/22947.43	% SZS status GaveUp for HL409722+5.p
173260.05/22947.43	eprover: CPU time limit exceeded, terminating
173260.05/22947.43	% SZS status Ended for HL409722+5.p
173262.00/22947.66	% SZS status Started for HL409729+4.p
173262.00/22947.66	% SZS status GaveUp for HL409729+4.p
173262.00/22947.66	eprover: CPU time limit exceeded, terminating
173262.00/22947.66	% SZS status Ended for HL409729+4.p
173264.17/22947.90	% SZS status Started for HL409723+5.p
173264.17/22947.90	% SZS status GaveUp for HL409723+5.p
173264.17/22947.90	eprover: CPU time limit exceeded, terminating
173264.17/22947.90	% SZS status Ended for HL409723+5.p
173283.38/22950.34	% SZS status Started for HL409724+5.p
173283.38/22950.34	% SZS status GaveUp for HL409724+5.p
173283.38/22950.34	eprover: CPU time limit exceeded, terminating
173283.38/22950.34	% SZS status Ended for HL409724+5.p
173284.09/22950.45	% SZS status Started for HL409730+4.p
173284.09/22950.45	% SZS status GaveUp for HL409730+4.p
173284.09/22950.45	eprover: CPU time limit exceeded, terminating
173284.09/22950.45	% SZS status Ended for HL409730+4.p
173287.89/22950.92	% SZS status Started for HL409732+4.p
173287.89/22950.92	% SZS status GaveUp for HL409732+4.p
173287.89/22950.92	eprover: CPU time limit exceeded, terminating
173287.89/22950.92	% SZS status Ended for HL409732+4.p
173288.58/22951.13	% SZS status Started for HL409725+5.p
173288.58/22951.13	% SZS status GaveUp for HL409725+5.p
173288.58/22951.13	eprover: CPU time limit exceeded, terminating
173288.58/22951.13	% SZS status Ended for HL409725+5.p
173308.88/22953.54	% SZS status Started for HL409733+4.p
173308.88/22953.54	% SZS status GaveUp for HL409733+4.p
173308.88/22953.54	eprover: CPU time limit exceeded, terminating
173308.88/22953.54	% SZS status Ended for HL409733+4.p
173310.41/22953.82	% SZS status Started for HL409726+5.p
173310.41/22953.82	% SZS status GaveUp for HL409726+5.p
173310.41/22953.82	eprover: CPU time limit exceeded, terminating
173310.41/22953.82	% SZS status Ended for HL409726+5.p
173313.58/22954.16	% SZS status Started for HL409734+4.p
173313.58/22954.16	% SZS status GaveUp for HL409734+4.p
173313.58/22954.16	eprover: CPU time limit exceeded, terminating
173313.58/22954.16	% SZS status Ended for HL409734+4.p
173317.31/22954.58	% SZS status Started for HL409727+5.p
173317.31/22954.58	% SZS status GaveUp for HL409727+5.p
173317.31/22954.58	eprover: CPU time limit exceeded, terminating
173317.31/22954.58	% SZS status Ended for HL409727+5.p
173334.39/22956.80	% SZS status Started for HL409729+5.p
173334.39/22956.80	% SZS status GaveUp for HL409729+5.p
173334.39/22956.80	eprover: CPU time limit exceeded, terminating
173334.39/22956.80	% SZS status Ended for HL409729+5.p
173335.14/22956.86	% SZS status Started for HL409735+4.p
173335.14/22956.86	% SZS status GaveUp for HL409735+4.p
173335.14/22956.86	eprover: CPU time limit exceeded, terminating
173335.14/22956.86	% SZS status Ended for HL409735+4.p
173341.03/22957.62	% SZS status Started for HL409736+4.p
173341.03/22957.62	% SZS status GaveUp for HL409736+4.p
173341.03/22957.62	eprover: CPU time limit exceeded, terminating
173341.03/22957.62	% SZS status Ended for HL409736+4.p
173344.58/22958.04	% SZS status Started for HL409730+5.p
173344.58/22958.04	% SZS status GaveUp for HL409730+5.p
173344.58/22958.04	eprover: CPU time limit exceeded, terminating
173344.58/22958.04	% SZS status Ended for HL409730+5.p
173359.23/22959.94	% SZS status Started for HL409737+4.p
173359.23/22959.94	% SZS status GaveUp for HL409737+4.p
173359.23/22959.94	eprover: CPU time limit exceeded, terminating
173359.23/22959.94	% SZS status Ended for HL409737+4.p
173365.03/22960.65	% SZS status Started for HL409732+5.p
173365.03/22960.65	% SZS status GaveUp for HL409732+5.p
173365.03/22960.65	eprover: CPU time limit exceeded, terminating
173365.03/22960.65	% SZS status Ended for HL409732+5.p
173368.81/22961.11	% SZS status Started for HL409738+4.p
173368.81/22961.11	% SZS status GaveUp for HL409738+4.p
173368.81/22961.11	eprover: CPU time limit exceeded, terminating
173368.81/22961.11	% SZS status Ended for HL409738+4.p
173374.62/22961.96	% SZS status Started for HL409733+5.p
173374.62/22961.96	% SZS status GaveUp for HL409733+5.p
173374.62/22961.96	eprover: CPU time limit exceeded, terminating
173374.62/22961.96	% SZS status Ended for HL409733+5.p
173389.02/22963.70	% SZS status Started for HL409739+4.p
173389.02/22963.70	% SZS status GaveUp for HL409739+4.p
173389.02/22963.70	eprover: CPU time limit exceeded, terminating
173389.02/22963.70	% SZS status Ended for HL409739+4.p
173390.95/22964.06	% SZS status Started for HL409734+5.p
173390.95/22964.06	% SZS status GaveUp for HL409734+5.p
173390.95/22964.06	eprover: CPU time limit exceeded, terminating
173390.95/22964.06	% SZS status Ended for HL409734+5.p
173395.97/22964.56	% SZS status Started for HL409735+5.p
173395.97/22964.56	% SZS status GaveUp for HL409735+5.p
173395.97/22964.56	eprover: CPU time limit exceeded, terminating
173395.97/22964.56	% SZS status Ended for HL409735+5.p
173399.86/22965.00	% SZS status Started for HL409740+4.p
173399.86/22965.00	% SZS status GaveUp for HL409740+4.p
173399.86/22965.00	eprover: CPU time limit exceeded, terminating
173399.86/22965.00	% SZS status Ended for HL409740+4.p
173416.53/22967.12	% SZS status Started for HL409742+4.p
173416.53/22967.12	% SZS status GaveUp for HL409742+4.p
173416.53/22967.12	eprover: CPU time limit exceeded, terminating
173416.53/22967.12	% SZS status Ended for HL409742+4.p
173422.05/22967.81	% SZS status Started for HL409736+5.p
173422.05/22967.81	% SZS status GaveUp for HL409736+5.p
173422.05/22967.81	eprover: CPU time limit exceeded, terminating
173422.05/22967.81	% SZS status Ended for HL409736+5.p
173423.09/22967.96	% SZS status Started for HL409737+5.p
173423.09/22967.96	% SZS status GaveUp for HL409737+5.p
173423.09/22967.96	eprover: CPU time limit exceeded, terminating
173423.09/22967.96	% SZS status Ended for HL409737+5.p
173423.53/22968.04	% SZS status Started for HL409743+4.p
173423.53/22968.04	% SZS status GaveUp for HL409743+4.p
173423.53/22968.04	eprover: CPU time limit exceeded, terminating
173423.53/22968.04	% SZS status Ended for HL409743+4.p
173443.16/22970.48	% SZS status Started for HL409738+5.p
173443.16/22970.48	% SZS status GaveUp for HL409738+5.p
173443.16/22970.48	eprover: CPU time limit exceeded, terminating
173443.16/22970.48	% SZS status Ended for HL409738+5.p
173445.16/22970.85	% SZS status Started for HL409744+4.p
173445.16/22970.85	% SZS status GaveUp for HL409744+4.p
173445.16/22970.85	eprover: CPU time limit exceeded, terminating
173445.16/22970.85	% SZS status Ended for HL409744+4.p
173448.09/22971.08	% SZS status Started for HL409745+4.p
173448.09/22971.08	% SZS status GaveUp for HL409745+4.p
173448.09/22971.08	eprover: CPU time limit exceeded, terminating
173448.09/22971.08	% SZS status Ended for HL409745+4.p
173449.80/22971.38	% SZS status Started for HL409739+5.p
173449.80/22971.38	% SZS status GaveUp for HL409739+5.p
173449.80/22971.38	eprover: CPU time limit exceeded, terminating
173449.80/22971.38	% SZS status Ended for HL409739+5.p
173470.19/22973.88	% SZS status Started for HL409746+4.p
173470.19/22973.88	% SZS status GaveUp for HL409746+4.p
173470.19/22973.88	eprover: CPU time limit exceeded, terminating
173470.19/22973.88	% SZS status Ended for HL409746+4.p
173471.78/22974.15	% SZS status Started for HL409740+5.p
173471.78/22974.15	% SZS status GaveUp for HL409740+5.p
173471.78/22974.15	eprover: CPU time limit exceeded, terminating
173471.78/22974.15	% SZS status Ended for HL409740+5.p
173474.89/22974.41	% SZS status Started for HL409747+4.p
173474.89/22974.41	% SZS status GaveUp for HL409747+4.p
173474.89/22974.41	eprover: CPU time limit exceeded, terminating
173474.89/22974.41	% SZS status Ended for HL409747+4.p
173477.39/22974.85	% SZS status Started for HL409742+5.p
173477.39/22974.85	% SZS status GaveUp for HL409742+5.p
173477.39/22974.85	eprover: CPU time limit exceeded, terminating
173477.39/22974.85	% SZS status Ended for HL409742+5.p
173496.55/22977.20	% SZS status Started for HL409748+4.p
173496.55/22977.20	% SZS status GaveUp for HL409748+4.p
173496.55/22977.20	eprover: CPU time limit exceeded, terminating
173496.55/22977.20	% SZS status Ended for HL409748+4.p
173498.67/22977.54	% SZS status Started for HL409743+5.p
173498.67/22977.54	% SZS status GaveUp for HL409743+5.p
173498.67/22977.54	eprover: CPU time limit exceeded, terminating
173498.67/22977.54	% SZS status Ended for HL409743+5.p
173502.19/22977.88	% SZS status Started for HL409749+4.p
173502.19/22977.88	% SZS status GaveUp for HL409749+4.p
173502.19/22977.88	eprover: CPU time limit exceeded, terminating
173502.19/22977.88	% SZS status Ended for HL409749+4.p
173504.78/22978.27	% SZS status Started for HL409744+5.p
173504.78/22978.27	% SZS status GaveUp for HL409744+5.p
173504.78/22978.27	eprover: CPU time limit exceeded, terminating
173504.78/22978.27	% SZS status Ended for HL409744+5.p
173523.62/22980.57	% SZS status Started for HL409750+4.p
173523.62/22980.57	% SZS status GaveUp for HL409750+4.p
173523.62/22980.57	eprover: CPU time limit exceeded, terminating
173523.62/22980.57	% SZS status Ended for HL409750+4.p
173526.05/22980.90	% SZS status Started for HL409745+5.p
173526.05/22980.90	% SZS status GaveUp for HL409745+5.p
173526.05/22980.90	eprover: CPU time limit exceeded, terminating
173526.05/22980.90	% SZS status Ended for HL409745+5.p
173529.22/22981.29	% SZS status Started for HL409751+4.p
173529.22/22981.29	% SZS status GaveUp for HL409751+4.p
173529.22/22981.29	eprover: CPU time limit exceeded, terminating
173529.22/22981.29	% SZS status Ended for HL409751+4.p
173530.98/22981.53	% SZS status Started for HL409746+5.p
173530.98/22981.53	% SZS status GaveUp for HL409746+5.p
173530.98/22981.53	eprover: CPU time limit exceeded, terminating
173530.98/22981.53	% SZS status Ended for HL409746+5.p
173550.48/22983.99	% SZS status Started for HL409753+4.p
173550.48/22983.99	% SZS status GaveUp for HL409753+4.p
173550.48/22983.99	eprover: CPU time limit exceeded, terminating
173550.48/22983.99	% SZS status Ended for HL409753+4.p
173553.23/22984.35	% SZS status Started for HL409747+5.p
173553.23/22984.35	% SZS status GaveUp for HL409747+5.p
173553.23/22984.35	eprover: CPU time limit exceeded, terminating
173553.23/22984.35	% SZS status Ended for HL409747+5.p
173556.19/22984.65	% SZS status Started for HL409755+4.p
173556.19/22984.65	% SZS status GaveUp for HL409755+4.p
173556.19/22984.65	eprover: CPU time limit exceeded, terminating
173556.19/22984.65	% SZS status Ended for HL409755+4.p
173556.78/22984.72	% SZS status Started for HL409748+5.p
173556.78/22984.72	% SZS status GaveUp for HL409748+5.p
173556.78/22984.72	eprover: CPU time limit exceeded, terminating
173556.78/22984.72	% SZS status Ended for HL409748+5.p
173578.41/22987.49	% SZS status Started for HL409756+4.p
173578.41/22987.49	% SZS status GaveUp for HL409756+4.p
173578.41/22987.49	eprover: CPU time limit exceeded, terminating
173578.41/22987.49	% SZS status Ended for HL409756+4.p
173579.08/22987.54	% SZS status Started for HL409749+5.p
173579.08/22987.54	% SZS status GaveUp for HL409749+5.p
173579.08/22987.54	eprover: CPU time limit exceeded, terminating
173579.08/22987.54	% SZS status Ended for HL409749+5.p
173580.22/22987.75	% SZS status Started for HL409758+4.p
173580.22/22987.75	% SZS status GaveUp for HL409758+4.p
173580.22/22987.75	eprover: CPU time limit exceeded, terminating
173580.22/22987.75	% SZS status Ended for HL409758+4.p
173583.88/22988.17	% SZS status Started for HL409750+5.p
173583.88/22988.17	% SZS status GaveUp for HL409750+5.p
173583.88/22988.17	eprover: CPU time limit exceeded, terminating
173583.88/22988.17	% SZS status Ended for HL409750+5.p
173603.66/22990.63	% SZS status Started for HL409759+4.p
173603.66/22990.63	% SZS status GaveUp for HL409759+4.p
173603.66/22990.63	eprover: CPU time limit exceeded, terminating
173603.66/22990.63	% SZS status Ended for HL409759+4.p
173605.41/22990.83	% SZS status Started for HL409751+5.p
173605.41/22990.83	% SZS status GaveUp for HL409751+5.p
173605.41/22990.83	eprover: CPU time limit exceeded, terminating
173605.41/22990.83	% SZS status Ended for HL409751+5.p
173607.05/22991.20	% SZS status Started for HL409760+4.p
173607.05/22991.20	% SZS status GaveUp for HL409760+4.p
173607.05/22991.20	eprover: CPU time limit exceeded, terminating
173607.05/22991.20	% SZS status Ended for HL409760+4.p
173611.06/22991.56	% SZS status Started for HL409753+5.p
173611.06/22991.56	% SZS status GaveUp for HL409753+5.p
173611.06/22991.56	eprover: CPU time limit exceeded, terminating
173611.06/22991.56	% SZS status Ended for HL409753+5.p
173629.27/22993.85	% SZS status Started for HL409761+4.p
173629.27/22993.85	% SZS status GaveUp for HL409761+4.p
173629.27/22993.85	eprover: CPU time limit exceeded, terminating
173629.27/22993.85	% SZS status Ended for HL409761+4.p
173634.38/22994.58	% SZS status Started for HL409762+4.p
173634.38/22994.58	% SZS status GaveUp for HL409762+4.p
173634.38/22994.58	eprover: CPU time limit exceeded, terminating
173634.38/22994.58	% SZS status Ended for HL409762+4.p
173637.84/22994.94	% SZS status Started for HL409756+5.p
173637.84/22994.94	% SZS status GaveUp for HL409756+5.p
173637.84/22994.94	eprover: CPU time limit exceeded, terminating
173637.84/22994.94	% SZS status Ended for HL409756+5.p
173638.92/22995.14	% SZS status Started for HL409755+5.p
173638.92/22995.14	% SZS status GaveUp for HL409755+5.p
173638.92/22995.14	eprover: CPU time limit exceeded, terminating
173638.92/22995.14	% SZS status Ended for HL409755+5.p
173659.86/22997.78	% SZS status Started for HL409763+4.p
173659.86/22997.78	% SZS status GaveUp for HL409763+4.p
173659.86/22997.78	eprover: CPU time limit exceeded, terminating
173659.86/22997.78	% SZS status Ended for HL409763+4.p
173660.53/22997.84	% SZS status Started for HL409758+5.p
173660.53/22997.84	% SZS status GaveUp for HL409758+5.p
173660.53/22997.84	eprover: CPU time limit exceeded, terminating
173660.53/22997.84	% SZS status Ended for HL409758+5.p
173662.44/22998.04	% SZS status Started for HL409759+5.p
173662.44/22998.04	% SZS status GaveUp for HL409759+5.p
173662.44/22998.04	eprover: CPU time limit exceeded, terminating
173662.44/22998.04	% SZS status Ended for HL409759+5.p
173663.52/22998.19	% SZS status Started for HL409765+4.p
173663.52/22998.19	% SZS status GaveUp for HL409765+4.p
173663.52/22998.19	eprover: CPU time limit exceeded, terminating
173663.52/22998.19	% SZS status Ended for HL409765+4.p
173685.31/23000.93	% SZS status Started for HL409767+4.p
173685.31/23000.93	% SZS status GaveUp for HL409767+4.p
173685.31/23000.93	eprover: CPU time limit exceeded, terminating
173685.31/23000.93	% SZS status Ended for HL409767+4.p
173687.38/23001.28	% SZS status Started for HL409760+5.p
173687.38/23001.28	% SZS status GaveUp for HL409760+5.p
173687.38/23001.28	eprover: CPU time limit exceeded, terminating
173687.38/23001.28	% SZS status Ended for HL409760+5.p
173687.38/23001.32	% SZS status Started for HL409768+4.p
173687.38/23001.32	% SZS status GaveUp for HL409768+4.p
173687.38/23001.32	eprover: CPU time limit exceeded, terminating
173687.38/23001.32	% SZS status Ended for HL409768+4.p
173689.48/23001.49	% SZS status Started for HL409761+5.p
173689.48/23001.49	% SZS status GaveUp for HL409761+5.p
173689.48/23001.49	eprover: CPU time limit exceeded, terminating
173689.48/23001.49	% SZS status Ended for HL409761+5.p
173711.70/23004.27	% SZS status Started for HL409762+5.p
173711.70/23004.27	% SZS status GaveUp for HL409762+5.p
173711.70/23004.27	eprover: CPU time limit exceeded, terminating
173711.70/23004.27	% SZS status Ended for HL409762+5.p
173712.06/23004.33	% SZS status Started for HL409769+4.p
173712.06/23004.33	% SZS status GaveUp for HL409769+4.p
173712.06/23004.33	eprover: CPU time limit exceeded, terminating
173712.06/23004.33	% SZS status Ended for HL409769+4.p
173712.84/23004.57	% SZS status Started for HL409770+4.p
173712.84/23004.57	% SZS status GaveUp for HL409770+4.p
173712.84/23004.57	eprover: CPU time limit exceeded, terminating
173712.84/23004.57	% SZS status Ended for HL409770+4.p
173718.72/23005.23	% SZS status Started for HL409763+5.p
173718.72/23005.23	% SZS status GaveUp for HL409763+5.p
173718.72/23005.23	eprover: CPU time limit exceeded, terminating
173718.72/23005.23	% SZS status Ended for HL409763+5.p
173736.19/23007.38	% SZS status Started for HL409771+4.p
173736.19/23007.38	% SZS status GaveUp for HL409771+4.p
173736.19/23007.38	eprover: CPU time limit exceeded, terminating
173736.19/23007.38	% SZS status Ended for HL409771+4.p
173742.58/23008.17	% SZS status Started for HL409765+5.p
173742.58/23008.17	% SZS status GaveUp for HL409765+5.p
173742.58/23008.17	eprover: CPU time limit exceeded, terminating
173742.58/23008.17	% SZS status Ended for HL409765+5.p
173743.36/23008.28	% SZS status Started for HL409773+4.p
173743.36/23008.28	% SZS status GaveUp for HL409773+4.p
173743.36/23008.28	eprover: CPU time limit exceeded, terminating
173743.36/23008.28	% SZS status Ended for HL409773+4.p
173744.02/23008.41	% SZS status Started for HL409767+5.p
173744.02/23008.41	% SZS status GaveUp for HL409767+5.p
173744.02/23008.41	eprover: CPU time limit exceeded, terminating
173744.02/23008.41	% SZS status Ended for HL409767+5.p
173765.70/23011.23	% SZS status Started for HL409774+4.p
173765.70/23011.23	% SZS status GaveUp for HL409774+4.p
173765.70/23011.23	eprover: CPU time limit exceeded, terminating
173765.70/23011.23	% SZS status Ended for HL409774+4.p
173768.81/23011.47	% SZS status Started for HL409775+4.p
173768.81/23011.47	% SZS status GaveUp for HL409775+4.p
173768.81/23011.47	eprover: CPU time limit exceeded, terminating
173768.81/23011.47	% SZS status Ended for HL409775+4.p
173769.34/23011.56	% SZS status Started for HL409768+5.p
173769.34/23011.56	% SZS status GaveUp for HL409768+5.p
173769.34/23011.56	eprover: CPU time limit exceeded, terminating
173769.34/23011.56	% SZS status Ended for HL409768+5.p
173769.89/23011.66	% SZS status Started for HL409769+5.p
173769.89/23011.66	% SZS status GaveUp for HL409769+5.p
173769.89/23011.66	eprover: CPU time limit exceeded, terminating
173769.89/23011.66	% SZS status Ended for HL409769+5.p
173792.64/23014.52	% SZS status Started for HL409776+4.p
173792.64/23014.52	% SZS status GaveUp for HL409776+4.p
173792.64/23014.52	eprover: CPU time limit exceeded, terminating
173792.64/23014.52	% SZS status Ended for HL409776+4.p
173793.19/23014.58	% SZS status Started for HL409770+5.p
173793.19/23014.58	% SZS status GaveUp for HL409770+5.p
173793.19/23014.58	eprover: CPU time limit exceeded, terminating
173793.19/23014.58	% SZS status Ended for HL409770+5.p
173793.70/23014.71	% SZS status Started for HL409778+4.p
173793.70/23014.71	% SZS status GaveUp for HL409778+4.p
173793.70/23014.71	eprover: CPU time limit exceeded, terminating
173793.70/23014.71	% SZS status Ended for HL409778+4.p
173795.94/23014.92	% SZS status Started for HL409771+5.p
173795.94/23014.92	% SZS status GaveUp for HL409771+5.p
173795.94/23014.92	eprover: CPU time limit exceeded, terminating
173795.94/23014.92	% SZS status Ended for HL409771+5.p
173817.81/23017.72	% SZS status Started for HL409779+4.p
173817.81/23017.72	% SZS status GaveUp for HL409779+4.p
173817.81/23017.72	eprover: CPU time limit exceeded, terminating
173817.81/23017.72	% SZS status Ended for HL409779+4.p
173818.58/23017.81	% SZS status Started for HL409773+5.p
173818.58/23017.81	% SZS status GaveUp for HL409773+5.p
173818.58/23017.81	eprover: CPU time limit exceeded, terminating
173818.58/23017.81	% SZS status Ended for HL409773+5.p
173819.44/23017.97	% SZS status Started for HL409780+4.p
173819.44/23017.97	% SZS status GaveUp for HL409780+4.p
173819.44/23017.97	eprover: CPU time limit exceeded, terminating
173819.44/23017.97	% SZS status Ended for HL409780+4.p
173827.25/23018.90	% SZS status Started for HL409774+5.p
173827.25/23018.90	% SZS status GaveUp for HL409774+5.p
173827.25/23018.90	eprover: CPU time limit exceeded, terminating
173827.25/23018.90	% SZS status Ended for HL409774+5.p
173842.91/23020.94	% SZS status Started for HL409782+4.p
173842.91/23020.94	% SZS status GaveUp for HL409782+4.p
173842.91/23020.94	eprover: CPU time limit exceeded, terminating
173842.91/23020.94	% SZS status Ended for HL409782+4.p
173848.06/23021.54	% SZS status Started for HL409775+5.p
173848.06/23021.54	% SZS status GaveUp for HL409775+5.p
173848.06/23021.54	eprover: CPU time limit exceeded, terminating
173848.06/23021.54	% SZS status Ended for HL409775+5.p
173850.89/23021.90	% SZS status Started for HL409776+5.p
173850.89/23021.90	% SZS status GaveUp for HL409776+5.p
173850.89/23021.90	eprover: CPU time limit exceeded, terminating
173850.89/23021.90	% SZS status Ended for HL409776+5.p
173851.19/23021.95	% SZS status Started for HL409783+4.p
173851.19/23021.95	% SZS status GaveUp for HL409783+4.p
173851.19/23021.95	eprover: CPU time limit exceeded, terminating
173851.19/23021.95	% SZS status Ended for HL409783+4.p
173874.95/23024.56	% SZS status Started for HL409785+4.p
173874.95/23024.56	% SZS status GaveUp for HL409785+4.p
173874.95/23024.56	eprover: CPU time limit exceeded, terminating
173874.95/23024.56	% SZS status Ended for HL409785+4.p
173877.94/23024.91	% SZS status Started for HL409778+5.p
173877.94/23024.91	% SZS status GaveUp for HL409778+5.p
173877.94/23024.91	eprover: CPU time limit exceeded, terminating
173877.94/23024.91	% SZS status Ended for HL409778+5.p
173878.61/23024.99	% SZS status Started for HL409786+4.p
173878.61/23024.99	% SZS status GaveUp for HL409786+4.p
173878.61/23024.99	eprover: CPU time limit exceeded, terminating
173878.61/23024.99	% SZS status Ended for HL409786+4.p
173879.73/23025.14	% SZS status Started for HL409779+5.p
173879.73/23025.14	% SZS status GaveUp for HL409779+5.p
173879.73/23025.14	eprover: CPU time limit exceeded, terminating
173879.73/23025.14	% SZS status Ended for HL409779+5.p
173902.55/23027.98	% SZS status Started for HL409787+4.p
173902.55/23027.98	% SZS status GaveUp for HL409787+4.p
173902.55/23027.98	eprover: CPU time limit exceeded, terminating
173902.55/23027.98	% SZS status Ended for HL409787+4.p
173903.67/23028.16	% SZS status Started for HL409789+4.p
173903.67/23028.16	% SZS status GaveUp for HL409789+4.p
173903.67/23028.16	eprover: CPU time limit exceeded, terminating
173903.67/23028.16	% SZS status Ended for HL409789+4.p
173904.50/23028.28	% SZS status Started for HL409782+5.p
173904.50/23028.28	% SZS status GaveUp for HL409782+5.p
173904.50/23028.28	eprover: CPU time limit exceeded, terminating
173904.50/23028.28	% SZS status Ended for HL409782+5.p
173904.84/23028.39	% SZS status Started for HL409780+5.p
173904.84/23028.39	% SZS status GaveUp for HL409780+5.p
173904.84/23028.39	eprover: CPU time limit exceeded, terminating
173904.84/23028.39	% SZS status Ended for HL409780+5.p
173927.77/23031.20	% SZS status Started for HL409790+4.p
173927.77/23031.20	% SZS status GaveUp for HL409790+4.p
173927.77/23031.20	eprover: CPU time limit exceeded, terminating
173927.77/23031.20	% SZS status Ended for HL409790+4.p
173929.33/23031.41	% SZS status Started for HL409791+4.p
173929.33/23031.41	% SZS status GaveUp for HL409791+4.p
173929.33/23031.41	eprover: CPU time limit exceeded, terminating
173929.33/23031.41	% SZS status Ended for HL409791+4.p
173930.09/23031.51	% SZS status Started for HL409783+5.p
173930.09/23031.51	% SZS status GaveUp for HL409783+5.p
173930.09/23031.51	eprover: CPU time limit exceeded, terminating
173930.09/23031.51	% SZS status Ended for HL409783+5.p
173936.38/23032.33	% SZS status Started for HL409785+5.p
173936.38/23032.33	% SZS status GaveUp for HL409785+5.p
173936.38/23032.33	eprover: CPU time limit exceeded, terminating
173936.38/23032.33	% SZS status Ended for HL409785+5.p
173953.19/23034.45	% SZS status Started for HL409792+4.p
173953.19/23034.45	% SZS status GaveUp for HL409792+4.p
173953.19/23034.45	eprover: CPU time limit exceeded, terminating
173953.19/23034.45	% SZS status Ended for HL409792+4.p
173959.70/23035.23	% SZS status Started for HL409786+5.p
173959.70/23035.23	% SZS status GaveUp for HL409786+5.p
173959.70/23035.23	eprover: CPU time limit exceeded, terminating
173959.70/23035.23	% SZS status Ended for HL409786+5.p
173960.17/23035.31	% SZS status Started for HL409787+5.p
173960.17/23035.31	% SZS status GaveUp for HL409787+5.p
173960.17/23035.31	eprover: CPU time limit exceeded, terminating
173960.17/23035.31	% SZS status Ended for HL409787+5.p
173961.00/23035.39	% SZS status Started for HL409793+4.p
173961.00/23035.39	% SZS status GaveUp for HL409793+4.p
173961.00/23035.39	eprover: CPU time limit exceeded, terminating
173961.00/23035.39	% SZS status Ended for HL409793+4.p
173983.89/23038.30	% SZS status Started for HL409794+4.p
173983.89/23038.30	% SZS status GaveUp for HL409794+4.p
173983.89/23038.30	eprover: CPU time limit exceeded, terminating
173983.89/23038.30	% SZS status Ended for HL409794+4.p
173984.83/23038.43	% SZS status Started for HL409795+4.p
173984.83/23038.43	% SZS status GaveUp for HL409795+4.p
173984.83/23038.43	eprover: CPU time limit exceeded, terminating
173984.83/23038.43	% SZS status Ended for HL409795+4.p
173985.92/23038.55	% SZS status Started for HL409790+5.p
173985.92/23038.55	% SZS status GaveUp for HL409790+5.p
173985.92/23038.55	eprover: CPU time limit exceeded, terminating
173985.92/23038.55	% SZS status Ended for HL409790+5.p
173986.34/23038.66	% SZS status Started for HL409789+5.p
173986.34/23038.66	% SZS status GaveUp for HL409789+5.p
173986.34/23038.66	eprover: CPU time limit exceeded, terminating
173986.34/23038.66	% SZS status Ended for HL409789+5.p
174009.12/23041.48	% SZS status Started for HL409796+4.p
174009.12/23041.48	% SZS status GaveUp for HL409796+4.p
174009.12/23041.48	eprover: CPU time limit exceeded, terminating
174009.12/23041.48	% SZS status Ended for HL409796+4.p
174010.72/23041.71	% SZS status Started for HL409797+4.p
174010.72/23041.71	% SZS status GaveUp for HL409797+4.p
174010.72/23041.71	eprover: CPU time limit exceeded, terminating
174010.72/23041.71	% SZS status Ended for HL409797+4.p
174012.17/23041.86	% SZS status Started for HL409791+5.p
174012.17/23041.86	% SZS status GaveUp for HL409791+5.p
174012.17/23041.86	eprover: CPU time limit exceeded, terminating
174012.17/23041.86	% SZS status Ended for HL409791+5.p
174013.56/23042.03	% SZS status Started for HL409792+5.p
174013.56/23042.03	% SZS status GaveUp for HL409792+5.p
174013.56/23042.03	eprover: CPU time limit exceeded, terminating
174013.56/23042.03	% SZS status Ended for HL409792+5.p
174034.94/23044.74	% SZS status Started for HL409793+5.p
174034.94/23044.74	% SZS status GaveUp for HL409793+5.p
174034.94/23044.74	eprover: CPU time limit exceeded, terminating
174034.94/23044.74	% SZS status Ended for HL409793+5.p
174035.31/23044.74	% SZS status Started for HL409798+4.p
174035.31/23044.74	% SZS status GaveUp for HL409798+4.p
174035.31/23044.74	eprover: CPU time limit exceeded, terminating
174035.31/23044.74	% SZS status Ended for HL409798+4.p
174036.03/23045.08	% SZS status Started for HL409799+4.p
174036.03/23045.08	% SZS status GaveUp for HL409799+4.p
174036.03/23045.08	eprover: CPU time limit exceeded, terminating
174036.03/23045.08	% SZS status Ended for HL409799+4.p
174042.41/23045.64	% SZS status Started for HL409794+5.p
174042.41/23045.64	% SZS status GaveUp for HL409794+5.p
174042.41/23045.64	eprover: CPU time limit exceeded, terminating
174042.41/23045.64	% SZS status Ended for HL409794+5.p
174070.23/23047.90	% SZS status Started for HL409800+4.p
174070.23/23047.90	% SZS status GaveUp for HL409800+4.p
174070.23/23047.90	eprover: CPU time limit exceeded, terminating
174070.23/23047.90	% SZS status Ended for HL409800+4.p
174076.55/23048.67	% SZS status Started for HL409801+4.p
174076.55/23048.67	% SZS status GaveUp for HL409801+4.p
174076.55/23048.67	eprover: CPU time limit exceeded, terminating
174076.55/23048.67	% SZS status Ended for HL409801+4.p
174077.22/23048.78	% SZS status Started for HL409795+5.p
174077.22/23048.78	% SZS status GaveUp for HL409795+5.p
174077.22/23048.78	eprover: CPU time limit exceeded, terminating
174077.22/23048.78	% SZS status Ended for HL409795+5.p
174078.27/23048.92	% SZS status Started for HL409796+5.p
174078.27/23048.92	% SZS status GaveUp for HL409796+5.p
174078.27/23048.92	eprover: CPU time limit exceeded, terminating
174078.27/23048.92	% SZS status Ended for HL409796+5.p
174100.70/23051.80	% SZS status Started for HL409802+4.p
174100.70/23051.80	% SZS status GaveUp for HL409802+4.p
174100.70/23051.80	eprover: CPU time limit exceeded, terminating
174100.70/23051.80	% SZS status Ended for HL409802+4.p
174102.03/23051.89	% SZS status Started for HL409797+5.p
174102.03/23051.89	% SZS status GaveUp for HL409797+5.p
174102.03/23051.89	eprover: CPU time limit exceeded, terminating
174102.03/23051.89	% SZS status Ended for HL409797+5.p
174102.03/23051.94	% SZS status Started for HL409803+4.p
174102.03/23051.94	% SZS status GaveUp for HL409803+4.p
174102.03/23051.94	eprover: CPU time limit exceeded, terminating
174102.03/23051.94	% SZS status Ended for HL409803+4.p
174103.33/23052.14	% SZS status Started for HL409798+5.p
174103.33/23052.14	% SZS status GaveUp for HL409798+5.p
174103.33/23052.14	eprover: CPU time limit exceeded, terminating
174103.33/23052.14	% SZS status Ended for HL409798+5.p
174125.78/23054.93	% SZS status Started for HL409804+4.p
174125.78/23054.93	% SZS status GaveUp for HL409804+4.p
174125.78/23054.93	eprover: CPU time limit exceeded, terminating
174125.78/23054.93	% SZS status Ended for HL409804+4.p
174127.80/23055.17	% SZS status Started for HL409806+4.p
174127.80/23055.17	% SZS status GaveUp for HL409806+4.p
174127.80/23055.17	eprover: CPU time limit exceeded, terminating
174127.80/23055.17	% SZS status Ended for HL409806+4.p
174128.22/23055.22	% SZS status Started for HL409799+5.p
174128.22/23055.22	% SZS status GaveUp for HL409799+5.p
174128.22/23055.22	eprover: CPU time limit exceeded, terminating
174128.22/23055.22	% SZS status Ended for HL409799+5.p
174129.20/23055.46	% SZS status Started for HL409800+5.p
174129.20/23055.46	% SZS status GaveUp for HL409800+5.p
174129.20/23055.46	eprover: CPU time limit exceeded, terminating
174129.20/23055.46	% SZS status Ended for HL409800+5.p
174151.86/23058.19	% SZS status Started for HL409807+4.p
174151.86/23058.19	% SZS status GaveUp for HL409807+4.p
174151.86/23058.19	eprover: CPU time limit exceeded, terminating
174151.86/23058.19	% SZS status Ended for HL409807+4.p
174152.27/23058.28	% SZS status Started for HL409807+5.p
174152.27/23058.28	% SZS status GaveUp for HL409807+5.p
174152.27/23058.28	eprover: CPU time limit exceeded, terminating
174152.27/23058.28	% SZS status Ended for HL409807+5.p
174152.53/23058.37	% SZS status Started for HL409801+5.p
174152.53/23058.37	% SZS status GaveUp for HL409801+5.p
174152.53/23058.37	eprover: CPU time limit exceeded, terminating
174152.53/23058.37	% SZS status Ended for HL409801+5.p
174154.44/23058.49	% SZS status Started for HL409808+4.p
174154.44/23058.49	% SZS status GaveUp for HL409808+4.p
174154.44/23058.49	eprover: CPU time limit exceeded, terminating
174154.44/23058.49	% SZS status Ended for HL409808+4.p
174160.59/23059.34	% SZS status Started for HL409802+5.p
174160.59/23059.34	% SZS status GaveUp for HL409802+5.p
174160.59/23059.34	eprover: CPU time limit exceeded, terminating
174160.59/23059.34	% SZS status Ended for HL409802+5.p
174176.75/23061.33	% SZS status Started for HL409809+4.p
174176.75/23061.33	% SZS status GaveUp for HL409809+4.p
174176.75/23061.33	eprover: CPU time limit exceeded, terminating
174176.75/23061.33	% SZS status Ended for HL409809+4.p
174178.08/23061.57	% SZS status Started for HL409810+4.p
174178.08/23061.57	% SZS status GaveUp for HL409810+4.p
174178.08/23061.57	eprover: CPU time limit exceeded, terminating
174178.08/23061.57	% SZS status Ended for HL409810+4.p
174182.27/23062.06	% SZS status Started for HL409803+5.p
174182.27/23062.06	% SZS status GaveUp for HL409803+5.p
174182.27/23062.06	eprover: CPU time limit exceeded, terminating
174182.27/23062.06	% SZS status Ended for HL409803+5.p
174184.36/23062.27	% SZS status Started for HL409804+5.p
174184.36/23062.27	% SZS status GaveUp for HL409804+5.p
174184.36/23062.27	eprover: CPU time limit exceeded, terminating
174184.36/23062.27	% SZS status Ended for HL409804+5.p
174201.00/23064.35	% SZS status Started for HL409811+4.p
174201.00/23064.35	% SZS status GaveUp for HL409811+4.p
174201.00/23064.35	eprover: CPU time limit exceeded, terminating
174201.00/23064.35	% SZS status Ended for HL409811+4.p
174205.28/23065.09	% SZS status Started for HL409812+4.p
174205.28/23065.09	% SZS status GaveUp for HL409812+4.p
174205.28/23065.09	eprover: CPU time limit exceeded, terminating
174205.28/23065.09	% SZS status Ended for HL409812+4.p
174208.84/23065.38	% SZS status Started for HL409806+5.p
174208.84/23065.38	% SZS status GaveUp for HL409806+5.p
174208.84/23065.38	eprover: CPU time limit exceeded, terminating
174208.84/23065.38	% SZS status Ended for HL409806+5.p
174224.91/23067.41	% SZS status Started for HL409814+4.p
174224.91/23067.41	% SZS status GaveUp for HL409814+4.p
174224.91/23067.41	eprover: CPU time limit exceeded, terminating
174224.91/23067.41	% SZS status Ended for HL409814+4.p
174232.91/23068.42	% SZS status Started for HL409815+4.p
174232.91/23068.42	% SZS status GaveUp for HL409815+4.p
174232.91/23068.42	eprover: CPU time limit exceeded, terminating
174232.91/23068.42	% SZS status Ended for HL409815+4.p
174235.67/23068.77	% SZS status Started for HL409809+5.p
174235.67/23068.77	% SZS status GaveUp for HL409809+5.p
174235.67/23068.77	eprover: CPU time limit exceeded, terminating
174235.67/23068.77	% SZS status Ended for HL409809+5.p
174236.50/23068.91	% SZS status Started for HL409808+5.p
174236.50/23068.91	% SZS status GaveUp for HL409808+5.p
174236.50/23068.91	eprover: CPU time limit exceeded, terminating
174236.50/23068.91	% SZS status Ended for HL409808+5.p
174243.52/23069.78	% SZS status Started for HL409810+5.p
174243.52/23069.78	% SZS status GaveUp for HL409810+5.p
174243.52/23069.78	eprover: CPU time limit exceeded, terminating
174243.52/23069.78	% SZS status Ended for HL409810+5.p
174257.19/23071.48	% SZS status Started for HL409816+4.p
174257.19/23071.48	% SZS status GaveUp for HL409816+4.p
174257.19/23071.48	eprover: CPU time limit exceeded, terminating
174257.19/23071.48	% SZS status Ended for HL409816+4.p
174261.38/23071.96	% SZS status Started for HL409817+4.p
174261.38/23071.96	% SZS status GaveUp for HL409817+4.p
174261.38/23071.96	eprover: CPU time limit exceeded, terminating
174261.38/23071.96	% SZS status Ended for HL409817+4.p
174261.38/23071.96	% SZS status Started for HL409811+5.p
174261.38/23071.96	% SZS status GaveUp for HL409811+5.p
174261.38/23071.96	eprover: CPU time limit exceeded, terminating
174261.38/23071.96	% SZS status Ended for HL409811+5.p
174266.47/23072.69	% SZS status Started for HL409812+5.p
174266.47/23072.69	% SZS status GaveUp for HL409812+5.p
174266.47/23072.69	eprover: CPU time limit exceeded, terminating
174266.47/23072.69	% SZS status Ended for HL409812+5.p
174282.11/23074.61	% SZS status Started for HL409818+4.p
174282.11/23074.61	% SZS status GaveUp for HL409818+4.p
174282.11/23074.61	eprover: CPU time limit exceeded, terminating
174282.11/23074.61	% SZS status Ended for HL409818+4.p
174284.70/23074.99	% SZS status Started for HL409819+4.p
174284.70/23074.99	% SZS status GaveUp for HL409819+4.p
174284.70/23074.99	eprover: CPU time limit exceeded, terminating
174284.70/23074.99	% SZS status Ended for HL409819+4.p
174287.88/23075.41	% SZS status Started for HL409814+5.p
174287.88/23075.41	% SZS status GaveUp for HL409814+5.p
174287.88/23075.41	eprover: CPU time limit exceeded, terminating
174287.88/23075.41	% SZS status Ended for HL409814+5.p
174306.98/23077.78	% SZS status Started for HL409820+4.p
174306.98/23077.78	% SZS status GaveUp for HL409820+4.p
174306.98/23077.78	eprover: CPU time limit exceeded, terminating
174306.98/23077.78	% SZS status Ended for HL409820+4.p
174306.98/23077.79	% SZS status Started for HL409815+5.p
174306.98/23077.79	% SZS status GaveUp for HL409815+5.p
174306.98/23077.79	eprover: CPU time limit exceeded, terminating
174306.98/23077.79	% SZS status Ended for HL409815+5.p
174312.61/23078.44	% SZS status Started for HL409821+4.p
174312.61/23078.44	% SZS status GaveUp for HL409821+4.p
174312.61/23078.44	eprover: CPU time limit exceeded, terminating
174312.61/23078.44	% SZS status Ended for HL409821+4.p
174318.86/23079.26	% SZS status Started for HL409816+5.p
174318.86/23079.26	% SZS status GaveUp for HL409816+5.p
174318.86/23079.26	eprover: CPU time limit exceeded, terminating
174318.86/23079.26	% SZS status Ended for HL409816+5.p
174327.09/23080.24	% SZS status Started for HL409817+5.p
174327.09/23080.24	% SZS status GaveUp for HL409817+5.p
174327.09/23080.24	eprover: CPU time limit exceeded, terminating
174327.09/23080.24	% SZS status Ended for HL409817+5.p
174331.27/23080.81	% SZS status Started for HL409822+4.p
174331.27/23080.81	% SZS status GaveUp for HL409822+4.p
174331.27/23080.81	eprover: CPU time limit exceeded, terminating
174331.27/23080.81	% SZS status Ended for HL409822+4.p
174344.08/23082.41	% SZS status Started for HL409823+4.p
174344.08/23082.41	% SZS status GaveUp for HL409823+4.p
174344.08/23082.41	eprover: CPU time limit exceeded, terminating
174344.08/23082.41	% SZS status Ended for HL409823+4.p
174344.59/23082.49	% SZS status Started for HL409818+5.p
174344.59/23082.49	% SZS status GaveUp for HL409818+5.p
174344.59/23082.49	eprover: CPU time limit exceeded, terminating
174344.59/23082.49	% SZS status Ended for HL409818+5.p
174348.98/23083.00	% SZS status Started for HL409819+5.p
174348.98/23083.00	% SZS status GaveUp for HL409819+5.p
174348.98/23083.00	eprover: CPU time limit exceeded, terminating
174348.98/23083.00	% SZS status Ended for HL409819+5.p
174355.11/23083.84	% SZS status Started for HL409824+4.p
174355.11/23083.84	% SZS status GaveUp for HL409824+4.p
174355.11/23083.84	eprover: CPU time limit exceeded, terminating
174355.11/23083.84	% SZS status Ended for HL409824+4.p
174367.08/23085.33	% SZS status Started for HL409820+5.p
174367.08/23085.33	% SZS status GaveUp for HL409820+5.p
174367.08/23085.33	eprover: CPU time limit exceeded, terminating
174367.08/23085.33	% SZS status Ended for HL409820+5.p
174368.12/23085.53	% SZS status Started for HL409825+4.p
174368.12/23085.53	% SZS status GaveUp for HL409825+4.p
174368.12/23085.53	eprover: CPU time limit exceeded, terminating
174368.12/23085.53	% SZS status Ended for HL409825+4.p
174379.77/23086.93	% SZS status Started for HL409827+4.p
174379.77/23086.93	% SZS status GaveUp for HL409827+4.p
174379.77/23086.93	eprover: CPU time limit exceeded, terminating
174379.77/23086.93	% SZS status Ended for HL409827+4.p
174389.92/23088.18	% SZS status Started for HL409821+5.p
174389.92/23088.18	% SZS status GaveUp for HL409821+5.p
174389.92/23088.18	eprover: CPU time limit exceeded, terminating
174389.92/23088.18	% SZS status Ended for HL409821+5.p
174393.05/23088.62	% SZS status Started for HL409828+4.p
174393.05/23088.62	% SZS status GaveUp for HL409828+4.p
174393.05/23088.62	eprover: CPU time limit exceeded, terminating
174393.05/23088.62	% SZS status Ended for HL409828+4.p
174393.88/23088.75	% SZS status Started for HL409822+5.p
174393.88/23088.75	% SZS status GaveUp for HL409822+5.p
174393.88/23088.75	eprover: CPU time limit exceeded, terminating
174393.88/23088.75	% SZS status Ended for HL409822+5.p
174407.28/23090.52	% SZS status Started for HL409823+5.p
174407.28/23090.52	% SZS status GaveUp for HL409823+5.p
174407.28/23090.52	eprover: CPU time limit exceeded, terminating
174407.28/23090.52	% SZS status Ended for HL409823+5.p
174413.98/23091.21	% SZS status Started for HL409830+4.p
174413.98/23091.21	% SZS status GaveUp for HL409830+4.p
174413.98/23091.21	eprover: CPU time limit exceeded, terminating
174413.98/23091.21	% SZS status Ended for HL409830+4.p
174419.11/23091.86	% SZS status Started for HL409831+4.p
174419.11/23091.86	% SZS status GaveUp for HL409831+4.p
174419.11/23091.86	eprover: CPU time limit exceeded, terminating
174419.11/23091.86	% SZS status Ended for HL409831+4.p
174426.08/23092.78	% SZS status Started for HL409824+5.p
174426.08/23092.78	% SZS status GaveUp for HL409824+5.p
174426.08/23092.78	eprover: CPU time limit exceeded, terminating
174426.08/23092.78	% SZS status Ended for HL409824+5.p
174429.11/23093.28	% SZS status Started for HL409825+5.p
174429.11/23093.28	% SZS status GaveUp for HL409825+5.p
174429.11/23093.28	eprover: CPU time limit exceeded, terminating
174429.11/23093.28	% SZS status Ended for HL409825+5.p
174437.48/23094.23	% SZS status Started for HL409832+4.p
174437.48/23094.23	% SZS status GaveUp for HL409832+4.p
174437.48/23094.23	eprover: CPU time limit exceeded, terminating
174437.48/23094.23	% SZS status Ended for HL409832+4.p
174450.92/23095.87	% SZS status Started for HL409833+4.p
174450.92/23095.87	% SZS status GaveUp for HL409833+4.p
174450.92/23095.87	eprover: CPU time limit exceeded, terminating
174450.92/23095.87	% SZS status Ended for HL409833+4.p
174451.72/23096.03	% SZS status Started for HL409827+5.p
174451.72/23096.03	% SZS status GaveUp for HL409827+5.p
174451.72/23096.03	eprover: CPU time limit exceeded, terminating
174451.72/23096.03	% SZS status Ended for HL409827+5.p
174461.25/23097.19	% SZS status Started for HL409828+5.p
174461.25/23097.19	% SZS status GaveUp for HL409828+5.p
174461.25/23097.19	eprover: CPU time limit exceeded, terminating
174461.25/23097.19	% SZS status Ended for HL409828+5.p
174461.80/23097.26	% SZS status Started for HL409834+4.p
174461.80/23097.26	% SZS status GaveUp for HL409834+4.p
174461.80/23097.26	eprover: CPU time limit exceeded, terminating
174461.80/23097.26	% SZS status Ended for HL409834+4.p
174474.86/23098.94	% SZS status Started for HL409830+5.p
174474.86/23098.94	% SZS status GaveUp for HL409830+5.p
174474.86/23098.94	eprover: CPU time limit exceeded, terminating
174474.86/23098.94	% SZS status Ended for HL409830+5.p
174476.41/23099.07	% SZS status Started for HL409835+4.p
174476.41/23099.07	% SZS status GaveUp for HL409835+4.p
174476.41/23099.07	eprover: CPU time limit exceeded, terminating
174476.41/23099.07	% SZS status Ended for HL409835+4.p
174486.19/23100.33	% SZS status Started for HL409836+4.p
174486.19/23100.33	% SZS status GaveUp for HL409836+4.p
174486.19/23100.33	eprover: CPU time limit exceeded, terminating
174486.19/23100.33	% SZS status Ended for HL409836+4.p
174493.31/23101.23	% SZS status Started for HL409831+5.p
174493.31/23101.23	% SZS status GaveUp for HL409831+5.p
174493.31/23101.23	eprover: CPU time limit exceeded, terminating
174493.31/23101.23	% SZS status Ended for HL409831+5.p
174500.39/23102.12	% SZS status Started for HL409838+4.p
174500.39/23102.12	% SZS status GaveUp for HL409838+4.p
174500.39/23102.12	eprover: CPU time limit exceeded, terminating
174500.39/23102.12	% SZS status Ended for HL409838+4.p
174504.56/23102.63	% SZS status Started for HL409832+5.p
174504.56/23102.63	% SZS status GaveUp for HL409832+5.p
174504.56/23102.63	eprover: CPU time limit exceeded, terminating
174504.56/23102.63	% SZS status Ended for HL409832+5.p
174513.38/23103.76	% SZS status Started for HL409833+5.p
174513.38/23103.76	% SZS status GaveUp for HL409833+5.p
174513.38/23103.76	eprover: CPU time limit exceeded, terminating
174513.38/23103.76	% SZS status Ended for HL409833+5.p
174517.89/23104.27	% SZS status Started for HL409840+4.p
174517.89/23104.27	% SZS status GaveUp for HL409840+4.p
174517.89/23104.27	eprover: CPU time limit exceeded, terminating
174517.89/23104.27	% SZS status Ended for HL409840+4.p
174528.14/23105.66	% SZS status Started for HL409842+4.p
174528.14/23105.66	% SZS status GaveUp for HL409842+4.p
174528.14/23105.66	eprover: CPU time limit exceeded, terminating
174528.14/23105.66	% SZS status Ended for HL409842+4.p
174534.03/23106.14	% SZS status Started for HL409834+5.p
174534.03/23106.14	% SZS status GaveUp for HL409834+5.p
174534.03/23106.14	eprover: CPU time limit exceeded, terminating
174534.03/23106.14	% SZS status Ended for HL409834+5.p
174543.75/23107.33	% SZS status Started for HL409843+4.p
174543.75/23107.33	% SZS status GaveUp for HL409843+4.p
174543.75/23107.33	eprover: CPU time limit exceeded, terminating
174543.75/23107.33	% SZS status Ended for HL409843+4.p
174547.95/23107.61	% SZS status Started for HL409835+5.p
174547.95/23107.61	% SZS status GaveUp for HL409835+5.p
174547.95/23107.61	eprover: CPU time limit exceeded, terminating
174547.95/23107.61	% SZS status Ended for HL409835+5.p
174560.97/23109.16	% SZS status Started for HL409844+4.p
174560.97/23109.16	% SZS status GaveUp for HL409844+4.p
174560.97/23109.16	eprover: CPU time limit exceeded, terminating
174560.97/23109.16	% SZS status Ended for HL409844+4.p
174562.77/23109.46	% SZS status Started for HL409836+5.p
174562.77/23109.46	% SZS status GaveUp for HL409836+5.p
174562.77/23109.46	eprover: CPU time limit exceeded, terminating
174562.77/23109.46	% SZS status Ended for HL409836+5.p
174572.31/23110.60	% SZS status Started for HL409838+5.p
174572.31/23110.60	% SZS status GaveUp for HL409838+5.p
174572.31/23110.60	eprover: CPU time limit exceeded, terminating
174572.31/23110.60	% SZS status Ended for HL409838+5.p
174572.98/23110.66	% SZS status Started for HL409845+4.p
174572.98/23110.66	% SZS status GaveUp for HL409845+4.p
174572.98/23110.66	eprover: CPU time limit exceeded, terminating
174572.98/23110.66	% SZS status Ended for HL409845+4.p
174587.31/23112.45	% SZS status Started for HL409840+5.p
174587.31/23112.45	% SZS status GaveUp for HL409840+5.p
174587.31/23112.45	eprover: CPU time limit exceeded, terminating
174587.31/23112.45	% SZS status Ended for HL409840+5.p
174587.77/23112.53	% SZS status Started for HL409846+4.p
174587.77/23112.53	% SZS status GaveUp for HL409846+4.p
174587.77/23112.53	eprover: CPU time limit exceeded, terminating
174587.77/23112.53	% SZS status Ended for HL409846+4.p
174597.02/23113.69	% SZS status Started for HL409847+4.p
174597.02/23113.69	% SZS status GaveUp for HL409847+4.p
174597.02/23113.69	eprover: CPU time limit exceeded, terminating
174597.02/23113.69	% SZS status Ended for HL409847+4.p
174600.27/23114.10	% SZS status Started for HL409842+5.p
174600.27/23114.10	% SZS status GaveUp for HL409842+5.p
174600.27/23114.10	eprover: CPU time limit exceeded, terminating
174600.27/23114.10	% SZS status Ended for HL409842+5.p
174612.27/23115.63	% SZS status Started for HL409848+4.p
174612.27/23115.63	% SZS status GaveUp for HL409848+4.p
174612.27/23115.63	eprover: CPU time limit exceeded, terminating
174612.27/23115.63	% SZS status Ended for HL409848+4.p
174614.61/23116.01	% SZS status Started for HL409843+5.p
174614.61/23116.01	% SZS status GaveUp for HL409843+5.p
174614.61/23116.01	eprover: CPU time limit exceeded, terminating
174614.61/23116.01	% SZS status Ended for HL409843+5.p
174624.48/23117.20	% SZS status Started for HL409849+4.p
174624.48/23117.20	% SZS status GaveUp for HL409849+4.p
174624.48/23117.20	eprover: CPU time limit exceeded, terminating
174624.48/23117.20	% SZS status Ended for HL409849+4.p
174628.94/23117.75	% SZS status Started for HL409844+5.p
174628.94/23117.75	% SZS status GaveUp for HL409844+5.p
174628.94/23117.75	eprover: CPU time limit exceeded, terminating
174628.94/23117.75	% SZS status Ended for HL409844+5.p
174636.73/23118.67	% SZS status Started for HL409849+5.p
174636.73/23118.67	% SZS status GaveUp for HL409849+5.p
174636.73/23118.67	eprover: CPU time limit exceeded, terminating
174636.73/23118.67	% SZS status Ended for HL409849+5.p
174639.02/23119.05	% SZS status Started for HL409850+4.p
174639.02/23119.05	% SZS status GaveUp for HL409850+4.p
174639.02/23119.05	eprover: CPU time limit exceeded, terminating
174639.02/23119.05	% SZS status Ended for HL409850+4.p
174642.48/23119.46	% SZS status Started for HL409845+5.p
174642.48/23119.46	% SZS status GaveUp for HL409845+5.p
174642.48/23119.46	eprover: CPU time limit exceeded, terminating
174642.48/23119.46	% SZS status Ended for HL409845+5.p
174649.36/23120.26	% SZS status Started for HL409850+5.p
174649.36/23120.26	% SZS status GaveUp for HL409850+5.p
174649.36/23120.26	eprover: CPU time limit exceeded, terminating
174649.36/23120.26	% SZS status Ended for HL409850+5.p
174653.95/23120.85	% SZS status Started for HL409851+4.p
174653.95/23120.85	% SZS status GaveUp for HL409851+4.p
174653.95/23120.85	eprover: CPU time limit exceeded, terminating
174653.95/23120.85	% SZS status Ended for HL409851+4.p
174655.53/23121.08	% SZS status Started for HL409846+5.p
174655.53/23121.08	% SZS status GaveUp for HL409846+5.p
174655.53/23121.08	eprover: CPU time limit exceeded, terminating
174655.53/23121.08	% SZS status Ended for HL409846+5.p
174660.47/23121.72	% SZS status Started for HL409851+5.p
174660.47/23121.72	% SZS status GaveUp for HL409851+5.p
174660.47/23121.72	eprover: CPU time limit exceeded, terminating
174660.47/23121.72	% SZS status Ended for HL409851+5.p
174664.08/23122.09	% SZS status Started for HL409852+4.p
174664.08/23122.09	% SZS status GaveUp for HL409852+4.p
174664.08/23122.09	eprover: CPU time limit exceeded, terminating
174664.08/23122.09	% SZS status Ended for HL409852+4.p
174667.03/23122.50	% SZS status Started for HL409852+5.p
174667.03/23122.50	% SZS status GaveUp for HL409852+5.p
174667.03/23122.50	eprover: CPU time limit exceeded, terminating
174667.03/23122.50	% SZS status Ended for HL409852+5.p
174669.03/23122.78	% SZS status Started for HL409847+5.p
174669.03/23122.78	% SZS status GaveUp for HL409847+5.p
174669.03/23122.78	eprover: CPU time limit exceeded, terminating
174669.03/23122.78	% SZS status Ended for HL409847+5.p
174673.23/23123.30	% SZS status Started for HL409854+4.p
174673.23/23123.30	% SZS status GaveUp for HL409854+4.p
174673.23/23123.30	eprover: CPU time limit exceeded, terminating
174673.23/23123.30	% SZS status Ended for HL409854+4.p
174679.16/23124.03	% SZS status Started for HL409854+5.p
174679.16/23124.03	% SZS status GaveUp for HL409854+5.p
174679.16/23124.03	eprover: CPU time limit exceeded, terminating
174679.16/23124.03	% SZS status Ended for HL409854+5.p
174679.75/23124.12	% SZS status Started for HL409855+4.p
174679.75/23124.12	% SZS status GaveUp for HL409855+4.p
174679.75/23124.12	eprover: CPU time limit exceeded, terminating
174679.75/23124.12	% SZS status Ended for HL409855+4.p
174681.75/23124.37	% SZS status Started for HL409848+5.p
174681.75/23124.37	% SZS status GaveUp for HL409848+5.p
174681.75/23124.37	eprover: CPU time limit exceeded, terminating
174681.75/23124.37	% SZS status Ended for HL409848+5.p
174685.11/23124.76	% SZS status Started for HL409855+5.p
174685.11/23124.76	% SZS status GaveUp for HL409855+5.p
174685.11/23124.76	eprover: CPU time limit exceeded, terminating
174685.11/23124.76	% SZS status Ended for HL409855+5.p
174687.70/23125.12	% SZS status Started for HL409856+4.p
174687.70/23125.12	% SZS status GaveUp for HL409856+4.p
174687.70/23125.12	eprover: CPU time limit exceeded, terminating
174687.70/23125.12	% SZS status Ended for HL409856+4.p
174691.19/23125.54	% SZS status Started for HL409856+5.p
174691.19/23125.54	% SZS status GaveUp for HL409856+5.p
174691.19/23125.54	eprover: CPU time limit exceeded, terminating
174691.19/23125.54	% SZS status Ended for HL409856+5.p
174693.28/23125.81	% SZS status Started for HL409858+4.p
174693.28/23125.81	% SZS status GaveUp for HL409858+4.p
174693.28/23125.81	eprover: CPU time limit exceeded, terminating
174693.28/23125.81	% SZS status Ended for HL409858+4.p
174697.83/23126.34	% SZS status Started for HL409858+5.p
174697.83/23126.34	% SZS status GaveUp for HL409858+5.p
174697.83/23126.34	eprover: CPU time limit exceeded, terminating
174697.83/23126.34	% SZS status Ended for HL409858+5.p
174704.28/23127.16	% SZS status Started for HL409859+5.p
174704.28/23127.16	% SZS status GaveUp for HL409859+5.p
174704.28/23127.16	eprover: CPU time limit exceeded, terminating
174704.28/23127.16	% SZS status Ended for HL409859+5.p
174704.28/23127.23	% SZS status Started for HL409859+4.p
174704.28/23127.23	% SZS status GaveUp for HL409859+4.p
174704.28/23127.23	eprover: CPU time limit exceeded, terminating
174704.28/23127.23	% SZS status Ended for HL409859+4.p
174705.70/23127.40	% SZS status Started for HL409860+4.p
174705.70/23127.40	% SZS status GaveUp for HL409860+4.p
174705.70/23127.40	eprover: CPU time limit exceeded, terminating
174705.70/23127.40	% SZS status Ended for HL409860+4.p
174708.88/23127.80	% SZS status Started for HL409860+5.p
174708.88/23127.80	% SZS status GaveUp for HL409860+5.p
174708.88/23127.80	eprover: CPU time limit exceeded, terminating
174708.88/23127.80	% SZS status Ended for HL409860+5.p
174712.25/23128.16	% SZS status Started for HL409864+4.p
174712.25/23128.16	% SZS status GaveUp for HL409864+4.p
174712.25/23128.16	eprover: CPU time limit exceeded, terminating
174712.25/23128.16	% SZS status Ended for HL409864+4.p
174715.59/23128.58	% SZS status Started for HL409864+5.p
174715.59/23128.58	% SZS status GaveUp for HL409864+5.p
174715.59/23128.58	eprover: CPU time limit exceeded, terminating
174715.59/23128.58	% SZS status Ended for HL409864+5.p
174717.22/23128.85	% SZS status Started for HL409865+4.p
174717.22/23128.85	% SZS status GaveUp for HL409865+4.p
174717.22/23128.85	eprover: CPU time limit exceeded, terminating
174717.22/23128.85	% SZS status Ended for HL409865+4.p
174721.56/23129.37	% SZS status Started for HL409865+5.p
174721.56/23129.37	% SZS status GaveUp for HL409865+5.p
174721.56/23129.37	eprover: CPU time limit exceeded, terminating
174721.56/23129.37	% SZS status Ended for HL409865+5.p
174728.31/23130.21	% SZS status Started for HL409867+4.p
174728.31/23130.21	% SZS status GaveUp for HL409867+4.p
174728.31/23130.21	eprover: CPU time limit exceeded, terminating
174728.31/23130.21	% SZS status Ended for HL409867+4.p
174728.73/23130.26	% SZS status Started for HL409867+5.p
174728.73/23130.26	% SZS status GaveUp for HL409867+5.p
174728.73/23130.26	eprover: CPU time limit exceeded, terminating
174728.73/23130.26	% SZS status Ended for HL409867+5.p
174730.59/23130.58	% SZS status Started for HL409868+4.p
174730.59/23130.58	% SZS status GaveUp for HL409868+4.p
174730.59/23130.58	eprover: CPU time limit exceeded, terminating
174730.59/23130.58	% SZS status Ended for HL409868+4.p
174733.09/23130.83	% SZS status Started for HL409868+5.p
174733.09/23130.83	% SZS status GaveUp for HL409868+5.p
174733.09/23130.83	eprover: CPU time limit exceeded, terminating
174733.09/23130.83	% SZS status Ended for HL409868+5.p
174736.00/23131.19	% SZS status Started for HL409869+4.p
174736.00/23131.19	% SZS status GaveUp for HL409869+4.p
174736.00/23131.19	eprover: CPU time limit exceeded, terminating
174736.00/23131.19	% SZS status Ended for HL409869+4.p
174739.25/23131.61	% SZS status Started for HL409869+5.p
174739.25/23131.61	% SZS status GaveUp for HL409869+5.p
174739.25/23131.61	eprover: CPU time limit exceeded, terminating
174739.25/23131.61	% SZS status Ended for HL409869+5.p
174741.81/23131.88	% SZS status Started for HL409870+4.p
174741.81/23131.88	% SZS status GaveUp for HL409870+4.p
174741.81/23131.88	eprover: CPU time limit exceeded, terminating
174741.81/23131.88	% SZS status Ended for HL409870+4.p
174745.66/23132.41	% SZS status Started for HL409870+5.p
174745.66/23132.41	% SZS status GaveUp for HL409870+5.p
174745.66/23132.41	eprover: CPU time limit exceeded, terminating
174745.66/23132.41	% SZS status Ended for HL409870+5.p
174752.36/23133.25	% SZS status Started for HL409871+4.p
174752.36/23133.25	% SZS status GaveUp for HL409871+4.p
174752.36/23133.25	eprover: CPU time limit exceeded, terminating
174752.36/23133.25	% SZS status Ended for HL409871+4.p
174752.77/23133.30	% SZS status Started for HL409871+5.p
174752.77/23133.30	% SZS status GaveUp for HL409871+5.p
174752.77/23133.30	eprover: CPU time limit exceeded, terminating
174752.77/23133.30	% SZS status Ended for HL409871+5.p
174755.33/23133.63	% SZS status Started for HL409872+4.p
174755.33/23133.63	% SZS status GaveUp for HL409872+4.p
174755.33/23133.63	eprover: CPU time limit exceeded, terminating
174755.33/23133.63	% SZS status Ended for HL409872+4.p
174757.53/23133.88	% SZS status Started for HL409872+5.p
174757.53/23133.88	% SZS status GaveUp for HL409872+5.p
174757.53/23133.88	eprover: CPU time limit exceeded, terminating
174757.53/23133.88	% SZS status Ended for HL409872+5.p
174760.53/23134.25	% SZS status Started for HL409873+4.p
174760.53/23134.25	% SZS status GaveUp for HL409873+4.p
174760.53/23134.25	eprover: CPU time limit exceeded, terminating
174760.53/23134.25	% SZS status Ended for HL409873+4.p
174765.09/23134.82	% SZS status Started for HL409873+5.p
174765.09/23134.82	% SZS status GaveUp for HL409873+5.p
174765.09/23134.82	eprover: CPU time limit exceeded, terminating
174765.09/23134.82	% SZS status Ended for HL409873+5.p
174765.47/23134.92	% SZS status Started for HL409875+4.p
174765.47/23134.92	% SZS status GaveUp for HL409875+4.p
174765.47/23134.92	eprover: CPU time limit exceeded, terminating
174765.47/23134.92	% SZS status Ended for HL409875+4.p
174769.84/23135.45	% SZS status Started for HL409875+5.p
174769.84/23135.45	% SZS status GaveUp for HL409875+5.p
174769.84/23135.45	eprover: CPU time limit exceeded, terminating
174769.84/23135.45	% SZS status Ended for HL409875+5.p
174776.59/23136.28	% SZS status Started for HL409876+4.p
174776.59/23136.28	% SZS status GaveUp for HL409876+4.p
174776.59/23136.28	eprover: CPU time limit exceeded, terminating
174776.59/23136.28	% SZS status Ended for HL409876+4.p
174776.59/23136.34	% SZS status Started for HL409876+5.p
174776.59/23136.34	% SZS status GaveUp for HL409876+5.p
174776.59/23136.34	eprover: CPU time limit exceeded, terminating
174776.59/23136.34	% SZS status Ended for HL409876+5.p
174779.11/23136.66	% SZS status Started for HL409878+4.p
174779.11/23136.66	% SZS status GaveUp for HL409878+4.p
174779.11/23136.66	eprover: CPU time limit exceeded, terminating
174779.11/23136.66	% SZS status Ended for HL409878+4.p
174781.62/23136.91	% SZS status Started for HL409878+5.p
174781.62/23136.91	% SZS status GaveUp for HL409878+5.p
174781.62/23136.91	eprover: CPU time limit exceeded, terminating
174781.62/23136.91	% SZS status Ended for HL409878+5.p
174785.52/23137.41	% SZS status Started for HL409879+4.p
174785.52/23137.41	% SZS status GaveUp for HL409879+4.p
174785.52/23137.41	eprover: CPU time limit exceeded, terminating
174785.52/23137.41	% SZS status Ended for HL409879+4.p
174788.69/23137.85	% SZS status Started for HL409879+5.p
174788.69/23137.85	% SZS status GaveUp for HL409879+5.p
174788.69/23137.85	eprover: CPU time limit exceeded, terminating
174788.69/23137.85	% SZS status Ended for HL409879+5.p
174792.27/23137.96	% SZS status Started for HL409880+4.p
174792.27/23137.96	% SZS status GaveUp for HL409880+4.p
174792.27/23137.96	eprover: CPU time limit exceeded, terminating
174792.27/23137.96	% SZS status Ended for HL409880+4.p
174795.36/23138.49	% SZS status Started for HL409880+5.p
174795.36/23138.49	% SZS status GaveUp for HL409880+5.p
174795.36/23138.49	eprover: CPU time limit exceeded, terminating
174795.36/23138.49	% SZS status Ended for HL409880+5.p
174803.22/23139.31	% SZS status Started for HL409881+4.p
174803.22/23139.31	% SZS status GaveUp for HL409881+4.p
174803.22/23139.31	eprover: CPU time limit exceeded, terminating
174803.22/23139.31	% SZS status Ended for HL409881+4.p
174803.31/23139.37	% SZS status Started for HL409881+5.p
174803.31/23139.37	% SZS status GaveUp for HL409881+5.p
174803.31/23139.37	eprover: CPU time limit exceeded, terminating
174803.31/23139.37	% SZS status Ended for HL409881+5.p
174805.91/23139.69	% SZS status Started for HL409883+4.p
174805.91/23139.69	% SZS status GaveUp for HL409883+4.p
174805.91/23139.69	eprover: CPU time limit exceeded, terminating
174805.91/23139.69	% SZS status Ended for HL409883+4.p
174808.66/23140.05	% SZS status Started for HL409883+5.p
174808.66/23140.05	% SZS status GaveUp for HL409883+5.p
174808.66/23140.05	eprover: CPU time limit exceeded, terminating
174808.66/23140.05	% SZS status Ended for HL409883+5.p
174812.05/23140.44	% SZS status Started for HL409884+4.p
174812.05/23140.44	% SZS status GaveUp for HL409884+4.p
174812.05/23140.44	eprover: CPU time limit exceeded, terminating
174812.05/23140.44	% SZS status Ended for HL409884+4.p
174815.53/23140.89	% SZS status Started for HL409884+5.p
174815.53/23140.89	% SZS status GaveUp for HL409884+5.p
174815.53/23140.89	eprover: CPU time limit exceeded, terminating
174815.53/23140.89	% SZS status Ended for HL409884+5.p
174816.16/23140.99	% SZS status Started for HL409885+4.p
174816.16/23140.99	% SZS status GaveUp for HL409885+4.p
174816.16/23140.99	eprover: CPU time limit exceeded, terminating
174816.16/23140.99	% SZS status Ended for HL409885+4.p
174820.16/23141.54	% SZS status Started for HL409885+5.p
174820.16/23141.54	% SZS status GaveUp for HL409885+5.p
174820.16/23141.54	eprover: CPU time limit exceeded, terminating
174820.16/23141.54	% SZS status Ended for HL409885+5.p
174827.12/23142.35	% SZS status Started for HL409886+4.p
174827.12/23142.35	% SZS status GaveUp for HL409886+4.p
174827.12/23142.35	eprover: CPU time limit exceeded, terminating
174827.12/23142.35	% SZS status Ended for HL409886+4.p
174827.12/23142.41	% SZS status Started for HL409886+5.p
174827.12/23142.41	% SZS status GaveUp for HL409886+5.p
174827.12/23142.41	eprover: CPU time limit exceeded, terminating
174827.12/23142.41	% SZS status Ended for HL409886+5.p
174829.98/23142.73	% SZS status Started for HL409887+4.p
174829.98/23142.73	% SZS status GaveUp for HL409887+4.p
174829.98/23142.73	eprover: CPU time limit exceeded, terminating
174829.98/23142.73	% SZS status Ended for HL409887+4.p
174832.80/23143.11	% SZS status Started for HL409887+5.p
174832.80/23143.11	% SZS status GaveUp for HL409887+5.p
174832.80/23143.11	eprover: CPU time limit exceeded, terminating
174832.80/23143.11	% SZS status Ended for HL409887+5.p
174836.03/23143.50	% SZS status Started for HL409888+4.p
174836.03/23143.50	% SZS status GaveUp for HL409888+4.p
174836.03/23143.50	eprover: CPU time limit exceeded, terminating
174836.03/23143.50	% SZS status Ended for HL409888+4.p
174839.31/23143.92	% SZS status Started for HL409888+5.p
174839.31/23143.92	% SZS status GaveUp for HL409888+5.p
174839.31/23143.92	eprover: CPU time limit exceeded, terminating
174839.31/23143.92	% SZS status Ended for HL409888+5.p
174840.84/23144.10	% SZS status Started for HL409889+4.p
174840.84/23144.10	% SZS status GaveUp for HL409889+4.p
174840.84/23144.10	eprover: CPU time limit exceeded, terminating
174840.84/23144.10	% SZS status Ended for HL409889+4.p
174844.91/23144.58	% SZS status Started for HL409889+5.p
174844.91/23144.58	% SZS status GaveUp for HL409889+5.p
174844.91/23144.58	eprover: CPU time limit exceeded, terminating
174844.91/23144.58	% SZS status Ended for HL409889+5.p
174851.41/23145.38	% SZS status Started for HL409891+4.p
174851.41/23145.38	% SZS status GaveUp for HL409891+4.p
174851.41/23145.38	eprover: CPU time limit exceeded, terminating
174851.41/23145.38	% SZS status Ended for HL409891+4.p
174852.33/23145.58	% SZS status Started for HL409891+5.p
174852.33/23145.58	% SZS status GaveUp for HL409891+5.p
174852.33/23145.58	eprover: CPU time limit exceeded, terminating
174852.33/23145.58	% SZS status Ended for HL409891+5.p
174853.72/23145.76	% SZS status Started for HL409892+4.p
174853.72/23145.76	% SZS status GaveUp for HL409892+4.p
174853.72/23145.76	eprover: CPU time limit exceeded, terminating
174853.72/23145.76	% SZS status Ended for HL409892+4.p
174857.22/23146.14	% SZS status Started for HL409892+5.p
174857.22/23146.14	% SZS status GaveUp for HL409892+5.p
174857.22/23146.14	eprover: CPU time limit exceeded, terminating
174857.22/23146.14	% SZS status Ended for HL409892+5.p
174860.62/23146.54	% SZS status Started for HL409894+4.p
174860.62/23146.54	% SZS status GaveUp for HL409894+4.p
174860.62/23146.54	eprover: CPU time limit exceeded, terminating
174860.62/23146.54	% SZS status Ended for HL409894+4.p
174863.55/23146.96	% SZS status Started for HL409894+5.p
174863.55/23146.96	% SZS status GaveUp for HL409894+5.p
174863.55/23146.96	eprover: CPU time limit exceeded, terminating
174863.55/23146.96	% SZS status Ended for HL409894+5.p
174865.19/23147.14	% SZS status Started for HL409895+4.p
174865.19/23147.14	% SZS status GaveUp for HL409895+4.p
174865.19/23147.14	eprover: CPU time limit exceeded, terminating
174865.19/23147.14	% SZS status Ended for HL409895+4.p
174868.94/23147.62	% SZS status Started for HL409895+5.p
174868.94/23147.62	% SZS status GaveUp for HL409895+5.p
174868.94/23147.62	eprover: CPU time limit exceeded, terminating
174868.94/23147.62	% SZS status Ended for HL409895+5.p
174875.20/23148.42	% SZS status Started for HL409897+4.p
174875.20/23148.42	% SZS status GaveUp for HL409897+4.p
174875.20/23148.42	eprover: CPU time limit exceeded, terminating
174875.20/23148.42	% SZS status Ended for HL409897+4.p
174876.45/23148.62	% SZS status Started for HL409897+5.p
174876.45/23148.62	% SZS status GaveUp for HL409897+5.p
174876.45/23148.62	eprover: CPU time limit exceeded, terminating
174876.45/23148.62	% SZS status Ended for HL409897+5.p
174878.77/23148.86	% SZS status Started for HL409898+4.p
174878.77/23148.86	% SZS status GaveUp for HL409898+4.p
174878.77/23148.86	eprover: CPU time limit exceeded, terminating
174878.77/23148.86	% SZS status Ended for HL409898+4.p
174880.91/23149.18	% SZS status Started for HL409898+5.p
174880.91/23149.18	% SZS status GaveUp for HL409898+5.p
174880.91/23149.18	eprover: CPU time limit exceeded, terminating
174880.91/23149.18	% SZS status Ended for HL409898+5.p
174884.22/23149.57	% SZS status Started for HL409899+4.p
174884.22/23149.57	% SZS status GaveUp for HL409899+4.p
174884.22/23149.57	eprover: CPU time limit exceeded, terminating
174884.22/23149.57	% SZS status Ended for HL409899+4.p
174889.12/23150.14	% SZS status Started for HL409899+5.p
174889.12/23150.14	% SZS status GaveUp for HL409899+5.p
174889.12/23150.14	eprover: CPU time limit exceeded, terminating
174889.12/23150.14	% SZS status Ended for HL409899+5.p
174889.12/23150.17	% SZS status Started for HL409900+4.p
174889.12/23150.17	% SZS status GaveUp for HL409900+4.p
174889.12/23150.17	eprover: CPU time limit exceeded, terminating
174889.12/23150.17	% SZS status Ended for HL409900+4.p
174893.25/23150.66	% SZS status Started for HL409900+5.p
174893.25/23150.66	% SZS status GaveUp for HL409900+5.p
174893.25/23150.66	eprover: CPU time limit exceeded, terminating
174893.25/23150.66	% SZS status Ended for HL409900+5.p
174899.28/23151.45	% SZS status Started for HL409901+4.p
174899.28/23151.45	% SZS status GaveUp for HL409901+4.p
174899.28/23151.45	eprover: CPU time limit exceeded, terminating
174899.28/23151.45	% SZS status Ended for HL409901+4.p
174900.98/23151.66	% SZS status Started for HL409901+5.p
174900.98/23151.66	% SZS status GaveUp for HL409901+5.p
174900.98/23151.66	eprover: CPU time limit exceeded, terminating
174900.98/23151.66	% SZS status Ended for HL409901+5.p
174902.36/23151.90	% SZS status Started for HL409902+4.p
174902.36/23151.90	% SZS status GaveUp for HL409902+4.p
174902.36/23151.90	eprover: CPU time limit exceeded, terminating
174902.36/23151.90	% SZS status Ended for HL409902+4.p
174905.62/23152.22	% SZS status Started for HL409902+5.p
174905.62/23152.22	% SZS status GaveUp for HL409902+5.p
174905.62/23152.22	eprover: CPU time limit exceeded, terminating
174905.62/23152.22	% SZS status Ended for HL409902+5.p
174907.83/23152.61	% SZS status Started for HL409904+4.p
174907.83/23152.61	% SZS status GaveUp for HL409904+4.p
174907.83/23152.61	eprover: CPU time limit exceeded, terminating
174907.83/23152.61	% SZS status Ended for HL409904+4.p
174912.25/23153.17	% SZS status Started for HL409904+5.p
174912.25/23153.17	% SZS status GaveUp for HL409904+5.p
174912.25/23153.17	eprover: CPU time limit exceeded, terminating
174912.25/23153.17	% SZS status Ended for HL409904+5.p
174913.78/23153.24	% SZS status Started for HL409905+4.p
174913.78/23153.24	% SZS status GaveUp for HL409905+4.p
174913.78/23153.24	eprover: CPU time limit exceeded, terminating
174913.78/23153.24	% SZS status Ended for HL409905+4.p
174916.95/23153.75	% SZS status Started for HL409905+5.p
174916.95/23153.75	% SZS status GaveUp for HL409905+5.p
174916.95/23153.75	eprover: CPU time limit exceeded, terminating
174916.95/23153.75	% SZS status Ended for HL409905+5.p
174923.84/23154.53	% SZS status Started for HL409906+4.p
174923.84/23154.53	% SZS status GaveUp for HL409906+4.p
174923.84/23154.53	eprover: CPU time limit exceeded, terminating
174923.84/23154.53	% SZS status Ended for HL409906+4.p
174925.28/23154.70	% SZS status Started for HL409906+5.p
174925.28/23154.70	% SZS status GaveUp for HL409906+5.p
174925.28/23154.70	eprover: CPU time limit exceeded, terminating
174925.28/23154.70	% SZS status Ended for HL409906+5.p
174926.69/23154.93	% SZS status Started for HL409907+4.p
174926.69/23154.93	% SZS status GaveUp for HL409907+4.p
174926.69/23154.93	eprover: CPU time limit exceeded, terminating
174926.69/23154.93	% SZS status Ended for HL409907+4.p
174929.55/23155.26	% SZS status Started for HL409907+5.p
174929.55/23155.26	% SZS status GaveUp for HL409907+5.p
174929.55/23155.26	eprover: CPU time limit exceeded, terminating
174929.55/23155.26	% SZS status Ended for HL409907+5.p
174933.97/23155.78	% SZS status Started for HL409908+4.p
174933.97/23155.78	% SZS status GaveUp for HL409908+4.p
174933.97/23155.78	eprover: CPU time limit exceeded, terminating
174933.97/23155.78	% SZS status Ended for HL409908+4.p
174937.17/23156.21	% SZS status Started for HL409908+5.p
174937.17/23156.21	% SZS status GaveUp for HL409908+5.p
174937.17/23156.21	eprover: CPU time limit exceeded, terminating
174937.17/23156.21	% SZS status Ended for HL409908+5.p
174937.17/23156.27	% SZS status Started for HL409909+4.p
174937.17/23156.27	% SZS status GaveUp for HL409909+4.p
174937.17/23156.27	eprover: CPU time limit exceeded, terminating
174937.17/23156.27	% SZS status Ended for HL409909+4.p
174941.64/23156.79	% SZS status Started for HL409909+5.p
174941.64/23156.79	% SZS status GaveUp for HL409909+5.p
174941.64/23156.79	eprover: CPU time limit exceeded, terminating
174941.64/23156.79	% SZS status Ended for HL409909+5.p
174948.12/23157.56	% SZS status Started for HL409910+4.p
174948.12/23157.56	% SZS status GaveUp for HL409910+4.p
174948.12/23157.56	eprover: CPU time limit exceeded, terminating
174948.12/23157.56	% SZS status Ended for HL409910+4.p
174948.95/23157.74	% SZS status Started for HL409910+5.p
174948.95/23157.74	% SZS status GaveUp for HL409910+5.p
174948.95/23157.74	eprover: CPU time limit exceeded, terminating
174948.95/23157.74	% SZS status Ended for HL409910+5.p
174951.22/23157.96	% SZS status Started for HL409911+4.p
174951.22/23157.96	% SZS status GaveUp for HL409911+4.p
174951.22/23157.96	eprover: CPU time limit exceeded, terminating
174951.22/23157.96	% SZS status Ended for HL409911+4.p
174954.25/23158.40	% SZS status Started for HL409911+5.p
174954.25/23158.40	% SZS status GaveUp for HL409911+5.p
174954.25/23158.40	eprover: CPU time limit exceeded, terminating
174954.25/23158.40	% SZS status Ended for HL409911+5.p
174957.81/23158.82	% SZS status Started for HL409912+4.p
174957.81/23158.82	% SZS status GaveUp for HL409912+4.p
174957.81/23158.82	eprover: CPU time limit exceeded, terminating
174957.81/23158.82	% SZS status Ended for HL409912+4.p
174961.38/23159.24	% SZS status Started for HL409912+5.p
174961.38/23159.24	% SZS status GaveUp for HL409912+5.p
174961.38/23159.24	eprover: CPU time limit exceeded, terminating
174961.38/23159.24	% SZS status Ended for HL409912+5.p
174961.56/23159.30	% SZS status Started for HL409913+4.p
174961.56/23159.30	% SZS status GaveUp for HL409913+4.p
174961.56/23159.30	eprover: CPU time limit exceeded, terminating
174961.56/23159.30	% SZS status Ended for HL409913+4.p
174965.78/23159.83	% SZS status Started for HL409913+5.p
174965.78/23159.83	% SZS status GaveUp for HL409913+5.p
174965.78/23159.83	eprover: CPU time limit exceeded, terminating
174965.78/23159.83	% SZS status Ended for HL409913+5.p
174971.91/23160.60	% SZS status Started for HL409914+4.p
174971.91/23160.60	% SZS status GaveUp for HL409914+4.p
174971.91/23160.60	eprover: CPU time limit exceeded, terminating
174971.91/23160.60	% SZS status Ended for HL409914+4.p
174973.33/23160.78	% SZS status Started for HL409914+5.p
174973.33/23160.78	% SZS status GaveUp for HL409914+5.p
174973.33/23160.78	eprover: CPU time limit exceeded, terminating
174973.33/23160.78	% SZS status Ended for HL409914+5.p
174978.28/23161.12	% SZS status Started for HL409915+4.p
174978.28/23161.12	% SZS status GaveUp for HL409915+4.p
174978.28/23161.12	eprover: CPU time limit exceeded, terminating
174978.28/23161.12	% SZS status Ended for HL409915+4.p
174981.08/23161.44	% SZS status Started for HL409915+5.p
174981.08/23161.44	% SZS status GaveUp for HL409915+5.p
174981.08/23161.44	eprover: CPU time limit exceeded, terminating
174981.08/23161.44	% SZS status Ended for HL409915+5.p
174984.77/23161.86	% SZS status Started for HL409917+4.p
174984.77/23161.86	% SZS status GaveUp for HL409917+4.p
174984.77/23161.86	eprover: CPU time limit exceeded, terminating
174984.77/23161.86	% SZS status Ended for HL409917+4.p
174987.48/23162.27	% SZS status Started for HL409917+5.p
174987.48/23162.27	% SZS status GaveUp for HL409917+5.p
174987.48/23162.27	eprover: CPU time limit exceeded, terminating
174987.48/23162.27	% SZS status Ended for HL409917+5.p
174987.97/23162.34	% SZS status Started for HL409918+4.p
174987.97/23162.34	% SZS status GaveUp for HL409918+4.p
174987.97/23162.34	eprover: CPU time limit exceeded, terminating
174987.97/23162.34	% SZS status Ended for HL409918+4.p
174992.83/23162.87	% SZS status Started for HL409918+5.p
174992.83/23162.87	% SZS status GaveUp for HL409918+5.p
174992.83/23162.87	eprover: CPU time limit exceeded, terminating
174992.83/23162.87	% SZS status Ended for HL409918+5.p
174998.59/23163.63	% SZS status Started for HL409919+4.p
174998.59/23163.63	% SZS status GaveUp for HL409919+4.p
174998.59/23163.63	eprover: CPU time limit exceeded, terminating
174998.59/23163.63	% SZS status Ended for HL409919+4.p
175001.00/23163.94	% SZS status Started for HL409919+5.p
175001.00/23163.94	% SZS status GaveUp for HL409919+5.p
175001.00/23163.94	eprover: CPU time limit exceeded, terminating
175001.00/23163.94	% SZS status Ended for HL409919+5.p
175002.28/23164.15	% SZS status Started for HL409920+4.p
175002.28/23164.15	% SZS status GaveUp for HL409920+4.p
175002.28/23164.15	eprover: CPU time limit exceeded, terminating
175002.28/23164.15	% SZS status Ended for HL409920+4.p
175005.23/23164.47	% SZS status Started for HL409920+5.p
175005.23/23164.47	% SZS status GaveUp for HL409920+5.p
175005.23/23164.47	eprover: CPU time limit exceeded, terminating
175005.23/23164.47	% SZS status Ended for HL409920+5.p
175008.86/23164.89	% SZS status Started for HL409921+4.p
175008.86/23164.89	% SZS status GaveUp for HL409921+4.p
175008.86/23164.89	eprover: CPU time limit exceeded, terminating
175008.86/23164.89	% SZS status Ended for HL409921+4.p
175011.86/23165.31	% SZS status Started for HL409921+5.p
175011.86/23165.31	% SZS status GaveUp for HL409921+5.p
175011.86/23165.31	eprover: CPU time limit exceeded, terminating
175011.86/23165.31	% SZS status Ended for HL409921+5.p
175012.48/23165.38	% SZS status Started for HL409922+4.p
175012.48/23165.38	% SZS status GaveUp for HL409922+4.p
175012.48/23165.38	eprover: CPU time limit exceeded, terminating
175012.48/23165.38	% SZS status Ended for HL409922+4.p
175015.64/23165.91	% SZS status Started for HL409922+5.p
175015.64/23165.91	% SZS status GaveUp for HL409922+5.p
175015.64/23165.91	eprover: CPU time limit exceeded, terminating
175015.64/23165.91	% SZS status Ended for HL409922+5.p
175024.89/23166.70	% SZS status Started for HL409923+4.p
175024.89/23166.70	% SZS status GaveUp for HL409923+4.p
175024.89/23166.70	eprover: CPU time limit exceeded, terminating
175024.89/23166.70	% SZS status Ended for HL409923+4.p
175026.81/23166.97	% SZS status Started for HL409923+5.p
175026.81/23166.97	% SZS status GaveUp for HL409923+5.p
175026.81/23166.97	eprover: CPU time limit exceeded, terminating
175026.81/23166.97	% SZS status Ended for HL409923+5.p
175029.41/23167.30	% SZS status Started for HL409925+4.p
175029.41/23167.30	% SZS status GaveUp for HL409925+4.p
175029.41/23167.30	eprover: CPU time limit exceeded, terminating
175029.41/23167.30	% SZS status Ended for HL409925+4.p
175031.47/23167.55	% SZS status Started for HL409925+5.p
175031.47/23167.55	% SZS status GaveUp for HL409925+5.p
175031.47/23167.55	eprover: CPU time limit exceeded, terminating
175031.47/23167.55	% SZS status Ended for HL409925+5.p
175034.17/23167.93	% SZS status Started for HL409927+4.p
175034.17/23167.93	% SZS status GaveUp for HL409927+4.p
175034.17/23167.93	eprover: CPU time limit exceeded, terminating
175034.17/23167.93	% SZS status Ended for HL409927+4.p
175037.70/23168.34	% SZS status Started for HL409927+5.p
175037.70/23168.34	% SZS status GaveUp for HL409927+5.p
175037.70/23168.34	eprover: CPU time limit exceeded, terminating
175037.70/23168.34	% SZS status Ended for HL409927+5.p
175037.98/23168.41	% SZS status Started for HL409929+4.p
175037.98/23168.41	% SZS status GaveUp for HL409929+4.p
175037.98/23168.41	eprover: CPU time limit exceeded, terminating
175037.98/23168.41	% SZS status Ended for HL409929+4.p
175042.72/23168.95	% SZS status Started for HL409929+5.p
175042.72/23168.95	% SZS status GaveUp for HL409929+5.p
175042.72/23168.95	eprover: CPU time limit exceeded, terminating
175042.72/23168.95	% SZS status Ended for HL409929+5.p
175048.89/23169.73	% SZS status Started for HL409930+4.p
175048.89/23169.73	% SZS status GaveUp for HL409930+4.p
175048.89/23169.73	eprover: CPU time limit exceeded, terminating
175048.89/23169.73	% SZS status Ended for HL409930+4.p
175051.14/23170.01	% SZS status Started for HL409930+5.p
175051.14/23170.01	% SZS status GaveUp for HL409930+5.p
175051.14/23170.01	eprover: CPU time limit exceeded, terminating
175051.14/23170.01	% SZS status Ended for HL409930+5.p
175053.28/23170.33	% SZS status Started for HL409931+4.p
175053.28/23170.33	% SZS status GaveUp for HL409931+4.p
175053.28/23170.33	eprover: CPU time limit exceeded, terminating
175053.28/23170.33	% SZS status Ended for HL409931+4.p
175055.88/23170.61	% SZS status Started for HL409931+5.p
175055.88/23170.61	% SZS status GaveUp for HL409931+5.p
175055.88/23170.61	eprover: CPU time limit exceeded, terminating
175055.88/23170.61	% SZS status Ended for HL409931+5.p
175060.02/23171.12	% SZS status Started for HL409932+4.p
175060.02/23171.12	% SZS status GaveUp for HL409932+4.p
175060.02/23171.12	eprover: CPU time limit exceeded, terminating
175060.02/23171.12	% SZS status Ended for HL409932+4.p
175061.73/23171.37	% SZS status Started for HL409932+5.p
175061.73/23171.37	% SZS status GaveUp for HL409932+5.p
175061.73/23171.37	eprover: CPU time limit exceeded, terminating
175061.73/23171.37	% SZS status Ended for HL409932+5.p
175062.16/23171.45	% SZS status Started for HL409933+4.p
175062.16/23171.45	% SZS status GaveUp for HL409933+4.p
175062.16/23171.45	eprover: CPU time limit exceeded, terminating
175062.16/23171.45	% SZS status Ended for HL409933+4.p
175066.52/23171.99	% SZS status Started for HL409933+5.p
175066.52/23171.99	% SZS status GaveUp for HL409933+5.p
175066.52/23171.99	eprover: CPU time limit exceeded, terminating
175066.52/23171.99	% SZS status Ended for HL409933+5.p
175072.88/23172.77	% SZS status Started for HL409934+4.p
175072.88/23172.77	% SZS status GaveUp for HL409934+4.p
175072.88/23172.77	eprover: CPU time limit exceeded, terminating
175072.88/23172.77	% SZS status Ended for HL409934+4.p
175074.88/23173.06	% SZS status Started for HL409934+5.p
175074.88/23173.06	% SZS status GaveUp for HL409934+5.p
175074.88/23173.06	eprover: CPU time limit exceeded, terminating
175074.88/23173.06	% SZS status Ended for HL409934+5.p
175077.67/23173.37	% SZS status Started for HL409935+4.p
175077.67/23173.37	% SZS status GaveUp for HL409935+4.p
175077.67/23173.37	eprover: CPU time limit exceeded, terminating
175077.67/23173.37	% SZS status Ended for HL409935+4.p
175079.66/23173.65	% SZS status Started for HL409935+5.p
175079.66/23173.65	% SZS status GaveUp for HL409935+5.p
175079.66/23173.65	eprover: CPU time limit exceeded, terminating
175079.66/23173.65	% SZS status Ended for HL409935+5.p
175084.56/23174.23	% SZS status Started for HL409936+4.p
175084.56/23174.23	% SZS status GaveUp for HL409936+4.p
175084.56/23174.23	eprover: CPU time limit exceeded, terminating
175084.56/23174.23	% SZS status Ended for HL409936+4.p
175085.86/23174.41	% SZS status Started for HL409936+5.p
175085.86/23174.41	% SZS status GaveUp for HL409936+5.p
175085.86/23174.41	eprover: CPU time limit exceeded, terminating
175085.86/23174.41	% SZS status Ended for HL409936+5.p
175086.36/23174.48	% SZS status Started for HL409938+4.p
175086.36/23174.48	% SZS status GaveUp for HL409938+4.p
175086.36/23174.48	eprover: CPU time limit exceeded, terminating
175086.36/23174.48	% SZS status Ended for HL409938+4.p
175092.77/23175.03	% SZS status Started for HL409938+5.p
175092.77/23175.03	% SZS status GaveUp for HL409938+5.p
175092.77/23175.03	eprover: CPU time limit exceeded, terminating
175092.77/23175.03	% SZS status Ended for HL409938+5.p
175100.52/23175.91	% SZS status Started for HL409939+4.p
175100.52/23175.91	% SZS status GaveUp for HL409939+4.p
175100.52/23175.91	eprover: CPU time limit exceeded, terminating
175100.52/23175.91	% SZS status Ended for HL409939+4.p
175101.69/23176.09	% SZS status Started for HL409939+5.p
175101.69/23176.09	% SZS status GaveUp for HL409939+5.p
175101.69/23176.09	eprover: CPU time limit exceeded, terminating
175101.69/23176.09	% SZS status Ended for HL409939+5.p
175103.91/23176.40	% SZS status Started for HL409940+4.p
175103.91/23176.40	% SZS status GaveUp for HL409940+4.p
175103.91/23176.40	eprover: CPU time limit exceeded, terminating
175103.91/23176.40	% SZS status Ended for HL409940+4.p
175106.12/23176.68	% SZS status Started for HL409940+5.p
175106.12/23176.68	% SZS status GaveUp for HL409940+5.p
175106.12/23176.68	eprover: CPU time limit exceeded, terminating
175106.12/23176.68	% SZS status Ended for HL409940+5.p
175110.97/23177.27	% SZS status Started for HL409941+4.p
175110.97/23177.27	% SZS status GaveUp for HL409941+4.p
175110.97/23177.27	eprover: CPU time limit exceeded, terminating
175110.97/23177.27	% SZS status Ended for HL409941+4.p
175112.83/23177.45	% SZS status Started for HL409941+5.p
175112.83/23177.45	% SZS status GaveUp for HL409941+5.p
175112.83/23177.45	eprover: CPU time limit exceeded, terminating
175112.83/23177.45	% SZS status Ended for HL409941+5.p
175113.34/23177.52	% SZS status Started for HL409942+4.p
175113.34/23177.52	% SZS status GaveUp for HL409942+4.p
175113.34/23177.52	eprover: CPU time limit exceeded, terminating
175113.34/23177.52	% SZS status Ended for HL409942+4.p
175118.39/23178.18	% SZS status Started for HL409942+5.p
175118.39/23178.18	% SZS status GaveUp for HL409942+5.p
175118.39/23178.18	eprover: CPU time limit exceeded, terminating
175118.39/23178.18	% SZS status Ended for HL409942+5.p
175124.75/23178.94	% SZS status Started for HL409944+4.p
175124.75/23178.94	% SZS status GaveUp for HL409944+4.p
175124.75/23178.94	eprover: CPU time limit exceeded, terminating
175124.75/23178.94	% SZS status Ended for HL409944+4.p
175125.83/23179.13	% SZS status Started for HL409944+5.p
175125.83/23179.13	% SZS status GaveUp for HL409944+5.p
175125.83/23179.13	eprover: CPU time limit exceeded, terminating
175125.83/23179.13	% SZS status Ended for HL409944+5.p
175128.12/23179.43	% SZS status Started for HL409945+4.p
175128.12/23179.43	% SZS status GaveUp for HL409945+4.p
175128.12/23179.43	eprover: CPU time limit exceeded, terminating
175128.12/23179.43	% SZS status Ended for HL409945+4.p
175130.91/23179.72	% SZS status Started for HL409945+5.p
175130.91/23179.72	% SZS status GaveUp for HL409945+5.p
175130.91/23179.72	eprover: CPU time limit exceeded, terminating
175130.91/23179.72	% SZS status Ended for HL409945+5.p
175134.39/23180.30	% SZS status Started for HL409946+4.p
175134.39/23180.30	% SZS status GaveUp for HL409946+4.p
175134.39/23180.30	eprover: CPU time limit exceeded, terminating
175134.39/23180.30	% SZS status Ended for HL409946+4.p
175136.44/23180.56	% SZS status Started for HL409948+4.p
175136.44/23180.56	% SZS status GaveUp for HL409948+4.p
175136.44/23180.56	eprover: CPU time limit exceeded, terminating
175136.44/23180.56	% SZS status Ended for HL409948+4.p
175138.39/23180.79	% SZS status Started for HL409946+5.p
175138.39/23180.79	% SZS status GaveUp for HL409946+5.p
175138.39/23180.79	eprover: CPU time limit exceeded, terminating
175138.39/23180.79	% SZS status Ended for HL409946+5.p
175142.22/23181.22	% SZS status Started for HL409948+5.p
175142.22/23181.22	% SZS status GaveUp for HL409948+5.p
175142.22/23181.22	eprover: CPU time limit exceeded, terminating
175142.22/23181.22	% SZS status Ended for HL409948+5.p
175148.05/23181.98	% SZS status Started for HL409949+4.p
175148.05/23181.98	% SZS status GaveUp for HL409949+4.p
175148.05/23181.98	eprover: CPU time limit exceeded, terminating
175148.05/23181.98	% SZS status Ended for HL409949+4.p
175149.81/23182.17	% SZS status Started for HL409949+5.p
175149.81/23182.17	% SZS status GaveUp for HL409949+5.p
175149.81/23182.17	eprover: CPU time limit exceeded, terminating
175149.81/23182.17	% SZS status Ended for HL409949+5.p
175151.95/23182.48	% SZS status Started for HL409950+4.p
175151.95/23182.48	% SZS status GaveUp for HL409950+4.p
175151.95/23182.48	eprover: CPU time limit exceeded, terminating
175151.95/23182.48	% SZS status Ended for HL409950+4.p
175157.59/23183.13	% SZS status Started for HL409950+5.p
175157.59/23183.13	% SZS status GaveUp for HL409950+5.p
175157.59/23183.13	eprover: CPU time limit exceeded, terminating
175157.59/23183.13	% SZS status Ended for HL409950+5.p
175159.14/23183.34	% SZS status Started for HL409951+4.p
175159.14/23183.34	% SZS status GaveUp for HL409951+4.p
175159.14/23183.34	eprover: CPU time limit exceeded, terminating
175159.14/23183.34	% SZS status Ended for HL409951+4.p
175160.97/23183.60	% SZS status Started for HL409951+5.p
175160.97/23183.60	% SZS status GaveUp for HL409951+5.p
175160.97/23183.60	eprover: CPU time limit exceeded, terminating
175160.97/23183.60	% SZS status Ended for HL409951+5.p
175162.89/23183.83	% SZS status Started for HL409952+4.p
175162.89/23183.83	% SZS status GaveUp for HL409952+4.p
175162.89/23183.83	eprover: CPU time limit exceeded, terminating
175162.89/23183.83	% SZS status Ended for HL409952+4.p
175165.67/23184.26	% SZS status Started for HL409952+5.p
175165.67/23184.26	% SZS status GaveUp for HL409952+5.p
175165.67/23184.26	eprover: CPU time limit exceeded, terminating
175165.67/23184.26	% SZS status Ended for HL409952+5.p
175172.14/23185.01	% SZS status Started for HL409953+4.p
175172.14/23185.01	% SZS status GaveUp for HL409953+4.p
175172.14/23185.01	eprover: CPU time limit exceeded, terminating
175172.14/23185.01	% SZS status Ended for HL409953+4.p
175173.62/23185.21	% SZS status Started for HL409953+5.p
175173.62/23185.21	% SZS status GaveUp for HL409953+5.p
175173.62/23185.21	eprover: CPU time limit exceeded, terminating
175173.62/23185.21	% SZS status Ended for HL409953+5.p
175176.33/23185.51	% SZS status Started for HL409954+4.p
175176.33/23185.51	% SZS status GaveUp for HL409954+4.p
175176.33/23185.51	eprover: CPU time limit exceeded, terminating
175176.33/23185.51	% SZS status Ended for HL409954+4.p
175182.67/23186.32	% SZS status Started for HL409954+5.p
175182.67/23186.32	% SZS status GaveUp for HL409954+5.p
175182.67/23186.32	eprover: CPU time limit exceeded, terminating
175182.67/23186.32	% SZS status Ended for HL409954+5.p
175183.20/23186.38	% SZS status Started for HL409955+4.p
175183.20/23186.38	% SZS status GaveUp for HL409955+4.p
175183.20/23186.38	eprover: CPU time limit exceeded, terminating
175183.20/23186.38	% SZS status Ended for HL409955+4.p
175185.25/23186.63	% SZS status Started for HL409955+5.p
175185.25/23186.63	% SZS status GaveUp for HL409955+5.p
175185.25/23186.63	eprover: CPU time limit exceeded, terminating
175185.25/23186.63	% SZS status Ended for HL409955+5.p
175186.73/23186.86	% SZS status Started for HL409956+4.p
175186.73/23186.86	% SZS status GaveUp for HL409956+4.p
175186.73/23186.86	eprover: CPU time limit exceeded, terminating
175186.73/23186.86	% SZS status Ended for HL409956+4.p
175190.72/23187.30	% SZS status Started for HL409956+5.p
175190.72/23187.30	% SZS status GaveUp for HL409956+5.p
175190.72/23187.30	eprover: CPU time limit exceeded, terminating
175190.72/23187.30	% SZS status Ended for HL409956+5.p
175195.91/23188.05	% SZS status Started for HL409957+4.p
175195.91/23188.05	% SZS status GaveUp for HL409957+4.p
175195.91/23188.05	eprover: CPU time limit exceeded, terminating
175195.91/23188.05	% SZS status Ended for HL409957+4.p
175197.75/23188.24	% SZS status Started for HL409957+5.p
175197.75/23188.24	% SZS status GaveUp for HL409957+5.p
175197.75/23188.24	eprover: CPU time limit exceeded, terminating
175197.75/23188.24	% SZS status Ended for HL409957+5.p
175201.45/23188.66	% SZS status Started for HL409958+4.p
175201.45/23188.66	% SZS status GaveUp for HL409958+4.p
175201.45/23188.66	eprover: CPU time limit exceeded, terminating
175201.45/23188.66	% SZS status Ended for HL409958+4.p
175206.98/23189.35	% SZS status Started for HL409958+5.p
175206.98/23189.35	% SZS status GaveUp for HL409958+5.p
175206.98/23189.35	eprover: CPU time limit exceeded, terminating
175206.98/23189.35	% SZS status Ended for HL409958+5.p
175207.53/23189.42	% SZS status Started for HL409960+4.p
175207.53/23189.42	% SZS status GaveUp for HL409960+4.p
175207.53/23189.42	eprover: CPU time limit exceeded, terminating
175207.53/23189.42	% SZS status Ended for HL409960+4.p
175209.34/23189.67	% SZS status Started for HL409960+5.p
175209.34/23189.67	% SZS status GaveUp for HL409960+5.p
175209.34/23189.67	eprover: CPU time limit exceeded, terminating
175209.34/23189.67	% SZS status Ended for HL409960+5.p
175210.92/23189.90	% SZS status Started for HL409961+4.p
175210.92/23189.90	% SZS status GaveUp for HL409961+4.p
175210.92/23189.90	eprover: CPU time limit exceeded, terminating
175210.92/23189.90	% SZS status Ended for HL409961+4.p
175214.69/23190.34	% SZS status Started for HL409961+5.p
175214.69/23190.34	% SZS status GaveUp for HL409961+5.p
175214.69/23190.34	eprover: CPU time limit exceeded, terminating
175214.69/23190.34	% SZS status Ended for HL409961+5.p
175220.25/23191.09	% SZS status Started for HL409962+4.p
175220.25/23191.09	% SZS status GaveUp for HL409962+4.p
175220.25/23191.09	eprover: CPU time limit exceeded, terminating
175220.25/23191.09	% SZS status Ended for HL409962+4.p
175222.89/23191.39	% SZS status Started for HL409962+5.p
175222.89/23191.39	% SZS status GaveUp for HL409962+5.p
175222.89/23191.39	eprover: CPU time limit exceeded, terminating
175222.89/23191.39	% SZS status Ended for HL409962+5.p
175225.17/23191.70	% SZS status Started for HL409964+4.p
175225.17/23191.70	% SZS status GaveUp for HL409964+4.p
175225.17/23191.70	eprover: CPU time limit exceeded, terminating
175225.17/23191.70	% SZS status Ended for HL409964+4.p
175231.08/23192.39	% SZS status Started for HL409964+5.p
175231.08/23192.39	% SZS status GaveUp for HL409964+5.p
175231.08/23192.39	eprover: CPU time limit exceeded, terminating
175231.08/23192.39	% SZS status Ended for HL409964+5.p
175231.72/23192.49	% SZS status Started for HL409965+4.p
175231.72/23192.49	% SZS status GaveUp for HL409965+4.p
175231.72/23192.49	eprover: CPU time limit exceeded, terminating
175231.72/23192.49	% SZS status Ended for HL409965+4.p
175233.06/23192.71	% SZS status Started for HL409965+5.p
175233.06/23192.71	% SZS status GaveUp for HL409965+5.p
175233.06/23192.71	eprover: CPU time limit exceeded, terminating
175233.06/23192.71	% SZS status Ended for HL409965+5.p
175235.33/23192.94	% SZS status Started for HL409966+4.p
175235.33/23192.94	% SZS status GaveUp for HL409966+4.p
175235.33/23192.94	eprover: CPU time limit exceeded, terminating
175235.33/23192.94	% SZS status Ended for HL409966+4.p
175238.92/23193.37	% SZS status Started for HL409966+5.p
175238.92/23193.37	% SZS status GaveUp for HL409966+5.p
175238.92/23193.37	eprover: CPU time limit exceeded, terminating
175238.92/23193.37	% SZS status Ended for HL409966+5.p
175244.80/23194.14	% SZS status Started for HL409967+4.p
175244.80/23194.14	% SZS status GaveUp for HL409967+4.p
175244.80/23194.14	eprover: CPU time limit exceeded, terminating
175244.80/23194.14	% SZS status Ended for HL409967+4.p
175247.38/23194.44	% SZS status Started for HL409967+5.p
175247.38/23194.44	% SZS status GaveUp for HL409967+5.p
175247.38/23194.44	eprover: CPU time limit exceeded, terminating
175247.38/23194.44	% SZS status Ended for HL409967+5.p
175249.25/23194.73	% SZS status Started for HL409968+4.p
175249.25/23194.73	% SZS status GaveUp for HL409968+4.p
175249.25/23194.73	eprover: CPU time limit exceeded, terminating
175249.25/23194.73	% SZS status Ended for HL409968+4.p
175255.69/23195.53	% SZS status Started for HL409969+4.p
175255.69/23195.53	% SZS status GaveUp for HL409969+4.p
175255.69/23195.53	eprover: CPU time limit exceeded, terminating
175255.69/23195.53	% SZS status Ended for HL409969+4.p
175255.69/23195.55	% SZS status Started for HL409968+5.p
175255.69/23195.55	% SZS status GaveUp for HL409968+5.p
175255.69/23195.55	eprover: CPU time limit exceeded, terminating
175255.69/23195.55	% SZS status Ended for HL409968+5.p
175257.41/23195.75	% SZS status Started for HL409969+5.p
175257.41/23195.75	% SZS status GaveUp for HL409969+5.p
175257.41/23195.75	eprover: CPU time limit exceeded, terminating
175257.41/23195.75	% SZS status Ended for HL409969+5.p
175258.19/23195.97	% SZS status Started for HL409970+4.p
175258.19/23195.97	% SZS status GaveUp for HL409970+4.p
175258.19/23195.97	eprover: CPU time limit exceeded, terminating
175258.19/23195.97	% SZS status Ended for HL409970+4.p
175262.30/23196.41	% SZS status Started for HL409970+5.p
175262.30/23196.41	% SZS status GaveUp for HL409970+5.p
175262.30/23196.41	eprover: CPU time limit exceeded, terminating
175262.30/23196.41	% SZS status Ended for HL409970+5.p
175268.44/23197.17	% SZS status Started for HL409972+4.p
175268.44/23197.17	% SZS status GaveUp for HL409972+4.p
175268.44/23197.17	eprover: CPU time limit exceeded, terminating
175268.44/23197.17	% SZS status Ended for HL409972+4.p
175271.36/23197.48	% SZS status Started for HL409972+5.p
175271.36/23197.48	% SZS status GaveUp for HL409972+5.p
175271.36/23197.48	eprover: CPU time limit exceeded, terminating
175271.36/23197.48	% SZS status Ended for HL409972+5.p
175273.52/23197.77	% SZS status Started for HL409973+4.p
175273.52/23197.77	% SZS status GaveUp for HL409973+4.p
175273.52/23197.77	eprover: CPU time limit exceeded, terminating
175273.52/23197.77	% SZS status Ended for HL409973+4.p
175279.80/23198.56	% SZS status Started for HL409973+5.p
175279.80/23198.56	% SZS status GaveUp for HL409973+5.p
175279.80/23198.56	eprover: CPU time limit exceeded, terminating
175279.80/23198.56	% SZS status Ended for HL409973+5.p
175280.47/23198.60	% SZS status Started for HL409974+4.p
175280.47/23198.60	% SZS status GaveUp for HL409974+4.p
175280.47/23198.60	eprover: CPU time limit exceeded, terminating
175280.47/23198.60	% SZS status Ended for HL409974+4.p
175281.28/23198.78	% SZS status Started for HL409974+5.p
175281.28/23198.78	% SZS status GaveUp for HL409974+5.p
175281.28/23198.78	eprover: CPU time limit exceeded, terminating
175281.28/23198.78	% SZS status Ended for HL409974+5.p
175283.81/23199.03	% SZS status Started for HL409975+4.p
175283.81/23199.03	% SZS status GaveUp for HL409975+4.p
175283.81/23199.03	eprover: CPU time limit exceeded, terminating
175283.81/23199.03	% SZS status Ended for HL409975+4.p
175288.41/23199.60	% SZS status Started for HL409975+5.p
175288.41/23199.60	% SZS status GaveUp for HL409975+5.p
175288.41/23199.60	eprover: CPU time limit exceeded, terminating
175288.41/23199.60	% SZS status Ended for HL409975+5.p
175293.16/23200.20	% SZS status Started for HL409976+4.p
175293.16/23200.20	% SZS status GaveUp for HL409976+4.p
175293.16/23200.20	eprover: CPU time limit exceeded, terminating
175293.16/23200.20	% SZS status Ended for HL409976+4.p
175295.30/23200.51	% SZS status Started for HL409976+5.p
175295.30/23200.51	% SZS status GaveUp for HL409976+5.p
175295.30/23200.51	eprover: CPU time limit exceeded, terminating
175295.30/23200.51	% SZS status Ended for HL409976+5.p
175297.84/23200.81	% SZS status Started for HL409977+4.p
175297.84/23200.81	% SZS status GaveUp for HL409977+4.p
175297.84/23200.81	eprover: CPU time limit exceeded, terminating
175297.84/23200.81	% SZS status Ended for HL409977+4.p
175304.34/23201.60	% SZS status Started for HL409977+5.p
175304.34/23201.60	% SZS status GaveUp for HL409977+5.p
175304.34/23201.60	eprover: CPU time limit exceeded, terminating
175304.34/23201.60	% SZS status Ended for HL409977+5.p
175304.34/23201.64	% SZS status Started for HL409978+4.p
175304.34/23201.64	% SZS status GaveUp for HL409978+4.p
175304.34/23201.64	eprover: CPU time limit exceeded, terminating
175304.34/23201.64	% SZS status Ended for HL409978+4.p
175305.75/23201.82	% SZS status Started for HL409978+5.p
175305.75/23201.82	% SZS status GaveUp for HL409978+5.p
175305.75/23201.82	eprover: CPU time limit exceeded, terminating
175305.75/23201.82	% SZS status Ended for HL409978+5.p
175308.38/23202.17	% SZS status Started for HL409979+4.p
175308.38/23202.17	% SZS status GaveUp for HL409979+4.p
175308.38/23202.17	eprover: CPU time limit exceeded, terminating
175308.38/23202.17	% SZS status Ended for HL409979+4.p
175312.59/23202.64	% SZS status Started for HL409979+5.p
175312.59/23202.64	% SZS status GaveUp for HL409979+5.p
175312.59/23202.64	eprover: CPU time limit exceeded, terminating
175312.59/23202.64	% SZS status Ended for HL409979+5.p
175318.98/23203.52	% SZS status Started for HL409981+4.p
175318.98/23203.52	% SZS status GaveUp for HL409981+4.p
175318.98/23203.52	eprover: CPU time limit exceeded, terminating
175318.98/23203.52	% SZS status Ended for HL409981+4.p
175319.28/23203.55	% SZS status Started for HL409981+5.p
175319.28/23203.55	% SZS status GaveUp for HL409981+5.p
175319.28/23203.55	eprover: CPU time limit exceeded, terminating
175319.28/23203.55	% SZS status Ended for HL409981+5.p
175321.66/23203.84	% SZS status Started for HL409982+4.p
175321.66/23203.84	% SZS status GaveUp for HL409982+4.p
175321.66/23203.84	eprover: CPU time limit exceeded, terminating
175321.66/23203.84	% SZS status Ended for HL409982+4.p
175327.66/23204.64	% SZS status Started for HL409982+5.p
175327.66/23204.64	% SZS status GaveUp for HL409982+5.p
175327.66/23204.64	eprover: CPU time limit exceeded, terminating
175327.66/23204.64	% SZS status Ended for HL409982+5.p
175328.31/23204.67	% SZS status Started for HL409983+4.p
175328.31/23204.67	% SZS status GaveUp for HL409983+4.p
175328.31/23204.67	eprover: CPU time limit exceeded, terminating
175328.31/23204.67	% SZS status Ended for HL409983+4.p
175329.20/23204.86	% SZS status Started for HL409983+5.p
175329.20/23204.86	% SZS status GaveUp for HL409983+5.p
175329.20/23204.86	eprover: CPU time limit exceeded, terminating
175329.20/23204.86	% SZS status Ended for HL409983+5.p
175332.44/23205.24	% SZS status Started for HL409984+4.p
175332.44/23205.24	% SZS status GaveUp for HL409984+4.p
175332.44/23205.24	eprover: CPU time limit exceeded, terminating
175332.44/23205.24	% SZS status Ended for HL409984+4.p
175338.14/23205.93	% SZS status Started for HL409984+5.p
175338.14/23205.93	% SZS status GaveUp for HL409984+5.p
175338.14/23205.93	eprover: CPU time limit exceeded, terminating
175338.14/23205.93	% SZS status Ended for HL409984+5.p
175343.09/23206.58	% SZS status Started for HL409985+5.p
175343.09/23206.58	% SZS status GaveUp for HL409985+5.p
175343.09/23206.58	eprover: CPU time limit exceeded, terminating
175343.09/23206.58	% SZS status Ended for HL409985+5.p
175344.20/23206.69	% SZS status Started for HL409985+4.p
175344.20/23206.69	% SZS status GaveUp for HL409985+4.p
175344.20/23206.69	eprover: CPU time limit exceeded, terminating
175344.20/23206.69	% SZS status Ended for HL409985+4.p
175345.44/23206.88	% SZS status Started for HL409986+4.p
175345.44/23206.88	% SZS status GaveUp for HL409986+4.p
175345.44/23206.88	eprover: CPU time limit exceeded, terminating
175345.44/23206.88	% SZS status Ended for HL409986+4.p
175351.83/23207.67	% SZS status Started for HL409986+5.p
175351.83/23207.67	% SZS status GaveUp for HL409986+5.p
175351.83/23207.67	eprover: CPU time limit exceeded, terminating
175351.83/23207.67	% SZS status Ended for HL409986+5.p
175352.41/23207.71	% SZS status Started for HL409989+4.p
175352.41/23207.71	% SZS status GaveUp for HL409989+4.p
175352.41/23207.71	eprover: CPU time limit exceeded, terminating
175352.41/23207.71	% SZS status Ended for HL409989+4.p
175353.58/23207.90	% SZS status Started for HL409989+5.p
175353.58/23207.90	% SZS status GaveUp for HL409989+5.p
175353.58/23207.90	eprover: CPU time limit exceeded, terminating
175353.58/23207.90	% SZS status Ended for HL409989+5.p
175357.67/23208.40	% SZS status Started for HL409990+4.p
175357.67/23208.40	% SZS status GaveUp for HL409990+4.p
175357.67/23208.40	eprover: CPU time limit exceeded, terminating
175357.67/23208.40	% SZS status Ended for HL409990+4.p
175361.75/23208.97	% SZS status Started for HL409990+5.p
175361.75/23208.97	% SZS status GaveUp for HL409990+5.p
175361.75/23208.97	eprover: CPU time limit exceeded, terminating
175361.75/23208.97	% SZS status Ended for HL409990+5.p
175367.48/23209.62	% SZS status Started for HL409991+4.p
175367.48/23209.62	% SZS status GaveUp for HL409991+4.p
175367.48/23209.62	eprover: CPU time limit exceeded, terminating
175367.48/23209.62	% SZS status Ended for HL409991+4.p
175368.12/23209.73	% SZS status Started for HL409991+5.p
175368.12/23209.73	% SZS status GaveUp for HL409991+5.p
175368.12/23209.73	eprover: CPU time limit exceeded, terminating
175368.12/23209.73	% SZS status Ended for HL409991+5.p
175369.95/23210.07	% SZS status Started for HL409992+4.p
175369.95/23210.07	% SZS status GaveUp for HL409992+4.p
175369.95/23210.07	eprover: CPU time limit exceeded, terminating
175369.95/23210.07	% SZS status Ended for HL409992+4.p
175376.00/23210.71	% SZS status Started for HL409992+5.p
175376.00/23210.71	% SZS status GaveUp for HL409992+5.p
175376.00/23210.71	eprover: CPU time limit exceeded, terminating
175376.00/23210.71	% SZS status Ended for HL409992+5.p
175376.00/23210.74	% SZS status Started for HL409993+4.p
175376.00/23210.74	% SZS status GaveUp for HL409993+4.p
175376.00/23210.74	eprover: CPU time limit exceeded, terminating
175376.00/23210.74	% SZS status Ended for HL409993+4.p
175377.88/23210.94	% SZS status Started for HL409993+5.p
175377.88/23210.94	% SZS status GaveUp for HL409993+5.p
175377.88/23210.94	eprover: CPU time limit exceeded, terminating
175377.88/23210.94	% SZS status Ended for HL409993+5.p
175381.94/23211.44	% SZS status Started for HL409994+4.p
175381.94/23211.44	% SZS status GaveUp for HL409994+4.p
175381.94/23211.44	eprover: CPU time limit exceeded, terminating
175381.94/23211.44	% SZS status Ended for HL409994+4.p
175386.36/23212.00	% SZS status Started for HL409994+5.p
175386.36/23212.00	% SZS status GaveUp for HL409994+5.p
175386.36/23212.00	eprover: CPU time limit exceeded, terminating
175386.36/23212.00	% SZS status Ended for HL409994+5.p
175391.30/23212.65	% SZS status Started for HL409995+4.p
175391.30/23212.65	% SZS status GaveUp for HL409995+4.p
175391.30/23212.65	eprover: CPU time limit exceeded, terminating
175391.30/23212.65	% SZS status Ended for HL409995+4.p
175392.05/23212.77	% SZS status Started for HL409995+5.p
175392.05/23212.77	% SZS status GaveUp for HL409995+5.p
175392.05/23212.77	eprover: CPU time limit exceeded, terminating
175392.05/23212.77	% SZS status Ended for HL409995+5.p
175395.94/23213.25	% SZS status Started for HL409997+4.p
175395.94/23213.25	% SZS status GaveUp for HL409997+4.p
175395.94/23213.25	eprover: CPU time limit exceeded, terminating
175395.94/23213.25	% SZS status Ended for HL409997+4.p
175399.66/23213.74	% SZS status Started for HL409997+5.p
175399.66/23213.74	% SZS status GaveUp for HL409997+5.p
175399.66/23213.74	eprover: CPU time limit exceeded, terminating
175399.66/23213.74	% SZS status Ended for HL409997+5.p
175399.66/23213.78	% SZS status Started for HL409999+4.p
175399.66/23213.78	% SZS status GaveUp for HL409999+4.p
175399.66/23213.78	eprover: CPU time limit exceeded, terminating
175399.66/23213.78	% SZS status Ended for HL409999+4.p
175401.70/23213.98	% SZS status Started for HL409999+5.p
175401.70/23213.98	% SZS status GaveUp for HL409999+5.p
175401.70/23213.98	eprover: CPU time limit exceeded, terminating
175401.70/23213.98	% SZS status Ended for HL409999+5.p
175405.02/23214.48	% SZS status Started for HL410000+4.p
175405.02/23214.48	% SZS status GaveUp for HL410000+4.p
175405.02/23214.48	eprover: CPU time limit exceeded, terminating
175405.02/23214.48	% SZS status Ended for HL410000+4.p
175412.11/23215.03	% SZS status Started for HL410000+5.p
175412.11/23215.03	% SZS status GaveUp for HL410000+5.p
175412.11/23215.03	eprover: CPU time limit exceeded, terminating
175412.11/23215.03	% SZS status Ended for HL410000+5.p
175416.98/23215.69	% SZS status Started for HL410001+4.p
175416.98/23215.69	% SZS status GaveUp for HL410001+4.p
175416.98/23215.69	eprover: CPU time limit exceeded, terminating
175416.98/23215.69	% SZS status Ended for HL410001+4.p
175418.42/23215.85	% SZS status Started for HL410001+5.p
175418.42/23215.85	% SZS status GaveUp for HL410001+5.p
175418.42/23215.85	eprover: CPU time limit exceeded, terminating
175418.42/23215.85	% SZS status Ended for HL410001+5.p
175421.77/23216.29	% SZS status Started for HL410002+4.p
175421.77/23216.29	% SZS status GaveUp for HL410002+4.p
175421.77/23216.29	eprover: CPU time limit exceeded, terminating
175421.77/23216.29	% SZS status Ended for HL410002+4.p
175425.36/23216.78	% SZS status Started for HL410002+5.p
175425.36/23216.78	% SZS status GaveUp for HL410002+5.p
175425.36/23216.78	eprover: CPU time limit exceeded, terminating
175425.36/23216.78	% SZS status Ended for HL410002+5.p
175425.95/23216.81	% SZS status Started for HL410003+4.p
175425.95/23216.81	% SZS status GaveUp for HL410003+4.p
175425.95/23216.81	eprover: CPU time limit exceeded, terminating
175425.95/23216.81	% SZS status Ended for HL410003+4.p
175427.53/23217.02	% SZS status Started for HL410003+5.p
175427.53/23217.02	% SZS status GaveUp for HL410003+5.p
175427.53/23217.02	eprover: CPU time limit exceeded, terminating
175427.53/23217.02	% SZS status Ended for HL410003+5.p
175432.88/23217.65	% SZS status Started for HL410004+4.p
175432.88/23217.65	% SZS status GaveUp for HL410004+4.p
175432.88/23217.65	eprover: CPU time limit exceeded, terminating
175432.88/23217.65	% SZS status Ended for HL410004+4.p
175435.95/23218.07	% SZS status Started for HL410004+5.p
175435.95/23218.07	% SZS status GaveUp for HL410004+5.p
175435.95/23218.07	eprover: CPU time limit exceeded, terminating
175435.95/23218.07	% SZS status Ended for HL410004+5.p
175441.53/23218.72	% SZS status Started for HL410006+4.p
175441.53/23218.72	% SZS status GaveUp for HL410006+4.p
175441.53/23218.72	eprover: CPU time limit exceeded, terminating
175441.53/23218.72	% SZS status Ended for HL410006+4.p
175442.45/23218.88	% SZS status Started for HL410006+5.p
175442.45/23218.88	% SZS status GaveUp for HL410006+5.p
175442.45/23218.88	eprover: CPU time limit exceeded, terminating
175442.45/23218.88	% SZS status Ended for HL410006+5.p
175445.42/23219.33	% SZS status Started for HL410007+4.p
175445.42/23219.33	% SZS status GaveUp for HL410007+4.p
175445.42/23219.33	eprover: CPU time limit exceeded, terminating
175445.42/23219.33	% SZS status Ended for HL410007+4.p
175450.41/23219.81	% SZS status Started for HL410007+5.p
175450.41/23219.81	% SZS status GaveUp for HL410007+5.p
175450.41/23219.81	eprover: CPU time limit exceeded, terminating
175450.41/23219.81	% SZS status Ended for HL410007+5.p
175450.58/23219.84	% SZS status Started for HL410009+4.p
175450.58/23219.84	% SZS status GaveUp for HL410009+4.p
175450.58/23219.84	eprover: CPU time limit exceeded, terminating
175450.58/23219.84	% SZS status Ended for HL410009+4.p
175452.98/23220.15	% SZS status Started for HL410009+5.p
175452.98/23220.15	% SZS status GaveUp for HL410009+5.p
175452.98/23220.15	eprover: CPU time limit exceeded, terminating
175452.98/23220.15	% SZS status Ended for HL410009+5.p
175457.39/23220.69	% SZS status Started for HL410010+4.p
175457.39/23220.69	% SZS status GaveUp for HL410010+4.p
175457.39/23220.69	eprover: CPU time limit exceeded, terminating
175457.39/23220.69	% SZS status Ended for HL410010+4.p
175460.28/23221.11	% SZS status Started for HL410010+5.p
175460.28/23221.11	% SZS status GaveUp for HL410010+5.p
175460.28/23221.11	eprover: CPU time limit exceeded, terminating
175460.28/23221.11	% SZS status Ended for HL410010+5.p
175465.58/23221.76	% SZS status Started for HL410011+4.p
175465.58/23221.76	% SZS status GaveUp for HL410011+4.p
175465.58/23221.76	eprover: CPU time limit exceeded, terminating
175465.58/23221.76	% SZS status Ended for HL410011+4.p
175467.14/23221.92	% SZS status Started for HL410011+5.p
175467.14/23221.92	% SZS status GaveUp for HL410011+5.p
175467.14/23221.92	eprover: CPU time limit exceeded, terminating
175467.14/23221.92	% SZS status Ended for HL410011+5.p
175469.89/23222.37	% SZS status Started for HL410012+4.p
175469.89/23222.37	% SZS status GaveUp for HL410012+4.p
175469.89/23222.37	eprover: CPU time limit exceeded, terminating
175469.89/23222.37	% SZS status Ended for HL410012+4.p
175473.91/23222.85	% SZS status Started for HL410012+5.p
175473.91/23222.85	% SZS status GaveUp for HL410012+5.p
175473.91/23222.85	eprover: CPU time limit exceeded, terminating
175473.91/23222.85	% SZS status Ended for HL410012+5.p
175473.91/23222.88	% SZS status Started for HL410013+4.p
175473.91/23222.88	% SZS status GaveUp for HL410013+4.p
175473.91/23222.88	eprover: CPU time limit exceeded, terminating
175473.91/23222.88	% SZS status Ended for HL410013+4.p
175478.05/23223.29	% SZS status Started for HL410013+5.p
175478.05/23223.29	% SZS status GaveUp for HL410013+5.p
175478.05/23223.29	eprover: CPU time limit exceeded, terminating
175478.05/23223.29	% SZS status Ended for HL410013+5.p
175481.44/23223.72	% SZS status Started for HL410014+4.p
175481.44/23223.72	% SZS status GaveUp for HL410014+4.p
175481.44/23223.72	eprover: CPU time limit exceeded, terminating
175481.44/23223.72	% SZS status Ended for HL410014+4.p
175484.34/23224.15	% SZS status Started for HL410014+5.p
175484.34/23224.15	% SZS status GaveUp for HL410014+5.p
175484.34/23224.15	eprover: CPU time limit exceeded, terminating
175484.34/23224.15	% SZS status Ended for HL410014+5.p
175489.64/23224.79	% SZS status Started for HL410015+4.p
175489.64/23224.79	% SZS status GaveUp for HL410015+4.p
175489.64/23224.79	eprover: CPU time limit exceeded, terminating
175489.64/23224.79	% SZS status Ended for HL410015+4.p
175491.20/23224.96	% SZS status Started for HL410015+5.p
175491.20/23224.96	% SZS status GaveUp for HL410015+5.p
175491.20/23224.96	eprover: CPU time limit exceeded, terminating
175491.20/23224.96	% SZS status Ended for HL410015+5.p
175495.88/23225.54	% SZS status Started for HL410016+4.p
175495.88/23225.54	% SZS status GaveUp for HL410016+4.p
175495.88/23225.54	eprover: CPU time limit exceeded, terminating
175495.88/23225.54	% SZS status Ended for HL410016+4.p
175498.02/23225.88	% SZS status Started for HL410016+5.p
175498.02/23225.88	% SZS status GaveUp for HL410016+5.p
175498.02/23225.88	eprover: CPU time limit exceeded, terminating
175498.02/23225.88	% SZS status Ended for HL410016+5.p
175498.58/23225.92	% SZS status Started for HL410018+4.p
175498.58/23225.92	% SZS status GaveUp for HL410018+4.p
175498.58/23225.92	eprover: CPU time limit exceeded, terminating
175498.58/23225.92	% SZS status Ended for HL410018+4.p
175501.94/23226.32	% SZS status Started for HL410018+5.p
175501.94/23226.32	% SZS status GaveUp for HL410018+5.p
175501.94/23226.32	eprover: CPU time limit exceeded, terminating
175501.94/23226.32	% SZS status Ended for HL410018+5.p
175505.30/23226.76	% SZS status Started for HL410020+4.p
175505.30/23226.76	% SZS status GaveUp for HL410020+4.p
175505.30/23226.76	eprover: CPU time limit exceeded, terminating
175505.30/23226.76	% SZS status Ended for HL410020+4.p
175508.11/23227.18	% SZS status Started for HL410020+5.p
175508.11/23227.18	% SZS status GaveUp for HL410020+5.p
175508.11/23227.18	eprover: CPU time limit exceeded, terminating
175508.11/23227.18	% SZS status Ended for HL410020+5.p
175513.80/23227.83	% SZS status Started for HL410022+4.p
175513.80/23227.83	% SZS status GaveUp for HL410022+4.p
175513.80/23227.83	eprover: CPU time limit exceeded, terminating
175513.80/23227.83	% SZS status Ended for HL410022+4.p
175516.17/23228.10	% SZS status Started for HL410022+5.p
175516.17/23228.10	% SZS status GaveUp for HL410022+5.p
175516.17/23228.10	eprover: CPU time limit exceeded, terminating
175516.17/23228.10	% SZS status Ended for HL410022+5.p
175519.70/23228.58	% SZS status Started for HL410023+4.p
175519.70/23228.58	% SZS status GaveUp for HL410023+4.p
175519.70/23228.58	eprover: CPU time limit exceeded, terminating
175519.70/23228.58	% SZS status Ended for HL410023+4.p
175522.36/23228.93	% SZS status Started for HL410023+5.p
175522.36/23228.93	% SZS status GaveUp for HL410023+5.p
175522.36/23228.93	eprover: CPU time limit exceeded, terminating
175522.36/23228.93	% SZS status Ended for HL410023+5.p
175522.36/23228.95	% SZS status Started for HL410024+4.p
175522.36/23228.95	% SZS status GaveUp for HL410024+4.p
175522.36/23228.95	eprover: CPU time limit exceeded, terminating
175522.36/23228.95	% SZS status Ended for HL410024+4.p
175525.39/23229.36	% SZS status Started for HL410024+5.p
175525.39/23229.36	% SZS status GaveUp for HL410024+5.p
175525.39/23229.36	eprover: CPU time limit exceeded, terminating
175525.39/23229.36	% SZS status Ended for HL410024+5.p
175529.75/23229.82	% SZS status Started for HL410025+4.p
175529.75/23229.82	% SZS status GaveUp for HL410025+4.p
175529.75/23229.82	eprover: CPU time limit exceeded, terminating
175529.75/23229.82	% SZS status Ended for HL410025+4.p
175531.95/23230.22	% SZS status Started for HL410025+5.p
175531.95/23230.22	% SZS status GaveUp for HL410025+5.p
175531.95/23230.22	eprover: CPU time limit exceeded, terminating
175531.95/23230.22	% SZS status Ended for HL410025+5.p
175538.89/23230.86	% SZS status Started for HL410026+4.p
175538.89/23230.86	% SZS status GaveUp for HL410026+4.p
175538.89/23230.86	eprover: CPU time limit exceeded, terminating
175538.89/23230.86	% SZS status Ended for HL410026+4.p
175542.20/23231.16	% SZS status Started for HL410026+5.p
175542.20/23231.16	% SZS status GaveUp for HL410026+5.p
175542.20/23231.16	eprover: CPU time limit exceeded, terminating
175542.20/23231.16	% SZS status Ended for HL410026+5.p
175545.92/23231.62	% SZS status Started for HL410027+4.p
175545.92/23231.62	% SZS status GaveUp for HL410027+4.p
175545.92/23231.62	eprover: CPU time limit exceeded, terminating
175545.92/23231.62	% SZS status Ended for HL410027+4.p
175548.06/23231.96	% SZS status Started for HL410027+5.p
175548.06/23231.96	% SZS status GaveUp for HL410027+5.p
175548.06/23231.96	eprover: CPU time limit exceeded, terminating
175548.06/23231.96	% SZS status Ended for HL410027+5.p
175549.66/23232.08	% SZS status Started for HL410029+4.p
175549.66/23232.08	% SZS status GaveUp for HL410029+4.p
175549.66/23232.08	eprover: CPU time limit exceeded, terminating
175549.66/23232.08	% SZS status Ended for HL410029+4.p
175551.47/23232.41	% SZS status Started for HL410029+5.p
175551.47/23232.41	% SZS status GaveUp for HL410029+5.p
175551.47/23232.41	eprover: CPU time limit exceeded, terminating
175551.47/23232.41	% SZS status Ended for HL410029+5.p
175555.52/23232.86	% SZS status Started for HL410031+4.p
175555.52/23232.86	% SZS status GaveUp for HL410031+4.p
175555.52/23232.86	eprover: CPU time limit exceeded, terminating
175555.52/23232.86	% SZS status Ended for HL410031+4.p
175558.78/23233.26	% SZS status Started for HL410031+5.p
175558.78/23233.26	% SZS status GaveUp for HL410031+5.p
175558.78/23233.26	eprover: CPU time limit exceeded, terminating
175558.78/23233.26	% SZS status Ended for HL410031+5.p
175564.56/23233.94	% SZS status Started for HL410032+4.p
175564.56/23233.94	% SZS status GaveUp for HL410032+4.p
175564.56/23233.94	eprover: CPU time limit exceeded, terminating
175564.56/23233.94	% SZS status Ended for HL410032+4.p
175566.22/23234.20	% SZS status Started for HL410032+5.p
175566.22/23234.20	% SZS status GaveUp for HL410032+5.p
175566.22/23234.20	eprover: CPU time limit exceeded, terminating
175566.22/23234.20	% SZS status Ended for HL410032+5.p
175570.12/23234.66	% SZS status Started for HL410033+4.p
175570.12/23234.66	% SZS status GaveUp for HL410033+4.p
175570.12/23234.66	eprover: CPU time limit exceeded, terminating
175570.12/23234.66	% SZS status Ended for HL410033+4.p
175573.34/23235.13	% SZS status Started for HL410036+4.p
175573.34/23235.13	% SZS status GaveUp for HL410036+4.p
175573.34/23235.13	eprover: CPU time limit exceeded, terminating
175573.34/23235.13	% SZS status Ended for HL410036+4.p
175573.34/23235.14	% SZS status Started for HL410033+5.p
175573.34/23235.14	% SZS status GaveUp for HL410033+5.p
175573.34/23235.14	eprover: CPU time limit exceeded, terminating
175573.34/23235.14	% SZS status Ended for HL410033+5.p
175576.11/23235.45	% SZS status Started for HL410036+5.p
175576.11/23235.45	% SZS status GaveUp for HL410036+5.p
175576.11/23235.45	eprover: CPU time limit exceeded, terminating
175576.11/23235.45	% SZS status Ended for HL410036+5.p
175579.94/23235.89	% SZS status Started for HL410038+4.p
175579.94/23235.89	% SZS status GaveUp for HL410038+4.p
175579.94/23235.89	eprover: CPU time limit exceeded, terminating
175579.94/23235.89	% SZS status Ended for HL410038+4.p
175588.25/23236.99	% SZS status Started for HL410039+4.p
175588.25/23236.99	% SZS status GaveUp for HL410039+4.p
175588.25/23236.99	eprover: CPU time limit exceeded, terminating
175588.25/23236.99	% SZS status Ended for HL410039+4.p
175594.12/23237.71	% SZS status Started for HL410040+4.p
175594.12/23237.71	% SZS status GaveUp for HL410040+4.p
175594.12/23237.71	eprover: CPU time limit exceeded, terminating
175594.12/23237.71	% SZS status Ended for HL410040+4.p
175597.95/23238.22	% SZS status Started for HL410041+4.p
175597.95/23238.22	% SZS status GaveUp for HL410041+4.p
175597.95/23238.22	eprover: CPU time limit exceeded, terminating
175597.95/23238.22	% SZS status Ended for HL410041+4.p
175603.53/23238.93	% SZS status Started for HL410042+4.p
175603.53/23238.93	% SZS status GaveUp for HL410042+4.p
175603.53/23238.93	eprover: CPU time limit exceeded, terminating
175603.53/23238.93	% SZS status Ended for HL410042+4.p
175617.34/23240.76	% SZS status Started for HL410043+4.p
175617.34/23240.76	% SZS status GaveUp for HL410043+4.p
175617.34/23240.76	eprover: CPU time limit exceeded, terminating
175617.34/23240.76	% SZS status Ended for HL410043+4.p
175627.41/23241.96	% SZS status Started for HL410044+4.p
175627.41/23241.96	% SZS status GaveUp for HL410044+4.p
175627.41/23241.96	eprover: CPU time limit exceeded, terminating
175627.41/23241.96	% SZS status Ended for HL410044+4.p
175645.27/23244.25	% SZS status Started for HL410038+5.p
175645.27/23244.25	% SZS status GaveUp for HL410038+5.p
175645.27/23244.25	eprover: CPU time limit exceeded, terminating
175645.27/23244.25	% SZS status Ended for HL410038+5.p
175650.72/23244.93	% SZS status Started for HL410039+5.p
175650.72/23244.93	% SZS status GaveUp for HL410039+5.p
175650.72/23244.93	eprover: CPU time limit exceeded, terminating
175650.72/23244.93	% SZS status Ended for HL410039+5.p
175652.70/23245.03	% SZS status Started for HL410045+4.p
175652.70/23245.03	% SZS status GaveUp for HL410045+4.p
175652.70/23245.03	eprover: CPU time limit exceeded, terminating
175652.70/23245.03	% SZS status Ended for HL410045+4.p
175655.38/23245.49	% SZS status Started for HL410040+5.p
175655.38/23245.49	% SZS status GaveUp for HL410040+5.p
175655.38/23245.49	eprover: CPU time limit exceeded, terminating
175655.38/23245.49	% SZS status Ended for HL410040+5.p
175658.66/23245.83	% SZS status Started for HL410041+5.p
175658.66/23245.83	% SZS status GaveUp for HL410041+5.p
175658.66/23245.83	eprover: CPU time limit exceeded, terminating
175658.66/23245.83	% SZS status Ended for HL410041+5.p
175670.84/23247.37	% SZS status Started for HL410042+5.p
175670.84/23247.37	% SZS status GaveUp for HL410042+5.p
175670.84/23247.37	eprover: CPU time limit exceeded, terminating
175670.84/23247.37	% SZS status Ended for HL410042+5.p
175675.70/23248.00	% SZS status Started for HL410046+4.p
175675.70/23248.00	% SZS status GaveUp for HL410046+4.p
175675.70/23248.00	eprover: CPU time limit exceeded, terminating
175675.70/23248.00	% SZS status Ended for HL410046+4.p
175680.58/23248.53	% SZS status Started for HL410047+4.p
175680.58/23248.53	% SZS status GaveUp for HL410047+4.p
175680.58/23248.53	eprover: CPU time limit exceeded, terminating
175680.58/23248.53	% SZS status Ended for HL410047+4.p
175680.58/23248.60	% SZS status Started for HL410043+5.p
175680.58/23248.60	% SZS status GaveUp for HL410043+5.p
175680.58/23248.60	eprover: CPU time limit exceeded, terminating
175680.58/23248.60	% SZS status Ended for HL410043+5.p
175694.66/23250.40	% SZS status Started for HL410048+4.p
175694.66/23250.40	% SZS status GaveUp for HL410048+4.p
175694.66/23250.40	eprover: CPU time limit exceeded, terminating
175694.66/23250.40	% SZS status Ended for HL410048+4.p
175700.94/23251.13	% SZS status Started for HL410044+5.p
175700.94/23251.13	% SZS status GaveUp for HL410044+5.p
175700.94/23251.13	eprover: CPU time limit exceeded, terminating
175700.94/23251.13	% SZS status Ended for HL410044+5.p
175704.81/23251.58	% SZS status Started for HL410049+4.p
175704.81/23251.58	% SZS status GaveUp for HL410049+4.p
175704.81/23251.58	eprover: CPU time limit exceeded, terminating
175704.81/23251.58	% SZS status Ended for HL410049+4.p
175719.08/23253.45	% SZS status Started for HL410050+4.p
175719.08/23253.45	% SZS status GaveUp for HL410050+4.p
175719.08/23253.45	eprover: CPU time limit exceeded, terminating
175719.08/23253.45	% SZS status Ended for HL410050+4.p
175727.92/23254.61	% SZS status Started for HL410051+4.p
175727.92/23254.61	% SZS status GaveUp for HL410051+4.p
175727.92/23254.61	eprover: CPU time limit exceeded, terminating
175727.92/23254.61	% SZS status Ended for HL410051+4.p
175727.92/23254.70	% SZS status Started for HL410045+5.p
175727.92/23254.70	% SZS status GaveUp for HL410045+5.p
175727.92/23254.70	eprover: CPU time limit exceeded, terminating
175727.92/23254.70	% SZS status Ended for HL410045+5.p
175734.55/23255.46	% SZS status Started for HL410046+5.p
175734.55/23255.46	% SZS status GaveUp for HL410046+5.p
175734.55/23255.46	eprover: CPU time limit exceeded, terminating
175734.55/23255.46	% SZS status Ended for HL410046+5.p
175741.73/23256.32	% SZS status Started for HL410047+5.p
175741.73/23256.32	% SZS status GaveUp for HL410047+5.p
175741.73/23256.32	eprover: CPU time limit exceeded, terminating
175741.73/23256.32	% SZS status Ended for HL410047+5.p
175751.81/23257.67	% SZS status Started for HL410052+4.p
175751.81/23257.67	% SZS status GaveUp for HL410052+4.p
175751.81/23257.67	eprover: CPU time limit exceeded, terminating
175751.81/23257.67	% SZS status Ended for HL410052+4.p
175759.02/23258.44	% SZS status Started for HL410048+5.p
175759.02/23258.44	% SZS status GaveUp for HL410048+5.p
175759.02/23258.44	eprover: CPU time limit exceeded, terminating
175759.02/23258.44	% SZS status Ended for HL410048+5.p
175759.55/23258.52	% SZS status Started for HL410053+4.p
175759.55/23258.52	% SZS status GaveUp for HL410053+4.p
175759.55/23258.52	eprover: CPU time limit exceeded, terminating
175759.55/23258.52	% SZS status Ended for HL410053+4.p
175764.94/23259.20	% SZS status Started for HL410049+5.p
175764.94/23259.20	% SZS status GaveUp for HL410049+5.p
175764.94/23259.20	eprover: CPU time limit exceeded, terminating
175764.94/23259.20	% SZS status Ended for HL410049+5.p
175777.73/23260.83	% SZS status Started for HL410054+4.p
175777.73/23260.83	% SZS status GaveUp for HL410054+4.p
175777.73/23260.83	eprover: CPU time limit exceeded, terminating
175777.73/23260.83	% SZS status Ended for HL410054+4.p
175783.53/23261.52	% SZS status Started for HL410050+5.p
175783.53/23261.52	% SZS status GaveUp for HL410050+5.p
175783.53/23261.52	eprover: CPU time limit exceeded, terminating
175783.53/23261.52	% SZS status Ended for HL410050+5.p
175783.62/23261.60	% SZS status Started for HL410056+4.p
175783.62/23261.60	% SZS status GaveUp for HL410056+4.p
175783.62/23261.60	eprover: CPU time limit exceeded, terminating
175783.62/23261.60	% SZS status Ended for HL410056+4.p
175802.11/23263.89	% SZS status Started for HL410057+4.p
175802.11/23263.89	% SZS status GaveUp for HL410057+4.p
175802.11/23263.89	eprover: CPU time limit exceeded, terminating
175802.11/23263.89	% SZS status Ended for HL410057+4.p
175804.03/23264.13	% SZS status Started for HL410051+5.p
175804.03/23264.13	% SZS status GaveUp for HL410051+5.p
175804.03/23264.13	eprover: CPU time limit exceeded, terminating
175804.03/23264.13	% SZS status Ended for HL410051+5.p
175808.03/23264.75	% SZS status Started for HL410058+4.p
175808.03/23264.75	% SZS status GaveUp for HL410058+4.p
175808.03/23264.75	eprover: CPU time limit exceeded, terminating
175808.03/23264.75	% SZS status Ended for HL410058+4.p
175811.50/23265.10	% SZS status Started for HL410052+5.p
175811.50/23265.10	% SZS status GaveUp for HL410052+5.p
175811.50/23265.10	eprover: CPU time limit exceeded, terminating
175811.50/23265.10	% SZS status Ended for HL410052+5.p
175824.59/23266.76	% SZS status Started for HL410053+5.p
175824.59/23266.76	% SZS status GaveUp for HL410053+5.p
175824.59/23266.76	eprover: CPU time limit exceeded, terminating
175824.59/23266.76	% SZS status Ended for HL410053+5.p
175826.58/23267.17	% SZS status Started for HL410059+4.p
175826.58/23267.17	% SZS status GaveUp for HL410059+4.p
175826.58/23267.17	eprover: CPU time limit exceeded, terminating
175826.58/23267.17	% SZS status Ended for HL410059+4.p
175835.67/23268.17	% SZS status Started for HL410060+4.p
175835.67/23268.17	% SZS status GaveUp for HL410060+4.p
175835.67/23268.17	eprover: CPU time limit exceeded, terminating
175835.67/23268.17	% SZS status Ended for HL410060+4.p
175842.36/23269.07	% SZS status Started for HL410054+5.p
175842.36/23269.07	% SZS status GaveUp for HL410054+5.p
175842.36/23269.07	eprover: CPU time limit exceeded, terminating
175842.36/23269.07	% SZS status Ended for HL410054+5.p
175846.69/23269.57	% SZS status Started for HL410056+5.p
175846.69/23269.57	% SZS status GaveUp for HL410056+5.p
175846.69/23269.57	eprover: CPU time limit exceeded, terminating
175846.69/23269.57	% SZS status Ended for HL410056+5.p
175851.44/23270.19	% SZS status Started for HL410061+4.p
175851.44/23270.19	% SZS status GaveUp for HL410061+4.p
175851.44/23270.19	eprover: CPU time limit exceeded, terminating
175851.44/23270.19	% SZS status Ended for HL410061+4.p
175865.48/23271.94	% SZS status Started for HL410057+5.p
175865.48/23271.94	% SZS status GaveUp for HL410057+5.p
175865.48/23271.94	eprover: CPU time limit exceeded, terminating
175865.48/23271.94	% SZS status Ended for HL410057+5.p
175867.38/23272.17	% SZS status Started for HL410062+4.p
175867.38/23272.17	% SZS status GaveUp for HL410062+4.p
175867.38/23272.17	eprover: CPU time limit exceeded, terminating
175867.38/23272.17	% SZS status Ended for HL410062+4.p
175875.53/23273.26	% SZS status Started for HL410063+4.p
175875.53/23273.26	% SZS status GaveUp for HL410063+4.p
175875.53/23273.26	eprover: CPU time limit exceeded, terminating
175875.53/23273.26	% SZS status Ended for HL410063+4.p
175886.28/23274.58	% SZS status Started for HL410058+5.p
175886.28/23274.58	% SZS status GaveUp for HL410058+5.p
175886.28/23274.58	eprover: CPU time limit exceeded, terminating
175886.28/23274.58	% SZS status Ended for HL410058+5.p
175891.45/23275.20	% SZS status Started for HL410059+5.p
175891.45/23275.20	% SZS status GaveUp for HL410059+5.p
175891.45/23275.20	eprover: CPU time limit exceeded, terminating
175891.45/23275.20	% SZS status Ended for HL410059+5.p
175891.45/23275.23	% SZS status Started for HL410064+4.p
175891.45/23275.23	% SZS status GaveUp for HL410064+4.p
175891.45/23275.23	eprover: CPU time limit exceeded, terminating
175891.45/23275.23	% SZS status Ended for HL410064+4.p
175909.16/23277.43	% SZS status Started for HL410060+5.p
175909.16/23277.43	% SZS status GaveUp for HL410060+5.p
175909.16/23277.43	eprover: CPU time limit exceeded, terminating
175909.16/23277.43	% SZS status Ended for HL410060+5.p
175911.17/23277.61	% SZS status Started for HL410065+4.p
175911.17/23277.61	% SZS status GaveUp for HL410065+4.p
175911.17/23277.61	eprover: CPU time limit exceeded, terminating
175911.17/23277.61	% SZS status Ended for HL410065+4.p
175916.05/23278.27	% SZS status Started for HL410067+4.p
175916.05/23278.27	% SZS status GaveUp for HL410067+4.p
175916.05/23278.27	eprover: CPU time limit exceeded, terminating
175916.05/23278.27	% SZS status Ended for HL410067+4.p
175922.12/23278.99	% SZS status Started for HL410061+5.p
175922.12/23278.99	% SZS status GaveUp for HL410061+5.p
175922.12/23278.99	eprover: CPU time limit exceeded, terminating
175922.12/23278.99	% SZS status Ended for HL410061+5.p
175931.02/23280.13	% SZS status Started for HL410062+5.p
175931.02/23280.13	% SZS status GaveUp for HL410062+5.p
175931.02/23280.13	eprover: CPU time limit exceeded, terminating
175931.02/23280.13	% SZS status Ended for HL410062+5.p
175935.08/23280.66	% SZS status Started for HL410068+4.p
175935.08/23280.66	% SZS status GaveUp for HL410068+4.p
175935.08/23280.66	eprover: CPU time limit exceeded, terminating
175935.08/23280.66	% SZS status Ended for HL410068+4.p
175945.88/23282.06	% SZS status Started for HL410069+4.p
175945.88/23282.06	% SZS status GaveUp for HL410069+4.p
175945.88/23282.06	eprover: CPU time limit exceeded, terminating
175945.88/23282.06	% SZS status Ended for HL410069+4.p
175950.08/23282.55	% SZS status Started for HL410063+5.p
175950.08/23282.55	% SZS status GaveUp for HL410063+5.p
175950.08/23282.55	eprover: CPU time limit exceeded, terminating
175950.08/23282.55	% SZS status Ended for HL410063+5.p
175958.77/23283.62	% SZS status Started for HL410064+5.p
175958.77/23283.62	% SZS status GaveUp for HL410064+5.p
175958.77/23283.62	eprover: CPU time limit exceeded, terminating
175958.77/23283.62	% SZS status Ended for HL410064+5.p
175959.23/23283.75	% SZS status Started for HL410070+4.p
175959.23/23283.75	% SZS status GaveUp for HL410070+4.p
175959.23/23283.75	eprover: CPU time limit exceeded, terminating
175959.23/23283.75	% SZS status Ended for HL410070+4.p
175974.23/23285.60	% SZS status Started for HL410065+5.p
175974.23/23285.60	% SZS status GaveUp for HL410065+5.p
175974.23/23285.60	eprover: CPU time limit exceeded, terminating
175974.23/23285.60	% SZS status Ended for HL410065+5.p
175974.23/23285.63	% SZS status Started for HL410071+4.p
175974.23/23285.63	% SZS status GaveUp for HL410071+4.p
175974.23/23285.63	eprover: CPU time limit exceeded, terminating
175974.23/23285.63	% SZS status Ended for HL410071+4.p
175983.91/23286.88	% SZS status Started for HL410072+4.p
175983.91/23286.88	% SZS status GaveUp for HL410072+4.p
175983.91/23286.88	eprover: CPU time limit exceeded, terminating
175983.91/23286.88	% SZS status Ended for HL410072+4.p
175991.98/23287.82	% SZS status Started for HL410067+5.p
175991.98/23287.82	% SZS status GaveUp for HL410067+5.p
175991.98/23287.82	eprover: CPU time limit exceeded, terminating
175991.98/23287.82	% SZS status Ended for HL410067+5.p
175998.56/23288.66	% SZS status Started for HL410073+4.p
175998.56/23288.66	% SZS status GaveUp for HL410073+4.p
175998.56/23288.66	eprover: CPU time limit exceeded, terminating
175998.56/23288.66	% SZS status Ended for HL410073+4.p
175998.56/23288.71	% SZS status Started for HL410068+5.p
175998.56/23288.71	% SZS status GaveUp for HL410068+5.p
175998.56/23288.71	eprover: CPU time limit exceeded, terminating
175998.56/23288.71	% SZS status Ended for HL410068+5.p
176008.39/23289.94	% SZS status Started for HL410073+5.p
176008.39/23289.94	% SZS status GaveUp for HL410073+5.p
176008.39/23289.94	eprover: CPU time limit exceeded, terminating
176008.39/23289.94	% SZS status Ended for HL410073+5.p
176014.98/23290.81	% SZS status Started for HL410069+5.p
176014.98/23290.81	% SZS status GaveUp for HL410069+5.p
176014.98/23290.81	eprover: CPU time limit exceeded, terminating
176014.98/23290.81	% SZS status Ended for HL410069+5.p
176016.08/23290.87	% SZS status Started for HL410074+4.p
176016.08/23290.87	% SZS status GaveUp for HL410074+4.p
176016.08/23290.87	eprover: CPU time limit exceeded, terminating
176016.08/23290.87	% SZS status Ended for HL410074+4.p
176023.02/23291.76	% SZS status Started for HL410075+4.p
176023.02/23291.76	% SZS status GaveUp for HL410075+4.p
176023.02/23291.76	eprover: CPU time limit exceeded, terminating
176023.02/23291.76	% SZS status Ended for HL410075+4.p
176030.12/23292.57	% SZS status Started for HL410070+5.p
176030.12/23292.57	% SZS status GaveUp for HL410070+5.p
176030.12/23292.57	eprover: CPU time limit exceeded, terminating
176030.12/23292.57	% SZS status Ended for HL410070+5.p
176040.16/23293.84	% SZS status Started for HL410076+4.p
176040.16/23293.84	% SZS status GaveUp for HL410076+4.p
176040.16/23293.84	eprover: CPU time limit exceeded, terminating
176040.16/23293.84	% SZS status Ended for HL410076+4.p
176040.73/23293.92	% SZS status Started for HL410076+5.p
176040.73/23293.92	% SZS status GaveUp for HL410076+5.p
176040.73/23293.92	eprover: CPU time limit exceeded, terminating
176040.73/23293.92	% SZS status Ended for HL410076+5.p
176041.17/23294.01	% SZS status Started for HL410071+5.p
176041.17/23294.01	% SZS status GaveUp for HL410071+5.p
176041.17/23294.01	eprover: CPU time limit exceeded, terminating
176041.17/23294.01	% SZS status Ended for HL410071+5.p
176047.39/23294.79	% SZS status Started for HL410078+4.p
176047.39/23294.79	% SZS status GaveUp for HL410078+4.p
176047.39/23294.79	eprover: CPU time limit exceeded, terminating
176047.39/23294.79	% SZS status Ended for HL410078+4.p
176058.98/23296.25	% SZS status Started for HL410072+5.p
176058.98/23296.25	% SZS status GaveUp for HL410072+5.p
176058.98/23296.25	eprover: CPU time limit exceeded, terminating
176058.98/23296.25	% SZS status Ended for HL410072+5.p
176064.03/23296.87	% SZS status Started for HL410079+4.p
176064.03/23296.87	% SZS status GaveUp for HL410079+4.p
176064.03/23296.87	eprover: CPU time limit exceeded, terminating
176064.03/23296.87	% SZS status Ended for HL410079+4.p
176065.20/23297.04	% SZS status Started for HL410080+4.p
176065.20/23297.04	% SZS status GaveUp for HL410080+4.p
176065.20/23297.04	eprover: CPU time limit exceeded, terminating
176065.20/23297.04	% SZS status Ended for HL410080+4.p
176081.42/23299.09	% SZS status Started for HL410074+5.p
176081.42/23299.09	% SZS status GaveUp for HL410074+5.p
176081.42/23299.09	eprover: CPU time limit exceeded, terminating
176081.42/23299.09	% SZS status Ended for HL410074+5.p
176083.34/23299.31	% SZS status Started for HL410082+4.p
176083.34/23299.31	% SZS status GaveUp for HL410082+4.p
176083.34/23299.31	eprover: CPU time limit exceeded, terminating
176083.34/23299.31	% SZS status Ended for HL410082+4.p
176089.56/23300.15	% SZS status Started for HL410083+4.p
176089.56/23300.15	% SZS status GaveUp for HL410083+4.p
176089.56/23300.15	eprover: CPU time limit exceeded, terminating
176089.56/23300.15	% SZS status Ended for HL410083+4.p
176090.55/23300.32	% SZS status Started for HL410075+5.p
176090.55/23300.32	% SZS status GaveUp for HL410075+5.p
176090.55/23300.32	eprover: CPU time limit exceeded, terminating
176090.55/23300.32	% SZS status Ended for HL410075+5.p
176106.70/23302.36	% SZS status Started for HL410084+4.p
176106.70/23302.36	% SZS status GaveUp for HL410084+4.p
176106.70/23302.36	eprover: CPU time limit exceeded, terminating
176106.70/23302.36	% SZS status Ended for HL410084+4.p
176112.48/23302.96	% SZS status Started for HL410078+5.p
176112.48/23302.96	% SZS status GaveUp for HL410078+5.p
176112.48/23302.96	eprover: CPU time limit exceeded, terminating
176112.48/23302.96	% SZS status Ended for HL410078+5.p
176115.20/23303.40	% SZS status Started for HL410085+4.p
176115.20/23303.40	% SZS status GaveUp for HL410085+4.p
176115.20/23303.40	eprover: CPU time limit exceeded, terminating
176115.20/23303.40	% SZS status Ended for HL410085+4.p
176123.70/23304.43	% SZS status Started for HL410079+5.p
176123.70/23304.43	% SZS status GaveUp for HL410079+5.p
176123.70/23304.43	eprover: CPU time limit exceeded, terminating
176123.70/23304.43	% SZS status Ended for HL410079+5.p
176131.44/23305.38	% SZS status Started for HL410080+5.p
176131.44/23305.38	% SZS status GaveUp for HL410080+5.p
176131.44/23305.38	eprover: CPU time limit exceeded, terminating
176131.44/23305.38	% SZS status Ended for HL410080+5.p
176133.70/23306.01	% SZS status Started for HL410086+4.p
176133.70/23306.01	% SZS status GaveUp for HL410086+4.p
176133.70/23306.01	eprover: CPU time limit exceeded, terminating
176133.70/23306.01	% SZS status Ended for HL410086+4.p
176147.78/23307.43	% SZS status Started for HL410082+5.p
176147.78/23307.43	% SZS status GaveUp for HL410082+5.p
176147.78/23307.43	eprover: CPU time limit exceeded, terminating
176147.78/23307.43	% SZS status Ended for HL410082+5.p
176148.19/23307.47	% SZS status Started for HL410087+4.p
176148.19/23307.47	% SZS status GaveUp for HL410087+4.p
176148.19/23307.47	eprover: CPU time limit exceeded, terminating
176148.19/23307.47	% SZS status Ended for HL410087+4.p
176160.75/23309.05	% SZS status Started for HL410088+4.p
176160.75/23309.05	% SZS status GaveUp for HL410088+4.p
176160.75/23309.05	eprover: CPU time limit exceeded, terminating
176160.75/23309.05	% SZS status Ended for HL410088+4.p
176164.19/23309.50	% SZS status Started for HL410083+5.p
176164.19/23309.50	% SZS status GaveUp for HL410083+5.p
176164.19/23309.50	eprover: CPU time limit exceeded, terminating
176164.19/23309.50	% SZS status Ended for HL410083+5.p
176172.23/23310.50	% SZS status Started for HL410089+4.p
176172.23/23310.50	% SZS status GaveUp for HL410089+4.p
176172.23/23310.50	eprover: CPU time limit exceeded, terminating
176172.23/23310.50	% SZS status Ended for HL410089+4.p
176173.44/23310.69	% SZS status Started for HL410084+5.p
176173.44/23310.69	% SZS status GaveUp for HL410084+5.p
176173.44/23310.69	eprover: CPU time limit exceeded, terminating
176173.44/23310.69	% SZS status Ended for HL410084+5.p
176188.36/23312.55	% SZS status Started for HL410090+4.p
176188.36/23312.55	% SZS status GaveUp for HL410090+4.p
176188.36/23312.55	eprover: CPU time limit exceeded, terminating
176188.36/23312.55	% SZS status Ended for HL410090+4.p
176190.00/23312.73	% SZS status Started for HL410085+5.p
176190.00/23312.73	% SZS status GaveUp for HL410085+5.p
176190.00/23312.73	eprover: CPU time limit exceeded, terminating
176190.00/23312.73	% SZS status Ended for HL410085+5.p
176197.61/23313.74	% SZS status Started for HL410091+4.p
176197.61/23313.74	% SZS status GaveUp for HL410091+4.p
176197.61/23313.74	eprover: CPU time limit exceeded, terminating
176197.61/23313.74	% SZS status Ended for HL410091+4.p
176198.27/23313.80	% SZS status Started for HL410086+5.p
176198.27/23313.80	% SZS status GaveUp for HL410086+5.p
176198.27/23313.80	eprover: CPU time limit exceeded, terminating
176198.27/23313.80	% SZS status Ended for HL410086+5.p
176213.69/23315.81	% SZS status Started for HL410092+4.p
176213.69/23315.81	% SZS status GaveUp for HL410092+4.p
176213.69/23315.81	eprover: CPU time limit exceeded, terminating
176213.69/23315.81	% SZS status Ended for HL410092+4.p
176214.55/23315.89	% SZS status Started for HL410087+5.p
176214.55/23315.89	% SZS status GaveUp for HL410087+5.p
176214.55/23315.89	eprover: CPU time limit exceeded, terminating
176214.55/23315.89	% SZS status Ended for HL410087+5.p
176222.22/23316.87	% SZS status Started for HL410094+4.p
176222.22/23316.87	% SZS status GaveUp for HL410094+4.p
176222.22/23316.87	eprover: CPU time limit exceeded, terminating
176222.22/23316.87	% SZS status Ended for HL410094+4.p
176231.42/23317.98	% SZS status Started for HL410088+5.p
176231.42/23317.98	% SZS status GaveUp for HL410088+5.p
176231.42/23317.98	eprover: CPU time limit exceeded, terminating
176231.42/23317.98	% SZS status Ended for HL410088+5.p
176238.75/23318.93	% SZS status Started for HL410095+4.p
176238.75/23318.93	% SZS status GaveUp for HL410095+4.p
176238.75/23318.93	eprover: CPU time limit exceeded, terminating
176238.75/23318.93	% SZS status Ended for HL410095+4.p
176244.64/23319.65	% SZS status Started for HL410089+5.p
176244.64/23319.65	% SZS status GaveUp for HL410089+5.p
176244.64/23319.65	eprover: CPU time limit exceeded, terminating
176244.64/23319.65	% SZS status Ended for HL410089+5.p
176255.31/23321.01	% SZS status Started for HL410090+5.p
176255.31/23321.01	% SZS status GaveUp for HL410090+5.p
176255.31/23321.01	eprover: CPU time limit exceeded, terminating
176255.31/23321.01	% SZS status Ended for HL410090+5.p
176255.89/23321.08	% SZS status Started for HL410096+4.p
176255.89/23321.08	% SZS status GaveUp for HL410096+4.p
176255.89/23321.08	eprover: CPU time limit exceeded, terminating
176255.89/23321.08	% SZS status Ended for HL410096+4.p
176268.81/23322.70	% SZS status Started for HL410097+4.p
176268.81/23322.70	% SZS status GaveUp for HL410097+4.p
176268.81/23322.70	eprover: CPU time limit exceeded, terminating
176268.81/23322.70	% SZS status Ended for HL410097+4.p
176271.00/23323.00	% SZS status Started for HL410091+5.p
176271.00/23323.00	% SZS status GaveUp for HL410091+5.p
176271.00/23323.00	eprover: CPU time limit exceeded, terminating
176271.00/23323.00	% SZS status Ended for HL410091+5.p
176280.42/23324.16	% SZS status Started for HL410098+4.p
176280.42/23324.16	% SZS status GaveUp for HL410098+4.p
176280.42/23324.16	eprover: CPU time limit exceeded, terminating
176280.42/23324.16	% SZS status Ended for HL410098+4.p
176280.42/23324.17	% SZS status Started for HL410092+5.p
176280.42/23324.17	% SZS status GaveUp for HL410092+5.p
176280.42/23324.17	eprover: CPU time limit exceeded, terminating
176280.42/23324.17	% SZS status Ended for HL410092+5.p
176294.98/23326.03	% SZS status Started for HL410099+4.p
176294.98/23326.03	% SZS status GaveUp for HL410099+4.p
176294.98/23326.03	eprover: CPU time limit exceeded, terminating
176294.98/23326.03	% SZS status Ended for HL410099+4.p
176296.12/23326.19	% SZS status Started for HL410094+5.p
176296.12/23326.19	% SZS status GaveUp for HL410094+5.p
176296.12/23326.19	eprover: CPU time limit exceeded, terminating
176296.12/23326.19	% SZS status Ended for HL410094+5.p
176304.86/23327.23	% SZS status Started for HL410100+4.p
176304.86/23327.23	% SZS status GaveUp for HL410100+4.p
176304.86/23327.23	eprover: CPU time limit exceeded, terminating
176304.86/23327.23	% SZS status Ended for HL410100+4.p
176305.80/23327.37	% SZS status Started for HL410095+5.p
176305.80/23327.37	% SZS status GaveUp for HL410095+5.p
176305.80/23327.37	eprover: CPU time limit exceeded, terminating
176305.80/23327.37	% SZS status Ended for HL410095+5.p
176320.98/23329.30	% SZS status Started for HL410101+4.p
176320.98/23329.30	% SZS status GaveUp for HL410101+4.p
176320.98/23329.30	eprover: CPU time limit exceeded, terminating
176320.98/23329.30	% SZS status Ended for HL410101+4.p
176322.47/23329.52	% SZS status Started for HL410096+5.p
176322.47/23329.52	% SZS status GaveUp for HL410096+5.p
176322.47/23329.52	eprover: CPU time limit exceeded, terminating
176322.47/23329.52	% SZS status Ended for HL410096+5.p
176330.03/23330.44	% SZS status Started for HL410102+4.p
176330.03/23330.44	% SZS status GaveUp for HL410102+4.p
176330.03/23330.44	eprover: CPU time limit exceeded, terminating
176330.03/23330.44	% SZS status Ended for HL410102+4.p
176340.95/23331.99	% SZS status Started for HL410097+5.p
176340.95/23331.99	% SZS status GaveUp for HL410097+5.p
176340.95/23331.99	eprover: CPU time limit exceeded, terminating
176340.95/23331.99	% SZS status Ended for HL410097+5.p
176346.94/23332.57	% SZS status Started for HL410103+4.p
176346.94/23332.57	% SZS status GaveUp for HL410103+4.p
176346.94/23332.57	eprover: CPU time limit exceeded, terminating
176346.94/23332.57	% SZS status Ended for HL410103+4.p
176352.77/23333.31	% SZS status Started for HL410098+5.p
176352.77/23333.31	% SZS status GaveUp for HL410098+5.p
176352.77/23333.31	eprover: CPU time limit exceeded, terminating
176352.77/23333.31	% SZS status Ended for HL410098+5.p
176362.98/23334.60	% SZS status Started for HL410099+5.p
176362.98/23334.60	% SZS status GaveUp for HL410099+5.p
176362.98/23334.60	eprover: CPU time limit exceeded, terminating
176362.98/23334.60	% SZS status Ended for HL410099+5.p
176366.53/23335.03	% SZS status Started for HL410104+4.p
176366.53/23335.03	% SZS status GaveUp for HL410104+4.p
176366.53/23335.03	eprover: CPU time limit exceeded, terminating
176366.53/23335.03	% SZS status Ended for HL410104+4.p
176376.94/23336.34	% SZS status Started for HL410105+4.p
176376.94/23336.34	% SZS status GaveUp for HL410105+4.p
176376.94/23336.34	eprover: CPU time limit exceeded, terminating
176376.94/23336.34	% SZS status Ended for HL410105+4.p
176379.12/23336.63	% SZS status Started for HL410100+5.p
176379.12/23336.63	% SZS status GaveUp for HL410100+5.p
176379.12/23336.63	eprover: CPU time limit exceeded, terminating
176379.12/23336.63	% SZS status Ended for HL410100+5.p
176387.52/23337.72	% SZS status Started for HL410101+5.p
176387.52/23337.72	% SZS status GaveUp for HL410101+5.p
176387.52/23337.72	eprover: CPU time limit exceeded, terminating
176387.52/23337.72	% SZS status Ended for HL410101+5.p
176389.86/23338.07	% SZS status Started for HL410106+4.p
176389.86/23338.07	% SZS status GaveUp for HL410106+4.p
176389.86/23338.07	eprover: CPU time limit exceeded, terminating
176389.86/23338.07	% SZS status Ended for HL410106+4.p
176403.47/23339.66	% SZS status Started for HL410107+4.p
176403.47/23339.66	% SZS status GaveUp for HL410107+4.p
176403.47/23339.66	eprover: CPU time limit exceeded, terminating
176403.47/23339.66	% SZS status Ended for HL410107+4.p
176405.95/23339.99	% SZS status Started for HL410102+5.p
176405.95/23339.99	% SZS status GaveUp for HL410102+5.p
176405.95/23339.99	eprover: CPU time limit exceeded, terminating
176405.95/23339.99	% SZS status Ended for HL410102+5.p
176412.66/23340.84	% SZS status Started for HL410103+5.p
176412.66/23340.84	% SZS status GaveUp for HL410103+5.p
176412.66/23340.84	eprover: CPU time limit exceeded, terminating
176412.66/23340.84	% SZS status Ended for HL410103+5.p
176414.45/23341.11	% SZS status Started for HL410108+4.p
176414.45/23341.11	% SZS status GaveUp for HL410108+4.p
176414.45/23341.11	eprover: CPU time limit exceeded, terminating
176414.45/23341.11	% SZS status Ended for HL410108+4.p
176429.75/23343.04	% SZS status Started for HL410109+4.p
176429.75/23343.04	% SZS status GaveUp for HL410109+4.p
176429.75/23343.04	eprover: CPU time limit exceeded, terminating
176429.75/23343.04	% SZS status Ended for HL410109+4.p
176429.98/23343.07	% SZS status Started for HL410104+5.p
176429.98/23343.07	% SZS status GaveUp for HL410104+5.p
176429.98/23343.07	eprover: CPU time limit exceeded, terminating
176429.98/23343.07	% SZS status Ended for HL410104+5.p
176438.42/23344.20	% SZS status Started for HL410111+4.p
176438.42/23344.20	% SZS status GaveUp for HL410111+4.p
176438.42/23344.20	eprover: CPU time limit exceeded, terminating
176438.42/23344.20	% SZS status Ended for HL410111+4.p
176446.11/23345.04	% SZS status Started for HL410105+5.p
176446.11/23345.04	% SZS status GaveUp for HL410105+5.p
176446.11/23345.04	eprover: CPU time limit exceeded, terminating
176446.11/23345.04	% SZS status Ended for HL410105+5.p
176454.08/23346.09	% SZS status Started for HL410112+4.p
176454.08/23346.09	% SZS status GaveUp for HL410112+4.p
176454.08/23346.09	eprover: CPU time limit exceeded, terminating
176454.08/23346.09	% SZS status Ended for HL410112+4.p
176458.84/23346.71	% SZS status Started for HL410106+5.p
176458.84/23346.71	% SZS status GaveUp for HL410106+5.p
176458.84/23346.71	eprover: CPU time limit exceeded, terminating
176458.84/23346.71	% SZS status Ended for HL410106+5.p
176470.38/23348.11	% SZS status Started for HL410113+4.p
176470.38/23348.11	% SZS status GaveUp for HL410113+4.p
176470.38/23348.11	eprover: CPU time limit exceeded, terminating
176470.38/23348.11	% SZS status Ended for HL410113+4.p
176471.47/23348.28	% SZS status Started for HL410107+5.p
176471.47/23348.28	% SZS status GaveUp for HL410107+5.p
176471.47/23348.28	eprover: CPU time limit exceeded, terminating
176471.47/23348.28	% SZS status Ended for HL410107+5.p
176478.62/23349.15	% SZS status Started for HL410113+5.p
176478.62/23349.15	% SZS status GaveUp for HL410113+5.p
176478.62/23349.15	eprover: CPU time limit exceeded, terminating
176478.62/23349.15	% SZS status Ended for HL410113+5.p
176482.92/23349.76	% SZS status Started for HL410114+4.p
176482.92/23349.76	% SZS status GaveUp for HL410114+4.p
176482.92/23349.76	eprover: CPU time limit exceeded, terminating
176482.92/23349.76	% SZS status Ended for HL410114+4.p
176485.98/23350.08	% SZS status Started for HL410108+5.p
176485.98/23350.08	% SZS status GaveUp for HL410108+5.p
176485.98/23350.08	eprover: CPU time limit exceeded, terminating
176485.98/23350.08	% SZS status Ended for HL410108+5.p
176496.45/23351.39	% SZS status Started for HL410115+4.p
176496.45/23351.39	% SZS status GaveUp for HL410115+4.p
176496.45/23351.39	eprover: CPU time limit exceeded, terminating
176496.45/23351.39	% SZS status Ended for HL410115+4.p
176497.48/23351.53	% SZS status Started for HL410109+5.p
176497.48/23351.53	% SZS status GaveUp for HL410109+5.p
176497.48/23351.53	eprover: CPU time limit exceeded, terminating
176497.48/23351.53	% SZS status Ended for HL410109+5.p
176507.02/23352.78	% SZS status Started for HL410116+4.p
176507.02/23352.78	% SZS status GaveUp for HL410116+4.p
176507.02/23352.78	eprover: CPU time limit exceeded, terminating
176507.02/23352.78	% SZS status Ended for HL410116+4.p
176513.58/23353.64	% SZS status Started for HL410111+5.p
176513.58/23353.64	% SZS status GaveUp for HL410111+5.p
176513.58/23353.64	eprover: CPU time limit exceeded, terminating
176513.58/23353.64	% SZS status Ended for HL410111+5.p
176520.16/23354.42	% SZS status Started for HL410117+4.p
176520.16/23354.42	% SZS status GaveUp for HL410117+4.p
176520.16/23354.42	eprover: CPU time limit exceeded, terminating
176520.16/23354.42	% SZS status Ended for HL410117+4.p
176521.56/23354.61	% SZS status Started for HL410112+5.p
176521.56/23354.61	% SZS status GaveUp for HL410112+5.p
176521.56/23354.61	eprover: CPU time limit exceeded, terminating
176521.56/23354.61	% SZS status Ended for HL410112+5.p
176530.91/23355.82	% SZS status Started for HL410118+4.p
176530.91/23355.82	% SZS status GaveUp for HL410118+4.p
176530.91/23355.82	eprover: CPU time limit exceeded, terminating
176530.91/23355.82	% SZS status Ended for HL410118+4.p
176545.30/23357.52	% SZS status Started for HL410119+4.p
176545.30/23357.52	% SZS status GaveUp for HL410119+4.p
176545.30/23357.52	eprover: CPU time limit exceeded, terminating
176545.30/23357.52	% SZS status Ended for HL410119+4.p
176552.61/23358.50	% SZS status Started for HL410114+5.p
176552.61/23358.50	% SZS status GaveUp for HL410114+5.p
176552.61/23358.50	eprover: CPU time limit exceeded, terminating
176552.61/23358.50	% SZS status Ended for HL410114+5.p
176556.08/23358.90	% SZS status Started for HL410120+4.p
176556.08/23358.90	% SZS status GaveUp for HL410120+4.p
176556.08/23358.90	eprover: CPU time limit exceeded, terminating
176556.08/23358.90	% SZS status Ended for HL410120+4.p
176562.36/23359.69	% SZS status Started for HL410115+5.p
176562.36/23359.69	% SZS status GaveUp for HL410115+5.p
176562.36/23359.69	eprover: CPU time limit exceeded, terminating
176562.36/23359.69	% SZS status Ended for HL410115+5.p
176566.55/23360.49	% SZS status Started for HL410116+5.p
176566.55/23360.49	% SZS status GaveUp for HL410116+5.p
176566.55/23360.49	eprover: CPU time limit exceeded, terminating
176566.55/23360.49	% SZS status Ended for HL410116+5.p
176576.27/23361.59	% SZS status Started for HL410121+4.p
176576.27/23361.59	% SZS status GaveUp for HL410121+4.p
176576.27/23361.59	eprover: CPU time limit exceeded, terminating
176576.27/23361.59	% SZS status Ended for HL410121+4.p
176580.38/23361.97	% SZS status Started for HL410117+5.p
176580.38/23361.97	% SZS status GaveUp for HL410117+5.p
176580.38/23361.97	eprover: CPU time limit exceeded, terminating
176580.38/23361.97	% SZS status Ended for HL410117+5.p
176586.56/23362.75	% SZS status Started for HL410122+4.p
176586.56/23362.75	% SZS status GaveUp for HL410122+4.p
176586.56/23362.75	eprover: CPU time limit exceeded, terminating
176586.56/23362.75	% SZS status Ended for HL410122+4.p
176597.55/23364.09	% SZS status Started for HL410118+5.p
176597.55/23364.09	% SZS status GaveUp for HL410118+5.p
176597.55/23364.09	eprover: CPU time limit exceeded, terminating
176597.55/23364.09	% SZS status Ended for HL410118+5.p
176601.45/23364.61	% SZS status Started for HL410123+4.p
176601.45/23364.61	% SZS status GaveUp for HL410123+4.p
176601.45/23364.61	eprover: CPU time limit exceeded, terminating
176601.45/23364.61	% SZS status Ended for HL410123+4.p
176605.75/23365.12	% SZS status Started for HL410119+5.p
176605.75/23365.12	% SZS status GaveUp for HL410119+5.p
176605.75/23365.12	eprover: CPU time limit exceeded, terminating
176605.75/23365.12	% SZS status Ended for HL410119+5.p
176609.27/23365.78	% SZS status Started for HL410124+4.p
176609.27/23365.78	% SZS status GaveUp for HL410124+4.p
176609.27/23365.78	eprover: CPU time limit exceeded, terminating
176609.27/23365.78	% SZS status Ended for HL410124+4.p
176624.89/23367.65	% SZS status Started for HL410126+4.p
176624.89/23367.65	% SZS status GaveUp for HL410126+4.p
176624.89/23367.65	eprover: CPU time limit exceeded, terminating
176624.89/23367.65	% SZS status Ended for HL410126+4.p
176629.09/23368.09	% SZS status Started for HL410120+5.p
176629.09/23368.09	% SZS status GaveUp for HL410120+5.p
176629.09/23368.09	eprover: CPU time limit exceeded, terminating
176629.09/23368.09	% SZS status Ended for HL410120+5.p
176634.09/23368.82	% SZS status Started for HL410127+4.p
176634.09/23368.82	% SZS status GaveUp for HL410127+4.p
176634.09/23368.82	eprover: CPU time limit exceeded, terminating
176634.09/23368.82	% SZS status Ended for HL410127+4.p
176638.28/23369.27	% SZS status Started for HL410121+5.p
176638.28/23369.27	% SZS status GaveUp for HL410121+5.p
176638.28/23369.27	eprover: CPU time limit exceeded, terminating
176638.28/23369.27	% SZS status Ended for HL410121+5.p
176651.50/23370.89	% SZS status Started for HL410122+5.p
176651.50/23370.89	% SZS status GaveUp for HL410122+5.p
176651.50/23370.89	eprover: CPU time limit exceeded, terminating
176651.50/23370.89	% SZS status Ended for HL410122+5.p
176652.97/23371.11	% SZS status Started for HL410128+4.p
176652.97/23371.11	% SZS status GaveUp for HL410128+4.p
176652.97/23371.11	eprover: CPU time limit exceeded, terminating
176652.97/23371.11	% SZS status Ended for HL410128+4.p
176662.61/23372.32	% SZS status Started for HL410129+4.p
176662.61/23372.32	% SZS status GaveUp for HL410129+4.p
176662.61/23372.32	eprover: CPU time limit exceeded, terminating
176662.61/23372.32	% SZS status Ended for HL410129+4.p
176664.45/23372.54	% SZS status Started for HL410123+5.p
176664.45/23372.54	% SZS status GaveUp for HL410123+5.p
176664.45/23372.54	eprover: CPU time limit exceeded, terminating
176664.45/23372.54	% SZS status Ended for HL410123+5.p
176676.94/23374.16	% SZS status Started for HL410130+4.p
176676.94/23374.16	% SZS status GaveUp for HL410130+4.p
176676.94/23374.16	eprover: CPU time limit exceeded, terminating
176676.94/23374.16	% SZS status Ended for HL410130+4.p
176679.66/23374.47	% SZS status Started for HL410124+5.p
176679.66/23374.47	% SZS status GaveUp for HL410124+5.p
176679.66/23374.47	eprover: CPU time limit exceeded, terminating
176679.66/23374.47	% SZS status Ended for HL410124+5.p
176688.38/23375.57	% SZS status Started for HL410131+4.p
176688.38/23375.57	% SZS status GaveUp for HL410131+4.p
176688.38/23375.57	eprover: CPU time limit exceeded, terminating
176688.38/23375.57	% SZS status Ended for HL410131+4.p
176689.66/23375.73	% SZS status Started for HL410126+5.p
176689.66/23375.73	% SZS status GaveUp for HL410126+5.p
176689.66/23375.73	eprover: CPU time limit exceeded, terminating
176689.66/23375.73	% SZS status Ended for HL410126+5.p
176703.73/23377.50	% SZS status Started for HL410132+4.p
176703.73/23377.50	% SZS status GaveUp for HL410132+4.p
176703.73/23377.50	eprover: CPU time limit exceeded, terminating
176703.73/23377.50	% SZS status Ended for HL410132+4.p
176712.61/23378.66	% SZS status Started for HL410127+5.p
176712.61/23378.66	% SZS status GaveUp for HL410127+5.p
176712.61/23378.66	eprover: CPU time limit exceeded, terminating
176712.61/23378.66	% SZS status Ended for HL410127+5.p
176713.22/23378.76	% SZS status Started for HL410133+4.p
176713.22/23378.76	% SZS status GaveUp for HL410133+4.p
176713.22/23378.76	eprover: CPU time limit exceeded, terminating
176713.22/23378.76	% SZS status Ended for HL410133+4.p
176717.69/23379.20	% SZS status Started for HL410128+5.p
176717.69/23379.20	% SZS status GaveUp for HL410128+5.p
176717.69/23379.20	eprover: CPU time limit exceeded, terminating
176717.69/23379.20	% SZS status Ended for HL410128+5.p
176735.44/23381.46	% SZS status Started for HL410129+5.p
176735.44/23381.46	% SZS status GaveUp for HL410129+5.p
176735.44/23381.46	eprover: CPU time limit exceeded, terminating
176735.44/23381.46	% SZS status Ended for HL410129+5.p
176737.23/23381.69	% SZS status Started for HL410134+4.p
176737.23/23381.69	% SZS status GaveUp for HL410134+4.p
176737.23/23381.69	eprover: CPU time limit exceeded, terminating
176737.23/23381.69	% SZS status Ended for HL410134+4.p
176741.14/23382.25	% SZS status Started for HL410135+4.p
176741.14/23382.25	% SZS status GaveUp for HL410135+4.p
176741.14/23382.25	eprover: CPU time limit exceeded, terminating
176741.14/23382.25	% SZS status Ended for HL410135+4.p
176745.52/23382.71	% SZS status Started for HL410130+5.p
176745.52/23382.71	% SZS status GaveUp for HL410130+5.p
176745.52/23382.71	eprover: CPU time limit exceeded, terminating
176745.52/23382.71	% SZS status Ended for HL410130+5.p
176760.19/23384.60	% SZS status Started for HL410131+5.p
176760.19/23384.60	% SZS status GaveUp for HL410131+5.p
176760.19/23384.60	eprover: CPU time limit exceeded, terminating
176760.19/23384.60	% SZS status Ended for HL410131+5.p
176761.75/23384.75	% SZS status Started for HL410136+4.p
176761.75/23384.75	% SZS status GaveUp for HL410136+4.p
176761.75/23384.75	eprover: CPU time limit exceeded, terminating
176761.75/23384.75	% SZS status Ended for HL410136+4.p
176769.50/23385.76	% SZS status Started for HL410137+4.p
176769.50/23385.76	% SZS status GaveUp for HL410137+4.p
176769.50/23385.76	eprover: CPU time limit exceeded, terminating
176769.50/23385.76	% SZS status Ended for HL410137+4.p
176770.98/23385.96	% SZS status Started for HL410132+5.p
176770.98/23385.96	% SZS status GaveUp for HL410132+5.p
176770.98/23385.96	eprover: CPU time limit exceeded, terminating
176770.98/23385.96	% SZS status Ended for HL410132+5.p
176785.88/23387.78	% SZS status Started for HL410139+4.p
176785.88/23387.78	% SZS status GaveUp for HL410139+4.p
176785.88/23387.78	eprover: CPU time limit exceeded, terminating
176785.88/23387.78	% SZS status Ended for HL410139+4.p
176785.88/23387.90	% SZS status Started for HL410133+5.p
176785.88/23387.90	% SZS status GaveUp for HL410133+5.p
176785.88/23387.90	eprover: CPU time limit exceeded, terminating
176785.88/23387.90	% SZS status Ended for HL410133+5.p
176802.83/23388.80	% SZS status Started for HL410139+5.p
176802.83/23388.80	% SZS status GaveUp for HL410139+5.p
176802.83/23388.80	eprover: CPU time limit exceeded, terminating
176802.83/23388.80	% SZS status Ended for HL410139+5.p
176803.84/23389.01	% SZS status Started for HL410141+4.p
176803.84/23389.01	% SZS status GaveUp for HL410141+4.p
176803.84/23389.01	eprover: CPU time limit exceeded, terminating
176803.84/23389.01	% SZS status Ended for HL410141+4.p
176806.34/23389.20	% SZS status Started for HL410134+5.p
176806.34/23389.20	% SZS status GaveUp for HL410134+5.p
176806.34/23389.20	eprover: CPU time limit exceeded, terminating
176806.34/23389.20	% SZS status Ended for HL410134+5.p
176820.16/23390.93	% SZS status Started for HL410142+4.p
176820.16/23390.93	% SZS status GaveUp for HL410142+4.p
176820.16/23390.93	eprover: CPU time limit exceeded, terminating
176820.16/23390.93	% SZS status Ended for HL410142+4.p
176820.16/23390.96	% SZS status Started for HL410141+5.p
176820.16/23390.96	% SZS status GaveUp for HL410141+5.p
176820.16/23390.96	eprover: CPU time limit exceeded, terminating
176820.16/23390.96	% SZS status Ended for HL410141+5.p
176827.31/23391.84	% SZS status Started for HL410142+5.p
176827.31/23391.84	% SZS status GaveUp for HL410142+5.p
176827.31/23391.84	eprover: CPU time limit exceeded, terminating
176827.31/23391.84	% SZS status Ended for HL410142+5.p
176827.72/23391.95	% SZS status Started for HL410135+5.p
176827.72/23391.95	% SZS status GaveUp for HL410135+5.p
176827.72/23391.95	eprover: CPU time limit exceeded, terminating
176827.72/23391.95	% SZS status Ended for HL410135+5.p
176828.02/23392.05	% SZS status Started for HL410143+4.p
176828.02/23392.05	% SZS status GaveUp for HL410143+4.p
176828.02/23392.05	eprover: CPU time limit exceeded, terminating
176828.02/23392.05	% SZS status Ended for HL410143+4.p
176830.55/23392.25	% SZS status Started for HL410143+5.p
176830.55/23392.25	% SZS status GaveUp for HL410143+5.p
176830.55/23392.25	eprover: CPU time limit exceeded, terminating
176830.55/23392.25	% SZS status Ended for HL410143+5.p
176833.36/23392.76	% SZS status Started for HL410136+5.p
176833.36/23392.76	% SZS status GaveUp for HL410136+5.p
176833.36/23392.76	eprover: CPU time limit exceeded, terminating
176833.36/23392.76	% SZS status Ended for HL410136+5.p
176843.92/23394.00	% SZS status Started for HL410144+5.p
176843.92/23394.00	% SZS status GaveUp for HL410144+5.p
176843.92/23394.00	eprover: CPU time limit exceeded, terminating
176843.92/23394.00	% SZS status Ended for HL410144+5.p
176843.92/23394.01	% SZS status Started for HL410144+4.p
176843.92/23394.01	% SZS status GaveUp for HL410144+4.p
176843.92/23394.01	eprover: CPU time limit exceeded, terminating
176843.92/23394.01	% SZS status Ended for HL410144+4.p
176851.09/23394.87	% SZS status Started for HL410146+4.p
176851.09/23394.87	% SZS status GaveUp for HL410146+4.p
176851.09/23394.87	eprover: CPU time limit exceeded, terminating
176851.09/23394.87	% SZS status Ended for HL410146+4.p
176851.75/23394.99	% SZS status Started for HL410146+5.p
176851.75/23394.99	% SZS status GaveUp for HL410146+5.p
176851.75/23394.99	eprover: CPU time limit exceeded, terminating
176851.75/23394.99	% SZS status Ended for HL410146+5.p
176852.92/23395.10	% SZS status Started for HL410147+4.p
176852.92/23395.10	% SZS status GaveUp for HL410147+4.p
176852.92/23395.10	eprover: CPU time limit exceeded, terminating
176852.92/23395.10	% SZS status Ended for HL410147+4.p
176854.50/23395.29	% SZS status Started for HL410147+5.p
176854.50/23395.29	% SZS status GaveUp for HL410147+5.p
176854.50/23395.29	eprover: CPU time limit exceeded, terminating
176854.50/23395.29	% SZS status Ended for HL410147+5.p
176858.98/23395.82	% SZS status Started for HL410137+5.p
176858.98/23395.82	% SZS status GaveUp for HL410137+5.p
176858.98/23395.82	eprover: CPU time limit exceeded, terminating
176858.98/23395.82	% SZS status Ended for HL410137+5.p
176859.61/23395.88	% SZS status Started for HL410148+4.p
176859.61/23395.88	% SZS status GaveUp for HL410148+4.p
176859.61/23395.88	eprover: CPU time limit exceeded, terminating
176859.61/23395.88	% SZS status Ended for HL410148+4.p
176868.38/23397.03	% SZS status Started for HL410148+5.p
176868.38/23397.03	% SZS status GaveUp for HL410148+5.p
176868.38/23397.03	eprover: CPU time limit exceeded, terminating
176868.38/23397.03	% SZS status Ended for HL410148+5.p
176868.38/23397.05	% SZS status Started for HL410149+4.p
176868.38/23397.05	% SZS status GaveUp for HL410149+4.p
176868.38/23397.05	eprover: CPU time limit exceeded, terminating
176868.38/23397.05	% SZS status Ended for HL410149+4.p
176875.86/23397.91	% SZS status Started for HL410149+5.p
176875.86/23397.91	% SZS status GaveUp for HL410149+5.p
176875.86/23397.91	eprover: CPU time limit exceeded, terminating
176875.86/23397.91	% SZS status Ended for HL410149+5.p
176877.23/23398.14	% SZS status Started for HL410150+5.p
176877.23/23398.14	% SZS status GaveUp for HL410150+5.p
176877.23/23398.14	eprover: CPU time limit exceeded, terminating
176877.23/23398.14	% SZS status Ended for HL410150+5.p
176877.23/23398.18	% SZS status Started for HL410150+4.p
176877.23/23398.18	% SZS status GaveUp for HL410150+4.p
176877.23/23398.18	eprover: CPU time limit exceeded, terminating
176877.23/23398.18	% SZS status Ended for HL410150+4.p
176878.44/23398.33	% SZS status Started for HL410151+4.p
176878.44/23398.33	% SZS status GaveUp for HL410151+4.p
176878.44/23398.33	eprover: CPU time limit exceeded, terminating
176878.44/23398.33	% SZS status Ended for HL410151+4.p
176882.77/23398.85	% SZS status Started for HL410151+5.p
176882.77/23398.85	% SZS status GaveUp for HL410151+5.p
176882.77/23398.85	eprover: CPU time limit exceeded, terminating
176882.77/23398.85	% SZS status Ended for HL410151+5.p
176883.88/23398.92	% SZS status Started for HL410152+4.p
176883.88/23398.92	% SZS status GaveUp for HL410152+4.p
176883.88/23398.92	eprover: CPU time limit exceeded, terminating
176883.88/23398.92	% SZS status Ended for HL410152+4.p
176892.89/23400.06	% SZS status Started for HL410152+5.p
176892.89/23400.06	% SZS status GaveUp for HL410152+5.p
176892.89/23400.06	eprover: CPU time limit exceeded, terminating
176892.89/23400.06	% SZS status Ended for HL410152+5.p
176892.89/23400.09	% SZS status Started for HL410153+4.p
176892.89/23400.09	% SZS status GaveUp for HL410153+4.p
176892.89/23400.09	eprover: CPU time limit exceeded, terminating
176892.89/23400.09	% SZS status Ended for HL410153+4.p
176899.55/23400.95	% SZS status Started for HL410153+5.p
176899.55/23400.95	% SZS status GaveUp for HL410153+5.p
176899.55/23400.95	eprover: CPU time limit exceeded, terminating
176899.55/23400.95	% SZS status Ended for HL410153+5.p
176901.75/23401.21	% SZS status Started for HL410154+4.p
176901.75/23401.21	% SZS status GaveUp for HL410154+4.p
176901.75/23401.21	eprover: CPU time limit exceeded, terminating
176901.75/23401.21	% SZS status Ended for HL410154+4.p
176901.75/23401.22	% SZS status Started for HL410154+5.p
176901.75/23401.22	% SZS status GaveUp for HL410154+5.p
176901.75/23401.22	eprover: CPU time limit exceeded, terminating
176901.75/23401.22	% SZS status Ended for HL410154+5.p
176902.45/23401.37	% SZS status Started for HL410155+4.p
176902.45/23401.37	% SZS status GaveUp for HL410155+4.p
176902.45/23401.37	eprover: CPU time limit exceeded, terminating
176902.45/23401.37	% SZS status Ended for HL410155+4.p
176907.59/23401.95	% SZS status Started for HL410157+4.p
176907.59/23401.95	% SZS status GaveUp for HL410157+4.p
176907.59/23401.95	eprover: CPU time limit exceeded, terminating
176907.59/23401.95	% SZS status Ended for HL410157+4.p
176908.39/23402.02	% SZS status Started for HL410155+5.p
176908.39/23402.02	% SZS status GaveUp for HL410155+5.p
176908.39/23402.02	eprover: CPU time limit exceeded, terminating
176908.39/23402.02	% SZS status Ended for HL410155+5.p
176916.91/23403.10	% SZS status Started for HL410157+5.p
176916.91/23403.10	% SZS status GaveUp for HL410157+5.p
176916.91/23403.10	eprover: CPU time limit exceeded, terminating
176916.91/23403.10	% SZS status Ended for HL410157+5.p
176917.27/23403.12	% SZS status Started for HL410158+4.p
176917.27/23403.12	% SZS status GaveUp for HL410158+4.p
176917.27/23403.12	eprover: CPU time limit exceeded, terminating
176917.27/23403.12	% SZS status Ended for HL410158+4.p
176923.84/23403.99	% SZS status Started for HL410158+5.p
176923.84/23403.99	% SZS status GaveUp for HL410158+5.p
176923.84/23403.99	eprover: CPU time limit exceeded, terminating
176923.84/23403.99	% SZS status Ended for HL410158+5.p
176926.22/23404.25	% SZS status Started for HL410159+4.p
176926.22/23404.25	% SZS status GaveUp for HL410159+4.p
176926.22/23404.25	eprover: CPU time limit exceeded, terminating
176926.22/23404.25	% SZS status Ended for HL410159+4.p
176926.22/23404.25	% SZS status Started for HL410159+5.p
176926.22/23404.25	% SZS status GaveUp for HL410159+5.p
176926.22/23404.25	eprover: CPU time limit exceeded, terminating
176926.22/23404.25	% SZS status Ended for HL410159+5.p
176927.09/23404.41	% SZS status Started for HL410161+4.p
176927.09/23404.41	% SZS status GaveUp for HL410161+4.p
176927.09/23404.41	eprover: CPU time limit exceeded, terminating
176927.09/23404.41	% SZS status Ended for HL410161+4.p
176932.06/23405.07	% SZS status Started for HL410163+4.p
176932.06/23405.07	% SZS status GaveUp for HL410163+4.p
176932.06/23405.07	eprover: CPU time limit exceeded, terminating
176932.06/23405.07	% SZS status Ended for HL410163+4.p
176933.12/23405.12	% SZS status Started for HL410161+5.p
176933.12/23405.12	% SZS status GaveUp for HL410161+5.p
176933.12/23405.12	eprover: CPU time limit exceeded, terminating
176933.12/23405.12	% SZS status Ended for HL410161+5.p
176941.16/23406.13	% SZS status Started for HL410163+5.p
176941.16/23406.13	% SZS status GaveUp for HL410163+5.p
176941.16/23406.13	eprover: CPU time limit exceeded, terminating
176941.16/23406.13	% SZS status Ended for HL410163+5.p
176941.16/23406.16	% SZS status Started for HL410164+4.p
176941.16/23406.16	% SZS status GaveUp for HL410164+4.p
176941.16/23406.16	eprover: CPU time limit exceeded, terminating
176941.16/23406.16	% SZS status Ended for HL410164+4.p
176948.33/23407.03	% SZS status Started for HL410164+5.p
176948.33/23407.03	% SZS status GaveUp for HL410164+5.p
176948.33/23407.03	eprover: CPU time limit exceeded, terminating
176948.33/23407.03	% SZS status Ended for HL410164+5.p
176950.08/23407.28	% SZS status Started for HL410165+4.p
176950.08/23407.28	% SZS status GaveUp for HL410165+4.p
176950.08/23407.28	eprover: CPU time limit exceeded, terminating
176950.08/23407.28	% SZS status Ended for HL410165+4.p
176950.08/23407.29	% SZS status Started for HL410165+5.p
176950.08/23407.29	% SZS status GaveUp for HL410165+5.p
176950.08/23407.29	eprover: CPU time limit exceeded, terminating
176950.08/23407.29	% SZS status Ended for HL410165+5.p
176950.84/23407.45	% SZS status Started for HL410166+4.p
176950.84/23407.45	% SZS status GaveUp for HL410166+4.p
176950.84/23407.45	eprover: CPU time limit exceeded, terminating
176950.84/23407.45	% SZS status Ended for HL410166+4.p
176957.22/23408.18	% SZS status Started for HL410166+5.p
176957.22/23408.18	% SZS status GaveUp for HL410166+5.p
176957.22/23408.18	eprover: CPU time limit exceeded, terminating
176957.22/23408.18	% SZS status Ended for HL410166+5.p
176957.22/23408.20	% SZS status Started for HL410167+4.p
176957.22/23408.20	% SZS status GaveUp for HL410167+4.p
176957.22/23408.20	eprover: CPU time limit exceeded, terminating
176957.22/23408.20	% SZS status Ended for HL410167+4.p
176964.80/23409.18	% SZS status Started for HL410167+5.p
176964.80/23409.18	% SZS status GaveUp for HL410167+5.p
176964.80/23409.18	eprover: CPU time limit exceeded, terminating
176964.80/23409.18	% SZS status Ended for HL410167+5.p
176965.58/23409.20	% SZS status Started for HL410168+4.p
176965.58/23409.20	% SZS status GaveUp for HL410168+4.p
176965.58/23409.20	eprover: CPU time limit exceeded, terminating
176965.58/23409.20	% SZS status Ended for HL410168+4.p
176971.98/23410.06	% SZS status Started for HL410168+5.p
176971.98/23410.06	% SZS status GaveUp for HL410168+5.p
176971.98/23410.06	eprover: CPU time limit exceeded, terminating
176971.98/23410.06	% SZS status Ended for HL410168+5.p
176974.00/23410.31	% SZS status Started for HL410169+4.p
176974.00/23410.31	% SZS status GaveUp for HL410169+4.p
176974.00/23410.31	eprover: CPU time limit exceeded, terminating
176974.00/23410.31	% SZS status Ended for HL410169+4.p
176974.62/23410.33	% SZS status Started for HL410169+5.p
176974.62/23410.33	% SZS status GaveUp for HL410169+5.p
176974.62/23410.33	eprover: CPU time limit exceeded, terminating
176974.62/23410.33	% SZS status Ended for HL410169+5.p
176975.41/23410.49	% SZS status Started for HL410170+4.p
176975.41/23410.49	% SZS status GaveUp for HL410170+4.p
176975.41/23410.49	eprover: CPU time limit exceeded, terminating
176975.41/23410.49	% SZS status Ended for HL410170+4.p
176981.53/23411.22	% SZS status Started for HL410170+5.p
176981.53/23411.22	% SZS status GaveUp for HL410170+5.p
176981.53/23411.22	eprover: CPU time limit exceeded, terminating
176981.53/23411.22	% SZS status Ended for HL410170+5.p
176982.70/23411.38	% SZS status Started for HL410171+4.p
176982.70/23411.38	% SZS status GaveUp for HL410171+4.p
176982.70/23411.38	eprover: CPU time limit exceeded, terminating
176982.70/23411.38	% SZS status Ended for HL410171+4.p
176989.39/23412.21	% SZS status Started for HL410171+5.p
176989.39/23412.21	% SZS status GaveUp for HL410171+5.p
176989.39/23412.21	eprover: CPU time limit exceeded, terminating
176989.39/23412.21	% SZS status Ended for HL410171+5.p
176989.39/23412.23	% SZS status Started for HL410172+4.p
176989.39/23412.23	% SZS status GaveUp for HL410172+4.p
176989.39/23412.23	eprover: CPU time limit exceeded, terminating
176989.39/23412.23	% SZS status Ended for HL410172+4.p
176996.11/23413.10	% SZS status Started for HL410172+5.p
176996.11/23413.10	% SZS status GaveUp for HL410172+5.p
176996.11/23413.10	eprover: CPU time limit exceeded, terminating
176996.11/23413.10	% SZS status Ended for HL410172+5.p
176998.31/23413.34	% SZS status Started for HL410173+4.p
176998.31/23413.34	% SZS status GaveUp for HL410173+4.p
176998.31/23413.34	eprover: CPU time limit exceeded, terminating
176998.31/23413.34	% SZS status Ended for HL410173+4.p
176998.31/23413.38	% SZS status Started for HL410173+5.p
176998.31/23413.38	% SZS status GaveUp for HL410173+5.p
176998.31/23413.38	eprover: CPU time limit exceeded, terminating
176998.31/23413.38	% SZS status Ended for HL410173+5.p
177000.75/23413.64	% SZS status Started for HL410174+4.p
177000.75/23413.64	% SZS status GaveUp for HL410174+4.p
177000.75/23413.64	eprover: CPU time limit exceeded, terminating
177000.75/23413.64	% SZS status Ended for HL410174+4.p
177005.75/23414.26	% SZS status Started for HL410174+5.p
177005.75/23414.26	% SZS status GaveUp for HL410174+5.p
177005.75/23414.26	eprover: CPU time limit exceeded, terminating
177005.75/23414.26	% SZS status Ended for HL410174+5.p
177006.50/23414.42	% SZS status Started for HL410175+4.p
177006.50/23414.42	% SZS status GaveUp for HL410175+4.p
177006.50/23414.42	eprover: CPU time limit exceeded, terminating
177006.50/23414.42	% SZS status Ended for HL410175+4.p
177013.61/23415.24	% SZS status Started for HL410175+5.p
177013.61/23415.24	% SZS status GaveUp for HL410175+5.p
177013.61/23415.24	eprover: CPU time limit exceeded, terminating
177013.61/23415.24	% SZS status Ended for HL410175+5.p
177013.61/23415.28	% SZS status Started for HL410176+4.p
177013.61/23415.28	% SZS status GaveUp for HL410176+4.p
177013.61/23415.28	eprover: CPU time limit exceeded, terminating
177013.61/23415.28	% SZS status Ended for HL410176+4.p
177020.61/23416.14	% SZS status Started for HL410176+5.p
177020.61/23416.14	% SZS status GaveUp for HL410176+5.p
177020.61/23416.14	eprover: CPU time limit exceeded, terminating
177020.61/23416.14	% SZS status Ended for HL410176+5.p
177022.45/23416.38	% SZS status Started for HL410177+4.p
177022.45/23416.38	% SZS status GaveUp for HL410177+4.p
177022.45/23416.38	eprover: CPU time limit exceeded, terminating
177022.45/23416.38	% SZS status Ended for HL410177+4.p
177023.22/23416.50	% SZS status Started for HL410177+5.p
177023.22/23416.50	% SZS status GaveUp for HL410177+5.p
177023.22/23416.50	eprover: CPU time limit exceeded, terminating
177023.22/23416.50	% SZS status Ended for HL410177+5.p
177024.67/23416.68	% SZS status Started for HL410178+4.p
177024.67/23416.68	% SZS status GaveUp for HL410178+4.p
177024.67/23416.68	eprover: CPU time limit exceeded, terminating
177024.67/23416.68	% SZS status Ended for HL410178+4.p
177029.53/23417.30	% SZS status Started for HL410178+5.p
177029.53/23417.30	% SZS status GaveUp for HL410178+5.p
177029.53/23417.30	eprover: CPU time limit exceeded, terminating
177029.53/23417.30	% SZS status Ended for HL410178+5.p
177031.00/23417.45	% SZS status Started for HL410179+4.p
177031.00/23417.45	% SZS status GaveUp for HL410179+4.p
177031.00/23417.45	eprover: CPU time limit exceeded, terminating
177031.00/23417.45	% SZS status Ended for HL410179+4.p
177037.48/23418.28	% SZS status Started for HL410179+5.p
177037.48/23418.28	% SZS status GaveUp for HL410179+5.p
177037.48/23418.28	eprover: CPU time limit exceeded, terminating
177037.48/23418.28	% SZS status Ended for HL410179+5.p
177039.00/23418.46	% SZS status Started for HL410180+4.p
177039.00/23418.46	% SZS status GaveUp for HL410180+4.p
177039.00/23418.46	eprover: CPU time limit exceeded, terminating
177039.00/23418.46	% SZS status Ended for HL410180+4.p
177044.47/23419.17	% SZS status Started for HL410180+5.p
177044.47/23419.17	% SZS status GaveUp for HL410180+5.p
177044.47/23419.17	eprover: CPU time limit exceeded, terminating
177044.47/23419.17	% SZS status Ended for HL410180+5.p
177046.56/23419.41	% SZS status Started for HL410181+4.p
177046.56/23419.41	% SZS status GaveUp for HL410181+4.p
177046.56/23419.41	eprover: CPU time limit exceeded, terminating
177046.56/23419.41	% SZS status Ended for HL410181+4.p
177047.53/23419.53	% SZS status Started for HL410181+5.p
177047.53/23419.53	% SZS status GaveUp for HL410181+5.p
177047.53/23419.53	eprover: CPU time limit exceeded, terminating
177047.53/23419.53	% SZS status Ended for HL410181+5.p
177048.59/23419.72	% SZS status Started for HL410182+4.p
177048.59/23419.72	% SZS status GaveUp for HL410182+4.p
177048.59/23419.72	eprover: CPU time limit exceeded, terminating
177048.59/23419.72	% SZS status Ended for HL410182+4.p
177053.75/23420.33	% SZS status Started for HL410182+5.p
177053.75/23420.33	% SZS status GaveUp for HL410182+5.p
177053.75/23420.33	eprover: CPU time limit exceeded, terminating
177053.75/23420.33	% SZS status Ended for HL410182+5.p
177055.12/23420.49	% SZS status Started for HL410183+4.p
177055.12/23420.49	% SZS status GaveUp for HL410183+4.p
177055.12/23420.49	eprover: CPU time limit exceeded, terminating
177055.12/23420.49	% SZS status Ended for HL410183+4.p
177062.30/23421.38	% SZS status Started for HL410183+5.p
177062.30/23421.38	% SZS status GaveUp for HL410183+5.p
177062.30/23421.38	eprover: CPU time limit exceeded, terminating
177062.30/23421.38	% SZS status Ended for HL410183+5.p
177063.02/23421.52	% SZS status Started for HL410184+4.p
177063.02/23421.52	% SZS status GaveUp for HL410184+4.p
177063.02/23421.52	eprover: CPU time limit exceeded, terminating
177063.02/23421.52	% SZS status Ended for HL410184+4.p
177069.05/23422.23	% SZS status Started for HL410184+5.p
177069.05/23422.23	% SZS status GaveUp for HL410184+5.p
177069.05/23422.23	eprover: CPU time limit exceeded, terminating
177069.05/23422.23	% SZS status Ended for HL410184+5.p
177070.78/23422.47	% SZS status Started for HL410186+4.p
177070.78/23422.47	% SZS status GaveUp for HL410186+4.p
177070.78/23422.47	eprover: CPU time limit exceeded, terminating
177070.78/23422.47	% SZS status Ended for HL410186+4.p
177071.27/23422.57	% SZS status Started for HL410186+5.p
177071.27/23422.57	% SZS status GaveUp for HL410186+5.p
177071.27/23422.57	eprover: CPU time limit exceeded, terminating
177071.27/23422.57	% SZS status Ended for HL410186+5.p
177072.84/23422.76	% SZS status Started for HL410187+4.p
177072.84/23422.76	% SZS status GaveUp for HL410187+4.p
177072.84/23422.76	eprover: CPU time limit exceeded, terminating
177072.84/23422.76	% SZS status Ended for HL410187+4.p
177077.75/23423.37	% SZS status Started for HL410187+5.p
177077.75/23423.37	% SZS status GaveUp for HL410187+5.p
177077.75/23423.37	eprover: CPU time limit exceeded, terminating
177077.75/23423.37	% SZS status Ended for HL410187+5.p
177079.34/23423.53	% SZS status Started for HL410188+4.p
177079.34/23423.53	% SZS status GaveUp for HL410188+4.p
177079.34/23423.53	eprover: CPU time limit exceeded, terminating
177079.34/23423.53	% SZS status Ended for HL410188+4.p
177087.66/23424.56	% SZS status Started for HL410189+4.p
177087.66/23424.56	% SZS status GaveUp for HL410189+4.p
177087.66/23424.56	eprover: CPU time limit exceeded, terminating
177087.66/23424.56	% SZS status Ended for HL410189+4.p
177087.66/23424.57	% SZS status Started for HL410188+5.p
177087.66/23424.57	% SZS status GaveUp for HL410188+5.p
177087.66/23424.57	eprover: CPU time limit exceeded, terminating
177087.66/23424.57	% SZS status Ended for HL410188+5.p
177093.25/23425.26	% SZS status Started for HL410189+5.p
177093.25/23425.26	% SZS status GaveUp for HL410189+5.p
177093.25/23425.26	eprover: CPU time limit exceeded, terminating
177093.25/23425.26	% SZS status Ended for HL410189+5.p
177095.06/23425.51	% SZS status Started for HL410190+4.p
177095.06/23425.51	% SZS status GaveUp for HL410190+4.p
177095.06/23425.51	eprover: CPU time limit exceeded, terminating
177095.06/23425.51	% SZS status Ended for HL410190+4.p
177095.75/23425.61	% SZS status Started for HL410190+5.p
177095.75/23425.61	% SZS status GaveUp for HL410190+5.p
177095.75/23425.61	eprover: CPU time limit exceeded, terminating
177095.75/23425.61	% SZS status Ended for HL410190+5.p
177096.89/23425.80	% SZS status Started for HL410191+4.p
177096.89/23425.80	% SZS status GaveUp for HL410191+4.p
177096.89/23425.80	eprover: CPU time limit exceeded, terminating
177096.89/23425.80	% SZS status Ended for HL410191+4.p
177102.19/23426.41	% SZS status Started for HL410191+5.p
177102.19/23426.41	% SZS status GaveUp for HL410191+5.p
177102.19/23426.41	eprover: CPU time limit exceeded, terminating
177102.19/23426.41	% SZS status Ended for HL410191+5.p
177103.30/23426.57	% SZS status Started for HL410192+4.p
177103.30/23426.57	% SZS status GaveUp for HL410192+4.p
177103.30/23426.57	eprover: CPU time limit exceeded, terminating
177103.30/23426.57	% SZS status Ended for HL410192+4.p
177111.42/23427.59	% SZS status Started for HL410192+5.p
177111.42/23427.59	% SZS status GaveUp for HL410192+5.p
177111.42/23427.59	eprover: CPU time limit exceeded, terminating
177111.42/23427.59	% SZS status Ended for HL410192+5.p
177112.25/23427.74	% SZS status Started for HL410193+4.p
177112.25/23427.74	% SZS status GaveUp for HL410193+4.p
177112.25/23427.74	eprover: CPU time limit exceeded, terminating
177112.25/23427.74	% SZS status Ended for HL410193+4.p
177116.81/23428.30	% SZS status Started for HL410193+5.p
177116.81/23428.30	% SZS status GaveUp for HL410193+5.p
177116.81/23428.30	eprover: CPU time limit exceeded, terminating
177116.81/23428.30	% SZS status Ended for HL410193+5.p
177119.11/23428.54	% SZS status Started for HL410194+4.p
177119.11/23428.54	% SZS status GaveUp for HL410194+4.p
177119.11/23428.54	eprover: CPU time limit exceeded, terminating
177119.11/23428.54	% SZS status Ended for HL410194+4.p
177119.98/23428.65	% SZS status Started for HL410194+5.p
177119.98/23428.65	% SZS status GaveUp for HL410194+5.p
177119.98/23428.65	eprover: CPU time limit exceeded, terminating
177119.98/23428.65	% SZS status Ended for HL410194+5.p
177121.11/23428.84	% SZS status Started for HL410195+4.p
177121.11/23428.84	% SZS status GaveUp for HL410195+4.p
177121.11/23428.84	eprover: CPU time limit exceeded, terminating
177121.11/23428.84	% SZS status Ended for HL410195+4.p
177126.31/23429.44	% SZS status Started for HL410195+5.p
177126.31/23429.44	% SZS status GaveUp for HL410195+5.p
177126.31/23429.44	eprover: CPU time limit exceeded, terminating
177126.31/23429.44	% SZS status Ended for HL410195+5.p
177127.61/23429.61	% SZS status Started for HL410196+4.p
177127.61/23429.61	% SZS status GaveUp for HL410196+4.p
177127.61/23429.61	eprover: CPU time limit exceeded, terminating
177127.61/23429.61	% SZS status Ended for HL410196+4.p
177135.86/23430.64	% SZS status Started for HL410196+5.p
177135.86/23430.64	% SZS status GaveUp for HL410196+5.p
177135.86/23430.64	eprover: CPU time limit exceeded, terminating
177135.86/23430.64	% SZS status Ended for HL410196+5.p
177137.62/23430.92	% SZS status Started for HL410197+4.p
177137.62/23430.92	% SZS status GaveUp for HL410197+4.p
177137.62/23430.92	eprover: CPU time limit exceeded, terminating
177137.62/23430.92	% SZS status Ended for HL410197+4.p
177140.84/23431.34	% SZS status Started for HL410197+5.p
177140.84/23431.34	% SZS status GaveUp for HL410197+5.p
177140.84/23431.34	eprover: CPU time limit exceeded, terminating
177140.84/23431.34	% SZS status Ended for HL410197+5.p
177143.06/23431.58	% SZS status Started for HL410198+4.p
177143.06/23431.58	% SZS status GaveUp for HL410198+4.p
177143.06/23431.58	eprover: CPU time limit exceeded, terminating
177143.06/23431.58	% SZS status Ended for HL410198+4.p
177143.69/23431.69	% SZS status Started for HL410198+5.p
177143.69/23431.69	% SZS status GaveUp for HL410198+5.p
177143.69/23431.69	eprover: CPU time limit exceeded, terminating
177143.69/23431.69	% SZS status Ended for HL410198+5.p
177145.62/23431.88	% SZS status Started for HL410199+4.p
177145.62/23431.88	% SZS status GaveUp for HL410199+4.p
177145.62/23431.88	eprover: CPU time limit exceeded, terminating
177145.62/23431.88	% SZS status Ended for HL410199+4.p
177150.17/23432.48	% SZS status Started for HL410199+5.p
177150.17/23432.48	% SZS status GaveUp for HL410199+5.p
177150.17/23432.48	eprover: CPU time limit exceeded, terminating
177150.17/23432.48	% SZS status Ended for HL410199+5.p
177151.22/23432.65	% SZS status Started for HL410201+4.p
177151.22/23432.65	% SZS status GaveUp for HL410201+4.p
177151.22/23432.65	eprover: CPU time limit exceeded, terminating
177151.22/23432.65	% SZS status Ended for HL410201+4.p
177160.06/23433.68	% SZS status Started for HL410201+5.p
177160.06/23433.68	% SZS status GaveUp for HL410201+5.p
177160.06/23433.68	eprover: CPU time limit exceeded, terminating
177160.06/23433.68	% SZS status Ended for HL410201+5.p
177162.16/23433.98	% SZS status Started for HL410202+4.p
177162.16/23433.98	% SZS status GaveUp for HL410202+4.p
177162.16/23433.98	eprover: CPU time limit exceeded, terminating
177162.16/23433.98	% SZS status Ended for HL410202+4.p
177165.06/23434.38	% SZS status Started for HL410202+5.p
177165.06/23434.38	% SZS status GaveUp for HL410202+5.p
177165.06/23434.38	eprover: CPU time limit exceeded, terminating
177165.06/23434.38	% SZS status Ended for HL410202+5.p
177167.80/23434.72	% SZS status Started for HL410205+4.p
177167.80/23434.72	% SZS status GaveUp for HL410205+4.p
177167.80/23434.72	eprover: CPU time limit exceeded, terminating
177167.80/23434.72	% SZS status Ended for HL410205+4.p
177167.80/23434.73	% SZS status Started for HL410205+5.p
177167.80/23434.73	% SZS status GaveUp for HL410205+5.p
177167.80/23434.73	eprover: CPU time limit exceeded, terminating
177167.80/23434.73	% SZS status Ended for HL410205+5.p
177169.55/23434.92	% SZS status Started for HL410206+4.p
177169.55/23434.92	% SZS status GaveUp for HL410206+4.p
177169.55/23434.92	eprover: CPU time limit exceeded, terminating
177169.55/23434.92	% SZS status Ended for HL410206+4.p
177174.41/23435.52	% SZS status Started for HL410206+5.p
177174.41/23435.52	% SZS status GaveUp for HL410206+5.p
177174.41/23435.52	eprover: CPU time limit exceeded, terminating
177174.41/23435.52	% SZS status Ended for HL410206+5.p
177176.02/23435.69	% SZS status Started for HL410207+4.p
177176.02/23435.69	% SZS status GaveUp for HL410207+4.p
177176.02/23435.69	eprover: CPU time limit exceeded, terminating
177176.02/23435.69	% SZS status Ended for HL410207+4.p
177184.20/23436.72	% SZS status Started for HL410207+5.p
177184.20/23436.72	% SZS status GaveUp for HL410207+5.p
177184.20/23436.72	eprover: CPU time limit exceeded, terminating
177184.20/23436.72	% SZS status Ended for HL410207+5.p
177187.25/23437.15	% SZS status Started for HL410208+4.p
177187.25/23437.15	% SZS status GaveUp for HL410208+4.p
177187.25/23437.15	eprover: CPU time limit exceeded, terminating
177187.25/23437.15	% SZS status Ended for HL410208+4.p
177189.44/23437.42	% SZS status Started for HL410208+5.p
177189.44/23437.42	% SZS status GaveUp for HL410208+5.p
177189.44/23437.42	eprover: CPU time limit exceeded, terminating
177189.44/23437.42	% SZS status Ended for HL410208+5.p
177191.86/23437.75	% SZS status Started for HL410209+4.p
177191.86/23437.75	% SZS status GaveUp for HL410209+4.p
177191.86/23437.75	eprover: CPU time limit exceeded, terminating
177191.86/23437.75	% SZS status Ended for HL410209+4.p
177192.58/23437.78	% SZS status Started for HL410209+5.p
177192.58/23437.78	% SZS status GaveUp for HL410209+5.p
177192.58/23437.78	eprover: CPU time limit exceeded, terminating
177192.58/23437.78	% SZS status Ended for HL410209+5.p
177193.52/23437.96	% SZS status Started for HL410210+4.p
177193.52/23437.96	% SZS status GaveUp for HL410210+4.p
177193.52/23437.96	eprover: CPU time limit exceeded, terminating
177193.52/23437.96	% SZS status Ended for HL410210+4.p
177198.66/23438.55	% SZS status Started for HL410210+5.p
177198.66/23438.55	% SZS status GaveUp for HL410210+5.p
177198.66/23438.55	eprover: CPU time limit exceeded, terminating
177198.66/23438.55	% SZS status Ended for HL410210+5.p
177199.91/23438.72	% SZS status Started for HL410211+4.p
177199.91/23438.72	% SZS status GaveUp for HL410211+4.p
177199.91/23438.72	eprover: CPU time limit exceeded, terminating
177199.91/23438.72	% SZS status Ended for HL410211+4.p
177208.12/23439.76	% SZS status Started for HL410211+5.p
177208.12/23439.76	% SZS status GaveUp for HL410211+5.p
177208.12/23439.76	eprover: CPU time limit exceeded, terminating
177208.12/23439.76	% SZS status Ended for HL410211+5.p
177211.78/23440.19	% SZS status Started for HL410214+4.p
177211.78/23440.19	% SZS status GaveUp for HL410214+4.p
177211.78/23440.19	eprover: CPU time limit exceeded, terminating
177211.78/23440.19	% SZS status Ended for HL410214+4.p
177215.12/23440.62	% SZS status Started for HL410214+5.p
177215.12/23440.62	% SZS status GaveUp for HL410214+5.p
177215.12/23440.62	eprover: CPU time limit exceeded, terminating
177215.12/23440.62	% SZS status Ended for HL410214+5.p
177215.88/23440.79	% SZS status Started for HL410215+4.p
177215.88/23440.79	% SZS status GaveUp for HL410215+4.p
177215.88/23440.79	eprover: CPU time limit exceeded, terminating
177215.88/23440.79	% SZS status Ended for HL410215+4.p
177216.52/23440.83	% SZS status Started for HL410215+5.p
177216.52/23440.83	% SZS status GaveUp for HL410215+5.p
177216.52/23440.83	eprover: CPU time limit exceeded, terminating
177216.52/23440.83	% SZS status Ended for HL410215+5.p
177217.56/23440.99	% SZS status Started for HL410216+4.p
177217.56/23440.99	% SZS status GaveUp for HL410216+4.p
177217.56/23440.99	eprover: CPU time limit exceeded, terminating
177217.56/23440.99	% SZS status Ended for HL410216+4.p
177222.88/23441.59	% SZS status Started for HL410216+5.p
177222.88/23441.59	% SZS status GaveUp for HL410216+5.p
177222.88/23441.59	eprover: CPU time limit exceeded, terminating
177222.88/23441.59	% SZS status Ended for HL410216+5.p
177223.94/23441.76	% SZS status Started for HL410217+4.p
177223.94/23441.76	% SZS status GaveUp for HL410217+4.p
177223.94/23441.76	eprover: CPU time limit exceeded, terminating
177223.94/23441.76	% SZS status Ended for HL410217+4.p
177232.22/23442.79	% SZS status Started for HL410217+5.p
177232.22/23442.79	% SZS status GaveUp for HL410217+5.p
177232.22/23442.79	eprover: CPU time limit exceeded, terminating
177232.22/23442.79	% SZS status Ended for HL410217+5.p
177236.72/23443.33	% SZS status Started for HL410218+4.p
177236.72/23443.33	% SZS status GaveUp for HL410218+4.p
177236.72/23443.33	eprover: CPU time limit exceeded, terminating
177236.72/23443.33	% SZS status Ended for HL410218+4.p
177238.83/23443.66	% SZS status Started for HL410218+5.p
177238.83/23443.66	% SZS status GaveUp for HL410218+5.p
177238.83/23443.66	eprover: CPU time limit exceeded, terminating
177238.83/23443.66	% SZS status Ended for HL410218+5.p
177240.55/23443.82	% SZS status Started for HL410219+4.p
177240.55/23443.82	% SZS status GaveUp for HL410219+4.p
177240.55/23443.82	eprover: CPU time limit exceeded, terminating
177240.55/23443.82	% SZS status Ended for HL410219+4.p
177240.61/23443.87	% SZS status Started for HL410219+5.p
177240.61/23443.87	% SZS status GaveUp for HL410219+5.p
177240.61/23443.87	eprover: CPU time limit exceeded, terminating
177240.61/23443.87	% SZS status Ended for HL410219+5.p
177241.47/23444.03	% SZS status Started for HL410220+4.p
177241.47/23444.03	% SZS status GaveUp for HL410220+4.p
177241.47/23444.03	eprover: CPU time limit exceeded, terminating
177241.47/23444.03	% SZS status Ended for HL410220+4.p
177246.86/23444.62	% SZS status Started for HL410220+5.p
177246.86/23444.62	% SZS status GaveUp for HL410220+5.p
177246.86/23444.62	eprover: CPU time limit exceeded, terminating
177246.86/23444.62	% SZS status Ended for HL410220+5.p
177248.28/23444.80	% SZS status Started for HL410221+4.p
177248.28/23444.80	% SZS status GaveUp for HL410221+4.p
177248.28/23444.80	eprover: CPU time limit exceeded, terminating
177248.28/23444.80	% SZS status Ended for HL410221+4.p
177256.58/23445.84	% SZS status Started for HL410221+5.p
177256.58/23445.84	% SZS status GaveUp for HL410221+5.p
177256.58/23445.84	eprover: CPU time limit exceeded, terminating
177256.58/23445.84	% SZS status Ended for HL410221+5.p
177260.80/23446.36	% SZS status Started for HL410223+4.p
177260.80/23446.36	% SZS status GaveUp for HL410223+4.p
177260.80/23446.36	eprover: CPU time limit exceeded, terminating
177260.80/23446.36	% SZS status Ended for HL410223+4.p
177264.12/23446.77	% SZS status Started for HL410223+5.p
177264.12/23446.77	% SZS status GaveUp for HL410223+5.p
177264.12/23446.77	eprover: CPU time limit exceeded, terminating
177264.12/23446.77	% SZS status Ended for HL410223+5.p
177264.70/23446.86	% SZS status Started for HL410225+4.p
177264.70/23446.86	% SZS status GaveUp for HL410225+4.p
177264.70/23446.86	eprover: CPU time limit exceeded, terminating
177264.70/23446.86	% SZS status Ended for HL410225+4.p
177264.92/23446.91	% SZS status Started for HL410225+5.p
177264.92/23446.91	% SZS status GaveUp for HL410225+5.p
177264.92/23446.91	eprover: CPU time limit exceeded, terminating
177264.92/23446.91	% SZS status Ended for HL410225+5.p
177265.67/23447.08	% SZS status Started for HL410226+4.p
177265.67/23447.08	% SZS status GaveUp for HL410226+4.p
177265.67/23447.08	eprover: CPU time limit exceeded, terminating
177265.67/23447.08	% SZS status Ended for HL410226+4.p
177270.88/23447.65	% SZS status Started for HL410226+5.p
177270.88/23447.65	% SZS status GaveUp for HL410226+5.p
177270.88/23447.65	eprover: CPU time limit exceeded, terminating
177270.88/23447.65	% SZS status Ended for HL410226+5.p
177272.84/23447.92	% SZS status Started for HL410227+4.p
177272.84/23447.92	% SZS status GaveUp for HL410227+4.p
177272.84/23447.92	eprover: CPU time limit exceeded, terminating
177272.84/23447.92	% SZS status Ended for HL410227+4.p
177280.66/23448.88	% SZS status Started for HL410227+5.p
177280.66/23448.88	% SZS status GaveUp for HL410227+5.p
177280.66/23448.88	eprover: CPU time limit exceeded, terminating
177280.66/23448.88	% SZS status Ended for HL410227+5.p
177285.03/23449.40	% SZS status Started for HL410228+4.p
177285.03/23449.40	% SZS status GaveUp for HL410228+4.p
177285.03/23449.40	eprover: CPU time limit exceeded, terminating
177285.03/23449.40	% SZS status Ended for HL410228+4.p
177287.48/23449.80	% SZS status Started for HL410228+5.p
177287.48/23449.80	% SZS status GaveUp for HL410228+5.p
177287.48/23449.80	eprover: CPU time limit exceeded, terminating
177287.48/23449.80	% SZS status Ended for HL410228+5.p
177288.47/23449.90	% SZS status Started for HL410229+4.p
177288.47/23449.90	% SZS status GaveUp for HL410229+4.p
177288.47/23449.90	eprover: CPU time limit exceeded, terminating
177288.47/23449.90	% SZS status Ended for HL410229+4.p
177288.47/23449.95	% SZS status Started for HL410229+5.p
177288.47/23449.95	% SZS status GaveUp for HL410229+5.p
177288.47/23449.95	eprover: CPU time limit exceeded, terminating
177288.47/23449.95	% SZS status Ended for HL410229+5.p
177290.66/23450.14	% SZS status Started for HL410233+4.p
177290.66/23450.14	% SZS status GaveUp for HL410233+4.p
177290.66/23450.14	eprover: CPU time limit exceeded, terminating
177290.66/23450.14	% SZS status Ended for HL410233+4.p
177295.89/23450.85	% SZS status Started for HL410233+5.p
177295.89/23450.85	% SZS status GaveUp for HL410233+5.p
177295.89/23450.85	eprover: CPU time limit exceeded, terminating
177295.89/23450.85	% SZS status Ended for HL410233+5.p
177297.09/23450.96	% SZS status Started for HL410234+4.p
177297.09/23450.96	% SZS status GaveUp for HL410234+4.p
177297.09/23450.96	eprover: CPU time limit exceeded, terminating
177297.09/23450.96	% SZS status Ended for HL410234+4.p
177304.91/23451.91	% SZS status Started for HL410234+5.p
177304.91/23451.91	% SZS status GaveUp for HL410234+5.p
177304.91/23451.91	eprover: CPU time limit exceeded, terminating
177304.91/23451.91	% SZS status Ended for HL410234+5.p
177308.48/23452.44	% SZS status Started for HL410235+4.p
177308.48/23452.44	% SZS status GaveUp for HL410235+4.p
177308.48/23452.44	eprover: CPU time limit exceeded, terminating
177308.48/23452.44	% SZS status Ended for HL410235+4.p
177312.12/23452.84	% SZS status Started for HL410235+5.p
177312.12/23452.84	% SZS status GaveUp for HL410235+5.p
177312.12/23452.84	eprover: CPU time limit exceeded, terminating
177312.12/23452.84	% SZS status Ended for HL410235+5.p
177312.52/23452.93	% SZS status Started for HL410236+4.p
177312.52/23452.93	% SZS status GaveUp for HL410236+4.p
177312.52/23452.93	eprover: CPU time limit exceeded, terminating
177312.52/23452.93	% SZS status Ended for HL410236+4.p
177313.31/23452.99	% SZS status Started for HL410236+5.p
177313.31/23452.99	% SZS status GaveUp for HL410236+5.p
177313.31/23452.99	eprover: CPU time limit exceeded, terminating
177313.31/23452.99	% SZS status Ended for HL410236+5.p
177314.25/23453.18	% SZS status Started for HL410238+4.p
177314.25/23453.18	% SZS status GaveUp for HL410238+4.p
177314.25/23453.18	eprover: CPU time limit exceeded, terminating
177314.25/23453.18	% SZS status Ended for HL410238+4.p
177320.16/23453.89	% SZS status Started for HL410238+5.p
177320.16/23453.89	% SZS status GaveUp for HL410238+5.p
177320.16/23453.89	eprover: CPU time limit exceeded, terminating
177320.16/23453.89	% SZS status Ended for HL410238+5.p
177324.92/23454.15	% SZS status Started for HL410239+4.p
177324.92/23454.15	% SZS status GaveUp for HL410239+4.p
177324.92/23454.15	eprover: CPU time limit exceeded, terminating
177324.92/23454.15	% SZS status Ended for HL410239+4.p
177331.34/23454.95	% SZS status Started for HL410239+5.p
177331.34/23454.95	% SZS status GaveUp for HL410239+5.p
177331.34/23454.95	eprover: CPU time limit exceeded, terminating
177331.34/23454.95	% SZS status Ended for HL410239+5.p
177334.98/23455.48	% SZS status Started for HL410240+4.p
177334.98/23455.48	% SZS status GaveUp for HL410240+4.p
177334.98/23455.48	eprover: CPU time limit exceeded, terminating
177334.98/23455.48	% SZS status Ended for HL410240+4.p
177338.62/23455.88	% SZS status Started for HL410240+5.p
177338.62/23455.88	% SZS status GaveUp for HL410240+5.p
177338.62/23455.88	eprover: CPU time limit exceeded, terminating
177338.62/23455.88	% SZS status Ended for HL410240+5.p
177339.14/23455.97	% SZS status Started for HL410241+4.p
177339.14/23455.97	% SZS status GaveUp for HL410241+4.p
177339.14/23455.97	eprover: CPU time limit exceeded, terminating
177339.14/23455.97	% SZS status Ended for HL410241+4.p
177339.75/23456.03	% SZS status Started for HL410241+5.p
177339.75/23456.03	% SZS status GaveUp for HL410241+5.p
177339.75/23456.03	eprover: CPU time limit exceeded, terminating
177339.75/23456.03	% SZS status Ended for HL410241+5.p
177341.19/23456.22	% SZS status Started for HL410242+4.p
177341.19/23456.22	% SZS status GaveUp for HL410242+4.p
177341.19/23456.22	eprover: CPU time limit exceeded, terminating
177341.19/23456.22	% SZS status Ended for HL410242+4.p
177347.88/23457.08	% SZS status Started for HL410242+5.p
177347.88/23457.08	% SZS status GaveUp for HL410242+5.p
177347.88/23457.08	eprover: CPU time limit exceeded, terminating
177347.88/23457.08	% SZS status Ended for HL410242+5.p
177348.83/23457.19	% SZS status Started for HL410243+4.p
177348.83/23457.19	% SZS status GaveUp for HL410243+4.p
177348.83/23457.19	eprover: CPU time limit exceeded, terminating
177348.83/23457.19	% SZS status Ended for HL410243+4.p
177357.00/23458.22	% SZS status Started for HL410243+5.p
177357.00/23458.22	% SZS status GaveUp for HL410243+5.p
177357.00/23458.22	eprover: CPU time limit exceeded, terminating
177357.00/23458.22	% SZS status Ended for HL410243+5.p
177359.50/23458.52	% SZS status Started for HL410244+4.p
177359.50/23458.52	% SZS status GaveUp for HL410244+4.p
177359.50/23458.52	eprover: CPU time limit exceeded, terminating
177359.50/23458.52	% SZS status Ended for HL410244+4.p
177362.19/23458.92	% SZS status Started for HL410244+5.p
177362.19/23458.92	% SZS status GaveUp for HL410244+5.p
177362.19/23458.92	eprover: CPU time limit exceeded, terminating
177362.19/23458.92	% SZS status Ended for HL410244+5.p
177362.97/23459.01	% SZS status Started for HL410245+4.p
177362.97/23459.01	% SZS status GaveUp for HL410245+4.p
177362.97/23459.01	eprover: CPU time limit exceeded, terminating
177362.97/23459.01	% SZS status Ended for HL410245+4.p
177363.81/23459.07	% SZS status Started for HL410245+5.p
177363.81/23459.07	% SZS status GaveUp for HL410245+5.p
177363.81/23459.07	eprover: CPU time limit exceeded, terminating
177363.81/23459.07	% SZS status Ended for HL410245+5.p
177365.17/23459.26	% SZS status Started for HL410247+4.p
177365.17/23459.26	% SZS status GaveUp for HL410247+4.p
177365.17/23459.26	eprover: CPU time limit exceeded, terminating
177365.17/23459.26	% SZS status Ended for HL410247+4.p
177372.77/23460.19	% SZS status Started for HL410247+5.p
177372.77/23460.19	% SZS status GaveUp for HL410247+5.p
177372.77/23460.19	eprover: CPU time limit exceeded, terminating
177372.77/23460.19	% SZS status Ended for HL410247+5.p
177373.03/23460.23	% SZS status Started for HL410248+4.p
177373.03/23460.23	% SZS status GaveUp for HL410248+4.p
177373.03/23460.23	eprover: CPU time limit exceeded, terminating
177373.03/23460.23	% SZS status Ended for HL410248+4.p
177381.22/23461.26	% SZS status Started for HL410248+5.p
177381.22/23461.26	% SZS status GaveUp for HL410248+5.p
177381.22/23461.26	eprover: CPU time limit exceeded, terminating
177381.22/23461.26	% SZS status Ended for HL410248+5.p
177383.25/23461.55	% SZS status Started for HL410249+4.p
177383.25/23461.55	% SZS status GaveUp for HL410249+4.p
177383.25/23461.55	eprover: CPU time limit exceeded, terminating
177383.25/23461.55	% SZS status Ended for HL410249+4.p
177386.44/23461.96	% SZS status Started for HL410249+5.p
177386.44/23461.96	% SZS status GaveUp for HL410249+5.p
177386.44/23461.96	eprover: CPU time limit exceeded, terminating
177386.44/23461.96	% SZS status Ended for HL410249+5.p
177388.05/23462.12	% SZS status Started for HL410250+5.p
177388.05/23462.12	% SZS status GaveUp for HL410250+5.p
177388.05/23462.12	eprover: CPU time limit exceeded, terminating
177388.05/23462.12	% SZS status Ended for HL410250+5.p
177388.05/23462.15	% SZS status Started for HL410250+4.p
177388.05/23462.15	% SZS status GaveUp for HL410250+4.p
177388.05/23462.15	eprover: CPU time limit exceeded, terminating
177388.05/23462.15	% SZS status Ended for HL410250+4.p
177389.05/23462.30	% SZS status Started for HL410251+4.p
177389.05/23462.30	% SZS status GaveUp for HL410251+4.p
177389.05/23462.30	eprover: CPU time limit exceeded, terminating
177389.05/23462.30	% SZS status Ended for HL410251+4.p
177396.42/23463.23	% SZS status Started for HL410251+5.p
177396.42/23463.23	% SZS status GaveUp for HL410251+5.p
177396.42/23463.23	eprover: CPU time limit exceeded, terminating
177396.42/23463.23	% SZS status Ended for HL410251+5.p
177397.19/23463.27	% SZS status Started for HL410252+4.p
177397.19/23463.27	% SZS status GaveUp for HL410252+4.p
177397.19/23463.27	eprover: CPU time limit exceeded, terminating
177397.19/23463.27	% SZS status Ended for HL410252+4.p
177405.80/23464.34	% SZS status Started for HL410252+5.p
177405.80/23464.34	% SZS status GaveUp for HL410252+5.p
177405.80/23464.34	eprover: CPU time limit exceeded, terminating
177405.80/23464.34	% SZS status Ended for HL410252+5.p
177407.52/23464.59	% SZS status Started for HL410253+4.p
177407.52/23464.59	% SZS status GaveUp for HL410253+4.p
177407.52/23464.59	eprover: CPU time limit exceeded, terminating
177407.52/23464.59	% SZS status Ended for HL410253+4.p
177411.88/23465.12	% SZS status Started for HL410253+5.p
177411.88/23465.12	% SZS status GaveUp for HL410253+5.p
177411.88/23465.12	eprover: CPU time limit exceeded, terminating
177411.88/23465.12	% SZS status Ended for HL410253+5.p
177412.31/23465.15	% SZS status Started for HL410254+4.p
177412.31/23465.15	% SZS status GaveUp for HL410254+4.p
177412.31/23465.15	eprover: CPU time limit exceeded, terminating
177412.31/23465.15	% SZS status Ended for HL410254+4.p
177412.31/23465.18	% SZS status Started for HL410254+5.p
177412.31/23465.18	% SZS status GaveUp for HL410254+5.p
177412.31/23465.18	eprover: CPU time limit exceeded, terminating
177412.31/23465.18	% SZS status Ended for HL410254+5.p
177413.22/23465.33	% SZS status Started for HL410256+4.p
177413.22/23465.33	% SZS status GaveUp for HL410256+4.p
177413.22/23465.33	eprover: CPU time limit exceeded, terminating
177413.22/23465.33	% SZS status Ended for HL410256+4.p
177420.86/23466.27	% SZS status Started for HL410256+5.p
177420.86/23466.27	% SZS status GaveUp for HL410256+5.p
177420.86/23466.27	eprover: CPU time limit exceeded, terminating
177420.86/23466.27	% SZS status Ended for HL410256+5.p
177421.42/23466.31	% SZS status Started for HL410257+4.p
177421.42/23466.31	% SZS status GaveUp for HL410257+4.p
177421.42/23466.31	eprover: CPU time limit exceeded, terminating
177421.42/23466.31	% SZS status Ended for HL410257+4.p
177429.94/23467.37	% SZS status Started for HL410257+5.p
177429.94/23467.37	% SZS status GaveUp for HL410257+5.p
177429.94/23467.37	eprover: CPU time limit exceeded, terminating
177429.94/23467.37	% SZS status Ended for HL410257+5.p
177431.75/23467.63	% SZS status Started for HL410258+4.p
177431.75/23467.63	% SZS status GaveUp for HL410258+4.p
177431.75/23467.63	eprover: CPU time limit exceeded, terminating
177431.75/23467.63	% SZS status Ended for HL410258+4.p
177435.95/23468.16	% SZS status Started for HL410258+5.p
177435.95/23468.16	% SZS status GaveUp for HL410258+5.p
177435.95/23468.16	eprover: CPU time limit exceeded, terminating
177435.95/23468.16	% SZS status Ended for HL410258+5.p
177436.28/23468.20	% SZS status Started for HL410259+4.p
177436.28/23468.20	% SZS status GaveUp for HL410259+4.p
177436.28/23468.20	eprover: CPU time limit exceeded, terminating
177436.28/23468.20	% SZS status Ended for HL410259+4.p
177437.30/23468.35	% SZS status Started for HL410259+5.p
177437.30/23468.35	% SZS status GaveUp for HL410259+5.p
177437.30/23468.35	eprover: CPU time limit exceeded, terminating
177437.30/23468.35	% SZS status Ended for HL410259+5.p
177437.88/23468.38	% SZS status Started for HL410260+4.p
177437.88/23468.38	% SZS status GaveUp for HL410260+4.p
177437.88/23468.38	eprover: CPU time limit exceeded, terminating
177437.88/23468.38	% SZS status Ended for HL410260+4.p
177445.06/23469.30	% SZS status Started for HL410260+5.p
177445.06/23469.30	% SZS status GaveUp for HL410260+5.p
177445.06/23469.30	eprover: CPU time limit exceeded, terminating
177445.06/23469.30	% SZS status Ended for HL410260+5.p
177445.06/23469.35	% SZS status Started for HL410264+4.p
177445.06/23469.35	% SZS status GaveUp for HL410264+4.p
177445.06/23469.35	eprover: CPU time limit exceeded, terminating
177445.06/23469.35	% SZS status Ended for HL410264+4.p
177453.98/23470.41	% SZS status Started for HL410264+5.p
177453.98/23470.41	% SZS status GaveUp for HL410264+5.p
177453.98/23470.41	eprover: CPU time limit exceeded, terminating
177453.98/23470.41	% SZS status Ended for HL410264+5.p
177455.81/23470.67	% SZS status Started for HL410265+4.p
177455.81/23470.67	% SZS status GaveUp for HL410265+4.p
177455.81/23470.67	eprover: CPU time limit exceeded, terminating
177455.81/23470.67	% SZS status Ended for HL410265+4.p
177459.92/23471.20	% SZS status Started for HL410265+5.p
177459.92/23471.20	% SZS status GaveUp for HL410265+5.p
177459.92/23471.20	eprover: CPU time limit exceeded, terminating
177459.92/23471.20	% SZS status Ended for HL410265+5.p
177460.56/23471.24	% SZS status Started for HL410266+4.p
177460.56/23471.24	% SZS status GaveUp for HL410266+4.p
177460.56/23471.24	eprover: CPU time limit exceeded, terminating
177460.56/23471.24	% SZS status Ended for HL410266+4.p
177461.50/23471.42	% SZS status Started for HL410267+4.p
177461.50/23471.42	% SZS status GaveUp for HL410267+4.p
177461.50/23471.42	eprover: CPU time limit exceeded, terminating
177461.50/23471.42	% SZS status Ended for HL410267+4.p
177462.44/23471.53	% SZS status Started for HL410266+5.p
177462.44/23471.53	% SZS status GaveUp for HL410266+5.p
177462.44/23471.53	eprover: CPU time limit exceeded, terminating
177462.44/23471.53	% SZS status Ended for HL410266+5.p
177469.39/23472.34	% SZS status Started for HL410267+5.p
177469.39/23472.34	% SZS status GaveUp for HL410267+5.p
177469.39/23472.34	eprover: CPU time limit exceeded, terminating
177469.39/23472.34	% SZS status Ended for HL410267+5.p
177469.78/23472.39	% SZS status Started for HL410268+4.p
177469.78/23472.39	% SZS status GaveUp for HL410268+4.p
177469.78/23472.39	eprover: CPU time limit exceeded, terminating
177469.78/23472.39	% SZS status Ended for HL410268+4.p
177478.17/23473.44	% SZS status Started for HL410268+5.p
177478.17/23473.44	% SZS status GaveUp for HL410268+5.p
177478.17/23473.44	eprover: CPU time limit exceeded, terminating
177478.17/23473.44	% SZS status Ended for HL410268+5.p
177479.73/23473.71	% SZS status Started for HL410269+4.p
177479.73/23473.71	% SZS status GaveUp for HL410269+4.p
177479.73/23473.71	eprover: CPU time limit exceeded, terminating
177479.73/23473.71	% SZS status Ended for HL410269+4.p
177485.66/23474.23	% SZS status Started for HL410269+5.p
177485.66/23474.23	% SZS status GaveUp for HL410269+5.p
177485.66/23474.23	eprover: CPU time limit exceeded, terminating
177485.66/23474.23	% SZS status Ended for HL410269+5.p
177486.92/23474.28	% SZS status Started for HL410270+4.p
177486.92/23474.28	% SZS status GaveUp for HL410270+4.p
177486.92/23474.28	eprover: CPU time limit exceeded, terminating
177486.92/23474.28	% SZS status Ended for HL410270+4.p
177488.70/23474.57	% SZS status Started for HL410270+5.p
177488.70/23474.57	% SZS status GaveUp for HL410270+5.p
177488.70/23474.57	eprover: CPU time limit exceeded, terminating
177488.70/23474.57	% SZS status Ended for HL410270+5.p
177488.70/23474.57	% SZS status Started for HL410271+4.p
177488.70/23474.57	% SZS status GaveUp for HL410271+4.p
177488.70/23474.57	eprover: CPU time limit exceeded, terminating
177488.70/23474.57	% SZS status Ended for HL410271+4.p
177495.64/23475.38	% SZS status Started for HL410271+5.p
177495.64/23475.38	% SZS status GaveUp for HL410271+5.p
177495.64/23475.38	eprover: CPU time limit exceeded, terminating
177495.64/23475.38	% SZS status Ended for HL410271+5.p
177495.91/23475.43	% SZS status Started for HL410272+4.p
177495.91/23475.43	% SZS status GaveUp for HL410272+4.p
177495.91/23475.43	eprover: CPU time limit exceeded, terminating
177495.91/23475.43	% SZS status Ended for HL410272+4.p
177504.53/23476.48	% SZS status Started for HL410272+5.p
177504.53/23476.48	% SZS status GaveUp for HL410272+5.p
177504.53/23476.48	eprover: CPU time limit exceeded, terminating
177504.53/23476.48	% SZS status Ended for HL410272+5.p
177506.52/23476.74	% SZS status Started for HL410273+4.p
177506.52/23476.74	% SZS status GaveUp for HL410273+4.p
177506.52/23476.74	eprover: CPU time limit exceeded, terminating
177506.52/23476.74	% SZS status Ended for HL410273+4.p
177510.61/23477.32	% SZS status Started for HL410274+4.p
177510.61/23477.32	% SZS status GaveUp for HL410274+4.p
177510.61/23477.32	eprover: CPU time limit exceeded, terminating
177510.61/23477.32	% SZS status Ended for HL410274+4.p
177511.38/23477.32	% SZS status Started for HL410273+5.p
177511.38/23477.32	% SZS status GaveUp for HL410273+5.p
177511.38/23477.32	eprover: CPU time limit exceeded, terminating
177511.38/23477.32	% SZS status Ended for HL410273+5.p
177512.67/23477.60	% SZS status Started for HL410274+5.p
177512.67/23477.60	% SZS status GaveUp for HL410274+5.p
177512.67/23477.60	eprover: CPU time limit exceeded, terminating
177512.67/23477.60	% SZS status Ended for HL410274+5.p
177512.67/23477.61	% SZS status Started for HL410275+4.p
177512.67/23477.61	% SZS status GaveUp for HL410275+4.p
177512.67/23477.61	eprover: CPU time limit exceeded, terminating
177512.67/23477.61	% SZS status Ended for HL410275+4.p
177519.72/23478.42	% SZS status Started for HL410275+5.p
177519.72/23478.42	% SZS status GaveUp for HL410275+5.p
177519.72/23478.42	eprover: CPU time limit exceeded, terminating
177519.72/23478.42	% SZS status Ended for HL410275+5.p
177520.98/23478.58	% SZS status Started for HL410276+4.p
177520.98/23478.58	% SZS status GaveUp for HL410276+4.p
177520.98/23478.58	eprover: CPU time limit exceeded, terminating
177520.98/23478.58	% SZS status Ended for HL410276+4.p
177528.47/23479.52	% SZS status Started for HL410276+5.p
177528.47/23479.52	% SZS status GaveUp for HL410276+5.p
177528.47/23479.52	eprover: CPU time limit exceeded, terminating
177528.47/23479.52	% SZS status Ended for HL410276+5.p
177530.64/23479.78	% SZS status Started for HL410278+4.p
177530.64/23479.78	% SZS status GaveUp for HL410278+4.p
177530.64/23479.78	eprover: CPU time limit exceeded, terminating
177530.64/23479.78	% SZS status Ended for HL410278+4.p
177535.19/23480.35	% SZS status Started for HL410278+5.p
177535.19/23480.35	% SZS status GaveUp for HL410278+5.p
177535.19/23480.35	eprover: CPU time limit exceeded, terminating
177535.19/23480.35	% SZS status Ended for HL410278+5.p
177535.19/23480.37	% SZS status Started for HL410279+4.p
177535.19/23480.37	% SZS status GaveUp for HL410279+4.p
177535.19/23480.37	eprover: CPU time limit exceeded, terminating
177535.19/23480.37	% SZS status Ended for HL410279+4.p
177537.55/23480.63	% SZS status Started for HL410279+5.p
177537.55/23480.63	% SZS status GaveUp for HL410279+5.p
177537.55/23480.63	eprover: CPU time limit exceeded, terminating
177537.55/23480.63	% SZS status Ended for HL410279+5.p
177538.64/23480.78	% SZS status Started for HL410280+4.p
177538.64/23480.78	% SZS status GaveUp for HL410280+4.p
177538.64/23480.78	eprover: CPU time limit exceeded, terminating
177538.64/23480.78	% SZS status Ended for HL410280+4.p
177543.72/23481.45	% SZS status Started for HL410280+5.p
177543.72/23481.45	% SZS status GaveUp for HL410280+5.p
177543.72/23481.45	eprover: CPU time limit exceeded, terminating
177543.72/23481.45	% SZS status Ended for HL410280+5.p
177545.19/23481.62	% SZS status Started for HL410281+4.p
177545.19/23481.62	% SZS status GaveUp for HL410281+4.p
177545.19/23481.62	eprover: CPU time limit exceeded, terminating
177545.19/23481.62	% SZS status Ended for HL410281+4.p
177552.84/23482.56	% SZS status Started for HL410281+5.p
177552.84/23482.56	% SZS status GaveUp for HL410281+5.p
177552.84/23482.56	eprover: CPU time limit exceeded, terminating
177552.84/23482.56	% SZS status Ended for HL410281+5.p
177554.75/23482.82	% SZS status Started for HL410282+4.p
177554.75/23482.82	% SZS status GaveUp for HL410282+4.p
177554.75/23482.82	eprover: CPU time limit exceeded, terminating
177554.75/23482.82	% SZS status Ended for HL410282+4.p
177559.03/23483.38	% SZS status Started for HL410282+5.p
177559.03/23483.38	% SZS status GaveUp for HL410282+5.p
177559.03/23483.38	eprover: CPU time limit exceeded, terminating
177559.03/23483.38	% SZS status Ended for HL410282+5.p
177559.69/23483.41	% SZS status Started for HL410283+4.p
177559.69/23483.41	% SZS status GaveUp for HL410283+4.p
177559.69/23483.41	eprover: CPU time limit exceeded, terminating
177559.69/23483.41	% SZS status Ended for HL410283+4.p
177561.94/23483.79	% SZS status Started for HL410283+5.p
177561.94/23483.79	% SZS status GaveUp for HL410283+5.p
177561.94/23483.79	eprover: CPU time limit exceeded, terminating
177561.94/23483.79	% SZS status Ended for HL410283+5.p
177561.94/23483.82	% SZS status Started for HL410284+4.p
177561.94/23483.82	% SZS status GaveUp for HL410284+4.p
177561.94/23483.82	eprover: CPU time limit exceeded, terminating
177561.94/23483.82	% SZS status Ended for HL410284+4.p
177568.02/23484.49	% SZS status Started for HL410284+5.p
177568.02/23484.49	% SZS status GaveUp for HL410284+5.p
177568.02/23484.49	eprover: CPU time limit exceeded, terminating
177568.02/23484.49	% SZS status Ended for HL410284+5.p
177569.41/23484.66	% SZS status Started for HL410285+4.p
177569.41/23484.66	% SZS status GaveUp for HL410285+4.p
177569.41/23484.66	eprover: CPU time limit exceeded, terminating
177569.41/23484.66	% SZS status Ended for HL410285+4.p
177577.00/23485.60	% SZS status Started for HL410285+5.p
177577.00/23485.60	% SZS status GaveUp for HL410285+5.p
177577.00/23485.60	eprover: CPU time limit exceeded, terminating
177577.00/23485.60	% SZS status Ended for HL410285+5.p
177578.73/23485.85	% SZS status Started for HL410286+4.p
177578.73/23485.85	% SZS status GaveUp for HL410286+4.p
177578.73/23485.85	eprover: CPU time limit exceeded, terminating
177578.73/23485.85	% SZS status Ended for HL410286+4.p
177583.28/23486.42	% SZS status Started for HL410286+5.p
177583.28/23486.42	% SZS status GaveUp for HL410286+5.p
177583.28/23486.42	eprover: CPU time limit exceeded, terminating
177583.28/23486.42	% SZS status Ended for HL410286+5.p
177584.34/23486.58	% SZS status Started for HL410287+4.p
177584.34/23486.58	% SZS status GaveUp for HL410287+4.p
177584.34/23486.58	eprover: CPU time limit exceeded, terminating
177584.34/23486.58	% SZS status Ended for HL410287+4.p
177586.19/23486.82	% SZS status Started for HL410287+5.p
177586.19/23486.82	% SZS status GaveUp for HL410287+5.p
177586.19/23486.82	eprover: CPU time limit exceeded, terminating
177586.19/23486.82	% SZS status Ended for HL410287+5.p
177586.19/23486.86	% SZS status Started for HL410288+4.p
177586.19/23486.86	% SZS status GaveUp for HL410288+4.p
177586.19/23486.86	eprover: CPU time limit exceeded, terminating
177586.19/23486.86	% SZS status Ended for HL410288+4.p
177592.03/23487.53	% SZS status Started for HL410288+5.p
177592.03/23487.53	% SZS status GaveUp for HL410288+5.p
177592.03/23487.53	eprover: CPU time limit exceeded, terminating
177592.03/23487.53	% SZS status Ended for HL410288+5.p
177593.31/23487.70	% SZS status Started for HL410289+4.p
177593.31/23487.70	% SZS status GaveUp for HL410289+4.p
177593.31/23487.70	eprover: CPU time limit exceeded, terminating
177593.31/23487.70	% SZS status Ended for HL410289+4.p
177600.62/23488.64	% SZS status Started for HL410289+5.p
177600.62/23488.64	% SZS status GaveUp for HL410289+5.p
177600.62/23488.64	eprover: CPU time limit exceeded, terminating
177600.62/23488.64	% SZS status Ended for HL410289+5.p
177603.00/23488.89	% SZS status Started for HL410290+4.p
177603.00/23488.89	% SZS status GaveUp for HL410290+4.p
177603.00/23488.89	eprover: CPU time limit exceeded, terminating
177603.00/23488.89	% SZS status Ended for HL410290+4.p
177607.59/23489.46	% SZS status Started for HL410290+5.p
177607.59/23489.46	% SZS status GaveUp for HL410290+5.p
177607.59/23489.46	eprover: CPU time limit exceeded, terminating
177607.59/23489.46	% SZS status Ended for HL410290+5.p
177609.73/23489.75	% SZS status Started for HL410291+4.p
177609.73/23489.75	% SZS status GaveUp for HL410291+4.p
177609.73/23489.75	eprover: CPU time limit exceeded, terminating
177609.73/23489.75	% SZS status Ended for HL410291+4.p
177610.36/23489.86	% SZS status Started for HL410291+5.p
177610.36/23489.86	% SZS status GaveUp for HL410291+5.p
177610.36/23489.86	eprover: CPU time limit exceeded, terminating
177610.36/23489.86	% SZS status Ended for HL410291+5.p
177610.36/23489.90	% SZS status Started for HL410293+4.p
177610.36/23489.90	% SZS status GaveUp for HL410293+4.p
177610.36/23489.90	eprover: CPU time limit exceeded, terminating
177610.36/23489.90	% SZS status Ended for HL410293+4.p
177618.16/23490.57	% SZS status Started for HL410293+5.p
177618.16/23490.57	% SZS status GaveUp for HL410293+5.p
177618.16/23490.57	eprover: CPU time limit exceeded, terminating
177618.16/23490.57	% SZS status Ended for HL410293+5.p
177619.42/23490.74	% SZS status Started for HL410295+4.p
177619.42/23490.74	% SZS status GaveUp for HL410295+4.p
177619.42/23490.74	eprover: CPU time limit exceeded, terminating
177619.42/23490.74	% SZS status Ended for HL410295+4.p
177627.38/23491.68	% SZS status Started for HL410295+5.p
177627.38/23491.68	% SZS status GaveUp for HL410295+5.p
177627.38/23491.68	eprover: CPU time limit exceeded, terminating
177627.38/23491.68	% SZS status Ended for HL410295+5.p
177628.84/23491.93	% SZS status Started for HL410296+4.p
177628.84/23491.93	% SZS status GaveUp for HL410296+4.p
177628.84/23491.93	eprover: CPU time limit exceeded, terminating
177628.84/23491.93	% SZS status Ended for HL410296+4.p
177633.52/23492.50	% SZS status Started for HL410296+5.p
177633.52/23492.50	% SZS status GaveUp for HL410296+5.p
177633.52/23492.50	eprover: CPU time limit exceeded, terminating
177633.52/23492.50	% SZS status Ended for HL410296+5.p
177636.83/23492.89	% SZS status Started for HL410297+5.p
177636.83/23492.89	% SZS status GaveUp for HL410297+5.p
177636.83/23492.89	eprover: CPU time limit exceeded, terminating
177636.83/23492.89	% SZS status Ended for HL410297+5.p
177637.42/23492.94	% SZS status Started for HL410297+4.p
177637.42/23492.94	% SZS status GaveUp for HL410297+4.p
177637.42/23492.94	eprover: CPU time limit exceeded, terminating
177637.42/23492.94	% SZS status Ended for HL410297+4.p
177637.42/23492.95	% SZS status Started for HL410299+4.p
177637.42/23492.95	% SZS status GaveUp for HL410299+4.p
177637.42/23492.95	eprover: CPU time limit exceeded, terminating
177637.42/23492.95	% SZS status Ended for HL410299+4.p
177642.05/23493.60	% SZS status Started for HL410299+5.p
177642.05/23493.60	% SZS status GaveUp for HL410299+5.p
177642.05/23493.60	eprover: CPU time limit exceeded, terminating
177642.05/23493.60	% SZS status Ended for HL410299+5.p
177643.89/23493.77	% SZS status Started for HL410300+4.p
177643.89/23493.77	% SZS status GaveUp for HL410300+4.p
177643.89/23493.77	eprover: CPU time limit exceeded, terminating
177643.89/23493.77	% SZS status Ended for HL410300+4.p
177651.44/23494.72	% SZS status Started for HL410300+5.p
177651.44/23494.72	% SZS status GaveUp for HL410300+5.p
177651.44/23494.72	eprover: CPU time limit exceeded, terminating
177651.44/23494.72	% SZS status Ended for HL410300+5.p
177653.08/23494.96	% SZS status Started for HL410301+4.p
177653.08/23494.96	% SZS status GaveUp for HL410301+4.p
177653.08/23494.96	eprover: CPU time limit exceeded, terminating
177653.08/23494.96	% SZS status Ended for HL410301+4.p
177657.91/23495.54	% SZS status Started for HL410301+5.p
177657.91/23495.54	% SZS status GaveUp for HL410301+5.p
177657.91/23495.54	eprover: CPU time limit exceeded, terminating
177657.91/23495.54	% SZS status Ended for HL410301+5.p
177661.30/23495.98	% SZS status Started for HL410303+5.p
177661.30/23495.98	% SZS status GaveUp for HL410303+5.p
177661.30/23495.98	eprover: CPU time limit exceeded, terminating
177661.30/23495.98	% SZS status Ended for HL410303+5.p
177661.30/23495.98	% SZS status Started for HL410304+4.p
177661.30/23495.98	% SZS status GaveUp for HL410304+4.p
177661.30/23495.98	eprover: CPU time limit exceeded, terminating
177661.30/23495.98	% SZS status Ended for HL410304+4.p
177661.97/23496.06	% SZS status Started for HL410303+4.p
177661.97/23496.06	% SZS status GaveUp for HL410303+4.p
177661.97/23496.06	eprover: CPU time limit exceeded, terminating
177661.97/23496.06	% SZS status Ended for HL410303+4.p
177666.41/23496.64	% SZS status Started for HL410304+5.p
177666.41/23496.64	% SZS status GaveUp for HL410304+5.p
177666.41/23496.64	eprover: CPU time limit exceeded, terminating
177666.41/23496.64	% SZS status Ended for HL410304+5.p
177667.55/23496.82	% SZS status Started for HL410306+4.p
177667.55/23496.82	% SZS status GaveUp for HL410306+4.p
177667.55/23496.82	eprover: CPU time limit exceeded, terminating
177667.55/23496.82	% SZS status Ended for HL410306+4.p
177675.11/23497.76	% SZS status Started for HL410306+5.p
177675.11/23497.76	% SZS status GaveUp for HL410306+5.p
177675.11/23497.76	eprover: CPU time limit exceeded, terminating
177675.11/23497.76	% SZS status Ended for HL410306+5.p
177677.34/23498.00	% SZS status Started for HL410307+4.p
177677.34/23498.00	% SZS status GaveUp for HL410307+4.p
177677.34/23498.00	eprover: CPU time limit exceeded, terminating
177677.34/23498.00	% SZS status Ended for HL410307+4.p
177681.83/23498.58	% SZS status Started for HL410307+5.p
177681.83/23498.58	% SZS status GaveUp for HL410307+5.p
177681.83/23498.58	eprover: CPU time limit exceeded, terminating
177681.83/23498.58	% SZS status Ended for HL410307+5.p
177685.42/23499.02	% SZS status Started for HL410308+5.p
177685.42/23499.02	% SZS status GaveUp for HL410308+5.p
177685.42/23499.02	eprover: CPU time limit exceeded, terminating
177685.42/23499.02	% SZS status Ended for HL410308+5.p
177686.08/23499.10	% SZS status Started for HL410309+4.p
177686.08/23499.10	% SZS status GaveUp for HL410309+4.p
177686.08/23499.10	eprover: CPU time limit exceeded, terminating
177686.08/23499.10	% SZS status Ended for HL410309+4.p
177686.66/23499.15	% SZS status Started for HL410308+4.p
177686.66/23499.15	% SZS status GaveUp for HL410308+4.p
177686.66/23499.15	eprover: CPU time limit exceeded, terminating
177686.66/23499.15	% SZS status Ended for HL410308+4.p
177690.70/23499.67	% SZS status Started for HL410309+5.p
177690.70/23499.67	% SZS status GaveUp for HL410309+5.p
177690.70/23499.67	eprover: CPU time limit exceeded, terminating
177690.70/23499.67	% SZS status Ended for HL410309+5.p
177691.94/23499.85	% SZS status Started for HL410310+4.p
177691.94/23499.85	% SZS status GaveUp for HL410310+4.p
177691.94/23499.85	eprover: CPU time limit exceeded, terminating
177691.94/23499.85	% SZS status Ended for HL410310+4.p
177699.78/23500.80	% SZS status Started for HL410310+5.p
177699.78/23500.80	% SZS status GaveUp for HL410310+5.p
177699.78/23500.80	eprover: CPU time limit exceeded, terminating
177699.78/23500.80	% SZS status Ended for HL410310+5.p
177701.70/23501.04	% SZS status Started for HL410311+4.p
177701.70/23501.04	% SZS status GaveUp for HL410311+4.p
177701.70/23501.04	eprover: CPU time limit exceeded, terminating
177701.70/23501.04	% SZS status Ended for HL410311+4.p
177705.66/23501.62	% SZS status Started for HL410311+5.p
177705.66/23501.62	% SZS status GaveUp for HL410311+5.p
177705.66/23501.62	eprover: CPU time limit exceeded, terminating
177705.66/23501.62	% SZS status Ended for HL410311+5.p
177711.48/23502.05	% SZS status Started for HL410312+4.p
177711.48/23502.05	% SZS status GaveUp for HL410312+4.p
177711.48/23502.05	eprover: CPU time limit exceeded, terminating
177711.48/23502.05	% SZS status Ended for HL410312+4.p
177711.89/23502.14	% SZS status Started for HL410312+5.p
177711.89/23502.14	% SZS status GaveUp for HL410312+5.p
177711.89/23502.14	eprover: CPU time limit exceeded, terminating
177711.89/23502.14	% SZS status Ended for HL410312+5.p
177713.09/23502.21	% SZS status Started for HL410313+4.p
177713.09/23502.21	% SZS status GaveUp for HL410313+4.p
177713.09/23502.21	eprover: CPU time limit exceeded, terminating
177713.09/23502.21	% SZS status Ended for HL410313+4.p
177716.50/23502.71	% SZS status Started for HL410313+5.p
177716.50/23502.71	% SZS status GaveUp for HL410313+5.p
177716.50/23502.71	eprover: CPU time limit exceeded, terminating
177716.50/23502.71	% SZS status Ended for HL410313+5.p
177718.83/23502.94	% SZS status Started for HL410314+4.p
177718.83/23502.94	% SZS status GaveUp for HL410314+4.p
177718.83/23502.94	eprover: CPU time limit exceeded, terminating
177718.83/23502.94	% SZS status Ended for HL410314+4.p
177726.89/23503.95	% SZS status Started for HL410314+5.p
177726.89/23503.95	% SZS status GaveUp for HL410314+5.p
177726.89/23503.95	eprover: CPU time limit exceeded, terminating
177726.89/23503.95	% SZS status Ended for HL410314+5.p
177727.67/23504.07	% SZS status Started for HL410315+4.p
177727.67/23504.07	% SZS status GaveUp for HL410315+4.p
177727.67/23504.07	eprover: CPU time limit exceeded, terminating
177727.67/23504.07	% SZS status Ended for HL410315+4.p
177732.20/23504.66	% SZS status Started for HL410315+5.p
177732.20/23504.66	% SZS status GaveUp for HL410315+5.p
177732.20/23504.66	eprover: CPU time limit exceeded, terminating
177732.20/23504.66	% SZS status Ended for HL410315+5.p
177735.83/23505.09	% SZS status Started for HL410316+4.p
177735.83/23505.09	% SZS status GaveUp for HL410316+4.p
177735.83/23505.09	eprover: CPU time limit exceeded, terminating
177735.83/23505.09	% SZS status Ended for HL410316+4.p
177736.89/23505.22	% SZS status Started for HL410316+5.p
177736.89/23505.22	% SZS status GaveUp for HL410316+5.p
177736.89/23505.22	eprover: CPU time limit exceeded, terminating
177736.89/23505.22	% SZS status Ended for HL410316+5.p
177737.61/23505.34	% SZS status Started for HL410317+4.p
177737.61/23505.34	% SZS status GaveUp for HL410317+4.p
177737.61/23505.34	eprover: CPU time limit exceeded, terminating
177737.61/23505.34	% SZS status Ended for HL410317+4.p
177741.27/23505.74	% SZS status Started for HL410317+5.p
177741.27/23505.74	% SZS status GaveUp for HL410317+5.p
177741.27/23505.74	eprover: CPU time limit exceeded, terminating
177741.27/23505.74	% SZS status Ended for HL410317+5.p
177742.88/23505.97	% SZS status Started for HL410318+4.p
177742.88/23505.97	% SZS status GaveUp for HL410318+4.p
177742.88/23505.97	eprover: CPU time limit exceeded, terminating
177742.88/23505.97	% SZS status Ended for HL410318+4.p
177752.02/23507.11	% SZS status Started for HL410319+4.p
177752.02/23507.11	% SZS status GaveUp for HL410319+4.p
177752.02/23507.11	eprover: CPU time limit exceeded, terminating
177752.02/23507.11	% SZS status Ended for HL410319+4.p
177760.28/23508.13	% SZS status Started for HL410321+4.p
177760.28/23508.13	% SZS status GaveUp for HL410321+4.p
177760.28/23508.13	eprover: CPU time limit exceeded, terminating
177760.28/23508.13	% SZS status Ended for HL410321+4.p
177761.97/23508.39	% SZS status Started for HL410322+4.p
177761.97/23508.39	% SZS status GaveUp for HL410322+4.p
177761.97/23508.39	eprover: CPU time limit exceeded, terminating
177761.97/23508.39	% SZS status Ended for HL410322+4.p
177766.84/23509.01	% SZS status Started for HL410323+4.p
177766.84/23509.01	% SZS status GaveUp for HL410323+4.p
177766.84/23509.01	eprover: CPU time limit exceeded, terminating
177766.84/23509.01	% SZS status Ended for HL410323+4.p
177784.05/23511.17	% SZS status Started for HL410326+4.p
177784.05/23511.17	% SZS status GaveUp for HL410326+4.p
177784.05/23511.17	eprover: CPU time limit exceeded, terminating
177784.05/23511.17	% SZS status Ended for HL410326+4.p
177790.39/23512.05	% SZS status Started for HL410327+4.p
177790.39/23512.05	% SZS status GaveUp for HL410327+4.p
177790.39/23512.05	eprover: CPU time limit exceeded, terminating
177790.39/23512.05	% SZS status Ended for HL410327+4.p
177812.50/23514.80	% SZS status Started for HL410318+5.p
177812.50/23514.80	% SZS status GaveUp for HL410318+5.p
177812.50/23514.80	eprover: CPU time limit exceeded, terminating
177812.50/23514.80	% SZS status Ended for HL410318+5.p
177815.52/23515.11	% SZS status Started for HL410328+4.p
177815.52/23515.11	% SZS status GaveUp for HL410328+4.p
177815.52/23515.11	eprover: CPU time limit exceeded, terminating
177815.52/23515.11	% SZS status Ended for HL410328+4.p
177816.64/23515.31	% SZS status Started for HL410319+5.p
177816.64/23515.31	% SZS status GaveUp for HL410319+5.p
177816.64/23515.31	eprover: CPU time limit exceeded, terminating
177816.64/23515.31	% SZS status Ended for HL410319+5.p
177819.95/23515.69	% SZS status Started for HL410321+5.p
177819.95/23515.69	% SZS status GaveUp for HL410321+5.p
177819.95/23515.69	eprover: CPU time limit exceeded, terminating
177819.95/23515.69	% SZS status Ended for HL410321+5.p
177824.91/23516.30	% SZS status Started for HL410322+5.p
177824.91/23516.30	% SZS status GaveUp for HL410322+5.p
177824.91/23516.30	eprover: CPU time limit exceeded, terminating
177824.91/23516.30	% SZS status Ended for HL410322+5.p
177834.25/23517.54	% SZS status Started for HL410323+5.p
177834.25/23517.54	% SZS status GaveUp for HL410323+5.p
177834.25/23517.54	eprover: CPU time limit exceeded, terminating
177834.25/23517.54	% SZS status Ended for HL410323+5.p
177839.31/23518.16	% SZS status Started for HL410329+4.p
177839.31/23518.16	% SZS status GaveUp for HL410329+4.p
177839.31/23518.16	eprover: CPU time limit exceeded, terminating
177839.31/23518.16	% SZS status Ended for HL410329+4.p
177844.12/23518.74	% SZS status Started for HL410330+4.p
177844.12/23518.74	% SZS status GaveUp for HL410330+4.p
177844.12/23518.74	eprover: CPU time limit exceeded, terminating
177844.12/23518.74	% SZS status Ended for HL410330+4.p
177845.50/23518.89	% SZS status Started for HL410326+5.p
177845.50/23518.89	% SZS status GaveUp for HL410326+5.p
177845.50/23518.89	eprover: CPU time limit exceeded, terminating
177845.50/23518.89	% SZS status Ended for HL410326+5.p
177859.16/23520.58	% SZS status Started for HL410332+4.p
177859.16/23520.58	% SZS status GaveUp for HL410332+4.p
177859.16/23520.58	eprover: CPU time limit exceeded, terminating
177859.16/23520.58	% SZS status Ended for HL410332+4.p
177867.97/23521.74	% SZS status Started for HL410327+5.p
177867.97/23521.74	% SZS status GaveUp for HL410327+5.p
177867.97/23521.74	eprover: CPU time limit exceeded, terminating
177867.97/23521.74	% SZS status Ended for HL410327+5.p
177868.28/23521.77	% SZS status Started for HL410333+4.p
177868.28/23521.77	% SZS status GaveUp for HL410333+4.p
177868.28/23521.77	eprover: CPU time limit exceeded, terminating
177868.28/23521.77	% SZS status Ended for HL410333+4.p
177883.33/23523.63	% SZS status Started for HL410334+4.p
177883.33/23523.63	% SZS status GaveUp for HL410334+4.p
177883.33/23523.63	eprover: CPU time limit exceeded, terminating
177883.33/23523.63	% SZS status Ended for HL410334+4.p
177892.61/23524.87	% SZS status Started for HL410335+4.p
177892.61/23524.87	% SZS status GaveUp for HL410335+4.p
177892.61/23524.87	eprover: CPU time limit exceeded, terminating
177892.61/23524.87	% SZS status Ended for HL410335+4.p
177896.14/23525.28	% SZS status Started for HL410328+5.p
177896.14/23525.28	% SZS status GaveUp for HL410328+5.p
177896.14/23525.28	eprover: CPU time limit exceeded, terminating
177896.14/23525.28	% SZS status Ended for HL410328+5.p
177900.31/23525.78	% SZS status Started for HL410329+5.p
177900.31/23525.78	% SZS status GaveUp for HL410329+5.p
177900.31/23525.78	eprover: CPU time limit exceeded, terminating
177900.31/23525.78	% SZS status Ended for HL410329+5.p
177907.72/23526.76	% SZS status Started for HL410330+5.p
177907.72/23526.76	% SZS status GaveUp for HL410330+5.p
177907.72/23526.76	eprover: CPU time limit exceeded, terminating
177907.72/23526.76	% SZS status Ended for HL410330+5.p
177916.84/23527.92	% SZS status Started for HL410336+4.p
177916.84/23527.92	% SZS status GaveUp for HL410336+4.p
177916.84/23527.92	eprover: CPU time limit exceeded, terminating
177916.84/23527.92	% SZS status Ended for HL410336+4.p
177923.33/23528.71	% SZS status Started for HL410332+5.p
177923.33/23528.71	% SZS status GaveUp for HL410332+5.p
177923.33/23528.71	eprover: CPU time limit exceeded, terminating
177923.33/23528.71	% SZS status Ended for HL410332+5.p
177924.62/23528.89	% SZS status Started for HL410337+4.p
177924.62/23528.89	% SZS status GaveUp for HL410337+4.p
177924.62/23528.89	eprover: CPU time limit exceeded, terminating
177924.62/23528.89	% SZS status Ended for HL410337+4.p
177929.14/23529.42	% SZS status Started for HL410333+5.p
177929.14/23529.42	% SZS status GaveUp for HL410333+5.p
177929.14/23529.42	eprover: CPU time limit exceeded, terminating
177929.14/23529.42	% SZS status Ended for HL410333+5.p
177932.09/23529.81	% SZS status Started for HL410337+5.p
177932.09/23529.81	% SZS status GaveUp for HL410337+5.p
177932.09/23529.81	eprover: CPU time limit exceeded, terminating
177932.09/23529.81	% SZS status Ended for HL410337+5.p
177940.97/23530.95	% SZS status Started for HL410338+4.p
177940.97/23530.95	% SZS status GaveUp for HL410338+4.p
177940.97/23530.95	eprover: CPU time limit exceeded, terminating
177940.97/23530.95	% SZS status Ended for HL410338+4.p
177949.17/23531.94	% SZS status Started for HL410339+4.p
177949.17/23531.94	% SZS status GaveUp for HL410339+4.p
177949.17/23531.94	eprover: CPU time limit exceeded, terminating
177949.17/23531.94	% SZS status Ended for HL410339+4.p
177950.94/23532.22	% SZS status Started for HL410334+5.p
177950.94/23532.22	% SZS status GaveUp for HL410334+5.p
177950.94/23532.22	eprover: CPU time limit exceeded, terminating
177950.94/23532.22	% SZS status Ended for HL410334+5.p
177956.23/23532.86	% SZS status Started for HL410340+4.p
177956.23/23532.86	% SZS status GaveUp for HL410340+4.p
177956.23/23532.86	eprover: CPU time limit exceeded, terminating
177956.23/23532.86	% SZS status Ended for HL410340+4.p
177966.06/23534.11	% SZS status Started for HL410335+5.p
177966.06/23534.11	% SZS status GaveUp for HL410335+5.p
177966.06/23534.11	eprover: CPU time limit exceeded, terminating
177966.06/23534.11	% SZS status Ended for HL410335+5.p
177973.22/23534.97	% SZS status Started for HL410343+4.p
177973.22/23534.97	% SZS status GaveUp for HL410343+4.p
177973.22/23534.97	eprover: CPU time limit exceeded, terminating
177973.22/23534.97	% SZS status Ended for HL410343+4.p
177979.08/23535.79	% SZS status Started for HL410336+5.p
177979.08/23535.79	% SZS status GaveUp for HL410336+5.p
177979.08/23535.79	eprover: CPU time limit exceeded, terminating
177979.08/23535.79	% SZS status Ended for HL410336+5.p
177980.67/23535.91	% SZS status Started for HL410344+4.p
177980.67/23535.91	% SZS status GaveUp for HL410344+4.p
177980.67/23535.91	eprover: CPU time limit exceeded, terminating
177980.67/23535.91	% SZS status Ended for HL410344+4.p
177997.52/23538.01	% SZS status Started for HL410345+4.p
177997.52/23538.01	% SZS status GaveUp for HL410345+4.p
177997.52/23538.01	eprover: CPU time limit exceeded, terminating
177997.52/23538.01	% SZS status Ended for HL410345+4.p
178003.97/23538.94	% SZS status Started for HL410346+4.p
178003.97/23538.94	% SZS status GaveUp for HL410346+4.p
178003.97/23538.94	eprover: CPU time limit exceeded, terminating
178003.97/23538.94	% SZS status Ended for HL410346+4.p
178009.61/23539.67	% SZS status Started for HL410338+5.p
178009.61/23539.67	% SZS status GaveUp for HL410338+5.p
178009.61/23539.67	eprover: CPU time limit exceeded, terminating
178009.61/23539.67	% SZS status Ended for HL410338+5.p
178023.27/23540.18	% SZS status Started for HL410339+5.p
178023.27/23540.18	% SZS status GaveUp for HL410339+5.p
178023.27/23540.18	eprover: CPU time limit exceeded, terminating
178023.27/23540.18	% SZS status Ended for HL410339+5.p
178034.00/23541.42	% SZS status Started for HL410340+5.p
178034.00/23541.42	% SZS status GaveUp for HL410340+5.p
178034.00/23541.42	eprover: CPU time limit exceeded, terminating
178034.00/23541.42	% SZS status Ended for HL410340+5.p
178038.56/23541.99	% SZS status Started for HL410347+4.p
178038.56/23541.99	% SZS status GaveUp for HL410347+4.p
178038.56/23541.99	eprover: CPU time limit exceeded, terminating
178038.56/23541.99	% SZS status Ended for HL410347+4.p
178044.61/23542.74	% SZS status Started for HL410343+5.p
178044.61/23542.74	% SZS status GaveUp for HL410343+5.p
178044.61/23542.74	eprover: CPU time limit exceeded, terminating
178044.61/23542.74	% SZS status Ended for HL410343+5.p
178048.59/23543.25	% SZS status Started for HL410350+4.p
178048.59/23543.25	% SZS status GaveUp for HL410350+4.p
178048.59/23543.25	eprover: CPU time limit exceeded, terminating
178048.59/23543.25	% SZS status Ended for HL410350+4.p
178059.91/23544.80	% SZS status Started for HL410344+5.p
178059.91/23544.80	% SZS status GaveUp for HL410344+5.p
178059.91/23544.80	eprover: CPU time limit exceeded, terminating
178059.91/23544.80	% SZS status Ended for HL410344+5.p
178062.06/23545.02	% SZS status Started for HL410351+4.p
178062.06/23545.02	% SZS status GaveUp for HL410351+4.p
178062.06/23545.02	eprover: CPU time limit exceeded, terminating
178062.06/23545.02	% SZS status Ended for HL410351+4.p
178072.34/23546.31	% SZS status Started for HL410345+5.p
178072.34/23546.31	% SZS status GaveUp for HL410345+5.p
178072.34/23546.31	eprover: CPU time limit exceeded, terminating
178072.34/23546.31	% SZS status Ended for HL410345+5.p
178072.67/23546.35	% SZS status Started for HL410352+4.p
178072.67/23546.35	% SZS status GaveUp for HL410352+4.p
178072.67/23546.35	eprover: CPU time limit exceeded, terminating
178072.67/23546.35	% SZS status Ended for HL410352+4.p
178086.52/23548.06	% SZS status Started for HL410354+4.p
178086.52/23548.06	% SZS status GaveUp for HL410354+4.p
178086.52/23548.06	eprover: CPU time limit exceeded, terminating
178086.52/23548.06	% SZS status Ended for HL410354+4.p
178089.67/23548.48	% SZS status Started for HL410346+5.p
178089.67/23548.48	% SZS status GaveUp for HL410346+5.p
178089.67/23548.48	eprover: CPU time limit exceeded, terminating
178089.67/23548.48	% SZS status Ended for HL410346+5.p
178097.80/23549.50	% SZS status Started for HL410355+4.p
178097.80/23549.50	% SZS status GaveUp for HL410355+4.p
178097.80/23549.50	eprover: CPU time limit exceeded, terminating
178097.80/23549.50	% SZS status Ended for HL410355+4.p
178102.80/23550.10	% SZS status Started for HL410347+5.p
178102.80/23550.10	% SZS status GaveUp for HL410347+5.p
178102.80/23550.10	eprover: CPU time limit exceeded, terminating
178102.80/23550.10	% SZS status Ended for HL410347+5.p
178113.67/23551.51	% SZS status Started for HL410357+4.p
178113.67/23551.51	% SZS status GaveUp for HL410357+4.p
178113.67/23551.51	eprover: CPU time limit exceeded, terminating
178113.67/23551.51	% SZS status Ended for HL410357+4.p
178117.78/23551.99	% SZS status Started for HL410350+5.p
178117.78/23551.99	% SZS status GaveUp for HL410350+5.p
178117.78/23551.99	eprover: CPU time limit exceeded, terminating
178117.78/23551.99	% SZS status Ended for HL410350+5.p
178126.98/23553.14	% SZS status Started for HL410358+4.p
178126.98/23553.14	% SZS status GaveUp for HL410358+4.p
178126.98/23553.14	eprover: CPU time limit exceeded, terminating
178126.98/23553.14	% SZS status Ended for HL410358+4.p
178128.05/23553.28	% SZS status Started for HL410351+5.p
178128.05/23553.28	% SZS status GaveUp for HL410351+5.p
178128.05/23553.28	eprover: CPU time limit exceeded, terminating
178128.05/23553.28	% SZS status Ended for HL410351+5.p
178141.67/23555.02	% SZS status Started for HL410359+4.p
178141.67/23555.02	% SZS status GaveUp for HL410359+4.p
178141.67/23555.02	eprover: CPU time limit exceeded, terminating
178141.67/23555.02	% SZS status Ended for HL410359+4.p
178146.12/23555.57	% SZS status Started for HL410352+5.p
178146.12/23555.57	% SZS status GaveUp for HL410352+5.p
178146.12/23555.57	eprover: CPU time limit exceeded, terminating
178146.12/23555.57	% SZS status Ended for HL410352+5.p
178152.38/23556.35	% SZS status Started for HL410362+4.p
178152.38/23556.35	% SZS status GaveUp for HL410362+4.p
178152.38/23556.35	eprover: CPU time limit exceeded, terminating
178152.38/23556.35	% SZS status Ended for HL410362+4.p
178156.80/23556.89	% SZS status Started for HL410354+5.p
178156.80/23556.89	% SZS status GaveUp for HL410354+5.p
178156.80/23556.89	eprover: CPU time limit exceeded, terminating
178156.80/23556.89	% SZS status Ended for HL410354+5.p
178169.53/23558.49	% SZS status Started for HL410355+5.p
178169.53/23558.49	% SZS status GaveUp for HL410355+5.p
178169.53/23558.49	eprover: CPU time limit exceeded, terminating
178169.53/23558.49	% SZS status Ended for HL410355+5.p
178170.50/23558.66	% SZS status Started for HL410363+4.p
178170.50/23558.66	% SZS status GaveUp for HL410363+4.p
178170.50/23558.66	eprover: CPU time limit exceeded, terminating
178170.50/23558.66	% SZS status Ended for HL410363+4.p
178180.86/23559.99	% SZS status Started for HL410364+4.p
178180.86/23559.99	% SZS status GaveUp for HL410364+4.p
178180.86/23559.99	eprover: CPU time limit exceeded, terminating
178180.86/23559.99	% SZS status Ended for HL410364+4.p
178184.81/23560.44	% SZS status Started for HL410357+5.p
178184.81/23560.44	% SZS status GaveUp for HL410357+5.p
178184.81/23560.44	eprover: CPU time limit exceeded, terminating
178184.81/23560.44	% SZS status Ended for HL410357+5.p
178194.80/23561.71	% SZS status Started for HL410365+4.p
178194.80/23561.71	% SZS status GaveUp for HL410365+4.p
178194.80/23561.71	eprover: CPU time limit exceeded, terminating
178194.80/23561.71	% SZS status Ended for HL410365+4.p
178197.28/23561.96	% SZS status Started for HL410358+5.p
178197.28/23561.96	% SZS status GaveUp for HL410358+5.p
178197.28/23561.96	eprover: CPU time limit exceeded, terminating
178197.28/23561.96	% SZS status Ended for HL410358+5.p
178208.73/23563.50	% SZS status Started for HL410366+4.p
178208.73/23563.50	% SZS status GaveUp for HL410366+4.p
178208.73/23563.50	eprover: CPU time limit exceeded, terminating
178208.73/23563.50	% SZS status Ended for HL410366+4.p
178210.73/23563.75	% SZS status Started for HL410359+5.p
178210.73/23563.75	% SZS status GaveUp for HL410359+5.p
178210.73/23563.75	eprover: CPU time limit exceeded, terminating
178210.73/23563.75	% SZS status Ended for HL410359+5.p
178222.00/23565.11	% SZS status Started for HL410367+4.p
178222.00/23565.11	% SZS status GaveUp for HL410367+4.p
178222.00/23565.11	eprover: CPU time limit exceeded, terminating
178222.00/23565.11	% SZS status Ended for HL410367+4.p
178224.19/23565.49	% SZS status Started for HL410362+5.p
178224.19/23565.49	% SZS status GaveUp for HL410362+5.p
178224.19/23565.49	eprover: CPU time limit exceeded, terminating
178224.19/23565.49	% SZS status Ended for HL410362+5.p
178235.45/23566.80	% SZS status Started for HL410368+4.p
178235.45/23566.80	% SZS status GaveUp for HL410368+4.p
178235.45/23566.80	eprover: CPU time limit exceeded, terminating
178235.45/23566.80	% SZS status Ended for HL410368+4.p
178235.45/23566.80	% SZS status Started for HL410363+5.p
178235.45/23566.80	% SZS status GaveUp for HL410363+5.p
178235.45/23566.80	eprover: CPU time limit exceeded, terminating
178235.45/23566.80	% SZS status Ended for HL410363+5.p
178249.91/23568.60	% SZS status Started for HL410369+4.p
178249.91/23568.60	% SZS status GaveUp for HL410369+4.p
178249.91/23568.60	eprover: CPU time limit exceeded, terminating
178249.91/23568.60	% SZS status Ended for HL410369+4.p
178254.48/23569.20	% SZS status Started for HL410364+5.p
178254.48/23569.20	% SZS status GaveUp for HL410364+5.p
178254.48/23569.20	eprover: CPU time limit exceeded, terminating
178254.48/23569.20	% SZS status Ended for HL410364+5.p
178259.42/23569.83	% SZS status Started for HL410370+4.p
178259.42/23569.83	% SZS status GaveUp for HL410370+4.p
178259.42/23569.83	eprover: CPU time limit exceeded, terminating
178259.42/23569.83	% SZS status Ended for HL410370+4.p
178267.16/23570.80	% SZS status Started for HL410365+5.p
178267.16/23570.80	% SZS status GaveUp for HL410365+5.p
178267.16/23570.80	eprover: CPU time limit exceeded, terminating
178267.16/23570.80	% SZS status Ended for HL410365+5.p
178278.95/23572.33	% SZS status Started for HL410371+4.p
178278.95/23572.33	% SZS status GaveUp for HL410371+4.p
178278.95/23572.33	eprover: CPU time limit exceeded, terminating
178278.95/23572.33	% SZS status Ended for HL410371+4.p
178278.95/23572.34	% SZS status Started for HL410366+5.p
178278.95/23572.34	% SZS status GaveUp for HL410366+5.p
178278.95/23572.34	eprover: CPU time limit exceeded, terminating
178278.95/23572.34	% SZS status Ended for HL410366+5.p
178291.69/23573.90	% SZS status Started for HL410372+4.p
178291.69/23573.90	% SZS status GaveUp for HL410372+4.p
178291.69/23573.90	eprover: CPU time limit exceeded, terminating
178291.69/23573.90	% SZS status Ended for HL410372+4.p
178292.45/23573.94	% SZS status Started for HL410367+5.p
178292.45/23573.94	% SZS status GaveUp for HL410367+5.p
178292.45/23573.94	eprover: CPU time limit exceeded, terminating
178292.45/23573.94	% SZS status Ended for HL410367+5.p
178303.78/23575.40	% SZS status Started for HL410373+4.p
178303.78/23575.40	% SZS status GaveUp for HL410373+4.p
178303.78/23575.40	eprover: CPU time limit exceeded, terminating
178303.78/23575.40	% SZS status Ended for HL410373+4.p
178309.91/23576.21	% SZS status Started for HL410368+5.p
178309.91/23576.21	% SZS status GaveUp for HL410368+5.p
178309.91/23576.21	eprover: CPU time limit exceeded, terminating
178309.91/23576.21	% SZS status Ended for HL410368+5.p
178316.56/23577.01	% SZS status Started for HL410374+4.p
178316.56/23577.01	% SZS status GaveUp for HL410374+4.p
178316.56/23577.01	eprover: CPU time limit exceeded, terminating
178316.56/23577.01	% SZS status Ended for HL410374+4.p
178317.78/23577.24	% SZS status Started for HL410369+5.p
178317.78/23577.24	% SZS status GaveUp for HL410369+5.p
178317.78/23577.24	eprover: CPU time limit exceeded, terminating
178317.78/23577.24	% SZS status Ended for HL410369+5.p
178333.67/23579.22	% SZS status Started for HL410370+5.p
178333.67/23579.22	% SZS status GaveUp for HL410370+5.p
178333.67/23579.22	eprover: CPU time limit exceeded, terminating
178333.67/23579.22	% SZS status Ended for HL410370+5.p
178334.58/23579.30	% SZS status Started for HL410375+4.p
178334.58/23579.30	% SZS status GaveUp for HL410375+4.p
178334.58/23579.30	eprover: CPU time limit exceeded, terminating
178334.58/23579.30	% SZS status Ended for HL410375+4.p
178342.36/23580.29	% SZS status Started for HL410376+4.p
178342.36/23580.29	% SZS status GaveUp for HL410376+4.p
178342.36/23580.29	eprover: CPU time limit exceeded, terminating
178342.36/23580.29	% SZS status Ended for HL410376+4.p
178344.52/23580.64	% SZS status Started for HL410371+5.p
178344.52/23580.64	% SZS status GaveUp for HL410371+5.p
178344.52/23580.64	eprover: CPU time limit exceeded, terminating
178344.52/23580.64	% SZS status Ended for HL410371+5.p
178358.44/23582.37	% SZS status Started for HL410377+4.p
178358.44/23582.37	% SZS status GaveUp for HL410377+4.p
178358.44/23582.37	eprover: CPU time limit exceeded, terminating
178358.44/23582.37	% SZS status Ended for HL410377+4.p
178361.08/23582.81	% SZS status Started for HL410372+5.p
178361.08/23582.81	% SZS status GaveUp for HL410372+5.p
178361.08/23582.81	eprover: CPU time limit exceeded, terminating
178361.08/23582.81	% SZS status Ended for HL410372+5.p
178369.17/23583.73	% SZS status Started for HL410379+4.p
178369.17/23583.73	% SZS status GaveUp for HL410379+4.p
178369.17/23583.73	eprover: CPU time limit exceeded, terminating
178369.17/23583.73	% SZS status Ended for HL410379+4.p
178375.66/23584.48	% SZS status Started for HL410373+5.p
178375.66/23584.48	% SZS status GaveUp for HL410373+5.p
178375.66/23584.48	eprover: CPU time limit exceeded, terminating
178375.66/23584.48	% SZS status Ended for HL410373+5.p
178386.56/23585.84	% SZS status Started for HL410380+4.p
178386.56/23585.84	% SZS status GaveUp for HL410380+4.p
178386.56/23585.84	eprover: CPU time limit exceeded, terminating
178386.56/23585.84	% SZS status Ended for HL410380+4.p
178387.41/23585.99	% SZS status Started for HL410374+5.p
178387.41/23585.99	% SZS status GaveUp for HL410374+5.p
178387.41/23585.99	eprover: CPU time limit exceeded, terminating
178387.41/23585.99	% SZS status Ended for HL410374+5.p
178399.84/23587.50	% SZS status Started for HL410381+4.p
178399.84/23587.50	% SZS status GaveUp for HL410381+4.p
178399.84/23587.50	eprover: CPU time limit exceeded, terminating
178399.84/23587.50	% SZS status Ended for HL410381+4.p
178400.22/23587.57	% SZS status Started for HL410375+5.p
178400.22/23587.57	% SZS status GaveUp for HL410375+5.p
178400.22/23587.57	eprover: CPU time limit exceeded, terminating
178400.22/23587.57	% SZS status Ended for HL410375+5.p
178411.33/23589.02	% SZS status Started for HL410384+4.p
178411.33/23589.02	% SZS status GaveUp for HL410384+4.p
178411.33/23589.02	eprover: CPU time limit exceeded, terminating
178411.33/23589.02	% SZS status Ended for HL410384+4.p
178416.86/23589.65	% SZS status Started for HL410376+5.p
178416.86/23589.65	% SZS status GaveUp for HL410376+5.p
178416.86/23589.65	eprover: CPU time limit exceeded, terminating
178416.86/23589.65	% SZS status Ended for HL410376+5.p
178424.52/23590.62	% SZS status Started for HL410385+4.p
178424.52/23590.62	% SZS status GaveUp for HL410385+4.p
178424.52/23590.62	eprover: CPU time limit exceeded, terminating
178424.52/23590.62	% SZS status Ended for HL410385+4.p
178425.83/23590.81	% SZS status Started for HL410377+5.p
178425.83/23590.81	% SZS status GaveUp for HL410377+5.p
178425.83/23590.81	eprover: CPU time limit exceeded, terminating
178425.83/23590.81	% SZS status Ended for HL410377+5.p
178441.09/23592.69	% SZS status Started for HL410386+4.p
178441.09/23592.69	% SZS status GaveUp for HL410386+4.p
178441.09/23592.69	eprover: CPU time limit exceeded, terminating
178441.09/23592.69	% SZS status Ended for HL410386+4.p
178443.97/23593.17	% SZS status Started for HL410379+5.p
178443.97/23593.17	% SZS status GaveUp for HL410379+5.p
178443.97/23593.17	eprover: CPU time limit exceeded, terminating
178443.97/23593.17	% SZS status Ended for HL410379+5.p
178449.88/23593.85	% SZS status Started for HL410390+4.p
178449.88/23593.85	% SZS status GaveUp for HL410390+4.p
178449.88/23593.85	eprover: CPU time limit exceeded, terminating
178449.88/23593.85	% SZS status Ended for HL410390+4.p
178454.59/23594.46	% SZS status Started for HL410380+5.p
178454.59/23594.46	% SZS status GaveUp for HL410380+5.p
178454.59/23594.46	eprover: CPU time limit exceeded, terminating
178454.59/23594.46	% SZS status Ended for HL410380+5.p
178468.62/23596.20	% SZS status Started for HL410391+4.p
178468.62/23596.20	% SZS status GaveUp for HL410391+4.p
178468.62/23596.20	eprover: CPU time limit exceeded, terminating
178468.62/23596.20	% SZS status Ended for HL410391+4.p
178472.42/23596.64	% SZS status Started for HL410381+5.p
178472.42/23596.64	% SZS status GaveUp for HL410381+5.p
178472.42/23596.64	eprover: CPU time limit exceeded, terminating
178472.42/23596.64	% SZS status Ended for HL410381+5.p
178478.86/23597.50	% SZS status Started for HL410393+4.p
178478.86/23597.50	% SZS status GaveUp for HL410393+4.p
178478.86/23597.50	eprover: CPU time limit exceeded, terminating
178478.86/23597.50	% SZS status Ended for HL410393+4.p
178483.34/23598.02	% SZS status Started for HL410384+5.p
178483.34/23598.02	% SZS status GaveUp for HL410384+5.p
178483.34/23598.02	eprover: CPU time limit exceeded, terminating
178483.34/23598.02	% SZS status Ended for HL410384+5.p
178492.80/23599.24	% SZS status Started for HL410393+5.p
178492.80/23599.24	% SZS status GaveUp for HL410393+5.p
178492.80/23599.24	eprover: CPU time limit exceeded, terminating
178492.80/23599.24	% SZS status Ended for HL410393+5.p
178494.88/23599.46	% SZS status Started for HL410385+5.p
178494.88/23599.46	% SZS status GaveUp for HL410385+5.p
178494.88/23599.46	eprover: CPU time limit exceeded, terminating
178494.88/23599.46	% SZS status Ended for HL410385+5.p
178496.20/23599.70	% SZS status Started for HL410395+4.p
178496.20/23599.70	% SZS status GaveUp for HL410395+4.p
178496.20/23599.70	eprover: CPU time limit exceeded, terminating
178496.20/23599.70	% SZS status Ended for HL410395+4.p
178507.45/23601.06	% SZS status Started for HL410398+4.p
178507.45/23601.06	% SZS status GaveUp for HL410398+4.p
178507.45/23601.06	eprover: CPU time limit exceeded, terminating
178507.45/23601.06	% SZS status Ended for HL410398+4.p
178507.45/23601.07	% SZS status Started for HL410386+5.p
178507.45/23601.07	% SZS status GaveUp for HL410386+5.p
178507.45/23601.07	eprover: CPU time limit exceeded, terminating
178507.45/23601.07	% SZS status Ended for HL410386+5.p
178518.81/23602.50	% SZS status Started for HL410399+4.p
178518.81/23602.50	% SZS status GaveUp for HL410399+4.p
178518.81/23602.50	eprover: CPU time limit exceeded, terminating
178518.81/23602.50	% SZS status Ended for HL410399+4.p
178525.05/23603.32	% SZS status Started for HL410390+5.p
178525.05/23603.32	% SZS status GaveUp for HL410390+5.p
178525.05/23603.32	eprover: CPU time limit exceeded, terminating
178525.05/23603.32	% SZS status Ended for HL410390+5.p
178531.14/23604.09	% SZS status Started for HL410400+4.p
178531.14/23604.09	% SZS status GaveUp for HL410400+4.p
178531.14/23604.09	eprover: CPU time limit exceeded, terminating
178531.14/23604.09	% SZS status Ended for HL410400+4.p
178535.91/23604.64	% SZS status Started for HL410391+5.p
178535.91/23604.64	% SZS status GaveUp for HL410391+5.p
178535.91/23604.64	eprover: CPU time limit exceeded, terminating
178535.91/23604.64	% SZS status Ended for HL410391+5.p
178542.83/23605.54	% SZS status Started for HL410401+4.p
178542.83/23605.54	% SZS status GaveUp for HL410401+4.p
178542.83/23605.54	eprover: CPU time limit exceeded, terminating
178542.83/23605.54	% SZS status Ended for HL410401+4.p
178555.23/23607.11	% SZS status Started for HL410403+4.p
178555.23/23607.11	% SZS status GaveUp for HL410403+4.p
178555.23/23607.11	eprover: CPU time limit exceeded, terminating
178555.23/23607.11	% SZS status Ended for HL410403+4.p
178561.94/23607.99	% SZS status Started for HL410395+5.p
178561.94/23607.99	% SZS status GaveUp for HL410395+5.p
178561.94/23607.99	eprover: CPU time limit exceeded, terminating
178561.94/23607.99	% SZS status Ended for HL410395+5.p
178567.52/23608.61	% SZS status Started for HL410404+4.p
178567.52/23608.61	% SZS status GaveUp for HL410404+4.p
178567.52/23608.61	eprover: CPU time limit exceeded, terminating
178567.52/23608.61	% SZS status Ended for HL410404+4.p
178575.84/23609.73	% SZS status Started for HL410398+5.p
178575.84/23609.73	% SZS status GaveUp for HL410398+5.p
178575.84/23609.73	eprover: CPU time limit exceeded, terminating
178575.84/23609.73	% SZS status Ended for HL410398+5.p
178578.53/23610.15	% SZS status Started for HL410404+5.p
178578.53/23610.15	% SZS status GaveUp for HL410404+5.p
178578.53/23610.15	eprover: CPU time limit exceeded, terminating
178578.53/23610.15	% SZS status Ended for HL410404+5.p
178582.72/23610.58	% SZS status Started for HL410399+5.p
178582.72/23610.58	% SZS status GaveUp for HL410399+5.p
178582.72/23610.58	eprover: CPU time limit exceeded, terminating
178582.72/23610.58	% SZS status Ended for HL410399+5.p
178586.89/23611.11	% SZS status Started for HL410406+4.p
178586.89/23611.11	% SZS status GaveUp for HL410406+4.p
178586.89/23611.11	eprover: CPU time limit exceeded, terminating
178586.89/23611.11	% SZS status Ended for HL410406+4.p
178592.44/23611.76	% SZS status Started for HL410400+5.p
178592.44/23611.76	% SZS status GaveUp for HL410400+5.p
178592.44/23611.76	eprover: CPU time limit exceeded, terminating
178592.44/23611.76	% SZS status Ended for HL410400+5.p
178600.28/23612.76	% SZS status Started for HL410407+4.p
178600.28/23612.76	% SZS status GaveUp for HL410407+4.p
178600.28/23612.76	eprover: CPU time limit exceeded, terminating
178600.28/23612.76	% SZS status Ended for HL410407+4.p
178607.50/23613.63	% SZS status Started for HL410408+4.p
178607.50/23613.63	% SZS status GaveUp for HL410408+4.p
178607.50/23613.63	eprover: CPU time limit exceeded, terminating
178607.50/23613.63	% SZS status Ended for HL410408+4.p
178609.77/23613.95	% SZS status Started for HL410401+5.p
178609.77/23613.95	% SZS status GaveUp for HL410401+5.p
178609.77/23613.95	eprover: CPU time limit exceeded, terminating
178609.77/23613.95	% SZS status Ended for HL410401+5.p
178617.00/23614.82	% SZS status Started for HL410409+4.p
178617.00/23614.82	% SZS status GaveUp for HL410409+4.p
178617.00/23614.82	eprover: CPU time limit exceeded, terminating
178617.00/23614.82	% SZS status Ended for HL410409+4.p
178619.48/23615.19	% SZS status Started for HL410403+5.p
178619.48/23615.19	% SZS status GaveUp for HL410403+5.p
178619.48/23615.19	eprover: CPU time limit exceeded, terminating
178619.48/23615.19	% SZS status Ended for HL410403+5.p
178630.92/23616.70	% SZS status Started for HL410410+4.p
178630.92/23616.70	% SZS status GaveUp for HL410410+4.p
178630.92/23616.70	eprover: CPU time limit exceeded, terminating
178630.92/23616.70	% SZS status Ended for HL410410+4.p
178639.73/23617.85	% SZS status Started for HL410412+4.p
178639.73/23617.85	% SZS status GaveUp for HL410412+4.p
178639.73/23617.85	eprover: CPU time limit exceeded, terminating
178639.73/23617.85	% SZS status Ended for HL410412+4.p
178652.12/23619.28	% SZS status Started for HL410406+5.p
178652.12/23619.28	% SZS status GaveUp for HL410406+5.p
178652.12/23619.28	eprover: CPU time limit exceeded, terminating
178652.12/23619.28	% SZS status Ended for HL410406+5.p
178654.69/23619.74	% SZS status Started for HL410413+4.p
178654.69/23619.74	% SZS status GaveUp for HL410413+4.p
178654.69/23619.74	eprover: CPU time limit exceeded, terminating
178654.69/23619.74	% SZS status Ended for HL410413+4.p
178662.44/23620.63	% SZS status Started for HL410407+5.p
178662.44/23620.63	% SZS status GaveUp for HL410407+5.p
178662.44/23620.63	eprover: CPU time limit exceeded, terminating
178662.44/23620.63	% SZS status Ended for HL410407+5.p
178670.28/23621.54	% SZS status Started for HL410408+5.p
178670.28/23621.54	% SZS status GaveUp for HL410408+5.p
178670.28/23621.54	eprover: CPU time limit exceeded, terminating
178670.28/23621.54	% SZS status Ended for HL410408+5.p
178676.08/23622.33	% SZS status Started for HL410414+4.p
178676.08/23622.33	% SZS status GaveUp for HL410414+4.p
178676.08/23622.33	eprover: CPU time limit exceeded, terminating
178676.08/23622.33	% SZS status Ended for HL410414+4.p
178686.59/23623.67	% SZS status Started for HL410409+5.p
178686.59/23623.67	% SZS status GaveUp for HL410409+5.p
178686.59/23623.67	eprover: CPU time limit exceeded, terminating
178686.59/23623.67	% SZS status Ended for HL410409+5.p
178686.59/23623.70	% SZS status Started for HL410416+4.p
178686.59/23623.70	% SZS status GaveUp for HL410416+4.p
178686.59/23623.70	eprover: CPU time limit exceeded, terminating
178686.59/23623.70	% SZS status Ended for HL410416+4.p
178695.39/23624.49	% SZS status Started for HL410410+5.p
178695.39/23624.49	% SZS status GaveUp for HL410410+5.p
178695.39/23624.49	eprover: CPU time limit exceeded, terminating
178695.39/23624.49	% SZS status Ended for HL410410+5.p
178703.34/23625.39	% SZS status Started for HL410417+4.p
178703.34/23625.39	% SZS status GaveUp for HL410417+4.p
178703.34/23625.39	eprover: CPU time limit exceeded, terminating
178703.34/23625.39	% SZS status Ended for HL410417+4.p
178709.03/23626.15	% SZS status Started for HL410412+5.p
178709.03/23626.15	% SZS status GaveUp for HL410412+5.p
178709.03/23626.15	eprover: CPU time limit exceeded, terminating
178709.03/23626.15	% SZS status Ended for HL410412+5.p
178713.53/23626.73	% SZS status Started for HL410418+4.p
178713.53/23626.73	% SZS status GaveUp for HL410418+4.p
178713.53/23626.73	eprover: CPU time limit exceeded, terminating
178713.53/23626.73	% SZS status Ended for HL410418+4.p
178727.62/23628.42	% SZS status Started for HL410419+4.p
178727.62/23628.42	% SZS status GaveUp for HL410419+4.p
178727.62/23628.42	eprover: CPU time limit exceeded, terminating
178727.62/23628.42	% SZS status Ended for HL410419+4.p
178728.58/23628.56	% SZS status Started for HL410413+5.p
178728.58/23628.56	% SZS status GaveUp for HL410413+5.p
178728.58/23628.56	eprover: CPU time limit exceeded, terminating
178728.58/23628.56	% SZS status Ended for HL410413+5.p
178738.05/23629.77	% SZS status Started for HL410421+4.p
178738.05/23629.77	% SZS status GaveUp for HL410421+4.p
178738.05/23629.77	eprover: CPU time limit exceeded, terminating
178738.05/23629.77	% SZS status Ended for HL410421+4.p
178741.55/23630.19	% SZS status Started for HL410414+5.p
178741.55/23630.19	% SZS status GaveUp for HL410414+5.p
178741.55/23630.19	eprover: CPU time limit exceeded, terminating
178741.55/23630.19	% SZS status Ended for HL410414+5.p
178752.47/23631.61	% SZS status Started for HL410422+4.p
178752.47/23631.61	% SZS status GaveUp for HL410422+4.p
178752.47/23631.61	eprover: CPU time limit exceeded, terminating
178752.47/23631.61	% SZS status Ended for HL410422+4.p
178760.62/23632.69	% SZS status Started for HL410416+5.p
178760.62/23632.69	% SZS status GaveUp for HL410416+5.p
178760.62/23632.69	eprover: CPU time limit exceeded, terminating
178760.62/23632.69	% SZS status Ended for HL410416+5.p
178765.20/23633.28	% SZS status Started for HL410423+4.p
178765.20/23633.28	% SZS status GaveUp for HL410423+4.p
178765.20/23633.28	eprover: CPU time limit exceeded, terminating
178765.20/23633.28	% SZS status Ended for HL410423+4.p
178772.17/23634.36	% SZS status Started for HL410417+5.p
178772.17/23634.36	% SZS status GaveUp for HL410417+5.p
178772.17/23634.36	eprover: CPU time limit exceeded, terminating
178772.17/23634.36	% SZS status Ended for HL410417+5.p
178778.55/23635.04	% SZS status Started for HL410418+5.p
178778.55/23635.04	% SZS status GaveUp for HL410418+5.p
178778.55/23635.04	eprover: CPU time limit exceeded, terminating
178778.55/23635.04	% SZS status Ended for HL410418+5.p
178783.98/23635.74	% SZS status Started for HL410425+4.p
178783.98/23635.74	% SZS status GaveUp for HL410425+4.p
178783.98/23635.74	eprover: CPU time limit exceeded, terminating
178783.98/23635.74	% SZS status Ended for HL410425+4.p
178792.91/23636.83	% SZS status Started for HL410419+5.p
178792.91/23636.83	% SZS status GaveUp for HL410419+5.p
178792.91/23636.83	eprover: CPU time limit exceeded, terminating
178792.91/23636.83	% SZS status Ended for HL410419+5.p
178797.61/23637.51	% SZS status Started for HL410426+4.p
178797.61/23637.51	% SZS status GaveUp for HL410426+4.p
178797.61/23637.51	eprover: CPU time limit exceeded, terminating
178797.61/23637.51	% SZS status Ended for HL410426+4.p
178808.12/23638.80	% SZS status Started for HL410430+4.p
178808.12/23638.80	% SZS status GaveUp for HL410430+4.p
178808.12/23638.80	eprover: CPU time limit exceeded, terminating
178808.12/23638.80	% SZS status Ended for HL410430+4.p
178810.12/23639.03	% SZS status Started for HL410421+5.p
178810.12/23639.03	% SZS status GaveUp for HL410421+5.p
178810.12/23639.03	eprover: CPU time limit exceeded, terminating
178810.12/23639.03	% SZS status Ended for HL410421+5.p
178822.16/23640.53	% SZS status Started for HL410431+4.p
178822.16/23640.53	% SZS status GaveUp for HL410431+4.p
178822.16/23640.53	eprover: CPU time limit exceeded, terminating
178822.16/23640.53	% SZS status Ended for HL410431+4.p
178823.55/23640.76	% SZS status Started for HL410422+5.p
178823.55/23640.76	% SZS status GaveUp for HL410422+5.p
178823.55/23640.76	eprover: CPU time limit exceeded, terminating
178823.55/23640.76	% SZS status Ended for HL410422+5.p
178833.67/23642.11	% SZS status Started for HL410423+5.p
178833.67/23642.11	% SZS status GaveUp for HL410423+5.p
178833.67/23642.11	eprover: CPU time limit exceeded, terminating
178833.67/23642.11	% SZS status Ended for HL410423+5.p
178833.67/23642.12	% SZS status Started for HL410433+4.p
178833.67/23642.12	% SZS status GaveUp for HL410433+4.p
178833.67/23642.12	eprover: CPU time limit exceeded, terminating
178833.67/23642.12	% SZS status Ended for HL410433+4.p
178847.72/23643.79	% SZS status Started for HL410434+4.p
178847.72/23643.79	% SZS status GaveUp for HL410434+4.p
178847.72/23643.79	eprover: CPU time limit exceeded, terminating
178847.72/23643.79	% SZS status Ended for HL410434+4.p
178858.17/23645.06	% SZS status Started for HL410425+5.p
178858.17/23645.06	% SZS status GaveUp for HL410425+5.p
178858.17/23645.06	eprover: CPU time limit exceeded, terminating
178858.17/23645.06	% SZS status Ended for HL410425+5.p
178858.92/23645.19	% SZS status Started for HL410435+4.p
178858.92/23645.19	% SZS status GaveUp for HL410435+4.p
178858.92/23645.19	eprover: CPU time limit exceeded, terminating
178858.92/23645.19	% SZS status Ended for HL410435+4.p
178863.53/23645.77	% SZS status Started for HL410426+5.p
178863.53/23645.77	% SZS status GaveUp for HL410426+5.p
178863.53/23645.77	eprover: CPU time limit exceeded, terminating
178863.53/23645.77	% SZS status Ended for HL410426+5.p
178876.44/23647.39	% SZS status Started for HL410430+5.p
178876.44/23647.39	% SZS status GaveUp for HL410430+5.p
178876.44/23647.39	eprover: CPU time limit exceeded, terminating
178876.44/23647.39	% SZS status Ended for HL410430+5.p
178881.97/23648.09	% SZS status Started for HL410436+4.p
178881.97/23648.09	% SZS status GaveUp for HL410436+4.p
178881.97/23648.09	eprover: CPU time limit exceeded, terminating
178881.97/23648.09	% SZS status Ended for HL410436+4.p
178887.30/23648.82	% SZS status Started for HL410437+4.p
178887.30/23648.82	% SZS status GaveUp for HL410437+4.p
178887.30/23648.82	eprover: CPU time limit exceeded, terminating
178887.30/23648.82	% SZS status Ended for HL410437+4.p
178895.41/23649.85	% SZS status Started for HL410431+5.p
178895.41/23649.85	% SZS status GaveUp for HL410431+5.p
178895.41/23649.85	eprover: CPU time limit exceeded, terminating
178895.41/23649.85	% SZS status Ended for HL410431+5.p
178905.31/23651.09	% SZS status Started for HL410433+5.p
178905.31/23651.09	% SZS status GaveUp for HL410433+5.p
178905.31/23651.09	eprover: CPU time limit exceeded, terminating
178905.31/23651.09	% SZS status Ended for HL410433+5.p
178905.31/23651.11	% SZS status Started for HL410438+4.p
178905.31/23651.11	% SZS status GaveUp for HL410438+4.p
178905.31/23651.11	eprover: CPU time limit exceeded, terminating
178905.31/23651.11	% SZS status Ended for HL410438+4.p
178917.73/23652.59	% SZS status Started for HL410434+5.p
178917.73/23652.59	% SZS status GaveUp for HL410434+5.p
178917.73/23652.59	eprover: CPU time limit exceeded, terminating
178917.73/23652.59	% SZS status Ended for HL410434+5.p
178919.78/23652.89	% SZS status Started for HL410439+4.p
178919.78/23652.89	% SZS status GaveUp for HL410439+4.p
178919.78/23652.89	eprover: CPU time limit exceeded, terminating
178919.78/23652.89	% SZS status Ended for HL410439+4.p
178930.28/23654.14	% SZS status Started for HL410440+4.p
178930.28/23654.14	% SZS status GaveUp for HL410440+4.p
178930.28/23654.14	eprover: CPU time limit exceeded, terminating
178930.28/23654.14	% SZS status Ended for HL410440+4.p
178931.38/23654.31	% SZS status Started for HL410435+5.p
178931.38/23654.31	% SZS status GaveUp for HL410435+5.p
178931.38/23654.31	eprover: CPU time limit exceeded, terminating
178931.38/23654.31	% SZS status Ended for HL410435+5.p
178943.34/23655.79	% SZS status Started for HL410436+5.p
178943.34/23655.79	% SZS status GaveUp for HL410436+5.p
178943.34/23655.79	eprover: CPU time limit exceeded, terminating
178943.34/23655.79	% SZS status Ended for HL410436+5.p
178945.16/23656.10	% SZS status Started for HL410441+4.p
178945.16/23656.10	% SZS status GaveUp for HL410441+4.p
178945.16/23656.10	eprover: CPU time limit exceeded, terminating
178945.16/23656.10	% SZS status Ended for HL410441+4.p
178954.44/23657.34	% SZS status Started for HL410442+4.p
178954.44/23657.34	% SZS status GaveUp for HL410442+4.p
178954.44/23657.34	eprover: CPU time limit exceeded, terminating
178954.44/23657.34	% SZS status Ended for HL410442+4.p
178960.88/23658.01	% SZS status Started for HL410437+5.p
178960.88/23658.01	% SZS status GaveUp for HL410437+5.p
178960.88/23658.01	eprover: CPU time limit exceeded, terminating
178960.88/23658.01	% SZS status Ended for HL410437+5.p
178967.58/23658.89	% SZS status Started for HL410442+5.p
178967.58/23658.89	% SZS status GaveUp for HL410442+5.p
178967.58/23658.89	eprover: CPU time limit exceeded, terminating
178967.58/23658.89	% SZS status Ended for HL410442+5.p
178969.36/23659.14	% SZS status Started for HL410443+4.p
178969.36/23659.14	% SZS status GaveUp for HL410443+4.p
178969.36/23659.14	eprover: CPU time limit exceeded, terminating
178969.36/23659.14	% SZS status Ended for HL410443+4.p
178970.61/23659.33	% SZS status Started for HL410438+5.p
178970.61/23659.33	% SZS status GaveUp for HL410438+5.p
178970.61/23659.33	eprover: CPU time limit exceeded, terminating
178970.61/23659.33	% SZS status Ended for HL410438+5.p
178979.28/23660.38	% SZS status Started for HL410443+5.p
178979.28/23660.38	% SZS status GaveUp for HL410443+5.p
178979.28/23660.38	eprover: CPU time limit exceeded, terminating
178979.28/23660.38	% SZS status Ended for HL410443+5.p
178985.86/23661.16	% SZS status Started for HL410444+4.p
178985.86/23661.16	% SZS status GaveUp for HL410444+4.p
178985.86/23661.16	eprover: CPU time limit exceeded, terminating
178985.86/23661.16	% SZS status Ended for HL410444+4.p
178989.28/23661.62	% SZS status Started for HL410439+5.p
178989.28/23661.62	% SZS status GaveUp for HL410439+5.p
178989.28/23661.62	eprover: CPU time limit exceeded, terminating
178989.28/23661.62	% SZS status Ended for HL410439+5.p
178991.48/23661.93	% SZS status Started for HL410444+5.p
178991.48/23661.93	% SZS status GaveUp for HL410444+5.p
178991.48/23661.93	eprover: CPU time limit exceeded, terminating
178991.48/23661.93	% SZS status Ended for HL410444+5.p
178993.67/23662.17	% SZS status Started for HL410445+4.p
178993.67/23662.17	% SZS status GaveUp for HL410445+4.p
178993.67/23662.17	eprover: CPU time limit exceeded, terminating
178993.67/23662.17	% SZS status Ended for HL410445+4.p
178994.52/23662.37	% SZS status Started for HL410445+5.p
178994.52/23662.37	% SZS status GaveUp for HL410445+5.p
178994.52/23662.37	eprover: CPU time limit exceeded, terminating
178994.52/23662.37	% SZS status Ended for HL410445+5.p
179001.27/23663.11	% SZS status Started for HL410440+5.p
179001.27/23663.11	% SZS status GaveUp for HL410440+5.p
179001.27/23663.11	eprover: CPU time limit exceeded, terminating
179001.27/23663.11	% SZS status Ended for HL410440+5.p
179003.22/23663.45	% SZS status Started for HL410446+4.p
179003.22/23663.45	% SZS status GaveUp for HL410446+4.p
179003.22/23663.45	eprover: CPU time limit exceeded, terminating
179003.22/23663.45	% SZS status Ended for HL410446+4.p
179010.02/23664.20	% SZS status Started for HL410446+5.p
179010.02/23664.20	% SZS status GaveUp for HL410446+5.p
179010.02/23664.20	eprover: CPU time limit exceeded, terminating
179010.02/23664.20	% SZS status Ended for HL410446+5.p
179013.36/23664.65	% SZS status Started for HL410448+4.p
179013.36/23664.65	% SZS status GaveUp for HL410448+4.p
179013.36/23664.65	eprover: CPU time limit exceeded, terminating
179013.36/23664.65	% SZS status Ended for HL410448+4.p
179015.89/23664.98	% SZS status Started for HL410448+5.p
179015.89/23664.98	% SZS status GaveUp for HL410448+5.p
179015.89/23664.98	eprover: CPU time limit exceeded, terminating
179015.89/23664.98	% SZS status Ended for HL410448+5.p
179017.30/23665.20	% SZS status Started for HL410441+5.p
179017.30/23665.20	% SZS status GaveUp for HL410441+5.p
179017.30/23665.20	eprover: CPU time limit exceeded, terminating
179017.30/23665.20	% SZS status Ended for HL410441+5.p
179020.39/23665.56	% SZS status Started for HL410449+5.p
179020.39/23665.56	% SZS status GaveUp for HL410449+5.p
179020.39/23665.56	eprover: CPU time limit exceeded, terminating
179020.39/23665.56	% SZS status Ended for HL410449+5.p
179020.66/23665.62	% SZS status Started for HL410449+4.p
179020.66/23665.62	% SZS status GaveUp for HL410449+4.p
179020.66/23665.62	eprover: CPU time limit exceeded, terminating
179020.66/23665.62	% SZS status Ended for HL410449+4.p
179024.97/23666.16	% SZS status Started for HL410450+4.p
179024.97/23666.16	% SZS status GaveUp for HL410450+4.p
179024.97/23666.16	eprover: CPU time limit exceeded, terminating
179024.97/23666.16	% SZS status Ended for HL410450+4.p
179027.88/23666.50	% SZS status Started for HL410450+5.p
179027.88/23666.50	% SZS status GaveUp for HL410450+5.p
179027.88/23666.50	eprover: CPU time limit exceeded, terminating
179027.88/23666.50	% SZS status Ended for HL410450+5.p
179033.25/23667.30	% SZS status Started for HL410451+4.p
179033.25/23667.30	% SZS status GaveUp for HL410451+4.p
179033.25/23667.30	eprover: CPU time limit exceeded, terminating
179033.25/23667.30	% SZS status Ended for HL410451+4.p
179037.70/23667.93	% SZS status Started for HL410451+5.p
179037.70/23667.93	% SZS status GaveUp for HL410451+5.p
179037.70/23667.93	eprover: CPU time limit exceeded, terminating
179037.70/23667.93	% SZS status Ended for HL410451+5.p
179038.70/23668.01	% SZS status Started for HL410453+4.p
179038.70/23668.01	% SZS status GaveUp for HL410453+4.p
179038.70/23668.01	eprover: CPU time limit exceeded, terminating
179038.70/23668.01	% SZS status Ended for HL410453+4.p
179039.73/23668.24	% SZS status Started for HL410453+5.p
179039.73/23668.24	% SZS status GaveUp for HL410453+5.p
179039.73/23668.24	eprover: CPU time limit exceeded, terminating
179039.73/23668.24	% SZS status Ended for HL410453+5.p
179042.83/23668.59	% SZS status Started for HL410454+4.p
179042.83/23668.59	% SZS status GaveUp for HL410454+4.p
179042.83/23668.59	eprover: CPU time limit exceeded, terminating
179042.83/23668.59	% SZS status Ended for HL410454+4.p
179047.14/23669.05	% SZS status Started for HL410454+5.p
179047.14/23669.05	% SZS status GaveUp for HL410454+5.p
179047.14/23669.05	eprover: CPU time limit exceeded, terminating
179047.14/23669.05	% SZS status Ended for HL410454+5.p
179048.77/23669.32	% SZS status Started for HL410455+4.p
179048.77/23669.32	% SZS status GaveUp for HL410455+4.p
179048.77/23669.32	eprover: CPU time limit exceeded, terminating
179048.77/23669.32	% SZS status Ended for HL410455+4.p
179053.58/23669.89	% SZS status Started for HL410455+5.p
179053.58/23669.89	% SZS status GaveUp for HL410455+5.p
179053.58/23669.89	eprover: CPU time limit exceeded, terminating
179053.58/23669.89	% SZS status Ended for HL410455+5.p
179058.31/23670.45	% SZS status Started for HL410456+4.p
179058.31/23670.45	% SZS status GaveUp for HL410456+4.p
179058.31/23670.45	eprover: CPU time limit exceeded, terminating
179058.31/23670.45	% SZS status Ended for HL410456+4.p
179061.97/23670.99	% SZS status Started for HL410456+5.p
179061.97/23670.99	% SZS status GaveUp for HL410456+5.p
179061.97/23670.99	eprover: CPU time limit exceeded, terminating
179061.97/23670.99	% SZS status Ended for HL410456+5.p
179061.97/23671.04	% SZS status Started for HL410457+4.p
179061.97/23671.04	% SZS status GaveUp for HL410457+4.p
179061.97/23671.04	eprover: CPU time limit exceeded, terminating
179061.97/23671.04	% SZS status Ended for HL410457+4.p
179064.50/23671.30	% SZS status Started for HL410457+5.p
179064.50/23671.30	% SZS status GaveUp for HL410457+5.p
179064.50/23671.30	eprover: CPU time limit exceeded, terminating
179064.50/23671.30	% SZS status Ended for HL410457+5.p
179068.05/23671.72	% SZS status Started for HL410459+4.p
179068.05/23671.72	% SZS status GaveUp for HL410459+4.p
179068.05/23671.72	eprover: CPU time limit exceeded, terminating
179068.05/23671.72	% SZS status Ended for HL410459+4.p
179070.55/23672.10	% SZS status Started for HL410459+5.p
179070.55/23672.10	% SZS status GaveUp for HL410459+5.p
179070.55/23672.10	eprover: CPU time limit exceeded, terminating
179070.55/23672.10	% SZS status Ended for HL410459+5.p
179073.27/23672.38	% SZS status Started for HL410460+4.p
179073.27/23672.38	% SZS status GaveUp for HL410460+4.p
179073.27/23672.38	eprover: CPU time limit exceeded, terminating
179073.27/23672.38	% SZS status Ended for HL410460+4.p
179077.75/23672.96	% SZS status Started for HL410460+5.p
179077.75/23672.96	% SZS status GaveUp for HL410460+5.p
179077.75/23672.96	eprover: CPU time limit exceeded, terminating
179077.75/23672.96	% SZS status Ended for HL410460+5.p
179082.02/23673.48	% SZS status Started for HL410463+4.p
179082.02/23673.48	% SZS status GaveUp for HL410463+4.p
179082.02/23673.48	eprover: CPU time limit exceeded, terminating
179082.02/23673.48	% SZS status Ended for HL410463+4.p
179086.38/23674.08	% SZS status Started for HL410464+4.p
179086.38/23674.08	% SZS status GaveUp for HL410464+4.p
179086.38/23674.08	eprover: CPU time limit exceeded, terminating
179086.38/23674.08	% SZS status Ended for HL410464+4.p
179087.55/23674.24	% SZS status Started for HL410463+5.p
179087.55/23674.24	% SZS status GaveUp for HL410463+5.p
179087.55/23674.24	eprover: CPU time limit exceeded, terminating
179087.55/23674.24	% SZS status Ended for HL410463+5.p
179088.97/23674.41	% SZS status Started for HL410464+5.p
179088.97/23674.41	% SZS status GaveUp for HL410464+5.p
179088.97/23674.41	eprover: CPU time limit exceeded, terminating
179088.97/23674.41	% SZS status Ended for HL410464+5.p
179091.83/23674.75	% SZS status Started for HL410465+4.p
179091.83/23674.75	% SZS status GaveUp for HL410465+4.p
179091.83/23674.75	eprover: CPU time limit exceeded, terminating
179091.83/23674.75	% SZS status Ended for HL410465+4.p
179094.36/23675.16	% SZS status Started for HL410465+5.p
179094.36/23675.16	% SZS status GaveUp for HL410465+5.p
179094.36/23675.16	eprover: CPU time limit exceeded, terminating
179094.36/23675.16	% SZS status Ended for HL410465+5.p
179096.80/23675.44	% SZS status Started for HL410466+4.p
179096.80/23675.44	% SZS status GaveUp for HL410466+4.p
179096.80/23675.44	eprover: CPU time limit exceeded, terminating
179096.80/23675.44	% SZS status Ended for HL410466+4.p
179101.70/23676.04	% SZS status Started for HL410466+5.p
179101.70/23676.04	% SZS status GaveUp for HL410466+5.p
179101.70/23676.04	eprover: CPU time limit exceeded, terminating
179101.70/23676.04	% SZS status Ended for HL410466+5.p
179105.02/23676.53	% SZS status Started for HL410467+4.p
179105.02/23676.53	% SZS status GaveUp for HL410467+4.p
179105.02/23676.53	eprover: CPU time limit exceeded, terminating
179105.02/23676.53	% SZS status Ended for HL410467+4.p
179110.36/23677.19	% SZS status Started for HL410467+5.p
179110.36/23677.19	% SZS status GaveUp for HL410467+5.p
179110.36/23677.19	eprover: CPU time limit exceeded, terminating
179110.36/23677.19	% SZS status Ended for HL410467+5.p
179111.19/23677.31	% SZS status Started for HL410468+4.p
179111.19/23677.31	% SZS status GaveUp for HL410468+4.p
179111.19/23677.31	eprover: CPU time limit exceeded, terminating
179111.19/23677.31	% SZS status Ended for HL410468+4.p
179113.23/23677.61	% SZS status Started for HL410468+5.p
179113.23/23677.61	% SZS status GaveUp for HL410468+5.p
179113.23/23677.61	eprover: CPU time limit exceeded, terminating
179113.23/23677.61	% SZS status Ended for HL410468+5.p
179115.11/23677.96	% SZS status Started for HL410469+4.p
179115.11/23677.96	% SZS status GaveUp for HL410469+4.p
179115.11/23677.96	eprover: CPU time limit exceeded, terminating
179115.11/23677.96	% SZS status Ended for HL410469+4.p
179122.11/23678.73	% SZS status Started for HL410471+4.p
179122.11/23678.73	% SZS status GaveUp for HL410471+4.p
179122.11/23678.73	eprover: CPU time limit exceeded, terminating
179122.11/23678.73	% SZS status Ended for HL410471+4.p
179126.75/23679.27	% SZS status Started for HL410471+5.p
179126.75/23679.27	% SZS status GaveUp for HL410471+5.p
179126.75/23679.27	eprover: CPU time limit exceeded, terminating
179126.75/23679.27	% SZS status Ended for HL410471+5.p
179128.70/23679.63	% SZS status Started for HL410473+4.p
179128.70/23679.63	% SZS status GaveUp for HL410473+4.p
179128.70/23679.63	eprover: CPU time limit exceeded, terminating
179128.70/23679.63	% SZS status Ended for HL410473+4.p
179134.45/23680.34	% SZS status Started for HL410474+4.p
179134.45/23680.34	% SZS status GaveUp for HL410474+4.p
179134.45/23680.34	eprover: CPU time limit exceeded, terminating
179134.45/23680.34	% SZS status Ended for HL410474+4.p
179135.92/23680.55	% SZS status Started for HL410473+5.p
179135.92/23680.55	% SZS status GaveUp for HL410473+5.p
179135.92/23680.55	eprover: CPU time limit exceeded, terminating
179135.92/23680.55	% SZS status Ended for HL410473+5.p
179138.53/23680.85	% SZS status Started for HL410474+5.p
179138.53/23680.85	% SZS status GaveUp for HL410474+5.p
179138.53/23680.85	eprover: CPU time limit exceeded, terminating
179138.53/23680.85	% SZS status Ended for HL410474+5.p
179140.03/23681.10	% SZS status Started for HL410477+4.p
179140.03/23681.10	% SZS status GaveUp for HL410477+4.p
179140.03/23681.10	eprover: CPU time limit exceeded, terminating
179140.03/23681.10	% SZS status Ended for HL410477+4.p
179145.89/23681.80	% SZS status Started for HL410477+5.p
179145.89/23681.80	% SZS status GaveUp for HL410477+5.p
179145.89/23681.80	eprover: CPU time limit exceeded, terminating
179145.89/23681.80	% SZS status Ended for HL410477+5.p
179150.91/23682.40	% SZS status Started for HL410478+4.p
179150.91/23682.40	% SZS status GaveUp for HL410478+4.p
179150.91/23682.40	eprover: CPU time limit exceeded, terminating
179150.91/23682.40	% SZS status Ended for HL410478+4.p
179153.17/23682.67	% SZS status Started for HL410478+5.p
179153.17/23682.67	% SZS status GaveUp for HL410478+5.p
179153.17/23682.67	eprover: CPU time limit exceeded, terminating
179153.17/23682.67	% SZS status Ended for HL410478+5.p
179158.72/23683.38	% SZS status Started for HL410479+4.p
179158.72/23683.38	% SZS status GaveUp for HL410479+4.p
179158.72/23683.38	eprover: CPU time limit exceeded, terminating
179158.72/23683.38	% SZS status Ended for HL410479+4.p
179159.86/23683.58	% SZS status Started for HL410479+5.p
179159.86/23683.58	% SZS status GaveUp for HL410479+5.p
179159.86/23683.58	eprover: CPU time limit exceeded, terminating
179159.86/23683.58	% SZS status Ended for HL410479+5.p
179163.41/23684.13	% SZS status Started for HL410480+5.p
179163.41/23684.13	% SZS status GaveUp for HL410480+5.p
179163.41/23684.13	eprover: CPU time limit exceeded, terminating
179163.41/23684.13	% SZS status Ended for HL410480+5.p
179164.28/23684.23	% SZS status Started for HL410480+4.p
179164.28/23684.23	% SZS status GaveUp for HL410480+4.p
179164.28/23684.23	eprover: CPU time limit exceeded, terminating
179164.28/23684.23	% SZS status Ended for HL410480+4.p
179169.25/23684.86	% SZS status Started for HL410481+4.p
179169.25/23684.86	% SZS status GaveUp for HL410481+4.p
179169.25/23684.86	eprover: CPU time limit exceeded, terminating
179169.25/23684.86	% SZS status Ended for HL410481+4.p
179173.73/23685.43	% SZS status Started for HL410481+5.p
179173.73/23685.43	% SZS status GaveUp for HL410481+5.p
179173.73/23685.43	eprover: CPU time limit exceeded, terminating
179173.73/23685.43	% SZS status Ended for HL410481+5.p
179175.67/23685.71	% SZS status Started for HL410482+4.p
179175.67/23685.71	% SZS status GaveUp for HL410482+4.p
179175.67/23685.71	eprover: CPU time limit exceeded, terminating
179175.67/23685.71	% SZS status Ended for HL410482+4.p
179180.95/23686.42	% SZS status Started for HL410469+5.p
179180.95/23686.42	% SZS status GaveUp for HL410469+5.p
179180.95/23686.42	eprover: CPU time limit exceeded, terminating
179180.95/23686.42	% SZS status Ended for HL410469+5.p
179182.75/23686.62	% SZS status Started for HL410483+4.p
179182.75/23686.62	% SZS status GaveUp for HL410483+4.p
179182.75/23686.62	eprover: CPU time limit exceeded, terminating
179182.75/23686.62	% SZS status Ended for HL410483+4.p
179187.48/23687.20	% SZS status Started for HL410483+5.p
179187.48/23687.20	% SZS status GaveUp for HL410483+5.p
179187.48/23687.20	eprover: CPU time limit exceeded, terminating
179187.48/23687.20	% SZS status Ended for HL410483+5.p
179188.38/23687.37	% SZS status Started for HL410484+4.p
179188.38/23687.37	% SZS status GaveUp for HL410484+4.p
179188.38/23687.37	eprover: CPU time limit exceeded, terminating
179188.38/23687.37	% SZS status Ended for HL410484+4.p
179197.08/23688.45	% SZS status Started for HL410484+5.p
179197.08/23688.45	% SZS status GaveUp for HL410484+5.p
179197.08/23688.45	eprover: CPU time limit exceeded, terminating
179197.08/23688.45	% SZS status Ended for HL410484+5.p
179197.55/23688.46	% SZS status Started for HL410485+4.p
179197.55/23688.46	% SZS status GaveUp for HL410485+4.p
179197.55/23688.46	eprover: CPU time limit exceeded, terminating
179197.55/23688.46	% SZS status Ended for HL410485+4.p
179199.08/23688.74	% SZS status Started for HL410485+5.p
179199.08/23688.74	% SZS status GaveUp for HL410485+5.p
179199.08/23688.74	eprover: CPU time limit exceeded, terminating
179199.08/23688.74	% SZS status Ended for HL410485+5.p
179205.66/23689.49	% SZS status Started for HL410486+4.p
179205.66/23689.49	% SZS status GaveUp for HL410486+4.p
179205.66/23689.49	eprover: CPU time limit exceeded, terminating
179205.66/23689.49	% SZS status Ended for HL410486+4.p
179206.92/23689.73	% SZS status Started for HL410486+5.p
179206.92/23689.73	% SZS status GaveUp for HL410486+5.p
179206.92/23689.73	eprover: CPU time limit exceeded, terminating
179206.92/23689.73	% SZS status Ended for HL410486+5.p
179211.62/23690.26	% SZS status Started for HL410487+4.p
179211.62/23690.26	% SZS status GaveUp for HL410487+4.p
179211.62/23690.26	eprover: CPU time limit exceeded, terminating
179211.62/23690.26	% SZS status Ended for HL410487+4.p
179212.75/23690.40	% SZS status Started for HL410487+5.p
179212.75/23690.40	% SZS status GaveUp for HL410487+5.p
179212.75/23690.40	eprover: CPU time limit exceeded, terminating
179212.75/23690.40	% SZS status Ended for HL410487+5.p
179220.83/23691.49	% SZS status Started for HL410489+5.p
179220.83/23691.49	% SZS status GaveUp for HL410489+5.p
179220.83/23691.49	eprover: CPU time limit exceeded, terminating
179220.83/23691.49	% SZS status Ended for HL410489+5.p
179222.08/23691.65	% SZS status Started for HL410489+4.p
179222.08/23691.65	% SZS status GaveUp for HL410489+4.p
179222.08/23691.65	eprover: CPU time limit exceeded, terminating
179222.08/23691.65	% SZS status Ended for HL410489+4.p
179223.36/23691.77	% SZS status Started for HL410490+4.p
179223.36/23691.77	% SZS status GaveUp for HL410490+4.p
179223.36/23691.77	eprover: CPU time limit exceeded, terminating
179223.36/23691.77	% SZS status Ended for HL410490+4.p
179230.56/23692.76	% SZS status Started for HL410493+4.p
179230.56/23692.76	% SZS status GaveUp for HL410493+4.p
179230.56/23692.76	eprover: CPU time limit exceeded, terminating
179230.56/23692.76	% SZS status Ended for HL410493+4.p
179230.92/23692.79	% SZS status Started for HL410490+5.p
179230.92/23692.79	% SZS status GaveUp for HL410490+5.p
179230.92/23692.79	eprover: CPU time limit exceeded, terminating
179230.92/23692.79	% SZS status Ended for HL410490+5.p
179234.97/23693.29	% SZS status Started for HL410493+5.p
179234.97/23693.29	% SZS status GaveUp for HL410493+5.p
179234.97/23693.29	eprover: CPU time limit exceeded, terminating
179234.97/23693.29	% SZS status Ended for HL410493+5.p
179237.05/23693.55	% SZS status Started for HL410494+4.p
179237.05/23693.55	% SZS status GaveUp for HL410494+4.p
179237.05/23693.55	eprover: CPU time limit exceeded, terminating
179237.05/23693.55	% SZS status Ended for HL410494+4.p
179244.88/23694.53	% SZS status Started for HL410494+5.p
179244.88/23694.53	% SZS status GaveUp for HL410494+5.p
179244.88/23694.53	eprover: CPU time limit exceeded, terminating
179244.88/23694.53	% SZS status Ended for HL410494+5.p
179245.84/23694.70	% SZS status Started for HL410496+4.p
179245.84/23694.70	% SZS status GaveUp for HL410496+4.p
179245.84/23694.70	eprover: CPU time limit exceeded, terminating
179245.84/23694.70	% SZS status Ended for HL410496+4.p
179248.72/23695.02	% SZS status Started for HL410496+5.p
179248.72/23695.02	% SZS status GaveUp for HL410496+5.p
179248.72/23695.02	eprover: CPU time limit exceeded, terminating
179248.72/23695.02	% SZS status Ended for HL410496+5.p
179252.19/23695.43	% SZS status Started for HL410482+5.p
179252.19/23695.43	% SZS status GaveUp for HL410482+5.p
179252.19/23695.43	eprover: CPU time limit exceeded, terminating
179252.19/23695.43	% SZS status Ended for HL410482+5.p
179254.78/23695.80	% SZS status Started for HL410498+4.p
179254.78/23695.80	% SZS status GaveUp for HL410498+4.p
179254.78/23695.80	eprover: CPU time limit exceeded, terminating
179254.78/23695.80	% SZS status Ended for HL410498+4.p
179254.78/23695.85	% SZS status Started for HL410498+5.p
179254.78/23695.85	% SZS status GaveUp for HL410498+5.p
179254.78/23695.85	eprover: CPU time limit exceeded, terminating
179254.78/23695.85	% SZS status Ended for HL410498+5.p
179258.86/23696.34	% SZS status Started for HL410499+4.p
179258.86/23696.34	% SZS status GaveUp for HL410499+4.p
179258.86/23696.34	eprover: CPU time limit exceeded, terminating
179258.86/23696.34	% SZS status Ended for HL410499+4.p
179261.78/23696.64	% SZS status Started for HL410499+5.p
179261.78/23696.64	% SZS status GaveUp for HL410499+5.p
179261.78/23696.64	eprover: CPU time limit exceeded, terminating
179261.78/23696.64	% SZS status Ended for HL410499+5.p
179268.92/23697.59	% SZS status Started for HL410501+4.p
179268.92/23697.59	% SZS status GaveUp for HL410501+4.p
179268.92/23697.59	eprover: CPU time limit exceeded, terminating
179268.92/23697.59	% SZS status Ended for HL410501+4.p
179270.22/23697.77	% SZS status Started for HL410501+5.p
179270.22/23697.77	% SZS status GaveUp for HL410501+5.p
179270.22/23697.77	eprover: CPU time limit exceeded, terminating
179270.22/23697.77	% SZS status Ended for HL410501+5.p
179272.14/23698.06	% SZS status Started for HL410503+4.p
179272.14/23698.06	% SZS status GaveUp for HL410503+4.p
179272.14/23698.06	eprover: CPU time limit exceeded, terminating
179272.14/23698.06	% SZS status Ended for HL410503+4.p
179275.50/23698.46	% SZS status Started for HL410503+5.p
179275.50/23698.46	% SZS status GaveUp for HL410503+5.p
179275.50/23698.46	eprover: CPU time limit exceeded, terminating
179275.50/23698.46	% SZS status Ended for HL410503+5.p
179278.73/23698.83	% SZS status Started for HL410504+4.p
179278.73/23698.83	% SZS status GaveUp for HL410504+4.p
179278.73/23698.83	eprover: CPU time limit exceeded, terminating
179278.73/23698.83	% SZS status Ended for HL410504+4.p
179280.41/23699.09	% SZS status Started for HL410504+5.p
179280.41/23699.09	% SZS status GaveUp for HL410504+5.p
179280.41/23699.09	eprover: CPU time limit exceeded, terminating
179280.41/23699.09	% SZS status Ended for HL410504+5.p
179282.69/23699.39	% SZS status Started for HL410505+4.p
179282.69/23699.39	% SZS status GaveUp for HL410505+4.p
179282.69/23699.39	eprover: CPU time limit exceeded, terminating
179282.69/23699.39	% SZS status Ended for HL410505+4.p
179287.25/23699.95	% SZS status Started for HL410505+5.p
179287.25/23699.95	% SZS status GaveUp for HL410505+5.p
179287.25/23699.95	eprover: CPU time limit exceeded, terminating
179287.25/23699.95	% SZS status Ended for HL410505+5.p
179293.14/23700.70	% SZS status Started for HL410506+4.p
179293.14/23700.70	% SZS status GaveUp for HL410506+4.p
179293.14/23700.70	eprover: CPU time limit exceeded, terminating
179293.14/23700.70	% SZS status Ended for HL410506+4.p
179294.05/23700.82	% SZS status Started for HL410506+5.p
179294.05/23700.82	% SZS status GaveUp for HL410506+5.p
179294.05/23700.82	eprover: CPU time limit exceeded, terminating
179294.05/23700.82	% SZS status Ended for HL410506+5.p
179297.28/23701.22	% SZS status Started for HL410507+4.p
179297.28/23701.22	% SZS status GaveUp for HL410507+4.p
179297.28/23701.22	eprover: CPU time limit exceeded, terminating
179297.28/23701.22	% SZS status Ended for HL410507+4.p
179299.91/23701.55	% SZS status Started for HL410507+5.p
179299.91/23701.55	% SZS status GaveUp for HL410507+5.p
179299.91/23701.55	eprover: CPU time limit exceeded, terminating
179299.91/23701.55	% SZS status Ended for HL410507+5.p
179302.00/23701.88	% SZS status Started for HL410508+4.p
179302.00/23701.88	% SZS status GaveUp for HL410508+4.p
179302.00/23701.88	eprover: CPU time limit exceeded, terminating
179302.00/23701.88	% SZS status Ended for HL410508+4.p
179307.17/23702.47	% SZS status Started for HL410508+5.p
179307.17/23702.47	% SZS status GaveUp for HL410508+5.p
179307.17/23702.47	eprover: CPU time limit exceeded, terminating
179307.17/23702.47	% SZS status Ended for HL410508+5.p
179307.17/23702.52	% SZS status Started for HL410509+4.p
179307.17/23702.52	% SZS status GaveUp for HL410509+4.p
179307.17/23702.52	eprover: CPU time limit exceeded, terminating
179307.17/23702.52	% SZS status Ended for HL410509+4.p
179311.00/23702.98	% SZS status Started for HL410509+5.p
179311.00/23702.98	% SZS status GaveUp for HL410509+5.p
179311.00/23702.98	eprover: CPU time limit exceeded, terminating
179311.00/23702.98	% SZS status Ended for HL410509+5.p
179317.38/23703.74	% SZS status Started for HL410510+4.p
179317.38/23703.74	% SZS status GaveUp for HL410510+4.p
179317.38/23703.74	eprover: CPU time limit exceeded, terminating
179317.38/23703.74	% SZS status Ended for HL410510+4.p
179317.91/23703.86	% SZS status Started for HL410510+5.p
179317.91/23703.86	% SZS status GaveUp for HL410510+5.p
179317.91/23703.86	eprover: CPU time limit exceeded, terminating
179317.91/23703.86	% SZS status Ended for HL410510+5.p
179320.86/23704.25	% SZS status Started for HL410511+4.p
179320.86/23704.25	% SZS status GaveUp for HL410511+4.p
179320.86/23704.25	eprover: CPU time limit exceeded, terminating
179320.86/23704.25	% SZS status Ended for HL410511+4.p
179324.09/23704.59	% SZS status Started for HL410511+5.p
179324.09/23704.59	% SZS status GaveUp for HL410511+5.p
179324.09/23704.59	eprover: CPU time limit exceeded, terminating
179324.09/23704.59	% SZS status Ended for HL410511+5.p
179326.20/23704.92	% SZS status Started for HL410512+4.p
179326.20/23704.92	% SZS status GaveUp for HL410512+4.p
179326.20/23704.92	eprover: CPU time limit exceeded, terminating
179326.20/23704.92	% SZS status Ended for HL410512+4.p
179333.94/23705.55	% SZS status Started for HL410515+4.p
179333.94/23705.55	% SZS status GaveUp for HL410515+4.p
179333.94/23705.55	eprover: CPU time limit exceeded, terminating
179333.94/23705.55	% SZS status Ended for HL410515+4.p
179334.31/23705.59	% SZS status Started for HL410512+5.p
179334.31/23705.59	% SZS status GaveUp for HL410512+5.p
179334.31/23705.59	eprover: CPU time limit exceeded, terminating
179334.31/23705.59	% SZS status Ended for HL410512+5.p
179336.86/23706.01	% SZS status Started for HL410515+5.p
179336.86/23706.01	% SZS status GaveUp for HL410515+5.p
179336.86/23706.01	eprover: CPU time limit exceeded, terminating
179336.86/23706.01	% SZS status Ended for HL410515+5.p
179343.64/23706.77	% SZS status Started for HL410516+4.p
179343.64/23706.77	% SZS status GaveUp for HL410516+4.p
179343.64/23706.77	eprover: CPU time limit exceeded, terminating
179343.64/23706.77	% SZS status Ended for HL410516+4.p
179345.61/23707.01	% SZS status Started for HL410516+5.p
179345.61/23707.01	% SZS status GaveUp for HL410516+5.p
179345.61/23707.01	eprover: CPU time limit exceeded, terminating
179345.61/23707.01	% SZS status Ended for HL410516+5.p
179347.97/23707.28	% SZS status Started for HL410517+4.p
179347.97/23707.28	% SZS status GaveUp for HL410517+4.p
179347.97/23707.28	eprover: CPU time limit exceeded, terminating
179347.97/23707.28	% SZS status Ended for HL410517+4.p
179350.36/23707.63	% SZS status Started for HL410517+5.p
179350.36/23707.63	% SZS status GaveUp for HL410517+5.p
179350.36/23707.63	eprover: CPU time limit exceeded, terminating
179350.36/23707.63	% SZS status Ended for HL410517+5.p
179352.94/23707.96	% SZS status Started for HL410518+4.p
179352.94/23707.96	% SZS status GaveUp for HL410518+4.p
179352.94/23707.96	eprover: CPU time limit exceeded, terminating
179352.94/23707.96	% SZS status Ended for HL410518+4.p
179358.28/23708.58	% SZS status Started for HL410518+5.p
179358.28/23708.58	% SZS status GaveUp for HL410518+5.p
179358.28/23708.58	eprover: CPU time limit exceeded, terminating
179358.28/23708.58	% SZS status Ended for HL410518+5.p
179358.28/23708.62	% SZS status Started for HL410519+4.p
179358.28/23708.62	% SZS status GaveUp for HL410519+4.p
179358.28/23708.62	eprover: CPU time limit exceeded, terminating
179358.28/23708.62	% SZS status Ended for HL410519+4.p
179362.72/23709.14	% SZS status Started for HL410519+5.p
179362.72/23709.14	% SZS status GaveUp for HL410519+5.p
179362.72/23709.14	eprover: CPU time limit exceeded, terminating
179362.72/23709.14	% SZS status Ended for HL410519+5.p
179367.66/23709.80	% SZS status Started for HL410521+4.p
179367.66/23709.80	% SZS status GaveUp for HL410521+4.p
179367.66/23709.80	eprover: CPU time limit exceeded, terminating
179367.66/23709.80	% SZS status Ended for HL410521+4.p
179369.47/23710.04	% SZS status Started for HL410521+5.p
179369.47/23710.04	% SZS status GaveUp for HL410521+5.p
179369.47/23710.04	eprover: CPU time limit exceeded, terminating
179369.47/23710.04	% SZS status Ended for HL410521+5.p
179371.45/23710.31	% SZS status Started for HL410522+4.p
179371.45/23710.31	% SZS status GaveUp for HL410522+4.p
179371.45/23710.31	eprover: CPU time limit exceeded, terminating
179371.45/23710.31	% SZS status Ended for HL410522+4.p
179374.38/23710.66	% SZS status Started for HL410522+5.p
179374.38/23710.66	% SZS status GaveUp for HL410522+5.p
179374.38/23710.66	eprover: CPU time limit exceeded, terminating
179374.38/23710.66	% SZS status Ended for HL410522+5.p
179377.45/23711.03	% SZS status Started for HL410523+4.p
179377.45/23711.03	% SZS status GaveUp for HL410523+4.p
179377.45/23711.03	eprover: CPU time limit exceeded, terminating
179377.45/23711.03	% SZS status Ended for HL410523+4.p
179382.02/23711.63	% SZS status Started for HL410523+5.p
179382.02/23711.63	% SZS status GaveUp for HL410523+5.p
179382.02/23711.63	eprover: CPU time limit exceeded, terminating
179382.02/23711.63	% SZS status Ended for HL410523+5.p
179382.62/23711.71	% SZS status Started for HL410524+4.p
179382.62/23711.71	% SZS status GaveUp for HL410524+4.p
179382.62/23711.71	eprover: CPU time limit exceeded, terminating
179382.62/23711.71	% SZS status Ended for HL410524+4.p
179386.09/23712.19	% SZS status Started for HL410524+5.p
179386.09/23712.19	% SZS status GaveUp for HL410524+5.p
179386.09/23712.19	eprover: CPU time limit exceeded, terminating
179386.09/23712.19	% SZS status Ended for HL410524+5.p
179391.62/23712.83	% SZS status Started for HL410525+4.p
179391.62/23712.83	% SZS status GaveUp for HL410525+4.p
179391.62/23712.83	eprover: CPU time limit exceeded, terminating
179391.62/23712.83	% SZS status Ended for HL410525+4.p
179393.48/23713.07	% SZS status Started for HL410525+5.p
179393.48/23713.07	% SZS status GaveUp for HL410525+5.p
179393.48/23713.07	eprover: CPU time limit exceeded, terminating
179393.48/23713.07	% SZS status Ended for HL410525+5.p
179395.20/23713.34	% SZS status Started for HL410526+4.p
179395.20/23713.34	% SZS status GaveUp for HL410526+4.p
179395.20/23713.34	eprover: CPU time limit exceeded, terminating
179395.20/23713.34	% SZS status Ended for HL410526+4.p
179399.89/23713.90	% SZS status Started for HL410526+5.p
179399.89/23713.90	% SZS status GaveUp for HL410526+5.p
179399.89/23713.90	eprover: CPU time limit exceeded, terminating
179399.89/23713.90	% SZS status Ended for HL410526+5.p
179402.86/23714.28	% SZS status Started for HL410527+4.p
179402.86/23714.28	% SZS status GaveUp for HL410527+4.p
179402.86/23714.28	eprover: CPU time limit exceeded, terminating
179402.86/23714.28	% SZS status Ended for HL410527+4.p
179405.95/23714.70	% SZS status Started for HL410527+5.p
179405.95/23714.70	% SZS status GaveUp for HL410527+5.p
179405.95/23714.70	eprover: CPU time limit exceeded, terminating
179405.95/23714.70	% SZS status Ended for HL410527+5.p
179406.56/23714.75	% SZS status Started for HL410528+4.p
179406.56/23714.75	% SZS status GaveUp for HL410528+4.p
179406.56/23714.75	eprover: CPU time limit exceeded, terminating
179406.56/23714.75	% SZS status Ended for HL410528+4.p
179410.81/23715.29	% SZS status Started for HL410528+5.p
179410.81/23715.29	% SZS status GaveUp for HL410528+5.p
179410.81/23715.29	eprover: CPU time limit exceeded, terminating
179410.81/23715.29	% SZS status Ended for HL410528+5.p
179417.05/23716.10	% SZS status Started for HL410529+4.p
179417.05/23716.10	% SZS status GaveUp for HL410529+4.p
179417.05/23716.10	eprover: CPU time limit exceeded, terminating
179417.05/23716.10	% SZS status Ended for HL410529+4.p
179417.05/23716.11	% SZS status Started for HL410529+5.p
179417.05/23716.11	% SZS status GaveUp for HL410529+5.p
179417.05/23716.11	eprover: CPU time limit exceeded, terminating
179417.05/23716.11	% SZS status Ended for HL410529+5.p
179419.47/23716.42	% SZS status Started for HL410531+4.p
179419.47/23716.42	% SZS status GaveUp for HL410531+4.p
179419.47/23716.42	eprover: CPU time limit exceeded, terminating
179419.47/23716.42	% SZS status Ended for HL410531+4.p
179423.95/23716.97	% SZS status Started for HL410531+5.p
179423.95/23716.97	% SZS status GaveUp for HL410531+5.p
179423.95/23716.97	eprover: CPU time limit exceeded, terminating
179423.95/23716.97	% SZS status Ended for HL410531+5.p
179427.41/23717.45	% SZS status Started for HL410532+4.p
179427.41/23717.45	% SZS status GaveUp for HL410532+4.p
179427.41/23717.45	eprover: CPU time limit exceeded, terminating
179427.41/23717.45	% SZS status Ended for HL410532+4.p
179430.06/23717.73	% SZS status Started for HL410532+5.p
179430.06/23717.73	% SZS status GaveUp for HL410532+5.p
179430.06/23717.73	eprover: CPU time limit exceeded, terminating
179430.06/23717.73	% SZS status Ended for HL410532+5.p
179430.06/23717.78	% SZS status Started for HL410533+4.p
179430.06/23717.78	% SZS status GaveUp for HL410533+4.p
179430.06/23717.78	eprover: CPU time limit exceeded, terminating
179430.06/23717.78	% SZS status Ended for HL410533+4.p
179435.45/23718.43	% SZS status Started for HL410533+5.p
179435.45/23718.43	% SZS status GaveUp for HL410533+5.p
179435.45/23718.43	eprover: CPU time limit exceeded, terminating
179435.45/23718.43	% SZS status Ended for HL410533+5.p
179440.80/23719.14	% SZS status Started for HL410534+4.p
179440.80/23719.14	% SZS status GaveUp for HL410534+4.p
179440.80/23719.14	eprover: CPU time limit exceeded, terminating
179440.80/23719.14	% SZS status Ended for HL410534+4.p
179441.70/23719.21	% SZS status Started for HL410534+5.p
179441.70/23719.21	% SZS status GaveUp for HL410534+5.p
179441.70/23719.21	eprover: CPU time limit exceeded, terminating
179441.70/23719.21	% SZS status Ended for HL410534+5.p
179443.70/23719.52	% SZS status Started for HL410535+4.p
179443.70/23719.52	% SZS status GaveUp for HL410535+4.p
179443.70/23719.52	eprover: CPU time limit exceeded, terminating
179443.70/23719.52	% SZS status Ended for HL410535+4.p
179447.56/23720.01	% SZS status Started for HL410535+5.p
179447.56/23720.01	% SZS status GaveUp for HL410535+5.p
179447.56/23720.01	eprover: CPU time limit exceeded, terminating
179447.56/23720.01	% SZS status Ended for HL410535+5.p
179451.83/23720.48	% SZS status Started for HL410536+4.p
179451.83/23720.48	% SZS status GaveUp for HL410536+4.p
179451.83/23720.48	eprover: CPU time limit exceeded, terminating
179451.83/23720.48	% SZS status Ended for HL410536+4.p
179453.59/23720.76	% SZS status Started for HL410536+5.p
179453.59/23720.76	% SZS status GaveUp for HL410536+5.p
179453.59/23720.76	eprover: CPU time limit exceeded, terminating
179453.59/23720.76	% SZS status Ended for HL410536+5.p
179453.95/23720.81	% SZS status Started for HL410537+4.p
179453.95/23720.81	% SZS status GaveUp for HL410537+4.p
179453.95/23720.81	eprover: CPU time limit exceeded, terminating
179453.95/23720.81	% SZS status Ended for HL410537+4.p
179459.59/23721.49	% SZS status Started for HL410537+5.p
179459.59/23721.49	% SZS status GaveUp for HL410537+5.p
179459.59/23721.49	eprover: CPU time limit exceeded, terminating
179459.59/23721.49	% SZS status Ended for HL410537+5.p
179466.02/23722.26	% SZS status Started for HL410538+5.p
179466.02/23722.26	% SZS status GaveUp for HL410538+5.p
179466.02/23722.26	eprover: CPU time limit exceeded, terminating
179466.02/23722.26	% SZS status Ended for HL410538+5.p
179466.19/23722.31	% SZS status Started for HL410538+4.p
179466.19/23722.31	% SZS status GaveUp for HL410538+4.p
179466.19/23722.31	eprover: CPU time limit exceeded, terminating
179466.19/23722.31	% SZS status Ended for HL410538+4.p
179467.48/23722.55	% SZS status Started for HL410540+4.p
179467.48/23722.55	% SZS status GaveUp for HL410540+4.p
179467.48/23722.55	eprover: CPU time limit exceeded, terminating
179467.48/23722.55	% SZS status Ended for HL410540+4.p
179472.09/23723.04	% SZS status Started for HL410540+5.p
179472.09/23723.04	% SZS status GaveUp for HL410540+5.p
179472.09/23723.04	eprover: CPU time limit exceeded, terminating
179472.09/23723.04	% SZS status Ended for HL410540+5.p
179475.86/23723.52	% SZS status Started for HL410542+4.p
179475.86/23723.52	% SZS status GaveUp for HL410542+4.p
179475.86/23723.52	eprover: CPU time limit exceeded, terminating
179475.86/23723.52	% SZS status Ended for HL410542+4.p
179478.50/23723.89	% SZS status Started for HL410543+4.p
179478.50/23723.89	% SZS status GaveUp for HL410543+4.p
179478.50/23723.89	eprover: CPU time limit exceeded, terminating
179478.50/23723.89	% SZS status Ended for HL410543+4.p
179479.06/23723.95	% SZS status Started for HL410542+5.p
179479.06/23723.95	% SZS status GaveUp for HL410542+5.p
179479.06/23723.95	eprover: CPU time limit exceeded, terminating
179479.06/23723.95	% SZS status Ended for HL410542+5.p
179484.00/23724.62	% SZS status Started for HL410543+5.p
179484.00/23724.62	% SZS status GaveUp for HL410543+5.p
179484.00/23724.62	eprover: CPU time limit exceeded, terminating
179484.00/23724.62	% SZS status Ended for HL410543+5.p
179489.66/23725.34	% SZS status Started for HL410544+5.p
179489.66/23725.34	% SZS status GaveUp for HL410544+5.p
179489.66/23725.34	eprover: CPU time limit exceeded, terminating
179489.66/23725.34	% SZS status Ended for HL410544+5.p
179489.66/23725.39	% SZS status Started for HL410544+4.p
179489.66/23725.39	% SZS status GaveUp for HL410544+4.p
179489.66/23725.39	eprover: CPU time limit exceeded, terminating
179489.66/23725.39	% SZS status Ended for HL410544+4.p
179494.23/23725.58	% SZS status Started for HL410545+4.p
179494.23/23725.58	% SZS status GaveUp for HL410545+4.p
179494.23/23725.58	eprover: CPU time limit exceeded, terminating
179494.23/23725.58	% SZS status Ended for HL410545+4.p
179498.47/23726.09	% SZS status Started for HL410545+5.p
179498.47/23726.09	% SZS status GaveUp for HL410545+5.p
179498.47/23726.09	eprover: CPU time limit exceeded, terminating
179498.47/23726.09	% SZS status Ended for HL410545+5.p
179503.69/23726.78	% SZS status Started for HL410546+4.p
179503.69/23726.78	% SZS status GaveUp for HL410546+4.p
179503.69/23726.78	eprover: CPU time limit exceeded, terminating
179503.69/23726.78	% SZS status Ended for HL410546+4.p
179505.67/23727.00	% SZS status Started for HL410547+4.p
179505.67/23727.00	% SZS status GaveUp for HL410547+4.p
179505.67/23727.00	eprover: CPU time limit exceeded, terminating
179505.67/23727.00	% SZS status Ended for HL410547+4.p
179505.67/23727.03	% SZS status Started for HL410546+5.p
179505.67/23727.03	% SZS status GaveUp for HL410546+5.p
179505.67/23727.03	eprover: CPU time limit exceeded, terminating
179505.67/23727.03	% SZS status Ended for HL410546+5.p
179510.38/23727.67	% SZS status Started for HL410547+5.p
179510.38/23727.67	% SZS status GaveUp for HL410547+5.p
179510.38/23727.67	eprover: CPU time limit exceeded, terminating
179510.38/23727.67	% SZS status Ended for HL410547+5.p
179515.72/23728.37	% SZS status Started for HL410548+4.p
179515.72/23728.37	% SZS status GaveUp for HL410548+4.p
179515.72/23728.37	eprover: CPU time limit exceeded, terminating
179515.72/23728.37	% SZS status Ended for HL410548+4.p
179516.22/23728.42	% SZS status Started for HL410548+5.p
179516.22/23728.42	% SZS status GaveUp for HL410548+5.p
179516.22/23728.42	eprover: CPU time limit exceeded, terminating
179516.22/23728.42	% SZS status Ended for HL410548+5.p
179517.23/23728.62	% SZS status Started for HL410551+4.p
179517.23/23728.62	% SZS status GaveUp for HL410551+4.p
179517.23/23728.62	eprover: CPU time limit exceeded, terminating
179517.23/23728.62	% SZS status Ended for HL410551+4.p
179523.38/23729.29	% SZS status Started for HL410551+5.p
179523.38/23729.29	% SZS status GaveUp for HL410551+5.p
179523.38/23729.29	eprover: CPU time limit exceeded, terminating
179523.38/23729.29	% SZS status Ended for HL410551+5.p
179528.92/23730.04	% SZS status Started for HL410554+4.p
179528.92/23730.04	% SZS status GaveUp for HL410554+4.p
179528.92/23730.04	eprover: CPU time limit exceeded, terminating
179528.92/23730.04	% SZS status Ended for HL410554+4.p
179529.67/23730.11	% SZS status Started for HL410554+5.p
179529.67/23730.11	% SZS status GaveUp for HL410554+5.p
179529.67/23730.11	eprover: CPU time limit exceeded, terminating
179529.67/23730.11	% SZS status Ended for HL410554+5.p
179530.09/23730.15	% SZS status Started for HL410555+4.p
179530.09/23730.15	% SZS status GaveUp for HL410555+4.p
179530.09/23730.15	eprover: CPU time limit exceeded, terminating
179530.09/23730.15	% SZS status Ended for HL410555+4.p
179535.75/23730.88	% SZS status Started for HL410555+5.p
179535.75/23730.88	% SZS status GaveUp for HL410555+5.p
179535.75/23730.88	eprover: CPU time limit exceeded, terminating
179535.75/23730.88	% SZS status Ended for HL410555+5.p
179539.92/23731.40	% SZS status Started for HL410556+4.p
179539.92/23731.40	% SZS status GaveUp for HL410556+4.p
179539.92/23731.40	eprover: CPU time limit exceeded, terminating
179539.92/23731.40	% SZS status Ended for HL410556+4.p
179540.42/23731.46	% SZS status Started for HL410556+5.p
179540.42/23731.46	% SZS status GaveUp for HL410556+5.p
179540.42/23731.46	eprover: CPU time limit exceeded, terminating
179540.42/23731.46	% SZS status Ended for HL410556+5.p
179540.97/23731.65	% SZS status Started for HL410557+4.p
179540.97/23731.65	% SZS status GaveUp for HL410557+4.p
179540.97/23731.65	eprover: CPU time limit exceeded, terminating
179540.97/23731.65	% SZS status Ended for HL410557+4.p
179548.59/23732.32	% SZS status Started for HL410557+5.p
179548.59/23732.32	% SZS status GaveUp for HL410557+5.p
179548.59/23732.32	eprover: CPU time limit exceeded, terminating
179548.59/23732.32	% SZS status Ended for HL410557+5.p
179555.06/23733.08	% SZS status Started for HL410558+4.p
179555.06/23733.08	% SZS status GaveUp for HL410558+4.p
179555.06/23733.08	eprover: CPU time limit exceeded, terminating
179555.06/23733.08	% SZS status Ended for HL410558+4.p
179555.06/23733.14	% SZS status Started for HL410558+5.p
179555.06/23733.14	% SZS status GaveUp for HL410558+5.p
179555.06/23733.14	eprover: CPU time limit exceeded, terminating
179555.06/23733.14	% SZS status Ended for HL410558+5.p
179556.19/23733.31	% SZS status Started for HL410561+4.p
179556.19/23733.31	% SZS status GaveUp for HL410561+4.p
179556.19/23733.31	eprover: CPU time limit exceeded, terminating
179556.19/23733.31	% SZS status Ended for HL410561+4.p
179563.03/23734.14	% SZS status Started for HL410561+5.p
179563.03/23734.14	% SZS status GaveUp for HL410561+5.p
179563.03/23734.14	eprover: CPU time limit exceeded, terminating
179563.03/23734.14	% SZS status Ended for HL410561+5.p
179565.22/23734.42	% SZS status Started for HL410562+4.p
179565.22/23734.42	% SZS status GaveUp for HL410562+4.p
179565.22/23734.42	eprover: CPU time limit exceeded, terminating
179565.22/23734.42	% SZS status Ended for HL410562+4.p
179565.81/23734.51	% SZS status Started for HL410562+5.p
179565.81/23734.51	% SZS status GaveUp for HL410562+5.p
179565.81/23734.51	eprover: CPU time limit exceeded, terminating
179565.81/23734.51	% SZS status Ended for HL410562+5.p
179571.23/23734.88	% SZS status Started for HL410563+4.p
179571.23/23734.88	% SZS status GaveUp for HL410563+4.p
179571.23/23734.88	eprover: CPU time limit exceeded, terminating
179571.23/23734.88	% SZS status Ended for HL410563+4.p
179575.39/23735.36	% SZS status Started for HL410563+5.p
179575.39/23735.36	% SZS status GaveUp for HL410563+5.p
179575.39/23735.36	eprover: CPU time limit exceeded, terminating
179575.39/23735.36	% SZS status Ended for HL410563+5.p
179581.17/23736.11	% SZS status Started for HL410565+4.p
179581.17/23736.11	% SZS status GaveUp for HL410565+4.p
179581.17/23736.11	eprover: CPU time limit exceeded, terminating
179581.17/23736.11	% SZS status Ended for HL410565+4.p
179581.75/23736.18	% SZS status Started for HL410565+5.p
179581.75/23736.18	% SZS status GaveUp for HL410565+5.p
179581.75/23736.18	eprover: CPU time limit exceeded, terminating
179581.75/23736.18	% SZS status Ended for HL410565+5.p
179585.92/23736.39	% SZS status Started for HL410567+4.p
179585.92/23736.39	% SZS status GaveUp for HL410567+4.p
179585.92/23736.39	eprover: CPU time limit exceeded, terminating
179585.92/23736.39	% SZS status Ended for HL410567+4.p
179592.61/23737.18	% SZS status Started for HL410567+5.p
179592.61/23737.18	% SZS status GaveUp for HL410567+5.p
179592.61/23737.18	eprover: CPU time limit exceeded, terminating
179592.61/23737.18	% SZS status Ended for HL410567+5.p
179595.03/23737.51	% SZS status Started for HL410568+4.p
179595.03/23737.51	% SZS status GaveUp for HL410568+4.p
179595.03/23737.51	eprover: CPU time limit exceeded, terminating
179595.03/23737.51	% SZS status Ended for HL410568+4.p
179595.03/23737.54	% SZS status Started for HL410568+5.p
179595.03/23737.54	% SZS status GaveUp for HL410568+5.p
179595.03/23737.54	eprover: CPU time limit exceeded, terminating
179595.03/23737.54	% SZS status Ended for HL410568+5.p
179597.50/23737.91	% SZS status Started for HL410569+4.p
179597.50/23737.91	% SZS status GaveUp for HL410569+4.p
179597.50/23737.91	eprover: CPU time limit exceeded, terminating
179597.50/23737.91	% SZS status Ended for HL410569+4.p
179603.66/23738.41	% SZS status Started for HL410569+5.p
179603.66/23738.41	% SZS status GaveUp for HL410569+5.p
179603.66/23738.41	eprover: CPU time limit exceeded, terminating
179603.66/23738.41	% SZS status Ended for HL410569+5.p
179609.48/23739.14	% SZS status Started for HL410570+4.p
179609.48/23739.14	% SZS status GaveUp for HL410570+4.p
179609.48/23739.14	eprover: CPU time limit exceeded, terminating
179609.48/23739.14	% SZS status Ended for HL410570+4.p
179609.73/23739.21	% SZS status Started for HL410570+5.p
179609.73/23739.21	% SZS status GaveUp for HL410570+5.p
179609.73/23739.21	eprover: CPU time limit exceeded, terminating
179609.73/23739.21	% SZS status Ended for HL410570+5.p
179611.27/23739.50	% SZS status Started for HL410571+4.p
179611.27/23739.50	% SZS status GaveUp for HL410571+4.p
179611.27/23739.50	eprover: CPU time limit exceeded, terminating
179611.27/23739.50	% SZS status Ended for HL410571+4.p
179619.84/23740.55	% SZS status Started for HL410572+4.p
179619.84/23740.55	% SZS status GaveUp for HL410572+4.p
179619.84/23740.55	eprover: CPU time limit exceeded, terminating
179619.84/23740.55	% SZS status Ended for HL410572+4.p
179620.92/23740.64	% SZS status Started for HL410572+5.p
179620.92/23740.64	% SZS status GaveUp for HL410572+5.p
179620.92/23740.64	eprover: CPU time limit exceeded, terminating
179620.92/23740.64	% SZS status Ended for HL410572+5.p
179621.61/23740.79	% SZS status Started for HL410571+5.p
179621.61/23740.79	% SZS status GaveUp for HL410571+5.p
179621.61/23740.79	eprover: CPU time limit exceeded, terminating
179621.61/23740.79	% SZS status Ended for HL410571+5.p
179622.52/23740.94	% SZS status Started for HL410573+4.p
179622.52/23740.94	% SZS status GaveUp for HL410573+4.p
179622.52/23740.94	eprover: CPU time limit exceeded, terminating
179622.52/23740.94	% SZS status Ended for HL410573+4.p
179631.48/23742.01	% SZS status Started for HL410573+5.p
179631.48/23742.01	% SZS status GaveUp for HL410573+5.p
179631.48/23742.01	eprover: CPU time limit exceeded, terminating
179631.48/23742.01	% SZS status Ended for HL410573+5.p
179633.27/23742.24	% SZS status Started for HL410575+4.p
179633.27/23742.24	% SZS status GaveUp for HL410575+4.p
179633.27/23742.24	eprover: CPU time limit exceeded, terminating
179633.27/23742.24	% SZS status Ended for HL410575+4.p
179633.27/23742.24	% SZS status Started for HL410575+5.p
179633.27/23742.24	% SZS status GaveUp for HL410575+5.p
179633.27/23742.24	eprover: CPU time limit exceeded, terminating
179633.27/23742.24	% SZS status Ended for HL410575+5.p
179636.72/23742.62	% SZS status Started for HL410578+4.p
179636.72/23742.62	% SZS status GaveUp for HL410578+4.p
179636.72/23742.62	eprover: CPU time limit exceeded, terminating
179636.72/23742.62	% SZS status Ended for HL410578+4.p
179644.34/23743.60	% SZS status Started for HL410578+5.p
179644.34/23743.60	% SZS status GaveUp for HL410578+5.p
179644.34/23743.60	eprover: CPU time limit exceeded, terminating
179644.34/23743.60	% SZS status Ended for HL410578+5.p
179645.31/23743.77	% SZS status Started for HL410579+4.p
179645.31/23743.77	% SZS status GaveUp for HL410579+4.p
179645.31/23743.77	eprover: CPU time limit exceeded, terminating
179645.31/23743.77	% SZS status Ended for HL410579+4.p
179645.80/23743.86	% SZS status Started for HL410579+5.p
179645.80/23743.86	% SZS status GaveUp for HL410579+5.p
179645.80/23743.86	eprover: CPU time limit exceeded, terminating
179645.80/23743.86	% SZS status Ended for HL410579+5.p
179646.78/23744.00	% SZS status Started for HL410580+4.p
179646.78/23744.00	% SZS status GaveUp for HL410580+4.p
179646.78/23744.00	eprover: CPU time limit exceeded, terminating
179646.78/23744.00	% SZS status Ended for HL410580+4.p
179655.20/23745.04	% SZS status Started for HL410580+5.p
179655.20/23745.04	% SZS status GaveUp for HL410580+5.p
179655.20/23745.04	eprover: CPU time limit exceeded, terminating
179655.20/23745.04	% SZS status Ended for HL410580+5.p
179657.02/23745.28	% SZS status Started for HL410581+5.p
179657.02/23745.28	% SZS status GaveUp for HL410581+5.p
179657.02/23745.28	eprover: CPU time limit exceeded, terminating
179657.02/23745.28	% SZS status Ended for HL410581+5.p
179658.03/23745.42	% SZS status Started for HL410581+4.p
179658.03/23745.42	% SZS status GaveUp for HL410581+4.p
179658.03/23745.42	eprover: CPU time limit exceeded, terminating
179658.03/23745.42	% SZS status Ended for HL410581+4.p
179660.50/23745.66	% SZS status Started for HL410583+4.p
179660.50/23745.66	% SZS status GaveUp for HL410583+4.p
179660.50/23745.66	eprover: CPU time limit exceeded, terminating
179660.50/23745.66	% SZS status Ended for HL410583+4.p
179669.05/23746.83	% SZS status Started for HL410583+5.p
179669.05/23746.83	% SZS status GaveUp for HL410583+5.p
179669.05/23746.83	eprover: CPU time limit exceeded, terminating
179669.05/23746.83	% SZS status Ended for HL410583+5.p
179669.47/23746.89	% SZS status Started for HL410584+4.p
179669.47/23746.89	% SZS status GaveUp for HL410584+4.p
179669.47/23746.89	eprover: CPU time limit exceeded, terminating
179669.47/23746.89	% SZS status Ended for HL410584+4.p
179669.47/23746.93	% SZS status Started for HL410584+5.p
179669.47/23746.93	% SZS status GaveUp for HL410584+5.p
179669.47/23746.93	eprover: CPU time limit exceeded, terminating
179669.47/23746.93	% SZS status Ended for HL410584+5.p
179671.39/23747.27	% SZS status Started for HL410585+4.p
179671.39/23747.27	% SZS status GaveUp for HL410585+4.p
179671.39/23747.27	eprover: CPU time limit exceeded, terminating
179671.39/23747.27	% SZS status Ended for HL410585+4.p
179678.06/23748.07	% SZS status Started for HL410585+5.p
179678.06/23748.07	% SZS status GaveUp for HL410585+5.p
179678.06/23748.07	eprover: CPU time limit exceeded, terminating
179678.06/23748.07	% SZS status Ended for HL410585+5.p
179681.70/23748.45	% SZS status Started for HL410588+5.p
179681.70/23748.45	% SZS status GaveUp for HL410588+5.p
179681.70/23748.45	eprover: CPU time limit exceeded, terminating
179681.70/23748.45	% SZS status Ended for HL410588+5.p
179682.73/23748.62	% SZS status Started for HL410588+4.p
179682.73/23748.62	% SZS status GaveUp for HL410588+4.p
179682.73/23748.62	eprover: CPU time limit exceeded, terminating
179682.73/23748.62	% SZS status Ended for HL410588+4.p
179684.62/23748.91	% SZS status Started for HL410589+4.p
179684.62/23748.91	% SZS status GaveUp for HL410589+4.p
179684.62/23748.91	eprover: CPU time limit exceeded, terminating
179684.62/23748.91	% SZS status Ended for HL410589+4.p
179693.19/23749.89	% SZS status Started for HL410589+5.p
179693.19/23749.89	% SZS status GaveUp for HL410589+5.p
179693.19/23749.89	eprover: CPU time limit exceeded, terminating
179693.19/23749.89	% SZS status Ended for HL410589+5.p
179693.73/23749.96	% SZS status Started for HL410590+5.p
179693.73/23749.96	% SZS status GaveUp for HL410590+5.p
179693.73/23749.96	eprover: CPU time limit exceeded, terminating
179693.73/23749.96	% SZS status Ended for HL410590+5.p
179694.56/23750.06	% SZS status Started for HL410590+4.p
179694.56/23750.06	% SZS status GaveUp for HL410590+4.p
179694.56/23750.06	eprover: CPU time limit exceeded, terminating
179694.56/23750.06	% SZS status Ended for HL410590+4.p
179695.97/23750.31	% SZS status Started for HL410591+4.p
179695.97/23750.31	% SZS status GaveUp for HL410591+4.p
179695.97/23750.31	eprover: CPU time limit exceeded, terminating
179695.97/23750.31	% SZS status Ended for HL410591+4.p
179702.59/23751.10	% SZS status Started for HL410591+5.p
179702.59/23751.10	% SZS status GaveUp for HL410591+5.p
179702.59/23751.10	eprover: CPU time limit exceeded, terminating
179702.59/23751.10	% SZS status Ended for HL410591+5.p
179705.34/23751.48	% SZS status Started for HL410592+4.p
179705.34/23751.48	% SZS status GaveUp for HL410592+4.p
179705.34/23751.48	eprover: CPU time limit exceeded, terminating
179705.34/23751.48	% SZS status Ended for HL410592+4.p
179706.70/23751.76	% SZS status Started for HL410592+5.p
179706.70/23751.76	% SZS status GaveUp for HL410592+5.p
179706.70/23751.76	eprover: CPU time limit exceeded, terminating
179706.70/23751.76	% SZS status Ended for HL410592+5.p
179709.86/23752.11	% SZS status Started for HL410593+4.p
179709.86/23752.11	% SZS status GaveUp for HL410593+4.p
179709.86/23752.11	eprover: CPU time limit exceeded, terminating
179709.86/23752.11	% SZS status Ended for HL410593+4.p
179716.00/23752.95	% SZS status Started for HL410593+5.p
179716.00/23752.95	% SZS status GaveUp for HL410593+5.p
179716.00/23752.95	eprover: CPU time limit exceeded, terminating
179716.00/23752.95	% SZS status Ended for HL410593+5.p
179719.23/23753.00	% SZS status Started for HL410594+4.p
179719.23/23753.00	% SZS status GaveUp for HL410594+4.p
179719.23/23753.00	eprover: CPU time limit exceeded, terminating
179719.23/23753.00	% SZS status Ended for HL410594+4.p
179721.12/23753.35	% SZS status Started for HL410594+5.p
179721.12/23753.35	% SZS status GaveUp for HL410594+5.p
179721.12/23753.35	eprover: CPU time limit exceeded, terminating
179721.12/23753.35	% SZS status Ended for HL410594+5.p
179721.53/23753.38	% SZS status Started for HL410596+4.p
179721.53/23753.38	% SZS status GaveUp for HL410596+4.p
179721.53/23753.38	eprover: CPU time limit exceeded, terminating
179721.53/23753.38	% SZS status Ended for HL410596+4.p
179729.81/23754.33	% SZS status Started for HL410596+5.p
179729.81/23754.33	% SZS status GaveUp for HL410596+5.p
179729.81/23754.33	eprover: CPU time limit exceeded, terminating
179729.81/23754.33	% SZS status Ended for HL410596+5.p
179730.92/23754.51	% SZS status Started for HL410601+4.p
179730.92/23754.51	% SZS status GaveUp for HL410601+4.p
179730.92/23754.51	eprover: CPU time limit exceeded, terminating
179730.92/23754.51	% SZS status Ended for HL410601+4.p
179734.56/23754.93	% SZS status Started for HL410601+5.p
179734.56/23754.93	% SZS status GaveUp for HL410601+5.p
179734.56/23754.93	eprover: CPU time limit exceeded, terminating
179734.56/23754.93	% SZS status Ended for HL410601+5.p
179737.84/23755.36	% SZS status Started for HL410602+4.p
179737.84/23755.36	% SZS status GaveUp for HL410602+4.p
179737.84/23755.36	eprover: CPU time limit exceeded, terminating
179737.84/23755.36	% SZS status Ended for HL410602+4.p
179742.86/23755.98	% SZS status Started for HL410602+5.p
179742.86/23755.98	% SZS status GaveUp for HL410602+5.p
179742.86/23755.98	eprover: CPU time limit exceeded, terminating
179742.86/23755.98	% SZS status Ended for HL410602+5.p
179742.86/23756.03	% SZS status Started for HL410603+4.p
179742.86/23756.03	% SZS status GaveUp for HL410603+4.p
179742.86/23756.03	eprover: CPU time limit exceeded, terminating
179742.86/23756.03	% SZS status Ended for HL410603+4.p
179746.14/23756.42	% SZS status Started for HL410604+4.p
179746.14/23756.42	% SZS status GaveUp for HL410604+4.p
179746.14/23756.42	eprover: CPU time limit exceeded, terminating
179746.14/23756.42	% SZS status Ended for HL410604+4.p
179746.14/23756.44	% SZS status Started for HL410603+5.p
179746.14/23756.44	% SZS status GaveUp for HL410603+5.p
179746.14/23756.44	eprover: CPU time limit exceeded, terminating
179746.14/23756.44	% SZS status Ended for HL410603+5.p
179753.77/23757.36	% SZS status Started for HL410604+5.p
179753.77/23757.36	% SZS status GaveUp for HL410604+5.p
179753.77/23757.36	eprover: CPU time limit exceeded, terminating
179753.77/23757.36	% SZS status Ended for HL410604+5.p
179755.02/23757.54	% SZS status Started for HL410605+4.p
179755.02/23757.54	% SZS status GaveUp for HL410605+4.p
179755.02/23757.54	eprover: CPU time limit exceeded, terminating
179755.02/23757.54	% SZS status Ended for HL410605+4.p
179759.25/23758.08	% SZS status Started for HL410605+5.p
179759.25/23758.08	% SZS status GaveUp for HL410605+5.p
179759.25/23758.08	eprover: CPU time limit exceeded, terminating
179759.25/23758.08	% SZS status Ended for HL410605+5.p
179761.25/23758.38	% SZS status Started for HL410606+4.p
179761.25/23758.38	% SZS status GaveUp for HL410606+4.p
179761.25/23758.38	eprover: CPU time limit exceeded, terminating
179761.25/23758.38	% SZS status Ended for HL410606+4.p
179767.16/23759.06	% SZS status Started for HL410608+4.p
179767.16/23759.06	% SZS status GaveUp for HL410608+4.p
179767.16/23759.06	eprover: CPU time limit exceeded, terminating
179767.16/23759.06	% SZS status Ended for HL410608+4.p
179767.16/23759.08	% SZS status Started for HL410606+5.p
179767.16/23759.08	% SZS status GaveUp for HL410606+5.p
179767.16/23759.08	eprover: CPU time limit exceeded, terminating
179767.16/23759.08	% SZS status Ended for HL410606+5.p
179770.33/23759.46	% SZS status Started for HL410609+4.p
179770.33/23759.46	% SZS status GaveUp for HL410609+4.p
179770.33/23759.46	eprover: CPU time limit exceeded, terminating
179770.33/23759.46	% SZS status Ended for HL410609+4.p
179770.64/23759.47	% SZS status Started for HL410608+5.p
179770.64/23759.47	% SZS status GaveUp for HL410608+5.p
179770.64/23759.47	eprover: CPU time limit exceeded, terminating
179770.64/23759.47	% SZS status Ended for HL410608+5.p
179777.59/23760.39	% SZS status Started for HL410609+5.p
179777.59/23760.39	% SZS status GaveUp for HL410609+5.p
179777.59/23760.39	eprover: CPU time limit exceeded, terminating
179777.59/23760.39	% SZS status Ended for HL410609+5.p
179779.36/23760.63	% SZS status Started for HL410610+4.p
179779.36/23760.63	% SZS status GaveUp for HL410610+4.p
179779.36/23760.63	eprover: CPU time limit exceeded, terminating
179779.36/23760.63	% SZS status Ended for HL410610+4.p
179783.28/23761.11	% SZS status Started for HL410610+5.p
179783.28/23761.11	% SZS status GaveUp for HL410610+5.p
179783.28/23761.11	eprover: CPU time limit exceeded, terminating
179783.28/23761.11	% SZS status Ended for HL410610+5.p
179785.72/23761.42	% SZS status Started for HL410611+4.p
179785.72/23761.42	% SZS status GaveUp for HL410611+4.p
179785.72/23761.42	eprover: CPU time limit exceeded, terminating
179785.72/23761.42	% SZS status Ended for HL410611+4.p
179791.47/23762.09	% SZS status Started for HL410611+5.p
179791.47/23762.09	% SZS status GaveUp for HL410611+5.p
179791.47/23762.09	eprover: CPU time limit exceeded, terminating
179791.47/23762.09	% SZS status Ended for HL410611+5.p
179792.03/23762.17	% SZS status Started for HL410612+4.p
179792.03/23762.17	% SZS status GaveUp for HL410612+4.p
179792.03/23762.17	eprover: CPU time limit exceeded, terminating
179792.03/23762.17	% SZS status Ended for HL410612+4.p
179794.30/23762.50	% SZS status Started for HL410612+5.p
179794.30/23762.50	% SZS status GaveUp for HL410612+5.p
179794.30/23762.50	eprover: CPU time limit exceeded, terminating
179794.30/23762.50	% SZS status Ended for HL410612+5.p
179794.86/23762.56	% SZS status Started for HL410613+4.p
179794.86/23762.56	% SZS status GaveUp for HL410613+4.p
179794.86/23762.56	eprover: CPU time limit exceeded, terminating
179794.86/23762.56	% SZS status Ended for HL410613+4.p
179801.61/23763.42	% SZS status Started for HL410613+5.p
179801.61/23763.42	% SZS status GaveUp for HL410613+5.p
179801.61/23763.42	eprover: CPU time limit exceeded, terminating
179801.61/23763.42	% SZS status Ended for HL410613+5.p
179803.41/23763.66	% SZS status Started for HL410614+4.p
179803.41/23763.66	% SZS status GaveUp for HL410614+4.p
179803.41/23763.66	eprover: CPU time limit exceeded, terminating
179803.41/23763.66	% SZS status Ended for HL410614+4.p
179807.56/23764.14	% SZS status Started for HL410614+5.p
179807.56/23764.14	% SZS status GaveUp for HL410614+5.p
179807.56/23764.14	eprover: CPU time limit exceeded, terminating
179807.56/23764.14	% SZS status Ended for HL410614+5.p
179810.11/23764.45	% SZS status Started for HL410615+4.p
179810.11/23764.45	% SZS status GaveUp for HL410615+4.p
179810.11/23764.45	eprover: CPU time limit exceeded, terminating
179810.11/23764.45	% SZS status Ended for HL410615+4.p
179815.59/23765.20	% SZS status Started for HL410617+4.p
179815.59/23765.20	% SZS status GaveUp for HL410617+4.p
179815.59/23765.20	eprover: CPU time limit exceeded, terminating
179815.59/23765.20	% SZS status Ended for HL410617+4.p
179816.75/23765.34	% SZS status Started for HL410615+5.p
179816.75/23765.34	% SZS status GaveUp for HL410615+5.p
179816.75/23765.34	eprover: CPU time limit exceeded, terminating
179816.75/23765.34	% SZS status Ended for HL410615+5.p
179818.75/23765.58	% SZS status Started for HL410617+5.p
179818.75/23765.58	% SZS status GaveUp for HL410617+5.p
179818.75/23765.58	eprover: CPU time limit exceeded, terminating
179818.75/23765.58	% SZS status Ended for HL410617+5.p
179818.75/23765.61	% SZS status Started for HL410618+4.p
179818.75/23765.61	% SZS status GaveUp for HL410618+4.p
179818.75/23765.61	eprover: CPU time limit exceeded, terminating
179818.75/23765.61	% SZS status Ended for HL410618+4.p
179825.69/23766.45	% SZS status Started for HL410618+5.p
179825.69/23766.45	% SZS status GaveUp for HL410618+5.p
179825.69/23766.45	eprover: CPU time limit exceeded, terminating
179825.69/23766.45	% SZS status Ended for HL410618+5.p
179828.20/23766.79	% SZS status Started for HL410619+4.p
179828.20/23766.79	% SZS status GaveUp for HL410619+4.p
179828.20/23766.79	eprover: CPU time limit exceeded, terminating
179828.20/23766.79	% SZS status Ended for HL410619+4.p
179831.39/23767.17	% SZS status Started for HL410619+5.p
179831.39/23767.17	% SZS status GaveUp for HL410619+5.p
179831.39/23767.17	eprover: CPU time limit exceeded, terminating
179831.39/23767.17	% SZS status Ended for HL410619+5.p
179835.03/23767.71	% SZS status Started for HL410621+4.p
179835.03/23767.71	% SZS status GaveUp for HL410621+4.p
179835.03/23767.71	eprover: CPU time limit exceeded, terminating
179835.03/23767.71	% SZS status Ended for HL410621+4.p
179839.08/23768.23	% SZS status Started for HL410621+5.p
179839.08/23768.23	% SZS status GaveUp for HL410621+5.p
179839.08/23768.23	eprover: CPU time limit exceeded, terminating
179839.08/23768.23	% SZS status Ended for HL410621+5.p
179841.05/23768.37	% SZS status Started for HL410622+4.p
179841.05/23768.37	% SZS status GaveUp for HL410622+4.p
179841.05/23768.37	eprover: CPU time limit exceeded, terminating
179841.05/23768.37	% SZS status Ended for HL410622+4.p
179842.36/23768.63	% SZS status Started for HL410622+5.p
179842.36/23768.63	% SZS status GaveUp for HL410622+5.p
179842.36/23768.63	eprover: CPU time limit exceeded, terminating
179842.36/23768.63	% SZS status Ended for HL410622+5.p
179842.92/23768.65	% SZS status Started for HL410628+4.p
179842.92/23768.65	% SZS status GaveUp for HL410628+4.p
179842.92/23768.65	eprover: CPU time limit exceeded, terminating
179842.92/23768.65	% SZS status Ended for HL410628+4.p
179849.50/23769.49	% SZS status Started for HL410628+5.p
179849.50/23769.49	% SZS status GaveUp for HL410628+5.p
179849.50/23769.49	eprover: CPU time limit exceeded, terminating
179849.50/23769.49	% SZS status Ended for HL410628+5.p
179852.14/23769.82	% SZS status Started for HL410629+4.p
179852.14/23769.82	% SZS status GaveUp for HL410629+4.p
179852.14/23769.82	eprover: CPU time limit exceeded, terminating
179852.14/23769.82	% SZS status Ended for HL410629+4.p
179855.14/23770.21	% SZS status Started for HL410629+5.p
179855.14/23770.21	% SZS status GaveUp for HL410629+5.p
179855.14/23770.21	eprover: CPU time limit exceeded, terminating
179855.14/23770.21	% SZS status Ended for HL410629+5.p
179860.66/23770.84	% SZS status Started for HL410630+4.p
179860.66/23770.84	% SZS status GaveUp for HL410630+4.p
179860.66/23770.84	eprover: CPU time limit exceeded, terminating
179860.66/23770.84	% SZS status Ended for HL410630+4.p
179863.80/23771.27	% SZS status Started for HL410630+5.p
179863.80/23771.27	% SZS status GaveUp for HL410630+5.p
179863.80/23771.27	eprover: CPU time limit exceeded, terminating
179863.80/23771.27	% SZS status Ended for HL410630+5.p
179864.73/23771.41	% SZS status Started for HL410631+4.p
179864.73/23771.41	% SZS status GaveUp for HL410631+4.p
179864.73/23771.41	eprover: CPU time limit exceeded, terminating
179864.73/23771.41	% SZS status Ended for HL410631+4.p
179866.41/23771.68	% SZS status Started for HL410632+4.p
179866.41/23771.68	% SZS status GaveUp for HL410632+4.p
179866.41/23771.68	eprover: CPU time limit exceeded, terminating
179866.41/23771.68	% SZS status Ended for HL410632+4.p
179866.41/23771.69	% SZS status Started for HL410631+5.p
179866.41/23771.69	% SZS status GaveUp for HL410631+5.p
179866.41/23771.69	eprover: CPU time limit exceeded, terminating
179866.41/23771.69	% SZS status Ended for HL410631+5.p
179875.97/23772.52	% SZS status Started for HL410632+5.p
179875.97/23772.52	% SZS status GaveUp for HL410632+5.p
179875.97/23772.52	eprover: CPU time limit exceeded, terminating
179875.97/23772.52	% SZS status Ended for HL410632+5.p
179879.03/23772.92	% SZS status Started for HL410633+4.p
179879.03/23772.92	% SZS status GaveUp for HL410633+4.p
179879.03/23772.92	eprover: CPU time limit exceeded, terminating
179879.03/23772.92	% SZS status Ended for HL410633+4.p
179881.22/23773.24	% SZS status Started for HL410633+5.p
179881.22/23773.24	% SZS status GaveUp for HL410633+5.p
179881.22/23773.24	eprover: CPU time limit exceeded, terminating
179881.22/23773.24	% SZS status Ended for HL410633+5.p
179886.58/23773.89	% SZS status Started for HL410634+4.p
179886.58/23773.89	% SZS status GaveUp for HL410634+4.p
179886.58/23773.89	eprover: CPU time limit exceeded, terminating
179886.58/23773.89	% SZS status Ended for HL410634+4.p
179889.72/23774.30	% SZS status Started for HL410634+5.p
179889.72/23774.30	% SZS status GaveUp for HL410634+5.p
179889.72/23774.30	eprover: CPU time limit exceeded, terminating
179889.72/23774.30	% SZS status Ended for HL410634+5.p
179891.52/23774.49	% SZS status Started for HL410635+4.p
179891.52/23774.49	% SZS status GaveUp for HL410635+4.p
179891.52/23774.49	eprover: CPU time limit exceeded, terminating
179891.52/23774.49	% SZS status Ended for HL410635+4.p
179893.19/23774.71	% SZS status Started for HL410635+5.p
179893.19/23774.71	% SZS status GaveUp for HL410635+5.p
179893.19/23774.71	eprover: CPU time limit exceeded, terminating
179893.19/23774.71	% SZS status Ended for HL410635+5.p
179893.59/23774.74	% SZS status Started for HL410638+4.p
179893.59/23774.74	% SZS status GaveUp for HL410638+4.p
179893.59/23774.74	eprover: CPU time limit exceeded, terminating
179893.59/23774.74	% SZS status Ended for HL410638+4.p
179900.25/23775.57	% SZS status Started for HL410638+5.p
179900.25/23775.57	% SZS status GaveUp for HL410638+5.p
179900.25/23775.57	eprover: CPU time limit exceeded, terminating
179900.25/23775.57	% SZS status Ended for HL410638+5.p
179904.09/23776.06	% SZS status Started for HL410639+4.p
179904.09/23776.06	% SZS status GaveUp for HL410639+4.p
179904.09/23776.06	eprover: CPU time limit exceeded, terminating
179904.09/23776.06	% SZS status Ended for HL410639+4.p
179910.64/23776.92	% SZS status Started for HL410640+4.p
179910.64/23776.92	% SZS status GaveUp for HL410640+4.p
179910.64/23776.92	eprover: CPU time limit exceeded, terminating
179910.64/23776.92	% SZS status Ended for HL410640+4.p
179915.78/23777.52	% SZS status Started for HL410641+4.p
179915.78/23777.52	% SZS status GaveUp for HL410641+4.p
179915.78/23777.52	eprover: CPU time limit exceeded, terminating
179915.78/23777.52	% SZS status Ended for HL410641+4.p
179917.50/23777.80	% SZS status Started for HL410642+4.p
179917.50/23777.80	% SZS status GaveUp for HL410642+4.p
179917.50/23777.80	eprover: CPU time limit exceeded, terminating
179917.50/23777.80	% SZS status Ended for HL410642+4.p
179927.94/23779.11	% SZS status Started for HL410643+4.p
179927.94/23779.11	% SZS status GaveUp for HL410643+4.p
179927.94/23779.11	eprover: CPU time limit exceeded, terminating
179927.94/23779.11	% SZS status Ended for HL410643+4.p
179939.97/23780.57	% SZS status Started for HL410644+4.p
179939.97/23780.57	% SZS status GaveUp for HL410644+4.p
179939.97/23780.57	eprover: CPU time limit exceeded, terminating
179939.97/23780.57	% SZS status Ended for HL410644+4.p
179951.94/23782.14	% SZS status Started for HL410646+4.p
179951.94/23782.14	% SZS status GaveUp for HL410646+4.p
179951.94/23782.14	eprover: CPU time limit exceeded, terminating
179951.94/23782.14	% SZS status Ended for HL410646+4.p
179969.02/23784.34	% SZS status Started for HL410639+5.p
179969.02/23784.34	% SZS status GaveUp for HL410639+5.p
179969.02/23784.34	eprover: CPU time limit exceeded, terminating
179969.02/23784.34	% SZS status Ended for HL410639+5.p
179975.47/23785.06	% SZS status Started for HL410640+5.p
179975.47/23785.06	% SZS status GaveUp for HL410640+5.p
179975.47/23785.06	eprover: CPU time limit exceeded, terminating
179975.47/23785.06	% SZS status Ended for HL410640+5.p
179976.20/23785.16	% SZS status Started for HL410647+4.p
179976.20/23785.16	% SZS status GaveUp for HL410647+4.p
179976.20/23785.16	eprover: CPU time limit exceeded, terminating
179976.20/23785.16	% SZS status Ended for HL410647+4.p
179977.08/23785.43	% SZS status Started for HL410641+5.p
179977.08/23785.43	% SZS status GaveUp for HL410641+5.p
179977.08/23785.43	eprover: CPU time limit exceeded, terminating
179977.08/23785.43	% SZS status Ended for HL410641+5.p
179983.62/23786.06	% SZS status Started for HL410642+5.p
179983.62/23786.06	% SZS status GaveUp for HL410642+5.p
179983.62/23786.06	eprover: CPU time limit exceeded, terminating
179983.62/23786.06	% SZS status Ended for HL410642+5.p
179994.73/23787.48	% SZS status Started for HL410643+5.p
179994.73/23787.48	% SZS status GaveUp for HL410643+5.p
179994.73/23787.48	eprover: CPU time limit exceeded, terminating
179994.73/23787.48	% SZS status Ended for HL410643+5.p
179999.42/23788.12	% SZS status Started for HL410649+4.p
179999.42/23788.12	% SZS status GaveUp for HL410649+4.p
179999.42/23788.12	eprover: CPU time limit exceeded, terminating
179999.42/23788.12	% SZS status Ended for HL410649+4.p
180001.78/23788.35	% SZS status Started for HL410644+5.p
180001.78/23788.35	% SZS status GaveUp for HL410644+5.p
180001.78/23788.35	eprover: CPU time limit exceeded, terminating
180001.78/23788.35	% SZS status Ended for HL410644+5.p
180002.81/23788.49	% SZS status Started for HL410650+4.p
180002.81/23788.49	% SZS status GaveUp for HL410650+4.p
180002.81/23788.49	eprover: CPU time limit exceeded, terminating
180002.81/23788.49	% SZS status Ended for HL410650+4.p
180018.77/23790.53	% SZS status Started for HL410651+4.p
180018.77/23790.53	% SZS status GaveUp for HL410651+4.p
180018.77/23790.53	eprover: CPU time limit exceeded, terminating
180018.77/23790.53	% SZS status Ended for HL410651+4.p
180023.66/23791.14	% SZS status Started for HL410646+5.p
180023.66/23791.14	% SZS status GaveUp for HL410646+5.p
180023.66/23791.14	eprover: CPU time limit exceeded, terminating
180023.66/23791.14	% SZS status Ended for HL410646+5.p
180025.81/23791.39	% SZS status Started for HL410652+4.p
180025.81/23791.39	% SZS status GaveUp for HL410652+4.p
180025.81/23791.39	eprover: CPU time limit exceeded, terminating
180025.81/23791.39	% SZS status Ended for HL410652+4.p
180043.25/23793.57	% SZS status Started for HL410653+4.p
180043.25/23793.57	% SZS status GaveUp for HL410653+4.p
180043.25/23793.57	eprover: CPU time limit exceeded, terminating
180043.25/23793.57	% SZS status Ended for HL410653+4.p
180047.86/23794.18	% SZS status Started for HL410653+5.p
180047.86/23794.18	% SZS status GaveUp for HL410653+5.p
180047.86/23794.18	eprover: CPU time limit exceeded, terminating
180047.86/23794.18	% SZS status Ended for HL410653+5.p
180049.33/23794.43	% SZS status Started for HL410654+4.p
180049.33/23794.43	% SZS status GaveUp for HL410654+4.p
180049.33/23794.43	eprover: CPU time limit exceeded, terminating
180049.33/23794.43	% SZS status Ended for HL410654+4.p
180052.67/23794.88	% SZS status Started for HL410647+5.p
180052.67/23794.88	% SZS status GaveUp for HL410647+5.p
180052.67/23794.88	eprover: CPU time limit exceeded, terminating
180052.67/23794.88	% SZS status Ended for HL410647+5.p
180060.03/23795.71	% SZS status Started for HL410649+5.p
180060.03/23795.71	% SZS status GaveUp for HL410649+5.p
180060.03/23795.71	eprover: CPU time limit exceeded, terminating
180060.03/23795.71	% SZS status Ended for HL410649+5.p
180075.84/23796.61	% SZS status Started for HL410654+5.p
180075.84/23796.61	% SZS status GaveUp for HL410654+5.p
180075.84/23796.61	eprover: CPU time limit exceeded, terminating
180075.84/23796.61	% SZS status Ended for HL410654+5.p
180076.17/23796.73	% SZS status Started for HL410650+5.p
180076.17/23796.73	% SZS status GaveUp for HL410650+5.p
180076.17/23796.73	eprover: CPU time limit exceeded, terminating
180076.17/23796.73	% SZS status Ended for HL410650+5.p
180080.33/23797.21	% SZS status Started for HL410655+4.p
180080.33/23797.21	% SZS status GaveUp for HL410655+4.p
180080.33/23797.21	eprover: CPU time limit exceeded, terminating
180080.33/23797.21	% SZS status Ended for HL410655+4.p
180082.86/23797.51	% SZS status Started for HL410655+5.p
180082.86/23797.51	% SZS status GaveUp for HL410655+5.p
180082.86/23797.51	eprover: CPU time limit exceeded, terminating
180082.86/23797.51	% SZS status Ended for HL410655+5.p
180085.12/23797.93	% SZS status Started for HL410656+4.p
180085.12/23797.93	% SZS status GaveUp for HL410656+4.p
180085.12/23797.93	eprover: CPU time limit exceeded, terminating
180085.12/23797.93	% SZS status Ended for HL410656+4.p
180093.27/23798.86	% SZS status Started for HL410651+5.p
180093.27/23798.86	% SZS status GaveUp for HL410651+5.p
180093.27/23798.86	eprover: CPU time limit exceeded, terminating
180093.27/23798.86	% SZS status Ended for HL410651+5.p
180093.84/23798.91	% SZS status Started for HL410656+5.p
180093.84/23798.91	% SZS status GaveUp for HL410656+5.p
180093.84/23798.91	eprover: CPU time limit exceeded, terminating
180093.84/23798.91	% SZS status Ended for HL410656+5.p
180099.20/23799.65	% SZS status Started for HL410657+4.p
180099.20/23799.65	% SZS status GaveUp for HL410657+4.p
180099.20/23799.65	eprover: CPU time limit exceeded, terminating
180099.20/23799.65	% SZS status Ended for HL410657+4.p
180099.20/23799.67	% SZS status Started for HL410652+5.p
180099.20/23799.67	% SZS status GaveUp for HL410652+5.p
180099.20/23799.67	eprover: CPU time limit exceeded, terminating
180099.20/23799.67	% SZS status Ended for HL410652+5.p
180111.02/23799.77	% SZS status Started for HL410657+5.p
180111.02/23799.77	% SZS status GaveUp for HL410657+5.p
180111.02/23799.77	eprover: CPU time limit exceeded, terminating
180111.02/23799.77	% SZS status Ended for HL410657+5.p
180115.12/23800.25	% SZS status Started for HL410658+4.p
180115.12/23800.25	% SZS status GaveUp for HL410658+4.p
180115.12/23800.25	eprover: CPU time limit exceeded, terminating
180115.12/23800.25	% SZS status Ended for HL410658+4.p
180117.25/23800.55	% SZS status Started for HL410658+5.p
180117.25/23800.55	% SZS status GaveUp for HL410658+5.p
180117.25/23800.55	eprover: CPU time limit exceeded, terminating
180117.25/23800.55	% SZS status Ended for HL410658+5.p
180120.86/23800.96	% SZS status Started for HL410659+4.p
180120.86/23800.96	% SZS status GaveUp for HL410659+4.p
180120.86/23800.96	eprover: CPU time limit exceeded, terminating
180120.86/23800.96	% SZS status Ended for HL410659+4.p
180127.92/23801.90	% SZS status Started for HL410659+5.p
180127.92/23801.90	% SZS status GaveUp for HL410659+5.p
180127.92/23801.90	eprover: CPU time limit exceeded, terminating
180127.92/23801.90	% SZS status Ended for HL410659+5.p
180129.61/23802.11	% SZS status Started for HL410661+4.p
180129.61/23802.11	% SZS status GaveUp for HL410661+4.p
180129.61/23802.11	eprover: CPU time limit exceeded, terminating
180129.61/23802.11	% SZS status Ended for HL410661+4.p
180134.30/23802.68	% SZS status Started for HL410661+5.p
180134.30/23802.68	% SZS status GaveUp for HL410661+5.p
180134.30/23802.68	eprover: CPU time limit exceeded, terminating
180134.30/23802.68	% SZS status Ended for HL410661+5.p
180134.30/23802.71	% SZS status Started for HL410664+4.p
180134.30/23802.71	% SZS status GaveUp for HL410664+4.p
180134.30/23802.71	eprover: CPU time limit exceeded, terminating
180134.30/23802.71	% SZS status Ended for HL410664+4.p
180135.34/23802.82	% SZS status Started for HL410664+5.p
180135.34/23802.82	% SZS status GaveUp for HL410664+5.p
180135.34/23802.82	eprover: CPU time limit exceeded, terminating
180135.34/23802.82	% SZS status Ended for HL410664+5.p
180139.39/23803.29	% SZS status Started for HL410665+4.p
180139.39/23803.29	% SZS status GaveUp for HL410665+4.p
180139.39/23803.29	eprover: CPU time limit exceeded, terminating
180139.39/23803.29	% SZS status Ended for HL410665+4.p
180141.47/23803.59	% SZS status Started for HL410665+5.p
180141.47/23803.59	% SZS status GaveUp for HL410665+5.p
180141.47/23803.59	eprover: CPU time limit exceeded, terminating
180141.47/23803.59	% SZS status Ended for HL410665+5.p
180144.69/23804.00	% SZS status Started for HL410668+4.p
180144.69/23804.00	% SZS status GaveUp for HL410668+4.p
180144.69/23804.00	eprover: CPU time limit exceeded, terminating
180144.69/23804.00	% SZS status Ended for HL410668+4.p
180152.44/23804.95	% SZS status Started for HL410668+5.p
180152.44/23804.95	% SZS status GaveUp for HL410668+5.p
180152.44/23804.95	eprover: CPU time limit exceeded, terminating
180152.44/23804.95	% SZS status Ended for HL410668+5.p
180154.28/23805.18	% SZS status Started for HL410670+4.p
180154.28/23805.18	% SZS status GaveUp for HL410670+4.p
180154.28/23805.18	eprover: CPU time limit exceeded, terminating
180154.28/23805.18	% SZS status Ended for HL410670+4.p
180158.69/23805.74	% SZS status Started for HL410671+4.p
180158.69/23805.74	% SZS status GaveUp for HL410671+4.p
180158.69/23805.74	eprover: CPU time limit exceeded, terminating
180158.69/23805.74	% SZS status Ended for HL410671+4.p
180159.77/23805.86	% SZS status Started for HL410671+5.p
180159.77/23805.86	% SZS status GaveUp for HL410671+5.p
180159.77/23805.86	eprover: CPU time limit exceeded, terminating
180159.77/23805.86	% SZS status Ended for HL410671+5.p
180159.77/23805.87	% SZS status Started for HL410670+5.p
180159.77/23805.87	% SZS status GaveUp for HL410670+5.p
180159.77/23805.87	eprover: CPU time limit exceeded, terminating
180159.77/23805.87	% SZS status Ended for HL410670+5.p
180163.05/23806.33	% SZS status Started for HL410672+4.p
180163.05/23806.33	% SZS status GaveUp for HL410672+4.p
180163.05/23806.33	eprover: CPU time limit exceeded, terminating
180163.05/23806.33	% SZS status Ended for HL410672+4.p
180165.58/23806.63	% SZS status Started for HL410672+5.p
180165.58/23806.63	% SZS status GaveUp for HL410672+5.p
180165.58/23806.63	eprover: CPU time limit exceeded, terminating
180165.58/23806.63	% SZS status Ended for HL410672+5.p
180168.41/23807.04	% SZS status Started for HL410673+4.p
180168.41/23807.04	% SZS status GaveUp for HL410673+4.p
180168.41/23807.04	eprover: CPU time limit exceeded, terminating
180168.41/23807.04	% SZS status Ended for HL410673+4.p
180176.88/23807.99	% SZS status Started for HL410673+5.p
180176.88/23807.99	% SZS status GaveUp for HL410673+5.p
180176.88/23807.99	eprover: CPU time limit exceeded, terminating
180176.88/23807.99	% SZS status Ended for HL410673+5.p
180178.23/23808.22	% SZS status Started for HL410675+4.p
180178.23/23808.22	% SZS status GaveUp for HL410675+4.p
180178.23/23808.22	eprover: CPU time limit exceeded, terminating
180178.23/23808.22	% SZS status Ended for HL410675+4.p
180182.61/23808.78	% SZS status Started for HL410675+5.p
180182.61/23808.78	% SZS status GaveUp for HL410675+5.p
180182.61/23808.78	eprover: CPU time limit exceeded, terminating
180182.61/23808.78	% SZS status Ended for HL410675+5.p
180183.78/23808.89	% SZS status Started for HL410676+4.p
180183.78/23808.89	% SZS status GaveUp for HL410676+4.p
180183.78/23808.89	eprover: CPU time limit exceeded, terminating
180183.78/23808.89	% SZS status Ended for HL410676+4.p
180184.09/23808.98	% SZS status Started for HL410676+5.p
180184.09/23808.98	% SZS status GaveUp for HL410676+5.p
180184.09/23808.98	eprover: CPU time limit exceeded, terminating
180184.09/23808.98	% SZS status Ended for HL410676+5.p
180187.58/23809.37	% SZS status Started for HL410677+4.p
180187.58/23809.37	% SZS status GaveUp for HL410677+4.p
180187.58/23809.37	eprover: CPU time limit exceeded, terminating
180187.58/23809.37	% SZS status Ended for HL410677+4.p
180189.77/23809.67	% SZS status Started for HL410677+5.p
180189.77/23809.67	% SZS status GaveUp for HL410677+5.p
180189.77/23809.67	eprover: CPU time limit exceeded, terminating
180189.77/23809.67	% SZS status Ended for HL410677+5.p
180193.06/23810.12	% SZS status Started for HL410678+4.p
180193.06/23810.12	% SZS status GaveUp for HL410678+4.p
180193.06/23810.12	eprover: CPU time limit exceeded, terminating
180193.06/23810.12	% SZS status Ended for HL410678+4.p
180201.80/23811.20	% SZS status Started for HL410678+5.p
180201.80/23811.20	% SZS status GaveUp for HL410678+5.p
180201.80/23811.20	eprover: CPU time limit exceeded, terminating
180201.80/23811.20	% SZS status Ended for HL410678+5.p
180202.52/23811.26	% SZS status Started for HL410679+4.p
180202.52/23811.26	% SZS status GaveUp for HL410679+4.p
180202.52/23811.26	eprover: CPU time limit exceeded, terminating
180202.52/23811.26	% SZS status Ended for HL410679+4.p
180206.75/23811.82	% SZS status Started for HL410679+5.p
180206.75/23811.82	% SZS status GaveUp for HL410679+5.p
180206.75/23811.82	eprover: CPU time limit exceeded, terminating
180206.75/23811.82	% SZS status Ended for HL410679+5.p
180208.00/23811.94	% SZS status Started for HL410680+4.p
180208.00/23811.94	% SZS status GaveUp for HL410680+4.p
180208.00/23811.94	eprover: CPU time limit exceeded, terminating
180208.00/23811.94	% SZS status Ended for HL410680+4.p
180208.75/23812.03	% SZS status Started for HL410680+5.p
180208.75/23812.03	% SZS status GaveUp for HL410680+5.p
180208.75/23812.03	eprover: CPU time limit exceeded, terminating
180208.75/23812.03	% SZS status Ended for HL410680+5.p
180210.89/23812.41	% SZS status Started for HL410681+4.p
180210.89/23812.41	% SZS status GaveUp for HL410681+4.p
180210.89/23812.41	eprover: CPU time limit exceeded, terminating
180210.89/23812.41	% SZS status Ended for HL410681+4.p
180213.98/23812.71	% SZS status Started for HL410681+5.p
180213.98/23812.71	% SZS status GaveUp for HL410681+5.p
180213.98/23812.71	eprover: CPU time limit exceeded, terminating
180213.98/23812.71	% SZS status Ended for HL410681+5.p
180217.56/23813.16	% SZS status Started for HL410682+4.p
180217.56/23813.16	% SZS status GaveUp for HL410682+4.p
180217.56/23813.16	eprover: CPU time limit exceeded, terminating
180217.56/23813.16	% SZS status Ended for HL410682+4.p
180225.73/23814.24	% SZS status Started for HL410682+5.p
180225.73/23814.24	% SZS status GaveUp for HL410682+5.p
180225.73/23814.24	eprover: CPU time limit exceeded, terminating
180225.73/23814.24	% SZS status Ended for HL410682+5.p
180226.81/23814.32	% SZS status Started for HL410683+4.p
180226.81/23814.32	% SZS status GaveUp for HL410683+4.p
180226.81/23814.32	eprover: CPU time limit exceeded, terminating
180226.81/23814.32	% SZS status Ended for HL410683+4.p
180230.17/23814.87	% SZS status Started for HL410683+5.p
180230.17/23814.87	% SZS status GaveUp for HL410683+5.p
180230.17/23814.87	eprover: CPU time limit exceeded, terminating
180230.17/23814.87	% SZS status Ended for HL410683+5.p
180232.14/23815.06	% SZS status Started for HL410684+5.p
180232.14/23815.06	% SZS status GaveUp for HL410684+5.p
180232.14/23815.06	eprover: CPU time limit exceeded, terminating
180232.14/23815.06	% SZS status Ended for HL410684+5.p
180233.33/23815.16	% SZS status Started for HL410684+4.p
180233.33/23815.16	% SZS status GaveUp for HL410684+4.p
180233.33/23815.16	eprover: CPU time limit exceeded, terminating
180233.33/23815.16	% SZS status Ended for HL410684+4.p
180235.20/23815.47	% SZS status Started for HL410685+4.p
180235.20/23815.47	% SZS status GaveUp for HL410685+4.p
180235.20/23815.47	eprover: CPU time limit exceeded, terminating
180235.20/23815.47	% SZS status Ended for HL410685+4.p
180237.84/23815.75	% SZS status Started for HL410685+5.p
180237.84/23815.75	% SZS status GaveUp for HL410685+5.p
180237.84/23815.75	eprover: CPU time limit exceeded, terminating
180237.84/23815.75	% SZS status Ended for HL410685+5.p
180241.23/23816.20	% SZS status Started for HL410686+4.p
180241.23/23816.20	% SZS status GaveUp for HL410686+4.p
180241.23/23816.20	eprover: CPU time limit exceeded, terminating
180241.23/23816.20	% SZS status Ended for HL410686+4.p
180250.38/23817.28	% SZS status Started for HL410686+5.p
180250.38/23817.28	% SZS status GaveUp for HL410686+5.p
180250.38/23817.28	eprover: CPU time limit exceeded, terminating
180250.38/23817.28	% SZS status Ended for HL410686+5.p
180250.94/23817.36	% SZS status Started for HL410688+4.p
180250.94/23817.36	% SZS status GaveUp for HL410688+4.p
180250.94/23817.36	eprover: CPU time limit exceeded, terminating
180250.94/23817.36	% SZS status Ended for HL410688+4.p
180254.97/23817.91	% SZS status Started for HL410688+5.p
180254.97/23817.91	% SZS status GaveUp for HL410688+5.p
180254.97/23817.91	eprover: CPU time limit exceeded, terminating
180254.97/23817.91	% SZS status Ended for HL410688+5.p
180257.44/23818.20	% SZS status Started for HL410689+5.p
180257.44/23818.20	% SZS status GaveUp for HL410689+5.p
180257.44/23818.20	eprover: CPU time limit exceeded, terminating
180257.44/23818.20	% SZS status Ended for HL410689+5.p
180258.02/23818.27	% SZS status Started for HL410689+4.p
180258.02/23818.27	% SZS status GaveUp for HL410689+4.p
180258.02/23818.27	eprover: CPU time limit exceeded, terminating
180258.02/23818.27	% SZS status Ended for HL410689+4.p
180259.38/23818.50	% SZS status Started for HL410690+4.p
180259.38/23818.50	% SZS status GaveUp for HL410690+4.p
180259.38/23818.50	eprover: CPU time limit exceeded, terminating
180259.38/23818.50	% SZS status Ended for HL410690+4.p
180262.33/23818.79	% SZS status Started for HL410690+5.p
180262.33/23818.79	% SZS status GaveUp for HL410690+5.p
180262.33/23818.79	eprover: CPU time limit exceeded, terminating
180262.33/23818.79	% SZS status Ended for HL410690+5.p
180265.47/23819.24	% SZS status Started for HL410692+4.p
180265.47/23819.24	% SZS status GaveUp for HL410692+4.p
180265.47/23819.24	eprover: CPU time limit exceeded, terminating
180265.47/23819.24	% SZS status Ended for HL410692+4.p
180274.45/23820.32	% SZS status Started for HL410692+5.p
180274.45/23820.32	% SZS status GaveUp for HL410692+5.p
180274.45/23820.32	eprover: CPU time limit exceeded, terminating
180274.45/23820.32	% SZS status Ended for HL410692+5.p
180274.75/23820.40	% SZS status Started for HL410693+4.p
180274.75/23820.40	% SZS status GaveUp for HL410693+4.p
180274.75/23820.40	eprover: CPU time limit exceeded, terminating
180274.75/23820.40	% SZS status Ended for HL410693+4.p
180279.11/23820.95	% SZS status Started for HL410693+5.p
180279.11/23820.95	% SZS status GaveUp for HL410693+5.p
180279.11/23820.95	eprover: CPU time limit exceeded, terminating
180279.11/23820.95	% SZS status Ended for HL410693+5.p
180281.75/23821.26	% SZS status Started for HL410694+4.p
180281.75/23821.26	% SZS status GaveUp for HL410694+4.p
180281.75/23821.26	eprover: CPU time limit exceeded, terminating
180281.75/23821.26	% SZS status Ended for HL410694+4.p
180283.47/23821.54	% SZS status Started for HL410695+4.p
180283.47/23821.54	% SZS status GaveUp for HL410695+4.p
180283.47/23821.54	eprover: CPU time limit exceeded, terminating
180283.47/23821.54	% SZS status Ended for HL410695+4.p
180284.33/23821.68	% SZS status Started for HL410694+5.p
180284.33/23821.68	% SZS status GaveUp for HL410694+5.p
180284.33/23821.68	eprover: CPU time limit exceeded, terminating
180284.33/23821.68	% SZS status Ended for HL410694+5.p
180285.30/23821.84	% SZS status Started for HL410695+5.p
180285.30/23821.84	% SZS status GaveUp for HL410695+5.p
180285.30/23821.84	eprover: CPU time limit exceeded, terminating
180285.30/23821.84	% SZS status Ended for HL410695+5.p
180289.52/23822.39	% SZS status Started for HL410696+4.p
180289.52/23822.39	% SZS status GaveUp for HL410696+4.p
180289.52/23822.39	eprover: CPU time limit exceeded, terminating
180289.52/23822.39	% SZS status Ended for HL410696+4.p
180297.23/23823.36	% SZS status Started for HL410696+5.p
180297.23/23823.36	% SZS status GaveUp for HL410696+5.p
180297.23/23823.36	eprover: CPU time limit exceeded, terminating
180297.23/23823.36	% SZS status Ended for HL410696+5.p
180302.53/23823.99	% SZS status Started for HL410698+5.p
180302.53/23823.99	% SZS status GaveUp for HL410698+5.p
180302.53/23823.99	eprover: CPU time limit exceeded, terminating
180302.53/23823.99	% SZS status Ended for HL410698+5.p
180303.28/23824.08	% SZS status Started for HL410698+4.p
180303.28/23824.08	% SZS status GaveUp for HL410698+4.p
180303.28/23824.08	eprover: CPU time limit exceeded, terminating
180303.28/23824.08	% SZS status Ended for HL410698+4.p
180304.50/23824.30	% SZS status Started for HL410699+4.p
180304.50/23824.30	% SZS status GaveUp for HL410699+4.p
180304.50/23824.30	eprover: CPU time limit exceeded, terminating
180304.50/23824.30	% SZS status Ended for HL410699+4.p
180307.31/23824.59	% SZS status Started for HL410699+5.p
180307.31/23824.59	% SZS status GaveUp for HL410699+5.p
180307.31/23824.59	eprover: CPU time limit exceeded, terminating
180307.31/23824.59	% SZS status Ended for HL410699+5.p
180309.23/23824.88	% SZS status Started for HL410700+5.p
180309.23/23824.88	% SZS status GaveUp for HL410700+5.p
180309.23/23824.88	eprover: CPU time limit exceeded, terminating
180309.23/23824.88	% SZS status Ended for HL410700+5.p
180309.78/23824.94	% SZS status Started for HL410700+4.p
180309.78/23824.94	% SZS status GaveUp for HL410700+4.p
180309.78/23824.94	eprover: CPU time limit exceeded, terminating
180309.78/23824.94	% SZS status Ended for HL410700+4.p
180313.25/23825.42	% SZS status Started for HL410701+4.p
180313.25/23825.42	% SZS status GaveUp for HL410701+4.p
180313.25/23825.42	eprover: CPU time limit exceeded, terminating
180313.25/23825.42	% SZS status Ended for HL410701+4.p
180321.70/23826.40	% SZS status Started for HL410701+5.p
180321.70/23826.40	% SZS status GaveUp for HL410701+5.p
180321.70/23826.40	eprover: CPU time limit exceeded, terminating
180321.70/23826.40	% SZS status Ended for HL410701+5.p
180327.03/23827.07	% SZS status Started for HL410702+4.p
180327.03/23827.07	% SZS status GaveUp for HL410702+4.p
180327.03/23827.07	eprover: CPU time limit exceeded, terminating
180327.03/23827.07	% SZS status Ended for HL410702+4.p
180327.34/23827.12	% SZS status Started for HL410702+5.p
180327.34/23827.12	% SZS status GaveUp for HL410702+5.p
180327.34/23827.12	eprover: CPU time limit exceeded, terminating
180327.34/23827.12	% SZS status Ended for HL410702+5.p
180329.02/23827.34	% SZS status Started for HL410703+4.p
180329.02/23827.34	% SZS status GaveUp for HL410703+4.p
180329.02/23827.34	eprover: CPU time limit exceeded, terminating
180329.02/23827.34	% SZS status Ended for HL410703+4.p
180331.14/23827.62	% SZS status Started for HL410703+5.p
180331.14/23827.62	% SZS status GaveUp for HL410703+5.p
180331.14/23827.62	eprover: CPU time limit exceeded, terminating
180331.14/23827.62	% SZS status Ended for HL410703+5.p
180333.25/23827.91	% SZS status Started for HL410704+4.p
180333.25/23827.91	% SZS status GaveUp for HL410704+4.p
180333.25/23827.91	eprover: CPU time limit exceeded, terminating
180333.25/23827.91	% SZS status Ended for HL410704+4.p
180335.17/23828.13	% SZS status Started for HL410704+5.p
180335.17/23828.13	% SZS status GaveUp for HL410704+5.p
180335.17/23828.13	eprover: CPU time limit exceeded, terminating
180335.17/23828.13	% SZS status Ended for HL410704+5.p
180337.94/23828.46	% SZS status Started for HL410705+4.p
180337.94/23828.46	% SZS status GaveUp for HL410705+4.p
180337.94/23828.46	eprover: CPU time limit exceeded, terminating
180337.94/23828.46	% SZS status Ended for HL410705+4.p
180345.69/23829.44	% SZS status Started for HL410705+5.p
180345.69/23829.44	% SZS status GaveUp for HL410705+5.p
180345.69/23829.44	eprover: CPU time limit exceeded, terminating
180345.69/23829.44	% SZS status Ended for HL410705+5.p
180350.20/23830.10	% SZS status Started for HL410707+4.p
180350.20/23830.10	% SZS status GaveUp for HL410707+4.p
180350.20/23830.10	eprover: CPU time limit exceeded, terminating
180350.20/23830.10	% SZS status Ended for HL410707+4.p
180351.62/23830.16	% SZS status Started for HL410707+5.p
180351.62/23830.16	% SZS status GaveUp for HL410707+5.p
180351.62/23830.16	eprover: CPU time limit exceeded, terminating
180351.62/23830.16	% SZS status Ended for HL410707+5.p
180352.61/23830.38	% SZS status Started for HL410708+4.p
180352.61/23830.38	% SZS status GaveUp for HL410708+4.p
180352.61/23830.38	eprover: CPU time limit exceeded, terminating
180352.61/23830.38	% SZS status Ended for HL410708+4.p
180355.45/23830.66	% SZS status Started for HL410708+5.p
180355.45/23830.66	% SZS status GaveUp for HL410708+5.p
180355.45/23830.66	eprover: CPU time limit exceeded, terminating
180355.45/23830.66	% SZS status Ended for HL410708+5.p
180357.47/23830.95	% SZS status Started for HL410709+4.p
180357.47/23830.95	% SZS status GaveUp for HL410709+4.p
180357.47/23830.95	eprover: CPU time limit exceeded, terminating
180357.47/23830.95	% SZS status Ended for HL410709+4.p
180360.23/23831.33	% SZS status Started for HL410709+5.p
180360.23/23831.33	% SZS status GaveUp for HL410709+5.p
180360.23/23831.33	eprover: CPU time limit exceeded, terminating
180360.23/23831.33	% SZS status Ended for HL410709+5.p
180361.84/23831.50	% SZS status Started for HL410710+4.p
180361.84/23831.50	% SZS status GaveUp for HL410710+4.p
180361.84/23831.50	eprover: CPU time limit exceeded, terminating
180361.84/23831.50	% SZS status Ended for HL410710+4.p
180370.00/23832.48	% SZS status Started for HL410710+5.p
180370.00/23832.48	% SZS status GaveUp for HL410710+5.p
180370.00/23832.48	eprover: CPU time limit exceeded, terminating
180370.00/23832.48	% SZS status Ended for HL410710+5.p
180374.66/23833.14	% SZS status Started for HL410711+4.p
180374.66/23833.14	% SZS status GaveUp for HL410711+4.p
180374.66/23833.14	eprover: CPU time limit exceeded, terminating
180374.66/23833.14	% SZS status Ended for HL410711+4.p
180375.62/23833.20	% SZS status Started for HL410711+5.p
180375.62/23833.20	% SZS status GaveUp for HL410711+5.p
180375.62/23833.20	eprover: CPU time limit exceeded, terminating
180375.62/23833.20	% SZS status Ended for HL410711+5.p
180376.73/23833.41	% SZS status Started for HL410712+4.p
180376.73/23833.41	% SZS status GaveUp for HL410712+4.p
180376.73/23833.41	eprover: CPU time limit exceeded, terminating
180376.73/23833.41	% SZS status Ended for HL410712+4.p
180379.23/23833.70	% SZS status Started for HL410712+5.p
180379.23/23833.70	% SZS status GaveUp for HL410712+5.p
180379.23/23833.70	eprover: CPU time limit exceeded, terminating
180379.23/23833.70	% SZS status Ended for HL410712+5.p
180382.78/23834.17	% SZS status Started for HL410715+4.p
180382.78/23834.17	% SZS status GaveUp for HL410715+4.p
180382.78/23834.17	eprover: CPU time limit exceeded, terminating
180382.78/23834.17	% SZS status Ended for HL410715+4.p
180384.39/23834.37	% SZS status Started for HL410715+5.p
180384.39/23834.37	% SZS status GaveUp for HL410715+5.p
180384.39/23834.37	eprover: CPU time limit exceeded, terminating
180384.39/23834.37	% SZS status Ended for HL410715+5.p
180385.42/23834.53	% SZS status Started for HL410717+4.p
180385.42/23834.53	% SZS status GaveUp for HL410717+4.p
180385.42/23834.53	eprover: CPU time limit exceeded, terminating
180385.42/23834.53	% SZS status Ended for HL410717+4.p
180393.58/23835.52	% SZS status Started for HL410717+5.p
180393.58/23835.52	% SZS status GaveUp for HL410717+5.p
180393.58/23835.52	eprover: CPU time limit exceeded, terminating
180393.58/23835.52	% SZS status Ended for HL410717+5.p
180399.19/23836.18	% SZS status Started for HL410719+4.p
180399.19/23836.18	% SZS status GaveUp for HL410719+4.p
180399.19/23836.18	eprover: CPU time limit exceeded, terminating
180399.19/23836.18	% SZS status Ended for HL410719+4.p
180399.47/23836.24	% SZS status Started for HL410719+5.p
180399.47/23836.24	% SZS status GaveUp for HL410719+5.p
180399.47/23836.24	eprover: CPU time limit exceeded, terminating
180399.47/23836.24	% SZS status Ended for HL410719+5.p
180400.98/23836.46	% SZS status Started for HL410720+4.p
180400.98/23836.46	% SZS status GaveUp for HL410720+4.p
180400.98/23836.46	eprover: CPU time limit exceeded, terminating
180400.98/23836.46	% SZS status Ended for HL410720+4.p
180405.50/23836.99	% SZS status Started for HL410720+5.p
180405.50/23836.99	% SZS status GaveUp for HL410720+5.p
180405.50/23836.99	eprover: CPU time limit exceeded, terminating
180405.50/23836.99	% SZS status Ended for HL410720+5.p
180407.08/23837.20	% SZS status Started for HL410722+4.p
180407.08/23837.20	% SZS status GaveUp for HL410722+4.p
180407.08/23837.20	eprover: CPU time limit exceeded, terminating
180407.08/23837.20	% SZS status Ended for HL410722+4.p
180408.08/23837.40	% SZS status Started for HL410722+5.p
180408.08/23837.40	% SZS status GaveUp for HL410722+5.p
180408.08/23837.40	eprover: CPU time limit exceeded, terminating
180408.08/23837.40	% SZS status Ended for HL410722+5.p
180410.08/23837.59	% SZS status Started for HL410723+4.p
180410.08/23837.59	% SZS status GaveUp for HL410723+4.p
180410.08/23837.59	eprover: CPU time limit exceeded, terminating
180410.08/23837.59	% SZS status Ended for HL410723+4.p
180417.89/23838.56	% SZS status Started for HL410723+5.p
180417.89/23838.56	% SZS status GaveUp for HL410723+5.p
180417.89/23838.56	eprover: CPU time limit exceeded, terminating
180417.89/23838.56	% SZS status Ended for HL410723+5.p
180423.17/23839.22	% SZS status Started for HL410724+4.p
180423.17/23839.22	% SZS status GaveUp for HL410724+4.p
180423.17/23839.22	eprover: CPU time limit exceeded, terminating
180423.17/23839.22	% SZS status Ended for HL410724+4.p
180423.17/23839.28	% SZS status Started for HL410724+5.p
180423.17/23839.28	% SZS status GaveUp for HL410724+5.p
180423.17/23839.28	eprover: CPU time limit exceeded, terminating
180423.17/23839.28	% SZS status Ended for HL410724+5.p
180425.53/23839.64	% SZS status Started for HL410725+4.p
180425.53/23839.64	% SZS status GaveUp for HL410725+4.p
180425.53/23839.64	eprover: CPU time limit exceeded, terminating
180425.53/23839.64	% SZS status Ended for HL410725+4.p
180429.50/23840.03	% SZS status Started for HL410725+5.p
180429.50/23840.03	% SZS status GaveUp for HL410725+5.p
180429.50/23840.03	eprover: CPU time limit exceeded, terminating
180429.50/23840.03	% SZS status Ended for HL410725+5.p
180430.73/23840.24	% SZS status Started for HL410726+4.p
180430.73/23840.24	% SZS status GaveUp for HL410726+4.p
180430.73/23840.24	eprover: CPU time limit exceeded, terminating
180430.73/23840.24	% SZS status Ended for HL410726+4.p
180433.52/23840.54	% SZS status Started for HL410726+5.p
180433.52/23840.54	% SZS status GaveUp for HL410726+5.p
180433.52/23840.54	eprover: CPU time limit exceeded, terminating
180433.52/23840.54	% SZS status Ended for HL410726+5.p
180433.81/23840.63	% SZS status Started for HL410727+4.p
180433.81/23840.63	% SZS status GaveUp for HL410727+4.p
180433.81/23840.63	eprover: CPU time limit exceeded, terminating
180433.81/23840.63	% SZS status Ended for HL410727+4.p
180441.83/23841.60	% SZS status Started for HL410727+5.p
180441.83/23841.60	% SZS status GaveUp for HL410727+5.p
180441.83/23841.60	eprover: CPU time limit exceeded, terminating
180441.83/23841.60	% SZS status Ended for HL410727+5.p
180447.20/23842.26	% SZS status Started for HL410728+4.p
180447.20/23842.26	% SZS status GaveUp for HL410728+4.p
180447.20/23842.26	eprover: CPU time limit exceeded, terminating
180447.20/23842.26	% SZS status Ended for HL410728+4.p
180448.67/23842.46	% SZS status Started for HL410728+5.p
180448.67/23842.46	% SZS status GaveUp for HL410728+5.p
180448.67/23842.46	eprover: CPU time limit exceeded, terminating
180448.67/23842.46	% SZS status Ended for HL410728+5.p
180450.64/23842.69	% SZS status Started for HL410730+4.p
180450.64/23842.69	% SZS status GaveUp for HL410730+4.p
180450.64/23842.69	eprover: CPU time limit exceeded, terminating
180450.64/23842.69	% SZS status Ended for HL410730+4.p
180453.33/23843.06	% SZS status Started for HL410730+5.p
180453.33/23843.06	% SZS status GaveUp for HL410730+5.p
180453.33/23843.06	eprover: CPU time limit exceeded, terminating
180453.33/23843.06	% SZS status Ended for HL410730+5.p
180455.41/23843.28	% SZS status Started for HL410731+4.p
180455.41/23843.28	% SZS status GaveUp for HL410731+4.p
180455.41/23843.28	eprover: CPU time limit exceeded, terminating
180455.41/23843.28	% SZS status Ended for HL410731+4.p
180457.52/23843.58	% SZS status Started for HL410731+5.p
180457.52/23843.58	% SZS status GaveUp for HL410731+5.p
180457.52/23843.58	eprover: CPU time limit exceeded, terminating
180457.52/23843.58	% SZS status Ended for HL410731+5.p
180457.89/23843.67	% SZS status Started for HL410732+4.p
180457.89/23843.67	% SZS status GaveUp for HL410732+4.p
180457.89/23843.67	eprover: CPU time limit exceeded, terminating
180457.89/23843.67	% SZS status Ended for HL410732+4.p
180465.81/23844.64	% SZS status Started for HL410732+5.p
180465.81/23844.64	% SZS status GaveUp for HL410732+5.p
180465.81/23844.64	eprover: CPU time limit exceeded, terminating
180465.81/23844.64	% SZS status Ended for HL410732+5.p
180471.20/23845.30	% SZS status Started for HL410733+4.p
180471.20/23845.30	% SZS status GaveUp for HL410733+4.p
180471.20/23845.30	eprover: CPU time limit exceeded, terminating
180471.20/23845.30	% SZS status Ended for HL410733+4.p
180473.31/23845.57	% SZS status Started for HL410733+5.p
180473.31/23845.57	% SZS status GaveUp for HL410733+5.p
180473.31/23845.57	eprover: CPU time limit exceeded, terminating
180473.31/23845.57	% SZS status Ended for HL410733+5.p
180474.45/23845.72	% SZS status Started for HL410734+4.p
180474.45/23845.72	% SZS status GaveUp for HL410734+4.p
180474.45/23845.72	eprover: CPU time limit exceeded, terminating
180474.45/23845.72	% SZS status Ended for HL410734+4.p
180477.70/23846.11	% SZS status Started for HL410734+5.p
180477.70/23846.11	% SZS status GaveUp for HL410734+5.p
180477.70/23846.11	eprover: CPU time limit exceeded, terminating
180477.70/23846.11	% SZS status Ended for HL410734+5.p
180479.34/23846.32	% SZS status Started for HL410735+4.p
180479.34/23846.32	% SZS status GaveUp for HL410735+4.p
180479.34/23846.32	eprover: CPU time limit exceeded, terminating
180479.34/23846.32	% SZS status Ended for HL410735+4.p
180481.34/23846.62	% SZS status Started for HL410735+5.p
180481.34/23846.62	% SZS status GaveUp for HL410735+5.p
180481.34/23846.62	eprover: CPU time limit exceeded, terminating
180481.34/23846.62	% SZS status Ended for HL410735+5.p
180483.55/23846.85	% SZS status Started for HL410737+4.p
180483.55/23846.85	% SZS status GaveUp for HL410737+4.p
180483.55/23846.85	eprover: CPU time limit exceeded, terminating
180483.55/23846.85	% SZS status Ended for HL410737+4.p
180490.11/23847.68	% SZS status Started for HL410737+5.p
180490.11/23847.68	% SZS status GaveUp for HL410737+5.p
180490.11/23847.68	eprover: CPU time limit exceeded, terminating
180490.11/23847.68	% SZS status Ended for HL410737+5.p
180495.44/23848.33	% SZS status Started for HL410738+4.p
180495.44/23848.33	% SZS status GaveUp for HL410738+4.p
180495.44/23848.33	eprover: CPU time limit exceeded, terminating
180495.44/23848.33	% SZS status Ended for HL410738+4.p
180497.16/23848.60	% SZS status Started for HL410738+5.p
180497.16/23848.60	% SZS status GaveUp for HL410738+5.p
180497.16/23848.60	eprover: CPU time limit exceeded, terminating
180497.16/23848.60	% SZS status Ended for HL410738+5.p
180498.36/23848.76	% SZS status Started for HL410739+4.p
180498.36/23848.76	% SZS status GaveUp for HL410739+4.p
180498.36/23848.76	eprover: CPU time limit exceeded, terminating
180498.36/23848.76	% SZS status Ended for HL410739+4.p
180501.25/23849.14	% SZS status Started for HL410739+5.p
180501.25/23849.14	% SZS status GaveUp for HL410739+5.p
180501.25/23849.14	eprover: CPU time limit exceeded, terminating
180501.25/23849.14	% SZS status Ended for HL410739+5.p
180502.28/23849.36	% SZS status Started for HL410740+4.p
180502.28/23849.36	% SZS status GaveUp for HL410740+4.p
180502.28/23849.36	eprover: CPU time limit exceeded, terminating
180502.28/23849.36	% SZS status Ended for HL410740+4.p
180506.23/23849.75	% SZS status Started for HL410740+5.p
180506.23/23849.75	% SZS status GaveUp for HL410740+5.p
180506.23/23849.75	eprover: CPU time limit exceeded, terminating
180506.23/23849.75	% SZS status Ended for HL410740+5.p
180507.27/23849.89	% SZS status Started for HL410742+4.p
180507.27/23849.89	% SZS status GaveUp for HL410742+4.p
180507.27/23849.89	eprover: CPU time limit exceeded, terminating
180507.27/23849.89	% SZS status Ended for HL410742+4.p
180514.08/23850.72	% SZS status Started for HL410742+5.p
180514.08/23850.72	% SZS status GaveUp for HL410742+5.p
180514.08/23850.72	eprover: CPU time limit exceeded, terminating
180514.08/23850.72	% SZS status Ended for HL410742+5.p
180519.36/23851.37	% SZS status Started for HL410743+4.p
180519.36/23851.37	% SZS status GaveUp for HL410743+4.p
180519.36/23851.37	eprover: CPU time limit exceeded, terminating
180519.36/23851.37	% SZS status Ended for HL410743+4.p
180521.19/23851.64	% SZS status Started for HL410743+5.p
180521.19/23851.64	% SZS status GaveUp for HL410743+5.p
180521.19/23851.64	eprover: CPU time limit exceeded, terminating
180521.19/23851.64	% SZS status Ended for HL410743+5.p
180523.25/23851.85	% SZS status Started for HL410745+4.p
180523.25/23851.85	% SZS status GaveUp for HL410745+4.p
180523.25/23851.85	eprover: CPU time limit exceeded, terminating
180523.25/23851.85	% SZS status Ended for HL410745+4.p
180525.08/23852.19	% SZS status Started for HL410745+5.p
180525.08/23852.19	% SZS status GaveUp for HL410745+5.p
180525.08/23852.19	eprover: CPU time limit exceeded, terminating
180525.08/23852.19	% SZS status Ended for HL410745+5.p
180527.25/23852.39	% SZS status Started for HL410746+4.p
180527.25/23852.39	% SZS status GaveUp for HL410746+4.p
180527.25/23852.39	eprover: CPU time limit exceeded, terminating
180527.25/23852.39	% SZS status Ended for HL410746+4.p
180530.44/23852.79	% SZS status Started for HL410746+5.p
180530.44/23852.79	% SZS status GaveUp for HL410746+5.p
180530.44/23852.79	eprover: CPU time limit exceeded, terminating
180530.44/23852.79	% SZS status Ended for HL410746+5.p
180532.47/23853.08	% SZS status Started for HL410747+4.p
180532.47/23853.08	% SZS status GaveUp for HL410747+4.p
180532.47/23853.08	eprover: CPU time limit exceeded, terminating
180532.47/23853.08	% SZS status Ended for HL410747+4.p
180538.36/23853.76	% SZS status Started for HL410747+5.p
180538.36/23853.76	% SZS status GaveUp for HL410747+5.p
180538.36/23853.76	eprover: CPU time limit exceeded, terminating
180538.36/23853.76	% SZS status Ended for HL410747+5.p
180543.52/23854.40	% SZS status Started for HL410748+4.p
180543.52/23854.40	% SZS status GaveUp for HL410748+4.p
180543.52/23854.40	eprover: CPU time limit exceeded, terminating
180543.52/23854.40	% SZS status Ended for HL410748+4.p
180545.78/23854.67	% SZS status Started for HL410748+5.p
180545.78/23854.67	% SZS status GaveUp for HL410748+5.p
180545.78/23854.67	eprover: CPU time limit exceeded, terminating
180545.78/23854.67	% SZS status Ended for HL410748+5.p
180547.27/23854.89	% SZS status Started for HL410749+4.p
180547.27/23854.89	% SZS status GaveUp for HL410749+4.p
180547.27/23854.89	eprover: CPU time limit exceeded, terminating
180547.27/23854.89	% SZS status Ended for HL410749+4.p
180550.27/23855.23	% SZS status Started for HL410749+5.p
180550.27/23855.23	% SZS status GaveUp for HL410749+5.p
180550.27/23855.23	eprover: CPU time limit exceeded, terminating
180550.27/23855.23	% SZS status Ended for HL410749+5.p
180551.39/23855.43	% SZS status Started for HL410750+4.p
180551.39/23855.43	% SZS status GaveUp for HL410750+4.p
180551.39/23855.43	eprover: CPU time limit exceeded, terminating
180551.39/23855.43	% SZS status Ended for HL410750+4.p
180554.41/23855.83	% SZS status Started for HL410750+5.p
180554.41/23855.83	% SZS status GaveUp for HL410750+5.p
180554.41/23855.83	eprover: CPU time limit exceeded, terminating
180554.41/23855.83	% SZS status Ended for HL410750+5.p
180557.33/23856.14	% SZS status Started for HL410751+4.p
180557.33/23856.14	% SZS status GaveUp for HL410751+4.p
180557.33/23856.14	eprover: CPU time limit exceeded, terminating
180557.33/23856.14	% SZS status Ended for HL410751+4.p
180563.62/23856.92	% SZS status Started for HL410751+5.p
180563.62/23856.92	% SZS status GaveUp for HL410751+5.p
180563.62/23856.92	eprover: CPU time limit exceeded, terminating
180563.62/23856.92	% SZS status Ended for HL410751+5.p
180567.00/23857.44	% SZS status Started for HL410752+4.p
180567.00/23857.44	% SZS status GaveUp for HL410752+4.p
180567.00/23857.44	eprover: CPU time limit exceeded, terminating
180567.00/23857.44	% SZS status Ended for HL410752+4.p
180569.95/23857.71	% SZS status Started for HL410752+5.p
180569.95/23857.71	% SZS status GaveUp for HL410752+5.p
180569.95/23857.71	eprover: CPU time limit exceeded, terminating
180569.95/23857.71	% SZS status Ended for HL410752+5.p
180571.34/23857.93	% SZS status Started for HL410753+4.p
180571.34/23857.93	% SZS status GaveUp for HL410753+4.p
180571.34/23857.93	eprover: CPU time limit exceeded, terminating
180571.34/23857.93	% SZS status Ended for HL410753+4.p
180572.98/23858.26	% SZS status Started for HL410753+5.p
180572.98/23858.26	% SZS status GaveUp for HL410753+5.p
180572.98/23858.26	eprover: CPU time limit exceeded, terminating
180572.98/23858.26	% SZS status Ended for HL410753+5.p
180575.75/23858.47	% SZS status Started for HL410756+4.p
180575.75/23858.47	% SZS status GaveUp for HL410756+4.p
180575.75/23858.47	eprover: CPU time limit exceeded, terminating
180575.75/23858.47	% SZS status Ended for HL410756+4.p
180580.08/23859.00	% SZS status Started for HL410756+5.p
180580.08/23859.00	% SZS status GaveUp for HL410756+5.p
180580.08/23859.00	eprover: CPU time limit exceeded, terminating
180580.08/23859.00	% SZS status Ended for HL410756+5.p
180581.53/23859.18	% SZS status Started for HL410757+4.p
180581.53/23859.18	% SZS status GaveUp for HL410757+4.p
180581.53/23859.18	eprover: CPU time limit exceeded, terminating
180581.53/23859.18	% SZS status Ended for HL410757+4.p
180587.61/23859.96	% SZS status Started for HL410757+5.p
180587.61/23859.96	% SZS status GaveUp for HL410757+5.p
180587.61/23859.96	eprover: CPU time limit exceeded, terminating
180587.61/23859.96	% SZS status Ended for HL410757+5.p
180591.53/23860.48	% SZS status Started for HL410758+4.p
180591.53/23860.48	% SZS status GaveUp for HL410758+4.p
180591.53/23860.48	eprover: CPU time limit exceeded, terminating
180591.53/23860.48	% SZS status Ended for HL410758+4.p
180593.95/23860.75	% SZS status Started for HL410758+5.p
180593.95/23860.75	% SZS status GaveUp for HL410758+5.p
180593.95/23860.75	eprover: CPU time limit exceeded, terminating
180593.95/23860.75	% SZS status Ended for HL410758+5.p
180595.09/23860.96	% SZS status Started for HL410761+4.p
180595.09/23860.96	% SZS status GaveUp for HL410761+4.p
180595.09/23860.96	eprover: CPU time limit exceeded, terminating
180595.09/23860.96	% SZS status Ended for HL410761+4.p
180597.61/23861.30	% SZS status Started for HL410761+5.p
180597.61/23861.30	% SZS status GaveUp for HL410761+5.p
180597.61/23861.30	eprover: CPU time limit exceeded, terminating
180597.61/23861.30	% SZS status Ended for HL410761+5.p
180600.98/23861.61	% SZS status Started for HL410762+4.p
180600.98/23861.61	% SZS status GaveUp for HL410762+4.p
180600.98/23861.61	eprover: CPU time limit exceeded, terminating
180600.98/23861.61	% SZS status Ended for HL410762+4.p
180603.48/23862.04	% SZS status Started for HL410762+5.p
180603.48/23862.04	% SZS status GaveUp for HL410762+5.p
180603.48/23862.04	eprover: CPU time limit exceeded, terminating
180603.48/23862.04	% SZS status Ended for HL410762+5.p
180605.34/23862.22	% SZS status Started for HL410764+4.p
180605.34/23862.22	% SZS status GaveUp for HL410764+4.p
180605.34/23862.22	eprover: CPU time limit exceeded, terminating
180605.34/23862.22	% SZS status Ended for HL410764+4.p
180611.95/23863.00	% SZS status Started for HL410764+5.p
180611.95/23863.00	% SZS status GaveUp for HL410764+5.p
180611.95/23863.00	eprover: CPU time limit exceeded, terminating
180611.95/23863.00	% SZS status Ended for HL410764+5.p
180616.02/23863.51	% SZS status Started for HL410765+4.p
180616.02/23863.51	% SZS status GaveUp for HL410765+4.p
180616.02/23863.51	eprover: CPU time limit exceeded, terminating
180616.02/23863.51	% SZS status Ended for HL410765+4.p
180617.78/23863.78	% SZS status Started for HL410765+5.p
180617.78/23863.78	% SZS status GaveUp for HL410765+5.p
180617.78/23863.78	eprover: CPU time limit exceeded, terminating
180617.78/23863.78	% SZS status Ended for HL410765+5.p
180619.28/23864.00	% SZS status Started for HL410766+4.p
180619.28/23864.00	% SZS status GaveUp for HL410766+4.p
180619.28/23864.00	eprover: CPU time limit exceeded, terminating
180619.28/23864.00	% SZS status Ended for HL410766+4.p
180622.62/23864.34	% SZS status Started for HL410766+5.p
180622.62/23864.34	% SZS status GaveUp for HL410766+5.p
180622.62/23864.34	eprover: CPU time limit exceeded, terminating
180622.62/23864.34	% SZS status Ended for HL410766+5.p
180624.50/23864.65	% SZS status Started for HL410767+4.p
180624.50/23864.65	% SZS status GaveUp for HL410767+4.p
180624.50/23864.65	eprover: CPU time limit exceeded, terminating
180624.50/23864.65	% SZS status Ended for HL410767+4.p
180629.23/23865.24	% SZS status Started for HL410767+5.p
180629.23/23865.24	% SZS status GaveUp for HL410767+5.p
180629.23/23865.24	eprover: CPU time limit exceeded, terminating
180629.23/23865.24	% SZS status Ended for HL410767+5.p
180630.03/23865.26	% SZS status Started for HL410768+4.p
180630.03/23865.26	% SZS status GaveUp for HL410768+4.p
180630.03/23865.26	eprover: CPU time limit exceeded, terminating
180630.03/23865.26	% SZS status Ended for HL410768+4.p
180635.59/23866.04	% SZS status Started for HL410768+5.p
180635.59/23866.04	% SZS status GaveUp for HL410768+5.p
180635.59/23866.04	eprover: CPU time limit exceeded, terminating
180635.59/23866.04	% SZS status Ended for HL410768+5.p
180640.19/23866.55	% SZS status Started for HL410770+4.p
180640.19/23866.55	% SZS status GaveUp for HL410770+4.p
180640.19/23866.55	eprover: CPU time limit exceeded, terminating
180640.19/23866.55	% SZS status Ended for HL410770+4.p
180642.34/23866.82	% SZS status Started for HL410770+5.p
180642.34/23866.82	% SZS status GaveUp for HL410770+5.p
180642.34/23866.82	eprover: CPU time limit exceeded, terminating
180642.34/23866.82	% SZS status Ended for HL410770+5.p
180643.69/23867.04	% SZS status Started for HL410771+4.p
180643.69/23867.04	% SZS status GaveUp for HL410771+4.p
180643.69/23867.04	eprover: CPU time limit exceeded, terminating
180643.69/23867.04	% SZS status Ended for HL410771+4.p
180646.28/23867.37	% SZS status Started for HL410771+5.p
180646.28/23867.37	% SZS status GaveUp for HL410771+5.p
180646.28/23867.37	eprover: CPU time limit exceeded, terminating
180646.28/23867.37	% SZS status Ended for HL410771+5.p
180649.83/23867.81	% SZS status Started for HL410772+4.p
180649.83/23867.81	% SZS status GaveUp for HL410772+4.p
180649.83/23867.81	eprover: CPU time limit exceeded, terminating
180649.83/23867.81	% SZS status Ended for HL410772+4.p
180653.41/23868.27	% SZS status Started for HL410772+5.p
180653.41/23868.27	% SZS status GaveUp for HL410772+5.p
180653.41/23868.27	eprover: CPU time limit exceeded, terminating
180653.41/23868.27	% SZS status Ended for HL410772+5.p
180654.11/23868.30	% SZS status Started for HL410773+4.p
180654.11/23868.30	% SZS status GaveUp for HL410773+4.p
180654.11/23868.30	eprover: CPU time limit exceeded, terminating
180654.11/23868.30	% SZS status Ended for HL410773+4.p
180660.11/23869.07	% SZS status Started for HL410773+5.p
180660.11/23869.07	% SZS status GaveUp for HL410773+5.p
180660.11/23869.07	eprover: CPU time limit exceeded, terminating
180660.11/23869.07	% SZS status Ended for HL410773+5.p
180664.23/23869.58	% SZS status Started for HL410774+4.p
180664.23/23869.58	% SZS status GaveUp for HL410774+4.p
180664.23/23869.58	eprover: CPU time limit exceeded, terminating
180664.23/23869.58	% SZS status Ended for HL410774+4.p
180665.95/23869.86	% SZS status Started for HL410774+5.p
180665.95/23869.86	% SZS status GaveUp for HL410774+5.p
180665.95/23869.86	eprover: CPU time limit exceeded, terminating
180665.95/23869.86	% SZS status Ended for HL410774+5.p
180667.75/23870.07	% SZS status Started for HL410775+4.p
180667.75/23870.07	% SZS status GaveUp for HL410775+4.p
180667.75/23870.07	eprover: CPU time limit exceeded, terminating
180667.75/23870.07	% SZS status Ended for HL410775+4.p
180670.94/23870.42	% SZS status Started for HL410775+5.p
180670.94/23870.42	% SZS status GaveUp for HL410775+5.p
180670.94/23870.42	eprover: CPU time limit exceeded, terminating
180670.94/23870.42	% SZS status Ended for HL410775+5.p
180673.84/23870.87	% SZS status Started for HL410776+4.p
180673.84/23870.87	% SZS status GaveUp for HL410776+4.p
180673.84/23870.87	eprover: CPU time limit exceeded, terminating
180673.84/23870.87	% SZS status Ended for HL410776+4.p
180678.02/23871.31	% SZS status Started for HL410776+5.p
180678.02/23871.31	% SZS status GaveUp for HL410776+5.p
180678.02/23871.31	eprover: CPU time limit exceeded, terminating
180678.02/23871.31	% SZS status Ended for HL410776+5.p
180678.70/23871.41	% SZS status Started for HL410777+4.p
180678.70/23871.41	% SZS status GaveUp for HL410777+4.p
180678.70/23871.41	eprover: CPU time limit exceeded, terminating
180678.70/23871.41	% SZS status Ended for HL410777+4.p
180684.33/23872.11	% SZS status Started for HL410777+5.p
180684.33/23872.11	% SZS status GaveUp for HL410777+5.p
180684.33/23872.11	eprover: CPU time limit exceeded, terminating
180684.33/23872.11	% SZS status Ended for HL410777+5.p
180687.98/23872.62	% SZS status Started for HL410778+4.p
180687.98/23872.62	% SZS status GaveUp for HL410778+4.p
180687.98/23872.62	eprover: CPU time limit exceeded, terminating
180687.98/23872.62	% SZS status Ended for HL410778+4.p
180690.17/23872.91	% SZS status Started for HL410778+5.p
180690.17/23872.91	% SZS status GaveUp for HL410778+5.p
180690.17/23872.91	eprover: CPU time limit exceeded, terminating
180690.17/23872.91	% SZS status Ended for HL410778+5.p
180693.55/23873.25	% SZS status Started for HL410779+4.p
180693.55/23873.25	% SZS status GaveUp for HL410779+4.p
180693.55/23873.25	eprover: CPU time limit exceeded, terminating
180693.55/23873.25	% SZS status Ended for HL410779+4.p
180694.97/23873.46	% SZS status Started for HL410779+5.p
180694.97/23873.46	% SZS status GaveUp for HL410779+5.p
180694.97/23873.46	eprover: CPU time limit exceeded, terminating
180694.97/23873.46	% SZS status Ended for HL410779+5.p
180698.53/23873.91	% SZS status Started for HL410780+4.p
180698.53/23873.91	% SZS status GaveUp for HL410780+4.p
180698.53/23873.91	eprover: CPU time limit exceeded, terminating
180698.53/23873.91	% SZS status Ended for HL410780+4.p
180701.69/23874.35	% SZS status Started for HL410780+5.p
180701.69/23874.35	% SZS status GaveUp for HL410780+5.p
180701.69/23874.35	eprover: CPU time limit exceeded, terminating
180701.69/23874.35	% SZS status Ended for HL410780+5.p
180702.62/23874.44	% SZS status Started for HL410782+4.p
180702.62/23874.44	% SZS status GaveUp for HL410782+4.p
180702.62/23874.44	eprover: CPU time limit exceeded, terminating
180702.62/23874.44	% SZS status Ended for HL410782+4.p
180708.33/23875.14	% SZS status Started for HL410782+5.p
180708.33/23875.14	% SZS status GaveUp for HL410782+5.p
180708.33/23875.14	eprover: CPU time limit exceeded, terminating
180708.33/23875.14	% SZS status Ended for HL410782+5.p
180712.39/23875.67	% SZS status Started for HL410785+4.p
180712.39/23875.67	% SZS status GaveUp for HL410785+4.p
180712.39/23875.67	eprover: CPU time limit exceeded, terminating
180712.39/23875.67	% SZS status Ended for HL410785+4.p
180714.52/23875.95	% SZS status Started for HL410785+5.p
180714.52/23875.95	% SZS status GaveUp for HL410785+5.p
180714.52/23875.95	eprover: CPU time limit exceeded, terminating
180714.52/23875.95	% SZS status Ended for HL410785+5.p
180718.33/23876.42	% SZS status Started for HL410786+4.p
180718.33/23876.42	% SZS status GaveUp for HL410786+4.p
180718.33/23876.42	eprover: CPU time limit exceeded, terminating
180718.33/23876.42	% SZS status Ended for HL410786+4.p
180719.27/23876.50	% SZS status Started for HL410786+5.p
180719.27/23876.50	% SZS status GaveUp for HL410786+5.p
180719.27/23876.50	eprover: CPU time limit exceeded, terminating
180719.27/23876.50	% SZS status Ended for HL410786+5.p
180722.19/23876.94	% SZS status Started for HL410787+4.p
180722.19/23876.94	% SZS status GaveUp for HL410787+4.p
180722.19/23876.94	eprover: CPU time limit exceeded, terminating
180722.19/23876.94	% SZS status Ended for HL410787+4.p
180726.31/23877.39	% SZS status Started for HL410787+5.p
180726.31/23877.39	% SZS status GaveUp for HL410787+5.p
180726.31/23877.39	eprover: CPU time limit exceeded, terminating
180726.31/23877.39	% SZS status Ended for HL410787+5.p
180726.94/23877.49	% SZS status Started for HL410788+4.p
180726.94/23877.49	% SZS status GaveUp for HL410788+4.p
180726.94/23877.49	eprover: CPU time limit exceeded, terminating
180726.94/23877.49	% SZS status Ended for HL410788+4.p
180732.30/23878.18	% SZS status Started for HL410788+5.p
180732.30/23878.18	% SZS status GaveUp for HL410788+5.p
180732.30/23878.18	eprover: CPU time limit exceeded, terminating
180732.30/23878.18	% SZS status Ended for HL410788+5.p
180736.84/23878.71	% SZS status Started for HL410789+4.p
180736.84/23878.71	% SZS status GaveUp for HL410789+4.p
180736.84/23878.71	eprover: CPU time limit exceeded, terminating
180736.84/23878.71	% SZS status Ended for HL410789+4.p
180738.31/23878.99	% SZS status Started for HL410789+5.p
180738.31/23878.99	% SZS status GaveUp for HL410789+5.p
180738.31/23878.99	eprover: CPU time limit exceeded, terminating
180738.31/23878.99	% SZS status Ended for HL410789+5.p
180742.38/23879.46	% SZS status Started for HL410790+4.p
180742.38/23879.46	% SZS status GaveUp for HL410790+4.p
180742.38/23879.46	eprover: CPU time limit exceeded, terminating
180742.38/23879.46	% SZS status Ended for HL410790+4.p
180743.05/23879.57	% SZS status Started for HL410790+5.p
180743.05/23879.57	% SZS status GaveUp for HL410790+5.p
180743.05/23879.57	eprover: CPU time limit exceeded, terminating
180743.05/23879.57	% SZS status Ended for HL410790+5.p
180746.83/23880.00	% SZS status Started for HL410791+4.p
180746.83/23880.00	% SZS status GaveUp for HL410791+4.p
180746.83/23880.00	eprover: CPU time limit exceeded, terminating
180746.83/23880.00	% SZS status Ended for HL410791+4.p
180749.78/23880.44	% SZS status Started for HL410791+5.p
180749.78/23880.44	% SZS status GaveUp for HL410791+5.p
180749.78/23880.44	eprover: CPU time limit exceeded, terminating
180749.78/23880.44	% SZS status Ended for HL410791+5.p
180752.22/23880.66	% SZS status Started for HL410792+4.p
180752.22/23880.66	% SZS status GaveUp for HL410792+4.p
180752.22/23880.66	eprover: CPU time limit exceeded, terminating
180752.22/23880.66	% SZS status Ended for HL410792+4.p
180756.45/23881.22	% SZS status Started for HL410792+5.p
180756.45/23881.22	% SZS status GaveUp for HL410792+5.p
180756.45/23881.22	eprover: CPU time limit exceeded, terminating
180756.45/23881.22	% SZS status Ended for HL410792+5.p
180760.97/23881.74	% SZS status Started for HL410793+4.p
180760.97/23881.74	% SZS status GaveUp for HL410793+4.p
180760.97/23881.74	eprover: CPU time limit exceeded, terminating
180760.97/23881.74	% SZS status Ended for HL410793+4.p
180762.88/23882.03	% SZS status Started for HL410793+5.p
180762.88/23882.03	% SZS status GaveUp for HL410793+5.p
180762.88/23882.03	eprover: CPU time limit exceeded, terminating
180762.88/23882.03	% SZS status Ended for HL410793+5.p
180766.33/23882.49	% SZS status Started for HL410795+4.p
180766.33/23882.49	% SZS status GaveUp for HL410795+4.p
180766.33/23882.49	eprover: CPU time limit exceeded, terminating
180766.33/23882.49	% SZS status Ended for HL410795+4.p
180767.69/23882.62	% SZS status Started for HL410795+5.p
180767.69/23882.62	% SZS status GaveUp for HL410795+5.p
180767.69/23882.62	eprover: CPU time limit exceeded, terminating
180767.69/23882.62	% SZS status Ended for HL410795+5.p
180771.17/23883.04	% SZS status Started for HL410796+4.p
180771.17/23883.04	% SZS status GaveUp for HL410796+4.p
180771.17/23883.04	eprover: CPU time limit exceeded, terminating
180771.17/23883.04	% SZS status Ended for HL410796+4.p
180774.41/23883.48	% SZS status Started for HL410796+5.p
180774.41/23883.48	% SZS status GaveUp for HL410796+5.p
180774.41/23883.48	eprover: CPU time limit exceeded, terminating
180774.41/23883.48	% SZS status Ended for HL410796+5.p
180777.38/23883.84	% SZS status Started for HL410797+4.p
180777.38/23883.84	% SZS status GaveUp for HL410797+4.p
180777.38/23883.84	eprover: CPU time limit exceeded, terminating
180777.38/23883.84	% SZS status Ended for HL410797+4.p
180780.27/23884.25	% SZS status Started for HL410797+5.p
180780.27/23884.25	% SZS status GaveUp for HL410797+5.p
180780.27/23884.25	eprover: CPU time limit exceeded, terminating
180780.27/23884.25	% SZS status Ended for HL410797+5.p
180784.98/23884.78	% SZS status Started for HL410799+4.p
180784.98/23884.78	% SZS status GaveUp for HL410799+4.p
180784.98/23884.78	eprover: CPU time limit exceeded, terminating
180784.98/23884.78	% SZS status Ended for HL410799+4.p
180787.02/23885.07	% SZS status Started for HL410799+5.p
180787.02/23885.07	% SZS status GaveUp for HL410799+5.p
180787.02/23885.07	eprover: CPU time limit exceeded, terminating
180787.02/23885.07	% SZS status Ended for HL410799+5.p
180791.06/23885.53	% SZS status Started for HL410800+4.p
180791.06/23885.53	% SZS status GaveUp for HL410800+4.p
180791.06/23885.53	eprover: CPU time limit exceeded, terminating
180791.06/23885.53	% SZS status Ended for HL410800+4.p
180791.72/23885.66	% SZS status Started for HL410800+5.p
180791.72/23885.66	% SZS status GaveUp for HL410800+5.p
180791.72/23885.66	eprover: CPU time limit exceeded, terminating
180791.72/23885.66	% SZS status Ended for HL410800+5.p
180794.84/23886.07	% SZS status Started for HL410802+4.p
180794.84/23886.07	% SZS status GaveUp for HL410802+4.p
180794.84/23886.07	eprover: CPU time limit exceeded, terminating
180794.84/23886.07	% SZS status Ended for HL410802+4.p
180798.31/23886.53	% SZS status Started for HL410802+5.p
180798.31/23886.53	% SZS status GaveUp for HL410802+5.p
180798.31/23886.53	eprover: CPU time limit exceeded, terminating
180798.31/23886.53	% SZS status Ended for HL410802+5.p
180801.48/23886.97	% SZS status Started for HL410803+4.p
180801.48/23886.97	% SZS status GaveUp for HL410803+4.p
180801.48/23886.97	eprover: CPU time limit exceeded, terminating
180801.48/23886.97	% SZS status Ended for HL410803+4.p
180804.23/23887.29	% SZS status Started for HL410803+5.p
180804.23/23887.29	% SZS status GaveUp for HL410803+5.p
180804.23/23887.29	eprover: CPU time limit exceeded, terminating
180804.23/23887.29	% SZS status Ended for HL410803+5.p
180807.97/23887.82	% SZS status Started for HL410805+4.p
180807.97/23887.82	% SZS status GaveUp for HL410805+4.p
180807.97/23887.82	eprover: CPU time limit exceeded, terminating
180807.97/23887.82	% SZS status Ended for HL410805+4.p
180810.88/23888.11	% SZS status Started for HL410805+5.p
180810.88/23888.11	% SZS status GaveUp for HL410805+5.p
180810.88/23888.11	eprover: CPU time limit exceeded, terminating
180810.88/23888.11	% SZS status Ended for HL410805+5.p
180814.69/23888.56	% SZS status Started for HL410808+4.p
180814.69/23888.56	% SZS status GaveUp for HL410808+4.p
180814.69/23888.56	eprover: CPU time limit exceeded, terminating
180814.69/23888.56	% SZS status Ended for HL410808+4.p
180817.16/23888.97	% SZS status Started for HL410808+5.p
180817.16/23888.97	% SZS status GaveUp for HL410808+5.p
180817.16/23888.97	eprover: CPU time limit exceeded, terminating
180817.16/23888.97	% SZS status Ended for HL410808+5.p
180818.98/23889.13	% SZS status Started for HL410809+4.p
180818.98/23889.13	% SZS status GaveUp for HL410809+4.p
180818.98/23889.13	eprover: CPU time limit exceeded, terminating
180818.98/23889.13	% SZS status Ended for HL410809+4.p
180824.53/23889.85	% SZS status Started for HL410809+5.p
180824.53/23889.85	% SZS status GaveUp for HL410809+5.p
180824.53/23889.85	eprover: CPU time limit exceeded, terminating
180824.53/23889.85	% SZS status Ended for HL410809+5.p
180826.09/23890.05	% SZS status Started for HL410812+4.p
180826.09/23890.05	% SZS status GaveUp for HL410812+4.p
180826.09/23890.05	eprover: CPU time limit exceeded, terminating
180826.09/23890.05	% SZS status Ended for HL410812+4.p
180828.48/23890.34	% SZS status Started for HL410812+5.p
180828.48/23890.34	% SZS status GaveUp for HL410812+5.p
180828.48/23890.34	eprover: CPU time limit exceeded, terminating
180828.48/23890.34	% SZS status Ended for HL410812+5.p
180832.66/23890.87	% SZS status Started for HL410813+4.p
180832.66/23890.87	% SZS status GaveUp for HL410813+4.p
180832.66/23890.87	eprover: CPU time limit exceeded, terminating
180832.66/23890.87	% SZS status Ended for HL410813+4.p
180834.81/23891.18	% SZS status Started for HL410813+5.p
180834.81/23891.18	% SZS status GaveUp for HL410813+5.p
180834.81/23891.18	eprover: CPU time limit exceeded, terminating
180834.81/23891.18	% SZS status Ended for HL410813+5.p
180838.59/23891.62	% SZS status Started for HL410814+4.p
180838.59/23891.62	% SZS status GaveUp for HL410814+4.p
180838.59/23891.62	eprover: CPU time limit exceeded, terminating
180838.59/23891.62	% SZS status Ended for HL410814+4.p
180841.92/23892.01	% SZS status Started for HL410814+5.p
180841.92/23892.01	% SZS status GaveUp for HL410814+5.p
180841.92/23892.01	eprover: CPU time limit exceeded, terminating
180841.92/23892.01	% SZS status Ended for HL410814+5.p
180843.05/23892.16	% SZS status Started for HL410815+4.p
180843.05/23892.16	% SZS status GaveUp for HL410815+4.p
180843.05/23892.16	eprover: CPU time limit exceeded, terminating
180843.05/23892.16	% SZS status Ended for HL410815+4.p
180848.84/23892.89	% SZS status Started for HL410815+5.p
180848.84/23892.89	% SZS status GaveUp for HL410815+5.p
180848.84/23892.89	eprover: CPU time limit exceeded, terminating
180848.84/23892.89	% SZS status Ended for HL410815+5.p
180850.03/23893.11	% SZS status Started for HL410816+4.p
180850.03/23893.11	% SZS status GaveUp for HL410816+4.p
180850.03/23893.11	eprover: CPU time limit exceeded, terminating
180850.03/23893.11	% SZS status Ended for HL410816+4.p
180852.70/23893.41	% SZS status Started for HL410816+5.p
180852.70/23893.41	% SZS status GaveUp for HL410816+5.p
180852.70/23893.41	eprover: CPU time limit exceeded, terminating
180852.70/23893.41	% SZS status Ended for HL410816+5.p
180857.02/23893.91	% SZS status Started for HL410818+4.p
180857.02/23893.91	% SZS status GaveUp for HL410818+4.p
180857.02/23893.91	eprover: CPU time limit exceeded, terminating
180857.02/23893.91	% SZS status Ended for HL410818+4.p
180859.16/23894.24	% SZS status Started for HL410818+5.p
180859.16/23894.24	% SZS status GaveUp for HL410818+5.p
180859.16/23894.24	eprover: CPU time limit exceeded, terminating
180859.16/23894.24	% SZS status Ended for HL410818+5.p
180863.89/23894.77	% SZS status Started for HL410819+4.p
180863.89/23894.77	% SZS status GaveUp for HL410819+4.p
180863.89/23894.77	eprover: CPU time limit exceeded, terminating
180863.89/23894.77	% SZS status Ended for HL410819+4.p
180866.06/23895.05	% SZS status Started for HL410819+5.p
180866.06/23895.05	% SZS status GaveUp for HL410819+5.p
180866.06/23895.05	eprover: CPU time limit exceeded, terminating
180866.06/23895.05	% SZS status Ended for HL410819+5.p
180866.92/23895.20	% SZS status Started for HL410820+4.p
180866.92/23895.20	% SZS status GaveUp for HL410820+4.p
180866.92/23895.20	eprover: CPU time limit exceeded, terminating
180866.92/23895.20	% SZS status Ended for HL410820+4.p
180873.06/23895.93	% SZS status Started for HL410820+5.p
180873.06/23895.93	% SZS status GaveUp for HL410820+5.p
180873.06/23895.93	eprover: CPU time limit exceeded, terminating
180873.06/23895.93	% SZS status Ended for HL410820+5.p
180875.50/23896.26	% SZS status Started for HL410821+4.p
180875.50/23896.26	% SZS status GaveUp for HL410821+4.p
180875.50/23896.26	eprover: CPU time limit exceeded, terminating
180875.50/23896.26	% SZS status Ended for HL410821+4.p
180877.09/23896.46	% SZS status Started for HL410821+5.p
180877.09/23896.46	% SZS status GaveUp for HL410821+5.p
180877.09/23896.46	eprover: CPU time limit exceeded, terminating
180877.09/23896.46	% SZS status Ended for HL410821+5.p
180880.86/23896.94	% SZS status Started for HL410822+4.p
180880.86/23896.94	% SZS status GaveUp for HL410822+4.p
180880.86/23896.94	eprover: CPU time limit exceeded, terminating
180880.86/23896.94	% SZS status Ended for HL410822+4.p
180883.34/23897.29	% SZS status Started for HL410822+5.p
180883.34/23897.29	% SZS status GaveUp for HL410822+5.p
180883.34/23897.29	eprover: CPU time limit exceeded, terminating
180883.34/23897.29	% SZS status Ended for HL410822+5.p
180887.50/23897.80	% SZS status Started for HL410823+4.p
180887.50/23897.80	% SZS status GaveUp for HL410823+4.p
180887.50/23897.80	eprover: CPU time limit exceeded, terminating
180887.50/23897.80	% SZS status Ended for HL410823+4.p
180890.20/23898.09	% SZS status Started for HL410823+5.p
180890.20/23898.09	% SZS status GaveUp for HL410823+5.p
180890.20/23898.09	eprover: CPU time limit exceeded, terminating
180890.20/23898.09	% SZS status Ended for HL410823+5.p
180891.33/23898.24	% SZS status Started for HL410825+4.p
180891.33/23898.24	% SZS status GaveUp for HL410825+4.p
180891.33/23898.24	eprover: CPU time limit exceeded, terminating
180891.33/23898.24	% SZS status Ended for HL410825+4.p
180897.34/23898.97	% SZS status Started for HL410825+5.p
180897.34/23898.97	% SZS status GaveUp for HL410825+5.p
180897.34/23898.97	eprover: CPU time limit exceeded, terminating
180897.34/23898.97	% SZS status Ended for HL410825+5.p
180899.50/23899.30	% SZS status Started for HL410827+4.p
180899.50/23899.30	% SZS status GaveUp for HL410827+4.p
180899.50/23899.30	eprover: CPU time limit exceeded, terminating
180899.50/23899.30	% SZS status Ended for HL410827+4.p
180902.89/23899.67	% SZS status Started for HL410827+5.p
180902.89/23899.67	% SZS status GaveUp for HL410827+5.p
180902.89/23899.67	eprover: CPU time limit exceeded, terminating
180902.89/23899.67	% SZS status Ended for HL410827+5.p
180905.03/23899.98	% SZS status Started for HL410829+4.p
180905.03/23899.98	% SZS status GaveUp for HL410829+4.p
180905.03/23899.98	eprover: CPU time limit exceeded, terminating
180905.03/23899.98	% SZS status Ended for HL410829+4.p
180908.05/23900.32	% SZS status Started for HL410829+5.p
180908.05/23900.32	% SZS status GaveUp for HL410829+5.p
180908.05/23900.32	eprover: CPU time limit exceeded, terminating
180908.05/23900.32	% SZS status Ended for HL410829+5.p
180911.80/23900.84	% SZS status Started for HL410830+4.p
180911.80/23900.84	% SZS status GaveUp for HL410830+4.p
180911.80/23900.84	eprover: CPU time limit exceeded, terminating
180911.80/23900.84	% SZS status Ended for HL410830+4.p
180913.98/23901.13	% SZS status Started for HL410830+5.p
180913.98/23901.13	% SZS status GaveUp for HL410830+5.p
180913.98/23901.13	eprover: CPU time limit exceeded, terminating
180913.98/23901.13	% SZS status Ended for HL410830+5.p
180915.25/23901.28	% SZS status Started for HL410832+4.p
180915.25/23901.28	% SZS status GaveUp for HL410832+4.p
180915.25/23901.28	eprover: CPU time limit exceeded, terminating
180915.25/23901.28	% SZS status Ended for HL410832+4.p
180921.02/23902.01	% SZS status Started for HL410832+5.p
180921.02/23902.01	% SZS status GaveUp for HL410832+5.p
180921.02/23902.01	eprover: CPU time limit exceeded, terminating
180921.02/23902.01	% SZS status Ended for HL410832+5.p
180923.70/23902.35	% SZS status Started for HL410833+4.p
180923.70/23902.35	% SZS status GaveUp for HL410833+4.p
180923.70/23902.35	eprover: CPU time limit exceeded, terminating
180923.70/23902.35	% SZS status Ended for HL410833+4.p
180926.91/23902.71	% SZS status Started for HL410833+5.p
180926.91/23902.71	% SZS status GaveUp for HL410833+5.p
180926.91/23902.71	eprover: CPU time limit exceeded, terminating
180926.91/23902.71	% SZS status Ended for HL410833+5.p
180929.77/23903.12	% SZS status Started for HL410835+4.p
180929.77/23903.12	% SZS status GaveUp for HL410835+4.p
180929.77/23903.12	eprover: CPU time limit exceeded, terminating
180929.77/23903.12	% SZS status Ended for HL410835+4.p
180932.09/23903.36	% SZS status Started for HL410835+5.p
180932.09/23903.36	% SZS status GaveUp for HL410835+5.p
180932.09/23903.36	eprover: CPU time limit exceeded, terminating
180932.09/23903.36	% SZS status Ended for HL410835+5.p
180936.25/23903.87	% SZS status Started for HL410838+4.p
180936.25/23903.87	% SZS status GaveUp for HL410838+4.p
180936.25/23903.87	eprover: CPU time limit exceeded, terminating
180936.25/23903.87	% SZS status Ended for HL410838+4.p
180938.36/23904.17	% SZS status Started for HL410838+5.p
180938.36/23904.17	% SZS status GaveUp for HL410838+5.p
180938.36/23904.17	eprover: CPU time limit exceeded, terminating
180938.36/23904.17	% SZS status Ended for HL410838+5.p
180938.77/23904.31	% SZS status Started for HL410839+4.p
180938.77/23904.31	% SZS status GaveUp for HL410839+4.p
180938.77/23904.31	eprover: CPU time limit exceeded, terminating
180938.77/23904.31	% SZS status Ended for HL410839+4.p
180945.33/23905.04	% SZS status Started for HL410839+5.p
180945.33/23905.04	% SZS status GaveUp for HL410839+5.p
180945.33/23905.04	eprover: CPU time limit exceeded, terminating
180945.33/23905.04	% SZS status Ended for HL410839+5.p
180949.55/23905.56	% SZS status Started for HL410840+4.p
180949.55/23905.56	% SZS status GaveUp for HL410840+4.p
180949.55/23905.56	eprover: CPU time limit exceeded, terminating
180949.55/23905.56	% SZS status Ended for HL410840+4.p
180951.00/23905.75	% SZS status Started for HL410840+5.p
180951.00/23905.75	% SZS status GaveUp for HL410840+5.p
180951.00/23905.75	eprover: CPU time limit exceeded, terminating
180951.00/23905.75	% SZS status Ended for HL410840+5.p
180953.97/23906.15	% SZS status Started for HL410841+4.p
180953.97/23906.15	% SZS status GaveUp for HL410841+4.p
180953.97/23906.15	eprover: CPU time limit exceeded, terminating
180953.97/23906.15	% SZS status Ended for HL410841+4.p
180955.78/23906.40	% SZS status Started for HL410841+5.p
180955.78/23906.40	% SZS status GaveUp for HL410841+5.p
180955.78/23906.40	eprover: CPU time limit exceeded, terminating
180955.78/23906.40	% SZS status Ended for HL410841+5.p
180960.06/23906.92	% SZS status Started for HL410842+4.p
180960.06/23906.92	% SZS status GaveUp for HL410842+4.p
180960.06/23906.92	eprover: CPU time limit exceeded, terminating
180960.06/23906.92	% SZS status Ended for HL410842+4.p
180962.61/23907.21	% SZS status Started for HL410842+5.p
180962.61/23907.21	% SZS status GaveUp for HL410842+5.p
180962.61/23907.21	eprover: CPU time limit exceeded, terminating
180962.61/23907.21	% SZS status Ended for HL410842+5.p
180963.67/23907.35	% SZS status Started for HL410843+4.p
180963.67/23907.35	% SZS status GaveUp for HL410843+4.p
180963.67/23907.35	eprover: CPU time limit exceeded, terminating
180963.67/23907.35	% SZS status Ended for HL410843+4.p
180970.64/23908.20	% SZS status Started for HL410843+5.p
180970.64/23908.20	% SZS status GaveUp for HL410843+5.p
180970.64/23908.20	eprover: CPU time limit exceeded, terminating
180970.64/23908.20	% SZS status Ended for HL410843+5.p
180973.53/23908.61	% SZS status Started for HL410844+4.p
180973.53/23908.61	% SZS status GaveUp for HL410844+4.p
180973.53/23908.61	eprover: CPU time limit exceeded, terminating
180973.53/23908.61	% SZS status Ended for HL410844+4.p
180974.66/23908.79	% SZS status Started for HL410844+5.p
180974.66/23908.79	% SZS status GaveUp for HL410844+5.p
180974.66/23908.79	eprover: CPU time limit exceeded, terminating
180974.66/23908.79	% SZS status Ended for HL410844+5.p
180978.48/23909.19	% SZS status Started for HL410845+4.p
180978.48/23909.19	% SZS status GaveUp for HL410845+4.p
180978.48/23909.19	eprover: CPU time limit exceeded, terminating
180978.48/23909.19	% SZS status Ended for HL410845+4.p
180979.70/23909.44	% SZS status Started for HL410845+5.p
180979.70/23909.44	% SZS status GaveUp for HL410845+5.p
180979.70/23909.44	eprover: CPU time limit exceeded, terminating
180979.70/23909.44	% SZS status Ended for HL410845+5.p
180984.11/23909.96	% SZS status Started for HL410846+4.p
180984.11/23909.96	% SZS status GaveUp for HL410846+4.p
180984.11/23909.96	eprover: CPU time limit exceeded, terminating
180984.11/23909.96	% SZS status Ended for HL410846+4.p
180986.83/23910.24	% SZS status Started for HL410846+5.p
180986.83/23910.24	% SZS status GaveUp for HL410846+5.p
180986.83/23910.24	eprover: CPU time limit exceeded, terminating
180986.83/23910.24	% SZS status Ended for HL410846+5.p
180987.70/23910.39	% SZS status Started for HL410847+4.p
180987.70/23910.39	% SZS status GaveUp for HL410847+4.p
180987.70/23910.39	eprover: CPU time limit exceeded, terminating
180987.70/23910.39	% SZS status Ended for HL410847+4.p
180998.02/23911.66	% SZS status Started for HL410848+4.p
180998.02/23911.66	% SZS status GaveUp for HL410848+4.p
180998.02/23911.66	eprover: CPU time limit exceeded, terminating
180998.02/23911.66	% SZS status Ended for HL410848+4.p
181001.03/23912.23	% SZS status Started for HL410849+4.p
181001.03/23912.23	% SZS status GaveUp for HL410849+4.p
181001.03/23912.23	eprover: CPU time limit exceeded, terminating
181001.03/23912.23	% SZS status Ended for HL410849+4.p
181008.42/23912.99	% SZS status Started for HL410851+4.p
181008.42/23912.99	% SZS status GaveUp for HL410851+4.p
181008.42/23912.99	eprover: CPU time limit exceeded, terminating
181008.42/23912.99	% SZS status Ended for HL410851+4.p
181010.97/23913.42	% SZS status Started for HL410854+4.p
181010.97/23913.42	% SZS status GaveUp for HL410854+4.p
181010.97/23913.42	eprover: CPU time limit exceeded, terminating
181010.97/23913.42	% SZS status Ended for HL410854+4.p
181026.56/23915.26	% SZS status Started for HL410856+4.p
181026.56/23915.26	% SZS status GaveUp for HL410856+4.p
181026.56/23915.26	eprover: CPU time limit exceeded, terminating
181026.56/23915.26	% SZS status Ended for HL410856+4.p
181035.52/23916.45	% SZS status Started for HL410857+4.p
181035.52/23916.45	% SZS status GaveUp for HL410857+4.p
181035.52/23916.45	eprover: CPU time limit exceeded, terminating
181035.52/23916.45	% SZS status Ended for HL410857+4.p
181060.05/23919.47	% SZS status Started for HL410847+5.p
181060.05/23919.47	% SZS status GaveUp for HL410847+5.p
181060.05/23919.47	eprover: CPU time limit exceeded, terminating
181060.05/23919.47	% SZS status Ended for HL410847+5.p
181060.05/23919.49	% SZS status Started for HL410858+4.p
181060.05/23919.49	% SZS status GaveUp for HL410858+4.p
181060.05/23919.49	eprover: CPU time limit exceeded, terminating
181060.05/23919.49	% SZS status Ended for HL410858+4.p
181061.84/23919.77	% SZS status Started for HL410848+5.p
181061.84/23919.77	% SZS status GaveUp for HL410848+5.p
181061.84/23919.77	eprover: CPU time limit exceeded, terminating
181061.84/23919.77	% SZS status Ended for HL410848+5.p
181065.67/23920.17	% SZS status Started for HL410849+5.p
181065.67/23920.17	% SZS status GaveUp for HL410849+5.p
181065.67/23920.17	eprover: CPU time limit exceeded, terminating
181065.67/23920.17	% SZS status Ended for HL410849+5.p
181070.53/23920.83	% SZS status Started for HL410851+5.p
181070.53/23920.83	% SZS status GaveUp for HL410851+5.p
181070.53/23920.83	eprover: CPU time limit exceeded, terminating
181070.53/23920.83	% SZS status Ended for HL410851+5.p
181081.55/23922.19	% SZS status Started for HL410854+5.p
181081.55/23922.19	% SZS status GaveUp for HL410854+5.p
181081.55/23922.19	eprover: CPU time limit exceeded, terminating
181081.55/23922.19	% SZS status Ended for HL410854+5.p
181084.06/23922.54	% SZS status Started for HL410859+4.p
181084.06/23922.54	% SZS status GaveUp for HL410859+4.p
181084.06/23922.54	eprover: CPU time limit exceeded, terminating
181084.06/23922.54	% SZS status Ended for HL410859+4.p
181089.31/23923.22	% SZS status Started for HL410860+4.p
181089.31/23923.22	% SZS status GaveUp for HL410860+4.p
181089.31/23923.22	eprover: CPU time limit exceeded, terminating
181089.31/23923.22	% SZS status Ended for HL410860+4.p
181093.56/23923.68	% SZS status Started for HL410856+5.p
181093.56/23923.68	% SZS status GaveUp for HL410856+5.p
181093.56/23923.68	eprover: CPU time limit exceeded, terminating
181093.56/23923.68	% SZS status Ended for HL410856+5.p
181105.94/23925.22	% SZS status Started for HL410862+4.p
181105.94/23925.22	% SZS status GaveUp for HL410862+4.p
181105.94/23925.22	eprover: CPU time limit exceeded, terminating
181105.94/23925.22	% SZS status Ended for HL410862+4.p
181111.12/23925.91	% SZS status Started for HL410857+5.p
181111.12/23925.91	% SZS status GaveUp for HL410857+5.p
181111.12/23925.91	eprover: CPU time limit exceeded, terminating
181111.12/23925.91	% SZS status Ended for HL410857+5.p
181112.72/23926.26	% SZS status Started for HL410863+4.p
181112.72/23926.26	% SZS status GaveUp for HL410863+4.p
181112.72/23926.26	eprover: CPU time limit exceeded, terminating
181112.72/23926.26	% SZS status Ended for HL410863+4.p
181129.86/23928.26	% SZS status Started for HL410865+4.p
181129.86/23928.26	% SZS status GaveUp for HL410865+4.p
181129.86/23928.26	eprover: CPU time limit exceeded, terminating
181129.86/23928.26	% SZS status Ended for HL410865+4.p
181134.80/23928.94	% SZS status Started for HL410865+5.p
181134.80/23928.94	% SZS status GaveUp for HL410865+5.p
181134.80/23928.94	eprover: CPU time limit exceeded, terminating
181134.80/23928.94	% SZS status Ended for HL410865+5.p
181138.72/23929.40	% SZS status Started for HL410866+4.p
181138.72/23929.40	% SZS status GaveUp for HL410866+4.p
181138.72/23929.40	eprover: CPU time limit exceeded, terminating
181138.72/23929.40	% SZS status Ended for HL410866+4.p
181144.09/23930.06	% SZS status Started for HL410858+5.p
181144.09/23930.06	% SZS status GaveUp for HL410858+5.p
181144.09/23930.06	eprover: CPU time limit exceeded, terminating
181144.09/23930.06	% SZS status Ended for HL410858+5.p
181145.47/23930.37	% SZS status Started for HL410859+5.p
181145.47/23930.37	% SZS status GaveUp for HL410859+5.p
181145.47/23930.37	eprover: CPU time limit exceeded, terminating
181145.47/23930.37	% SZS status Ended for HL410859+5.p
181153.59/23931.32	% SZS status Started for HL410866+5.p
181153.59/23931.32	% SZS status GaveUp for HL410866+5.p
181153.59/23931.32	eprover: CPU time limit exceeded, terminating
181153.59/23931.32	% SZS status Ended for HL410866+5.p
181155.45/23931.53	% SZS status Started for HL410860+5.p
181155.45/23931.53	% SZS status GaveUp for HL410860+5.p
181155.45/23931.53	eprover: CPU time limit exceeded, terminating
181155.45/23931.53	% SZS status Ended for HL410860+5.p
181159.94/23932.06	% SZS status Started for HL410867+4.p
181159.94/23932.06	% SZS status GaveUp for HL410867+4.p
181159.94/23932.06	eprover: CPU time limit exceeded, terminating
181159.94/23932.06	% SZS status Ended for HL410867+4.p
181162.55/23932.46	% SZS status Started for HL410867+5.p
181162.55/23932.46	% SZS status GaveUp for HL410867+5.p
181162.55/23932.46	eprover: CPU time limit exceeded, terminating
181162.55/23932.46	% SZS status Ended for HL410867+5.p
181167.70/23933.09	% SZS status Started for HL410870+4.p
181167.70/23933.09	% SZS status GaveUp for HL410870+4.p
181167.70/23933.09	eprover: CPU time limit exceeded, terminating
181167.70/23933.09	% SZS status Ended for HL410870+4.p
181167.70/23933.13	% SZS status Started for HL410862+5.p
181167.70/23933.13	% SZS status GaveUp for HL410862+5.p
181167.70/23933.13	eprover: CPU time limit exceeded, terminating
181167.70/23933.13	% SZS status Ended for HL410862+5.p
181170.98/23933.43	% SZS status Started for HL410870+5.p
181170.98/23933.43	% SZS status GaveUp for HL410870+5.p
181170.98/23933.43	eprover: CPU time limit exceeded, terminating
181170.98/23933.43	% SZS status Ended for HL410870+5.p
181178.14/23934.37	% SZS status Started for HL410872+4.p
181178.14/23934.37	% SZS status GaveUp for HL410872+4.p
181178.14/23934.37	eprover: CPU time limit exceeded, terminating
181178.14/23934.37	% SZS status Ended for HL410872+4.p
181180.41/23934.62	% SZS status Started for HL410872+5.p
181180.41/23934.62	% SZS status GaveUp for HL410872+5.p
181180.41/23934.62	eprover: CPU time limit exceeded, terminating
181180.41/23934.62	% SZS status Ended for HL410872+5.p
181181.33/23934.75	% SZS status Started for HL410863+5.p
181181.33/23934.75	% SZS status GaveUp for HL410863+5.p
181181.33/23934.75	eprover: CPU time limit exceeded, terminating
181181.33/23934.75	% SZS status Ended for HL410863+5.p
181183.20/23935.10	% SZS status Started for HL410875+4.p
181183.20/23935.10	% SZS status GaveUp for HL410875+4.p
181183.20/23935.10	eprover: CPU time limit exceeded, terminating
181183.20/23935.10	% SZS status Ended for HL410875+4.p
181187.23/23935.53	% SZS status Started for HL410875+5.p
181187.23/23935.53	% SZS status GaveUp for HL410875+5.p
181187.23/23935.53	eprover: CPU time limit exceeded, terminating
181187.23/23935.53	% SZS status Ended for HL410875+5.p
181192.45/23936.14	% SZS status Started for HL410876+4.p
181192.45/23936.14	% SZS status GaveUp for HL410876+4.p
181192.45/23936.14	eprover: CPU time limit exceeded, terminating
181192.45/23936.14	% SZS status Ended for HL410876+4.p
181192.69/23936.22	% SZS status Started for HL410876+5.p
181192.69/23936.22	% SZS status GaveUp for HL410876+5.p
181192.69/23936.22	eprover: CPU time limit exceeded, terminating
181192.69/23936.22	% SZS status Ended for HL410876+5.p
181194.92/23936.47	% SZS status Started for HL410878+4.p
181194.92/23936.47	% SZS status GaveUp for HL410878+4.p
181194.92/23936.47	eprover: CPU time limit exceeded, terminating
181194.92/23936.47	% SZS status Ended for HL410878+4.p
181201.92/23937.41	% SZS status Started for HL410878+5.p
181201.92/23937.41	% SZS status GaveUp for HL410878+5.p
181201.92/23937.41	eprover: CPU time limit exceeded, terminating
181201.92/23937.41	% SZS status Ended for HL410878+5.p
181203.81/23937.65	% SZS status Started for HL410879+4.p
181203.81/23937.65	% SZS status GaveUp for HL410879+4.p
181203.81/23937.65	eprover: CPU time limit exceeded, terminating
181203.81/23937.65	% SZS status Ended for HL410879+4.p
181204.91/23937.78	% SZS status Started for HL410879+5.p
181204.91/23937.78	% SZS status GaveUp for HL410879+5.p
181204.91/23937.78	eprover: CPU time limit exceeded, terminating
181204.91/23937.78	% SZS status Ended for HL410879+5.p
181206.73/23938.16	% SZS status Started for HL410880+4.p
181206.73/23938.16	% SZS status GaveUp for HL410880+4.p
181206.73/23938.16	eprover: CPU time limit exceeded, terminating
181206.73/23938.16	% SZS status Ended for HL410880+4.p
181211.11/23938.57	% SZS status Started for HL410880+5.p
181211.11/23938.57	% SZS status GaveUp for HL410880+5.p
181211.11/23938.57	eprover: CPU time limit exceeded, terminating
181211.11/23938.57	% SZS status Ended for HL410880+5.p
181217.70/23939.44	% SZS status Started for HL410881+4.p
181217.70/23939.44	% SZS status GaveUp for HL410881+4.p
181217.70/23939.44	eprover: CPU time limit exceeded, terminating
181217.70/23939.44	% SZS status Ended for HL410881+4.p
181218.42/23939.50	% SZS status Started for HL410882+4.p
181218.42/23939.50	% SZS status GaveUp for HL410882+4.p
181218.42/23939.50	eprover: CPU time limit exceeded, terminating
181218.42/23939.50	% SZS status Ended for HL410882+4.p
181219.75/23939.68	% SZS status Started for HL410881+5.p
181219.75/23939.68	% SZS status GaveUp for HL410881+5.p
181219.75/23939.68	eprover: CPU time limit exceeded, terminating
181219.75/23939.68	% SZS status Ended for HL410881+5.p
181226.20/23940.45	% SZS status Started for HL410882+5.p
181226.20/23940.45	% SZS status GaveUp for HL410882+5.p
181226.20/23940.45	eprover: CPU time limit exceeded, terminating
181226.20/23940.45	% SZS status Ended for HL410882+5.p
181227.61/23940.68	% SZS status Started for HL410883+4.p
181227.61/23940.68	% SZS status GaveUp for HL410883+4.p
181227.61/23940.68	eprover: CPU time limit exceeded, terminating
181227.61/23940.68	% SZS status Ended for HL410883+4.p
181228.95/23940.82	% SZS status Started for HL410883+5.p
181228.95/23940.82	% SZS status GaveUp for HL410883+5.p
181228.95/23940.82	eprover: CPU time limit exceeded, terminating
181228.95/23940.82	% SZS status Ended for HL410883+5.p
181232.22/23941.20	% SZS status Started for HL410884+4.p
181232.22/23941.20	% SZS status GaveUp for HL410884+4.p
181232.22/23941.20	eprover: CPU time limit exceeded, terminating
181232.22/23941.20	% SZS status Ended for HL410884+4.p
181234.95/23941.61	% SZS status Started for HL410884+5.p
181234.95/23941.61	% SZS status GaveUp for HL410884+5.p
181234.95/23941.61	eprover: CPU time limit exceeded, terminating
181234.95/23941.61	% SZS status Ended for HL410884+5.p
181242.09/23942.47	% SZS status Started for HL410886+4.p
181242.09/23942.47	% SZS status GaveUp for HL410886+4.p
181242.09/23942.47	eprover: CPU time limit exceeded, terminating
181242.09/23942.47	% SZS status Ended for HL410886+4.p
181242.83/23942.54	% SZS status Started for HL410886+5.p
181242.83/23942.54	% SZS status GaveUp for HL410886+5.p
181242.83/23942.54	eprover: CPU time limit exceeded, terminating
181242.83/23942.54	% SZS status Ended for HL410886+5.p
181244.30/23942.79	% SZS status Started for HL410887+4.p
181244.30/23942.79	% SZS status GaveUp for HL410887+4.p
181244.30/23942.79	eprover: CPU time limit exceeded, terminating
181244.30/23942.79	% SZS status Ended for HL410887+4.p
181250.22/23943.48	% SZS status Started for HL410887+5.p
181250.22/23943.48	% SZS status GaveUp for HL410887+5.p
181250.22/23943.48	eprover: CPU time limit exceeded, terminating
181250.22/23943.48	% SZS status Ended for HL410887+5.p
181251.78/23943.72	% SZS status Started for HL410888+4.p
181251.78/23943.72	% SZS status GaveUp for HL410888+4.p
181251.78/23943.72	eprover: CPU time limit exceeded, terminating
181251.78/23943.72	% SZS status Ended for HL410888+4.p
181253.34/23943.95	% SZS status Started for HL410888+5.p
181253.34/23943.95	% SZS status GaveUp for HL410888+5.p
181253.34/23943.95	eprover: CPU time limit exceeded, terminating
181253.34/23943.95	% SZS status Ended for HL410888+5.p
181256.20/23944.24	% SZS status Started for HL410889+4.p
181256.20/23944.24	% SZS status GaveUp for HL410889+4.p
181256.20/23944.24	eprover: CPU time limit exceeded, terminating
181256.20/23944.24	% SZS status Ended for HL410889+4.p
181259.19/23944.64	% SZS status Started for HL410889+5.p
181259.19/23944.64	% SZS status GaveUp for HL410889+5.p
181259.19/23944.64	eprover: CPU time limit exceeded, terminating
181259.19/23944.64	% SZS status Ended for HL410889+5.p
181265.95/23945.50	% SZS status Started for HL410890+4.p
181265.95/23945.50	% SZS status GaveUp for HL410890+4.p
181265.95/23945.50	eprover: CPU time limit exceeded, terminating
181265.95/23945.50	% SZS status Ended for HL410890+4.p
181266.58/23945.57	% SZS status Started for HL410890+5.p
181266.58/23945.57	% SZS status GaveUp for HL410890+5.p
181266.58/23945.57	eprover: CPU time limit exceeded, terminating
181266.58/23945.57	% SZS status Ended for HL410890+5.p
181268.53/23945.82	% SZS status Started for HL410891+4.p
181268.53/23945.82	% SZS status GaveUp for HL410891+4.p
181268.53/23945.82	eprover: CPU time limit exceeded, terminating
181268.53/23945.82	% SZS status Ended for HL410891+4.p
181274.06/23946.53	% SZS status Started for HL410891+5.p
181274.06/23946.53	% SZS status GaveUp for HL410891+5.p
181274.06/23946.53	eprover: CPU time limit exceeded, terminating
181274.06/23946.53	% SZS status Ended for HL410891+5.p
181275.39/23946.75	% SZS status Started for HL410892+4.p
181275.39/23946.75	% SZS status GaveUp for HL410892+4.p
181275.39/23946.75	eprover: CPU time limit exceeded, terminating
181275.39/23946.75	% SZS status Ended for HL410892+4.p
181277.39/23947.00	% SZS status Started for HL410892+5.p
181277.39/23947.00	% SZS status GaveUp for HL410892+5.p
181277.39/23947.00	eprover: CPU time limit exceeded, terminating
181277.39/23947.00	% SZS status Ended for HL410892+5.p
181279.27/23947.29	% SZS status Started for HL410894+4.p
181279.27/23947.29	% SZS status GaveUp for HL410894+4.p
181279.27/23947.29	eprover: CPU time limit exceeded, terminating
181279.27/23947.29	% SZS status Ended for HL410894+4.p
181283.39/23947.70	% SZS status Started for HL410894+5.p
181283.39/23947.70	% SZS status GaveUp for HL410894+5.p
181283.39/23947.70	eprover: CPU time limit exceeded, terminating
181283.39/23947.70	% SZS status Ended for HL410894+5.p
181290.27/23948.61	% SZS status Started for HL410895+5.p
181290.27/23948.61	% SZS status GaveUp for HL410895+5.p
181290.27/23948.61	eprover: CPU time limit exceeded, terminating
181290.27/23948.61	% SZS status Ended for HL410895+5.p
181291.77/23948.80	% SZS status Started for HL410895+4.p
181291.77/23948.80	% SZS status GaveUp for HL410895+4.p
181291.77/23948.80	eprover: CPU time limit exceeded, terminating
181291.77/23948.80	% SZS status Ended for HL410895+4.p
181294.33/23949.10	% SZS status Started for HL410896+4.p
181294.33/23949.10	% SZS status GaveUp for HL410896+4.p
181294.33/23949.10	eprover: CPU time limit exceeded, terminating
181294.33/23949.10	% SZS status Ended for HL410896+4.p
181297.77/23949.56	% SZS status Started for HL410896+5.p
181297.77/23949.56	% SZS status GaveUp for HL410896+5.p
181297.77/23949.56	eprover: CPU time limit exceeded, terminating
181297.77/23949.56	% SZS status Ended for HL410896+5.p
181300.38/23949.87	% SZS status Started for HL410897+4.p
181300.38/23949.87	% SZS status GaveUp for HL410897+4.p
181300.38/23949.87	eprover: CPU time limit exceeded, terminating
181300.38/23949.87	% SZS status Ended for HL410897+4.p
181301.52/23950.03	% SZS status Started for HL410897+5.p
181301.52/23950.03	% SZS status GaveUp for HL410897+5.p
181301.52/23950.03	eprover: CPU time limit exceeded, terminating
181301.52/23950.03	% SZS status Ended for HL410897+5.p
181304.11/23950.32	% SZS status Started for HL410898+4.p
181304.11/23950.32	% SZS status GaveUp for HL410898+4.p
181304.11/23950.32	eprover: CPU time limit exceeded, terminating
181304.11/23950.32	% SZS status Ended for HL410898+4.p
181306.62/23950.74	% SZS status Started for HL410898+5.p
181306.62/23950.74	% SZS status GaveUp for HL410898+5.p
181306.62/23950.74	eprover: CPU time limit exceeded, terminating
181306.62/23950.74	% SZS status Ended for HL410898+5.p
181314.70/23951.70	% SZS status Started for HL410899+4.p
181314.70/23951.70	% SZS status GaveUp for HL410899+4.p
181314.70/23951.70	eprover: CPU time limit exceeded, terminating
181314.70/23951.70	% SZS status Ended for HL410899+4.p
181315.83/23951.83	% SZS status Started for HL410899+5.p
181315.83/23951.83	% SZS status GaveUp for HL410899+5.p
181315.83/23951.83	eprover: CPU time limit exceeded, terminating
181315.83/23951.83	% SZS status Ended for HL410899+5.p
181318.27/23952.13	% SZS status Started for HL410900+4.p
181318.27/23952.13	% SZS status GaveUp for HL410900+4.p
181318.27/23952.13	eprover: CPU time limit exceeded, terminating
181318.27/23952.13	% SZS status Ended for HL410900+4.p
181322.12/23952.60	% SZS status Started for HL410900+5.p
181322.12/23952.60	% SZS status GaveUp for HL410900+5.p
181322.12/23952.60	eprover: CPU time limit exceeded, terminating
181322.12/23952.60	% SZS status Ended for HL410900+5.p
181324.34/23952.90	% SZS status Started for HL410901+4.p
181324.34/23952.90	% SZS status GaveUp for HL410901+4.p
181324.34/23952.90	eprover: CPU time limit exceeded, terminating
181324.34/23952.90	% SZS status Ended for HL410901+4.p
181325.88/23953.07	% SZS status Started for HL410901+5.p
181325.88/23953.07	% SZS status GaveUp for HL410901+5.p
181325.88/23953.07	eprover: CPU time limit exceeded, terminating
181325.88/23953.07	% SZS status Ended for HL410901+5.p
181328.94/23953.48	% SZS status Started for HL410902+4.p
181328.94/23953.48	% SZS status GaveUp for HL410902+4.p
181328.94/23953.48	eprover: CPU time limit exceeded, terminating
181328.94/23953.48	% SZS status Ended for HL410902+4.p
181331.62/23953.78	% SZS status Started for HL410902+5.p
181331.62/23953.78	% SZS status GaveUp for HL410902+5.p
181331.62/23953.78	eprover: CPU time limit exceeded, terminating
181331.62/23953.78	% SZS status Ended for HL410902+5.p
181338.53/23954.73	% SZS status Started for HL410903+4.p
181338.53/23954.73	% SZS status GaveUp for HL410903+4.p
181338.53/23954.73	eprover: CPU time limit exceeded, terminating
181338.53/23954.73	% SZS status Ended for HL410903+4.p
181339.89/23954.87	% SZS status Started for HL410903+5.p
181339.89/23954.87	% SZS status GaveUp for HL410903+5.p
181339.89/23954.87	eprover: CPU time limit exceeded, terminating
181339.89/23954.87	% SZS status Ended for HL410903+5.p
181341.77/23955.17	% SZS status Started for HL410905+4.p
181341.77/23955.17	% SZS status GaveUp for HL410905+4.p
181341.77/23955.17	eprover: CPU time limit exceeded, terminating
181341.77/23955.17	% SZS status Ended for HL410905+4.p
181346.36/23955.63	% SZS status Started for HL410905+5.p
181346.36/23955.63	% SZS status GaveUp for HL410905+5.p
181346.36/23955.63	eprover: CPU time limit exceeded, terminating
181346.36/23955.63	% SZS status Ended for HL410905+5.p
181349.09/23955.98	% SZS status Started for HL410907+4.p
181349.09/23955.98	% SZS status GaveUp for HL410907+4.p
181349.09/23955.98	eprover: CPU time limit exceeded, terminating
181349.09/23955.98	% SZS status Ended for HL410907+4.p
181350.25/23956.15	% SZS status Started for HL410907+5.p
181350.25/23956.15	% SZS status GaveUp for HL410907+5.p
181350.25/23956.15	eprover: CPU time limit exceeded, terminating
181350.25/23956.15	% SZS status Ended for HL410907+5.p
181353.30/23956.51	% SZS status Started for HL410908+4.p
181353.30/23956.51	% SZS status GaveUp for HL410908+4.p
181353.30/23956.51	eprover: CPU time limit exceeded, terminating
181353.30/23956.51	% SZS status Ended for HL410908+4.p
181355.39/23956.83	% SZS status Started for HL410908+5.p
181355.39/23956.83	% SZS status GaveUp for HL410908+5.p
181355.39/23956.83	eprover: CPU time limit exceeded, terminating
181355.39/23956.83	% SZS status Ended for HL410908+5.p
181364.36/23957.90	% SZS status Started for HL410909+4.p
181364.36/23957.90	% SZS status GaveUp for HL410909+4.p
181364.36/23957.90	eprover: CPU time limit exceeded, terminating
181364.36/23957.90	% SZS status Ended for HL410909+4.p
181364.36/23957.91	% SZS status Started for HL410909+5.p
181364.36/23957.91	% SZS status GaveUp for HL410909+5.p
181364.36/23957.91	eprover: CPU time limit exceeded, terminating
181364.36/23957.91	% SZS status Ended for HL410909+5.p
181366.48/23958.20	% SZS status Started for HL410910+4.p
181366.48/23958.20	% SZS status GaveUp for HL410910+4.p
181366.48/23958.20	eprover: CPU time limit exceeded, terminating
181366.48/23958.20	% SZS status Ended for HL410910+4.p
181369.48/23958.65	% SZS status Started for HL410910+5.p
181369.48/23958.65	% SZS status GaveUp for HL410910+5.p
181369.48/23958.65	eprover: CPU time limit exceeded, terminating
181369.48/23958.65	% SZS status Ended for HL410910+5.p
181372.89/23959.00	% SZS status Started for HL410911+4.p
181372.89/23959.00	% SZS status GaveUp for HL410911+4.p
181372.89/23959.00	eprover: CPU time limit exceeded, terminating
181372.89/23959.00	% SZS status Ended for HL410911+4.p
181374.47/23959.18	% SZS status Started for HL410911+5.p
181374.47/23959.18	% SZS status GaveUp for HL410911+5.p
181374.47/23959.18	eprover: CPU time limit exceeded, terminating
181374.47/23959.18	% SZS status Ended for HL410911+5.p
181377.39/23959.54	% SZS status Started for HL410912+4.p
181377.39/23959.54	% SZS status GaveUp for HL410912+4.p
181377.39/23959.54	eprover: CPU time limit exceeded, terminating
181377.39/23959.54	% SZS status Ended for HL410912+4.p
181379.80/23959.86	% SZS status Started for HL410912+5.p
181379.80/23959.86	% SZS status GaveUp for HL410912+5.p
181379.80/23959.86	eprover: CPU time limit exceeded, terminating
181379.80/23959.86	% SZS status Ended for HL410912+5.p
181387.92/23960.93	% SZS status Started for HL410916+4.p
181387.92/23960.93	% SZS status GaveUp for HL410916+4.p
181387.92/23960.93	eprover: CPU time limit exceeded, terminating
181387.92/23960.93	% SZS status Ended for HL410916+4.p
181388.70/23960.96	% SZS status Started for HL410916+5.p
181388.70/23960.96	% SZS status GaveUp for HL410916+5.p
181388.70/23960.96	eprover: CPU time limit exceeded, terminating
181388.70/23960.96	% SZS status Ended for HL410916+5.p
181390.89/23961.24	% SZS status Started for HL410917+4.p
181390.89/23961.24	% SZS status GaveUp for HL410917+4.p
181390.89/23961.24	eprover: CPU time limit exceeded, terminating
181390.89/23961.24	% SZS status Ended for HL410917+4.p
181394.56/23961.71	% SZS status Started for HL410917+5.p
181394.56/23961.71	% SZS status GaveUp for HL410917+5.p
181394.56/23961.71	eprover: CPU time limit exceeded, terminating
181394.56/23961.71	% SZS status Ended for HL410917+5.p
181396.67/23962.04	% SZS status Started for HL410918+4.p
181396.67/23962.04	% SZS status GaveUp for HL410918+4.p
181396.67/23962.04	eprover: CPU time limit exceeded, terminating
181396.67/23962.04	% SZS status Ended for HL410918+4.p
181398.89/23962.24	% SZS status Started for HL410918+5.p
181398.89/23962.24	% SZS status GaveUp for HL410918+5.p
181398.89/23962.24	eprover: CPU time limit exceeded, terminating
181398.89/23962.24	% SZS status Ended for HL410918+5.p
181401.39/23962.59	% SZS status Started for HL410920+4.p
181401.39/23962.59	% SZS status GaveUp for HL410920+4.p
181401.39/23962.59	eprover: CPU time limit exceeded, terminating
181401.39/23962.59	% SZS status Ended for HL410920+4.p
181405.27/23963.03	% SZS status Started for HL410920+5.p
181405.27/23963.03	% SZS status GaveUp for HL410920+5.p
181405.27/23963.03	eprover: CPU time limit exceeded, terminating
181405.27/23963.03	% SZS status Ended for HL410920+5.p
181412.50/23963.96	% SZS status Started for HL410921+4.p
181412.50/23963.96	% SZS status GaveUp for HL410921+4.p
181412.50/23963.96	eprover: CPU time limit exceeded, terminating
181412.50/23963.96	% SZS status Ended for HL410921+4.p
181412.50/23963.99	% SZS status Started for HL410921+5.p
181412.50/23963.99	% SZS status GaveUp for HL410921+5.p
181412.50/23963.99	eprover: CPU time limit exceeded, terminating
181412.50/23963.99	% SZS status Ended for HL410921+5.p
181414.41/23964.28	% SZS status Started for HL410924+4.p
181414.41/23964.28	% SZS status GaveUp for HL410924+4.p
181414.41/23964.28	eprover: CPU time limit exceeded, terminating
181414.41/23964.28	% SZS status Ended for HL410924+4.p
181418.48/23964.74	% SZS status Started for HL410924+5.p
181418.48/23964.74	% SZS status GaveUp for HL410924+5.p
181418.48/23964.74	eprover: CPU time limit exceeded, terminating
181418.48/23964.74	% SZS status Ended for HL410924+5.p
181421.00/23965.07	% SZS status Started for HL410926+4.p
181421.00/23965.07	% SZS status GaveUp for HL410926+4.p
181421.00/23965.07	eprover: CPU time limit exceeded, terminating
181421.00/23965.07	% SZS status Ended for HL410926+4.p
181422.53/23965.27	% SZS status Started for HL410926+5.p
181422.53/23965.27	% SZS status GaveUp for HL410926+5.p
181422.53/23965.27	eprover: CPU time limit exceeded, terminating
181422.53/23965.27	% SZS status Ended for HL410926+5.p
181425.20/23965.63	% SZS status Started for HL410928+4.p
181425.20/23965.63	% SZS status GaveUp for HL410928+4.p
181425.20/23965.63	eprover: CPU time limit exceeded, terminating
181425.20/23965.63	% SZS status Ended for HL410928+4.p
181429.44/23966.10	% SZS status Started for HL410928+5.p
181429.44/23966.10	% SZS status GaveUp for HL410928+5.p
181429.44/23966.10	eprover: CPU time limit exceeded, terminating
181429.44/23966.10	% SZS status Ended for HL410928+5.p
181436.70/23966.99	% SZS status Started for HL410929+4.p
181436.70/23966.99	% SZS status GaveUp for HL410929+4.p
181436.70/23966.99	eprover: CPU time limit exceeded, terminating
181436.70/23966.99	% SZS status Ended for HL410929+4.p
181436.70/23967.02	% SZS status Started for HL410929+5.p
181436.70/23967.02	% SZS status GaveUp for HL410929+5.p
181436.70/23967.02	eprover: CPU time limit exceeded, terminating
181436.70/23967.02	% SZS status Ended for HL410929+5.p
181439.23/23967.34	% SZS status Started for HL410930+4.p
181439.23/23967.34	% SZS status GaveUp for HL410930+4.p
181439.23/23967.34	eprover: CPU time limit exceeded, terminating
181439.23/23967.34	% SZS status Ended for HL410930+4.p
181442.33/23967.79	% SZS status Started for HL410930+5.p
181442.33/23967.79	% SZS status GaveUp for HL410930+5.p
181442.33/23967.79	eprover: CPU time limit exceeded, terminating
181442.33/23967.79	% SZS status Ended for HL410930+5.p
181445.19/23968.11	% SZS status Started for HL410932+4.p
181445.19/23968.11	% SZS status GaveUp for HL410932+4.p
181445.19/23968.11	eprover: CPU time limit exceeded, terminating
181445.19/23968.11	% SZS status Ended for HL410932+4.p
181448.00/23968.41	% SZS status Started for HL410932+5.p
181448.00/23968.41	% SZS status GaveUp for HL410932+5.p
181448.00/23968.41	eprover: CPU time limit exceeded, terminating
181448.00/23968.41	% SZS status Ended for HL410932+5.p
181449.55/23968.68	% SZS status Started for HL410933+4.p
181449.55/23968.68	% SZS status GaveUp for HL410933+4.p
181449.55/23968.68	eprover: CPU time limit exceeded, terminating
181449.55/23968.68	% SZS status Ended for HL410933+4.p
181453.28/23969.14	% SZS status Started for HL410933+5.p
181453.28/23969.14	% SZS status GaveUp for HL410933+5.p
181453.28/23969.14	eprover: CPU time limit exceeded, terminating
181453.28/23969.14	% SZS status Ended for HL410933+5.p
181460.28/23970.02	% SZS status Started for HL410934+4.p
181460.28/23970.02	% SZS status GaveUp for HL410934+4.p
181460.28/23970.02	eprover: CPU time limit exceeded, terminating
181460.28/23970.02	% SZS status Ended for HL410934+4.p
181460.95/23970.05	% SZS status Started for HL410934+5.p
181460.95/23970.05	% SZS status GaveUp for HL410934+5.p
181460.95/23970.05	eprover: CPU time limit exceeded, terminating
181460.95/23970.05	% SZS status Ended for HL410934+5.p
181462.69/23970.38	% SZS status Started for HL410935+4.p
181462.69/23970.38	% SZS status GaveUp for HL410935+4.p
181462.69/23970.38	eprover: CPU time limit exceeded, terminating
181462.69/23970.38	% SZS status Ended for HL410935+4.p
181466.62/23970.83	% SZS status Started for HL410935+5.p
181466.62/23970.83	% SZS status GaveUp for HL410935+5.p
181466.62/23970.83	eprover: CPU time limit exceeded, terminating
181466.62/23970.83	% SZS status Ended for HL410935+5.p
181469.41/23971.14	% SZS status Started for HL410936+4.p
181469.41/23971.14	% SZS status GaveUp for HL410936+4.p
181469.41/23971.14	eprover: CPU time limit exceeded, terminating
181469.41/23971.14	% SZS status Ended for HL410936+4.p
181473.05/23971.57	% SZS status Started for HL410936+5.p
181473.05/23971.57	% SZS status GaveUp for HL410936+5.p
181473.05/23971.57	eprover: CPU time limit exceeded, terminating
181473.05/23971.57	% SZS status Ended for HL410936+5.p
181473.58/23971.71	% SZS status Started for HL410937+4.p
181473.58/23971.71	% SZS status GaveUp for HL410937+4.p
181473.58/23971.71	eprover: CPU time limit exceeded, terminating
181473.58/23971.71	% SZS status Ended for HL410937+4.p
181476.97/23972.18	% SZS status Started for HL410937+5.p
181476.97/23972.18	% SZS status GaveUp for HL410937+5.p
181476.97/23972.18	eprover: CPU time limit exceeded, terminating
181476.97/23972.18	% SZS status Ended for HL410937+5.p
181484.64/23973.05	% SZS status Started for HL410940+4.p
181484.64/23973.05	% SZS status GaveUp for HL410940+4.p
181484.64/23973.05	eprover: CPU time limit exceeded, terminating
181484.64/23973.05	% SZS status Ended for HL410940+4.p
181485.00/23973.09	% SZS status Started for HL410940+5.p
181485.00/23973.09	% SZS status GaveUp for HL410940+5.p
181485.00/23973.09	eprover: CPU time limit exceeded, terminating
181485.00/23973.09	% SZS status Ended for HL410940+5.p
181486.80/23973.41	% SZS status Started for HL410941+4.p
181486.80/23973.41	% SZS status GaveUp for HL410941+4.p
181486.80/23973.41	eprover: CPU time limit exceeded, terminating
181486.80/23973.41	% SZS status Ended for HL410941+4.p
181491.31/23973.86	% SZS status Started for HL410941+5.p
181491.31/23973.86	% SZS status GaveUp for HL410941+5.p
181491.31/23973.86	eprover: CPU time limit exceeded, terminating
181491.31/23973.86	% SZS status Ended for HL410941+5.p
181493.66/23974.18	% SZS status Started for HL410942+4.p
181493.66/23974.18	% SZS status GaveUp for HL410942+4.p
181493.66/23974.18	eprover: CPU time limit exceeded, terminating
181493.66/23974.18	% SZS status Ended for HL410942+4.p
181497.19/23974.62	% SZS status Started for HL410942+5.p
181497.19/23974.62	% SZS status GaveUp for HL410942+5.p
181497.19/23974.62	eprover: CPU time limit exceeded, terminating
181497.19/23974.62	% SZS status Ended for HL410942+5.p
181498.78/23974.87	% SZS status Started for HL410943+4.p
181498.78/23974.87	% SZS status GaveUp for HL410943+4.p
181498.78/23974.87	eprover: CPU time limit exceeded, terminating
181498.78/23974.87	% SZS status Ended for HL410943+4.p
181501.44/23975.21	% SZS status Started for HL410943+5.p
181501.44/23975.21	% SZS status GaveUp for HL410943+5.p
181501.44/23975.21	eprover: CPU time limit exceeded, terminating
181501.44/23975.21	% SZS status Ended for HL410943+5.p
181508.67/23976.08	% SZS status Started for HL410944+4.p
181508.67/23976.08	% SZS status GaveUp for HL410944+4.p
181508.67/23976.08	eprover: CPU time limit exceeded, terminating
181508.67/23976.08	% SZS status Ended for HL410944+4.p
181508.67/23976.12	% SZS status Started for HL410944+5.p
181508.67/23976.12	% SZS status GaveUp for HL410944+5.p
181508.67/23976.12	eprover: CPU time limit exceeded, terminating
181508.67/23976.12	% SZS status Ended for HL410944+5.p
181511.23/23976.43	% SZS status Started for HL410945+4.p
181511.23/23976.43	% SZS status GaveUp for HL410945+4.p
181511.23/23976.43	eprover: CPU time limit exceeded, terminating
181511.23/23976.43	% SZS status Ended for HL410945+4.p
181515.27/23976.89	% SZS status Started for HL410945+5.p
181515.27/23976.89	% SZS status GaveUp for HL410945+5.p
181515.27/23976.89	eprover: CPU time limit exceeded, terminating
181515.27/23976.89	% SZS status Ended for HL410945+5.p
181517.39/23977.22	% SZS status Started for HL410948+4.p
181517.39/23977.22	% SZS status GaveUp for HL410948+4.p
181517.39/23977.22	eprover: CPU time limit exceeded, terminating
181517.39/23977.22	% SZS status Ended for HL410948+4.p
181522.08/23977.77	% SZS status Started for HL410948+5.p
181522.08/23977.77	% SZS status GaveUp for HL410948+5.p
181522.08/23977.77	eprover: CPU time limit exceeded, terminating
181522.08/23977.77	% SZS status Ended for HL410948+5.p
181523.06/23977.90	% SZS status Started for HL410949+4.p
181523.06/23977.90	% SZS status GaveUp for HL410949+4.p
181523.06/23977.90	eprover: CPU time limit exceeded, terminating
181523.06/23977.90	% SZS status Ended for HL410949+4.p
181525.59/23978.26	% SZS status Started for HL410949+5.p
181525.59/23978.26	% SZS status GaveUp for HL410949+5.p
181525.59/23978.26	eprover: CPU time limit exceeded, terminating
181525.59/23978.26	% SZS status Ended for HL410949+5.p
181532.62/23979.12	% SZS status Started for HL410950+4.p
181532.62/23979.12	% SZS status GaveUp for HL410950+4.p
181532.62/23979.12	eprover: CPU time limit exceeded, terminating
181532.62/23979.12	% SZS status Ended for HL410950+4.p
181533.34/23979.16	% SZS status Started for HL410950+5.p
181533.34/23979.16	% SZS status GaveUp for HL410950+5.p
181533.34/23979.16	eprover: CPU time limit exceeded, terminating
181533.34/23979.16	% SZS status Ended for HL410950+5.p
181535.17/23979.46	% SZS status Started for HL410952+4.p
181535.17/23979.46	% SZS status GaveUp for HL410952+4.p
181535.17/23979.46	eprover: CPU time limit exceeded, terminating
181535.17/23979.46	% SZS status Ended for HL410952+4.p
181538.81/23979.93	% SZS status Started for HL410952+5.p
181538.81/23979.93	% SZS status GaveUp for HL410952+5.p
181538.81/23979.93	eprover: CPU time limit exceeded, terminating
181538.81/23979.93	% SZS status Ended for HL410952+5.p
181541.41/23980.25	% SZS status Started for HL410954+4.p
181541.41/23980.25	% SZS status GaveUp for HL410954+4.p
181541.41/23980.25	eprover: CPU time limit exceeded, terminating
181541.41/23980.25	% SZS status Ended for HL410954+4.p
181546.30/23980.81	% SZS status Started for HL410954+5.p
181546.30/23980.81	% SZS status GaveUp for HL410954+5.p
181546.30/23980.81	eprover: CPU time limit exceeded, terminating
181546.30/23980.81	% SZS status Ended for HL410954+5.p
181547.45/23980.94	% SZS status Started for HL410955+4.p
181547.45/23980.94	% SZS status GaveUp for HL410955+4.p
181547.45/23980.94	eprover: CPU time limit exceeded, terminating
181547.45/23980.94	% SZS status Ended for HL410955+4.p
181551.08/23981.41	% SZS status Started for HL410955+5.p
181551.08/23981.41	% SZS status GaveUp for HL410955+5.p
181551.08/23981.41	eprover: CPU time limit exceeded, terminating
181551.08/23981.41	% SZS status Ended for HL410955+5.p
181557.05/23982.14	% SZS status Started for HL410956+4.p
181557.05/23982.14	% SZS status GaveUp for HL410956+4.p
181557.05/23982.14	eprover: CPU time limit exceeded, terminating
181557.05/23982.14	% SZS status Ended for HL410956+4.p
181557.91/23982.25	% SZS status Started for HL410956+5.p
181557.91/23982.25	% SZS status GaveUp for HL410956+5.p
181557.91/23982.25	eprover: CPU time limit exceeded, terminating
181557.91/23982.25	% SZS status Ended for HL410956+5.p
181559.86/23982.49	% SZS status Started for HL410957+4.p
181559.86/23982.49	% SZS status GaveUp for HL410957+4.p
181559.86/23982.49	eprover: CPU time limit exceeded, terminating
181559.86/23982.49	% SZS status Ended for HL410957+4.p
181563.39/23982.96	% SZS status Started for HL410957+5.p
181563.39/23982.96	% SZS status GaveUp for HL410957+5.p
181563.39/23982.96	eprover: CPU time limit exceeded, terminating
181563.39/23982.96	% SZS status Ended for HL410957+5.p
181565.55/23983.28	% SZS status Started for HL410960+4.p
181565.55/23983.28	% SZS status GaveUp for HL410960+4.p
181565.55/23983.28	eprover: CPU time limit exceeded, terminating
181565.55/23983.28	% SZS status Ended for HL410960+4.p
181570.03/23983.84	% SZS status Started for HL410960+5.p
181570.03/23983.84	% SZS status GaveUp for HL410960+5.p
181570.03/23983.84	eprover: CPU time limit exceeded, terminating
181570.03/23983.84	% SZS status Ended for HL410960+5.p
181571.48/23983.97	% SZS status Started for HL410961+4.p
181571.48/23983.97	% SZS status GaveUp for HL410961+4.p
181571.48/23983.97	eprover: CPU time limit exceeded, terminating
181571.48/23983.97	% SZS status Ended for HL410961+4.p
181575.14/23984.50	% SZS status Started for HL410961+5.p
181575.14/23984.50	% SZS status GaveUp for HL410961+5.p
181575.14/23984.50	eprover: CPU time limit exceeded, terminating
181575.14/23984.50	% SZS status Ended for HL410961+5.p
181581.91/23985.28	% SZS status Started for HL410962+4.p
181581.91/23985.28	% SZS status GaveUp for HL410962+4.p
181581.91/23985.28	eprover: CPU time limit exceeded, terminating
181581.91/23985.28	% SZS status Ended for HL410962+4.p
181581.91/23985.29	% SZS status Started for HL410962+5.p
181581.91/23985.29	% SZS status GaveUp for HL410962+5.p
181581.91/23985.29	eprover: CPU time limit exceeded, terminating
181581.91/23985.29	% SZS status Ended for HL410962+5.p
181583.22/23985.53	% SZS status Started for HL410963+4.p
181583.22/23985.53	% SZS status GaveUp for HL410963+4.p
181583.22/23985.53	eprover: CPU time limit exceeded, terminating
181583.22/23985.53	% SZS status Ended for HL410963+4.p
181587.50/23986.01	% SZS status Started for HL410963+5.p
181587.50/23986.01	% SZS status GaveUp for HL410963+5.p
181587.50/23986.01	eprover: CPU time limit exceeded, terminating
181587.50/23986.01	% SZS status Ended for HL410963+5.p
181590.05/23986.31	% SZS status Started for HL410964+4.p
181590.05/23986.31	% SZS status GaveUp for HL410964+4.p
181590.05/23986.31	eprover: CPU time limit exceeded, terminating
181590.05/23986.31	% SZS status Ended for HL410964+4.p
181593.97/23986.87	% SZS status Started for HL410964+5.p
181593.97/23986.87	% SZS status GaveUp for HL410964+5.p
181593.97/23986.87	eprover: CPU time limit exceeded, terminating
181593.97/23986.87	% SZS status Ended for HL410964+5.p
181595.44/23987.02	% SZS status Started for HL410965+4.p
181595.44/23987.02	% SZS status GaveUp for HL410965+4.p
181595.44/23987.02	eprover: CPU time limit exceeded, terminating
181595.44/23987.02	% SZS status Ended for HL410965+4.p
181600.73/23987.67	% SZS status Started for HL410965+5.p
181600.73/23987.67	% SZS status GaveUp for HL410965+5.p
181600.73/23987.67	eprover: CPU time limit exceeded, terminating
181600.73/23987.67	% SZS status Ended for HL410965+5.p
181605.53/23988.30	% SZS status Started for HL410966+4.p
181605.53/23988.30	% SZS status GaveUp for HL410966+4.p
181605.53/23988.30	eprover: CPU time limit exceeded, terminating
181605.53/23988.30	% SZS status Ended for HL410966+4.p
181605.53/23988.32	% SZS status Started for HL410966+5.p
181605.53/23988.32	% SZS status GaveUp for HL410966+5.p
181605.53/23988.32	eprover: CPU time limit exceeded, terminating
181605.53/23988.32	% SZS status Ended for HL410966+5.p
181607.52/23988.55	% SZS status Started for HL410967+4.p
181607.52/23988.55	% SZS status GaveUp for HL410967+4.p
181607.52/23988.55	eprover: CPU time limit exceeded, terminating
181607.52/23988.55	% SZS status Ended for HL410967+4.p
181611.75/23989.04	% SZS status Started for HL410967+5.p
181611.75/23989.04	% SZS status GaveUp for HL410967+5.p
181611.75/23989.04	eprover: CPU time limit exceeded, terminating
181611.75/23989.04	% SZS status Ended for HL410967+5.p
181613.53/23989.35	% SZS status Started for HL410968+4.p
181613.53/23989.35	% SZS status GaveUp for HL410968+4.p
181613.53/23989.35	eprover: CPU time limit exceeded, terminating
181613.53/23989.35	% SZS status Ended for HL410968+4.p
181620.56/23989.91	% SZS status Started for HL410968+5.p
181620.56/23989.91	% SZS status GaveUp for HL410968+5.p
181620.56/23989.91	eprover: CPU time limit exceeded, terminating
181620.56/23989.91	% SZS status Ended for HL410968+5.p
181621.89/23990.10	% SZS status Started for HL410969+4.p
181621.89/23990.10	% SZS status GaveUp for HL410969+4.p
181621.89/23990.10	eprover: CPU time limit exceeded, terminating
181621.89/23990.10	% SZS status Ended for HL410969+4.p
181626.81/23990.75	% SZS status Started for HL410969+5.p
181626.81/23990.75	% SZS status GaveUp for HL410969+5.p
181626.81/23990.75	eprover: CPU time limit exceeded, terminating
181626.81/23990.75	% SZS status Ended for HL410969+5.p
181630.94/23991.34	% SZS status Started for HL410970+4.p
181630.94/23991.34	% SZS status GaveUp for HL410970+4.p
181630.94/23991.34	eprover: CPU time limit exceeded, terminating
181630.94/23991.34	% SZS status Ended for HL410970+4.p
181632.31/23991.35	% SZS status Started for HL410970+5.p
181632.31/23991.35	% SZS status GaveUp for HL410970+5.p
181632.31/23991.35	eprover: CPU time limit exceeded, terminating
181632.31/23991.35	% SZS status Ended for HL410970+5.p
181634.05/23991.65	% SZS status Started for HL410971+4.p
181634.05/23991.65	% SZS status GaveUp for HL410971+4.p
181634.05/23991.65	eprover: CPU time limit exceeded, terminating
181634.05/23991.65	% SZS status Ended for HL410971+4.p
181638.12/23992.08	% SZS status Started for HL410971+5.p
181638.12/23992.08	% SZS status GaveUp for HL410971+5.p
181638.12/23992.08	eprover: CPU time limit exceeded, terminating
181638.12/23992.08	% SZS status Ended for HL410971+5.p
181640.25/23992.38	% SZS status Started for HL410972+4.p
181640.25/23992.38	% SZS status GaveUp for HL410972+4.p
181640.25/23992.38	eprover: CPU time limit exceeded, terminating
181640.25/23992.38	% SZS status Ended for HL410972+4.p
181645.11/23993.04	% SZS status Started for HL410972+5.p
181645.11/23993.04	% SZS status GaveUp for HL410972+5.p
181645.11/23993.04	eprover: CPU time limit exceeded, terminating
181645.11/23993.04	% SZS status Ended for HL410972+5.p
181648.39/23993.15	% SZS status Started for HL410973+4.p
181648.39/23993.15	% SZS status GaveUp for HL410973+4.p
181648.39/23993.15	eprover: CPU time limit exceeded, terminating
181648.39/23993.15	% SZS status Ended for HL410973+4.p
181653.84/23993.79	% SZS status Started for HL410973+5.p
181653.84/23993.79	% SZS status GaveUp for HL410973+5.p
181653.84/23993.79	eprover: CPU time limit exceeded, terminating
181653.84/23993.79	% SZS status Ended for HL410973+5.p
181658.42/23994.37	% SZS status Started for HL410974+4.p
181658.42/23994.37	% SZS status GaveUp for HL410974+4.p
181658.42/23994.37	eprover: CPU time limit exceeded, terminating
181658.42/23994.37	% SZS status Ended for HL410974+4.p
181658.42/23994.39	% SZS status Started for HL410974+5.p
181658.42/23994.39	% SZS status GaveUp for HL410974+5.p
181658.42/23994.39	eprover: CPU time limit exceeded, terminating
181658.42/23994.39	% SZS status Ended for HL410974+5.p
181660.34/23994.70	% SZS status Started for HL410975+4.p
181660.34/23994.70	% SZS status GaveUp for HL410975+4.p
181660.34/23994.70	eprover: CPU time limit exceeded, terminating
181660.34/23994.70	% SZS status Ended for HL410975+4.p
181664.61/23995.12	% SZS status Started for HL410975+5.p
181664.61/23995.12	% SZS status GaveUp for HL410975+5.p
181664.61/23995.12	eprover: CPU time limit exceeded, terminating
181664.61/23995.12	% SZS status Ended for HL410975+5.p
181667.16/23995.45	% SZS status Started for HL410977+4.p
181667.16/23995.45	% SZS status GaveUp for HL410977+4.p
181667.16/23995.45	eprover: CPU time limit exceeded, terminating
181667.16/23995.45	% SZS status Ended for HL410977+4.p
181672.09/23996.07	% SZS status Started for HL410977+5.p
181672.09/23996.07	% SZS status GaveUp for HL410977+5.p
181672.09/23996.07	eprover: CPU time limit exceeded, terminating
181672.09/23996.07	% SZS status Ended for HL410977+5.p
181672.84/23996.21	% SZS status Started for HL410978+4.p
181672.84/23996.21	% SZS status GaveUp for HL410978+4.p
181672.84/23996.21	eprover: CPU time limit exceeded, terminating
181672.84/23996.21	% SZS status Ended for HL410978+4.p
181679.22/23996.98	% SZS status Started for HL410978+5.p
181679.22/23996.98	% SZS status GaveUp for HL410978+5.p
181679.22/23996.98	eprover: CPU time limit exceeded, terminating
181679.22/23996.98	% SZS status Ended for HL410978+5.p
181682.41/23997.40	% SZS status Started for HL410979+4.p
181682.41/23997.40	% SZS status GaveUp for HL410979+4.p
181682.41/23997.40	eprover: CPU time limit exceeded, terminating
181682.41/23997.40	% SZS status Ended for HL410979+4.p
181682.41/23997.42	% SZS status Started for HL410979+5.p
181682.41/23997.42	% SZS status GaveUp for HL410979+5.p
181682.41/23997.42	eprover: CPU time limit exceeded, terminating
181682.41/23997.42	% SZS status Ended for HL410979+5.p
181685.19/23997.73	% SZS status Started for HL410980+4.p
181685.19/23997.73	% SZS status GaveUp for HL410980+4.p
181685.19/23997.73	eprover: CPU time limit exceeded, terminating
181685.19/23997.73	% SZS status Ended for HL410980+4.p
181687.58/23998.15	% SZS status Started for HL410980+5.p
181687.58/23998.15	% SZS status GaveUp for HL410980+5.p
181687.58/23998.15	eprover: CPU time limit exceeded, terminating
181687.58/23998.15	% SZS status Ended for HL410980+5.p
181690.70/23998.49	% SZS status Started for HL410981+4.p
181690.70/23998.49	% SZS status GaveUp for HL410981+4.p
181690.70/23998.49	eprover: CPU time limit exceeded, terminating
181690.70/23998.49	% SZS status Ended for HL410981+4.p
181695.84/23999.10	% SZS status Started for HL410981+5.p
181695.84/23999.10	% SZS status GaveUp for HL410981+5.p
181695.84/23999.10	eprover: CPU time limit exceeded, terminating
181695.84/23999.10	% SZS status Ended for HL410981+5.p
181697.67/23999.32	% SZS status Started for HL410982+4.p
181697.67/23999.32	% SZS status GaveUp for HL410982+4.p
181697.67/23999.32	eprover: CPU time limit exceeded, terminating
181697.67/23999.32	% SZS status Ended for HL410982+4.p
181703.14/24000.01	% SZS status Started for HL410982+5.p
181703.14/24000.01	% SZS status GaveUp for HL410982+5.p
181703.14/24000.01	eprover: CPU time limit exceeded, terminating
181703.14/24000.01	% SZS status Ended for HL410982+5.p
181706.28/24000.43	% SZS status Started for HL410983+4.p
181706.28/24000.43	% SZS status GaveUp for HL410983+4.p
181706.28/24000.43	eprover: CPU time limit exceeded, terminating
181706.28/24000.43	% SZS status Ended for HL410983+4.p
181707.06/24000.46	% SZS status Started for HL410983+5.p
181707.06/24000.46	% SZS status GaveUp for HL410983+5.p
181707.06/24000.46	eprover: CPU time limit exceeded, terminating
181707.06/24000.46	% SZS status Ended for HL410983+5.p
181708.89/24000.77	% SZS status Started for HL410984+4.p
181708.89/24000.77	% SZS status GaveUp for HL410984+4.p
181708.89/24000.77	eprover: CPU time limit exceeded, terminating
181708.89/24000.77	% SZS status Ended for HL410984+4.p
181712.39/24001.19	% SZS status Started for HL410984+5.p
181712.39/24001.19	% SZS status GaveUp for HL410984+5.p
181712.39/24001.19	eprover: CPU time limit exceeded, terminating
181712.39/24001.19	% SZS status Ended for HL410984+5.p
181715.59/24001.56	% SZS status Started for HL410985+4.p
181715.59/24001.56	% SZS status GaveUp for HL410985+4.p
181715.59/24001.56	eprover: CPU time limit exceeded, terminating
181715.59/24001.56	% SZS status Ended for HL410985+4.p
181719.53/24002.13	% SZS status Started for HL410985+5.p
181719.53/24002.13	% SZS status GaveUp for HL410985+5.p
181719.53/24002.13	eprover: CPU time limit exceeded, terminating
181719.53/24002.13	% SZS status Ended for HL410985+5.p
181723.61/24002.35	% SZS status Started for HL410986+4.p
181723.61/24002.35	% SZS status GaveUp for HL410986+4.p
181723.61/24002.35	eprover: CPU time limit exceeded, terminating
181723.61/24002.35	% SZS status Ended for HL410986+4.p
181729.64/24003.06	% SZS status Started for HL410986+5.p
181729.64/24003.06	% SZS status GaveUp for HL410986+5.p
181729.64/24003.06	eprover: CPU time limit exceeded, terminating
181729.64/24003.06	% SZS status Ended for HL410986+5.p
181732.98/24003.45	% SZS status Started for HL410987+4.p
181732.98/24003.45	% SZS status GaveUp for HL410987+4.p
181732.98/24003.45	eprover: CPU time limit exceeded, terminating
181732.98/24003.45	% SZS status Ended for HL410987+4.p
181732.98/24003.50	% SZS status Started for HL410987+5.p
181732.98/24003.50	% SZS status GaveUp for HL410987+5.p
181732.98/24003.50	eprover: CPU time limit exceeded, terminating
181732.98/24003.50	% SZS status Ended for HL410987+5.p
181735.55/24003.82	% SZS status Started for HL410989+4.p
181735.55/24003.82	% SZS status GaveUp for HL410989+4.p
181735.55/24003.82	eprover: CPU time limit exceeded, terminating
181735.55/24003.82	% SZS status Ended for HL410989+4.p
181739.59/24004.35	% SZS status Started for HL410989+5.p
181739.59/24004.35	% SZS status GaveUp for HL410989+5.p
181739.59/24004.35	eprover: CPU time limit exceeded, terminating
181739.59/24004.35	% SZS status Ended for HL410989+5.p
181741.62/24004.59	% SZS status Started for HL410991+4.p
181741.62/24004.59	% SZS status GaveUp for HL410991+4.p
181741.62/24004.59	eprover: CPU time limit exceeded, terminating
181741.62/24004.59	% SZS status Ended for HL410991+4.p
181745.95/24005.16	% SZS status Started for HL410991+5.p
181745.95/24005.16	% SZS status GaveUp for HL410991+5.p
181745.95/24005.16	eprover: CPU time limit exceeded, terminating
181745.95/24005.16	% SZS status Ended for HL410991+5.p
181747.64/24005.38	% SZS status Started for HL410992+4.p
181747.64/24005.38	% SZS status GaveUp for HL410992+4.p
181747.64/24005.38	eprover: CPU time limit exceeded, terminating
181747.64/24005.38	% SZS status Ended for HL410992+4.p
181754.67/24006.18	% SZS status Started for HL410992+5.p
181754.67/24006.18	% SZS status GaveUp for HL410992+5.p
181754.67/24006.18	eprover: CPU time limit exceeded, terminating
181754.67/24006.18	% SZS status Ended for HL410992+5.p
181756.77/24006.48	% SZS status Started for HL410993+4.p
181756.77/24006.48	% SZS status GaveUp for HL410993+4.p
181756.77/24006.48	eprover: CPU time limit exceeded, terminating
181756.77/24006.48	% SZS status Ended for HL410993+4.p
181756.77/24006.53	% SZS status Started for HL410993+5.p
181756.77/24006.53	% SZS status GaveUp for HL410993+5.p
181756.77/24006.53	eprover: CPU time limit exceeded, terminating
181756.77/24006.53	% SZS status Ended for HL410993+5.p
181759.83/24006.88	% SZS status Started for HL410995+4.p
181759.83/24006.88	% SZS status GaveUp for HL410995+4.p
181759.83/24006.88	eprover: CPU time limit exceeded, terminating
181759.83/24006.88	% SZS status Ended for HL410995+4.p
181764.06/24007.38	% SZS status Started for HL410995+5.p
181764.06/24007.38	% SZS status GaveUp for HL410995+5.p
181764.06/24007.38	eprover: CPU time limit exceeded, terminating
181764.06/24007.38	% SZS status Ended for HL410995+5.p
181765.80/24007.63	% SZS status Started for HL410996+4.p
181765.80/24007.63	% SZS status GaveUp for HL410996+4.p
181765.80/24007.63	eprover: CPU time limit exceeded, terminating
181765.80/24007.63	% SZS status Ended for HL410996+4.p
181770.45/24008.20	% SZS status Started for HL410996+5.p
181770.45/24008.20	% SZS status GaveUp for HL410996+5.p
181770.45/24008.20	eprover: CPU time limit exceeded, terminating
181770.45/24008.20	% SZS status Ended for HL410996+5.p
181772.97/24008.51	% SZS status Started for HL410997+4.p
181772.97/24008.51	% SZS status GaveUp for HL410997+4.p
181772.97/24008.51	eprover: CPU time limit exceeded, terminating
181772.97/24008.51	% SZS status Ended for HL410997+4.p
181778.78/24009.24	% SZS status Started for HL410997+5.p
181778.78/24009.24	% SZS status GaveUp for HL410997+5.p
181778.78/24009.24	eprover: CPU time limit exceeded, terminating
181778.78/24009.24	% SZS status Ended for HL410997+5.p
181780.84/24009.51	% SZS status Started for HL411000+4.p
181780.84/24009.51	% SZS status GaveUp for HL411000+4.p
181780.84/24009.51	eprover: CPU time limit exceeded, terminating
181780.84/24009.51	% SZS status Ended for HL411000+4.p
181781.30/24009.56	% SZS status Started for HL411000+5.p
181781.30/24009.56	% SZS status GaveUp for HL411000+5.p
181781.30/24009.56	eprover: CPU time limit exceeded, terminating
181781.30/24009.56	% SZS status Ended for HL411000+5.p
181783.36/24009.91	% SZS status Started for HL411001+4.p
181783.36/24009.91	% SZS status GaveUp for HL411001+4.p
181783.36/24009.91	eprover: CPU time limit exceeded, terminating
181783.36/24009.91	% SZS status Ended for HL411001+4.p
181788.05/24010.41	% SZS status Started for HL411001+5.p
181788.05/24010.41	% SZS status GaveUp for HL411001+5.p
181788.05/24010.41	eprover: CPU time limit exceeded, terminating
181788.05/24010.41	% SZS status Ended for HL411001+5.p
181790.12/24010.66	% SZS status Started for HL411002+4.p
181790.12/24010.66	% SZS status GaveUp for HL411002+4.p
181790.12/24010.66	eprover: CPU time limit exceeded, terminating
181790.12/24010.66	% SZS status Ended for HL411002+4.p
181795.61/24011.36	% SZS status Started for HL411002+5.p
181795.61/24011.36	% SZS status GaveUp for HL411002+5.p
181795.61/24011.36	eprover: CPU time limit exceeded, terminating
181795.61/24011.36	% SZS status Ended for HL411002+5.p
181796.78/24011.55	% SZS status Started for HL411005+4.p
181796.78/24011.55	% SZS status GaveUp for HL411005+4.p
181796.78/24011.55	eprover: CPU time limit exceeded, terminating
181796.78/24011.55	% SZS status Ended for HL411005+4.p
181802.98/24012.28	% SZS status Started for HL411005+5.p
181802.98/24012.28	% SZS status GaveUp for HL411005+5.p
181802.98/24012.28	eprover: CPU time limit exceeded, terminating
181802.98/24012.28	% SZS status Ended for HL411005+5.p
181805.23/24012.55	% SZS status Started for HL411006+4.p
181805.23/24012.55	% SZS status GaveUp for HL411006+4.p
181805.23/24012.55	eprover: CPU time limit exceeded, terminating
181805.23/24012.55	% SZS status Ended for HL411006+4.p
181805.34/24012.60	% SZS status Started for HL411006+5.p
181805.34/24012.60	% SZS status GaveUp for HL411006+5.p
181805.34/24012.60	eprover: CPU time limit exceeded, terminating
181805.34/24012.60	% SZS status Ended for HL411006+5.p
181808.39/24012.95	% SZS status Started for HL411007+4.p
181808.39/24012.95	% SZS status GaveUp for HL411007+4.p
181808.39/24012.95	eprover: CPU time limit exceeded, terminating
181808.39/24012.95	% SZS status Ended for HL411007+4.p
181812.27/24013.46	% SZS status Started for HL411007+5.p
181812.27/24013.46	% SZS status GaveUp for HL411007+5.p
181812.27/24013.46	eprover: CPU time limit exceeded, terminating
181812.27/24013.46	% SZS status Ended for HL411007+5.p
181813.73/24013.69	% SZS status Started for HL411009+4.p
181813.73/24013.69	% SZS status GaveUp for HL411009+4.p
181813.73/24013.69	eprover: CPU time limit exceeded, terminating
181813.73/24013.69	% SZS status Ended for HL411009+4.p
181819.98/24014.45	% SZS status Started for HL411009+5.p
181819.98/24014.45	% SZS status GaveUp for HL411009+5.p
181819.98/24014.45	eprover: CPU time limit exceeded, terminating
181819.98/24014.45	% SZS status Ended for HL411009+5.p
181821.12/24014.59	% SZS status Started for HL411011+4.p
181821.12/24014.59	% SZS status GaveUp for HL411011+4.p
181821.12/24014.59	eprover: CPU time limit exceeded, terminating
181821.12/24014.59	% SZS status Ended for HL411011+4.p
181826.89/24015.31	% SZS status Started for HL411011+5.p
181826.89/24015.31	% SZS status GaveUp for HL411011+5.p
181826.89/24015.31	eprover: CPU time limit exceeded, terminating
181826.89/24015.31	% SZS status Ended for HL411011+5.p
181829.06/24015.63	% SZS status Started for HL411012+5.p
181829.06/24015.63	% SZS status GaveUp for HL411012+5.p
181829.06/24015.63	eprover: CPU time limit exceeded, terminating
181829.06/24015.63	% SZS status Ended for HL411012+5.p
181829.64/24015.67	% SZS status Started for HL411012+4.p
181829.64/24015.67	% SZS status GaveUp for HL411012+4.p
181829.64/24015.67	eprover: CPU time limit exceeded, terminating
181829.64/24015.67	% SZS status Ended for HL411012+4.p
181832.33/24015.98	% SZS status Started for HL411014+4.p
181832.33/24015.98	% SZS status GaveUp for HL411014+4.p
181832.33/24015.98	eprover: CPU time limit exceeded, terminating
181832.33/24015.98	% SZS status Ended for HL411014+4.p
181836.30/24016.49	% SZS status Started for HL411014+5.p
181836.30/24016.49	% SZS status GaveUp for HL411014+5.p
181836.30/24016.49	eprover: CPU time limit exceeded, terminating
181836.30/24016.49	% SZS status Ended for HL411014+5.p
181837.98/24016.72	% SZS status Started for HL411015+4.p
181837.98/24016.72	% SZS status GaveUp for HL411015+4.p
181837.98/24016.72	eprover: CPU time limit exceeded, terminating
181837.98/24016.72	% SZS status Ended for HL411015+4.p
181844.02/24017.48	% SZS status Started for HL411015+5.p
181844.02/24017.48	% SZS status GaveUp for HL411015+5.p
181844.02/24017.48	eprover: CPU time limit exceeded, terminating
181844.02/24017.48	% SZS status Ended for HL411015+5.p
181846.22/24017.76	% SZS status Started for HL411017+4.p
181846.22/24017.76	% SZS status GaveUp for HL411017+4.p
181846.22/24017.76	eprover: CPU time limit exceeded, terminating
181846.22/24017.76	% SZS status Ended for HL411017+4.p
181850.56/24018.34	% SZS status Started for HL411017+5.p
181850.56/24018.34	% SZS status GaveUp for HL411017+5.p
181850.56/24018.34	eprover: CPU time limit exceeded, terminating
181850.56/24018.34	% SZS status Ended for HL411017+5.p
181853.77/24018.66	% SZS status Started for HL411018+4.p
181853.77/24018.66	% SZS status GaveUp for HL411018+4.p
181853.77/24018.66	eprover: CPU time limit exceeded, terminating
181853.77/24018.66	% SZS status Ended for HL411018+4.p
181853.89/24018.70	% SZS status Started for HL411018+5.p
181853.89/24018.70	% SZS status GaveUp for HL411018+5.p
181853.89/24018.70	eprover: CPU time limit exceeded, terminating
181853.89/24018.70	% SZS status Ended for HL411018+5.p
181855.78/24019.01	% SZS status Started for HL411019+4.p
181855.78/24019.01	% SZS status GaveUp for HL411019+4.p
181855.78/24019.01	eprover: CPU time limit exceeded, terminating
181855.78/24019.01	% SZS status Ended for HL411019+4.p
181859.97/24019.52	% SZS status Started for HL411019+5.p
181859.97/24019.52	% SZS status GaveUp for HL411019+5.p
181859.97/24019.52	eprover: CPU time limit exceeded, terminating
181859.97/24019.52	% SZS status Ended for HL411019+5.p
181862.45/24019.76	% SZS status Started for HL411020+4.p
181862.45/24019.76	% SZS status GaveUp for HL411020+4.p
181862.45/24019.76	eprover: CPU time limit exceeded, terminating
181862.45/24019.76	% SZS status Ended for HL411020+4.p
181869.14/24020.58	% SZS status Started for HL411020+5.p
181869.14/24020.58	% SZS status GaveUp for HL411020+5.p
181869.14/24020.58	eprover: CPU time limit exceeded, terminating
181869.14/24020.58	% SZS status Ended for HL411020+5.p
181870.28/24020.79	% SZS status Started for HL411021+4.p
181870.28/24020.79	% SZS status GaveUp for HL411021+4.p
181870.28/24020.79	eprover: CPU time limit exceeded, terminating
181870.28/24020.79	% SZS status Ended for HL411021+4.p
181875.27/24021.37	% SZS status Started for HL411021+5.p
181875.27/24021.37	% SZS status GaveUp for HL411021+5.p
181875.27/24021.37	eprover: CPU time limit exceeded, terminating
181875.27/24021.37	% SZS status Ended for HL411021+5.p
181877.42/24021.69	% SZS status Started for HL411022+4.p
181877.42/24021.69	% SZS status GaveUp for HL411022+4.p
181877.42/24021.69	eprover: CPU time limit exceeded, terminating
181877.42/24021.69	% SZS status Ended for HL411022+4.p
181877.92/24021.73	% SZS status Started for HL411022+5.p
181877.92/24021.73	% SZS status GaveUp for HL411022+5.p
181877.92/24021.73	eprover: CPU time limit exceeded, terminating
181877.92/24021.73	% SZS status Ended for HL411022+5.p
181880.98/24022.17	% SZS status Started for HL411023+4.p
181880.98/24022.17	% SZS status GaveUp for HL411023+4.p
181880.98/24022.17	eprover: CPU time limit exceeded, terminating
181880.98/24022.17	% SZS status Ended for HL411023+4.p
181884.80/24022.56	% SZS status Started for HL411023+5.p
181884.80/24022.56	% SZS status GaveUp for HL411023+5.p
181884.80/24022.56	eprover: CPU time limit exceeded, terminating
181884.80/24022.56	% SZS status Ended for HL411023+5.p
181886.41/24022.78	% SZS status Started for HL411025+4.p
181886.41/24022.78	% SZS status GaveUp for HL411025+4.p
181886.41/24022.78	eprover: CPU time limit exceeded, terminating
181886.41/24022.78	% SZS status Ended for HL411025+4.p
181892.89/24023.62	% SZS status Started for HL411025+5.p
181892.89/24023.62	% SZS status GaveUp for HL411025+5.p
181892.89/24023.62	eprover: CPU time limit exceeded, terminating
181892.89/24023.62	% SZS status Ended for HL411025+5.p
181897.00/24023.82	% SZS status Started for HL411028+4.p
181897.00/24023.82	% SZS status GaveUp for HL411028+4.p
181897.00/24023.82	eprover: CPU time limit exceeded, terminating
181897.00/24023.82	% SZS status Ended for HL411028+4.p
181902.08/24024.41	% SZS status Started for HL411028+5.p
181902.08/24024.41	% SZS status GaveUp for HL411028+5.p
181902.08/24024.41	eprover: CPU time limit exceeded, terminating
181902.08/24024.41	% SZS status Ended for HL411028+5.p
181904.41/24024.72	% SZS status Started for HL411029+4.p
181904.41/24024.72	% SZS status GaveUp for HL411029+4.p
181904.41/24024.72	eprover: CPU time limit exceeded, terminating
181904.41/24024.72	% SZS status Ended for HL411029+4.p
181905.66/24024.90	% SZS status Started for HL411029+5.p
181905.66/24024.90	% SZS status GaveUp for HL411029+5.p
181905.66/24024.90	eprover: CPU time limit exceeded, terminating
181905.66/24024.90	% SZS status Ended for HL411029+5.p
181908.34/24025.20	% SZS status Started for HL411030+4.p
181908.34/24025.20	% SZS status GaveUp for HL411030+4.p
181908.34/24025.20	eprover: CPU time limit exceeded, terminating
181908.34/24025.20	% SZS status Ended for HL411030+4.p
181911.08/24025.59	% SZS status Started for HL411030+5.p
181911.08/24025.59	% SZS status GaveUp for HL411030+5.p
181911.08/24025.59	eprover: CPU time limit exceeded, terminating
181911.08/24025.59	% SZS status Ended for HL411030+5.p
181913.09/24025.82	% SZS status Started for HL411031+4.p
181913.09/24025.82	% SZS status GaveUp for HL411031+4.p
181913.09/24025.82	eprover: CPU time limit exceeded, terminating
181913.09/24025.82	% SZS status Ended for HL411031+4.p
181919.97/24026.65	% SZS status Started for HL411031+5.p
181919.97/24026.65	% SZS status GaveUp for HL411031+5.p
181919.97/24026.65	eprover: CPU time limit exceeded, terminating
181919.97/24026.65	% SZS status Ended for HL411031+5.p
181921.56/24026.85	% SZS status Started for HL411032+4.p
181921.56/24026.85	% SZS status GaveUp for HL411032+4.p
181921.56/24026.85	eprover: CPU time limit exceeded, terminating
181921.56/24026.85	% SZS status Ended for HL411032+4.p
181925.89/24027.44	% SZS status Started for HL411032+5.p
181925.89/24027.44	% SZS status GaveUp for HL411032+5.p
181925.89/24027.44	eprover: CPU time limit exceeded, terminating
181925.89/24027.44	% SZS status Ended for HL411032+5.p
181929.62/24027.87	% SZS status Started for HL411033+4.p
181929.62/24027.87	% SZS status GaveUp for HL411033+4.p
181929.62/24027.87	eprover: CPU time limit exceeded, terminating
181929.62/24027.87	% SZS status Ended for HL411033+4.p
181930.31/24027.97	% SZS status Started for HL411033+5.p
181930.31/24027.97	% SZS status GaveUp for HL411033+5.p
181930.31/24027.97	eprover: CPU time limit exceeded, terminating
181930.31/24027.97	% SZS status Ended for HL411033+5.p
181931.56/24028.24	% SZS status Started for HL411034+4.p
181931.56/24028.24	% SZS status GaveUp for HL411034+4.p
181931.56/24028.24	eprover: CPU time limit exceeded, terminating
181931.56/24028.24	% SZS status Ended for HL411034+4.p
181935.58/24028.62	% SZS status Started for HL411034+5.p
181935.58/24028.62	% SZS status GaveUp for HL411034+5.p
181935.58/24028.62	eprover: CPU time limit exceeded, terminating
181935.58/24028.62	% SZS status Ended for HL411034+5.p
181936.84/24028.85	% SZS status Started for HL411035+4.p
181936.84/24028.85	% SZS status GaveUp for HL411035+4.p
181936.84/24028.85	eprover: CPU time limit exceeded, terminating
181936.84/24028.85	% SZS status Ended for HL411035+4.p
181943.94/24029.68	% SZS status Started for HL411035+5.p
181943.94/24029.68	% SZS status GaveUp for HL411035+5.p
181943.94/24029.68	eprover: CPU time limit exceeded, terminating
181943.94/24029.68	% SZS status Ended for HL411035+5.p
181945.45/24029.88	% SZS status Started for HL411037+4.p
181945.45/24029.88	% SZS status GaveUp for HL411037+4.p
181945.45/24029.88	eprover: CPU time limit exceeded, terminating
181945.45/24029.88	% SZS status Ended for HL411037+4.p
181950.14/24030.48	% SZS status Started for HL411037+5.p
181950.14/24030.48	% SZS status GaveUp for HL411037+5.p
181950.14/24030.48	eprover: CPU time limit exceeded, terminating
181950.14/24030.48	% SZS status Ended for HL411037+5.p
181954.50/24031.00	% SZS status Started for HL411038+4.p
181954.50/24031.00	% SZS status GaveUp for HL411038+4.p
181954.50/24031.00	eprover: CPU time limit exceeded, terminating
181954.50/24031.00	% SZS status Ended for HL411038+4.p
181954.50/24031.00	% SZS status Started for HL411038+5.p
181954.50/24031.00	% SZS status GaveUp for HL411038+5.p
181954.50/24031.00	eprover: CPU time limit exceeded, terminating
181954.50/24031.00	% SZS status Ended for HL411038+5.p
181956.67/24031.26	% SZS status Started for HL411039+4.p
181956.67/24031.26	% SZS status GaveUp for HL411039+4.p
181956.67/24031.26	eprover: CPU time limit exceeded, terminating
181956.67/24031.26	% SZS status Ended for HL411039+4.p
181959.19/24031.65	% SZS status Started for HL411039+5.p
181959.19/24031.65	% SZS status GaveUp for HL411039+5.p
181959.19/24031.65	eprover: CPU time limit exceeded, terminating
181959.19/24031.65	% SZS status Ended for HL411039+5.p
181963.64/24031.89	% SZS status Started for HL411040+4.p
181963.64/24031.89	% SZS status GaveUp for HL411040+4.p
181963.64/24031.89	eprover: CPU time limit exceeded, terminating
181963.64/24031.89	% SZS status Ended for HL411040+4.p
181970.48/24032.72	% SZS status Started for HL411040+5.p
181970.48/24032.72	% SZS status GaveUp for HL411040+5.p
181970.48/24032.72	eprover: CPU time limit exceeded, terminating
181970.48/24032.72	% SZS status Ended for HL411040+5.p
181972.66/24033.04	% SZS status Started for HL411043+4.p
181972.66/24033.04	% SZS status GaveUp for HL411043+4.p
181972.66/24033.04	eprover: CPU time limit exceeded, terminating
181972.66/24033.04	% SZS status Ended for HL411043+4.p
181976.58/24033.51	% SZS status Started for HL411043+5.p
181976.58/24033.51	% SZS status GaveUp for HL411043+5.p
181976.58/24033.51	eprover: CPU time limit exceeded, terminating
181976.58/24033.51	% SZS status Ended for HL411043+5.p
181980.55/24034.03	% SZS status Started for HL411045+4.p
181980.55/24034.03	% SZS status GaveUp for HL411045+4.p
181980.55/24034.03	eprover: CPU time limit exceeded, terminating
181980.55/24034.03	% SZS status Ended for HL411045+4.p
181981.17/24034.04	% SZS status Started for HL411045+5.p
181981.17/24034.04	% SZS status GaveUp for HL411045+5.p
181981.17/24034.04	eprover: CPU time limit exceeded, terminating
181981.17/24034.04	% SZS status Ended for HL411045+5.p
181982.41/24034.29	% SZS status Started for HL411046+4.p
181982.41/24034.29	% SZS status GaveUp for HL411046+4.p
181982.41/24034.29	eprover: CPU time limit exceeded, terminating
181982.41/24034.29	% SZS status Ended for HL411046+4.p
181986.03/24034.68	% SZS status Started for HL411046+5.p
181986.03/24034.68	% SZS status GaveUp for HL411046+5.p
181986.03/24034.68	eprover: CPU time limit exceeded, terminating
181986.03/24034.68	% SZS status Ended for HL411046+5.p
181987.55/24034.92	% SZS status Started for HL411047+4.p
181987.55/24034.92	% SZS status GaveUp for HL411047+4.p
181987.55/24034.92	eprover: CPU time limit exceeded, terminating
181987.55/24034.92	% SZS status Ended for HL411047+4.p
181994.75/24035.75	% SZS status Started for HL411047+5.p
181994.75/24035.75	% SZS status GaveUp for HL411047+5.p
181994.75/24035.75	eprover: CPU time limit exceeded, terminating
181994.75/24035.75	% SZS status Ended for HL411047+5.p
181998.92/24036.29	% SZS status Started for HL411048+4.p
181998.92/24036.29	% SZS status GaveUp for HL411048+4.p
181998.92/24036.29	eprover: CPU time limit exceeded, terminating
181998.92/24036.29	% SZS status Ended for HL411048+4.p
182000.66/24036.54	% SZS status Started for HL411048+5.p
182000.66/24036.54	% SZS status GaveUp for HL411048+5.p
182000.66/24036.54	eprover: CPU time limit exceeded, terminating
182000.66/24036.54	% SZS status Ended for HL411048+5.p
182004.67/24037.05	% SZS status Started for HL411049+4.p
182004.67/24037.05	% SZS status GaveUp for HL411049+4.p
182004.67/24037.05	eprover: CPU time limit exceeded, terminating
182004.67/24037.05	% SZS status Ended for HL411049+4.p
182005.11/24037.07	% SZS status Started for HL411049+5.p
182005.11/24037.07	% SZS status GaveUp for HL411049+5.p
182005.11/24037.07	eprover: CPU time limit exceeded, terminating
182005.11/24037.07	% SZS status Ended for HL411049+5.p
182006.72/24037.32	% SZS status Started for HL411050+4.p
182006.72/24037.32	% SZS status GaveUp for HL411050+4.p
182006.72/24037.32	eprover: CPU time limit exceeded, terminating
182006.72/24037.32	% SZS status Ended for HL411050+4.p
182009.69/24037.71	% SZS status Started for HL411050+5.p
182009.69/24037.71	% SZS status GaveUp for HL411050+5.p
182009.69/24037.71	eprover: CPU time limit exceeded, terminating
182009.69/24037.71	% SZS status Ended for HL411050+5.p
182011.52/24037.96	% SZS status Started for HL411052+4.p
182011.52/24037.96	% SZS status GaveUp for HL411052+4.p
182011.52/24037.96	eprover: CPU time limit exceeded, terminating
182011.52/24037.96	% SZS status Ended for HL411052+4.p
182019.45/24038.90	% SZS status Started for HL411052+5.p
182019.45/24038.90	% SZS status GaveUp for HL411052+5.p
182019.45/24038.90	eprover: CPU time limit exceeded, terminating
182019.45/24038.90	% SZS status Ended for HL411052+5.p
182022.14/24039.31	% SZS status Started for HL411053+4.p
182022.14/24039.31	% SZS status GaveUp for HL411053+4.p
182022.14/24039.31	eprover: CPU time limit exceeded, terminating
182022.14/24039.31	% SZS status Ended for HL411053+4.p
182024.70/24039.58	% SZS status Started for HL411053+5.p
182024.70/24039.58	% SZS status GaveUp for HL411053+5.p
182024.70/24039.58	eprover: CPU time limit exceeded, terminating
182024.70/24039.58	% SZS status Ended for HL411053+5.p
182028.91/24040.08	% SZS status Started for HL411054+4.p
182028.91/24040.08	% SZS status GaveUp for HL411054+4.p
182028.91/24040.08	eprover: CPU time limit exceeded, terminating
182028.91/24040.08	% SZS status Ended for HL411054+4.p
182028.91/24040.10	% SZS status Started for HL411054+5.p
182028.91/24040.10	% SZS status GaveUp for HL411054+5.p
182028.91/24040.10	eprover: CPU time limit exceeded, terminating
182028.91/24040.10	% SZS status Ended for HL411054+5.p
182030.52/24040.35	% SZS status Started for HL411055+4.p
182030.52/24040.35	% SZS status GaveUp for HL411055+4.p
182030.52/24040.35	eprover: CPU time limit exceeded, terminating
182030.52/24040.35	% SZS status Ended for HL411055+4.p
182034.48/24040.78	% SZS status Started for HL411055+5.p
182034.48/24040.78	% SZS status GaveUp for HL411055+5.p
182034.48/24040.78	eprover: CPU time limit exceeded, terminating
182034.48/24040.78	% SZS status Ended for HL411055+5.p
182036.62/24041.08	% SZS status Started for HL411056+4.p
182036.62/24041.08	% SZS status GaveUp for HL411056+4.p
182036.62/24041.08	eprover: CPU time limit exceeded, terminating
182036.62/24041.08	% SZS status Ended for HL411056+4.p
182043.22/24041.94	% SZS status Started for HL411056+5.p
182043.22/24041.94	% SZS status GaveUp for HL411056+5.p
182043.22/24041.94	eprover: CPU time limit exceeded, terminating
182043.22/24041.94	% SZS status Ended for HL411056+5.p
182046.75/24042.34	% SZS status Started for HL411057+4.p
182046.75/24042.34	% SZS status GaveUp for HL411057+4.p
182046.75/24042.34	eprover: CPU time limit exceeded, terminating
182046.75/24042.34	% SZS status Ended for HL411057+4.p
182048.86/24042.61	% SZS status Started for HL411057+5.p
182048.86/24042.61	% SZS status GaveUp for HL411057+5.p
182048.86/24042.61	eprover: CPU time limit exceeded, terminating
182048.86/24042.61	% SZS status Ended for HL411057+5.p
182052.86/24043.11	% SZS status Started for HL411059+4.p
182052.86/24043.11	% SZS status GaveUp for HL411059+4.p
182052.86/24043.11	eprover: CPU time limit exceeded, terminating
182052.86/24043.11	% SZS status Ended for HL411059+4.p
182052.86/24043.14	% SZS status Started for HL411059+5.p
182052.86/24043.14	% SZS status GaveUp for HL411059+5.p
182052.86/24043.14	eprover: CPU time limit exceeded, terminating
182052.86/24043.14	% SZS status Ended for HL411059+5.p
182055.45/24043.49	% SZS status Started for HL411060+4.p
182055.45/24043.49	% SZS status GaveUp for HL411060+4.p
182055.45/24043.49	eprover: CPU time limit exceeded, terminating
182055.45/24043.49	% SZS status Ended for HL411060+4.p
182058.28/24043.81	% SZS status Started for HL411060+5.p
182058.28/24043.81	% SZS status GaveUp for HL411060+5.p
182058.28/24043.81	eprover: CPU time limit exceeded, terminating
182058.28/24043.81	% SZS status Ended for HL411060+5.p
182060.84/24044.11	% SZS status Started for HL411063+4.p
182060.84/24044.11	% SZS status GaveUp for HL411063+4.p
182060.84/24044.11	eprover: CPU time limit exceeded, terminating
182060.84/24044.11	% SZS status Ended for HL411063+4.p
182067.38/24044.97	% SZS status Started for HL411063+5.p
182067.38/24044.97	% SZS status GaveUp for HL411063+5.p
182067.38/24044.97	eprover: CPU time limit exceeded, terminating
182067.38/24044.97	% SZS status Ended for HL411063+5.p
182070.50/24045.37	% SZS status Started for HL411064+4.p
182070.50/24045.37	% SZS status GaveUp for HL411064+4.p
182070.50/24045.37	eprover: CPU time limit exceeded, terminating
182070.50/24045.37	% SZS status Ended for HL411064+4.p
182072.66/24045.64	% SZS status Started for HL411064+5.p
182072.66/24045.64	% SZS status GaveUp for HL411064+5.p
182072.66/24045.64	eprover: CPU time limit exceeded, terminating
182072.66/24045.64	% SZS status Ended for HL411064+5.p
182077.12/24046.14	% SZS status Started for HL411067+4.p
182077.12/24046.14	% SZS status GaveUp for HL411067+4.p
182077.12/24046.14	eprover: CPU time limit exceeded, terminating
182077.12/24046.14	% SZS status Ended for HL411067+4.p
182078.09/24046.27	% SZS status Started for HL411067+5.p
182078.09/24046.27	% SZS status GaveUp for HL411067+5.p
182078.09/24046.27	eprover: CPU time limit exceeded, terminating
182078.09/24046.27	% SZS status Ended for HL411067+5.p
182079.75/24046.52	% SZS status Started for HL411068+4.p
182079.75/24046.52	% SZS status GaveUp for HL411068+4.p
182079.75/24046.52	eprover: CPU time limit exceeded, terminating
182079.75/24046.52	% SZS status Ended for HL411068+4.p
182085.23/24047.15	% SZS status Started for HL411069+4.p
182085.23/24047.15	% SZS status GaveUp for HL411069+4.p
182085.23/24047.15	eprover: CPU time limit exceeded, terminating
182085.23/24047.15	% SZS status Ended for HL411069+4.p
182094.97/24048.44	% SZS status Started for HL411072+4.p
182094.97/24048.44	% SZS status GaveUp for HL411072+4.p
182094.97/24048.44	eprover: CPU time limit exceeded, terminating
182094.97/24048.44	% SZS status Ended for HL411072+4.p
182100.97/24049.16	% SZS status Started for HL411073+4.p
182100.97/24049.16	% SZS status GaveUp for HL411073+4.p
182100.97/24049.16	eprover: CPU time limit exceeded, terminating
182100.97/24049.16	% SZS status Ended for HL411073+4.p
182104.53/24049.58	% SZS status Started for HL411074+4.p
182104.53/24049.58	% SZS status GaveUp for HL411074+4.p
182104.53/24049.58	eprover: CPU time limit exceeded, terminating
182104.53/24049.58	% SZS status Ended for HL411074+4.p
182119.23/24051.46	% SZS status Started for HL411075+4.p
182119.23/24051.46	% SZS status GaveUp for HL411075+4.p
182119.23/24051.46	eprover: CPU time limit exceeded, terminating
182119.23/24051.46	% SZS status Ended for HL411075+4.p
182128.53/24052.62	% SZS status Started for HL411076+4.p
182128.53/24052.62	% SZS status GaveUp for HL411076+4.p
182128.53/24052.62	eprover: CPU time limit exceeded, terminating
182128.53/24052.62	% SZS status Ended for HL411076+4.p
182145.23/24054.77	% SZS status Started for HL411068+5.p
182145.23/24054.77	% SZS status GaveUp for HL411068+5.p
182145.23/24054.77	eprover: CPU time limit exceeded, terminating
182145.23/24054.77	% SZS status Ended for HL411068+5.p
182152.70/24055.63	% SZS status Started for HL411069+5.p
182152.70/24055.63	% SZS status GaveUp for HL411069+5.p
182152.70/24055.63	eprover: CPU time limit exceeded, terminating
182152.70/24055.63	% SZS status Ended for HL411069+5.p
182152.70/24055.73	% SZS status Started for HL411078+4.p
182152.70/24055.73	% SZS status GaveUp for HL411078+4.p
182152.70/24055.73	eprover: CPU time limit exceeded, terminating
182152.70/24055.73	% SZS status Ended for HL411078+4.p
182154.72/24056.18	% SZS status Started for HL411072+5.p
182154.72/24056.18	% SZS status GaveUp for HL411072+5.p
182154.72/24056.18	eprover: CPU time limit exceeded, terminating
182154.72/24056.18	% SZS status Ended for HL411072+5.p
182162.50/24056.91	% SZS status Started for HL411073+5.p
182162.50/24056.91	% SZS status GaveUp for HL411073+5.p
182162.50/24056.91	eprover: CPU time limit exceeded, terminating
182162.50/24056.91	% SZS status Ended for HL411073+5.p
182169.02/24057.76	% SZS status Started for HL411074+5.p
182169.02/24057.76	% SZS status GaveUp for HL411074+5.p
182169.02/24057.76	eprover: CPU time limit exceeded, terminating
182169.02/24057.76	% SZS status Ended for HL411074+5.p
182176.56/24058.69	% SZS status Started for HL411079+4.p
182176.56/24058.69	% SZS status GaveUp for HL411079+4.p
182176.56/24058.69	eprover: CPU time limit exceeded, terminating
182176.56/24058.69	% SZS status Ended for HL411079+4.p
182180.69/24059.21	% SZS status Started for HL411080+4.p
182180.69/24059.21	% SZS status GaveUp for HL411080+4.p
182180.69/24059.21	eprover: CPU time limit exceeded, terminating
182180.69/24059.21	% SZS status Ended for HL411080+4.p
182184.84/24059.72	% SZS status Started for HL411075+5.p
182184.84/24059.72	% SZS status GaveUp for HL411075+5.p
182184.84/24059.72	eprover: CPU time limit exceeded, terminating
182184.84/24059.72	% SZS status Ended for HL411075+5.p
182193.38/24060.80	% SZS status Started for HL411081+4.p
182193.38/24060.80	% SZS status GaveUp for HL411081+4.p
182193.38/24060.80	eprover: CPU time limit exceeded, terminating
182193.38/24060.80	% SZS status Ended for HL411081+4.p
182203.52/24062.07	% SZS status Started for HL411076+5.p
182203.52/24062.07	% SZS status GaveUp for HL411076+5.p
182203.52/24062.07	eprover: CPU time limit exceeded, terminating
182203.52/24062.07	% SZS status Ended for HL411076+5.p
182205.09/24062.23	% SZS status Started for HL411083+4.p
182205.09/24062.23	% SZS status GaveUp for HL411083+4.p
182205.09/24062.23	eprover: CPU time limit exceeded, terminating
182205.09/24062.23	% SZS status Ended for HL411083+4.p
182217.12/24063.86	% SZS status Started for HL411084+4.p
182217.12/24063.86	% SZS status GaveUp for HL411084+4.p
182217.12/24063.86	eprover: CPU time limit exceeded, terminating
182217.12/24063.86	% SZS status Ended for HL411084+4.p
182229.53/24065.34	% SZS status Started for HL411085+4.p
182229.53/24065.34	% SZS status GaveUp for HL411085+4.p
182229.53/24065.34	eprover: CPU time limit exceeded, terminating
182229.53/24065.34	% SZS status Ended for HL411085+4.p
182229.88/24065.45	% SZS status Started for HL411078+5.p
182229.88/24065.45	% SZS status GaveUp for HL411078+5.p
182229.88/24065.45	eprover: CPU time limit exceeded, terminating
182229.88/24065.45	% SZS status Ended for HL411078+5.p
182237.81/24066.40	% SZS status Started for HL411079+5.p
182237.81/24066.40	% SZS status GaveUp for HL411079+5.p
182237.81/24066.40	eprover: CPU time limit exceeded, terminating
182237.81/24066.40	% SZS status Ended for HL411079+5.p
182246.89/24067.60	% SZS status Started for HL411080+5.p
182246.89/24067.60	% SZS status GaveUp for HL411080+5.p
182246.89/24067.60	eprover: CPU time limit exceeded, terminating
182246.89/24067.60	% SZS status Ended for HL411080+5.p
182253.39/24068.38	% SZS status Started for HL411086+4.p
182253.39/24068.38	% SZS status GaveUp for HL411086+4.p
182253.39/24068.38	eprover: CPU time limit exceeded, terminating
182253.39/24068.38	% SZS status Ended for HL411086+4.p
182261.77/24069.40	% SZS status Started for HL411081+5.p
182261.77/24069.40	% SZS status GaveUp for HL411081+5.p
182261.77/24069.40	eprover: CPU time limit exceeded, terminating
182261.77/24069.40	% SZS status Ended for HL411081+5.p
182262.20/24069.49	% SZS status Started for HL411087+4.p
182262.20/24069.49	% SZS status GaveUp for HL411087+4.p
182262.20/24069.49	eprover: CPU time limit exceeded, terminating
182262.20/24069.49	% SZS status Ended for HL411087+4.p
182269.06/24070.39	% SZS status Started for HL411083+5.p
182269.06/24070.39	% SZS status GaveUp for HL411083+5.p
182269.06/24070.39	eprover: CPU time limit exceeded, terminating
182269.06/24070.39	% SZS status Ended for HL411083+5.p
182277.25/24071.44	% SZS status Started for HL411088+4.p
182277.25/24071.44	% SZS status GaveUp for HL411088+4.p
182277.25/24071.44	eprover: CPU time limit exceeded, terminating
182277.25/24071.44	% SZS status Ended for HL411088+4.p
182286.83/24072.60	% SZS status Started for HL411089+4.p
182286.83/24072.60	% SZS status GaveUp for HL411089+4.p
182286.83/24072.60	eprover: CPU time limit exceeded, terminating
182286.83/24072.60	% SZS status Ended for HL411089+4.p
182289.08/24072.87	% SZS status Started for HL411084+5.p
182289.08/24072.87	% SZS status GaveUp for HL411084+5.p
182289.08/24072.87	eprover: CPU time limit exceeded, terminating
182289.08/24072.87	% SZS status Ended for HL411084+5.p
182301.34/24074.44	% SZS status Started for HL411085+5.p
182301.34/24074.44	% SZS status GaveUp for HL411085+5.p
182301.34/24074.44	eprover: CPU time limit exceeded, terminating
182301.34/24074.44	% SZS status Ended for HL411085+5.p
182302.23/24074.51	% SZS status Started for HL411090+4.p
182302.23/24074.51	% SZS status GaveUp for HL411090+4.p
182302.23/24074.51	eprover: CPU time limit exceeded, terminating
182302.23/24074.51	% SZS status Ended for HL411090+4.p
182312.52/24075.91	% SZS status Started for HL411093+4.p
182312.52/24075.91	% SZS status GaveUp for HL411093+4.p
182312.52/24075.91	eprover: CPU time limit exceeded, terminating
182312.52/24075.91	% SZS status Ended for HL411093+4.p
182314.95/24076.19	% SZS status Started for HL411086+5.p
182314.95/24076.19	% SZS status GaveUp for HL411086+5.p
182314.95/24076.19	eprover: CPU time limit exceeded, terminating
182314.95/24076.19	% SZS status Ended for HL411086+5.p
182327.41/24077.67	% SZS status Started for HL411094+4.p
182327.41/24077.67	% SZS status GaveUp for HL411094+4.p
182327.41/24077.67	eprover: CPU time limit exceeded, terminating
182327.41/24077.67	% SZS status Ended for HL411094+4.p
182333.84/24078.47	% SZS status Started for HL411087+5.p
182333.84/24078.47	% SZS status GaveUp for HL411087+5.p
182333.84/24078.47	eprover: CPU time limit exceeded, terminating
182333.84/24078.47	% SZS status Ended for HL411087+5.p
182339.45/24079.24	% SZS status Started for HL411095+4.p
182339.45/24079.24	% SZS status GaveUp for HL411095+4.p
182339.45/24079.24	eprover: CPU time limit exceeded, terminating
182339.45/24079.24	% SZS status Ended for HL411095+4.p
182346.67/24080.06	% SZS status Started for HL411088+5.p
182346.67/24080.06	% SZS status GaveUp for HL411088+5.p
182346.67/24080.06	eprover: CPU time limit exceeded, terminating
182346.67/24080.06	% SZS status Ended for HL411088+5.p
182353.97/24081.04	% SZS status Started for HL411089+5.p
182353.97/24081.04	% SZS status GaveUp for HL411089+5.p
182353.97/24081.04	eprover: CPU time limit exceeded, terminating
182353.97/24081.04	% SZS status Ended for HL411089+5.p
182358.30/24081.52	% SZS status Started for HL411096+4.p
182358.30/24081.52	% SZS status GaveUp for HL411096+4.p
182358.30/24081.52	eprover: CPU time limit exceeded, terminating
182358.30/24081.52	% SZS status Ended for HL411096+4.p
182371.42/24083.19	% SZS status Started for HL411097+4.p
182371.42/24083.19	% SZS status GaveUp for HL411097+4.p
182371.42/24083.19	eprover: CPU time limit exceeded, terminating
182371.42/24083.19	% SZS status Ended for HL411097+4.p
182376.53/24083.85	% SZS status Started for HL411090+5.p
182376.53/24083.85	% SZS status GaveUp for HL411090+5.p
182376.53/24083.85	eprover: CPU time limit exceeded, terminating
182376.53/24083.85	% SZS status Ended for HL411090+5.p
182382.45/24084.57	% SZS status Started for HL411099+4.p
182382.45/24084.57	% SZS status GaveUp for HL411099+4.p
182382.45/24084.57	eprover: CPU time limit exceeded, terminating
182382.45/24084.57	% SZS status Ended for HL411099+4.p
182386.12/24085.13	% SZS status Started for HL411093+5.p
182386.12/24085.13	% SZS status GaveUp for HL411093+5.p
182386.12/24085.13	eprover: CPU time limit exceeded, terminating
182386.12/24085.13	% SZS status Ended for HL411093+5.p
182398.95/24086.67	% SZS status Started for HL411094+5.p
182398.95/24086.67	% SZS status GaveUp for HL411094+5.p
182398.95/24086.67	eprover: CPU time limit exceeded, terminating
182398.95/24086.67	% SZS status Ended for HL411094+5.p
182401.45/24086.97	% SZS status Started for HL411100+4.p
182401.45/24086.97	% SZS status GaveUp for HL411100+4.p
182401.45/24086.97	eprover: CPU time limit exceeded, terminating
182401.45/24086.97	% SZS status Ended for HL411100+4.p
182407.95/24087.86	% SZS status Started for HL411095+5.p
182407.95/24087.86	% SZS status GaveUp for HL411095+5.p
182407.95/24087.86	eprover: CPU time limit exceeded, terminating
182407.95/24087.86	% SZS status Ended for HL411095+5.p
182410.67/24088.17	% SZS status Started for HL411102+4.p
182410.67/24088.17	% SZS status GaveUp for HL411102+4.p
182410.67/24088.17	eprover: CPU time limit exceeded, terminating
182410.67/24088.17	% SZS status Ended for HL411102+4.p
182426.53/24089.84	% SZS status Started for HL411096+5.p
182426.53/24089.84	% SZS status GaveUp for HL411096+5.p
182426.53/24089.84	eprover: CPU time limit exceeded, terminating
182426.53/24089.84	% SZS status Ended for HL411096+5.p
182428.50/24090.10	% SZS status Started for HL411103+4.p
182428.50/24090.10	% SZS status GaveUp for HL411103+4.p
182428.50/24090.10	eprover: CPU time limit exceeded, terminating
182428.50/24090.10	% SZS status Ended for HL411103+4.p
182437.17/24091.20	% SZS status Started for HL411104+4.p
182437.17/24091.20	% SZS status GaveUp for HL411104+4.p
182437.17/24091.20	eprover: CPU time limit exceeded, terminating
182437.17/24091.20	% SZS status Ended for HL411104+4.p
182440.98/24091.66	% SZS status Started for HL411097+5.p
182440.98/24091.66	% SZS status GaveUp for HL411097+5.p
182440.98/24091.66	eprover: CPU time limit exceeded, terminating
182440.98/24091.66	% SZS status Ended for HL411097+5.p
182452.73/24093.15	% SZS status Started for HL411105+4.p
182452.73/24093.15	% SZS status GaveUp for HL411105+4.p
182452.73/24093.15	eprover: CPU time limit exceeded, terminating
182452.73/24093.15	% SZS status Ended for HL411105+4.p
182461.08/24093.91	% SZS status Started for HL411099+5.p
182461.08/24093.91	% SZS status GaveUp for HL411099+5.p
182461.08/24093.91	eprover: CPU time limit exceeded, terminating
182461.08/24093.91	% SZS status Ended for HL411099+5.p
182468.19/24094.72	% SZS status Started for HL411106+4.p
182468.19/24094.72	% SZS status GaveUp for HL411106+4.p
182468.19/24094.72	eprover: CPU time limit exceeded, terminating
182468.19/24094.72	% SZS status Ended for HL411106+4.p
182472.30/24095.27	% SZS status Started for HL411100+5.p
182472.30/24095.27	% SZS status GaveUp for HL411100+5.p
182472.30/24095.27	eprover: CPU time limit exceeded, terminating
182472.30/24095.27	% SZS status Ended for HL411100+5.p
182485.80/24096.95	% SZS status Started for HL411107+4.p
182485.80/24096.95	% SZS status GaveUp for HL411107+4.p
182485.80/24096.95	eprover: CPU time limit exceeded, terminating
182485.80/24096.95	% SZS status Ended for HL411107+4.p
182488.64/24097.38	% SZS status Started for HL411102+5.p
182488.64/24097.38	% SZS status GaveUp for HL411102+5.p
182488.64/24097.38	eprover: CPU time limit exceeded, terminating
182488.64/24097.38	% SZS status Ended for HL411102+5.p
182496.59/24098.33	% SZS status Started for HL411108+4.p
182496.59/24098.33	% SZS status GaveUp for HL411108+4.p
182496.59/24098.33	eprover: CPU time limit exceeded, terminating
182496.59/24098.33	% SZS status Ended for HL411108+4.p
182498.61/24098.58	% SZS status Started for HL411103+5.p
182498.61/24098.58	% SZS status GaveUp for HL411103+5.p
182498.61/24098.58	eprover: CPU time limit exceeded, terminating
182498.61/24098.58	% SZS status Ended for HL411103+5.p
182509.56/24100.02	% SZS status Started for HL411108+5.p
182509.56/24100.02	% SZS status GaveUp for HL411108+5.p
182509.56/24100.02	eprover: CPU time limit exceeded, terminating
182509.56/24100.02	% SZS status Ended for HL411108+5.p
182513.14/24100.44	% SZS status Started for HL411110+4.p
182513.14/24100.44	% SZS status GaveUp for HL411110+4.p
182513.14/24100.44	eprover: CPU time limit exceeded, terminating
182513.14/24100.44	% SZS status Ended for HL411110+4.p
182514.31/24100.59	% SZS status Started for HL411104+5.p
182514.31/24100.59	% SZS status GaveUp for HL411104+5.p
182514.31/24100.59	eprover: CPU time limit exceeded, terminating
182514.31/24100.59	% SZS status Ended for HL411104+5.p
182522.94/24101.68	% SZS status Started for HL411111+4.p
182522.94/24101.68	% SZS status GaveUp for HL411111+4.p
182522.94/24101.68	eprover: CPU time limit exceeded, terminating
182522.94/24101.68	% SZS status Ended for HL411111+4.p
182524.77/24101.88	% SZS status Started for HL411105+5.p
182524.77/24101.88	% SZS status GaveUp for HL411105+5.p
182524.77/24101.88	eprover: CPU time limit exceeded, terminating
182524.77/24101.88	% SZS status Ended for HL411105+5.p
182537.44/24103.46	% SZS status Started for HL411112+4.p
182537.44/24103.46	% SZS status GaveUp for HL411112+4.p
182537.44/24103.46	eprover: CPU time limit exceeded, terminating
182537.44/24103.46	% SZS status Ended for HL411112+4.p
182540.11/24103.91	% SZS status Started for HL411106+5.p
182540.11/24103.91	% SZS status GaveUp for HL411106+5.p
182540.11/24103.91	eprover: CPU time limit exceeded, terminating
182540.11/24103.91	% SZS status Ended for HL411106+5.p
182547.86/24104.79	% SZS status Started for HL411113+4.p
182547.86/24104.79	% SZS status GaveUp for HL411113+4.p
182547.86/24104.79	eprover: CPU time limit exceeded, terminating
182547.86/24104.79	% SZS status Ended for HL411113+4.p
182552.70/24105.40	% SZS status Started for HL411107+5.p
182552.70/24105.40	% SZS status GaveUp for HL411107+5.p
182552.70/24105.40	eprover: CPU time limit exceeded, terminating
182552.70/24105.40	% SZS status Ended for HL411107+5.p
182561.80/24106.54	% SZS status Started for HL411114+4.p
182561.80/24106.54	% SZS status GaveUp for HL411114+4.p
182561.80/24106.54	eprover: CPU time limit exceeded, terminating
182561.80/24106.54	% SZS status Ended for HL411114+4.p
182572.22/24107.90	% SZS status Started for HL411115+4.p
182572.22/24107.90	% SZS status GaveUp for HL411115+4.p
182572.22/24107.90	eprover: CPU time limit exceeded, terminating
182572.22/24107.90	% SZS status Ended for HL411115+4.p
182579.95/24108.94	% SZS status Started for HL411110+5.p
182579.95/24108.94	% SZS status GaveUp for HL411110+5.p
182579.95/24108.94	eprover: CPU time limit exceeded, terminating
182579.95/24108.94	% SZS status Ended for HL411110+5.p
182585.84/24109.58	% SZS status Started for HL411116+4.p
182585.84/24109.58	% SZS status GaveUp for HL411116+4.p
182585.84/24109.58	eprover: CPU time limit exceeded, terminating
182585.84/24109.58	% SZS status Ended for HL411116+4.p
182593.16/24110.59	% SZS status Started for HL411111+5.p
182593.16/24110.59	% SZS status GaveUp for HL411111+5.p
182593.16/24110.59	eprover: CPU time limit exceeded, terminating
182593.16/24110.59	% SZS status Ended for HL411111+5.p
182599.55/24111.30	% SZS status Started for HL411112+5.p
182599.55/24111.30	% SZS status GaveUp for HL411112+5.p
182599.55/24111.30	eprover: CPU time limit exceeded, terminating
182599.55/24111.30	% SZS status Ended for HL411112+5.p
182605.58/24112.10	% SZS status Started for HL411117+4.p
182605.58/24112.10	% SZS status GaveUp for HL411117+4.p
182605.58/24112.10	eprover: CPU time limit exceeded, terminating
182605.58/24112.10	% SZS status Ended for HL411117+4.p
182610.05/24112.72	% SZS status Started for HL411113+5.p
182610.05/24112.72	% SZS status GaveUp for HL411113+5.p
182610.05/24112.72	eprover: CPU time limit exceeded, terminating
182610.05/24112.72	% SZS status Ended for HL411113+5.p
182617.97/24113.68	% SZS status Started for HL411119+4.p
182617.97/24113.68	% SZS status GaveUp for HL411119+4.p
182617.97/24113.68	eprover: CPU time limit exceeded, terminating
182617.97/24113.68	% SZS status Ended for HL411119+4.p
182626.45/24114.73	% SZS status Started for HL411114+5.p
182626.45/24114.73	% SZS status GaveUp for HL411114+5.p
182626.45/24114.73	eprover: CPU time limit exceeded, terminating
182626.45/24114.73	% SZS status Ended for HL411114+5.p
182629.41/24115.13	% SZS status Started for HL411120+4.p
182629.41/24115.13	% SZS status GaveUp for HL411120+4.p
182629.41/24115.13	eprover: CPU time limit exceeded, terminating
182629.41/24115.13	% SZS status Ended for HL411120+4.p
182641.00/24116.62	% SZS status Started for HL411115+5.p
182641.00/24116.62	% SZS status GaveUp for HL411115+5.p
182641.00/24116.62	eprover: CPU time limit exceeded, terminating
182641.00/24116.62	% SZS status Ended for HL411115+5.p
182642.17/24116.73	% SZS status Started for HL411121+4.p
182642.17/24116.73	% SZS status GaveUp for HL411121+4.p
182642.17/24116.73	eprover: CPU time limit exceeded, terminating
182642.17/24116.73	% SZS status Ended for HL411121+4.p
182653.50/24118.15	% SZS status Started for HL411122+4.p
182653.50/24118.15	% SZS status GaveUp for HL411122+4.p
182653.50/24118.15	eprover: CPU time limit exceeded, terminating
182653.50/24118.15	% SZS status Ended for HL411122+4.p
182656.61/24118.51	% SZS status Started for HL411116+5.p
182656.61/24118.51	% SZS status GaveUp for HL411116+5.p
182656.61/24118.51	eprover: CPU time limit exceeded, terminating
182656.61/24118.51	% SZS status Ended for HL411116+5.p
182666.36/24119.77	% SZS status Started for HL411123+4.p
182666.36/24119.77	% SZS status GaveUp for HL411123+4.p
182666.36/24119.77	eprover: CPU time limit exceeded, terminating
182666.36/24119.77	% SZS status Ended for HL411123+4.p
182670.59/24120.31	% SZS status Started for HL411117+5.p
182670.59/24120.31	% SZS status GaveUp for HL411117+5.p
182670.59/24120.31	eprover: CPU time limit exceeded, terminating
182670.59/24120.31	% SZS status Ended for HL411117+5.p
182680.66/24121.56	% SZS status Started for HL411126+4.p
182680.66/24121.56	% SZS status GaveUp for HL411126+4.p
182680.66/24121.56	eprover: CPU time limit exceeded, terminating
182680.66/24121.56	% SZS status Ended for HL411126+4.p
182683.48/24121.91	% SZS status Started for HL411119+5.p
182683.48/24121.91	% SZS status GaveUp for HL411119+5.p
182683.48/24121.91	eprover: CPU time limit exceeded, terminating
182683.48/24121.91	% SZS status Ended for HL411119+5.p
182695.27/24123.41	% SZS status Started for HL411128+4.p
182695.27/24123.41	% SZS status GaveUp for HL411128+4.p
182695.27/24123.41	eprover: CPU time limit exceeded, terminating
182695.27/24123.41	% SZS status Ended for HL411128+4.p
182697.19/24123.69	% SZS status Started for HL411120+5.p
182697.19/24123.69	% SZS status GaveUp for HL411120+5.p
182697.19/24123.69	eprover: CPU time limit exceeded, terminating
182697.19/24123.69	% SZS status Ended for HL411120+5.p
182707.12/24125.01	% SZS status Started for HL411129+4.p
182707.12/24125.01	% SZS status GaveUp for HL411129+4.p
182707.12/24125.01	eprover: CPU time limit exceeded, terminating
182707.12/24125.01	% SZS status Ended for HL411129+4.p
182713.42/24125.76	% SZS status Started for HL411121+5.p
182713.42/24125.76	% SZS status GaveUp for HL411121+5.p
182713.42/24125.76	eprover: CPU time limit exceeded, terminating
182713.42/24125.76	% SZS status Ended for HL411121+5.p
182721.75/24126.72	% SZS status Started for HL411131+4.p
182721.75/24126.72	% SZS status GaveUp for HL411131+4.p
182721.75/24126.72	eprover: CPU time limit exceeded, terminating
182721.75/24126.72	% SZS status Ended for HL411131+4.p
182727.92/24127.63	% SZS status Started for HL411122+5.p
182727.92/24127.63	% SZS status GaveUp for HL411122+5.p
182727.92/24127.63	eprover: CPU time limit exceeded, terminating
182727.92/24127.63	% SZS status Ended for HL411122+5.p
182736.97/24128.79	% SZS status Started for HL411132+4.p
182736.97/24128.79	% SZS status GaveUp for HL411132+4.p
182736.97/24128.79	eprover: CPU time limit exceeded, terminating
182736.97/24128.79	% SZS status Ended for HL411132+4.p
182740.22/24129.10	% SZS status Started for HL411123+5.p
182740.22/24129.10	% SZS status GaveUp for HL411123+5.p
182740.22/24129.10	eprover: CPU time limit exceeded, terminating
182740.22/24129.10	% SZS status Ended for HL411123+5.p
182745.62/24129.78	% SZS status Started for HL411132+5.p
182745.62/24129.78	% SZS status GaveUp for HL411132+5.p
182745.62/24129.78	eprover: CPU time limit exceeded, terminating
182745.62/24129.78	% SZS status Ended for HL411132+5.p
182750.56/24130.35	% SZS status Started for HL411126+5.p
182750.56/24130.35	% SZS status GaveUp for HL411126+5.p
182750.56/24130.35	eprover: CPU time limit exceeded, terminating
182750.56/24130.35	% SZS status Ended for HL411126+5.p
182752.92/24130.69	% SZS status Started for HL411134+4.p
182752.92/24130.69	% SZS status GaveUp for HL411134+4.p
182752.92/24130.69	eprover: CPU time limit exceeded, terminating
182752.92/24130.69	% SZS status Ended for HL411134+4.p
182764.05/24132.12	% SZS status Started for HL411135+4.p
182764.05/24132.12	% SZS status GaveUp for HL411135+4.p
182764.05/24132.12	eprover: CPU time limit exceeded, terminating
182764.05/24132.12	% SZS status Ended for HL411135+4.p
182766.25/24132.39	% SZS status Started for HL411128+5.p
182766.25/24132.39	% SZS status GaveUp for HL411128+5.p
182766.25/24132.39	eprover: CPU time limit exceeded, terminating
182766.25/24132.39	% SZS status Ended for HL411128+5.p
182773.72/24133.40	% SZS status Started for HL411136+4.p
182773.72/24133.40	% SZS status GaveUp for HL411136+4.p
182773.72/24133.40	eprover: CPU time limit exceeded, terminating
182773.72/24133.40	% SZS status Ended for HL411136+4.p
182779.05/24134.00	% SZS status Started for HL411129+5.p
182779.05/24134.00	% SZS status GaveUp for HL411129+5.p
182779.05/24134.00	eprover: CPU time limit exceeded, terminating
182779.05/24134.00	% SZS status Ended for HL411129+5.p
182788.53/24135.25	% SZS status Started for HL411137+4.p
182788.53/24135.25	% SZS status GaveUp for HL411137+4.p
182788.53/24135.25	eprover: CPU time limit exceeded, terminating
182788.53/24135.25	% SZS status Ended for HL411137+4.p
182793.50/24135.81	% SZS status Started for HL411131+5.p
182793.50/24135.81	% SZS status GaveUp for HL411131+5.p
182793.50/24135.81	eprover: CPU time limit exceeded, terminating
182793.50/24135.81	% SZS status Ended for HL411131+5.p
182798.78/24136.46	% SZS status Started for HL411138+4.p
182798.78/24136.46	% SZS status GaveUp for HL411138+4.p
182798.78/24136.46	eprover: CPU time limit exceeded, terminating
182798.78/24136.46	% SZS status Ended for HL411138+4.p
182813.56/24138.31	% SZS status Started for HL411139+4.p
182813.56/24138.31	% SZS status GaveUp for HL411139+4.p
182813.56/24138.31	eprover: CPU time limit exceeded, terminating
182813.56/24138.31	% SZS status Ended for HL411139+4.p
182821.58/24139.49	% SZS status Started for HL411140+4.p
182821.58/24139.49	% SZS status GaveUp for HL411140+4.p
182821.58/24139.49	eprover: CPU time limit exceeded, terminating
182821.58/24139.49	% SZS status Ended for HL411140+4.p
182823.17/24139.59	% SZS status Started for HL411134+5.p
182823.17/24139.59	% SZS status GaveUp for HL411134+5.p
182823.17/24139.59	eprover: CPU time limit exceeded, terminating
182823.17/24139.59	% SZS status Ended for HL411134+5.p
182829.78/24140.39	% SZS status Started for HL411135+5.p
182829.78/24140.39	% SZS status GaveUp for HL411135+5.p
182829.78/24140.39	eprover: CPU time limit exceeded, terminating
182829.78/24140.39	% SZS status Ended for HL411135+5.p
182837.20/24141.32	% SZS status Started for HL411136+5.p
182837.20/24141.32	% SZS status GaveUp for HL411136+5.p
182837.20/24141.32	eprover: CPU time limit exceeded, terminating
182837.20/24141.32	% SZS status Ended for HL411136+5.p
182847.03/24142.54	% SZS status Started for HL411141+4.p
182847.03/24142.54	% SZS status GaveUp for HL411141+4.p
182847.03/24142.54	eprover: CPU time limit exceeded, terminating
182847.03/24142.54	% SZS status Ended for HL411141+4.p
182850.86/24143.07	% SZS status Started for HL411137+5.p
182850.86/24143.07	% SZS status GaveUp for HL411137+5.p
182850.86/24143.07	eprover: CPU time limit exceeded, terminating
182850.86/24143.07	% SZS status Ended for HL411137+5.p
182852.86/24143.43	% SZS status Started for HL411142+4.p
182852.86/24143.43	% SZS status GaveUp for HL411142+4.p
182852.86/24143.43	eprover: CPU time limit exceeded, terminating
182852.86/24143.43	% SZS status Ended for HL411142+4.p
182864.61/24144.75	% SZS status Started for HL411138+5.p
182864.61/24144.75	% SZS status GaveUp for HL411138+5.p
182864.61/24144.75	eprover: CPU time limit exceeded, terminating
182864.61/24144.75	% SZS status Ended for HL411138+5.p
182871.17/24145.61	% SZS status Started for HL411143+4.p
182871.17/24145.61	% SZS status GaveUp for HL411143+4.p
182871.17/24145.61	eprover: CPU time limit exceeded, terminating
182871.17/24145.61	% SZS status Ended for HL411143+4.p
182877.73/24146.41	% SZS status Started for HL411139+5.p
182877.73/24146.41	% SZS status GaveUp for HL411139+5.p
182877.73/24146.41	eprover: CPU time limit exceeded, terminating
182877.73/24146.41	% SZS status Ended for HL411139+5.p
182878.28/24146.49	% SZS status Started for HL411144+4.p
182878.28/24146.49	% SZS status GaveUp for HL411144+4.p
182878.28/24146.49	eprover: CPU time limit exceeded, terminating
182878.28/24146.49	% SZS status Ended for HL411144+4.p
182895.56/24148.69	% SZS status Started for HL411146+4.p
182895.56/24148.69	% SZS status GaveUp for HL411146+4.p
182895.56/24148.69	eprover: CPU time limit exceeded, terminating
182895.56/24148.69	% SZS status Ended for HL411146+4.p
182900.41/24149.28	% SZS status Started for HL411140+5.p
182900.41/24149.28	% SZS status GaveUp for HL411140+5.p
182900.41/24149.28	eprover: CPU time limit exceeded, terminating
182900.41/24149.28	% SZS status Ended for HL411140+5.p
182901.94/24149.56	% SZS status Started for HL411149+4.p
182901.94/24149.56	% SZS status GaveUp for HL411149+4.p
182901.94/24149.56	eprover: CPU time limit exceeded, terminating
182901.94/24149.56	% SZS status Ended for HL411149+4.p
182906.64/24150.18	% SZS status Started for HL411141+5.p
182906.64/24150.18	% SZS status GaveUp for HL411141+5.p
182906.64/24150.18	eprover: CPU time limit exceeded, terminating
182906.64/24150.18	% SZS status Ended for HL411141+5.p
182921.86/24152.01	% SZS status Started for HL411142+5.p
182921.86/24152.01	% SZS status GaveUp for HL411142+5.p
182921.86/24152.01	eprover: CPU time limit exceeded, terminating
182921.86/24152.01	% SZS status Ended for HL411142+5.p
182924.19/24152.36	% SZS status Started for HL411150+4.p
182924.19/24152.36	% SZS status GaveUp for HL411150+4.p
182924.19/24152.36	eprover: CPU time limit exceeded, terminating
182924.19/24152.36	% SZS status Ended for HL411150+4.p
182931.67/24153.29	% SZS status Started for HL411151+4.p
182931.67/24153.29	% SZS status GaveUp for HL411151+4.p
182931.67/24153.29	eprover: CPU time limit exceeded, terminating
182931.67/24153.29	% SZS status Ended for HL411151+4.p
182936.91/24153.72	% SZS status Started for HL411143+5.p
182936.91/24153.72	% SZS status GaveUp for HL411143+5.p
182936.91/24153.72	eprover: CPU time limit exceeded, terminating
182936.91/24153.72	% SZS status Ended for HL411143+5.p
182948.44/24155.06	% SZS status Started for HL411151+5.p
182948.44/24155.06	% SZS status GaveUp for HL411151+5.p
182948.44/24155.06	eprover: CPU time limit exceeded, terminating
182948.44/24155.06	% SZS status Ended for HL411151+5.p
182952.22/24155.50	% SZS status Started for HL411152+4.p
182952.22/24155.50	% SZS status GaveUp for HL411152+4.p
182952.22/24155.50	eprover: CPU time limit exceeded, terminating
182952.22/24155.50	% SZS status Ended for HL411152+4.p
182952.55/24155.53	% SZS status Started for HL411144+5.p
182952.55/24155.53	% SZS status GaveUp for HL411144+5.p
182952.55/24155.53	eprover: CPU time limit exceeded, terminating
182952.55/24155.53	% SZS status Ended for HL411144+5.p
182961.95/24156.76	% SZS status Started for HL411153+4.p
182961.95/24156.76	% SZS status GaveUp for HL411153+4.p
182961.95/24156.76	eprover: CPU time limit exceeded, terminating
182961.95/24156.76	% SZS status Ended for HL411153+4.p
182964.47/24157.07	% SZS status Started for HL411146+5.p
182964.47/24157.07	% SZS status GaveUp for HL411146+5.p
182964.47/24157.07	eprover: CPU time limit exceeded, terminating
182964.47/24157.07	% SZS status Ended for HL411146+5.p
182976.12/24158.54	% SZS status Started for HL411154+4.p
182976.12/24158.54	% SZS status GaveUp for HL411154+4.p
182976.12/24158.54	eprover: CPU time limit exceeded, terminating
182976.12/24158.54	% SZS status Ended for HL411154+4.p
182982.12/24159.32	% SZS status Started for HL411149+5.p
182982.12/24159.32	% SZS status GaveUp for HL411149+5.p
182982.12/24159.32	eprover: CPU time limit exceeded, terminating
182982.12/24159.32	% SZS status Ended for HL411149+5.p
182986.50/24159.86	% SZS status Started for HL411157+4.p
182986.50/24159.86	% SZS status GaveUp for HL411157+4.p
182986.50/24159.86	eprover: CPU time limit exceeded, terminating
182986.50/24159.86	% SZS status Ended for HL411157+4.p
182988.02/24160.17	% SZS status Started for HL411150+5.p
182988.02/24160.17	% SZS status GaveUp for HL411150+5.p
182988.02/24160.17	eprover: CPU time limit exceeded, terminating
182988.02/24160.17	% SZS status Ended for HL411150+5.p
183000.83/24161.65	% SZS status Started for HL411160+4.p
183000.83/24161.65	% SZS status GaveUp for HL411160+4.p
183000.83/24161.65	eprover: CPU time limit exceeded, terminating
183000.83/24161.65	% SZS status Ended for HL411160+4.p
183010.53/24162.89	% SZS status Started for HL411161+4.p
183010.53/24162.89	% SZS status GaveUp for HL411161+4.p
183010.53/24162.89	eprover: CPU time limit exceeded, terminating
183010.53/24162.89	% SZS status Ended for HL411161+4.p
183018.27/24163.88	% SZS status Started for HL411152+5.p
183018.27/24163.88	% SZS status GaveUp for HL411152+5.p
183018.27/24163.88	eprover: CPU time limit exceeded, terminating
183018.27/24163.88	% SZS status Ended for HL411152+5.p
183025.11/24164.69	% SZS status Started for HL411163+4.p
183025.11/24164.69	% SZS status GaveUp for HL411163+4.p
183025.11/24164.69	eprover: CPU time limit exceeded, terminating
183025.11/24164.69	% SZS status Ended for HL411163+4.p
183032.67/24165.71	% SZS status Started for HL411153+5.p
183032.67/24165.71	% SZS status GaveUp for HL411153+5.p
183032.67/24165.71	eprover: CPU time limit exceeded, terminating
183032.67/24165.71	% SZS status Ended for HL411153+5.p
183036.23/24166.17	% SZS status Started for HL411154+5.p
183036.23/24166.17	% SZS status GaveUp for HL411154+5.p
183036.23/24166.17	eprover: CPU time limit exceeded, terminating
183036.23/24166.17	% SZS status Ended for HL411154+5.p
183041.84/24166.93	% SZS status Started for HL411168+4.p
183041.84/24166.93	% SZS status GaveUp for HL411168+4.p
183041.84/24166.93	eprover: CPU time limit exceeded, terminating
183041.84/24166.93	% SZS status Ended for HL411168+4.p
183052.41/24168.17	% SZS status Started for HL411157+5.p
183052.41/24168.17	% SZS status GaveUp for HL411157+5.p
183052.41/24168.17	eprover: CPU time limit exceeded, terminating
183052.41/24168.17	% SZS status Ended for HL411157+5.p
183057.47/24168.80	% SZS status Started for HL411169+4.p
183057.47/24168.80	% SZS status GaveUp for HL411169+4.p
183057.47/24168.80	eprover: CPU time limit exceeded, terminating
183057.47/24168.80	% SZS status Ended for HL411169+4.p
183061.36/24169.26	% SZS status Started for HL411169+5.p
183061.36/24169.26	% SZS status GaveUp for HL411169+5.p
183061.36/24169.26	eprover: CPU time limit exceeded, terminating
183061.36/24169.26	% SZS status Ended for HL411169+5.p
183066.92/24169.97	% SZS status Started for HL411160+5.p
183066.92/24169.97	% SZS status GaveUp for HL411160+5.p
183066.92/24169.97	eprover: CPU time limit exceeded, terminating
183066.92/24169.97	% SZS status Ended for HL411160+5.p
183066.92/24170.00	% SZS status Started for HL411170+4.p
183066.92/24170.00	% SZS status GaveUp for HL411170+4.p
183066.92/24170.00	eprover: CPU time limit exceeded, terminating
183066.92/24170.00	% SZS status Ended for HL411170+4.p
183076.09/24171.16	% SZS status Started for HL411161+5.p
183076.09/24171.16	% SZS status GaveUp for HL411161+5.p
183076.09/24171.16	eprover: CPU time limit exceeded, terminating
183076.09/24171.16	% SZS status Ended for HL411161+5.p
183080.55/24171.83	% SZS status Started for HL411171+4.p
183080.55/24171.83	% SZS status GaveUp for HL411171+4.p
183080.55/24171.83	eprover: CPU time limit exceeded, terminating
183080.55/24171.83	% SZS status Ended for HL411171+4.p
183090.59/24172.99	% SZS status Started for HL411172+4.p
183090.59/24172.99	% SZS status GaveUp for HL411172+4.p
183090.59/24172.99	eprover: CPU time limit exceeded, terminating
183090.59/24172.99	% SZS status Ended for HL411172+4.p
183093.81/24173.49	% SZS status Started for HL411163+5.p
183093.81/24173.49	% SZS status GaveUp for HL411163+5.p
183093.81/24173.49	eprover: CPU time limit exceeded, terminating
183093.81/24173.49	% SZS status Ended for HL411163+5.p
183100.30/24174.20	% SZS status Started for HL411173+4.p
183100.30/24174.20	% SZS status GaveUp for HL411173+4.p
183100.30/24174.20	eprover: CPU time limit exceeded, terminating
183100.30/24174.20	% SZS status Ended for HL411173+4.p
183110.28/24175.42	% SZS status Started for HL411168+5.p
183110.28/24175.42	% SZS status GaveUp for HL411168+5.p
183110.28/24175.42	eprover: CPU time limit exceeded, terminating
183110.28/24175.42	% SZS status Ended for HL411168+5.p
183114.42/24176.02	% SZS status Started for HL411175+4.p
183114.42/24176.02	% SZS status GaveUp for HL411175+4.p
183114.42/24176.02	eprover: CPU time limit exceeded, terminating
183114.42/24176.02	% SZS status Ended for HL411175+4.p
183123.97/24177.23	% SZS status Started for HL411176+4.p
183123.97/24177.23	% SZS status GaveUp for HL411176+4.p
183123.97/24177.23	eprover: CPU time limit exceeded, terminating
183123.97/24177.23	% SZS status Ended for HL411176+4.p
183136.20/24178.74	% SZS status Started for HL411170+5.p
183136.20/24178.74	% SZS status GaveUp for HL411170+5.p
183136.20/24178.74	eprover: CPU time limit exceeded, terminating
183136.20/24178.74	% SZS status Ended for HL411170+5.p
183139.02/24179.05	% SZS status Started for HL411177+4.p
183139.02/24179.05	% SZS status GaveUp for HL411177+4.p
183139.02/24179.05	eprover: CPU time limit exceeded, terminating
183139.02/24179.05	% SZS status Ended for HL411177+4.p
183147.84/24180.24	% SZS status Started for HL411171+5.p
183147.84/24180.24	% SZS status GaveUp for HL411171+5.p
183147.84/24180.24	eprover: CPU time limit exceeded, terminating
183147.84/24180.24	% SZS status Ended for HL411171+5.p
183150.75/24180.63	% SZS status Started for HL411172+5.p
183150.75/24180.63	% SZS status GaveUp for HL411172+5.p
183150.75/24180.63	eprover: CPU time limit exceeded, terminating
183150.75/24180.63	% SZS status Ended for HL411172+5.p
183160.44/24181.77	% SZS status Started for HL411179+4.p
183160.44/24181.77	% SZS status GaveUp for HL411179+4.p
183160.44/24181.77	eprover: CPU time limit exceeded, terminating
183160.44/24181.77	% SZS status Ended for HL411179+4.p
183166.83/24182.55	% SZS status Started for HL411173+5.p
183166.83/24182.55	% SZS status GaveUp for HL411173+5.p
183166.83/24182.55	eprover: CPU time limit exceeded, terminating
183166.83/24182.55	% SZS status Ended for HL411173+5.p
183172.09/24183.29	% SZS status Started for HL411180+4.p
183172.09/24183.29	% SZS status GaveUp for HL411180+4.p
183172.09/24183.29	eprover: CPU time limit exceeded, terminating
183172.09/24183.29	% SZS status Ended for HL411180+4.p
183178.75/24184.07	% SZS status Started for HL411175+5.p
183178.75/24184.07	% SZS status GaveUp for HL411175+5.p
183178.75/24184.07	eprover: CPU time limit exceeded, terminating
183178.75/24184.07	% SZS status Ended for HL411175+5.p
183184.81/24184.80	% SZS status Started for HL411181+4.p
183184.81/24184.80	% SZS status GaveUp for HL411181+4.p
183184.81/24184.80	eprover: CPU time limit exceeded, terminating
183184.81/24184.80	% SZS status Ended for HL411181+4.p
183194.62/24186.10	% SZS status Started for HL411176+5.p
183194.62/24186.10	% SZS status GaveUp for HL411176+5.p
183194.62/24186.10	eprover: CPU time limit exceeded, terminating
183194.62/24186.10	% SZS status Ended for HL411176+5.p
183197.34/24186.37	% SZS status Started for HL411183+4.p
183197.34/24186.37	% SZS status GaveUp for HL411183+4.p
183197.34/24186.37	eprover: CPU time limit exceeded, terminating
183197.34/24186.37	% SZS status Ended for HL411183+4.p
183208.86/24187.85	% SZS status Started for HL411184+4.p
183208.86/24187.85	% SZS status GaveUp for HL411184+4.p
183208.86/24187.85	eprover: CPU time limit exceeded, terminating
183208.86/24187.85	% SZS status Ended for HL411184+4.p
183209.34/24187.89	% SZS status Started for HL411177+5.p
183209.34/24187.89	% SZS status GaveUp for HL411177+5.p
183209.34/24187.89	eprover: CPU time limit exceeded, terminating
183209.34/24187.89	% SZS status Ended for HL411177+5.p
183221.11/24189.40	% SZS status Started for HL411185+4.p
183221.11/24189.40	% SZS status GaveUp for HL411185+4.p
183221.11/24189.40	eprover: CPU time limit exceeded, terminating
183221.11/24189.40	% SZS status Ended for HL411185+4.p
183224.47/24189.83	% SZS status Started for HL411179+5.p
183224.47/24189.83	% SZS status GaveUp for HL411179+5.p
183224.47/24189.83	eprover: CPU time limit exceeded, terminating
183224.47/24189.83	% SZS status Ended for HL411179+5.p
183233.27/24190.95	% SZS status Started for HL411186+4.p
183233.27/24190.95	% SZS status GaveUp for HL411186+4.p
183233.27/24190.95	eprover: CPU time limit exceeded, terminating
183233.27/24190.95	% SZS status Ended for HL411186+4.p
183236.03/24191.23	% SZS status Started for HL411180+5.p
183236.03/24191.23	% SZS status GaveUp for HL411180+5.p
183236.03/24191.23	eprover: CPU time limit exceeded, terminating
183236.03/24191.23	% SZS status Ended for HL411180+5.p
183248.77/24192.86	% SZS status Started for HL411188+4.p
183248.77/24192.86	% SZS status GaveUp for HL411188+4.p
183248.77/24192.86	eprover: CPU time limit exceeded, terminating
183248.77/24192.86	% SZS status Ended for HL411188+4.p
183251.67/24193.28	% SZS status Started for HL411181+5.p
183251.67/24193.28	% SZS status GaveUp for HL411181+5.p
183251.67/24193.28	eprover: CPU time limit exceeded, terminating
183251.67/24193.28	% SZS status Ended for HL411181+5.p
183259.88/24194.27	% SZS status Started for HL411189+4.p
183259.88/24194.27	% SZS status GaveUp for HL411189+4.p
183259.88/24194.27	eprover: CPU time limit exceeded, terminating
183259.88/24194.27	% SZS status Ended for HL411189+4.p
183263.53/24194.69	% SZS status Started for HL411183+5.p
183263.53/24194.69	% SZS status GaveUp for HL411183+5.p
183263.53/24194.69	eprover: CPU time limit exceeded, terminating
183263.53/24194.69	% SZS status Ended for HL411183+5.p
183276.55/24196.37	% SZS status Started for HL411190+4.p
183276.55/24196.37	% SZS status GaveUp for HL411190+4.p
183276.55/24196.37	eprover: CPU time limit exceeded, terminating
183276.55/24196.37	% SZS status Ended for HL411190+4.p
183278.69/24196.76	% SZS status Started for HL411184+5.p
183278.69/24196.76	% SZS status GaveUp for HL411184+5.p
183278.69/24196.76	eprover: CPU time limit exceeded, terminating
183278.69/24196.76	% SZS status Ended for HL411184+5.p
183284.12/24197.33	% SZS status Started for HL411190+5.p
183284.12/24197.33	% SZS status GaveUp for HL411190+5.p
183284.12/24197.33	eprover: CPU time limit exceeded, terminating
183284.12/24197.33	% SZS status Ended for HL411190+5.p
183287.12/24197.72	% SZS status Started for HL411191+4.p
183287.12/24197.72	% SZS status GaveUp for HL411191+4.p
183287.12/24197.72	eprover: CPU time limit exceeded, terminating
183287.12/24197.72	% SZS status Ended for HL411191+4.p
183293.66/24198.51	% SZS status Started for HL411185+5.p
183293.66/24198.51	% SZS status GaveUp for HL411185+5.p
183293.66/24198.51	eprover: CPU time limit exceeded, terminating
183293.66/24198.51	% SZS status Ended for HL411185+5.p
183300.67/24199.40	% SZS status Started for HL411191+5.p
183300.67/24199.40	% SZS status GaveUp for HL411191+5.p
183300.67/24199.40	eprover: CPU time limit exceeded, terminating
183300.67/24199.40	% SZS status Ended for HL411191+5.p
183303.75/24199.80	% SZS status Started for HL411192+4.p
183303.75/24199.80	% SZS status GaveUp for HL411192+4.p
183303.75/24199.80	eprover: CPU time limit exceeded, terminating
183303.75/24199.80	% SZS status Ended for HL411192+4.p
183305.56/24200.07	% SZS status Started for HL411186+5.p
183305.56/24200.07	% SZS status GaveUp for HL411186+5.p
183305.56/24200.07	eprover: CPU time limit exceeded, terminating
183305.56/24200.07	% SZS status Ended for HL411186+5.p
183308.64/24200.36	% SZS status Started for HL411192+5.p
183308.64/24200.36	% SZS status GaveUp for HL411192+5.p
183308.64/24200.36	eprover: CPU time limit exceeded, terminating
183308.64/24200.36	% SZS status Ended for HL411192+5.p
183311.12/24200.76	% SZS status Started for HL411196+4.p
183311.12/24200.76	% SZS status GaveUp for HL411196+4.p
183311.12/24200.76	eprover: CPU time limit exceeded, terminating
183311.12/24200.76	% SZS status Ended for HL411196+4.p
183317.61/24201.55	% SZS status Started for HL411196+5.p
183317.61/24201.55	% SZS status GaveUp for HL411196+5.p
183317.61/24201.55	eprover: CPU time limit exceeded, terminating
183317.61/24201.55	% SZS status Ended for HL411196+5.p
183320.09/24201.90	% SZS status Started for HL411188+5.p
183320.09/24201.90	% SZS status GaveUp for HL411188+5.p
183320.09/24201.90	eprover: CPU time limit exceeded, terminating
183320.09/24201.90	% SZS status Ended for HL411188+5.p
183324.95/24202.44	% SZS status Started for HL411198+4.p
183324.95/24202.44	% SZS status GaveUp for HL411198+4.p
183324.95/24202.44	eprover: CPU time limit exceeded, terminating
183324.95/24202.44	% SZS status Ended for HL411198+4.p
183328.34/24202.84	% SZS status Started for HL411198+5.p
183328.34/24202.84	% SZS status GaveUp for HL411198+5.p
183328.34/24202.84	eprover: CPU time limit exceeded, terminating
183328.34/24202.84	% SZS status Ended for HL411198+5.p
183329.81/24203.11	% SZS status Started for HL411199+4.p
183329.81/24203.11	% SZS status GaveUp for HL411199+4.p
183329.81/24203.11	eprover: CPU time limit exceeded, terminating
183329.81/24203.11	% SZS status Ended for HL411199+4.p
183332.72/24203.40	% SZS status Started for HL411199+5.p
183332.72/24203.40	% SZS status GaveUp for HL411199+5.p
183332.72/24203.40	eprover: CPU time limit exceeded, terminating
183332.72/24203.40	% SZS status Ended for HL411199+5.p
183333.69/24203.55	% SZS status Started for HL411189+5.p
183333.69/24203.55	% SZS status GaveUp for HL411189+5.p
183333.69/24203.55	eprover: CPU time limit exceeded, terminating
183333.69/24203.55	% SZS status Ended for HL411189+5.p
183336.55/24203.90	% SZS status Started for HL411200+4.p
183336.55/24203.90	% SZS status GaveUp for HL411200+4.p
183336.55/24203.90	eprover: CPU time limit exceeded, terminating
183336.55/24203.90	% SZS status Ended for HL411200+4.p
183342.03/24204.59	% SZS status Started for HL411200+5.p
183342.03/24204.59	% SZS status GaveUp for HL411200+5.p
183342.03/24204.59	eprover: CPU time limit exceeded, terminating
183342.03/24204.59	% SZS status Ended for HL411200+5.p
183344.66/24204.96	% SZS status Started for HL411201+4.p
183344.66/24204.96	% SZS status GaveUp for HL411201+4.p
183344.66/24204.96	eprover: CPU time limit exceeded, terminating
183344.66/24204.96	% SZS status Ended for HL411201+4.p
183349.00/24205.52	% SZS status Started for HL411201+5.p
183349.00/24205.52	% SZS status GaveUp for HL411201+5.p
183349.00/24205.52	eprover: CPU time limit exceeded, terminating
183349.00/24205.52	% SZS status Ended for HL411201+5.p
183352.05/24205.88	% SZS status Started for HL411203+4.p
183352.05/24205.88	% SZS status GaveUp for HL411203+4.p
183352.05/24205.88	eprover: CPU time limit exceeded, terminating
183352.05/24205.88	% SZS status Ended for HL411203+4.p
183354.61/24206.16	% SZS status Started for HL411203+5.p
183354.61/24206.16	% SZS status GaveUp for HL411203+5.p
183354.61/24206.16	eprover: CPU time limit exceeded, terminating
183354.61/24206.16	% SZS status Ended for HL411203+5.p
183357.61/24206.58	% SZS status Started for HL411204+4.p
183357.61/24206.58	% SZS status GaveUp for HL411204+4.p
183357.61/24206.58	eprover: CPU time limit exceeded, terminating
183357.61/24206.58	% SZS status Ended for HL411204+4.p
183358.73/24206.68	% SZS status Started for HL411204+5.p
183358.73/24206.68	% SZS status GaveUp for HL411204+5.p
183358.73/24206.68	eprover: CPU time limit exceeded, terminating
183358.73/24206.68	% SZS status Ended for HL411204+5.p
183359.98/24206.94	% SZS status Started for HL411205+4.p
183359.98/24206.94	% SZS status GaveUp for HL411205+4.p
183359.98/24206.94	eprover: CPU time limit exceeded, terminating
183359.98/24206.94	% SZS status Ended for HL411205+4.p
183365.88/24207.63	% SZS status Started for HL411205+5.p
183365.88/24207.63	% SZS status GaveUp for HL411205+5.p
183365.88/24207.63	eprover: CPU time limit exceeded, terminating
183365.88/24207.63	% SZS status Ended for HL411205+5.p
183369.19/24208.00	% SZS status Started for HL411206+4.p
183369.19/24208.00	% SZS status GaveUp for HL411206+4.p
183369.19/24208.00	eprover: CPU time limit exceeded, terminating
183369.19/24208.00	% SZS status Ended for HL411206+4.p
183373.45/24208.56	% SZS status Started for HL411206+5.p
183373.45/24208.56	% SZS status GaveUp for HL411206+5.p
183373.45/24208.56	eprover: CPU time limit exceeded, terminating
183373.45/24208.56	% SZS status Ended for HL411206+5.p
183376.06/24208.92	% SZS status Started for HL411207+4.p
183376.06/24208.92	% SZS status GaveUp for HL411207+4.p
183376.06/24208.92	eprover: CPU time limit exceeded, terminating
183376.06/24208.92	% SZS status Ended for HL411207+4.p
183379.16/24209.32	% SZS status Started for HL411207+5.p
183379.16/24209.32	% SZS status GaveUp for HL411207+5.p
183379.16/24209.32	eprover: CPU time limit exceeded, terminating
183379.16/24209.32	% SZS status Ended for HL411207+5.p
183382.12/24209.62	% SZS status Started for HL411208+4.p
183382.12/24209.62	% SZS status GaveUp for HL411208+4.p
183382.12/24209.62	eprover: CPU time limit exceeded, terminating
183382.12/24209.62	% SZS status Ended for HL411208+4.p
183382.41/24209.73	% SZS status Started for HL411208+5.p
183382.41/24209.73	% SZS status GaveUp for HL411208+5.p
183382.41/24209.73	eprover: CPU time limit exceeded, terminating
183382.41/24209.73	% SZS status Ended for HL411208+5.p
183384.64/24209.98	% SZS status Started for HL411209+4.p
183384.64/24209.98	% SZS status GaveUp for HL411209+4.p
183384.64/24209.98	eprover: CPU time limit exceeded, terminating
183384.64/24209.98	% SZS status Ended for HL411209+4.p
183390.42/24210.68	% SZS status Started for HL411209+5.p
183390.42/24210.68	% SZS status GaveUp for HL411209+5.p
183390.42/24210.68	eprover: CPU time limit exceeded, terminating
183390.42/24210.68	% SZS status Ended for HL411209+5.p
183392.56/24211.04	% SZS status Started for HL411210+4.p
183392.56/24211.04	% SZS status GaveUp for HL411210+4.p
183392.56/24211.04	eprover: CPU time limit exceeded, terminating
183392.56/24211.04	% SZS status Ended for HL411210+4.p
183397.36/24211.60	% SZS status Started for HL411210+5.p
183397.36/24211.60	% SZS status GaveUp for HL411210+5.p
183397.36/24211.60	eprover: CPU time limit exceeded, terminating
183397.36/24211.60	% SZS status Ended for HL411210+5.p
183400.50/24211.96	% SZS status Started for HL411211+4.p
183400.50/24211.96	% SZS status GaveUp for HL411211+4.p
183400.50/24211.96	eprover: CPU time limit exceeded, terminating
183400.50/24211.96	% SZS status Ended for HL411211+4.p
183405.05/24212.53	% SZS status Started for HL411211+5.p
183405.05/24212.53	% SZS status GaveUp for HL411211+5.p
183405.05/24212.53	eprover: CPU time limit exceeded, terminating
183405.05/24212.53	% SZS status Ended for HL411211+5.p
183406.06/24212.66	% SZS status Started for HL411212+4.p
183406.06/24212.66	% SZS status GaveUp for HL411212+4.p
183406.06/24212.66	eprover: CPU time limit exceeded, terminating
183406.06/24212.66	% SZS status Ended for HL411212+4.p
183406.64/24212.77	% SZS status Started for HL411212+5.p
183406.64/24212.77	% SZS status GaveUp for HL411212+5.p
183406.64/24212.77	eprover: CPU time limit exceeded, terminating
183406.64/24212.77	% SZS status Ended for HL411212+5.p
183408.80/24213.02	% SZS status Started for HL411213+4.p
183408.80/24213.02	% SZS status GaveUp for HL411213+4.p
183408.80/24213.02	eprover: CPU time limit exceeded, terminating
183408.80/24213.02	% SZS status Ended for HL411213+4.p
183414.20/24213.72	% SZS status Started for HL411213+5.p
183414.20/24213.72	% SZS status GaveUp for HL411213+5.p
183414.20/24213.72	eprover: CPU time limit exceeded, terminating
183414.20/24213.72	% SZS status Ended for HL411213+5.p
183417.30/24214.08	% SZS status Started for HL411215+4.p
183417.30/24214.08	% SZS status GaveUp for HL411215+4.p
183417.30/24214.08	eprover: CPU time limit exceeded, terminating
183417.30/24214.08	% SZS status Ended for HL411215+4.p
183421.92/24214.64	% SZS status Started for HL411215+5.p
183421.92/24214.64	% SZS status GaveUp for HL411215+5.p
183421.92/24214.64	eprover: CPU time limit exceeded, terminating
183421.92/24214.64	% SZS status Ended for HL411215+5.p
183424.47/24215.01	% SZS status Started for HL411217+4.p
183424.47/24215.01	% SZS status GaveUp for HL411217+4.p
183424.47/24215.01	eprover: CPU time limit exceeded, terminating
183424.47/24215.01	% SZS status Ended for HL411217+4.p
183430.05/24215.69	% SZS status Started for HL411221+4.p
183430.05/24215.69	% SZS status GaveUp for HL411221+4.p
183430.05/24215.69	eprover: CPU time limit exceeded, terminating
183430.05/24215.69	% SZS status Ended for HL411221+4.p
183430.41/24215.71	% SZS status Started for HL411217+5.p
183430.41/24215.71	% SZS status GaveUp for HL411217+5.p
183430.41/24215.71	eprover: CPU time limit exceeded, terminating
183430.41/24215.71	% SZS status Ended for HL411217+5.p
183430.64/24215.80	% SZS status Started for HL411221+5.p
183430.64/24215.80	% SZS status GaveUp for HL411221+5.p
183430.64/24215.80	eprover: CPU time limit exceeded, terminating
183430.64/24215.80	% SZS status Ended for HL411221+5.p
183432.22/24216.06	% SZS status Started for HL411222+4.p
183432.22/24216.06	% SZS status GaveUp for HL411222+4.p
183432.22/24216.06	eprover: CPU time limit exceeded, terminating
183432.22/24216.06	% SZS status Ended for HL411222+4.p
183438.72/24216.76	% SZS status Started for HL411222+5.p
183438.72/24216.76	% SZS status GaveUp for HL411222+5.p
183438.72/24216.76	eprover: CPU time limit exceeded, terminating
183438.72/24216.76	% SZS status Ended for HL411222+5.p
183440.83/24217.11	% SZS status Started for HL411224+4.p
183440.83/24217.11	% SZS status GaveUp for HL411224+4.p
183440.83/24217.11	eprover: CPU time limit exceeded, terminating
183440.83/24217.11	% SZS status Ended for HL411224+4.p
183446.00/24217.68	% SZS status Started for HL411224+5.p
183446.00/24217.68	% SZS status GaveUp for HL411224+5.p
183446.00/24217.68	eprover: CPU time limit exceeded, terminating
183446.00/24217.68	% SZS status Ended for HL411224+5.p
183448.88/24218.06	% SZS status Started for HL411225+4.p
183448.88/24218.06	% SZS status GaveUp for HL411225+4.p
183448.88/24218.06	eprover: CPU time limit exceeded, terminating
183448.88/24218.06	% SZS status Ended for HL411225+4.p
183453.97/24218.73	% SZS status Started for HL411225+5.p
183453.97/24218.73	% SZS status GaveUp for HL411225+5.p
183453.97/24218.73	eprover: CPU time limit exceeded, terminating
183453.97/24218.73	% SZS status Ended for HL411225+5.p
183455.03/24218.82	% SZS status Started for HL411227+4.p
183455.03/24218.82	% SZS status GaveUp for HL411227+4.p
183455.03/24218.82	eprover: CPU time limit exceeded, terminating
183455.03/24218.82	% SZS status Ended for HL411227+4.p
183455.03/24218.85	% SZS status Started for HL411227+5.p
183455.03/24218.85	% SZS status GaveUp for HL411227+5.p
183455.03/24218.85	eprover: CPU time limit exceeded, terminating
183455.03/24218.85	% SZS status Ended for HL411227+5.p
183457.14/24219.10	% SZS status Started for HL411229+4.p
183457.14/24219.10	% SZS status GaveUp for HL411229+4.p
183457.14/24219.10	eprover: CPU time limit exceeded, terminating
183457.14/24219.10	% SZS status Ended for HL411229+4.p
183463.73/24219.93	% SZS status Started for HL411229+5.p
183463.73/24219.93	% SZS status GaveUp for HL411229+5.p
183463.73/24219.93	eprover: CPU time limit exceeded, terminating
183463.73/24219.93	% SZS status Ended for HL411229+5.p
183465.64/24220.15	% SZS status Started for HL411230+4.p
183465.64/24220.15	% SZS status GaveUp for HL411230+4.p
183465.64/24220.15	eprover: CPU time limit exceeded, terminating
183465.64/24220.15	% SZS status Ended for HL411230+4.p
183469.95/24220.72	% SZS status Started for HL411230+5.p
183469.95/24220.72	% SZS status GaveUp for HL411230+5.p
183469.95/24220.72	eprover: CPU time limit exceeded, terminating
183469.95/24220.72	% SZS status Ended for HL411230+5.p
183472.64/24221.09	% SZS status Started for HL411231+4.p
183472.64/24221.09	% SZS status GaveUp for HL411231+4.p
183472.64/24221.09	eprover: CPU time limit exceeded, terminating
183472.64/24221.09	% SZS status Ended for HL411231+4.p
183478.38/24221.77	% SZS status Started for HL411231+5.p
183478.38/24221.77	% SZS status GaveUp for HL411231+5.p
183478.38/24221.77	eprover: CPU time limit exceeded, terminating
183478.38/24221.77	% SZS status Ended for HL411231+5.p
183479.05/24221.85	% SZS status Started for HL411233+4.p
183479.05/24221.85	% SZS status GaveUp for HL411233+4.p
183479.05/24221.85	eprover: CPU time limit exceeded, terminating
183479.05/24221.85	% SZS status Ended for HL411233+4.p
183479.05/24221.89	% SZS status Started for HL411233+5.p
183479.05/24221.89	% SZS status GaveUp for HL411233+5.p
183479.05/24221.89	eprover: CPU time limit exceeded, terminating
183479.05/24221.89	% SZS status Ended for HL411233+5.p
183480.66/24222.14	% SZS status Started for HL411234+4.p
183480.66/24222.14	% SZS status GaveUp for HL411234+4.p
183480.66/24222.14	eprover: CPU time limit exceeded, terminating
183480.66/24222.14	% SZS status Ended for HL411234+4.p
183489.11/24223.12	% SZS status Started for HL411234+5.p
183489.11/24223.12	% SZS status GaveUp for HL411234+5.p
183489.11/24223.12	eprover: CPU time limit exceeded, terminating
183489.11/24223.12	% SZS status Ended for HL411234+5.p
183489.62/24223.19	% SZS status Started for HL411235+4.p
183489.62/24223.19	% SZS status GaveUp for HL411235+4.p
183489.62/24223.19	eprover: CPU time limit exceeded, terminating
183489.62/24223.19	% SZS status Ended for HL411235+4.p
183493.69/24223.75	% SZS status Started for HL411235+5.p
183493.69/24223.75	% SZS status GaveUp for HL411235+5.p
183493.69/24223.75	eprover: CPU time limit exceeded, terminating
183493.69/24223.75	% SZS status Ended for HL411235+5.p
183496.56/24224.14	% SZS status Started for HL411237+4.p
183496.56/24224.14	% SZS status GaveUp for HL411237+4.p
183496.56/24224.14	eprover: CPU time limit exceeded, terminating
183496.56/24224.14	% SZS status Ended for HL411237+4.p
183501.80/24224.81	% SZS status Started for HL411237+5.p
183501.80/24224.81	% SZS status GaveUp for HL411237+5.p
183501.80/24224.81	eprover: CPU time limit exceeded, terminating
183501.80/24224.81	% SZS status Ended for HL411237+5.p
183502.56/24224.89	% SZS status Started for HL411238+4.p
183502.56/24224.89	% SZS status GaveUp for HL411238+4.p
183502.56/24224.89	eprover: CPU time limit exceeded, terminating
183502.56/24224.89	% SZS status Ended for HL411238+4.p
183502.56/24224.93	% SZS status Started for HL411238+5.p
183502.56/24224.93	% SZS status GaveUp for HL411238+5.p
183502.56/24224.93	eprover: CPU time limit exceeded, terminating
183502.56/24224.93	% SZS status Ended for HL411238+5.p
183504.95/24225.18	% SZS status Started for HL411239+4.p
183504.95/24225.18	% SZS status GaveUp for HL411239+4.p
183504.95/24225.18	eprover: CPU time limit exceeded, terminating
183504.95/24225.18	% SZS status Ended for HL411239+4.p
183514.97/24226.42	% SZS status Started for HL411239+5.p
183514.97/24226.42	% SZS status GaveUp for HL411239+5.p
183514.97/24226.42	eprover: CPU time limit exceeded, terminating
183514.97/24226.42	% SZS status Ended for HL411239+5.p
183515.47/24226.51	% SZS status Started for HL411240+4.p
183515.47/24226.51	% SZS status GaveUp for HL411240+4.p
183515.47/24226.51	eprover: CPU time limit exceeded, terminating
183515.47/24226.51	% SZS status Ended for HL411240+4.p
183518.75/24226.91	% SZS status Started for HL411240+5.p
183518.75/24226.91	% SZS status GaveUp for HL411240+5.p
183518.75/24226.91	eprover: CPU time limit exceeded, terminating
183518.75/24226.91	% SZS status Ended for HL411240+5.p
183520.25/24227.17	% SZS status Started for HL411241+4.p
183520.25/24227.17	% SZS status GaveUp for HL411241+4.p
183520.25/24227.17	eprover: CPU time limit exceeded, terminating
183520.25/24227.17	% SZS status Ended for HL411241+4.p
183525.86/24227.85	% SZS status Started for HL411241+5.p
183525.86/24227.85	% SZS status GaveUp for HL411241+5.p
183525.86/24227.85	eprover: CPU time limit exceeded, terminating
183525.86/24227.85	% SZS status Ended for HL411241+5.p
183526.98/24227.93	% SZS status Started for HL411242+4.p
183526.98/24227.93	% SZS status GaveUp for HL411242+4.p
183526.98/24227.93	eprover: CPU time limit exceeded, terminating
183526.98/24227.93	% SZS status Ended for HL411242+4.p
183527.72/24228.04	% SZS status Started for HL411242+5.p
183527.72/24228.04	% SZS status GaveUp for HL411242+5.p
183527.72/24228.04	eprover: CPU time limit exceeded, terminating
183527.72/24228.04	% SZS status Ended for HL411242+5.p
183528.56/24228.22	% SZS status Started for HL411243+4.p
183528.56/24228.22	% SZS status GaveUp for HL411243+4.p
183528.56/24228.22	eprover: CPU time limit exceeded, terminating
183528.56/24228.22	% SZS status Ended for HL411243+4.p
183539.05/24229.45	% SZS status Started for HL411243+5.p
183539.05/24229.45	% SZS status GaveUp for HL411243+5.p
183539.05/24229.45	eprover: CPU time limit exceeded, terminating
183539.05/24229.45	% SZS status Ended for HL411243+5.p
183539.78/24229.56	% SZS status Started for HL411245+4.p
183539.78/24229.56	% SZS status GaveUp for HL411245+4.p
183539.78/24229.56	eprover: CPU time limit exceeded, terminating
183539.78/24229.56	% SZS status Ended for HL411245+4.p
183542.64/24229.95	% SZS status Started for HL411245+5.p
183542.64/24229.95	% SZS status GaveUp for HL411245+5.p
183542.64/24229.95	eprover: CPU time limit exceeded, terminating
183542.64/24229.95	% SZS status Ended for HL411245+5.p
183544.44/24230.21	% SZS status Started for HL411246+4.p
183544.44/24230.21	% SZS status GaveUp for HL411246+4.p
183544.44/24230.21	eprover: CPU time limit exceeded, terminating
183544.44/24230.21	% SZS status Ended for HL411246+4.p
183550.28/24230.89	% SZS status Started for HL411246+5.p
183550.28/24230.89	% SZS status GaveUp for HL411246+5.p
183550.28/24230.89	eprover: CPU time limit exceeded, terminating
183550.28/24230.89	% SZS status Ended for HL411246+5.p
183550.97/24230.96	% SZS status Started for HL411247+4.p
183550.97/24230.96	% SZS status GaveUp for HL411247+4.p
183550.97/24230.96	eprover: CPU time limit exceeded, terminating
183550.97/24230.96	% SZS status Ended for HL411247+4.p
183551.75/24231.12	% SZS status Started for HL411247+5.p
183551.75/24231.12	% SZS status GaveUp for HL411247+5.p
183551.75/24231.12	eprover: CPU time limit exceeded, terminating
183551.75/24231.12	% SZS status Ended for HL411247+5.p
183552.77/24231.26	% SZS status Started for HL411248+4.p
183552.77/24231.26	% SZS status GaveUp for HL411248+4.p
183552.77/24231.26	eprover: CPU time limit exceeded, terminating
183552.77/24231.26	% SZS status Ended for HL411248+4.p
183563.97/24232.61	% SZS status Started for HL411249+4.p
183563.97/24232.61	% SZS status GaveUp for HL411249+4.p
183563.97/24232.61	eprover: CPU time limit exceeded, terminating
183563.97/24232.61	% SZS status Ended for HL411249+4.p
183564.44/24232.65	% SZS status Started for HL411248+5.p
183564.44/24232.65	% SZS status GaveUp for HL411248+5.p
183564.44/24232.65	eprover: CPU time limit exceeded, terminating
183564.44/24232.65	% SZS status Ended for HL411248+5.p
183566.23/24232.99	% SZS status Started for HL411249+5.p
183566.23/24232.99	% SZS status GaveUp for HL411249+5.p
183566.23/24232.99	eprover: CPU time limit exceeded, terminating
183566.23/24232.99	% SZS status Ended for HL411249+5.p
183569.03/24233.25	% SZS status Started for HL411250+4.p
183569.03/24233.25	% SZS status GaveUp for HL411250+4.p
183569.03/24233.25	eprover: CPU time limit exceeded, terminating
183569.03/24233.25	% SZS status Ended for HL411250+4.p
183574.56/24233.92	% SZS status Started for HL411250+5.p
183574.56/24233.92	% SZS status GaveUp for HL411250+5.p
183574.56/24233.92	eprover: CPU time limit exceeded, terminating
183574.56/24233.92	% SZS status Ended for HL411250+5.p
183574.66/24234.00	% SZS status Started for HL411251+4.p
183574.66/24234.00	% SZS status GaveUp for HL411251+4.p
183574.66/24234.00	eprover: CPU time limit exceeded, terminating
183574.66/24234.00	% SZS status Ended for HL411251+4.p
183576.05/24234.16	% SZS status Started for HL411251+5.p
183576.05/24234.16	% SZS status GaveUp for HL411251+5.p
183576.05/24234.16	eprover: CPU time limit exceeded, terminating
183576.05/24234.16	% SZS status Ended for HL411251+5.p
183576.83/24234.30	% SZS status Started for HL411252+4.p
183576.83/24234.30	% SZS status GaveUp for HL411252+4.p
183576.83/24234.30	eprover: CPU time limit exceeded, terminating
183576.83/24234.30	% SZS status Ended for HL411252+4.p
183587.61/24235.68	% SZS status Started for HL411253+4.p
183587.61/24235.68	% SZS status GaveUp for HL411253+4.p
183587.61/24235.68	eprover: CPU time limit exceeded, terminating
183587.61/24235.68	% SZS status Ended for HL411253+4.p
183590.55/24236.03	% SZS status Started for HL411253+5.p
183590.55/24236.03	% SZS status GaveUp for HL411253+5.p
183590.55/24236.03	eprover: CPU time limit exceeded, terminating
183590.55/24236.03	% SZS status Ended for HL411253+5.p
183590.80/24236.08	% SZS status Started for HL411252+5.p
183590.80/24236.08	% SZS status GaveUp for HL411252+5.p
183590.80/24236.08	eprover: CPU time limit exceeded, terminating
183590.80/24236.08	% SZS status Ended for HL411252+5.p
183592.22/24236.30	% SZS status Started for HL411254+4.p
183592.22/24236.30	% SZS status GaveUp for HL411254+4.p
183592.22/24236.30	eprover: CPU time limit exceeded, terminating
183592.22/24236.30	% SZS status Ended for HL411254+4.p
183598.59/24237.04	% SZS status Started for HL411255+4.p
183598.59/24237.04	% SZS status GaveUp for HL411255+4.p
183598.59/24237.04	eprover: CPU time limit exceeded, terminating
183598.59/24237.04	% SZS status Ended for HL411255+4.p
183599.84/24237.20	% SZS status Started for HL411255+5.p
183599.84/24237.20	% SZS status GaveUp for HL411255+5.p
183599.84/24237.20	eprover: CPU time limit exceeded, terminating
183599.84/24237.20	% SZS status Ended for HL411255+5.p
183600.39/24237.30	% SZS status Started for HL411254+5.p
183600.39/24237.30	% SZS status GaveUp for HL411254+5.p
183600.39/24237.30	eprover: CPU time limit exceeded, terminating
183600.39/24237.30	% SZS status Ended for HL411254+5.p
183600.39/24237.34	% SZS status Started for HL411256+4.p
183600.39/24237.34	% SZS status GaveUp for HL411256+4.p
183600.39/24237.34	eprover: CPU time limit exceeded, terminating
183600.39/24237.34	% SZS status Ended for HL411256+4.p
183611.53/24238.72	% SZS status Started for HL411256+5.p
183611.53/24238.72	% SZS status GaveUp for HL411256+5.p
183611.53/24238.72	eprover: CPU time limit exceeded, terminating
183611.53/24238.72	% SZS status Ended for HL411256+5.p
183614.75/24239.07	% SZS status Started for HL411257+4.p
183614.75/24239.07	% SZS status GaveUp for HL411257+4.p
183614.75/24239.07	eprover: CPU time limit exceeded, terminating
183614.75/24239.07	% SZS status Ended for HL411257+4.p
183616.12/24239.26	% SZS status Started for HL411257+5.p
183616.12/24239.26	% SZS status GaveUp for HL411257+5.p
183616.12/24239.26	eprover: CPU time limit exceeded, terminating
183616.12/24239.26	% SZS status Ended for HL411257+5.p
183616.53/24239.34	% SZS status Started for HL411259+4.p
183616.53/24239.34	% SZS status GaveUp for HL411259+4.p
183616.53/24239.34	eprover: CPU time limit exceeded, terminating
183616.53/24239.34	% SZS status Ended for HL411259+4.p
183622.22/24240.07	% SZS status Started for HL411259+5.p
183622.22/24240.07	% SZS status GaveUp for HL411259+5.p
183622.22/24240.07	eprover: CPU time limit exceeded, terminating
183622.22/24240.07	% SZS status Ended for HL411259+5.p
183623.70/24240.24	% SZS status Started for HL411260+4.p
183623.70/24240.24	% SZS status GaveUp for HL411260+4.p
183623.70/24240.24	eprover: CPU time limit exceeded, terminating
183623.70/24240.24	% SZS status Ended for HL411260+4.p
183624.33/24240.33	% SZS status Started for HL411260+5.p
183624.33/24240.33	% SZS status GaveUp for HL411260+5.p
183624.33/24240.33	eprover: CPU time limit exceeded, terminating
183624.33/24240.33	% SZS status Ended for HL411260+5.p
183624.33/24240.38	% SZS status Started for HL411261+4.p
183624.33/24240.38	% SZS status GaveUp for HL411261+4.p
183624.33/24240.38	eprover: CPU time limit exceeded, terminating
183624.33/24240.38	% SZS status Ended for HL411261+4.p
183635.50/24241.76	% SZS status Started for HL411261+5.p
183635.50/24241.76	% SZS status GaveUp for HL411261+5.p
183635.50/24241.76	eprover: CPU time limit exceeded, terminating
183635.50/24241.76	% SZS status Ended for HL411261+5.p
183638.33/24242.10	% SZS status Started for HL411262+4.p
183638.33/24242.10	% SZS status GaveUp for HL411262+4.p
183638.33/24242.10	eprover: CPU time limit exceeded, terminating
183638.33/24242.10	% SZS status Ended for HL411262+4.p
183639.73/24242.37	% SZS status Started for HL411263+4.p
183639.73/24242.37	% SZS status GaveUp for HL411263+4.p
183639.73/24242.37	eprover: CPU time limit exceeded, terminating
183639.73/24242.37	% SZS status Ended for HL411263+4.p
183642.81/24242.43	% SZS status Started for HL411262+5.p
183642.81/24242.43	% SZS status GaveUp for HL411262+5.p
183642.81/24242.43	eprover: CPU time limit exceeded, terminating
183642.81/24242.43	% SZS status Ended for HL411262+5.p
183648.00/24243.11	% SZS status Started for HL411263+5.p
183648.00/24243.11	% SZS status GaveUp for HL411263+5.p
183648.00/24243.11	eprover: CPU time limit exceeded, terminating
183648.00/24243.11	% SZS status Ended for HL411263+5.p
183649.58/24243.28	% SZS status Started for HL411264+4.p
183649.58/24243.28	% SZS status GaveUp for HL411264+4.p
183649.58/24243.28	eprover: CPU time limit exceeded, terminating
183649.58/24243.28	% SZS status Ended for HL411264+4.p
183650.09/24243.38	% SZS status Started for HL411264+5.p
183650.09/24243.38	% SZS status GaveUp for HL411264+5.p
183650.09/24243.38	eprover: CPU time limit exceeded, terminating
183650.09/24243.38	% SZS status Ended for HL411264+5.p
183650.09/24243.42	% SZS status Started for HL411265+4.p
183650.09/24243.42	% SZS status GaveUp for HL411265+4.p
183650.09/24243.42	eprover: CPU time limit exceeded, terminating
183650.09/24243.42	% SZS status Ended for HL411265+4.p
183663.69/24245.15	% SZS status Started for HL411266+4.p
183663.69/24245.15	% SZS status GaveUp for HL411266+4.p
183663.69/24245.15	eprover: CPU time limit exceeded, terminating
183663.69/24245.15	% SZS status Ended for HL411266+4.p
183664.38/24245.21	% SZS status Started for HL411265+5.p
183664.38/24245.21	% SZS status GaveUp for HL411265+5.p
183664.38/24245.21	eprover: CPU time limit exceeded, terminating
183664.38/24245.21	% SZS status Ended for HL411265+5.p
183665.61/24245.41	% SZS status Started for HL411266+5.p
183665.61/24245.41	% SZS status GaveUp for HL411266+5.p
183665.61/24245.41	eprover: CPU time limit exceeded, terminating
183665.61/24245.41	% SZS status Ended for HL411266+5.p
183666.14/24245.48	% SZS status Started for HL411267+4.p
183666.14/24245.48	% SZS status GaveUp for HL411267+4.p
183666.14/24245.48	eprover: CPU time limit exceeded, terminating
183666.14/24245.48	% SZS status Ended for HL411267+4.p
183673.08/24246.31	% SZS status Started for HL411268+4.p
183673.08/24246.31	% SZS status GaveUp for HL411268+4.p
183673.08/24246.31	eprover: CPU time limit exceeded, terminating
183673.08/24246.31	% SZS status Ended for HL411268+4.p
183674.06/24246.41	% SZS status Started for HL411268+5.p
183674.06/24246.41	% SZS status GaveUp for HL411268+5.p
183674.06/24246.41	eprover: CPU time limit exceeded, terminating
183674.06/24246.41	% SZS status Ended for HL411268+5.p
183674.41/24246.45	% SZS status Started for HL411269+4.p
183674.41/24246.45	% SZS status GaveUp for HL411269+4.p
183674.41/24246.45	eprover: CPU time limit exceeded, terminating
183674.41/24246.45	% SZS status Ended for HL411269+4.p
183674.41/24246.46	% SZS status Started for HL411267+5.p
183674.41/24246.46	% SZS status GaveUp for HL411267+5.p
183674.41/24246.46	eprover: CPU time limit exceeded, terminating
183674.41/24246.46	% SZS status Ended for HL411267+5.p
183688.78/24248.25	% SZS status Started for HL411271+4.p
183688.78/24248.25	% SZS status GaveUp for HL411271+4.p
183688.78/24248.25	eprover: CPU time limit exceeded, terminating
183688.78/24248.25	% SZS status Ended for HL411271+4.p
183689.22/24248.34	% SZS status Started for HL411269+5.p
183689.22/24248.34	% SZS status GaveUp for HL411269+5.p
183689.22/24248.34	eprover: CPU time limit exceeded, terminating
183689.22/24248.34	% SZS status Ended for HL411269+5.p
183690.08/24248.45	% SZS status Started for HL411271+5.p
183690.08/24248.45	% SZS status GaveUp for HL411271+5.p
183690.08/24248.45	eprover: CPU time limit exceeded, terminating
183690.08/24248.45	% SZS status Ended for HL411271+5.p
183690.36/24248.52	% SZS status Started for HL411272+4.p
183690.36/24248.52	% SZS status GaveUp for HL411272+4.p
183690.36/24248.52	eprover: CPU time limit exceeded, terminating
183690.36/24248.52	% SZS status Ended for HL411272+4.p
183697.53/24249.35	% SZS status Started for HL411272+5.p
183697.53/24249.35	% SZS status GaveUp for HL411272+5.p
183697.53/24249.35	eprover: CPU time limit exceeded, terminating
183697.53/24249.35	% SZS status Ended for HL411272+5.p
183698.06/24249.45	% SZS status Started for HL411273+4.p
183698.06/24249.45	% SZS status GaveUp for HL411273+4.p
183698.06/24249.45	eprover: CPU time limit exceeded, terminating
183698.06/24249.45	% SZS status Ended for HL411273+4.p
183698.42/24249.49	% SZS status Started for HL411273+5.p
183698.42/24249.49	% SZS status GaveUp for HL411273+5.p
183698.42/24249.49	eprover: CPU time limit exceeded, terminating
183698.42/24249.49	% SZS status Ended for HL411273+5.p
183698.42/24249.50	% SZS status Started for HL411274+4.p
183698.42/24249.50	% SZS status GaveUp for HL411274+4.p
183698.42/24249.50	eprover: CPU time limit exceeded, terminating
183698.42/24249.50	% SZS status Ended for HL411274+4.p
183712.47/24251.29	% SZS status Started for HL411274+5.p
183712.47/24251.29	% SZS status GaveUp for HL411274+5.p
183712.47/24251.29	eprover: CPU time limit exceeded, terminating
183712.47/24251.29	% SZS status Ended for HL411274+5.p
183714.22/24251.49	% SZS status Started for HL411275+5.p
183714.22/24251.49	% SZS status GaveUp for HL411275+5.p
183714.22/24251.49	eprover: CPU time limit exceeded, terminating
183714.22/24251.49	% SZS status Ended for HL411275+5.p
183714.75/24251.53	% SZS status Started for HL411275+4.p
183714.75/24251.53	% SZS status GaveUp for HL411275+4.p
183714.75/24251.53	eprover: CPU time limit exceeded, terminating
183714.75/24251.53	% SZS status Ended for HL411275+4.p
183714.98/24251.56	% SZS status Started for HL411276+4.p
183714.98/24251.56	% SZS status GaveUp for HL411276+4.p
183714.98/24251.56	eprover: CPU time limit exceeded, terminating
183714.98/24251.56	% SZS status Ended for HL411276+4.p
183721.58/24252.39	% SZS status Started for HL411276+5.p
183721.58/24252.39	% SZS status GaveUp for HL411276+5.p
183721.58/24252.39	eprover: CPU time limit exceeded, terminating
183721.58/24252.39	% SZS status Ended for HL411276+5.p
183722.30/24252.48	% SZS status Started for HL411277+4.p
183722.30/24252.48	% SZS status GaveUp for HL411277+4.p
183722.30/24252.48	eprover: CPU time limit exceeded, terminating
183722.30/24252.48	% SZS status Ended for HL411277+4.p
183722.64/24252.53	% SZS status Started for HL411278+4.p
183722.64/24252.53	% SZS status GaveUp for HL411278+4.p
183722.64/24252.53	eprover: CPU time limit exceeded, terminating
183722.64/24252.53	% SZS status Ended for HL411278+4.p
183722.64/24252.54	% SZS status Started for HL411277+5.p
183722.64/24252.54	% SZS status GaveUp for HL411277+5.p
183722.64/24252.54	eprover: CPU time limit exceeded, terminating
183722.64/24252.54	% SZS status Ended for HL411277+5.p
183736.69/24254.32	% SZS status Started for HL411278+5.p
183736.69/24254.32	% SZS status GaveUp for HL411278+5.p
183736.69/24254.32	eprover: CPU time limit exceeded, terminating
183736.69/24254.32	% SZS status Ended for HL411278+5.p
183738.67/24254.56	% SZS status Started for HL411279+5.p
183738.67/24254.56	% SZS status GaveUp for HL411279+5.p
183738.67/24254.56	eprover: CPU time limit exceeded, terminating
183738.67/24254.56	% SZS status Ended for HL411279+5.p
183738.67/24254.60	% SZS status Started for HL411280+4.p
183738.67/24254.60	% SZS status GaveUp for HL411280+4.p
183738.67/24254.60	eprover: CPU time limit exceeded, terminating
183738.67/24254.60	% SZS status Ended for HL411280+4.p
183739.23/24254.66	% SZS status Started for HL411279+4.p
183739.23/24254.66	% SZS status GaveUp for HL411279+4.p
183739.23/24254.66	eprover: CPU time limit exceeded, terminating
183739.23/24254.66	% SZS status Ended for HL411279+4.p
183745.20/24255.43	% SZS status Started for HL411280+5.p
183745.20/24255.43	% SZS status GaveUp for HL411280+5.p
183745.20/24255.43	eprover: CPU time limit exceeded, terminating
183745.20/24255.43	% SZS status Ended for HL411280+5.p
183746.31/24255.51	% SZS status Started for HL411281+4.p
183746.31/24255.51	% SZS status GaveUp for HL411281+4.p
183746.31/24255.51	eprover: CPU time limit exceeded, terminating
183746.31/24255.51	% SZS status Ended for HL411281+4.p
183746.72/24255.58	% SZS status Started for HL411283+4.p
183746.72/24255.58	% SZS status GaveUp for HL411283+4.p
183746.72/24255.58	eprover: CPU time limit exceeded, terminating
183746.72/24255.58	% SZS status Ended for HL411283+4.p
183746.72/24255.58	% SZS status Started for HL411281+5.p
183746.72/24255.58	% SZS status GaveUp for HL411281+5.p
183746.72/24255.58	eprover: CPU time limit exceeded, terminating
183746.72/24255.58	% SZS status Ended for HL411281+5.p
183761.16/24257.36	% SZS status Started for HL411283+5.p
183761.16/24257.36	% SZS status GaveUp for HL411283+5.p
183761.16/24257.36	eprover: CPU time limit exceeded, terminating
183761.16/24257.36	% SZS status Ended for HL411283+5.p
183762.44/24257.60	% SZS status Started for HL411284+4.p
183762.44/24257.60	% SZS status GaveUp for HL411284+4.p
183762.44/24257.60	eprover: CPU time limit exceeded, terminating
183762.44/24257.60	% SZS status Ended for HL411284+4.p
183763.62/24257.71	% SZS status Started for HL411286+4.p
183763.62/24257.71	% SZS status GaveUp for HL411286+4.p
183763.62/24257.71	eprover: CPU time limit exceeded, terminating
183763.62/24257.71	% SZS status Ended for HL411286+4.p
183763.62/24257.75	% SZS status Started for HL411284+5.p
183763.62/24257.75	% SZS status GaveUp for HL411284+5.p
183763.62/24257.75	eprover: CPU time limit exceeded, terminating
183763.62/24257.75	% SZS status Ended for HL411284+5.p
183769.58/24258.47	% SZS status Started for HL411286+5.p
183769.58/24258.47	% SZS status GaveUp for HL411286+5.p
183769.58/24258.47	eprover: CPU time limit exceeded, terminating
183769.58/24258.47	% SZS status Ended for HL411286+5.p
183770.17/24258.55	% SZS status Started for HL411288+4.p
183770.17/24258.55	% SZS status GaveUp for HL411288+4.p
183770.17/24258.55	eprover: CPU time limit exceeded, terminating
183770.17/24258.55	% SZS status Ended for HL411288+4.p
183770.88/24258.61	% SZS status Started for HL411288+5.p
183770.88/24258.61	% SZS status GaveUp for HL411288+5.p
183770.88/24258.61	eprover: CPU time limit exceeded, terminating
183770.88/24258.61	% SZS status Ended for HL411288+5.p
183771.09/24258.63	% SZS status Started for HL411289+4.p
183771.09/24258.63	% SZS status GaveUp for HL411289+4.p
183771.09/24258.63	eprover: CPU time limit exceeded, terminating
183771.09/24258.63	% SZS status Ended for HL411289+4.p
183785.20/24260.40	% SZS status Started for HL411289+5.p
183785.20/24260.40	% SZS status GaveUp for HL411289+5.p
183785.20/24260.40	eprover: CPU time limit exceeded, terminating
183785.20/24260.40	% SZS status Ended for HL411289+5.p
183787.73/24260.75	% SZS status Started for HL411290+5.p
183787.73/24260.75	% SZS status GaveUp for HL411290+5.p
183787.73/24260.75	eprover: CPU time limit exceeded, terminating
183787.73/24260.75	% SZS status Ended for HL411290+5.p
183788.19/24260.78	% SZS status Started for HL411290+4.p
183788.19/24260.78	% SZS status GaveUp for HL411290+4.p
183788.19/24260.78	eprover: CPU time limit exceeded, terminating
183788.19/24260.78	% SZS status Ended for HL411290+4.p
183788.19/24260.80	% SZS status Started for HL411291+4.p
183788.19/24260.80	% SZS status GaveUp for HL411291+4.p
183788.19/24260.80	eprover: CPU time limit exceeded, terminating
183788.19/24260.80	% SZS status Ended for HL411291+4.p
183794.06/24261.51	% SZS status Started for HL411291+5.p
183794.06/24261.51	% SZS status GaveUp for HL411291+5.p
183794.06/24261.51	eprover: CPU time limit exceeded, terminating
183794.06/24261.51	% SZS status Ended for HL411291+5.p
183794.66/24261.58	% SZS status Started for HL411292+4.p
183794.66/24261.58	% SZS status GaveUp for HL411292+4.p
183794.66/24261.58	eprover: CPU time limit exceeded, terminating
183794.66/24261.58	% SZS status Ended for HL411292+4.p
183795.00/24261.64	% SZS status Started for HL411292+5.p
183795.00/24261.64	% SZS status GaveUp for HL411292+5.p
183795.00/24261.64	eprover: CPU time limit exceeded, terminating
183795.00/24261.64	% SZS status Ended for HL411292+5.p
183795.00/24261.66	% SZS status Started for HL411293+4.p
183795.00/24261.66	% SZS status GaveUp for HL411293+4.p
183795.00/24261.66	eprover: CPU time limit exceeded, terminating
183795.00/24261.66	% SZS status Ended for HL411293+4.p
183808.86/24263.44	% SZS status Started for HL411293+5.p
183808.86/24263.44	% SZS status GaveUp for HL411293+5.p
183808.86/24263.44	eprover: CPU time limit exceeded, terminating
183808.86/24263.44	% SZS status Ended for HL411293+5.p
183814.25/24263.82	% SZS status Started for HL411294+5.p
183814.25/24263.82	% SZS status GaveUp for HL411294+5.p
183814.25/24263.82	eprover: CPU time limit exceeded, terminating
183814.25/24263.82	% SZS status Ended for HL411294+5.p
183814.25/24263.84	% SZS status Started for HL411296+4.p
183814.25/24263.84	% SZS status GaveUp for HL411296+4.p
183814.25/24263.84	eprover: CPU time limit exceeded, terminating
183814.25/24263.84	% SZS status Ended for HL411296+4.p
183814.97/24263.92	% SZS status Started for HL411294+4.p
183814.97/24263.92	% SZS status GaveUp for HL411294+4.p
183814.97/24263.92	eprover: CPU time limit exceeded, terminating
183814.97/24263.92	% SZS status Ended for HL411294+4.p
183819.48/24264.55	% SZS status Started for HL411296+5.p
183819.48/24264.55	% SZS status GaveUp for HL411296+5.p
183819.48/24264.55	eprover: CPU time limit exceeded, terminating
183819.48/24264.55	% SZS status Ended for HL411296+5.p
183821.09/24264.62	% SZS status Started for HL411297+4.p
183821.09/24264.62	% SZS status GaveUp for HL411297+4.p
183821.09/24264.62	eprover: CPU time limit exceeded, terminating
183821.09/24264.62	% SZS status Ended for HL411297+4.p
183821.52/24264.68	% SZS status Started for HL411297+5.p
183821.52/24264.68	% SZS status GaveUp for HL411297+5.p
183821.52/24264.68	eprover: CPU time limit exceeded, terminating
183821.52/24264.68	% SZS status Ended for HL411297+5.p
183821.52/24264.70	% SZS status Started for HL411298+4.p
183821.52/24264.70	% SZS status GaveUp for HL411298+4.p
183821.52/24264.70	eprover: CPU time limit exceeded, terminating
183821.52/24264.70	% SZS status Ended for HL411298+4.p
183835.77/24266.48	% SZS status Started for HL411298+5.p
183835.77/24266.48	% SZS status GaveUp for HL411298+5.p
183835.77/24266.48	eprover: CPU time limit exceeded, terminating
183835.77/24266.48	% SZS status Ended for HL411298+5.p
183838.86/24266.86	% SZS status Started for HL411299+4.p
183838.86/24266.86	% SZS status GaveUp for HL411299+4.p
183838.86/24266.86	eprover: CPU time limit exceeded, terminating
183838.86/24266.86	% SZS status Ended for HL411299+4.p
183838.86/24266.88	% SZS status Started for HL411299+5.p
183838.86/24266.88	% SZS status GaveUp for HL411299+5.p
183838.86/24266.88	eprover: CPU time limit exceeded, terminating
183838.86/24266.88	% SZS status Ended for HL411299+5.p
183840.03/24267.06	% SZS status Started for HL411300+4.p
183840.03/24267.06	% SZS status GaveUp for HL411300+4.p
183840.03/24267.06	eprover: CPU time limit exceeded, terminating
183840.03/24267.06	% SZS status Ended for HL411300+4.p
183844.58/24267.59	% SZS status Started for HL411300+5.p
183844.58/24267.59	% SZS status GaveUp for HL411300+5.p
183844.58/24267.59	eprover: CPU time limit exceeded, terminating
183844.58/24267.59	% SZS status Ended for HL411300+5.p
183845.20/24267.65	% SZS status Started for HL411302+4.p
183845.20/24267.65	% SZS status GaveUp for HL411302+4.p
183845.20/24267.65	eprover: CPU time limit exceeded, terminating
183845.20/24267.65	% SZS status Ended for HL411302+4.p
183845.67/24267.74	% SZS status Started for HL411303+4.p
183845.67/24267.74	% SZS status GaveUp for HL411303+4.p
183845.67/24267.74	eprover: CPU time limit exceeded, terminating
183845.67/24267.74	% SZS status Ended for HL411303+4.p
183845.78/24267.81	% SZS status Started for HL411302+5.p
183845.78/24267.81	% SZS status GaveUp for HL411302+5.p
183845.78/24267.81	eprover: CPU time limit exceeded, terminating
183845.78/24267.81	% SZS status Ended for HL411302+5.p
183859.56/24269.51	% SZS status Started for HL411303+5.p
183859.56/24269.51	% SZS status GaveUp for HL411303+5.p
183859.56/24269.51	eprover: CPU time limit exceeded, terminating
183859.56/24269.51	% SZS status Ended for HL411303+5.p
183862.62/24269.89	% SZS status Started for HL411304+4.p
183862.62/24269.89	% SZS status GaveUp for HL411304+4.p
183862.62/24269.89	eprover: CPU time limit exceeded, terminating
183862.62/24269.89	% SZS status Ended for HL411304+4.p
183863.17/24269.92	% SZS status Started for HL411304+5.p
183863.17/24269.92	% SZS status GaveUp for HL411304+5.p
183863.17/24269.92	eprover: CPU time limit exceeded, terminating
183863.17/24269.92	% SZS status Ended for HL411304+5.p
183864.25/24270.09	% SZS status Started for HL411306+4.p
183864.25/24270.09	% SZS status GaveUp for HL411306+4.p
183864.25/24270.09	eprover: CPU time limit exceeded, terminating
183864.25/24270.09	% SZS status Ended for HL411306+4.p
183868.55/24270.63	% SZS status Started for HL411306+5.p
183868.55/24270.63	% SZS status GaveUp for HL411306+5.p
183868.55/24270.63	eprover: CPU time limit exceeded, terminating
183868.55/24270.63	% SZS status Ended for HL411306+5.p
183869.31/24270.69	% SZS status Started for HL411307+4.p
183869.31/24270.69	% SZS status GaveUp for HL411307+4.p
183869.31/24270.69	eprover: CPU time limit exceeded, terminating
183869.31/24270.69	% SZS status Ended for HL411307+4.p
183870.48/24270.85	% SZS status Started for HL411308+4.p
183870.48/24270.85	% SZS status GaveUp for HL411308+4.p
183870.48/24270.85	eprover: CPU time limit exceeded, terminating
183870.48/24270.85	% SZS status Ended for HL411308+4.p
183871.08/24270.94	% SZS status Started for HL411307+5.p
183871.08/24270.94	% SZS status GaveUp for HL411307+5.p
183871.08/24270.94	eprover: CPU time limit exceeded, terminating
183871.08/24270.94	% SZS status Ended for HL411307+5.p
183884.03/24272.56	% SZS status Started for HL411308+5.p
183884.03/24272.56	% SZS status GaveUp for HL411308+5.p
183884.03/24272.56	eprover: CPU time limit exceeded, terminating
183884.03/24272.56	% SZS status Ended for HL411308+5.p
183886.38/24272.93	% SZS status Started for HL411310+4.p
183886.38/24272.93	% SZS status GaveUp for HL411310+4.p
183886.38/24272.93	eprover: CPU time limit exceeded, terminating
183886.38/24272.93	% SZS status Ended for HL411310+4.p
183886.94/24272.96	% SZS status Started for HL411310+5.p
183886.94/24272.96	% SZS status GaveUp for HL411310+5.p
183886.94/24272.96	eprover: CPU time limit exceeded, terminating
183886.94/24272.96	% SZS status Ended for HL411310+5.p
183888.27/24273.13	% SZS status Started for HL411311+4.p
183888.27/24273.13	% SZS status GaveUp for HL411311+4.p
183888.27/24273.13	eprover: CPU time limit exceeded, terminating
183888.27/24273.13	% SZS status Ended for HL411311+4.p
183892.61/24273.67	% SZS status Started for HL411311+5.p
183892.61/24273.67	% SZS status GaveUp for HL411311+5.p
183892.61/24273.67	eprover: CPU time limit exceeded, terminating
183892.61/24273.67	% SZS status Ended for HL411311+5.p
183893.03/24273.73	% SZS status Started for HL411312+4.p
183893.03/24273.73	% SZS status GaveUp for HL411312+4.p
183893.03/24273.73	eprover: CPU time limit exceeded, terminating
183893.03/24273.73	% SZS status Ended for HL411312+4.p
183894.92/24273.98	% SZS status Started for HL411313+4.p
183894.92/24273.98	% SZS status GaveUp for HL411313+4.p
183894.92/24273.98	eprover: CPU time limit exceeded, terminating
183894.92/24273.98	% SZS status Ended for HL411313+4.p
183894.92/24274.02	% SZS status Started for HL411312+5.p
183894.92/24274.02	% SZS status GaveUp for HL411312+5.p
183894.92/24274.02	eprover: CPU time limit exceeded, terminating
183894.92/24274.02	% SZS status Ended for HL411312+5.p
183907.92/24275.59	% SZS status Started for HL411313+5.p
183907.92/24275.59	% SZS status GaveUp for HL411313+5.p
183907.92/24275.59	eprover: CPU time limit exceeded, terminating
183907.92/24275.59	% SZS status Ended for HL411313+5.p
183911.14/24275.96	% SZS status Started for HL411314+4.p
183911.14/24275.96	% SZS status GaveUp for HL411314+4.p
183911.14/24275.96	eprover: CPU time limit exceeded, terminating
183911.14/24275.96	% SZS status Ended for HL411314+4.p
183911.39/24276.00	% SZS status Started for HL411314+5.p
183911.39/24276.00	% SZS status GaveUp for HL411314+5.p
183911.39/24276.00	eprover: CPU time limit exceeded, terminating
183911.39/24276.00	% SZS status Ended for HL411314+5.p
183912.53/24276.17	% SZS status Started for HL411315+4.p
183912.53/24276.17	% SZS status GaveUp for HL411315+4.p
183912.53/24276.17	eprover: CPU time limit exceeded, terminating
183912.53/24276.17	% SZS status Ended for HL411315+4.p
183916.66/24276.70	% SZS status Started for HL411315+5.p
183916.66/24276.70	% SZS status GaveUp for HL411315+5.p
183916.66/24276.70	eprover: CPU time limit exceeded, terminating
183916.66/24276.70	% SZS status Ended for HL411315+5.p
183917.42/24276.76	% SZS status Started for HL411316+4.p
183917.42/24276.76	% SZS status GaveUp for HL411316+4.p
183917.42/24276.76	eprover: CPU time limit exceeded, terminating
183917.42/24276.76	% SZS status Ended for HL411316+4.p
183919.20/24277.07	% SZS status Started for HL411317+4.p
183919.20/24277.07	% SZS status GaveUp for HL411317+4.p
183919.20/24277.07	eprover: CPU time limit exceeded, terminating
183919.20/24277.07	% SZS status Ended for HL411317+4.p
183920.45/24277.19	% SZS status Started for HL411316+5.p
183920.45/24277.19	% SZS status GaveUp for HL411316+5.p
183920.45/24277.19	eprover: CPU time limit exceeded, terminating
183920.45/24277.19	% SZS status Ended for HL411316+5.p
183932.30/24278.63	% SZS status Started for HL411317+5.p
183932.30/24278.63	% SZS status GaveUp for HL411317+5.p
183932.30/24278.63	eprover: CPU time limit exceeded, terminating
183932.30/24278.63	% SZS status Ended for HL411317+5.p
183934.77/24279.02	% SZS status Started for HL411318+4.p
183934.77/24279.02	% SZS status GaveUp for HL411318+4.p
183934.77/24279.02	eprover: CPU time limit exceeded, terminating
183934.77/24279.02	% SZS status Ended for HL411318+4.p
183934.77/24279.04	% SZS status Started for HL411318+5.p
183934.77/24279.04	% SZS status GaveUp for HL411318+5.p
183934.77/24279.04	eprover: CPU time limit exceeded, terminating
183934.77/24279.04	% SZS status Ended for HL411318+5.p
183936.66/24279.21	% SZS status Started for HL411319+4.p
183936.66/24279.21	% SZS status GaveUp for HL411319+4.p
183936.66/24279.21	eprover: CPU time limit exceeded, terminating
183936.66/24279.21	% SZS status Ended for HL411319+4.p
183940.77/24279.74	% SZS status Started for HL411319+5.p
183940.77/24279.74	% SZS status GaveUp for HL411319+5.p
183940.77/24279.74	eprover: CPU time limit exceeded, terminating
183940.77/24279.74	% SZS status Ended for HL411319+5.p
183941.58/24279.80	% SZS status Started for HL411320+4.p
183941.58/24279.80	% SZS status GaveUp for HL411320+4.p
183941.58/24279.80	eprover: CPU time limit exceeded, terminating
183941.58/24279.80	% SZS status Ended for HL411320+4.p
183943.42/24280.11	% SZS status Started for HL411320+5.p
183943.42/24280.11	% SZS status GaveUp for HL411320+5.p
183943.42/24280.11	eprover: CPU time limit exceeded, terminating
183943.42/24280.11	% SZS status Ended for HL411320+5.p
183945.52/24280.30	% SZS status Started for HL411322+4.p
183945.52/24280.30	% SZS status GaveUp for HL411322+4.p
183945.52/24280.30	eprover: CPU time limit exceeded, terminating
183945.52/24280.30	% SZS status Ended for HL411322+4.p
183957.19/24281.79	% SZS status Started for HL411322+5.p
183957.19/24281.79	% SZS status GaveUp for HL411322+5.p
183957.19/24281.79	eprover: CPU time limit exceeded, terminating
183957.19/24281.79	% SZS status Ended for HL411322+5.p
183959.30/24282.04	% SZS status Started for HL411324+4.p
183959.30/24282.04	% SZS status GaveUp for HL411324+4.p
183959.30/24282.04	eprover: CPU time limit exceeded, terminating
183959.30/24282.04	% SZS status Ended for HL411324+4.p
183959.73/24282.09	% SZS status Started for HL411324+5.p
183959.73/24282.09	% SZS status GaveUp for HL411324+5.p
183959.73/24282.09	eprover: CPU time limit exceeded, terminating
183959.73/24282.09	% SZS status Ended for HL411324+5.p
183960.84/24282.25	% SZS status Started for HL411325+4.p
183960.84/24282.25	% SZS status GaveUp for HL411325+4.p
183960.84/24282.25	eprover: CPU time limit exceeded, terminating
183960.84/24282.25	% SZS status Ended for HL411325+4.p
183965.12/24282.78	% SZS status Started for HL411325+5.p
183965.12/24282.78	% SZS status GaveUp for HL411325+5.p
183965.12/24282.78	eprover: CPU time limit exceeded, terminating
183965.12/24282.78	% SZS status Ended for HL411325+5.p
183965.78/24282.84	% SZS status Started for HL411327+4.p
183965.78/24282.84	% SZS status GaveUp for HL411327+4.p
183965.78/24282.84	eprover: CPU time limit exceeded, terminating
183965.78/24282.84	% SZS status Ended for HL411327+4.p
183967.59/24283.14	% SZS status Started for HL411327+5.p
183967.59/24283.14	% SZS status GaveUp for HL411327+5.p
183967.59/24283.14	eprover: CPU time limit exceeded, terminating
183967.59/24283.14	% SZS status Ended for HL411327+5.p
183969.03/24283.34	% SZS status Started for HL411328+4.p
183969.03/24283.34	% SZS status GaveUp for HL411328+4.p
183969.03/24283.34	eprover: CPU time limit exceeded, terminating
183969.03/24283.34	% SZS status Ended for HL411328+4.p
183982.39/24284.96	% SZS status Started for HL411328+5.p
183982.39/24284.96	% SZS status GaveUp for HL411328+5.p
183982.39/24284.96	eprover: CPU time limit exceeded, terminating
183982.39/24284.96	% SZS status Ended for HL411328+5.p
183983.55/24285.08	% SZS status Started for HL411329+4.p
183983.55/24285.08	% SZS status GaveUp for HL411329+4.p
183983.55/24285.08	eprover: CPU time limit exceeded, terminating
183983.55/24285.08	% SZS status Ended for HL411329+4.p
183983.95/24285.13	% SZS status Started for HL411329+5.p
183983.95/24285.13	% SZS status GaveUp for HL411329+5.p
183983.95/24285.13	eprover: CPU time limit exceeded, terminating
183983.95/24285.13	% SZS status Ended for HL411329+5.p
183985.25/24285.29	% SZS status Started for HL411330+4.p
183985.25/24285.29	% SZS status GaveUp for HL411330+4.p
183985.25/24285.29	eprover: CPU time limit exceeded, terminating
183985.25/24285.29	% SZS status Ended for HL411330+4.p
183989.20/24285.82	% SZS status Started for HL411330+5.p
183989.20/24285.82	% SZS status GaveUp for HL411330+5.p
183989.20/24285.82	eprover: CPU time limit exceeded, terminating
183989.20/24285.82	% SZS status Ended for HL411330+5.p
183989.88/24285.88	% SZS status Started for HL411331+4.p
183989.88/24285.88	% SZS status GaveUp for HL411331+4.p
183989.88/24285.88	eprover: CPU time limit exceeded, terminating
183989.88/24285.88	% SZS status Ended for HL411331+4.p
183991.72/24286.18	% SZS status Started for HL411331+5.p
183991.72/24286.18	% SZS status GaveUp for HL411331+5.p
183991.72/24286.18	eprover: CPU time limit exceeded, terminating
183991.72/24286.18	% SZS status Ended for HL411331+5.p
183993.95/24286.39	% SZS status Started for HL411332+4.p
183993.95/24286.39	% SZS status GaveUp for HL411332+4.p
183993.95/24286.39	eprover: CPU time limit exceeded, terminating
183993.95/24286.39	% SZS status Ended for HL411332+4.p
184007.59/24288.12	% SZS status Started for HL411333+4.p
184007.59/24288.12	% SZS status GaveUp for HL411333+4.p
184007.59/24288.12	eprover: CPU time limit exceeded, terminating
184007.59/24288.12	% SZS status Ended for HL411333+4.p
184007.59/24288.15	% SZS status Started for HL411332+5.p
184007.59/24288.15	% SZS status GaveUp for HL411332+5.p
184007.59/24288.15	eprover: CPU time limit exceeded, terminating
184007.59/24288.15	% SZS status Ended for HL411332+5.p
184008.22/24288.18	% SZS status Started for HL411333+5.p
184008.22/24288.18	% SZS status GaveUp for HL411333+5.p
184008.22/24288.18	eprover: CPU time limit exceeded, terminating
184008.22/24288.18	% SZS status Ended for HL411333+5.p
184009.00/24288.33	% SZS status Started for HL411334+4.p
184009.00/24288.33	% SZS status GaveUp for HL411334+4.p
184009.00/24288.33	eprover: CPU time limit exceeded, terminating
184009.00/24288.33	% SZS status Ended for HL411334+4.p
184013.64/24288.86	% SZS status Started for HL411334+5.p
184013.64/24288.86	% SZS status GaveUp for HL411334+5.p
184013.64/24288.86	eprover: CPU time limit exceeded, terminating
184013.64/24288.86	% SZS status Ended for HL411334+5.p
184013.64/24288.91	% SZS status Started for HL411336+4.p
184013.64/24288.91	% SZS status GaveUp for HL411336+4.p
184013.64/24288.91	eprover: CPU time limit exceeded, terminating
184013.64/24288.91	% SZS status Ended for HL411336+4.p
184016.17/24289.21	% SZS status Started for HL411336+5.p
184016.17/24289.21	% SZS status GaveUp for HL411336+5.p
184016.17/24289.21	eprover: CPU time limit exceeded, terminating
184016.17/24289.21	% SZS status Ended for HL411336+5.p
184018.05/24289.43	% SZS status Started for HL411337+4.p
184018.05/24289.43	% SZS status GaveUp for HL411337+4.p
184018.05/24289.43	eprover: CPU time limit exceeded, terminating
184018.05/24289.43	% SZS status Ended for HL411337+4.p
184031.83/24291.15	% SZS status Started for HL411337+5.p
184031.83/24291.15	% SZS status GaveUp for HL411337+5.p
184031.83/24291.15	eprover: CPU time limit exceeded, terminating
184031.83/24291.15	% SZS status Ended for HL411337+5.p
184032.25/24291.21	% SZS status Started for HL411338+5.p
184032.25/24291.21	% SZS status GaveUp for HL411338+5.p
184032.25/24291.21	eprover: CPU time limit exceeded, terminating
184032.25/24291.21	% SZS status Ended for HL411338+5.p
184032.66/24291.31	% SZS status Started for HL411338+4.p
184032.66/24291.31	% SZS status GaveUp for HL411338+4.p
184032.66/24291.31	eprover: CPU time limit exceeded, terminating
184032.66/24291.31	% SZS status Ended for HL411338+4.p
184033.23/24291.38	% SZS status Started for HL411342+4.p
184033.23/24291.38	% SZS status GaveUp for HL411342+4.p
184033.23/24291.38	eprover: CPU time limit exceeded, terminating
184033.23/24291.38	% SZS status Ended for HL411342+4.p
184037.33/24291.89	% SZS status Started for HL411342+5.p
184037.33/24291.89	% SZS status GaveUp for HL411342+5.p
184037.33/24291.89	eprover: CPU time limit exceeded, terminating
184037.33/24291.89	% SZS status Ended for HL411342+5.p
184037.95/24291.95	% SZS status Started for HL411343+4.p
184037.95/24291.95	% SZS status GaveUp for HL411343+4.p
184037.95/24291.95	eprover: CPU time limit exceeded, terminating
184037.95/24291.95	% SZS status Ended for HL411343+4.p
184040.58/24292.26	% SZS status Started for HL411343+5.p
184040.58/24292.26	% SZS status GaveUp for HL411343+5.p
184040.58/24292.26	eprover: CPU time limit exceeded, terminating
184040.58/24292.26	% SZS status Ended for HL411343+5.p
184042.11/24292.47	% SZS status Started for HL411345+4.p
184042.11/24292.47	% SZS status GaveUp for HL411345+4.p
184042.11/24292.47	eprover: CPU time limit exceeded, terminating
184042.11/24292.47	% SZS status Ended for HL411345+4.p
184055.53/24294.19	% SZS status Started for HL411345+5.p
184055.53/24294.19	% SZS status GaveUp for HL411345+5.p
184055.53/24294.19	eprover: CPU time limit exceeded, terminating
184055.53/24294.19	% SZS status Ended for HL411345+5.p
184056.09/24294.25	% SZS status Started for HL411346+4.p
184056.09/24294.25	% SZS status GaveUp for HL411346+4.p
184056.09/24294.25	eprover: CPU time limit exceeded, terminating
184056.09/24294.25	% SZS status Ended for HL411346+4.p
184057.06/24294.35	% SZS status Started for HL411346+5.p
184057.06/24294.35	% SZS status GaveUp for HL411346+5.p
184057.06/24294.35	eprover: CPU time limit exceeded, terminating
184057.06/24294.35	% SZS status Ended for HL411346+5.p
184058.59/24294.59	% SZS status Started for HL411348+4.p
184058.59/24294.59	% SZS status GaveUp for HL411348+4.p
184058.59/24294.59	eprover: CPU time limit exceeded, terminating
184058.59/24294.59	% SZS status Ended for HL411348+4.p
184061.86/24294.93	% SZS status Started for HL411348+5.p
184061.86/24294.93	% SZS status GaveUp for HL411348+5.p
184061.86/24294.93	eprover: CPU time limit exceeded, terminating
184061.86/24294.93	% SZS status Ended for HL411348+5.p
184061.86/24294.98	% SZS status Started for HL411349+4.p
184061.86/24294.98	% SZS status GaveUp for HL411349+4.p
184061.86/24294.98	eprover: CPU time limit exceeded, terminating
184061.86/24294.98	% SZS status Ended for HL411349+4.p
184064.17/24295.30	% SZS status Started for HL411349+5.p
184064.17/24295.30	% SZS status GaveUp for HL411349+5.p
184064.17/24295.30	eprover: CPU time limit exceeded, terminating
184064.17/24295.30	% SZS status Ended for HL411349+5.p
184066.00/24295.51	% SZS status Started for HL411350+4.p
184066.00/24295.51	% SZS status GaveUp for HL411350+4.p
184066.00/24295.51	eprover: CPU time limit exceeded, terminating
184066.00/24295.51	% SZS status Ended for HL411350+4.p
184080.02/24297.23	% SZS status Started for HL411350+5.p
184080.02/24297.23	% SZS status GaveUp for HL411350+5.p
184080.02/24297.23	eprover: CPU time limit exceeded, terminating
184080.02/24297.23	% SZS status Ended for HL411350+5.p
184080.41/24297.29	% SZS status Started for HL411351+4.p
184080.41/24297.29	% SZS status GaveUp for HL411351+4.p
184080.41/24297.29	eprover: CPU time limit exceeded, terminating
184080.41/24297.29	% SZS status Ended for HL411351+4.p
184081.20/24297.39	% SZS status Started for HL411351+5.p
184081.20/24297.39	% SZS status GaveUp for HL411351+5.p
184081.20/24297.39	eprover: CPU time limit exceeded, terminating
184081.20/24297.39	% SZS status Ended for HL411351+5.p
184082.09/24297.64	% SZS status Started for HL411352+4.p
184082.09/24297.64	% SZS status GaveUp for HL411352+4.p
184082.09/24297.64	eprover: CPU time limit exceeded, terminating
184082.09/24297.64	% SZS status Ended for HL411352+4.p
184085.64/24297.96	% SZS status Started for HL411352+5.p
184085.64/24297.96	% SZS status GaveUp for HL411352+5.p
184085.64/24297.96	eprover: CPU time limit exceeded, terminating
184085.64/24297.96	% SZS status Ended for HL411352+5.p
184086.19/24298.02	% SZS status Started for HL411353+4.p
184086.19/24298.02	% SZS status GaveUp for HL411353+4.p
184086.19/24298.02	eprover: CPU time limit exceeded, terminating
184086.19/24298.02	% SZS status Ended for HL411353+4.p
184090.11/24298.50	% SZS status Started for HL411353+5.p
184090.11/24298.50	% SZS status GaveUp for HL411353+5.p
184090.11/24298.50	eprover: CPU time limit exceeded, terminating
184090.11/24298.50	% SZS status Ended for HL411353+5.p
184090.41/24298.55	% SZS status Started for HL411354+4.p
184090.41/24298.55	% SZS status GaveUp for HL411354+4.p
184090.41/24298.55	eprover: CPU time limit exceeded, terminating
184090.41/24298.55	% SZS status Ended for HL411354+4.p
184103.86/24300.26	% SZS status Started for HL411354+5.p
184103.86/24300.26	% SZS status GaveUp for HL411354+5.p
184103.86/24300.26	eprover: CPU time limit exceeded, terminating
184103.86/24300.26	% SZS status Ended for HL411354+5.p
184104.42/24300.32	% SZS status Started for HL411355+4.p
184104.42/24300.32	% SZS status GaveUp for HL411355+4.p
184104.42/24300.32	eprover: CPU time limit exceeded, terminating
184104.42/24300.32	% SZS status Ended for HL411355+4.p
184105.25/24300.43	% SZS status Started for HL411355+5.p
184105.25/24300.43	% SZS status GaveUp for HL411355+5.p
184105.25/24300.43	eprover: CPU time limit exceeded, terminating
184105.25/24300.43	% SZS status Ended for HL411355+5.p
184107.28/24300.68	% SZS status Started for HL411356+4.p
184107.28/24300.68	% SZS status GaveUp for HL411356+4.p
184107.28/24300.68	eprover: CPU time limit exceeded, terminating
184107.28/24300.68	% SZS status Ended for HL411356+4.p
184109.09/24301.00	% SZS status Started for HL411356+5.p
184109.09/24301.00	% SZS status GaveUp for HL411356+5.p
184109.09/24301.00	eprover: CPU time limit exceeded, terminating
184109.09/24301.00	% SZS status Ended for HL411356+5.p
184109.67/24301.06	% SZS status Started for HL411357+4.p
184109.67/24301.06	% SZS status GaveUp for HL411357+4.p
184109.67/24301.06	eprover: CPU time limit exceeded, terminating
184109.67/24301.06	% SZS status Ended for HL411357+4.p
184114.38/24301.59	% SZS status Started for HL411358+4.p
184114.38/24301.59	% SZS status GaveUp for HL411358+4.p
184114.38/24301.59	eprover: CPU time limit exceeded, terminating
184114.38/24301.59	% SZS status Ended for HL411358+4.p
184114.38/24301.63	% SZS status Started for HL411357+5.p
184114.38/24301.63	% SZS status GaveUp for HL411357+5.p
184114.38/24301.63	eprover: CPU time limit exceeded, terminating
184114.38/24301.63	% SZS status Ended for HL411357+5.p
184127.95/24303.30	% SZS status Started for HL411358+5.p
184127.95/24303.30	% SZS status GaveUp for HL411358+5.p
184127.95/24303.30	eprover: CPU time limit exceeded, terminating
184127.95/24303.30	% SZS status Ended for HL411358+5.p
184128.56/24303.36	% SZS status Started for HL411359+4.p
184128.56/24303.36	% SZS status GaveUp for HL411359+4.p
184128.56/24303.36	eprover: CPU time limit exceeded, terminating
184128.56/24303.36	% SZS status Ended for HL411359+4.p
184129.45/24303.48	% SZS status Started for HL411359+5.p
184129.45/24303.48	% SZS status GaveUp for HL411359+5.p
184129.45/24303.48	eprover: CPU time limit exceeded, terminating
184129.45/24303.48	% SZS status Ended for HL411359+5.p
184131.34/24303.85	% SZS status Started for HL411361+4.p
184131.34/24303.85	% SZS status GaveUp for HL411361+4.p
184131.34/24303.85	eprover: CPU time limit exceeded, terminating
184131.34/24303.85	% SZS status Ended for HL411361+4.p
184135.34/24304.03	% SZS status Started for HL411361+5.p
184135.34/24304.03	% SZS status GaveUp for HL411361+5.p
184135.34/24304.03	eprover: CPU time limit exceeded, terminating
184135.34/24304.03	% SZS status Ended for HL411361+5.p
184136.00/24304.10	% SZS status Started for HL411362+4.p
184136.00/24304.10	% SZS status GaveUp for HL411362+4.p
184136.00/24304.10	eprover: CPU time limit exceeded, terminating
184136.00/24304.10	% SZS status Ended for HL411362+4.p
184140.22/24304.62	% SZS status Started for HL411362+5.p
184140.22/24304.62	% SZS status GaveUp for HL411362+5.p
184140.22/24304.62	eprover: CPU time limit exceeded, terminating
184140.22/24304.62	% SZS status Ended for HL411362+5.p
184140.59/24304.67	% SZS status Started for HL411363+4.p
184140.59/24304.67	% SZS status GaveUp for HL411363+4.p
184140.59/24304.67	eprover: CPU time limit exceeded, terminating
184140.59/24304.67	% SZS status Ended for HL411363+4.p
184154.17/24306.40	% SZS status Started for HL411365+4.p
184154.17/24306.40	% SZS status GaveUp for HL411365+4.p
184154.17/24306.40	eprover: CPU time limit exceeded, terminating
184154.17/24306.40	% SZS status Ended for HL411365+4.p
184154.91/24306.47	% SZS status Started for HL411363+5.p
184154.91/24306.47	% SZS status GaveUp for HL411363+5.p
184154.91/24306.47	eprover: CPU time limit exceeded, terminating
184154.91/24306.47	% SZS status Ended for HL411363+5.p
184155.20/24306.52	% SZS status Started for HL411365+5.p
184155.20/24306.52	% SZS status GaveUp for HL411365+5.p
184155.20/24306.52	eprover: CPU time limit exceeded, terminating
184155.20/24306.52	% SZS status Ended for HL411365+5.p
184157.88/24306.88	% SZS status Started for HL411366+4.p
184157.88/24306.88	% SZS status GaveUp for HL411366+4.p
184157.88/24306.88	eprover: CPU time limit exceeded, terminating
184157.88/24306.88	% SZS status Ended for HL411366+4.p
184159.08/24307.07	% SZS status Started for HL411366+5.p
184159.08/24307.07	% SZS status GaveUp for HL411366+5.p
184159.08/24307.07	eprover: CPU time limit exceeded, terminating
184159.08/24307.07	% SZS status Ended for HL411366+5.p
184160.00/24307.14	% SZS status Started for HL411367+4.p
184160.00/24307.14	% SZS status GaveUp for HL411367+4.p
184160.00/24307.14	eprover: CPU time limit exceeded, terminating
184160.00/24307.14	% SZS status Ended for HL411367+4.p
184164.23/24307.66	% SZS status Started for HL411367+5.p
184164.23/24307.66	% SZS status GaveUp for HL411367+5.p
184164.23/24307.66	eprover: CPU time limit exceeded, terminating
184164.23/24307.66	% SZS status Ended for HL411367+5.p
184164.88/24307.71	% SZS status Started for HL411368+4.p
184164.88/24307.71	% SZS status GaveUp for HL411368+4.p
184164.88/24307.71	eprover: CPU time limit exceeded, terminating
184164.88/24307.71	% SZS status Ended for HL411368+4.p
184178.61/24309.44	% SZS status Started for HL411368+5.p
184178.61/24309.44	% SZS status GaveUp for HL411368+5.p
184178.61/24309.44	eprover: CPU time limit exceeded, terminating
184178.61/24309.44	% SZS status Ended for HL411368+5.p
184178.81/24309.51	% SZS status Started for HL411369+4.p
184178.81/24309.51	% SZS status GaveUp for HL411369+4.p
184178.81/24309.51	eprover: CPU time limit exceeded, terminating
184178.81/24309.51	% SZS status Ended for HL411369+4.p
184179.30/24309.59	% SZS status Started for HL411369+5.p
184179.30/24309.59	% SZS status GaveUp for HL411369+5.p
184179.30/24309.59	eprover: CPU time limit exceeded, terminating
184179.30/24309.59	% SZS status Ended for HL411369+5.p
184185.44/24310.06	% SZS status Started for HL411370+4.p
184185.44/24310.06	% SZS status GaveUp for HL411370+4.p
184185.44/24310.06	eprover: CPU time limit exceeded, terminating
184185.44/24310.06	% SZS status Ended for HL411370+4.p
184185.44/24310.11	% SZS status Started for HL411370+5.p
184185.44/24310.11	% SZS status GaveUp for HL411370+5.p
184185.44/24310.11	eprover: CPU time limit exceeded, terminating
184185.44/24310.11	% SZS status Ended for HL411370+5.p
184185.98/24310.18	% SZS status Started for HL411371+4.p
184185.98/24310.18	% SZS status GaveUp for HL411371+4.p
184185.98/24310.18	eprover: CPU time limit exceeded, terminating
184185.98/24310.18	% SZS status Ended for HL411371+4.p
184190.09/24310.69	% SZS status Started for HL411371+5.p
184190.09/24310.69	% SZS status GaveUp for HL411371+5.p
184190.09/24310.69	eprover: CPU time limit exceeded, terminating
184190.09/24310.69	% SZS status Ended for HL411371+5.p
184191.28/24310.75	% SZS status Started for HL411372+4.p
184191.28/24310.75	% SZS status GaveUp for HL411372+4.p
184191.28/24310.75	eprover: CPU time limit exceeded, terminating
184191.28/24310.75	% SZS status Ended for HL411372+4.p
184204.92/24312.47	% SZS status Started for HL411372+5.p
184204.92/24312.47	% SZS status GaveUp for HL411372+5.p
184204.92/24312.47	eprover: CPU time limit exceeded, terminating
184204.92/24312.47	% SZS status Ended for HL411372+5.p
184205.31/24312.54	% SZS status Started for HL411373+4.p
184205.31/24312.54	% SZS status GaveUp for HL411373+4.p
184205.31/24312.54	eprover: CPU time limit exceeded, terminating
184205.31/24312.54	% SZS status Ended for HL411373+4.p
184206.17/24312.64	% SZS status Started for HL411373+5.p
184206.17/24312.64	% SZS status GaveUp for HL411373+5.p
184206.17/24312.64	eprover: CPU time limit exceeded, terminating
184206.17/24312.64	% SZS status Ended for HL411373+5.p
184209.72/24313.09	% SZS status Started for HL411374+4.p
184209.72/24313.09	% SZS status GaveUp for HL411374+4.p
184209.72/24313.09	eprover: CPU time limit exceeded, terminating
184209.72/24313.09	% SZS status Ended for HL411374+4.p
184210.17/24313.14	% SZS status Started for HL411374+5.p
184210.17/24313.14	% SZS status GaveUp for HL411374+5.p
184210.17/24313.14	eprover: CPU time limit exceeded, terminating
184210.17/24313.14	% SZS status Ended for HL411374+5.p
184210.89/24313.24	% SZS status Started for HL411375+4.p
184210.89/24313.24	% SZS status GaveUp for HL411375+4.p
184210.89/24313.24	eprover: CPU time limit exceeded, terminating
184210.89/24313.24	% SZS status Ended for HL411375+4.p
184215.58/24313.79	% SZS status Started for HL411376+4.p
184215.58/24313.79	% SZS status GaveUp for HL411376+4.p
184215.58/24313.79	eprover: CPU time limit exceeded, terminating
184215.58/24313.79	% SZS status Ended for HL411376+4.p
184215.98/24313.85	% SZS status Started for HL411375+5.p
184215.98/24313.85	% SZS status GaveUp for HL411375+5.p
184215.98/24313.85	eprover: CPU time limit exceeded, terminating
184215.98/24313.85	% SZS status Ended for HL411375+5.p
184229.23/24315.50	% SZS status Started for HL411376+5.p
184229.23/24315.50	% SZS status GaveUp for HL411376+5.p
184229.23/24315.50	eprover: CPU time limit exceeded, terminating
184229.23/24315.50	% SZS status Ended for HL411376+5.p
184229.23/24315.58	% SZS status Started for HL411378+4.p
184229.23/24315.58	% SZS status GaveUp for HL411378+4.p
184229.23/24315.58	eprover: CPU time limit exceeded, terminating
184229.23/24315.58	% SZS status Ended for HL411378+4.p
184229.94/24315.68	% SZS status Started for HL411378+5.p
184229.94/24315.68	% SZS status GaveUp for HL411378+5.p
184229.94/24315.68	eprover: CPU time limit exceeded, terminating
184229.94/24315.68	% SZS status Ended for HL411378+5.p
184234.23/24316.12	% SZS status Started for HL411379+4.p
184234.23/24316.12	% SZS status GaveUp for HL411379+4.p
184234.23/24316.12	eprover: CPU time limit exceeded, terminating
184234.23/24316.12	% SZS status Ended for HL411379+4.p
184234.23/24316.17	% SZS status Started for HL411379+5.p
184234.23/24316.17	% SZS status GaveUp for HL411379+5.p
184234.23/24316.17	eprover: CPU time limit exceeded, terminating
184234.23/24316.17	% SZS status Ended for HL411379+5.p
184234.94/24316.28	% SZS status Started for HL411380+4.p
184234.94/24316.28	% SZS status GaveUp for HL411380+4.p
184234.94/24316.28	eprover: CPU time limit exceeded, terminating
184234.94/24316.28	% SZS status Ended for HL411380+4.p
184240.50/24316.91	% SZS status Started for HL411381+4.p
184240.50/24316.91	% SZS status GaveUp for HL411381+4.p
184240.50/24316.91	eprover: CPU time limit exceeded, terminating
184240.50/24316.91	% SZS status Ended for HL411381+4.p
184254.06/24318.61	% SZS status Started for HL411382+4.p
184254.06/24318.61	% SZS status GaveUp for HL411382+4.p
184254.06/24318.61	eprover: CPU time limit exceeded, terminating
184254.06/24318.61	% SZS status Ended for HL411382+4.p
184258.08/24319.14	% SZS status Started for HL411384+4.p
184258.08/24319.14	% SZS status GaveUp for HL411384+4.p
184258.08/24319.14	eprover: CPU time limit exceeded, terminating
184258.08/24319.14	% SZS status Ended for HL411384+4.p
184259.28/24319.31	% SZS status Started for HL411386+4.p
184259.28/24319.31	% SZS status GaveUp for HL411386+4.p
184259.28/24319.31	eprover: CPU time limit exceeded, terminating
184259.28/24319.31	% SZS status Ended for HL411386+4.p
184277.91/24321.66	% SZS status Started for HL411387+4.p
184277.91/24321.66	% SZS status GaveUp for HL411387+4.p
184277.91/24321.66	eprover: CPU time limit exceeded, terminating
184277.91/24321.66	% SZS status Ended for HL411387+4.p
184282.84/24322.35	% SZS status Started for HL411388+4.p
184282.84/24322.35	% SZS status GaveUp for HL411388+4.p
184282.84/24322.35	eprover: CPU time limit exceeded, terminating
184282.84/24322.35	% SZS status Ended for HL411388+4.p
184304.02/24324.94	% SZS status Started for HL411380+5.p
184304.02/24324.94	% SZS status GaveUp for HL411380+5.p
184304.02/24324.94	eprover: CPU time limit exceeded, terminating
184304.02/24324.94	% SZS status Ended for HL411380+5.p
184307.77/24325.39	% SZS status Started for HL411390+4.p
184307.77/24325.39	% SZS status GaveUp for HL411390+4.p
184307.77/24325.39	eprover: CPU time limit exceeded, terminating
184307.77/24325.39	% SZS status Ended for HL411390+4.p
184313.47/24326.18	% SZS status Started for HL411381+5.p
184313.47/24326.18	% SZS status GaveUp for HL411381+5.p
184313.47/24326.18	eprover: CPU time limit exceeded, terminating
184313.47/24326.18	% SZS status Ended for HL411381+5.p
184313.75/24326.30	% SZS status Started for HL411382+5.p
184313.75/24326.30	% SZS status GaveUp for HL411382+5.p
184313.75/24326.30	eprover: CPU time limit exceeded, terminating
184313.75/24326.30	% SZS status Ended for HL411382+5.p
184318.38/24326.79	% SZS status Started for HL411384+5.p
184318.38/24326.79	% SZS status GaveUp for HL411384+5.p
184318.38/24326.79	eprover: CPU time limit exceeded, terminating
184318.38/24326.79	% SZS status Ended for HL411384+5.p
184324.77/24327.56	% SZS status Started for HL411386+5.p
184324.77/24327.56	% SZS status GaveUp for HL411386+5.p
184324.77/24327.56	eprover: CPU time limit exceeded, terminating
184324.77/24327.56	% SZS status Ended for HL411386+5.p
184331.42/24328.42	% SZS status Started for HL411392+4.p
184331.42/24328.42	% SZS status GaveUp for HL411392+4.p
184331.42/24328.42	eprover: CPU time limit exceeded, terminating
184331.42/24328.42	% SZS status Ended for HL411392+4.p
184339.45/24329.33	% SZS status Started for HL411395+4.p
184339.45/24329.33	% SZS status GaveUp for HL411395+4.p
184339.45/24329.33	eprover: CPU time limit exceeded, terminating
184339.45/24329.33	% SZS status Ended for HL411395+4.p
184343.00/24329.82	% SZS status Started for HL411387+5.p
184343.00/24329.82	% SZS status GaveUp for HL411387+5.p
184343.00/24329.82	eprover: CPU time limit exceeded, terminating
184343.00/24329.82	% SZS status Ended for HL411387+5.p
184349.34/24330.61	% SZS status Started for HL411396+4.p
184349.34/24330.61	% SZS status GaveUp for HL411396+4.p
184349.34/24330.61	eprover: CPU time limit exceeded, terminating
184349.34/24330.61	% SZS status Ended for HL411396+4.p
184363.67/24332.40	% SZS status Started for HL411397+4.p
184363.67/24332.40	% SZS status GaveUp for HL411397+4.p
184363.67/24332.40	eprover: CPU time limit exceeded, terminating
184363.67/24332.40	% SZS status Ended for HL411397+4.p
184363.94/24332.50	% SZS status Started for HL411388+5.p
184363.94/24332.50	% SZS status GaveUp for HL411388+5.p
184363.94/24332.50	eprover: CPU time limit exceeded, terminating
184363.94/24332.50	% SZS status Ended for HL411388+5.p
184373.34/24333.64	% SZS status Started for HL411398+4.p
184373.34/24333.64	% SZS status GaveUp for HL411398+4.p
184373.34/24333.64	eprover: CPU time limit exceeded, terminating
184373.34/24333.64	% SZS status Ended for HL411398+4.p
184388.78/24335.57	% SZS status Started for HL411399+4.p
184388.78/24335.57	% SZS status GaveUp for HL411399+4.p
184388.78/24335.57	eprover: CPU time limit exceeded, terminating
184388.78/24335.57	% SZS status Ended for HL411399+4.p
184388.97/24335.60	% SZS status Started for HL411390+5.p
184388.97/24335.60	% SZS status GaveUp for HL411390+5.p
184388.97/24335.60	eprover: CPU time limit exceeded, terminating
184388.97/24335.60	% SZS status Ended for HL411390+5.p
184398.81/24336.87	% SZS status Started for HL411392+5.p
184398.81/24336.87	% SZS status GaveUp for HL411392+5.p
184398.81/24336.87	eprover: CPU time limit exceeded, terminating
184398.81/24336.87	% SZS status Ended for HL411392+5.p
184403.28/24337.42	% SZS status Started for HL411395+5.p
184403.28/24337.42	% SZS status GaveUp for HL411395+5.p
184403.28/24337.42	eprover: CPU time limit exceeded, terminating
184403.28/24337.42	% SZS status Ended for HL411395+5.p
184411.38/24338.61	% SZS status Started for HL411401+4.p
184411.38/24338.61	% SZS status GaveUp for HL411401+4.p
184411.38/24338.61	eprover: CPU time limit exceeded, terminating
184411.38/24338.61	% SZS status Ended for HL411401+4.p
184417.31/24339.21	% SZS status Started for HL411396+5.p
184417.31/24339.21	% SZS status GaveUp for HL411396+5.p
184417.31/24339.21	eprover: CPU time limit exceeded, terminating
184417.31/24339.21	% SZS status Ended for HL411396+5.p
184423.06/24339.92	% SZS status Started for HL411402+4.p
184423.06/24339.92	% SZS status GaveUp for HL411402+4.p
184423.06/24339.92	eprover: CPU time limit exceeded, terminating
184423.06/24339.92	% SZS status Ended for HL411402+4.p
184429.22/24340.69	% SZS status Started for HL411397+5.p
184429.22/24340.69	% SZS status GaveUp for HL411397+5.p
184429.22/24340.69	eprover: CPU time limit exceeded, terminating
184429.22/24340.69	% SZS status Ended for HL411397+5.p
184437.16/24341.68	% SZS status Started for HL411403+4.p
184437.16/24341.68	% SZS status GaveUp for HL411403+4.p
184437.16/24341.68	eprover: CPU time limit exceeded, terminating
184437.16/24341.68	% SZS status Ended for HL411403+4.p
184445.16/24342.96	% SZS status Started for HL411405+4.p
184445.16/24342.96	% SZS status GaveUp for HL411405+4.p
184445.16/24342.96	eprover: CPU time limit exceeded, terminating
184445.16/24342.96	% SZS status Ended for HL411405+4.p
184448.84/24343.14	% SZS status Started for HL411398+5.p
184448.84/24343.14	% SZS status GaveUp for HL411398+5.p
184448.84/24343.14	eprover: CPU time limit exceeded, terminating
184448.84/24343.14	% SZS status Ended for HL411398+5.p
184459.06/24344.49	% SZS status Started for HL411399+5.p
184459.06/24344.49	% SZS status GaveUp for HL411399+5.p
184459.06/24344.49	eprover: CPU time limit exceeded, terminating
184459.06/24344.49	% SZS status Ended for HL411399+5.p
184461.88/24344.78	% SZS status Started for HL411406+4.p
184461.88/24344.78	% SZS status GaveUp for HL411406+4.p
184461.88/24344.78	eprover: CPU time limit exceeded, terminating
184461.88/24344.78	% SZS status Ended for HL411406+4.p
184472.86/24346.22	% SZS status Started for HL411407+4.p
184472.86/24346.22	% SZS status GaveUp for HL411407+4.p
184472.86/24346.22	eprover: CPU time limit exceeded, terminating
184472.86/24346.22	% SZS status Ended for HL411407+4.p
184473.95/24346.32	% SZS status Started for HL411401+5.p
184473.95/24346.32	% SZS status GaveUp for HL411401+5.p
184473.95/24346.32	eprover: CPU time limit exceeded, terminating
184473.95/24346.32	% SZS status Ended for HL411401+5.p
184485.80/24347.80	% SZS status Started for HL411408+4.p
184485.80/24347.80	% SZS status GaveUp for HL411408+4.p
184485.80/24347.80	eprover: CPU time limit exceeded, terminating
184485.80/24347.80	% SZS status Ended for HL411408+4.p
184491.20/24348.51	% SZS status Started for HL411402+5.p
184491.20/24348.51	% SZS status GaveUp for HL411402+5.p
184491.20/24348.51	eprover: CPU time limit exceeded, terminating
184491.20/24348.51	% SZS status Ended for HL411402+5.p
184496.84/24349.36	% SZS status Started for HL411409+4.p
184496.84/24349.36	% SZS status GaveUp for HL411409+4.p
184496.84/24349.36	eprover: CPU time limit exceeded, terminating
184496.84/24349.36	% SZS status Ended for HL411409+4.p
184501.64/24349.86	% SZS status Started for HL411403+5.p
184501.64/24349.86	% SZS status GaveUp for HL411403+5.p
184501.64/24349.86	eprover: CPU time limit exceeded, terminating
184501.64/24349.86	% SZS status Ended for HL411403+5.p
184514.36/24351.45	% SZS status Started for HL411405+5.p
184514.36/24351.45	% SZS status GaveUp for HL411405+5.p
184514.36/24351.45	eprover: CPU time limit exceeded, terminating
184514.36/24351.45	% SZS status Ended for HL411405+5.p
184515.67/24351.61	% SZS status Started for HL411410+4.p
184515.67/24351.61	% SZS status GaveUp for HL411410+4.p
184515.67/24351.61	eprover: CPU time limit exceeded, terminating
184515.67/24351.61	% SZS status Ended for HL411410+4.p
184525.89/24352.90	% SZS status Started for HL411413+4.p
184525.89/24352.90	% SZS status GaveUp for HL411413+4.p
184525.89/24352.90	eprover: CPU time limit exceeded, terminating
184525.89/24352.90	% SZS status Ended for HL411413+4.p
184531.64/24353.66	% SZS status Started for HL411406+5.p
184531.64/24353.66	% SZS status GaveUp for HL411406+5.p
184531.64/24353.66	eprover: CPU time limit exceeded, terminating
184531.64/24353.66	% SZS status Ended for HL411406+5.p
184540.03/24354.67	% SZS status Started for HL411414+4.p
184540.03/24354.67	% SZS status GaveUp for HL411414+4.p
184540.03/24354.67	eprover: CPU time limit exceeded, terminating
184540.03/24354.67	% SZS status Ended for HL411414+4.p
184544.72/24355.38	% SZS status Started for HL411407+5.p
184544.72/24355.38	% SZS status GaveUp for HL411407+5.p
184544.72/24355.38	eprover: CPU time limit exceeded, terminating
184544.72/24355.38	% SZS status Ended for HL411407+5.p
184556.27/24356.73	% SZS status Started for HL411415+4.p
184556.27/24356.73	% SZS status GaveUp for HL411415+4.p
184556.27/24356.73	eprover: CPU time limit exceeded, terminating
184556.27/24356.73	% SZS status Ended for HL411415+4.p
184558.09/24357.02	% SZS status Started for HL411408+5.p
184558.09/24357.02	% SZS status GaveUp for HL411408+5.p
184558.09/24357.02	eprover: CPU time limit exceeded, terminating
184558.09/24357.02	% SZS status Ended for HL411408+5.p
184563.56/24357.75	% SZS status Started for HL411415+5.p
184563.56/24357.75	% SZS status GaveUp for HL411415+5.p
184563.56/24357.75	eprover: CPU time limit exceeded, terminating
184563.56/24357.75	% SZS status Ended for HL411415+5.p
184570.12/24358.44	% SZS status Started for HL411416+4.p
184570.12/24358.44	% SZS status GaveUp for HL411416+4.p
184570.12/24358.44	eprover: CPU time limit exceeded, terminating
184570.12/24358.44	% SZS status Ended for HL411416+4.p
184570.69/24358.52	% SZS status Started for HL411409+5.p
184570.69/24358.52	% SZS status GaveUp for HL411409+5.p
184570.69/24358.52	eprover: CPU time limit exceeded, terminating
184570.69/24358.52	% SZS status Ended for HL411409+5.p
184582.80/24360.08	% SZS status Started for HL411410+5.p
184582.80/24360.08	% SZS status GaveUp for HL411410+5.p
184582.80/24360.08	eprover: CPU time limit exceeded, terminating
184582.80/24360.08	% SZS status Ended for HL411410+5.p
184583.39/24360.10	% SZS status Started for HL411417+4.p
184583.39/24360.10	% SZS status GaveUp for HL411417+4.p
184583.39/24360.10	eprover: CPU time limit exceeded, terminating
184583.39/24360.10	% SZS status Ended for HL411417+4.p
184594.02/24361.48	% SZS status Started for HL411418+4.p
184594.02/24361.48	% SZS status GaveUp for HL411418+4.p
184594.02/24361.48	eprover: CPU time limit exceeded, terminating
184594.02/24361.48	% SZS status Ended for HL411418+4.p
184600.73/24362.32	% SZS status Started for HL411413+5.p
184600.73/24362.32	% SZS status GaveUp for HL411413+5.p
184600.73/24362.32	eprover: CPU time limit exceeded, terminating
184600.73/24362.32	% SZS status Ended for HL411413+5.p
184606.09/24363.11	% SZS status Started for HL411421+4.p
184606.09/24363.11	% SZS status GaveUp for HL411421+4.p
184606.09/24363.11	eprover: CPU time limit exceeded, terminating
184606.09/24363.11	% SZS status Ended for HL411421+4.p
184612.55/24363.85	% SZS status Started for HL411414+5.p
184612.55/24363.85	% SZS status GaveUp for HL411414+5.p
184612.55/24363.85	eprover: CPU time limit exceeded, terminating
184612.55/24363.85	% SZS status Ended for HL411414+5.p
184618.00/24364.51	% SZS status Started for HL411422+4.p
184618.00/24364.51	% SZS status GaveUp for HL411422+4.p
184618.00/24364.51	eprover: CPU time limit exceeded, terminating
184618.00/24364.51	% SZS status Ended for HL411422+4.p
184630.38/24366.14	% SZS status Started for HL411423+4.p
184630.38/24366.14	% SZS status GaveUp for HL411423+4.p
184630.38/24366.14	eprover: CPU time limit exceeded, terminating
184630.38/24366.14	% SZS status Ended for HL411423+4.p
184642.34/24367.54	% SZS status Started for HL411424+4.p
184642.34/24367.54	% SZS status GaveUp for HL411424+4.p
184642.34/24367.54	eprover: CPU time limit exceeded, terminating
184642.34/24367.54	% SZS status Ended for HL411424+4.p
184644.19/24367.82	% SZS status Started for HL411416+5.p
184644.19/24367.82	% SZS status GaveUp for HL411416+5.p
184644.19/24367.82	eprover: CPU time limit exceeded, terminating
184644.19/24367.82	% SZS status Ended for HL411416+5.p
184652.38/24368.81	% SZS status Started for HL411417+5.p
184652.38/24368.81	% SZS status GaveUp for HL411417+5.p
184652.38/24368.81	eprover: CPU time limit exceeded, terminating
184652.38/24368.81	% SZS status Ended for HL411417+5.p
184656.25/24369.34	% SZS status Started for HL411418+5.p
184656.25/24369.34	% SZS status GaveUp for HL411418+5.p
184656.25/24369.34	eprover: CPU time limit exceeded, terminating
184656.25/24369.34	% SZS status Ended for HL411418+5.p
184666.17/24370.62	% SZS status Started for HL411426+4.p
184666.17/24370.62	% SZS status GaveUp for HL411426+4.p
184666.17/24370.62	eprover: CPU time limit exceeded, terminating
184666.17/24370.62	% SZS status Ended for HL411426+4.p
184666.81/24370.77	% SZS status Started for HL411421+5.p
184666.81/24370.77	% SZS status GaveUp for HL411421+5.p
184666.81/24370.77	eprover: CPU time limit exceeded, terminating
184666.81/24370.77	% SZS status Ended for HL411421+5.p
184675.34/24371.91	% SZS status Started for HL411427+4.p
184675.34/24371.91	% SZS status GaveUp for HL411427+4.p
184675.34/24371.91	eprover: CPU time limit exceeded, terminating
184675.34/24371.91	% SZS status Ended for HL411427+4.p
184689.00/24373.51	% SZS status Started for HL411422+5.p
184689.00/24373.51	% SZS status GaveUp for HL411422+5.p
184689.00/24373.51	eprover: CPU time limit exceeded, terminating
184689.00/24373.51	% SZS status Ended for HL411422+5.p
184690.09/24373.65	% SZS status Started for HL411428+4.p
184690.09/24373.65	% SZS status GaveUp for HL411428+4.p
184690.09/24373.65	eprover: CPU time limit exceeded, terminating
184690.09/24373.65	% SZS status Ended for HL411428+4.p
184697.97/24374.57	% SZS status Started for HL411423+5.p
184697.97/24374.57	% SZS status GaveUp for HL411423+5.p
184697.97/24374.57	eprover: CPU time limit exceeded, terminating
184697.97/24374.57	% SZS status Ended for HL411423+5.p
184700.89/24374.94	% SZS status Started for HL411429+4.p
184700.89/24374.94	% SZS status GaveUp for HL411429+4.p
184700.89/24374.94	eprover: CPU time limit exceeded, terminating
184700.89/24374.94	% SZS status Ended for HL411429+4.p
184714.34/24376.68	% SZS status Started for HL411430+4.p
184714.34/24376.68	% SZS status GaveUp for HL411430+4.p
184714.34/24376.68	eprover: CPU time limit exceeded, terminating
184714.34/24376.68	% SZS status Ended for HL411430+4.p
184715.42/24376.80	% SZS status Started for HL411424+5.p
184715.42/24376.80	% SZS status GaveUp for HL411424+5.p
184715.42/24376.80	eprover: CPU time limit exceeded, terminating
184715.42/24376.80	% SZS status Ended for HL411424+5.p
184725.20/24378.03	% SZS status Started for HL411431+4.p
184725.20/24378.03	% SZS status GaveUp for HL411431+4.p
184725.20/24378.03	eprover: CPU time limit exceeded, terminating
184725.20/24378.03	% SZS status Ended for HL411431+4.p
184729.22/24378.61	% SZS status Started for HL411426+5.p
184729.22/24378.61	% SZS status GaveUp for HL411426+5.p
184729.22/24378.61	eprover: CPU time limit exceeded, terminating
184729.22/24378.61	% SZS status Ended for HL411426+5.p
184739.41/24379.90	% SZS status Started for HL411432+4.p
184739.41/24379.90	% SZS status GaveUp for HL411432+4.p
184739.41/24379.90	eprover: CPU time limit exceeded, terminating
184739.41/24379.90	% SZS status Ended for HL411432+4.p
184742.52/24380.26	% SZS status Started for HL411427+5.p
184742.52/24380.26	% SZS status GaveUp for HL411427+5.p
184742.52/24380.26	eprover: CPU time limit exceeded, terminating
184742.52/24380.26	% SZS status Ended for HL411427+5.p
184752.94/24381.54	% SZS status Started for HL411428+5.p
184752.94/24381.54	% SZS status GaveUp for HL411428+5.p
184752.94/24381.54	eprover: CPU time limit exceeded, terminating
184752.94/24381.54	% SZS status Ended for HL411428+5.p
184753.61/24381.68	% SZS status Started for HL411433+4.p
184753.61/24381.68	% SZS status GaveUp for HL411433+4.p
184753.61/24381.68	eprover: CPU time limit exceeded, terminating
184753.61/24381.68	% SZS status Ended for HL411433+4.p
184767.12/24383.29	% SZS status Started for HL411434+4.p
184767.12/24383.29	% SZS status GaveUp for HL411434+4.p
184767.12/24383.29	eprover: CPU time limit exceeded, terminating
184767.12/24383.29	% SZS status Ended for HL411434+4.p
184775.92/24384.42	% SZS status Started for HL411429+5.p
184775.92/24384.42	% SZS status GaveUp for HL411429+5.p
184775.92/24384.42	eprover: CPU time limit exceeded, terminating
184775.92/24384.42	% SZS status Ended for HL411429+5.p
184778.11/24384.70	% SZS status Started for HL411437+4.p
184778.11/24384.70	% SZS status GaveUp for HL411437+4.p
184778.11/24384.70	eprover: CPU time limit exceeded, terminating
184778.11/24384.70	% SZS status Ended for HL411437+4.p
184782.86/24385.28	% SZS status Started for HL411430+5.p
184782.86/24385.28	% SZS status GaveUp for HL411430+5.p
184782.86/24385.28	eprover: CPU time limit exceeded, terminating
184782.86/24385.28	% SZS status Ended for HL411430+5.p
184800.08/24387.46	% SZS status Started for HL411438+4.p
184800.08/24387.46	% SZS status GaveUp for HL411438+4.p
184800.08/24387.46	eprover: CPU time limit exceeded, terminating
184800.08/24387.46	% SZS status Ended for HL411438+4.p
184800.73/24387.55	% SZS status Started for HL411431+5.p
184800.73/24387.55	% SZS status GaveUp for HL411431+5.p
184800.73/24387.55	eprover: CPU time limit exceeded, terminating
184800.73/24387.55	% SZS status Ended for HL411431+5.p
184806.81/24388.35	% SZS status Started for HL411439+4.p
184806.81/24388.35	% SZS status GaveUp for HL411439+4.p
184806.81/24388.35	eprover: CPU time limit exceeded, terminating
184806.81/24388.35	% SZS status Ended for HL411439+4.p
184810.55/24388.80	% SZS status Started for HL411432+5.p
184810.55/24388.80	% SZS status GaveUp for HL411432+5.p
184810.55/24388.80	eprover: CPU time limit exceeded, terminating
184810.55/24388.80	% SZS status Ended for HL411432+5.p
184824.33/24390.52	% SZS status Started for HL411433+5.p
184824.33/24390.52	% SZS status GaveUp for HL411433+5.p
184824.33/24390.52	eprover: CPU time limit exceeded, terminating
184824.33/24390.52	% SZS status Ended for HL411433+5.p
184824.75/24390.58	% SZS status Started for HL411441+4.p
184824.75/24390.58	% SZS status GaveUp for HL411441+4.p
184824.75/24390.58	eprover: CPU time limit exceeded, terminating
184824.75/24390.58	% SZS status Ended for HL411441+4.p
184833.89/24391.84	% SZS status Started for HL411442+4.p
184833.89/24391.84	% SZS status GaveUp for HL411442+4.p
184833.89/24391.84	eprover: CPU time limit exceeded, terminating
184833.89/24391.84	% SZS status Ended for HL411442+4.p
184840.05/24392.52	% SZS status Started for HL411434+5.p
184840.05/24392.52	% SZS status GaveUp for HL411434+5.p
184840.05/24392.52	eprover: CPU time limit exceeded, terminating
184840.05/24392.52	% SZS status Ended for HL411434+5.p
184848.47/24393.58	% SZS status Started for HL411442+5.p
184848.47/24393.58	% SZS status GaveUp for HL411442+5.p
184848.47/24393.58	eprover: CPU time limit exceeded, terminating
184848.47/24393.58	% SZS status Ended for HL411442+5.p
184849.38/24393.64	% SZS status Started for HL411443+4.p
184849.38/24393.64	% SZS status GaveUp for HL411443+4.p
184849.38/24393.64	eprover: CPU time limit exceeded, terminating
184849.38/24393.64	% SZS status Ended for HL411443+4.p
184851.98/24394.01	% SZS status Started for HL411437+5.p
184851.98/24394.01	% SZS status GaveUp for HL411437+5.p
184851.98/24394.01	eprover: CPU time limit exceeded, terminating
184851.98/24394.01	% SZS status Ended for HL411437+5.p
184861.94/24395.36	% SZS status Started for HL411438+5.p
184861.94/24395.36	% SZS status GaveUp for HL411438+5.p
184861.94/24395.36	eprover: CPU time limit exceeded, terminating
184861.94/24395.36	% SZS status Ended for HL411438+5.p
184874.12/24395.65	% SZS status Started for HL411444+4.p
184874.12/24395.65	% SZS status GaveUp for HL411444+4.p
184874.12/24395.65	eprover: CPU time limit exceeded, terminating
184874.12/24395.65	% SZS status Ended for HL411444+4.p
184882.62/24396.68	% SZS status Started for HL411445+4.p
184882.62/24396.68	% SZS status GaveUp for HL411445+4.p
184882.62/24396.68	eprover: CPU time limit exceeded, terminating
184882.62/24396.68	% SZS status Ended for HL411445+4.p
184893.53/24398.08	% SZS status Started for HL411439+5.p
184893.53/24398.08	% SZS status GaveUp for HL411439+5.p
184893.53/24398.08	eprover: CPU time limit exceeded, terminating
184893.53/24398.08	% SZS status Ended for HL411439+5.p
184895.91/24398.49	% SZS status Started for HL411446+4.p
184895.91/24398.49	% SZS status GaveUp for HL411446+4.p
184895.91/24398.49	eprover: CPU time limit exceeded, terminating
184895.91/24398.49	% SZS status Ended for HL411446+4.p
184901.95/24399.15	% SZS status Started for HL411441+5.p
184901.95/24399.15	% SZS status GaveUp for HL411441+5.p
184901.95/24399.15	eprover: CPU time limit exceeded, terminating
184901.95/24399.15	% SZS status Ended for HL411441+5.p
184906.52/24399.75	% SZS status Started for HL411447+4.p
184906.52/24399.75	% SZS status GaveUp for HL411447+4.p
184906.52/24399.75	eprover: CPU time limit exceeded, terminating
184906.52/24399.75	% SZS status Ended for HL411447+4.p
184921.50/24401.55	% SZS status Started for HL411448+4.p
184921.50/24401.55	% SZS status GaveUp for HL411448+4.p
184921.50/24401.55	eprover: CPU time limit exceeded, terminating
184921.50/24401.55	% SZS status Ended for HL411448+4.p
184928.73/24402.52	% SZS status Started for HL411443+5.p
184928.73/24402.52	% SZS status GaveUp for HL411443+5.p
184928.73/24402.52	eprover: CPU time limit exceeded, terminating
184928.73/24402.52	% SZS status Ended for HL411443+5.p
184931.30/24402.87	% SZS status Started for HL411449+4.p
184931.30/24402.87	% SZS status GaveUp for HL411449+4.p
184931.30/24402.87	eprover: CPU time limit exceeded, terminating
184931.30/24402.87	% SZS status Ended for HL411449+4.p
184943.88/24404.44	% SZS status Started for HL411444+5.p
184943.88/24404.44	% SZS status GaveUp for HL411444+5.p
184943.88/24404.44	eprover: CPU time limit exceeded, terminating
184943.88/24404.44	% SZS status Ended for HL411444+5.p
184946.00/24404.77	% SZS status Started for HL411445+5.p
184946.00/24404.77	% SZS status GaveUp for HL411445+5.p
184946.00/24404.77	eprover: CPU time limit exceeded, terminating
184946.00/24404.77	% SZS status Ended for HL411445+5.p
184953.25/24405.58	% SZS status Started for HL411452+4.p
184953.25/24405.58	% SZS status GaveUp for HL411452+4.p
184953.25/24405.58	eprover: CPU time limit exceeded, terminating
184953.25/24405.58	% SZS status Ended for HL411452+4.p
184958.91/24406.28	% SZS status Started for HL411446+5.p
184958.91/24406.28	% SZS status GaveUp for HL411446+5.p
184958.91/24406.28	eprover: CPU time limit exceeded, terminating
184958.91/24406.28	% SZS status Ended for HL411446+5.p
184968.53/24407.49	% SZS status Started for HL411453+4.p
184968.53/24407.49	% SZS status GaveUp for HL411453+4.p
184968.53/24407.49	eprover: CPU time limit exceeded, terminating
184968.53/24407.49	% SZS status Ended for HL411453+4.p
184977.28/24408.62	% SZS status Started for HL411454+4.p
184977.28/24408.62	% SZS status GaveUp for HL411454+4.p
184977.28/24408.62	eprover: CPU time limit exceeded, terminating
184977.28/24408.62	% SZS status Ended for HL411454+4.p
184978.73/24408.79	% SZS status Started for HL411447+5.p
184978.73/24408.79	% SZS status GaveUp for HL411447+5.p
184978.73/24408.79	eprover: CPU time limit exceeded, terminating
184978.73/24408.79	% SZS status Ended for HL411447+5.p
184986.30/24409.83	% SZS status Started for HL411448+5.p
184986.30/24409.83	% SZS status GaveUp for HL411448+5.p
184986.30/24409.83	eprover: CPU time limit exceeded, terminating
184986.30/24409.83	% SZS status Ended for HL411448+5.p
184992.44/24410.52	% SZS status Started for HL411458+4.p
184992.44/24410.52	% SZS status GaveUp for HL411458+4.p
184992.44/24410.52	eprover: CPU time limit exceeded, terminating
184992.44/24410.52	% SZS status Ended for HL411458+4.p
185002.48/24411.84	% SZS status Started for HL411459+4.p
185002.48/24411.84	% SZS status GaveUp for HL411459+4.p
185002.48/24411.84	eprover: CPU time limit exceeded, terminating
185002.48/24411.84	% SZS status Ended for HL411459+4.p
185008.88/24412.69	% SZS status Started for HL411449+5.p
185008.88/24412.69	% SZS status GaveUp for HL411449+5.p
185008.88/24412.69	eprover: CPU time limit exceeded, terminating
185008.88/24412.69	% SZS status Ended for HL411449+5.p
185016.42/24413.56	% SZS status Started for HL411461+4.p
185016.42/24413.56	% SZS status GaveUp for HL411461+4.p
185016.42/24413.56	eprover: CPU time limit exceeded, terminating
185016.42/24413.56	% SZS status Ended for HL411461+4.p
185016.86/24413.61	% SZS status Started for HL411452+5.p
185016.86/24413.61	% SZS status GaveUp for HL411452+5.p
185016.86/24413.61	eprover: CPU time limit exceeded, terminating
185016.86/24413.61	% SZS status Ended for HL411452+5.p
185031.41/24415.53	% SZS status Started for HL411453+5.p
185031.41/24415.53	% SZS status GaveUp for HL411453+5.p
185031.41/24415.53	eprover: CPU time limit exceeded, terminating
185031.41/24415.53	% SZS status Ended for HL411453+5.p
185033.75/24415.73	% SZS status Started for HL411462+4.p
185033.75/24415.73	% SZS status GaveUp for HL411462+4.p
185033.75/24415.73	eprover: CPU time limit exceeded, terminating
185033.75/24415.73	% SZS status Ended for HL411462+4.p
185039.45/24416.63	% SZS status Started for HL411463+4.p
185039.45/24416.63	% SZS status GaveUp for HL411463+4.p
185039.45/24416.63	eprover: CPU time limit exceeded, terminating
185039.45/24416.63	% SZS status Ended for HL411463+4.p
185045.98/24417.30	% SZS status Started for HL411454+5.p
185045.98/24417.30	% SZS status GaveUp for HL411454+5.p
185045.98/24417.30	eprover: CPU time limit exceeded, terminating
185045.98/24417.30	% SZS status Ended for HL411454+5.p
185057.66/24418.80	% SZS status Started for HL411464+4.p
185057.66/24418.80	% SZS status GaveUp for HL411464+4.p
185057.66/24418.80	eprover: CPU time limit exceeded, terminating
185057.66/24418.80	% SZS status Ended for HL411464+4.p
185061.64/24419.33	% SZS status Started for HL411458+5.p
185061.64/24419.33	% SZS status GaveUp for HL411458+5.p
185061.64/24419.33	eprover: CPU time limit exceeded, terminating
185061.64/24419.33	% SZS status Ended for HL411458+5.p
185070.38/24420.43	% SZS status Started for HL411467+4.p
185070.38/24420.43	% SZS status GaveUp for HL411467+4.p
185070.38/24420.43	eprover: CPU time limit exceeded, terminating
185070.38/24420.43	% SZS status Ended for HL411467+4.p
185075.77/24421.06	% SZS status Started for HL411459+5.p
185075.77/24421.06	% SZS status GaveUp for HL411459+5.p
185075.77/24421.06	eprover: CPU time limit exceeded, terminating
185075.77/24421.06	% SZS status Ended for HL411459+5.p
185086.48/24422.38	% SZS status Started for HL411468+4.p
185086.48/24422.38	% SZS status GaveUp for HL411468+4.p
185086.48/24422.38	eprover: CPU time limit exceeded, terminating
185086.48/24422.38	% SZS status Ended for HL411468+4.p
185087.53/24422.53	% SZS status Started for HL411461+5.p
185087.53/24422.53	% SZS status GaveUp for HL411461+5.p
185087.53/24422.53	eprover: CPU time limit exceeded, terminating
185087.53/24422.53	% SZS status Ended for HL411461+5.p
185100.61/24424.17	% SZS status Started for HL411469+4.p
185100.61/24424.17	% SZS status GaveUp for HL411469+4.p
185100.61/24424.17	eprover: CPU time limit exceeded, terminating
185100.61/24424.17	% SZS status Ended for HL411469+4.p
185100.61/24424.22	% SZS status Started for HL411462+5.p
185100.61/24424.22	% SZS status GaveUp for HL411462+5.p
185100.61/24424.22	eprover: CPU time limit exceeded, terminating
185100.61/24424.22	% SZS status Ended for HL411462+5.p
185111.64/24425.57	% SZS status Started for HL411470+4.p
185111.64/24425.57	% SZS status GaveUp for HL411470+4.p
185111.64/24425.57	eprover: CPU time limit exceeded, terminating
185111.64/24425.57	% SZS status Ended for HL411470+4.p
185117.41/24426.30	% SZS status Started for HL411463+5.p
185117.41/24426.30	% SZS status GaveUp for HL411463+5.p
185117.41/24426.30	eprover: CPU time limit exceeded, terminating
185117.41/24426.30	% SZS status Ended for HL411463+5.p
185125.41/24427.32	% SZS status Started for HL411471+4.p
185125.41/24427.32	% SZS status GaveUp for HL411471+4.p
185125.41/24427.32	eprover: CPU time limit exceeded, terminating
185125.41/24427.32	% SZS status Ended for HL411471+4.p
185125.62/24427.34	% SZS status Started for HL411464+5.p
185125.62/24427.34	% SZS status GaveUp for HL411464+5.p
185125.62/24427.34	eprover: CPU time limit exceeded, terminating
185125.62/24427.34	% SZS status Ended for HL411464+5.p
185141.09/24429.35	% SZS status Started for HL411472+4.p
185141.09/24429.35	% SZS status GaveUp for HL411472+4.p
185141.09/24429.35	eprover: CPU time limit exceeded, terminating
185141.09/24429.35	% SZS status Ended for HL411472+4.p
185142.75/24429.50	% SZS status Started for HL411467+5.p
185142.75/24429.50	% SZS status GaveUp for HL411467+5.p
185142.75/24429.50	eprover: CPU time limit exceeded, terminating
185142.75/24429.50	% SZS status Ended for HL411467+5.p
185149.53/24430.37	% SZS status Started for HL411473+4.p
185149.53/24430.37	% SZS status GaveUp for HL411473+4.p
185149.53/24430.37	eprover: CPU time limit exceeded, terminating
185149.53/24430.37	% SZS status Ended for HL411473+4.p
185157.61/24431.38	% SZS status Started for HL411468+5.p
185157.61/24431.38	% SZS status GaveUp for HL411468+5.p
185157.61/24431.38	eprover: CPU time limit exceeded, terminating
185157.61/24431.38	% SZS status Ended for HL411468+5.p
185166.78/24432.53	% SZS status Started for HL411474+4.p
185166.78/24432.53	% SZS status GaveUp for HL411474+4.p
185166.78/24432.53	eprover: CPU time limit exceeded, terminating
185166.78/24432.53	% SZS status Ended for HL411474+4.p
185171.91/24433.26	% SZS status Started for HL411469+5.p
185171.91/24433.26	% SZS status GaveUp for HL411469+5.p
185171.91/24433.26	eprover: CPU time limit exceeded, terminating
185171.91/24433.26	% SZS status Ended for HL411469+5.p
185180.67/24434.41	% SZS status Started for HL411475+4.p
185180.67/24434.41	% SZS status GaveUp for HL411475+4.p
185180.67/24434.41	eprover: CPU time limit exceeded, terminating
185180.67/24434.41	% SZS status Ended for HL411475+4.p
185185.19/24434.89	% SZS status Started for HL411470+5.p
185185.19/24434.89	% SZS status GaveUp for HL411470+5.p
185185.19/24434.89	eprover: CPU time limit exceeded, terminating
185185.19/24434.89	% SZS status Ended for HL411470+5.p
185197.06/24436.36	% SZS status Started for HL411476+4.p
185197.06/24436.36	% SZS status GaveUp for HL411476+4.p
185197.06/24436.36	eprover: CPU time limit exceeded, terminating
185197.06/24436.36	% SZS status Ended for HL411476+4.p
185199.25/24436.66	% SZS status Started for HL411471+5.p
185199.25/24436.66	% SZS status GaveUp for HL411471+5.p
185199.25/24436.66	eprover: CPU time limit exceeded, terminating
185199.25/24436.66	% SZS status Ended for HL411471+5.p
185210.05/24437.96	% SZS status Started for HL411478+4.p
185210.05/24437.96	% SZS status GaveUp for HL411478+4.p
185210.05/24437.96	eprover: CPU time limit exceeded, terminating
185210.05/24437.96	% SZS status Ended for HL411478+4.p
185210.47/24438.05	% SZS status Started for HL411472+5.p
185210.47/24438.05	% SZS status GaveUp for HL411472+5.p
185210.47/24438.05	eprover: CPU time limit exceeded, terminating
185210.47/24438.05	% SZS status Ended for HL411472+5.p
185223.45/24439.69	% SZS status Started for HL411479+4.p
185223.45/24439.69	% SZS status GaveUp for HL411479+4.p
185223.45/24439.69	eprover: CPU time limit exceeded, terminating
185223.45/24439.69	% SZS status Ended for HL411479+4.p
185226.73/24440.18	% SZS status Started for HL411473+5.p
185226.73/24440.18	% SZS status GaveUp for HL411473+5.p
185226.73/24440.18	eprover: CPU time limit exceeded, terminating
185226.73/24440.18	% SZS status Ended for HL411473+5.p
185234.62/24441.07	% SZS status Started for HL411474+5.p
185234.62/24441.07	% SZS status GaveUp for HL411474+5.p
185234.62/24441.07	eprover: CPU time limit exceeded, terminating
185234.62/24441.07	% SZS status Ended for HL411474+5.p
185234.97/24441.10	% SZS status Started for HL411480+4.p
185234.97/24441.10	% SZS status GaveUp for HL411480+4.p
185234.97/24441.10	eprover: CPU time limit exceeded, terminating
185234.97/24441.10	% SZS status Ended for HL411480+4.p
185252.02/24443.29	% SZS status Started for HL411475+5.p
185252.02/24443.29	% SZS status GaveUp for HL411475+5.p
185252.02/24443.29	eprover: CPU time limit exceeded, terminating
185252.02/24443.29	% SZS status Ended for HL411475+5.p
185252.02/24443.30	% SZS status Started for HL411481+4.p
185252.02/24443.30	% SZS status GaveUp for HL411481+4.p
185252.02/24443.30	eprover: CPU time limit exceeded, terminating
185252.02/24443.30	% SZS status Ended for HL411481+4.p
185258.12/24444.14	% SZS status Started for HL411483+4.p
185258.12/24444.14	% SZS status GaveUp for HL411483+4.p
185258.12/24444.14	eprover: CPU time limit exceeded, terminating
185258.12/24444.14	% SZS status Ended for HL411483+4.p
185266.73/24445.10	% SZS status Started for HL411476+5.p
185266.73/24445.10	% SZS status GaveUp for HL411476+5.p
185266.73/24445.10	eprover: CPU time limit exceeded, terminating
185266.73/24445.10	% SZS status Ended for HL411476+5.p
185276.95/24446.40	% SZS status Started for HL411485+4.p
185276.95/24446.40	% SZS status GaveUp for HL411485+4.p
185276.95/24446.40	eprover: CPU time limit exceeded, terminating
185276.95/24446.40	% SZS status Ended for HL411485+4.p
185283.09/24447.18	% SZS status Started for HL411478+5.p
185283.09/24447.18	% SZS status GaveUp for HL411478+5.p
185283.09/24447.18	eprover: CPU time limit exceeded, terminating
185283.09/24447.18	% SZS status Ended for HL411478+5.p
185289.81/24448.13	% SZS status Started for HL411486+4.p
185289.81/24448.13	% SZS status GaveUp for HL411486+4.p
185289.81/24448.13	eprover: CPU time limit exceeded, terminating
185289.81/24448.13	% SZS status Ended for HL411486+4.p
185295.02/24448.67	% SZS status Started for HL411479+5.p
185295.02/24448.67	% SZS status GaveUp for HL411479+5.p
185295.02/24448.67	eprover: CPU time limit exceeded, terminating
185295.02/24448.67	% SZS status Ended for HL411479+5.p
185301.52/24449.48	% SZS status Started for HL411486+5.p
185301.52/24449.48	% SZS status GaveUp for HL411486+5.p
185301.52/24449.48	eprover: CPU time limit exceeded, terminating
185301.52/24449.48	% SZS status Ended for HL411486+5.p
185306.52/24450.23	% SZS status Started for HL411487+4.p
185306.52/24450.23	% SZS status GaveUp for HL411487+4.p
185306.52/24450.23	eprover: CPU time limit exceeded, terminating
185306.52/24450.23	% SZS status Ended for HL411487+4.p
185310.45/24450.62	% SZS status Started for HL411480+5.p
185310.45/24450.62	% SZS status GaveUp for HL411480+5.p
185310.45/24450.62	eprover: CPU time limit exceeded, terminating
185310.45/24450.62	% SZS status Ended for HL411480+5.p
185318.91/24451.71	% SZS status Started for HL411488+4.p
185318.91/24451.71	% SZS status GaveUp for HL411488+4.p
185318.91/24451.71	eprover: CPU time limit exceeded, terminating
185318.91/24451.71	% SZS status Ended for HL411488+4.p
185319.53/24451.75	% SZS status Started for HL411481+5.p
185319.53/24451.75	% SZS status GaveUp for HL411481+5.p
185319.53/24451.75	eprover: CPU time limit exceeded, terminating
185319.53/24451.75	% SZS status Ended for HL411481+5.p
185331.41/24453.27	% SZS status Started for HL411489+4.p
185331.41/24453.27	% SZS status GaveUp for HL411489+4.p
185331.41/24453.27	eprover: CPU time limit exceeded, terminating
185331.41/24453.27	% SZS status Ended for HL411489+4.p
185337.00/24453.96	% SZS status Started for HL411483+5.p
185337.00/24453.96	% SZS status GaveUp for HL411483+5.p
185337.00/24453.96	eprover: CPU time limit exceeded, terminating
185337.00/24453.96	% SZS status Ended for HL411483+5.p
185342.83/24454.73	% SZS status Started for HL411492+4.p
185342.83/24454.73	% SZS status GaveUp for HL411492+4.p
185342.83/24454.73	eprover: CPU time limit exceeded, terminating
185342.83/24454.73	% SZS status Ended for HL411492+4.p
185343.70/24454.82	% SZS status Started for HL411485+5.p
185343.70/24454.82	% SZS status GaveUp for HL411485+5.p
185343.70/24454.82	eprover: CPU time limit exceeded, terminating
185343.70/24454.82	% SZS status Ended for HL411485+5.p
185355.67/24456.30	% SZS status Started for HL411493+4.p
185355.67/24456.30	% SZS status GaveUp for HL411493+4.p
185355.67/24456.30	eprover: CPU time limit exceeded, terminating
185355.67/24456.30	% SZS status Ended for HL411493+4.p
185366.61/24457.77	% SZS status Started for HL411494+4.p
185366.61/24457.77	% SZS status GaveUp for HL411494+4.p
185366.61/24457.77	eprover: CPU time limit exceeded, terminating
185366.61/24457.77	% SZS status Ended for HL411494+4.p
185375.16/24458.91	% SZS status Started for HL411487+5.p
185375.16/24458.91	% SZS status GaveUp for HL411487+5.p
185375.16/24458.91	eprover: CPU time limit exceeded, terminating
185375.16/24458.91	% SZS status Ended for HL411487+5.p
185379.80/24459.37	% SZS status Started for HL411495+4.p
185379.80/24459.37	% SZS status GaveUp for HL411495+4.p
185379.80/24459.37	eprover: CPU time limit exceeded, terminating
185379.80/24459.37	% SZS status Ended for HL411495+4.p
185385.62/24460.12	% SZS status Started for HL411488+5.p
185385.62/24460.12	% SZS status GaveUp for HL411488+5.p
185385.62/24460.12	eprover: CPU time limit exceeded, terminating
185385.62/24460.12	% SZS status Ended for HL411488+5.p
185396.25/24461.40	% SZS status Started for HL411489+5.p
185396.25/24461.40	% SZS status GaveUp for HL411489+5.p
185396.25/24461.40	eprover: CPU time limit exceeded, terminating
185396.25/24461.40	% SZS status Ended for HL411489+5.p
185400.66/24461.94	% SZS status Started for HL411496+4.p
185400.66/24461.94	% SZS status GaveUp for HL411496+4.p
185400.66/24461.94	eprover: CPU time limit exceeded, terminating
185400.66/24461.94	% SZS status Ended for HL411496+4.p
185405.31/24462.53	% SZS status Started for HL411492+5.p
185405.31/24462.53	% SZS status GaveUp for HL411492+5.p
185405.31/24462.53	eprover: CPU time limit exceeded, terminating
185405.31/24462.53	% SZS status Ended for HL411492+5.p
185410.03/24463.15	% SZS status Started for HL411497+4.p
185410.03/24463.15	% SZS status GaveUp for HL411497+4.p
185410.03/24463.15	eprover: CPU time limit exceeded, terminating
185410.03/24463.15	% SZS status Ended for HL411497+4.p
185422.33/24464.72	% SZS status Started for HL411493+5.p
185422.33/24464.72	% SZS status GaveUp for HL411493+5.p
185422.33/24464.72	eprover: CPU time limit exceeded, terminating
185422.33/24464.72	% SZS status Ended for HL411493+5.p
185424.53/24465.00	% SZS status Started for HL411498+4.p
185424.53/24465.00	% SZS status GaveUp for HL411498+4.p
185424.53/24465.00	eprover: CPU time limit exceeded, terminating
185424.53/24465.00	% SZS status Ended for HL411498+4.p
185429.11/24465.55	% SZS status Started for HL411494+5.p
185429.11/24465.55	% SZS status GaveUp for HL411494+5.p
185429.11/24465.55	eprover: CPU time limit exceeded, terminating
185429.11/24465.55	% SZS status Ended for HL411494+5.p
185433.94/24466.18	% SZS status Started for HL411499+4.p
185433.94/24466.18	% SZS status GaveUp for HL411499+4.p
185433.94/24466.18	eprover: CPU time limit exceeded, terminating
185433.94/24466.18	% SZS status Ended for HL411499+4.p
185446.80/24467.76	% SZS status Started for HL411499+5.p
185446.80/24467.76	% SZS status GaveUp for HL411499+5.p
185446.80/24467.76	eprover: CPU time limit exceeded, terminating
185446.80/24467.76	% SZS status Ended for HL411499+5.p
185448.92/24468.02	% SZS status Started for HL411502+4.p
185448.92/24468.02	% SZS status GaveUp for HL411502+4.p
185448.92/24468.02	eprover: CPU time limit exceeded, terminating
185448.92/24468.02	% SZS status Ended for HL411502+4.p
185450.88/24468.51	% SZS status Started for HL411495+5.p
185450.88/24468.51	% SZS status GaveUp for HL411495+5.p
185450.88/24468.51	eprover: CPU time limit exceeded, terminating
185450.88/24468.51	% SZS status Ended for HL411495+5.p
185458.41/24469.22	% SZS status Started for HL411503+4.p
185458.41/24469.22	% SZS status GaveUp for HL411503+4.p
185458.41/24469.22	eprover: CPU time limit exceeded, terminating
185458.41/24469.22	% SZS status Ended for HL411503+4.p
185466.66/24470.25	% SZS status Started for HL411496+5.p
185466.66/24470.25	% SZS status GaveUp for HL411496+5.p
185466.66/24470.25	eprover: CPU time limit exceeded, terminating
185466.66/24470.25	% SZS status Ended for HL411496+5.p
185472.91/24471.06	% SZS status Started for HL411505+4.p
185472.91/24471.06	% SZS status GaveUp for HL411505+4.p
185472.91/24471.06	eprover: CPU time limit exceeded, terminating
185472.91/24471.06	% SZS status Ended for HL411505+4.p
185481.72/24472.18	% SZS status Started for HL411497+5.p
185481.72/24472.18	% SZS status GaveUp for HL411497+5.p
185481.72/24472.18	eprover: CPU time limit exceeded, terminating
185481.72/24472.18	% SZS status Ended for HL411497+5.p
185482.25/24472.29	% SZS status Started for HL411506+4.p
185482.25/24472.29	% SZS status GaveUp for HL411506+4.p
185482.25/24472.29	eprover: CPU time limit exceeded, terminating
185482.25/24472.29	% SZS status Ended for HL411506+4.p
185490.20/24473.22	% SZS status Started for HL411498+5.p
185490.20/24473.22	% SZS status GaveUp for HL411498+5.p
185490.20/24473.22	eprover: CPU time limit exceeded, terminating
185490.20/24473.22	% SZS status Ended for HL411498+5.p
185497.16/24474.09	% SZS status Started for HL411507+4.p
185497.16/24474.09	% SZS status GaveUp for HL411507+4.p
185497.16/24474.09	eprover: CPU time limit exceeded, terminating
185497.16/24474.09	% SZS status Ended for HL411507+4.p
185506.64/24475.33	% SZS status Started for HL411508+4.p
185506.64/24475.33	% SZS status GaveUp for HL411508+4.p
185506.64/24475.33	eprover: CPU time limit exceeded, terminating
185506.64/24475.33	% SZS status Ended for HL411508+4.p
185513.06/24476.26	% SZS status Started for HL411502+5.p
185513.06/24476.26	% SZS status GaveUp for HL411502+5.p
185513.06/24476.26	eprover: CPU time limit exceeded, terminating
185513.06/24476.26	% SZS status Ended for HL411502+5.p
185520.59/24477.14	% SZS status Started for HL411509+4.p
185520.59/24477.14	% SZS status GaveUp for HL411509+4.p
185520.59/24477.14	eprover: CPU time limit exceeded, terminating
185520.59/24477.14	% SZS status Ended for HL411509+4.p
185534.23/24478.76	% SZS status Started for HL411503+5.p
185534.23/24478.76	% SZS status GaveUp for HL411503+5.p
185534.23/24478.76	eprover: CPU time limit exceeded, terminating
185534.23/24478.76	% SZS status Ended for HL411503+5.p
185537.41/24479.16	% SZS status Started for HL411505+5.p
185537.41/24479.16	% SZS status GaveUp for HL411505+5.p
185537.41/24479.16	eprover: CPU time limit exceeded, terminating
185537.41/24479.16	% SZS status Ended for HL411505+5.p
185538.14/24479.29	% SZS status Started for HL411510+4.p
185538.14/24479.29	% SZS status GaveUp for HL411510+4.p
185538.14/24479.29	eprover: CPU time limit exceeded, terminating
185538.14/24479.29	% SZS status Ended for HL411510+4.p
185551.02/24480.92	% SZS status Started for HL411506+5.p
185551.02/24480.92	% SZS status GaveUp for HL411506+5.p
185551.02/24480.92	eprover: CPU time limit exceeded, terminating
185551.02/24480.92	% SZS status Ended for HL411506+5.p
185558.14/24481.80	% SZS status Started for HL411511+4.p
185558.14/24481.80	% SZS status GaveUp for HL411511+4.p
185558.14/24481.80	eprover: CPU time limit exceeded, terminating
185558.14/24481.80	% SZS status Ended for HL411511+4.p
185562.52/24482.32	% SZS status Started for HL411512+4.p
185562.52/24482.32	% SZS status GaveUp for HL411512+4.p
185562.52/24482.32	eprover: CPU time limit exceeded, terminating
185562.52/24482.32	% SZS status Ended for HL411512+4.p
185567.59/24483.02	% SZS status Started for HL411507+5.p
185567.59/24483.02	% SZS status GaveUp for HL411507+5.p
185567.59/24483.02	eprover: CPU time limit exceeded, terminating
185567.59/24483.02	% SZS status Ended for HL411507+5.p
185575.81/24483.99	% SZS status Started for HL411508+5.p
185575.81/24483.99	% SZS status GaveUp for HL411508+5.p
185575.81/24483.99	eprover: CPU time limit exceeded, terminating
185575.81/24483.99	% SZS status Ended for HL411508+5.p
185582.44/24484.86	% SZS status Started for HL411513+4.p
185582.44/24484.86	% SZS status GaveUp for HL411513+4.p
185582.44/24484.86	eprover: CPU time limit exceeded, terminating
185582.44/24484.86	% SZS status Ended for HL411513+4.p
185591.47/24486.08	% SZS status Started for HL411515+4.p
185591.47/24486.08	% SZS status GaveUp for HL411515+4.p
185591.47/24486.08	eprover: CPU time limit exceeded, terminating
185591.47/24486.08	% SZS status Ended for HL411515+4.p
185593.98/24486.32	% SZS status Started for HL411509+5.p
185593.98/24486.32	% SZS status GaveUp for HL411509+5.p
185593.98/24486.32	eprover: CPU time limit exceeded, terminating
185593.98/24486.32	% SZS status Ended for HL411509+5.p
185606.66/24487.89	% SZS status Started for HL411516+4.p
185606.66/24487.89	% SZS status GaveUp for HL411516+4.p
185606.66/24487.89	eprover: CPU time limit exceeded, terminating
185606.66/24487.89	% SZS status Ended for HL411516+4.p
185607.28/24487.98	% SZS status Started for HL411510+5.p
185607.28/24487.98	% SZS status GaveUp for HL411510+5.p
185607.28/24487.98	eprover: CPU time limit exceeded, terminating
185607.28/24487.98	% SZS status Ended for HL411510+5.p
185618.09/24489.38	% SZS status Started for HL411517+4.p
185618.09/24489.38	% SZS status GaveUp for HL411517+4.p
185618.09/24489.38	eprover: CPU time limit exceeded, terminating
185618.09/24489.38	% SZS status Ended for HL411517+4.p
185621.91/24489.85	% SZS status Started for HL411511+5.p
185621.91/24489.85	% SZS status GaveUp for HL411511+5.p
185621.91/24489.85	eprover: CPU time limit exceeded, terminating
185621.91/24489.85	% SZS status Ended for HL411511+5.p
185630.55/24491.04	% SZS status Started for HL411518+4.p
185630.55/24491.04	% SZS status GaveUp for HL411518+4.p
185630.55/24491.04	eprover: CPU time limit exceeded, terminating
185630.55/24491.04	% SZS status Ended for HL411518+4.p
185638.02/24491.95	% SZS status Started for HL411512+5.p
185638.02/24491.95	% SZS status GaveUp for HL411512+5.p
185638.02/24491.95	eprover: CPU time limit exceeded, terminating
185638.02/24491.95	% SZS status Ended for HL411512+5.p
185645.70/24492.88	% SZS status Started for HL411519+4.p
185645.70/24492.88	% SZS status GaveUp for HL411519+4.p
185645.70/24492.88	eprover: CPU time limit exceeded, terminating
185645.70/24492.88	% SZS status Ended for HL411519+4.p
185646.61/24493.00	% SZS status Started for HL411513+5.p
185646.61/24493.00	% SZS status GaveUp for HL411513+5.p
185646.61/24493.00	eprover: CPU time limit exceeded, terminating
185646.61/24493.00	% SZS status Ended for HL411513+5.p
185661.09/24494.77	% SZS status Started for HL411515+5.p
185661.09/24494.77	% SZS status GaveUp for HL411515+5.p
185661.09/24494.77	eprover: CPU time limit exceeded, terminating
185661.09/24494.77	% SZS status Ended for HL411515+5.p
185662.91/24494.98	% SZS status Started for HL411520+4.p
185662.91/24494.98	% SZS status GaveUp for HL411520+4.p
185662.91/24494.98	eprover: CPU time limit exceeded, terminating
185662.91/24494.98	% SZS status Ended for HL411520+4.p
185671.23/24496.05	% SZS status Started for HL411521+4.p
185671.23/24496.05	% SZS status GaveUp for HL411521+4.p
185671.23/24496.05	eprover: CPU time limit exceeded, terminating
185671.23/24496.05	% SZS status Ended for HL411521+4.p
185677.86/24496.92	% SZS status Started for HL411516+5.p
185677.86/24496.92	% SZS status GaveUp for HL411516+5.p
185677.86/24496.92	eprover: CPU time limit exceeded, terminating
185677.86/24496.92	% SZS status Ended for HL411516+5.p
185685.41/24497.84	% SZS status Started for HL411521+5.p
185685.41/24497.84	% SZS status GaveUp for HL411521+5.p
185685.41/24497.84	eprover: CPU time limit exceeded, terminating
185685.41/24497.84	% SZS status Ended for HL411521+5.p
185686.03/24498.03	% SZS status Started for HL411522+4.p
185686.03/24498.03	% SZS status GaveUp for HL411522+4.p
185686.03/24498.03	eprover: CPU time limit exceeded, terminating
185686.03/24498.03	% SZS status Ended for HL411522+4.p
185692.58/24498.81	% SZS status Started for HL411517+5.p
185692.58/24498.81	% SZS status GaveUp for HL411517+5.p
185692.58/24498.81	eprover: CPU time limit exceeded, terminating
185692.58/24498.81	% SZS status Ended for HL411517+5.p
185701.53/24499.96	% SZS status Started for HL411523+4.p
185701.53/24499.96	% SZS status GaveUp for HL411523+4.p
185701.53/24499.96	eprover: CPU time limit exceeded, terminating
185701.53/24499.96	% SZS status Ended for HL411523+4.p
185703.56/24500.16	% SZS status Started for HL411518+5.p
185703.56/24500.16	% SZS status GaveUp for HL411518+5.p
185703.56/24500.16	eprover: CPU time limit exceeded, terminating
185703.56/24500.16	% SZS status Ended for HL411518+5.p
185709.98/24501.06	% SZS status Started for HL411524+4.p
185709.98/24501.06	% SZS status GaveUp for HL411524+4.p
185709.98/24501.06	eprover: CPU time limit exceeded, terminating
185709.98/24501.06	% SZS status Ended for HL411524+4.p
185717.20/24501.88	% SZS status Started for HL411519+5.p
185717.20/24501.88	% SZS status GaveUp for HL411519+5.p
185717.20/24501.88	eprover: CPU time limit exceeded, terminating
185717.20/24501.88	% SZS status Ended for HL411519+5.p
185726.38/24502.99	% SZS status Started for HL411526+4.p
185726.38/24502.99	% SZS status GaveUp for HL411526+4.p
185726.38/24502.99	eprover: CPU time limit exceeded, terminating
185726.38/24502.99	% SZS status Ended for HL411526+4.p
185733.02/24503.89	% SZS status Started for HL411520+5.p
185733.02/24503.89	% SZS status GaveUp for HL411520+5.p
185733.02/24503.89	eprover: CPU time limit exceeded, terminating
185733.02/24503.89	% SZS status Ended for HL411520+5.p
185734.78/24504.09	% SZS status Started for HL411528+4.p
185734.78/24504.09	% SZS status GaveUp for HL411528+4.p
185734.78/24504.09	eprover: CPU time limit exceeded, terminating
185734.78/24504.09	% SZS status Ended for HL411528+4.p
185749.44/24506.02	% SZS status Started for HL411529+4.p
185749.44/24506.02	% SZS status GaveUp for HL411529+4.p
185749.44/24506.02	eprover: CPU time limit exceeded, terminating
185749.44/24506.02	% SZS status Ended for HL411529+4.p
185755.80/24506.74	% SZS status Started for HL411522+5.p
185755.80/24506.74	% SZS status GaveUp for HL411522+5.p
185755.80/24506.74	eprover: CPU time limit exceeded, terminating
185755.80/24506.74	% SZS status Ended for HL411522+5.p
185759.81/24507.21	% SZS status Started for HL411530+4.p
185759.81/24507.21	% SZS status GaveUp for HL411530+4.p
185759.81/24507.21	eprover: CPU time limit exceeded, terminating
185759.81/24507.21	% SZS status Ended for HL411530+4.p
185773.45/24508.91	% SZS status Started for HL411523+5.p
185773.45/24508.91	% SZS status GaveUp for HL411523+5.p
185773.45/24508.91	eprover: CPU time limit exceeded, terminating
185773.45/24508.91	% SZS status Ended for HL411523+5.p
185779.28/24509.78	% SZS status Started for HL411531+4.p
185779.28/24509.78	% SZS status GaveUp for HL411531+4.p
185779.28/24509.78	eprover: CPU time limit exceeded, terminating
185779.28/24509.78	% SZS status Ended for HL411531+4.p
185779.84/24509.84	% SZS status Started for HL411524+5.p
185779.84/24509.84	% SZS status GaveUp for HL411524+5.p
185779.84/24509.84	eprover: CPU time limit exceeded, terminating
185779.84/24509.84	% SZS status Ended for HL411524+5.p
185788.61/24510.83	% SZS status Started for HL411526+5.p
185788.61/24510.83	% SZS status GaveUp for HL411526+5.p
185788.61/24510.83	eprover: CPU time limit exceeded, terminating
185788.61/24510.83	% SZS status Ended for HL411526+5.p
185797.36/24511.97	% SZS status Started for HL411532+4.p
185797.36/24511.97	% SZS status GaveUp for HL411532+4.p
185797.36/24511.97	eprover: CPU time limit exceeded, terminating
185797.36/24511.97	% SZS status Ended for HL411532+4.p
185802.00/24512.55	% SZS status Started for HL411528+5.p
185802.00/24512.55	% SZS status GaveUp for HL411528+5.p
185802.00/24512.55	eprover: CPU time limit exceeded, terminating
185802.00/24512.55	% SZS status Ended for HL411528+5.p
185805.28/24512.92	% SZS status Started for HL411534+4.p
185805.28/24512.92	% SZS status GaveUp for HL411534+4.p
185805.28/24512.92	eprover: CPU time limit exceeded, terminating
185805.28/24512.92	% SZS status Ended for HL411534+4.p
185818.52/24514.66	% SZS status Started for HL411529+5.p
185818.52/24514.66	% SZS status GaveUp for HL411529+5.p
185818.52/24514.66	eprover: CPU time limit exceeded, terminating
185818.52/24514.66	% SZS status Ended for HL411529+5.p
185821.66/24515.01	% SZS status Started for HL411535+4.p
185821.66/24515.01	% SZS status GaveUp for HL411535+4.p
185821.66/24515.01	eprover: CPU time limit exceeded, terminating
185821.66/24515.01	% SZS status Ended for HL411535+4.p
185829.02/24515.98	% SZS status Started for HL411536+4.p
185829.02/24515.98	% SZS status GaveUp for HL411536+4.p
185829.02/24515.98	eprover: CPU time limit exceeded, terminating
185829.02/24515.98	% SZS status Ended for HL411536+4.p
185834.34/24516.66	% SZS status Started for HL411530+5.p
185834.34/24516.66	% SZS status GaveUp for HL411530+5.p
185834.34/24516.66	eprover: CPU time limit exceeded, terminating
185834.34/24516.66	% SZS status Ended for HL411530+5.p
185845.81/24518.05	% SZS status Started for HL411537+4.p
185845.81/24518.05	% SZS status GaveUp for HL411537+4.p
185845.81/24518.05	eprover: CPU time limit exceeded, terminating
185845.81/24518.05	% SZS status Ended for HL411537+4.p
185846.52/24518.13	% SZS status Started for HL411531+5.p
185846.52/24518.13	% SZS status GaveUp for HL411531+5.p
185846.52/24518.13	eprover: CPU time limit exceeded, terminating
185846.52/24518.13	% SZS status Ended for HL411531+5.p
185858.61/24519.73	% SZS status Started for HL411538+4.p
185858.61/24519.73	% SZS status GaveUp for HL411538+4.p
185858.61/24519.73	eprover: CPU time limit exceeded, terminating
185858.61/24519.73	% SZS status Ended for HL411538+4.p
185865.50/24520.65	% SZS status Started for HL411532+5.p
185865.50/24520.65	% SZS status GaveUp for HL411532+5.p
185865.50/24520.65	eprover: CPU time limit exceeded, terminating
185865.50/24520.65	% SZS status Ended for HL411532+5.p
185870.05/24521.17	% SZS status Started for HL411539+4.p
185870.05/24521.17	% SZS status GaveUp for HL411539+4.p
185870.05/24521.17	eprover: CPU time limit exceeded, terminating
185870.05/24521.17	% SZS status Ended for HL411539+4.p
185873.25/24521.57	% SZS status Started for HL411534+5.p
185873.25/24521.57	% SZS status GaveUp for HL411534+5.p
185873.25/24521.57	eprover: CPU time limit exceeded, terminating
185873.25/24521.57	% SZS status Ended for HL411534+5.p
185886.67/24523.29	% SZS status Started for HL411535+5.p
185886.67/24523.29	% SZS status GaveUp for HL411535+5.p
185886.67/24523.29	eprover: CPU time limit exceeded, terminating
185886.67/24523.29	% SZS status Ended for HL411535+5.p
185890.50/24523.69	% SZS status Started for HL411541+4.p
185890.50/24523.69	% SZS status GaveUp for HL411541+4.p
185890.50/24523.69	eprover: CPU time limit exceeded, terminating
185890.50/24523.69	% SZS status Ended for HL411541+4.p
185897.31/24524.59	% SZS status Started for HL411542+4.p
185897.31/24524.59	% SZS status GaveUp for HL411542+4.p
185897.31/24524.59	eprover: CPU time limit exceeded, terminating
185897.31/24524.59	% SZS status Ended for HL411542+4.p
185904.55/24525.45	% SZS status Started for HL411536+5.p
185904.55/24525.45	% SZS status GaveUp for HL411536+5.p
185904.55/24525.45	eprover: CPU time limit exceeded, terminating
185904.55/24525.45	% SZS status Ended for HL411536+5.p
185911.25/24526.34	% SZS status Started for HL411542+5.p
185911.25/24526.34	% SZS status GaveUp for HL411542+5.p
185911.25/24526.34	eprover: CPU time limit exceeded, terminating
185911.25/24526.34	% SZS status Ended for HL411542+5.p
185914.06/24526.62	% SZS status Started for HL411537+5.p
185914.06/24526.62	% SZS status GaveUp for HL411537+5.p
185914.06/24526.62	eprover: CPU time limit exceeded, terminating
185914.06/24526.62	% SZS status Ended for HL411537+5.p
185914.75/24526.73	% SZS status Started for HL411543+4.p
185914.75/24526.73	% SZS status GaveUp for HL411543+4.p
185914.75/24526.73	eprover: CPU time limit exceeded, terminating
185914.75/24526.73	% SZS status Ended for HL411543+4.p
185929.09/24528.55	% SZS status Started for HL411544+4.p
185929.09/24528.55	% SZS status GaveUp for HL411544+4.p
185929.09/24528.55	eprover: CPU time limit exceeded, terminating
185929.09/24528.55	% SZS status Ended for HL411544+4.p
185931.20/24528.96	% SZS status Started for HL411538+5.p
185931.20/24528.96	% SZS status GaveUp for HL411538+5.p
185931.20/24528.96	eprover: CPU time limit exceeded, terminating
185931.20/24528.96	% SZS status Ended for HL411538+5.p
185937.64/24529.69	% SZS status Started for HL411545+4.p
185937.64/24529.69	% SZS status GaveUp for HL411545+4.p
185937.64/24529.69	eprover: CPU time limit exceeded, terminating
185937.64/24529.69	% SZS status Ended for HL411545+4.p
185945.58/24530.62	% SZS status Started for HL411539+5.p
185945.58/24530.62	% SZS status GaveUp for HL411539+5.p
185945.58/24530.62	eprover: CPU time limit exceeded, terminating
185945.58/24530.62	% SZS status Ended for HL411539+5.p
185953.59/24531.62	% SZS status Started for HL411546+4.p
185953.59/24531.62	% SZS status GaveUp for HL411546+4.p
185953.59/24531.62	eprover: CPU time limit exceeded, terminating
185953.59/24531.62	% SZS status Ended for HL411546+4.p
185956.09/24531.96	% SZS status Started for HL411541+5.p
185956.09/24531.96	% SZS status GaveUp for HL411541+5.p
185956.09/24531.96	eprover: CPU time limit exceeded, terminating
185956.09/24531.96	% SZS status Ended for HL411541+5.p
185961.91/24532.74	% SZS status Started for HL411547+4.p
185961.91/24532.74	% SZS status GaveUp for HL411547+4.p
185961.91/24532.74	eprover: CPU time limit exceeded, terminating
185961.91/24532.74	% SZS status Ended for HL411547+4.p
185977.28/24534.65	% SZS status Started for HL411548+4.p
185977.28/24534.65	% SZS status GaveUp for HL411548+4.p
185977.28/24534.65	eprover: CPU time limit exceeded, terminating
185977.28/24534.65	% SZS status Ended for HL411548+4.p
185985.09/24535.60	% SZS status Started for HL411543+5.p
185985.09/24535.60	% SZS status GaveUp for HL411543+5.p
185985.09/24535.60	eprover: CPU time limit exceeded, terminating
185985.09/24535.60	% SZS status Ended for HL411543+5.p
185986.55/24535.88	% SZS status Started for HL411549+4.p
185986.55/24535.88	% SZS status GaveUp for HL411549+4.p
185986.55/24535.88	eprover: CPU time limit exceeded, terminating
185986.55/24535.88	% SZS status Ended for HL411549+4.p
185996.14/24537.08	% SZS status Started for HL411544+5.p
185996.14/24537.08	% SZS status GaveUp for HL411544+5.p
185996.14/24537.08	eprover: CPU time limit exceeded, terminating
185996.14/24537.08	% SZS status Ended for HL411544+5.p
186001.02/24537.65	% SZS status Started for HL411545+5.p
186001.02/24537.65	% SZS status GaveUp for HL411545+5.p
186001.02/24537.65	eprover: CPU time limit exceeded, terminating
186001.02/24537.65	% SZS status Ended for HL411545+5.p
186008.98/24538.64	% SZS status Started for HL411550+4.p
186008.98/24538.64	% SZS status GaveUp for HL411550+4.p
186008.98/24538.64	eprover: CPU time limit exceeded, terminating
186008.98/24538.64	% SZS status Ended for HL411550+4.p
186012.02/24538.99	% SZS status Started for HL411550+5.p
186012.02/24538.99	% SZS status GaveUp for HL411550+5.p
186012.02/24538.99	eprover: CPU time limit exceeded, terminating
186012.02/24538.99	% SZS status Ended for HL411550+5.p
186018.66/24539.88	% SZS status Started for HL411546+5.p
186018.66/24539.88	% SZS status GaveUp for HL411546+5.p
186018.66/24539.88	eprover: CPU time limit exceeded, terminating
186018.66/24539.88	% SZS status Ended for HL411546+5.p
186020.25/24540.12	% SZS status Started for HL411551+4.p
186020.25/24540.12	% SZS status GaveUp for HL411551+4.p
186020.25/24540.12	eprover: CPU time limit exceeded, terminating
186020.25/24540.12	% SZS status Ended for HL411551+4.p
186030.72/24541.36	% SZS status Started for HL411547+5.p
186030.72/24541.36	% SZS status GaveUp for HL411547+5.p
186030.72/24541.36	eprover: CPU time limit exceeded, terminating
186030.72/24541.36	% SZS status Ended for HL411547+5.p
186032.39/24541.68	% SZS status Started for HL411553+4.p
186032.39/24541.68	% SZS status GaveUp for HL411553+4.p
186032.39/24541.68	eprover: CPU time limit exceeded, terminating
186032.39/24541.68	% SZS status Ended for HL411553+4.p
186040.70/24542.66	% SZS status Started for HL411548+5.p
186040.70/24542.66	% SZS status GaveUp for HL411548+5.p
186040.70/24542.66	eprover: CPU time limit exceeded, terminating
186040.70/24542.66	% SZS status Ended for HL411548+5.p
186042.22/24542.91	% SZS status Started for HL411555+4.p
186042.22/24542.91	% SZS status GaveUp for HL411555+4.p
186042.22/24542.91	eprover: CPU time limit exceeded, terminating
186042.22/24542.91	% SZS status Ended for HL411555+4.p
186054.22/24544.38	% SZS status Started for HL411556+4.p
186054.22/24544.38	% SZS status GaveUp for HL411556+4.p
186054.22/24544.38	eprover: CPU time limit exceeded, terminating
186054.22/24544.38	% SZS status Ended for HL411556+4.p
186064.22/24545.59	% SZS status Started for HL411549+5.p
186064.22/24545.59	% SZS status GaveUp for HL411549+5.p
186064.22/24545.59	eprover: CPU time limit exceeded, terminating
186064.22/24545.59	% SZS status Ended for HL411549+5.p
186064.48/24545.68	% SZS status Started for HL411558+4.p
186064.48/24545.68	% SZS status GaveUp for HL411558+4.p
186064.48/24545.68	eprover: CPU time limit exceeded, terminating
186064.48/24545.68	% SZS status Ended for HL411558+4.p
186078.98/24547.42	% SZS status Started for HL411559+4.p
186078.98/24547.42	% SZS status GaveUp for HL411559+4.p
186078.98/24547.42	eprover: CPU time limit exceeded, terminating
186078.98/24547.42	% SZS status Ended for HL411559+4.p
186086.89/24548.43	% SZS status Started for HL411551+5.p
186086.89/24548.43	% SZS status GaveUp for HL411551+5.p
186086.89/24548.43	eprover: CPU time limit exceeded, terminating
186086.89/24548.43	% SZS status Ended for HL411551+5.p
186089.48/24548.73	% SZS status Started for HL411560+4.p
186089.48/24548.73	% SZS status GaveUp for HL411560+4.p
186089.48/24548.73	eprover: CPU time limit exceeded, terminating
186089.48/24548.73	% SZS status Ended for HL411560+4.p
186096.19/24549.69	% SZS status Started for HL411553+5.p
186096.19/24549.69	% SZS status GaveUp for HL411553+5.p
186096.19/24549.69	eprover: CPU time limit exceeded, terminating
186096.19/24549.69	% SZS status Ended for HL411553+5.p
186107.64/24551.05	% SZS status Started for HL411555+5.p
186107.64/24551.05	% SZS status GaveUp for HL411555+5.p
186107.64/24551.05	eprover: CPU time limit exceeded, terminating
186107.64/24551.05	% SZS status Ended for HL411555+5.p
186109.97/24551.47	% SZS status Started for HL411563+4.p
186109.97/24551.47	% SZS status GaveUp for HL411563+4.p
186109.97/24551.47	eprover: CPU time limit exceeded, terminating
186109.97/24551.47	% SZS status Ended for HL411563+4.p
186117.66/24552.36	% SZS status Started for HL411556+5.p
186117.66/24552.36	% SZS status GaveUp for HL411556+5.p
186117.66/24552.36	eprover: CPU time limit exceeded, terminating
186117.66/24552.36	% SZS status Ended for HL411556+5.p
186120.61/24552.72	% SZS status Started for HL411564+4.p
186120.61/24552.72	% SZS status GaveUp for HL411564+4.p
186120.61/24552.72	eprover: CPU time limit exceeded, terminating
186120.61/24552.72	% SZS status Ended for HL411564+4.p
186129.78/24553.82	% SZS status Started for HL411558+5.p
186129.78/24553.82	% SZS status GaveUp for HL411558+5.p
186129.78/24553.82	eprover: CPU time limit exceeded, terminating
186129.78/24553.82	% SZS status Ended for HL411558+5.p
186134.64/24554.49	% SZS status Started for HL411565+4.p
186134.64/24554.49	% SZS status GaveUp for HL411565+4.p
186134.64/24554.49	eprover: CPU time limit exceeded, terminating
186134.64/24554.49	% SZS status Ended for HL411565+4.p
186145.66/24555.80	% SZS status Started for HL411566+4.p
186145.66/24555.80	% SZS status GaveUp for HL411566+4.p
186145.66/24555.80	eprover: CPU time limit exceeded, terminating
186145.66/24555.80	% SZS status Ended for HL411566+4.p
186150.39/24556.46	% SZS status Started for HL411559+5.p
186150.39/24556.46	% SZS status GaveUp for HL411559+5.p
186150.39/24556.46	eprover: CPU time limit exceeded, terminating
186150.39/24556.46	% SZS status Ended for HL411559+5.p
186158.97/24557.53	% SZS status Started for HL411567+4.p
186158.97/24557.53	% SZS status GaveUp for HL411567+4.p
186158.97/24557.53	eprover: CPU time limit exceeded, terminating
186158.97/24557.53	% SZS status Ended for HL411567+4.p
186163.56/24558.13	% SZS status Started for HL411560+5.p
186163.56/24558.13	% SZS status GaveUp for HL411560+5.p
186163.56/24558.13	eprover: CPU time limit exceeded, terminating
186163.56/24558.13	% SZS status Ended for HL411560+5.p
186173.78/24559.41	% SZS status Started for HL411563+5.p
186173.78/24559.41	% SZS status GaveUp for HL411563+5.p
186173.78/24559.41	eprover: CPU time limit exceeded, terminating
186173.78/24559.41	% SZS status Ended for HL411563+5.p
186175.19/24559.51	% SZS status Started for HL411568+4.p
186175.19/24559.51	% SZS status GaveUp for HL411568+4.p
186175.19/24559.51	eprover: CPU time limit exceeded, terminating
186175.19/24559.51	% SZS status Ended for HL411568+4.p
186188.02/24561.21	% SZS status Started for HL411569+4.p
186188.02/24561.21	% SZS status GaveUp for HL411569+4.p
186188.02/24561.21	eprover: CPU time limit exceeded, terminating
186188.02/24561.21	% SZS status Ended for HL411569+4.p
186192.91/24561.83	% SZS status Started for HL411564+5.p
186192.91/24561.83	% SZS status GaveUp for HL411564+5.p
186192.91/24561.83	eprover: CPU time limit exceeded, terminating
186192.91/24561.83	% SZS status Ended for HL411564+5.p
186198.02/24562.60	% SZS status Started for HL411570+4.p
186198.02/24562.60	% SZS status GaveUp for HL411570+4.p
186198.02/24562.60	eprover: CPU time limit exceeded, terminating
186198.02/24562.60	% SZS status Ended for HL411570+4.p
186203.19/24563.03	% SZS status Started for HL411565+5.p
186203.19/24563.03	% SZS status GaveUp for HL411565+5.p
186203.19/24563.03	eprover: CPU time limit exceeded, terminating
186203.19/24563.03	% SZS status Ended for HL411565+5.p
186214.97/24564.51	% SZS status Started for HL411566+5.p
186214.97/24564.51	% SZS status GaveUp for HL411566+5.p
186214.97/24564.51	eprover: CPU time limit exceeded, terminating
186214.97/24564.51	% SZS status Ended for HL411566+5.p
186216.95/24564.89	% SZS status Started for HL411571+4.p
186216.95/24564.89	% SZS status GaveUp for HL411571+4.p
186216.95/24564.89	eprover: CPU time limit exceeded, terminating
186216.95/24564.89	% SZS status Ended for HL411571+4.p
186227.50/24566.12	% SZS status Started for HL411573+4.p
186227.50/24566.12	% SZS status GaveUp for HL411573+4.p
186227.50/24566.12	eprover: CPU time limit exceeded, terminating
186227.50/24566.12	% SZS status Ended for HL411573+4.p
186232.30/24566.70	% SZS status Started for HL411567+5.p
186232.30/24566.70	% SZS status GaveUp for HL411567+5.p
186232.30/24566.70	eprover: CPU time limit exceeded, terminating
186232.30/24566.70	% SZS status Ended for HL411567+5.p
186242.70/24568.03	% SZS status Started for HL411574+4.p
186242.70/24568.03	% SZS status GaveUp for HL411574+4.p
186242.70/24568.03	eprover: CPU time limit exceeded, terminating
186242.70/24568.03	% SZS status Ended for HL411574+4.p
186243.56/24568.19	% SZS status Started for HL411568+5.p
186243.56/24568.19	% SZS status GaveUp for HL411568+5.p
186243.56/24568.19	eprover: CPU time limit exceeded, terminating
186243.56/24568.19	% SZS status Ended for HL411568+5.p
186255.62/24569.74	% SZS status Started for HL411575+4.p
186255.62/24569.74	% SZS status GaveUp for HL411575+4.p
186255.62/24569.74	eprover: CPU time limit exceeded, terminating
186255.62/24569.74	% SZS status Ended for HL411575+4.p
186259.25/24570.15	% SZS status Started for HL411569+5.p
186259.25/24570.15	% SZS status GaveUp for HL411569+5.p
186259.25/24570.15	eprover: CPU time limit exceeded, terminating
186259.25/24570.15	% SZS status Ended for HL411569+5.p
186268.11/24571.25	% SZS status Started for HL411576+4.p
186268.11/24571.25	% SZS status GaveUp for HL411576+4.p
186268.11/24571.25	eprover: CPU time limit exceeded, terminating
186268.11/24571.25	% SZS status Ended for HL411576+4.p
186273.44/24571.94	% SZS status Started for HL411570+5.p
186273.44/24571.94	% SZS status GaveUp for HL411570+5.p
186273.44/24571.94	eprover: CPU time limit exceeded, terminating
186273.44/24571.94	% SZS status Ended for HL411570+5.p
186283.33/24573.18	% SZS status Started for HL411578+4.p
186283.33/24573.18	% SZS status GaveUp for HL411578+4.p
186283.33/24573.18	eprover: CPU time limit exceeded, terminating
186283.33/24573.18	% SZS status Ended for HL411578+4.p
186283.59/24573.25	% SZS status Started for HL411571+5.p
186283.59/24573.25	% SZS status GaveUp for HL411571+5.p
186283.59/24573.25	eprover: CPU time limit exceeded, terminating
186283.59/24573.25	% SZS status Ended for HL411571+5.p
186297.59/24574.97	% SZS status Started for HL411579+4.p
186297.59/24574.97	% SZS status GaveUp for HL411579+4.p
186297.59/24574.97	eprover: CPU time limit exceeded, terminating
186297.59/24574.97	% SZS status Ended for HL411579+4.p
186302.95/24575.67	% SZS status Started for HL411573+5.p
186302.95/24575.67	% SZS status GaveUp for HL411573+5.p
186302.95/24575.67	eprover: CPU time limit exceeded, terminating
186302.95/24575.67	% SZS status Ended for HL411573+5.p
186308.25/24576.34	% SZS status Started for HL411582+4.p
186308.25/24576.34	% SZS status GaveUp for HL411582+4.p
186308.25/24576.34	eprover: CPU time limit exceeded, terminating
186308.25/24576.34	% SZS status Ended for HL411582+4.p
186314.77/24577.12	% SZS status Started for HL411574+5.p
186314.77/24577.12	% SZS status GaveUp for HL411574+5.p
186314.77/24577.12	eprover: CPU time limit exceeded, terminating
186314.77/24577.12	% SZS status Ended for HL411574+5.p
186321.91/24578.02	% SZS status Started for HL411582+5.p
186321.91/24578.02	% SZS status GaveUp for HL411582+5.p
186321.91/24578.02	eprover: CPU time limit exceeded, terminating
186321.91/24578.02	% SZS status Ended for HL411582+5.p
186327.14/24578.70	% SZS status Started for HL411583+4.p
186327.14/24578.70	% SZS status GaveUp for HL411583+4.p
186327.14/24578.70	eprover: CPU time limit exceeded, terminating
186327.14/24578.70	% SZS status Ended for HL411583+4.p
186329.17/24578.97	% SZS status Started for HL411575+5.p
186329.17/24578.97	% SZS status GaveUp for HL411575+5.p
186329.17/24578.97	eprover: CPU time limit exceeded, terminating
186329.17/24578.97	% SZS status Ended for HL411575+5.p
186338.69/24580.16	% SZS status Started for HL411584+4.p
186338.69/24580.16	% SZS status GaveUp for HL411584+4.p
186338.69/24580.16	eprover: CPU time limit exceeded, terminating
186338.69/24580.16	% SZS status Ended for HL411584+4.p
186340.94/24580.41	% SZS status Started for HL411576+5.p
186340.94/24580.41	% SZS status GaveUp for HL411576+5.p
186340.94/24580.41	eprover: CPU time limit exceeded, terminating
186340.94/24580.41	% SZS status Ended for HL411576+5.p
186351.39/24581.77	% SZS status Started for HL411585+4.p
186351.39/24581.77	% SZS status GaveUp for HL411585+4.p
186351.39/24581.77	eprover: CPU time limit exceeded, terminating
186351.39/24581.77	% SZS status Ended for HL411585+4.p
186354.25/24582.13	% SZS status Started for HL411578+5.p
186354.25/24582.13	% SZS status GaveUp for HL411578+5.p
186354.25/24582.13	eprover: CPU time limit exceeded, terminating
186354.25/24582.13	% SZS status Ended for HL411578+5.p
186362.86/24583.23	% SZS status Started for HL411586+4.p
186362.86/24583.23	% SZS status GaveUp for HL411586+4.p
186362.86/24583.23	eprover: CPU time limit exceeded, terminating
186362.86/24583.23	% SZS status Ended for HL411586+4.p
186369.03/24584.02	% SZS status Started for HL411579+5.p
186369.03/24584.02	% SZS status GaveUp for HL411579+5.p
186369.03/24584.02	eprover: CPU time limit exceeded, terminating
186369.03/24584.02	% SZS status Ended for HL411579+5.p
186376.50/24584.89	% SZS status Started for HL411587+4.p
186376.50/24584.89	% SZS status GaveUp for HL411587+4.p
186376.50/24584.89	eprover: CPU time limit exceeded, terminating
186376.50/24584.89	% SZS status Ended for HL411587+4.p
186387.08/24586.27	% SZS status Started for HL411588+4.p
186387.08/24586.27	% SZS status GaveUp for HL411588+4.p
186387.08/24586.27	eprover: CPU time limit exceeded, terminating
186387.08/24586.27	% SZS status Ended for HL411588+4.p
186394.48/24587.15	% SZS status Started for HL411583+5.p
186394.48/24587.15	% SZS status GaveUp for HL411583+5.p
186394.48/24587.15	eprover: CPU time limit exceeded, terminating
186394.48/24587.15	% SZS status Ended for HL411583+5.p
186400.23/24587.95	% SZS status Started for HL411589+4.p
186400.23/24587.95	% SZS status GaveUp for HL411589+4.p
186400.23/24587.95	eprover: CPU time limit exceeded, terminating
186400.23/24587.95	% SZS status Ended for HL411589+4.p
186407.73/24588.85	% SZS status Started for HL411584+5.p
186407.73/24588.85	% SZS status GaveUp for HL411584+5.p
186407.73/24588.85	eprover: CPU time limit exceeded, terminating
186407.73/24588.85	% SZS status Ended for HL411584+5.p
186415.06/24589.74	% SZS status Started for HL411585+5.p
186415.06/24589.74	% SZS status GaveUp for HL411585+5.p
186415.06/24589.74	eprover: CPU time limit exceeded, terminating
186415.06/24589.74	% SZS status Ended for HL411585+5.p
186418.33/24590.17	% SZS status Started for HL411591+4.p
186418.33/24590.17	% SZS status GaveUp for HL411591+4.p
186418.33/24590.17	eprover: CPU time limit exceeded, terminating
186418.33/24590.17	% SZS status Ended for HL411591+4.p
186426.20/24591.16	% SZS status Started for HL411586+5.p
186426.20/24591.16	% SZS status GaveUp for HL411586+5.p
186426.20/24591.16	eprover: CPU time limit exceeded, terminating
186426.20/24591.16	% SZS status Ended for HL411586+5.p
186431.92/24591.88	% SZS status Started for HL411593+4.p
186431.92/24591.88	% SZS status GaveUp for HL411593+4.p
186431.92/24591.88	eprover: CPU time limit exceeded, terminating
186431.92/24591.88	% SZS status Ended for HL411593+4.p
186439.73/24592.84	% SZS status Started for HL411587+5.p
186439.73/24592.84	% SZS status GaveUp for HL411587+5.p
186439.73/24592.84	eprover: CPU time limit exceeded, terminating
186439.73/24592.84	% SZS status Ended for HL411587+5.p
186441.88/24593.20	% SZS status Started for HL411594+4.p
186441.88/24593.20	% SZS status GaveUp for HL411594+4.p
186441.88/24593.20	eprover: CPU time limit exceeded, terminating
186441.88/24593.20	% SZS status Ended for HL411594+4.p
186455.20/24594.91	% SZS status Started for HL411595+4.p
186455.20/24594.91	% SZS status GaveUp for HL411595+4.p
186455.20/24594.91	eprover: CPU time limit exceeded, terminating
186455.20/24594.91	% SZS status Ended for HL411595+4.p
186457.33/24595.09	% SZS status Started for HL411588+5.p
186457.33/24595.09	% SZS status GaveUp for HL411588+5.p
186457.33/24595.09	eprover: CPU time limit exceeded, terminating
186457.33/24595.09	% SZS status Ended for HL411588+5.p
186466.03/24596.23	% SZS status Started for HL411597+4.p
186466.03/24596.23	% SZS status GaveUp for HL411597+4.p
186466.03/24596.23	eprover: CPU time limit exceeded, terminating
186466.03/24596.23	% SZS status Ended for HL411597+4.p
186474.73/24596.98	% SZS status Started for HL411589+5.p
186474.73/24596.98	% SZS status GaveUp for HL411589+5.p
186474.73/24596.98	eprover: CPU time limit exceeded, terminating
186474.73/24596.98	% SZS status Ended for HL411589+5.p
186483.59/24598.13	% SZS status Started for HL411598+4.p
186483.59/24598.13	% SZS status GaveUp for HL411598+4.p
186483.59/24598.13	eprover: CPU time limit exceeded, terminating
186483.59/24598.13	% SZS status Ended for HL411598+4.p
186487.61/24598.62	% SZS status Started for HL411591+5.p
186487.61/24598.62	% SZS status GaveUp for HL411591+5.p
186487.61/24598.62	eprover: CPU time limit exceeded, terminating
186487.61/24598.62	% SZS status Ended for HL411591+5.p
186498.27/24600.03	% SZS status Started for HL411599+4.p
186498.27/24600.03	% SZS status GaveUp for HL411599+4.p
186498.27/24600.03	eprover: CPU time limit exceeded, terminating
186498.27/24600.03	% SZS status Ended for HL411599+4.p
186503.06/24600.54	% SZS status Started for HL411593+5.p
186503.06/24600.54	% SZS status GaveUp for HL411593+5.p
186503.06/24600.54	eprover: CPU time limit exceeded, terminating
186503.06/24600.54	% SZS status Ended for HL411593+5.p
186512.02/24601.65	% SZS status Started for HL411601+4.p
186512.02/24601.65	% SZS status GaveUp for HL411601+4.p
186512.02/24601.65	eprover: CPU time limit exceeded, terminating
186512.02/24601.65	% SZS status Ended for HL411601+4.p
186514.19/24601.96	% SZS status Started for HL411594+5.p
186514.19/24601.96	% SZS status GaveUp for HL411594+5.p
186514.19/24601.96	eprover: CPU time limit exceeded, terminating
186514.19/24601.96	% SZS status Ended for HL411594+5.p
186523.06/24603.06	% SZS status Started for HL411601+5.p
186523.06/24603.06	% SZS status GaveUp for HL411601+5.p
186523.06/24603.06	eprover: CPU time limit exceeded, terminating
186523.06/24603.06	% SZS status Ended for HL411601+5.p
186527.23/24603.58	% SZS status Started for HL411602+4.p
186527.23/24603.58	% SZS status GaveUp for HL411602+4.p
186527.23/24603.58	eprover: CPU time limit exceeded, terminating
186527.23/24603.58	% SZS status Ended for HL411602+4.p
186528.05/24603.68	% SZS status Started for HL411595+5.p
186528.05/24603.68	% SZS status GaveUp for HL411595+5.p
186528.05/24603.68	eprover: CPU time limit exceeded, terminating
186528.05/24603.68	% SZS status Ended for HL411595+5.p
186535.95/24604.69	% SZS status Started for HL411602+5.p
186535.95/24604.69	% SZS status GaveUp for HL411602+5.p
186535.95/24604.69	eprover: CPU time limit exceeded, terminating
186535.95/24604.69	% SZS status Ended for HL411602+5.p
186537.78/24605.00	% SZS status Started for HL411604+4.p
186537.78/24605.00	% SZS status GaveUp for HL411604+4.p
186537.78/24605.00	eprover: CPU time limit exceeded, terminating
186537.78/24605.00	% SZS status Ended for HL411604+4.p
186543.58/24605.66	% SZS status Started for HL411597+5.p
186543.58/24605.66	% SZS status GaveUp for HL411597+5.p
186543.58/24605.66	eprover: CPU time limit exceeded, terminating
186543.58/24605.66	% SZS status Ended for HL411597+5.p
186546.98/24606.09	% SZS status Started for HL411604+5.p
186546.98/24606.09	% SZS status GaveUp for HL411604+5.p
186546.98/24606.09	eprover: CPU time limit exceeded, terminating
186546.98/24606.09	% SZS status Ended for HL411604+5.p
186550.56/24606.61	% SZS status Started for HL411605+4.p
186550.56/24606.61	% SZS status GaveUp for HL411605+4.p
186550.56/24606.61	eprover: CPU time limit exceeded, terminating
186550.56/24606.61	% SZS status Ended for HL411605+4.p
186551.11/24606.71	% SZS status Started for HL411605+5.p
186551.11/24606.71	% SZS status GaveUp for HL411605+5.p
186551.11/24606.71	eprover: CPU time limit exceeded, terminating
186551.11/24606.71	% SZS status Ended for HL411605+5.p
186559.25/24607.37	% SZS status Started for HL411598+5.p
186559.25/24607.37	% SZS status GaveUp for HL411598+5.p
186559.25/24607.37	eprover: CPU time limit exceeded, terminating
186559.25/24607.37	% SZS status Ended for HL411598+5.p
186561.42/24607.72	% SZS status Started for HL411606+4.p
186561.42/24607.72	% SZS status GaveUp for HL411606+4.p
186561.42/24607.72	eprover: CPU time limit exceeded, terminating
186561.42/24607.72	% SZS status Ended for HL411606+4.p
186564.58/24608.03	% SZS status Started for HL411606+5.p
186564.58/24608.03	% SZS status GaveUp for HL411606+5.p
186564.58/24608.03	eprover: CPU time limit exceeded, terminating
186564.58/24608.03	% SZS status Ended for HL411606+5.p
186569.72/24608.70	% SZS status Started for HL411607+4.p
186569.72/24608.70	% SZS status GaveUp for HL411607+4.p
186569.72/24608.70	eprover: CPU time limit exceeded, terminating
186569.72/24608.70	% SZS status Ended for HL411607+4.p
186572.27/24609.00	% SZS status Started for HL411599+5.p
186572.27/24609.00	% SZS status GaveUp for HL411599+5.p
186572.27/24609.00	eprover: CPU time limit exceeded, terminating
186572.27/24609.00	% SZS status Ended for HL411599+5.p
186573.20/24609.13	% SZS status Started for HL411607+5.p
186573.20/24609.13	% SZS status GaveUp for HL411607+5.p
186573.20/24609.13	eprover: CPU time limit exceeded, terminating
186573.20/24609.13	% SZS status Ended for HL411607+5.p
186577.22/24609.65	% SZS status Started for HL411608+4.p
186577.22/24609.65	% SZS status GaveUp for HL411608+4.p
186577.22/24609.65	eprover: CPU time limit exceeded, terminating
186577.22/24609.65	% SZS status Ended for HL411608+4.p
186578.80/24609.85	% SZS status Started for HL411608+5.p
186578.80/24609.85	% SZS status GaveUp for HL411608+5.p
186578.80/24609.85	eprover: CPU time limit exceeded, terminating
186578.80/24609.85	% SZS status Ended for HL411608+5.p
186583.38/24610.41	% SZS status Started for HL411609+4.p
186583.38/24610.41	% SZS status GaveUp for HL411609+4.p
186583.38/24610.41	eprover: CPU time limit exceeded, terminating
186583.38/24610.41	% SZS status Ended for HL411609+4.p
186586.28/24610.76	% SZS status Started for HL411609+5.p
186586.28/24610.76	% SZS status GaveUp for HL411609+5.p
186586.28/24610.76	eprover: CPU time limit exceeded, terminating
186586.28/24610.76	% SZS status Ended for HL411609+5.p
186588.42/24611.07	% SZS status Started for HL411610+4.p
186588.42/24611.07	% SZS status GaveUp for HL411610+4.p
186588.42/24611.07	eprover: CPU time limit exceeded, terminating
186588.42/24611.07	% SZS status Ended for HL411610+4.p
186594.02/24611.73	% SZS status Started for HL411610+5.p
186594.02/24611.73	% SZS status GaveUp for HL411610+5.p
186594.02/24611.73	eprover: CPU time limit exceeded, terminating
186594.02/24611.73	% SZS status Ended for HL411610+5.p
186596.25/24612.03	% SZS status Started for HL411611+4.p
186596.25/24612.03	% SZS status GaveUp for HL411611+4.p
186596.25/24612.03	eprover: CPU time limit exceeded, terminating
186596.25/24612.03	% SZS status Ended for HL411611+4.p
186596.73/24612.16	% SZS status Started for HL411611+5.p
186596.73/24612.16	% SZS status GaveUp for HL411611+5.p
186596.73/24612.16	eprover: CPU time limit exceeded, terminating
186596.73/24612.16	% SZS status Ended for HL411611+5.p
186600.97/24612.68	% SZS status Started for HL411612+4.p
186600.97/24612.68	% SZS status GaveUp for HL411612+4.p
186600.97/24612.68	eprover: CPU time limit exceeded, terminating
186600.97/24612.68	% SZS status Ended for HL411612+4.p
186604.33/24613.03	% SZS status Started for HL411612+5.p
186604.33/24613.03	% SZS status GaveUp for HL411612+5.p
186604.33/24613.03	eprover: CPU time limit exceeded, terminating
186604.33/24613.03	% SZS status Ended for HL411612+5.p
186606.95/24613.44	% SZS status Started for HL411613+4.p
186606.95/24613.44	% SZS status GaveUp for HL411613+4.p
186606.95/24613.44	eprover: CPU time limit exceeded, terminating
186606.95/24613.44	% SZS status Ended for HL411613+4.p
186610.23/24613.79	% SZS status Started for HL411613+5.p
186610.23/24613.79	% SZS status GaveUp for HL411613+5.p
186610.23/24613.79	eprover: CPU time limit exceeded, terminating
186610.23/24613.79	% SZS status Ended for HL411613+5.p
186612.80/24614.10	% SZS status Started for HL411615+4.p
186612.80/24614.10	% SZS status GaveUp for HL411615+4.p
186612.80/24614.10	eprover: CPU time limit exceeded, terminating
186612.80/24614.10	% SZS status Ended for HL411615+4.p
186617.98/24614.77	% SZS status Started for HL411615+5.p
186617.98/24614.77	% SZS status GaveUp for HL411615+5.p
186617.98/24614.77	eprover: CPU time limit exceeded, terminating
186617.98/24614.77	% SZS status Ended for HL411615+5.p
186620.12/24615.06	% SZS status Started for HL411616+4.p
186620.12/24615.06	% SZS status GaveUp for HL411616+4.p
186620.12/24615.06	eprover: CPU time limit exceeded, terminating
186620.12/24615.06	% SZS status Ended for HL411616+4.p
186620.67/24615.19	% SZS status Started for HL411616+5.p
186620.67/24615.19	% SZS status GaveUp for HL411616+5.p
186620.67/24615.19	eprover: CPU time limit exceeded, terminating
186620.67/24615.19	% SZS status Ended for HL411616+5.p
186624.59/24615.71	% SZS status Started for HL411618+4.p
186624.59/24615.71	% SZS status GaveUp for HL411618+4.p
186624.59/24615.71	eprover: CPU time limit exceeded, terminating
186624.59/24615.71	% SZS status Ended for HL411618+4.p
186628.44/24616.16	% SZS status Started for HL411618+5.p
186628.44/24616.16	% SZS status GaveUp for HL411618+5.p
186628.44/24616.16	eprover: CPU time limit exceeded, terminating
186628.44/24616.16	% SZS status Ended for HL411618+5.p
186631.34/24616.47	% SZS status Started for HL411620+4.p
186631.34/24616.47	% SZS status GaveUp for HL411620+4.p
186631.34/24616.47	eprover: CPU time limit exceeded, terminating
186631.34/24616.47	% SZS status Ended for HL411620+4.p
186633.91/24616.83	% SZS status Started for HL411620+5.p
186633.91/24616.83	% SZS status GaveUp for HL411620+5.p
186633.91/24616.83	eprover: CPU time limit exceeded, terminating
186633.91/24616.83	% SZS status Ended for HL411620+5.p
186636.94/24617.14	% SZS status Started for HL411621+4.p
186636.94/24617.14	% SZS status GaveUp for HL411621+4.p
186636.94/24617.14	eprover: CPU time limit exceeded, terminating
186636.94/24617.14	% SZS status Ended for HL411621+4.p
186642.16/24617.80	% SZS status Started for HL411621+5.p
186642.16/24617.80	% SZS status GaveUp for HL411621+5.p
186642.16/24617.80	eprover: CPU time limit exceeded, terminating
186642.16/24617.80	% SZS status Ended for HL411621+5.p
186644.30/24618.10	% SZS status Started for HL411622+4.p
186644.30/24618.10	% SZS status GaveUp for HL411622+4.p
186644.30/24618.10	eprover: CPU time limit exceeded, terminating
186644.30/24618.10	% SZS status Ended for HL411622+4.p
186645.64/24618.25	% SZS status Started for HL411622+5.p
186645.64/24618.25	% SZS status GaveUp for HL411622+5.p
186645.64/24618.25	eprover: CPU time limit exceeded, terminating
186645.64/24618.25	% SZS status Ended for HL411622+5.p
186650.39/24618.88	% SZS status Started for HL411625+4.p
186650.39/24618.88	% SZS status GaveUp for HL411625+4.p
186650.39/24618.88	eprover: CPU time limit exceeded, terminating
186650.39/24618.88	% SZS status Ended for HL411625+4.p
186652.92/24619.20	% SZS status Started for HL411625+5.p
186652.92/24619.20	% SZS status GaveUp for HL411625+5.p
186652.92/24619.20	eprover: CPU time limit exceeded, terminating
186652.92/24619.20	% SZS status Ended for HL411625+5.p
186654.94/24619.50	% SZS status Started for HL411626+4.p
186654.94/24619.50	% SZS status GaveUp for HL411626+4.p
186654.94/24619.50	eprover: CPU time limit exceeded, terminating
186654.94/24619.50	% SZS status Ended for HL411626+4.p
186658.42/24619.86	% SZS status Started for HL411626+5.p
186658.42/24619.86	% SZS status GaveUp for HL411626+5.p
186658.42/24619.86	eprover: CPU time limit exceeded, terminating
186658.42/24619.86	% SZS status Ended for HL411626+5.p
186660.62/24620.17	% SZS status Started for HL411627+4.p
186660.62/24620.17	% SZS status GaveUp for HL411627+4.p
186660.62/24620.17	eprover: CPU time limit exceeded, terminating
186660.62/24620.17	% SZS status Ended for HL411627+4.p
186665.91/24620.84	% SZS status Started for HL411627+5.p
186665.91/24620.84	% SZS status GaveUp for HL411627+5.p
186665.91/24620.84	eprover: CPU time limit exceeded, terminating
186665.91/24620.84	% SZS status Ended for HL411627+5.p
186667.92/24621.12	% SZS status Started for HL411630+4.p
186667.92/24621.12	% SZS status GaveUp for HL411630+4.p
186667.92/24621.12	eprover: CPU time limit exceeded, terminating
186667.92/24621.12	% SZS status Ended for HL411630+4.p
186670.67/24621.41	% SZS status Started for HL411630+5.p
186670.67/24621.41	% SZS status GaveUp for HL411630+5.p
186670.67/24621.41	eprover: CPU time limit exceeded, terminating
186670.67/24621.41	% SZS status Ended for HL411630+5.p
186674.36/24621.91	% SZS status Started for HL411632+4.p
186674.36/24621.91	% SZS status GaveUp for HL411632+4.p
186674.36/24621.91	eprover: CPU time limit exceeded, terminating
186674.36/24621.91	% SZS status Ended for HL411632+4.p
186677.05/24622.23	% SZS status Started for HL411632+5.p
186677.05/24622.23	% SZS status GaveUp for HL411632+5.p
186677.05/24622.23	eprover: CPU time limit exceeded, terminating
186677.05/24622.23	% SZS status Ended for HL411632+5.p
186679.34/24622.53	% SZS status Started for HL411633+4.p
186679.34/24622.53	% SZS status GaveUp for HL411633+4.p
186679.34/24622.53	eprover: CPU time limit exceeded, terminating
186679.34/24622.53	% SZS status Ended for HL411633+4.p
186682.23/24622.90	% SZS status Started for HL411633+5.p
186682.23/24622.90	% SZS status GaveUp for HL411633+5.p
186682.23/24622.90	eprover: CPU time limit exceeded, terminating
186682.23/24622.90	% SZS status Ended for HL411633+5.p
186684.88/24623.21	% SZS status Started for HL411634+4.p
186684.88/24623.21	% SZS status GaveUp for HL411634+4.p
186684.88/24623.21	eprover: CPU time limit exceeded, terminating
186684.88/24623.21	% SZS status Ended for HL411634+4.p
186690.27/24623.87	% SZS status Started for HL411634+5.p
186690.27/24623.87	% SZS status GaveUp for HL411634+5.p
186690.27/24623.87	eprover: CPU time limit exceeded, terminating
186690.27/24623.87	% SZS status Ended for HL411634+5.p
186692.78/24624.16	% SZS status Started for HL411635+4.p
186692.78/24624.16	% SZS status GaveUp for HL411635+4.p
186692.78/24624.16	eprover: CPU time limit exceeded, terminating
186692.78/24624.16	% SZS status Ended for HL411635+4.p
186695.50/24624.56	% SZS status Started for HL411635+5.p
186695.50/24624.56	% SZS status GaveUp for HL411635+5.p
186695.50/24624.56	eprover: CPU time limit exceeded, terminating
186695.50/24624.56	% SZS status Ended for HL411635+5.p
186699.03/24624.94	% SZS status Started for HL411636+4.p
186699.03/24624.94	% SZS status GaveUp for HL411636+4.p
186699.03/24624.94	eprover: CPU time limit exceeded, terminating
186699.03/24624.94	% SZS status Ended for HL411636+4.p
186701.52/24625.27	% SZS status Started for HL411636+5.p
186701.52/24625.27	% SZS status GaveUp for HL411636+5.p
186701.52/24625.27	eprover: CPU time limit exceeded, terminating
186701.52/24625.27	% SZS status Ended for HL411636+5.p
186703.64/24625.56	% SZS status Started for HL411637+4.p
186703.64/24625.56	% SZS status GaveUp for HL411637+4.p
186703.64/24625.56	eprover: CPU time limit exceeded, terminating
186703.64/24625.56	% SZS status Ended for HL411637+4.p
186706.83/24625.93	% SZS status Started for HL411637+5.p
186706.83/24625.93	% SZS status GaveUp for HL411637+5.p
186706.83/24625.93	eprover: CPU time limit exceeded, terminating
186706.83/24625.93	% SZS status Ended for HL411637+5.p
186708.91/24626.24	% SZS status Started for HL411638+4.p
186708.91/24626.24	% SZS status GaveUp for HL411638+4.p
186708.91/24626.24	eprover: CPU time limit exceeded, terminating
186708.91/24626.24	% SZS status Ended for HL411638+4.p
186713.83/24626.90	% SZS status Started for HL411638+5.p
186713.83/24626.90	% SZS status GaveUp for HL411638+5.p
186713.83/24626.90	eprover: CPU time limit exceeded, terminating
186713.83/24626.90	% SZS status Ended for HL411638+5.p
186717.02/24627.30	% SZS status Started for HL411639+4.p
186717.02/24627.30	% SZS status GaveUp for HL411639+4.p
186717.02/24627.30	eprover: CPU time limit exceeded, terminating
186717.02/24627.30	% SZS status Ended for HL411639+4.p
186719.83/24627.59	% SZS status Started for HL411639+5.p
186719.83/24627.59	% SZS status GaveUp for HL411639+5.p
186719.83/24627.59	eprover: CPU time limit exceeded, terminating
186719.83/24627.59	% SZS status Ended for HL411639+5.p
186722.25/24627.98	% SZS status Started for HL411640+4.p
186722.25/24627.98	% SZS status GaveUp for HL411640+4.p
186722.25/24627.98	eprover: CPU time limit exceeded, terminating
186722.25/24627.98	% SZS status Ended for HL411640+4.p
186724.98/24628.30	% SZS status Started for HL411640+5.p
186724.98/24628.30	% SZS status GaveUp for HL411640+5.p
186724.98/24628.30	eprover: CPU time limit exceeded, terminating
186724.98/24628.30	% SZS status Ended for HL411640+5.p
186727.48/24628.59	% SZS status Started for HL411641+4.p
186727.48/24628.59	% SZS status GaveUp for HL411641+4.p
186727.48/24628.59	eprover: CPU time limit exceeded, terminating
186727.48/24628.59	% SZS status Ended for HL411641+4.p
186730.19/24628.96	% SZS status Started for HL411641+5.p
186730.19/24628.96	% SZS status GaveUp for HL411641+5.p
186730.19/24628.96	eprover: CPU time limit exceeded, terminating
186730.19/24628.96	% SZS status Ended for HL411641+5.p
186733.08/24629.28	% SZS status Started for HL411642+4.p
186733.08/24629.28	% SZS status GaveUp for HL411642+4.p
186733.08/24629.28	eprover: CPU time limit exceeded, terminating
186733.08/24629.28	% SZS status Ended for HL411642+4.p
186739.73/24630.16	% SZS status Started for HL411642+5.p
186739.73/24630.16	% SZS status GaveUp for HL411642+5.p
186739.73/24630.16	eprover: CPU time limit exceeded, terminating
186739.73/24630.16	% SZS status Ended for HL411642+5.p
186742.81/24630.52	% SZS status Started for HL411643+4.p
186742.81/24630.52	% SZS status GaveUp for HL411643+4.p
186742.81/24630.52	eprover: CPU time limit exceeded, terminating
186742.81/24630.52	% SZS status Ended for HL411643+4.p
186744.52/24630.76	% SZS status Started for HL411643+5.p
186744.52/24630.76	% SZS status GaveUp for HL411643+5.p
186744.52/24630.76	eprover: CPU time limit exceeded, terminating
186744.52/24630.76	% SZS status Ended for HL411643+5.p
186746.66/24631.01	% SZS status Started for HL411644+4.p
186746.66/24631.01	% SZS status GaveUp for HL411644+4.p
186746.66/24631.01	eprover: CPU time limit exceeded, terminating
186746.66/24631.01	% SZS status Ended for HL411644+4.p
186749.00/24631.33	% SZS status Started for HL411644+5.p
186749.00/24631.33	% SZS status GaveUp for HL411644+5.p
186749.00/24631.33	eprover: CPU time limit exceeded, terminating
186749.00/24631.33	% SZS status Ended for HL411644+5.p
186751.47/24631.62	% SZS status Started for HL411645+4.p
186751.47/24631.62	% SZS status GaveUp for HL411645+4.p
186751.47/24631.62	eprover: CPU time limit exceeded, terminating
186751.47/24631.62	% SZS status Ended for HL411645+4.p
186754.05/24631.99	% SZS status Started for HL411645+5.p
186754.05/24631.99	% SZS status GaveUp for HL411645+5.p
186754.05/24631.99	eprover: CPU time limit exceeded, terminating
186754.05/24631.99	% SZS status Ended for HL411645+5.p
186756.64/24632.31	% SZS status Started for HL411646+4.p
186756.64/24632.31	% SZS status GaveUp for HL411646+4.p
186756.64/24632.31	eprover: CPU time limit exceeded, terminating
186756.64/24632.31	% SZS status Ended for HL411646+4.p
186763.67/24633.19	% SZS status Started for HL411646+5.p
186763.67/24633.19	% SZS status GaveUp for HL411646+5.p
186763.67/24633.19	eprover: CPU time limit exceeded, terminating
186763.67/24633.19	% SZS status Ended for HL411646+5.p
186767.12/24633.67	% SZS status Started for HL411647+4.p
186767.12/24633.67	% SZS status GaveUp for HL411647+4.p
186767.12/24633.67	eprover: CPU time limit exceeded, terminating
186767.12/24633.67	% SZS status Ended for HL411647+4.p
186768.36/24633.80	% SZS status Started for HL411647+5.p
186768.36/24633.80	% SZS status GaveUp for HL411647+5.p
186768.36/24633.80	eprover: CPU time limit exceeded, terminating
186768.36/24633.80	% SZS status Ended for HL411647+5.p
186770.44/24634.04	% SZS status Started for HL411648+4.p
186770.44/24634.04	% SZS status GaveUp for HL411648+4.p
186770.44/24634.04	eprover: CPU time limit exceeded, terminating
186770.44/24634.04	% SZS status Ended for HL411648+4.p
186772.73/24634.37	% SZS status Started for HL411648+5.p
186772.73/24634.37	% SZS status GaveUp for HL411648+5.p
186772.73/24634.37	eprover: CPU time limit exceeded, terminating
186772.73/24634.37	% SZS status Ended for HL411648+5.p
186775.55/24634.66	% SZS status Started for HL411649+4.p
186775.55/24634.66	% SZS status GaveUp for HL411649+4.p
186775.55/24634.66	eprover: CPU time limit exceeded, terminating
186775.55/24634.66	% SZS status Ended for HL411649+4.p
186778.55/24635.03	% SZS status Started for HL411649+5.p
186778.55/24635.03	% SZS status GaveUp for HL411649+5.p
186778.55/24635.03	eprover: CPU time limit exceeded, terminating
186778.55/24635.03	% SZS status Ended for HL411649+5.p
186781.05/24635.35	% SZS status Started for HL411650+4.p
186781.05/24635.35	% SZS status GaveUp for HL411650+4.p
186781.05/24635.35	eprover: CPU time limit exceeded, terminating
186781.05/24635.35	% SZS status Ended for HL411650+4.p
186788.30/24636.23	% SZS status Started for HL411650+5.p
186788.30/24636.23	% SZS status GaveUp for HL411650+5.p
186788.30/24636.23	eprover: CPU time limit exceeded, terminating
186788.30/24636.23	% SZS status Ended for HL411650+5.p
186792.11/24636.73	% SZS status Started for HL411651+4.p
186792.11/24636.73	% SZS status GaveUp for HL411651+4.p
186792.11/24636.73	eprover: CPU time limit exceeded, terminating
186792.11/24636.73	% SZS status Ended for HL411651+4.p
186792.83/24636.82	% SZS status Started for HL411651+5.p
186792.83/24636.82	% SZS status GaveUp for HL411651+5.p
186792.83/24636.82	eprover: CPU time limit exceeded, terminating
186792.83/24636.82	% SZS status Ended for HL411651+5.p
186794.14/24637.07	% SZS status Started for HL411652+4.p
186794.14/24637.07	% SZS status GaveUp for HL411652+4.p
186794.14/24637.07	eprover: CPU time limit exceeded, terminating
186794.14/24637.07	% SZS status Ended for HL411652+4.p
186798.64/24637.53	% SZS status Started for HL411652+5.p
186798.64/24637.53	% SZS status GaveUp for HL411652+5.p
186798.64/24637.53	eprover: CPU time limit exceeded, terminating
186798.64/24637.53	% SZS status Ended for HL411652+5.p
186799.39/24637.69	% SZS status Started for HL411654+4.p
186799.39/24637.69	% SZS status GaveUp for HL411654+4.p
186799.39/24637.69	eprover: CPU time limit exceeded, terminating
186799.39/24637.69	% SZS status Ended for HL411654+4.p
186802.64/24638.06	% SZS status Started for HL411654+5.p
186802.64/24638.06	% SZS status GaveUp for HL411654+5.p
186802.64/24638.06	eprover: CPU time limit exceeded, terminating
186802.64/24638.06	% SZS status Ended for HL411654+5.p
186805.17/24638.38	% SZS status Started for HL411655+4.p
186805.17/24638.38	% SZS status GaveUp for HL411655+4.p
186805.17/24638.38	eprover: CPU time limit exceeded, terminating
186805.17/24638.38	% SZS status Ended for HL411655+4.p
186812.25/24639.26	% SZS status Started for HL411655+5.p
186812.25/24639.26	% SZS status GaveUp for HL411655+5.p
186812.25/24639.26	eprover: CPU time limit exceeded, terminating
186812.25/24639.26	% SZS status Ended for HL411655+5.p
186816.06/24639.76	% SZS status Started for HL411656+4.p
186816.06/24639.76	% SZS status GaveUp for HL411656+4.p
186816.06/24639.76	eprover: CPU time limit exceeded, terminating
186816.06/24639.76	% SZS status Ended for HL411656+4.p
186816.81/24639.86	% SZS status Started for HL411656+5.p
186816.81/24639.86	% SZS status GaveUp for HL411656+5.p
186816.81/24639.86	eprover: CPU time limit exceeded, terminating
186816.81/24639.86	% SZS status Ended for HL411656+5.p
186820.09/24640.22	% SZS status Started for HL411657+4.p
186820.09/24640.22	% SZS status GaveUp for HL411657+4.p
186820.09/24640.22	eprover: CPU time limit exceeded, terminating
186820.09/24640.22	% SZS status Ended for HL411657+4.p
186822.19/24640.56	% SZS status Started for HL411657+5.p
186822.19/24640.56	% SZS status GaveUp for HL411657+5.p
186822.19/24640.56	eprover: CPU time limit exceeded, terminating
186822.19/24640.56	% SZS status Ended for HL411657+5.p
186823.33/24640.72	% SZS status Started for HL411658+4.p
186823.33/24640.72	% SZS status GaveUp for HL411658+4.p
186823.33/24640.72	eprover: CPU time limit exceeded, terminating
186823.33/24640.72	% SZS status Ended for HL411658+4.p
186827.00/24641.09	% SZS status Started for HL411658+5.p
186827.00/24641.09	% SZS status GaveUp for HL411658+5.p
186827.00/24641.09	eprover: CPU time limit exceeded, terminating
186827.00/24641.09	% SZS status Ended for HL411658+5.p
186829.56/24641.42	% SZS status Started for HL411659+4.p
186829.56/24641.42	% SZS status GaveUp for HL411659+4.p
186829.56/24641.42	eprover: CPU time limit exceeded, terminating
186829.56/24641.42	% SZS status Ended for HL411659+4.p
186836.42/24642.29	% SZS status Started for HL411659+5.p
186836.42/24642.29	% SZS status GaveUp for HL411659+5.p
186836.42/24642.29	eprover: CPU time limit exceeded, terminating
186836.42/24642.29	% SZS status Ended for HL411659+5.p
186840.06/24642.79	% SZS status Started for HL411661+4.p
186840.06/24642.79	% SZS status GaveUp for HL411661+4.p
186840.06/24642.79	eprover: CPU time limit exceeded, terminating
186840.06/24642.79	% SZS status Ended for HL411661+4.p
186841.81/24642.99	% SZS status Started for HL411661+5.p
186841.81/24642.99	% SZS status GaveUp for HL411661+5.p
186841.81/24642.99	eprover: CPU time limit exceeded, terminating
186841.81/24642.99	% SZS status Ended for HL411661+5.p
186843.97/24643.25	% SZS status Started for HL411662+4.p
186843.97/24643.25	% SZS status GaveUp for HL411662+4.p
186843.97/24643.25	eprover: CPU time limit exceeded, terminating
186843.97/24643.25	% SZS status Ended for HL411662+4.p
186845.94/24643.59	% SZS status Started for HL411662+5.p
186845.94/24643.59	% SZS status GaveUp for HL411662+5.p
186845.94/24643.59	eprover: CPU time limit exceeded, terminating
186845.94/24643.59	% SZS status Ended for HL411662+5.p
186847.95/24643.75	% SZS status Started for HL411663+4.p
186847.95/24643.75	% SZS status GaveUp for HL411663+4.p
186847.95/24643.75	eprover: CPU time limit exceeded, terminating
186847.95/24643.75	% SZS status Ended for HL411663+4.p
186850.77/24644.12	% SZS status Started for HL411663+5.p
186850.77/24644.12	% SZS status GaveUp for HL411663+5.p
186850.77/24644.12	eprover: CPU time limit exceeded, terminating
186850.77/24644.12	% SZS status Ended for HL411663+5.p
186853.64/24644.45	% SZS status Started for HL411664+4.p
186853.64/24644.45	% SZS status GaveUp for HL411664+4.p
186853.64/24644.45	eprover: CPU time limit exceeded, terminating
186853.64/24644.45	% SZS status Ended for HL411664+4.p
186860.50/24645.33	% SZS status Started for HL411664+5.p
186860.50/24645.33	% SZS status GaveUp for HL411664+5.p
186860.50/24645.33	eprover: CPU time limit exceeded, terminating
186860.50/24645.33	% SZS status Ended for HL411664+5.p
186865.12/24645.90	% SZS status Started for HL411665+4.p
186865.12/24645.90	% SZS status GaveUp for HL411665+4.p
186865.12/24645.90	eprover: CPU time limit exceeded, terminating
186865.12/24645.90	% SZS status Ended for HL411665+4.p
186866.14/24646.02	% SZS status Started for HL411665+5.p
186866.14/24646.02	% SZS status GaveUp for HL411665+5.p
186866.14/24646.02	eprover: CPU time limit exceeded, terminating
186866.14/24646.02	% SZS status Ended for HL411665+5.p
186867.77/24646.29	% SZS status Started for HL411666+4.p
186867.77/24646.29	% SZS status GaveUp for HL411666+4.p
186867.77/24646.29	eprover: CPU time limit exceeded, terminating
186867.77/24646.29	% SZS status Ended for HL411666+4.p
186870.59/24646.62	% SZS status Started for HL411666+5.p
186870.59/24646.62	% SZS status GaveUp for HL411666+5.p
186870.59/24646.62	eprover: CPU time limit exceeded, terminating
186870.59/24646.62	% SZS status Ended for HL411666+5.p
186871.77/24646.78	% SZS status Started for HL411667+4.p
186871.77/24646.78	% SZS status GaveUp for HL411667+4.p
186871.77/24646.78	eprover: CPU time limit exceeded, terminating
186871.77/24646.78	% SZS status Ended for HL411667+4.p
186875.30/24647.24	% SZS status Started for HL411667+5.p
186875.30/24647.24	% SZS status GaveUp for HL411667+5.p
186875.30/24647.24	eprover: CPU time limit exceeded, terminating
186875.30/24647.24	% SZS status Ended for HL411667+5.p
186877.39/24647.48	% SZS status Started for HL411668+4.p
186877.39/24647.48	% SZS status GaveUp for HL411668+4.p
186877.39/24647.48	eprover: CPU time limit exceeded, terminating
186877.39/24647.48	% SZS status Ended for HL411668+4.p
186884.58/24648.40	% SZS status Started for HL411668+5.p
186884.58/24648.40	% SZS status GaveUp for HL411668+5.p
186884.58/24648.40	eprover: CPU time limit exceeded, terminating
186884.58/24648.40	% SZS status Ended for HL411668+5.p
186889.11/24648.93	% SZS status Started for HL411669+4.p
186889.11/24648.93	% SZS status GaveUp for HL411669+4.p
186889.11/24648.93	eprover: CPU time limit exceeded, terminating
186889.11/24648.93	% SZS status Ended for HL411669+4.p
186890.12/24649.06	% SZS status Started for HL411669+5.p
186890.12/24649.06	% SZS status GaveUp for HL411669+5.p
186890.12/24649.06	eprover: CPU time limit exceeded, terminating
186890.12/24649.06	% SZS status Ended for HL411669+5.p
186892.36/24649.32	% SZS status Started for HL411670+4.p
186892.36/24649.32	% SZS status GaveUp for HL411670+4.p
186892.36/24649.32	eprover: CPU time limit exceeded, terminating
186892.36/24649.32	% SZS status Ended for HL411670+4.p
186894.48/24649.65	% SZS status Started for HL411670+5.p
186894.48/24649.65	% SZS status GaveUp for HL411670+5.p
186894.48/24649.65	eprover: CPU time limit exceeded, terminating
186894.48/24649.65	% SZS status Ended for HL411670+5.p
186896.44/24649.82	% SZS status Started for HL411671+4.p
186896.44/24649.82	% SZS status GaveUp for HL411671+4.p
186896.44/24649.82	eprover: CPU time limit exceeded, terminating
186896.44/24649.82	% SZS status Ended for HL411671+4.p
186899.25/24650.27	% SZS status Started for HL411671+5.p
186899.25/24650.27	% SZS status GaveUp for HL411671+5.p
186899.25/24650.27	eprover: CPU time limit exceeded, terminating
186899.25/24650.27	% SZS status Ended for HL411671+5.p
186901.73/24650.59	% SZS status Started for HL411672+4.p
186901.73/24650.59	% SZS status GaveUp for HL411672+4.p
186901.73/24650.59	eprover: CPU time limit exceeded, terminating
186901.73/24650.59	% SZS status Ended for HL411672+4.p
186909.09/24651.43	% SZS status Started for HL411672+5.p
186909.09/24651.43	% SZS status GaveUp for HL411672+5.p
186909.09/24651.43	eprover: CPU time limit exceeded, terminating
186909.09/24651.43	% SZS status Ended for HL411672+5.p
186913.48/24651.96	% SZS status Started for HL411675+4.p
186913.48/24651.96	% SZS status GaveUp for HL411675+4.p
186913.48/24651.96	eprover: CPU time limit exceeded, terminating
186913.48/24651.96	% SZS status Ended for HL411675+4.p
186913.98/24652.10	% SZS status Started for HL411675+5.p
186913.98/24652.10	% SZS status GaveUp for HL411675+5.p
186913.98/24652.10	eprover: CPU time limit exceeded, terminating
186913.98/24652.10	% SZS status Ended for HL411675+5.p
186916.53/24652.35	% SZS status Started for HL411676+4.p
186916.53/24652.35	% SZS status GaveUp for HL411676+4.p
186916.53/24652.35	eprover: CPU time limit exceeded, terminating
186916.53/24652.35	% SZS status Ended for HL411676+4.p
186918.62/24652.68	% SZS status Started for HL411676+5.p
186918.62/24652.68	% SZS status GaveUp for HL411676+5.p
186918.62/24652.68	eprover: CPU time limit exceeded, terminating
186918.62/24652.68	% SZS status Ended for HL411676+5.p
186919.56/24652.85	% SZS status Started for HL411677+4.p
186919.56/24652.85	% SZS status GaveUp for HL411677+4.p
186919.56/24652.85	eprover: CPU time limit exceeded, terminating
186919.56/24652.85	% SZS status Ended for HL411677+4.p
186924.86/24653.40	% SZS status Started for HL411677+5.p
186924.86/24653.40	% SZS status GaveUp for HL411677+5.p
186924.86/24653.40	eprover: CPU time limit exceeded, terminating
186924.86/24653.40	% SZS status Ended for HL411677+5.p
186926.34/24653.62	% SZS status Started for HL411678+4.p
186926.34/24653.62	% SZS status GaveUp for HL411678+4.p
186926.34/24653.62	eprover: CPU time limit exceeded, terminating
186926.34/24653.62	% SZS status Ended for HL411678+4.p
186933.08/24654.46	% SZS status Started for HL411678+5.p
186933.08/24654.46	% SZS status GaveUp for HL411678+5.p
186933.08/24654.46	eprover: CPU time limit exceeded, terminating
186933.08/24654.46	% SZS status Ended for HL411678+5.p
186936.56/24654.99	% SZS status Started for HL411679+4.p
186936.56/24654.99	% SZS status GaveUp for HL411679+4.p
186936.56/24654.99	eprover: CPU time limit exceeded, terminating
186936.56/24654.99	% SZS status Ended for HL411679+4.p
186938.64/24655.13	% SZS status Started for HL411679+5.p
186938.64/24655.13	% SZS status GaveUp for HL411679+5.p
186938.64/24655.13	eprover: CPU time limit exceeded, terminating
186938.64/24655.13	% SZS status Ended for HL411679+5.p
186940.31/24655.38	% SZS status Started for HL411681+4.p
186940.31/24655.38	% SZS status GaveUp for HL411681+4.p
186940.31/24655.38	eprover: CPU time limit exceeded, terminating
186940.31/24655.38	% SZS status Ended for HL411681+4.p
186943.20/24655.72	% SZS status Started for HL411681+5.p
186943.20/24655.72	% SZS status GaveUp for HL411681+5.p
186943.20/24655.72	eprover: CPU time limit exceeded, terminating
186943.20/24655.72	% SZS status Ended for HL411681+5.p
186945.36/24656.03	% SZS status Started for HL411682+4.p
186945.36/24656.03	% SZS status GaveUp for HL411682+4.p
186945.36/24656.03	eprover: CPU time limit exceeded, terminating
186945.36/24656.03	% SZS status Ended for HL411682+4.p
186949.00/24656.43	% SZS status Started for HL411682+5.p
186949.00/24656.43	% SZS status GaveUp for HL411682+5.p
186949.00/24656.43	eprover: CPU time limit exceeded, terminating
186949.00/24656.43	% SZS status Ended for HL411682+5.p
186950.52/24656.65	% SZS status Started for HL411683+4.p
186950.52/24656.65	% SZS status GaveUp for HL411683+4.p
186950.52/24656.65	eprover: CPU time limit exceeded, terminating
186950.52/24656.65	% SZS status Ended for HL411683+4.p
186956.83/24657.49	% SZS status Started for HL411683+5.p
186956.83/24657.49	% SZS status GaveUp for HL411683+5.p
186956.83/24657.49	eprover: CPU time limit exceeded, terminating
186956.83/24657.49	% SZS status Ended for HL411683+5.p
186960.34/24658.02	% SZS status Started for HL411684+4.p
186960.34/24658.02	% SZS status GaveUp for HL411684+4.p
186960.34/24658.02	eprover: CPU time limit exceeded, terminating
186960.34/24658.02	% SZS status Ended for HL411684+4.p
186964.05/24658.17	% SZS status Started for HL411684+5.p
186964.05/24658.17	% SZS status GaveUp for HL411684+5.p
186964.05/24658.17	eprover: CPU time limit exceeded, terminating
186964.05/24658.17	% SZS status Ended for HL411684+5.p
186965.80/24658.41	% SZS status Started for HL411685+4.p
186965.80/24658.41	% SZS status GaveUp for HL411685+4.p
186965.80/24658.41	eprover: CPU time limit exceeded, terminating
186965.80/24658.41	% SZS status Ended for HL411685+4.p
186969.69/24658.86	% SZS status Started for HL411685+5.p
186969.69/24658.86	% SZS status GaveUp for HL411685+5.p
186969.69/24658.86	eprover: CPU time limit exceeded, terminating
186969.69/24658.86	% SZS status Ended for HL411685+5.p
186971.38/24659.06	% SZS status Started for HL411686+4.p
186971.38/24659.06	% SZS status GaveUp for HL411686+4.p
186971.38/24659.06	eprover: CPU time limit exceeded, terminating
186971.38/24659.06	% SZS status Ended for HL411686+4.p
186974.73/24659.46	% SZS status Started for HL411686+5.p
186974.73/24659.46	% SZS status GaveUp for HL411686+5.p
186974.73/24659.46	eprover: CPU time limit exceeded, terminating
186974.73/24659.46	% SZS status Ended for HL411686+5.p
186976.16/24659.68	% SZS status Started for HL411687+4.p
186976.16/24659.68	% SZS status GaveUp for HL411687+4.p
186976.16/24659.68	eprover: CPU time limit exceeded, terminating
186976.16/24659.68	% SZS status Ended for HL411687+4.p
186983.22/24660.53	% SZS status Started for HL411687+5.p
186983.22/24660.53	% SZS status GaveUp for HL411687+5.p
186983.22/24660.53	eprover: CPU time limit exceeded, terminating
186983.22/24660.53	% SZS status Ended for HL411687+5.p
186987.03/24661.05	% SZS status Started for HL411688+4.p
186987.03/24661.05	% SZS status GaveUp for HL411688+4.p
186987.03/24661.05	eprover: CPU time limit exceeded, terminating
186987.03/24661.05	% SZS status Ended for HL411688+4.p
186988.52/24661.20	% SZS status Started for HL411688+5.p
186988.52/24661.20	% SZS status GaveUp for HL411688+5.p
186988.52/24661.20	eprover: CPU time limit exceeded, terminating
186988.52/24661.20	% SZS status Ended for HL411688+5.p
186990.44/24661.51	% SZS status Started for HL411689+4.p
186990.44/24661.51	% SZS status GaveUp for HL411689+4.p
186990.44/24661.51	eprover: CPU time limit exceeded, terminating
186990.44/24661.51	% SZS status Ended for HL411689+4.p
186993.34/24661.89	% SZS status Started for HL411689+5.p
186993.34/24661.89	% SZS status GaveUp for HL411689+5.p
186993.34/24661.89	eprover: CPU time limit exceeded, terminating
186993.34/24661.89	% SZS status Ended for HL411689+5.p
186994.89/24662.09	% SZS status Started for HL411690+4.p
186994.89/24662.09	% SZS status GaveUp for HL411690+4.p
186994.89/24662.09	eprover: CPU time limit exceeded, terminating
186994.89/24662.09	% SZS status Ended for HL411690+4.p
186998.16/24662.49	% SZS status Started for HL411690+5.p
186998.16/24662.49	% SZS status GaveUp for HL411690+5.p
186998.16/24662.49	eprover: CPU time limit exceeded, terminating
186998.16/24662.49	% SZS status Ended for HL411690+5.p
187000.89/24662.77	% SZS status Started for HL411692+4.p
187000.89/24662.77	% SZS status GaveUp for HL411692+4.p
187000.89/24662.77	eprover: CPU time limit exceeded, terminating
187000.89/24662.77	% SZS status Ended for HL411692+4.p
187007.36/24663.56	% SZS status Started for HL411692+5.p
187007.36/24663.56	% SZS status GaveUp for HL411692+5.p
187007.36/24663.56	eprover: CPU time limit exceeded, terminating
187007.36/24663.56	% SZS status Ended for HL411692+5.p
187011.61/24664.16	% SZS status Started for HL411693+4.p
187011.61/24664.16	% SZS status GaveUp for HL411693+4.p
187011.61/24664.16	eprover: CPU time limit exceeded, terminating
187011.61/24664.16	% SZS status Ended for HL411693+4.p
187012.58/24664.23	% SZS status Started for HL411693+5.p
187012.58/24664.23	% SZS status GaveUp for HL411693+5.p
187012.58/24664.23	eprover: CPU time limit exceeded, terminating
187012.58/24664.23	% SZS status Ended for HL411693+5.p
187014.88/24664.54	% SZS status Started for HL411694+4.p
187014.88/24664.54	% SZS status GaveUp for HL411694+4.p
187014.88/24664.54	eprover: CPU time limit exceeded, terminating
187014.88/24664.54	% SZS status Ended for HL411694+4.p
187017.70/24664.93	% SZS status Started for HL411694+5.p
187017.70/24664.93	% SZS status GaveUp for HL411694+5.p
187017.70/24664.93	eprover: CPU time limit exceeded, terminating
187017.70/24664.93	% SZS status Ended for HL411694+5.p
187019.77/24665.13	% SZS status Started for HL411695+4.p
187019.77/24665.13	% SZS status GaveUp for HL411695+4.p
187019.77/24665.13	eprover: CPU time limit exceeded, terminating
187019.77/24665.13	% SZS status Ended for HL411695+4.p
187022.64/24665.53	% SZS status Started for HL411695+5.p
187022.64/24665.53	% SZS status GaveUp for HL411695+5.p
187022.64/24665.53	eprover: CPU time limit exceeded, terminating
187022.64/24665.53	% SZS status Ended for HL411695+5.p
187024.20/24665.81	% SZS status Started for HL411697+4.p
187024.20/24665.81	% SZS status GaveUp for HL411697+4.p
187024.20/24665.81	eprover: CPU time limit exceeded, terminating
187024.20/24665.81	% SZS status Ended for HL411697+4.p
187031.12/24666.60	% SZS status Started for HL411697+5.p
187031.12/24666.60	% SZS status GaveUp for HL411697+5.p
187031.12/24666.60	eprover: CPU time limit exceeded, terminating
187031.12/24666.60	% SZS status Ended for HL411697+5.p
187035.91/24667.19	% SZS status Started for HL411698+4.p
187035.91/24667.19	% SZS status GaveUp for HL411698+4.p
187035.91/24667.19	eprover: CPU time limit exceeded, terminating
187035.91/24667.19	% SZS status Ended for HL411698+4.p
187036.86/24667.29	% SZS status Started for HL411698+5.p
187036.86/24667.29	% SZS status GaveUp for HL411698+5.p
187036.86/24667.29	eprover: CPU time limit exceeded, terminating
187036.86/24667.29	% SZS status Ended for HL411698+5.p
187038.34/24667.58	% SZS status Started for HL411699+4.p
187038.34/24667.58	% SZS status GaveUp for HL411699+4.p
187038.34/24667.58	eprover: CPU time limit exceeded, terminating
187038.34/24667.58	% SZS status Ended for HL411699+4.p
187042.53/24668.06	% SZS status Started for HL411699+5.p
187042.53/24668.06	% SZS status GaveUp for HL411699+5.p
187042.53/24668.06	eprover: CPU time limit exceeded, terminating
187042.53/24668.06	% SZS status Ended for HL411699+5.p
187043.59/24668.15	% SZS status Started for HL411700+4.p
187043.59/24668.15	% SZS status GaveUp for HL411700+4.p
187043.59/24668.15	eprover: CPU time limit exceeded, terminating
187043.59/24668.15	% SZS status Ended for HL411700+4.p
187046.28/24668.56	% SZS status Started for HL411700+5.p
187046.28/24668.56	% SZS status GaveUp for HL411700+5.p
187046.28/24668.56	eprover: CPU time limit exceeded, terminating
187046.28/24668.56	% SZS status Ended for HL411700+5.p
187049.12/24668.85	% SZS status Started for HL411702+4.p
187049.12/24668.85	% SZS status GaveUp for HL411702+4.p
187049.12/24668.85	eprover: CPU time limit exceeded, terminating
187049.12/24668.85	% SZS status Ended for HL411702+4.p
187055.67/24669.63	% SZS status Started for HL411702+5.p
187055.67/24669.63	% SZS status GaveUp for HL411702+5.p
187055.67/24669.63	eprover: CPU time limit exceeded, terminating
187055.67/24669.63	% SZS status Ended for HL411702+5.p
187060.30/24670.22	% SZS status Started for HL411705+4.p
187060.30/24670.22	% SZS status GaveUp for HL411705+4.p
187060.30/24670.22	eprover: CPU time limit exceeded, terminating
187060.30/24670.22	% SZS status Ended for HL411705+4.p
187060.56/24670.32	% SZS status Started for HL411705+5.p
187060.56/24670.32	% SZS status GaveUp for HL411705+5.p
187060.56/24670.32	eprover: CPU time limit exceeded, terminating
187060.56/24670.32	% SZS status Ended for HL411705+5.p
187063.44/24670.62	% SZS status Started for HL411706+4.p
187063.44/24670.62	% SZS status GaveUp for HL411706+4.p
187063.44/24670.62	eprover: CPU time limit exceeded, terminating
187063.44/24670.62	% SZS status Ended for HL411706+4.p
187067.33/24671.11	% SZS status Started for HL411706+5.p
187067.33/24671.11	% SZS status GaveUp for HL411706+5.p
187067.33/24671.11	eprover: CPU time limit exceeded, terminating
187067.33/24671.11	% SZS status Ended for HL411706+5.p
187067.58/24671.19	% SZS status Started for HL411707+4.p
187067.58/24671.19	% SZS status GaveUp for HL411707+4.p
187067.58/24671.19	eprover: CPU time limit exceeded, terminating
187067.58/24671.19	% SZS status Ended for HL411707+4.p
187070.08/24671.61	% SZS status Started for HL411707+5.p
187070.08/24671.61	% SZS status GaveUp for HL411707+5.p
187070.08/24671.61	eprover: CPU time limit exceeded, terminating
187070.08/24671.61	% SZS status Ended for HL411707+5.p
187075.08/24671.91	% SZS status Started for HL411708+4.p
187075.08/24671.91	% SZS status GaveUp for HL411708+4.p
187075.08/24671.91	eprover: CPU time limit exceeded, terminating
187075.08/24671.91	% SZS status Ended for HL411708+4.p
187081.61/24672.76	% SZS status Started for HL411708+5.p
187081.61/24672.76	% SZS status GaveUp for HL411708+5.p
187081.61/24672.76	eprover: CPU time limit exceeded, terminating
187081.61/24672.76	% SZS status Ended for HL411708+5.p
187085.73/24673.25	% SZS status Started for HL411709+4.p
187085.73/24673.25	% SZS status GaveUp for HL411709+4.p
187085.73/24673.25	eprover: CPU time limit exceeded, terminating
187085.73/24673.25	% SZS status Ended for HL411709+4.p
187086.22/24673.35	% SZS status Started for HL411709+5.p
187086.22/24673.35	% SZS status GaveUp for HL411709+5.p
187086.22/24673.35	eprover: CPU time limit exceeded, terminating
187086.22/24673.35	% SZS status Ended for HL411709+5.p
187088.62/24673.64	% SZS status Started for HL411711+4.p
187088.62/24673.64	% SZS status GaveUp for HL411711+4.p
187088.62/24673.64	eprover: CPU time limit exceeded, terminating
187088.62/24673.64	% SZS status Ended for HL411711+4.p
187092.95/24674.14	% SZS status Started for HL411711+5.p
187092.95/24674.14	% SZS status GaveUp for HL411711+5.p
187092.95/24674.14	eprover: CPU time limit exceeded, terminating
187092.95/24674.14	% SZS status Ended for HL411711+5.p
187094.20/24674.29	% SZS status Started for HL411712+4.p
187094.20/24674.29	% SZS status GaveUp for HL411712+4.p
187094.20/24674.29	eprover: CPU time limit exceeded, terminating
187094.20/24674.29	% SZS status Ended for HL411712+4.p
187097.17/24674.65	% SZS status Started for HL411712+5.p
187097.17/24674.65	% SZS status GaveUp for HL411712+5.p
187097.17/24674.65	eprover: CPU time limit exceeded, terminating
187097.17/24674.65	% SZS status Ended for HL411712+5.p
187099.28/24674.94	% SZS status Started for HL411713+4.p
187099.28/24674.94	% SZS status GaveUp for HL411713+4.p
187099.28/24674.94	eprover: CPU time limit exceeded, terminating
187099.28/24674.94	% SZS status Ended for HL411713+4.p
187106.36/24675.80	% SZS status Started for HL411713+5.p
187106.36/24675.80	% SZS status GaveUp for HL411713+5.p
187106.36/24675.80	eprover: CPU time limit exceeded, terminating
187106.36/24675.80	% SZS status Ended for HL411713+5.p
187109.86/24676.28	% SZS status Started for HL411715+4.p
187109.86/24676.28	% SZS status GaveUp for HL411715+4.p
187109.86/24676.28	eprover: CPU time limit exceeded, terminating
187109.86/24676.28	% SZS status Ended for HL411715+4.p
187110.98/24676.43	% SZS status Started for HL411715+5.p
187110.98/24676.43	% SZS status GaveUp for HL411715+5.p
187110.98/24676.43	eprover: CPU time limit exceeded, terminating
187110.98/24676.43	% SZS status Ended for HL411715+5.p
187112.50/24676.68	% SZS status Started for HL411718+4.p
187112.50/24676.68	% SZS status GaveUp for HL411718+4.p
187112.50/24676.68	eprover: CPU time limit exceeded, terminating
187112.50/24676.68	% SZS status Ended for HL411718+4.p
187117.20/24677.17	% SZS status Started for HL411718+5.p
187117.20/24677.17	% SZS status GaveUp for HL411718+5.p
187117.20/24677.17	eprover: CPU time limit exceeded, terminating
187117.20/24677.17	% SZS status Ended for HL411718+5.p
187119.44/24677.45	% SZS status Started for HL411719+4.p
187119.44/24677.45	% SZS status GaveUp for HL411719+4.p
187119.44/24677.45	eprover: CPU time limit exceeded, terminating
187119.44/24677.45	% SZS status Ended for HL411719+4.p
187120.81/24677.68	% SZS status Started for HL411719+5.p
187120.81/24677.68	% SZS status GaveUp for HL411719+5.p
187120.81/24677.68	eprover: CPU time limit exceeded, terminating
187120.81/24677.68	% SZS status Ended for HL411719+5.p
187123.61/24677.97	% SZS status Started for HL411721+4.p
187123.61/24677.97	% SZS status GaveUp for HL411721+4.p
187123.61/24677.97	eprover: CPU time limit exceeded, terminating
187123.61/24677.97	% SZS status Ended for HL411721+4.p
187130.14/24678.83	% SZS status Started for HL411721+5.p
187130.14/24678.83	% SZS status GaveUp for HL411721+5.p
187130.14/24678.83	eprover: CPU time limit exceeded, terminating
187130.14/24678.83	% SZS status Ended for HL411721+5.p
187134.11/24679.30	% SZS status Started for HL411723+4.p
187134.11/24679.30	% SZS status GaveUp for HL411723+4.p
187134.11/24679.30	eprover: CPU time limit exceeded, terminating
187134.11/24679.30	% SZS status Ended for HL411723+4.p
187135.03/24679.46	% SZS status Started for HL411723+5.p
187135.03/24679.46	% SZS status GaveUp for HL411723+5.p
187135.03/24679.46	eprover: CPU time limit exceeded, terminating
187135.03/24679.46	% SZS status Ended for HL411723+5.p
187136.75/24679.71	% SZS status Started for HL411725+4.p
187136.75/24679.71	% SZS status GaveUp for HL411725+4.p
187136.75/24679.71	eprover: CPU time limit exceeded, terminating
187136.75/24679.71	% SZS status Ended for HL411725+4.p
187144.56/24680.33	% SZS status Started for HL411725+5.p
187144.56/24680.33	% SZS status GaveUp for HL411725+5.p
187144.56/24680.33	eprover: CPU time limit exceeded, terminating
187144.56/24680.33	% SZS status Ended for HL411725+5.p
187145.67/24680.48	% SZS status Started for HL411726+4.p
187145.67/24680.48	% SZS status GaveUp for HL411726+4.p
187145.67/24680.48	eprover: CPU time limit exceeded, terminating
187145.67/24680.48	% SZS status Ended for HL411726+4.p
187146.83/24680.70	% SZS status Started for HL411726+5.p
187146.83/24680.70	% SZS status GaveUp for HL411726+5.p
187146.83/24680.70	eprover: CPU time limit exceeded, terminating
187146.83/24680.70	% SZS status Ended for HL411726+5.p
187149.64/24681.01	% SZS status Started for HL411727+4.p
187149.64/24681.01	% SZS status GaveUp for HL411727+4.p
187149.64/24681.01	eprover: CPU time limit exceeded, terminating
187149.64/24681.01	% SZS status Ended for HL411727+4.p
187156.66/24681.87	% SZS status Started for HL411727+5.p
187156.66/24681.87	% SZS status GaveUp for HL411727+5.p
187156.66/24681.87	eprover: CPU time limit exceeded, terminating
187156.66/24681.87	% SZS status Ended for HL411727+5.p
187160.28/24682.33	% SZS status Started for HL411729+4.p
187160.28/24682.33	% SZS status GaveUp for HL411729+4.p
187160.28/24682.33	eprover: CPU time limit exceeded, terminating
187160.28/24682.33	% SZS status Ended for HL411729+4.p
187161.25/24682.50	% SZS status Started for HL411729+5.p
187161.25/24682.50	% SZS status GaveUp for HL411729+5.p
187161.25/24682.50	eprover: CPU time limit exceeded, terminating
187161.25/24682.50	% SZS status Ended for HL411729+5.p
187164.44/24682.83	% SZS status Started for HL411732+4.p
187164.44/24682.83	% SZS status GaveUp for HL411732+4.p
187164.44/24682.83	eprover: CPU time limit exceeded, terminating
187164.44/24682.83	% SZS status Ended for HL411732+4.p
187168.78/24683.39	% SZS status Started for HL411732+5.p
187168.78/24683.39	% SZS status GaveUp for HL411732+5.p
187168.78/24683.39	eprover: CPU time limit exceeded, terminating
187168.78/24683.39	% SZS status Ended for HL411732+5.p
187169.39/24683.50	% SZS status Started for HL411733+4.p
187169.39/24683.50	% SZS status GaveUp for HL411733+4.p
187169.39/24683.50	eprover: CPU time limit exceeded, terminating
187169.39/24683.50	% SZS status Ended for HL411733+4.p
187171.75/24683.73	% SZS status Started for HL411733+5.p
187171.75/24683.73	% SZS status GaveUp for HL411733+5.p
187171.75/24683.73	eprover: CPU time limit exceeded, terminating
187171.75/24683.73	% SZS status Ended for HL411733+5.p
187173.84/24684.04	% SZS status Started for HL411734+4.p
187173.84/24684.04	% SZS status GaveUp for HL411734+4.p
187173.84/24684.04	eprover: CPU time limit exceeded, terminating
187173.84/24684.04	% SZS status Ended for HL411734+4.p
187180.59/24684.90	% SZS status Started for HL411734+5.p
187180.59/24684.90	% SZS status GaveUp for HL411734+5.p
187180.59/24684.90	eprover: CPU time limit exceeded, terminating
187180.59/24684.90	% SZS status Ended for HL411734+5.p
187184.19/24685.36	% SZS status Started for HL411735+4.p
187184.19/24685.36	% SZS status GaveUp for HL411735+4.p
187184.19/24685.36	eprover: CPU time limit exceeded, terminating
187184.19/24685.36	% SZS status Ended for HL411735+4.p
187185.86/24685.54	% SZS status Started for HL411735+5.p
187185.86/24685.54	% SZS status GaveUp for HL411735+5.p
187185.86/24685.54	eprover: CPU time limit exceeded, terminating
187185.86/24685.54	% SZS status Ended for HL411735+5.p
187189.31/24685.95	% SZS status Started for HL411736+4.p
187189.31/24685.95	% SZS status GaveUp for HL411736+4.p
187189.31/24685.95	eprover: CPU time limit exceeded, terminating
187189.31/24685.95	% SZS status Ended for HL411736+4.p
187192.31/24686.42	% SZS status Started for HL411736+5.p
187192.31/24686.42	% SZS status GaveUp for HL411736+5.p
187192.31/24686.42	eprover: CPU time limit exceeded, terminating
187192.31/24686.42	% SZS status Ended for HL411736+5.p
187193.16/24686.53	% SZS status Started for HL411737+4.p
187193.16/24686.53	% SZS status GaveUp for HL411737+4.p
187193.16/24686.53	eprover: CPU time limit exceeded, terminating
187193.16/24686.53	% SZS status Ended for HL411737+4.p
187195.59/24686.76	% SZS status Started for HL411737+5.p
187195.59/24686.76	% SZS status GaveUp for HL411737+5.p
187195.59/24686.76	eprover: CPU time limit exceeded, terminating
187195.59/24686.76	% SZS status Ended for HL411737+5.p
187197.25/24687.07	% SZS status Started for HL411738+4.p
187197.25/24687.07	% SZS status GaveUp for HL411738+4.p
187197.25/24687.07	eprover: CPU time limit exceeded, terminating
187197.25/24687.07	% SZS status Ended for HL411738+4.p
187204.97/24687.98	% SZS status Started for HL411738+5.p
187204.97/24687.98	% SZS status GaveUp for HL411738+5.p
187204.97/24687.98	eprover: CPU time limit exceeded, terminating
187204.97/24687.98	% SZS status Ended for HL411738+5.p
187208.55/24688.41	% SZS status Started for HL411739+4.p
187208.55/24688.41	% SZS status GaveUp for HL411739+4.p
187208.55/24688.41	eprover: CPU time limit exceeded, terminating
187208.55/24688.41	% SZS status Ended for HL411739+4.p
187209.81/24688.57	% SZS status Started for HL411739+5.p
187209.81/24688.57	% SZS status GaveUp for HL411739+5.p
187209.81/24688.57	eprover: CPU time limit exceeded, terminating
187209.81/24688.57	% SZS status Ended for HL411739+5.p
187213.11/24688.98	% SZS status Started for HL411740+4.p
187213.11/24688.98	% SZS status GaveUp for HL411740+4.p
187213.11/24688.98	eprover: CPU time limit exceeded, terminating
187213.11/24688.98	% SZS status Ended for HL411740+4.p
187216.89/24689.46	% SZS status Started for HL411740+5.p
187216.89/24689.46	% SZS status GaveUp for HL411740+5.p
187216.89/24689.46	eprover: CPU time limit exceeded, terminating
187216.89/24689.46	% SZS status Ended for HL411740+5.p
187217.42/24689.56	% SZS status Started for HL411741+4.p
187217.42/24689.56	% SZS status GaveUp for HL411741+4.p
187217.42/24689.56	eprover: CPU time limit exceeded, terminating
187217.42/24689.56	% SZS status Ended for HL411741+4.p
187219.30/24689.80	% SZS status Started for HL411741+5.p
187219.30/24689.80	% SZS status GaveUp for HL411741+5.p
187219.30/24689.80	eprover: CPU time limit exceeded, terminating
187219.30/24689.80	% SZS status Ended for HL411741+5.p
187222.20/24690.13	% SZS status Started for HL411742+4.p
187222.20/24690.13	% SZS status GaveUp for HL411742+4.p
187222.20/24690.13	eprover: CPU time limit exceeded, terminating
187222.20/24690.13	% SZS status Ended for HL411742+4.p
187230.11/24691.15	% SZS status Started for HL411742+5.p
187230.11/24691.15	% SZS status GaveUp for HL411742+5.p
187230.11/24691.15	eprover: CPU time limit exceeded, terminating
187230.11/24691.15	% SZS status Ended for HL411742+5.p
187232.31/24691.44	% SZS status Started for HL411743+4.p
187232.31/24691.44	% SZS status GaveUp for HL411743+4.p
187232.31/24691.44	eprover: CPU time limit exceeded, terminating
187232.31/24691.44	% SZS status Ended for HL411743+4.p
187233.92/24691.60	% SZS status Started for HL411743+5.p
187233.92/24691.60	% SZS status GaveUp for HL411743+5.p
187233.92/24691.60	eprover: CPU time limit exceeded, terminating
187233.92/24691.60	% SZS status Ended for HL411743+5.p
187237.09/24692.01	% SZS status Started for HL411744+4.p
187237.09/24692.01	% SZS status GaveUp for HL411744+4.p
187237.09/24692.01	eprover: CPU time limit exceeded, terminating
187237.09/24692.01	% SZS status Ended for HL411744+4.p
187241.33/24692.50	% SZS status Started for HL411744+5.p
187241.33/24692.50	% SZS status GaveUp for HL411744+5.p
187241.33/24692.50	eprover: CPU time limit exceeded, terminating
187241.33/24692.50	% SZS status Ended for HL411744+5.p
187241.91/24692.59	% SZS status Started for HL411746+4.p
187241.91/24692.59	% SZS status GaveUp for HL411746+4.p
187241.91/24692.59	eprover: CPU time limit exceeded, terminating
187241.91/24692.59	% SZS status Ended for HL411746+4.p
187243.88/24692.84	% SZS status Started for HL411746+5.p
187243.88/24692.84	% SZS status GaveUp for HL411746+5.p
187243.88/24692.84	eprover: CPU time limit exceeded, terminating
187243.88/24692.84	% SZS status Ended for HL411746+5.p
187246.52/24693.25	% SZS status Started for HL411747+4.p
187246.52/24693.25	% SZS status GaveUp for HL411747+4.p
187246.52/24693.25	eprover: CPU time limit exceeded, terminating
187246.52/24693.25	% SZS status Ended for HL411747+4.p
187254.56/24694.19	% SZS status Started for HL411747+5.p
187254.56/24694.19	% SZS status GaveUp for HL411747+5.p
187254.56/24694.19	eprover: CPU time limit exceeded, terminating
187254.56/24694.19	% SZS status Ended for HL411747+5.p
187256.80/24694.47	% SZS status Started for HL411750+4.p
187256.80/24694.47	% SZS status GaveUp for HL411750+4.p
187256.80/24694.47	eprover: CPU time limit exceeded, terminating
187256.80/24694.47	% SZS status Ended for HL411750+4.p
187258.14/24694.64	% SZS status Started for HL411750+5.p
187258.14/24694.64	% SZS status GaveUp for HL411750+5.p
187258.14/24694.64	eprover: CPU time limit exceeded, terminating
187258.14/24694.64	% SZS status Ended for HL411750+5.p
187261.00/24695.05	% SZS status Started for HL411751+4.p
187261.00/24695.05	% SZS status GaveUp for HL411751+4.p
187261.00/24695.05	eprover: CPU time limit exceeded, terminating
187261.00/24695.05	% SZS status Ended for HL411751+4.p
187265.36/24695.53	% SZS status Started for HL411751+5.p
187265.36/24695.53	% SZS status GaveUp for HL411751+5.p
187265.36/24695.53	eprover: CPU time limit exceeded, terminating
187265.36/24695.53	% SZS status Ended for HL411751+5.p
187265.75/24695.62	% SZS status Started for HL411752+4.p
187265.75/24695.62	% SZS status GaveUp for HL411752+4.p
187265.75/24695.62	eprover: CPU time limit exceeded, terminating
187265.75/24695.62	% SZS status Ended for HL411752+4.p
187267.69/24695.87	% SZS status Started for HL411752+5.p
187267.69/24695.87	% SZS status GaveUp for HL411752+5.p
187267.69/24695.87	eprover: CPU time limit exceeded, terminating
187267.69/24695.87	% SZS status Ended for HL411752+5.p
187272.58/24696.43	% SZS status Started for HL411753+4.p
187272.58/24696.43	% SZS status GaveUp for HL411753+4.p
187272.58/24696.43	eprover: CPU time limit exceeded, terminating
187272.58/24696.43	% SZS status Ended for HL411753+4.p
187278.73/24697.22	% SZS status Started for HL411753+5.p
187278.73/24697.22	% SZS status GaveUp for HL411753+5.p
187278.73/24697.22	eprover: CPU time limit exceeded, terminating
187278.73/24697.22	% SZS status Ended for HL411753+5.p
187280.84/24697.50	% SZS status Started for HL411754+4.p
187280.84/24697.50	% SZS status GaveUp for HL411754+4.p
187280.84/24697.50	eprover: CPU time limit exceeded, terminating
187280.84/24697.50	% SZS status Ended for HL411754+4.p
187282.22/24697.67	% SZS status Started for HL411754+5.p
187282.22/24697.67	% SZS status GaveUp for HL411754+5.p
187282.22/24697.67	eprover: CPU time limit exceeded, terminating
187282.22/24697.67	% SZS status Ended for HL411754+5.p
187285.58/24698.08	% SZS status Started for HL411755+4.p
187285.58/24698.08	% SZS status GaveUp for HL411755+4.p
187285.58/24698.08	eprover: CPU time limit exceeded, terminating
187285.58/24698.08	% SZS status Ended for HL411755+4.p
187289.55/24698.56	% SZS status Started for HL411755+5.p
187289.55/24698.56	% SZS status GaveUp for HL411755+5.p
187289.55/24698.56	eprover: CPU time limit exceeded, terminating
187289.55/24698.56	% SZS status Ended for HL411755+5.p
187290.17/24698.65	% SZS status Started for HL411758+4.p
187290.17/24698.65	% SZS status GaveUp for HL411758+4.p
187290.17/24698.65	eprover: CPU time limit exceeded, terminating
187290.17/24698.65	% SZS status Ended for HL411758+4.p
187291.98/24699.00	% SZS status Started for HL411758+5.p
187291.98/24699.00	% SZS status GaveUp for HL411758+5.p
187291.98/24699.00	eprover: CPU time limit exceeded, terminating
187291.98/24699.00	% SZS status Ended for HL411758+5.p
187296.12/24699.47	% SZS status Started for HL411759+4.p
187296.12/24699.47	% SZS status GaveUp for HL411759+4.p
187296.12/24699.47	eprover: CPU time limit exceeded, terminating
187296.12/24699.47	% SZS status Ended for HL411759+4.p
187302.58/24700.25	% SZS status Started for HL411759+5.p
187302.58/24700.25	% SZS status GaveUp for HL411759+5.p
187302.58/24700.25	eprover: CPU time limit exceeded, terminating
187302.58/24700.25	% SZS status Ended for HL411759+5.p
187305.16/24700.53	% SZS status Started for HL411760+4.p
187305.16/24700.53	% SZS status GaveUp for HL411760+4.p
187305.16/24700.53	eprover: CPU time limit exceeded, terminating
187305.16/24700.53	% SZS status Ended for HL411760+4.p
187306.20/24700.71	% SZS status Started for HL411760+5.p
187306.20/24700.71	% SZS status GaveUp for HL411760+5.p
187306.20/24700.71	eprover: CPU time limit exceeded, terminating
187306.20/24700.71	% SZS status Ended for HL411760+5.p
187308.66/24701.12	% SZS status Started for HL411761+4.p
187308.66/24701.12	% SZS status GaveUp for HL411761+4.p
187308.66/24701.12	eprover: CPU time limit exceeded, terminating
187308.66/24701.12	% SZS status Ended for HL411761+4.p
187313.33/24701.60	% SZS status Started for HL411761+5.p
187313.33/24701.60	% SZS status GaveUp for HL411761+5.p
187313.33/24701.60	eprover: CPU time limit exceeded, terminating
187313.33/24701.60	% SZS status Ended for HL411761+5.p
187314.23/24701.69	% SZS status Started for HL411762+4.p
187314.23/24701.69	% SZS status GaveUp for HL411762+4.p
187314.23/24701.69	eprover: CPU time limit exceeded, terminating
187314.23/24701.69	% SZS status Ended for HL411762+4.p
187317.25/24702.06	% SZS status Started for HL411762+5.p
187317.25/24702.06	% SZS status GaveUp for HL411762+5.p
187317.25/24702.06	eprover: CPU time limit exceeded, terminating
187317.25/24702.06	% SZS status Ended for HL411762+5.p
187321.11/24702.53	% SZS status Started for HL411763+4.p
187321.11/24702.53	% SZS status GaveUp for HL411763+4.p
187321.11/24702.53	eprover: CPU time limit exceeded, terminating
187321.11/24702.53	% SZS status Ended for HL411763+4.p
187328.19/24703.44	% SZS status Started for HL411763+5.p
187328.19/24703.44	% SZS status GaveUp for HL411763+5.p
187328.19/24703.44	eprover: CPU time limit exceeded, terminating
187328.19/24703.44	% SZS status Ended for HL411763+5.p
187328.84/24703.57	% SZS status Started for HL411764+4.p
187328.84/24703.57	% SZS status GaveUp for HL411764+4.p
187328.84/24703.57	eprover: CPU time limit exceeded, terminating
187328.84/24703.57	% SZS status Ended for HL411764+4.p
187330.02/24703.74	% SZS status Started for HL411764+5.p
187330.02/24703.74	% SZS status GaveUp for HL411764+5.p
187330.02/24703.74	eprover: CPU time limit exceeded, terminating
187330.02/24703.74	% SZS status Ended for HL411764+5.p
187333.80/24704.15	% SZS status Started for HL411765+4.p
187333.80/24704.15	% SZS status GaveUp for HL411765+4.p
187333.80/24704.15	eprover: CPU time limit exceeded, terminating
187333.80/24704.15	% SZS status Ended for HL411765+4.p
187336.95/24704.63	% SZS status Started for HL411765+5.p
187336.95/24704.63	% SZS status GaveUp for HL411765+5.p
187336.95/24704.63	eprover: CPU time limit exceeded, terminating
187336.95/24704.63	% SZS status Ended for HL411765+5.p
187338.41/24704.72	% SZS status Started for HL411767+4.p
187338.41/24704.72	% SZS status GaveUp for HL411767+4.p
187338.41/24704.72	eprover: CPU time limit exceeded, terminating
187338.41/24704.72	% SZS status Ended for HL411767+4.p
187340.78/24705.09	% SZS status Started for HL411767+5.p
187340.78/24705.09	% SZS status GaveUp for HL411767+5.p
187340.78/24705.09	eprover: CPU time limit exceeded, terminating
187340.78/24705.09	% SZS status Ended for HL411767+5.p
187345.73/24705.64	% SZS status Started for HL411768+4.p
187345.73/24705.64	% SZS status GaveUp for HL411768+4.p
187345.73/24705.64	eprover: CPU time limit exceeded, terminating
187345.73/24705.64	% SZS status Ended for HL411768+4.p
187351.89/24706.47	% SZS status Started for HL411768+5.p
187351.89/24706.47	% SZS status GaveUp for HL411768+5.p
187351.89/24706.47	eprover: CPU time limit exceeded, terminating
187351.89/24706.47	% SZS status Ended for HL411768+5.p
187352.73/24706.60	% SZS status Started for HL411769+4.p
187352.73/24706.60	% SZS status GaveUp for HL411769+4.p
187352.73/24706.60	eprover: CPU time limit exceeded, terminating
187352.73/24706.60	% SZS status Ended for HL411769+4.p
187356.30/24706.77	% SZS status Started for HL411769+5.p
187356.30/24706.77	% SZS status GaveUp for HL411769+5.p
187356.30/24706.77	eprover: CPU time limit exceeded, terminating
187356.30/24706.77	% SZS status Ended for HL411769+5.p
187359.89/24707.18	% SZS status Started for HL411770+4.p
187359.89/24707.18	% SZS status GaveUp for HL411770+4.p
187359.89/24707.18	eprover: CPU time limit exceeded, terminating
187359.89/24707.18	% SZS status Ended for HL411770+4.p
187364.02/24707.66	% SZS status Started for HL411770+5.p
187364.02/24707.66	% SZS status GaveUp for HL411770+5.p
187364.02/24707.66	eprover: CPU time limit exceeded, terminating
187364.02/24707.66	% SZS status Ended for HL411770+5.p
187364.64/24707.75	% SZS status Started for HL411772+4.p
187364.64/24707.75	% SZS status GaveUp for HL411772+4.p
187364.64/24707.75	eprover: CPU time limit exceeded, terminating
187364.64/24707.75	% SZS status Ended for HL411772+4.p
187366.91/24708.12	% SZS status Started for HL411772+5.p
187366.91/24708.12	% SZS status GaveUp for HL411772+5.p
187366.91/24708.12	eprover: CPU time limit exceeded, terminating
187366.91/24708.12	% SZS status Ended for HL411772+5.p
187373.28/24708.81	% SZS status Started for HL411773+4.p
187373.28/24708.81	% SZS status GaveUp for HL411773+4.p
187373.28/24708.81	eprover: CPU time limit exceeded, terminating
187373.28/24708.81	% SZS status Ended for HL411773+4.p
187378.42/24709.52	% SZS status Started for HL411773+5.p
187378.42/24709.52	% SZS status GaveUp for HL411773+5.p
187378.42/24709.52	eprover: CPU time limit exceeded, terminating
187378.42/24709.52	% SZS status Ended for HL411773+5.p
187379.53/24709.63	% SZS status Started for HL411774+4.p
187379.53/24709.63	% SZS status GaveUp for HL411774+4.p
187379.53/24709.63	eprover: CPU time limit exceeded, terminating
187379.53/24709.63	% SZS status Ended for HL411774+4.p
187380.50/24709.81	% SZS status Started for HL411774+5.p
187380.50/24709.81	% SZS status GaveUp for HL411774+5.p
187380.50/24709.81	eprover: CPU time limit exceeded, terminating
187380.50/24709.81	% SZS status Ended for HL411774+5.p
187384.41/24710.21	% SZS status Started for HL411776+4.p
187384.41/24710.21	% SZS status GaveUp for HL411776+4.p
187384.41/24710.21	eprover: CPU time limit exceeded, terminating
187384.41/24710.21	% SZS status Ended for HL411776+4.p
187387.72/24710.69	% SZS status Started for HL411776+5.p
187387.72/24710.69	% SZS status GaveUp for HL411776+5.p
187387.72/24710.69	eprover: CPU time limit exceeded, terminating
187387.72/24710.69	% SZS status Ended for HL411776+5.p
187388.44/24710.78	% SZS status Started for HL411779+4.p
187388.44/24710.78	% SZS status GaveUp for HL411779+4.p
187388.44/24710.78	eprover: CPU time limit exceeded, terminating
187388.44/24710.78	% SZS status Ended for HL411779+4.p
187390.88/24711.18	% SZS status Started for HL411779+5.p
187390.88/24711.18	% SZS status GaveUp for HL411779+5.p
187390.88/24711.18	eprover: CPU time limit exceeded, terminating
187390.88/24711.18	% SZS status Ended for HL411779+5.p
187397.45/24711.85	% SZS status Started for HL411783+4.p
187397.45/24711.85	% SZS status GaveUp for HL411783+4.p
187397.45/24711.85	eprover: CPU time limit exceeded, terminating
187397.45/24711.85	% SZS status Ended for HL411783+4.p
187402.83/24712.55	% SZS status Started for HL411783+5.p
187402.83/24712.55	% SZS status GaveUp for HL411783+5.p
187402.83/24712.55	eprover: CPU time limit exceeded, terminating
187402.83/24712.55	% SZS status Ended for HL411783+5.p
187404.44/24712.73	% SZS status Started for HL411784+4.p
187404.44/24712.73	% SZS status GaveUp for HL411784+4.p
187404.44/24712.73	eprover: CPU time limit exceeded, terminating
187404.44/24712.73	% SZS status Ended for HL411784+4.p
187404.95/24712.85	% SZS status Started for HL411784+5.p
187404.95/24712.85	% SZS status GaveUp for HL411784+5.p
187404.95/24712.85	eprover: CPU time limit exceeded, terminating
187404.95/24712.85	% SZS status Ended for HL411784+5.p
187408.23/24713.25	% SZS status Started for HL411785+4.p
187408.23/24713.25	% SZS status GaveUp for HL411785+4.p
187408.23/24713.25	eprover: CPU time limit exceeded, terminating
187408.23/24713.25	% SZS status Ended for HL411785+4.p
187412.33/24713.72	% SZS status Started for HL411785+5.p
187412.33/24713.72	% SZS status GaveUp for HL411785+5.p
187412.33/24713.72	eprover: CPU time limit exceeded, terminating
187412.33/24713.72	% SZS status Ended for HL411785+5.p
187413.02/24713.81	% SZS status Started for HL411786+4.p
187413.02/24713.81	% SZS status GaveUp for HL411786+4.p
187413.02/24713.81	eprover: CPU time limit exceeded, terminating
187413.02/24713.81	% SZS status Ended for HL411786+4.p
187417.12/24714.34	% SZS status Started for HL411786+5.p
187417.12/24714.34	% SZS status GaveUp for HL411786+5.p
187417.12/24714.34	eprover: CPU time limit exceeded, terminating
187417.12/24714.34	% SZS status Ended for HL411786+5.p
187421.22/24714.88	% SZS status Started for HL411787+4.p
187421.22/24714.88	% SZS status GaveUp for HL411787+4.p
187421.22/24714.88	eprover: CPU time limit exceeded, terminating
187421.22/24714.88	% SZS status Ended for HL411787+4.p
187427.31/24715.59	% SZS status Started for HL411787+5.p
187427.31/24715.59	% SZS status GaveUp for HL411787+5.p
187427.31/24715.59	eprover: CPU time limit exceeded, terminating
187427.31/24715.59	% SZS status Ended for HL411787+5.p
187428.36/24715.77	% SZS status Started for HL411788+4.p
187428.36/24715.77	% SZS status GaveUp for HL411788+4.p
187428.36/24715.77	eprover: CPU time limit exceeded, terminating
187428.36/24715.77	% SZS status Ended for HL411788+4.p
187428.94/24715.88	% SZS status Started for HL411788+5.p
187428.94/24715.88	% SZS status GaveUp for HL411788+5.p
187428.94/24715.88	eprover: CPU time limit exceeded, terminating
187428.94/24715.88	% SZS status Ended for HL411788+5.p
187432.61/24716.28	% SZS status Started for HL411790+4.p
187432.61/24716.28	% SZS status GaveUp for HL411790+4.p
187432.61/24716.28	eprover: CPU time limit exceeded, terminating
187432.61/24716.28	% SZS status Ended for HL411790+4.p
187436.33/24716.75	% SZS status Started for HL411790+5.p
187436.33/24716.75	% SZS status GaveUp for HL411790+5.p
187436.33/24716.75	eprover: CPU time limit exceeded, terminating
187436.33/24716.75	% SZS status Ended for HL411790+5.p
187437.73/24716.95	% SZS status Started for HL411791+4.p
187437.73/24716.95	% SZS status GaveUp for HL411791+4.p
187437.73/24716.95	eprover: CPU time limit exceeded, terminating
187437.73/24716.95	% SZS status Ended for HL411791+4.p
187440.97/24717.37	% SZS status Started for HL411791+5.p
187440.97/24717.37	% SZS status GaveUp for HL411791+5.p
187440.97/24717.37	eprover: CPU time limit exceeded, terminating
187440.97/24717.37	% SZS status Ended for HL411791+5.p
187445.73/24717.92	% SZS status Started for HL411792+4.p
187445.73/24717.92	% SZS status GaveUp for HL411792+4.p
187445.73/24717.92	eprover: CPU time limit exceeded, terminating
187445.73/24717.92	% SZS status Ended for HL411792+4.p
187450.55/24718.62	% SZS status Started for HL411792+5.p
187450.55/24718.62	% SZS status GaveUp for HL411792+5.p
187450.55/24718.62	eprover: CPU time limit exceeded, terminating
187450.55/24718.62	% SZS status Ended for HL411792+5.p
187452.30/24718.80	% SZS status Started for HL411793+4.p
187452.30/24718.80	% SZS status GaveUp for HL411793+4.p
187452.30/24718.80	eprover: CPU time limit exceeded, terminating
187452.30/24718.80	% SZS status Ended for HL411793+4.p
187453.41/24718.92	% SZS status Started for HL411793+5.p
187453.41/24718.92	% SZS status GaveUp for HL411793+5.p
187453.41/24718.92	eprover: CPU time limit exceeded, terminating
187453.41/24718.92	% SZS status Ended for HL411793+5.p
187459.47/24719.75	% SZS status Started for HL411794+4.p
187459.47/24719.75	% SZS status GaveUp for HL411794+4.p
187459.47/24719.75	eprover: CPU time limit exceeded, terminating
187459.47/24719.75	% SZS status Ended for HL411794+4.p
187460.12/24719.83	% SZS status Started for HL411794+5.p
187460.12/24719.83	% SZS status GaveUp for HL411794+5.p
187460.12/24719.83	eprover: CPU time limit exceeded, terminating
187460.12/24719.83	% SZS status Ended for HL411794+5.p
187461.17/24719.98	% SZS status Started for HL411795+4.p
187461.17/24719.98	% SZS status GaveUp for HL411795+4.p
187461.17/24719.98	eprover: CPU time limit exceeded, terminating
187461.17/24719.98	% SZS status Ended for HL411795+4.p
187463.94/24720.41	% SZS status Started for HL411795+5.p
187463.94/24720.41	% SZS status GaveUp for HL411795+5.p
187463.94/24720.41	eprover: CPU time limit exceeded, terminating
187463.94/24720.41	% SZS status Ended for HL411795+5.p
187468.31/24720.96	% SZS status Started for HL411796+4.p
187468.31/24720.96	% SZS status GaveUp for HL411796+4.p
187468.31/24720.96	eprover: CPU time limit exceeded, terminating
187468.31/24720.96	% SZS status Ended for HL411796+4.p
187474.16/24721.65	% SZS status Started for HL411796+5.p
187474.16/24721.65	% SZS status GaveUp for HL411796+5.p
187474.16/24721.65	eprover: CPU time limit exceeded, terminating
187474.16/24721.65	% SZS status Ended for HL411796+5.p
187476.09/24721.95	% SZS status Started for HL411797+4.p
187476.09/24721.95	% SZS status GaveUp for HL411797+4.p
187476.09/24721.95	eprover: CPU time limit exceeded, terminating
187476.09/24721.95	% SZS status Ended for HL411797+4.p
187483.16/24722.80	% SZS status Started for HL411798+4.p
187483.16/24722.80	% SZS status GaveUp for HL411798+4.p
187483.16/24722.80	eprover: CPU time limit exceeded, terminating
187483.16/24722.80	% SZS status Ended for HL411798+4.p
187485.33/24723.09	% SZS status Started for HL411799+4.p
187485.33/24723.09	% SZS status GaveUp for HL411799+4.p
187485.33/24723.09	eprover: CPU time limit exceeded, terminating
187485.33/24723.09	% SZS status Ended for HL411799+4.p
187492.17/24723.98	% SZS status Started for HL411801+4.p
187492.17/24723.98	% SZS status GaveUp for HL411801+4.p
187492.17/24723.98	eprover: CPU time limit exceeded, terminating
187492.17/24723.98	% SZS status Ended for HL411801+4.p
187500.25/24724.98	% SZS status Started for HL411802+4.p
187500.25/24724.98	% SZS status GaveUp for HL411802+4.p
187500.25/24724.98	eprover: CPU time limit exceeded, terminating
187500.25/24724.98	% SZS status Ended for HL411802+4.p
187509.75/24726.13	% SZS status Started for HL411803+4.p
187509.75/24726.13	% SZS status GaveUp for HL411803+4.p
187509.75/24726.13	eprover: CPU time limit exceeded, terminating
187509.75/24726.13	% SZS status Ended for HL411803+4.p
187525.03/24728.03	% SZS status Started for HL411804+4.p
187525.03/24728.03	% SZS status GaveUp for HL411804+4.p
187525.03/24728.03	eprover: CPU time limit exceeded, terminating
187525.03/24728.03	% SZS status Ended for HL411804+4.p
187541.72/24730.17	% SZS status Started for HL411797+5.p
187541.72/24730.17	% SZS status GaveUp for HL411797+5.p
187541.72/24730.17	eprover: CPU time limit exceeded, terminating
187541.72/24730.17	% SZS status Ended for HL411797+5.p
187546.28/24730.70	% SZS status Started for HL411798+5.p
187546.28/24730.70	% SZS status GaveUp for HL411798+5.p
187546.28/24730.70	eprover: CPU time limit exceeded, terminating
187546.28/24730.70	% SZS status Ended for HL411798+5.p
187549.00/24731.06	% SZS status Started for HL411805+4.p
187549.00/24731.06	% SZS status GaveUp for HL411805+4.p
187549.00/24731.06	eprover: CPU time limit exceeded, terminating
187549.00/24731.06	% SZS status Ended for HL411805+4.p
187549.00/24731.07	% SZS status Started for HL411799+5.p
187549.00/24731.07	% SZS status GaveUp for HL411799+5.p
187549.00/24731.07	eprover: CPU time limit exceeded, terminating
187549.00/24731.07	% SZS status Ended for HL411799+5.p
187559.17/24732.32	% SZS status Started for HL411801+5.p
187559.17/24732.32	% SZS status GaveUp for HL411801+5.p
187559.17/24732.32	eprover: CPU time limit exceeded, terminating
187559.17/24732.32	% SZS status Ended for HL411801+5.p
187570.06/24733.73	% SZS status Started for HL411806+4.p
187570.06/24733.73	% SZS status GaveUp for HL411806+4.p
187570.06/24733.73	eprover: CPU time limit exceeded, terminating
187570.06/24733.73	% SZS status Ended for HL411806+4.p
187570.06/24733.73	% SZS status Started for HL411802+5.p
187570.06/24733.73	% SZS status GaveUp for HL411802+5.p
187570.06/24733.73	eprover: CPU time limit exceeded, terminating
187570.06/24733.73	% SZS status Ended for HL411802+5.p
187572.61/24734.09	% SZS status Started for HL411807+4.p
187572.61/24734.09	% SZS status GaveUp for HL411807+4.p
187572.61/24734.09	eprover: CPU time limit exceeded, terminating
187572.61/24734.09	% SZS status Ended for HL411807+4.p
187578.47/24734.77	% SZS status Started for HL411803+5.p
187578.47/24734.77	% SZS status GaveUp for HL411803+5.p
187578.47/24734.77	eprover: CPU time limit exceeded, terminating
187578.47/24734.77	% SZS status Ended for HL411803+5.p
187594.67/24736.78	% SZS status Started for HL411808+4.p
187594.67/24736.78	% SZS status GaveUp for HL411808+4.p
187594.67/24736.78	eprover: CPU time limit exceeded, terminating
187594.67/24736.78	% SZS status Ended for HL411808+4.p
187595.19/24736.87	% SZS status Started for HL411804+5.p
187595.19/24736.87	% SZS status GaveUp for HL411804+5.p
187595.19/24736.87	eprover: CPU time limit exceeded, terminating
187595.19/24736.87	% SZS status Ended for HL411804+5.p
187595.91/24737.12	% SZS status Started for HL411809+4.p
187595.91/24737.12	% SZS status GaveUp for HL411809+4.p
187595.91/24737.12	eprover: CPU time limit exceeded, terminating
187595.91/24737.12	% SZS status Ended for HL411809+4.p
187602.72/24737.81	% SZS status Started for HL411809+5.p
187602.72/24737.81	% SZS status GaveUp for HL411809+5.p
187602.72/24737.81	eprover: CPU time limit exceeded, terminating
187602.72/24737.81	% SZS status Ended for HL411809+5.p
187617.77/24739.81	% SZS status Started for HL411810+4.p
187617.77/24739.81	% SZS status GaveUp for HL411810+4.p
187617.77/24739.81	eprover: CPU time limit exceeded, terminating
187617.77/24739.81	% SZS status Ended for HL411810+4.p
187621.42/24740.17	% SZS status Started for HL411811+4.p
187621.42/24740.17	% SZS status GaveUp for HL411811+4.p
187621.42/24740.17	eprover: CPU time limit exceeded, terminating
187621.42/24740.17	% SZS status Ended for HL411811+4.p
187626.88/24740.88	% SZS status Started for HL411805+5.p
187626.88/24740.88	% SZS status GaveUp for HL411805+5.p
187626.88/24740.88	eprover: CPU time limit exceeded, terminating
187626.88/24740.88	% SZS status Ended for HL411805+5.p
187635.11/24741.87	% SZS status Started for HL411806+5.p
187635.11/24741.87	% SZS status GaveUp for HL411806+5.p
187635.11/24741.87	eprover: CPU time limit exceeded, terminating
187635.11/24741.87	% SZS status Ended for HL411806+5.p
187643.48/24742.97	% SZS status Started for HL411812+4.p
187643.48/24742.97	% SZS status GaveUp for HL411812+4.p
187643.48/24742.97	eprover: CPU time limit exceeded, terminating
187643.48/24742.97	% SZS status Ended for HL411812+4.p
187644.11/24743.00	% SZS status Started for HL411807+5.p
187644.11/24743.00	% SZS status GaveUp for HL411807+5.p
187644.11/24743.00	eprover: CPU time limit exceeded, terminating
187644.11/24743.00	% SZS status Ended for HL411807+5.p
187650.22/24743.94	% SZS status Started for HL411814+4.p
187650.22/24743.94	% SZS status GaveUp for HL411814+4.p
187650.22/24743.94	eprover: CPU time limit exceeded, terminating
187650.22/24743.94	% SZS status Ended for HL411814+4.p
187655.48/24744.51	% SZS status Started for HL411808+5.p
187655.48/24744.51	% SZS status GaveUp for HL411808+5.p
187655.48/24744.51	eprover: CPU time limit exceeded, terminating
187655.48/24744.51	% SZS status Ended for HL411808+5.p
187667.12/24746.01	% SZS status Started for HL411816+4.p
187667.12/24746.01	% SZS status GaveUp for HL411816+4.p
187667.12/24746.01	eprover: CPU time limit exceeded, terminating
187667.12/24746.01	% SZS status Ended for HL411816+4.p
187675.53/24746.98	% SZS status Started for HL411817+4.p
187675.53/24746.98	% SZS status GaveUp for HL411817+4.p
187675.53/24746.98	eprover: CPU time limit exceeded, terminating
187675.53/24746.98	% SZS status Ended for HL411817+4.p
187680.53/24747.63	% SZS status Started for HL411817+5.p
187680.53/24747.63	% SZS status GaveUp for HL411817+5.p
187680.53/24747.63	eprover: CPU time limit exceeded, terminating
187680.53/24747.63	% SZS status Ended for HL411817+5.p
187681.30/24747.71	% SZS status Started for HL411810+5.p
187681.30/24747.71	% SZS status GaveUp for HL411810+5.p
187681.30/24747.71	eprover: CPU time limit exceeded, terminating
187681.30/24747.71	% SZS status Ended for HL411810+5.p
187687.78/24748.54	% SZS status Started for HL411811+5.p
187687.78/24748.54	% SZS status GaveUp for HL411811+5.p
187687.78/24748.54	eprover: CPU time limit exceeded, terminating
187687.78/24748.54	% SZS status Ended for HL411811+5.p
187692.48/24749.10	% SZS status Started for HL411822+4.p
187692.48/24749.10	% SZS status GaveUp for HL411822+4.p
187692.48/24749.10	eprover: CPU time limit exceeded, terminating
187692.48/24749.10	% SZS status Ended for HL411822+4.p
187704.66/24750.70	% SZS status Started for HL411823+4.p
187704.66/24750.70	% SZS status GaveUp for HL411823+4.p
187704.66/24750.70	eprover: CPU time limit exceeded, terminating
187704.66/24750.70	% SZS status Ended for HL411823+4.p
187707.94/24751.19	% SZS status Started for HL411812+5.p
187707.94/24751.19	% SZS status GaveUp for HL411812+5.p
187707.94/24751.19	eprover: CPU time limit exceeded, terminating
187707.94/24751.19	% SZS status Ended for HL411812+5.p
187711.81/24751.57	% SZS status Started for HL411824+4.p
187711.81/24751.57	% SZS status GaveUp for HL411824+4.p
187711.81/24751.57	eprover: CPU time limit exceeded, terminating
187711.81/24751.57	% SZS status Ended for HL411824+4.p
187722.98/24752.95	% SZS status Started for HL411814+5.p
187722.98/24752.95	% SZS status GaveUp for HL411814+5.p
187722.98/24752.95	eprover: CPU time limit exceeded, terminating
187722.98/24752.95	% SZS status Ended for HL411814+5.p
187729.55/24753.80	% SZS status Started for HL411825+4.p
187729.55/24753.80	% SZS status GaveUp for HL411825+4.p
187729.55/24753.80	eprover: CPU time limit exceeded, terminating
187729.55/24753.80	% SZS status Ended for HL411825+4.p
187729.55/24753.83	% SZS status Started for HL411816+5.p
187729.55/24753.83	% SZS status GaveUp for HL411816+5.p
187729.55/24753.83	eprover: CPU time limit exceeded, terminating
187729.55/24753.83	% SZS status Ended for HL411816+5.p
187733.14/24754.22	% SZS status Started for HL411825+5.p
187733.14/24754.22	% SZS status GaveUp for HL411825+5.p
187733.14/24754.22	eprover: CPU time limit exceeded, terminating
187733.14/24754.22	% SZS status Ended for HL411825+5.p
187735.95/24754.66	% SZS status Started for HL411826+4.p
187735.95/24754.66	% SZS status GaveUp for HL411826+4.p
187735.95/24754.66	eprover: CPU time limit exceeded, terminating
187735.95/24754.66	% SZS status Ended for HL411826+4.p
187753.38/24756.93	% SZS status Started for HL411828+4.p
187753.38/24756.93	% SZS status GaveUp for HL411828+4.p
187753.38/24756.93	eprover: CPU time limit exceeded, terminating
187753.38/24756.93	% SZS status Ended for HL411828+4.p
187757.34/24757.28	% SZS status Started for HL411829+4.p
187757.34/24757.28	% SZS status GaveUp for HL411829+4.p
187757.34/24757.28	eprover: CPU time limit exceeded, terminating
187757.34/24757.28	% SZS status Ended for HL411829+4.p
187762.28/24757.96	% SZS status Started for HL411822+5.p
187762.28/24757.96	% SZS status GaveUp for HL411822+5.p
187762.28/24757.96	eprover: CPU time limit exceeded, terminating
187762.28/24757.96	% SZS status Ended for HL411822+5.p
187766.72/24758.50	% SZS status Started for HL411823+5.p
187766.72/24758.50	% SZS status GaveUp for HL411823+5.p
187766.72/24758.50	eprover: CPU time limit exceeded, terminating
187766.72/24758.50	% SZS status Ended for HL411823+5.p
187778.56/24759.99	% SZS status Started for HL411830+4.p
187778.56/24759.99	% SZS status GaveUp for HL411830+4.p
187778.56/24759.99	eprover: CPU time limit exceeded, terminating
187778.56/24759.99	% SZS status Ended for HL411830+4.p
187778.80/24760.03	% SZS status Started for HL411824+5.p
187778.80/24760.03	% SZS status GaveUp for HL411824+5.p
187778.80/24760.03	eprover: CPU time limit exceeded, terminating
187778.80/24760.03	% SZS status Ended for HL411824+5.p
187786.70/24761.02	% SZS status Started for HL411831+4.p
187786.70/24761.02	% SZS status GaveUp for HL411831+4.p
187786.70/24761.02	eprover: CPU time limit exceeded, terminating
187786.70/24761.02	% SZS status Ended for HL411831+4.p
187803.36/24763.13	% SZS status Started for HL411832+4.p
187803.36/24763.13	% SZS status GaveUp for HL411832+4.p
187803.36/24763.13	eprover: CPU time limit exceeded, terminating
187803.36/24763.13	% SZS status Ended for HL411832+4.p
187808.88/24763.83	% SZS status Started for HL411826+5.p
187808.88/24763.83	% SZS status GaveUp for HL411826+5.p
187808.88/24763.83	eprover: CPU time limit exceeded, terminating
187808.88/24763.83	% SZS status Ended for HL411826+5.p
187810.39/24764.10	% SZS status Started for HL411833+4.p
187810.39/24764.10	% SZS status GaveUp for HL411833+4.p
187810.39/24764.10	eprover: CPU time limit exceeded, terminating
187810.39/24764.10	% SZS status Ended for HL411833+4.p
187816.70/24764.81	% SZS status Started for HL411828+5.p
187816.70/24764.81	% SZS status GaveUp for HL411828+5.p
187816.70/24764.81	eprover: CPU time limit exceeded, terminating
187816.70/24764.81	% SZS status Ended for HL411828+5.p
187821.52/24765.43	% SZS status Started for HL411829+5.p
187821.52/24765.43	% SZS status GaveUp for HL411829+5.p
187821.52/24765.43	eprover: CPU time limit exceeded, terminating
187821.52/24765.43	% SZS status Ended for HL411829+5.p
187833.80/24766.93	% SZS status Started for HL411834+4.p
187833.80/24766.93	% SZS status GaveUp for HL411834+4.p
187833.80/24766.93	eprover: CPU time limit exceeded, terminating
187833.80/24766.93	% SZS status Ended for HL411834+4.p
187840.88/24767.86	% SZS status Started for HL411835+4.p
187840.88/24767.86	% SZS status GaveUp for HL411835+4.p
187840.88/24767.86	eprover: CPU time limit exceeded, terminating
187840.88/24767.86	% SZS status Ended for HL411835+4.p
187842.78/24768.09	% SZS status Started for HL411830+5.p
187842.78/24768.09	% SZS status GaveUp for HL411830+5.p
187842.78/24768.09	eprover: CPU time limit exceeded, terminating
187842.78/24768.09	% SZS status Ended for HL411830+5.p
187852.95/24769.34	% SZS status Started for HL411831+5.p
187852.95/24769.34	% SZS status GaveUp for HL411831+5.p
187852.95/24769.34	eprover: CPU time limit exceeded, terminating
187852.95/24769.34	% SZS status Ended for HL411831+5.p
187857.56/24769.98	% SZS status Started for HL411837+4.p
187857.56/24769.98	% SZS status GaveUp for HL411837+4.p
187857.56/24769.98	eprover: CPU time limit exceeded, terminating
187857.56/24769.98	% SZS status Ended for HL411837+4.p
187865.69/24770.96	% SZS status Started for HL411832+5.p
187865.69/24770.96	% SZS status GaveUp for HL411832+5.p
187865.69/24770.96	eprover: CPU time limit exceeded, terminating
187865.69/24770.96	% SZS status Ended for HL411832+5.p
187866.47/24771.12	% SZS status Started for HL411838+4.p
187866.47/24771.12	% SZS status GaveUp for HL411838+4.p
187866.47/24771.12	eprover: CPU time limit exceeded, terminating
187866.47/24771.12	% SZS status Ended for HL411838+4.p
187882.77/24773.10	% SZS status Started for HL411839+4.p
187882.77/24773.10	% SZS status GaveUp for HL411839+4.p
187882.77/24773.10	eprover: CPU time limit exceeded, terminating
187882.77/24773.10	% SZS status Ended for HL411839+4.p
187888.69/24773.85	% SZS status Started for HL411833+5.p
187888.69/24773.85	% SZS status GaveUp for HL411833+5.p
187888.69/24773.85	eprover: CPU time limit exceeded, terminating
187888.69/24773.85	% SZS status Ended for HL411833+5.p
187891.12/24774.19	% SZS status Started for HL411840+4.p
187891.12/24774.19	% SZS status GaveUp for HL411840+4.p
187891.12/24774.19	eprover: CPU time limit exceeded, terminating
187891.12/24774.19	% SZS status Ended for HL411840+4.p
187896.95/24774.94	% SZS status Started for HL411834+5.p
187896.95/24774.94	% SZS status GaveUp for HL411834+5.p
187896.95/24774.94	eprover: CPU time limit exceeded, terminating
187896.95/24774.94	% SZS status Ended for HL411834+5.p
187907.41/24776.29	% SZS status Started for HL411835+5.p
187907.41/24776.29	% SZS status GaveUp for HL411835+5.p
187907.41/24776.29	eprover: CPU time limit exceeded, terminating
187907.41/24776.29	% SZS status Ended for HL411835+5.p
187912.19/24776.87	% SZS status Started for HL411841+4.p
187912.19/24776.87	% SZS status GaveUp for HL411841+4.p
187912.19/24776.87	eprover: CPU time limit exceeded, terminating
187912.19/24776.87	% SZS status Ended for HL411841+4.p
187920.41/24777.97	% SZS status Started for HL411842+4.p
187920.41/24777.97	% SZS status GaveUp for HL411842+4.p
187920.41/24777.97	eprover: CPU time limit exceeded, terminating
187920.41/24777.97	% SZS status Ended for HL411842+4.p
187925.86/24778.61	% SZS status Started for HL411837+5.p
187925.86/24778.61	% SZS status GaveUp for HL411837+5.p
187925.86/24778.61	eprover: CPU time limit exceeded, terminating
187925.86/24778.61	% SZS status Ended for HL411837+5.p
187936.30/24779.90	% SZS status Started for HL411843+4.p
187936.30/24779.90	% SZS status GaveUp for HL411843+4.p
187936.30/24779.90	eprover: CPU time limit exceeded, terminating
187936.30/24779.90	% SZS status Ended for HL411843+4.p
187937.91/24780.10	% SZS status Started for HL411838+5.p
187937.91/24780.10	% SZS status GaveUp for HL411838+5.p
187937.91/24780.10	eprover: CPU time limit exceeded, terminating
187937.91/24780.10	% SZS status Ended for HL411838+5.p
187950.77/24781.69	% SZS status Started for HL411839+5.p
187950.77/24781.69	% SZS status GaveUp for HL411839+5.p
187950.77/24781.69	eprover: CPU time limit exceeded, terminating
187950.77/24781.69	% SZS status Ended for HL411839+5.p
187950.77/24781.70	% SZS status Started for HL411844+4.p
187950.77/24781.70	% SZS status GaveUp for HL411844+4.p
187950.77/24781.70	eprover: CPU time limit exceeded, terminating
187950.77/24781.70	% SZS status Ended for HL411844+4.p
187961.66/24783.14	% SZS status Started for HL411845+4.p
187961.66/24783.14	% SZS status GaveUp for HL411845+4.p
187961.66/24783.14	eprover: CPU time limit exceeded, terminating
187961.66/24783.14	% SZS status Ended for HL411845+4.p
187970.52/24784.22	% SZS status Started for HL411840+5.p
187970.52/24784.22	% SZS status GaveUp for HL411840+5.p
187970.52/24784.22	eprover: CPU time limit exceeded, terminating
187970.52/24784.22	% SZS status Ended for HL411840+5.p
187974.83/24784.78	% SZS status Started for HL411847+4.p
187974.83/24784.78	% SZS status GaveUp for HL411847+4.p
187974.83/24784.78	eprover: CPU time limit exceeded, terminating
187974.83/24784.78	% SZS status Ended for HL411847+4.p
187977.33/24785.01	% SZS status Started for HL411841+5.p
187977.33/24785.01	% SZS status GaveUp for HL411841+5.p
187977.33/24785.01	eprover: CPU time limit exceeded, terminating
187977.33/24785.01	% SZS status Ended for HL411841+5.p
187995.28/24787.28	% SZS status Started for HL411842+5.p
187995.28/24787.28	% SZS status GaveUp for HL411842+5.p
187995.28/24787.28	eprover: CPU time limit exceeded, terminating
187995.28/24787.28	% SZS status Ended for HL411842+5.p
187995.62/24787.33	% SZS status Started for HL411848+4.p
187995.62/24787.33	% SZS status GaveUp for HL411848+4.p
187995.62/24787.33	eprover: CPU time limit exceeded, terminating
187995.62/24787.33	% SZS status Ended for HL411848+4.p
188000.88/24788.04	% SZS status Started for HL411849+4.p
188000.88/24788.04	% SZS status GaveUp for HL411849+4.p
188000.88/24788.04	eprover: CPU time limit exceeded, terminating
188000.88/24788.04	% SZS status Ended for HL411849+4.p
188006.64/24788.82	% SZS status Started for HL411843+5.p
188006.64/24788.82	% SZS status GaveUp for HL411843+5.p
188006.64/24788.82	eprover: CPU time limit exceeded, terminating
188006.64/24788.82	% SZS status Ended for HL411843+5.p
188019.52/24790.36	% SZS status Started for HL411850+4.p
188019.52/24790.36	% SZS status GaveUp for HL411850+4.p
188019.52/24790.36	eprover: CPU time limit exceeded, terminating
188019.52/24790.36	% SZS status Ended for HL411850+4.p
188021.62/24790.60	% SZS status Started for HL411844+5.p
188021.62/24790.60	% SZS status GaveUp for HL411844+5.p
188021.62/24790.60	eprover: CPU time limit exceeded, terminating
188021.62/24790.60	% SZS status Ended for HL411844+5.p
188031.25/24791.85	% SZS status Started for HL411851+4.p
188031.25/24791.85	% SZS status GaveUp for HL411851+4.p
188031.25/24791.85	eprover: CPU time limit exceeded, terminating
188031.25/24791.85	% SZS status Ended for HL411851+4.p
188036.92/24792.58	% SZS status Started for HL411845+5.p
188036.92/24792.58	% SZS status GaveUp for HL411845+5.p
188036.92/24792.58	eprover: CPU time limit exceeded, terminating
188036.92/24792.58	% SZS status Ended for HL411845+5.p
188045.34/24793.64	% SZS status Started for HL411852+4.p
188045.34/24793.64	% SZS status GaveUp for HL411852+4.p
188045.34/24793.64	eprover: CPU time limit exceeded, terminating
188045.34/24793.64	% SZS status Ended for HL411852+4.p
188049.56/24794.13	% SZS status Started for HL411847+5.p
188049.56/24794.13	% SZS status GaveUp for HL411847+5.p
188049.56/24794.13	eprover: CPU time limit exceeded, terminating
188049.56/24794.13	% SZS status Ended for HL411847+5.p
188055.81/24794.91	% SZS status Started for HL411852+5.p
188055.81/24794.91	% SZS status GaveUp for HL411852+5.p
188055.81/24794.91	eprover: CPU time limit exceeded, terminating
188055.81/24794.91	% SZS status Ended for HL411852+5.p
188060.16/24795.62	% SZS status Started for HL411854+4.p
188060.16/24795.62	% SZS status GaveUp for HL411854+4.p
188060.16/24795.62	eprover: CPU time limit exceeded, terminating
188060.16/24795.62	% SZS status Ended for HL411854+4.p
188063.97/24795.94	% SZS status Started for HL411848+5.p
188063.97/24795.94	% SZS status GaveUp for HL411848+5.p
188063.97/24795.94	eprover: CPU time limit exceeded, terminating
188063.97/24795.94	% SZS status Ended for HL411848+5.p
188073.52/24797.18	% SZS status Started for HL411855+4.p
188073.52/24797.18	% SZS status GaveUp for HL411855+4.p
188073.52/24797.18	eprover: CPU time limit exceeded, terminating
188073.52/24797.18	% SZS status Ended for HL411855+4.p
188082.11/24798.24	% SZS status Started for HL411849+5.p
188082.11/24798.24	% SZS status GaveUp for HL411849+5.p
188082.11/24798.24	eprover: CPU time limit exceeded, terminating
188082.11/24798.24	% SZS status Ended for HL411849+5.p
188085.38/24798.70	% SZS status Started for HL411856+4.p
188085.38/24798.70	% SZS status GaveUp for HL411856+4.p
188085.38/24798.70	eprover: CPU time limit exceeded, terminating
188085.38/24798.70	% SZS status Ended for HL411856+4.p
188087.42/24799.04	% SZS status Started for HL411850+5.p
188087.42/24799.04	% SZS status GaveUp for HL411850+5.p
188087.42/24799.04	eprover: CPU time limit exceeded, terminating
188087.42/24799.04	% SZS status Ended for HL411850+5.p
188098.73/24800.32	% SZS status Started for HL411857+4.p
188098.73/24800.32	% SZS status GaveUp for HL411857+4.p
188098.73/24800.32	eprover: CPU time limit exceeded, terminating
188098.73/24800.32	% SZS status Ended for HL411857+4.p
188106.00/24801.27	% SZS status Started for HL411851+5.p
188106.00/24801.27	% SZS status GaveUp for HL411851+5.p
188106.00/24801.27	eprover: CPU time limit exceeded, terminating
188106.00/24801.27	% SZS status Ended for HL411851+5.p
188109.36/24801.73	% SZS status Started for HL411859+4.p
188109.36/24801.73	% SZS status GaveUp for HL411859+4.p
188109.36/24801.73	eprover: CPU time limit exceeded, terminating
188109.36/24801.73	% SZS status Ended for HL411859+4.p
188123.27/24803.44	% SZS status Started for HL411862+4.p
188123.27/24803.44	% SZS status GaveUp for HL411862+4.p
188123.27/24803.44	eprover: CPU time limit exceeded, terminating
188123.27/24803.44	% SZS status Ended for HL411862+4.p
188132.34/24804.56	% SZS status Started for HL411854+5.p
188132.34/24804.56	% SZS status GaveUp for HL411854+5.p
188132.34/24804.56	eprover: CPU time limit exceeded, terminating
188132.34/24804.56	% SZS status Ended for HL411854+5.p
188133.77/24804.77	% SZS status Started for HL411864+4.p
188133.77/24804.77	% SZS status GaveUp for HL411864+4.p
188133.77/24804.77	eprover: CPU time limit exceeded, terminating
188133.77/24804.77	% SZS status Ended for HL411864+4.p
188140.28/24805.66	% SZS status Started for HL411855+5.p
188140.28/24805.66	% SZS status GaveUp for HL411855+5.p
188140.28/24805.66	eprover: CPU time limit exceeded, terminating
188140.28/24805.66	% SZS status Ended for HL411855+5.p
188160.06/24806.81	% SZS status Started for HL411856+5.p
188160.06/24806.81	% SZS status GaveUp for HL411856+5.p
188160.06/24806.81	eprover: CPU time limit exceeded, terminating
188160.06/24806.81	% SZS status Ended for HL411856+5.p
188166.66/24807.68	% SZS status Started for HL411865+4.p
188166.66/24807.68	% SZS status GaveUp for HL411865+4.p
188166.66/24807.68	eprover: CPU time limit exceeded, terminating
188166.66/24807.68	% SZS status Ended for HL411865+4.p
188174.61/24808.68	% SZS status Started for HL411867+4.p
188174.61/24808.68	% SZS status GaveUp for HL411867+4.p
188174.61/24808.68	eprover: CPU time limit exceeded, terminating
188174.61/24808.68	% SZS status Ended for HL411867+4.p
188177.86/24809.07	% SZS status Started for HL411857+5.p
188177.86/24809.07	% SZS status GaveUp for HL411857+5.p
188177.86/24809.07	eprover: CPU time limit exceeded, terminating
188177.86/24809.07	% SZS status Ended for HL411857+5.p
188185.69/24810.12	% SZS status Started for HL411859+5.p
188185.69/24810.12	% SZS status GaveUp for HL411859+5.p
188185.69/24810.12	eprover: CPU time limit exceeded, terminating
188185.69/24810.12	% SZS status Ended for HL411859+5.p
188190.97/24810.72	% SZS status Started for HL411869+4.p
188190.97/24810.72	% SZS status GaveUp for HL411869+4.p
188190.97/24810.72	eprover: CPU time limit exceeded, terminating
188190.97/24810.72	% SZS status Ended for HL411869+4.p
188202.03/24812.10	% SZS status Started for HL411870+4.p
188202.03/24812.10	% SZS status GaveUp for HL411870+4.p
188202.03/24812.10	eprover: CPU time limit exceeded, terminating
188202.03/24812.10	% SZS status Ended for HL411870+4.p
188202.61/24812.20	% SZS status Started for HL411862+5.p
188202.61/24812.20	% SZS status GaveUp for HL411862+5.p
188202.61/24812.20	eprover: CPU time limit exceeded, terminating
188202.61/24812.20	% SZS status Ended for HL411862+5.p
188214.77/24813.82	% SZS status Started for HL411871+4.p
188214.77/24813.82	% SZS status GaveUp for HL411871+4.p
188214.77/24813.82	eprover: CPU time limit exceeded, terminating
188214.77/24813.82	% SZS status Ended for HL411871+4.p
188220.02/24814.34	% SZS status Started for HL411864+5.p
188220.02/24814.34	% SZS status GaveUp for HL411864+5.p
188220.02/24814.34	eprover: CPU time limit exceeded, terminating
188220.02/24814.34	% SZS status Ended for HL411864+5.p
188227.50/24815.29	% SZS status Started for HL411872+4.p
188227.50/24815.29	% SZS status GaveUp for HL411872+4.p
188227.50/24815.29	eprover: CPU time limit exceeded, terminating
188227.50/24815.29	% SZS status Ended for HL411872+4.p
188230.08/24815.66	% SZS status Started for HL411865+5.p
188230.08/24815.66	% SZS status GaveUp for HL411865+5.p
188230.08/24815.66	eprover: CPU time limit exceeded, terminating
188230.08/24815.66	% SZS status Ended for HL411865+5.p
188243.91/24817.40	% SZS status Started for HL411874+4.p
188243.91/24817.40	% SZS status GaveUp for HL411874+4.p
188243.91/24817.40	eprover: CPU time limit exceeded, terminating
188243.91/24817.40	% SZS status Ended for HL411874+4.p
188246.91/24817.92	% SZS status Started for HL411867+5.p
188246.91/24817.92	% SZS status GaveUp for HL411867+5.p
188246.91/24817.92	eprover: CPU time limit exceeded, terminating
188246.91/24817.92	% SZS status Ended for HL411867+5.p
188254.84/24818.80	% SZS status Started for HL411875+4.p
188254.84/24818.80	% SZS status GaveUp for HL411875+4.p
188254.84/24818.80	eprover: CPU time limit exceeded, terminating
188254.84/24818.80	% SZS status Ended for HL411875+4.p
188262.89/24819.79	% SZS status Started for HL411869+5.p
188262.89/24819.79	% SZS status GaveUp for HL411869+5.p
188262.89/24819.79	eprover: CPU time limit exceeded, terminating
188262.89/24819.79	% SZS status Ended for HL411869+5.p
188271.00/24820.85	% SZS status Started for HL411870+5.p
188271.00/24820.85	% SZS status GaveUp for HL411870+5.p
188271.00/24820.85	eprover: CPU time limit exceeded, terminating
188271.00/24820.85	% SZS status Ended for HL411870+5.p
188272.08/24821.00	% SZS status Started for HL411876+4.p
188272.08/24821.00	% SZS status GaveUp for HL411876+4.p
188272.08/24821.00	eprover: CPU time limit exceeded, terminating
188272.08/24821.00	% SZS status Ended for HL411876+4.p
188286.22/24822.81	% SZS status Started for HL411871+5.p
188286.22/24822.81	% SZS status GaveUp for HL411871+5.p
188286.22/24822.81	eprover: CPU time limit exceeded, terminating
188286.22/24822.81	% SZS status Ended for HL411871+5.p
188286.56/24822.83	% SZS status Started for HL411879+4.p
188286.56/24822.83	% SZS status GaveUp for HL411879+4.p
188286.56/24822.83	eprover: CPU time limit exceeded, terminating
188286.56/24822.83	% SZS status Ended for HL411879+4.p
188296.67/24824.03	% SZS status Started for HL411880+4.p
188296.67/24824.03	% SZS status GaveUp for HL411880+4.p
188296.67/24824.03	eprover: CPU time limit exceeded, terminating
188296.67/24824.03	% SZS status Ended for HL411880+4.p
188300.92/24824.60	% SZS status Started for HL411872+5.p
188300.92/24824.60	% SZS status GaveUp for HL411872+5.p
188300.92/24824.60	eprover: CPU time limit exceeded, terminating
188300.92/24824.60	% SZS status Ended for HL411872+5.p
188310.83/24825.86	% SZS status Started for HL411881+4.p
188310.83/24825.86	% SZS status GaveUp for HL411881+4.p
188310.83/24825.86	eprover: CPU time limit exceeded, terminating
188310.83/24825.86	% SZS status Ended for HL411881+4.p
188313.52/24826.21	% SZS status Started for HL411874+5.p
188313.52/24826.21	% SZS status GaveUp for HL411874+5.p
188313.52/24826.21	eprover: CPU time limit exceeded, terminating
188313.52/24826.21	% SZS status Ended for HL411874+5.p
188320.42/24827.13	% SZS status Started for HL411881+5.p
188320.42/24827.13	% SZS status GaveUp for HL411881+5.p
188320.42/24827.13	eprover: CPU time limit exceeded, terminating
188320.42/24827.13	% SZS status Ended for HL411881+5.p
188325.44/24827.77	% SZS status Started for HL411882+4.p
188325.44/24827.77	% SZS status GaveUp for HL411882+4.p
188325.44/24827.77	eprover: CPU time limit exceeded, terminating
188325.44/24827.77	% SZS status Ended for HL411882+4.p
188330.98/24828.40	% SZS status Started for HL411875+5.p
188330.98/24828.40	% SZS status GaveUp for HL411875+5.p
188330.98/24828.40	eprover: CPU time limit exceeded, terminating
188330.98/24828.40	% SZS status Ended for HL411875+5.p
188337.89/24829.25	% SZS status Started for HL411883+4.p
188337.89/24829.25	% SZS status GaveUp for HL411883+4.p
188337.89/24829.25	eprover: CPU time limit exceeded, terminating
188337.89/24829.25	% SZS status Ended for HL411883+4.p
188339.70/24829.51	% SZS status Started for HL411876+5.p
188339.70/24829.51	% SZS status GaveUp for HL411876+5.p
188339.70/24829.51	eprover: CPU time limit exceeded, terminating
188339.70/24829.51	% SZS status Ended for HL411876+5.p
188345.41/24830.20	% SZS status Started for HL411883+5.p
188345.41/24830.20	% SZS status GaveUp for HL411883+5.p
188345.41/24830.20	eprover: CPU time limit exceeded, terminating
188345.41/24830.20	% SZS status Ended for HL411883+5.p
188349.95/24830.82	% SZS status Started for HL411884+4.p
188349.95/24830.82	% SZS status GaveUp for HL411884+4.p
188349.95/24830.82	eprover: CPU time limit exceeded, terminating
188349.95/24830.82	% SZS status Ended for HL411884+4.p
188360.59/24831.78	% SZS status Started for HL411879+5.p
188360.59/24831.78	% SZS status GaveUp for HL411879+5.p
188360.59/24831.78	eprover: CPU time limit exceeded, terminating
188360.59/24831.78	% SZS status Ended for HL411879+5.p
188364.67/24832.28	% SZS status Started for HL411885+4.p
188364.67/24832.28	% SZS status GaveUp for HL411885+4.p
188364.67/24832.28	eprover: CPU time limit exceeded, terminating
188364.67/24832.28	% SZS status Ended for HL411885+4.p
188373.42/24833.37	% SZS status Started for HL411886+4.p
188373.42/24833.37	% SZS status GaveUp for HL411886+4.p
188373.42/24833.37	eprover: CPU time limit exceeded, terminating
188373.42/24833.37	% SZS status Ended for HL411886+4.p
188377.83/24833.98	% SZS status Started for HL411880+5.p
188377.83/24833.98	% SZS status GaveUp for HL411880+5.p
188377.83/24833.98	eprover: CPU time limit exceeded, terminating
188377.83/24833.98	% SZS status Ended for HL411880+5.p
188384.25/24834.83	% SZS status Started for HL411887+4.p
188384.25/24834.83	% SZS status GaveUp for HL411887+4.p
188384.25/24834.83	eprover: CPU time limit exceeded, terminating
188384.25/24834.83	% SZS status Ended for HL411887+4.p
188396.55/24836.40	% SZS status Started for HL411888+4.p
188396.55/24836.40	% SZS status GaveUp for HL411888+4.p
188396.55/24836.40	eprover: CPU time limit exceeded, terminating
188396.55/24836.40	% SZS status Ended for HL411888+4.p
188400.50/24836.82	% SZS status Started for HL411882+5.p
188400.50/24836.82	% SZS status GaveUp for HL411882+5.p
188400.50/24836.82	eprover: CPU time limit exceeded, terminating
188400.50/24836.82	% SZS status Ended for HL411882+5.p
188408.92/24837.85	% SZS status Started for HL411889+4.p
188408.92/24837.85	% SZS status GaveUp for HL411889+4.p
188408.92/24837.85	eprover: CPU time limit exceeded, terminating
188408.92/24837.85	% SZS status Ended for HL411889+4.p
188419.38/24839.19	% SZS status Started for HL411884+5.p
188419.38/24839.19	% SZS status GaveUp for HL411884+5.p
188419.38/24839.19	eprover: CPU time limit exceeded, terminating
188419.38/24839.19	% SZS status Ended for HL411884+5.p
188424.08/24839.85	% SZS status Started for HL411891+4.p
188424.08/24839.85	% SZS status GaveUp for HL411891+4.p
188424.08/24839.85	eprover: CPU time limit exceeded, terminating
188424.08/24839.85	% SZS status Ended for HL411891+4.p
188431.14/24840.45	% SZS status Started for HL411885+5.p
188431.14/24840.45	% SZS status GaveUp for HL411885+5.p
188431.14/24840.45	eprover: CPU time limit exceeded, terminating
188431.14/24840.45	% SZS status Ended for HL411885+5.p
188442.44/24841.81	% SZS status Started for HL411886+5.p
188442.44/24841.81	% SZS status GaveUp for HL411886+5.p
188442.44/24841.81	eprover: CPU time limit exceeded, terminating
188442.44/24841.81	% SZS status Ended for HL411886+5.p
188446.23/24842.31	% SZS status Started for HL411892+4.p
188446.23/24842.31	% SZS status GaveUp for HL411892+4.p
188446.23/24842.31	eprover: CPU time limit exceeded, terminating
188446.23/24842.31	% SZS status Ended for HL411892+4.p
188453.50/24843.18	% SZS status Started for HL411887+5.p
188453.50/24843.18	% SZS status GaveUp for HL411887+5.p
188453.50/24843.18	eprover: CPU time limit exceeded, terminating
188453.50/24843.18	% SZS status Ended for HL411887+5.p
188455.38/24843.48	% SZS status Started for HL411893+4.p
188455.38/24843.48	% SZS status GaveUp for HL411893+4.p
188455.38/24843.48	eprover: CPU time limit exceeded, terminating
188455.38/24843.48	% SZS status Ended for HL411893+4.p
188465.05/24844.71	% SZS status Started for HL411888+5.p
188465.05/24844.71	% SZS status GaveUp for HL411888+5.p
188465.05/24844.71	eprover: CPU time limit exceeded, terminating
188465.05/24844.71	% SZS status Ended for HL411888+5.p
188470.81/24845.34	% SZS status Started for HL411894+4.p
188470.81/24845.34	% SZS status GaveUp for HL411894+4.p
188470.81/24845.34	eprover: CPU time limit exceeded, terminating
188470.81/24845.34	% SZS status Ended for HL411894+4.p
188479.98/24846.51	% SZS status Started for HL411895+4.p
188479.98/24846.51	% SZS status GaveUp for HL411895+4.p
188479.98/24846.51	eprover: CPU time limit exceeded, terminating
188479.98/24846.51	% SZS status Ended for HL411895+4.p
188485.86/24847.23	% SZS status Started for HL411889+5.p
188485.86/24847.23	% SZS status GaveUp for HL411889+5.p
188485.86/24847.23	eprover: CPU time limit exceeded, terminating
188485.86/24847.23	% SZS status Ended for HL411889+5.p
188489.98/24847.78	% SZS status Started for HL411895+5.p
188489.98/24847.78	% SZS status GaveUp for HL411895+5.p
188489.98/24847.78	eprover: CPU time limit exceeded, terminating
188489.98/24847.78	% SZS status Ended for HL411895+5.p
188494.92/24848.37	% SZS status Started for HL411896+4.p
188494.92/24848.37	% SZS status GaveUp for HL411896+4.p
188494.92/24848.37	eprover: CPU time limit exceeded, terminating
188494.92/24848.37	% SZS status Ended for HL411896+4.p
188496.98/24848.67	% SZS status Started for HL411891+5.p
188496.98/24848.67	% SZS status GaveUp for HL411891+5.p
188496.98/24848.67	eprover: CPU time limit exceeded, terminating
188496.98/24848.67	% SZS status Ended for HL411891+5.p
188509.73/24850.26	% SZS status Started for HL411897+4.p
188509.73/24850.26	% SZS status GaveUp for HL411897+4.p
188509.73/24850.26	eprover: CPU time limit exceeded, terminating
188509.73/24850.26	% SZS status Ended for HL411897+4.p
188514.47/24850.86	% SZS status Started for HL411892+5.p
188514.47/24850.86	% SZS status GaveUp for HL411892+5.p
188514.47/24850.86	eprover: CPU time limit exceeded, terminating
188514.47/24850.86	% SZS status Ended for HL411892+5.p
188518.72/24851.43	% SZS status Started for HL411898+4.p
188518.72/24851.43	% SZS status GaveUp for HL411898+4.p
188518.72/24851.43	eprover: CPU time limit exceeded, terminating
188518.72/24851.43	% SZS status Ended for HL411898+4.p
188531.38/24852.98	% SZS status Started for HL411893+5.p
188531.38/24852.98	% SZS status GaveUp for HL411893+5.p
188531.38/24852.98	eprover: CPU time limit exceeded, terminating
188531.38/24852.98	% SZS status Ended for HL411893+5.p
188533.16/24853.28	% SZS status Started for HL411899+4.p
188533.16/24853.28	% SZS status GaveUp for HL411899+4.p
188533.16/24853.28	eprover: CPU time limit exceeded, terminating
188533.16/24853.28	% SZS status Ended for HL411899+4.p
188538.39/24854.01	% SZS status Started for HL411894+5.p
188538.39/24854.01	% SZS status GaveUp for HL411894+5.p
188538.39/24854.01	eprover: CPU time limit exceeded, terminating
188538.39/24854.01	% SZS status Ended for HL411894+5.p
188543.19/24854.48	% SZS status Started for HL411900+4.p
188543.19/24854.48	% SZS status GaveUp for HL411900+4.p
188543.19/24854.48	eprover: CPU time limit exceeded, terminating
188543.19/24854.48	% SZS status Ended for HL411900+4.p
188557.81/24856.33	% SZS status Started for HL411902+4.p
188557.81/24856.33	% SZS status GaveUp for HL411902+4.p
188557.81/24856.33	eprover: CPU time limit exceeded, terminating
188557.81/24856.33	% SZS status Ended for HL411902+4.p
188570.00/24857.53	% SZS status Started for HL411903+4.p
188570.00/24857.53	% SZS status GaveUp for HL411903+4.p
188570.00/24857.53	eprover: CPU time limit exceeded, terminating
188570.00/24857.53	% SZS status Ended for HL411903+4.p
188570.97/24857.67	% SZS status Started for HL411896+5.p
188570.97/24857.67	% SZS status GaveUp for HL411896+5.p
188570.97/24857.67	eprover: CPU time limit exceeded, terminating
188570.97/24857.67	% SZS status Ended for HL411896+5.p
188580.19/24858.84	% SZS status Started for HL411897+5.p
188580.19/24858.84	% SZS status GaveUp for HL411897+5.p
188580.19/24858.84	eprover: CPU time limit exceeded, terminating
188580.19/24858.84	% SZS status Ended for HL411897+5.p
188586.22/24859.53	% SZS status Started for HL411898+5.p
188586.22/24859.53	% SZS status GaveUp for HL411898+5.p
188586.22/24859.53	eprover: CPU time limit exceeded, terminating
188586.22/24859.53	% SZS status Ended for HL411898+5.p
188594.25/24860.56	% SZS status Started for HL411917+4.p
188594.25/24860.56	% SZS status GaveUp for HL411917+4.p
188594.25/24860.56	eprover: CPU time limit exceeded, terminating
188594.25/24860.56	% SZS status Ended for HL411917+4.p
188602.78/24861.64	% SZS status Started for HL411899+5.p
188602.78/24861.64	% SZS status GaveUp for HL411899+5.p
188602.78/24861.64	eprover: CPU time limit exceeded, terminating
188602.78/24861.64	% SZS status Ended for HL411899+5.p
188604.02/24861.91	% SZS status Started for HL411921+4.p
188604.02/24861.91	% SZS status GaveUp for HL411921+4.p
188604.02/24861.91	eprover: CPU time limit exceeded, terminating
188604.02/24861.91	% SZS status Ended for HL411921+4.p
188617.84/24863.59	% SZS status Started for HL411922+4.p
188617.84/24863.59	% SZS status GaveUp for HL411922+4.p
188617.84/24863.59	eprover: CPU time limit exceeded, terminating
188617.84/24863.59	% SZS status Ended for HL411922+4.p
188620.56/24863.85	% SZS status Started for HL411900+5.p
188620.56/24863.85	% SZS status GaveUp for HL411900+5.p
188620.56/24863.85	eprover: CPU time limit exceeded, terminating
188620.56/24863.85	% SZS status Ended for HL411900+5.p
188627.08/24864.75	% SZS status Started for HL411902+5.p
188627.08/24864.75	% SZS status GaveUp for HL411902+5.p
188627.08/24864.75	eprover: CPU time limit exceeded, terminating
188627.08/24864.75	% SZS status Ended for HL411902+5.p
188628.75/24864.94	% SZS status Started for HL411923+4.p
188628.75/24864.94	% SZS status GaveUp for HL411923+4.p
188628.75/24864.94	eprover: CPU time limit exceeded, terminating
188628.75/24864.94	% SZS status Ended for HL411923+4.p
188644.78/24866.89	% SZS status Started for HL411924+4.p
188644.78/24866.89	% SZS status GaveUp for HL411924+4.p
188644.78/24866.89	eprover: CPU time limit exceeded, terminating
188644.78/24866.89	% SZS status Ended for HL411924+4.p
188647.78/24867.28	% SZS status Started for HL411903+5.p
188647.78/24867.28	% SZS status GaveUp for HL411903+5.p
188647.78/24867.28	eprover: CPU time limit exceeded, terminating
188647.78/24867.28	% SZS status Ended for HL411903+5.p
188653.66/24868.00	% SZS status Started for HL411935+4.p
188653.66/24868.00	% SZS status GaveUp for HL411935+4.p
188653.66/24868.00	eprover: CPU time limit exceeded, terminating
188653.66/24868.00	% SZS status Ended for HL411935+4.p
188657.33/24868.54	% SZS status Started for HL411917+5.p
188657.33/24868.54	% SZS status GaveUp for HL411917+5.p
188657.33/24868.54	eprover: CPU time limit exceeded, terminating
188657.33/24868.54	% SZS status Ended for HL411917+5.p
188671.67/24870.28	% SZS status Started for HL411921+5.p
188671.67/24870.28	% SZS status GaveUp for HL411921+5.p
188671.67/24870.28	eprover: CPU time limit exceeded, terminating
188671.67/24870.28	% SZS status Ended for HL411921+5.p
188672.38/24870.37	% SZS status Started for HL411938+4.p
188672.38/24870.37	% SZS status GaveUp for HL411938+4.p
188672.38/24870.37	eprover: CPU time limit exceeded, terminating
188672.38/24870.37	% SZS status Ended for HL411938+4.p
188681.67/24871.60	% SZS status Started for HL411944+4.p
188681.67/24871.60	% SZS status GaveUp for HL411944+4.p
188681.67/24871.60	eprover: CPU time limit exceeded, terminating
188681.67/24871.60	% SZS status Ended for HL411944+4.p
188688.88/24872.49	% SZS status Started for HL411922+5.p
188688.88/24872.49	% SZS status GaveUp for HL411922+5.p
188688.88/24872.49	eprover: CPU time limit exceeded, terminating
188688.88/24872.49	% SZS status Ended for HL411922+5.p
188696.27/24873.40	% SZS status Started for HL411947+4.p
188696.27/24873.40	% SZS status GaveUp for HL411947+4.p
188696.27/24873.40	eprover: CPU time limit exceeded, terminating
188696.27/24873.40	% SZS status Ended for HL411947+4.p
188705.23/24874.50	% SZS status Started for HL411923+5.p
188705.23/24874.50	% SZS status GaveUp for HL411923+5.p
188705.23/24874.50	eprover: CPU time limit exceeded, terminating
188705.23/24874.50	% SZS status Ended for HL411923+5.p
188713.00/24875.49	% SZS status Started for HL411924+5.p
188713.00/24875.49	% SZS status GaveUp for HL411924+5.p
188713.00/24875.49	eprover: CPU time limit exceeded, terminating
188713.00/24875.49	% SZS status Ended for HL411924+5.p
188713.00/24875.51	% SZS status Started for HL411948+4.p
188713.00/24875.51	% SZS status GaveUp for HL411948+4.p
188713.00/24875.51	eprover: CPU time limit exceeded, terminating
188713.00/24875.51	% SZS status Ended for HL411948+4.p
188729.03/24877.58	% SZS status Started for HL411950+4.p
188729.03/24877.58	% SZS status GaveUp for HL411950+4.p
188729.03/24877.58	eprover: CPU time limit exceeded, terminating
188729.03/24877.58	% SZS status Ended for HL411950+4.p
188729.70/24877.69	% SZS status Started for HL411935+5.p
188729.70/24877.69	% SZS status GaveUp for HL411935+5.p
188729.70/24877.69	eprover: CPU time limit exceeded, terminating
188729.70/24877.69	% SZS status Ended for HL411935+5.p
188737.56/24878.58	% SZS status Started for HL411951+4.p
188737.56/24878.58	% SZS status GaveUp for HL411951+4.p
188737.56/24878.58	eprover: CPU time limit exceeded, terminating
188737.56/24878.58	% SZS status Ended for HL411951+4.p
188739.69/24878.87	% SZS status Started for HL411938+5.p
188739.69/24878.87	% SZS status GaveUp for HL411938+5.p
188739.69/24878.87	eprover: CPU time limit exceeded, terminating
188739.69/24878.87	% SZS status Ended for HL411938+5.p
188754.73/24880.71	% SZS status Started for HL411952+4.p
188754.73/24880.71	% SZS status GaveUp for HL411952+4.p
188754.73/24880.71	eprover: CPU time limit exceeded, terminating
188754.73/24880.71	% SZS status Ended for HL411952+4.p
188758.34/24881.35	% SZS status Started for HL411944+5.p
188758.34/24881.35	% SZS status GaveUp for HL411944+5.p
188758.34/24881.35	eprover: CPU time limit exceeded, terminating
188758.34/24881.35	% SZS status Ended for HL411944+5.p
188761.91/24881.70	% SZS status Started for HL411952+5.p
188761.91/24881.70	% SZS status GaveUp for HL411952+5.p
188761.91/24881.70	eprover: CPU time limit exceeded, terminating
188761.91/24881.70	% SZS status Ended for HL411952+5.p
188763.42/24881.93	% SZS status Started for HL411953+4.p
188763.42/24881.93	% SZS status GaveUp for HL411953+4.p
188763.42/24881.93	eprover: CPU time limit exceeded, terminating
188763.42/24881.93	% SZS status Ended for HL411953+4.p
188766.88/24882.33	% SZS status Started for HL411947+5.p
188766.88/24882.33	% SZS status GaveUp for HL411947+5.p
188766.88/24882.33	eprover: CPU time limit exceeded, terminating
188766.88/24882.33	% SZS status Ended for HL411947+5.p
188779.03/24883.76	% SZS status Started for HL411953+5.p
188779.03/24883.76	% SZS status GaveUp for HL411953+5.p
188779.03/24883.76	eprover: CPU time limit exceeded, terminating
188779.03/24883.76	% SZS status Ended for HL411953+5.p
188781.81/24884.18	% SZS status Started for HL411948+5.p
188781.81/24884.18	% SZS status GaveUp for HL411948+5.p
188781.81/24884.18	eprover: CPU time limit exceeded, terminating
188781.81/24884.18	% SZS status Ended for HL411948+5.p
188783.69/24884.38	% SZS status Started for HL411959+4.p
188783.69/24884.38	% SZS status GaveUp for HL411959+4.p
188783.69/24884.38	eprover: CPU time limit exceeded, terminating
188783.69/24884.38	% SZS status Ended for HL411959+4.p
188787.53/24885.05	% SZS status Started for HL411962+4.p
188787.53/24885.05	% SZS status GaveUp for HL411962+4.p
188787.53/24885.05	eprover: CPU time limit exceeded, terminating
188787.53/24885.05	% SZS status Ended for HL411962+4.p
188791.30/24885.39	% SZS status Started for HL411962+5.p
188791.30/24885.39	% SZS status GaveUp for HL411962+5.p
188791.30/24885.39	eprover: CPU time limit exceeded, terminating
188791.30/24885.39	% SZS status Ended for HL411962+5.p
188798.95/24886.29	% SZS status Started for HL411950+5.p
188798.95/24886.29	% SZS status GaveUp for HL411950+5.p
188798.95/24886.29	eprover: CPU time limit exceeded, terminating
188798.95/24886.29	% SZS status Ended for HL411950+5.p
188803.05/24886.79	% SZS status Started for HL411963+4.p
188803.05/24886.79	% SZS status GaveUp for HL411963+4.p
188803.05/24886.79	eprover: CPU time limit exceeded, terminating
188803.05/24886.79	% SZS status Ended for HL411963+4.p
188807.84/24887.45	% SZS status Started for HL411980+4.p
188807.84/24887.45	% SZS status GaveUp for HL411980+4.p
188807.84/24887.45	eprover: CPU time limit exceeded, terminating
188807.84/24887.45	% SZS status Ended for HL411980+4.p
188815.36/24888.35	% SZS status Started for HL411951+5.p
188815.36/24888.35	% SZS status GaveUp for HL411951+5.p
188815.36/24888.35	eprover: CPU time limit exceeded, terminating
188815.36/24888.35	% SZS status Ended for HL411951+5.p
188815.80/24888.44	% SZS status Started for HL411981+4.p
188815.80/24888.44	% SZS status GaveUp for HL411981+4.p
188815.80/24888.44	eprover: CPU time limit exceeded, terminating
188815.80/24888.44	% SZS status Ended for HL411981+4.p
188823.38/24889.37	% SZS status Started for HL411981+5.p
188823.38/24889.37	% SZS status GaveUp for HL411981+5.p
188823.38/24889.37	eprover: CPU time limit exceeded, terminating
188823.38/24889.37	% SZS status Ended for HL411981+5.p
188826.62/24889.84	% SZS status Started for HL411989+4.p
188826.62/24889.84	% SZS status GaveUp for HL411989+4.p
188826.62/24889.84	eprover: CPU time limit exceeded, terminating
188826.62/24889.84	% SZS status Ended for HL411989+4.p
188838.66/24891.38	% SZS status Started for HL412000+4.p
188838.66/24891.38	% SZS status GaveUp for HL412000+4.p
188838.66/24891.38	eprover: CPU time limit exceeded, terminating
188838.66/24891.38	% SZS status Ended for HL412000+4.p
188847.17/24892.42	% SZS status Started for HL412002+4.p
188847.17/24892.42	% SZS status GaveUp for HL412002+4.p
188847.17/24892.42	eprover: CPU time limit exceeded, terminating
188847.17/24892.42	% SZS status Ended for HL412002+4.p
188849.47/24892.69	% SZS status Started for HL411959+5.p
188849.47/24892.69	% SZS status GaveUp for HL411959+5.p
188849.47/24892.69	eprover: CPU time limit exceeded, terminating
188849.47/24892.69	% SZS status Ended for HL411959+5.p
188863.42/24894.42	% SZS status Started for HL412010+4.p
188863.42/24894.42	% SZS status GaveUp for HL412010+4.p
188863.42/24894.42	eprover: CPU time limit exceeded, terminating
188863.42/24894.42	% SZS status Ended for HL412010+4.p
188867.77/24894.97	% SZS status Started for HL411963+5.p
188867.77/24894.97	% SZS status GaveUp for HL411963+5.p
188867.77/24894.97	eprover: CPU time limit exceeded, terminating
188867.77/24894.97	% SZS status Ended for HL411963+5.p
188871.75/24895.48	% SZS status Started for HL412010+5.p
188871.75/24895.48	% SZS status GaveUp for HL412010+5.p
188871.75/24895.48	eprover: CPU time limit exceeded, terminating
188871.75/24895.48	% SZS status Ended for HL412010+5.p
188873.36/24895.73	% SZS status Started for HL412021+4.p
188873.36/24895.73	% SZS status GaveUp for HL412021+4.p
188873.36/24895.73	eprover: CPU time limit exceeded, terminating
188873.36/24895.73	% SZS status Ended for HL412021+4.p
188874.88/24896.04	% SZS status Started for HL411980+5.p
188874.88/24896.04	% SZS status GaveUp for HL411980+5.p
188874.88/24896.04	eprover: CPU time limit exceeded, terminating
188874.88/24896.04	% SZS status Ended for HL411980+5.p
188891.91/24898.01	% SZS status Started for HL412022+4.p
188891.91/24898.01	% SZS status GaveUp for HL412022+4.p
188891.91/24898.01	eprover: CPU time limit exceeded, terminating
188891.91/24898.01	% SZS status Ended for HL412022+4.p
188893.58/24898.29	% SZS status Started for HL411989+5.p
188893.58/24898.29	% SZS status GaveUp for HL411989+5.p
188893.58/24898.29	eprover: CPU time limit exceeded, terminating
188893.58/24898.29	% SZS status Ended for HL411989+5.p
188896.97/24898.75	% SZS status Started for HL412027+4.p
188896.97/24898.75	% SZS status GaveUp for HL412027+4.p
188896.97/24898.75	eprover: CPU time limit exceeded, terminating
188896.97/24898.75	% SZS status Ended for HL412027+4.p
188902.56/24899.42	% SZS status Started for HL412000+5.p
188902.56/24899.42	% SZS status GaveUp for HL412000+5.p
188902.56/24899.42	eprover: CPU time limit exceeded, terminating
188902.56/24899.42	% SZS status Ended for HL412000+5.p
188912.47/24900.59	% SZS status Started for HL412002+5.p
188912.47/24900.59	% SZS status GaveUp for HL412002+5.p
188912.47/24900.59	eprover: CPU time limit exceeded, terminating
188912.47/24900.59	% SZS status Ended for HL412002+5.p
188916.12/24901.05	% SZS status Started for HL412030+4.p
188916.12/24901.05	% SZS status GaveUp for HL412030+4.p
188916.12/24901.05	eprover: CPU time limit exceeded, terminating
188916.12/24901.05	% SZS status Ended for HL412030+4.p
188921.73/24901.78	% SZS status Started for HL412052+4.p
188921.73/24901.78	% SZS status GaveUp for HL412052+4.p
188921.73/24901.78	eprover: CPU time limit exceeded, terminating
188921.73/24901.78	% SZS status Ended for HL412052+4.p
188936.97/24903.69	% SZS status Started for HL412058+4.p
188936.97/24903.69	% SZS status GaveUp for HL412058+4.p
188936.97/24903.69	eprover: CPU time limit exceeded, terminating
188936.97/24903.69	% SZS status Ended for HL412058+4.p
188946.19/24904.86	% SZS status Started for HL412059+4.p
188946.19/24904.86	% SZS status GaveUp for HL412059+4.p
188946.19/24904.86	eprover: CPU time limit exceeded, terminating
188946.19/24904.86	% SZS status Ended for HL412059+4.p
188949.41/24905.26	% SZS status Started for HL412021+5.p
188949.41/24905.26	% SZS status GaveUp for HL412021+5.p
188949.41/24905.26	eprover: CPU time limit exceeded, terminating
188949.41/24905.26	% SZS status Ended for HL412021+5.p
188958.27/24906.38	% SZS status Started for HL412022+5.p
188958.27/24906.38	% SZS status GaveUp for HL412022+5.p
188958.27/24906.38	eprover: CPU time limit exceeded, terminating
188958.27/24906.38	% SZS status Ended for HL412022+5.p
188960.94/24906.76	% SZS status Started for HL412059+5.p
188960.94/24906.76	% SZS status GaveUp for HL412059+5.p
188960.94/24906.76	eprover: CPU time limit exceeded, terminating
188960.94/24906.76	% SZS status Ended for HL412059+5.p
188962.86/24906.97	% SZS status Started for HL412027+5.p
188962.86/24906.97	% SZS status GaveUp for HL412027+5.p
188962.86/24906.97	eprover: CPU time limit exceeded, terminating
188962.86/24906.97	% SZS status Ended for HL412027+5.p
188970.08/24907.91	% SZS status Started for HL412060+4.p
188970.08/24907.91	% SZS status GaveUp for HL412060+4.p
188970.08/24907.91	eprover: CPU time limit exceeded, terminating
188970.08/24907.91	% SZS status Ended for HL412060+4.p
188979.78/24909.07	% SZS status Started for HL412030+5.p
188979.78/24909.07	% SZS status GaveUp for HL412030+5.p
188979.78/24909.07	eprover: CPU time limit exceeded, terminating
188979.78/24909.07	% SZS status Ended for HL412030+5.p
188981.80/24909.42	% SZS status Started for HL412061+4.p
188981.80/24909.42	% SZS status GaveUp for HL412061+4.p
188981.80/24909.42	eprover: CPU time limit exceeded, terminating
188981.80/24909.42	% SZS status Ended for HL412061+4.p
188985.25/24909.79	% SZS status Started for HL412061+5.p
188985.25/24909.79	% SZS status GaveUp for HL412061+5.p
188985.25/24909.79	eprover: CPU time limit exceeded, terminating
188985.25/24909.79	% SZS status Ended for HL412061+5.p
188987.34/24910.05	% SZS status Started for HL412063+4.p
188987.34/24910.05	% SZS status GaveUp for HL412063+4.p
188987.34/24910.05	eprover: CPU time limit exceeded, terminating
188987.34/24910.05	% SZS status Ended for HL412063+4.p
188988.64/24910.25	% SZS status Started for HL412052+5.p
188988.64/24910.25	% SZS status GaveUp for HL412052+5.p
188988.64/24910.25	eprover: CPU time limit exceeded, terminating
188988.64/24910.25	% SZS status Ended for HL412052+5.p
189003.47/24912.09	% SZS status Started for HL412064+4.p
189003.47/24912.09	% SZS status GaveUp for HL412064+4.p
189003.47/24912.09	eprover: CPU time limit exceeded, terminating
189003.47/24912.09	% SZS status Ended for HL412064+4.p
189004.16/24912.16	% SZS status Started for HL412058+5.p
189004.16/24912.16	% SZS status GaveUp for HL412058+5.p
189004.16/24912.16	eprover: CPU time limit exceeded, terminating
189004.16/24912.16	% SZS status Ended for HL412058+5.p
189009.36/24912.84	% SZS status Started for HL412065+4.p
189009.36/24912.84	% SZS status GaveUp for HL412065+4.p
189009.36/24912.84	eprover: CPU time limit exceeded, terminating
189009.36/24912.84	% SZS status Ended for HL412065+4.p
189012.83/24913.29	% SZS status Started for HL412066+4.p
189012.83/24913.29	% SZS status GaveUp for HL412066+4.p
189012.83/24913.29	eprover: CPU time limit exceeded, terminating
189012.83/24913.29	% SZS status Ended for HL412066+4.p
189027.16/24915.25	% SZS status Started for HL412067+4.p
189027.16/24915.25	% SZS status GaveUp for HL412067+4.p
189027.16/24915.25	eprover: CPU time limit exceeded, terminating
189027.16/24915.25	% SZS status Ended for HL412067+4.p
189035.06/24916.11	% SZS status Started for HL412060+5.p
189035.06/24916.11	% SZS status GaveUp for HL412060+5.p
189035.06/24916.11	eprover: CPU time limit exceeded, terminating
189035.06/24916.11	% SZS status Ended for HL412060+5.p
189036.36/24916.35	% SZS status Started for HL412068+4.p
189036.36/24916.35	% SZS status GaveUp for HL412068+4.p
189036.36/24916.35	eprover: CPU time limit exceeded, terminating
189036.36/24916.35	% SZS status Ended for HL412068+4.p
189057.62/24918.93	% SZS status Started for HL412063+5.p
189057.62/24918.93	% SZS status GaveUp for HL412063+5.p
189057.62/24918.93	eprover: CPU time limit exceeded, terminating
189057.62/24918.93	% SZS status Ended for HL412063+5.p
189058.50/24919.13	% SZS status Started for HL412069+4.p
189058.50/24919.13	% SZS status GaveUp for HL412069+4.p
189058.50/24919.13	eprover: CPU time limit exceeded, terminating
189058.50/24919.13	% SZS status Ended for HL412069+4.p
189069.52/24920.40	% SZS status Started for HL412064+5.p
189069.52/24920.40	% SZS status GaveUp for HL412064+5.p
189069.52/24920.40	eprover: CPU time limit exceeded, terminating
189069.52/24920.40	% SZS status Ended for HL412064+5.p
189074.53/24921.04	% SZS status Started for HL412065+5.p
189074.53/24921.04	% SZS status GaveUp for HL412065+5.p
189074.53/24921.04	eprover: CPU time limit exceeded, terminating
189074.53/24921.04	% SZS status Ended for HL412065+5.p
189081.81/24921.99	% SZS status Started for HL412070+4.p
189081.81/24921.99	% SZS status GaveUp for HL412070+4.p
189081.81/24921.99	eprover: CPU time limit exceeded, terminating
189081.81/24921.99	% SZS status Ended for HL412070+4.p
189089.89/24923.03	% SZS status Started for HL412066+5.p
189089.89/24923.03	% SZS status GaveUp for HL412066+5.p
189089.89/24923.03	eprover: CPU time limit exceeded, terminating
189089.89/24923.03	% SZS status Ended for HL412066+5.p
189093.16/24923.42	% SZS status Started for HL412071+4.p
189093.16/24923.42	% SZS status GaveUp for HL412071+4.p
189093.16/24923.42	eprover: CPU time limit exceeded, terminating
189093.16/24923.42	% SZS status Ended for HL412071+4.p
189096.91/24923.84	% SZS status Started for HL412067+5.p
189096.91/24923.84	% SZS status GaveUp for HL412067+5.p
189096.91/24923.84	eprover: CPU time limit exceeded, terminating
189096.91/24923.84	% SZS status Ended for HL412067+5.p
189106.23/24925.02	% SZS status Started for HL412073+4.p
189106.23/24925.02	% SZS status GaveUp for HL412073+4.p
189106.23/24925.02	eprover: CPU time limit exceeded, terminating
189106.23/24925.02	% SZS status Ended for HL412073+4.p
189116.25/24926.45	% SZS status Started for HL412068+5.p
189116.25/24926.45	% SZS status GaveUp for HL412068+5.p
189116.25/24926.45	eprover: CPU time limit exceeded, terminating
189116.25/24926.45	% SZS status Ended for HL412068+5.p
189116.25/24926.45	% SZS status Started for HL412075+4.p
189116.25/24926.45	% SZS status GaveUp for HL412075+4.p
189116.25/24926.45	eprover: CPU time limit exceeded, terminating
189116.25/24926.45	% SZS status Ended for HL412075+4.p
189123.12/24927.22	% SZS status Started for HL412069+5.p
189123.12/24927.22	% SZS status GaveUp for HL412069+5.p
189123.12/24927.22	eprover: CPU time limit exceeded, terminating
189123.12/24927.22	% SZS status Ended for HL412069+5.p
189129.94/24928.05	% SZS status Started for HL412077+4.p
189129.94/24928.05	% SZS status GaveUp for HL412077+4.p
189129.94/24928.05	eprover: CPU time limit exceeded, terminating
189129.94/24928.05	% SZS status Ended for HL412077+4.p
189141.77/24929.52	% SZS status Started for HL412078+4.p
189141.77/24929.52	% SZS status GaveUp for HL412078+4.p
189141.77/24929.52	eprover: CPU time limit exceeded, terminating
189141.77/24929.52	% SZS status Ended for HL412078+4.p
189145.34/24929.96	% SZS status Started for HL412070+5.p
189145.34/24929.96	% SZS status GaveUp for HL412070+5.p
189145.34/24929.96	eprover: CPU time limit exceeded, terminating
189145.34/24929.96	% SZS status Ended for HL412070+5.p
189154.44/24931.08	% SZS status Started for HL412079+4.p
189154.44/24931.08	% SZS status GaveUp for HL412079+4.p
189154.44/24931.08	eprover: CPU time limit exceeded, terminating
189154.44/24931.08	% SZS status Ended for HL412079+4.p
189163.56/24932.23	% SZS status Started for HL412071+5.p
189163.56/24932.23	% SZS status GaveUp for HL412071+5.p
189163.56/24932.23	eprover: CPU time limit exceeded, terminating
189163.56/24932.23	% SZS status Ended for HL412071+5.p
189169.39/24933.01	% SZS status Started for HL412080+4.p
189169.39/24933.01	% SZS status GaveUp for HL412080+4.p
189169.39/24933.01	eprover: CPU time limit exceeded, terminating
189169.39/24933.01	% SZS status Ended for HL412080+4.p
189176.94/24933.95	% SZS status Started for HL412073+5.p
189176.94/24933.95	% SZS status GaveUp for HL412073+5.p
189176.94/24933.95	eprover: CPU time limit exceeded, terminating
189176.94/24933.95	% SZS status Ended for HL412073+5.p
189184.91/24934.96	% SZS status Started for HL412075+5.p
189184.91/24934.96	% SZS status GaveUp for HL412075+5.p
189184.91/24934.96	eprover: CPU time limit exceeded, terminating
189184.91/24934.96	% SZS status Ended for HL412075+5.p
189186.72/24935.27	% SZS status Started for HL412081+4.p
189186.72/24935.27	% SZS status GaveUp for HL412081+4.p
189186.72/24935.27	eprover: CPU time limit exceeded, terminating
189186.72/24935.27	% SZS status Ended for HL412081+4.p
189201.22/24937.01	% SZS status Started for HL412082+4.p
189201.22/24937.01	% SZS status GaveUp for HL412082+4.p
189201.22/24937.01	eprover: CPU time limit exceeded, terminating
189201.22/24937.01	% SZS status Ended for HL412082+4.p
189202.47/24937.28	% SZS status Started for HL412077+5.p
189202.47/24937.28	% SZS status GaveUp for HL412077+5.p
189202.47/24937.28	eprover: CPU time limit exceeded, terminating
189202.47/24937.28	% SZS status Ended for HL412077+5.p
189210.00/24938.11	% SZS status Started for HL412078+5.p
189210.00/24938.11	% SZS status GaveUp for HL412078+5.p
189210.00/24938.11	eprover: CPU time limit exceeded, terminating
189210.00/24938.11	% SZS status Ended for HL412078+5.p
189211.20/24938.30	% SZS status Started for HL412083+4.p
189211.20/24938.30	% SZS status GaveUp for HL412083+4.p
189211.20/24938.30	eprover: CPU time limit exceeded, terminating
189211.20/24938.30	% SZS status Ended for HL412083+4.p
189227.83/24940.36	% SZS status Started for HL412084+4.p
189227.83/24940.36	% SZS status GaveUp for HL412084+4.p
189227.83/24940.36	eprover: CPU time limit exceeded, terminating
189227.83/24940.36	% SZS status Ended for HL412084+4.p
189228.45/24940.48	% SZS status Started for HL412079+5.p
189228.45/24940.48	% SZS status GaveUp for HL412079+5.p
189228.45/24940.48	eprover: CPU time limit exceeded, terminating
189228.45/24940.48	% SZS status Ended for HL412079+5.p
189233.78/24941.33	% SZS status Started for HL412085+4.p
189233.78/24941.33	% SZS status GaveUp for HL412085+4.p
189233.78/24941.33	eprover: CPU time limit exceeded, terminating
189233.78/24941.33	% SZS status Ended for HL412085+4.p
189241.12/24942.02	% SZS status Started for HL412080+5.p
189241.12/24942.02	% SZS status GaveUp for HL412080+5.p
189241.12/24942.02	eprover: CPU time limit exceeded, terminating
189241.12/24942.02	% SZS status Ended for HL412080+5.p
189250.61/24943.41	% SZS status Started for HL412085+5.p
189250.61/24943.41	% SZS status GaveUp for HL412085+5.p
189250.61/24943.41	eprover: CPU time limit exceeded, terminating
189250.61/24943.41	% SZS status Ended for HL412085+5.p
189253.16/24943.56	% SZS status Started for HL412086+4.p
189253.16/24943.56	% SZS status GaveUp for HL412086+4.p
189253.16/24943.56	eprover: CPU time limit exceeded, terminating
189253.16/24943.56	% SZS status Ended for HL412086+4.p
189255.23/24943.84	% SZS status Started for HL412081+5.p
189255.23/24943.84	% SZS status GaveUp for HL412081+5.p
189255.23/24943.84	eprover: CPU time limit exceeded, terminating
189255.23/24943.84	% SZS status Ended for HL412081+5.p
189265.25/24945.09	% SZS status Started for HL412087+4.p
189265.25/24945.09	% SZS status GaveUp for HL412087+4.p
189265.25/24945.09	eprover: CPU time limit exceeded, terminating
189265.25/24945.09	% SZS status Ended for HL412087+4.p
189271.23/24945.81	% SZS status Started for HL412082+5.p
189271.23/24945.81	% SZS status GaveUp for HL412082+5.p
189271.23/24945.81	eprover: CPU time limit exceeded, terminating
189271.23/24945.81	% SZS status Ended for HL412082+5.p
189276.72/24946.61	% SZS status Started for HL412089+4.p
189276.72/24946.61	% SZS status GaveUp for HL412089+4.p
189276.72/24946.61	eprover: CPU time limit exceeded, terminating
189276.72/24946.61	% SZS status Ended for HL412089+4.p
189287.64/24947.97	% SZS status Started for HL412083+5.p
189287.64/24947.97	% SZS status GaveUp for HL412083+5.p
189287.64/24947.97	eprover: CPU time limit exceeded, terminating
189287.64/24947.97	% SZS status Ended for HL412083+5.p
189289.53/24948.17	% SZS status Started for HL412091+4.p
189289.53/24948.17	% SZS status GaveUp for HL412091+4.p
189289.53/24948.17	eprover: CPU time limit exceeded, terminating
189289.53/24948.17	% SZS status Ended for HL412091+4.p
189295.30/24948.94	% SZS status Started for HL412084+5.p
189295.30/24948.94	% SZS status GaveUp for HL412084+5.p
189295.30/24948.94	eprover: CPU time limit exceeded, terminating
189295.30/24948.94	% SZS status Ended for HL412084+5.p
189301.11/24949.65	% SZS status Started for HL412094+4.p
189301.11/24949.65	% SZS status GaveUp for HL412094+4.p
189301.11/24949.65	eprover: CPU time limit exceeded, terminating
189301.11/24949.65	% SZS status Ended for HL412094+4.p
189313.16/24951.13	% SZS status Started for HL412094+5.p
189313.16/24951.13	% SZS status GaveUp for HL412094+5.p
189313.16/24951.13	eprover: CPU time limit exceeded, terminating
189313.16/24951.13	% SZS status Ended for HL412094+5.p
189313.80/24951.23	% SZS status Started for HL412095+4.p
189313.80/24951.23	% SZS status GaveUp for HL412095+4.p
189313.80/24951.23	eprover: CPU time limit exceeded, terminating
189313.80/24951.23	% SZS status Ended for HL412095+4.p
189320.42/24952.22	% SZS status Started for HL412086+5.p
189320.42/24952.22	% SZS status GaveUp for HL412086+5.p
189320.42/24952.22	eprover: CPU time limit exceeded, terminating
189320.42/24952.22	% SZS status Ended for HL412086+5.p
189326.39/24952.84	% SZS status Started for HL412096+4.p
189326.39/24952.84	% SZS status GaveUp for HL412096+4.p
189326.39/24952.84	eprover: CPU time limit exceeded, terminating
189326.39/24952.84	% SZS status Ended for HL412096+4.p
189338.44/24954.35	% SZS status Started for HL412104+4.p
189338.44/24954.35	% SZS status GaveUp for HL412104+4.p
189338.44/24954.35	eprover: CPU time limit exceeded, terminating
189338.44/24954.35	% SZS status Ended for HL412104+4.p
189339.12/24954.41	% SZS status Started for HL412087+5.p
189339.12/24954.41	% SZS status GaveUp for HL412087+5.p
189339.12/24954.41	eprover: CPU time limit exceeded, terminating
189339.12/24954.41	% SZS status Ended for HL412087+5.p
189341.56/24954.85	% SZS status Started for HL412089+5.p
189341.56/24954.85	% SZS status GaveUp for HL412089+5.p
189341.56/24954.85	eprover: CPU time limit exceeded, terminating
189341.56/24954.85	% SZS status Ended for HL412089+5.p
189350.20/24955.87	% SZS status Started for HL412105+4.p
189350.20/24955.87	% SZS status GaveUp for HL412105+4.p
189350.20/24955.87	eprover: CPU time limit exceeded, terminating
189350.20/24955.87	% SZS status Ended for HL412105+4.p
189358.33/24956.88	% SZS status Started for HL412091+5.p
189358.33/24956.88	% SZS status GaveUp for HL412091+5.p
189358.33/24956.88	eprover: CPU time limit exceeded, terminating
189358.33/24956.88	% SZS status Ended for HL412091+5.p
189363.03/24957.46	% SZS status Started for HL412110+4.p
189363.03/24957.46	% SZS status GaveUp for HL412110+4.p
189363.03/24957.46	eprover: CPU time limit exceeded, terminating
189363.03/24957.46	% SZS status Ended for HL412110+4.p
189374.91/24958.94	% SZS status Started for HL412111+4.p
189374.91/24958.94	% SZS status GaveUp for HL412111+4.p
189374.91/24958.94	eprover: CPU time limit exceeded, terminating
189374.91/24958.94	% SZS status Ended for HL412111+4.p
189381.98/24959.87	% SZS status Started for HL412095+5.p
189381.98/24959.87	% SZS status GaveUp for HL412095+5.p
189381.98/24959.87	eprover: CPU time limit exceeded, terminating
189381.98/24959.87	% SZS status Ended for HL412095+5.p
189388.30/24960.59	% SZS status Started for HL412118+4.p
189388.30/24960.59	% SZS status GaveUp for HL412118+4.p
189388.30/24960.59	eprover: CPU time limit exceeded, terminating
189388.30/24960.59	% SZS status Ended for HL412118+4.p
189398.73/24962.09	% SZS status Started for HL412096+5.p
189398.73/24962.09	% SZS status GaveUp for HL412096+5.p
189398.73/24962.09	eprover: CPU time limit exceeded, terminating
189398.73/24962.09	% SZS status Ended for HL412096+5.p
189406.59/24962.91	% SZS status Started for HL412119+4.p
189406.59/24962.91	% SZS status GaveUp for HL412119+4.p
189406.59/24962.91	eprover: CPU time limit exceeded, terminating
189406.59/24962.91	% SZS status Ended for HL412119+4.p
189407.34/24963.03	% SZS status Started for HL412104+5.p
189407.34/24963.03	% SZS status GaveUp for HL412104+5.p
189407.34/24963.03	eprover: CPU time limit exceeded, terminating
189407.34/24963.03	% SZS status Ended for HL412104+5.p
189424.14/24965.16	% SZS status Started for HL412120+4.p
189424.14/24965.16	% SZS status GaveUp for HL412120+4.p
189424.14/24965.16	eprover: CPU time limit exceeded, terminating
189424.14/24965.16	% SZS status Ended for HL412120+4.p
189424.81/24965.25	% SZS status Started for HL412105+5.p
189424.81/24965.25	% SZS status GaveUp for HL412105+5.p
189424.81/24965.25	eprover: CPU time limit exceeded, terminating
189424.81/24965.25	% SZS status Ended for HL412105+5.p
189428.86/24965.74	% SZS status Started for HL412110+5.p
189428.86/24965.74	% SZS status GaveUp for HL412110+5.p
189428.86/24965.74	eprover: CPU time limit exceeded, terminating
189428.86/24965.74	% SZS status Ended for HL412110+5.p
189430.45/24966.09	% SZS status Started for HL412126+4.p
189430.45/24966.09	% SZS status GaveUp for HL412126+4.p
189430.45/24966.09	eprover: CPU time limit exceeded, terminating
189430.45/24966.09	% SZS status Ended for HL412126+4.p
189445.88/24967.95	% SZS status Started for HL412111+5.p
189445.88/24967.95	% SZS status GaveUp for HL412111+5.p
189445.88/24967.95	eprover: CPU time limit exceeded, terminating
189445.88/24967.95	% SZS status Ended for HL412111+5.p
189449.02/24968.33	% SZS status Started for HL412128+4.p
189449.02/24968.33	% SZS status GaveUp for HL412128+4.p
189449.02/24968.33	eprover: CPU time limit exceeded, terminating
189449.02/24968.33	% SZS status Ended for HL412128+4.p
189455.33/24969.18	% SZS status Started for HL412129+4.p
189455.33/24969.18	% SZS status GaveUp for HL412129+4.p
189455.33/24969.18	eprover: CPU time limit exceeded, terminating
189455.33/24969.18	% SZS status Ended for HL412129+4.p
189461.86/24969.90	% SZS status Started for HL412118+5.p
189461.86/24969.90	% SZS status GaveUp for HL412118+5.p
189461.86/24969.90	eprover: CPU time limit exceeded, terminating
189461.86/24969.90	% SZS status Ended for HL412118+5.p
189473.52/24971.39	% SZS status Started for HL412131+4.p
189473.52/24971.39	% SZS status GaveUp for HL412131+4.p
189473.52/24971.39	eprover: CPU time limit exceeded, terminating
189473.52/24971.39	% SZS status Ended for HL412131+4.p
189475.50/24971.61	% SZS status Started for HL412119+5.p
189475.50/24971.61	% SZS status GaveUp for HL412119+5.p
189475.50/24971.61	eprover: CPU time limit exceeded, terminating
189475.50/24971.61	% SZS status Ended for HL412119+5.p
189485.66/24972.94	% SZS status Started for HL412132+4.p
189485.66/24972.94	% SZS status GaveUp for HL412132+4.p
189485.66/24972.94	eprover: CPU time limit exceeded, terminating
189485.66/24972.94	% SZS status Ended for HL412132+4.p
189492.34/24973.80	% SZS status Started for HL412120+5.p
189492.34/24973.80	% SZS status GaveUp for HL412120+5.p
189492.34/24973.80	eprover: CPU time limit exceeded, terminating
189492.34/24973.80	% SZS status Ended for HL412120+5.p
189499.58/24974.65	% SZS status Started for HL412133+4.p
189499.58/24974.65	% SZS status GaveUp for HL412133+4.p
189499.58/24974.65	eprover: CPU time limit exceeded, terminating
189499.58/24974.65	% SZS status Ended for HL412133+4.p
189512.38/24976.30	% SZS status Started for HL412126+5.p
189512.38/24976.30	% SZS status GaveUp for HL412126+5.p
189512.38/24976.30	eprover: CPU time limit exceeded, terminating
189512.38/24976.30	% SZS status Ended for HL412126+5.p
189514.56/24976.54	% SZS status Started for HL412128+5.p
189514.56/24976.54	% SZS status GaveUp for HL412128+5.p
189514.56/24976.54	eprover: CPU time limit exceeded, terminating
189514.56/24976.54	% SZS status Ended for HL412128+5.p
189516.48/24976.84	% SZS status Started for HL412134+4.p
189516.48/24976.84	% SZS status GaveUp for HL412134+4.p
189516.48/24976.84	eprover: CPU time limit exceeded, terminating
189516.48/24976.84	% SZS status Ended for HL412134+4.p
189533.89/24978.98	% SZS status Started for HL412129+5.p
189533.89/24978.98	% SZS status GaveUp for HL412129+5.p
189533.89/24978.98	eprover: CPU time limit exceeded, terminating
189533.89/24978.98	% SZS status Ended for HL412129+5.p
189537.36/24979.42	% SZS status Started for HL412135+4.p
189537.36/24979.42	% SZS status GaveUp for HL412135+4.p
189537.36/24979.42	eprover: CPU time limit exceeded, terminating
189537.36/24979.42	% SZS status Ended for HL412135+4.p
189538.31/24979.59	% SZS status Started for HL412135+5.p
189538.31/24979.59	% SZS status GaveUp for HL412135+5.p
189538.31/24979.59	eprover: CPU time limit exceeded, terminating
189538.31/24979.59	% SZS status Ended for HL412135+5.p
189539.81/24979.88	% SZS status Started for HL412136+4.p
189539.81/24979.88	% SZS status GaveUp for HL412136+4.p
189539.81/24979.88	eprover: CPU time limit exceeded, terminating
189539.81/24979.88	% SZS status Ended for HL412136+4.p
189541.86/24980.18	% SZS status Started for HL412131+5.p
189541.86/24980.18	% SZS status GaveUp for HL412131+5.p
189541.86/24980.18	eprover: CPU time limit exceeded, terminating
189541.86/24980.18	% SZS status Ended for HL412131+5.p
189550.52/24982.30	% SZS status Started for HL412132+5.p
189550.52/24982.30	% SZS status GaveUp for HL412132+5.p
189550.52/24982.30	eprover: CPU time limit exceeded, terminating
189550.52/24982.30	% SZS status Ended for HL412132+5.p
189554.67/24983.76	% SZS status Started for HL412133+5.p
189554.67/24983.76	% SZS status GaveUp for HL412133+5.p
189554.67/24983.76	eprover: CPU time limit exceeded, terminating
189554.67/24983.76	% SZS status Ended for HL412133+5.p
189558.52/24985.49	% SZS status Started for HL412134+5.p
189558.52/24985.49	% SZS status GaveUp for HL412134+5.p
189558.52/24985.49	eprover: CPU time limit exceeded, terminating
189558.52/24985.49	% SZS status Ended for HL412134+5.p
189562.91/24989.76	% SZS status Started for HL412136+5.p
189562.91/24989.76	% SZS status GaveUp for HL412136+5.p
189562.91/24989.76	eprover: CPU time limit exceeded, terminating
189562.91/24989.76	% SZS status Ended for HL412136+5.p
1294137.12/172800.02	EOF