TSTP Solution File: SYN537+1 by Refute---2015
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%------------------------------------------------------------------------------
% File : Refute---2015
% Problem : SYN537+1 : TPTP v6.4.0. Released v2.1.0.
% Transfm : none
% Format : tptp:raw
% Command : isabelle tptp_refute %d %s
% Computer : n106.star.cs.uiowa.edu
% Model : x86_64 x86_64
% CPU : Intel(R) Xeon(R) CPU E5-2609 0 2.40GHz
% Memory : 32218.75MB
% OS : Linux 3.10.0-327.10.1.el7.x86_64
% CPULimit : 300s
% DateTime : Thu Apr 14 06:42:18 EDT 2016
% Result : CounterSatisfiable 22.23s
% Output : Assurance 0s
% Verified :
% SZS Type : None (Parsing solution fails)
% Syntax : Number of formulae : 0
% Comments :
%------------------------------------------------------------------------------
%----No solution output by system
%------------------------------------------------------------------------------
%----ORIGINAL SYSTEM OUTPUT
% 0.00/0.03 % Problem : SYN537+1 : TPTP v6.4.0. Released v2.1.0.
% 0.00/0.04 % Command : isabelle tptp_refute %d %s
% 0.02/0.23 % Computer : n106.star.cs.uiowa.edu
% 0.02/0.23 % Model : x86_64 x86_64
% 0.02/0.23 % CPU : Intel(R) Xeon(R) CPU E5-2609 0 @ 2.40GHz
% 0.02/0.23 % Memory : 32218.75MB
% 0.02/0.23 % OS : Linux 3.10.0-327.10.1.el7.x86_64
% 0.02/0.23 % CPULimit : 300
% 0.02/0.23 % DateTime : Sat Apr 9 00:15:09 CDT 2016
% 0.02/0.23 % CPUTime:
% 6.30/5.84 > val it = (): unit
% 6.60/6.18 Trying to find a model that refutes: ~ ((((((((((((((((((((((((((((((((ALL U.
% 6.60/6.18 bnd_ndr1_0 -->
% 6.60/6.18 (bnd_c1_1 U |
% 6.60/6.18 ((bnd_ndr1_1 U & bnd_c2_2 U bnd_a640) & ~ bnd_c5_2 U bnd_a640) &
% 6.60/6.18 bnd_c3_2 U bnd_a640) |
% 6.60/6.18 (ALL V.
% 6.60/6.18 bnd_ndr1_1 U --> (~ bnd_c2_2 U V | ~ bnd_c1_2 U V) | bnd_c3_2 U V)) |
% 6.60/6.18 (ALL W.
% 6.60/6.18 bnd_ndr1_0 -->
% 6.60/6.18 (~ bnd_c1_1 W | ~ bnd_c5_1 W) |
% 6.60/6.18 bnd_c3_1 W)) |
% 6.60/6.18 ~ bnd_c5_0) &
% 6.60/6.18 ((~ bnd_c3_0 | ~ bnd_c4_0) |
% 6.60/6.18 (((bnd_ndr1_0 & bnd_ndr1_1 bnd_a641) &
% 6.60/6.18 ~ bnd_c1_2 bnd_a641 bnd_a642) &
% 6.60/6.18 ~ bnd_c3_2 bnd_a641 bnd_a642) &
% 6.60/6.18 (ALL X.
% 6.60/6.18 bnd_ndr1_1 bnd_a641 -->
% 6.60/6.18 (~ bnd_c4_2 bnd_a641 X |
% 6.60/6.18 ~ bnd_c5_2 bnd_a641 X) |
% 6.60/6.18 bnd_c3_2 bnd_a641 X))) &
% 6.60/6.18 ((~ bnd_c4_0 | ~ bnd_c1_0) | ~ bnd_c2_0)) &
% 6.60/6.18 ((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a643) &
% 6.60/6.18 ~ bnd_c2_2 bnd_a643 bnd_a644) &
% 6.60/6.18 bnd_c5_2 bnd_a643 bnd_a644) &
% 6.60/6.18 ~ bnd_c1_1 bnd_a643) &
% 6.60/6.18 bnd_c4_1 bnd_a643 |
% 6.60/6.18 (((((bnd_ndr1_0 & ~ bnd_c1_1 bnd_a645) &
% 6.60/6.18 bnd_ndr1_1 bnd_a645) &
% 6.60/6.18 bnd_c3_2 bnd_a645 bnd_a646) &
% 6.60/6.18 bnd_c2_2 bnd_a645 bnd_a646) &
% 6.60/6.18 ~ bnd_c5_2 bnd_a645 bnd_a646) &
% 6.60/6.18 ~ bnd_c2_1 bnd_a645) |
% 6.60/6.18 ~ bnd_c3_0)) &
% 6.60/6.18 (((ALL Y.
% 6.60/6.18 bnd_ndr1_0 -->
% 6.60/6.18 (~ bnd_c3_1 Y | ~ bnd_c1_1 Y) |
% 6.60/6.18 ~ bnd_c4_1 Y) |
% 6.60/6.18 ~ bnd_c2_0) |
% 6.60/6.18 bnd_c1_0)) &
% 6.60/6.18 (((ALL Z.
% 6.60/6.18 bnd_ndr1_0 -->
% 6.60/6.18 ((ALL X1.
% 6.60/6.18 bnd_ndr1_1 Z --> (~ bnd_c4_2 Z X1 | ~ bnd_c1_2 Z X1) | ~ bnd_c3_2 Z X1) |
% 6.60/6.18 bnd_c1_1 Z) |
% 6.60/6.18 bnd_c2_1 Z) |
% 6.60/6.18 ~ bnd_c3_0) |
% 6.60/6.18 bnd_c1_0)) &
% 6.60/6.18 (bnd_c5_0 | ~ bnd_c4_0)) &
% 6.60/6.18 ((bnd_c3_0 | bnd_c5_0) |
% 6.60/6.18 (ALL X2.
% 6.60/6.18 bnd_ndr1_0 -->
% 6.60/6.18 (((bnd_ndr1_1 X2 & bnd_c5_2 X2 bnd_a647) &
% 6.60/6.18 ~ bnd_c2_2 X2 bnd_a647) &
% 6.60/6.18 ~ bnd_c1_2 X2 bnd_a647 |
% 6.60/6.18 bnd_c1_1 X2) |
% 6.60/6.18 ~ bnd_c2_1 X2))) &
% 6.60/6.18 ((bnd_c4_0 |
% 6.60/6.18 (ALL X3.
% 6.60/6.18 bnd_ndr1_0 -->
% 6.60/6.18 ((ALL X4.
% 6.60/6.18 bnd_ndr1_1 X3 -->
% 6.60/6.18 ~ bnd_c1_2 X3 X4 | bnd_c4_2 X3 X4) |
% 6.60/6.18 bnd_c1_1 X3) |
% 6.60/6.18 (ALL X5.
% 6.60/6.18 bnd_ndr1_1 X3 -->
% 6.60/6.18 (bnd_c3_2 X3 X5 | ~ bnd_c1_2 X3 X5) |
% 6.60/6.18 bnd_c5_2 X3 X5))) |
% 6.60/6.18 ((bnd_ndr1_0 & ~ bnd_c3_1 bnd_a648) &
% 6.60/6.18 (ALL X6.
% 6.60/6.18 bnd_ndr1_1 bnd_a648 -->
% 6.60/6.18 ~ bnd_c1_2 bnd_a648 X6 |
% 6.60/6.18 ~ bnd_c3_2 bnd_a648 X6)) &
% 6.60/6.18 (ALL X7.
% 6.60/6.18 bnd_ndr1_1 bnd_a648 -->
% 6.60/6.18 (~ bnd_c5_2 bnd_a648 X7 |
% 6.60/6.18 bnd_c4_2 bnd_a648 X7) |
% 6.60/6.18 ~ bnd_c2_2 bnd_a648 X7))) &
% 6.60/6.18 ((ALL X8.
% 6.60/6.18 bnd_ndr1_0 -->
% 6.60/6.18 (~ bnd_c4_1 X8 |
% 6.60/6.18 ((bnd_ndr1_1 X8 & bnd_c4_2 X8 bnd_a649) &
% 6.60/6.18 bnd_c1_2 X8 bnd_a649) &
% 6.60/6.18 ~ bnd_c5_2 X8 bnd_a649) |
% 6.60/6.18 ((bnd_ndr1_1 X8 & bnd_c5_2 X8 bnd_a650) &
% 6.60/6.18 ~ bnd_c3_2 X8 bnd_a650) &
% 6.60/6.18 bnd_c4_2 X8 bnd_a650) |
% 6.60/6.18 bnd_c3_0)) &
% 6.60/6.18 ((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a651) &
% 6.60/6.18 ~ bnd_c5_2 bnd_a651 bnd_a652) &
% 6.60/6.18 bnd_c1_2 bnd_a651 bnd_a652) &
% 6.60/6.18 ~ bnd_c2_2 bnd_a651 bnd_a652) &
% 6.60/6.18 (ALL X9.
% 6.60/6.18 bnd_ndr1_1 bnd_a651 -->
% 6.60/6.18 (~ bnd_c1_2 bnd_a651 X9 |
% 6.60/6.18 bnd_c5_2 bnd_a651 X9) |
% 6.60/6.18 bnd_c3_2 bnd_a651 X9) |
% 6.60/6.18 ~ bnd_c5_0) |
% 6.60/6.18 ~ bnd_c1_0)) &
% 6.60/6.18 (((ALL X10.
% 6.60/6.18 bnd_ndr1_0 --> bnd_c5_1 X10 | bnd_c1_1 X10) |
% 6.60/6.18 ((bnd_ndr1_0 &
% 6.60/6.18 (ALL X11.
% 6.60/6.18 bnd_ndr1_1 bnd_a653 -->
% 6.60/6.18 bnd_c3_2 bnd_a653 X11 |
% 6.60/6.18 bnd_c1_2 bnd_a653 X11)) &
% 6.60/6.18 ~ bnd_c4_1 bnd_a653) &
% 6.60/6.18 ~ bnd_c1_1 bnd_a653) |
% 6.60/6.18 ~ bnd_c4_0)) &
% 6.60/6.18 (((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a654) &
% 6.60/6.18 bnd_c5_2 bnd_a654 bnd_a655) &
% 6.60/6.18 ~ bnd_c4_2 bnd_a654 bnd_a655) &
% 6.60/6.18 bnd_c3_2 bnd_a654 bnd_a655) &
% 6.60/6.18 ~ bnd_c1_1 bnd_a654) &
% 6.60/6.18 ~ bnd_c5_1 bnd_a654 |
% 6.60/6.18 (ALL X12.
% 6.60/6.18 bnd_ndr1_0 -->
% 6.60/6.18 (ALL X13.
% 6.60/6.18 bnd_ndr1_1 X12 -->
% 6.60/6.18 (bnd_c5_2 X12 X13 | ~ bnd_c4_2 X12 X13) |
% 6.60/6.18 bnd_c1_2 X12 X13))) |
% 6.60/6.18 ~ bnd_c2_0)) &
% 6.60/6.18 ((~ bnd_c1_0 |
% 6.60/6.18 (ALL X14.
% 6.60/6.18 bnd_ndr1_0 -->
% 6.60/6.18 ~ bnd_c3_1 X14 |
% 6.60/6.18 (ALL X15.
% 6.60/6.18 bnd_ndr1_1 X14 -->
% 6.60/6.18 (~ bnd_c4_2 X14 X15 | ~ bnd_c1_2 X14 X15) |
% 6.60/6.18 bnd_c3_2 X14 X15))) |
% 6.60/6.18 ~ bnd_c4_0)) &
% 6.60/6.18 (bnd_c5_0 |
% 6.60/6.18 (ALL X16.
% 6.60/6.18 bnd_ndr1_0 -->
% 6.60/6.18 (bnd_c5_1 X16 | ~ bnd_c2_1 X16) |
% 6.60/6.18 ((bnd_ndr1_1 X16 & ~ bnd_c2_2 X16 bnd_a656) &
% 6.60/6.18 ~ bnd_c1_2 X16 bnd_a656) &
% 6.60/6.18 ~ bnd_c3_2 X16 bnd_a656))) &
% 6.60/6.18 (((ALL X17.
% 6.60/6.18 bnd_ndr1_0 -->
% 6.60/6.18 bnd_c2_1 X17 |
% 6.60/6.18 ((bnd_ndr1_1 X17 & ~ bnd_c4_2 X17 bnd_a657) &
% 6.60/6.18 ~ bnd_c1_2 X17 bnd_a657) &
% 6.60/6.18 ~ bnd_c5_2 X17 bnd_a657) |
% 6.60/6.18 (ALL X18.
% 6.60/6.18 bnd_ndr1_0 -->
% 6.60/6.18 (bnd_c4_1 X18 |
% 6.60/6.18 (bnd_ndr1_1 X18 & bnd_c4_2 X18 bnd_a658) &
% 6.60/6.18 bnd_c5_2 X18 bnd_a658) |
% 6.60/6.18 (ALL X19.
% 6.60/6.18 bnd_ndr1_1 X18 -->
% 6.60/6.18 (bnd_c5_2 X18 X19 | ~ bnd_c2_2 X18 X19) |
% 6.60/6.18 bnd_c1_2 X18 X19))) |
% 6.60/6.18 bnd_c3_0)) &
% 6.60/6.18 (((bnd_ndr1_0 &
% 6.60/6.18 (ALL X20.
% 6.60/6.18 bnd_ndr1_1 bnd_a659 -->
% 6.60/6.18 (bnd_c5_2 bnd_a659 X20 | ~ bnd_c1_2 bnd_a659 X20) |
% 6.60/6.18 ~ bnd_c3_2 bnd_a659 X20)) &
% 6.60/6.18 ~ bnd_c1_1 bnd_a659) &
% 6.60/6.18 bnd_c2_1 bnd_a659 |
% 6.60/6.18 bnd_c5_0)) &
% 6.60/6.18 ((((((((((bnd_ndr1_0 & ~ bnd_c4_1 bnd_a660) &
% 6.60/6.19 bnd_ndr1_1 bnd_a660) &
% 6.60/6.19 ~ bnd_c4_2 bnd_a660 bnd_a661) &
% 6.60/6.19 bnd_c2_2 bnd_a660 bnd_a661) &
% 6.60/6.19 ~ bnd_c3_2 bnd_a660 bnd_a661) &
% 6.60/6.19 bnd_ndr1_1 bnd_a660) &
% 6.60/6.19 ~ bnd_c4_2 bnd_a660 bnd_a662) &
% 6.60/6.19 ~ bnd_c5_2 bnd_a660 bnd_a662) &
% 6.60/6.19 ~ bnd_c2_2 bnd_a660 bnd_a662 |
% 6.60/6.19 bnd_c4_0) |
% 6.60/6.19 bnd_c2_0)) &
% 6.60/6.19 ((bnd_c5_0 |
% 6.60/6.19 ((((bnd_ndr1_0 &
% 6.60/6.19 (ALL X21.
% 6.60/6.19 bnd_ndr1_1 bnd_a663 -->
% 6.60/6.19 (bnd_c4_2 bnd_a663 X21 | bnd_c1_2 bnd_a663 X21) |
% 6.60/6.19 bnd_c2_2 bnd_a663 X21)) &
% 6.60/6.19 bnd_c4_1 bnd_a663) &
% 6.60/6.19 bnd_ndr1_1 bnd_a663) &
% 6.60/6.19 ~ bnd_c5_2 bnd_a663 bnd_a664) &
% 6.60/6.19 bnd_c1_2 bnd_a663 bnd_a664) |
% 6.60/6.19 ~ bnd_c3_0)) &
% 6.60/6.19 ((((bnd_ndr1_0 & ~ bnd_c5_1 bnd_a665) & bnd_c3_1 bnd_a665) &
% 6.60/6.19 (ALL X22.
% 6.60/6.19 bnd_ndr1_1 bnd_a665 -->
% 6.60/6.19 bnd_c5_2 bnd_a665 X22 | ~ bnd_c1_2 bnd_a665 X22) |
% 6.60/6.19 bnd_c2_0) |
% 6.60/6.19 bnd_c4_0)) &
% 6.60/6.19 ((bnd_c2_0 |
% 6.60/6.19 ((bnd_ndr1_0 & ~ bnd_c1_1 bnd_a666) & bnd_c3_1 bnd_a666) &
% 6.60/6.19 (ALL X23.
% 6.60/6.19 bnd_ndr1_1 bnd_a666 -->
% 6.60/6.19 bnd_c3_2 bnd_a666 X23 | ~ bnd_c5_2 bnd_a666 X23)) |
% 6.60/6.19 (((bnd_ndr1_0 & ~ bnd_c4_1 bnd_a667) & bnd_ndr1_1 bnd_a667) &
% 6.60/6.19 ~ bnd_c4_2 bnd_a667 bnd_a668) &
% 6.60/6.19 ~ bnd_c1_2 bnd_a667 bnd_a668)) &
% 6.60/6.19 ((((((bnd_ndr1_0 &
% 6.60/6.19 (ALL X24.
% 6.60/6.19 bnd_ndr1_1 bnd_a669 -->
% 6.60/6.19 (bnd_c3_2 bnd_a669 X24 | ~ bnd_c4_2 bnd_a669 X24) |
% 6.60/6.19 bnd_c2_2 bnd_a669 X24)) &
% 6.60/6.19 ~ bnd_c1_1 bnd_a669) &
% 6.60/6.19 bnd_ndr1_1 bnd_a669) &
% 6.60/6.19 ~ bnd_c5_2 bnd_a669 bnd_a670) &
% 6.60/6.19 bnd_c1_2 bnd_a669 bnd_a670) &
% 6.60/6.19 ~ bnd_c2_2 bnd_a669 bnd_a670 |
% 6.60/6.19 ~ bnd_c5_0)) &
% 6.60/6.19 ~ bnd_c3_0) &
% 6.60/6.19 ((bnd_c5_0 | bnd_c1_0) |
% 6.60/6.19 ((bnd_ndr1_0 &
% 6.60/6.19 (ALL X25.
% 6.60/6.19 bnd_ndr1_1 bnd_a671 -->
% 6.60/6.19 bnd_c5_2 bnd_a671 X25 | ~ bnd_c2_2 bnd_a671 X25)) &
% 6.60/6.19 ~ bnd_c5_1 bnd_a671) &
% 6.60/6.19 (ALL X26.
% 6.60/6.19 bnd_ndr1_1 bnd_a671 -->
% 6.60/6.19 (~ bnd_c4_2 bnd_a671 X26 | bnd_c5_2 bnd_a671 X26) |
% 6.60/6.19 ~ bnd_c1_2 bnd_a671 X26))) &
% 6.60/6.19 ((bnd_c4_0 |
% 6.60/6.19 ((bnd_ndr1_0 & ~ bnd_c5_1 bnd_a672) &
% 6.60/6.19 (ALL X27.
% 6.60/6.19 bnd_ndr1_1 bnd_a672 -->
% 6.60/6.19 (bnd_c1_2 bnd_a672 X27 | bnd_c4_2 bnd_a672 X27) |
% 6.60/6.19 ~ bnd_c5_2 bnd_a672 X27)) &
% 6.60/6.19 ~ bnd_c1_1 bnd_a672) |
% 6.60/6.19 (ALL X28.
% 6.60/6.19 bnd_ndr1_0 -->
% 6.60/6.19 (bnd_c2_1 X28 |
% 6.60/6.19 ((bnd_ndr1_1 X28 & ~ bnd_c5_2 X28 bnd_a673) &
% 6.60/6.19 ~ bnd_c4_2 X28 bnd_a673) &
% 6.60/6.19 ~ bnd_c1_2 X28 bnd_a673) |
% 6.60/6.19 ~ bnd_c3_1 X28))) &
% 6.60/6.19 (~ bnd_c2_0 |
% 6.60/6.19 (bnd_ndr1_0 & bnd_c4_1 bnd_a674) & bnd_c2_1 bnd_a674)) &
% 6.60/6.19 bnd_c1_0) &
% 6.60/6.19 (((bnd_ndr1_0 & bnd_c3_1 bnd_a675) & bnd_c5_1 bnd_a675 |
% 6.60/6.19 (ALL X29.
% 6.60/6.19 bnd_ndr1_0 -->
% 6.60/6.19 (bnd_c5_1 X29 |
% 6.60/6.19 (ALL X30.
% 6.60/6.19 bnd_ndr1_1 X29 -->
% 6.60/6.19 (~ bnd_c2_2 X29 X30 | bnd_c1_2 X29 X30) |
% 6.60/6.19 ~ bnd_c4_2 X29 X30)) |
% 6.60/6.19 ~ bnd_c1_1 X29)) |
% 6.60/6.19 ~ bnd_c5_0)) &
% 6.60/6.19 ((~ bnd_c2_0 | ~ bnd_c5_0) |
% 6.60/6.19 (((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a676) &
% 6.60/6.19 ~ bnd_c4_2 bnd_a676 bnd_a677) &
% 6.60/6.19 ~ bnd_c2_2 bnd_a676 bnd_a677) &
% 6.60/6.19 ~ bnd_c3_2 bnd_a676 bnd_a677) &
% 6.60/6.19 bnd_c3_1 bnd_a676) &
% 6.60/6.19 bnd_c4_1 bnd_a676)) &
% 6.60/6.19 (((bnd_ndr1_0 & ~ bnd_c2_1 bnd_a678) & ~ bnd_c4_1 bnd_a678 |
% 6.60/6.19 ((bnd_ndr1_0 & ~ bnd_c4_1 bnd_a679) &
% 6.60/6.19 (ALL X31.
% 6.60/6.19 bnd_ndr1_1 bnd_a679 -->
% 6.60/6.19 (bnd_c1_2 bnd_a679 X31 | bnd_c5_2 bnd_a679 X31) |
% 6.60/6.19 bnd_c3_2 bnd_a679 X31)) &
% 6.60/6.19 ~ bnd_c5_1 bnd_a679) |
% 6.60/6.19 (bnd_ndr1_0 &
% 6.60/6.19 (ALL X32.
% 6.60/6.19 bnd_ndr1_1 bnd_a680 -->
% 6.60/6.19 ~ bnd_c1_2 bnd_a680 X32 | bnd_c2_2 bnd_a680 X32)) &
% 6.60/6.19 ~ bnd_c3_1 bnd_a680))
% 9.02/8.51 Unfolded term: ~ ((((((((((((((((((((((((((((((((ALL U.
% 9.02/8.51 bnd_ndr1_0 -->
% 9.02/8.51 (bnd_c1_1 U |
% 9.02/8.51 ((bnd_ndr1_1 U & bnd_c2_2 U bnd_a640) & ~ bnd_c5_2 U bnd_a640) &
% 9.02/8.51 bnd_c3_2 U bnd_a640) |
% 9.02/8.51 (ALL V.
% 9.02/8.51 bnd_ndr1_1 U --> (~ bnd_c2_2 U V | ~ bnd_c1_2 U V) | bnd_c3_2 U V)) |
% 9.02/8.51 (ALL W.
% 9.02/8.51 bnd_ndr1_0 -->
% 9.02/8.51 (~ bnd_c1_1 W | ~ bnd_c5_1 W) |
% 9.02/8.51 bnd_c3_1 W)) |
% 9.02/8.51 ~ bnd_c5_0) &
% 9.02/8.51 ((~ bnd_c3_0 | ~ bnd_c4_0) |
% 9.02/8.51 (((bnd_ndr1_0 & bnd_ndr1_1 bnd_a641) &
% 9.02/8.51 ~ bnd_c1_2 bnd_a641 bnd_a642) &
% 9.02/8.51 ~ bnd_c3_2 bnd_a641 bnd_a642) &
% 9.02/8.51 (ALL X.
% 9.02/8.51 bnd_ndr1_1 bnd_a641 -->
% 9.02/8.51 (~ bnd_c4_2 bnd_a641 X |
% 9.12/8.67 ~ bnd_c5_2 bnd_a641 X) |
% 9.12/8.67 bnd_c3_2 bnd_a641 X))) &
% 9.12/8.67 ((~ bnd_c4_0 | ~ bnd_c1_0) | ~ bnd_c2_0)) &
% 9.12/8.67 ((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a643) &
% 9.12/8.67 ~ bnd_c2_2 bnd_a643 bnd_a644) &
% 9.12/8.67 bnd_c5_2 bnd_a643 bnd_a644) &
% 9.12/8.67 ~ bnd_c1_1 bnd_a643) &
% 9.12/8.67 bnd_c4_1 bnd_a643 |
% 9.12/8.67 (((((bnd_ndr1_0 & ~ bnd_c1_1 bnd_a645) &
% 9.12/8.67 bnd_ndr1_1 bnd_a645) &
% 9.12/8.67 bnd_c3_2 bnd_a645 bnd_a646) &
% 9.12/8.67 bnd_c2_2 bnd_a645 bnd_a646) &
% 9.12/8.67 ~ bnd_c5_2 bnd_a645 bnd_a646) &
% 9.12/8.67 ~ bnd_c2_1 bnd_a645) |
% 9.12/8.67 ~ bnd_c3_0)) &
% 9.12/8.67 (((ALL Y.
% 9.12/8.67 bnd_ndr1_0 -->
% 9.12/8.67 (~ bnd_c3_1 Y | ~ bnd_c1_1 Y) |
% 9.12/8.67 ~ bnd_c4_1 Y) |
% 9.12/8.67 ~ bnd_c2_0) |
% 9.12/8.67 bnd_c1_0)) &
% 9.12/8.67 (((ALL Z.
% 9.12/8.67 bnd_ndr1_0 -->
% 9.12/8.67 ((ALL X1.
% 9.12/8.67 bnd_ndr1_1 Z --> (~ bnd_c4_2 Z X1 | ~ bnd_c1_2 Z X1) | ~ bnd_c3_2 Z X1) |
% 9.12/8.67 bnd_c1_1 Z) |
% 9.12/8.67 bnd_c2_1 Z) |
% 9.12/8.67 ~ bnd_c3_0) |
% 9.12/8.67 bnd_c1_0)) &
% 9.12/8.67 (bnd_c5_0 | ~ bnd_c4_0)) &
% 9.12/8.67 ((bnd_c3_0 | bnd_c5_0) |
% 9.12/8.67 (ALL X2.
% 9.12/8.67 bnd_ndr1_0 -->
% 9.12/8.67 (((bnd_ndr1_1 X2 & bnd_c5_2 X2 bnd_a647) &
% 9.12/8.67 ~ bnd_c2_2 X2 bnd_a647) &
% 9.12/8.67 ~ bnd_c1_2 X2 bnd_a647 |
% 9.12/8.67 bnd_c1_1 X2) |
% 9.12/8.67 ~ bnd_c2_1 X2))) &
% 9.12/8.67 ((bnd_c4_0 |
% 9.12/8.67 (ALL X3.
% 9.12/8.67 bnd_ndr1_0 -->
% 9.12/8.67 ((ALL X4.
% 9.12/8.67 bnd_ndr1_1 X3 -->
% 9.12/8.67 ~ bnd_c1_2 X3 X4 | bnd_c4_2 X3 X4) |
% 9.12/8.67 bnd_c1_1 X3) |
% 9.12/8.67 (ALL X5.
% 9.12/8.67 bnd_ndr1_1 X3 -->
% 9.12/8.67 (bnd_c3_2 X3 X5 | ~ bnd_c1_2 X3 X5) |
% 9.12/8.67 bnd_c5_2 X3 X5))) |
% 9.12/8.67 ((bnd_ndr1_0 & ~ bnd_c3_1 bnd_a648) &
% 9.12/8.67 (ALL X6.
% 9.12/8.67 bnd_ndr1_1 bnd_a648 -->
% 9.12/8.67 ~ bnd_c1_2 bnd_a648 X6 |
% 9.12/8.67 ~ bnd_c3_2 bnd_a648 X6)) &
% 9.12/8.67 (ALL X7.
% 9.12/8.67 bnd_ndr1_1 bnd_a648 -->
% 9.12/8.67 (~ bnd_c5_2 bnd_a648 X7 |
% 9.12/8.67 bnd_c4_2 bnd_a648 X7) |
% 9.12/8.67 ~ bnd_c2_2 bnd_a648 X7))) &
% 9.12/8.67 ((ALL X8.
% 9.12/8.67 bnd_ndr1_0 -->
% 9.12/8.67 (~ bnd_c4_1 X8 |
% 9.12/8.67 ((bnd_ndr1_1 X8 & bnd_c4_2 X8 bnd_a649) &
% 9.12/8.67 bnd_c1_2 X8 bnd_a649) &
% 9.12/8.67 ~ bnd_c5_2 X8 bnd_a649) |
% 9.12/8.67 ((bnd_ndr1_1 X8 & bnd_c5_2 X8 bnd_a650) &
% 9.12/8.67 ~ bnd_c3_2 X8 bnd_a650) &
% 9.12/8.67 bnd_c4_2 X8 bnd_a650) |
% 9.12/8.67 bnd_c3_0)) &
% 9.12/8.67 ((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a651) &
% 9.12/8.67 ~ bnd_c5_2 bnd_a651 bnd_a652) &
% 9.12/8.67 bnd_c1_2 bnd_a651 bnd_a652) &
% 9.12/8.67 ~ bnd_c2_2 bnd_a651 bnd_a652) &
% 9.12/8.67 (ALL X9.
% 9.12/8.67 bnd_ndr1_1 bnd_a651 -->
% 9.12/8.67 (~ bnd_c1_2 bnd_a651 X9 |
% 9.12/8.67 bnd_c5_2 bnd_a651 X9) |
% 9.12/8.67 bnd_c3_2 bnd_a651 X9) |
% 9.12/8.67 ~ bnd_c5_0) |
% 9.12/8.67 ~ bnd_c1_0)) &
% 9.12/8.67 (((ALL X10.
% 9.12/8.67 bnd_ndr1_0 --> bnd_c5_1 X10 | bnd_c1_1 X10) |
% 9.12/8.67 ((bnd_ndr1_0 &
% 9.12/8.67 (ALL X11.
% 9.12/8.67 bnd_ndr1_1 bnd_a653 -->
% 9.12/8.67 bnd_c3_2 bnd_a653 X11 |
% 9.12/8.67 bnd_c1_2 bnd_a653 X11)) &
% 9.12/8.67 ~ bnd_c4_1 bnd_a653) &
% 9.12/8.67 ~ bnd_c1_1 bnd_a653) |
% 9.12/8.67 ~ bnd_c4_0)) &
% 9.12/8.67 (((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a654) &
% 9.12/8.67 bnd_c5_2 bnd_a654 bnd_a655) &
% 9.12/8.67 ~ bnd_c4_2 bnd_a654 bnd_a655) &
% 9.12/8.67 bnd_c3_2 bnd_a654 bnd_a655) &
% 9.12/8.67 ~ bnd_c1_1 bnd_a654) &
% 9.12/8.67 ~ bnd_c5_1 bnd_a654 |
% 9.12/8.67 (ALL X12.
% 9.12/8.67 bnd_ndr1_0 -->
% 9.12/8.67 (ALL X13.
% 9.12/8.67 bnd_ndr1_1 X12 -->
% 9.12/8.67 (bnd_c5_2 X12 X13 | ~ bnd_c4_2 X12 X13) |
% 9.12/8.67 bnd_c1_2 X12 X13))) |
% 9.12/8.67 ~ bnd_c2_0)) &
% 9.12/8.67 ((~ bnd_c1_0 |
% 9.12/8.67 (ALL X14.
% 9.12/8.67 bnd_ndr1_0 -->
% 9.12/8.67 ~ bnd_c3_1 X14 |
% 9.12/8.67 (ALL X15.
% 9.12/8.67 bnd_ndr1_1 X14 -->
% 9.12/8.67 (~ bnd_c4_2 X14 X15 | ~ bnd_c1_2 X14 X15) |
% 9.12/8.67 bnd_c3_2 X14 X15))) |
% 9.12/8.67 ~ bnd_c4_0)) &
% 9.12/8.67 (bnd_c5_0 |
% 9.12/8.67 (ALL X16.
% 9.12/8.67 bnd_ndr1_0 -->
% 9.12/8.67 (bnd_c5_1 X16 | ~ bnd_c2_1 X16) |
% 9.12/8.67 ((bnd_ndr1_1 X16 & ~ bnd_c2_2 X16 bnd_a656) &
% 9.12/8.67 ~ bnd_c1_2 X16 bnd_a656) &
% 9.12/8.67 ~ bnd_c3_2 X16 bnd_a656))) &
% 9.12/8.67 (((ALL X17.
% 9.12/8.67 bnd_ndr1_0 -->
% 9.12/8.67 bnd_c2_1 X17 |
% 9.12/8.67 ((bnd_ndr1_1 X17 & ~ bnd_c4_2 X17 bnd_a657) &
% 9.12/8.67 ~ bnd_c1_2 X17 bnd_a657) &
% 9.12/8.67 ~ bnd_c5_2 X17 bnd_a657) |
% 9.12/8.67 (ALL X18.
% 9.12/8.67 bnd_ndr1_0 -->
% 9.12/8.67 (bnd_c4_1 X18 |
% 9.12/8.67 (bnd_ndr1_1 X18 & bnd_c4_2 X18 bnd_a658) &
% 9.12/8.67 bnd_c5_2 X18 bnd_a658) |
% 9.12/8.67 (ALL X19.
% 9.12/8.67 bnd_ndr1_1 X18 -->
% 9.12/8.67 (bnd_c5_2 X18 X19 | ~ bnd_c2_2 X18 X19) |
% 9.12/8.67 bnd_c1_2 X18 X19))) |
% 9.12/8.67 bnd_c3_0)) &
% 9.12/8.67 (((bnd_ndr1_0 &
% 9.12/8.67 (ALL X20.
% 9.12/8.67 bnd_ndr1_1 bnd_a659 -->
% 9.12/8.67 (bnd_c5_2 bnd_a659 X20 | ~ bnd_c1_2 bnd_a659 X20) |
% 9.12/8.67 ~ bnd_c3_2 bnd_a659 X20)) &
% 9.12/8.67 ~ bnd_c1_1 bnd_a659) &
% 9.12/8.67 bnd_c2_1 bnd_a659 |
% 9.12/8.67 bnd_c5_0)) &
% 9.12/8.67 ((((((((((bnd_ndr1_0 & ~ bnd_c4_1 bnd_a660) &
% 9.12/8.67 bnd_ndr1_1 bnd_a660) &
% 9.12/8.67 ~ bnd_c4_2 bnd_a660 bnd_a661) &
% 9.12/8.67 bnd_c2_2 bnd_a660 bnd_a661) &
% 9.12/8.67 ~ bnd_c3_2 bnd_a660 bnd_a661) &
% 9.12/8.67 bnd_ndr1_1 bnd_a660) &
% 9.12/8.67 ~ bnd_c4_2 bnd_a660 bnd_a662) &
% 9.12/8.67 ~ bnd_c5_2 bnd_a660 bnd_a662) &
% 9.12/8.67 ~ bnd_c2_2 bnd_a660 bnd_a662 |
% 9.12/8.67 bnd_c4_0) |
% 9.12/8.67 bnd_c2_0)) &
% 9.12/8.67 ((bnd_c5_0 |
% 9.12/8.67 ((((bnd_ndr1_0 &
% 9.12/8.67 (ALL X21.
% 9.12/8.67 bnd_ndr1_1 bnd_a663 -->
% 9.12/8.67 (bnd_c4_2 bnd_a663 X21 | bnd_c1_2 bnd_a663 X21) |
% 9.12/8.67 bnd_c2_2 bnd_a663 X21)) &
% 9.12/8.67 bnd_c4_1 bnd_a663) &
% 9.12/8.67 bnd_ndr1_1 bnd_a663) &
% 9.12/8.67 ~ bnd_c5_2 bnd_a663 bnd_a664) &
% 9.12/8.67 bnd_c1_2 bnd_a663 bnd_a664) |
% 9.12/8.67 ~ bnd_c3_0)) &
% 9.12/8.67 ((((bnd_ndr1_0 & ~ bnd_c5_1 bnd_a665) & bnd_c3_1 bnd_a665) &
% 9.12/8.67 (ALL X22.
% 9.12/8.67 bnd_ndr1_1 bnd_a665 -->
% 9.12/8.67 bnd_c5_2 bnd_a665 X22 | ~ bnd_c1_2 bnd_a665 X22) |
% 9.12/8.67 bnd_c2_0) |
% 9.12/8.67 bnd_c4_0)) &
% 9.12/8.67 ((bnd_c2_0 |
% 9.12/8.67 ((bnd_ndr1_0 & ~ bnd_c1_1 bnd_a666) & bnd_c3_1 bnd_a666) &
% 9.12/8.67 (ALL X23.
% 9.12/8.67 bnd_ndr1_1 bnd_a666 -->
% 9.12/8.67 bnd_c3_2 bnd_a666 X23 | ~ bnd_c5_2 bnd_a666 X23)) |
% 9.12/8.67 (((bnd_ndr1_0 & ~ bnd_c4_1 bnd_a667) & bnd_ndr1_1 bnd_a667) &
% 9.12/8.67 ~ bnd_c4_2 bnd_a667 bnd_a668) &
% 9.12/8.67 ~ bnd_c1_2 bnd_a667 bnd_a668)) &
% 9.12/8.67 ((((((bnd_ndr1_0 &
% 9.12/8.67 (ALL X24.
% 9.12/8.67 bnd_ndr1_1 bnd_a669 -->
% 9.12/8.67 (bnd_c3_2 bnd_a669 X24 | ~ bnd_c4_2 bnd_a669 X24) |
% 9.12/8.67 bnd_c2_2 bnd_a669 X24)) &
% 9.12/8.67 ~ bnd_c1_1 bnd_a669) &
% 9.12/8.67 bnd_ndr1_1 bnd_a669) &
% 9.12/8.67 ~ bnd_c5_2 bnd_a669 bnd_a670) &
% 9.12/8.67 bnd_c1_2 bnd_a669 bnd_a670) &
% 9.12/8.67 ~ bnd_c2_2 bnd_a669 bnd_a670 |
% 9.12/8.67 ~ bnd_c5_0)) &
% 9.12/8.67 ~ bnd_c3_0) &
% 9.12/8.67 ((bnd_c5_0 | bnd_c1_0) |
% 9.12/8.67 ((bnd_ndr1_0 &
% 9.12/8.67 (ALL X25.
% 9.12/8.67 bnd_ndr1_1 bnd_a671 -->
% 9.12/8.67 bnd_c5_2 bnd_a671 X25 | ~ bnd_c2_2 bnd_a671 X25)) &
% 9.12/8.67 ~ bnd_c5_1 bnd_a671) &
% 9.12/8.67 (ALL X26.
% 9.12/8.67 bnd_ndr1_1 bnd_a671 -->
% 9.12/8.67 (~ bnd_c4_2 bnd_a671 X26 | bnd_c5_2 bnd_a671 X26) |
% 9.12/8.67 ~ bnd_c1_2 bnd_a671 X26))) &
% 9.12/8.67 ((bnd_c4_0 |
% 9.12/8.67 ((bnd_ndr1_0 & ~ bnd_c5_1 bnd_a672) &
% 9.12/8.67 (ALL X27.
% 9.12/8.67 bnd_ndr1_1 bnd_a672 -->
% 9.12/8.67 (bnd_c1_2 bnd_a672 X27 | bnd_c4_2 bnd_a672 X27) |
% 9.12/8.67 ~ bnd_c5_2 bnd_a672 X27)) &
% 9.12/8.67 ~ bnd_c1_1 bnd_a672) |
% 9.12/8.67 (ALL X28.
% 9.12/8.67 bnd_ndr1_0 -->
% 9.12/8.67 (bnd_c2_1 X28 |
% 9.12/8.67 ((bnd_ndr1_1 X28 & ~ bnd_c5_2 X28 bnd_a673) &
% 9.12/8.67 ~ bnd_c4_2 X28 bnd_a673) &
% 9.12/8.67 ~ bnd_c1_2 X28 bnd_a673) |
% 9.12/8.67 ~ bnd_c3_1 X28))) &
% 9.12/8.67 (~ bnd_c2_0 |
% 9.12/8.67 (bnd_ndr1_0 & bnd_c4_1 bnd_a674) & bnd_c2_1 bnd_a674)) &
% 9.12/8.67 bnd_c1_0) &
% 9.12/8.67 (((bnd_ndr1_0 & bnd_c3_1 bnd_a675) & bnd_c5_1 bnd_a675 |
% 9.12/8.67 (ALL X29.
% 9.12/8.67 bnd_ndr1_0 -->
% 9.12/8.67 (bnd_c5_1 X29 |
% 9.12/8.67 (ALL X30.
% 9.12/8.67 bnd_ndr1_1 X29 -->
% 9.12/8.67 (~ bnd_c2_2 X29 X30 | bnd_c1_2 X29 X30) |
% 9.12/8.67 ~ bnd_c4_2 X29 X30)) |
% 9.12/8.67 ~ bnd_c1_1 X29)) |
% 9.12/8.67 ~ bnd_c5_0)) &
% 9.12/8.67 ((~ bnd_c2_0 | ~ bnd_c5_0) |
% 9.12/8.67 (((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a676) &
% 9.12/8.67 ~ bnd_c4_2 bnd_a676 bnd_a677) &
% 9.12/8.67 ~ bnd_c2_2 bnd_a676 bnd_a677) &
% 9.12/8.67 ~ bnd_c3_2 bnd_a676 bnd_a677) &
% 9.12/8.67 bnd_c3_1 bnd_a676) &
% 9.12/8.67 bnd_c4_1 bnd_a676)) &
% 9.12/8.67 (((bnd_ndr1_0 & ~ bnd_c2_1 bnd_a678) & ~ bnd_c4_1 bnd_a678 |
% 9.12/8.67 ((bnd_ndr1_0 & ~ bnd_c4_1 bnd_a679) &
% 9.12/8.67 (ALL X31.
% 9.12/8.67 bnd_ndr1_1 bnd_a679 -->
% 9.12/8.67 (bnd_c1_2 bnd_a679 X31 | bnd_c5_2 bnd_a679 X31) |
% 9.12/8.67 bnd_c3_2 bnd_a679 X31)) &
% 9.12/8.67 ~ bnd_c5_1 bnd_a679) |
% 9.12/8.67 (bnd_ndr1_0 &
% 9.12/8.67 (ALL X32.
% 9.12/8.67 bnd_ndr1_1 bnd_a680 -->
% 9.12/8.67 ~ bnd_c1_2 bnd_a680 X32 | bnd_c2_2 bnd_a680 X32)) &
% 9.12/8.67 ~ bnd_c3_1 bnd_a680))
% 9.12/8.67 Adding axioms...
% 9.12/8.67 Typedef.type_definition_def
% 16.13/15.64 ...done.
% 16.13/15.65 Ground types: ?'b, TPTP_Interpret.ind
% 16.13/15.65 Translating term (sizes: 1, 1) ...
% 22.03/21.59 Invoking SAT solver...
% 22.23/21.71 Model found:
% 22.23/21.71 Size of types: ?'b: 1, TPTP_Interpret.ind: 1
% 22.23/21.71 bnd_a680: ??.TPTP_Interpret.ind0
% 22.23/21.71 bnd_a679: ??.TPTP_Interpret.ind0
% 22.23/21.71 bnd_a678: ??.TPTP_Interpret.ind0
% 22.23/21.71 bnd_a677: ??.TPTP_Interpret.ind0
% 22.23/21.71 bnd_a676: ??.TPTP_Interpret.ind0
% 22.23/21.71 bnd_a675: ??.TPTP_Interpret.ind0
% 22.23/21.71 bnd_a674: ??.TPTP_Interpret.ind0
% 22.23/21.71 bnd_a673: ??.TPTP_Interpret.ind0
% 22.23/21.71 bnd_a672: ??.TPTP_Interpret.ind0
% 22.23/21.71 bnd_a671: ??.TPTP_Interpret.ind0
% 22.23/21.71 bnd_a670: ??.TPTP_Interpret.ind0
% 22.23/21.71 bnd_a669: ??.TPTP_Interpret.ind0
% 22.23/21.71 bnd_a668: ??.TPTP_Interpret.ind0
% 22.23/21.71 bnd_a667: ??.TPTP_Interpret.ind0
% 22.23/21.71 bnd_a666: ??.TPTP_Interpret.ind0
% 22.23/21.71 bnd_a665: ??.TPTP_Interpret.ind0
% 22.23/21.71 bnd_a664: ??.TPTP_Interpret.ind0
% 22.23/21.71 bnd_a663: ??.TPTP_Interpret.ind0
% 22.23/21.71 bnd_a662: ??.TPTP_Interpret.ind0
% 22.23/21.71 bnd_a661: ??.TPTP_Interpret.ind0
% 22.23/21.71 bnd_a660: ??.TPTP_Interpret.ind0
% 22.23/21.71 bnd_a659: ??.TPTP_Interpret.ind0
% 22.23/21.71 bnd_a658: ??.TPTP_Interpret.ind0
% 22.23/21.71 bnd_a657: ??.TPTP_Interpret.ind0
% 22.23/21.71 bnd_a656: ??.TPTP_Interpret.ind0
% 22.23/21.71 bnd_a655: ??.TPTP_Interpret.ind0
% 22.23/21.71 bnd_a654: ??.TPTP_Interpret.ind0
% 22.23/21.71 bnd_a653: ??.TPTP_Interpret.ind0
% 22.23/21.71 bnd_a652: ??.TPTP_Interpret.ind0
% 22.23/21.71 bnd_a651: ??.TPTP_Interpret.ind0
% 22.23/21.71 bnd_a650: ??.TPTP_Interpret.ind0
% 22.23/21.71 bnd_a649: ??.TPTP_Interpret.ind0
% 22.23/21.71 bnd_a648: ??.TPTP_Interpret.ind0
% 22.23/21.71 bnd_a647: ??.TPTP_Interpret.ind0
% 22.23/21.71 bnd_c2_1: {(??.TPTP_Interpret.ind0, True)}
% 22.23/21.71 bnd_a646: ??.TPTP_Interpret.ind0
% 22.23/21.71 bnd_a645: ??.TPTP_Interpret.ind0
% 22.23/21.71 bnd_c4_1: {(??.TPTP_Interpret.ind0, True)}
% 22.23/21.71 bnd_a644: ??.TPTP_Interpret.ind0
% 22.23/21.71 bnd_a643: ??.TPTP_Interpret.ind0
% 22.23/21.71 bnd_c2_0: True
% 22.23/21.71 bnd_c1_0: True
% 22.23/21.71 bnd_c4_2: {(??.TPTP_Interpret.ind0, {(??.TPTP_Interpret.ind0, True)})}
% 22.23/21.71 bnd_a642: ??.TPTP_Interpret.ind0
% 22.23/21.71 bnd_a641: ??.TPTP_Interpret.ind0
% 22.23/21.71 bnd_c4_0: False
% 22.23/21.71 bnd_c3_0: False
% 22.23/21.71 bnd_c5_0: False
% 22.23/21.71 bnd_c3_1: {(??.TPTP_Interpret.ind0, False)}
% 22.23/21.71 bnd_c5_1: {(??.TPTP_Interpret.ind0, False)}
% 22.23/21.71 bnd_c1_2: {(??.TPTP_Interpret.ind0, {(??.TPTP_Interpret.ind0, False)})}
% 22.23/21.71 bnd_c3_2: {(??.TPTP_Interpret.ind0, {(??.TPTP_Interpret.ind0, False)})}
% 22.23/21.71 bnd_c5_2: {(??.TPTP_Interpret.ind0, {(??.TPTP_Interpret.ind0, True)})}
% 22.23/21.71 bnd_a640: ??.TPTP_Interpret.ind0
% 22.23/21.71 bnd_c2_2: {(??.TPTP_Interpret.ind0, {(??.TPTP_Interpret.ind0, False)})}
% 22.23/21.71 bnd_ndr1_1: {(??.TPTP_Interpret.ind0, True)}
% 22.23/21.71 bnd_c1_1: {(??.TPTP_Interpret.ind0, False)}
% 22.23/21.71 bnd_ndr1_0: True
% 22.23/21.71
% 22.23/21.71 % SZS status CounterSatisfiable
%------------------------------------------------------------------------------