TSTP Solution File: SYN531+1 by Refute---2015
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%------------------------------------------------------------------------------
% File : Refute---2015
% Problem : SYN531+1 : TPTP v6.4.0. Released v2.1.0.
% Transfm : none
% Format : tptp:raw
% Command : isabelle tptp_refute %d %s
% Computer : n078.star.cs.uiowa.edu
% Model : x86_64 x86_64
% CPU : Intel(R) Xeon(R) CPU E5-2609 0 2.40GHz
% Memory : 32218.75MB
% OS : Linux 3.10.0-327.10.1.el7.x86_64
% CPULimit : 300s
% DateTime : Thu Apr 14 06:42:16 EDT 2016
% Result : CounterSatisfiable 15.72s
% Output : Assurance 0s
% Verified :
% SZS Type : None (Parsing solution fails)
% Syntax : Number of formulae : 0
% Comments :
%------------------------------------------------------------------------------
%----No solution output by system
%------------------------------------------------------------------------------
%----ORIGINAL SYSTEM OUTPUT
% 0.00/0.03 % Problem : SYN531+1 : TPTP v6.4.0. Released v2.1.0.
% 0.00/0.04 % Command : isabelle tptp_refute %d %s
% 0.03/0.23 % Computer : n078.star.cs.uiowa.edu
% 0.03/0.23 % Model : x86_64 x86_64
% 0.03/0.23 % CPU : Intel(R) Xeon(R) CPU E5-2609 0 @ 2.40GHz
% 0.03/0.23 % Memory : 32218.75MB
% 0.03/0.23 % OS : Linux 3.10.0-327.10.1.el7.x86_64
% 0.03/0.23 % CPULimit : 300
% 0.03/0.23 % DateTime : Sat Apr 9 00:14:09 CDT 2016
% 0.03/0.23 % CPUTime:
% 6.30/5.84 > val it = (): unit
% 6.60/6.13 Trying to find a model that refutes: ~ ((((((((((((((((((((((ALL U.
% 6.60/6.13 bnd_ndr1_0 -->
% 6.60/6.13 (ALL V.
% 6.60/6.13 bnd_ndr1_1 U -->
% 6.60/6.13 bnd_c3_2 U V | bnd_c2_2 U V) |
% 6.60/6.13 bnd_c3_1 U) |
% 6.60/6.13 ~ bnd_c1_0) |
% 6.60/6.13 ~ bnd_c5_0) &
% 6.60/6.13 ((ALL W.
% 6.60/6.13 bnd_ndr1_0 -->
% 6.60/6.13 (((bnd_ndr1_1 W & bnd_c5_2 W bnd_a387) &
% 6.60/6.13 bnd_c2_2 W bnd_a387) &
% 6.60/6.13 bnd_c3_2 W bnd_a387 |
% 6.60/6.13 ((bnd_ndr1_1 W & bnd_c3_2 W bnd_a388) &
% 6.60/6.13 ~ bnd_c1_2 W bnd_a388) &
% 6.60/6.13 bnd_c2_2 W bnd_a388) |
% 6.60/6.13 bnd_c2_1 W) |
% 6.60/6.13 (ALL X.
% 6.60/6.13 bnd_ndr1_0 -->
% 6.60/6.13 (~ bnd_c1_1 X | ~ bnd_c5_1 X) |
% 6.60/6.13 (bnd_ndr1_1 X & bnd_c1_2 X bnd_a389) &
% 6.60/6.13 ~ bnd_c3_2 X bnd_a389))) &
% 6.60/6.13 (((ALL Y.
% 6.60/6.13 bnd_ndr1_0 -->
% 6.60/6.13 (bnd_c3_1 Y |
% 6.60/6.13 (ALL Z.
% 6.60/6.13 bnd_ndr1_1 Y -->
% 6.60/6.13 bnd_c1_2 Y Z | ~ bnd_c3_2 Y Z)) |
% 6.60/6.13 bnd_c5_1 Y) |
% 6.60/6.13 (bnd_ndr1_0 & ~ bnd_c1_1 bnd_a390) &
% 6.60/6.13 (ALL X1.
% 6.60/6.13 bnd_ndr1_1 bnd_a390 -->
% 6.60/6.13 bnd_c1_2 bnd_a390 X1 | bnd_c5_2 bnd_a390 X1)) |
% 6.60/6.13 ((bnd_ndr1_0 &
% 6.60/6.13 (ALL X2.
% 6.60/6.13 bnd_ndr1_1 bnd_a391 -->
% 6.60/6.13 (bnd_c4_2 bnd_a391 X2 | ~ bnd_c1_2 bnd_a391 X2) |
% 6.60/6.13 ~ bnd_c3_2 bnd_a391 X2)) &
% 6.60/6.13 ~ bnd_c3_1 bnd_a391) &
% 6.60/6.13 (ALL X3.
% 6.60/6.13 bnd_ndr1_1 bnd_a391 -->
% 6.60/6.13 (bnd_c4_2 bnd_a391 X3 | bnd_c1_2 bnd_a391 X3) |
% 6.60/6.13 ~ bnd_c5_2 bnd_a391 X3))) &
% 6.60/6.13 (~ bnd_c4_0 |
% 6.60/6.13 (ALL X4.
% 6.60/6.13 bnd_ndr1_0 -->
% 6.60/6.13 (bnd_c4_1 X4 | bnd_c2_1 X4) | bnd_c5_1 X4))) &
% 6.60/6.13 ((((bnd_ndr1_0 & bnd_c5_1 bnd_a392) & bnd_c3_1 bnd_a392) &
% 6.60/6.13 bnd_c1_1 bnd_a392 |
% 6.60/6.13 bnd_c5_0) |
% 6.60/6.13 (((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a393) &
% 6.60/6.13 ~ bnd_c2_2 bnd_a393 bnd_a394) &
% 6.60/6.13 ~ bnd_c3_2 bnd_a393 bnd_a394) &
% 6.60/6.13 bnd_c5_2 bnd_a393 bnd_a394) &
% 6.60/6.13 bnd_ndr1_1 bnd_a393) &
% 6.60/6.13 ~ bnd_c1_2 bnd_a393 bnd_a395) &
% 6.60/6.13 bnd_c2_2 bnd_a393 bnd_a395) &
% 6.60/6.13 bnd_c3_1 bnd_a393)) &
% 6.60/6.13 ((~ bnd_c1_0 |
% 6.60/6.13 (((((bnd_ndr1_0 & ~ bnd_c3_1 bnd_a396) &
% 6.60/6.13 bnd_c4_1 bnd_a396) &
% 6.60/6.13 bnd_ndr1_1 bnd_a396) &
% 6.60/6.13 ~ bnd_c5_2 bnd_a396 bnd_a397) &
% 6.60/6.13 ~ bnd_c4_2 bnd_a396 bnd_a397) &
% 6.60/6.13 bnd_c3_2 bnd_a396 bnd_a397) |
% 6.60/6.13 ~ bnd_c2_0)) &
% 6.60/6.13 ((bnd_c3_0 | bnd_c4_0) |
% 6.60/6.13 (ALL X5.
% 6.60/6.13 bnd_ndr1_0 -->
% 6.60/6.13 (~ bnd_c3_1 X5 |
% 6.60/6.13 bnd_ndr1_1 X5 & bnd_c3_2 X5 bnd_a398) |
% 6.60/6.13 ~ bnd_c1_1 X5))) &
% 6.60/6.13 ((bnd_c4_0 | ~ bnd_c5_0) | ~ bnd_c2_0)) &
% 6.60/6.13 (~ bnd_c2_0 | ~ bnd_c3_0)) &
% 6.60/6.13 ((ALL X6.
% 6.60/6.13 bnd_ndr1_0 -->
% 6.60/6.13 (bnd_c4_1 X6 | bnd_c5_1 X6) | ~ bnd_c3_1 X6) |
% 6.60/6.13 ~ bnd_c2_0)) &
% 6.60/6.13 (((bnd_ndr1_0 & ~ bnd_c2_1 bnd_a399) &
% 6.60/6.13 (ALL X7.
% 6.60/6.13 bnd_ndr1_1 bnd_a399 -->
% 6.60/6.13 (~ bnd_c2_2 bnd_a399 X7 | ~ bnd_c1_2 bnd_a399 X7) |
% 6.60/6.13 ~ bnd_c5_2 bnd_a399 X7) |
% 6.60/6.13 bnd_c3_0) |
% 6.60/6.13 ~ bnd_c5_0)) &
% 6.60/6.13 ((bnd_c3_0 |
% 6.60/6.13 (ALL X8.
% 6.60/6.13 bnd_ndr1_0 -->
% 6.60/6.13 (ALL X9.
% 6.60/6.13 bnd_ndr1_1 X8 -->
% 6.60/6.13 (bnd_c3_2 X8 X9 | bnd_c2_2 X8 X9) | bnd_c4_2 X8 X9) |
% 6.60/6.13 bnd_c1_1 X8)) |
% 6.60/6.13 bnd_c2_0)) &
% 6.60/6.13 ((~ bnd_c2_0 |
% 6.60/6.13 ((bnd_ndr1_0 & bnd_c2_1 bnd_a400) & ~ bnd_c1_1 bnd_a400) &
% 6.60/6.13 (ALL X10. bnd_ndr1_1 bnd_a400 --> ~ bnd_c3_2 bnd_a400 X10)) |
% 6.60/6.13 (((bnd_ndr1_0 & bnd_ndr1_1 bnd_a401) &
% 6.60/6.13 bnd_c2_2 bnd_a401 bnd_a402) &
% 6.60/6.13 ~ bnd_c1_2 bnd_a401 bnd_a402) &
% 6.60/6.13 bnd_c4_1 bnd_a401)) &
% 6.60/6.13 (((ALL X11.
% 6.60/6.13 bnd_ndr1_0 -->
% 6.60/6.13 (bnd_c2_1 X11 | bnd_c1_1 X11) | ~ bnd_c3_1 X11) |
% 6.60/6.13 ~ bnd_c5_0) |
% 6.60/6.13 ((((bnd_ndr1_0 & bnd_c1_1 bnd_a403) & bnd_ndr1_1 bnd_a403) &
% 6.60/6.13 bnd_c3_2 bnd_a403 bnd_a404) &
% 6.60/6.13 ~ bnd_c4_2 bnd_a403 bnd_a404) &
% 6.60/6.13 bnd_c2_1 bnd_a403)) &
% 6.60/6.13 (bnd_c5_0 | bnd_c4_0)) &
% 6.60/6.13 ((~ bnd_c5_0 | bnd_c1_0) | bnd_c3_0)) &
% 6.60/6.13 ((ALL X12.
% 6.60/6.13 bnd_ndr1_0 -->
% 6.60/6.13 (~ bnd_c1_1 X12 |
% 6.60/6.13 (ALL X13.
% 6.60/6.13 bnd_ndr1_1 X12 -->
% 6.60/6.13 (bnd_c2_2 X12 X13 | ~ bnd_c3_2 X12 X13) |
% 6.60/6.13 bnd_c5_2 X12 X13)) |
% 6.60/6.13 ((bnd_ndr1_1 X12 & ~ bnd_c5_2 X12 bnd_a405) &
% 6.60/6.13 ~ bnd_c2_2 X12 bnd_a405) &
% 6.60/6.13 ~ bnd_c1_2 X12 bnd_a405) |
% 6.60/6.13 (ALL X14.
% 6.60/6.13 bnd_ndr1_0 -->
% 6.60/6.13 (ALL X15.
% 6.60/6.13 bnd_ndr1_1 X14 --> bnd_c1_2 X14 X15 | bnd_c3_2 X14 X15) |
% 6.60/6.13 ((bnd_ndr1_1 X14 & bnd_c4_2 X14 bnd_a406) &
% 6.60/6.13 bnd_c2_2 X14 bnd_a406) &
% 6.60/6.13 bnd_c3_2 X14 bnd_a406))) &
% 6.60/6.13 (((((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a407) &
% 6.60/6.13 ~ bnd_c3_2 bnd_a407 bnd_a408) &
% 6.60/6.13 bnd_c1_2 bnd_a407 bnd_a408) &
% 6.60/6.13 ~ bnd_c5_2 bnd_a407 bnd_a408) &
% 6.60/6.13 ~ bnd_c2_1 bnd_a407) &
% 6.60/6.13 bnd_ndr1_1 bnd_a407) &
% 6.60/6.13 ~ bnd_c3_2 bnd_a407 bnd_a409) &
% 6.60/6.13 bnd_c1_2 bnd_a407 bnd_a409) &
% 6.60/6.13 bnd_c2_2 bnd_a407 bnd_a409 |
% 6.60/6.13 (ALL X16.
% 6.60/6.13 bnd_ndr1_0 -->
% 6.60/6.13 (bnd_c5_1 X16 |
% 6.60/6.13 (ALL X17.
% 6.60/6.13 bnd_ndr1_1 X16 --> bnd_c2_2 X16 X17 | bnd_c1_2 X16 X17)) |
% 6.60/6.13 (ALL X18.
% 6.60/6.13 bnd_ndr1_1 X16 --> ~ bnd_c4_2 X16 X18 | bnd_c2_2 X16 X18)))) &
% 6.60/6.13 (bnd_c2_0 | ~ bnd_c5_0)) &
% 6.60/6.13 ((bnd_c1_0 |
% 6.60/6.13 (ALL X19.
% 6.60/6.13 bnd_ndr1_0 -->
% 6.60/6.13 ((bnd_ndr1_1 X19 & bnd_c1_2 X19 bnd_a410) &
% 6.60/6.13 ~ bnd_c4_2 X19 bnd_a410) &
% 6.60/6.13 bnd_c2_2 X19 bnd_a410 |
% 6.60/6.13 bnd_c4_1 X19)) |
% 6.60/6.13 bnd_c4_0))
% 8.00/7.56 Unfolded term: ~ ((((((((((((((((((((((ALL U.
% 8.00/7.56 bnd_ndr1_0 -->
% 8.00/7.56 (ALL V.
% 8.00/7.56 bnd_ndr1_1 U -->
% 8.00/7.56 bnd_c3_2 U V | bnd_c2_2 U V) |
% 8.00/7.56 bnd_c3_1 U) |
% 8.00/7.56 ~ bnd_c1_0) |
% 8.00/7.56 ~ bnd_c5_0) &
% 8.00/7.56 ((ALL W.
% 8.00/7.56 bnd_ndr1_0 -->
% 8.00/7.56 (((bnd_ndr1_1 W & bnd_c5_2 W bnd_a387) &
% 8.00/7.56 bnd_c2_2 W bnd_a387) &
% 8.00/7.56 bnd_c3_2 W bnd_a387 |
% 8.00/7.56 ((bnd_ndr1_1 W & bnd_c3_2 W bnd_a388) &
% 8.00/7.56 ~ bnd_c1_2 W bnd_a388) &
% 8.00/7.56 bnd_c2_2 W bnd_a388) |
% 8.00/7.56 bnd_c2_1 W) |
% 8.00/7.56 (ALL X.
% 8.00/7.56 bnd_ndr1_0 -->
% 8.00/7.56 (~ bnd_c1_1 X | ~ bnd_c5_1 X) |
% 8.00/7.56 (bnd_ndr1_1 X & bnd_c1_2 X bnd_a389) &
% 8.00/7.56 ~ bnd_c3_2 X bnd_a389))) &
% 8.00/7.56 (((ALL Y.
% 8.00/7.56 bnd_ndr1_0 -->
% 8.00/7.56 (bnd_c3_1 Y |
% 8.00/7.56 (ALL Z.
% 8.00/7.56 bnd_ndr1_1 Y -->
% 8.00/7.56 bnd_c1_2 Y Z | ~ bnd_c3_2 Y Z)) |
% 8.00/7.56 bnd_c5_1 Y) |
% 8.00/7.56 (bnd_ndr1_0 & ~ bnd_c1_1 bnd_a390) &
% 8.00/7.56 (ALL X1.
% 8.00/7.56 bnd_ndr1_1 bnd_a390 -->
% 8.00/7.56 bnd_c1_2 bnd_a390 X1 | bnd_c5_2 bnd_a390 X1)) |
% 8.00/7.56 ((bnd_ndr1_0 &
% 8.00/7.56 (ALL X2.
% 8.00/7.56 bnd_ndr1_1 bnd_a391 -->
% 8.00/7.56 (bnd_c4_2 bnd_a391 X2 | ~ bnd_c1_2 bnd_a391 X2) |
% 8.00/7.56 ~ bnd_c3_2 bnd_a391 X2)) &
% 8.00/7.56 ~ bnd_c3_1 bnd_a391) &
% 8.00/7.56 (ALL X3.
% 8.00/7.56 bnd_ndr1_1 bnd_a391 -->
% 8.00/7.56 (bnd_c4_2 bnd_a391 X3 | bnd_c1_2 bnd_a391 X3) |
% 8.00/7.56 ~ bnd_c5_2 bnd_a391 X3))) &
% 8.00/7.56 (~ bnd_c4_0 |
% 8.00/7.56 (ALL X4.
% 8.00/7.56 bnd_ndr1_0 -->
% 8.00/7.56 (bnd_c4_1 X4 | bnd_c2_1 X4) | bnd_c5_1 X4))) &
% 8.00/7.56 ((((bnd_ndr1_0 & bnd_c5_1 bnd_a392) & bnd_c3_1 bnd_a392) &
% 8.00/7.56 bnd_c1_1 bnd_a392 |
% 8.00/7.56 bnd_c5_0) |
% 8.00/7.56 (((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a393) &
% 8.00/7.56 ~ bnd_c2_2 bnd_a393 bnd_a394) &
% 8.00/7.56 ~ bnd_c3_2 bnd_a393 bnd_a394) &
% 8.00/7.56 bnd_c5_2 bnd_a393 bnd_a394) &
% 8.00/7.56 bnd_ndr1_1 bnd_a393) &
% 8.00/7.56 ~ bnd_c1_2 bnd_a393 bnd_a395) &
% 8.00/7.56 bnd_c2_2 bnd_a393 bnd_a395) &
% 8.00/7.56 bnd_c3_1 bnd_a393)) &
% 8.00/7.56 ((~ bnd_c1_0 |
% 8.00/7.56 (((((bnd_ndr1_0 & ~ bnd_c3_1 bnd_a396) &
% 8.00/7.56 bnd_c4_1 bnd_a396) &
% 8.00/7.56 bnd_ndr1_1 bnd_a396) &
% 8.00/7.56 ~ bnd_c5_2 bnd_a396 bnd_a397) &
% 8.00/7.56 ~ bnd_c4_2 bnd_a396 bnd_a397) &
% 8.00/7.56 bnd_c3_2 bnd_a396 bnd_a397) |
% 8.00/7.56 ~ bnd_c2_0)) &
% 8.00/7.56 ((bnd_c3_0 | bnd_c4_0) |
% 8.00/7.56 (ALL X5.
% 8.00/7.56 bnd_ndr1_0 -->
% 8.00/7.56 (~ bnd_c3_1 X5 |
% 8.00/7.56 bnd_ndr1_1 X5 & bnd_c3_2 X5 bnd_a398) |
% 8.00/7.56 ~ bnd_c1_1 X5))) &
% 8.00/7.56 ((bnd_c4_0 | ~ bnd_c5_0) | ~ bnd_c2_0)) &
% 8.00/7.56 (~ bnd_c2_0 | ~ bnd_c3_0)) &
% 8.00/7.56 ((ALL X6.
% 8.00/7.56 bnd_ndr1_0 -->
% 8.00/7.56 (bnd_c4_1 X6 | bnd_c5_1 X6) | ~ bnd_c3_1 X6) |
% 8.00/7.56 ~ bnd_c2_0)) &
% 8.00/7.56 (((bnd_ndr1_0 & ~ bnd_c2_1 bnd_a399) &
% 8.00/7.56 (ALL X7.
% 8.00/7.56 bnd_ndr1_1 bnd_a399 -->
% 8.00/7.56 (~ bnd_c2_2 bnd_a399 X7 | ~ bnd_c1_2 bnd_a399 X7) |
% 8.00/7.56 ~ bnd_c5_2 bnd_a399 X7) |
% 8.00/7.56 bnd_c3_0) |
% 8.00/7.56 ~ bnd_c5_0)) &
% 8.00/7.56 ((bnd_c3_0 |
% 8.00/7.56 (ALL X8.
% 8.00/7.56 bnd_ndr1_0 -->
% 8.00/7.56 (ALL X9.
% 8.00/7.56 bnd_ndr1_1 X8 -->
% 8.00/7.56 (bnd_c3_2 X8 X9 | bnd_c2_2 X8 X9) | bnd_c4_2 X8 X9) |
% 8.00/7.56 bnd_c1_1 X8)) |
% 8.00/7.56 bnd_c2_0)) &
% 8.00/7.56 ((~ bnd_c2_0 |
% 8.00/7.56 ((bnd_ndr1_0 & bnd_c2_1 bnd_a400) & ~ bnd_c1_1 bnd_a400) &
% 8.00/7.56 (ALL X10. bnd_ndr1_1 bnd_a400 --> ~ bnd_c3_2 bnd_a400 X10)) |
% 8.00/7.56 (((bnd_ndr1_0 & bnd_ndr1_1 bnd_a401) &
% 8.00/7.56 bnd_c2_2 bnd_a401 bnd_a402) &
% 8.00/7.56 ~ bnd_c1_2 bnd_a401 bnd_a402) &
% 8.00/7.56 bnd_c4_1 bnd_a401)) &
% 8.00/7.56 (((ALL X11.
% 8.00/7.56 bnd_ndr1_0 -->
% 8.00/7.56 (bnd_c2_1 X11 | bnd_c1_1 X11) | ~ bnd_c3_1 X11) |
% 8.00/7.56 ~ bnd_c5_0) |
% 8.00/7.56 ((((bnd_ndr1_0 & bnd_c1_1 bnd_a403) & bnd_ndr1_1 bnd_a403) &
% 8.00/7.56 bnd_c3_2 bnd_a403 bnd_a404) &
% 8.00/7.56 ~ bnd_c4_2 bnd_a403 bnd_a404) &
% 8.00/7.56 bnd_c2_1 bnd_a403)) &
% 8.00/7.56 (bnd_c5_0 | bnd_c4_0)) &
% 8.00/7.56 ((~ bnd_c5_0 | bnd_c1_0) | bnd_c3_0)) &
% 8.00/7.56 ((ALL X12.
% 8.00/7.56 bnd_ndr1_0 -->
% 8.00/7.56 (~ bnd_c1_1 X12 |
% 8.00/7.56 (ALL X13.
% 8.00/7.56 bnd_ndr1_1 X12 -->
% 8.00/7.56 (bnd_c2_2 X12 X13 | ~ bnd_c3_2 X12 X13) |
% 8.00/7.56 bnd_c5_2 X12 X13)) |
% 8.00/7.56 ((bnd_ndr1_1 X12 & ~ bnd_c5_2 X12 bnd_a405) &
% 8.00/7.56 ~ bnd_c2_2 X12 bnd_a405) &
% 8.00/7.56 ~ bnd_c1_2 X12 bnd_a405) |
% 8.00/7.56 (ALL X14.
% 8.00/7.56 bnd_ndr1_0 -->
% 8.00/7.56 (ALL X15.
% 8.00/7.56 bnd_ndr1_1 X14 --> bnd_c1_2 X14 X15 | bnd_c3_2 X14 X15) |
% 8.00/7.56 ((bnd_ndr1_1 X14 & bnd_c4_2 X14 bnd_a406) &
% 8.00/7.56 bnd_c2_2 X14 bnd_a406) &
% 8.00/7.56 bnd_c3_2 X14 bnd_a406))) &
% 8.00/7.56 (((((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a407) &
% 8.00/7.56 ~ bnd_c3_2 bnd_a407 bnd_a408) &
% 8.00/7.56 bnd_c1_2 bnd_a407 bnd_a408) &
% 8.00/7.56 ~ bnd_c5_2 bnd_a407 bnd_a408) &
% 8.00/7.56 ~ bnd_c2_1 bnd_a407) &
% 8.00/7.56 bnd_ndr1_1 bnd_a407) &
% 8.00/7.56 ~ bnd_c3_2 bnd_a407 bnd_a409) &
% 8.00/7.56 bnd_c1_2 bnd_a407 bnd_a409) &
% 8.00/7.56 bnd_c2_2 bnd_a407 bnd_a409 |
% 8.00/7.56 (ALL X16.
% 8.00/7.56 bnd_ndr1_0 -->
% 8.00/7.56 (bnd_c5_1 X16 |
% 8.00/7.56 (ALL X17.
% 8.00/7.56 bnd_ndr1_1 X16 --> bnd_c2_2 X16 X17 | bnd_c1_2 X16 X17)) |
% 8.00/7.56 (ALL X18.
% 8.00/7.56 bnd_ndr1_1 X16 --> ~ bnd_c4_2 X16 X18 | bnd_c2_2 X16 X18)))) &
% 8.00/7.56 (bnd_c2_0 | ~ bnd_c5_0)) &
% 8.00/7.56 ((bnd_c1_0 |
% 8.00/7.56 (ALL X19.
% 8.00/7.56 bnd_ndr1_0 -->
% 8.00/7.56 ((bnd_ndr1_1 X19 & bnd_c1_2 X19 bnd_a410) &
% 8.00/7.56 ~ bnd_c4_2 X19 bnd_a410) &
% 8.00/7.56 bnd_c2_2 X19 bnd_a410 |
% 8.00/7.56 bnd_c4_1 X19)) |
% 8.00/7.56 bnd_c4_0))
% 8.00/7.56 Adding axioms...
% 8.00/7.56 Typedef.type_definition_def
% 12.21/11.73 ...done.
% 12.21/11.74 Ground types: ?'b, TPTP_Interpret.ind
% 12.21/11.74 Translating term (sizes: 1, 1) ...
% 15.72/15.20 Invoking SAT solver...
% 15.72/15.30 Model found:
% 15.72/15.30 Size of types: ?'b: 1, TPTP_Interpret.ind: 1
% 15.72/15.30 bnd_a410: ??.TPTP_Interpret.ind0
% 15.72/15.30 bnd_a409: ??.TPTP_Interpret.ind0
% 15.72/15.30 bnd_a408: ??.TPTP_Interpret.ind0
% 15.72/15.30 bnd_a407: ??.TPTP_Interpret.ind0
% 15.72/15.30 bnd_a406: ??.TPTP_Interpret.ind0
% 15.72/15.30 bnd_a405: ??.TPTP_Interpret.ind0
% 15.72/15.30 bnd_a404: ??.TPTP_Interpret.ind0
% 15.72/15.30 bnd_a403: ??.TPTP_Interpret.ind0
% 15.72/15.30 bnd_a402: ??.TPTP_Interpret.ind0
% 15.72/15.30 bnd_a401: ??.TPTP_Interpret.ind0
% 15.72/15.30 bnd_a400: ??.TPTP_Interpret.ind0
% 15.72/15.30 bnd_a399: ??.TPTP_Interpret.ind0
% 15.72/15.30 bnd_a398: ??.TPTP_Interpret.ind0
% 15.72/15.30 bnd_c3_0: True
% 15.72/15.30 bnd_c2_0: False
% 15.72/15.30 bnd_a397: ??.TPTP_Interpret.ind0
% 15.72/15.30 bnd_a396: ??.TPTP_Interpret.ind0
% 15.72/15.30 bnd_a395: ??.TPTP_Interpret.ind0
% 15.72/15.30 bnd_a394: ??.TPTP_Interpret.ind0
% 15.72/15.30 bnd_a393: ??.TPTP_Interpret.ind0
% 15.72/15.30 bnd_a392: ??.TPTP_Interpret.ind0
% 15.72/15.30 bnd_c4_1: {(??.TPTP_Interpret.ind0, True)}
% 15.72/15.30 bnd_c4_0: True
% 15.72/15.30 bnd_c4_2: {(??.TPTP_Interpret.ind0, {(??.TPTP_Interpret.ind0, False)})}
% 15.72/15.30 bnd_a391: ??.TPTP_Interpret.ind0
% 15.72/15.30 bnd_a390: ??.TPTP_Interpret.ind0
% 15.72/15.30 bnd_a389: ??.TPTP_Interpret.ind0
% 15.72/15.30 bnd_c5_1: {(??.TPTP_Interpret.ind0, True)}
% 15.72/15.30 bnd_c1_1: {(??.TPTP_Interpret.ind0, True)}
% 15.72/15.30 bnd_c2_1: {(??.TPTP_Interpret.ind0, False)}
% 15.72/15.30 bnd_c1_2: {(??.TPTP_Interpret.ind0, {(??.TPTP_Interpret.ind0, True)})}
% 15.72/15.30 bnd_a388: ??.TPTP_Interpret.ind0
% 15.72/15.30 bnd_a387: ??.TPTP_Interpret.ind0
% 15.72/15.30 bnd_c5_2: {(??.TPTP_Interpret.ind0, {(??.TPTP_Interpret.ind0, False)})}
% 15.72/15.30 bnd_c5_0: False
% 15.72/15.30 bnd_c1_0: True
% 15.72/15.30 bnd_c3_1: {(??.TPTP_Interpret.ind0, True)}
% 15.72/15.30 bnd_c2_2: {(??.TPTP_Interpret.ind0, {(??.TPTP_Interpret.ind0, True)})}
% 15.72/15.30 bnd_c3_2: {(??.TPTP_Interpret.ind0, {(??.TPTP_Interpret.ind0, False)})}
% 15.72/15.30 bnd_ndr1_1: {(??.TPTP_Interpret.ind0, True)}
% 15.72/15.30 bnd_ndr1_0: True
% 15.72/15.30
% 15.72/15.30 % SZS status CounterSatisfiable
%------------------------------------------------------------------------------