TSTP Solution File: SYN514+1 by Refute---2015
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%------------------------------------------------------------------------------
% File : Refute---2015
% Problem : SYN514+1 : TPTP v6.4.0. Released v2.1.0.
% Transfm : none
% Format : tptp:raw
% Command : isabelle tptp_refute %d %s
% Computer : n101.star.cs.uiowa.edu
% Model : x86_64 x86_64
% CPU : Intel(R) Xeon(R) CPU E5-2609 0 2.40GHz
% Memory : 32218.75MB
% OS : Linux 3.10.0-327.10.1.el7.x86_64
% CPULimit : 300s
% DateTime : Thu Apr 14 06:42:11 EDT 2016
% Result : CounterSatisfiable 87.16s
% Output : Assurance 0s
% Verified :
% SZS Type : None (Parsing solution fails)
% Syntax : Number of formulae : 0
% Comments :
%------------------------------------------------------------------------------
%----No solution output by system
%------------------------------------------------------------------------------
%----ORIGINAL SYSTEM OUTPUT
% 0.00/0.03 % Problem : SYN514+1 : TPTP v6.4.0. Released v2.1.0.
% 0.00/0.04 % Command : isabelle tptp_refute %d %s
% 0.02/0.23 % Computer : n101.star.cs.uiowa.edu
% 0.02/0.23 % Model : x86_64 x86_64
% 0.02/0.23 % CPU : Intel(R) Xeon(R) CPU E5-2609 0 @ 2.40GHz
% 0.02/0.23 % Memory : 32218.75MB
% 0.02/0.23 % OS : Linux 3.10.0-327.10.1.el7.x86_64
% 0.02/0.23 % CPULimit : 300
% 0.02/0.23 % DateTime : Sat Apr 9 00:11:24 CDT 2016
% 0.02/0.23 % CPUTime:
% 6.29/7.23 > val it = (): unit
% 6.81/7.77 Trying to find a model that refutes: ~ ((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((~ bnd_c4_0 &
% 6.81/7.77 ((bnd_c1_0 | bnd_c3_0) |
% 6.81/7.77 (ALL U.
% 6.81/7.77 bnd_ndr1_0 -->
% 6.81/7.77 (~ bnd_c2_1 U |
% 6.81/7.77 (ALL V.
% 6.81/7.77 bnd_ndr1_1 U --> (bnd_c5_2 U V | ~ bnd_c3_2 U V) | ~ bnd_c4_2 U V)) |
% 6.81/7.77 (ALL W.
% 6.81/7.77 bnd_ndr1_1 U --> (~ bnd_c1_2 U W | ~ bnd_c3_2 U W) | ~ bnd_c5_2 U W)))) &
% 6.81/7.77 ((bnd_c1_0 | bnd_c5_0) | ~ bnd_c2_0)) &
% 6.81/7.77 ((bnd_c1_0 | ~ bnd_c2_0) | ~ bnd_c5_0)) &
% 6.81/7.77 ((bnd_c1_0 | ~ bnd_c2_0) |
% 6.81/7.77 (ALL X.
% 6.81/7.77 bnd_ndr1_0 -->
% 6.81/7.77 ((bnd_ndr1_1 X & bnd_c3_2 X bnd_a175) &
% 6.81/7.77 bnd_c5_2 X bnd_a175) &
% 6.81/7.77 ~ bnd_c4_2 X bnd_a175 |
% 6.81/7.77 ((bnd_ndr1_1 X & bnd_c3_2 X bnd_a176) &
% 6.81/7.77 ~ bnd_c2_2 X bnd_a176) &
% 6.81/7.77 ~ bnd_c5_2 X bnd_a176))) &
% 6.81/7.77 ((bnd_c1_0 | ~ bnd_c3_0) |
% 6.81/7.77 ((bnd_ndr1_0 & bnd_c3_1 bnd_a177) &
% 6.81/7.77 (ALL Y.
% 6.81/7.77 bnd_ndr1_1 bnd_a177 -->
% 6.81/7.77 bnd_c2_2 bnd_a177 Y |
% 6.81/7.77 ~ bnd_c5_2 bnd_a177 Y)) &
% 6.81/7.77 (ALL Z.
% 6.81/7.77 bnd_ndr1_1 bnd_a177 -->
% 6.81/7.77 (bnd_c4_2 bnd_a177 Z | bnd_c5_2 bnd_a177 Z) |
% 6.81/7.77 ~ bnd_c1_2 bnd_a177 Z))) &
% 6.81/7.77 ((bnd_c1_0 | ~ bnd_c5_0) |
% 6.81/7.77 (ALL X1.
% 6.81/7.77 bnd_ndr1_0 -->
% 6.81/7.77 (~ bnd_c1_1 X1 |
% 6.81/7.77 (ALL X2.
% 6.81/7.77 bnd_ndr1_1 X1 -->
% 6.81/7.77 bnd_c3_2 X1 X2 | ~ bnd_c5_2 X1 X2)) |
% 6.81/7.77 (ALL X3.
% 6.81/7.77 bnd_ndr1_1 X1 -->
% 6.81/7.77 ~ bnd_c2_2 X1 X3 | ~ bnd_c3_2 X1 X3)))) &
% 6.81/7.77 (bnd_c1_0 |
% 6.81/7.77 (ALL X4.
% 6.81/7.77 bnd_ndr1_0 -->
% 6.81/7.77 ~ bnd_c5_1 X4 |
% 6.81/7.77 ((bnd_ndr1_1 X4 & bnd_c3_2 X4 bnd_a178) &
% 6.81/7.77 bnd_c4_2 X4 bnd_a178) &
% 6.81/7.77 bnd_c5_2 X4 bnd_a178))) &
% 6.81/7.77 (bnd_c1_0 |
% 6.81/7.77 ((((bnd_ndr1_0 & ~ bnd_c3_1 bnd_a179) &
% 6.81/7.77 bnd_ndr1_1 bnd_a179) &
% 6.81/7.77 bnd_c5_2 bnd_a179 bnd_a180) &
% 6.81/7.77 ~ bnd_c1_2 bnd_a179 bnd_a180) &
% 6.81/7.77 ~ bnd_c3_2 bnd_a179 bnd_a180)) &
% 6.81/7.77 ((bnd_c2_0 | bnd_c3_0) |
% 6.81/7.77 (ALL X5.
% 6.81/7.77 bnd_ndr1_0 -->
% 6.81/7.77 (bnd_c5_1 X5 | ~ bnd_c1_1 X5) |
% 6.81/7.77 (ALL X6.
% 6.81/7.77 bnd_ndr1_1 X5 -->
% 6.81/7.77 (bnd_c3_2 X5 X6 | bnd_c5_2 X5 X6) |
% 6.81/7.77 ~ bnd_c4_2 X5 X6)))) &
% 6.81/7.77 ((bnd_c2_0 | bnd_c5_0) |
% 6.81/7.77 (ALL X7.
% 6.81/7.77 bnd_ndr1_0 -->
% 6.81/7.77 (bnd_c5_1 X7 |
% 6.81/7.77 (ALL X8.
% 6.81/7.77 bnd_ndr1_1 X7 -->
% 6.81/7.77 bnd_c1_2 X7 X8 | ~ bnd_c4_2 X7 X8)) |
% 6.81/7.77 ((bnd_ndr1_1 X7 & bnd_c1_2 X7 bnd_a181) &
% 6.81/7.77 bnd_c5_2 X7 bnd_a181) &
% 6.81/7.77 ~ bnd_c3_2 X7 bnd_a181))) &
% 6.81/7.77 ((bnd_c2_0 | ~ bnd_c3_0) |
% 6.81/7.77 (bnd_ndr1_0 & ~ bnd_c2_1 bnd_a182) &
% 6.81/7.77 (ALL X9.
% 6.81/7.77 bnd_ndr1_1 bnd_a182 -->
% 6.81/7.77 (bnd_c1_2 bnd_a182 X9 | bnd_c5_2 bnd_a182 X9) |
% 6.81/7.77 ~ bnd_c4_2 bnd_a182 X9))) &
% 6.81/7.77 (bnd_c2_0 | ~ bnd_c5_0)) &
% 6.81/7.77 ((bnd_c2_0 | ~ bnd_c5_0) |
% 6.81/7.77 (ALL X10.
% 6.81/7.77 bnd_ndr1_0 -->
% 6.81/7.77 (~ bnd_c4_1 X10 |
% 6.81/7.77 (ALL X11.
% 6.81/7.77 bnd_ndr1_1 X10 -->
% 6.81/7.77 bnd_c3_2 X10 X11 | ~ bnd_c4_2 X10 X11)) |
% 6.81/7.77 ((bnd_ndr1_1 X10 & bnd_c2_2 X10 bnd_a183) &
% 6.81/7.77 bnd_c4_2 X10 bnd_a183) &
% 6.81/7.77 ~ bnd_c3_2 X10 bnd_a183))) &
% 6.81/7.77 (bnd_c2_0 |
% 6.81/7.77 (ALL X12.
% 6.81/7.77 bnd_ndr1_0 -->
% 6.81/7.77 (bnd_c2_1 X12 | ~ bnd_c3_1 X12) | ~ bnd_c4_1 X12))) &
% 6.81/7.77 (bnd_c2_0 |
% 6.81/7.77 (ALL X13.
% 6.81/7.77 bnd_ndr1_0 -->
% 6.81/7.77 (~ bnd_c5_1 X13 |
% 6.81/7.77 (ALL X14.
% 6.81/7.77 bnd_ndr1_1 X13 -->
% 6.81/7.77 (bnd_c3_2 X13 X14 | bnd_c4_2 X13 X14) |
% 6.81/7.77 bnd_c5_2 X13 X14)) |
% 6.81/7.77 ((bnd_ndr1_1 X13 & bnd_c1_2 X13 bnd_a184) &
% 6.81/7.77 bnd_c3_2 X13 bnd_a184) &
% 6.81/7.77 ~ bnd_c4_2 X13 bnd_a184))) &
% 6.81/7.77 ((bnd_c2_0 |
% 6.81/7.77 (bnd_ndr1_0 & bnd_c2_1 bnd_a185) &
% 6.81/7.77 (ALL X15.
% 6.81/7.77 bnd_ndr1_1 bnd_a185 -->
% 6.81/7.77 bnd_c4_2 bnd_a185 X15 | ~ bnd_c2_2 bnd_a185 X15)) |
% 6.81/7.77 (((((bnd_ndr1_0 & ~ bnd_c1_1 bnd_a186) &
% 6.81/7.77 (ALL X16.
% 6.81/7.77 bnd_ndr1_1 bnd_a186 -->
% 6.81/7.77 (~ bnd_c1_2 bnd_a186 X16 |
% 6.81/7.77 ~ bnd_c2_2 bnd_a186 X16) |
% 6.81/7.77 ~ bnd_c3_2 bnd_a186 X16)) &
% 6.81/7.77 bnd_ndr1_1 bnd_a186) &
% 6.81/7.77 bnd_c1_2 bnd_a186 bnd_a187) &
% 6.81/7.77 ~ bnd_c2_2 bnd_a186 bnd_a187) &
% 6.81/7.77 ~ bnd_c3_2 bnd_a186 bnd_a187)) &
% 6.81/7.77 (bnd_c2_0 |
% 6.81/7.77 ((bnd_ndr1_0 & bnd_c5_1 bnd_a188) &
% 6.81/7.77 (ALL X17.
% 6.81/7.77 bnd_ndr1_1 bnd_a188 -->
% 6.81/7.77 (bnd_c2_2 bnd_a188 X17 | ~ bnd_c3_2 bnd_a188 X17) |
% 6.81/7.77 ~ bnd_c4_2 bnd_a188 X17)) &
% 6.81/7.77 (ALL X18.
% 6.81/7.77 bnd_ndr1_1 bnd_a188 -->
% 6.81/7.77 bnd_c2_2 bnd_a188 X18 | ~ bnd_c4_2 bnd_a188 X18))) &
% 6.81/7.77 (bnd_c3_0 |
% 6.81/7.77 (bnd_ndr1_0 & ~ bnd_c3_1 bnd_a189) &
% 6.81/7.77 (ALL X19.
% 6.81/7.77 bnd_ndr1_1 bnd_a189 -->
% 6.81/7.77 (bnd_c1_2 bnd_a189 X19 | ~ bnd_c4_2 bnd_a189 X19) |
% 6.81/7.77 ~ bnd_c5_2 bnd_a189 X19))) &
% 6.81/7.77 ((bnd_c3_0 | bnd_c5_0) |
% 6.81/7.77 (ALL X20.
% 6.81/7.77 bnd_ndr1_0 -->
% 6.81/7.77 (~ bnd_c5_1 X20 |
% 6.81/7.77 (ALL X21.
% 6.81/7.77 bnd_ndr1_1 X20 -->
% 6.81/7.77 (bnd_c3_2 X20 X21 | bnd_c4_2 X20 X21) |
% 6.81/7.77 ~ bnd_c1_2 X20 X21)) |
% 6.81/7.77 ((bnd_ndr1_1 X20 & bnd_c1_2 X20 bnd_a190) &
% 6.81/7.77 bnd_c2_2 X20 bnd_a190) &
% 6.81/7.77 ~ bnd_c5_2 X20 bnd_a190))) &
% 6.81/7.77 ((bnd_c3_0 | bnd_c5_0) |
% 6.81/7.77 (bnd_ndr1_0 & bnd_c2_1 bnd_a191) & ~ bnd_c1_1 bnd_a191)) &
% 6.81/7.77 ((bnd_c3_0 | bnd_c5_0) |
% 6.81/7.77 ((bnd_ndr1_0 & bnd_c2_1 bnd_a192) & ~ bnd_c4_1 bnd_a192) &
% 6.81/7.77 (ALL X22.
% 6.81/7.77 bnd_ndr1_1 bnd_a192 -->
% 6.81/7.77 (bnd_c2_2 bnd_a192 X22 | bnd_c3_2 bnd_a192 X22) |
% 6.81/7.77 ~ bnd_c5_2 bnd_a192 X22))) &
% 6.81/7.77 ((bnd_c3_0 | bnd_c5_0) |
% 6.81/7.77 ((bnd_ndr1_0 & bnd_c5_1 bnd_a193) &
% 6.81/7.77 (ALL X23.
% 6.81/7.77 bnd_ndr1_1 bnd_a193 -->
% 6.81/7.77 (bnd_c1_2 bnd_a193 X23 | bnd_c3_2 bnd_a193 X23) |
% 6.81/7.77 bnd_c4_2 bnd_a193 X23)) &
% 6.81/7.77 (ALL X24.
% 6.81/7.77 bnd_ndr1_1 bnd_a193 -->
% 6.81/7.77 (bnd_c3_2 bnd_a193 X24 | ~ bnd_c4_2 bnd_a193 X24) |
% 6.81/7.77 ~ bnd_c5_2 bnd_a193 X24))) &
% 6.81/7.77 ((bnd_c3_0 | ~ bnd_c5_0) |
% 6.81/7.77 ((bnd_ndr1_0 & bnd_c1_1 bnd_a194) & ~ bnd_c3_1 bnd_a194) &
% 6.81/7.77 (ALL X25.
% 6.81/7.77 bnd_ndr1_1 bnd_a194 -->
% 6.81/7.77 (bnd_c5_2 bnd_a194 X25 | ~ bnd_c1_2 bnd_a194 X25) |
% 6.81/7.77 ~ bnd_c4_2 bnd_a194 X25))) &
% 6.81/7.77 ((bnd_c3_0 |
% 6.81/7.77 (ALL X26.
% 6.81/7.77 bnd_ndr1_0 -->
% 6.81/7.77 (bnd_c1_1 X26 | bnd_c2_1 X26) |
% 6.81/7.77 ((bnd_ndr1_1 X26 & bnd_c1_2 X26 bnd_a195) &
% 6.81/7.77 bnd_c3_2 X26 bnd_a195) &
% 6.81/7.77 bnd_c5_2 X26 bnd_a195)) |
% 6.81/7.77 (ALL X27.
% 6.81/7.77 bnd_ndr1_0 -->
% 6.81/7.77 ((ALL X28.
% 6.81/7.77 bnd_ndr1_1 X27 -->
% 6.81/7.77 ~ bnd_c1_2 X27 X28 | ~ bnd_c2_2 X27 X28) |
% 6.81/7.77 (ALL X29.
% 6.81/7.77 bnd_ndr1_1 X27 -->
% 6.81/7.77 (~ bnd_c3_2 X27 X29 | ~ bnd_c4_2 X27 X29) |
% 6.81/7.77 ~ bnd_c5_2 X27 X29)) |
% 6.81/7.77 ((bnd_ndr1_1 X27 & bnd_c4_2 X27 bnd_a196) &
% 6.81/7.77 ~ bnd_c3_2 X27 bnd_a196) &
% 6.81/7.77 ~ bnd_c5_2 X27 bnd_a196))) &
% 6.81/7.77 ((bnd_c3_0 |
% 6.81/7.77 (ALL X30.
% 6.81/7.77 bnd_ndr1_0 -->
% 6.81/7.77 (bnd_c2_1 X30 | bnd_c4_1 X30) |
% 6.81/7.77 (ALL X31.
% 6.81/7.77 bnd_ndr1_1 X30 -->
% 6.81/7.77 (bnd_c4_2 X30 X31 | ~ bnd_c1_2 X30 X31) |
% 6.81/7.77 ~ bnd_c2_2 X30 X31))) |
% 6.81/7.77 (ALL X32.
% 6.81/7.77 bnd_ndr1_0 -->
% 6.81/7.77 (bnd_c5_1 X32 | ~ bnd_c2_1 X32) |
% 6.81/7.77 ((bnd_ndr1_1 X32 & ~ bnd_c1_2 X32 bnd_a197) &
% 6.81/7.77 ~ bnd_c2_2 X32 bnd_a197) &
% 6.81/7.77 ~ bnd_c5_2 X32 bnd_a197))) &
% 6.81/7.77 ((bnd_c3_0 |
% 6.81/7.77 (ALL X33.
% 6.81/7.77 bnd_ndr1_0 -->
% 6.81/7.77 (~ bnd_c4_1 X33 | ~ bnd_c5_1 X33) |
% 6.81/7.77 (bnd_ndr1_1 X33 & bnd_c5_2 X33 bnd_a198) &
% 6.81/7.77 ~ bnd_c1_2 X33 bnd_a198)) |
% 6.81/7.77 ((bnd_ndr1_0 & ~ bnd_c1_1 bnd_a199) & ~ bnd_c4_1 bnd_a199) &
% 6.81/7.77 (ALL X34.
% 6.81/7.77 bnd_ndr1_1 bnd_a199 -->
% 6.81/7.77 (bnd_c3_2 bnd_a199 X34 | ~ bnd_c1_2 bnd_a199 X34) |
% 6.81/7.77 ~ bnd_c4_2 bnd_a199 X34))) &
% 6.81/7.77 ((bnd_c3_0 | bnd_ndr1_0 & bnd_c2_1 bnd_a200) |
% 6.81/7.77 (bnd_ndr1_0 & bnd_c2_1 bnd_a201) & ~ bnd_c1_1 bnd_a201)) &
% 6.81/7.77 (bnd_c5_0 | ~ bnd_c2_0)) &
% 6.81/7.77 (bnd_c5_0 |
% 6.81/7.77 (bnd_ndr1_0 & bnd_c3_1 bnd_a202) &
% 6.81/7.77 (ALL X35.
% 6.81/7.77 bnd_ndr1_1 bnd_a202 -->
% 6.81/7.77 (bnd_c2_2 bnd_a202 X35 | bnd_c5_2 bnd_a202 X35) |
% 6.81/7.77 ~ bnd_c1_2 bnd_a202 X35))) &
% 6.81/7.77 (~ bnd_c5_0 |
% 6.81/7.77 (ALL X36.
% 6.81/7.77 bnd_ndr1_0 -->
% 6.81/7.77 (bnd_c2_1 X36 |
% 6.81/7.77 (bnd_ndr1_1 X36 & bnd_c4_2 X36 bnd_a203) & ~ bnd_c1_2 X36 bnd_a203) |
% 6.81/7.77 (bnd_ndr1_1 X36 & bnd_c4_2 X36 bnd_a204) &
% 6.81/7.77 ~ bnd_c2_2 X36 bnd_a204))) &
% 6.81/7.77 ((ALL X37.
% 6.81/7.77 bnd_ndr1_0 -->
% 6.81/7.77 (bnd_c2_1 X37 | bnd_c5_1 X37) |
% 6.81/7.77 (ALL X38.
% 6.81/7.77 bnd_ndr1_1 X37 -->
% 6.81/7.77 (bnd_c3_2 X37 X38 | ~ bnd_c2_2 X37 X38) | ~ bnd_c4_2 X37 X38)) |
% 6.81/7.77 (ALL X39.
% 6.81/7.77 bnd_ndr1_0 -->
% 6.81/7.77 (bnd_c4_1 X39 |
% 6.81/7.77 (ALL X40.
% 6.81/7.77 bnd_ndr1_1 X39 -->
% 6.81/7.77 (bnd_c2_2 X39 X40 | ~ bnd_c1_2 X39 X40) | ~ bnd_c3_2 X39 X40)) |
% 6.81/7.77 ((bnd_ndr1_1 X39 & bnd_c3_2 X39 bnd_a205) & bnd_c4_2 X39 bnd_a205) &
% 6.81/7.77 bnd_c5_2 X39 bnd_a205))) &
% 6.81/7.77 ((ALL X41.
% 6.81/7.77 bnd_ndr1_0 -->
% 6.81/7.77 (bnd_c4_1 X41 |
% 6.81/7.77 (ALL X42. bnd_ndr1_1 X41 --> bnd_c2_2 X41 X42 | ~ bnd_c1_2 X41 X42)) |
% 6.81/7.77 (bnd_ndr1_1 X41 & bnd_c3_2 X41 bnd_a206) & bnd_c5_2 X41 bnd_a206) |
% 6.81/7.77 (((((bnd_ndr1_0 & bnd_c4_1 bnd_a207) & ~ bnd_c2_1 bnd_a207) &
% 6.81/7.77 bnd_ndr1_1 bnd_a207) &
% 6.81/7.77 bnd_c4_2 bnd_a207 bnd_a208) &
% 6.81/7.77 bnd_c5_2 bnd_a207 bnd_a208) &
% 6.81/7.77 ~ bnd_c3_2 bnd_a207 bnd_a208)) &
% 6.81/7.77 ((bnd_c5_0 | ~ bnd_c1_0) |
% 6.81/7.77 ((((bnd_ndr1_0 & bnd_c3_1 bnd_a209) &
% 6.81/7.77 ~ bnd_c4_1 bnd_a209) &
% 6.81/7.77 bnd_ndr1_1 bnd_a209) &
% 6.81/7.77 bnd_c2_2 bnd_a209 bnd_a210) &
% 6.81/7.77 ~ bnd_c3_2 bnd_a209 bnd_a210)) &
% 6.81/7.77 (bnd_c5_0 | ~ bnd_c2_0)) &
% 6.81/7.77 ((bnd_c5_0 | ~ bnd_c3_0) |
% 6.81/7.77 (((((bnd_ndr1_0 & bnd_c3_1 bnd_a211) &
% 6.81/7.77 (ALL X43.
% 6.81/7.77 bnd_ndr1_1 bnd_a211 -->
% 6.81/7.77 (bnd_c2_2 bnd_a211 X43 | bnd_c5_2 bnd_a211 X43) |
% 6.81/7.77 ~ bnd_c1_2 bnd_a211 X43)) &
% 6.81/7.77 bnd_ndr1_1 bnd_a211) &
% 6.81/7.77 bnd_c2_2 bnd_a211 bnd_a212) &
% 6.81/7.77 bnd_c5_2 bnd_a211 bnd_a212) &
% 6.81/7.77 ~ bnd_c1_2 bnd_a211 bnd_a212)) &
% 6.81/7.77 ((bnd_c5_0 |
% 6.81/7.77 (ALL X44.
% 6.81/7.77 bnd_ndr1_0 -->
% 6.81/7.77 bnd_c2_1 X44 |
% 6.81/7.77 (bnd_ndr1_1 X44 & bnd_c4_2 X44 bnd_a213) & ~ bnd_c2_2 X44 bnd_a213)) |
% 6.81/7.77 (((((bnd_ndr1_0 & ~ bnd_c3_1 bnd_a214) &
% 6.81/7.77 (ALL X45.
% 6.81/7.77 bnd_ndr1_1 bnd_a214 -->
% 6.81/7.77 (bnd_c3_2 bnd_a214 X45 | ~ bnd_c2_2 bnd_a214 X45) |
% 6.81/7.77 ~ bnd_c4_2 bnd_a214 X45)) &
% 6.81/7.77 bnd_ndr1_1 bnd_a214) &
% 6.81/7.77 ~ bnd_c1_2 bnd_a214 bnd_a215) &
% 6.81/7.77 ~ bnd_c3_2 bnd_a214 bnd_a215) &
% 6.81/7.77 ~ bnd_c5_2 bnd_a214 bnd_a215)) &
% 6.81/7.77 (bnd_c5_0 |
% 6.81/7.77 (ALL X46.
% 6.81/7.77 bnd_ndr1_0 -->
% 6.81/7.77 (bnd_c3_1 X46 |
% 6.81/7.77 (bnd_ndr1_1 X46 & bnd_c2_2 X46 bnd_a216) & ~ bnd_c3_2 X46 bnd_a216) |
% 6.81/7.77 (bnd_ndr1_1 X46 &
% 6.81/7.77 bnd_c3_2 X46 bnd_a217) &
% 6.81/7.77 ~ bnd_c2_2 X46 bnd_a217))) &
% 6.81/7.77 ((bnd_c5_0 |
% 6.81/7.77 (ALL X47.
% 6.81/7.77 bnd_ndr1_0 -->
% 6.81/7.77 (~ bnd_c1_1 X47 |
% 6.81/7.77 (ALL X48.
% 6.81/7.77 bnd_ndr1_1 X47 -->
% 6.81/7.77 (bnd_c1_2 X47 X48 | bnd_c4_2 X47 X48) | bnd_c5_2 X47 X48)) |
% 6.81/7.77 ((bnd_ndr1_1 X47 &
% 6.81/7.77 bnd_c1_2 X47 bnd_a218) &
% 6.81/7.77 bnd_c2_2 X47 bnd_a218) &
% 6.81/7.77 ~ bnd_c5_2 X47 bnd_a218)) |
% 6.81/7.77 (((bnd_ndr1_0 & ~ bnd_c3_1 bnd_a219) &
% 6.81/7.77 bnd_ndr1_1 bnd_a219) &
% 6.81/7.77 bnd_c2_2 bnd_a219 bnd_a220) &
% 6.81/7.77 ~ bnd_c3_2 bnd_a219 bnd_a220)) &
% 6.81/7.77 (bnd_c5_0 |
% 6.81/7.77 (ALL X49.
% 6.81/7.77 bnd_ndr1_0 -->
% 6.81/7.77 ((ALL X50.
% 6.81/7.77 bnd_ndr1_1 X49 -->
% 6.81/7.77 (bnd_c1_2 X49 X50 | bnd_c5_2 X49 X50) | ~ bnd_c4_2 X49 X50) |
% 6.81/7.77 (ALL X51.
% 6.81/7.77 bnd_ndr1_1 X49 -->
% 6.81/7.77 (bnd_c2_2 X49 X51 | ~ bnd_c1_2 X49 X51) | ~ bnd_c5_2 X49 X51)) |
% 6.81/7.77 ((bnd_ndr1_1 X49 &
% 6.81/7.77 bnd_c2_2 X49 bnd_a221) &
% 6.81/7.77 bnd_c4_2 X49 bnd_a221) &
% 6.81/7.77 bnd_c5_2 X49 bnd_a221))) &
% 6.81/7.77 (bnd_c5_0 |
% 6.81/7.77 (ALL X52.
% 6.81/7.77 bnd_ndr1_0 -->
% 6.81/7.77 ((ALL X53.
% 6.81/7.77 bnd_ndr1_1 X52 --> bnd_c1_2 X52 X53 | ~ bnd_c5_2 X52 X53) |
% 6.81/7.77 (bnd_ndr1_1 X52 &
% 6.81/7.77 bnd_c1_2 X52 bnd_a222) &
% 6.81/7.77 ~ bnd_c2_2 X52 bnd_a222) |
% 6.81/7.77 ((bnd_ndr1_1 X52 &
% 6.81/7.77 bnd_c2_2 X52 bnd_a223) &
% 6.81/7.77 bnd_c3_2 X52 bnd_a223) &
% 6.81/7.77 ~ bnd_c5_2 X52 bnd_a223))) &
% 6.81/7.77 (bnd_c5_0 |
% 6.81/7.77 (ALL X54.
% 6.81/7.77 bnd_ndr1_0 -->
% 6.81/7.77 ((ALL X55.
% 6.81/7.77 bnd_ndr1_1 X54 -->
% 6.81/7.77 (bnd_c2_2 X54 X55 | ~ bnd_c3_2 X54 X55) | ~ bnd_c5_2 X54 X55) |
% 6.81/7.77 (ALL X56.
% 6.81/7.77 bnd_ndr1_1 X54 -->
% 6.81/7.77 (bnd_c3_2 X54 X56 | bnd_c5_2 X54 X56) | ~ bnd_c4_2 X54 X56)) |
% 6.81/7.77 ((bnd_ndr1_1 X54 & bnd_c1_2 X54 bnd_a224) &
% 6.81/7.77 bnd_c4_2 X54 bnd_a224) &
% 6.81/7.77 ~ bnd_c5_2 X54 bnd_a224))) &
% 6.81/7.77 ((bnd_c5_0 |
% 6.81/7.77 ((bnd_ndr1_0 & bnd_c3_1 bnd_a225) &
% 6.81/7.77 bnd_c4_1 bnd_a225) &
% 6.81/7.77 (ALL X57.
% 6.81/7.77 bnd_ndr1_1 bnd_a225 -->
% 6.81/7.77 bnd_c1_2 bnd_a225 X57 |
% 6.81/7.77 ~ bnd_c2_2 bnd_a225 X57)) |
% 6.81/7.77 (bnd_ndr1_0 &
% 6.81/7.77 (ALL X58.
% 6.81/7.77 bnd_ndr1_1 bnd_a226 -->
% 6.81/7.77 (bnd_c1_2 bnd_a226 X58 |
% 6.81/7.77 ~ bnd_c2_2 bnd_a226 X58) |
% 6.81/7.77 ~ bnd_c4_2 bnd_a226 X58)) &
% 6.81/7.77 (ALL X59.
% 6.81/7.77 bnd_ndr1_1 bnd_a226 -->
% 6.81/7.77 (~ bnd_c2_2 bnd_a226 X59 |
% 6.81/7.77 ~ bnd_c3_2 bnd_a226 X59) |
% 6.81/7.77 ~ bnd_c4_2 bnd_a226 X59))) &
% 6.81/7.77 (~ bnd_c1_0 | ~ bnd_c2_0)) &
% 6.81/7.77 ((~ bnd_c1_0 | ~ bnd_c2_0) | ~ bnd_c3_0)) &
% 6.81/7.77 ((~ bnd_c1_0 | ~ bnd_c3_0) | ~ bnd_c5_0)) &
% 6.81/7.77 ((~ bnd_c1_0 | ~ bnd_c3_0) |
% 6.81/7.77 (((((bnd_ndr1_0 & bnd_c3_1 bnd_a227) &
% 6.81/7.77 (ALL X60.
% 6.81/7.77 bnd_ndr1_1 bnd_a227 -->
% 6.81/7.77 (bnd_c2_2 bnd_a227 X60 |
% 6.81/7.77 ~ bnd_c3_2 bnd_a227 X60) |
% 6.81/7.77 ~ bnd_c4_2 bnd_a227 X60)) &
% 6.81/7.77 bnd_ndr1_1 bnd_a227) &
% 6.81/7.77 bnd_c4_2 bnd_a227 bnd_a228) &
% 6.81/7.77 ~ bnd_c2_2 bnd_a227 bnd_a228) &
% 6.81/7.77 ~ bnd_c5_2 bnd_a227 bnd_a228)) &
% 6.81/7.77 ((~ bnd_c1_0 | ~ bnd_c5_0) |
% 6.81/7.77 ((((bnd_ndr1_0 & ~ bnd_c3_1 bnd_a229) &
% 6.81/7.77 ~ bnd_c4_1 bnd_a229) &
% 6.81/7.77 bnd_ndr1_1 bnd_a229) &
% 6.81/7.77 bnd_c3_2 bnd_a229 bnd_a230) &
% 6.81/7.77 bnd_c4_2 bnd_a229 bnd_a230)) &
% 6.81/7.77 ((~ bnd_c1_0 |
% 6.81/7.77 (ALL X61.
% 6.81/7.77 bnd_ndr1_0 -->
% 6.81/7.77 (bnd_c4_1 X61 | ~ bnd_c1_1 X61) |
% 6.81/7.77 (ALL X62.
% 6.81/7.77 bnd_ndr1_1 X61 -->
% 6.81/7.77 bnd_c1_2 X61 X62 | ~ bnd_c4_2 X61 X62))) |
% 6.81/7.77 ((((bnd_ndr1_0 & ~ bnd_c2_1 bnd_a231) &
% 6.81/7.77 bnd_ndr1_1 bnd_a231) &
% 6.81/7.77 bnd_c1_2 bnd_a231 bnd_a232) &
% 6.81/7.77 bnd_c2_2 bnd_a231 bnd_a232) &
% 6.81/7.77 bnd_c5_2 bnd_a231 bnd_a232)) &
% 6.81/7.77 ((~ bnd_c1_0 |
% 6.81/7.77 (ALL X63.
% 6.81/7.77 bnd_ndr1_0 -->
% 6.81/7.77 (bnd_c4_1 X63 |
% 6.81/7.77 (ALL X64.
% 6.81/7.77 bnd_ndr1_1 X63 -->
% 6.81/7.77 (bnd_c3_2 X63 X64 | ~ bnd_c4_2 X63 X64) |
% 6.81/7.77 ~ bnd_c5_2 X63 X64)) |
% 6.81/7.77 (bnd_ndr1_1 X63 & bnd_c3_2 X63 bnd_a233) &
% 6.81/7.77 ~ bnd_c5_2 X63 bnd_a233)) |
% 6.81/7.77 (ALL X65.
% 6.81/7.77 bnd_ndr1_0 -->
% 6.81/7.77 (bnd_c5_1 X65 | ~ bnd_c4_1 X65) |
% 6.81/7.77 (ALL X66.
% 6.81/7.77 bnd_ndr1_1 X65 -->
% 6.81/7.77 bnd_c2_2 X65 X66 | ~ bnd_c3_2 X65 X66)))) &
% 6.81/7.77 ((~ bnd_c1_0 |
% 6.81/7.77 (ALL X67.
% 6.81/7.77 bnd_ndr1_0 -->
% 6.81/7.77 (~ bnd_c5_1 X67 |
% 6.81/7.77 (ALL X68.
% 6.81/7.77 bnd_ndr1_1 X67 -->
% 6.81/7.77 bnd_c1_2 X67 X68 | ~ bnd_c3_2 X67 X68)) |
% 6.81/7.77 (bnd_ndr1_1 X67 & bnd_c5_2 X67 bnd_a234) &
% 6.81/7.77 ~ bnd_c4_2 X67 bnd_a234)) |
% 6.81/7.77 (((((bnd_ndr1_0 & ~ bnd_c1_1 bnd_a235) &
% 6.81/7.77 (ALL X69.
% 6.81/7.77 bnd_ndr1_1 bnd_a235 -->
% 6.81/7.77 (bnd_c3_2 bnd_a235 X69 |
% 6.81/7.77 bnd_c4_2 bnd_a235 X69) |
% 6.81/7.77 ~ bnd_c5_2 bnd_a235 X69)) &
% 6.81/7.77 bnd_ndr1_1 bnd_a235) &
% 6.81/7.77 ~ bnd_c2_2 bnd_a235 bnd_a236) &
% 6.81/7.77 ~ bnd_c4_2 bnd_a235 bnd_a236) &
% 6.81/7.77 ~ bnd_c5_2 bnd_a235 bnd_a236)) &
% 6.81/7.77 (~ bnd_c2_0 |
% 6.81/7.77 ((bnd_ndr1_0 & bnd_c3_1 bnd_a237) &
% 6.81/7.77 ~ bnd_c4_1 bnd_a237) &
% 6.81/7.77 (ALL X70.
% 6.81/7.77 bnd_ndr1_1 bnd_a237 -->
% 6.81/7.77 bnd_c5_2 bnd_a237 X70 | ~ bnd_c3_2 bnd_a237 X70))) &
% 6.81/7.77 (~ bnd_c3_0 | ~ bnd_c5_0)) &
% 6.81/7.77 (~ bnd_c3_0 |
% 6.81/7.77 (ALL X71.
% 6.81/7.77 bnd_ndr1_0 -->
% 6.81/7.77 bnd_c1_1 X71 |
% 6.81/7.77 (ALL X72.
% 6.81/7.77 bnd_ndr1_1 X71 -->
% 6.81/7.77 ~ bnd_c1_2 X71 X72 | ~ bnd_c3_2 X71 X72)))) &
% 6.81/7.77 ((~ bnd_c3_0 |
% 6.81/7.77 (ALL X73.
% 6.81/7.77 bnd_ndr1_0 -->
% 6.81/7.77 (bnd_c3_1 X73 | bnd_c5_1 X73) |
% 6.81/7.77 (bnd_ndr1_1 X73 & bnd_c4_2 X73 bnd_a238) &
% 6.81/7.77 ~ bnd_c1_2 X73 bnd_a238)) |
% 6.81/7.77 (ALL X74.
% 6.81/7.77 bnd_ndr1_0 -->
% 6.81/7.77 (bnd_c5_1 X74 |
% 6.81/7.77 (ALL X75.
% 6.81/7.77 bnd_ndr1_1 X74 -->
% 6.81/7.77 (bnd_c4_2 X74 X75 | ~ bnd_c1_2 X74 X75) |
% 6.81/7.77 ~ bnd_c3_2 X74 X75)) |
% 6.81/7.77 (ALL X76.
% 6.81/7.77 bnd_ndr1_1 X74 -->
% 6.81/7.77 (~ bnd_c1_2 X74 X76 | ~ bnd_c3_2 X74 X76) |
% 6.81/7.77 ~ bnd_c4_2 X74 X76)))) &
% 6.81/7.77 ((~ bnd_c3_0 |
% 6.81/7.77 (ALL X77.
% 6.81/7.77 bnd_ndr1_0 -->
% 6.81/7.77 (bnd_c4_1 X77 | bnd_c5_1 X77) | ~ bnd_c1_1 X77)) |
% 6.81/7.77 (ALL X78.
% 6.81/7.77 bnd_ndr1_0 -->
% 6.81/7.77 bnd_c5_1 X78 |
% 6.81/7.77 (ALL X79.
% 6.81/7.77 bnd_ndr1_1 X78 -->
% 6.81/7.77 (bnd_c2_2 X78 X79 | bnd_c5_2 X78 X79) |
% 6.81/7.77 ~ bnd_c1_2 X78 X79)))) &
% 6.81/7.77 ((~ bnd_c3_0 |
% 6.81/7.77 (ALL X80. bnd_ndr1_0 --> bnd_c4_1 X80 | ~ bnd_c5_1 X80)) |
% 6.81/7.77 (ALL X81.
% 6.81/7.77 bnd_ndr1_0 -->
% 6.81/7.77 (~ bnd_c3_1 X81 | ~ bnd_c5_1 X81) |
% 6.81/7.77 ((bnd_ndr1_1 X81 & bnd_c1_2 X81 bnd_a239) &
% 6.81/7.77 bnd_c3_2 X81 bnd_a239) &
% 6.81/7.77 bnd_c4_2 X81 bnd_a239))) &
% 6.81/7.77 ((~ bnd_c3_0 |
% 6.81/7.77 (ALL X82.
% 6.81/7.77 bnd_ndr1_0 -->
% 6.81/7.77 (bnd_c5_1 X82 |
% 6.81/7.77 (ALL X83.
% 6.81/7.77 bnd_ndr1_1 X82 -->
% 6.81/7.77 (bnd_c4_2 X82 X83 | ~ bnd_c1_2 X82 X83) |
% 6.81/7.77 ~ bnd_c2_2 X82 X83)) |
% 6.81/7.77 (ALL X84.
% 6.81/7.77 bnd_ndr1_1 X82 -->
% 6.81/7.77 ~ bnd_c1_2 X82 X84 | ~ bnd_c5_2 X82 X84))) |
% 6.81/7.77 (bnd_ndr1_0 & bnd_c2_1 bnd_a240) & ~ bnd_c3_1 bnd_a240)) &
% 6.81/7.77 (((ALL X85.
% 6.81/7.77 bnd_ndr1_0 -->
% 6.81/7.77 (bnd_c1_1 X85 | ~ bnd_c2_1 X85) |
% 6.81/7.77 (ALL X86.
% 6.81/7.77 bnd_ndr1_1 X85 -->
% 6.81/7.77 (bnd_c1_2 X85 X86 | bnd_c3_2 X85 X86) |
% 6.81/7.77 ~ bnd_c4_2 X85 X86)) |
% 6.81/7.77 (ALL X87.
% 6.81/7.77 bnd_ndr1_0 -->
% 6.81/7.77 (bnd_c1_1 X87 | ~ bnd_c2_1 X87) |
% 6.81/7.77 (ALL X88.
% 6.81/7.77 bnd_ndr1_1 X87 -->
% 6.81/7.77 bnd_c1_2 X87 X88 | bnd_c4_2 X87 X88))) |
% 6.81/7.77 (((((bnd_ndr1_0 & bnd_c4_1 bnd_a241) &
% 6.81/7.77 (ALL X89.
% 6.81/7.77 bnd_ndr1_1 bnd_a241 --> ~ bnd_c4_2 bnd_a241 X89)) &
% 6.81/7.77 bnd_ndr1_1 bnd_a241) &
% 6.81/7.77 bnd_c3_2 bnd_a241 bnd_a242) &
% 6.81/7.77 ~ bnd_c2_2 bnd_a241 bnd_a242) &
% 6.81/7.77 ~ bnd_c4_2 bnd_a241 bnd_a242)) &
% 6.81/7.77 (((ALL X90.
% 6.81/7.77 bnd_ndr1_0 -->
% 6.81/7.77 (bnd_c2_1 X90 | bnd_c3_1 X90) |
% 6.81/7.77 (ALL X91.
% 6.81/7.77 bnd_ndr1_1 X90 -->
% 6.81/7.77 (bnd_c3_2 X90 X91 | ~ bnd_c2_2 X90 X91) |
% 6.81/7.77 ~ bnd_c4_2 X90 X91)) |
% 6.81/7.77 (ALL X92.
% 6.81/7.77 bnd_ndr1_0 -->
% 6.81/7.77 ~ bnd_c4_1 X92 |
% 6.81/7.77 (ALL X93.
% 6.81/7.77 bnd_ndr1_1 X92 -->
% 6.81/7.77 (~ bnd_c1_2 X92 X93 | ~ bnd_c2_2 X92 X93) |
% 6.81/7.77 ~ bnd_c5_2 X92 X93))) |
% 6.81/7.77 ((((bnd_ndr1_0 & ~ bnd_c2_1 bnd_a243) &
% 6.81/7.77 (ALL X94.
% 6.81/7.77 bnd_ndr1_1 bnd_a243 -->
% 6.81/7.77 (bnd_c1_2 bnd_a243 X94 | bnd_c4_2 bnd_a243 X94) |
% 6.81/7.77 ~ bnd_c3_2 bnd_a243 X94)) &
% 6.81/7.77 bnd_ndr1_1 bnd_a243) &
% 6.81/7.77 bnd_c2_2 bnd_a243 bnd_a244) &
% 6.81/7.77 ~ bnd_c3_2 bnd_a243 bnd_a244)) &
% 6.81/7.77 (((ALL X95.
% 6.81/7.77 bnd_ndr1_0 -->
% 6.81/7.77 (bnd_c2_1 X95 |
% 6.81/7.77 (ALL X96.
% 6.81/7.77 bnd_ndr1_1 X95 -->
% 6.81/7.77 (bnd_c1_2 X95 X96 | bnd_c5_2 X95 X96) |
% 6.81/7.77 ~ bnd_c4_2 X95 X96)) |
% 6.81/7.77 (ALL X97.
% 6.81/7.77 bnd_ndr1_1 X95 -->
% 6.81/7.77 bnd_c2_2 X95 X97 | ~ bnd_c5_2 X95 X97)) |
% 6.81/7.77 (ALL X98.
% 6.81/7.77 bnd_ndr1_0 -->
% 6.81/7.77 bnd_c3_1 X98 |
% 6.81/7.77 (ALL X99.
% 6.81/7.77 bnd_ndr1_1 X98 -->
% 6.81/7.77 bnd_c1_2 X98 X99 | bnd_c2_2 X98 X99))) |
% 6.81/7.77 (ALL X100.
% 6.81/7.77 bnd_ndr1_0 -->
% 6.81/7.77 (bnd_c4_1 X100 | ~ bnd_c5_1 X100) |
% 6.81/7.77 (ALL X101.
% 6.81/7.77 bnd_ndr1_1 X100 -->
% 6.81/7.77 (bnd_c2_2 X100 X101 | bnd_c4_2 X100 X101) |
% 6.81/7.77 ~ bnd_c5_2 X100 X101)))) &
% 6.81/7.77 (((ALL X102.
% 6.81/7.77 bnd_ndr1_0 -->
% 6.81/7.77 (bnd_c3_1 X102 |
% 6.81/7.77 ((bnd_ndr1_1 X102 & bnd_c1_2 X102 bnd_a245) &
% 6.81/7.77 bnd_c4_2 X102 bnd_a245) &
% 6.81/7.77 bnd_c5_2 X102 bnd_a245) |
% 6.81/7.77 ((bnd_ndr1_1 X102 & ~ bnd_c1_2 X102 bnd_a246) &
% 6.81/7.77 ~ bnd_c4_2 X102 bnd_a246) &
% 6.81/7.77 ~ bnd_c5_2 X102 bnd_a246) |
% 6.81/7.77 (ALL X103.
% 6.81/7.77 bnd_ndr1_0 -->
% 6.81/7.77 (bnd_c4_1 X103 | ~ bnd_c3_1 X103) |
% 6.81/7.77 (bnd_ndr1_1 X103 & bnd_c3_2 X103 bnd_a247) &
% 6.81/7.77 ~ bnd_c4_2 X103 bnd_a247)) |
% 6.81/7.77 (bnd_ndr1_0 & bnd_c4_1 bnd_a248) & ~ bnd_c5_1 bnd_a248)) &
% 6.81/7.77 (((ALL X104. bnd_ndr1_0 --> bnd_c4_1 X104 | ~ bnd_c1_1 X104) |
% 6.81/7.77 (ALL X105.
% 6.81/7.77 bnd_ndr1_0 -->
% 6.81/7.77 (~ bnd_c3_1 X105 | ~ bnd_c5_1 X105) |
% 6.81/7.77 (ALL X106.
% 6.81/7.77 bnd_ndr1_1 X105 -->
% 6.81/7.77 (bnd_c2_2 X105 X106 | bnd_c3_2 X105 X106) |
% 6.81/7.77 ~ bnd_c5_2 X105 X106))) |
% 6.81/7.77 ((bnd_ndr1_0 &
% 6.81/7.77 (ALL X107.
% 6.81/7.77 bnd_ndr1_1 bnd_a249 -->
% 6.81/7.77 (bnd_c1_2 bnd_a249 X107 | bnd_c2_2 bnd_a249 X107) |
% 6.81/7.77 bnd_c4_2 bnd_a249 X107)) &
% 6.81/7.77 (ALL X108.
% 6.81/7.77 bnd_ndr1_1 bnd_a249 -->
% 6.81/7.77 bnd_c1_2 bnd_a249 X108 | ~ bnd_c5_2 bnd_a249 X108)) &
% 6.81/7.77 (ALL X109.
% 6.81/7.77 bnd_ndr1_1 bnd_a249 -->
% 6.81/7.77 (bnd_c4_2 bnd_a249 X109 | ~ bnd_c1_2 bnd_a249 X109) |
% 6.81/7.77 ~ bnd_c2_2 bnd_a249 X109))) &
% 6.81/7.77 ((ALL X110.
% 6.81/7.77 bnd_ndr1_0 -->
% 6.81/7.77 (bnd_c4_1 X110 | ~ bnd_c5_1 X110) |
% 6.81/7.77 (bnd_ndr1_1 X110 & bnd_c1_2 X110 bnd_a250) &
% 6.81/7.77 ~ bnd_c4_2 X110 bnd_a250) |
% 6.81/7.77 (ALL X111.
% 6.81/7.77 bnd_ndr1_0 -->
% 6.81/7.77 (~ bnd_c1_1 X111 | ~ bnd_c2_1 X111) |
% 6.81/7.77 (ALL X112.
% 6.81/7.77 bnd_ndr1_1 X111 -->
% 6.81/7.77 bnd_c5_2 X111 X112 | ~ bnd_c2_2 X111 X112)))) &
% 6.81/7.77 (((ALL X113.
% 6.81/7.77 bnd_ndr1_0 -->
% 6.81/7.77 (bnd_c5_1 X113 |
% 6.81/7.77 (bnd_ndr1_1 X113 & bnd_c1_2 X113 bnd_a251) &
% 6.81/7.77 ~ bnd_c5_2 X113 bnd_a251) |
% 6.81/7.77 ((bnd_ndr1_1 X113 & bnd_c2_2 X113 bnd_a252) &
% 6.81/7.77 bnd_c5_2 X113 bnd_a252) &
% 6.81/7.77 ~ bnd_c1_2 X113 bnd_a252) |
% 6.81/7.77 (((((bnd_ndr1_0 & bnd_c1_1 bnd_a253) & ~ bnd_c4_1 bnd_a253) &
% 6.81/7.77 bnd_ndr1_1 bnd_a253) &
% 6.81/7.77 bnd_c2_2 bnd_a253 bnd_a254) &
% 6.81/7.77 bnd_c3_2 bnd_a253 bnd_a254) &
% 6.81/7.77 bnd_c5_2 bnd_a253 bnd_a254) |
% 6.81/7.77 bnd_ndr1_0 & ~ bnd_c3_1 bnd_a255)) &
% 6.81/7.77 (((ALL X114.
% 6.81/7.77 bnd_ndr1_0 -->
% 6.81/7.77 ~ bnd_c2_1 X114 |
% 6.81/7.77 (bnd_ndr1_1 X114 & bnd_c1_2 X114 bnd_a256) &
% 6.81/7.77 bnd_c3_2 X114 bnd_a256) |
% 6.81/7.77 ((((bnd_ndr1_0 & bnd_c4_1 bnd_a257) & ~ bnd_c1_1 bnd_a257) &
% 6.81/7.77 bnd_ndr1_1 bnd_a257) &
% 6.81/7.77 bnd_c5_2 bnd_a257 bnd_a258) &
% 6.81/7.77 ~ bnd_c4_2 bnd_a257 bnd_a258) |
% 6.81/7.77 (bnd_ndr1_0 & ~ bnd_c1_1 bnd_a259) &
% 6.81/7.77 (ALL X115.
% 6.81/7.77 bnd_ndr1_1 bnd_a259 -->
% 6.81/7.77 ~ bnd_c1_2 bnd_a259 X115 | ~ bnd_c5_2 bnd_a259 X115))) &
% 6.81/7.77 (((((((bnd_ndr1_0 & bnd_c1_1 bnd_a260) & ~ bnd_c4_1 bnd_a260) &
% 6.81/7.77 bnd_ndr1_1 bnd_a260) &
% 6.81/7.77 bnd_c1_2 bnd_a260 bnd_a261) &
% 6.81/7.77 bnd_c2_2 bnd_a260 bnd_a261) &
% 6.81/7.77 bnd_c4_2 bnd_a260 bnd_a261 |
% 6.81/7.77 (bnd_ndr1_0 & bnd_c5_1 bnd_a262) &
% 6.81/7.77 (ALL X116.
% 6.81/7.77 bnd_ndr1_1 bnd_a262 -->
% 6.81/7.77 (bnd_c4_2 bnd_a262 X116 | ~ bnd_c3_2 bnd_a262 X116) |
% 6.81/7.77 ~ bnd_c5_2 bnd_a262 X116)) |
% 6.81/7.77 ((((bnd_ndr1_0 & ~ bnd_c1_1 bnd_a263) & bnd_ndr1_1 bnd_a263) &
% 6.81/7.77 bnd_c1_2 bnd_a263 bnd_a264) &
% 6.81/7.77 bnd_c3_2 bnd_a263 bnd_a264) &
% 6.81/7.77 ~ bnd_c4_2 bnd_a263 bnd_a264))
% 12.00/12.92 Unfolded term: ~ ((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((~ bnd_c4_0 &
% 12.00/12.92 ((bnd_c1_0 | bnd_c3_0) |
% 12.00/12.92 (ALL U.
% 12.00/12.92 bnd_ndr1_0 -->
% 12.00/12.92 (~ bnd_c2_1 U |
% 12.00/12.92 (ALL V.
% 12.00/12.92 bnd_ndr1_1 U --> (bnd_c5_2 U V | ~ bnd_c3_2 U V) | ~ bnd_c4_2 U V)) |
% 12.00/12.92 (ALL W.
% 12.00/12.92 bnd_ndr1_1 U --> (~ bnd_c1_2 U W | ~ bnd_c3_2 U W) | ~ bnd_c5_2 U W)))) &
% 12.00/12.92 ((bnd_c1_0 | bnd_c5_0) | ~ bnd_c2_0)) &
% 12.00/12.92 ((bnd_c1_0 | ~ bnd_c2_0) | ~ bnd_c5_0)) &
% 12.00/12.92 ((bnd_c1_0 | ~ bnd_c2_0) |
% 12.00/12.92 (ALL X.
% 12.00/12.92 bnd_ndr1_0 -->
% 12.00/12.92 ((bnd_ndr1_1 X & bnd_c3_2 X bnd_a175) &
% 12.00/12.92 bnd_c5_2 X bnd_a175) &
% 12.00/12.92 ~ bnd_c4_2 X bnd_a175 |
% 12.00/12.92 ((bnd_ndr1_1 X & bnd_c3_2 X bnd_a176) &
% 12.00/12.92 ~ bnd_c2_2 X bnd_a176) &
% 12.00/12.92 ~ bnd_c5_2 X bnd_a176))) &
% 12.00/12.92 ((bnd_c1_0 | ~ bnd_c3_0) |
% 12.00/12.92 ((bnd_ndr1_0 & bnd_c3_1 bnd_a177) &
% 12.00/12.92 (ALL Y.
% 12.00/12.92 bnd_ndr1_1 bnd_a177 -->
% 12.00/12.92 bnd_c2_2 bnd_a177 Y |
% 12.00/12.92 ~ bnd_c5_2 bnd_a177 Y)) &
% 12.00/12.92 (ALL Z.
% 12.00/12.92 bnd_ndr1_1 bnd_a177 -->
% 12.00/12.92 (bnd_c4_2 bnd_a177 Z | bnd_c5_2 bnd_a177 Z) |
% 12.00/12.92 ~ bnd_c1_2 bnd_a177 Z))) &
% 12.00/12.92 ((bnd_c1_0 | ~ bnd_c5_0) |
% 12.00/12.92 (ALL X1.
% 12.00/12.92 bnd_ndr1_0 -->
% 12.00/12.92 (~ bnd_c1_1 X1 |
% 12.00/12.92 (ALL X2.
% 12.00/12.92 bnd_ndr1_1 X1 -->
% 12.00/12.92 bnd_c3_2 X1 X2 | ~ bnd_c5_2 X1 X2)) |
% 12.00/12.92 (ALL X3.
% 12.00/12.92 bnd_ndr1_1 X1 -->
% 12.00/12.92 ~ bnd_c2_2 X1 X3 | ~ bnd_c3_2 X1 X3)))) &
% 12.00/12.92 (bnd_c1_0 |
% 12.00/12.92 (ALL X4.
% 12.00/12.92 bnd_ndr1_0 -->
% 12.00/12.92 ~ bnd_c5_1 X4 |
% 12.00/12.92 ((bnd_ndr1_1 X4 & bnd_c3_2 X4 bnd_a178) &
% 12.00/12.92 bnd_c4_2 X4 bnd_a178) &
% 12.00/12.92 bnd_c5_2 X4 bnd_a178))) &
% 12.00/12.92 (bnd_c1_0 |
% 12.00/12.92 ((((bnd_ndr1_0 & ~ bnd_c3_1 bnd_a179) &
% 12.00/12.92 bnd_ndr1_1 bnd_a179) &
% 12.00/12.92 bnd_c5_2 bnd_a179 bnd_a180) &
% 12.00/12.92 ~ bnd_c1_2 bnd_a179 bnd_a180) &
% 12.00/12.92 ~ bnd_c3_2 bnd_a179 bnd_a180)) &
% 12.00/12.92 ((bnd_c2_0 | bnd_c3_0) |
% 12.00/12.92 (ALL X5.
% 12.00/12.92 bnd_ndr1_0 -->
% 12.00/12.92 (bnd_c5_1 X5 | ~ bnd_c1_1 X5) |
% 12.00/12.92 (ALL X6.
% 12.00/12.92 bnd_ndr1_1 X5 -->
% 12.00/12.92 (bnd_c3_2 X5 X6 | bnd_c5_2 X5 X6) |
% 12.00/12.92 ~ bnd_c4_2 X5 X6)))) &
% 12.00/12.92 ((bnd_c2_0 | bnd_c5_0) |
% 12.00/12.92 (ALL X7.
% 12.00/12.92 bnd_ndr1_0 -->
% 12.00/12.92 (bnd_c5_1 X7 |
% 12.00/12.92 (ALL X8.
% 12.00/12.92 bnd_ndr1_1 X7 -->
% 12.00/12.92 bnd_c1_2 X7 X8 | ~ bnd_c4_2 X7 X8)) |
% 12.00/12.92 ((bnd_ndr1_1 X7 & bnd_c1_2 X7 bnd_a181) &
% 12.00/12.92 bnd_c5_2 X7 bnd_a181) &
% 12.00/12.92 ~ bnd_c3_2 X7 bnd_a181))) &
% 12.00/12.92 ((bnd_c2_0 | ~ bnd_c3_0) |
% 12.00/12.92 (bnd_ndr1_0 & ~ bnd_c2_1 bnd_a182) &
% 12.00/12.92 (ALL X9.
% 12.00/12.92 bnd_ndr1_1 bnd_a182 -->
% 12.00/12.92 (bnd_c1_2 bnd_a182 X9 | bnd_c5_2 bnd_a182 X9) |
% 12.00/12.92 ~ bnd_c4_2 bnd_a182 X9))) &
% 12.00/12.92 (bnd_c2_0 | ~ bnd_c5_0)) &
% 12.00/12.92 ((bnd_c2_0 | ~ bnd_c5_0) |
% 12.00/12.92 (ALL X10.
% 12.00/12.92 bnd_ndr1_0 -->
% 12.00/12.92 (~ bnd_c4_1 X10 |
% 12.00/12.92 (ALL X11.
% 12.00/12.92 bnd_ndr1_1 X10 -->
% 12.00/12.92 bnd_c3_2 X10 X11 | ~ bnd_c4_2 X10 X11)) |
% 12.00/12.92 ((bnd_ndr1_1 X10 & bnd_c2_2 X10 bnd_a183) &
% 12.00/12.92 bnd_c4_2 X10 bnd_a183) &
% 12.00/12.92 ~ bnd_c3_2 X10 bnd_a183))) &
% 12.00/12.92 (bnd_c2_0 |
% 12.00/12.92 (ALL X12.
% 12.00/12.92 bnd_ndr1_0 -->
% 12.00/12.92 (bnd_c2_1 X12 | ~ bnd_c3_1 X12) | ~ bnd_c4_1 X12))) &
% 12.00/12.92 (bnd_c2_0 |
% 12.00/12.92 (ALL X13.
% 12.00/12.92 bnd_ndr1_0 -->
% 12.00/12.92 (~ bnd_c5_1 X13 |
% 12.00/12.92 (ALL X14.
% 12.00/12.92 bnd_ndr1_1 X13 -->
% 12.00/12.92 (bnd_c3_2 X13 X14 | bnd_c4_2 X13 X14) |
% 12.00/12.92 bnd_c5_2 X13 X14)) |
% 12.00/12.92 ((bnd_ndr1_1 X13 & bnd_c1_2 X13 bnd_a184) &
% 12.00/12.92 bnd_c3_2 X13 bnd_a184) &
% 12.00/12.92 ~ bnd_c4_2 X13 bnd_a184))) &
% 12.00/12.92 ((bnd_c2_0 |
% 12.00/12.92 (bnd_ndr1_0 & bnd_c2_1 bnd_a185) &
% 12.00/12.92 (ALL X15.
% 12.00/12.92 bnd_ndr1_1 bnd_a185 -->
% 12.00/12.92 bnd_c4_2 bnd_a185 X15 | ~ bnd_c2_2 bnd_a185 X15)) |
% 12.00/12.92 (((((bnd_ndr1_0 & ~ bnd_c1_1 bnd_a186) &
% 12.00/12.92 (ALL X16.
% 12.00/12.92 bnd_ndr1_1 bnd_a186 -->
% 12.00/12.92 (~ bnd_c1_2 bnd_a186 X16 |
% 12.00/12.92 ~ bnd_c2_2 bnd_a186 X16) |
% 12.00/12.92 ~ bnd_c3_2 bnd_a186 X16)) &
% 12.00/12.92 bnd_ndr1_1 bnd_a186) &
% 12.00/12.92 bnd_c1_2 bnd_a186 bnd_a187) &
% 12.00/12.92 ~ bnd_c2_2 bnd_a186 bnd_a187) &
% 12.00/12.92 ~ bnd_c3_2 bnd_a186 bnd_a187)) &
% 12.00/12.92 (bnd_c2_0 |
% 12.00/12.92 ((bnd_ndr1_0 & bnd_c5_1 bnd_a188) &
% 12.00/12.92 (ALL X17.
% 12.00/12.92 bnd_ndr1_1 bnd_a188 -->
% 12.00/12.92 (bnd_c2_2 bnd_a188 X17 | ~ bnd_c3_2 bnd_a188 X17) |
% 12.00/12.92 ~ bnd_c4_2 bnd_a188 X17)) &
% 12.00/12.92 (ALL X18.
% 12.00/12.92 bnd_ndr1_1 bnd_a188 -->
% 12.00/12.92 bnd_c2_2 bnd_a188 X18 | ~ bnd_c4_2 bnd_a188 X18))) &
% 12.00/12.92 (bnd_c3_0 |
% 12.00/12.92 (bnd_ndr1_0 & ~ bnd_c3_1 bnd_a189) &
% 12.00/12.92 (ALL X19.
% 12.00/12.92 bnd_ndr1_1 bnd_a189 -->
% 12.00/12.92 (bnd_c1_2 bnd_a189 X19 | ~ bnd_c4_2 bnd_a189 X19) |
% 12.00/12.92 ~ bnd_c5_2 bnd_a189 X19))) &
% 12.00/12.92 ((bnd_c3_0 | bnd_c5_0) |
% 12.00/12.92 (ALL X20.
% 12.00/12.92 bnd_ndr1_0 -->
% 12.00/12.92 (~ bnd_c5_1 X20 |
% 12.00/12.92 (ALL X21.
% 12.00/12.92 bnd_ndr1_1 X20 -->
% 12.00/12.92 (bnd_c3_2 X20 X21 | bnd_c4_2 X20 X21) |
% 12.00/12.92 ~ bnd_c1_2 X20 X21)) |
% 12.00/12.92 ((bnd_ndr1_1 X20 & bnd_c1_2 X20 bnd_a190) &
% 12.00/12.92 bnd_c2_2 X20 bnd_a190) &
% 12.00/12.92 ~ bnd_c5_2 X20 bnd_a190))) &
% 12.00/12.92 ((bnd_c3_0 | bnd_c5_0) |
% 12.00/12.92 (bnd_ndr1_0 & bnd_c2_1 bnd_a191) & ~ bnd_c1_1 bnd_a191)) &
% 12.00/12.92 ((bnd_c3_0 | bnd_c5_0) |
% 12.00/12.92 ((bnd_ndr1_0 & bnd_c2_1 bnd_a192) & ~ bnd_c4_1 bnd_a192) &
% 12.00/12.92 (ALL X22.
% 12.00/12.92 bnd_ndr1_1 bnd_a192 -->
% 12.00/12.92 (bnd_c2_2 bnd_a192 X22 | bnd_c3_2 bnd_a192 X22) |
% 12.00/12.92 ~ bnd_c5_2 bnd_a192 X22))) &
% 12.00/12.92 ((bnd_c3_0 | bnd_c5_0) |
% 12.00/12.92 ((bnd_ndr1_0 & bnd_c5_1 bnd_a193) &
% 12.00/12.92 (ALL X23.
% 12.00/12.92 bnd_ndr1_1 bnd_a193 -->
% 12.00/12.92 (bnd_c1_2 bnd_a193 X23 | bnd_c3_2 bnd_a193 X23) |
% 12.00/12.92 bnd_c4_2 bnd_a193 X23)) &
% 12.00/12.92 (ALL X24.
% 12.00/12.92 bnd_ndr1_1 bnd_a193 -->
% 12.00/12.92 (bnd_c3_2 bnd_a193 X24 | ~ bnd_c4_2 bnd_a193 X24) |
% 12.00/12.92 ~ bnd_c5_2 bnd_a193 X24))) &
% 12.00/12.92 ((bnd_c3_0 | ~ bnd_c5_0) |
% 12.00/12.92 ((bnd_ndr1_0 & bnd_c1_1 bnd_a194) & ~ bnd_c3_1 bnd_a194) &
% 12.00/12.92 (ALL X25.
% 12.00/12.92 bnd_ndr1_1 bnd_a194 -->
% 12.00/12.92 (bnd_c5_2 bnd_a194 X25 | ~ bnd_c1_2 bnd_a194 X25) |
% 12.00/12.92 ~ bnd_c4_2 bnd_a194 X25))) &
% 12.00/12.92 ((bnd_c3_0 |
% 12.00/12.92 (ALL X26.
% 12.00/12.92 bnd_ndr1_0 -->
% 12.00/12.92 (bnd_c1_1 X26 | bnd_c2_1 X26) |
% 12.00/12.92 ((bnd_ndr1_1 X26 & bnd_c1_2 X26 bnd_a195) &
% 12.00/12.92 bnd_c3_2 X26 bnd_a195) &
% 12.00/12.92 bnd_c5_2 X26 bnd_a195)) |
% 12.00/12.92 (ALL X27.
% 12.00/12.92 bnd_ndr1_0 -->
% 12.00/12.92 ((ALL X28.
% 12.00/12.92 bnd_ndr1_1 X27 -->
% 12.00/12.92 ~ bnd_c1_2 X27 X28 | ~ bnd_c2_2 X27 X28) |
% 12.00/12.92 (ALL X29.
% 12.00/12.92 bnd_ndr1_1 X27 -->
% 12.00/12.92 (~ bnd_c3_2 X27 X29 | ~ bnd_c4_2 X27 X29) |
% 12.00/12.92 ~ bnd_c5_2 X27 X29)) |
% 12.00/12.92 ((bnd_ndr1_1 X27 & bnd_c4_2 X27 bnd_a196) &
% 12.00/12.92 ~ bnd_c3_2 X27 bnd_a196) &
% 12.00/12.92 ~ bnd_c5_2 X27 bnd_a196))) &
% 12.00/12.92 ((bnd_c3_0 |
% 12.00/12.92 (ALL X30.
% 12.00/12.92 bnd_ndr1_0 -->
% 12.00/12.92 (bnd_c2_1 X30 | bnd_c4_1 X30) |
% 12.00/12.92 (ALL X31.
% 12.00/12.92 bnd_ndr1_1 X30 -->
% 12.00/12.92 (bnd_c4_2 X30 X31 | ~ bnd_c1_2 X30 X31) |
% 12.00/12.92 ~ bnd_c2_2 X30 X31))) |
% 12.00/12.92 (ALL X32.
% 12.00/12.92 bnd_ndr1_0 -->
% 12.00/12.92 (bnd_c5_1 X32 | ~ bnd_c2_1 X32) |
% 12.00/12.92 ((bnd_ndr1_1 X32 & ~ bnd_c1_2 X32 bnd_a197) &
% 12.00/12.92 ~ bnd_c2_2 X32 bnd_a197) &
% 12.00/12.92 ~ bnd_c5_2 X32 bnd_a197))) &
% 12.00/12.92 ((bnd_c3_0 |
% 12.00/12.92 (ALL X33.
% 12.00/12.92 bnd_ndr1_0 -->
% 12.00/12.92 (~ bnd_c4_1 X33 | ~ bnd_c5_1 X33) |
% 12.00/12.92 (bnd_ndr1_1 X33 & bnd_c5_2 X33 bnd_a198) &
% 12.00/12.92 ~ bnd_c1_2 X33 bnd_a198)) |
% 12.00/12.92 ((bnd_ndr1_0 & ~ bnd_c1_1 bnd_a199) & ~ bnd_c4_1 bnd_a199) &
% 12.00/12.92 (ALL X34.
% 12.00/12.92 bnd_ndr1_1 bnd_a199 -->
% 12.00/12.92 (bnd_c3_2 bnd_a199 X34 | ~ bnd_c1_2 bnd_a199 X34) |
% 12.00/12.92 ~ bnd_c4_2 bnd_a199 X34))) &
% 12.00/12.92 ((bnd_c3_0 | bnd_ndr1_0 & bnd_c2_1 bnd_a200) |
% 12.00/12.92 (bnd_ndr1_0 & bnd_c2_1 bnd_a201) & ~ bnd_c1_1 bnd_a201)) &
% 12.00/12.92 (bnd_c5_0 | ~ bnd_c2_0)) &
% 12.00/12.92 (bnd_c5_0 |
% 12.00/12.92 (bnd_ndr1_0 & bnd_c3_1 bnd_a202) &
% 12.00/12.92 (ALL X35.
% 12.00/12.92 bnd_ndr1_1 bnd_a202 -->
% 12.00/12.92 (bnd_c2_2 bnd_a202 X35 | bnd_c5_2 bnd_a202 X35) |
% 12.00/12.92 ~ bnd_c1_2 bnd_a202 X35))) &
% 12.00/12.92 (~ bnd_c5_0 |
% 12.00/12.92 (ALL X36.
% 12.00/12.92 bnd_ndr1_0 -->
% 12.00/12.92 (bnd_c2_1 X36 |
% 12.00/12.92 (bnd_ndr1_1 X36 & bnd_c4_2 X36 bnd_a203) & ~ bnd_c1_2 X36 bnd_a203) |
% 12.00/12.92 (bnd_ndr1_1 X36 & bnd_c4_2 X36 bnd_a204) &
% 12.00/12.92 ~ bnd_c2_2 X36 bnd_a204))) &
% 12.00/12.92 ((ALL X37.
% 12.00/12.92 bnd_ndr1_0 -->
% 12.00/12.92 (bnd_c2_1 X37 | bnd_c5_1 X37) |
% 12.00/12.92 (ALL X38.
% 12.00/12.92 bnd_ndr1_1 X37 -->
% 12.00/12.92 (bnd_c3_2 X37 X38 | ~ bnd_c2_2 X37 X38) | ~ bnd_c4_2 X37 X38)) |
% 12.00/12.92 (ALL X39.
% 12.00/12.92 bnd_ndr1_0 -->
% 12.00/12.92 (bnd_c4_1 X39 |
% 12.00/12.92 (ALL X40.
% 12.00/12.92 bnd_ndr1_1 X39 -->
% 12.00/12.92 (bnd_c2_2 X39 X40 | ~ bnd_c1_2 X39 X40) | ~ bnd_c3_2 X39 X40)) |
% 12.00/12.92 ((bnd_ndr1_1 X39 & bnd_c3_2 X39 bnd_a205) & bnd_c4_2 X39 bnd_a205) &
% 12.00/12.92 bnd_c5_2 X39 bnd_a205))) &
% 12.00/12.92 ((ALL X41.
% 12.00/12.92 bnd_ndr1_0 -->
% 12.00/12.92 (bnd_c4_1 X41 |
% 12.00/12.92 (ALL X42. bnd_ndr1_1 X41 --> bnd_c2_2 X41 X42 | ~ bnd_c1_2 X41 X42)) |
% 12.00/12.92 (bnd_ndr1_1 X41 & bnd_c3_2 X41 bnd_a206) & bnd_c5_2 X41 bnd_a206) |
% 12.00/12.92 (((((bnd_ndr1_0 & bnd_c4_1 bnd_a207) & ~ bnd_c2_1 bnd_a207) &
% 12.00/12.92 bnd_ndr1_1 bnd_a207) &
% 12.00/12.92 bnd_c4_2 bnd_a207 bnd_a208) &
% 12.00/12.92 bnd_c5_2 bnd_a207 bnd_a208) &
% 12.00/12.92 ~ bnd_c3_2 bnd_a207 bnd_a208)) &
% 12.00/12.92 ((bnd_c5_0 | ~ bnd_c1_0) |
% 12.00/12.92 ((((bnd_ndr1_0 & bnd_c3_1 bnd_a209) &
% 12.00/12.92 ~ bnd_c4_1 bnd_a209) &
% 12.00/12.92 bnd_ndr1_1 bnd_a209) &
% 12.00/12.92 bnd_c2_2 bnd_a209 bnd_a210) &
% 12.00/12.92 ~ bnd_c3_2 bnd_a209 bnd_a210)) &
% 12.00/12.92 (bnd_c5_0 | ~ bnd_c2_0)) &
% 12.00/12.92 ((bnd_c5_0 | ~ bnd_c3_0) |
% 12.00/12.92 (((((bnd_ndr1_0 & bnd_c3_1 bnd_a211) &
% 12.00/12.92 (ALL X43.
% 12.00/12.92 bnd_ndr1_1 bnd_a211 -->
% 12.00/12.92 (bnd_c2_2 bnd_a211 X43 | bnd_c5_2 bnd_a211 X43) |
% 12.00/12.92 ~ bnd_c1_2 bnd_a211 X43)) &
% 12.00/12.92 bnd_ndr1_1 bnd_a211) &
% 12.00/12.92 bnd_c2_2 bnd_a211 bnd_a212) &
% 12.00/12.92 bnd_c5_2 bnd_a211 bnd_a212) &
% 12.00/12.92 ~ bnd_c1_2 bnd_a211 bnd_a212)) &
% 12.00/12.92 ((bnd_c5_0 |
% 12.00/12.92 (ALL X44.
% 12.00/12.92 bnd_ndr1_0 -->
% 12.00/12.92 bnd_c2_1 X44 |
% 12.00/12.92 (bnd_ndr1_1 X44 & bnd_c4_2 X44 bnd_a213) & ~ bnd_c2_2 X44 bnd_a213)) |
% 12.00/12.92 (((((bnd_ndr1_0 & ~ bnd_c3_1 bnd_a214) &
% 12.00/12.92 (ALL X45.
% 12.00/12.92 bnd_ndr1_1 bnd_a214 -->
% 12.00/12.92 (bnd_c3_2 bnd_a214 X45 | ~ bnd_c2_2 bnd_a214 X45) |
% 12.00/12.92 ~ bnd_c4_2 bnd_a214 X45)) &
% 12.00/12.92 bnd_ndr1_1 bnd_a214) &
% 12.00/12.92 ~ bnd_c1_2 bnd_a214 bnd_a215) &
% 12.00/12.92 ~ bnd_c3_2 bnd_a214 bnd_a215) &
% 12.00/12.92 ~ bnd_c5_2 bnd_a214 bnd_a215)) &
% 12.00/12.92 (bnd_c5_0 |
% 12.00/12.92 (ALL X46.
% 12.00/12.92 bnd_ndr1_0 -->
% 12.00/12.92 (bnd_c3_1 X46 |
% 12.00/12.92 (bnd_ndr1_1 X46 & bnd_c2_2 X46 bnd_a216) & ~ bnd_c3_2 X46 bnd_a216) |
% 12.00/12.92 (bnd_ndr1_1 X46 &
% 12.00/12.92 bnd_c3_2 X46 bnd_a217) &
% 12.00/12.92 ~ bnd_c2_2 X46 bnd_a217))) &
% 12.00/12.92 ((bnd_c5_0 |
% 12.00/12.92 (ALL X47.
% 12.00/12.92 bnd_ndr1_0 -->
% 12.00/12.92 (~ bnd_c1_1 X47 |
% 12.00/12.92 (ALL X48.
% 12.00/12.92 bnd_ndr1_1 X47 -->
% 12.00/12.92 (bnd_c1_2 X47 X48 | bnd_c4_2 X47 X48) | bnd_c5_2 X47 X48)) |
% 12.00/12.92 ((bnd_ndr1_1 X47 &
% 12.00/12.92 bnd_c1_2 X47 bnd_a218) &
% 12.00/12.92 bnd_c2_2 X47 bnd_a218) &
% 12.00/12.92 ~ bnd_c5_2 X47 bnd_a218)) |
% 12.00/12.92 (((bnd_ndr1_0 & ~ bnd_c3_1 bnd_a219) &
% 12.00/12.92 bnd_ndr1_1 bnd_a219) &
% 12.00/12.92 bnd_c2_2 bnd_a219 bnd_a220) &
% 12.00/12.92 ~ bnd_c3_2 bnd_a219 bnd_a220)) &
% 12.00/12.92 (bnd_c5_0 |
% 12.00/12.92 (ALL X49.
% 12.00/12.92 bnd_ndr1_0 -->
% 12.00/12.92 ((ALL X50.
% 12.00/12.92 bnd_ndr1_1 X49 -->
% 12.00/12.92 (bnd_c1_2 X49 X50 | bnd_c5_2 X49 X50) | ~ bnd_c4_2 X49 X50) |
% 12.00/12.92 (ALL X51.
% 12.00/12.92 bnd_ndr1_1 X49 -->
% 12.00/12.92 (bnd_c2_2 X49 X51 | ~ bnd_c1_2 X49 X51) | ~ bnd_c5_2 X49 X51)) |
% 12.00/12.92 ((bnd_ndr1_1 X49 &
% 12.00/12.92 bnd_c2_2 X49 bnd_a221) &
% 12.00/12.92 bnd_c4_2 X49 bnd_a221) &
% 12.00/12.92 bnd_c5_2 X49 bnd_a221))) &
% 12.00/12.92 (bnd_c5_0 |
% 12.00/12.92 (ALL X52.
% 12.00/12.92 bnd_ndr1_0 -->
% 12.00/12.92 ((ALL X53.
% 12.00/12.92 bnd_ndr1_1 X52 --> bnd_c1_2 X52 X53 | ~ bnd_c5_2 X52 X53) |
% 12.00/12.92 (bnd_ndr1_1 X52 &
% 12.00/12.92 bnd_c1_2 X52 bnd_a222) &
% 12.00/12.92 ~ bnd_c2_2 X52 bnd_a222) |
% 12.00/12.92 ((bnd_ndr1_1 X52 &
% 12.00/12.92 bnd_c2_2 X52 bnd_a223) &
% 12.00/12.92 bnd_c3_2 X52 bnd_a223) &
% 12.00/12.92 ~ bnd_c5_2 X52 bnd_a223))) &
% 12.00/12.92 (bnd_c5_0 |
% 12.00/12.92 (ALL X54.
% 12.00/12.92 bnd_ndr1_0 -->
% 12.00/12.92 ((ALL X55.
% 12.00/12.92 bnd_ndr1_1 X54 -->
% 12.00/12.92 (bnd_c2_2 X54 X55 | ~ bnd_c3_2 X54 X55) | ~ bnd_c5_2 X54 X55) |
% 12.00/12.92 (ALL X56.
% 12.00/12.92 bnd_ndr1_1 X54 -->
% 12.00/12.92 (bnd_c3_2 X54 X56 | bnd_c5_2 X54 X56) | ~ bnd_c4_2 X54 X56)) |
% 12.00/12.92 ((bnd_ndr1_1 X54 & bnd_c1_2 X54 bnd_a224) &
% 12.00/12.92 bnd_c4_2 X54 bnd_a224) &
% 12.00/12.92 ~ bnd_c5_2 X54 bnd_a224))) &
% 12.00/12.92 ((bnd_c5_0 |
% 12.00/12.92 ((bnd_ndr1_0 & bnd_c3_1 bnd_a225) &
% 12.00/12.92 bnd_c4_1 bnd_a225) &
% 12.00/12.92 (ALL X57.
% 12.00/12.92 bnd_ndr1_1 bnd_a225 -->
% 12.00/12.92 bnd_c1_2 bnd_a225 X57 |
% 12.00/12.92 ~ bnd_c2_2 bnd_a225 X57)) |
% 12.00/12.92 (bnd_ndr1_0 &
% 12.00/12.92 (ALL X58.
% 12.00/12.92 bnd_ndr1_1 bnd_a226 -->
% 12.00/12.92 (bnd_c1_2 bnd_a226 X58 |
% 12.00/12.92 ~ bnd_c2_2 bnd_a226 X58) |
% 12.00/12.92 ~ bnd_c4_2 bnd_a226 X58)) &
% 12.00/12.92 (ALL X59.
% 12.00/12.92 bnd_ndr1_1 bnd_a226 -->
% 12.00/12.92 (~ bnd_c2_2 bnd_a226 X59 |
% 12.00/12.92 ~ bnd_c3_2 bnd_a226 X59) |
% 12.00/12.92 ~ bnd_c4_2 bnd_a226 X59))) &
% 12.00/12.92 (~ bnd_c1_0 | ~ bnd_c2_0)) &
% 12.00/12.92 ((~ bnd_c1_0 | ~ bnd_c2_0) | ~ bnd_c3_0)) &
% 12.00/12.92 ((~ bnd_c1_0 | ~ bnd_c3_0) | ~ bnd_c5_0)) &
% 12.00/12.92 ((~ bnd_c1_0 | ~ bnd_c3_0) |
% 12.00/12.92 (((((bnd_ndr1_0 & bnd_c3_1 bnd_a227) &
% 12.00/12.92 (ALL X60.
% 12.00/12.92 bnd_ndr1_1 bnd_a227 -->
% 12.00/12.92 (bnd_c2_2 bnd_a227 X60 |
% 12.00/12.92 ~ bnd_c3_2 bnd_a227 X60) |
% 12.00/12.92 ~ bnd_c4_2 bnd_a227 X60)) &
% 12.00/12.92 bnd_ndr1_1 bnd_a227) &
% 12.00/12.92 bnd_c4_2 bnd_a227 bnd_a228) &
% 12.00/12.92 ~ bnd_c2_2 bnd_a227 bnd_a228) &
% 12.00/12.92 ~ bnd_c5_2 bnd_a227 bnd_a228)) &
% 12.00/12.92 ((~ bnd_c1_0 | ~ bnd_c5_0) |
% 12.00/12.92 ((((bnd_ndr1_0 & ~ bnd_c3_1 bnd_a229) &
% 12.00/12.92 ~ bnd_c4_1 bnd_a229) &
% 12.00/12.92 bnd_ndr1_1 bnd_a229) &
% 12.00/12.92 bnd_c3_2 bnd_a229 bnd_a230) &
% 12.00/12.92 bnd_c4_2 bnd_a229 bnd_a230)) &
% 12.00/12.92 ((~ bnd_c1_0 |
% 12.00/12.92 (ALL X61.
% 12.00/12.92 bnd_ndr1_0 -->
% 12.00/12.92 (bnd_c4_1 X61 | ~ bnd_c1_1 X61) |
% 12.00/12.92 (ALL X62.
% 12.00/12.92 bnd_ndr1_1 X61 -->
% 12.00/12.92 bnd_c1_2 X61 X62 | ~ bnd_c4_2 X61 X62))) |
% 12.00/12.92 ((((bnd_ndr1_0 & ~ bnd_c2_1 bnd_a231) &
% 12.00/12.92 bnd_ndr1_1 bnd_a231) &
% 12.00/12.92 bnd_c1_2 bnd_a231 bnd_a232) &
% 12.00/12.92 bnd_c2_2 bnd_a231 bnd_a232) &
% 12.00/12.92 bnd_c5_2 bnd_a231 bnd_a232)) &
% 12.00/12.92 ((~ bnd_c1_0 |
% 12.00/12.92 (ALL X63.
% 12.00/12.92 bnd_ndr1_0 -->
% 12.00/12.92 (bnd_c4_1 X63 |
% 12.00/12.92 (ALL X64.
% 12.00/12.92 bnd_ndr1_1 X63 -->
% 12.00/12.92 (bnd_c3_2 X63 X64 | ~ bnd_c4_2 X63 X64) |
% 12.00/12.92 ~ bnd_c5_2 X63 X64)) |
% 12.00/12.92 (bnd_ndr1_1 X63 & bnd_c3_2 X63 bnd_a233) &
% 12.00/12.92 ~ bnd_c5_2 X63 bnd_a233)) |
% 12.00/12.92 (ALL X65.
% 12.00/12.92 bnd_ndr1_0 -->
% 12.00/12.92 (bnd_c5_1 X65 | ~ bnd_c4_1 X65) |
% 12.00/12.92 (ALL X66.
% 12.00/12.92 bnd_ndr1_1 X65 -->
% 12.00/12.92 bnd_c2_2 X65 X66 | ~ bnd_c3_2 X65 X66)))) &
% 12.00/12.92 ((~ bnd_c1_0 |
% 12.00/12.92 (ALL X67.
% 12.00/12.92 bnd_ndr1_0 -->
% 12.00/12.92 (~ bnd_c5_1 X67 |
% 12.00/12.92 (ALL X68.
% 12.00/12.92 bnd_ndr1_1 X67 -->
% 12.00/12.92 bnd_c1_2 X67 X68 | ~ bnd_c3_2 X67 X68)) |
% 12.00/12.92 (bnd_ndr1_1 X67 & bnd_c5_2 X67 bnd_a234) &
% 12.00/12.92 ~ bnd_c4_2 X67 bnd_a234)) |
% 12.00/12.92 (((((bnd_ndr1_0 & ~ bnd_c1_1 bnd_a235) &
% 12.00/12.92 (ALL X69.
% 12.00/12.92 bnd_ndr1_1 bnd_a235 -->
% 12.00/12.92 (bnd_c3_2 bnd_a235 X69 |
% 12.00/12.92 bnd_c4_2 bnd_a235 X69) |
% 12.00/12.92 ~ bnd_c5_2 bnd_a235 X69)) &
% 12.00/12.92 bnd_ndr1_1 bnd_a235) &
% 12.00/12.92 ~ bnd_c2_2 bnd_a235 bnd_a236) &
% 12.00/12.92 ~ bnd_c4_2 bnd_a235 bnd_a236) &
% 12.00/12.92 ~ bnd_c5_2 bnd_a235 bnd_a236)) &
% 12.00/12.92 (~ bnd_c2_0 |
% 12.00/12.92 ((bnd_ndr1_0 & bnd_c3_1 bnd_a237) &
% 12.00/12.92 ~ bnd_c4_1 bnd_a237) &
% 12.00/12.92 (ALL X70.
% 12.00/12.92 bnd_ndr1_1 bnd_a237 -->
% 12.00/12.92 bnd_c5_2 bnd_a237 X70 | ~ bnd_c3_2 bnd_a237 X70))) &
% 12.00/12.92 (~ bnd_c3_0 | ~ bnd_c5_0)) &
% 12.00/12.92 (~ bnd_c3_0 |
% 12.00/12.92 (ALL X71.
% 12.00/12.92 bnd_ndr1_0 -->
% 12.00/12.92 bnd_c1_1 X71 |
% 12.00/12.92 (ALL X72.
% 12.00/12.92 bnd_ndr1_1 X71 -->
% 12.00/12.92 ~ bnd_c1_2 X71 X72 | ~ bnd_c3_2 X71 X72)))) &
% 12.00/12.92 ((~ bnd_c3_0 |
% 12.00/12.92 (ALL X73.
% 12.00/12.92 bnd_ndr1_0 -->
% 12.00/12.92 (bnd_c3_1 X73 | bnd_c5_1 X73) |
% 12.00/12.92 (bnd_ndr1_1 X73 & bnd_c4_2 X73 bnd_a238) &
% 12.00/12.92 ~ bnd_c1_2 X73 bnd_a238)) |
% 12.00/12.92 (ALL X74.
% 12.00/12.92 bnd_ndr1_0 -->
% 12.00/12.92 (bnd_c5_1 X74 |
% 12.00/12.92 (ALL X75.
% 12.00/12.92 bnd_ndr1_1 X74 -->
% 12.00/12.92 (bnd_c4_2 X74 X75 | ~ bnd_c1_2 X74 X75) |
% 12.00/12.92 ~ bnd_c3_2 X74 X75)) |
% 12.00/12.92 (ALL X76.
% 12.00/12.92 bnd_ndr1_1 X74 -->
% 12.00/12.92 (~ bnd_c1_2 X74 X76 | ~ bnd_c3_2 X74 X76) |
% 12.00/12.92 ~ bnd_c4_2 X74 X76)))) &
% 12.00/12.92 ((~ bnd_c3_0 |
% 12.00/12.92 (ALL X77.
% 12.00/12.92 bnd_ndr1_0 -->
% 12.00/12.92 (bnd_c4_1 X77 | bnd_c5_1 X77) | ~ bnd_c1_1 X77)) |
% 12.00/12.92 (ALL X78.
% 12.00/12.92 bnd_ndr1_0 -->
% 12.00/12.92 bnd_c5_1 X78 |
% 12.00/12.92 (ALL X79.
% 12.00/12.92 bnd_ndr1_1 X78 -->
% 12.00/12.92 (bnd_c2_2 X78 X79 | bnd_c5_2 X78 X79) |
% 12.00/12.92 ~ bnd_c1_2 X78 X79)))) &
% 12.00/12.92 ((~ bnd_c3_0 |
% 12.00/12.92 (ALL X80. bnd_ndr1_0 --> bnd_c4_1 X80 | ~ bnd_c5_1 X80)) |
% 12.00/12.92 (ALL X81.
% 12.00/12.92 bnd_ndr1_0 -->
% 12.00/12.92 (~ bnd_c3_1 X81 | ~ bnd_c5_1 X81) |
% 12.00/12.92 ((bnd_ndr1_1 X81 & bnd_c1_2 X81 bnd_a239) &
% 12.00/12.92 bnd_c3_2 X81 bnd_a239) &
% 12.00/12.92 bnd_c4_2 X81 bnd_a239))) &
% 12.00/12.92 ((~ bnd_c3_0 |
% 12.00/12.92 (ALL X82.
% 12.00/12.92 bnd_ndr1_0 -->
% 12.00/12.92 (bnd_c5_1 X82 |
% 12.00/12.92 (ALL X83.
% 12.00/12.92 bnd_ndr1_1 X82 -->
% 12.00/12.92 (bnd_c4_2 X82 X83 | ~ bnd_c1_2 X82 X83) |
% 12.00/12.92 ~ bnd_c2_2 X82 X83)) |
% 12.00/12.92 (ALL X84.
% 12.00/12.92 bnd_ndr1_1 X82 -->
% 12.00/12.92 ~ bnd_c1_2 X82 X84 | ~ bnd_c5_2 X82 X84))) |
% 12.00/12.92 (bnd_ndr1_0 & bnd_c2_1 bnd_a240) & ~ bnd_c3_1 bnd_a240)) &
% 12.00/12.92 (((ALL X85.
% 12.00/12.92 bnd_ndr1_0 -->
% 12.00/12.92 (bnd_c1_1 X85 | ~ bnd_c2_1 X85) |
% 12.00/12.92 (ALL X86.
% 12.00/12.92 bnd_ndr1_1 X85 -->
% 12.00/12.92 (bnd_c1_2 X85 X86 | bnd_c3_2 X85 X86) |
% 12.00/12.92 ~ bnd_c4_2 X85 X86)) |
% 12.00/12.92 (ALL X87.
% 12.00/12.92 bnd_ndr1_0 -->
% 12.00/12.92 (bnd_c1_1 X87 | ~ bnd_c2_1 X87) |
% 12.00/12.92 (ALL X88.
% 12.00/12.92 bnd_ndr1_1 X87 -->
% 12.00/12.92 bnd_c1_2 X87 X88 | bnd_c4_2 X87 X88))) |
% 12.00/12.92 (((((bnd_ndr1_0 & bnd_c4_1 bnd_a241) &
% 12.00/12.92 (ALL X89.
% 12.00/12.92 bnd_ndr1_1 bnd_a241 --> ~ bnd_c4_2 bnd_a241 X89)) &
% 12.00/12.92 bnd_ndr1_1 bnd_a241) &
% 12.00/12.92 bnd_c3_2 bnd_a241 bnd_a242) &
% 12.00/12.92 ~ bnd_c2_2 bnd_a241 bnd_a242) &
% 12.00/12.92 ~ bnd_c4_2 bnd_a241 bnd_a242)) &
% 12.00/12.92 (((ALL X90.
% 12.00/12.92 bnd_ndr1_0 -->
% 12.00/12.92 (bnd_c2_1 X90 | bnd_c3_1 X90) |
% 12.00/12.92 (ALL X91.
% 12.00/12.92 bnd_ndr1_1 X90 -->
% 12.00/12.92 (bnd_c3_2 X90 X91 | ~ bnd_c2_2 X90 X91) |
% 12.00/12.92 ~ bnd_c4_2 X90 X91)) |
% 12.00/12.92 (ALL X92.
% 12.00/12.92 bnd_ndr1_0 -->
% 12.00/12.92 ~ bnd_c4_1 X92 |
% 12.00/12.92 (ALL X93.
% 12.00/12.92 bnd_ndr1_1 X92 -->
% 12.00/12.92 (~ bnd_c1_2 X92 X93 | ~ bnd_c2_2 X92 X93) |
% 12.00/12.92 ~ bnd_c5_2 X92 X93))) |
% 12.00/12.92 ((((bnd_ndr1_0 & ~ bnd_c2_1 bnd_a243) &
% 12.00/12.92 (ALL X94.
% 12.00/12.92 bnd_ndr1_1 bnd_a243 -->
% 12.00/12.92 (bnd_c1_2 bnd_a243 X94 | bnd_c4_2 bnd_a243 X94) |
% 12.00/12.92 ~ bnd_c3_2 bnd_a243 X94)) &
% 12.00/12.92 bnd_ndr1_1 bnd_a243) &
% 12.00/12.92 bnd_c2_2 bnd_a243 bnd_a244) &
% 12.00/12.92 ~ bnd_c3_2 bnd_a243 bnd_a244)) &
% 12.00/12.92 (((ALL X95.
% 12.00/12.92 bnd_ndr1_0 -->
% 12.00/12.92 (bnd_c2_1 X95 |
% 12.00/12.92 (ALL X96.
% 12.00/12.92 bnd_ndr1_1 X95 -->
% 12.00/12.92 (bnd_c1_2 X95 X96 | bnd_c5_2 X95 X96) |
% 12.00/12.92 ~ bnd_c4_2 X95 X96)) |
% 12.00/12.92 (ALL X97.
% 12.00/12.92 bnd_ndr1_1 X95 -->
% 12.00/12.92 bnd_c2_2 X95 X97 | ~ bnd_c5_2 X95 X97)) |
% 12.00/12.92 (ALL X98.
% 12.00/12.92 bnd_ndr1_0 -->
% 12.00/12.92 bnd_c3_1 X98 |
% 12.00/12.92 (ALL X99.
% 12.00/12.92 bnd_ndr1_1 X98 -->
% 12.00/12.92 bnd_c1_2 X98 X99 | bnd_c2_2 X98 X99))) |
% 12.00/12.92 (ALL X100.
% 12.00/12.92 bnd_ndr1_0 -->
% 12.00/12.92 (bnd_c4_1 X100 | ~ bnd_c5_1 X100) |
% 12.00/12.92 (ALL X101.
% 12.00/12.92 bnd_ndr1_1 X100 -->
% 12.00/12.92 (bnd_c2_2 X100 X101 | bnd_c4_2 X100 X101) |
% 12.00/12.92 ~ bnd_c5_2 X100 X101)))) &
% 12.00/12.92 (((ALL X102.
% 12.00/12.92 bnd_ndr1_0 -->
% 12.00/12.92 (bnd_c3_1 X102 |
% 12.00/12.92 ((bnd_ndr1_1 X102 & bnd_c1_2 X102 bnd_a245) &
% 12.00/12.92 bnd_c4_2 X102 bnd_a245) &
% 12.00/12.92 bnd_c5_2 X102 bnd_a245) |
% 12.00/12.92 ((bnd_ndr1_1 X102 & ~ bnd_c1_2 X102 bnd_a246) &
% 12.00/12.92 ~ bnd_c4_2 X102 bnd_a246) &
% 12.00/12.92 ~ bnd_c5_2 X102 bnd_a246) |
% 12.00/12.92 (ALL X103.
% 12.00/12.92 bnd_ndr1_0 -->
% 12.00/12.92 (bnd_c4_1 X103 | ~ bnd_c3_1 X103) |
% 12.00/12.92 (bnd_ndr1_1 X103 & bnd_c3_2 X103 bnd_a247) &
% 12.00/12.92 ~ bnd_c4_2 X103 bnd_a247)) |
% 12.00/12.92 (bnd_ndr1_0 & bnd_c4_1 bnd_a248) & ~ bnd_c5_1 bnd_a248)) &
% 12.00/12.92 (((ALL X104. bnd_ndr1_0 --> bnd_c4_1 X104 | ~ bnd_c1_1 X104) |
% 12.00/12.92 (ALL X105.
% 12.00/12.92 bnd_ndr1_0 -->
% 12.00/12.92 (~ bnd_c3_1 X105 | ~ bnd_c5_1 X105) |
% 12.00/12.92 (ALL X106.
% 12.00/12.92 bnd_ndr1_1 X105 -->
% 12.00/12.92 (bnd_c2_2 X105 X106 | bnd_c3_2 X105 X106) |
% 12.00/12.92 ~ bnd_c5_2 X105 X106))) |
% 12.00/12.92 ((bnd_ndr1_0 &
% 12.00/12.92 (ALL X107.
% 12.00/12.92 bnd_ndr1_1 bnd_a249 -->
% 12.00/12.92 (bnd_c1_2 bnd_a249 X107 | bnd_c2_2 bnd_a249 X107) |
% 12.00/12.92 bnd_c4_2 bnd_a249 X107)) &
% 12.00/12.92 (ALL X108.
% 12.00/12.92 bnd_ndr1_1 bnd_a249 -->
% 12.00/12.92 bnd_c1_2 bnd_a249 X108 | ~ bnd_c5_2 bnd_a249 X108)) &
% 12.00/12.92 (ALL X109.
% 12.00/12.92 bnd_ndr1_1 bnd_a249 -->
% 12.00/12.92 (bnd_c4_2 bnd_a249 X109 | ~ bnd_c1_2 bnd_a249 X109) |
% 12.00/12.92 ~ bnd_c2_2 bnd_a249 X109))) &
% 12.00/12.92 ((ALL X110.
% 12.00/12.92 bnd_ndr1_0 -->
% 12.00/12.92 (bnd_c4_1 X110 | ~ bnd_c5_1 X110) |
% 12.00/12.92 (bnd_ndr1_1 X110 & bnd_c1_2 X110 bnd_a250) &
% 12.00/12.92 ~ bnd_c4_2 X110 bnd_a250) |
% 12.00/12.92 (ALL X111.
% 12.00/12.92 bnd_ndr1_0 -->
% 12.00/12.92 (~ bnd_c1_1 X111 | ~ bnd_c2_1 X111) |
% 12.00/12.92 (ALL X112.
% 12.00/12.92 bnd_ndr1_1 X111 -->
% 12.00/12.92 bnd_c5_2 X111 X112 | ~ bnd_c2_2 X111 X112)))) &
% 12.00/12.92 (((ALL X113.
% 12.00/12.92 bnd_ndr1_0 -->
% 12.00/12.92 (bnd_c5_1 X113 |
% 12.00/12.92 (bnd_ndr1_1 X113 & bnd_c1_2 X113 bnd_a251) &
% 12.00/12.92 ~ bnd_c5_2 X113 bnd_a251) |
% 12.00/12.92 ((bnd_ndr1_1 X113 & bnd_c2_2 X113 bnd_a252) &
% 12.00/12.92 bnd_c5_2 X113 bnd_a252) &
% 12.00/12.92 ~ bnd_c1_2 X113 bnd_a252) |
% 12.00/12.92 (((((bnd_ndr1_0 & bnd_c1_1 bnd_a253) & ~ bnd_c4_1 bnd_a253) &
% 12.00/12.92 bnd_ndr1_1 bnd_a253) &
% 12.00/12.92 bnd_c2_2 bnd_a253 bnd_a254) &
% 12.00/12.92 bnd_c3_2 bnd_a253 bnd_a254) &
% 12.00/12.92 bnd_c5_2 bnd_a253 bnd_a254) |
% 12.00/12.92 bnd_ndr1_0 & ~ bnd_c3_1 bnd_a255)) &
% 12.00/12.92 (((ALL X114.
% 12.00/12.92 bnd_ndr1_0 -->
% 12.00/12.92 ~ bnd_c2_1 X114 |
% 12.00/12.92 (bnd_ndr1_1 X114 & bnd_c1_2 X114 bnd_a256) &
% 12.00/12.92 bnd_c3_2 X114 bnd_a256) |
% 12.00/12.92 ((((bnd_ndr1_0 & bnd_c4_1 bnd_a257) & ~ bnd_c1_1 bnd_a257) &
% 12.00/12.92 bnd_ndr1_1 bnd_a257) &
% 12.00/12.92 bnd_c5_2 bnd_a257 bnd_a258) &
% 12.00/12.92 ~ bnd_c4_2 bnd_a257 bnd_a258) |
% 12.00/12.92 (bnd_ndr1_0 & ~ bnd_c1_1 bnd_a259) &
% 12.00/12.92 (ALL X115.
% 12.00/12.92 bnd_ndr1_1 bnd_a259 -->
% 12.00/12.92 ~ bnd_c1_2 bnd_a259 X115 | ~ bnd_c5_2 bnd_a259 X115))) &
% 12.00/12.92 (((((((bnd_ndr1_0 & bnd_c1_1 bnd_a260) & ~ bnd_c4_1 bnd_a260) &
% 12.00/12.92 bnd_ndr1_1 bnd_a260) &
% 12.00/12.92 bnd_c1_2 bnd_a260 bnd_a261) &
% 12.00/12.92 bnd_c2_2 bnd_a260 bnd_a261) &
% 12.00/12.92 bnd_c4_2 bnd_a260 bnd_a261 |
% 12.00/12.92 (bnd_ndr1_0 & bnd_c5_1 bnd_a262) &
% 12.00/12.92 (ALL X116.
% 12.00/12.92 bnd_ndr1_1 bnd_a262 -->
% 12.00/12.92 (bnd_c4_2 bnd_a262 X116 | ~ bnd_c3_2 bnd_a262 X116) |
% 12.00/12.92 ~ bnd_c5_2 bnd_a262 X116)) |
% 12.00/12.92 ((((bnd_ndr1_0 & ~ bnd_c1_1 bnd_a263) & bnd_ndr1_1 bnd_a263) &
% 12.00/12.92 bnd_c1_2 bnd_a263 bnd_a264) &
% 12.00/12.92 bnd_c3_2 bnd_a263 bnd_a264) &
% 12.00/12.92 ~ bnd_c4_2 bnd_a263 bnd_a264))
% 12.00/12.92 Adding axioms...
% 12.00/12.94 Typedef.type_definition_def
% 28.73/29.64 ...done.
% 28.73/29.66 Ground types: ?'b, TPTP_Interpret.ind
% 28.73/29.66 Translating term (sizes: 1, 1) ...
% 42.85/43.79 Invoking SAT solver...
% 42.85/43.79 No model exists.
% 42.85/43.79 Translating term (sizes: 2, 1) ...
% 57.57/58.49 Invoking SAT solver...
% 57.57/58.49 No model exists.
% 57.57/58.49 Translating term (sizes: 1, 2) ...
% 86.06/86.84 Invoking SAT solver...
% 87.16/87.93 Model found:
% 87.16/87.93 Size of types: ?'b: 1, TPTP_Interpret.ind: 2
% 87.16/87.93 bnd_a264: ??.TPTP_Interpret.ind0
% 87.16/87.93 bnd_a263: ??.TPTP_Interpret.ind0
% 87.16/87.93 bnd_a262: ??.TPTP_Interpret.ind0
% 87.16/87.93 bnd_a261: ??.TPTP_Interpret.ind0
% 87.16/87.93 bnd_a260: ??.TPTP_Interpret.ind0
% 87.16/87.93 bnd_a259: ??.TPTP_Interpret.ind0
% 87.16/87.93 bnd_a258: ??.TPTP_Interpret.ind0
% 87.16/87.93 bnd_a257: ??.TPTP_Interpret.ind0
% 87.16/87.93 bnd_a256: ??.TPTP_Interpret.ind0
% 87.16/87.93 bnd_a255: ??.TPTP_Interpret.ind0
% 87.16/87.93 bnd_a254: ??.TPTP_Interpret.ind0
% 87.16/87.93 bnd_a253: ??.TPTP_Interpret.ind0
% 87.16/87.93 bnd_a252: ??.TPTP_Interpret.ind0
% 87.16/87.93 bnd_a251: ??.TPTP_Interpret.ind0
% 87.16/87.93 bnd_a250: ??.TPTP_Interpret.ind0
% 87.16/87.93 bnd_a249: ??.TPTP_Interpret.ind0
% 87.16/87.93 bnd_a248: ??.TPTP_Interpret.ind0
% 87.16/87.93 bnd_a247: ??.TPTP_Interpret.ind0
% 87.16/87.93 bnd_a246: ??.TPTP_Interpret.ind0
% 87.16/87.93 bnd_a245: ??.TPTP_Interpret.ind0
% 87.16/87.93 bnd_a244: ??.TPTP_Interpret.ind0
% 87.16/87.93 bnd_a243: ??.TPTP_Interpret.ind0
% 87.16/87.93 bnd_a242: ??.TPTP_Interpret.ind0
% 87.16/87.93 bnd_a241: ??.TPTP_Interpret.ind0
% 87.16/87.93 bnd_a240: ??.TPTP_Interpret.ind0
% 87.16/87.93 bnd_a239: ??.TPTP_Interpret.ind0
% 87.16/87.93 bnd_a238: ??.TPTP_Interpret.ind0
% 87.16/87.93 bnd_a237: ??.TPTP_Interpret.ind0
% 87.16/87.93 bnd_a236: ??.TPTP_Interpret.ind0
% 87.16/87.93 bnd_a235: ??.TPTP_Interpret.ind0
% 87.16/87.93 bnd_a234: ??.TPTP_Interpret.ind0
% 87.16/87.93 bnd_a233: ??.TPTP_Interpret.ind0
% 87.16/87.93 bnd_a232: ??.TPTP_Interpret.ind0
% 87.16/87.93 bnd_a231: ??.TPTP_Interpret.ind0
% 87.16/87.93 bnd_a230: ??.TPTP_Interpret.ind0
% 87.16/87.93 bnd_a229: ??.TPTP_Interpret.ind0
% 87.16/87.93 bnd_a228: ??.TPTP_Interpret.ind0
% 87.16/87.93 bnd_a227: ??.TPTP_Interpret.ind0
% 87.16/87.93 bnd_a226: ??.TPTP_Interpret.ind0
% 87.16/87.93 bnd_a225: ??.TPTP_Interpret.ind0
% 87.16/87.93 bnd_a224: ??.TPTP_Interpret.ind0
% 87.16/87.93 bnd_a223: ??.TPTP_Interpret.ind0
% 87.16/87.93 bnd_a222: ??.TPTP_Interpret.ind0
% 87.16/87.93 bnd_a221: ??.TPTP_Interpret.ind0
% 87.16/87.93 bnd_a220: ??.TPTP_Interpret.ind0
% 87.16/87.93 bnd_a219: ??.TPTP_Interpret.ind0
% 87.16/87.93 bnd_a218: ??.TPTP_Interpret.ind0
% 87.16/87.93 bnd_a217: ??.TPTP_Interpret.ind0
% 87.16/87.93 bnd_a216: ??.TPTP_Interpret.ind0
% 87.16/87.93 bnd_a215: ??.TPTP_Interpret.ind0
% 87.16/87.93 bnd_a214: ??.TPTP_Interpret.ind0
% 87.16/87.93 bnd_a213: ??.TPTP_Interpret.ind0
% 87.16/87.93 bnd_a212: ??.TPTP_Interpret.ind0
% 87.16/87.93 bnd_a211: ??.TPTP_Interpret.ind0
% 87.16/87.93 bnd_a210: ??.TPTP_Interpret.ind1
% 87.16/87.93 bnd_a209: ??.TPTP_Interpret.ind1
% 87.16/87.93 bnd_a208: ??.TPTP_Interpret.ind0
% 87.16/87.93 bnd_a207: ??.TPTP_Interpret.ind0
% 87.16/87.93 bnd_a206: ??.TPTP_Interpret.ind0
% 87.16/87.93 bnd_a205: ??.TPTP_Interpret.ind0
% 87.16/87.93 bnd_a204: ??.TPTP_Interpret.ind0
% 87.16/87.93 bnd_a203: ??.TPTP_Interpret.ind0
% 87.16/87.93 bnd_a202: ??.TPTP_Interpret.ind1
% 87.16/87.93 bnd_a201: ??.TPTP_Interpret.ind0
% 87.16/87.93 bnd_a200: ??.TPTP_Interpret.ind0
% 87.16/87.93 bnd_a199: ??.TPTP_Interpret.ind1
% 87.16/87.93 bnd_a198: ??.TPTP_Interpret.ind0
% 87.16/87.93 bnd_a197: ??.TPTP_Interpret.ind0
% 87.16/87.93 bnd_a196: ??.TPTP_Interpret.ind0
% 87.16/87.93 bnd_a195: ??.TPTP_Interpret.ind0
% 87.16/87.93 bnd_a194: ??.TPTP_Interpret.ind0
% 87.16/87.93 bnd_a193: ??.TPTP_Interpret.ind0
% 87.16/87.93 bnd_a192: ??.TPTP_Interpret.ind1
% 87.16/87.93 bnd_a191: ??.TPTP_Interpret.ind0
% 87.16/87.93 bnd_a190: ??.TPTP_Interpret.ind0
% 87.16/87.93 bnd_a189: ??.TPTP_Interpret.ind0
% 87.16/87.93 bnd_a188: ??.TPTP_Interpret.ind0
% 87.16/87.93 bnd_a187: ??.TPTP_Interpret.ind0
% 87.16/87.93 bnd_a186: ??.TPTP_Interpret.ind0
% 87.16/87.93 bnd_a185: ??.TPTP_Interpret.ind0
% 87.16/87.93 bnd_a184: ??.TPTP_Interpret.ind0
% 87.16/87.93 bnd_a183: ??.TPTP_Interpret.ind0
% 87.16/87.93 bnd_c4_1: {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, False)}
% 87.16/87.93 bnd_a182: ??.TPTP_Interpret.ind0
% 87.16/87.93 bnd_a181: ??.TPTP_Interpret.ind0
% 87.16/87.93 bnd_a180: ??.TPTP_Interpret.ind0
% 87.16/87.93 bnd_a179: ??.TPTP_Interpret.ind0
% 87.16/87.93 bnd_a178: ??.TPTP_Interpret.ind0
% 87.16/87.93 bnd_c5_1: {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, True)}
% 87.16/87.93 bnd_c1_1: {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, False)}
% 87.16/87.93 bnd_a177: ??.TPTP_Interpret.ind0
% 87.16/87.93 bnd_c3_1: {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, True)}
% 87.16/87.93 bnd_c2_2: {(??.TPTP_Interpret.ind0,
% 87.16/87.93 {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, False)}),
% 87.16/87.93 (??.TPTP_Interpret.ind1,
% 87.16/87.93 {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, True)})}
% 87.16/87.93 bnd_a176: ??.TPTP_Interpret.ind0
% 87.16/87.93 bnd_a175: ??.TPTP_Interpret.ind0
% 87.16/87.93 bnd_c2_0: False
% 87.16/87.93 bnd_c5_0: False
% 87.16/87.93 bnd_c1_2: {(??.TPTP_Interpret.ind0,
% 87.16/87.93 {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, True)}),
% 87.16/87.93 (??.TPTP_Interpret.ind1,
% 87.16/87.93 {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, True)})}
% 87.16/87.93 bnd_c4_2: {(??.TPTP_Interpret.ind0,
% 87.16/87.93 {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, False)}),
% 87.16/87.93 (??.TPTP_Interpret.ind1,
% 87.16/87.93 {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, False)})}
% 87.16/87.93 bnd_c3_2: {(??.TPTP_Interpret.ind0,
% 87.16/87.93 {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, True)}),
% 87.16/87.93 (??.TPTP_Interpret.ind1,
% 87.16/87.93 {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, False)})}
% 87.16/87.93 bnd_c5_2: {(??.TPTP_Interpret.ind0,
% 87.16/87.93 {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, False)}),
% 87.16/87.93 (??.TPTP_Interpret.ind1,
% 87.16/87.93 {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, False)})}
% 87.16/87.93 bnd_ndr1_1: {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, True)}
% 87.16/87.93 bnd_c2_1: {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, True)}
% 87.16/87.93 bnd_ndr1_0: True
% 87.16/87.93 bnd_c3_0: False
% 87.16/87.93 bnd_c1_0: True
% 87.16/87.93 bnd_c4_0: False
% 87.16/87.93
% 87.16/87.93 % SZS status CounterSatisfiable
%------------------------------------------------------------------------------