TSTP Solution File: SYN423+1 by Refute---2015
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%------------------------------------------------------------------------------
% File : Refute---2015
% Problem : SYN423+1 : TPTP v6.4.0. Released v2.1.0.
% Transfm : none
% Format : tptp:raw
% Command : isabelle tptp_refute %d %s
% Computer : n092.star.cs.uiowa.edu
% Model : x86_64 x86_64
% CPU : Intel(R) Xeon(R) CPU E5-2609 0 2.40GHz
% Memory : 32218.75MB
% OS : Linux 3.10.0-327.10.1.el7.x86_64
% CPULimit : 300s
% DateTime : Thu Apr 14 06:41:43 EDT 2016
% Result : CounterSatisfiable 157.58s
% Output : Assurance 0s
% Verified :
% SZS Type : None (Parsing solution fails)
% Syntax : Number of formulae : 0
% Comments :
%------------------------------------------------------------------------------
%----No solution output by system
%------------------------------------------------------------------------------
%----ORIGINAL SYSTEM OUTPUT
% 0.02/0.03 % Problem : SYN423+1 : TPTP v6.4.0. Released v2.1.0.
% 0.02/0.04 % Command : isabelle tptp_refute %d %s
% 0.03/0.23 % Computer : n092.star.cs.uiowa.edu
% 0.03/0.23 % Model : x86_64 x86_64
% 0.03/0.23 % CPU : Intel(R) Xeon(R) CPU E5-2609 0 @ 2.40GHz
% 0.03/0.23 % Memory : 32218.75MB
% 0.03/0.23 % OS : Linux 3.10.0-327.10.1.el7.x86_64
% 0.03/0.23 % CPULimit : 300
% 0.03/0.23 % DateTime : Fri Apr 8 23:49:24 CDT 2016
% 0.03/0.23 % CPUTime:
% 6.28/5.83 > val it = (): unit
% 7.18/6.75 Trying to find a model that refutes: ~ (((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((bnd_c6_0 &
% 7.18/6.75 ~ bnd_c8_0) &
% 7.18/6.75 ((bnd_c1_0 | bnd_c5_0) |
% 7.18/6.75 (ALL U.
% 7.18/6.75 bnd_ndr1_0 -->
% 7.18/6.75 (~ bnd_c2_1 U |
% 7.18/6.75 ((bnd_ndr1_1 U & bnd_c1_2 U bnd_a431) & bnd_c6_2 U bnd_a431) &
% 7.18/6.75 ~ bnd_c10_2 U bnd_a431) |
% 7.18/6.75 ((bnd_ndr1_1 U & bnd_c10_2 U bnd_a432) & bnd_c4_2 U bnd_a432) &
% 7.18/6.75 bnd_c5_2 U bnd_a432))) &
% 7.18/6.75 ((bnd_c1_0 | ~ bnd_c2_0) |
% 7.18/6.75 (ALL V.
% 7.18/6.75 bnd_ndr1_0 -->
% 7.18/6.75 (~ bnd_c6_1 V | ~ bnd_c7_1 V) |
% 7.18/6.75 ((bnd_ndr1_1 V & bnd_c5_2 V bnd_a433) & ~ bnd_c4_2 V bnd_a433) &
% 7.18/6.75 ~ bnd_c6_2 V bnd_a433))) &
% 7.18/6.75 ((bnd_c1_0 | ~ bnd_c3_0) |
% 7.18/6.75 (ALL W.
% 7.18/6.75 bnd_ndr1_0 -->
% 7.18/6.75 bnd_c1_1 W |
% 7.18/6.75 (ALL X.
% 7.18/6.75 bnd_ndr1_1 W -->
% 7.18/6.75 (bnd_c3_2 W X | bnd_c4_2 W X) | ~ bnd_c5_2 W X)))) &
% 7.18/6.75 (bnd_c1_0 | ~ bnd_c9_0)) &
% 7.18/6.75 ((bnd_c1_0 |
% 7.18/6.75 (((((bnd_ndr1_0 & bnd_c6_1 bnd_a434) &
% 7.18/6.75 (ALL Y.
% 7.18/6.75 bnd_ndr1_1 bnd_a434 -->
% 7.18/6.75 (bnd_c10_2 bnd_a434 Y | ~ bnd_c5_2 bnd_a434 Y) |
% 7.18/6.75 ~ bnd_c9_2 bnd_a434 Y)) &
% 7.18/6.75 bnd_ndr1_1 bnd_a434) &
% 7.18/6.75 ~ bnd_c1_2 bnd_a434 bnd_a435) &
% 7.18/6.75 ~ bnd_c5_2 bnd_a434 bnd_a435) &
% 7.18/6.75 ~ bnd_c8_2 bnd_a434 bnd_a435) |
% 7.18/6.75 ((bnd_ndr1_0 & bnd_c7_1 bnd_a436) &
% 7.18/6.75 ~ bnd_c3_1 bnd_a436) &
% 7.18/6.75 ~ bnd_c9_1 bnd_a436)) &
% 7.18/6.75 ((bnd_c10_0 | bnd_c3_0) |
% 7.18/6.75 (((((bnd_ndr1_0 & ~ bnd_c1_1 bnd_a437) &
% 7.18/6.75 (ALL Z.
% 7.18/6.75 bnd_ndr1_1 bnd_a437 -->
% 7.18/6.75 (bnd_c10_2 bnd_a437 Z | bnd_c5_2 bnd_a437 Z) |
% 7.18/6.75 ~ bnd_c8_2 bnd_a437 Z)) &
% 7.18/6.75 bnd_ndr1_1 bnd_a437) &
% 7.18/6.75 bnd_c9_2 bnd_a437 bnd_a438) &
% 7.18/6.75 ~ bnd_c4_2 bnd_a437 bnd_a438) &
% 7.18/6.75 ~ bnd_c8_2 bnd_a437 bnd_a438)) &
% 7.18/6.75 ((bnd_c10_0 | bnd_c4_0) |
% 7.18/6.75 (ALL X1.
% 7.18/6.75 bnd_ndr1_0 -->
% 7.18/6.75 (bnd_c9_1 X1 | ~ bnd_c2_1 X1) |
% 7.18/6.75 ((bnd_ndr1_1 X1 & ~ bnd_c4_2 X1 bnd_a439) & ~ bnd_c5_2 X1 bnd_a439) &
% 7.18/6.75 ~ bnd_c6_2 X1 bnd_a439))) &
% 7.18/6.75 ((bnd_c10_0 | bnd_c5_0) | ~ bnd_c9_0)) &
% 7.18/6.75 (bnd_c10_0 | bnd_c7_0)) &
% 7.18/6.75 ((bnd_c10_0 | bnd_c7_0) |
% 7.18/6.75 (((((bnd_ndr1_0 & ~ bnd_c3_1 bnd_a440) &
% 7.18/6.75 (ALL X2.
% 7.18/6.75 bnd_ndr1_1 bnd_a440 -->
% 7.18/6.75 (~ bnd_c2_2 bnd_a440 X2 | ~ bnd_c4_2 bnd_a440 X2) |
% 7.18/6.75 ~ bnd_c9_2 bnd_a440 X2)) &
% 7.18/6.75 bnd_ndr1_1 bnd_a440) &
% 7.18/6.75 bnd_c10_2 bnd_a440 bnd_a441) &
% 7.18/6.75 ~ bnd_c4_2 bnd_a440 bnd_a441) &
% 7.18/6.75 ~ bnd_c5_2 bnd_a440 bnd_a441)) &
% 7.18/6.75 ((bnd_c10_0 | ~ bnd_c2_0) |
% 7.18/6.75 (ALL X3.
% 7.18/6.75 bnd_ndr1_0 -->
% 7.18/6.75 ~ bnd_c5_1 X3 |
% 7.18/6.75 ((bnd_ndr1_1 X3 &
% 7.18/6.75 bnd_c10_2 X3 bnd_a442) &
% 7.18/6.75 bnd_c5_2 X3 bnd_a442) &
% 7.18/6.75 ~ bnd_c7_2 X3 bnd_a442))) &
% 7.18/6.75 ((bnd_c10_0 | ~ bnd_c7_0) |
% 7.18/6.75 (((((((bnd_ndr1_0 & bnd_c4_1 bnd_a443) &
% 7.18/6.75 bnd_ndr1_1 bnd_a443) &
% 7.18/6.75 bnd_c1_2 bnd_a443 bnd_a444) &
% 7.18/6.75 ~ bnd_c4_2 bnd_a443 bnd_a444) &
% 7.18/6.75 bnd_ndr1_1 bnd_a443) &
% 7.18/6.75 bnd_c5_2 bnd_a443 bnd_a445) &
% 7.18/6.75 ~ bnd_c10_2 bnd_a443 bnd_a445) &
% 7.18/6.75 ~ bnd_c8_2 bnd_a443 bnd_a445)) &
% 7.18/6.75 (bnd_c10_0 |
% 7.18/6.75 (ALL X4.
% 7.18/6.75 bnd_ndr1_0 -->
% 7.18/6.75 (bnd_c1_1 X4 | ~ bnd_c9_1 X4) |
% 7.18/6.75 (ALL X5.
% 7.18/6.75 bnd_ndr1_1 X4 -->
% 7.18/6.75 (bnd_c2_2 X4 X5 | bnd_c4_2 X4 X5) |
% 7.18/6.75 bnd_c9_2 X4 X5)))) &
% 7.18/6.75 ((bnd_c10_0 |
% 7.18/6.75 (ALL X6.
% 7.18/6.75 bnd_ndr1_0 -->
% 7.18/6.75 (bnd_c10_1 X6 |
% 7.18/6.75 ((bnd_ndr1_1 X6 & bnd_c1_2 X6 bnd_a446) &
% 7.18/6.75 ~ bnd_c6_2 X6 bnd_a446) &
% 7.18/6.75 ~ bnd_c9_2 X6 bnd_a446) |
% 7.18/6.75 ((bnd_ndr1_1 X6 &
% 7.18/6.75 ~ bnd_c10_2 X6 bnd_a447) &
% 7.18/6.75 ~ bnd_c2_2 X6 bnd_a447) &
% 7.18/6.75 ~ bnd_c3_2 X6 bnd_a447)) |
% 7.18/6.75 ((bnd_ndr1_0 & ~ bnd_c9_1 bnd_a448) &
% 7.18/6.75 (ALL X7.
% 7.18/6.75 bnd_ndr1_1 bnd_a448 -->
% 7.18/6.75 (bnd_c1_2 bnd_a448 X7 |
% 7.18/6.75 bnd_c5_2 bnd_a448 X7) |
% 7.18/6.75 ~ bnd_c8_2 bnd_a448 X7)) &
% 7.18/6.75 (ALL X8.
% 7.18/6.75 bnd_ndr1_1 bnd_a448 -->
% 7.18/6.75 (bnd_c1_2 bnd_a448 X8 |
% 7.18/6.75 ~ bnd_c4_2 bnd_a448 X8) |
% 7.18/6.75 ~ bnd_c6_2 bnd_a448 X8))) &
% 7.18/6.75 (bnd_c10_0 |
% 7.18/6.75 (ALL X9.
% 7.18/6.75 bnd_ndr1_0 -->
% 7.18/6.75 (bnd_c2_1 X9 | bnd_c9_1 X9) |
% 7.18/6.75 ~ bnd_c3_1 X9))) &
% 7.18/6.75 ((bnd_c10_0 |
% 7.18/6.75 (((((bnd_ndr1_0 & bnd_c3_1 bnd_a449) &
% 7.18/6.75 (ALL X10.
% 7.18/6.75 bnd_ndr1_1 bnd_a449 -->
% 7.18/6.75 bnd_c3_2 bnd_a449 X10 |
% 7.18/6.75 bnd_c6_2 bnd_a449 X10)) &
% 7.18/6.75 bnd_ndr1_1 bnd_a449) &
% 7.18/6.75 bnd_c4_2 bnd_a449 bnd_a450) &
% 7.18/6.75 bnd_c7_2 bnd_a449 bnd_a450) &
% 7.18/6.75 ~ bnd_c9_2 bnd_a449 bnd_a450) |
% 7.18/6.75 ((((bnd_ndr1_0 & ~ bnd_c6_1 bnd_a451) &
% 7.18/6.75 bnd_ndr1_1 bnd_a451) &
% 7.18/6.75 bnd_c5_2 bnd_a451 bnd_a452) &
% 7.18/6.75 ~ bnd_c6_2 bnd_a451 bnd_a452) &
% 7.18/6.75 ~ bnd_c9_2 bnd_a451 bnd_a452)) &
% 7.18/6.75 (bnd_c10_0 |
% 7.18/6.75 (((((bnd_ndr1_0 & bnd_c8_1 bnd_a453) &
% 7.18/6.75 (ALL X11.
% 7.18/6.75 bnd_ndr1_1 bnd_a453 -->
% 7.18/6.75 (~ bnd_c10_2 bnd_a453 X11 |
% 7.18/6.75 ~ bnd_c4_2 bnd_a453 X11) |
% 7.18/6.75 ~ bnd_c5_2 bnd_a453 X11)) &
% 7.18/6.75 bnd_ndr1_1 bnd_a453) &
% 7.18/6.75 bnd_c7_2 bnd_a453 bnd_a454) &
% 7.18/6.75 ~ bnd_c2_2 bnd_a453 bnd_a454) &
% 7.18/6.75 ~ bnd_c5_2 bnd_a453 bnd_a454)) &
% 7.18/6.75 (bnd_c10_0 |
% 7.18/6.75 (((((bnd_ndr1_0 &
% 7.18/6.75 (ALL X12.
% 7.18/6.75 bnd_ndr1_1 bnd_a455 -->
% 7.18/6.75 (bnd_c3_2 bnd_a455 X12 |
% 7.18/6.75 bnd_c8_2 bnd_a455 X12) |
% 7.18/6.75 ~ bnd_c1_2 bnd_a455 X12)) &
% 7.18/6.75 (ALL X13.
% 7.18/6.75 bnd_ndr1_1 bnd_a455 -->
% 7.18/6.75 (bnd_c3_2 bnd_a455 X13 |
% 7.18/6.75 bnd_c9_2 bnd_a455 X13) |
% 7.18/6.75 ~ bnd_c1_2 bnd_a455 X13)) &
% 7.18/6.75 bnd_ndr1_1 bnd_a455) &
% 7.18/6.75 bnd_c8_2 bnd_a455 bnd_a456) &
% 7.18/6.75 ~ bnd_c2_2 bnd_a455 bnd_a456) &
% 7.18/6.75 ~ bnd_c4_2 bnd_a455 bnd_a456)) &
% 7.18/6.75 (bnd_c10_0 |
% 7.18/6.75 ((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a457) &
% 7.18/6.75 bnd_c1_2 bnd_a457 bnd_a458) &
% 7.18/6.75 ~ bnd_c8_2 bnd_a457 bnd_a458) &
% 7.18/6.75 bnd_ndr1_1 bnd_a457) &
% 7.18/6.75 bnd_c10_2 bnd_a457 bnd_a459) &
% 7.18/6.75 ~ bnd_c2_2 bnd_a457 bnd_a459) &
% 7.18/6.75 ~ bnd_c4_2 bnd_a457 bnd_a459)) &
% 7.18/6.75 ((bnd_c2_0 | bnd_c7_0) |
% 7.18/6.75 ((bnd_ndr1_0 & bnd_c1_1 bnd_a460) &
% 7.18/6.75 bnd_c2_1 bnd_a460) &
% 7.18/6.75 ~ bnd_c5_1 bnd_a460)) &
% 7.18/6.75 ((bnd_c2_0 | ~ bnd_c1_0) |
% 7.18/6.75 (ALL X14.
% 7.18/6.75 bnd_ndr1_0 -->
% 7.18/6.75 (ALL X15.
% 7.18/6.75 bnd_ndr1_1 X14 -->
% 7.18/6.75 (~ bnd_c10_2 X14 X15 | ~ bnd_c4_2 X14 X15) |
% 7.18/6.75 ~ bnd_c9_2 X14 X15)))) &
% 7.18/6.75 ((bnd_c2_0 | ~ bnd_c4_0) | ~ bnd_c7_0)) &
% 7.18/6.75 ((bnd_c2_0 | ~ bnd_c5_0) |
% 7.18/6.75 (ALL X16.
% 7.18/6.75 bnd_ndr1_0 --> bnd_c3_1 X16 | ~ bnd_c6_1 X16))) &
% 7.18/6.75 ((bnd_c2_0 | ~ bnd_c7_0) |
% 7.18/6.75 (((((bnd_ndr1_0 & ~ bnd_c3_1 bnd_a461) &
% 7.18/6.75 ~ bnd_c4_1 bnd_a461) &
% 7.18/6.75 bnd_ndr1_1 bnd_a461) &
% 7.18/6.75 ~ bnd_c1_2 bnd_a461 bnd_a462) &
% 7.18/6.75 ~ bnd_c3_2 bnd_a461 bnd_a462) &
% 7.18/6.75 ~ bnd_c8_2 bnd_a461 bnd_a462)) &
% 7.18/6.75 ((bnd_c3_0 | bnd_c7_0) |
% 7.18/6.75 (ALL X17.
% 7.18/6.75 bnd_ndr1_0 -->
% 7.18/6.75 (bnd_c4_1 X17 |
% 7.18/6.75 (ALL X18.
% 7.18/6.75 bnd_ndr1_1 X17 -->
% 7.18/6.75 (bnd_c9_2 X17 X18 | ~ bnd_c1_2 X17 X18) |
% 7.18/6.75 ~ bnd_c3_2 X17 X18)) |
% 7.18/6.75 ((bnd_ndr1_1 X17 & bnd_c7_2 X17 bnd_a463) &
% 7.18/6.75 ~ bnd_c2_2 X17 bnd_a463) &
% 7.18/6.75 ~ bnd_c5_2 X17 bnd_a463))) &
% 7.18/6.75 ((bnd_c3_0 | ~ bnd_c1_0) |
% 7.18/6.75 (ALL X19.
% 7.18/6.75 bnd_ndr1_0 -->
% 7.18/6.75 (bnd_c4_1 X19 | ~ bnd_c8_1 X19) |
% 7.18/6.75 (ALL X20.
% 7.18/6.75 bnd_ndr1_1 X19 -->
% 7.18/6.75 (bnd_c1_2 X19 X20 | bnd_c6_2 X19 X20) |
% 7.18/6.75 ~ bnd_c3_2 X19 X20)))) &
% 7.18/6.75 ((bnd_c3_0 | ~ bnd_c1_0) |
% 7.18/6.75 (ALL X21.
% 7.18/6.75 bnd_ndr1_0 -->
% 7.18/6.75 ~ bnd_c7_1 X21 |
% 7.18/6.75 (ALL X22.
% 7.18/6.75 bnd_ndr1_1 X21 -->
% 7.18/6.75 (bnd_c5_2 X21 X22 | ~ bnd_c1_2 X21 X22) |
% 7.18/6.75 ~ bnd_c9_2 X21 X22)))) &
% 7.18/6.75 ((bnd_c3_0 | ~ bnd_c10_0) |
% 7.18/6.75 (ALL X23.
% 7.18/6.75 bnd_ndr1_0 -->
% 7.18/6.75 (bnd_c6_1 X23 |
% 7.18/6.75 (ALL X24.
% 7.18/6.75 bnd_ndr1_1 X23 -->
% 7.18/6.75 (bnd_c8_2 X23 X24 | ~ bnd_c3_2 X23 X24) |
% 7.18/6.75 ~ bnd_c6_2 X23 X24)) |
% 7.18/6.75 ((bnd_ndr1_1 X23 & bnd_c3_2 X23 bnd_a464) &
% 7.18/6.75 bnd_c7_2 X23 bnd_a464) &
% 7.18/6.75 ~ bnd_c6_2 X23 bnd_a464))) &
% 7.18/6.75 ((bnd_c3_0 | ~ bnd_c4_0) | ~ bnd_c7_0)) &
% 7.18/6.75 (bnd_c3_0 |
% 7.18/6.75 (((((bnd_ndr1_0 & ~ bnd_c10_1 bnd_a465) &
% 7.18/6.75 (ALL X25.
% 7.18/6.75 bnd_ndr1_1 bnd_a465 -->
% 7.18/6.75 (bnd_c8_2 bnd_a465 X25 | ~ bnd_c3_2 bnd_a465 X25) |
% 7.18/6.75 ~ bnd_c4_2 bnd_a465 X25)) &
% 7.18/6.75 bnd_ndr1_1 bnd_a465) &
% 7.18/6.75 bnd_c2_2 bnd_a465 bnd_a466) &
% 7.18/6.75 bnd_c6_2 bnd_a465 bnd_a466) &
% 7.18/6.75 ~ bnd_c1_2 bnd_a465 bnd_a466)) &
% 7.18/6.75 ((bnd_c3_0 |
% 7.18/6.75 (ALL X26.
% 7.18/6.75 bnd_ndr1_0 -->
% 7.18/6.75 (~ bnd_c7_1 X26 | ~ bnd_c8_1 X26) |
% 7.18/6.75 (ALL X27.
% 7.18/6.75 bnd_ndr1_1 X26 -->
% 7.18/6.75 bnd_c5_2 X26 X27 | ~ bnd_c3_2 X26 X27))) |
% 7.18/6.75 ((bnd_ndr1_0 & bnd_c1_1 bnd_a467) & bnd_c5_1 bnd_a467) &
% 7.18/6.75 ~ bnd_c6_1 bnd_a467)) &
% 7.18/6.75 ((bnd_c4_0 | bnd_c5_0) |
% 7.18/6.75 (((((bnd_ndr1_0 & ~ bnd_c6_1 bnd_a468) &
% 7.18/6.75 (ALL X28.
% 7.18/6.75 bnd_ndr1_1 bnd_a468 -->
% 7.18/6.75 (bnd_c1_2 bnd_a468 X28 | bnd_c9_2 bnd_a468 X28) |
% 7.18/6.75 ~ bnd_c4_2 bnd_a468 X28)) &
% 7.18/6.75 bnd_ndr1_1 bnd_a468) &
% 7.18/6.75 bnd_c6_2 bnd_a468 bnd_a469) &
% 7.18/6.75 bnd_c9_2 bnd_a468 bnd_a469) &
% 7.18/6.75 ~ bnd_c7_2 bnd_a468 bnd_a469)) &
% 7.18/6.75 (bnd_c4_0 |
% 7.18/6.75 ((((bnd_ndr1_0 & bnd_c8_1 bnd_a470) &
% 7.18/6.75 (ALL X29.
% 7.18/6.75 bnd_ndr1_1 bnd_a470 -->
% 7.18/6.75 (bnd_c3_2 bnd_a470 X29 | bnd_c7_2 bnd_a470 X29) |
% 7.18/6.75 ~ bnd_c4_2 bnd_a470 X29)) &
% 7.18/6.75 bnd_ndr1_1 bnd_a470) &
% 7.18/6.75 bnd_c7_2 bnd_a470 bnd_a471) &
% 7.18/6.75 bnd_c8_2 bnd_a470 bnd_a471)) &
% 7.18/6.75 ((bnd_c4_0 | ~ bnd_c9_0) |
% 7.18/6.75 (ALL X30.
% 7.18/6.75 bnd_ndr1_0 -->
% 7.18/6.75 (bnd_c9_1 X30 | ~ bnd_c10_1 X30) |
% 7.18/6.75 (ALL X31.
% 7.18/6.75 bnd_ndr1_1 X30 -->
% 7.18/6.75 (~ bnd_c10_2 X30 X31 | ~ bnd_c7_2 X30 X31) |
% 7.18/6.75 ~ bnd_c8_2 X30 X31)))) &
% 7.18/6.75 (bnd_c4_0 |
% 7.18/6.75 (ALL X32.
% 7.18/6.75 bnd_ndr1_0 -->
% 7.18/6.75 (bnd_c6_1 X32 |
% 7.18/6.75 (ALL X33.
% 7.18/6.75 bnd_ndr1_1 X32 -->
% 7.18/6.75 (bnd_c4_2 X32 X33 | bnd_c5_2 X32 X33) | bnd_c9_2 X32 X33)) |
% 7.18/6.75 (ALL X34.
% 7.18/6.75 bnd_ndr1_1 X32 -->
% 7.18/6.75 (bnd_c6_2 X32 X34 | bnd_c8_2 X32 X34) |
% 7.18/6.75 ~ bnd_c4_2 X32 X34)))) &
% 7.18/6.75 ((bnd_c4_0 |
% 7.18/6.75 (ALL X35.
% 7.18/6.75 bnd_ndr1_0 -->
% 7.18/6.75 (~ bnd_c5_1 X35 |
% 7.18/6.75 ((bnd_ndr1_1 X35 & bnd_c2_2 X35 bnd_a472) &
% 7.18/6.75 bnd_c9_2 X35 bnd_a472) &
% 7.18/6.75 ~ bnd_c3_2 X35 bnd_a472) |
% 7.18/6.75 ((bnd_ndr1_1 X35 & bnd_c5_2 X35 bnd_a473) &
% 7.18/6.75 bnd_c8_2 X35 bnd_a473) &
% 7.18/6.75 bnd_c9_2 X35 bnd_a473)) |
% 7.18/6.75 ((bnd_ndr1_0 & bnd_c10_1 bnd_a474) & ~ bnd_c8_1 bnd_a474) &
% 7.18/6.75 (ALL X36.
% 7.18/6.75 bnd_ndr1_1 bnd_a474 -->
% 7.18/6.75 (bnd_c10_2 bnd_a474 X36 | bnd_c4_2 bnd_a474 X36) |
% 7.18/6.75 ~ bnd_c3_2 bnd_a474 X36))) &
% 7.18/6.75 (bnd_c5_0 |
% 7.18/6.75 (ALL X37.
% 7.18/6.75 bnd_ndr1_0 -->
% 7.18/6.75 (~ bnd_c2_1 X37 |
% 7.18/6.75 (bnd_ndr1_1 X37 & bnd_c1_2 X37 bnd_a475) &
% 7.18/6.75 ~ bnd_c7_2 X37 bnd_a475) |
% 7.18/6.75 ((bnd_ndr1_1 X37 & bnd_c2_2 X37 bnd_a476) &
% 7.18/6.75 ~ bnd_c10_2 X37 bnd_a476) &
% 7.18/6.75 ~ bnd_c4_2 X37 bnd_a476))) &
% 7.18/6.75 ((bnd_c5_0 | ~ bnd_c1_0) |
% 7.18/6.75 ((bnd_ndr1_0 & bnd_c9_1 bnd_a477) & ~ bnd_c10_1 bnd_a477) &
% 7.18/6.75 ~ bnd_c3_1 bnd_a477)) &
% 7.18/6.75 ((bnd_c5_0 | ~ bnd_c3_0) |
% 7.18/6.75 (ALL X38.
% 7.18/6.75 bnd_ndr1_0 -->
% 7.18/6.75 (bnd_c10_1 X38 | bnd_c2_1 X38) |
% 7.18/6.75 ((bnd_ndr1_1 X38 & bnd_c6_2 X38 bnd_a478) &
% 7.18/6.75 ~ bnd_c4_2 X38 bnd_a478) &
% 7.18/6.75 ~ bnd_c7_2 X38 bnd_a478))) &
% 7.18/6.75 (bnd_c5_0 |
% 7.18/6.75 ((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a479) & bnd_c10_2 bnd_a479 bnd_a480) &
% 7.18/6.75 bnd_c9_2 bnd_a479 bnd_a480) &
% 7.18/6.75 bnd_ndr1_1 bnd_a479) &
% 7.18/6.75 bnd_c5_2 bnd_a479 bnd_a481) &
% 7.18/6.75 bnd_c8_2 bnd_a479 bnd_a481) &
% 7.18/6.75 ~ bnd_c4_2 bnd_a479 bnd_a481)) &
% 7.18/6.75 ((bnd_c5_0 | ~ bnd_c7_0) |
% 7.18/6.75 (bnd_ndr1_0 & bnd_c2_1 bnd_a482) & ~ bnd_c5_1 bnd_a482)) &
% 7.18/6.75 ((bnd_c5_0 | ~ bnd_c7_0) |
% 7.18/6.75 (bnd_ndr1_0 & bnd_c6_1 bnd_a483) & ~ bnd_c3_1 bnd_a483)) &
% 7.18/6.75 ((bnd_c5_0 |
% 7.18/6.75 (ALL X39.
% 7.18/6.75 bnd_ndr1_0 -->
% 7.18/6.75 bnd_c2_1 X39 |
% 7.18/6.75 ((bnd_ndr1_1 X39 & bnd_c4_2 X39 bnd_a484) & bnd_c5_2 X39 bnd_a484) &
% 7.18/6.75 bnd_c9_2 X39 bnd_a484)) |
% 7.18/6.75 ((((((((bnd_ndr1_0 &
% 7.18/6.75 bnd_c1_1 bnd_a485) &
% 7.18/6.75 bnd_ndr1_1 bnd_a485) &
% 7.18/6.75 bnd_c5_2 bnd_a485 bnd_a486) &
% 7.18/6.75 bnd_c7_2 bnd_a485 bnd_a486) &
% 7.18/6.75 ~ bnd_c6_2 bnd_a485 bnd_a486) &
% 7.18/6.75 bnd_ndr1_1 bnd_a485) &
% 7.18/6.75 ~ bnd_c2_2 bnd_a485 bnd_a487) &
% 7.18/6.75 ~ bnd_c3_2 bnd_a485 bnd_a487) &
% 7.18/6.75 ~ bnd_c8_2 bnd_a485 bnd_a487)) &
% 7.18/6.75 ((bnd_c5_0 |
% 7.18/6.75 (ALL X40.
% 7.18/6.75 bnd_ndr1_0 -->
% 7.18/6.75 (~ bnd_c3_1 X40 | ~ bnd_c7_1 X40) |
% 7.18/6.75 ((bnd_ndr1_1 X40 & bnd_c1_2 X40 bnd_a488) & bnd_c4_2 X40 bnd_a488) &
% 7.18/6.75 bnd_c5_2 X40 bnd_a488)) |
% 7.18/6.75 ((bnd_ndr1_0 & bnd_c3_1 bnd_a489) &
% 7.18/6.75 ~ bnd_c8_1 bnd_a489) &
% 7.18/6.75 (ALL X41.
% 7.18/6.75 bnd_ndr1_1 bnd_a489 -->
% 7.18/6.75 (bnd_c3_2 bnd_a489 X41 | bnd_c8_2 bnd_a489 X41) |
% 7.18/6.75 ~ bnd_c1_2 bnd_a489 X41))) &
% 7.18/6.75 ((bnd_c5_0 |
% 7.18/6.75 ((bnd_ndr1_0 & bnd_c6_1 bnd_a490) &
% 7.18/6.75 bnd_c8_1 bnd_a490) &
% 7.18/6.75 ~ bnd_c9_1 bnd_a490) |
% 7.18/6.75 (((((bnd_ndr1_0 & bnd_c8_1 bnd_a491) &
% 7.18/6.75 ~ bnd_c4_1 bnd_a491) &
% 7.18/6.75 bnd_ndr1_1 bnd_a491) &
% 7.18/6.75 bnd_c3_2 bnd_a491 bnd_a492) &
% 7.18/6.75 ~ bnd_c1_2 bnd_a491 bnd_a492) &
% 7.18/6.75 ~ bnd_c4_2 bnd_a491 bnd_a492)) &
% 7.18/6.75 (bnd_c7_0 | ~ bnd_c1_0)) &
% 7.18/6.75 ((bnd_c7_0 | ~ bnd_c5_0) |
% 7.18/6.75 (bnd_ndr1_0 & bnd_c2_1 bnd_a493) &
% 7.18/6.75 (ALL X42.
% 7.18/6.75 bnd_ndr1_1 bnd_a493 -->
% 7.18/6.75 (bnd_c10_2 bnd_a493 X42 |
% 7.18/6.75 bnd_c3_2 bnd_a493 X42) |
% 7.18/6.75 ~ bnd_c5_2 bnd_a493 X42))) &
% 7.18/6.75 ((bnd_c7_0 |
% 7.18/6.75 (ALL X43.
% 7.18/6.75 bnd_ndr1_0 -->
% 7.18/6.75 ~ bnd_c1_1 X43 | ~ bnd_c10_1 X43)) |
% 7.18/6.75 (ALL X44.
% 7.18/6.75 bnd_ndr1_0 -->
% 7.18/6.75 ((ALL X45.
% 7.18/6.75 bnd_ndr1_1 X44 -->
% 7.18/6.75 (bnd_c6_2 X44 X45 | bnd_c7_2 X44 X45) | ~ bnd_c3_2 X44 X45) |
% 7.18/6.75 ((bnd_ndr1_1 X44 &
% 7.18/6.75 bnd_c2_2 X44 bnd_a494) &
% 7.18/6.75 bnd_c5_2 X44 bnd_a494) &
% 7.18/6.75 bnd_c8_2 X44 bnd_a494) |
% 7.18/6.75 ((bnd_ndr1_1 X44 &
% 7.18/6.75 ~ bnd_c1_2 X44 bnd_a495) &
% 7.18/6.75 ~ bnd_c3_2 X44 bnd_a495) &
% 7.18/6.75 ~ bnd_c4_2 X44 bnd_a495))) &
% 7.18/6.75 ((bnd_c7_0 |
% 7.18/6.75 (ALL X46.
% 7.18/6.75 bnd_ndr1_0 -->
% 7.18/6.75 (~ bnd_c4_1 X46 |
% 7.18/6.75 ((bnd_ndr1_1 X46 &
% 7.18/6.75 bnd_c4_2 X46 bnd_a496) &
% 7.18/6.75 bnd_c9_2 X46 bnd_a496) &
% 7.18/6.75 ~ bnd_c7_2 X46 bnd_a496) |
% 7.18/6.75 ((bnd_ndr1_1 X46 &
% 7.18/6.75 bnd_c5_2 X46 bnd_a497) &
% 7.18/6.75 ~ bnd_c2_2 X46 bnd_a497) &
% 7.18/6.75 ~ bnd_c7_2 X46 bnd_a497)) |
% 7.18/6.75 (bnd_ndr1_0 & ~ bnd_c2_1 bnd_a498) &
% 7.18/6.75 ~ bnd_c6_1 bnd_a498)) &
% 7.18/6.75 ((bnd_c7_0 |
% 7.18/6.75 (bnd_ndr1_0 & bnd_c1_1 bnd_a499) &
% 7.18/6.75 ~ bnd_c2_1 bnd_a499) |
% 7.18/6.75 (bnd_ndr1_0 & bnd_c10_1 bnd_a500) &
% 7.18/6.75 bnd_c4_1 bnd_a500)) &
% 7.18/6.75 (bnd_c7_0 |
% 7.18/6.75 (((((bnd_ndr1_0 &
% 7.18/6.75 (ALL X47.
% 7.18/6.75 bnd_ndr1_1 bnd_a501 -->
% 7.18/6.75 (bnd_c3_2 bnd_a501 X47 | ~ bnd_c1_2 bnd_a501 X47) |
% 7.18/6.75 ~ bnd_c6_2 bnd_a501 X47)) &
% 7.18/6.75 (ALL X48.
% 7.18/6.75 bnd_ndr1_1 bnd_a501 -->
% 7.18/6.75 (bnd_c6_2 bnd_a501 X48 |
% 7.18/6.75 bnd_c9_2 bnd_a501 X48) |
% 7.18/6.75 ~ bnd_c7_2 bnd_a501 X48)) &
% 7.18/6.75 bnd_ndr1_1 bnd_a501) &
% 7.18/6.75 bnd_c3_2 bnd_a501 bnd_a502) &
% 7.18/6.75 bnd_c9_2 bnd_a501 bnd_a502) &
% 7.18/6.75 ~ bnd_c2_2 bnd_a501 bnd_a502)) &
% 7.18/6.75 (~ bnd_c10_0 | ~ bnd_c7_0)) &
% 7.18/6.75 (~ bnd_c10_0 |
% 7.18/6.75 ((bnd_ndr1_0 & ~ bnd_c6_1 bnd_a503) &
% 7.18/6.75 (ALL X49.
% 7.18/6.75 bnd_ndr1_1 bnd_a503 -->
% 7.18/6.75 (bnd_c4_2 bnd_a503 X49 |
% 7.18/6.75 bnd_c9_2 bnd_a503 X49) |
% 7.18/6.75 ~ bnd_c7_2 bnd_a503 X49)) &
% 7.18/6.75 (ALL X50.
% 7.18/6.75 bnd_ndr1_1 bnd_a503 -->
% 7.18/6.75 (bnd_c8_2 bnd_a503 X50 |
% 7.18/6.75 bnd_c9_2 bnd_a503 X50) |
% 7.18/6.75 ~ bnd_c1_2 bnd_a503 X50))) &
% 7.18/6.75 (~ bnd_c4_0 | ~ bnd_c5_0)) &
% 7.18/6.75 (ALL X51.
% 7.18/6.75 bnd_ndr1_0 -->
% 7.18/6.75 (bnd_c2_1 X51 | ~ bnd_c3_1 X51) |
% 7.18/6.75 (bnd_ndr1_1 X51 & bnd_c2_2 X51 bnd_a504) &
% 7.18/6.75 bnd_c3_2 X51 bnd_a504)) &
% 7.18/6.75 ((ALL X52.
% 7.18/6.75 bnd_ndr1_0 -->
% 7.18/6.75 (bnd_c1_1 X52 |
% 7.18/6.75 (ALL X53.
% 7.18/6.75 bnd_ndr1_1 X52 -->
% 7.18/6.75 (bnd_c2_2 X52 X53 | ~ bnd_c10_2 X52 X53) |
% 7.18/6.75 ~ bnd_c9_2 X52 X53)) |
% 7.18/6.75 (bnd_ndr1_1 X52 & bnd_c6_2 X52 bnd_a505) &
% 7.18/6.75 ~ bnd_c3_2 X52 bnd_a505) |
% 7.18/6.75 (ALL X54.
% 7.18/6.75 bnd_ndr1_0 -->
% 7.18/6.75 ((ALL X55.
% 7.18/6.75 bnd_ndr1_1 X54 -->
% 7.18/6.75 (bnd_c1_2 X54 X55 | bnd_c3_2 X54 X55) |
% 7.18/6.75 ~ bnd_c7_2 X54 X55) |
% 7.18/6.75 (ALL X56.
% 7.18/6.75 bnd_ndr1_1 X54 -->
% 7.18/6.75 (bnd_c2_2 X54 X56 | bnd_c3_2 X54 X56) |
% 7.18/6.75 ~ bnd_c6_2 X54 X56)) |
% 7.18/6.75 ((bnd_ndr1_1 X54 & bnd_c6_2 X54 bnd_a506) &
% 7.18/6.75 ~ bnd_c1_2 X54 bnd_a506) &
% 7.18/6.75 ~ bnd_c8_2 X54 bnd_a506))) &
% 7.18/6.75 ((ALL X57.
% 7.18/6.75 bnd_ndr1_0 -->
% 7.18/6.75 (bnd_c9_1 X57 | ~ bnd_c4_1 X57) |
% 7.18/6.75 ((bnd_ndr1_1 X57 & bnd_c1_2 X57 bnd_a507) &
% 7.18/6.75 ~ bnd_c2_2 X57 bnd_a507) &
% 7.18/6.75 ~ bnd_c5_2 X57 bnd_a507) |
% 7.18/6.75 ((((bnd_ndr1_0 &
% 7.18/6.75 (ALL X58.
% 7.18/6.75 bnd_ndr1_1 bnd_a508 -->
% 7.18/6.75 bnd_c8_2 bnd_a508 X58 |
% 7.18/6.75 ~ bnd_c6_2 bnd_a508 X58)) &
% 7.18/6.75 bnd_ndr1_1 bnd_a508) &
% 7.18/6.75 ~ bnd_c2_2 bnd_a508 bnd_a509) &
% 7.18/6.75 ~ bnd_c5_2 bnd_a508 bnd_a509) &
% 7.18/6.75 ~ bnd_c9_2 bnd_a508 bnd_a509)) &
% 7.18/6.75 ((ALL X59.
% 7.18/6.75 bnd_ndr1_0 -->
% 7.18/6.75 (~ bnd_c2_1 X59 | ~ bnd_c8_1 X59) |
% 7.18/6.75 (ALL X60.
% 7.18/6.75 bnd_ndr1_1 X59 -->
% 7.18/6.75 (bnd_c3_2 X59 X60 | bnd_c4_2 X59 X60) |
% 7.18/6.75 ~ bnd_c2_2 X59 X60)) |
% 7.18/6.75 ((bnd_ndr1_0 & bnd_c6_1 bnd_a510) &
% 7.18/6.75 bnd_c7_1 bnd_a510) &
% 7.18/6.75 ~ bnd_c8_1 bnd_a510)) &
% 7.18/6.75 (ALL X61.
% 7.18/6.75 bnd_ndr1_0 -->
% 7.18/6.75 (~ bnd_c2_1 X61 |
% 7.18/6.75 (ALL X62.
% 7.18/6.75 bnd_ndr1_1 X61 -->
% 7.18/6.75 (bnd_c8_2 X61 X62 | ~ bnd_c2_2 X61 X62) |
% 7.18/6.75 ~ bnd_c9_2 X61 X62)) |
% 7.18/6.75 ((bnd_ndr1_1 X61 & bnd_c1_2 X61 bnd_a511) &
% 7.18/6.75 bnd_c4_2 X61 bnd_a511) &
% 7.18/6.75 ~ bnd_c8_2 X61 bnd_a511)) &
% 7.18/6.75 ((ALL X63.
% 7.18/6.75 bnd_ndr1_0 -->
% 7.18/6.75 (~ bnd_c2_1 X63 |
% 7.18/6.75 (ALL X64.
% 7.18/6.75 bnd_ndr1_1 X63 -->
% 7.18/6.75 (~ bnd_c4_2 X63 X64 | ~ bnd_c7_2 X63 X64) |
% 7.18/6.75 ~ bnd_c9_2 X63 X64)) |
% 7.18/6.75 ((bnd_ndr1_1 X63 & bnd_c1_2 X63 bnd_a512) &
% 7.18/6.75 ~ bnd_c3_2 X63 bnd_a512) &
% 7.18/6.75 ~ bnd_c4_2 X63 bnd_a512) |
% 7.18/6.75 ((bnd_ndr1_0 & bnd_c10_1 bnd_a513) &
% 7.18/6.75 bnd_c3_1 bnd_a513) &
% 7.18/6.75 (ALL X65.
% 7.18/6.75 bnd_ndr1_1 bnd_a513 -->
% 7.18/6.75 (bnd_c8_2 bnd_a513 X65 | ~ bnd_c2_2 bnd_a513 X65) |
% 7.18/6.75 ~ bnd_c5_2 bnd_a513 X65))) &
% 7.18/6.75 (ALL X66.
% 7.18/6.75 bnd_ndr1_0 --> ~ bnd_c3_1 X66 | ~ bnd_c9_1 X66)) &
% 7.18/6.75 ((ALL X67.
% 7.18/6.75 bnd_ndr1_0 -->
% 7.18/6.75 (~ bnd_c8_1 X67 |
% 7.18/6.75 (ALL X68.
% 7.18/6.75 bnd_ndr1_1 X67 -->
% 7.18/6.75 (bnd_c10_2 X67 X68 | bnd_c2_2 X67 X68) |
% 7.18/6.75 bnd_c7_2 X67 X68)) |
% 7.18/6.75 (ALL X69.
% 7.18/6.75 bnd_ndr1_1 X67 -->
% 7.18/6.75 (bnd_c3_2 X67 X69 | bnd_c8_2 X67 X69) |
% 7.18/6.75 bnd_c9_2 X67 X69)) |
% 7.18/6.75 (bnd_ndr1_0 & bnd_c10_1 bnd_a514) &
% 7.18/6.75 ~ bnd_c8_1 bnd_a514)) &
% 7.18/6.75 (((bnd_ndr1_0 & bnd_c1_1 bnd_a515) & bnd_c8_1 bnd_a515) &
% 7.18/6.75 ~ bnd_c7_1 bnd_a515 |
% 7.18/6.75 ((bnd_ndr1_0 & bnd_c2_1 bnd_a516) & bnd_c7_1 bnd_a516) &
% 7.18/6.75 ~ bnd_c4_1 bnd_a516)) &
% 7.18/6.75 ((bnd_c9_0 | ~ bnd_c1_0) |
% 7.18/6.75 (bnd_ndr1_0 & bnd_c3_1 bnd_a517) &
% 7.18/6.75 (ALL X70.
% 7.18/6.75 bnd_ndr1_1 bnd_a517 -->
% 7.18/6.75 (bnd_c1_2 bnd_a517 X70 | bnd_c5_2 bnd_a517 X70) |
% 7.18/6.75 ~ bnd_c6_2 bnd_a517 X70))) &
% 7.18/6.75 ((bnd_c9_0 | ~ bnd_c10_0) |
% 7.18/6.75 (ALL X71.
% 7.18/6.75 bnd_ndr1_0 -->
% 7.18/6.75 (~ bnd_c1_1 X71 | ~ bnd_c9_1 X71) |
% 7.18/6.75 ((bnd_ndr1_1 X71 & bnd_c1_2 X71 bnd_a518) &
% 7.18/6.75 bnd_c4_2 X71 bnd_a518) &
% 7.18/6.75 ~ bnd_c8_2 X71 bnd_a518))) &
% 7.18/6.75 ((bnd_c9_0 | ~ bnd_c5_0) |
% 7.18/6.75 (ALL X72.
% 7.18/6.75 bnd_ndr1_0 -->
% 7.18/6.75 (bnd_c9_1 X72 | ~ bnd_c1_1 X72) |
% 7.18/6.75 ((bnd_ndr1_1 X72 & bnd_c2_2 X72 bnd_a519) &
% 7.18/6.75 ~ bnd_c1_2 X72 bnd_a519) &
% 7.18/6.75 ~ bnd_c3_2 X72 bnd_a519))) &
% 7.18/6.75 ((bnd_c9_0 |
% 7.18/6.75 (ALL X73.
% 7.18/6.75 bnd_ndr1_0 -->
% 7.18/6.75 (~ bnd_c1_1 X73 |
% 7.18/6.75 (ALL X74.
% 7.18/6.75 bnd_ndr1_1 X73 -->
% 7.18/6.75 (bnd_c1_2 X73 X74 | bnd_c4_2 X73 X74) |
% 7.18/6.75 ~ bnd_c3_2 X73 X74)) |
% 7.18/6.75 (bnd_ndr1_1 X73 & bnd_c8_2 X73 bnd_a520) &
% 7.18/6.75 ~ bnd_c2_2 X73 bnd_a520)) |
% 7.18/6.75 (((((bnd_ndr1_0 &
% 7.18/6.75 (ALL X75.
% 7.18/6.75 bnd_ndr1_1 bnd_a521 -->
% 7.18/6.75 (bnd_c1_2 bnd_a521 X75 | bnd_c3_2 bnd_a521 X75) |
% 7.18/6.75 ~ bnd_c4_2 bnd_a521 X75)) &
% 7.18/6.75 (ALL X76.
% 7.18/6.75 bnd_ndr1_1 bnd_a521 -->
% 7.18/6.75 (bnd_c1_2 bnd_a521 X76 | bnd_c8_2 bnd_a521 X76) |
% 7.18/6.75 ~ bnd_c4_2 bnd_a521 X76)) &
% 7.18/6.75 bnd_ndr1_1 bnd_a521) &
% 7.18/6.75 bnd_c3_2 bnd_a521 bnd_a522) &
% 7.18/6.75 bnd_c8_2 bnd_a521 bnd_a522) &
% 7.18/6.75 bnd_c9_2 bnd_a521 bnd_a522)) &
% 7.18/6.75 ((bnd_c9_0 |
% 7.18/6.75 (ALL X77.
% 7.18/6.75 bnd_ndr1_0 -->
% 7.18/6.75 ~ bnd_c10_1 X77 |
% 7.18/6.75 ((bnd_ndr1_1 X77 & bnd_c9_2 X77 bnd_a523) &
% 7.18/6.75 ~ bnd_c10_2 X77 bnd_a523) &
% 7.18/6.75 ~ bnd_c2_2 X77 bnd_a523)) |
% 7.18/6.75 ((((bnd_ndr1_0 & bnd_c3_1 bnd_a524) & bnd_ndr1_1 bnd_a524) &
% 7.18/6.75 bnd_c3_2 bnd_a524 bnd_a525) &
% 7.18/6.75 bnd_c7_2 bnd_a524 bnd_a525) &
% 7.18/6.75 ~ bnd_c4_2 bnd_a524 bnd_a525)) &
% 7.18/6.75 ((~ bnd_c1_0 | ~ bnd_c4_0) |
% 7.18/6.75 ((((bnd_ndr1_0 &
% 7.18/6.75 (ALL X78.
% 7.18/6.75 bnd_ndr1_1 bnd_a526 -->
% 7.18/6.75 (bnd_c8_2 bnd_a526 X78 | ~ bnd_c7_2 bnd_a526 X78) |
% 7.18/6.75 ~ bnd_c9_2 bnd_a526 X78)) &
% 7.18/6.75 (ALL X79.
% 7.18/6.75 bnd_ndr1_1 bnd_a526 -->
% 7.18/6.75 (bnd_c9_2 bnd_a526 X79 | ~ bnd_c2_2 bnd_a526 X79) |
% 7.18/6.75 ~ bnd_c4_2 bnd_a526 X79)) &
% 7.18/6.75 bnd_ndr1_1 bnd_a526) &
% 7.18/6.75 bnd_c9_2 bnd_a526 bnd_a527) &
% 7.18/6.75 ~ bnd_c1_2 bnd_a526 bnd_a527)) &
% 7.18/6.75 (~ bnd_c1_0 |
% 7.18/6.75 (((((bnd_ndr1_0 & bnd_c10_1 bnd_a528) & bnd_c5_1 bnd_a528) &
% 7.18/6.75 bnd_ndr1_1 bnd_a528) &
% 7.18/6.75 bnd_c4_2 bnd_a528 bnd_a529) &
% 7.18/6.75 bnd_c7_2 bnd_a528 bnd_a529) &
% 7.18/6.75 bnd_c9_2 bnd_a528 bnd_a529)) &
% 7.18/6.75 ((~ bnd_c1_0 |
% 7.18/6.75 (ALL X80.
% 7.18/6.75 bnd_ndr1_0 -->
% 7.18/6.75 (~ bnd_c1_1 X80 | ~ bnd_c10_1 X80) |
% 7.18/6.75 (bnd_ndr1_1 X80 & bnd_c8_2 X80 bnd_a530) &
% 7.18/6.75 ~ bnd_c10_2 X80 bnd_a530)) |
% 7.18/6.75 (((((bnd_ndr1_0 & bnd_c8_1 bnd_a531) & ~ bnd_c5_1 bnd_a531) &
% 7.18/6.75 bnd_ndr1_1 bnd_a531) &
% 7.18/6.75 bnd_c10_2 bnd_a531 bnd_a532) &
% 7.18/6.75 ~ bnd_c8_2 bnd_a531 bnd_a532) &
% 7.18/6.75 ~ bnd_c9_2 bnd_a531 bnd_a532)) &
% 7.18/6.75 ((~ bnd_c10_0 | ~ bnd_c4_0) |
% 7.18/6.75 (ALL X81.
% 7.18/6.75 bnd_ndr1_0 -->
% 7.18/6.75 bnd_c7_1 X81 |
% 7.18/6.75 ((bnd_ndr1_1 X81 & bnd_c10_2 X81 bnd_a533) &
% 7.18/6.75 bnd_c5_2 X81 bnd_a533) &
% 7.18/6.75 bnd_c8_2 X81 bnd_a533))) &
% 7.18/6.75 ((~ bnd_c10_0 | ~ bnd_c5_0) |
% 7.18/6.75 (ALL X82.
% 7.18/6.75 bnd_ndr1_0 -->
% 7.18/6.75 ((ALL X83.
% 7.18/6.75 bnd_ndr1_1 X82 --> bnd_c5_2 X82 X83 | ~ bnd_c3_2 X82 X83) |
% 7.18/6.75 ((bnd_ndr1_1 X82 & bnd_c8_2 X82 bnd_a534) &
% 7.18/6.75 ~ bnd_c4_2 X82 bnd_a534) &
% 7.18/6.75 ~ bnd_c5_2 X82 bnd_a534) |
% 7.18/6.75 ((bnd_ndr1_1 X82 & ~ bnd_c4_2 X82 bnd_a535) &
% 7.18/6.75 ~ bnd_c8_2 X82 bnd_a535) &
% 7.18/6.75 ~ bnd_c9_2 X82 bnd_a535))) &
% 7.18/6.75 ((~ bnd_c10_0 | ~ bnd_c5_0) |
% 7.18/6.75 (((((bnd_ndr1_0 & bnd_c10_1 bnd_a536) & ~ bnd_c6_1 bnd_a536) &
% 7.18/6.75 bnd_ndr1_1 bnd_a536) &
% 7.18/6.75 bnd_c1_2 bnd_a536 bnd_a537) &
% 7.18/6.75 bnd_c2_2 bnd_a536 bnd_a537) &
% 7.18/6.75 ~ bnd_c7_2 bnd_a536 bnd_a537)) &
% 7.18/6.75 ((~ bnd_c10_0 |
% 7.18/6.75 (ALL X84.
% 7.18/6.75 bnd_ndr1_0 -->
% 7.18/6.75 (bnd_c10_1 X84 | ~ bnd_c2_1 X84) | ~ bnd_c8_1 X84)) |
% 7.18/6.75 (ALL X85.
% 7.18/6.75 bnd_ndr1_0 -->
% 7.18/6.75 (bnd_c9_1 X85 | ~ bnd_c3_1 X85) |
% 7.18/6.75 (ALL X86.
% 7.18/6.75 bnd_ndr1_1 X85 -->
% 7.18/6.75 (bnd_c10_2 X85 X86 | ~ bnd_c1_2 X85 X86) |
% 7.18/6.75 ~ bnd_c7_2 X85 X86)))) &
% 7.18/6.75 ((~ bnd_c10_0 |
% 7.18/6.75 (ALL X87.
% 7.18/6.75 bnd_ndr1_0 -->
% 7.18/6.75 (bnd_c3_1 X87 | ~ bnd_c8_1 X87) |
% 7.18/6.75 ((bnd_ndr1_1 X87 & bnd_c2_2 X87 bnd_a538) &
% 7.18/6.75 bnd_c5_2 X87 bnd_a538) &
% 7.18/6.75 ~ bnd_c1_2 X87 bnd_a538)) |
% 7.18/6.75 (bnd_ndr1_0 & bnd_c3_1 bnd_a539) & ~ bnd_c9_1 bnd_a539)) &
% 7.18/6.75 ((~ bnd_c10_0 |
% 7.18/6.75 ((bnd_ndr1_0 & ~ bnd_c2_1 bnd_a540) & ~ bnd_c8_1 bnd_a540) &
% 7.18/6.75 (ALL X88.
% 7.18/6.75 bnd_ndr1_1 bnd_a540 -->
% 7.18/6.75 (bnd_c5_2 bnd_a540 X88 | bnd_c8_2 bnd_a540 X88) |
% 7.18/6.75 ~ bnd_c6_2 bnd_a540 X88)) |
% 7.18/6.75 ((bnd_ndr1_0 & ~ bnd_c5_1 bnd_a541) & ~ bnd_c8_1 bnd_a541) &
% 7.18/6.75 (ALL X89.
% 7.18/6.75 bnd_ndr1_1 bnd_a541 -->
% 7.18/6.75 (bnd_c1_2 bnd_a541 X89 | bnd_c3_2 bnd_a541 X89) |
% 7.18/6.75 bnd_c9_2 bnd_a541 X89))) &
% 7.18/6.75 ((~ bnd_c2_0 | ~ bnd_c7_0) |
% 7.18/6.75 (ALL X90.
% 7.18/6.75 bnd_ndr1_0 -->
% 7.18/6.75 bnd_c3_1 X90 |
% 7.18/6.75 (ALL X91.
% 7.18/6.75 bnd_ndr1_1 X90 -->
% 7.18/6.75 (bnd_c10_2 X90 X91 | ~ bnd_c1_2 X90 X91) |
% 7.18/6.75 ~ bnd_c2_2 X90 X91)))) &
% 7.18/6.75 ((~ bnd_c2_0 |
% 7.18/6.75 (ALL X92. bnd_ndr1_0 --> (bnd_c3_1 X92 | bnd_c5_1 X92) | bnd_c7_1 X92)) |
% 7.18/6.75 (bnd_ndr1_0 & ~ bnd_c10_1 bnd_a542) &
% 7.18/6.75 (ALL X93.
% 7.18/6.75 bnd_ndr1_1 bnd_a542 -->
% 7.18/6.75 bnd_c3_2 bnd_a542 X93 | ~ bnd_c6_2 bnd_a542 X93))) &
% 7.18/6.75 ((~ bnd_c2_0 |
% 7.18/6.75 ((bnd_ndr1_0 & bnd_c1_1 bnd_a543) &
% 7.18/6.75 (ALL X94.
% 7.18/6.75 bnd_ndr1_1 bnd_a543 -->
% 7.18/6.75 (bnd_c10_2 bnd_a543 X94 | bnd_c3_2 bnd_a543 X94) |
% 7.18/6.75 ~ bnd_c9_2 bnd_a543 X94)) &
% 7.18/6.75 (ALL X95.
% 7.18/6.75 bnd_ndr1_1 bnd_a543 -->
% 7.18/6.75 (bnd_c8_2 bnd_a543 X95 | bnd_c9_2 bnd_a543 X95) |
% 7.18/6.75 ~ bnd_c5_2 bnd_a543 X95)) |
% 7.18/6.75 ((bnd_ndr1_0 & bnd_c2_1 bnd_a544) & bnd_c6_1 bnd_a544) &
% 7.18/6.75 ~ bnd_c1_1 bnd_a544)) &
% 7.18/6.75 ((~ bnd_c3_0 |
% 7.18/6.75 (ALL X96. bnd_ndr1_0 --> bnd_c1_1 X96 | ~ bnd_c9_1 X96)) |
% 7.18/6.75 (ALL X97.
% 7.18/6.75 bnd_ndr1_0 -->
% 7.18/6.75 (bnd_c10_1 X97 | bnd_c3_1 X97) |
% 7.18/6.75 (ALL X98.
% 7.18/6.75 bnd_ndr1_1 X97 -->
% 7.18/6.75 (bnd_c6_2 X97 X98 | ~ bnd_c4_2 X97 X98) | ~ bnd_c9_2 X97 X98)))) &
% 7.18/6.75 ((~ bnd_c3_0 |
% 7.18/6.75 (ALL X99.
% 7.18/6.75 bnd_ndr1_0 -->
% 7.18/6.75 (ALL X100.
% 7.18/6.75 bnd_ndr1_1 X99 -->
% 7.18/6.75 (~ bnd_c10_2 X99 X100 | ~ bnd_c2_2 X99 X100) | ~ bnd_c8_2 X99 X100) |
% 7.18/6.75 ((bnd_ndr1_1 X99 & bnd_c4_2 X99 bnd_a545) & bnd_c6_2 X99 bnd_a545) &
% 7.18/6.75 ~ bnd_c8_2 X99 bnd_a545)) |
% 7.18/6.75 ((bnd_ndr1_0 & bnd_c3_1 bnd_a546) &
% 7.18/6.75 (ALL X101.
% 7.18/6.75 bnd_ndr1_1 bnd_a546 -->
% 7.18/6.75 (bnd_c1_2 bnd_a546 X101 | bnd_c3_2 bnd_a546 X101) |
% 7.18/6.75 bnd_c7_2 bnd_a546 X101)) &
% 7.18/6.75 (ALL X102.
% 7.18/6.75 bnd_ndr1_1 bnd_a546 -->
% 7.18/6.75 ~ bnd_c2_2 bnd_a546 X102 | ~ bnd_c3_2 bnd_a546 X102))) &
% 7.18/6.75 ((~ bnd_c3_0 |
% 7.18/6.75 (bnd_ndr1_0 & ~ bnd_c1_1 bnd_a547) &
% 7.18/6.75 ~ bnd_c8_1 bnd_a547) |
% 7.18/6.75 (((((bnd_ndr1_0 &
% 7.18/6.75 (ALL X103.
% 7.18/6.75 bnd_ndr1_1 bnd_a548 -->
% 7.18/6.75 (bnd_c4_2 bnd_a548 X103 | bnd_c5_2 bnd_a548 X103) |
% 7.18/6.75 bnd_c6_2 bnd_a548 X103)) &
% 7.18/6.75 (ALL X104.
% 7.18/6.75 bnd_ndr1_1 bnd_a548 -->
% 7.18/6.75 (bnd_c4_2 bnd_a548 X104 | bnd_c8_2 bnd_a548 X104) |
% 7.18/6.75 ~ bnd_c7_2 bnd_a548 X104)) &
% 7.18/6.75 bnd_ndr1_1 bnd_a548) &
% 7.18/6.75 bnd_c6_2 bnd_a548 bnd_a549) &
% 7.18/6.75 bnd_c9_2 bnd_a548 bnd_a549) &
% 7.18/6.75 ~ bnd_c5_2 bnd_a548 bnd_a549)) &
% 7.18/6.75 (~ bnd_c4_0 | ~ bnd_c9_0)) &
% 7.18/6.75 ((~ bnd_c4_0 | ~ bnd_c9_0) |
% 7.18/6.75 (ALL X105.
% 7.18/6.75 bnd_ndr1_0 -->
% 7.18/6.75 bnd_c4_1 X105 | bnd_c8_1 X105))) &
% 7.18/6.75 (~ bnd_c4_0 |
% 7.18/6.75 (ALL X106.
% 7.18/6.75 bnd_ndr1_0 -->
% 7.18/6.75 (bnd_c3_1 X106 |
% 7.18/6.75 (ALL X107.
% 7.18/6.75 bnd_ndr1_1 X106 -->
% 7.18/6.75 (bnd_c5_2 X106 X107 | ~ bnd_c10_2 X106 X107) | ~ bnd_c9_2 X106 X107)) |
% 7.18/6.75 ((bnd_ndr1_1 X106 &
% 7.18/6.75 ~ bnd_c10_2 X106 bnd_a550) &
% 7.18/6.75 ~ bnd_c5_2 X106 bnd_a550) &
% 7.18/6.75 ~ bnd_c7_2 X106 bnd_a550))) &
% 7.18/6.75 ((~ bnd_c4_0 |
% 7.18/6.75 (ALL X108.
% 7.18/6.75 bnd_ndr1_0 -->
% 7.18/6.75 (~ bnd_c10_1 X108 | ~ bnd_c3_1 X108) |
% 7.18/6.75 (ALL X109.
% 7.18/6.75 bnd_ndr1_1 X108 --> bnd_c1_2 X108 X109 | bnd_c5_2 X108 X109))) |
% 7.18/6.75 (ALL X110.
% 7.18/6.75 bnd_ndr1_0 -->
% 7.18/6.75 (~ bnd_c8_1 X110 |
% 7.18/6.75 (ALL X111.
% 7.18/6.75 bnd_ndr1_1 X110 --> bnd_c9_2 X110 X111 | ~ bnd_c6_2 X110 X111)) |
% 7.18/6.75 (ALL X112.
% 7.18/6.75 bnd_ndr1_1 X110 -->
% 7.18/6.75 (~ bnd_c1_2 X110 X112 | ~ bnd_c2_2 X110 X112) | ~ bnd_c8_2 X110 X112)))) &
% 7.18/6.75 (~ bnd_c5_0 |
% 7.18/6.75 (ALL X113.
% 7.18/6.75 bnd_ndr1_0 -->
% 7.18/6.75 ((ALL X114.
% 7.18/6.75 bnd_ndr1_1 X113 -->
% 7.18/6.75 (bnd_c5_2 X113 X114 | bnd_c9_2 X113 X114) | ~ bnd_c2_2 X113 X114) |
% 7.18/6.75 ((bnd_ndr1_1 X113 &
% 7.18/6.75 bnd_c1_2 X113 bnd_a551) &
% 7.18/6.75 bnd_c2_2 X113 bnd_a551) &
% 7.18/6.75 ~ bnd_c7_2 X113 bnd_a551) |
% 7.18/6.75 ((bnd_ndr1_1 X113 &
% 7.18/6.75 bnd_c3_2 X113 bnd_a552) &
% 7.18/6.75 ~ bnd_c10_2 X113 bnd_a552) &
% 7.18/6.75 ~ bnd_c4_2 X113 bnd_a552))) &
% 7.18/6.75 ((~ bnd_c5_0 | ~ bnd_c9_0) |
% 7.18/6.75 (ALL X115.
% 7.18/6.75 bnd_ndr1_0 -->
% 7.18/6.75 (bnd_c6_1 X115 | bnd_c7_1 X115) |
% 7.18/6.75 ~ bnd_c9_1 X115))) &
% 7.18/6.75 ((~ bnd_c5_0 | ~ bnd_c9_0) |
% 7.18/6.75 (((((bnd_ndr1_0 & bnd_c3_1 bnd_a553) &
% 7.18/6.75 bnd_c5_1 bnd_a553) &
% 7.18/6.75 bnd_ndr1_1 bnd_a553) &
% 7.18/6.75 bnd_c1_2 bnd_a553 bnd_a554) &
% 7.18/6.75 bnd_c2_2 bnd_a553 bnd_a554) &
% 7.18/6.75 ~ bnd_c3_2 bnd_a553 bnd_a554)) &
% 7.18/6.75 ((~ bnd_c5_0 |
% 7.18/6.75 (ALL X116.
% 7.18/6.75 bnd_ndr1_0 -->
% 7.18/6.75 (bnd_c1_1 X116 | ~ bnd_c7_1 X116) |
% 7.18/6.75 ((bnd_ndr1_1 X116 &
% 7.18/6.75 bnd_c1_2 X116 bnd_a555) &
% 7.18/6.75 ~ bnd_c2_2 X116 bnd_a555) &
% 7.18/6.75 ~ bnd_c6_2 X116 bnd_a555)) |
% 7.18/6.75 (bnd_ndr1_0 &
% 7.18/6.75 (ALL X117.
% 7.18/6.75 bnd_ndr1_1 bnd_a556 -->
% 7.18/6.75 (bnd_c1_2 bnd_a556 X117 |
% 7.18/6.75 bnd_c5_2 bnd_a556 X117) |
% 7.18/6.75 ~ bnd_c6_2 bnd_a556 X117)) &
% 7.18/6.75 (ALL X118.
% 7.18/6.75 bnd_ndr1_1 bnd_a556 -->
% 7.18/6.75 (bnd_c10_2 bnd_a556 X118 |
% 7.18/6.75 ~ bnd_c6_2 bnd_a556 X118) |
% 7.18/6.75 ~ bnd_c8_2 bnd_a556 X118))) &
% 7.18/6.75 ((~ bnd_c5_0 |
% 7.18/6.75 (ALL X119.
% 7.18/6.75 bnd_ndr1_0 -->
% 7.18/6.75 (bnd_c2_1 X119 | ~ bnd_c8_1 X119) |
% 7.18/6.75 ((bnd_ndr1_1 X119 &
% 7.18/6.75 bnd_c10_2 X119 bnd_a557) &
% 7.18/6.75 bnd_c5_2 X119 bnd_a557) &
% 7.18/6.75 ~ bnd_c4_2 X119 bnd_a557)) |
% 7.18/6.75 ((bnd_ndr1_0 & bnd_c4_1 bnd_a558) &
% 7.18/6.75 ~ bnd_c9_1 bnd_a558) &
% 7.18/6.75 (ALL X120.
% 7.18/6.75 bnd_ndr1_1 bnd_a558 -->
% 7.18/6.75 (bnd_c4_2 bnd_a558 X120 |
% 7.18/6.75 bnd_c9_2 bnd_a558 X120) |
% 7.18/6.75 ~ bnd_c3_2 bnd_a558 X120))) &
% 7.18/6.75 ((~ bnd_c5_0 |
% 7.18/6.75 (ALL X121.
% 7.18/6.75 bnd_ndr1_0 -->
% 7.18/6.75 (bnd_c7_1 X121 |
% 7.18/6.75 (ALL X122.
% 7.18/6.75 bnd_ndr1_1 X121 -->
% 7.18/6.75 bnd_c10_2 X121 X122 |
% 7.18/6.75 ~ bnd_c5_2 X121 X122)) |
% 7.18/6.75 ((bnd_ndr1_1 X121 & bnd_c6_2 X121 bnd_a559) &
% 7.18/6.75 bnd_c8_2 X121 bnd_a559) &
% 7.18/6.76 ~ bnd_c2_2 X121 bnd_a559)) |
% 7.18/6.76 (ALL X123.
% 7.18/6.76 bnd_ndr1_0 -->
% 7.18/6.76 (~ bnd_c5_1 X123 |
% 7.18/6.76 ((bnd_ndr1_1 X123 & bnd_c2_2 X123 bnd_a560) &
% 7.18/6.76 bnd_c5_2 X123 bnd_a560) &
% 7.18/6.76 bnd_c6_2 X123 bnd_a560) |
% 7.18/6.76 ((bnd_ndr1_1 X123 & ~ bnd_c1_2 X123 bnd_a561) &
% 7.18/6.76 ~ bnd_c8_2 X123 bnd_a561) &
% 7.18/6.76 ~ bnd_c9_2 X123 bnd_a561))) &
% 7.18/6.76 ((~ bnd_c5_0 |
% 7.18/6.76 (ALL X124.
% 7.18/6.76 bnd_ndr1_0 -->
% 7.18/6.76 (bnd_c8_1 X124 | ~ bnd_c3_1 X124) |
% 7.18/6.76 (ALL X125.
% 7.18/6.76 bnd_ndr1_1 X124 -->
% 7.18/6.76 (bnd_c4_2 X124 X125 | bnd_c6_2 X124 X125) |
% 7.18/6.76 bnd_c8_2 X124 X125))) |
% 7.18/6.76 ((bnd_ndr1_0 & bnd_c7_1 bnd_a562) &
% 7.18/6.76 ~ bnd_c10_1 bnd_a562) &
% 7.18/6.76 (ALL X126.
% 7.18/6.76 bnd_ndr1_1 bnd_a562 -->
% 7.18/6.76 (bnd_c2_2 bnd_a562 X126 |
% 7.18/6.76 ~ bnd_c10_2 bnd_a562 X126) |
% 7.18/6.76 ~ bnd_c8_2 bnd_a562 X126))) &
% 7.18/6.76 ((~ bnd_c5_0 |
% 7.18/6.76 (ALL X127.
% 7.18/6.76 bnd_ndr1_0 -->
% 7.18/6.76 (~ bnd_c5_1 X127 |
% 7.18/6.76 (ALL X128.
% 7.18/6.76 bnd_ndr1_1 X127 -->
% 7.18/6.76 (bnd_c10_2 X127 X128 |
% 7.18/6.76 ~ bnd_c5_2 X127 X128) |
% 7.18/6.76 ~ bnd_c6_2 X127 X128)) |
% 7.18/6.76 (ALL X129.
% 7.18/6.76 bnd_ndr1_1 X127 -->
% 7.18/6.76 bnd_c5_2 X127 X129 |
% 7.18/6.76 ~ bnd_c4_2 X127 X129))) |
% 7.18/6.76 ((bnd_ndr1_0 & bnd_c4_1 bnd_a563) &
% 7.18/6.76 ~ bnd_c8_1 bnd_a563) &
% 7.18/6.76 (ALL X130.
% 7.18/6.76 bnd_ndr1_1 bnd_a563 -->
% 7.18/6.76 (bnd_c6_2 bnd_a563 X130 |
% 7.18/6.76 ~ bnd_c10_2 bnd_a563 X130) |
% 7.18/6.76 ~ bnd_c2_2 bnd_a563 X130))) &
% 7.18/6.76 (~ bnd_c5_0 |
% 7.18/6.76 ((((bnd_ndr1_0 & bnd_c10_1 bnd_a564) &
% 7.18/6.76 ~ bnd_c1_1 bnd_a564) &
% 7.18/6.76 bnd_ndr1_1 bnd_a564) &
% 7.18/6.76 bnd_c10_2 bnd_a564 bnd_a565) &
% 7.18/6.76 bnd_c4_2 bnd_a564 bnd_a565)) &
% 7.18/6.76 ((~ bnd_c5_0 |
% 7.18/6.76 ((((bnd_ndr1_0 & bnd_c4_1 bnd_a566) &
% 7.18/6.76 (ALL X131.
% 7.18/6.76 bnd_ndr1_1 bnd_a566 -->
% 7.18/6.76 (~ bnd_c10_2 bnd_a566 X131 |
% 7.18/6.76 ~ bnd_c6_2 bnd_a566 X131) |
% 7.18/6.76 ~ bnd_c8_2 bnd_a566 X131)) &
% 7.18/6.76 bnd_ndr1_1 bnd_a566) &
% 7.18/6.76 bnd_c8_2 bnd_a566 bnd_a567) &
% 7.18/6.76 ~ bnd_c7_2 bnd_a566 bnd_a567) |
% 7.18/6.76 ((((((((bnd_ndr1_0 & ~ bnd_c7_1 bnd_a568) &
% 7.18/6.76 bnd_ndr1_1 bnd_a568) &
% 7.18/6.76 bnd_c10_2 bnd_a568 bnd_a569) &
% 7.18/6.76 bnd_c3_2 bnd_a568 bnd_a569) &
% 7.18/6.76 bnd_c9_2 bnd_a568 bnd_a569) &
% 7.18/6.76 bnd_ndr1_1 bnd_a568) &
% 7.18/6.76 bnd_c5_2 bnd_a568 bnd_a570) &
% 7.18/6.76 bnd_c8_2 bnd_a568 bnd_a570) &
% 7.18/6.76 ~ bnd_c7_2 bnd_a568 bnd_a570)) &
% 7.18/6.76 (((bnd_ndr1_0 & bnd_c1_1 bnd_a571) & bnd_c6_1 bnd_a571) &
% 7.18/6.76 bnd_c7_1 bnd_a571 |
% 7.18/6.76 (((((bnd_ndr1_0 & ~ bnd_c1_1 bnd_a572) &
% 7.18/6.76 (ALL X132.
% 7.18/6.76 bnd_ndr1_1 bnd_a572 -->
% 7.18/6.76 (bnd_c9_2 bnd_a572 X132 |
% 7.18/6.76 ~ bnd_c2_2 bnd_a572 X132) |
% 7.18/6.76 ~ bnd_c7_2 bnd_a572 X132)) &
% 7.18/6.76 bnd_ndr1_1 bnd_a572) &
% 7.18/6.76 bnd_c8_2 bnd_a572 bnd_a573) &
% 7.18/6.76 ~ bnd_c1_2 bnd_a572 bnd_a573) &
% 7.18/6.76 ~ bnd_c10_2 bnd_a572 bnd_a573)) &
% 7.18/6.76 (~ bnd_c7_0 |
% 7.18/6.76 ((bnd_ndr1_0 & bnd_c1_1 bnd_a574) &
% 7.18/6.76 ~ bnd_c10_1 bnd_a574) &
% 7.18/6.76 ~ bnd_c3_1 bnd_a574)) &
% 7.18/6.76 (~ bnd_c9_0 |
% 7.18/6.76 ((bnd_ndr1_0 &
% 7.18/6.76 (ALL X133.
% 7.18/6.76 bnd_ndr1_1 bnd_a575 -->
% 7.18/6.76 (bnd_c1_2 bnd_a575 X133 | bnd_c10_2 bnd_a575 X133) |
% 7.18/6.76 bnd_c7_2 bnd_a575 X133)) &
% 7.18/6.76 (ALL X134.
% 7.18/6.76 bnd_ndr1_1 bnd_a575 -->
% 7.18/6.76 (bnd_c1_2 bnd_a575 X134 | ~ bnd_c6_2 bnd_a575 X134) |
% 7.18/6.76 ~ bnd_c9_2 bnd_a575 X134)) &
% 7.18/6.76 (ALL X135.
% 7.18/6.76 bnd_ndr1_1 bnd_a575 -->
% 7.18/6.76 ~ bnd_c5_2 bnd_a575 X135 |
% 7.18/6.76 ~ bnd_c7_2 bnd_a575 X135))) &
% 7.18/6.76 (((ALL X136.
% 7.18/6.76 bnd_ndr1_0 -->
% 7.18/6.76 (bnd_c1_1 X136 | bnd_c2_1 X136) | ~ bnd_c7_1 X136) |
% 7.18/6.76 (ALL X137.
% 7.18/6.76 bnd_ndr1_0 -->
% 7.18/6.76 (bnd_c8_1 X137 | ~ bnd_c1_1 X137) |
% 7.18/6.76 ((bnd_ndr1_1 X137 & bnd_c5_2 X137 bnd_a576) &
% 7.18/6.76 ~ bnd_c6_2 X137 bnd_a576) &
% 7.18/6.76 ~ bnd_c7_2 X137 bnd_a576)) |
% 7.18/6.76 (ALL X138.
% 7.18/6.76 bnd_ndr1_0 -->
% 7.18/6.76 ((ALL X139.
% 7.18/6.76 bnd_ndr1_1 X138 -->
% 7.18/6.76 (bnd_c9_2 X138 X139 | ~ bnd_c1_2 X138 X139) |
% 7.18/6.76 ~ bnd_c3_2 X138 X139) |
% 7.18/6.76 (ALL X140.
% 7.18/6.76 bnd_ndr1_1 X138 -->
% 7.18/6.76 (~ bnd_c4_2 X138 X140 | ~ bnd_c8_2 X138 X140) |
% 7.18/6.76 ~ bnd_c9_2 X138 X140)) |
% 7.18/6.76 ((bnd_ndr1_1 X138 & bnd_c3_2 X138 bnd_a577) &
% 7.18/6.76 bnd_c9_2 X138 bnd_a577) &
% 7.18/6.76 ~ bnd_c8_2 X138 bnd_a577))) &
% 7.18/6.76 (((ALL X141.
% 7.18/6.76 bnd_ndr1_0 -->
% 7.18/6.76 (bnd_c1_1 X141 | bnd_c6_1 X141) |
% 7.18/6.76 ((bnd_ndr1_1 X141 & bnd_c4_2 X141 bnd_a578) &
% 7.18/6.76 bnd_c5_2 X141 bnd_a578) &
% 7.18/6.76 bnd_c9_2 X141 bnd_a578) |
% 7.18/6.76 (ALL X142.
% 7.18/6.76 bnd_ndr1_0 -->
% 7.18/6.76 (~ bnd_c3_1 X142 |
% 7.18/6.76 (ALL X143.
% 7.18/6.76 bnd_ndr1_1 X142 --> ~ bnd_c10_2 X142 X143)) |
% 7.18/6.76 (ALL X144.
% 7.18/6.76 bnd_ndr1_1 X142 -->
% 7.18/6.76 (~ bnd_c1_2 X142 X144 | ~ bnd_c10_2 X142 X144) |
% 7.18/6.76 ~ bnd_c5_2 X142 X144))) |
% 7.18/6.76 (ALL X145.
% 7.18/6.76 bnd_ndr1_0 -->
% 7.18/6.76 (~ bnd_c4_1 X145 |
% 7.18/6.76 (ALL X146.
% 7.18/6.76 bnd_ndr1_1 X145 -->
% 7.18/6.76 (bnd_c8_2 X145 X146 | ~ bnd_c10_2 X145 X146) |
% 7.18/6.76 ~ bnd_c4_2 X145 X146)) |
% 7.18/6.76 (ALL X147.
% 7.18/6.76 bnd_ndr1_1 X145 -->
% 7.18/6.76 (~ bnd_c5_2 X145 X147 | ~ bnd_c6_2 X145 X147) |
% 7.18/6.76 ~ bnd_c8_2 X145 X147)))) &
% 7.18/6.76 (((ALL X148.
% 7.18/6.76 bnd_ndr1_0 -->
% 7.18/6.76 (bnd_c10_1 X148 | ~ bnd_c3_1 X148) | ~ bnd_c5_1 X148) |
% 7.18/6.76 (((((bnd_ndr1_0 & bnd_c7_1 bnd_a579) &
% 7.18/6.76 ~ bnd_c1_1 bnd_a579) &
% 7.18/6.76 bnd_ndr1_1 bnd_a579) &
% 7.18/6.76 ~ bnd_c1_2 bnd_a579 bnd_a580) &
% 7.18/6.76 ~ bnd_c3_2 bnd_a579 bnd_a580) &
% 7.18/6.76 ~ bnd_c9_2 bnd_a579 bnd_a580) |
% 7.18/6.76 ((((bnd_ndr1_0 & ~ bnd_c2_1 bnd_a581) &
% 7.18/6.76 (ALL X149.
% 7.18/6.76 bnd_ndr1_1 bnd_a581 -->
% 7.18/6.76 (bnd_c1_2 bnd_a581 X149 | ~ bnd_c4_2 bnd_a581 X149) |
% 7.18/6.76 ~ bnd_c8_2 bnd_a581 X149)) &
% 7.18/6.76 bnd_ndr1_1 bnd_a581) &
% 7.18/6.76 bnd_c4_2 bnd_a581 bnd_a582) &
% 7.18/6.76 ~ bnd_c10_2 bnd_a581 bnd_a582)) &
% 7.18/6.76 (((ALL X150.
% 7.18/6.76 bnd_ndr1_0 -->
% 7.18/6.76 bnd_c10_1 X150 |
% 7.18/6.76 (ALL X151.
% 7.18/6.76 bnd_ndr1_1 X150 -->
% 7.18/6.76 (bnd_c10_2 X150 X151 | bnd_c2_2 X150 X151) |
% 7.18/6.76 bnd_c8_2 X150 X151)) |
% 7.18/6.76 (ALL X152.
% 7.18/6.76 bnd_ndr1_0 -->
% 7.18/6.76 (~ bnd_c3_1 X152 |
% 7.18/6.76 (ALL X153.
% 7.18/6.76 bnd_ndr1_1 X152 -->
% 7.18/6.76 (bnd_c5_2 X152 X153 | bnd_c6_2 X152 X153) |
% 7.18/6.76 ~ bnd_c7_2 X152 X153)) |
% 7.18/6.76 ((bnd_ndr1_1 X152 & bnd_c10_2 X152 bnd_a583) &
% 7.18/6.76 bnd_c4_2 X152 bnd_a583) &
% 7.18/6.76 ~ bnd_c6_2 X152 bnd_a583)) |
% 7.18/6.76 (((((bnd_ndr1_0 & ~ bnd_c8_1 bnd_a584) &
% 7.18/6.76 (ALL X154.
% 7.18/6.76 bnd_ndr1_1 bnd_a584 -->
% 7.18/6.76 (bnd_c2_2 bnd_a584 X154 | bnd_c9_2 bnd_a584 X154) |
% 7.18/6.76 ~ bnd_c7_2 bnd_a584 X154)) &
% 7.18/6.76 bnd_ndr1_1 bnd_a584) &
% 7.18/6.76 bnd_c7_2 bnd_a584 bnd_a585) &
% 7.18/6.76 ~ bnd_c2_2 bnd_a584 bnd_a585) &
% 7.18/6.76 ~ bnd_c4_2 bnd_a584 bnd_a585)) &
% 7.18/6.76 (((ALL X155.
% 7.18/6.76 bnd_ndr1_0 -->
% 7.18/6.76 (bnd_c3_1 X155 | ~ bnd_c1_1 X155) | ~ bnd_c2_1 X155) |
% 7.18/6.76 (((((bnd_ndr1_0 & bnd_c1_1 bnd_a586) & ~ bnd_c7_1 bnd_a586) &
% 7.18/6.76 bnd_ndr1_1 bnd_a586) &
% 7.18/6.76 bnd_c9_2 bnd_a586 bnd_a587) &
% 7.18/6.76 ~ bnd_c3_2 bnd_a586 bnd_a587) &
% 7.18/6.76 ~ bnd_c8_2 bnd_a586 bnd_a587) |
% 7.18/6.76 (((((bnd_ndr1_0 & ~ bnd_c1_1 bnd_a588) & ~ bnd_c3_1 bnd_a588) &
% 7.18/6.76 bnd_ndr1_1 bnd_a588) &
% 7.18/6.76 bnd_c6_2 bnd_a588 bnd_a589) &
% 7.18/6.76 ~ bnd_c1_2 bnd_a588 bnd_a589) &
% 7.18/6.76 ~ bnd_c3_2 bnd_a588 bnd_a589)) &
% 7.18/6.76 ((ALL X156.
% 7.18/6.76 bnd_ndr1_0 -->
% 7.18/6.76 (bnd_c3_1 X156 |
% 7.18/6.76 (ALL X157.
% 7.18/6.76 bnd_ndr1_1 X156 -->
% 7.18/6.76 (bnd_c3_2 X156 X157 | ~ bnd_c5_2 X156 X157) |
% 7.18/6.76 ~ bnd_c9_2 X156 X157)) |
% 7.18/6.76 (bnd_ndr1_1 X156 & ~ bnd_c10_2 X156 bnd_a590) &
% 7.18/6.76 ~ bnd_c9_2 X156 bnd_a590) |
% 7.18/6.76 (((((bnd_ndr1_0 & bnd_c6_1 bnd_a591) & bnd_c9_1 bnd_a591) &
% 7.18/6.76 bnd_ndr1_1 bnd_a591) &
% 7.18/6.76 bnd_c4_2 bnd_a591 bnd_a592) &
% 7.18/6.76 ~ bnd_c1_2 bnd_a591 bnd_a592) &
% 7.18/6.76 ~ bnd_c7_2 bnd_a591 bnd_a592)) &
% 7.18/6.76 (((ALL X158.
% 7.18/6.76 bnd_ndr1_0 -->
% 7.18/6.76 (bnd_c4_1 X158 |
% 7.18/6.76 ((bnd_ndr1_1 X158 & bnd_c5_2 X158 bnd_a593) &
% 7.18/6.76 ~ bnd_c6_2 X158 bnd_a593) &
% 7.18/6.76 ~ bnd_c7_2 X158 bnd_a593) |
% 7.18/6.76 (bnd_ndr1_1 X158 & bnd_c9_2 X158 bnd_a594) &
% 7.18/6.76 ~ bnd_c10_2 X158 bnd_a594) |
% 7.18/6.76 (ALL X159.
% 7.18/6.76 bnd_ndr1_0 -->
% 7.18/6.76 (~ bnd_c5_1 X159 | ~ bnd_c8_1 X159) |
% 7.18/6.76 (ALL X160.
% 7.18/6.76 bnd_ndr1_1 X159 -->
% 7.18/6.76 bnd_c1_2 X159 X160 | ~ bnd_c8_2 X159 X160))) |
% 7.18/6.76 ((bnd_ndr1_0 & ~ bnd_c3_1 bnd_a595) & ~ bnd_c9_1 bnd_a595) &
% 7.18/6.76 (ALL X161.
% 7.18/6.76 bnd_ndr1_1 bnd_a595 -->
% 7.18/6.76 bnd_c1_2 bnd_a595 X161 | bnd_c9_2 bnd_a595 X161))) &
% 7.18/6.76 ((ALL X162.
% 7.18/6.76 bnd_ndr1_0 -->
% 7.18/6.76 (bnd_c5_1 X162 | bnd_c8_1 X162) |
% 7.18/6.76 (bnd_ndr1_1 X162 & ~ bnd_c2_2 X162 bnd_a596) &
% 7.18/6.76 ~ bnd_c5_2 X162 bnd_a596) |
% 7.18/6.76 (ALL X163.
% 7.18/6.76 bnd_ndr1_0 -->
% 7.18/6.76 ~ bnd_c7_1 X163 |
% 7.18/6.76 ((bnd_ndr1_1 X163 & bnd_c10_2 X163 bnd_a597) &
% 7.18/6.76 ~ bnd_c3_2 X163 bnd_a597) &
% 7.18/6.76 ~ bnd_c5_2 X163 bnd_a597))) &
% 7.18/6.76 (((ALL X164.
% 7.18/6.76 bnd_ndr1_0 -->
% 7.18/6.76 (~ bnd_c10_1 X164 |
% 7.18/6.76 ((bnd_ndr1_1 X164 & bnd_c2_2 X164 bnd_a598) &
% 7.18/6.76 ~ bnd_c10_2 X164 bnd_a598) &
% 7.18/6.76 ~ bnd_c6_2 X164 bnd_a598) |
% 7.18/6.76 ((bnd_ndr1_1 X164 & bnd_c6_2 X164 bnd_a599) &
% 7.18/6.76 ~ bnd_c1_2 X164 bnd_a599) &
% 7.18/6.76 ~ bnd_c10_2 X164 bnd_a599) |
% 7.18/6.76 (ALL X165.
% 7.18/6.76 bnd_ndr1_0 -->
% 7.18/6.76 ((ALL X166.
% 7.18/6.76 bnd_ndr1_1 X165 -->
% 7.18/6.76 (bnd_c10_2 X165 X166 | ~ bnd_c3_2 X165 X166) |
% 7.18/6.76 ~ bnd_c6_2 X165 X166) |
% 7.18/6.76 (ALL X167.
% 7.18/6.76 bnd_ndr1_1 X165 -->
% 7.18/6.76 (bnd_c9_2 X165 X167 | ~ bnd_c4_2 X165 X167) |
% 7.18/6.76 ~ bnd_c8_2 X165 X167)) |
% 7.18/6.76 (ALL X168.
% 7.18/6.76 bnd_ndr1_1 X165 -->
% 7.18/6.76 (~ bnd_c5_2 X165 X168 | ~ bnd_c8_2 X165 X168) |
% 7.18/6.76 ~ bnd_c9_2 X165 X168))) |
% 7.18/6.76 (bnd_ndr1_0 & bnd_c10_1 bnd_a600) &
% 7.18/6.76 (ALL X169.
% 7.18/6.76 bnd_ndr1_1 bnd_a600 -->
% 7.18/6.76 bnd_c10_2 bnd_a600 X169 | ~ bnd_c1_2 bnd_a600 X169))) &
% 7.18/6.76 (((ALL X170.
% 7.18/6.76 bnd_ndr1_0 -->
% 7.18/6.76 (~ bnd_c4_1 X170 |
% 7.18/6.76 ((bnd_ndr1_1 X170 & bnd_c1_2 X170 bnd_a601) &
% 7.18/6.76 ~ bnd_c2_2 X170 bnd_a601) &
% 7.18/6.76 ~ bnd_c4_2 X170 bnd_a601) |
% 7.18/6.76 ((bnd_ndr1_1 X170 & bnd_c6_2 X170 bnd_a602) &
% 7.18/6.76 bnd_c7_2 X170 bnd_a602) &
% 7.18/6.76 bnd_c9_2 X170 bnd_a602) |
% 7.18/6.76 ((bnd_ndr1_0 & ~ bnd_c10_1 bnd_a603) & ~ bnd_c6_1 bnd_a603) &
% 7.18/6.76 ~ bnd_c8_1 bnd_a603) |
% 7.18/6.76 ((((((((bnd_ndr1_0 & ~ bnd_c6_1 bnd_a604) & bnd_ndr1_1 bnd_a604) &
% 7.18/6.76 bnd_c7_2 bnd_a604 bnd_a605) &
% 7.18/6.76 ~ bnd_c3_2 bnd_a604 bnd_a605) &
% 7.18/6.76 ~ bnd_c4_2 bnd_a604 bnd_a605) &
% 7.18/6.76 bnd_ndr1_1 bnd_a604) &
% 7.18/6.76 bnd_c8_2 bnd_a604 bnd_a606) &
% 7.18/6.76 ~ bnd_c2_2 bnd_a604 bnd_a606) &
% 7.18/6.76 ~ bnd_c3_2 bnd_a604 bnd_a606)) &
% 7.18/6.76 (((ALL X171.
% 7.18/6.76 bnd_ndr1_0 -->
% 7.18/6.76 (~ bnd_c9_1 X171 |
% 7.18/6.76 (ALL X172.
% 7.18/6.76 bnd_ndr1_1 X171 -->
% 7.18/6.76 (bnd_c2_2 X171 X172 | bnd_c4_2 X171 X172) |
% 7.18/6.76 bnd_c9_2 X171 X172)) |
% 7.18/6.76 ((bnd_ndr1_1 X171 & ~ bnd_c2_2 X171 bnd_a607) &
% 7.18/6.76 ~ bnd_c3_2 X171 bnd_a607) &
% 7.18/6.76 ~ bnd_c4_2 X171 bnd_a607) |
% 7.18/6.76 (bnd_ndr1_0 & bnd_c4_1 bnd_a608) &
% 7.18/6.76 (ALL X173.
% 7.18/6.76 bnd_ndr1_1 bnd_a608 -->
% 7.18/6.76 (bnd_c2_2 bnd_a608 X173 | ~ bnd_c10_2 bnd_a608 X173) |
% 7.18/6.76 ~ bnd_c7_2 bnd_a608 X173)) |
% 7.18/6.76 ((bnd_ndr1_0 & ~ bnd_c3_1 bnd_a609) &
% 7.18/6.76 (ALL X174.
% 7.18/6.76 bnd_ndr1_1 bnd_a609 -->
% 7.18/6.76 (bnd_c10_2 bnd_a609 X174 | bnd_c7_2 bnd_a609 X174) |
% 7.18/6.76 bnd_c8_2 bnd_a609 X174)) &
% 7.18/6.76 (ALL X175.
% 7.18/6.76 bnd_ndr1_1 bnd_a609 -->
% 7.18/6.76 bnd_c4_2 bnd_a609 X175 | ~ bnd_c8_2 bnd_a609 X175))) &
% 7.18/6.76 (bnd_ndr1_0 & bnd_c1_1 bnd_a610 |
% 7.18/6.76 (((((bnd_ndr1_0 & bnd_c6_1 bnd_a611) &
% 7.18/6.76 (ALL X176.
% 7.18/6.76 bnd_ndr1_1 bnd_a611 -->
% 7.18/6.76 (bnd_c5_2 bnd_a611 X176 | ~ bnd_c6_2 bnd_a611 X176) |
% 7.18/6.76 ~ bnd_c9_2 bnd_a611 X176)) &
% 7.18/6.76 bnd_ndr1_1 bnd_a611) &
% 7.18/6.76 bnd_c1_2 bnd_a611 bnd_a612) &
% 7.18/6.76 ~ bnd_c5_2 bnd_a611 bnd_a612) &
% 7.18/6.76 ~ bnd_c7_2 bnd_a611 bnd_a612)) &
% 7.18/6.76 ((((((bnd_ndr1_0 & bnd_c3_1 bnd_a613) & bnd_c8_1 bnd_a613) &
% 7.18/6.76 bnd_ndr1_1 bnd_a613) &
% 7.18/6.76 ~ bnd_c2_2 bnd_a613 bnd_a614) &
% 7.18/6.76 ~ bnd_c4_2 bnd_a613 bnd_a614) &
% 7.18/6.76 ~ bnd_c7_2 bnd_a613 bnd_a614 |
% 7.18/6.76 ((bnd_ndr1_0 & bnd_c7_1 bnd_a615) & ~ bnd_c1_1 bnd_a615) &
% 7.18/6.76 (ALL X177.
% 7.18/6.76 bnd_ndr1_1 bnd_a615 -->
% 7.18/6.76 (~ bnd_c4_2 bnd_a615 X177 | ~ bnd_c7_2 bnd_a615 X177) |
% 7.18/6.76 ~ bnd_c9_2 bnd_a615 X177))) &
% 7.18/6.76 ((((bnd_ndr1_0 & bnd_c6_1 bnd_a616) & ~ bnd_c1_1 bnd_a616) &
% 7.18/6.76 (ALL X178.
% 7.18/6.76 bnd_ndr1_1 bnd_a616 -->
% 7.18/6.76 (bnd_c10_2 bnd_a616 X178 | bnd_c3_2 bnd_a616 X178) |
% 7.18/6.76 ~ bnd_c6_2 bnd_a616 X178) |
% 7.18/6.76 (((((bnd_ndr1_0 & bnd_c6_1 bnd_a617) &
% 7.18/6.76 (ALL X179.
% 7.18/6.76 bnd_ndr1_1 bnd_a617 -->
% 7.18/6.76 (~ bnd_c10_2 bnd_a617 X179 | ~ bnd_c4_2 bnd_a617 X179) |
% 7.18/6.76 ~ bnd_c5_2 bnd_a617 X179)) &
% 7.18/6.76 bnd_ndr1_1 bnd_a617) &
% 7.18/6.76 bnd_c10_2 bnd_a617 bnd_a618) &
% 7.18/6.76 ~ bnd_c8_2 bnd_a617 bnd_a618) &
% 7.18/6.76 ~ bnd_c9_2 bnd_a617 bnd_a618) |
% 7.18/6.76 ((bnd_ndr1_0 & bnd_c8_1 bnd_a619) & ~ bnd_c3_1 bnd_a619) &
% 7.18/6.76 (ALL X180.
% 7.18/6.76 bnd_ndr1_1 bnd_a619 -->
% 7.18/6.76 (bnd_c3_2 bnd_a619 X180 | ~ bnd_c4_2 bnd_a619 X180) |
% 7.18/6.76 ~ bnd_c7_2 bnd_a619 X180)))
% 17.60/17.19 Unfolded term: ~ (((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((((bnd_c6_0 &
% 17.60/17.19 ~ bnd_c8_0) &
% 17.60/17.19 ((bnd_c1_0 | bnd_c5_0) |
% 17.60/17.19 (ALL U.
% 17.60/17.19 bnd_ndr1_0 -->
% 17.60/17.19 (~ bnd_c2_1 U |
% 17.60/17.19 ((bnd_ndr1_1 U & bnd_c1_2 U bnd_a431) & bnd_c6_2 U bnd_a431) &
% 17.60/17.19 ~ bnd_c10_2 U bnd_a431) |
% 17.60/17.19 ((bnd_ndr1_1 U & bnd_c10_2 U bnd_a432) & bnd_c4_2 U bnd_a432) &
% 17.60/17.19 bnd_c5_2 U bnd_a432))) &
% 17.60/17.19 ((bnd_c1_0 | ~ bnd_c2_0) |
% 17.60/17.19 (ALL V.
% 17.60/17.19 bnd_ndr1_0 -->
% 17.60/17.19 (~ bnd_c6_1 V | ~ bnd_c7_1 V) |
% 17.60/17.19 ((bnd_ndr1_1 V & bnd_c5_2 V bnd_a433) & ~ bnd_c4_2 V bnd_a433) &
% 17.60/17.19 ~ bnd_c6_2 V bnd_a433))) &
% 17.60/17.19 ((bnd_c1_0 | ~ bnd_c3_0) |
% 17.60/17.19 (ALL W.
% 17.60/17.19 bnd_ndr1_0 -->
% 17.60/17.19 bnd_c1_1 W |
% 17.60/17.19 (ALL X.
% 17.60/17.19 bnd_ndr1_1 W -->
% 17.60/17.19 (bnd_c3_2 W X | bnd_c4_2 W X) | ~ bnd_c5_2 W X)))) &
% 17.60/17.19 (bnd_c1_0 | ~ bnd_c9_0)) &
% 17.60/17.19 ((bnd_c1_0 |
% 17.60/17.19 (((((bnd_ndr1_0 & bnd_c6_1 bnd_a434) &
% 17.60/17.19 (ALL Y.
% 17.60/17.19 bnd_ndr1_1 bnd_a434 -->
% 17.60/17.19 (bnd_c10_2 bnd_a434 Y | ~ bnd_c5_2 bnd_a434 Y) |
% 17.60/17.19 ~ bnd_c9_2 bnd_a434 Y)) &
% 17.60/17.19 bnd_ndr1_1 bnd_a434) &
% 17.60/17.19 ~ bnd_c1_2 bnd_a434 bnd_a435) &
% 17.60/17.19 ~ bnd_c5_2 bnd_a434 bnd_a435) &
% 17.60/17.19 ~ bnd_c8_2 bnd_a434 bnd_a435) |
% 17.60/17.19 ((bnd_ndr1_0 & bnd_c7_1 bnd_a436) &
% 17.60/17.19 ~ bnd_c3_1 bnd_a436) &
% 17.60/17.19 ~ bnd_c9_1 bnd_a436)) &
% 17.60/17.19 ((bnd_c10_0 | bnd_c3_0) |
% 17.60/17.19 (((((bnd_ndr1_0 & ~ bnd_c1_1 bnd_a437) &
% 17.60/17.19 (ALL Z.
% 17.60/17.19 bnd_ndr1_1 bnd_a437 -->
% 17.60/17.19 (bnd_c10_2 bnd_a437 Z | bnd_c5_2 bnd_a437 Z) |
% 17.60/17.19 ~ bnd_c8_2 bnd_a437 Z)) &
% 17.60/17.19 bnd_ndr1_1 bnd_a437) &
% 17.60/17.19 bnd_c9_2 bnd_a437 bnd_a438) &
% 17.60/17.19 ~ bnd_c4_2 bnd_a437 bnd_a438) &
% 17.60/17.19 ~ bnd_c8_2 bnd_a437 bnd_a438)) &
% 17.60/17.19 ((bnd_c10_0 | bnd_c4_0) |
% 17.60/17.19 (ALL X1.
% 17.60/17.19 bnd_ndr1_0 -->
% 17.60/17.19 (bnd_c9_1 X1 | ~ bnd_c2_1 X1) |
% 17.60/17.19 ((bnd_ndr1_1 X1 & ~ bnd_c4_2 X1 bnd_a439) & ~ bnd_c5_2 X1 bnd_a439) &
% 17.60/17.19 ~ bnd_c6_2 X1 bnd_a439))) &
% 17.60/17.19 ((bnd_c10_0 | bnd_c5_0) | ~ bnd_c9_0)) &
% 17.60/17.19 (bnd_c10_0 | bnd_c7_0)) &
% 17.60/17.19 ((bnd_c10_0 | bnd_c7_0) |
% 17.60/17.19 (((((bnd_ndr1_0 & ~ bnd_c3_1 bnd_a440) &
% 17.60/17.19 (ALL X2.
% 17.60/17.19 bnd_ndr1_1 bnd_a440 -->
% 17.60/17.19 (~ bnd_c2_2 bnd_a440 X2 | ~ bnd_c4_2 bnd_a440 X2) |
% 17.60/17.19 ~ bnd_c9_2 bnd_a440 X2)) &
% 17.60/17.19 bnd_ndr1_1 bnd_a440) &
% 17.60/17.19 bnd_c10_2 bnd_a440 bnd_a441) &
% 17.60/17.19 ~ bnd_c4_2 bnd_a440 bnd_a441) &
% 17.60/17.19 ~ bnd_c5_2 bnd_a440 bnd_a441)) &
% 17.60/17.19 ((bnd_c10_0 | ~ bnd_c2_0) |
% 17.60/17.19 (ALL X3.
% 17.60/17.19 bnd_ndr1_0 -->
% 17.60/17.19 ~ bnd_c5_1 X3 |
% 17.60/17.19 ((bnd_ndr1_1 X3 &
% 17.60/17.19 bnd_c10_2 X3 bnd_a442) &
% 17.60/17.19 bnd_c5_2 X3 bnd_a442) &
% 17.60/17.19 ~ bnd_c7_2 X3 bnd_a442))) &
% 17.60/17.19 ((bnd_c10_0 | ~ bnd_c7_0) |
% 17.60/17.19 (((((((bnd_ndr1_0 & bnd_c4_1 bnd_a443) &
% 17.60/17.19 bnd_ndr1_1 bnd_a443) &
% 17.60/17.19 bnd_c1_2 bnd_a443 bnd_a444) &
% 17.60/17.19 ~ bnd_c4_2 bnd_a443 bnd_a444) &
% 17.60/17.19 bnd_ndr1_1 bnd_a443) &
% 17.60/17.19 bnd_c5_2 bnd_a443 bnd_a445) &
% 17.60/17.19 ~ bnd_c10_2 bnd_a443 bnd_a445) &
% 17.60/17.19 ~ bnd_c8_2 bnd_a443 bnd_a445)) &
% 17.60/17.19 (bnd_c10_0 |
% 17.60/17.19 (ALL X4.
% 17.60/17.19 bnd_ndr1_0 -->
% 17.60/17.19 (bnd_c1_1 X4 | ~ bnd_c9_1 X4) |
% 17.60/17.19 (ALL X5.
% 17.60/17.19 bnd_ndr1_1 X4 -->
% 17.60/17.19 (bnd_c2_2 X4 X5 | bnd_c4_2 X4 X5) |
% 17.60/17.19 bnd_c9_2 X4 X5)))) &
% 17.60/17.19 ((bnd_c10_0 |
% 17.60/17.19 (ALL X6.
% 17.60/17.19 bnd_ndr1_0 -->
% 17.60/17.19 (bnd_c10_1 X6 |
% 17.60/17.19 ((bnd_ndr1_1 X6 & bnd_c1_2 X6 bnd_a446) &
% 17.60/17.19 ~ bnd_c6_2 X6 bnd_a446) &
% 17.60/17.19 ~ bnd_c9_2 X6 bnd_a446) |
% 17.60/17.19 ((bnd_ndr1_1 X6 &
% 17.60/17.19 ~ bnd_c10_2 X6 bnd_a447) &
% 17.60/17.19 ~ bnd_c2_2 X6 bnd_a447) &
% 17.60/17.19 ~ bnd_c3_2 X6 bnd_a447)) |
% 17.60/17.19 ((bnd_ndr1_0 & ~ bnd_c9_1 bnd_a448) &
% 17.60/17.19 (ALL X7.
% 17.60/17.19 bnd_ndr1_1 bnd_a448 -->
% 17.60/17.19 (bnd_c1_2 bnd_a448 X7 |
% 17.60/17.19 bnd_c5_2 bnd_a448 X7) |
% 17.60/17.19 ~ bnd_c8_2 bnd_a448 X7)) &
% 17.60/17.19 (ALL X8.
% 17.60/17.19 bnd_ndr1_1 bnd_a448 -->
% 17.60/17.19 (bnd_c1_2 bnd_a448 X8 |
% 17.60/17.19 ~ bnd_c4_2 bnd_a448 X8) |
% 17.60/17.19 ~ bnd_c6_2 bnd_a448 X8))) &
% 17.60/17.19 (bnd_c10_0 |
% 17.60/17.19 (ALL X9.
% 17.60/17.19 bnd_ndr1_0 -->
% 17.60/17.19 (bnd_c2_1 X9 | bnd_c9_1 X9) |
% 17.60/17.19 ~ bnd_c3_1 X9))) &
% 17.60/17.19 ((bnd_c10_0 |
% 17.60/17.19 (((((bnd_ndr1_0 & bnd_c3_1 bnd_a449) &
% 17.60/17.19 (ALL X10.
% 17.60/17.19 bnd_ndr1_1 bnd_a449 -->
% 17.60/17.19 bnd_c3_2 bnd_a449 X10 |
% 17.60/17.19 bnd_c6_2 bnd_a449 X10)) &
% 17.60/17.19 bnd_ndr1_1 bnd_a449) &
% 17.60/17.19 bnd_c4_2 bnd_a449 bnd_a450) &
% 17.60/17.19 bnd_c7_2 bnd_a449 bnd_a450) &
% 17.60/17.19 ~ bnd_c9_2 bnd_a449 bnd_a450) |
% 17.60/17.19 ((((bnd_ndr1_0 & ~ bnd_c6_1 bnd_a451) &
% 17.60/17.19 bnd_ndr1_1 bnd_a451) &
% 17.60/17.19 bnd_c5_2 bnd_a451 bnd_a452) &
% 17.60/17.19 ~ bnd_c6_2 bnd_a451 bnd_a452) &
% 17.60/17.19 ~ bnd_c9_2 bnd_a451 bnd_a452)) &
% 17.60/17.19 (bnd_c10_0 |
% 17.60/17.19 (((((bnd_ndr1_0 & bnd_c8_1 bnd_a453) &
% 17.60/17.19 (ALL X11.
% 17.60/17.19 bnd_ndr1_1 bnd_a453 -->
% 17.60/17.19 (~ bnd_c10_2 bnd_a453 X11 |
% 17.60/17.19 ~ bnd_c4_2 bnd_a453 X11) |
% 17.60/17.19 ~ bnd_c5_2 bnd_a453 X11)) &
% 17.60/17.19 bnd_ndr1_1 bnd_a453) &
% 17.60/17.19 bnd_c7_2 bnd_a453 bnd_a454) &
% 17.60/17.19 ~ bnd_c2_2 bnd_a453 bnd_a454) &
% 17.60/17.19 ~ bnd_c5_2 bnd_a453 bnd_a454)) &
% 17.60/17.19 (bnd_c10_0 |
% 17.60/17.19 (((((bnd_ndr1_0 &
% 17.60/17.19 (ALL X12.
% 17.60/17.19 bnd_ndr1_1 bnd_a455 -->
% 17.60/17.19 (bnd_c3_2 bnd_a455 X12 |
% 17.60/17.19 bnd_c8_2 bnd_a455 X12) |
% 17.60/17.19 ~ bnd_c1_2 bnd_a455 X12)) &
% 17.60/17.19 (ALL X13.
% 17.60/17.19 bnd_ndr1_1 bnd_a455 -->
% 17.60/17.19 (bnd_c3_2 bnd_a455 X13 |
% 17.60/17.19 bnd_c9_2 bnd_a455 X13) |
% 17.60/17.19 ~ bnd_c1_2 bnd_a455 X13)) &
% 17.60/17.19 bnd_ndr1_1 bnd_a455) &
% 17.60/17.19 bnd_c8_2 bnd_a455 bnd_a456) &
% 17.60/17.19 ~ bnd_c2_2 bnd_a455 bnd_a456) &
% 17.60/17.19 ~ bnd_c4_2 bnd_a455 bnd_a456)) &
% 17.60/17.19 (bnd_c10_0 |
% 17.60/17.19 ((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a457) &
% 17.60/17.19 bnd_c1_2 bnd_a457 bnd_a458) &
% 17.60/17.19 ~ bnd_c8_2 bnd_a457 bnd_a458) &
% 17.60/17.19 bnd_ndr1_1 bnd_a457) &
% 17.60/17.19 bnd_c10_2 bnd_a457 bnd_a459) &
% 17.60/17.19 ~ bnd_c2_2 bnd_a457 bnd_a459) &
% 17.60/17.19 ~ bnd_c4_2 bnd_a457 bnd_a459)) &
% 17.60/17.19 ((bnd_c2_0 | bnd_c7_0) |
% 17.60/17.19 ((bnd_ndr1_0 & bnd_c1_1 bnd_a460) &
% 17.60/17.19 bnd_c2_1 bnd_a460) &
% 17.60/17.19 ~ bnd_c5_1 bnd_a460)) &
% 17.60/17.19 ((bnd_c2_0 | ~ bnd_c1_0) |
% 17.60/17.19 (ALL X14.
% 17.60/17.19 bnd_ndr1_0 -->
% 17.60/17.19 (ALL X15.
% 17.60/17.19 bnd_ndr1_1 X14 -->
% 17.60/17.19 (~ bnd_c10_2 X14 X15 | ~ bnd_c4_2 X14 X15) |
% 17.60/17.19 ~ bnd_c9_2 X14 X15)))) &
% 17.60/17.19 ((bnd_c2_0 | ~ bnd_c4_0) | ~ bnd_c7_0)) &
% 17.60/17.19 ((bnd_c2_0 | ~ bnd_c5_0) |
% 17.60/17.19 (ALL X16.
% 17.60/17.19 bnd_ndr1_0 --> bnd_c3_1 X16 | ~ bnd_c6_1 X16))) &
% 17.60/17.19 ((bnd_c2_0 | ~ bnd_c7_0) |
% 17.60/17.19 (((((bnd_ndr1_0 & ~ bnd_c3_1 bnd_a461) &
% 17.60/17.19 ~ bnd_c4_1 bnd_a461) &
% 17.60/17.19 bnd_ndr1_1 bnd_a461) &
% 17.60/17.19 ~ bnd_c1_2 bnd_a461 bnd_a462) &
% 17.60/17.19 ~ bnd_c3_2 bnd_a461 bnd_a462) &
% 17.60/17.19 ~ bnd_c8_2 bnd_a461 bnd_a462)) &
% 17.60/17.19 ((bnd_c3_0 | bnd_c7_0) |
% 17.60/17.19 (ALL X17.
% 17.60/17.19 bnd_ndr1_0 -->
% 17.60/17.19 (bnd_c4_1 X17 |
% 17.60/17.19 (ALL X18.
% 17.60/17.19 bnd_ndr1_1 X17 -->
% 17.60/17.19 (bnd_c9_2 X17 X18 | ~ bnd_c1_2 X17 X18) |
% 17.60/17.19 ~ bnd_c3_2 X17 X18)) |
% 17.60/17.19 ((bnd_ndr1_1 X17 & bnd_c7_2 X17 bnd_a463) &
% 17.60/17.19 ~ bnd_c2_2 X17 bnd_a463) &
% 17.60/17.19 ~ bnd_c5_2 X17 bnd_a463))) &
% 17.60/17.19 ((bnd_c3_0 | ~ bnd_c1_0) |
% 17.60/17.19 (ALL X19.
% 17.60/17.19 bnd_ndr1_0 -->
% 17.60/17.19 (bnd_c4_1 X19 | ~ bnd_c8_1 X19) |
% 17.60/17.19 (ALL X20.
% 17.60/17.19 bnd_ndr1_1 X19 -->
% 17.60/17.19 (bnd_c1_2 X19 X20 | bnd_c6_2 X19 X20) |
% 17.60/17.19 ~ bnd_c3_2 X19 X20)))) &
% 17.60/17.19 ((bnd_c3_0 | ~ bnd_c1_0) |
% 17.60/17.19 (ALL X21.
% 17.60/17.19 bnd_ndr1_0 -->
% 17.60/17.19 ~ bnd_c7_1 X21 |
% 17.60/17.19 (ALL X22.
% 17.60/17.19 bnd_ndr1_1 X21 -->
% 17.60/17.19 (bnd_c5_2 X21 X22 | ~ bnd_c1_2 X21 X22) |
% 17.60/17.19 ~ bnd_c9_2 X21 X22)))) &
% 17.60/17.19 ((bnd_c3_0 | ~ bnd_c10_0) |
% 17.60/17.19 (ALL X23.
% 17.60/17.19 bnd_ndr1_0 -->
% 17.60/17.19 (bnd_c6_1 X23 |
% 17.60/17.19 (ALL X24.
% 17.60/17.19 bnd_ndr1_1 X23 -->
% 17.60/17.19 (bnd_c8_2 X23 X24 | ~ bnd_c3_2 X23 X24) |
% 17.60/17.19 ~ bnd_c6_2 X23 X24)) |
% 17.60/17.19 ((bnd_ndr1_1 X23 & bnd_c3_2 X23 bnd_a464) &
% 17.60/17.19 bnd_c7_2 X23 bnd_a464) &
% 17.60/17.19 ~ bnd_c6_2 X23 bnd_a464))) &
% 17.60/17.19 ((bnd_c3_0 | ~ bnd_c4_0) | ~ bnd_c7_0)) &
% 17.60/17.19 (bnd_c3_0 |
% 17.60/17.19 (((((bnd_ndr1_0 & ~ bnd_c10_1 bnd_a465) &
% 17.60/17.19 (ALL X25.
% 17.60/17.19 bnd_ndr1_1 bnd_a465 -->
% 17.60/17.19 (bnd_c8_2 bnd_a465 X25 | ~ bnd_c3_2 bnd_a465 X25) |
% 17.60/17.19 ~ bnd_c4_2 bnd_a465 X25)) &
% 17.60/17.19 bnd_ndr1_1 bnd_a465) &
% 17.60/17.19 bnd_c2_2 bnd_a465 bnd_a466) &
% 17.60/17.19 bnd_c6_2 bnd_a465 bnd_a466) &
% 17.60/17.19 ~ bnd_c1_2 bnd_a465 bnd_a466)) &
% 17.60/17.19 ((bnd_c3_0 |
% 17.60/17.19 (ALL X26.
% 17.60/17.19 bnd_ndr1_0 -->
% 17.60/17.19 (~ bnd_c7_1 X26 | ~ bnd_c8_1 X26) |
% 17.60/17.19 (ALL X27.
% 17.60/17.19 bnd_ndr1_1 X26 -->
% 17.60/17.19 bnd_c5_2 X26 X27 | ~ bnd_c3_2 X26 X27))) |
% 17.60/17.19 ((bnd_ndr1_0 & bnd_c1_1 bnd_a467) & bnd_c5_1 bnd_a467) &
% 17.60/17.19 ~ bnd_c6_1 bnd_a467)) &
% 17.60/17.19 ((bnd_c4_0 | bnd_c5_0) |
% 17.60/17.19 (((((bnd_ndr1_0 & ~ bnd_c6_1 bnd_a468) &
% 17.60/17.19 (ALL X28.
% 17.60/17.19 bnd_ndr1_1 bnd_a468 -->
% 17.60/17.19 (bnd_c1_2 bnd_a468 X28 | bnd_c9_2 bnd_a468 X28) |
% 17.60/17.19 ~ bnd_c4_2 bnd_a468 X28)) &
% 17.60/17.19 bnd_ndr1_1 bnd_a468) &
% 17.60/17.19 bnd_c6_2 bnd_a468 bnd_a469) &
% 17.60/17.19 bnd_c9_2 bnd_a468 bnd_a469) &
% 17.60/17.19 ~ bnd_c7_2 bnd_a468 bnd_a469)) &
% 17.60/17.19 (bnd_c4_0 |
% 17.60/17.19 ((((bnd_ndr1_0 & bnd_c8_1 bnd_a470) &
% 17.60/17.19 (ALL X29.
% 17.60/17.19 bnd_ndr1_1 bnd_a470 -->
% 17.60/17.19 (bnd_c3_2 bnd_a470 X29 | bnd_c7_2 bnd_a470 X29) |
% 17.60/17.19 ~ bnd_c4_2 bnd_a470 X29)) &
% 17.60/17.19 bnd_ndr1_1 bnd_a470) &
% 17.60/17.19 bnd_c7_2 bnd_a470 bnd_a471) &
% 17.60/17.19 bnd_c8_2 bnd_a470 bnd_a471)) &
% 17.60/17.19 ((bnd_c4_0 | ~ bnd_c9_0) |
% 17.60/17.19 (ALL X30.
% 17.60/17.19 bnd_ndr1_0 -->
% 17.60/17.19 (bnd_c9_1 X30 | ~ bnd_c10_1 X30) |
% 17.60/17.19 (ALL X31.
% 17.60/17.19 bnd_ndr1_1 X30 -->
% 17.60/17.19 (~ bnd_c10_2 X30 X31 | ~ bnd_c7_2 X30 X31) |
% 17.60/17.19 ~ bnd_c8_2 X30 X31)))) &
% 17.60/17.19 (bnd_c4_0 |
% 17.60/17.19 (ALL X32.
% 17.60/17.19 bnd_ndr1_0 -->
% 17.60/17.19 (bnd_c6_1 X32 |
% 17.60/17.19 (ALL X33.
% 17.60/17.19 bnd_ndr1_1 X32 -->
% 17.60/17.19 (bnd_c4_2 X32 X33 | bnd_c5_2 X32 X33) | bnd_c9_2 X32 X33)) |
% 17.60/17.19 (ALL X34.
% 17.60/17.19 bnd_ndr1_1 X32 -->
% 17.60/17.19 (bnd_c6_2 X32 X34 | bnd_c8_2 X32 X34) |
% 17.60/17.19 ~ bnd_c4_2 X32 X34)))) &
% 17.60/17.19 ((bnd_c4_0 |
% 17.60/17.19 (ALL X35.
% 17.60/17.19 bnd_ndr1_0 -->
% 17.60/17.19 (~ bnd_c5_1 X35 |
% 17.60/17.19 ((bnd_ndr1_1 X35 & bnd_c2_2 X35 bnd_a472) &
% 17.60/17.19 bnd_c9_2 X35 bnd_a472) &
% 17.60/17.19 ~ bnd_c3_2 X35 bnd_a472) |
% 17.60/17.19 ((bnd_ndr1_1 X35 & bnd_c5_2 X35 bnd_a473) &
% 17.60/17.19 bnd_c8_2 X35 bnd_a473) &
% 17.60/17.19 bnd_c9_2 X35 bnd_a473)) |
% 17.60/17.19 ((bnd_ndr1_0 & bnd_c10_1 bnd_a474) & ~ bnd_c8_1 bnd_a474) &
% 17.60/17.19 (ALL X36.
% 17.60/17.19 bnd_ndr1_1 bnd_a474 -->
% 17.60/17.19 (bnd_c10_2 bnd_a474 X36 | bnd_c4_2 bnd_a474 X36) |
% 17.60/17.19 ~ bnd_c3_2 bnd_a474 X36))) &
% 17.60/17.19 (bnd_c5_0 |
% 17.60/17.19 (ALL X37.
% 17.60/17.19 bnd_ndr1_0 -->
% 17.60/17.19 (~ bnd_c2_1 X37 |
% 17.60/17.19 (bnd_ndr1_1 X37 & bnd_c1_2 X37 bnd_a475) &
% 17.60/17.19 ~ bnd_c7_2 X37 bnd_a475) |
% 17.60/17.19 ((bnd_ndr1_1 X37 & bnd_c2_2 X37 bnd_a476) &
% 17.60/17.19 ~ bnd_c10_2 X37 bnd_a476) &
% 17.60/17.19 ~ bnd_c4_2 X37 bnd_a476))) &
% 17.60/17.19 ((bnd_c5_0 | ~ bnd_c1_0) |
% 17.60/17.19 ((bnd_ndr1_0 & bnd_c9_1 bnd_a477) & ~ bnd_c10_1 bnd_a477) &
% 17.60/17.19 ~ bnd_c3_1 bnd_a477)) &
% 17.60/17.19 ((bnd_c5_0 | ~ bnd_c3_0) |
% 17.60/17.19 (ALL X38.
% 17.60/17.19 bnd_ndr1_0 -->
% 17.60/17.19 (bnd_c10_1 X38 | bnd_c2_1 X38) |
% 17.60/17.19 ((bnd_ndr1_1 X38 & bnd_c6_2 X38 bnd_a478) &
% 17.60/17.19 ~ bnd_c4_2 X38 bnd_a478) &
% 17.60/17.19 ~ bnd_c7_2 X38 bnd_a478))) &
% 17.60/17.19 (bnd_c5_0 |
% 17.60/17.19 ((((((bnd_ndr1_0 & bnd_ndr1_1 bnd_a479) & bnd_c10_2 bnd_a479 bnd_a480) &
% 17.60/17.19 bnd_c9_2 bnd_a479 bnd_a480) &
% 17.60/17.19 bnd_ndr1_1 bnd_a479) &
% 17.60/17.19 bnd_c5_2 bnd_a479 bnd_a481) &
% 17.60/17.19 bnd_c8_2 bnd_a479 bnd_a481) &
% 17.60/17.19 ~ bnd_c4_2 bnd_a479 bnd_a481)) &
% 17.60/17.19 ((bnd_c5_0 | ~ bnd_c7_0) |
% 17.60/17.19 (bnd_ndr1_0 & bnd_c2_1 bnd_a482) & ~ bnd_c5_1 bnd_a482)) &
% 17.60/17.19 ((bnd_c5_0 | ~ bnd_c7_0) |
% 17.60/17.19 (bnd_ndr1_0 & bnd_c6_1 bnd_a483) & ~ bnd_c3_1 bnd_a483)) &
% 17.60/17.19 ((bnd_c5_0 |
% 17.60/17.19 (ALL X39.
% 17.60/17.19 bnd_ndr1_0 -->
% 17.60/17.19 bnd_c2_1 X39 |
% 17.60/17.19 ((bnd_ndr1_1 X39 & bnd_c4_2 X39 bnd_a484) & bnd_c5_2 X39 bnd_a484) &
% 17.60/17.19 bnd_c9_2 X39 bnd_a484)) |
% 17.60/17.19 ((((((((bnd_ndr1_0 &
% 17.60/17.19 bnd_c1_1 bnd_a485) &
% 17.60/17.19 bnd_ndr1_1 bnd_a485) &
% 17.60/17.19 bnd_c5_2 bnd_a485 bnd_a486) &
% 17.60/17.19 bnd_c7_2 bnd_a485 bnd_a486) &
% 17.60/17.19 ~ bnd_c6_2 bnd_a485 bnd_a486) &
% 17.60/17.19 bnd_ndr1_1 bnd_a485) &
% 17.60/17.19 ~ bnd_c2_2 bnd_a485 bnd_a487) &
% 17.60/17.19 ~ bnd_c3_2 bnd_a485 bnd_a487) &
% 17.60/17.19 ~ bnd_c8_2 bnd_a485 bnd_a487)) &
% 17.60/17.19 ((bnd_c5_0 |
% 17.60/17.19 (ALL X40.
% 17.60/17.19 bnd_ndr1_0 -->
% 17.60/17.19 (~ bnd_c3_1 X40 | ~ bnd_c7_1 X40) |
% 17.60/17.19 ((bnd_ndr1_1 X40 & bnd_c1_2 X40 bnd_a488) & bnd_c4_2 X40 bnd_a488) &
% 17.60/17.19 bnd_c5_2 X40 bnd_a488)) |
% 17.60/17.19 ((bnd_ndr1_0 & bnd_c3_1 bnd_a489) &
% 17.60/17.19 ~ bnd_c8_1 bnd_a489) &
% 17.60/17.19 (ALL X41.
% 17.60/17.19 bnd_ndr1_1 bnd_a489 -->
% 17.60/17.19 (bnd_c3_2 bnd_a489 X41 | bnd_c8_2 bnd_a489 X41) |
% 17.60/17.19 ~ bnd_c1_2 bnd_a489 X41))) &
% 17.60/17.19 ((bnd_c5_0 |
% 17.60/17.19 ((bnd_ndr1_0 & bnd_c6_1 bnd_a490) &
% 17.60/17.19 bnd_c8_1 bnd_a490) &
% 17.60/17.19 ~ bnd_c9_1 bnd_a490) |
% 17.60/17.19 (((((bnd_ndr1_0 & bnd_c8_1 bnd_a491) &
% 17.60/17.19 ~ bnd_c4_1 bnd_a491) &
% 17.60/17.19 bnd_ndr1_1 bnd_a491) &
% 17.60/17.19 bnd_c3_2 bnd_a491 bnd_a492) &
% 17.60/17.19 ~ bnd_c1_2 bnd_a491 bnd_a492) &
% 17.60/17.19 ~ bnd_c4_2 bnd_a491 bnd_a492)) &
% 17.60/17.19 (bnd_c7_0 | ~ bnd_c1_0)) &
% 17.60/17.19 ((bnd_c7_0 | ~ bnd_c5_0) |
% 17.60/17.19 (bnd_ndr1_0 & bnd_c2_1 bnd_a493) &
% 17.60/17.19 (ALL X42.
% 17.60/17.19 bnd_ndr1_1 bnd_a493 -->
% 17.60/17.19 (bnd_c10_2 bnd_a493 X42 |
% 17.60/17.19 bnd_c3_2 bnd_a493 X42) |
% 17.60/17.19 ~ bnd_c5_2 bnd_a493 X42))) &
% 17.60/17.19 ((bnd_c7_0 |
% 17.60/17.19 (ALL X43.
% 17.60/17.19 bnd_ndr1_0 -->
% 17.60/17.19 ~ bnd_c1_1 X43 | ~ bnd_c10_1 X43)) |
% 17.60/17.19 (ALL X44.
% 17.60/17.19 bnd_ndr1_0 -->
% 17.60/17.19 ((ALL X45.
% 17.60/17.19 bnd_ndr1_1 X44 -->
% 17.60/17.19 (bnd_c6_2 X44 X45 | bnd_c7_2 X44 X45) | ~ bnd_c3_2 X44 X45) |
% 17.60/17.19 ((bnd_ndr1_1 X44 &
% 17.60/17.19 bnd_c2_2 X44 bnd_a494) &
% 17.60/17.19 bnd_c5_2 X44 bnd_a494) &
% 17.60/17.19 bnd_c8_2 X44 bnd_a494) |
% 17.60/17.19 ((bnd_ndr1_1 X44 &
% 17.60/17.19 ~ bnd_c1_2 X44 bnd_a495) &
% 17.60/17.19 ~ bnd_c3_2 X44 bnd_a495) &
% 17.60/17.19 ~ bnd_c4_2 X44 bnd_a495))) &
% 17.60/17.19 ((bnd_c7_0 |
% 17.60/17.19 (ALL X46.
% 17.60/17.19 bnd_ndr1_0 -->
% 17.60/17.19 (~ bnd_c4_1 X46 |
% 17.60/17.19 ((bnd_ndr1_1 X46 &
% 17.60/17.19 bnd_c4_2 X46 bnd_a496) &
% 17.60/17.19 bnd_c9_2 X46 bnd_a496) &
% 17.60/17.19 ~ bnd_c7_2 X46 bnd_a496) |
% 17.60/17.19 ((bnd_ndr1_1 X46 &
% 17.60/17.19 bnd_c5_2 X46 bnd_a497) &
% 17.60/17.19 ~ bnd_c2_2 X46 bnd_a497) &
% 17.60/17.19 ~ bnd_c7_2 X46 bnd_a497)) |
% 17.60/17.19 (bnd_ndr1_0 & ~ bnd_c2_1 bnd_a498) &
% 17.60/17.19 ~ bnd_c6_1 bnd_a498)) &
% 17.60/17.19 ((bnd_c7_0 |
% 17.60/17.19 (bnd_ndr1_0 & bnd_c1_1 bnd_a499) &
% 17.60/17.19 ~ bnd_c2_1 bnd_a499) |
% 17.60/17.19 (bnd_ndr1_0 & bnd_c10_1 bnd_a500) &
% 17.60/17.19 bnd_c4_1 bnd_a500)) &
% 17.60/17.19 (bnd_c7_0 |
% 17.60/17.19 (((((bnd_ndr1_0 &
% 17.60/17.19 (ALL X47.
% 17.60/17.19 bnd_ndr1_1 bnd_a501 -->
% 17.60/17.19 (bnd_c3_2 bnd_a501 X47 | ~ bnd_c1_2 bnd_a501 X47) |
% 17.60/17.19 ~ bnd_c6_2 bnd_a501 X47)) &
% 17.60/17.19 (ALL X48.
% 17.60/17.19 bnd_ndr1_1 bnd_a501 -->
% 17.60/17.19 (bnd_c6_2 bnd_a501 X48 |
% 17.60/17.19 bnd_c9_2 bnd_a501 X48) |
% 17.60/17.19 ~ bnd_c7_2 bnd_a501 X48)) &
% 17.60/17.19 bnd_ndr1_1 bnd_a501) &
% 17.60/17.19 bnd_c3_2 bnd_a501 bnd_a502) &
% 17.60/17.19 bnd_c9_2 bnd_a501 bnd_a502) &
% 17.60/17.19 ~ bnd_c2_2 bnd_a501 bnd_a502)) &
% 17.60/17.19 (~ bnd_c10_0 | ~ bnd_c7_0)) &
% 17.60/17.19 (~ bnd_c10_0 |
% 17.60/17.19 ((bnd_ndr1_0 & ~ bnd_c6_1 bnd_a503) &
% 17.60/17.19 (ALL X49.
% 17.60/17.19 bnd_ndr1_1 bnd_a503 -->
% 17.60/17.19 (bnd_c4_2 bnd_a503 X49 |
% 17.60/17.19 bnd_c9_2 bnd_a503 X49) |
% 17.60/17.19 ~ bnd_c7_2 bnd_a503 X49)) &
% 17.60/17.19 (ALL X50.
% 17.60/17.19 bnd_ndr1_1 bnd_a503 -->
% 17.60/17.19 (bnd_c8_2 bnd_a503 X50 |
% 17.60/17.19 bnd_c9_2 bnd_a503 X50) |
% 17.60/17.19 ~ bnd_c1_2 bnd_a503 X50))) &
% 17.60/17.19 (~ bnd_c4_0 | ~ bnd_c5_0)) &
% 17.60/17.19 (ALL X51.
% 17.60/17.19 bnd_ndr1_0 -->
% 17.60/17.19 (bnd_c2_1 X51 | ~ bnd_c3_1 X51) |
% 17.60/17.19 (bnd_ndr1_1 X51 & bnd_c2_2 X51 bnd_a504) &
% 17.60/17.19 bnd_c3_2 X51 bnd_a504)) &
% 17.60/17.19 ((ALL X52.
% 17.60/17.19 bnd_ndr1_0 -->
% 17.60/17.19 (bnd_c1_1 X52 |
% 17.60/17.19 (ALL X53.
% 17.60/17.19 bnd_ndr1_1 X52 -->
% 17.60/17.19 (bnd_c2_2 X52 X53 | ~ bnd_c10_2 X52 X53) |
% 17.60/17.19 ~ bnd_c9_2 X52 X53)) |
% 17.60/17.19 (bnd_ndr1_1 X52 & bnd_c6_2 X52 bnd_a505) &
% 17.60/17.19 ~ bnd_c3_2 X52 bnd_a505) |
% 17.60/17.19 (ALL X54.
% 17.60/17.19 bnd_ndr1_0 -->
% 17.60/17.19 ((ALL X55.
% 17.60/17.19 bnd_ndr1_1 X54 -->
% 17.60/17.19 (bnd_c1_2 X54 X55 | bnd_c3_2 X54 X55) |
% 17.60/17.19 ~ bnd_c7_2 X54 X55) |
% 17.60/17.19 (ALL X56.
% 17.60/17.19 bnd_ndr1_1 X54 -->
% 17.60/17.19 (bnd_c2_2 X54 X56 | bnd_c3_2 X54 X56) |
% 17.60/17.19 ~ bnd_c6_2 X54 X56)) |
% 17.60/17.19 ((bnd_ndr1_1 X54 & bnd_c6_2 X54 bnd_a506) &
% 17.60/17.19 ~ bnd_c1_2 X54 bnd_a506) &
% 17.60/17.19 ~ bnd_c8_2 X54 bnd_a506))) &
% 17.60/17.19 ((ALL X57.
% 17.60/17.19 bnd_ndr1_0 -->
% 17.60/17.19 (bnd_c9_1 X57 | ~ bnd_c4_1 X57) |
% 17.60/17.19 ((bnd_ndr1_1 X57 & bnd_c1_2 X57 bnd_a507) &
% 17.60/17.19 ~ bnd_c2_2 X57 bnd_a507) &
% 17.60/17.19 ~ bnd_c5_2 X57 bnd_a507) |
% 17.60/17.19 ((((bnd_ndr1_0 &
% 17.60/17.19 (ALL X58.
% 17.60/17.19 bnd_ndr1_1 bnd_a508 -->
% 17.60/17.19 bnd_c8_2 bnd_a508 X58 |
% 17.60/17.19 ~ bnd_c6_2 bnd_a508 X58)) &
% 17.60/17.19 bnd_ndr1_1 bnd_a508) &
% 17.60/17.19 ~ bnd_c2_2 bnd_a508 bnd_a509) &
% 17.60/17.19 ~ bnd_c5_2 bnd_a508 bnd_a509) &
% 17.60/17.19 ~ bnd_c9_2 bnd_a508 bnd_a509)) &
% 17.60/17.19 ((ALL X59.
% 17.60/17.19 bnd_ndr1_0 -->
% 17.60/17.19 (~ bnd_c2_1 X59 | ~ bnd_c8_1 X59) |
% 17.60/17.19 (ALL X60.
% 17.60/17.19 bnd_ndr1_1 X59 -->
% 17.60/17.19 (bnd_c3_2 X59 X60 | bnd_c4_2 X59 X60) |
% 17.60/17.19 ~ bnd_c2_2 X59 X60)) |
% 17.60/17.19 ((bnd_ndr1_0 & bnd_c6_1 bnd_a510) &
% 17.60/17.19 bnd_c7_1 bnd_a510) &
% 17.60/17.19 ~ bnd_c8_1 bnd_a510)) &
% 17.60/17.19 (ALL X61.
% 17.60/17.19 bnd_ndr1_0 -->
% 17.60/17.19 (~ bnd_c2_1 X61 |
% 17.60/17.19 (ALL X62.
% 17.60/17.19 bnd_ndr1_1 X61 -->
% 17.60/17.19 (bnd_c8_2 X61 X62 | ~ bnd_c2_2 X61 X62) |
% 17.60/17.19 ~ bnd_c9_2 X61 X62)) |
% 17.60/17.19 ((bnd_ndr1_1 X61 & bnd_c1_2 X61 bnd_a511) &
% 17.60/17.19 bnd_c4_2 X61 bnd_a511) &
% 17.60/17.19 ~ bnd_c8_2 X61 bnd_a511)) &
% 17.60/17.19 ((ALL X63.
% 17.60/17.19 bnd_ndr1_0 -->
% 17.60/17.19 (~ bnd_c2_1 X63 |
% 17.60/17.19 (ALL X64.
% 17.60/17.19 bnd_ndr1_1 X63 -->
% 17.60/17.19 (~ bnd_c4_2 X63 X64 | ~ bnd_c7_2 X63 X64) |
% 17.60/17.19 ~ bnd_c9_2 X63 X64)) |
% 17.60/17.19 ((bnd_ndr1_1 X63 & bnd_c1_2 X63 bnd_a512) &
% 17.60/17.19 ~ bnd_c3_2 X63 bnd_a512) &
% 17.60/17.19 ~ bnd_c4_2 X63 bnd_a512) |
% 17.60/17.19 ((bnd_ndr1_0 & bnd_c10_1 bnd_a513) &
% 17.60/17.19 bnd_c3_1 bnd_a513) &
% 17.60/17.19 (ALL X65.
% 17.60/17.19 bnd_ndr1_1 bnd_a513 -->
% 17.60/17.19 (bnd_c8_2 bnd_a513 X65 | ~ bnd_c2_2 bnd_a513 X65) |
% 17.60/17.19 ~ bnd_c5_2 bnd_a513 X65))) &
% 17.60/17.19 (ALL X66.
% 17.60/17.19 bnd_ndr1_0 --> ~ bnd_c3_1 X66 | ~ bnd_c9_1 X66)) &
% 17.60/17.19 ((ALL X67.
% 17.60/17.19 bnd_ndr1_0 -->
% 17.60/17.19 (~ bnd_c8_1 X67 |
% 17.60/17.19 (ALL X68.
% 17.60/17.19 bnd_ndr1_1 X67 -->
% 17.60/17.19 (bnd_c10_2 X67 X68 | bnd_c2_2 X67 X68) |
% 17.60/17.19 bnd_c7_2 X67 X68)) |
% 17.60/17.19 (ALL X69.
% 17.60/17.19 bnd_ndr1_1 X67 -->
% 17.60/17.19 (bnd_c3_2 X67 X69 | bnd_c8_2 X67 X69) |
% 17.60/17.19 bnd_c9_2 X67 X69)) |
% 17.60/17.19 (bnd_ndr1_0 & bnd_c10_1 bnd_a514) &
% 17.60/17.19 ~ bnd_c8_1 bnd_a514)) &
% 17.60/17.19 (((bnd_ndr1_0 & bnd_c1_1 bnd_a515) & bnd_c8_1 bnd_a515) &
% 17.60/17.19 ~ bnd_c7_1 bnd_a515 |
% 17.60/17.19 ((bnd_ndr1_0 & bnd_c2_1 bnd_a516) & bnd_c7_1 bnd_a516) &
% 17.60/17.19 ~ bnd_c4_1 bnd_a516)) &
% 17.60/17.19 ((bnd_c9_0 | ~ bnd_c1_0) |
% 17.60/17.19 (bnd_ndr1_0 & bnd_c3_1 bnd_a517) &
% 17.60/17.19 (ALL X70.
% 17.60/17.19 bnd_ndr1_1 bnd_a517 -->
% 17.60/17.19 (bnd_c1_2 bnd_a517 X70 | bnd_c5_2 bnd_a517 X70) |
% 17.60/17.19 ~ bnd_c6_2 bnd_a517 X70))) &
% 17.60/17.19 ((bnd_c9_0 | ~ bnd_c10_0) |
% 17.60/17.19 (ALL X71.
% 17.60/17.19 bnd_ndr1_0 -->
% 17.60/17.19 (~ bnd_c1_1 X71 | ~ bnd_c9_1 X71) |
% 17.60/17.19 ((bnd_ndr1_1 X71 & bnd_c1_2 X71 bnd_a518) &
% 17.60/17.19 bnd_c4_2 X71 bnd_a518) &
% 17.60/17.19 ~ bnd_c8_2 X71 bnd_a518))) &
% 17.60/17.19 ((bnd_c9_0 | ~ bnd_c5_0) |
% 17.60/17.19 (ALL X72.
% 17.60/17.19 bnd_ndr1_0 -->
% 17.60/17.19 (bnd_c9_1 X72 | ~ bnd_c1_1 X72) |
% 17.60/17.19 ((bnd_ndr1_1 X72 & bnd_c2_2 X72 bnd_a519) &
% 17.60/17.19 ~ bnd_c1_2 X72 bnd_a519) &
% 17.60/17.19 ~ bnd_c3_2 X72 bnd_a519))) &
% 17.60/17.19 ((bnd_c9_0 |
% 17.60/17.19 (ALL X73.
% 17.60/17.19 bnd_ndr1_0 -->
% 17.60/17.19 (~ bnd_c1_1 X73 |
% 17.60/17.19 (ALL X74.
% 17.60/17.19 bnd_ndr1_1 X73 -->
% 17.60/17.19 (bnd_c1_2 X73 X74 | bnd_c4_2 X73 X74) |
% 17.60/17.19 ~ bnd_c3_2 X73 X74)) |
% 17.60/17.19 (bnd_ndr1_1 X73 & bnd_c8_2 X73 bnd_a520) &
% 17.60/17.19 ~ bnd_c2_2 X73 bnd_a520)) |
% 17.60/17.19 (((((bnd_ndr1_0 &
% 17.60/17.19 (ALL X75.
% 17.60/17.19 bnd_ndr1_1 bnd_a521 -->
% 17.60/17.19 (bnd_c1_2 bnd_a521 X75 | bnd_c3_2 bnd_a521 X75) |
% 17.60/17.19 ~ bnd_c4_2 bnd_a521 X75)) &
% 17.60/17.19 (ALL X76.
% 17.60/17.19 bnd_ndr1_1 bnd_a521 -->
% 17.60/17.19 (bnd_c1_2 bnd_a521 X76 | bnd_c8_2 bnd_a521 X76) |
% 17.60/17.19 ~ bnd_c4_2 bnd_a521 X76)) &
% 17.60/17.19 bnd_ndr1_1 bnd_a521) &
% 17.60/17.19 bnd_c3_2 bnd_a521 bnd_a522) &
% 17.60/17.19 bnd_c8_2 bnd_a521 bnd_a522) &
% 17.60/17.19 bnd_c9_2 bnd_a521 bnd_a522)) &
% 17.60/17.19 ((bnd_c9_0 |
% 17.60/17.19 (ALL X77.
% 17.60/17.19 bnd_ndr1_0 -->
% 17.60/17.19 ~ bnd_c10_1 X77 |
% 17.60/17.19 ((bnd_ndr1_1 X77 & bnd_c9_2 X77 bnd_a523) &
% 17.60/17.19 ~ bnd_c10_2 X77 bnd_a523) &
% 17.60/17.19 ~ bnd_c2_2 X77 bnd_a523)) |
% 17.60/17.19 ((((bnd_ndr1_0 & bnd_c3_1 bnd_a524) & bnd_ndr1_1 bnd_a524) &
% 17.60/17.19 bnd_c3_2 bnd_a524 bnd_a525) &
% 17.60/17.19 bnd_c7_2 bnd_a524 bnd_a525) &
% 17.60/17.19 ~ bnd_c4_2 bnd_a524 bnd_a525)) &
% 17.60/17.19 ((~ bnd_c1_0 | ~ bnd_c4_0) |
% 17.60/17.19 ((((bnd_ndr1_0 &
% 17.60/17.19 (ALL X78.
% 17.60/17.19 bnd_ndr1_1 bnd_a526 -->
% 17.60/17.19 (bnd_c8_2 bnd_a526 X78 | ~ bnd_c7_2 bnd_a526 X78) |
% 17.60/17.19 ~ bnd_c9_2 bnd_a526 X78)) &
% 17.60/17.19 (ALL X79.
% 17.60/17.19 bnd_ndr1_1 bnd_a526 -->
% 17.60/17.19 (bnd_c9_2 bnd_a526 X79 | ~ bnd_c2_2 bnd_a526 X79) |
% 17.60/17.19 ~ bnd_c4_2 bnd_a526 X79)) &
% 17.60/17.19 bnd_ndr1_1 bnd_a526) &
% 17.60/17.19 bnd_c9_2 bnd_a526 bnd_a527) &
% 17.60/17.19 ~ bnd_c1_2 bnd_a526 bnd_a527)) &
% 17.60/17.19 (~ bnd_c1_0 |
% 17.60/17.19 (((((bnd_ndr1_0 & bnd_c10_1 bnd_a528) & bnd_c5_1 bnd_a528) &
% 17.60/17.19 bnd_ndr1_1 bnd_a528) &
% 17.60/17.19 bnd_c4_2 bnd_a528 bnd_a529) &
% 17.60/17.19 bnd_c7_2 bnd_a528 bnd_a529) &
% 17.60/17.19 bnd_c9_2 bnd_a528 bnd_a529)) &
% 17.60/17.19 ((~ bnd_c1_0 |
% 17.60/17.19 (ALL X80.
% 17.60/17.19 bnd_ndr1_0 -->
% 17.60/17.19 (~ bnd_c1_1 X80 | ~ bnd_c10_1 X80) |
% 17.60/17.19 (bnd_ndr1_1 X80 & bnd_c8_2 X80 bnd_a530) &
% 17.60/17.19 ~ bnd_c10_2 X80 bnd_a530)) |
% 17.60/17.19 (((((bnd_ndr1_0 & bnd_c8_1 bnd_a531) & ~ bnd_c5_1 bnd_a531) &
% 17.60/17.19 bnd_ndr1_1 bnd_a531) &
% 17.60/17.19 bnd_c10_2 bnd_a531 bnd_a532) &
% 17.60/17.19 ~ bnd_c8_2 bnd_a531 bnd_a532) &
% 17.60/17.19 ~ bnd_c9_2 bnd_a531 bnd_a532)) &
% 17.60/17.19 ((~ bnd_c10_0 | ~ bnd_c4_0) |
% 17.60/17.19 (ALL X81.
% 17.60/17.19 bnd_ndr1_0 -->
% 17.60/17.19 bnd_c7_1 X81 |
% 17.60/17.19 ((bnd_ndr1_1 X81 & bnd_c10_2 X81 bnd_a533) &
% 17.60/17.19 bnd_c5_2 X81 bnd_a533) &
% 17.60/17.19 bnd_c8_2 X81 bnd_a533))) &
% 17.60/17.19 ((~ bnd_c10_0 | ~ bnd_c5_0) |
% 17.60/17.19 (ALL X82.
% 17.60/17.19 bnd_ndr1_0 -->
% 17.60/17.19 ((ALL X83.
% 17.60/17.19 bnd_ndr1_1 X82 --> bnd_c5_2 X82 X83 | ~ bnd_c3_2 X82 X83) |
% 17.60/17.19 ((bnd_ndr1_1 X82 & bnd_c8_2 X82 bnd_a534) &
% 17.60/17.19 ~ bnd_c4_2 X82 bnd_a534) &
% 17.60/17.19 ~ bnd_c5_2 X82 bnd_a534) |
% 17.60/17.19 ((bnd_ndr1_1 X82 & ~ bnd_c4_2 X82 bnd_a535) &
% 17.60/17.19 ~ bnd_c8_2 X82 bnd_a535) &
% 17.60/17.19 ~ bnd_c9_2 X82 bnd_a535))) &
% 17.60/17.19 ((~ bnd_c10_0 | ~ bnd_c5_0) |
% 17.60/17.19 (((((bnd_ndr1_0 & bnd_c10_1 bnd_a536) & ~ bnd_c6_1 bnd_a536) &
% 17.60/17.19 bnd_ndr1_1 bnd_a536) &
% 17.60/17.19 bnd_c1_2 bnd_a536 bnd_a537) &
% 17.60/17.19 bnd_c2_2 bnd_a536 bnd_a537) &
% 17.60/17.19 ~ bnd_c7_2 bnd_a536 bnd_a537)) &
% 17.60/17.19 ((~ bnd_c10_0 |
% 17.60/17.19 (ALL X84.
% 17.60/17.19 bnd_ndr1_0 -->
% 17.60/17.19 (bnd_c10_1 X84 | ~ bnd_c2_1 X84) | ~ bnd_c8_1 X84)) |
% 17.60/17.19 (ALL X85.
% 17.60/17.19 bnd_ndr1_0 -->
% 17.60/17.19 (bnd_c9_1 X85 | ~ bnd_c3_1 X85) |
% 17.60/17.19 (ALL X86.
% 17.60/17.19 bnd_ndr1_1 X85 -->
% 17.60/17.19 (bnd_c10_2 X85 X86 | ~ bnd_c1_2 X85 X86) |
% 17.60/17.19 ~ bnd_c7_2 X85 X86)))) &
% 17.60/17.19 ((~ bnd_c10_0 |
% 17.60/17.19 (ALL X87.
% 17.60/17.19 bnd_ndr1_0 -->
% 17.60/17.19 (bnd_c3_1 X87 | ~ bnd_c8_1 X87) |
% 17.60/17.19 ((bnd_ndr1_1 X87 & bnd_c2_2 X87 bnd_a538) &
% 17.60/17.19 bnd_c5_2 X87 bnd_a538) &
% 17.60/17.19 ~ bnd_c1_2 X87 bnd_a538)) |
% 17.60/17.19 (bnd_ndr1_0 & bnd_c3_1 bnd_a539) & ~ bnd_c9_1 bnd_a539)) &
% 17.60/17.19 ((~ bnd_c10_0 |
% 17.60/17.19 ((bnd_ndr1_0 & ~ bnd_c2_1 bnd_a540) & ~ bnd_c8_1 bnd_a540) &
% 17.60/17.19 (ALL X88.
% 17.60/17.19 bnd_ndr1_1 bnd_a540 -->
% 17.60/17.19 (bnd_c5_2 bnd_a540 X88 | bnd_c8_2 bnd_a540 X88) |
% 17.60/17.19 ~ bnd_c6_2 bnd_a540 X88)) |
% 17.60/17.19 ((bnd_ndr1_0 & ~ bnd_c5_1 bnd_a541) & ~ bnd_c8_1 bnd_a541) &
% 17.60/17.19 (ALL X89.
% 17.60/17.19 bnd_ndr1_1 bnd_a541 -->
% 17.60/17.19 (bnd_c1_2 bnd_a541 X89 | bnd_c3_2 bnd_a541 X89) |
% 17.60/17.19 bnd_c9_2 bnd_a541 X89))) &
% 17.60/17.19 ((~ bnd_c2_0 | ~ bnd_c7_0) |
% 17.60/17.19 (ALL X90.
% 17.60/17.19 bnd_ndr1_0 -->
% 17.60/17.19 bnd_c3_1 X90 |
% 17.60/17.19 (ALL X91.
% 17.60/17.19 bnd_ndr1_1 X90 -->
% 17.60/17.19 (bnd_c10_2 X90 X91 | ~ bnd_c1_2 X90 X91) |
% 17.60/17.19 ~ bnd_c2_2 X90 X91)))) &
% 17.60/17.19 ((~ bnd_c2_0 |
% 17.60/17.19 (ALL X92. bnd_ndr1_0 --> (bnd_c3_1 X92 | bnd_c5_1 X92) | bnd_c7_1 X92)) |
% 17.60/17.19 (bnd_ndr1_0 & ~ bnd_c10_1 bnd_a542) &
% 17.60/17.19 (ALL X93.
% 17.60/17.19 bnd_ndr1_1 bnd_a542 -->
% 17.60/17.19 bnd_c3_2 bnd_a542 X93 | ~ bnd_c6_2 bnd_a542 X93))) &
% 17.60/17.19 ((~ bnd_c2_0 |
% 17.60/17.19 ((bnd_ndr1_0 & bnd_c1_1 bnd_a543) &
% 17.60/17.19 (ALL X94.
% 17.60/17.19 bnd_ndr1_1 bnd_a543 -->
% 17.60/17.19 (bnd_c10_2 bnd_a543 X94 | bnd_c3_2 bnd_a543 X94) |
% 17.60/17.19 ~ bnd_c9_2 bnd_a543 X94)) &
% 17.60/17.19 (ALL X95.
% 17.60/17.19 bnd_ndr1_1 bnd_a543 -->
% 17.60/17.19 (bnd_c8_2 bnd_a543 X95 | bnd_c9_2 bnd_a543 X95) |
% 17.60/17.19 ~ bnd_c5_2 bnd_a543 X95)) |
% 17.60/17.20 ((bnd_ndr1_0 & bnd_c2_1 bnd_a544) & bnd_c6_1 bnd_a544) &
% 17.60/17.20 ~ bnd_c1_1 bnd_a544)) &
% 17.60/17.20 ((~ bnd_c3_0 |
% 17.60/17.20 (ALL X96. bnd_ndr1_0 --> bnd_c1_1 X96 | ~ bnd_c9_1 X96)) |
% 17.60/17.20 (ALL X97.
% 17.60/17.20 bnd_ndr1_0 -->
% 17.60/17.20 (bnd_c10_1 X97 | bnd_c3_1 X97) |
% 17.60/17.20 (ALL X98.
% 17.60/17.20 bnd_ndr1_1 X97 -->
% 17.60/17.20 (bnd_c6_2 X97 X98 | ~ bnd_c4_2 X97 X98) | ~ bnd_c9_2 X97 X98)))) &
% 17.60/17.20 ((~ bnd_c3_0 |
% 17.60/17.20 (ALL X99.
% 17.60/17.20 bnd_ndr1_0 -->
% 17.60/17.20 (ALL X100.
% 17.60/17.20 bnd_ndr1_1 X99 -->
% 17.60/17.20 (~ bnd_c10_2 X99 X100 | ~ bnd_c2_2 X99 X100) | ~ bnd_c8_2 X99 X100) |
% 17.60/17.20 ((bnd_ndr1_1 X99 & bnd_c4_2 X99 bnd_a545) & bnd_c6_2 X99 bnd_a545) &
% 17.60/17.20 ~ bnd_c8_2 X99 bnd_a545)) |
% 17.60/17.20 ((bnd_ndr1_0 & bnd_c3_1 bnd_a546) &
% 17.60/17.20 (ALL X101.
% 17.60/17.20 bnd_ndr1_1 bnd_a546 -->
% 17.60/17.20 (bnd_c1_2 bnd_a546 X101 | bnd_c3_2 bnd_a546 X101) |
% 17.60/17.20 bnd_c7_2 bnd_a546 X101)) &
% 17.60/17.20 (ALL X102.
% 17.60/17.20 bnd_ndr1_1 bnd_a546 -->
% 17.60/17.20 ~ bnd_c2_2 bnd_a546 X102 | ~ bnd_c3_2 bnd_a546 X102))) &
% 17.60/17.20 ((~ bnd_c3_0 |
% 17.60/17.20 (bnd_ndr1_0 & ~ bnd_c1_1 bnd_a547) &
% 17.60/17.20 ~ bnd_c8_1 bnd_a547) |
% 17.60/17.20 (((((bnd_ndr1_0 &
% 17.60/17.20 (ALL X103.
% 17.60/17.20 bnd_ndr1_1 bnd_a548 -->
% 17.60/17.20 (bnd_c4_2 bnd_a548 X103 | bnd_c5_2 bnd_a548 X103) |
% 17.60/17.20 bnd_c6_2 bnd_a548 X103)) &
% 17.60/17.20 (ALL X104.
% 17.60/17.20 bnd_ndr1_1 bnd_a548 -->
% 17.60/17.20 (bnd_c4_2 bnd_a548 X104 | bnd_c8_2 bnd_a548 X104) |
% 17.60/17.20 ~ bnd_c7_2 bnd_a548 X104)) &
% 17.60/17.20 bnd_ndr1_1 bnd_a548) &
% 17.60/17.20 bnd_c6_2 bnd_a548 bnd_a549) &
% 17.60/17.20 bnd_c9_2 bnd_a548 bnd_a549) &
% 17.60/17.20 ~ bnd_c5_2 bnd_a548 bnd_a549)) &
% 17.60/17.20 (~ bnd_c4_0 | ~ bnd_c9_0)) &
% 17.60/17.20 ((~ bnd_c4_0 | ~ bnd_c9_0) |
% 17.60/17.20 (ALL X105.
% 17.60/17.20 bnd_ndr1_0 -->
% 17.60/17.20 bnd_c4_1 X105 | bnd_c8_1 X105))) &
% 17.60/17.20 (~ bnd_c4_0 |
% 17.60/17.20 (ALL X106.
% 17.60/17.20 bnd_ndr1_0 -->
% 17.60/17.20 (bnd_c3_1 X106 |
% 17.60/17.20 (ALL X107.
% 17.60/17.20 bnd_ndr1_1 X106 -->
% 17.60/17.20 (bnd_c5_2 X106 X107 | ~ bnd_c10_2 X106 X107) | ~ bnd_c9_2 X106 X107)) |
% 17.60/17.20 ((bnd_ndr1_1 X106 &
% 17.60/17.20 ~ bnd_c10_2 X106 bnd_a550) &
% 17.60/17.20 ~ bnd_c5_2 X106 bnd_a550) &
% 17.60/17.20 ~ bnd_c7_2 X106 bnd_a550))) &
% 17.60/17.20 ((~ bnd_c4_0 |
% 17.60/17.20 (ALL X108.
% 17.60/17.20 bnd_ndr1_0 -->
% 17.60/17.20 (~ bnd_c10_1 X108 | ~ bnd_c3_1 X108) |
% 17.60/17.20 (ALL X109.
% 17.60/17.20 bnd_ndr1_1 X108 --> bnd_c1_2 X108 X109 | bnd_c5_2 X108 X109))) |
% 17.60/17.20 (ALL X110.
% 17.60/17.20 bnd_ndr1_0 -->
% 17.60/17.20 (~ bnd_c8_1 X110 |
% 17.60/17.20 (ALL X111.
% 17.60/17.20 bnd_ndr1_1 X110 --> bnd_c9_2 X110 X111 | ~ bnd_c6_2 X110 X111)) |
% 17.60/17.20 (ALL X112.
% 17.60/17.20 bnd_ndr1_1 X110 -->
% 17.60/17.20 (~ bnd_c1_2 X110 X112 | ~ bnd_c2_2 X110 X112) | ~ bnd_c8_2 X110 X112)))) &
% 17.60/17.20 (~ bnd_c5_0 |
% 17.60/17.20 (ALL X113.
% 17.60/17.20 bnd_ndr1_0 -->
% 17.60/17.20 ((ALL X114.
% 17.60/17.20 bnd_ndr1_1 X113 -->
% 17.60/17.20 (bnd_c5_2 X113 X114 | bnd_c9_2 X113 X114) | ~ bnd_c2_2 X113 X114) |
% 17.60/17.20 ((bnd_ndr1_1 X113 &
% 17.60/17.20 bnd_c1_2 X113 bnd_a551) &
% 17.60/17.20 bnd_c2_2 X113 bnd_a551) &
% 17.60/17.20 ~ bnd_c7_2 X113 bnd_a551) |
% 17.60/17.20 ((bnd_ndr1_1 X113 &
% 17.60/17.20 bnd_c3_2 X113 bnd_a552) &
% 17.60/17.20 ~ bnd_c10_2 X113 bnd_a552) &
% 17.60/17.20 ~ bnd_c4_2 X113 bnd_a552))) &
% 17.60/17.20 ((~ bnd_c5_0 | ~ bnd_c9_0) |
% 17.60/17.20 (ALL X115.
% 17.60/17.20 bnd_ndr1_0 -->
% 17.60/17.20 (bnd_c6_1 X115 | bnd_c7_1 X115) |
% 17.60/17.20 ~ bnd_c9_1 X115))) &
% 17.60/17.20 ((~ bnd_c5_0 | ~ bnd_c9_0) |
% 17.60/17.20 (((((bnd_ndr1_0 & bnd_c3_1 bnd_a553) &
% 17.60/17.20 bnd_c5_1 bnd_a553) &
% 17.60/17.20 bnd_ndr1_1 bnd_a553) &
% 17.60/17.20 bnd_c1_2 bnd_a553 bnd_a554) &
% 17.60/17.20 bnd_c2_2 bnd_a553 bnd_a554) &
% 17.60/17.20 ~ bnd_c3_2 bnd_a553 bnd_a554)) &
% 17.60/17.20 ((~ bnd_c5_0 |
% 17.60/17.20 (ALL X116.
% 17.60/17.20 bnd_ndr1_0 -->
% 17.60/17.20 (bnd_c1_1 X116 | ~ bnd_c7_1 X116) |
% 17.60/17.20 ((bnd_ndr1_1 X116 &
% 17.60/17.20 bnd_c1_2 X116 bnd_a555) &
% 17.60/17.20 ~ bnd_c2_2 X116 bnd_a555) &
% 17.60/17.20 ~ bnd_c6_2 X116 bnd_a555)) |
% 17.60/17.20 (bnd_ndr1_0 &
% 17.60/17.20 (ALL X117.
% 17.60/17.20 bnd_ndr1_1 bnd_a556 -->
% 17.60/17.20 (bnd_c1_2 bnd_a556 X117 |
% 17.60/17.20 bnd_c5_2 bnd_a556 X117) |
% 17.60/17.20 ~ bnd_c6_2 bnd_a556 X117)) &
% 17.60/17.20 (ALL X118.
% 17.60/17.20 bnd_ndr1_1 bnd_a556 -->
% 17.60/17.20 (bnd_c10_2 bnd_a556 X118 |
% 17.60/17.20 ~ bnd_c6_2 bnd_a556 X118) |
% 17.60/17.20 ~ bnd_c8_2 bnd_a556 X118))) &
% 17.60/17.20 ((~ bnd_c5_0 |
% 17.60/17.20 (ALL X119.
% 17.60/17.20 bnd_ndr1_0 -->
% 17.60/17.20 (bnd_c2_1 X119 | ~ bnd_c8_1 X119) |
% 17.60/17.20 ((bnd_ndr1_1 X119 &
% 17.60/17.20 bnd_c10_2 X119 bnd_a557) &
% 17.60/17.20 bnd_c5_2 X119 bnd_a557) &
% 17.60/17.20 ~ bnd_c4_2 X119 bnd_a557)) |
% 17.60/17.20 ((bnd_ndr1_0 & bnd_c4_1 bnd_a558) &
% 17.60/17.20 ~ bnd_c9_1 bnd_a558) &
% 17.60/17.20 (ALL X120.
% 17.60/17.20 bnd_ndr1_1 bnd_a558 -->
% 17.60/17.20 (bnd_c4_2 bnd_a558 X120 |
% 17.60/17.20 bnd_c9_2 bnd_a558 X120) |
% 17.60/17.20 ~ bnd_c3_2 bnd_a558 X120))) &
% 17.60/17.20 ((~ bnd_c5_0 |
% 17.60/17.20 (ALL X121.
% 17.60/17.20 bnd_ndr1_0 -->
% 17.60/17.20 (bnd_c7_1 X121 |
% 17.60/17.20 (ALL X122.
% 17.60/17.20 bnd_ndr1_1 X121 -->
% 17.60/17.20 bnd_c10_2 X121 X122 |
% 17.60/17.20 ~ bnd_c5_2 X121 X122)) |
% 17.60/17.20 ((bnd_ndr1_1 X121 & bnd_c6_2 X121 bnd_a559) &
% 17.60/17.20 bnd_c8_2 X121 bnd_a559) &
% 17.60/17.20 ~ bnd_c2_2 X121 bnd_a559)) |
% 17.60/17.20 (ALL X123.
% 17.60/17.20 bnd_ndr1_0 -->
% 17.60/17.20 (~ bnd_c5_1 X123 |
% 17.60/17.20 ((bnd_ndr1_1 X123 & bnd_c2_2 X123 bnd_a560) &
% 17.60/17.20 bnd_c5_2 X123 bnd_a560) &
% 17.60/17.20 bnd_c6_2 X123 bnd_a560) |
% 17.60/17.20 ((bnd_ndr1_1 X123 & ~ bnd_c1_2 X123 bnd_a561) &
% 17.60/17.20 ~ bnd_c8_2 X123 bnd_a561) &
% 17.60/17.20 ~ bnd_c9_2 X123 bnd_a561))) &
% 17.60/17.20 ((~ bnd_c5_0 |
% 17.60/17.20 (ALL X124.
% 17.60/17.20 bnd_ndr1_0 -->
% 17.60/17.20 (bnd_c8_1 X124 | ~ bnd_c3_1 X124) |
% 17.60/17.20 (ALL X125.
% 17.60/17.20 bnd_ndr1_1 X124 -->
% 17.60/17.20 (bnd_c4_2 X124 X125 | bnd_c6_2 X124 X125) |
% 17.60/17.20 bnd_c8_2 X124 X125))) |
% 17.60/17.20 ((bnd_ndr1_0 & bnd_c7_1 bnd_a562) &
% 17.60/17.20 ~ bnd_c10_1 bnd_a562) &
% 17.60/17.20 (ALL X126.
% 17.60/17.20 bnd_ndr1_1 bnd_a562 -->
% 17.60/17.20 (bnd_c2_2 bnd_a562 X126 |
% 17.60/17.20 ~ bnd_c10_2 bnd_a562 X126) |
% 17.60/17.20 ~ bnd_c8_2 bnd_a562 X126))) &
% 17.60/17.20 ((~ bnd_c5_0 |
% 17.60/17.20 (ALL X127.
% 17.60/17.20 bnd_ndr1_0 -->
% 17.60/17.20 (~ bnd_c5_1 X127 |
% 17.60/17.20 (ALL X128.
% 17.60/17.20 bnd_ndr1_1 X127 -->
% 17.60/17.20 (bnd_c10_2 X127 X128 |
% 17.60/17.20 ~ bnd_c5_2 X127 X128) |
% 17.60/17.20 ~ bnd_c6_2 X127 X128)) |
% 17.60/17.20 (ALL X129.
% 17.60/17.20 bnd_ndr1_1 X127 -->
% 17.60/17.20 bnd_c5_2 X127 X129 |
% 17.60/17.20 ~ bnd_c4_2 X127 X129))) |
% 17.60/17.20 ((bnd_ndr1_0 & bnd_c4_1 bnd_a563) &
% 17.60/17.20 ~ bnd_c8_1 bnd_a563) &
% 17.60/17.20 (ALL X130.
% 17.60/17.20 bnd_ndr1_1 bnd_a563 -->
% 17.60/17.20 (bnd_c6_2 bnd_a563 X130 |
% 17.60/17.20 ~ bnd_c10_2 bnd_a563 X130) |
% 17.60/17.20 ~ bnd_c2_2 bnd_a563 X130))) &
% 17.60/17.20 (~ bnd_c5_0 |
% 17.60/17.20 ((((bnd_ndr1_0 & bnd_c10_1 bnd_a564) &
% 17.60/17.20 ~ bnd_c1_1 bnd_a564) &
% 17.60/17.20 bnd_ndr1_1 bnd_a564) &
% 17.60/17.20 bnd_c10_2 bnd_a564 bnd_a565) &
% 17.60/17.20 bnd_c4_2 bnd_a564 bnd_a565)) &
% 17.60/17.20 ((~ bnd_c5_0 |
% 17.60/17.20 ((((bnd_ndr1_0 & bnd_c4_1 bnd_a566) &
% 17.60/17.20 (ALL X131.
% 17.60/17.20 bnd_ndr1_1 bnd_a566 -->
% 17.60/17.20 (~ bnd_c10_2 bnd_a566 X131 |
% 17.60/17.20 ~ bnd_c6_2 bnd_a566 X131) |
% 17.60/17.20 ~ bnd_c8_2 bnd_a566 X131)) &
% 17.60/17.20 bnd_ndr1_1 bnd_a566) &
% 17.60/17.20 bnd_c8_2 bnd_a566 bnd_a567) &
% 17.60/17.20 ~ bnd_c7_2 bnd_a566 bnd_a567) |
% 17.60/17.20 ((((((((bnd_ndr1_0 & ~ bnd_c7_1 bnd_a568) &
% 17.60/17.20 bnd_ndr1_1 bnd_a568) &
% 17.60/17.20 bnd_c10_2 bnd_a568 bnd_a569) &
% 17.60/17.20 bnd_c3_2 bnd_a568 bnd_a569) &
% 17.60/17.20 bnd_c9_2 bnd_a568 bnd_a569) &
% 17.60/17.20 bnd_ndr1_1 bnd_a568) &
% 17.60/17.20 bnd_c5_2 bnd_a568 bnd_a570) &
% 17.60/17.20 bnd_c8_2 bnd_a568 bnd_a570) &
% 17.60/17.20 ~ bnd_c7_2 bnd_a568 bnd_a570)) &
% 17.60/17.20 (((bnd_ndr1_0 & bnd_c1_1 bnd_a571) & bnd_c6_1 bnd_a571) &
% 17.60/17.20 bnd_c7_1 bnd_a571 |
% 17.60/17.20 (((((bnd_ndr1_0 & ~ bnd_c1_1 bnd_a572) &
% 17.60/17.20 (ALL X132.
% 17.60/17.20 bnd_ndr1_1 bnd_a572 -->
% 17.60/17.20 (bnd_c9_2 bnd_a572 X132 |
% 17.60/17.20 ~ bnd_c2_2 bnd_a572 X132) |
% 17.60/17.20 ~ bnd_c7_2 bnd_a572 X132)) &
% 17.60/17.20 bnd_ndr1_1 bnd_a572) &
% 17.60/17.20 bnd_c8_2 bnd_a572 bnd_a573) &
% 17.60/17.20 ~ bnd_c1_2 bnd_a572 bnd_a573) &
% 17.60/17.20 ~ bnd_c10_2 bnd_a572 bnd_a573)) &
% 17.60/17.20 (~ bnd_c7_0 |
% 17.60/17.20 ((bnd_ndr1_0 & bnd_c1_1 bnd_a574) &
% 17.60/17.20 ~ bnd_c10_1 bnd_a574) &
% 17.60/17.20 ~ bnd_c3_1 bnd_a574)) &
% 17.60/17.20 (~ bnd_c9_0 |
% 17.60/17.20 ((bnd_ndr1_0 &
% 17.60/17.20 (ALL X133.
% 17.60/17.20 bnd_ndr1_1 bnd_a575 -->
% 17.60/17.20 (bnd_c1_2 bnd_a575 X133 | bnd_c10_2 bnd_a575 X133) |
% 17.60/17.20 bnd_c7_2 bnd_a575 X133)) &
% 17.60/17.20 (ALL X134.
% 17.60/17.20 bnd_ndr1_1 bnd_a575 -->
% 17.60/17.20 (bnd_c1_2 bnd_a575 X134 | ~ bnd_c6_2 bnd_a575 X134) |
% 17.60/17.20 ~ bnd_c9_2 bnd_a575 X134)) &
% 17.60/17.20 (ALL X135.
% 17.60/17.20 bnd_ndr1_1 bnd_a575 -->
% 17.60/17.20 ~ bnd_c5_2 bnd_a575 X135 |
% 17.60/17.20 ~ bnd_c7_2 bnd_a575 X135))) &
% 17.60/17.20 (((ALL X136.
% 17.60/17.20 bnd_ndr1_0 -->
% 17.60/17.20 (bnd_c1_1 X136 | bnd_c2_1 X136) | ~ bnd_c7_1 X136) |
% 17.60/17.20 (ALL X137.
% 17.60/17.20 bnd_ndr1_0 -->
% 17.60/17.20 (bnd_c8_1 X137 | ~ bnd_c1_1 X137) |
% 17.60/17.20 ((bnd_ndr1_1 X137 & bnd_c5_2 X137 bnd_a576) &
% 17.60/17.20 ~ bnd_c6_2 X137 bnd_a576) &
% 17.60/17.20 ~ bnd_c7_2 X137 bnd_a576)) |
% 17.60/17.20 (ALL X138.
% 17.60/17.20 bnd_ndr1_0 -->
% 17.60/17.20 ((ALL X139.
% 17.60/17.20 bnd_ndr1_1 X138 -->
% 17.60/17.20 (bnd_c9_2 X138 X139 | ~ bnd_c1_2 X138 X139) |
% 17.60/17.20 ~ bnd_c3_2 X138 X139) |
% 17.60/17.20 (ALL X140.
% 17.60/17.20 bnd_ndr1_1 X138 -->
% 17.60/17.20 (~ bnd_c4_2 X138 X140 | ~ bnd_c8_2 X138 X140) |
% 17.60/17.20 ~ bnd_c9_2 X138 X140)) |
% 17.60/17.20 ((bnd_ndr1_1 X138 & bnd_c3_2 X138 bnd_a577) &
% 17.60/17.20 bnd_c9_2 X138 bnd_a577) &
% 17.60/17.20 ~ bnd_c8_2 X138 bnd_a577))) &
% 17.60/17.20 (((ALL X141.
% 17.60/17.20 bnd_ndr1_0 -->
% 17.60/17.20 (bnd_c1_1 X141 | bnd_c6_1 X141) |
% 17.60/17.20 ((bnd_ndr1_1 X141 & bnd_c4_2 X141 bnd_a578) &
% 17.60/17.20 bnd_c5_2 X141 bnd_a578) &
% 17.60/17.20 bnd_c9_2 X141 bnd_a578) |
% 17.60/17.20 (ALL X142.
% 17.60/17.20 bnd_ndr1_0 -->
% 17.60/17.20 (~ bnd_c3_1 X142 |
% 17.60/17.20 (ALL X143.
% 17.60/17.20 bnd_ndr1_1 X142 --> ~ bnd_c10_2 X142 X143)) |
% 17.60/17.20 (ALL X144.
% 17.60/17.20 bnd_ndr1_1 X142 -->
% 17.60/17.20 (~ bnd_c1_2 X142 X144 | ~ bnd_c10_2 X142 X144) |
% 17.60/17.20 ~ bnd_c5_2 X142 X144))) |
% 17.60/17.20 (ALL X145.
% 17.60/17.20 bnd_ndr1_0 -->
% 17.60/17.20 (~ bnd_c4_1 X145 |
% 17.60/17.20 (ALL X146.
% 17.60/17.20 bnd_ndr1_1 X145 -->
% 17.60/17.20 (bnd_c8_2 X145 X146 | ~ bnd_c10_2 X145 X146) |
% 17.60/17.20 ~ bnd_c4_2 X145 X146)) |
% 17.60/17.20 (ALL X147.
% 17.60/17.20 bnd_ndr1_1 X145 -->
% 17.60/17.20 (~ bnd_c5_2 X145 X147 | ~ bnd_c6_2 X145 X147) |
% 17.60/17.20 ~ bnd_c8_2 X145 X147)))) &
% 17.60/17.20 (((ALL X148.
% 17.60/17.20 bnd_ndr1_0 -->
% 17.60/17.20 (bnd_c10_1 X148 | ~ bnd_c3_1 X148) | ~ bnd_c5_1 X148) |
% 17.60/17.20 (((((bnd_ndr1_0 & bnd_c7_1 bnd_a579) &
% 17.60/17.20 ~ bnd_c1_1 bnd_a579) &
% 17.60/17.20 bnd_ndr1_1 bnd_a579) &
% 17.60/17.20 ~ bnd_c1_2 bnd_a579 bnd_a580) &
% 17.60/17.20 ~ bnd_c3_2 bnd_a579 bnd_a580) &
% 17.60/17.20 ~ bnd_c9_2 bnd_a579 bnd_a580) |
% 17.60/17.20 ((((bnd_ndr1_0 & ~ bnd_c2_1 bnd_a581) &
% 17.60/17.20 (ALL X149.
% 17.60/17.20 bnd_ndr1_1 bnd_a581 -->
% 17.60/17.20 (bnd_c1_2 bnd_a581 X149 | ~ bnd_c4_2 bnd_a581 X149) |
% 17.60/17.20 ~ bnd_c8_2 bnd_a581 X149)) &
% 17.60/17.20 bnd_ndr1_1 bnd_a581) &
% 17.60/17.20 bnd_c4_2 bnd_a581 bnd_a582) &
% 17.60/17.20 ~ bnd_c10_2 bnd_a581 bnd_a582)) &
% 17.60/17.20 (((ALL X150.
% 17.60/17.20 bnd_ndr1_0 -->
% 17.60/17.20 bnd_c10_1 X150 |
% 17.60/17.20 (ALL X151.
% 17.60/17.20 bnd_ndr1_1 X150 -->
% 17.60/17.20 (bnd_c10_2 X150 X151 | bnd_c2_2 X150 X151) |
% 17.60/17.20 bnd_c8_2 X150 X151)) |
% 17.60/17.20 (ALL X152.
% 17.60/17.20 bnd_ndr1_0 -->
% 17.60/17.20 (~ bnd_c3_1 X152 |
% 17.60/17.20 (ALL X153.
% 17.60/17.20 bnd_ndr1_1 X152 -->
% 17.60/17.20 (bnd_c5_2 X152 X153 | bnd_c6_2 X152 X153) |
% 17.60/17.20 ~ bnd_c7_2 X152 X153)) |
% 17.60/17.20 ((bnd_ndr1_1 X152 & bnd_c10_2 X152 bnd_a583) &
% 17.60/17.20 bnd_c4_2 X152 bnd_a583) &
% 17.60/17.20 ~ bnd_c6_2 X152 bnd_a583)) |
% 17.60/17.20 (((((bnd_ndr1_0 & ~ bnd_c8_1 bnd_a584) &
% 17.60/17.20 (ALL X154.
% 17.60/17.20 bnd_ndr1_1 bnd_a584 -->
% 17.60/17.20 (bnd_c2_2 bnd_a584 X154 | bnd_c9_2 bnd_a584 X154) |
% 17.60/17.20 ~ bnd_c7_2 bnd_a584 X154)) &
% 17.60/17.20 bnd_ndr1_1 bnd_a584) &
% 17.60/17.20 bnd_c7_2 bnd_a584 bnd_a585) &
% 17.60/17.20 ~ bnd_c2_2 bnd_a584 bnd_a585) &
% 17.60/17.20 ~ bnd_c4_2 bnd_a584 bnd_a585)) &
% 17.60/17.20 (((ALL X155.
% 17.60/17.20 bnd_ndr1_0 -->
% 17.60/17.20 (bnd_c3_1 X155 | ~ bnd_c1_1 X155) | ~ bnd_c2_1 X155) |
% 17.60/17.20 (((((bnd_ndr1_0 & bnd_c1_1 bnd_a586) & ~ bnd_c7_1 bnd_a586) &
% 17.60/17.20 bnd_ndr1_1 bnd_a586) &
% 17.60/17.20 bnd_c9_2 bnd_a586 bnd_a587) &
% 17.60/17.20 ~ bnd_c3_2 bnd_a586 bnd_a587) &
% 17.60/17.20 ~ bnd_c8_2 bnd_a586 bnd_a587) |
% 17.60/17.20 (((((bnd_ndr1_0 & ~ bnd_c1_1 bnd_a588) & ~ bnd_c3_1 bnd_a588) &
% 17.60/17.20 bnd_ndr1_1 bnd_a588) &
% 17.60/17.20 bnd_c6_2 bnd_a588 bnd_a589) &
% 17.60/17.20 ~ bnd_c1_2 bnd_a588 bnd_a589) &
% 17.60/17.20 ~ bnd_c3_2 bnd_a588 bnd_a589)) &
% 17.60/17.20 ((ALL X156.
% 17.60/17.20 bnd_ndr1_0 -->
% 17.60/17.20 (bnd_c3_1 X156 |
% 17.60/17.20 (ALL X157.
% 17.60/17.20 bnd_ndr1_1 X156 -->
% 17.60/17.20 (bnd_c3_2 X156 X157 | ~ bnd_c5_2 X156 X157) |
% 17.60/17.20 ~ bnd_c9_2 X156 X157)) |
% 17.60/17.20 (bnd_ndr1_1 X156 & ~ bnd_c10_2 X156 bnd_a590) &
% 17.60/17.20 ~ bnd_c9_2 X156 bnd_a590) |
% 17.60/17.20 (((((bnd_ndr1_0 & bnd_c6_1 bnd_a591) & bnd_c9_1 bnd_a591) &
% 17.60/17.20 bnd_ndr1_1 bnd_a591) &
% 17.60/17.20 bnd_c4_2 bnd_a591 bnd_a592) &
% 17.60/17.20 ~ bnd_c1_2 bnd_a591 bnd_a592) &
% 17.60/17.20 ~ bnd_c7_2 bnd_a591 bnd_a592)) &
% 17.60/17.20 (((ALL X158.
% 17.60/17.20 bnd_ndr1_0 -->
% 17.60/17.20 (bnd_c4_1 X158 |
% 17.60/17.20 ((bnd_ndr1_1 X158 & bnd_c5_2 X158 bnd_a593) &
% 17.60/17.20 ~ bnd_c6_2 X158 bnd_a593) &
% 17.60/17.20 ~ bnd_c7_2 X158 bnd_a593) |
% 17.60/17.20 (bnd_ndr1_1 X158 & bnd_c9_2 X158 bnd_a594) &
% 17.60/17.20 ~ bnd_c10_2 X158 bnd_a594) |
% 17.60/17.20 (ALL X159.
% 17.60/17.20 bnd_ndr1_0 -->
% 17.60/17.20 (~ bnd_c5_1 X159 | ~ bnd_c8_1 X159) |
% 17.60/17.20 (ALL X160.
% 17.60/17.20 bnd_ndr1_1 X159 -->
% 17.60/17.20 bnd_c1_2 X159 X160 | ~ bnd_c8_2 X159 X160))) |
% 17.60/17.20 ((bnd_ndr1_0 & ~ bnd_c3_1 bnd_a595) & ~ bnd_c9_1 bnd_a595) &
% 17.70/17.20 (ALL X161.
% 17.70/17.20 bnd_ndr1_1 bnd_a595 -->
% 17.70/17.20 bnd_c1_2 bnd_a595 X161 | bnd_c9_2 bnd_a595 X161))) &
% 17.70/17.20 ((ALL X162.
% 17.70/17.20 bnd_ndr1_0 -->
% 17.70/17.20 (bnd_c5_1 X162 | bnd_c8_1 X162) |
% 17.70/17.20 (bnd_ndr1_1 X162 & ~ bnd_c2_2 X162 bnd_a596) &
% 17.70/17.20 ~ bnd_c5_2 X162 bnd_a596) |
% 17.70/17.20 (ALL X163.
% 17.70/17.20 bnd_ndr1_0 -->
% 17.70/17.20 ~ bnd_c7_1 X163 |
% 17.70/17.20 ((bnd_ndr1_1 X163 & bnd_c10_2 X163 bnd_a597) &
% 17.70/17.20 ~ bnd_c3_2 X163 bnd_a597) &
% 17.70/17.20 ~ bnd_c5_2 X163 bnd_a597))) &
% 17.70/17.20 (((ALL X164.
% 17.70/17.20 bnd_ndr1_0 -->
% 17.70/17.20 (~ bnd_c10_1 X164 |
% 17.70/17.20 ((bnd_ndr1_1 X164 & bnd_c2_2 X164 bnd_a598) &
% 17.70/17.20 ~ bnd_c10_2 X164 bnd_a598) &
% 17.70/17.20 ~ bnd_c6_2 X164 bnd_a598) |
% 17.70/17.20 ((bnd_ndr1_1 X164 & bnd_c6_2 X164 bnd_a599) &
% 17.70/17.20 ~ bnd_c1_2 X164 bnd_a599) &
% 17.70/17.20 ~ bnd_c10_2 X164 bnd_a599) |
% 17.70/17.20 (ALL X165.
% 17.70/17.20 bnd_ndr1_0 -->
% 17.70/17.20 ((ALL X166.
% 17.70/17.20 bnd_ndr1_1 X165 -->
% 17.70/17.20 (bnd_c10_2 X165 X166 | ~ bnd_c3_2 X165 X166) |
% 17.70/17.20 ~ bnd_c6_2 X165 X166) |
% 17.70/17.20 (ALL X167.
% 17.70/17.20 bnd_ndr1_1 X165 -->
% 17.70/17.20 (bnd_c9_2 X165 X167 | ~ bnd_c4_2 X165 X167) |
% 17.70/17.20 ~ bnd_c8_2 X165 X167)) |
% 17.70/17.20 (ALL X168.
% 17.70/17.20 bnd_ndr1_1 X165 -->
% 17.70/17.20 (~ bnd_c5_2 X165 X168 | ~ bnd_c8_2 X165 X168) |
% 17.70/17.20 ~ bnd_c9_2 X165 X168))) |
% 17.70/17.20 (bnd_ndr1_0 & bnd_c10_1 bnd_a600) &
% 17.70/17.20 (ALL X169.
% 17.70/17.20 bnd_ndr1_1 bnd_a600 -->
% 17.70/17.20 bnd_c10_2 bnd_a600 X169 | ~ bnd_c1_2 bnd_a600 X169))) &
% 17.70/17.20 (((ALL X170.
% 17.70/17.20 bnd_ndr1_0 -->
% 17.70/17.20 (~ bnd_c4_1 X170 |
% 17.70/17.20 ((bnd_ndr1_1 X170 & bnd_c1_2 X170 bnd_a601) &
% 17.70/17.20 ~ bnd_c2_2 X170 bnd_a601) &
% 17.70/17.20 ~ bnd_c4_2 X170 bnd_a601) |
% 17.70/17.20 ((bnd_ndr1_1 X170 & bnd_c6_2 X170 bnd_a602) &
% 17.70/17.20 bnd_c7_2 X170 bnd_a602) &
% 17.70/17.20 bnd_c9_2 X170 bnd_a602) |
% 17.70/17.20 ((bnd_ndr1_0 & ~ bnd_c10_1 bnd_a603) & ~ bnd_c6_1 bnd_a603) &
% 17.70/17.20 ~ bnd_c8_1 bnd_a603) |
% 17.70/17.20 ((((((((bnd_ndr1_0 & ~ bnd_c6_1 bnd_a604) & bnd_ndr1_1 bnd_a604) &
% 17.70/17.20 bnd_c7_2 bnd_a604 bnd_a605) &
% 17.70/17.20 ~ bnd_c3_2 bnd_a604 bnd_a605) &
% 17.70/17.20 ~ bnd_c4_2 bnd_a604 bnd_a605) &
% 17.70/17.20 bnd_ndr1_1 bnd_a604) &
% 17.70/17.20 bnd_c8_2 bnd_a604 bnd_a606) &
% 17.70/17.20 ~ bnd_c2_2 bnd_a604 bnd_a606) &
% 17.70/17.20 ~ bnd_c3_2 bnd_a604 bnd_a606)) &
% 17.70/17.20 (((ALL X171.
% 17.70/17.20 bnd_ndr1_0 -->
% 17.70/17.20 (~ bnd_c9_1 X171 |
% 17.70/17.20 (ALL X172.
% 17.70/17.20 bnd_ndr1_1 X171 -->
% 17.70/17.20 (bnd_c2_2 X171 X172 | bnd_c4_2 X171 X172) |
% 17.70/17.20 bnd_c9_2 X171 X172)) |
% 17.70/17.20 ((bnd_ndr1_1 X171 & ~ bnd_c2_2 X171 bnd_a607) &
% 17.70/17.20 ~ bnd_c3_2 X171 bnd_a607) &
% 17.70/17.20 ~ bnd_c4_2 X171 bnd_a607) |
% 17.70/17.20 (bnd_ndr1_0 & bnd_c4_1 bnd_a608) &
% 17.70/17.20 (ALL X173.
% 17.70/17.20 bnd_ndr1_1 bnd_a608 -->
% 17.70/17.20 (bnd_c2_2 bnd_a608 X173 | ~ bnd_c10_2 bnd_a608 X173) |
% 17.70/17.20 ~ bnd_c7_2 bnd_a608 X173)) |
% 17.70/17.20 ((bnd_ndr1_0 & ~ bnd_c3_1 bnd_a609) &
% 17.70/17.20 (ALL X174.
% 17.70/17.20 bnd_ndr1_1 bnd_a609 -->
% 17.70/17.20 (bnd_c10_2 bnd_a609 X174 | bnd_c7_2 bnd_a609 X174) |
% 17.70/17.20 bnd_c8_2 bnd_a609 X174)) &
% 17.70/17.20 (ALL X175.
% 17.70/17.20 bnd_ndr1_1 bnd_a609 -->
% 17.70/17.20 bnd_c4_2 bnd_a609 X175 | ~ bnd_c8_2 bnd_a609 X175))) &
% 17.70/17.20 (bnd_ndr1_0 & bnd_c1_1 bnd_a610 |
% 17.70/17.20 (((((bnd_ndr1_0 & bnd_c6_1 bnd_a611) &
% 17.70/17.20 (ALL X176.
% 17.70/17.20 bnd_ndr1_1 bnd_a611 -->
% 17.70/17.20 (bnd_c5_2 bnd_a611 X176 | ~ bnd_c6_2 bnd_a611 X176) |
% 17.70/17.20 ~ bnd_c9_2 bnd_a611 X176)) &
% 17.70/17.20 bnd_ndr1_1 bnd_a611) &
% 17.70/17.20 bnd_c1_2 bnd_a611 bnd_a612) &
% 17.70/17.20 ~ bnd_c5_2 bnd_a611 bnd_a612) &
% 17.70/17.20 ~ bnd_c7_2 bnd_a611 bnd_a612)) &
% 17.70/17.20 ((((((bnd_ndr1_0 & bnd_c3_1 bnd_a613) & bnd_c8_1 bnd_a613) &
% 17.70/17.20 bnd_ndr1_1 bnd_a613) &
% 17.70/17.20 ~ bnd_c2_2 bnd_a613 bnd_a614) &
% 17.70/17.20 ~ bnd_c4_2 bnd_a613 bnd_a614) &
% 17.70/17.20 ~ bnd_c7_2 bnd_a613 bnd_a614 |
% 17.70/17.20 ((bnd_ndr1_0 & bnd_c7_1 bnd_a615) & ~ bnd_c1_1 bnd_a615) &
% 17.70/17.20 (ALL X177.
% 17.70/17.20 bnd_ndr1_1 bnd_a615 -->
% 17.70/17.20 (~ bnd_c4_2 bnd_a615 X177 | ~ bnd_c7_2 bnd_a615 X177) |
% 17.70/17.20 ~ bnd_c9_2 bnd_a615 X177))) &
% 17.70/17.20 ((((bnd_ndr1_0 & bnd_c6_1 bnd_a616) & ~ bnd_c1_1 bnd_a616) &
% 17.70/17.20 (ALL X178.
% 17.70/17.20 bnd_ndr1_1 bnd_a616 -->
% 17.70/17.20 (bnd_c10_2 bnd_a616 X178 | bnd_c3_2 bnd_a616 X178) |
% 17.70/17.20 ~ bnd_c6_2 bnd_a616 X178) |
% 17.70/17.20 (((((bnd_ndr1_0 & bnd_c6_1 bnd_a617) &
% 17.70/17.20 (ALL X179.
% 17.70/17.20 bnd_ndr1_1 bnd_a617 -->
% 17.70/17.20 (~ bnd_c10_2 bnd_a617 X179 | ~ bnd_c4_2 bnd_a617 X179) |
% 17.70/17.20 ~ bnd_c5_2 bnd_a617 X179)) &
% 17.70/17.20 bnd_ndr1_1 bnd_a617) &
% 17.70/17.20 bnd_c10_2 bnd_a617 bnd_a618) &
% 17.70/17.20 ~ bnd_c8_2 bnd_a617 bnd_a618) &
% 17.70/17.20 ~ bnd_c9_2 bnd_a617 bnd_a618) |
% 17.70/17.20 ((bnd_ndr1_0 & bnd_c8_1 bnd_a619) & ~ bnd_c3_1 bnd_a619) &
% 17.70/17.20 (ALL X180.
% 17.70/17.20 bnd_ndr1_1 bnd_a619 -->
% 17.70/17.20 (bnd_c3_2 bnd_a619 X180 | ~ bnd_c4_2 bnd_a619 X180) |
% 17.70/17.20 ~ bnd_c7_2 bnd_a619 X180)))
% 17.70/17.20 Adding axioms...
% 17.70/17.22 Typedef.type_definition_def
% 49.97/49.45 ...done.
% 49.97/49.48 Ground types: ?'b, TPTP_Interpret.ind
% 49.97/49.48 Translating term (sizes: 1, 1) ...
% 76.45/75.90 Invoking SAT solver...
% 76.45/75.91 No model exists.
% 76.45/75.91 Translating term (sizes: 2, 1) ...
% 103.73/103.03 Invoking SAT solver...
% 103.73/103.03 No model exists.
% 103.73/103.03 Translating term (sizes: 1, 2) ...
% 152.55/151.70 Invoking SAT solver...
% 157.58/156.65 Model found:
% 157.58/156.65 Size of types: ?'b: 1, TPTP_Interpret.ind: 2
% 157.58/156.65 bnd_a619: ??.TPTP_Interpret.ind1
% 157.58/156.65 bnd_a618: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a617: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a616: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a615: ??.TPTP_Interpret.ind1
% 157.58/156.65 bnd_a614: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a613: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a612: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a611: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a610: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a609: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a608: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a607: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a606: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a605: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a604: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a603: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a602: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a601: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a600: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a599: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a598: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a597: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a596: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a595: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a594: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a593: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a592: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a591: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a590: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a589: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a588: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a587: ??.TPTP_Interpret.ind1
% 157.58/156.65 bnd_a586: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a585: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a584: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a583: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a582: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a581: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a580: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a579: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a578: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a577: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a576: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a575: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a574: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a573: ??.TPTP_Interpret.ind1
% 157.58/156.65 bnd_a572: ??.TPTP_Interpret.ind1
% 157.58/156.65 bnd_a571: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a570: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a569: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a568: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a567: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a566: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a565: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a564: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a563: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a562: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a561: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a560: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a559: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a558: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a557: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a556: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a555: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a554: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a553: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a552: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a551: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a550: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a549: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a548: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a547: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a546: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a545: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a544: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a543: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a542: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a541: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a540: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a539: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a538: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a537: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a536: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a535: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a534: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a533: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a532: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a531: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a530: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a529: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a528: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a527: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a526: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a525: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a524: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a523: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a522: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a521: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a520: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a519: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a518: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a517: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a516: ??.TPTP_Interpret.ind1
% 157.58/156.65 bnd_a515: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a514: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a513: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a512: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a511: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a510: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a509: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a508: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a507: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a506: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a505: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a504: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a503: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a502: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a501: ??.TPTP_Interpret.ind1
% 157.58/156.65 bnd_a500: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a499: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a498: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a497: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a496: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a495: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a494: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a493: ??.TPTP_Interpret.ind0
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% 157.58/156.65 bnd_a491: ??.TPTP_Interpret.ind1
% 157.58/156.65 bnd_a490: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a489: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a488: ??.TPTP_Interpret.ind0
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% 157.58/156.65 bnd_a485: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a484: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a483: ??.TPTP_Interpret.ind0
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% 157.58/156.65 bnd_a480: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a479: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a478: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a477: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a476: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a475: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a474: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a473: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a472: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a471: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a470: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a469: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a468: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a467: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a466: ??.TPTP_Interpret.ind1
% 157.58/156.65 bnd_a465: ??.TPTP_Interpret.ind1
% 157.58/156.65 bnd_a464: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a463: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a462: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a461: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a460: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a459: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a458: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a457: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a456: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a455: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a454: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a453: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_c8_1: {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, True)}
% 157.58/156.65 bnd_a452: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a451: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a450: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a449: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a448: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a447: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a446: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_c10_1: {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, False)}
% 157.58/156.65 bnd_a445: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a444: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a443: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_c4_1: {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, False)}
% 157.58/156.65 bnd_c7_2: {(??.TPTP_Interpret.ind0,
% 157.58/156.65 {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, False)}),
% 157.58/156.65 (??.TPTP_Interpret.ind1,
% 157.58/156.65 {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, False)})}
% 157.58/156.65 bnd_a442: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_c5_1: {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, False)}
% 157.58/156.65 bnd_a441: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_c2_2: {(??.TPTP_Interpret.ind0,
% 157.58/156.65 {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, False)}),
% 157.58/156.65 (??.TPTP_Interpret.ind1,
% 157.58/156.65 {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, True)})}
% 157.58/156.65 bnd_a440: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_c7_0: False
% 157.58/156.65 bnd_a439: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_c4_0: True
% 157.58/156.65 bnd_a438: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_a437: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_c10_0: True
% 157.58/156.65 bnd_c9_1: {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, False)}
% 157.58/156.65 bnd_c3_1: {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, False)}
% 157.58/156.65 bnd_a436: ??.TPTP_Interpret.ind1
% 157.58/156.65 bnd_c8_2: {(??.TPTP_Interpret.ind0,
% 157.58/156.65 {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, False)}),
% 157.58/156.65 (??.TPTP_Interpret.ind1,
% 157.58/156.65 {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, True)})}
% 157.58/156.65 bnd_a435: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_c9_2: {(??.TPTP_Interpret.ind0,
% 157.58/156.65 {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, True)}),
% 157.58/156.65 (??.TPTP_Interpret.ind1,
% 157.58/156.65 {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, True)})}
% 157.58/156.65 bnd_a434: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_c9_0: False
% 157.58/156.65 bnd_c3_2: {(??.TPTP_Interpret.ind0,
% 157.58/156.65 {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, False)}),
% 157.58/156.65 (??.TPTP_Interpret.ind1,
% 157.58/156.65 {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, True)})}
% 157.58/156.65 bnd_c1_1: {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, False)}
% 157.58/156.65 bnd_c3_0: False
% 157.58/156.65 bnd_a433: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_c7_1: {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, True)}
% 157.58/156.65 bnd_c6_1: {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, False)}
% 157.58/156.65 bnd_c2_0: True
% 157.58/156.65 bnd_c5_2: {(??.TPTP_Interpret.ind0,
% 157.58/156.65 {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, True)}),
% 157.58/156.65 (??.TPTP_Interpret.ind1,
% 157.58/156.65 {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, True)})}
% 157.58/156.65 bnd_c4_2: {(??.TPTP_Interpret.ind0,
% 157.58/156.65 {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, False)}),
% 157.58/156.65 (??.TPTP_Interpret.ind1,
% 157.58/156.65 {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, False)})}
% 157.58/156.65 bnd_a432: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_c10_2: {(??.TPTP_Interpret.ind0,
% 157.58/156.65 {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, True)}),
% 157.58/156.65 (??.TPTP_Interpret.ind1,
% 157.58/156.65 {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, False)})}
% 157.58/156.65 bnd_c6_2: {(??.TPTP_Interpret.ind0,
% 157.58/156.65 {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, False)}),
% 157.58/156.65 (??.TPTP_Interpret.ind1,
% 157.58/156.65 {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, True)})}
% 157.58/156.65 bnd_a431: ??.TPTP_Interpret.ind0
% 157.58/156.65 bnd_c1_2: {(??.TPTP_Interpret.ind0,
% 157.58/156.65 {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, True)}),
% 157.58/156.65 (??.TPTP_Interpret.ind1,
% 157.58/156.65 {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, False)})}
% 157.58/156.65 bnd_ndr1_1: {(??.TPTP_Interpret.ind0, True), (??.TPTP_Interpret.ind1, True)}
% 157.58/156.65 bnd_c2_1: {(??.TPTP_Interpret.ind0, False), (??.TPTP_Interpret.ind1, True)}
% 157.58/156.65 bnd_ndr1_0: True
% 157.58/156.65 bnd_c5_0: False
% 157.58/156.65 bnd_c1_0: False
% 157.58/156.65 bnd_c8_0: False
% 157.58/156.65 bnd_c6_0: True
% 157.58/156.65
% 157.58/156.65 % SZS status CounterSatisfiable
%------------------------------------------------------------------------------