TSTP Solution File: HWV091+1 by SuperZenon---0.0.1
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- Process Solution
%------------------------------------------------------------------------------
% File : SuperZenon---0.0.1
% Problem : HWV091+1 : TPTP v8.1.0. Released v6.1.0.
% Transfm : none
% Format : tptp:raw
% Command : run_super_zenon -p0 -itptp -om -max-time %d %s
% Computer : n005.cluster.edu
% Model : x86_64 x86_64
% CPU : Intel(R) Xeon(R) CPU E5-2620 v4 2.10GHz
% Memory : 8042.1875MB
% OS : Linux 3.10.0-693.el7.x86_64
% CPULimit : 300s
% WCLimit : 600s
% DateTime : Sat Jul 16 19:19:26 EDT 2022
% Result : Theorem 17.60s 17.80s
% Output : Proof 17.60s
% Verified :
% SZS Type : -
% Comments :
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%----WARNING: Could not form TPTP format derivation
%------------------------------------------------------------------------------
%----ORIGINAL SYSTEM OUTPUT
% 0.06/0.12 % Problem : HWV091+1 : TPTP v8.1.0. Released v6.1.0.
% 0.06/0.13 % Command : run_super_zenon -p0 -itptp -om -max-time %d %s
% 0.13/0.34 % Computer : n005.cluster.edu
% 0.13/0.34 % Model : x86_64 x86_64
% 0.13/0.34 % CPU : Intel(R) Xeon(R) CPU E5-2620 v4 @ 2.10GHz
% 0.13/0.34 % Memory : 8042.1875MB
% 0.13/0.34 % OS : Linux 3.10.0-693.el7.x86_64
% 0.13/0.34 % CPULimit : 300
% 0.13/0.34 % WCLimit : 600
% 0.13/0.34 % DateTime : Fri Jun 17 07:16:53 EDT 2022
% 0.13/0.34 % CPUTime :
% 17.60/17.80 % SZS status Theorem
% 17.60/17.80 (* PROOF-FOUND *)
% 17.60/17.80 (* BEGIN-PROOF *)
% 17.60/17.80 % SZS output start Proof
% 17.60/17.80 1. (-. (v22290 T_0)) (v22290 T_0) ### Axiom
% 17.60/17.80 2. (-. (-. (v22290 T_0))) (-. (v22290 T_0)) ### NotNot 1
% 17.60/17.80 3. (v22291 T_0) (-. (v22291 T_0)) ### Axiom
% 17.60/17.80 4. (v22292 T_0 (bitIndex0)) (-. (v22292 T_0 (bitIndex0))) ### Axiom
% 17.60/17.80 5. (v22296 T_0 (bitIndex9)) (-. (v22296 T_0 (bitIndex9))) ### Axiom
% 17.60/17.80 6. (All VarCurr, (-. (v22296 VarCurr (bitIndex9)))) (v22296 T_0 (bitIndex9)) ### All 5
% 17.60/17.80 7. ((v22295 T_0) /\ (v22296 T_0 (bitIndex9))) (All VarCurr, (-. (v22296 VarCurr (bitIndex9)))) ### And 6
% 17.60/17.80 8. (v22293 T_0) (All VarCurr, (-. (v22296 VarCurr (bitIndex9)))) ### Definition-Pseudo(v22293) 7
% 17.60/17.80 9. ((v22292 T_0 (bitIndex0)) <=> (v22293 T_0)) (All VarCurr, (-. (v22296 VarCurr (bitIndex9)))) (v22292 T_0 (bitIndex0)) ### Equiv 4 8
% 17.60/17.80 10. (All VarCurr, ((v22292 VarCurr (bitIndex0)) <=> (v22293 VarCurr))) (v22292 T_0 (bitIndex0)) (All VarCurr, (-. (v22296 VarCurr (bitIndex9)))) ### All 9
% 17.60/17.80 11. ((v22292 T_0 (bitIndex0)) /\ (v22292 T_0 (bitIndex1))) (All VarCurr, (-. (v22296 VarCurr (bitIndex9)))) (All VarCurr, ((v22292 VarCurr (bitIndex0)) <=> (v22293 VarCurr))) ### And 10
% 17.60/17.80 12. ((v22291 T_0) <=> ((v22292 T_0 (bitIndex0)) /\ (v22292 T_0 (bitIndex1)))) (All VarCurr, ((v22292 VarCurr (bitIndex0)) <=> (v22293 VarCurr))) (All VarCurr, (-. (v22296 VarCurr (bitIndex9)))) (v22291 T_0) ### Equiv 3 11
% 17.60/17.80 13. (All VarCurr, ((v22291 VarCurr) <=> ((v22292 VarCurr (bitIndex0)) /\ (v22292 VarCurr (bitIndex1))))) (v22291 T_0) (All VarCurr, (-. (v22296 VarCurr (bitIndex9)))) (All VarCurr, ((v22292 VarCurr (bitIndex0)) <=> (v22293 VarCurr))) ### All 12
% 17.60/17.80 14. ((-. (v22290 T_0)) <=> (v22291 T_0)) (All VarCurr, ((v22292 VarCurr (bitIndex0)) <=> (v22293 VarCurr))) (All VarCurr, (-. (v22296 VarCurr (bitIndex9)))) (All VarCurr, ((v22291 VarCurr) <=> ((v22292 VarCurr (bitIndex0)) /\ (v22292 VarCurr (bitIndex1))))) (-. (v22290 T_0)) ### Equiv 2 13
% 17.60/17.80 15. (All VarCurr, ((-. (v22290 VarCurr)) <=> (v22291 VarCurr))) (-. (v22290 T_0)) (All VarCurr, ((v22291 VarCurr) <=> ((v22292 VarCurr (bitIndex0)) /\ (v22292 VarCurr (bitIndex1))))) (All VarCurr, (-. (v22296 VarCurr (bitIndex9)))) (All VarCurr, ((v22292 VarCurr (bitIndex0)) <=> (v22293 VarCurr))) ### All 14
% 17.60/17.80 16. (-. True) ### NotTrue
% 17.60/17.80 17. (-. (v22292 T_0 (bitIndex1))) (v22292 T_0 (bitIndex1)) ### Axiom
% 17.60/17.80 18. ((v22292 T_0 (bitIndex1)) <=> True) (-. (v22292 T_0 (bitIndex1))) ### Equiv 16 17
% 17.60/17.80 19. (All VarCurr, ((v22292 VarCurr (bitIndex1)) <=> True)) (-. (v22292 T_0 (bitIndex1))) ### All 18
% 17.60/17.80 20. (-. ((v22292 T_0 (bitIndex0)) \/ (v22292 T_0 (bitIndex1)))) (All VarCurr, ((v22292 VarCurr (bitIndex1)) <=> True)) ### NotOr 19
% 17.60/17.80 21. (-. (v22314 T_0)) (All VarCurr, ((v22292 VarCurr (bitIndex1)) <=> True)) ### Definition-Pseudo(v22314) 20
% 17.60/17.80 22. (-. ((v22290 T_0) /\ (v22314 T_0))) (All VarCurr, ((v22292 VarCurr (bitIndex1)) <=> True)) (All VarCurr, ((v22292 VarCurr (bitIndex0)) <=> (v22293 VarCurr))) (All VarCurr, (-. (v22296 VarCurr (bitIndex9)))) (All VarCurr, ((v22291 VarCurr) <=> ((v22292 VarCurr (bitIndex0)) /\ (v22292 VarCurr (bitIndex1))))) (All VarCurr, ((-. (v22290 VarCurr)) <=> (v22291 VarCurr))) ### NotAnd 15 21
% 17.60/17.80 23. (-. (v22288 T_0)) (v22288 T_0) ### Axiom
% 17.60/17.80 24. ((v22288 T_0) <=> ((v22290 T_0) /\ (v22314 T_0))) (-. (v22288 T_0)) (All VarCurr, ((-. (v22290 VarCurr)) <=> (v22291 VarCurr))) (All VarCurr, ((v22291 VarCurr) <=> ((v22292 VarCurr (bitIndex0)) /\ (v22292 VarCurr (bitIndex1))))) (All VarCurr, (-. (v22296 VarCurr (bitIndex9)))) (All VarCurr, ((v22292 VarCurr (bitIndex0)) <=> (v22293 VarCurr))) (All VarCurr, ((v22292 VarCurr (bitIndex1)) <=> True)) ### Equiv 22 23
% 17.60/17.80 25. (All VarCurr, ((v22288 VarCurr) <=> ((v22290 VarCurr) /\ (v22314 VarCurr)))) (All VarCurr, ((v22292 VarCurr (bitIndex1)) <=> True)) (All VarCurr, ((v22292 VarCurr (bitIndex0)) <=> (v22293 VarCurr))) (All VarCurr, (-. (v22296 VarCurr (bitIndex9)))) (All VarCurr, ((v22291 VarCurr) <=> ((v22292 VarCurr (bitIndex0)) /\ (v22292 VarCurr (bitIndex1))))) (All VarCurr, ((-. (v22290 VarCurr)) <=> (v22291 VarCurr))) (-. (v22288 T_0)) ### All 24
% 17.60/17.80 26. (-. (v4 T_0)) (v4 T_0) ### Axiom
% 17.60/17.80 27. (-. (-. (v4 T_0))) (-. (v4 T_0)) ### NotNot 26
% 17.60/17.80 28. (-. (v22287 T_0)) (-. (v4 T_0)) ### Definition-Pseudo(v22287) 27
% 17.60/17.80 29. ((-. (v22287 T_0)) <=> (v22288 T_0)) (-. (v4 T_0)) (All VarCurr, ((-. (v22290 VarCurr)) <=> (v22291 VarCurr))) (All VarCurr, ((v22291 VarCurr) <=> ((v22292 VarCurr (bitIndex0)) /\ (v22292 VarCurr (bitIndex1))))) (All VarCurr, (-. (v22296 VarCurr (bitIndex9)))) (All VarCurr, ((v22292 VarCurr (bitIndex0)) <=> (v22293 VarCurr))) (All VarCurr, ((v22292 VarCurr (bitIndex1)) <=> True)) (All VarCurr, ((v22288 VarCurr) <=> ((v22290 VarCurr) /\ (v22314 VarCurr)))) ### Equiv 25 28
% 17.60/17.80 30. (All VarCurr, ((-. (v22287 VarCurr)) <=> (v22288 VarCurr))) (All VarCurr, ((v22288 VarCurr) <=> ((v22290 VarCurr) /\ (v22314 VarCurr)))) (All VarCurr, ((v22292 VarCurr (bitIndex1)) <=> True)) (All VarCurr, ((v22292 VarCurr (bitIndex0)) <=> (v22293 VarCurr))) (All VarCurr, (-. (v22296 VarCurr (bitIndex9)))) (All VarCurr, ((v22291 VarCurr) <=> ((v22292 VarCurr (bitIndex0)) /\ (v22292 VarCurr (bitIndex1))))) (All VarCurr, ((-. (v22290 VarCurr)) <=> (v22291 VarCurr))) (-. (v4 T_0)) ### All 29
% 17.60/17.80 31. (-. ((reachableState T_0) => (v4 T_0))) (All VarCurr, ((-. (v22290 VarCurr)) <=> (v22291 VarCurr))) (All VarCurr, ((v22291 VarCurr) <=> ((v22292 VarCurr (bitIndex0)) /\ (v22292 VarCurr (bitIndex1))))) (All VarCurr, (-. (v22296 VarCurr (bitIndex9)))) (All VarCurr, ((v22292 VarCurr (bitIndex0)) <=> (v22293 VarCurr))) (All VarCurr, ((v22292 VarCurr (bitIndex1)) <=> True)) (All VarCurr, ((v22288 VarCurr) <=> ((v22290 VarCurr) /\ (v22314 VarCurr)))) (All VarCurr, ((-. (v22287 VarCurr)) <=> (v22288 VarCurr))) ### NotImply 30
% 17.60/17.80 32. (-. (All VarCurr, ((reachableState VarCurr) => (v4 VarCurr)))) (All VarCurr, ((-. (v22287 VarCurr)) <=> (v22288 VarCurr))) (All VarCurr, ((v22288 VarCurr) <=> ((v22290 VarCurr) /\ (v22314 VarCurr)))) (All VarCurr, ((v22292 VarCurr (bitIndex1)) <=> True)) (All VarCurr, ((v22292 VarCurr (bitIndex0)) <=> (v22293 VarCurr))) (All VarCurr, (-. (v22296 VarCurr (bitIndex9)))) (All VarCurr, ((v22291 VarCurr) <=> ((v22292 VarCurr (bitIndex0)) /\ (v22292 VarCurr (bitIndex1))))) (All VarCurr, ((-. (v22290 VarCurr)) <=> (v22291 VarCurr))) ### NotAllEx 31
% 17.60/17.80 % SZS output end Proof
% 17.60/17.80 (* END-PROOF *)
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