TSTP Solution File: COM151+1 by Refute---2015
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%------------------------------------------------------------------------------
% File : Refute---2015
% Problem : COM151+1 : TPTP v6.4.0. Released v6.4.0.
% Transfm : none
% Format : tptp:raw
% Command : isabelle tptp_refute %d %s
% Computer : n054.star.cs.uiowa.edu
% Model : x86_64 x86_64
% CPU : Intel(R) Xeon(R) CPU E5-2609 0 2.40GHz
% Memory : 32218.75MB
% OS : Linux 3.10.0-327.10.1.el7.x86_64
% CPULimit : 300s
% DateTime : Tue Apr 12 12:12:18 EDT 2016
% Result : Timeout 300.04s
% Output : None
% Verified :
% SZS Type : None (Parsing solution fails)
% Syntax : Number of formulae : 0
% Comments :
%------------------------------------------------------------------------------
%----No solution output by system
%------------------------------------------------------------------------------
%----ORIGINAL SYSTEM OUTPUT
% 0.00/0.03 % Problem : COM151+1 : TPTP v6.4.0. Released v6.4.0.
% 0.00/0.04 % Command : isabelle tptp_refute %d %s
% 0.03/0.23 % Computer : n054.star.cs.uiowa.edu
% 0.03/0.23 % Model : x86_64 x86_64
% 0.03/0.23 % CPU : Intel(R) Xeon(R) CPU E5-2609 0 @ 2.40GHz
% 0.03/0.23 % Memory : 32218.75MB
% 0.03/0.23 % OS : Linux 3.10.0-327.10.1.el7.x86_64
% 0.03/0.23 % CPULimit : 300
% 0.03/0.23 % DateTime : Sat Apr 9 06:53:54 CDT 2016
% 0.03/0.23 % CPUTime :
% 6.29/5.84 > val it = (): unit
% 6.60/6.12 Trying to find a model that refutes: True
% 8.12/7.65 Unfolded term: [| ALL Ve Vx Ve1.
% 8.12/7.65 ~ bnd_visFreeVar Vx Ve & bnd_valphaEquivalent Ve Ve1 -->
% 8.12/7.65 ~ bnd_visFreeVar Vx Ve1;
% 8.12/7.65 ALL Ve VC Ve1 VT.
% 8.12/7.65 bnd_vtcheck VC Ve VT & bnd_valphaEquivalent Ve Ve1 -->
% 8.12/7.65 bnd_vtcheck VC Ve1 VT;
% 8.12/7.65 ALL VS Vx Vy Ve.
% 8.12/7.65 ~ bnd_visFreeVar Vy Ve -->
% 8.12/7.65 bnd_valphaEquivalent (bnd_vabs Vx VS Ve)
% 8.12/7.65 (bnd_vabs Vy VS (bnd_vsubst Vx (bnd_vvar Vy) Ve));
% 8.12/7.65 ALL Ve2 Ve1 Ve3.
% 8.12/7.65 bnd_valphaEquivalent Ve1 Ve2 & bnd_valphaEquivalent Ve2 Ve3 -->
% 8.12/7.65 bnd_valphaEquivalent Ve1 Ve3;
% 8.12/7.65 ALL Ve2 Ve1.
% 8.12/7.65 bnd_valphaEquivalent Ve1 Ve2 --> bnd_valphaEquivalent Ve2 Ve1;
% 8.12/7.65 ALL Ve. bnd_valphaEquivalent Ve Ve;
% 8.12/7.65 ALL Ve VT VC.
% 8.12/7.65 bnd_vtcheck VC Ve VT -->
% 8.12/7.65 ((EX Vx. Ve = bnd_vvar Vx & bnd_vlookup Vx VC = bnd_vsomeType VT) |
% 8.12/7.65 (EX Vx Ve2 VT1 VT2.
% 8.12/7.65 (Ve = bnd_vabs Vx VT1 Ve2 & VT = bnd_varrow VT1 VT2) &
% 8.12/7.65 bnd_vtcheck (bnd_vbind Vx VT1 VC) Ve2 VT2)) |
% 8.12/7.65 (EX Ve1 Ve2 VS.
% 8.12/7.65 (Ve = bnd_vapp Ve1 Ve2 & bnd_vtcheck VC Ve1 (bnd_varrow VS VT)) &
% 8.12/7.65 bnd_vtcheck VC Ve2 VS);
% 8.12/7.65 ALL VS VC Ve1 Ve2 VT.
% 8.12/7.65 bnd_vtcheck VC Ve1 (bnd_varrow VS VT) & bnd_vtcheck VC Ve2 VS -->
% 8.12/7.65 bnd_vtcheck VC (bnd_vapp Ve1 Ve2) VT;
% 8.12/7.65 ALL VC Vx Ve VS VT.
% 8.12/7.65 bnd_vtcheck (bnd_vbind Vx VS VC) Ve VT -->
% 8.12/7.65 bnd_vtcheck VC (bnd_vabs Vx VS Ve) (bnd_varrow VS VT);
% 8.12/7.65 ALL VC Vx VT.
% 8.12/7.65 bnd_vlookup Vx VC = bnd_vsomeType VT -->
% 8.12/7.65 bnd_vtcheck VC (bnd_vvar Vx) VT;
% 8.12/7.65 ALL VTyp0 VTyp1 VTyp2 VTyp3.
% 8.12/7.65 (bnd_varrow VTyp0 VTyp1 = bnd_varrow VTyp2 VTyp3 -->
% 8.12/7.65 VTyp0 = VTyp2 & VTyp1 = VTyp3) &
% 8.12/7.65 (VTyp0 = VTyp2 & VTyp1 = VTyp3 -->
% 8.12/7.65 bnd_varrow VTyp0 VTyp1 = bnd_varrow VTyp2 VTyp3);
% 8.12/7.65 ALL VExp0 RESULT.
% 8.12/7.65 bnd_vreduce VExp0 = RESULT -->
% 8.12/7.65 ((((((EX Vx. VExp0 = bnd_vvar Vx & RESULT = bnd_vnoExp) |
% 8.12/7.65 (EX Vx VS Ve. VExp0 = bnd_vabs Vx VS Ve & RESULT = bnd_vnoExp)) |
% 8.12/7.65 (EX Ve2 Vx VS Ve1 Ve2red.
% 8.12/7.65 ((VExp0 = bnd_vapp (bnd_vabs Vx VS Ve1) Ve2 &
% 8.12/7.65 Ve2red = bnd_vreduce Ve2) &
% 8.12/7.65 bnd_visSomeExp Ve2red) &
% 8.12/7.65 RESULT =
% 8.12/7.65 bnd_vsomeExp
% 8.12/7.65 (bnd_vapp (bnd_vabs Vx VS Ve1) (bnd_vgetSomeExp Ve2red)))) |
% 8.12/7.65 (EX VS Ve2red Vx Ve2 Ve1.
% 8.12/7.65 (((VExp0 = bnd_vapp (bnd_vabs Vx VS Ve1) Ve2 &
% 8.12/7.65 Ve2red = bnd_vreduce Ve2) &
% 8.12/7.65 ~ bnd_visSomeExp Ve2red) &
% 8.12/7.65 bnd_visValue Ve2) &
% 8.12/7.65 RESULT = bnd_vsomeExp (bnd_vsubst Vx Ve2 Ve1))) |
% 8.12/7.65 (EX Vx VS Ve1 Ve2red Ve2.
% 8.12/7.65 (((VExp0 = bnd_vapp (bnd_vabs Vx VS Ve1) Ve2 &
% 8.12/7.65 Ve2red = bnd_vreduce Ve2) &
% 8.12/7.65 ~ bnd_visSomeExp Ve2red) &
% 8.12/7.65 ~ bnd_visValue Ve2) &
% 8.12/7.65 RESULT = bnd_vnoExp)) |
% 8.12/7.65 (EX Ve1 Ve1red Ve2.
% 8.12/7.65 (((VExp0 = bnd_vapp Ve1 Ve2 &
% 8.12/7.65 (ALL VVx0 VVS0 VVe10. ~ Ve1 = bnd_vabs VVx0 VVS0 VVe10)) &
% 8.12/7.65 Ve1red = bnd_vreduce Ve1) &
% 8.12/7.65 bnd_visSomeExp Ve1red) &
% 8.12/7.65 RESULT = bnd_vsomeExp (bnd_vapp (bnd_vgetSomeExp Ve1red) Ve2))) |
% 8.12/7.65 (EX Ve2 Ve1 Ve1red.
% 8.12/7.65 (((VExp0 = bnd_vapp Ve1 Ve2 &
% 8.12/7.65 (ALL VVx0 VVS0 VVe10. ~ Ve1 = bnd_vabs VVx0 VVS0 VVe10)) &
% 8.12/7.65 Ve1red = bnd_vreduce Ve1) &
% 8.12/7.65 ~ bnd_visSomeExp Ve1red) &
% 8.12/7.65 RESULT = bnd_vnoExp);
% 8.12/7.65 ALL Ve2 Ve1 Ve1red VExp0 RESULT.
% 8.12/7.65 VExp0 = bnd_vapp Ve1 Ve2 &
% 8.12/7.65 (ALL VVx0 VVS0 VVe10. ~ Ve1 = bnd_vabs VVx0 VVS0 VVe10) -->
% 8.12/7.65 Ve1red = bnd_vreduce Ve1 & ~ bnd_visSomeExp Ve1red -->
% 8.12/7.65 RESULT = bnd_vreduce VExp0 --> RESULT = bnd_vnoExp;
% 8.12/7.65 ALL Ve1 VExp0 RESULT Ve1red Ve2.
% 8.12/7.65 VExp0 = bnd_vapp Ve1 Ve2 &
% 8.12/7.65 (ALL VVx0 VVS0 VVe10. ~ Ve1 = bnd_vabs VVx0 VVS0 VVe10) -->
% 8.12/7.65 Ve1red = bnd_vreduce Ve1 & bnd_visSomeExp Ve1red -->
% 8.12/7.65 RESULT = bnd_vreduce VExp0 -->
% 8.12/7.65 RESULT = bnd_vsomeExp (bnd_vapp (bnd_vgetSomeExp Ve1red) Ve2);
% 8.12/7.65 ALL Vx VS Ve1 Ve2red Ve2 VExp0 RESULT.
% 8.12/7.65 VExp0 = bnd_vapp (bnd_vabs Vx VS Ve1) Ve2 -->
% 8.12/7.65 (Ve2red = bnd_vreduce Ve2 & ~ bnd_visSomeExp Ve2red) &
% 8.12/7.65 ~ bnd_visValue Ve2 -->
% 8.12/7.65 RESULT = bnd_vreduce VExp0 --> RESULT = bnd_vnoExp;
% 8.12/7.65 ALL VS Ve2red VExp0 RESULT Vx Ve2 Ve1.
% 8.12/7.65 VExp0 = bnd_vapp (bnd_vabs Vx VS Ve1) Ve2 -->
% 8.12/7.65 (Ve2red = bnd_vreduce Ve2 & ~ bnd_visSomeExp Ve2red) &
% 8.12/7.65 bnd_visValue Ve2 -->
% 8.12/7.65 RESULT = bnd_vreduce VExp0 -->
% 8.12/7.65 RESULT = bnd_vsomeExp (bnd_vsubst Vx Ve2 Ve1);
% 8.12/7.65 ALL Ve2 VExp0 RESULT Vx VS Ve1 Ve2red.
% 8.12/7.65 VExp0 = bnd_vapp (bnd_vabs Vx VS Ve1) Ve2 -->
% 8.12/7.65 Ve2red = bnd_vreduce Ve2 & bnd_visSomeExp Ve2red -->
% 8.12/7.65 RESULT = bnd_vreduce VExp0 -->
% 8.12/7.65 RESULT =
% 8.12/7.65 bnd_vsomeExp (bnd_vapp (bnd_vabs Vx VS Ve1) (bnd_vgetSomeExp Ve2red));
% 8.12/7.65 ALL Vx VS Ve VExp0 RESULT.
% 8.12/7.65 VExp0 = bnd_vabs Vx VS Ve -->
% 8.12/7.65 RESULT = bnd_vreduce VExp0 --> RESULT = bnd_vnoExp;
% 8.12/7.65 ALL Vx VExp0 RESULT.
% 8.12/7.65 VExp0 = bnd_vvar Vx -->
% 8.12/7.65 RESULT = bnd_vreduce VExp0 --> RESULT = bnd_vnoExp;
% 8.12/7.65 ALL VOptExp0 RESULT Ve.
% 8.12/7.65 VOptExp0 = bnd_vsomeExp Ve -->
% 8.12/7.65 RESULT = bnd_vgetSomeExp VOptExp0 --> RESULT = Ve;
% 8.12/7.65 ALL Ve VOptExp0. VOptExp0 = bnd_vsomeExp Ve --> bnd_visSomeExp VOptExp0;
% 8.12/7.65 ALL VOptExp0. VOptExp0 = bnd_vnoExp --> ~ bnd_visSomeExp VOptExp0;
% 8.12/7.65 ALL VExp0. ~ bnd_vnoExp = bnd_vsomeExp VExp0;
% 8.12/7.65 ALL VExp0 VExp1.
% 8.12/7.65 (bnd_vsomeExp VExp0 = bnd_vsomeExp VExp1 --> VExp0 = VExp1) &
% 8.12/7.65 (VExp0 = VExp1 --> bnd_vsomeExp VExp0 = bnd_vsomeExp VExp1);
% 8.12/7.65 (bnd_vnoExp = bnd_vnoExp --> True) & (True --> bnd_vnoExp = bnd_vnoExp);
% 8.12/7.65 ALL VVar0 VExp0 VExp1 RESULT.
% 8.12/7.65 bnd_vsubst VVar0 VExp0 VExp1 = RESULT -->
% 8.12/7.65 (((((EX Vx Vy Ve.
% 8.12/7.65 (((VVar0 = Vx & VExp0 = Ve) & VExp1 = bnd_vvar Vy) &
% 8.12/7.65 Vx = Vy) &
% 8.12/7.65 RESULT = Ve) |
% 8.12/7.65 (EX Ve Vx Vy.
% 8.12/7.65 (((VVar0 = Vx & VExp0 = Ve) & VExp1 = bnd_vvar Vy) &
% 8.12/7.65 ~ Vx = Vy) &
% 8.12/7.65 RESULT = bnd_vvar Vy)) |
% 8.12/7.65 (EX Ve1 Vx Ve Ve2.
% 8.12/7.65 ((VVar0 = Vx & VExp0 = Ve) & VExp1 = bnd_vapp Ve1 Ve2) &
% 8.12/7.65 RESULT =
% 8.12/7.65 bnd_vapp (bnd_vsubst Vx Ve Ve1) (bnd_vsubst Vx Ve Ve2))) |
% 8.12/7.65 (EX Ve Vx Vy VT Ve1.
% 8.12/7.65 (((VVar0 = Vx & VExp0 = Ve) & VExp1 = bnd_vabs Vy VT Ve1) &
% 8.12/7.65 Vx = Vy) &
% 8.12/7.65 RESULT = bnd_vabs Vy VT Ve1)) |
% 8.12/7.65 (EX Vx Ve VT Vy Vfresh Ve1.
% 8.12/7.65 (((((VVar0 = Vx & VExp0 = Ve) & VExp1 = bnd_vabs Vy VT Ve1) &
% 8.12/7.65 ~ Vx = Vy) &
% 8.12/7.65 bnd_visFreeVar Vy Ve) &
% 8.12/7.65 Vfresh =
% 8.12/7.65 bnd_vgensym (bnd_vapp (bnd_vapp Ve Ve1) (bnd_vvar Vx))) &
% 8.12/7.65 RESULT =
% 8.12/7.65 bnd_vsubst Vx Ve
% 8.12/7.65 (bnd_vabs Vfresh VT (bnd_vsubst Vy (bnd_vvar Vfresh) Ve1)))) |
% 8.12/7.65 (EX Vy VT Vx Ve Ve1.
% 8.12/7.65 ((((VVar0 = Vx & VExp0 = Ve) & VExp1 = bnd_vabs Vy VT Ve1) &
% 8.12/7.65 ~ Vx = Vy) &
% 8.12/7.65 ~ bnd_visFreeVar Vy Ve) &
% 8.12/7.65 RESULT = bnd_vabs Vy VT (bnd_vsubst Vx Ve Ve1));
% 8.12/7.65 ALL VVar0 VExp0 VExp1 RESULT Vy VT Vx Ve Ve1.
% 8.12/7.65 (VVar0 = Vx & VExp0 = Ve) & VExp1 = bnd_vabs Vy VT Ve1 -->
% 8.12/7.65 ~ Vx = Vy & ~ bnd_visFreeVar Vy Ve -->
% 8.12/7.65 RESULT = bnd_vsubst VVar0 VExp0 VExp1 -->
% 8.12/7.65 RESULT = bnd_vabs Vy VT (bnd_vsubst Vx Ve Ve1);
% 8.12/7.65 ALL VVar0 VExp0 VExp1 RESULT Vx Ve VT Vy Vfresh Ve1.
% 8.12/7.65 (VVar0 = Vx & VExp0 = Ve) & VExp1 = bnd_vabs Vy VT Ve1 -->
% 8.12/7.65 (~ Vx = Vy & bnd_visFreeVar Vy Ve) &
% 8.12/7.65 Vfresh = bnd_vgensym (bnd_vapp (bnd_vapp Ve Ve1) (bnd_vvar Vx)) -->
% 8.12/7.65 RESULT = bnd_vsubst VVar0 VExp0 VExp1 -->
% 8.12/7.65 RESULT =
% 8.12/7.65 bnd_vsubst Vx Ve
% 8.12/7.65 (bnd_vabs Vfresh VT (bnd_vsubst Vy (bnd_vvar Vfresh) Ve1));
% 8.12/7.65 ALL Ve Vx VVar0 VExp0 VExp1 RESULT Vy VT Ve1.
% 8.12/7.65 (VVar0 = Vx & VExp0 = Ve) & VExp1 = bnd_vabs Vy VT Ve1 -->
% 8.12/7.65 Vx = Vy -->
% 8.12/7.65 RESULT = bnd_vsubst VVar0 VExp0 VExp1 --> RESULT = bnd_vabs Vy VT Ve1;
% 8.12/7.65 ALL VVar0 VExp0 VExp1 RESULT Ve1 Vx Ve Ve2.
% 8.12/7.65 (VVar0 = Vx & VExp0 = Ve) & VExp1 = bnd_vapp Ve1 Ve2 -->
% 8.12/7.65 RESULT = bnd_vsubst VVar0 VExp0 VExp1 -->
% 8.12/7.65 RESULT = bnd_vapp (bnd_vsubst Vx Ve Ve1) (bnd_vsubst Vx Ve Ve2);
% 8.12/7.65 ALL Ve Vx VVar0 VExp0 VExp1 RESULT Vy.
% 8.12/7.65 (VVar0 = Vx & VExp0 = Ve) & VExp1 = bnd_vvar Vy -->
% 8.12/7.65 ~ Vx = Vy -->
% 8.12/7.65 RESULT = bnd_vsubst VVar0 VExp0 VExp1 --> RESULT = bnd_vvar Vy;
% 8.12/7.65 ALL Vx Vy VVar0 VExp0 VExp1 RESULT Ve.
% 8.12/7.65 (VVar0 = Vx & VExp0 = Ve) & VExp1 = bnd_vvar Vy -->
% 8.12/7.65 Vx = Vy --> RESULT = bnd_vsubst VVar0 VExp0 VExp1 --> RESULT = Ve;
% 8.12/7.65 ALL Vv Ve. bnd_vgensym Ve = Vv --> ~ bnd_visFreeVar Vv Ve;
% 8.12/7.65 ALL Vy VTy Vx VTx VC Ve VT.
% 8.12/7.65 ~ Vx = Vy &
% 8.12/7.65 bnd_vtcheck (bnd_vbind Vx VTx (bnd_vbind Vy VTy VC)) Ve VT -->
% 8.12/7.65 bnd_vtcheck (bnd_vbind Vy VTy (bnd_vbind Vx VTx VC)) Ve VT;
% 8.12/7.65 ALL Vy VTy Vx VTx VC Ve VT.
% 8.12/7.65 Vx = Vy &
% 8.12/7.65 bnd_vtcheck (bnd_vbind Vx VTx (bnd_vbind Vy VTy VC)) Ve VT -->
% 8.12/7.65 bnd_vtcheck (bnd_vbind Vx VTx VC) Ve VT;
% 8.12/7.65 ALL VVar0 VCtx0 RESULT.
% 8.12/7.65 bnd_vlookup VVar0 VCtx0 = RESULT -->
% 8.12/7.65 ((EX Vx. (VVar0 = Vx & VCtx0 = bnd_vempty) & RESULT = bnd_vnoType) |
% 8.12/7.65 (EX VC Vx Vy VTy.
% 8.12/7.65 ((VVar0 = Vx & VCtx0 = bnd_vbind Vy VTy VC) & Vx = Vy) &
% 8.12/7.65 RESULT = bnd_vsomeType VTy)) |
% 8.12/7.65 (EX VTy Vy Vx VC.
% 8.12/7.65 ((VVar0 = Vx & VCtx0 = bnd_vbind Vy VTy VC) & ~ Vx = Vy) &
% 8.12/7.65 RESULT = bnd_vlookup Vx VC);
% 8.12/7.65 ALL VTy Vy VVar0 VCtx0 RESULT Vx VC.
% 8.12/7.65 VVar0 = Vx & VCtx0 = bnd_vbind Vy VTy VC -->
% 8.12/7.65 ~ Vx = Vy -->
% 8.12/7.65 RESULT = bnd_vlookup VVar0 VCtx0 --> RESULT = bnd_vlookup Vx VC;
% 8.12/7.65 ALL VC Vx Vy VVar0 VCtx0 RESULT VTy.
% 8.12/7.65 VVar0 = Vx & VCtx0 = bnd_vbind Vy VTy VC -->
% 8.12/7.65 Vx = Vy -->
% 8.12/7.65 RESULT = bnd_vlookup VVar0 VCtx0 --> RESULT = bnd_vsomeType VTy;
% 8.12/7.65 ALL Vx VVar0 VCtx0 RESULT.
% 8.12/7.65 VVar0 = Vx & VCtx0 = bnd_vempty -->
% 8.12/7.65 RESULT = bnd_vlookup VVar0 VCtx0 --> RESULT = bnd_vnoType;
% 8.12/7.65 ALL VOptTyp0 RESULT Ve.
% 8.12/7.65 VOptTyp0 = bnd_vsomeType Ve -->
% 8.12/7.65 RESULT = bnd_vgetSomeType VOptTyp0 --> RESULT = Ve;
% 8.12/7.65 ALL Ve VOptTyp0.
% 8.12/7.65 VOptTyp0 = bnd_vsomeType Ve --> bnd_visSomeType VOptTyp0;
% 8.12/7.65 ALL VOptTyp0. VOptTyp0 = bnd_vnoType --> ~ bnd_visSomeType VOptTyp0;
% 8.12/7.65 ALL VTyp0. ~ bnd_vnoType = bnd_vsomeType VTyp0;
% 8.12/7.65 ALL VVar0 VTyp0 VCtx0. ~ bnd_vempty = bnd_vbind VVar0 VTyp0 VCtx0;
% 8.12/7.65 ALL VTyp0 VTyp1.
% 8.12/7.65 (bnd_vsomeType VTyp0 = bnd_vsomeType VTyp1 --> VTyp0 = VTyp1) &
% 8.12/7.65 (VTyp0 = VTyp1 --> bnd_vsomeType VTyp0 = bnd_vsomeType VTyp1);
% 8.12/7.65 (bnd_vnoType = bnd_vnoType --> True) &
% 8.12/7.65 (True --> bnd_vnoType = bnd_vnoType);
% 8.12/7.65 ALL VVar0 VTyp0 VCtx0 VVar1 VTyp1 VCtx1.
% 8.12/7.65 (bnd_vbind VVar0 VTyp0 VCtx0 = bnd_vbind VVar1 VTyp1 VCtx1 -->
% 8.12/7.65 (VVar0 = VVar1 & VTyp0 = VTyp1) & VCtx0 = VCtx1) &
% 8.12/7.65 ((VVar0 = VVar1 & VTyp0 = VTyp1) & VCtx0 = VCtx1 -->
% 8.12/7.65 bnd_vbind VVar0 VTyp0 VCtx0 = bnd_vbind VVar1 VTyp1 VCtx1);
% 8.12/7.65 (bnd_vempty = bnd_vempty --> True) & (True --> bnd_vempty = bnd_vempty);
% 8.12/7.65 ALL VVar0 VExp0 Ve1 Vv Ve2.
% 8.12/7.65 VVar0 = Vv & VExp0 = bnd_vapp Ve1 Ve2 -->
% 8.12/7.65 (bnd_visFreeVar Vv Ve1 | bnd_visFreeVar Vv Ve2 -->
% 8.12/7.65 bnd_visFreeVar VVar0 VExp0) &
% 8.12/7.65 (bnd_visFreeVar VVar0 VExp0 -->
% 8.12/7.65 bnd_visFreeVar Vv Ve1 | bnd_visFreeVar Vv Ve2);
% 8.12/7.65 ALL VT VVar0 VExp0 Vx Vv Ve.
% 8.12/7.65 VVar0 = Vv & VExp0 = bnd_vabs Vx VT Ve -->
% 8.12/7.65 (~ Vx = Vv & bnd_visFreeVar Vv Ve --> bnd_visFreeVar VVar0 VExp0) &
% 8.12/7.65 (bnd_visFreeVar VVar0 VExp0 --> ~ Vx = Vv & bnd_visFreeVar Vv Ve);
% 8.12/7.65 ALL VVar0 VExp0 Vx Vv.
% 8.12/7.65 VVar0 = Vv & VExp0 = bnd_vvar Vx -->
% 8.12/7.65 (Vx = Vv --> bnd_visFreeVar VVar0 VExp0) &
% 8.12/7.65 (bnd_visFreeVar VVar0 VExp0 --> Vx = Vv);
% 8.12/7.65 ALL Ve1 Ve2 VExp0. VExp0 = bnd_vapp Ve1 Ve2 --> ~ bnd_visValue VExp0;
% 8.12/7.65 ALL Vx VExp0. VExp0 = bnd_vvar Vx --> ~ bnd_visValue VExp0;
% 8.12/7.65 ALL Vx VS Ve VExp0. VExp0 = bnd_vabs Vx VS Ve --> bnd_visValue VExp0;
% 8.12/7.65 ALL VVar0 VTyp0 VExp0 VExp1 VExp2.
% 8.12/7.65 ~ bnd_vabs VVar0 VTyp0 VExp0 = bnd_vapp VExp1 VExp2;
% 8.12/7.65 ALL VVar0 VExp0 VExp1. ~ bnd_vvar VVar0 = bnd_vapp VExp0 VExp1;
% 8.12/7.65 ALL VVar0 VVar1 VTyp0 VExp0.
% 8.12/7.65 ~ bnd_vvar VVar0 = bnd_vabs VVar1 VTyp0 VExp0;
% 8.12/7.65 ALL VExp0 VExp1 VExp2 VExp3.
% 8.12/7.65 (bnd_vapp VExp0 VExp1 = bnd_vapp VExp2 VExp3 -->
% 8.12/7.65 VExp0 = VExp2 & VExp1 = VExp3) &
% 8.12/7.65 (VExp0 = VExp2 & VExp1 = VExp3 -->
% 8.12/7.65 bnd_vapp VExp0 VExp1 = bnd_vapp VExp2 VExp3);
% 8.12/7.65 ALL VVar0 VTyp0 VExp0 VVar1 VTyp1 VExp1.
% 8.12/7.65 (bnd_vabs VVar0 VTyp0 VExp0 = bnd_vabs VVar1 VTyp1 VExp1 -->
% 8.12/7.65 (VVar0 = VVar1 & VTyp0 = VTyp1) & VExp0 = VExp1) &
% 8.12/7.65 ((VVar0 = VVar1 & VTyp0 = VTyp1) & VExp0 = VExp1 -->
% 8.12/7.65 bnd_vabs VVar0 VTyp0 VExp0 = bnd_vabs VVar1 VTyp1 VExp1);
% 8.12/7.65 ALL VVar0 VVar1.
% 8.12/7.65 (bnd_vvar VVar0 = bnd_vvar VVar1 --> VVar0 = VVar1) &
% 8.12/7.65 (VVar0 = VVar1 --> bnd_vvar VVar0 = bnd_vvar VVar1) |]
% 8.12/7.65 ==> True
% 8.12/7.65 Adding axioms...
% 8.12/7.66 Typedef.type_definition_def
% 23.82/23.38 ...done.
% 23.92/23.40 Ground types: ?'b, TPTP_Interpret.ind
% 23.92/23.40 Translating term (sizes: 1, 1) ...
% 31.84/31.37 Invoking SAT solver...
% 31.84/31.37 No model exists.
% 31.84/31.37 Translating term (sizes: 2, 1) ...
% 40.65/40.12 Invoking SAT solver...
% 40.65/40.12 No model exists.
% 40.65/40.12 Translating term (sizes: 1, 2) ...
% 300.04/298.12 /export/starexec/sandbox2/solver/lib/scripts/run-polyml-5.5.2: line 82: 24711 CPU time limit exceeded (core dumped) "$ISABELLE_HOME/lib/scripts/feeder" -p -h "$MLTEXT" -t "$MLEXIT" $FEEDER_OPTS
% 300.04/298.12 24712 (core dumped) | { read FPID; "$POLY" -q -i $ML_OPTIONS; RC="$?"; kill -TERM "$FPID"; exit "$RC"; }
% 300.04/298.13 /export/starexec/sandbox2/solver/src/HOL/TPTP/lib/Tools/tptp_refute: line 26: 24657 Exit 152 "$ISABELLE_PROCESS" -q -e "use_thy \"/tmp/$SCRATCH\"; exit 1;" HOL-TPTP
% 300.04/298.13 24658 CPU time limit exceeded (core dumped) | grep --line-buffered -v "^###\|^PROOF FAILED for depth\|^Failure node\|inferences so far. Searching to depth\|^val \|^Loading theory\|^Warning-The type of\|^ monotype.$"
%------------------------------------------------------------------------------