%------------------------------------------------------------------------------
% File     : cvc5---1.0.5
% Problem  : ARI497_1 : TPTP v8.2.0. Released v5.0.0.
% Transfm  : none
% Format   : tptp:raw
% Command  : do_cvc5 %s %d

% Computer : n014.cluster.edu
% Model    : x86_64 x86_64
% CPU      : Intel(R) Xeon(R) CPU E5-2620 v4 2.10GHz
% Memory   : 8042.1875MB
% OS       : Linux 3.10.0-693.el7.x86_64
% CPULimit : 300s
% WCLimit  : 300s
% DateTime : Wed May 29 16:33:58 EDT 2024

% Result   : Theorem 0.20s 0.51s
% Output   : Proof 0.20s
% Verified : 
% SZS Type : -

% Comments : 
%------------------------------------------------------------------------------
%----WARNING: Could not form TPTP format derivation
%------------------------------------------------------------------------------
%----ORIGINAL SYSTEM OUTPUT
% 0.12/0.13  % Problem    : ARI497_1 : TPTP v8.2.0. Released v5.0.0.
% 0.12/0.14  % Command    : do_cvc5 %s %d
% 0.14/0.35  % Computer : n014.cluster.edu
% 0.14/0.35  % Model    : x86_64 x86_64
% 0.14/0.35  % CPU      : Intel(R) Xeon(R) CPU E5-2620 v4 @ 2.10GHz
% 0.14/0.35  % Memory   : 8042.1875MB
% 0.14/0.35  % OS       : Linux 3.10.0-693.el7.x86_64
% 0.14/0.35  % CPULimit   : 300
% 0.14/0.35  % WCLimit    : 300
% 0.14/0.35  % DateTime   : Mon May 27 06:01:54 EDT 2024
% 0.14/0.35  % CPUTime    : 
% 0.20/0.49  %----Proving TF0_ARI
% 0.20/0.51  --- Run --finite-model-find --decision=internal at 15...
% 0.20/0.51  % SZS status Theorem for /export/starexec/sandbox/tmp/tmp.VukY0diXb7/cvc5---1.0.5_24132.smt2
% 0.20/0.51  % SZS output start Proof for /export/starexec/sandbox/tmp/tmp.VukY0diXb7/cvc5---1.0.5_24132.smt2
% 0.20/0.51  (assume a0 (not (is_int 17.0)))
% 0.20/0.51  (assume a1 true)
% 0.20/0.51  (step t1 (cl (not (= (not (is_int 17.0)) false)) (not (not (is_int 17.0))) false) :rule equiv_pos2)
% 0.20/0.51  (step t2 (cl (= (is_int 17.0) true)) :rule all_simplify)
% 0.20/0.51  (step t3 (cl (= (not (is_int 17.0)) (not true))) :rule cong :premises (t2))
% 0.20/0.51  (step t4 (cl (= (not true) false)) :rule all_simplify)
% 0.20/0.51  (step t5 (cl (= (not (is_int 17.0)) false)) :rule trans :premises (t3 t4))
% 0.20/0.51  (step t6 (cl false) :rule resolution :premises (t1 t5 a0))
% 0.20/0.51  (step t7 (cl (not false)) :rule false)
% 0.20/0.51  (step t8 (cl) :rule resolution :premises (t6 t7))
% 0.20/0.51  
% 0.20/0.51  % SZS output end Proof for /export/starexec/sandbox/tmp/tmp.VukY0diXb7/cvc5---1.0.5_24132.smt2
% 0.20/0.51  % cvc5---1.0.5 exiting
% 0.20/0.51  % cvc5---1.0.5 exiting
%------------------------------------------------------------------------------