TSTP Solution File: ARI312_1 by cvc5---1.0.5
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%------------------------------------------------------------------------------
% File : cvc5---1.0.5
% Problem : ARI312_1 : TPTP v8.2.0. Released v5.0.0.
% Transfm : none
% Format : tptp:raw
% Command : do_cvc5 %s %d
% Computer : n015.cluster.edu
% Model : x86_64 x86_64
% CPU : Intel(R) Xeon(R) CPU E5-2620 v4 2.10GHz
% Memory : 8042.1875MB
% OS : Linux 3.10.0-693.el7.x86_64
% CPULimit : 300s
% WCLimit : 300s
% DateTime : Wed May 29 16:33:38 EDT 2024
% Result : Theorem 0.22s 0.56s
% Output : Proof 0.22s
% Verified :
% SZS Type : -
% Comments :
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%----WARNING: Could not form TPTP format derivation
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%----ORIGINAL SYSTEM OUTPUT
% 0.08/0.16 % Problem : ARI312_1 : TPTP v8.2.0. Released v5.0.0.
% 0.08/0.17 % Command : do_cvc5 %s %d
% 0.15/0.38 % Computer : n015.cluster.edu
% 0.15/0.38 % Model : x86_64 x86_64
% 0.15/0.38 % CPU : Intel(R) Xeon(R) CPU E5-2620 v4 @ 2.10GHz
% 0.15/0.38 % Memory : 8042.1875MB
% 0.15/0.38 % OS : Linux 3.10.0-693.el7.x86_64
% 0.15/0.38 % CPULimit : 300
% 0.15/0.38 % WCLimit : 300
% 0.15/0.38 % DateTime : Mon May 27 05:24:54 EDT 2024
% 0.15/0.38 % CPUTime :
% 0.22/0.54 %----Proving TF0_ARI
% 0.22/0.56 --- Run --finite-model-find --decision=internal at 15...
% 0.22/0.56 % SZS status Theorem for /export/starexec/sandbox/tmp/tmp.7lm5v76G22/cvc5---1.0.5_26392.smt2
% 0.22/0.56 % SZS output start Proof for /export/starexec/sandbox/tmp/tmp.7lm5v76G22/cvc5---1.0.5_26392.smt2
% 0.22/0.56 (assume a0 (not (= (- (- (/ 3 4))) (/ 3 4))))
% 0.22/0.56 (assume a1 true)
% 0.22/0.56 (step t1 (cl (not (= (not (= (- (- (/ 3 4))) (/ 3 4))) false)) (not (not (= (- (- (/ 3 4))) (/ 3 4)))) false) :rule equiv_pos2)
% 0.22/0.56 (step t2 (cl (= (- (- (/ 3 4))) (* (- 1) (- (/ 3 4))))) :rule all_simplify)
% 0.22/0.56 (step t3 (cl (= (- 1) (- 1))) :rule refl)
% 0.22/0.56 (step t4 (cl (= (- (/ 3 4)) (/ (- 3) 4))) :rule all_simplify)
% 0.22/0.56 (step t5 (cl (= (* (- 1) (- (/ 3 4))) (* (- 1) (/ (- 3) 4)))) :rule cong :premises (t3 t4))
% 0.22/0.56 (step t6 (cl (= (* (- 1) (/ (- 3) 4)) (/ 3 4))) :rule all_simplify)
% 0.22/0.56 (step t7 (cl (= (* (- 1) (- (/ 3 4))) (/ 3 4))) :rule trans :premises (t5 t6))
% 0.22/0.56 (step t8 (cl (= (- (- (/ 3 4))) (/ 3 4))) :rule trans :premises (t2 t7))
% 0.22/0.56 (step t9 (cl (= (/ 3 4) (/ 3 4))) :rule refl)
% 0.22/0.56 (step t10 (cl (= (= (- (- (/ 3 4))) (/ 3 4)) (= (/ 3 4) (/ 3 4)))) :rule cong :premises (t8 t9))
% 0.22/0.56 (step t11 (cl (= (= (/ 3 4) (/ 3 4)) true)) :rule all_simplify)
% 0.22/0.56 (step t12 (cl (= (= (- (- (/ 3 4))) (/ 3 4)) true)) :rule trans :premises (t10 t11))
% 0.22/0.56 (step t13 (cl (= (not (= (- (- (/ 3 4))) (/ 3 4))) (not true))) :rule cong :premises (t12))
% 0.22/0.56 (step t14 (cl (= (not true) false)) :rule all_simplify)
% 0.22/0.56 (step t15 (cl (= (not (= (- (- (/ 3 4))) (/ 3 4))) false)) :rule trans :premises (t13 t14))
% 0.22/0.56 (step t16 (cl false) :rule resolution :premises (t1 t15 a0))
% 0.22/0.56 (step t17 (cl (not false)) :rule false)
% 0.22/0.56 (step t18 (cl) :rule resolution :premises (t16 t17))
% 0.22/0.56
% 0.22/0.56 % SZS output end Proof for /export/starexec/sandbox/tmp/tmp.7lm5v76G22/cvc5---1.0.5_26392.smt2
% 0.22/0.56 % cvc5---1.0.5 exiting
% 0.22/0.56 % cvc5---1.0.5 exiting
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