TSTP Solution File: ARI014_1 by cvc5---1.0.5
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%------------------------------------------------------------------------------
% File : cvc5---1.0.5
% Problem : ARI014_1 : TPTP v8.2.0. Released v5.0.0.
% Transfm : none
% Format : tptp:raw
% Command : do_cvc5 %s %d
% Computer : n011.cluster.edu
% Model : x86_64 x86_64
% CPU : Intel(R) Xeon(R) CPU E5-2620 v4 2.10GHz
% Memory : 8042.1875MB
% OS : Linux 3.10.0-693.el7.x86_64
% CPULimit : 300s
% WCLimit : 300s
% DateTime : Wed May 29 16:32:59 EDT 2024
% Result : Theorem 0.20s 0.51s
% Output : Proof 0.20s
% Verified :
% SZS Type : -
% Comments :
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%----WARNING: Could not form TPTP format derivation
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%----ORIGINAL SYSTEM OUTPUT
% 0.06/0.12 % Problem : ARI014_1 : TPTP v8.2.0. Released v5.0.0.
% 0.06/0.14 % Command : do_cvc5 %s %d
% 0.13/0.34 % Computer : n011.cluster.edu
% 0.13/0.34 % Model : x86_64 x86_64
% 0.13/0.34 % CPU : Intel(R) Xeon(R) CPU E5-2620 v4 @ 2.10GHz
% 0.13/0.34 % Memory : 8042.1875MB
% 0.13/0.34 % OS : Linux 3.10.0-693.el7.x86_64
% 0.13/0.34 % CPULimit : 300
% 0.13/0.34 % WCLimit : 300
% 0.13/0.34 % DateTime : Mon May 27 05:26:39 EDT 2024
% 0.13/0.34 % CPUTime :
% 0.20/0.48 %----Proving TF0_ARI
% 0.20/0.51 --- Run --finite-model-find --decision=internal at 15...
% 0.20/0.51 % SZS status Theorem for /export/starexec/sandbox2/tmp/tmp.GbtCUsVxIC/cvc5---1.0.5_28326.smt2
% 0.20/0.51 % SZS output start Proof for /export/starexec/sandbox2/tmp/tmp.GbtCUsVxIC/cvc5---1.0.5_28326.smt2
% 0.20/0.51 (assume a0 (not (<= 2 2)))
% 0.20/0.51 (assume a1 true)
% 0.20/0.51 (step t1 (cl (not (= (not (<= 2 2)) false)) (not (not (<= 2 2))) false) :rule equiv_pos2)
% 0.20/0.51 (step t2 (cl (= (<= 2 2) true)) :rule all_simplify)
% 0.20/0.51 (step t3 (cl (= (not (<= 2 2)) (not true))) :rule cong :premises (t2))
% 0.20/0.51 (step t4 (cl (= (not true) false)) :rule all_simplify)
% 0.20/0.51 (step t5 (cl (= (not (<= 2 2)) false)) :rule trans :premises (t3 t4))
% 0.20/0.51 (step t6 (cl false) :rule resolution :premises (t1 t5 a0))
% 0.20/0.51 (step t7 (cl (not false)) :rule false)
% 0.20/0.51 (step t8 (cl) :rule resolution :premises (t6 t7))
% 0.20/0.51
% 0.20/0.51 % SZS output end Proof for /export/starexec/sandbox2/tmp/tmp.GbtCUsVxIC/cvc5---1.0.5_28326.smt2
% 0.20/0.51 % cvc5---1.0.5 exiting
% 0.20/0.51 % cvc5---1.0.5 exiting
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