%--------------------------------------------------------------------------
% File     : HWV029-2 : TPTP v8.2.0. Released v2.5.0.
% Domain   : Hardware Verification
% Problem  : Safelogic VHDL design verification obligation
% Version  : [Mar02] axioms : Especial.
% English  :

% Refs     : [CHM02] Claessen et al. (2002), Verification of Hardware Systems
%          : [Mar02] Martensson (2002), Email to G. Sutcliffe
% Source   : [Mar02]
% Names    :

% Status   : Unsatisfiable
% Rating   : 0.45 v8.2.0, 0.48 v8.1.0, 0.53 v7.4.0, 0.47 v7.3.0, 0.42 v7.1.0, 0.33 v7.0.0, 0.53 v6.3.0, 0.45 v6.2.0, 0.60 v6.1.0, 0.71 v6.0.0, 0.90 v5.5.0, 0.95 v5.4.0, 1.00 v5.2.0, 0.88 v5.0.0, 0.86 v4.1.0, 0.92 v4.0.1, 0.82 v4.0.0, 0.73 v3.7.0, 0.80 v3.5.0, 0.82 v3.4.0, 0.83 v3.3.0, 1.00 v3.2.0, 0.92 v3.1.0, 0.91 v2.7.0, 0.92 v2.6.0, 0.88 v2.5.0
% Syntax   : Number of clauses     :  136 (  28 unt;  62 nHn;  95 RR)
%            Number of literals    :  418 (  80 equ; 188 neg)
%            Maximal clause size   :   10 (   3 avg)
%            Maximal term depth    :    5 (   2 avg)
%            Number of predicates  :    4 (   3 usr;   0 prp; 1-2 aty)
%            Number of functors    :   46 (  46 usr;   8 con; 0-3 aty)
%            Number of variables   :  225 (  20 sgn)
% SPC      : CNF_UNS_RFO_SEQ_NHN

% Comments :
%--------------------------------------------------------------------------
%----Include VHDL design axioms
include('Axioms/HWV004-0.ax').
%--------------------------------------------------------------------------
cnf(quest_1,negated_conjecture,
    p_LES_EQU_(fwork_DOTfifo_DOTrtl_DOTlevel_(t_206),fwork_DOTfifo_DOTrtl_DOTfifo__length_) ).

cnf(quest_2,negated_conjecture,
    ~ p_LES_EQU_(fwork_DOTfifo_DOTrtl_DOTlevel_(f_ADD_(t_206,n1)),fwork_DOTfifo_DOTrtl_DOTfifo__length_) ).

cnf(quest_3,negated_conjecture,
    ~ p_LES_EQU_(fwork_DOTfifo_DOTrtl_DOTfifo__length_,n0) ).

%--------------------------------------------------------------------------