%--------------------------------------------------------------------------
% File     : HWV024-2 : TPTP v8.2.0. Released v2.5.0.
% Domain   : Hardware Verification
% Problem  : Safelogic VHDL design verification obligation
% Version  : [Mar02] axioms : Especial.
% English  :

% Refs     : [CHM02] Claessen et al. (2002), Verification of Hardware Systems
%          : [Mar02] Martensson (2002), Email to G. Sutcliffe
% Source   : [Mar02]
% Names    :

% Status   : Unsatisfiable
% Rating   : 1.00 v2.5.0
% Syntax   : Number of clauses     :  138 (  30 unt;  62 nHn;  97 RR)
%            Number of literals    :  420 (  81 equ; 189 neg)
%            Maximal clause size   :   10 (   3 avg)
%            Maximal term depth    :    5 (   2 avg)
%            Number of predicates  :    4 (   3 usr;   0 prp; 1-2 aty)
%            Number of functors    :   47 (  47 usr;   9 con; 0-3 aty)
%            Number of variables   :  225 (  20 sgn)
% SPC      : CNF_UNS_RFO_SEQ_NHN

% Comments :
%--------------------------------------------------------------------------
%----Include VHDL design axioms
include('Axioms/HWV004-0.ax').
%--------------------------------------------------------------------------
cnf(quest_1,negated_conjecture,
    ~ p__pred_(fwork_DOTfifo_DOTrtl_DOTrd_(t_206)) ).

cnf(quest_2,negated_conjecture,
    ~ p__pred_(fwork_DOTfifo_DOTrtl_DOTreset_(t_206)) ).

cnf(quest_3,negated_conjecture,
    p_LES_EQU_(n0,x_207) ).

cnf(quest_4,negated_conjecture,
    p_LES_EQU_(x_207,f_SUB_(fwork_DOTfifo_DOTrtl_DOTfifo__width_,n1)) ).

cnf(quest_5,negated_conjecture,
    f__index_(fwork_DOTfifo_DOTrtl_DOTdata__out_(f_ADD_(t_206,n1)),f_SUB_(f_SUB_(fwork_DOTfifo_DOTrtl_DOTfifo__width_,n1),x_207)) != f__index_(fwork_DOTfifo_DOTrtl_DOTdata__out_(t_206),f_SUB_(f_SUB_(fwork_DOTfifo_DOTrtl_DOTfifo__width_,n1),x_207)) ).

%--------------------------------------------------------------------------